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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
0206e353 | 44 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
3dec0095 | 45 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 46 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 JB |
47 | |
48 | typedef struct { | |
0206e353 AJ |
49 | /* given values */ |
50 | int n; | |
51 | int m1, m2; | |
52 | int p1, p2; | |
53 | /* derived values */ | |
54 | int dot; | |
55 | int vco; | |
56 | int m; | |
57 | int p; | |
79e53945 JB |
58 | } intel_clock_t; |
59 | ||
60 | typedef struct { | |
0206e353 | 61 | int min, max; |
79e53945 JB |
62 | } intel_range_t; |
63 | ||
64 | typedef struct { | |
0206e353 AJ |
65 | int dot_limit; |
66 | int p2_slow, p2_fast; | |
79e53945 JB |
67 | } intel_p2_t; |
68 | ||
69 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
70 | typedef struct intel_limit intel_limit_t; |
71 | struct intel_limit { | |
0206e353 AJ |
72 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
73 | intel_p2_t p2; | |
74 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, | |
cec2f356 | 75 | int, int, intel_clock_t *, intel_clock_t *); |
d4906093 | 76 | }; |
79e53945 | 77 | |
2377b741 JB |
78 | /* FDI */ |
79 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
80 | ||
d2acd215 DV |
81 | int |
82 | intel_pch_rawclk(struct drm_device *dev) | |
83 | { | |
84 | struct drm_i915_private *dev_priv = dev->dev_private; | |
85 | ||
86 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
87 | ||
88 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
89 | } | |
90 | ||
d4906093 ML |
91 | static bool |
92 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
93 | int target, int refclk, intel_clock_t *match_clock, |
94 | intel_clock_t *best_clock); | |
d4906093 ML |
95 | static bool |
96 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
97 | int target, int refclk, intel_clock_t *match_clock, |
98 | intel_clock_t *best_clock); | |
79e53945 | 99 | |
a4fc5ed6 KP |
100 | static bool |
101 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
cec2f356 SP |
102 | int target, int refclk, intel_clock_t *match_clock, |
103 | intel_clock_t *best_clock); | |
5eb08b69 | 104 | static bool |
f2b115e6 | 105 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
cec2f356 SP |
106 | int target, int refclk, intel_clock_t *match_clock, |
107 | intel_clock_t *best_clock); | |
a4fc5ed6 | 108 | |
a0c4da24 JB |
109 | static bool |
110 | intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
111 | int target, int refclk, intel_clock_t *match_clock, | |
112 | intel_clock_t *best_clock); | |
113 | ||
021357ac CW |
114 | static inline u32 /* units of 100MHz */ |
115 | intel_fdi_link_freq(struct drm_device *dev) | |
116 | { | |
8b99e68c CW |
117 | if (IS_GEN5(dev)) { |
118 | struct drm_i915_private *dev_priv = dev->dev_private; | |
119 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
120 | } else | |
121 | return 27; | |
021357ac CW |
122 | } |
123 | ||
e4b36699 | 124 | static const intel_limit_t intel_limits_i8xx_dvo = { |
0206e353 AJ |
125 | .dot = { .min = 25000, .max = 350000 }, |
126 | .vco = { .min = 930000, .max = 1400000 }, | |
127 | .n = { .min = 3, .max = 16 }, | |
128 | .m = { .min = 96, .max = 140 }, | |
129 | .m1 = { .min = 18, .max = 26 }, | |
130 | .m2 = { .min = 6, .max = 16 }, | |
131 | .p = { .min = 4, .max = 128 }, | |
132 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
133 | .p2 = { .dot_limit = 165000, |
134 | .p2_slow = 4, .p2_fast = 2 }, | |
d4906093 | 135 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
136 | }; |
137 | ||
138 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
0206e353 AJ |
139 | .dot = { .min = 25000, .max = 350000 }, |
140 | .vco = { .min = 930000, .max = 1400000 }, | |
141 | .n = { .min = 3, .max = 16 }, | |
142 | .m = { .min = 96, .max = 140 }, | |
143 | .m1 = { .min = 18, .max = 26 }, | |
144 | .m2 = { .min = 6, .max = 16 }, | |
145 | .p = { .min = 4, .max = 128 }, | |
146 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
147 | .p2 = { .dot_limit = 165000, |
148 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 149 | .find_pll = intel_find_best_PLL, |
e4b36699 | 150 | }; |
273e27ca | 151 | |
e4b36699 | 152 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
153 | .dot = { .min = 20000, .max = 400000 }, |
154 | .vco = { .min = 1400000, .max = 2800000 }, | |
155 | .n = { .min = 1, .max = 6 }, | |
156 | .m = { .min = 70, .max = 120 }, | |
157 | .m1 = { .min = 10, .max = 22 }, | |
158 | .m2 = { .min = 5, .max = 9 }, | |
159 | .p = { .min = 5, .max = 80 }, | |
160 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
161 | .p2 = { .dot_limit = 200000, |
162 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 163 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
164 | }; |
165 | ||
166 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
167 | .dot = { .min = 20000, .max = 400000 }, |
168 | .vco = { .min = 1400000, .max = 2800000 }, | |
169 | .n = { .min = 1, .max = 6 }, | |
170 | .m = { .min = 70, .max = 120 }, | |
171 | .m1 = { .min = 10, .max = 22 }, | |
172 | .m2 = { .min = 5, .max = 9 }, | |
173 | .p = { .min = 7, .max = 98 }, | |
174 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
175 | .p2 = { .dot_limit = 112000, |
176 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 177 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
178 | }; |
179 | ||
273e27ca | 180 | |
e4b36699 | 181 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
182 | .dot = { .min = 25000, .max = 270000 }, |
183 | .vco = { .min = 1750000, .max = 3500000}, | |
184 | .n = { .min = 1, .max = 4 }, | |
185 | .m = { .min = 104, .max = 138 }, | |
186 | .m1 = { .min = 17, .max = 23 }, | |
187 | .m2 = { .min = 5, .max = 11 }, | |
188 | .p = { .min = 10, .max = 30 }, | |
189 | .p1 = { .min = 1, .max = 3}, | |
190 | .p2 = { .dot_limit = 270000, | |
191 | .p2_slow = 10, | |
192 | .p2_fast = 10 | |
044c7c41 | 193 | }, |
d4906093 | 194 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
195 | }; |
196 | ||
197 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
198 | .dot = { .min = 22000, .max = 400000 }, |
199 | .vco = { .min = 1750000, .max = 3500000}, | |
200 | .n = { .min = 1, .max = 4 }, | |
201 | .m = { .min = 104, .max = 138 }, | |
202 | .m1 = { .min = 16, .max = 23 }, | |
203 | .m2 = { .min = 5, .max = 11 }, | |
204 | .p = { .min = 5, .max = 80 }, | |
205 | .p1 = { .min = 1, .max = 8}, | |
206 | .p2 = { .dot_limit = 165000, | |
207 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 208 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
209 | }; |
210 | ||
211 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
212 | .dot = { .min = 20000, .max = 115000 }, |
213 | .vco = { .min = 1750000, .max = 3500000 }, | |
214 | .n = { .min = 1, .max = 3 }, | |
215 | .m = { .min = 104, .max = 138 }, | |
216 | .m1 = { .min = 17, .max = 23 }, | |
217 | .m2 = { .min = 5, .max = 11 }, | |
218 | .p = { .min = 28, .max = 112 }, | |
219 | .p1 = { .min = 2, .max = 8 }, | |
220 | .p2 = { .dot_limit = 0, | |
221 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 222 | }, |
d4906093 | 223 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
224 | }; |
225 | ||
226 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
227 | .dot = { .min = 80000, .max = 224000 }, |
228 | .vco = { .min = 1750000, .max = 3500000 }, | |
229 | .n = { .min = 1, .max = 3 }, | |
230 | .m = { .min = 104, .max = 138 }, | |
231 | .m1 = { .min = 17, .max = 23 }, | |
232 | .m2 = { .min = 5, .max = 11 }, | |
233 | .p = { .min = 14, .max = 42 }, | |
234 | .p1 = { .min = 2, .max = 6 }, | |
235 | .p2 = { .dot_limit = 0, | |
236 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 237 | }, |
d4906093 | 238 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
239 | }; |
240 | ||
241 | static const intel_limit_t intel_limits_g4x_display_port = { | |
0206e353 AJ |
242 | .dot = { .min = 161670, .max = 227000 }, |
243 | .vco = { .min = 1750000, .max = 3500000}, | |
244 | .n = { .min = 1, .max = 2 }, | |
245 | .m = { .min = 97, .max = 108 }, | |
246 | .m1 = { .min = 0x10, .max = 0x12 }, | |
247 | .m2 = { .min = 0x05, .max = 0x06 }, | |
248 | .p = { .min = 10, .max = 20 }, | |
249 | .p1 = { .min = 1, .max = 2}, | |
250 | .p2 = { .dot_limit = 0, | |
273e27ca | 251 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 252 | .find_pll = intel_find_pll_g4x_dp, |
e4b36699 KP |
253 | }; |
254 | ||
f2b115e6 | 255 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
256 | .dot = { .min = 20000, .max = 400000}, |
257 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 258 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
259 | .n = { .min = 3, .max = 6 }, |
260 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 261 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
262 | .m1 = { .min = 0, .max = 0 }, |
263 | .m2 = { .min = 0, .max = 254 }, | |
264 | .p = { .min = 5, .max = 80 }, | |
265 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
266 | .p2 = { .dot_limit = 200000, |
267 | .p2_slow = 10, .p2_fast = 5 }, | |
6115707b | 268 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
269 | }; |
270 | ||
f2b115e6 | 271 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
272 | .dot = { .min = 20000, .max = 400000 }, |
273 | .vco = { .min = 1700000, .max = 3500000 }, | |
274 | .n = { .min = 3, .max = 6 }, | |
275 | .m = { .min = 2, .max = 256 }, | |
276 | .m1 = { .min = 0, .max = 0 }, | |
277 | .m2 = { .min = 0, .max = 254 }, | |
278 | .p = { .min = 7, .max = 112 }, | |
279 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
280 | .p2 = { .dot_limit = 112000, |
281 | .p2_slow = 14, .p2_fast = 14 }, | |
6115707b | 282 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
283 | }; |
284 | ||
273e27ca EA |
285 | /* Ironlake / Sandybridge |
286 | * | |
287 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
288 | * the range value for them is (actual_value - 2). | |
289 | */ | |
b91ad0ec | 290 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
291 | .dot = { .min = 25000, .max = 350000 }, |
292 | .vco = { .min = 1760000, .max = 3510000 }, | |
293 | .n = { .min = 1, .max = 5 }, | |
294 | .m = { .min = 79, .max = 127 }, | |
295 | .m1 = { .min = 12, .max = 22 }, | |
296 | .m2 = { .min = 5, .max = 9 }, | |
297 | .p = { .min = 5, .max = 80 }, | |
298 | .p1 = { .min = 1, .max = 8 }, | |
299 | .p2 = { .dot_limit = 225000, | |
300 | .p2_slow = 10, .p2_fast = 5 }, | |
4547668a | 301 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
302 | }; |
303 | ||
b91ad0ec | 304 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
305 | .dot = { .min = 25000, .max = 350000 }, |
306 | .vco = { .min = 1760000, .max = 3510000 }, | |
307 | .n = { .min = 1, .max = 3 }, | |
308 | .m = { .min = 79, .max = 118 }, | |
309 | .m1 = { .min = 12, .max = 22 }, | |
310 | .m2 = { .min = 5, .max = 9 }, | |
311 | .p = { .min = 28, .max = 112 }, | |
312 | .p1 = { .min = 2, .max = 8 }, | |
313 | .p2 = { .dot_limit = 225000, | |
314 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
315 | .find_pll = intel_g4x_find_best_PLL, |
316 | }; | |
317 | ||
318 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
319 | .dot = { .min = 25000, .max = 350000 }, |
320 | .vco = { .min = 1760000, .max = 3510000 }, | |
321 | .n = { .min = 1, .max = 3 }, | |
322 | .m = { .min = 79, .max = 127 }, | |
323 | .m1 = { .min = 12, .max = 22 }, | |
324 | .m2 = { .min = 5, .max = 9 }, | |
325 | .p = { .min = 14, .max = 56 }, | |
326 | .p1 = { .min = 2, .max = 8 }, | |
327 | .p2 = { .dot_limit = 225000, | |
328 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
329 | .find_pll = intel_g4x_find_best_PLL, |
330 | }; | |
331 | ||
273e27ca | 332 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 333 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
334 | .dot = { .min = 25000, .max = 350000 }, |
335 | .vco = { .min = 1760000, .max = 3510000 }, | |
336 | .n = { .min = 1, .max = 2 }, | |
337 | .m = { .min = 79, .max = 126 }, | |
338 | .m1 = { .min = 12, .max = 22 }, | |
339 | .m2 = { .min = 5, .max = 9 }, | |
340 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 341 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
342 | .p2 = { .dot_limit = 225000, |
343 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
344 | .find_pll = intel_g4x_find_best_PLL, |
345 | }; | |
346 | ||
347 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
348 | .dot = { .min = 25000, .max = 350000 }, |
349 | .vco = { .min = 1760000, .max = 3510000 }, | |
350 | .n = { .min = 1, .max = 3 }, | |
351 | .m = { .min = 79, .max = 126 }, | |
352 | .m1 = { .min = 12, .max = 22 }, | |
353 | .m2 = { .min = 5, .max = 9 }, | |
354 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 355 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
356 | .p2 = { .dot_limit = 225000, |
357 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
358 | .find_pll = intel_g4x_find_best_PLL, |
359 | }; | |
360 | ||
361 | static const intel_limit_t intel_limits_ironlake_display_port = { | |
0206e353 AJ |
362 | .dot = { .min = 25000, .max = 350000 }, |
363 | .vco = { .min = 1760000, .max = 3510000}, | |
364 | .n = { .min = 1, .max = 2 }, | |
365 | .m = { .min = 81, .max = 90 }, | |
366 | .m1 = { .min = 12, .max = 22 }, | |
367 | .m2 = { .min = 5, .max = 9 }, | |
368 | .p = { .min = 10, .max = 20 }, | |
369 | .p1 = { .min = 1, .max = 2}, | |
370 | .p2 = { .dot_limit = 0, | |
273e27ca | 371 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 372 | .find_pll = intel_find_pll_ironlake_dp, |
79e53945 JB |
373 | }; |
374 | ||
a0c4da24 JB |
375 | static const intel_limit_t intel_limits_vlv_dac = { |
376 | .dot = { .min = 25000, .max = 270000 }, | |
377 | .vco = { .min = 4000000, .max = 6000000 }, | |
378 | .n = { .min = 1, .max = 7 }, | |
379 | .m = { .min = 22, .max = 450 }, /* guess */ | |
380 | .m1 = { .min = 2, .max = 3 }, | |
381 | .m2 = { .min = 11, .max = 156 }, | |
382 | .p = { .min = 10, .max = 30 }, | |
383 | .p1 = { .min = 2, .max = 3 }, | |
384 | .p2 = { .dot_limit = 270000, | |
385 | .p2_slow = 2, .p2_fast = 20 }, | |
386 | .find_pll = intel_vlv_find_best_pll, | |
387 | }; | |
388 | ||
389 | static const intel_limit_t intel_limits_vlv_hdmi = { | |
390 | .dot = { .min = 20000, .max = 165000 }, | |
17dc9257 | 391 | .vco = { .min = 4000000, .max = 5994000}, |
a0c4da24 JB |
392 | .n = { .min = 1, .max = 7 }, |
393 | .m = { .min = 60, .max = 300 }, /* guess */ | |
394 | .m1 = { .min = 2, .max = 3 }, | |
395 | .m2 = { .min = 11, .max = 156 }, | |
396 | .p = { .min = 10, .max = 30 }, | |
397 | .p1 = { .min = 2, .max = 3 }, | |
398 | .p2 = { .dot_limit = 270000, | |
399 | .p2_slow = 2, .p2_fast = 20 }, | |
400 | .find_pll = intel_vlv_find_best_pll, | |
401 | }; | |
402 | ||
403 | static const intel_limit_t intel_limits_vlv_dp = { | |
74a4dd2e VP |
404 | .dot = { .min = 25000, .max = 270000 }, |
405 | .vco = { .min = 4000000, .max = 6000000 }, | |
a0c4da24 | 406 | .n = { .min = 1, .max = 7 }, |
74a4dd2e | 407 | .m = { .min = 22, .max = 450 }, |
a0c4da24 JB |
408 | .m1 = { .min = 2, .max = 3 }, |
409 | .m2 = { .min = 11, .max = 156 }, | |
410 | .p = { .min = 10, .max = 30 }, | |
411 | .p1 = { .min = 2, .max = 3 }, | |
412 | .p2 = { .dot_limit = 270000, | |
413 | .p2_slow = 2, .p2_fast = 20 }, | |
414 | .find_pll = intel_vlv_find_best_pll, | |
415 | }; | |
416 | ||
57f350b6 JB |
417 | u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) |
418 | { | |
09153000 | 419 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
57f350b6 | 420 | |
57f350b6 JB |
421 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
422 | DRM_ERROR("DPIO idle wait timed out\n"); | |
09153000 | 423 | return 0; |
57f350b6 JB |
424 | } |
425 | ||
426 | I915_WRITE(DPIO_REG, reg); | |
427 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID | | |
428 | DPIO_BYTE); | |
429 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { | |
430 | DRM_ERROR("DPIO read wait timed out\n"); | |
09153000 | 431 | return 0; |
57f350b6 | 432 | } |
57f350b6 | 433 | |
09153000 | 434 | return I915_READ(DPIO_DATA); |
57f350b6 JB |
435 | } |
436 | ||
a0c4da24 JB |
437 | static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, |
438 | u32 val) | |
439 | { | |
09153000 | 440 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
a0c4da24 | 441 | |
a0c4da24 JB |
442 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
443 | DRM_ERROR("DPIO idle wait timed out\n"); | |
09153000 | 444 | return; |
a0c4da24 JB |
445 | } |
446 | ||
447 | I915_WRITE(DPIO_DATA, val); | |
448 | I915_WRITE(DPIO_REG, reg); | |
449 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID | | |
450 | DPIO_BYTE); | |
451 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) | |
452 | DRM_ERROR("DPIO write wait timed out\n"); | |
a0c4da24 JB |
453 | } |
454 | ||
57f350b6 JB |
455 | static void vlv_init_dpio(struct drm_device *dev) |
456 | { | |
457 | struct drm_i915_private *dev_priv = dev->dev_private; | |
458 | ||
459 | /* Reset the DPIO config */ | |
460 | I915_WRITE(DPIO_CTL, 0); | |
461 | POSTING_READ(DPIO_CTL); | |
462 | I915_WRITE(DPIO_CTL, 1); | |
463 | POSTING_READ(DPIO_CTL); | |
464 | } | |
465 | ||
1b894b59 CW |
466 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
467 | int refclk) | |
2c07245f | 468 | { |
b91ad0ec | 469 | struct drm_device *dev = crtc->dev; |
2c07245f | 470 | const intel_limit_t *limit; |
b91ad0ec ZW |
471 | |
472 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 473 | if (intel_is_dual_link_lvds(dev)) { |
b91ad0ec | 474 | /* LVDS dual channel */ |
1b894b59 | 475 | if (refclk == 100000) |
b91ad0ec ZW |
476 | limit = &intel_limits_ironlake_dual_lvds_100m; |
477 | else | |
478 | limit = &intel_limits_ironlake_dual_lvds; | |
479 | } else { | |
1b894b59 | 480 | if (refclk == 100000) |
b91ad0ec ZW |
481 | limit = &intel_limits_ironlake_single_lvds_100m; |
482 | else | |
483 | limit = &intel_limits_ironlake_single_lvds; | |
484 | } | |
485 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
547dc041 | 486 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
4547668a | 487 | limit = &intel_limits_ironlake_display_port; |
2c07245f | 488 | else |
b91ad0ec | 489 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
490 | |
491 | return limit; | |
492 | } | |
493 | ||
044c7c41 ML |
494 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
495 | { | |
496 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
497 | const intel_limit_t *limit; |
498 | ||
499 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 500 | if (intel_is_dual_link_lvds(dev)) |
044c7c41 | 501 | /* LVDS with dual channel */ |
e4b36699 | 502 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
503 | else |
504 | /* LVDS with dual channel */ | |
e4b36699 | 505 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
506 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
507 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 508 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 509 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 510 | limit = &intel_limits_g4x_sdvo; |
0206e353 | 511 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 512 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 513 | } else /* The option is for other outputs */ |
e4b36699 | 514 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
515 | |
516 | return limit; | |
517 | } | |
518 | ||
1b894b59 | 519 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
520 | { |
521 | struct drm_device *dev = crtc->dev; | |
522 | const intel_limit_t *limit; | |
523 | ||
bad720ff | 524 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 525 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 526 | else if (IS_G4X(dev)) { |
044c7c41 | 527 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 528 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 529 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 530 | limit = &intel_limits_pineview_lvds; |
2177832f | 531 | else |
f2b115e6 | 532 | limit = &intel_limits_pineview_sdvo; |
a0c4da24 JB |
533 | } else if (IS_VALLEYVIEW(dev)) { |
534 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) | |
535 | limit = &intel_limits_vlv_dac; | |
536 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
537 | limit = &intel_limits_vlv_hdmi; | |
538 | else | |
539 | limit = &intel_limits_vlv_dp; | |
a6c45cf0 CW |
540 | } else if (!IS_GEN2(dev)) { |
541 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
542 | limit = &intel_limits_i9xx_lvds; | |
543 | else | |
544 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
545 | } else { |
546 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 547 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 548 | else |
e4b36699 | 549 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
550 | } |
551 | return limit; | |
552 | } | |
553 | ||
f2b115e6 AJ |
554 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
555 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 556 | { |
2177832f SL |
557 | clock->m = clock->m2 + 2; |
558 | clock->p = clock->p1 * clock->p2; | |
559 | clock->vco = refclk * clock->m / clock->n; | |
560 | clock->dot = clock->vco / clock->p; | |
561 | } | |
562 | ||
563 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
564 | { | |
f2b115e6 AJ |
565 | if (IS_PINEVIEW(dev)) { |
566 | pineview_clock(refclk, clock); | |
2177832f SL |
567 | return; |
568 | } | |
79e53945 JB |
569 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
570 | clock->p = clock->p1 * clock->p2; | |
571 | clock->vco = refclk * clock->m / (clock->n + 2); | |
572 | clock->dot = clock->vco / clock->p; | |
573 | } | |
574 | ||
79e53945 JB |
575 | /** |
576 | * Returns whether any output on the specified pipe is of the specified type | |
577 | */ | |
4ef69c7a | 578 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 579 | { |
4ef69c7a | 580 | struct drm_device *dev = crtc->dev; |
4ef69c7a CW |
581 | struct intel_encoder *encoder; |
582 | ||
6c2b7c12 DV |
583 | for_each_encoder_on_crtc(dev, crtc, encoder) |
584 | if (encoder->type == type) | |
4ef69c7a CW |
585 | return true; |
586 | ||
587 | return false; | |
79e53945 JB |
588 | } |
589 | ||
7c04d1d9 | 590 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
591 | /** |
592 | * Returns whether the given set of divisors are valid for a given refclk with | |
593 | * the given connectors. | |
594 | */ | |
595 | ||
1b894b59 CW |
596 | static bool intel_PLL_is_valid(struct drm_device *dev, |
597 | const intel_limit_t *limit, | |
598 | const intel_clock_t *clock) | |
79e53945 | 599 | { |
79e53945 | 600 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 601 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 602 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
0206e353 | 603 | INTELPllInvalid("p out of range\n"); |
79e53945 | 604 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 605 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 606 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 607 | INTELPllInvalid("m1 out of range\n"); |
f2b115e6 | 608 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
0206e353 | 609 | INTELPllInvalid("m1 <= m2\n"); |
79e53945 | 610 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
0206e353 | 611 | INTELPllInvalid("m out of range\n"); |
79e53945 | 612 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
0206e353 | 613 | INTELPllInvalid("n out of range\n"); |
79e53945 | 614 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 615 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
616 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
617 | * connector, etc., rather than just a single range. | |
618 | */ | |
619 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 620 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
621 | |
622 | return true; | |
623 | } | |
624 | ||
d4906093 ML |
625 | static bool |
626 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
627 | int target, int refclk, intel_clock_t *match_clock, |
628 | intel_clock_t *best_clock) | |
d4906093 | 629 | |
79e53945 JB |
630 | { |
631 | struct drm_device *dev = crtc->dev; | |
79e53945 | 632 | intel_clock_t clock; |
79e53945 JB |
633 | int err = target; |
634 | ||
a210b028 | 635 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 636 | /* |
a210b028 DV |
637 | * For LVDS just rely on its current settings for dual-channel. |
638 | * We haven't figured out how to reliably set up different | |
639 | * single/dual channel state, if we even can. | |
79e53945 | 640 | */ |
1974cad0 | 641 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
642 | clock.p2 = limit->p2.p2_fast; |
643 | else | |
644 | clock.p2 = limit->p2.p2_slow; | |
645 | } else { | |
646 | if (target < limit->p2.dot_limit) | |
647 | clock.p2 = limit->p2.p2_slow; | |
648 | else | |
649 | clock.p2 = limit->p2.p2_fast; | |
650 | } | |
651 | ||
0206e353 | 652 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 653 | |
42158660 ZY |
654 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
655 | clock.m1++) { | |
656 | for (clock.m2 = limit->m2.min; | |
657 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
658 | /* m1 is always 0 in Pineview */ |
659 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
660 | break; |
661 | for (clock.n = limit->n.min; | |
662 | clock.n <= limit->n.max; clock.n++) { | |
663 | for (clock.p1 = limit->p1.min; | |
664 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
665 | int this_err; |
666 | ||
2177832f | 667 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
668 | if (!intel_PLL_is_valid(dev, limit, |
669 | &clock)) | |
79e53945 | 670 | continue; |
cec2f356 SP |
671 | if (match_clock && |
672 | clock.p != match_clock->p) | |
673 | continue; | |
79e53945 JB |
674 | |
675 | this_err = abs(clock.dot - target); | |
676 | if (this_err < err) { | |
677 | *best_clock = clock; | |
678 | err = this_err; | |
679 | } | |
680 | } | |
681 | } | |
682 | } | |
683 | } | |
684 | ||
685 | return (err != target); | |
686 | } | |
687 | ||
d4906093 ML |
688 | static bool |
689 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
690 | int target, int refclk, intel_clock_t *match_clock, |
691 | intel_clock_t *best_clock) | |
d4906093 ML |
692 | { |
693 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
694 | intel_clock_t clock; |
695 | int max_n; | |
696 | bool found; | |
6ba770dc AJ |
697 | /* approximately equals target * 0.00585 */ |
698 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
699 | found = false; |
700 | ||
701 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
702 | int lvds_reg; |
703 | ||
c619eed4 | 704 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
705 | lvds_reg = PCH_LVDS; |
706 | else | |
707 | lvds_reg = LVDS; | |
1974cad0 | 708 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
709 | clock.p2 = limit->p2.p2_fast; |
710 | else | |
711 | clock.p2 = limit->p2.p2_slow; | |
712 | } else { | |
713 | if (target < limit->p2.dot_limit) | |
714 | clock.p2 = limit->p2.p2_slow; | |
715 | else | |
716 | clock.p2 = limit->p2.p2_fast; | |
717 | } | |
718 | ||
719 | memset(best_clock, 0, sizeof(*best_clock)); | |
720 | max_n = limit->n.max; | |
f77f13e2 | 721 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 722 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 723 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
724 | for (clock.m1 = limit->m1.max; |
725 | clock.m1 >= limit->m1.min; clock.m1--) { | |
726 | for (clock.m2 = limit->m2.max; | |
727 | clock.m2 >= limit->m2.min; clock.m2--) { | |
728 | for (clock.p1 = limit->p1.max; | |
729 | clock.p1 >= limit->p1.min; clock.p1--) { | |
730 | int this_err; | |
731 | ||
2177832f | 732 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
733 | if (!intel_PLL_is_valid(dev, limit, |
734 | &clock)) | |
d4906093 | 735 | continue; |
cec2f356 SP |
736 | if (match_clock && |
737 | clock.p != match_clock->p) | |
738 | continue; | |
1b894b59 CW |
739 | |
740 | this_err = abs(clock.dot - target); | |
d4906093 ML |
741 | if (this_err < err_most) { |
742 | *best_clock = clock; | |
743 | err_most = this_err; | |
744 | max_n = clock.n; | |
745 | found = true; | |
746 | } | |
747 | } | |
748 | } | |
749 | } | |
750 | } | |
2c07245f ZW |
751 | return found; |
752 | } | |
753 | ||
5eb08b69 | 754 | static bool |
f2b115e6 | 755 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
756 | int target, int refclk, intel_clock_t *match_clock, |
757 | intel_clock_t *best_clock) | |
5eb08b69 ZW |
758 | { |
759 | struct drm_device *dev = crtc->dev; | |
760 | intel_clock_t clock; | |
4547668a | 761 | |
5eb08b69 ZW |
762 | if (target < 200000) { |
763 | clock.n = 1; | |
764 | clock.p1 = 2; | |
765 | clock.p2 = 10; | |
766 | clock.m1 = 12; | |
767 | clock.m2 = 9; | |
768 | } else { | |
769 | clock.n = 2; | |
770 | clock.p1 = 1; | |
771 | clock.p2 = 10; | |
772 | clock.m1 = 14; | |
773 | clock.m2 = 8; | |
774 | } | |
775 | intel_clock(dev, refclk, &clock); | |
776 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
777 | return true; | |
778 | } | |
779 | ||
a4fc5ed6 KP |
780 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
781 | static bool | |
782 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
783 | int target, int refclk, intel_clock_t *match_clock, |
784 | intel_clock_t *best_clock) | |
a4fc5ed6 | 785 | { |
5eddb70b CW |
786 | intel_clock_t clock; |
787 | if (target < 200000) { | |
788 | clock.p1 = 2; | |
789 | clock.p2 = 10; | |
790 | clock.n = 2; | |
791 | clock.m1 = 23; | |
792 | clock.m2 = 8; | |
793 | } else { | |
794 | clock.p1 = 1; | |
795 | clock.p2 = 10; | |
796 | clock.n = 1; | |
797 | clock.m1 = 14; | |
798 | clock.m2 = 2; | |
799 | } | |
800 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); | |
801 | clock.p = (clock.p1 * clock.p2); | |
802 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
803 | clock.vco = 0; | |
804 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
805 | return true; | |
a4fc5ed6 | 806 | } |
a0c4da24 JB |
807 | static bool |
808 | intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
809 | int target, int refclk, intel_clock_t *match_clock, | |
810 | intel_clock_t *best_clock) | |
811 | { | |
812 | u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; | |
813 | u32 m, n, fastclk; | |
814 | u32 updrate, minupdate, fracbits, p; | |
815 | unsigned long bestppm, ppm, absppm; | |
816 | int dotclk, flag; | |
817 | ||
af447bd3 | 818 | flag = 0; |
a0c4da24 JB |
819 | dotclk = target * 1000; |
820 | bestppm = 1000000; | |
821 | ppm = absppm = 0; | |
822 | fastclk = dotclk / (2*100); | |
823 | updrate = 0; | |
824 | minupdate = 19200; | |
825 | fracbits = 1; | |
826 | n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; | |
827 | bestm1 = bestm2 = bestp1 = bestp2 = 0; | |
828 | ||
829 | /* based on hardware requirement, prefer smaller n to precision */ | |
830 | for (n = limit->n.min; n <= ((refclk) / minupdate); n++) { | |
831 | updrate = refclk / n; | |
832 | for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) { | |
833 | for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) { | |
834 | if (p2 > 10) | |
835 | p2 = p2 - 1; | |
836 | p = p1 * p2; | |
837 | /* based on hardware requirement, prefer bigger m1,m2 values */ | |
838 | for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) { | |
839 | m2 = (((2*(fastclk * p * n / m1 )) + | |
840 | refclk) / (2*refclk)); | |
841 | m = m1 * m2; | |
842 | vco = updrate * m; | |
843 | if (vco >= limit->vco.min && vco < limit->vco.max) { | |
844 | ppm = 1000000 * ((vco / p) - fastclk) / fastclk; | |
845 | absppm = (ppm > 0) ? ppm : (-ppm); | |
846 | if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) { | |
847 | bestppm = 0; | |
848 | flag = 1; | |
849 | } | |
850 | if (absppm < bestppm - 10) { | |
851 | bestppm = absppm; | |
852 | flag = 1; | |
853 | } | |
854 | if (flag) { | |
855 | bestn = n; | |
856 | bestm1 = m1; | |
857 | bestm2 = m2; | |
858 | bestp1 = p1; | |
859 | bestp2 = p2; | |
860 | flag = 0; | |
861 | } | |
862 | } | |
863 | } | |
864 | } | |
865 | } | |
866 | } | |
867 | best_clock->n = bestn; | |
868 | best_clock->m1 = bestm1; | |
869 | best_clock->m2 = bestm2; | |
870 | best_clock->p1 = bestp1; | |
871 | best_clock->p2 = bestp2; | |
872 | ||
873 | return true; | |
874 | } | |
a4fc5ed6 | 875 | |
a5c961d1 PZ |
876 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
877 | enum pipe pipe) | |
878 | { | |
879 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
880 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
881 | ||
882 | return intel_crtc->cpu_transcoder; | |
883 | } | |
884 | ||
a928d536 PZ |
885 | static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) |
886 | { | |
887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
888 | u32 frame, frame_reg = PIPEFRAME(pipe); | |
889 | ||
890 | frame = I915_READ(frame_reg); | |
891 | ||
892 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
893 | DRM_DEBUG_KMS("vblank wait timed out\n"); | |
894 | } | |
895 | ||
9d0498a2 JB |
896 | /** |
897 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
898 | * @dev: drm device | |
899 | * @pipe: pipe to wait for | |
900 | * | |
901 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
902 | * mode setting code. | |
903 | */ | |
904 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 905 | { |
9d0498a2 | 906 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 907 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 908 | |
a928d536 PZ |
909 | if (INTEL_INFO(dev)->gen >= 5) { |
910 | ironlake_wait_for_vblank(dev, pipe); | |
911 | return; | |
912 | } | |
913 | ||
300387c0 CW |
914 | /* Clear existing vblank status. Note this will clear any other |
915 | * sticky status fields as well. | |
916 | * | |
917 | * This races with i915_driver_irq_handler() with the result | |
918 | * that either function could miss a vblank event. Here it is not | |
919 | * fatal, as we will either wait upon the next vblank interrupt or | |
920 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
921 | * called during modeset at which time the GPU should be idle and | |
922 | * should *not* be performing page flips and thus not waiting on | |
923 | * vblanks... | |
924 | * Currently, the result of us stealing a vblank from the irq | |
925 | * handler is that a single frame will be skipped during swapbuffers. | |
926 | */ | |
927 | I915_WRITE(pipestat_reg, | |
928 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
929 | ||
9d0498a2 | 930 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
931 | if (wait_for(I915_READ(pipestat_reg) & |
932 | PIPE_VBLANK_INTERRUPT_STATUS, | |
933 | 50)) | |
9d0498a2 JB |
934 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
935 | } | |
936 | ||
ab7ad7f6 KP |
937 | /* |
938 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
939 | * @dev: drm device |
940 | * @pipe: pipe to wait for | |
941 | * | |
942 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
943 | * spinning on the vblank interrupt status bit, since we won't actually | |
944 | * see an interrupt when the pipe is disabled. | |
945 | * | |
ab7ad7f6 KP |
946 | * On Gen4 and above: |
947 | * wait for the pipe register state bit to turn off | |
948 | * | |
949 | * Otherwise: | |
950 | * wait for the display line value to settle (it usually | |
951 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 952 | * |
9d0498a2 | 953 | */ |
58e10eb9 | 954 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
955 | { |
956 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
957 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
958 | pipe); | |
ab7ad7f6 KP |
959 | |
960 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 961 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
962 | |
963 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
964 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
965 | 100)) | |
284637d9 | 966 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 967 | } else { |
837ba00f | 968 | u32 last_line, line_mask; |
58e10eb9 | 969 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
970 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
971 | ||
837ba00f PZ |
972 | if (IS_GEN2(dev)) |
973 | line_mask = DSL_LINEMASK_GEN2; | |
974 | else | |
975 | line_mask = DSL_LINEMASK_GEN3; | |
976 | ||
ab7ad7f6 KP |
977 | /* Wait for the display line to settle */ |
978 | do { | |
837ba00f | 979 | last_line = I915_READ(reg) & line_mask; |
ab7ad7f6 | 980 | mdelay(5); |
837ba00f | 981 | } while (((I915_READ(reg) & line_mask) != last_line) && |
ab7ad7f6 KP |
982 | time_after(timeout, jiffies)); |
983 | if (time_after(jiffies, timeout)) | |
284637d9 | 984 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 985 | } |
79e53945 JB |
986 | } |
987 | ||
b0ea7d37 DL |
988 | /* |
989 | * ibx_digital_port_connected - is the specified port connected? | |
990 | * @dev_priv: i915 private structure | |
991 | * @port: the port to test | |
992 | * | |
993 | * Returns true if @port is connected, false otherwise. | |
994 | */ | |
995 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
996 | struct intel_digital_port *port) | |
997 | { | |
998 | u32 bit; | |
999 | ||
c36346e3 DL |
1000 | if (HAS_PCH_IBX(dev_priv->dev)) { |
1001 | switch(port->port) { | |
1002 | case PORT_B: | |
1003 | bit = SDE_PORTB_HOTPLUG; | |
1004 | break; | |
1005 | case PORT_C: | |
1006 | bit = SDE_PORTC_HOTPLUG; | |
1007 | break; | |
1008 | case PORT_D: | |
1009 | bit = SDE_PORTD_HOTPLUG; | |
1010 | break; | |
1011 | default: | |
1012 | return true; | |
1013 | } | |
1014 | } else { | |
1015 | switch(port->port) { | |
1016 | case PORT_B: | |
1017 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1018 | break; | |
1019 | case PORT_C: | |
1020 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1021 | break; | |
1022 | case PORT_D: | |
1023 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1024 | break; | |
1025 | default: | |
1026 | return true; | |
1027 | } | |
b0ea7d37 DL |
1028 | } |
1029 | ||
1030 | return I915_READ(SDEISR) & bit; | |
1031 | } | |
1032 | ||
b24e7179 JB |
1033 | static const char *state_string(bool enabled) |
1034 | { | |
1035 | return enabled ? "on" : "off"; | |
1036 | } | |
1037 | ||
1038 | /* Only for pre-ILK configs */ | |
1039 | static void assert_pll(struct drm_i915_private *dev_priv, | |
1040 | enum pipe pipe, bool state) | |
1041 | { | |
1042 | int reg; | |
1043 | u32 val; | |
1044 | bool cur_state; | |
1045 | ||
1046 | reg = DPLL(pipe); | |
1047 | val = I915_READ(reg); | |
1048 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1049 | WARN(cur_state != state, | |
1050 | "PLL state assertion failure (expected %s, current %s)\n", | |
1051 | state_string(state), state_string(cur_state)); | |
1052 | } | |
1053 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
1054 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
1055 | ||
040484af JB |
1056 | /* For ILK+ */ |
1057 | static void assert_pch_pll(struct drm_i915_private *dev_priv, | |
92b27b08 CW |
1058 | struct intel_pch_pll *pll, |
1059 | struct intel_crtc *crtc, | |
1060 | bool state) | |
040484af | 1061 | { |
040484af JB |
1062 | u32 val; |
1063 | bool cur_state; | |
1064 | ||
9d82aa17 ED |
1065 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1066 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
1067 | return; | |
1068 | } | |
1069 | ||
92b27b08 CW |
1070 | if (WARN (!pll, |
1071 | "asserting PCH PLL %s with no PLL\n", state_string(state))) | |
ee7b9f93 | 1072 | return; |
ee7b9f93 | 1073 | |
92b27b08 CW |
1074 | val = I915_READ(pll->pll_reg); |
1075 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1076 | WARN(cur_state != state, | |
1077 | "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n", | |
1078 | pll->pll_reg, state_string(state), state_string(cur_state), val); | |
1079 | ||
1080 | /* Make sure the selected PLL is correctly attached to the transcoder */ | |
1081 | if (crtc && HAS_PCH_CPT(dev_priv->dev)) { | |
d3ccbe86 JB |
1082 | u32 pch_dpll; |
1083 | ||
1084 | pch_dpll = I915_READ(PCH_DPLL_SEL); | |
92b27b08 CW |
1085 | cur_state = pll->pll_reg == _PCH_DPLL_B; |
1086 | if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state, | |
1087 | "PLL[%d] not attached to this transcoder %d: %08x\n", | |
1088 | cur_state, crtc->pipe, pch_dpll)) { | |
1089 | cur_state = !!(val >> (4*crtc->pipe + 3)); | |
1090 | WARN(cur_state != state, | |
1091 | "PLL[%d] not %s on this transcoder %d: %08x\n", | |
1092 | pll->pll_reg == _PCH_DPLL_B, | |
1093 | state_string(state), | |
1094 | crtc->pipe, | |
1095 | val); | |
1096 | } | |
d3ccbe86 | 1097 | } |
040484af | 1098 | } |
92b27b08 CW |
1099 | #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true) |
1100 | #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false) | |
040484af JB |
1101 | |
1102 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1103 | enum pipe pipe, bool state) | |
1104 | { | |
1105 | int reg; | |
1106 | u32 val; | |
1107 | bool cur_state; | |
ad80a810 PZ |
1108 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1109 | pipe); | |
040484af | 1110 | |
affa9354 PZ |
1111 | if (HAS_DDI(dev_priv->dev)) { |
1112 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1113 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1114 | val = I915_READ(reg); |
ad80a810 | 1115 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1116 | } else { |
1117 | reg = FDI_TX_CTL(pipe); | |
1118 | val = I915_READ(reg); | |
1119 | cur_state = !!(val & FDI_TX_ENABLE); | |
1120 | } | |
040484af JB |
1121 | WARN(cur_state != state, |
1122 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1123 | state_string(state), state_string(cur_state)); | |
1124 | } | |
1125 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1126 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1127 | ||
1128 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1129 | enum pipe pipe, bool state) | |
1130 | { | |
1131 | int reg; | |
1132 | u32 val; | |
1133 | bool cur_state; | |
1134 | ||
d63fa0dc PZ |
1135 | reg = FDI_RX_CTL(pipe); |
1136 | val = I915_READ(reg); | |
1137 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1138 | WARN(cur_state != state, |
1139 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1140 | state_string(state), state_string(cur_state)); | |
1141 | } | |
1142 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1143 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1144 | ||
1145 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1146 | enum pipe pipe) | |
1147 | { | |
1148 | int reg; | |
1149 | u32 val; | |
1150 | ||
1151 | /* ILK FDI PLL is always enabled */ | |
1152 | if (dev_priv->info->gen == 5) | |
1153 | return; | |
1154 | ||
bf507ef7 | 1155 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1156 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1157 | return; |
1158 | ||
040484af JB |
1159 | reg = FDI_TX_CTL(pipe); |
1160 | val = I915_READ(reg); | |
1161 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1162 | } | |
1163 | ||
1164 | static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, | |
1165 | enum pipe pipe) | |
1166 | { | |
1167 | int reg; | |
1168 | u32 val; | |
1169 | ||
1170 | reg = FDI_RX_CTL(pipe); | |
1171 | val = I915_READ(reg); | |
1172 | WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); | |
1173 | } | |
1174 | ||
ea0760cf JB |
1175 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1176 | enum pipe pipe) | |
1177 | { | |
1178 | int pp_reg, lvds_reg; | |
1179 | u32 val; | |
1180 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1181 | bool locked = true; |
ea0760cf JB |
1182 | |
1183 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1184 | pp_reg = PCH_PP_CONTROL; | |
1185 | lvds_reg = PCH_LVDS; | |
1186 | } else { | |
1187 | pp_reg = PP_CONTROL; | |
1188 | lvds_reg = LVDS; | |
1189 | } | |
1190 | ||
1191 | val = I915_READ(pp_reg); | |
1192 | if (!(val & PANEL_POWER_ON) || | |
1193 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1194 | locked = false; | |
1195 | ||
1196 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1197 | panel_pipe = PIPE_B; | |
1198 | ||
1199 | WARN(panel_pipe == pipe && locked, | |
1200 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1201 | pipe_name(pipe)); |
ea0760cf JB |
1202 | } |
1203 | ||
b840d907 JB |
1204 | void assert_pipe(struct drm_i915_private *dev_priv, |
1205 | enum pipe pipe, bool state) | |
b24e7179 JB |
1206 | { |
1207 | int reg; | |
1208 | u32 val; | |
63d7bbe9 | 1209 | bool cur_state; |
702e7a56 PZ |
1210 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1211 | pipe); | |
b24e7179 | 1212 | |
8e636784 DV |
1213 | /* if we need the pipe A quirk it must be always on */ |
1214 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1215 | state = true; | |
1216 | ||
69310161 PZ |
1217 | if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP && |
1218 | !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) { | |
1219 | cur_state = false; | |
1220 | } else { | |
1221 | reg = PIPECONF(cpu_transcoder); | |
1222 | val = I915_READ(reg); | |
1223 | cur_state = !!(val & PIPECONF_ENABLE); | |
1224 | } | |
1225 | ||
63d7bbe9 JB |
1226 | WARN(cur_state != state, |
1227 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1228 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1229 | } |
1230 | ||
931872fc CW |
1231 | static void assert_plane(struct drm_i915_private *dev_priv, |
1232 | enum plane plane, bool state) | |
b24e7179 JB |
1233 | { |
1234 | int reg; | |
1235 | u32 val; | |
931872fc | 1236 | bool cur_state; |
b24e7179 JB |
1237 | |
1238 | reg = DSPCNTR(plane); | |
1239 | val = I915_READ(reg); | |
931872fc CW |
1240 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1241 | WARN(cur_state != state, | |
1242 | "plane %c assertion failure (expected %s, current %s)\n", | |
1243 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1244 | } |
1245 | ||
931872fc CW |
1246 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1247 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1248 | ||
b24e7179 JB |
1249 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1250 | enum pipe pipe) | |
1251 | { | |
1252 | int reg, i; | |
1253 | u32 val; | |
1254 | int cur_pipe; | |
1255 | ||
19ec1358 | 1256 | /* Planes are fixed to pipes on ILK+ */ |
28c05794 AJ |
1257 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
1258 | reg = DSPCNTR(pipe); | |
1259 | val = I915_READ(reg); | |
1260 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1261 | "plane %c assertion failure, should be disabled but not\n", | |
1262 | plane_name(pipe)); | |
19ec1358 | 1263 | return; |
28c05794 | 1264 | } |
19ec1358 | 1265 | |
b24e7179 JB |
1266 | /* Need to check both planes against the pipe */ |
1267 | for (i = 0; i < 2; i++) { | |
1268 | reg = DSPCNTR(i); | |
1269 | val = I915_READ(reg); | |
1270 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1271 | DISPPLANE_SEL_PIPE_SHIFT; | |
1272 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1273 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1274 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1275 | } |
1276 | } | |
1277 | ||
92f2584a JB |
1278 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1279 | { | |
1280 | u32 val; | |
1281 | bool enabled; | |
1282 | ||
9d82aa17 ED |
1283 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1284 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); | |
1285 | return; | |
1286 | } | |
1287 | ||
92f2584a JB |
1288 | val = I915_READ(PCH_DREF_CONTROL); |
1289 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1290 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1291 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1292 | } | |
1293 | ||
1294 | static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, | |
1295 | enum pipe pipe) | |
1296 | { | |
1297 | int reg; | |
1298 | u32 val; | |
1299 | bool enabled; | |
1300 | ||
1301 | reg = TRANSCONF(pipe); | |
1302 | val = I915_READ(reg); | |
1303 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1304 | WARN(enabled, |
1305 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1306 | pipe_name(pipe)); | |
92f2584a JB |
1307 | } |
1308 | ||
4e634389 KP |
1309 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1310 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1311 | { |
1312 | if ((val & DP_PORT_EN) == 0) | |
1313 | return false; | |
1314 | ||
1315 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1316 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1317 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1318 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1319 | return false; | |
1320 | } else { | |
1321 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1322 | return false; | |
1323 | } | |
1324 | return true; | |
1325 | } | |
1326 | ||
1519b995 KP |
1327 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1328 | enum pipe pipe, u32 val) | |
1329 | { | |
1330 | if ((val & PORT_ENABLE) == 0) | |
1331 | return false; | |
1332 | ||
1333 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1334 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1335 | return false; | |
1336 | } else { | |
1337 | if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) | |
1338 | return false; | |
1339 | } | |
1340 | return true; | |
1341 | } | |
1342 | ||
1343 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1344 | enum pipe pipe, u32 val) | |
1345 | { | |
1346 | if ((val & LVDS_PORT_EN) == 0) | |
1347 | return false; | |
1348 | ||
1349 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1350 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1351 | return false; | |
1352 | } else { | |
1353 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1354 | return false; | |
1355 | } | |
1356 | return true; | |
1357 | } | |
1358 | ||
1359 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1360 | enum pipe pipe, u32 val) | |
1361 | { | |
1362 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1363 | return false; | |
1364 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1365 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1366 | return false; | |
1367 | } else { | |
1368 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1369 | return false; | |
1370 | } | |
1371 | return true; | |
1372 | } | |
1373 | ||
291906f1 | 1374 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1375 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1376 | { |
47a05eca | 1377 | u32 val = I915_READ(reg); |
4e634389 | 1378 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1379 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1380 | reg, pipe_name(pipe)); |
de9a35ab | 1381 | |
75c5da27 DV |
1382 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1383 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1384 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1385 | } |
1386 | ||
1387 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1388 | enum pipe pipe, int reg) | |
1389 | { | |
47a05eca | 1390 | u32 val = I915_READ(reg); |
b70ad586 | 1391 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1392 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1393 | reg, pipe_name(pipe)); |
de9a35ab | 1394 | |
75c5da27 DV |
1395 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0 |
1396 | && (val & SDVO_PIPE_B_SELECT), | |
de9a35ab | 1397 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1398 | } |
1399 | ||
1400 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1401 | enum pipe pipe) | |
1402 | { | |
1403 | int reg; | |
1404 | u32 val; | |
291906f1 | 1405 | |
f0575e92 KP |
1406 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1407 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1408 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1409 | |
1410 | reg = PCH_ADPA; | |
1411 | val = I915_READ(reg); | |
b70ad586 | 1412 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1413 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1414 | pipe_name(pipe)); |
291906f1 JB |
1415 | |
1416 | reg = PCH_LVDS; | |
1417 | val = I915_READ(reg); | |
b70ad586 | 1418 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1419 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1420 | pipe_name(pipe)); |
291906f1 JB |
1421 | |
1422 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); | |
1423 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); | |
1424 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); | |
1425 | } | |
1426 | ||
63d7bbe9 JB |
1427 | /** |
1428 | * intel_enable_pll - enable a PLL | |
1429 | * @dev_priv: i915 private structure | |
1430 | * @pipe: pipe PLL to enable | |
1431 | * | |
1432 | * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to | |
1433 | * make sure the PLL reg is writable first though, since the panel write | |
1434 | * protect mechanism may be enabled. | |
1435 | * | |
1436 | * Note! This is for pre-ILK only. | |
7434a255 TR |
1437 | * |
1438 | * Unfortunately needed by dvo_ns2501 since the dvo depends on it running. | |
63d7bbe9 JB |
1439 | */ |
1440 | static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1441 | { | |
1442 | int reg; | |
1443 | u32 val; | |
1444 | ||
1445 | /* No really, not for ILK+ */ | |
a0c4da24 | 1446 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5); |
63d7bbe9 JB |
1447 | |
1448 | /* PLL is protected by panel, make sure we can write it */ | |
1449 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
1450 | assert_panel_unlocked(dev_priv, pipe); | |
1451 | ||
1452 | reg = DPLL(pipe); | |
1453 | val = I915_READ(reg); | |
1454 | val |= DPLL_VCO_ENABLE; | |
1455 | ||
1456 | /* We do this three times for luck */ | |
1457 | I915_WRITE(reg, val); | |
1458 | POSTING_READ(reg); | |
1459 | udelay(150); /* wait for warmup */ | |
1460 | I915_WRITE(reg, val); | |
1461 | POSTING_READ(reg); | |
1462 | udelay(150); /* wait for warmup */ | |
1463 | I915_WRITE(reg, val); | |
1464 | POSTING_READ(reg); | |
1465 | udelay(150); /* wait for warmup */ | |
1466 | } | |
1467 | ||
1468 | /** | |
1469 | * intel_disable_pll - disable a PLL | |
1470 | * @dev_priv: i915 private structure | |
1471 | * @pipe: pipe PLL to disable | |
1472 | * | |
1473 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1474 | * | |
1475 | * Note! This is for pre-ILK only. | |
1476 | */ | |
1477 | static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1478 | { | |
1479 | int reg; | |
1480 | u32 val; | |
1481 | ||
1482 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1483 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1484 | return; | |
1485 | ||
1486 | /* Make sure the pipe isn't still relying on us */ | |
1487 | assert_pipe_disabled(dev_priv, pipe); | |
1488 | ||
1489 | reg = DPLL(pipe); | |
1490 | val = I915_READ(reg); | |
1491 | val &= ~DPLL_VCO_ENABLE; | |
1492 | I915_WRITE(reg, val); | |
1493 | POSTING_READ(reg); | |
1494 | } | |
1495 | ||
a416edef ED |
1496 | /* SBI access */ |
1497 | static void | |
988d6ee8 PZ |
1498 | intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, |
1499 | enum intel_sbi_destination destination) | |
a416edef | 1500 | { |
988d6ee8 | 1501 | u32 tmp; |
a416edef | 1502 | |
09153000 | 1503 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
a416edef | 1504 | |
39fb50f6 | 1505 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
a416edef ED |
1506 | 100)) { |
1507 | DRM_ERROR("timeout waiting for SBI to become ready\n"); | |
09153000 | 1508 | return; |
a416edef ED |
1509 | } |
1510 | ||
988d6ee8 PZ |
1511 | I915_WRITE(SBI_ADDR, (reg << 16)); |
1512 | I915_WRITE(SBI_DATA, value); | |
1513 | ||
1514 | if (destination == SBI_ICLK) | |
1515 | tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR; | |
1516 | else | |
1517 | tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR; | |
1518 | I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp); | |
a416edef | 1519 | |
39fb50f6 | 1520 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
a416edef ED |
1521 | 100)) { |
1522 | DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); | |
09153000 | 1523 | return; |
a416edef | 1524 | } |
a416edef ED |
1525 | } |
1526 | ||
1527 | static u32 | |
988d6ee8 PZ |
1528 | intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
1529 | enum intel_sbi_destination destination) | |
a416edef | 1530 | { |
39fb50f6 | 1531 | u32 value = 0; |
09153000 | 1532 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
a416edef | 1533 | |
39fb50f6 | 1534 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
a416edef ED |
1535 | 100)) { |
1536 | DRM_ERROR("timeout waiting for SBI to become ready\n"); | |
09153000 | 1537 | return 0; |
a416edef ED |
1538 | } |
1539 | ||
988d6ee8 PZ |
1540 | I915_WRITE(SBI_ADDR, (reg << 16)); |
1541 | ||
1542 | if (destination == SBI_ICLK) | |
1543 | value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD; | |
1544 | else | |
1545 | value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD; | |
1546 | I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY); | |
a416edef | 1547 | |
39fb50f6 | 1548 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
a416edef ED |
1549 | 100)) { |
1550 | DRM_ERROR("timeout waiting for SBI to complete read transaction\n"); | |
09153000 | 1551 | return 0; |
a416edef ED |
1552 | } |
1553 | ||
09153000 | 1554 | return I915_READ(SBI_DATA); |
a416edef ED |
1555 | } |
1556 | ||
92f2584a | 1557 | /** |
b6b4e185 | 1558 | * ironlake_enable_pch_pll - enable PCH PLL |
92f2584a JB |
1559 | * @dev_priv: i915 private structure |
1560 | * @pipe: pipe PLL to enable | |
1561 | * | |
1562 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1563 | * drives the transcoder clock. | |
1564 | */ | |
b6b4e185 | 1565 | static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc) |
92f2584a | 1566 | { |
ee7b9f93 | 1567 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
48da64a8 | 1568 | struct intel_pch_pll *pll; |
92f2584a JB |
1569 | int reg; |
1570 | u32 val; | |
1571 | ||
48da64a8 | 1572 | /* PCH PLLs only available on ILK, SNB and IVB */ |
92f2584a | 1573 | BUG_ON(dev_priv->info->gen < 5); |
48da64a8 CW |
1574 | pll = intel_crtc->pch_pll; |
1575 | if (pll == NULL) | |
1576 | return; | |
1577 | ||
1578 | if (WARN_ON(pll->refcount == 0)) | |
1579 | return; | |
ee7b9f93 JB |
1580 | |
1581 | DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n", | |
1582 | pll->pll_reg, pll->active, pll->on, | |
1583 | intel_crtc->base.base.id); | |
92f2584a JB |
1584 | |
1585 | /* PCH refclock must be enabled first */ | |
1586 | assert_pch_refclk_enabled(dev_priv); | |
1587 | ||
ee7b9f93 | 1588 | if (pll->active++ && pll->on) { |
92b27b08 | 1589 | assert_pch_pll_enabled(dev_priv, pll, NULL); |
ee7b9f93 JB |
1590 | return; |
1591 | } | |
1592 | ||
1593 | DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg); | |
1594 | ||
1595 | reg = pll->pll_reg; | |
92f2584a JB |
1596 | val = I915_READ(reg); |
1597 | val |= DPLL_VCO_ENABLE; | |
1598 | I915_WRITE(reg, val); | |
1599 | POSTING_READ(reg); | |
1600 | udelay(200); | |
ee7b9f93 JB |
1601 | |
1602 | pll->on = true; | |
92f2584a JB |
1603 | } |
1604 | ||
ee7b9f93 | 1605 | static void intel_disable_pch_pll(struct intel_crtc *intel_crtc) |
92f2584a | 1606 | { |
ee7b9f93 JB |
1607 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; |
1608 | struct intel_pch_pll *pll = intel_crtc->pch_pll; | |
92f2584a | 1609 | int reg; |
ee7b9f93 | 1610 | u32 val; |
4c609cb8 | 1611 | |
92f2584a JB |
1612 | /* PCH only available on ILK+ */ |
1613 | BUG_ON(dev_priv->info->gen < 5); | |
ee7b9f93 JB |
1614 | if (pll == NULL) |
1615 | return; | |
92f2584a | 1616 | |
48da64a8 CW |
1617 | if (WARN_ON(pll->refcount == 0)) |
1618 | return; | |
7a419866 | 1619 | |
ee7b9f93 JB |
1620 | DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n", |
1621 | pll->pll_reg, pll->active, pll->on, | |
1622 | intel_crtc->base.base.id); | |
7a419866 | 1623 | |
48da64a8 | 1624 | if (WARN_ON(pll->active == 0)) { |
92b27b08 | 1625 | assert_pch_pll_disabled(dev_priv, pll, NULL); |
48da64a8 CW |
1626 | return; |
1627 | } | |
1628 | ||
ee7b9f93 | 1629 | if (--pll->active) { |
92b27b08 | 1630 | assert_pch_pll_enabled(dev_priv, pll, NULL); |
7a419866 | 1631 | return; |
ee7b9f93 JB |
1632 | } |
1633 | ||
1634 | DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg); | |
1635 | ||
1636 | /* Make sure transcoder isn't still depending on us */ | |
1637 | assert_transcoder_disabled(dev_priv, intel_crtc->pipe); | |
7a419866 | 1638 | |
ee7b9f93 | 1639 | reg = pll->pll_reg; |
92f2584a JB |
1640 | val = I915_READ(reg); |
1641 | val &= ~DPLL_VCO_ENABLE; | |
1642 | I915_WRITE(reg, val); | |
1643 | POSTING_READ(reg); | |
1644 | udelay(200); | |
ee7b9f93 JB |
1645 | |
1646 | pll->on = false; | |
92f2584a JB |
1647 | } |
1648 | ||
b8a4f404 PZ |
1649 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1650 | enum pipe pipe) | |
040484af | 1651 | { |
23670b32 | 1652 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1653 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
23670b32 | 1654 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1655 | |
1656 | /* PCH only available on ILK+ */ | |
1657 | BUG_ON(dev_priv->info->gen < 5); | |
1658 | ||
1659 | /* Make sure PCH DPLL is enabled */ | |
92b27b08 CW |
1660 | assert_pch_pll_enabled(dev_priv, |
1661 | to_intel_crtc(crtc)->pch_pll, | |
1662 | to_intel_crtc(crtc)); | |
040484af JB |
1663 | |
1664 | /* FDI must be feeding us bits for PCH ports */ | |
1665 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1666 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1667 | ||
23670b32 DV |
1668 | if (HAS_PCH_CPT(dev)) { |
1669 | /* Workaround: Set the timing override bit before enabling the | |
1670 | * pch transcoder. */ | |
1671 | reg = TRANS_CHICKEN2(pipe); | |
1672 | val = I915_READ(reg); | |
1673 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1674 | I915_WRITE(reg, val); | |
59c859d6 | 1675 | } |
23670b32 | 1676 | |
040484af JB |
1677 | reg = TRANSCONF(pipe); |
1678 | val = I915_READ(reg); | |
5f7f726d | 1679 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1680 | |
1681 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1682 | /* | |
1683 | * make the BPC in transcoder be consistent with | |
1684 | * that in pipeconf reg. | |
1685 | */ | |
dfd07d72 DV |
1686 | val &= ~PIPECONF_BPC_MASK; |
1687 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1688 | } |
5f7f726d PZ |
1689 | |
1690 | val &= ~TRANS_INTERLACE_MASK; | |
1691 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1692 | if (HAS_PCH_IBX(dev_priv->dev) && |
1693 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1694 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1695 | else | |
1696 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1697 | else |
1698 | val |= TRANS_PROGRESSIVE; | |
1699 | ||
040484af JB |
1700 | I915_WRITE(reg, val | TRANS_ENABLE); |
1701 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
1702 | DRM_ERROR("failed to enable transcoder %d\n", pipe); | |
1703 | } | |
1704 | ||
8fb033d7 | 1705 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1706 | enum transcoder cpu_transcoder) |
040484af | 1707 | { |
8fb033d7 | 1708 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1709 | |
1710 | /* PCH only available on ILK+ */ | |
1711 | BUG_ON(dev_priv->info->gen < 5); | |
1712 | ||
8fb033d7 | 1713 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1714 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1715 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1716 | |
223a6fdf PZ |
1717 | /* Workaround: set timing override bit. */ |
1718 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1719 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1720 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1721 | ||
25f3ef11 | 1722 | val = TRANS_ENABLE; |
937bb610 | 1723 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1724 | |
9a76b1c6 PZ |
1725 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1726 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1727 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1728 | else |
1729 | val |= TRANS_PROGRESSIVE; | |
1730 | ||
25f3ef11 | 1731 | I915_WRITE(TRANSCONF(TRANSCODER_A), val); |
937bb610 PZ |
1732 | if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100)) |
1733 | DRM_ERROR("Failed to enable PCH transcoder\n"); | |
8fb033d7 PZ |
1734 | } |
1735 | ||
b8a4f404 PZ |
1736 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1737 | enum pipe pipe) | |
040484af | 1738 | { |
23670b32 DV |
1739 | struct drm_device *dev = dev_priv->dev; |
1740 | uint32_t reg, val; | |
040484af JB |
1741 | |
1742 | /* FDI relies on the transcoder */ | |
1743 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1744 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1745 | ||
291906f1 JB |
1746 | /* Ports must be off as well */ |
1747 | assert_pch_ports_disabled(dev_priv, pipe); | |
1748 | ||
040484af JB |
1749 | reg = TRANSCONF(pipe); |
1750 | val = I915_READ(reg); | |
1751 | val &= ~TRANS_ENABLE; | |
1752 | I915_WRITE(reg, val); | |
1753 | /* wait for PCH transcoder off, transcoder state */ | |
1754 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4c9c18c2 | 1755 | DRM_ERROR("failed to disable transcoder %d\n", pipe); |
23670b32 DV |
1756 | |
1757 | if (!HAS_PCH_IBX(dev)) { | |
1758 | /* Workaround: Clear the timing override chicken bit again. */ | |
1759 | reg = TRANS_CHICKEN2(pipe); | |
1760 | val = I915_READ(reg); | |
1761 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1762 | I915_WRITE(reg, val); | |
1763 | } | |
040484af JB |
1764 | } |
1765 | ||
ab4d966c | 1766 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1767 | { |
8fb033d7 PZ |
1768 | u32 val; |
1769 | ||
8a52fd9f | 1770 | val = I915_READ(_TRANSACONF); |
8fb033d7 | 1771 | val &= ~TRANS_ENABLE; |
8a52fd9f | 1772 | I915_WRITE(_TRANSACONF, val); |
8fb033d7 | 1773 | /* wait for PCH transcoder off, transcoder state */ |
8a52fd9f PZ |
1774 | if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50)) |
1775 | DRM_ERROR("Failed to disable PCH transcoder\n"); | |
223a6fdf PZ |
1776 | |
1777 | /* Workaround: clear timing override bit. */ | |
1778 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1779 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1780 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1781 | } |
1782 | ||
b24e7179 | 1783 | /** |
309cfea8 | 1784 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1785 | * @dev_priv: i915 private structure |
1786 | * @pipe: pipe to enable | |
040484af | 1787 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1788 | * |
1789 | * Enable @pipe, making sure that various hardware specific requirements | |
1790 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1791 | * | |
1792 | * @pipe should be %PIPE_A or %PIPE_B. | |
1793 | * | |
1794 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1795 | * returning. | |
1796 | */ | |
040484af JB |
1797 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1798 | bool pch_port) | |
b24e7179 | 1799 | { |
702e7a56 PZ |
1800 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1801 | pipe); | |
1a240d4d | 1802 | enum pipe pch_transcoder; |
b24e7179 JB |
1803 | int reg; |
1804 | u32 val; | |
1805 | ||
681e5811 | 1806 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1807 | pch_transcoder = TRANSCODER_A; |
1808 | else | |
1809 | pch_transcoder = pipe; | |
1810 | ||
b24e7179 JB |
1811 | /* |
1812 | * A pipe without a PLL won't actually be able to drive bits from | |
1813 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1814 | * need the check. | |
1815 | */ | |
1816 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
1817 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1818 | else { |
1819 | if (pch_port) { | |
1820 | /* if driving the PCH, we need FDI enabled */ | |
cc391bbb | 1821 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1822 | assert_fdi_tx_pll_enabled(dev_priv, |
1823 | (enum pipe) cpu_transcoder); | |
040484af JB |
1824 | } |
1825 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1826 | } | |
b24e7179 | 1827 | |
702e7a56 | 1828 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1829 | val = I915_READ(reg); |
00d70b15 CW |
1830 | if (val & PIPECONF_ENABLE) |
1831 | return; | |
1832 | ||
1833 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1834 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1835 | } | |
1836 | ||
1837 | /** | |
309cfea8 | 1838 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1839 | * @dev_priv: i915 private structure |
1840 | * @pipe: pipe to disable | |
1841 | * | |
1842 | * Disable @pipe, making sure that various hardware specific requirements | |
1843 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1844 | * | |
1845 | * @pipe should be %PIPE_A or %PIPE_B. | |
1846 | * | |
1847 | * Will wait until the pipe has shut down before returning. | |
1848 | */ | |
1849 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1850 | enum pipe pipe) | |
1851 | { | |
702e7a56 PZ |
1852 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1853 | pipe); | |
b24e7179 JB |
1854 | int reg; |
1855 | u32 val; | |
1856 | ||
1857 | /* | |
1858 | * Make sure planes won't keep trying to pump pixels to us, | |
1859 | * or we might hang the display. | |
1860 | */ | |
1861 | assert_planes_disabled(dev_priv, pipe); | |
1862 | ||
1863 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1864 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1865 | return; | |
1866 | ||
702e7a56 | 1867 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1868 | val = I915_READ(reg); |
00d70b15 CW |
1869 | if ((val & PIPECONF_ENABLE) == 0) |
1870 | return; | |
1871 | ||
1872 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1873 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1874 | } | |
1875 | ||
d74362c9 KP |
1876 | /* |
1877 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1878 | * trigger in order to latch. The display address reg provides this. | |
1879 | */ | |
6f1d69b0 | 1880 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
d74362c9 KP |
1881 | enum plane plane) |
1882 | { | |
14f86147 DL |
1883 | if (dev_priv->info->gen >= 4) |
1884 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); | |
1885 | else | |
1886 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); | |
d74362c9 KP |
1887 | } |
1888 | ||
b24e7179 JB |
1889 | /** |
1890 | * intel_enable_plane - enable a display plane on a given pipe | |
1891 | * @dev_priv: i915 private structure | |
1892 | * @plane: plane to enable | |
1893 | * @pipe: pipe being fed | |
1894 | * | |
1895 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1896 | */ | |
1897 | static void intel_enable_plane(struct drm_i915_private *dev_priv, | |
1898 | enum plane plane, enum pipe pipe) | |
1899 | { | |
1900 | int reg; | |
1901 | u32 val; | |
1902 | ||
1903 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1904 | assert_pipe_enabled(dev_priv, pipe); | |
1905 | ||
1906 | reg = DSPCNTR(plane); | |
1907 | val = I915_READ(reg); | |
00d70b15 CW |
1908 | if (val & DISPLAY_PLANE_ENABLE) |
1909 | return; | |
1910 | ||
1911 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
d74362c9 | 1912 | intel_flush_display_plane(dev_priv, plane); |
b24e7179 JB |
1913 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1914 | } | |
1915 | ||
b24e7179 JB |
1916 | /** |
1917 | * intel_disable_plane - disable a display plane | |
1918 | * @dev_priv: i915 private structure | |
1919 | * @plane: plane to disable | |
1920 | * @pipe: pipe consuming the data | |
1921 | * | |
1922 | * Disable @plane; should be an independent operation. | |
1923 | */ | |
1924 | static void intel_disable_plane(struct drm_i915_private *dev_priv, | |
1925 | enum plane plane, enum pipe pipe) | |
1926 | { | |
1927 | int reg; | |
1928 | u32 val; | |
1929 | ||
1930 | reg = DSPCNTR(plane); | |
1931 | val = I915_READ(reg); | |
00d70b15 CW |
1932 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1933 | return; | |
1934 | ||
1935 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
b24e7179 JB |
1936 | intel_flush_display_plane(dev_priv, plane); |
1937 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1938 | } | |
1939 | ||
127bd2ac | 1940 | int |
48b956c5 | 1941 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1942 | struct drm_i915_gem_object *obj, |
919926ae | 1943 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1944 | { |
ce453d81 | 1945 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1946 | u32 alignment; |
1947 | int ret; | |
1948 | ||
05394f39 | 1949 | switch (obj->tiling_mode) { |
6b95a207 | 1950 | case I915_TILING_NONE: |
534843da CW |
1951 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1952 | alignment = 128 * 1024; | |
a6c45cf0 | 1953 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1954 | alignment = 4 * 1024; |
1955 | else | |
1956 | alignment = 64 * 1024; | |
6b95a207 KH |
1957 | break; |
1958 | case I915_TILING_X: | |
1959 | /* pin() will align the object as required by fence */ | |
1960 | alignment = 0; | |
1961 | break; | |
1962 | case I915_TILING_Y: | |
1963 | /* FIXME: Is this true? */ | |
1964 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
1965 | return -EINVAL; | |
1966 | default: | |
1967 | BUG(); | |
1968 | } | |
1969 | ||
ce453d81 | 1970 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 1971 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 1972 | if (ret) |
ce453d81 | 1973 | goto err_interruptible; |
6b95a207 KH |
1974 | |
1975 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1976 | * fence, whereas 965+ only requires a fence if using | |
1977 | * framebuffer compression. For simplicity, we always install | |
1978 | * a fence as the cost is not that onerous. | |
1979 | */ | |
06d98131 | 1980 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
1981 | if (ret) |
1982 | goto err_unpin; | |
1690e1eb | 1983 | |
9a5a53b3 | 1984 | i915_gem_object_pin_fence(obj); |
6b95a207 | 1985 | |
ce453d81 | 1986 | dev_priv->mm.interruptible = true; |
6b95a207 | 1987 | return 0; |
48b956c5 CW |
1988 | |
1989 | err_unpin: | |
1990 | i915_gem_object_unpin(obj); | |
ce453d81 CW |
1991 | err_interruptible: |
1992 | dev_priv->mm.interruptible = true; | |
48b956c5 | 1993 | return ret; |
6b95a207 KH |
1994 | } |
1995 | ||
1690e1eb CW |
1996 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1997 | { | |
1998 | i915_gem_object_unpin_fence(obj); | |
1999 | i915_gem_object_unpin(obj); | |
2000 | } | |
2001 | ||
c2c75131 DV |
2002 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2003 | * is assumed to be a power-of-two. */ | |
5a35e99e DL |
2004 | unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y, |
2005 | unsigned int bpp, | |
2006 | unsigned int pitch) | |
c2c75131 DV |
2007 | { |
2008 | int tile_rows, tiles; | |
2009 | ||
2010 | tile_rows = *y / 8; | |
2011 | *y %= 8; | |
2012 | tiles = *x / (512/bpp); | |
2013 | *x %= 512/bpp; | |
2014 | ||
2015 | return tile_rows * pitch * 8 + tiles * 4096; | |
2016 | } | |
2017 | ||
17638cd6 JB |
2018 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2019 | int x, int y) | |
81255565 JB |
2020 | { |
2021 | struct drm_device *dev = crtc->dev; | |
2022 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2023 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2024 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2025 | struct drm_i915_gem_object *obj; |
81255565 | 2026 | int plane = intel_crtc->plane; |
e506a0c6 | 2027 | unsigned long linear_offset; |
81255565 | 2028 | u32 dspcntr; |
5eddb70b | 2029 | u32 reg; |
81255565 JB |
2030 | |
2031 | switch (plane) { | |
2032 | case 0: | |
2033 | case 1: | |
2034 | break; | |
2035 | default: | |
2036 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2037 | return -EINVAL; | |
2038 | } | |
2039 | ||
2040 | intel_fb = to_intel_framebuffer(fb); | |
2041 | obj = intel_fb->obj; | |
81255565 | 2042 | |
5eddb70b CW |
2043 | reg = DSPCNTR(plane); |
2044 | dspcntr = I915_READ(reg); | |
81255565 JB |
2045 | /* Mask out pixel format bits in case we change it */ |
2046 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2047 | switch (fb->pixel_format) { |
2048 | case DRM_FORMAT_C8: | |
81255565 JB |
2049 | dspcntr |= DISPPLANE_8BPP; |
2050 | break; | |
57779d06 VS |
2051 | case DRM_FORMAT_XRGB1555: |
2052 | case DRM_FORMAT_ARGB1555: | |
2053 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2054 | break; |
57779d06 VS |
2055 | case DRM_FORMAT_RGB565: |
2056 | dspcntr |= DISPPLANE_BGRX565; | |
2057 | break; | |
2058 | case DRM_FORMAT_XRGB8888: | |
2059 | case DRM_FORMAT_ARGB8888: | |
2060 | dspcntr |= DISPPLANE_BGRX888; | |
2061 | break; | |
2062 | case DRM_FORMAT_XBGR8888: | |
2063 | case DRM_FORMAT_ABGR8888: | |
2064 | dspcntr |= DISPPLANE_RGBX888; | |
2065 | break; | |
2066 | case DRM_FORMAT_XRGB2101010: | |
2067 | case DRM_FORMAT_ARGB2101010: | |
2068 | dspcntr |= DISPPLANE_BGRX101010; | |
2069 | break; | |
2070 | case DRM_FORMAT_XBGR2101010: | |
2071 | case DRM_FORMAT_ABGR2101010: | |
2072 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2073 | break; |
2074 | default: | |
57779d06 | 2075 | DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format); |
81255565 JB |
2076 | return -EINVAL; |
2077 | } | |
57779d06 | 2078 | |
a6c45cf0 | 2079 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2080 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2081 | dspcntr |= DISPPLANE_TILED; |
2082 | else | |
2083 | dspcntr &= ~DISPPLANE_TILED; | |
2084 | } | |
2085 | ||
5eddb70b | 2086 | I915_WRITE(reg, dspcntr); |
81255565 | 2087 | |
e506a0c6 | 2088 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2089 | |
c2c75131 DV |
2090 | if (INTEL_INFO(dev)->gen >= 4) { |
2091 | intel_crtc->dspaddr_offset = | |
5a35e99e DL |
2092 | intel_gen4_compute_offset_xtiled(&x, &y, |
2093 | fb->bits_per_pixel / 8, | |
2094 | fb->pitches[0]); | |
c2c75131 DV |
2095 | linear_offset -= intel_crtc->dspaddr_offset; |
2096 | } else { | |
e506a0c6 | 2097 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2098 | } |
e506a0c6 DV |
2099 | |
2100 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", | |
2101 | obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); | |
01f2c773 | 2102 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2103 | if (INTEL_INFO(dev)->gen >= 4) { |
c2c75131 DV |
2104 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2105 | obj->gtt_offset + intel_crtc->dspaddr_offset); | |
5eddb70b | 2106 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2107 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2108 | } else |
e506a0c6 | 2109 | I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset); |
5eddb70b | 2110 | POSTING_READ(reg); |
81255565 | 2111 | |
17638cd6 JB |
2112 | return 0; |
2113 | } | |
2114 | ||
2115 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2116 | struct drm_framebuffer *fb, int x, int y) | |
2117 | { | |
2118 | struct drm_device *dev = crtc->dev; | |
2119 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2120 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2121 | struct intel_framebuffer *intel_fb; | |
2122 | struct drm_i915_gem_object *obj; | |
2123 | int plane = intel_crtc->plane; | |
e506a0c6 | 2124 | unsigned long linear_offset; |
17638cd6 JB |
2125 | u32 dspcntr; |
2126 | u32 reg; | |
2127 | ||
2128 | switch (plane) { | |
2129 | case 0: | |
2130 | case 1: | |
27f8227b | 2131 | case 2: |
17638cd6 JB |
2132 | break; |
2133 | default: | |
2134 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2135 | return -EINVAL; | |
2136 | } | |
2137 | ||
2138 | intel_fb = to_intel_framebuffer(fb); | |
2139 | obj = intel_fb->obj; | |
2140 | ||
2141 | reg = DSPCNTR(plane); | |
2142 | dspcntr = I915_READ(reg); | |
2143 | /* Mask out pixel format bits in case we change it */ | |
2144 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2145 | switch (fb->pixel_format) { |
2146 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2147 | dspcntr |= DISPPLANE_8BPP; |
2148 | break; | |
57779d06 VS |
2149 | case DRM_FORMAT_RGB565: |
2150 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2151 | break; |
57779d06 VS |
2152 | case DRM_FORMAT_XRGB8888: |
2153 | case DRM_FORMAT_ARGB8888: | |
2154 | dspcntr |= DISPPLANE_BGRX888; | |
2155 | break; | |
2156 | case DRM_FORMAT_XBGR8888: | |
2157 | case DRM_FORMAT_ABGR8888: | |
2158 | dspcntr |= DISPPLANE_RGBX888; | |
2159 | break; | |
2160 | case DRM_FORMAT_XRGB2101010: | |
2161 | case DRM_FORMAT_ARGB2101010: | |
2162 | dspcntr |= DISPPLANE_BGRX101010; | |
2163 | break; | |
2164 | case DRM_FORMAT_XBGR2101010: | |
2165 | case DRM_FORMAT_ABGR2101010: | |
2166 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2167 | break; |
2168 | default: | |
57779d06 | 2169 | DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format); |
17638cd6 JB |
2170 | return -EINVAL; |
2171 | } | |
2172 | ||
2173 | if (obj->tiling_mode != I915_TILING_NONE) | |
2174 | dspcntr |= DISPPLANE_TILED; | |
2175 | else | |
2176 | dspcntr &= ~DISPPLANE_TILED; | |
2177 | ||
2178 | /* must disable */ | |
2179 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2180 | ||
2181 | I915_WRITE(reg, dspcntr); | |
2182 | ||
e506a0c6 | 2183 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2184 | intel_crtc->dspaddr_offset = |
5a35e99e DL |
2185 | intel_gen4_compute_offset_xtiled(&x, &y, |
2186 | fb->bits_per_pixel / 8, | |
2187 | fb->pitches[0]); | |
c2c75131 | 2188 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2189 | |
e506a0c6 DV |
2190 | DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", |
2191 | obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); | |
01f2c773 | 2192 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
c2c75131 DV |
2193 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
2194 | obj->gtt_offset + intel_crtc->dspaddr_offset); | |
bc1c91eb DL |
2195 | if (IS_HASWELL(dev)) { |
2196 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); | |
2197 | } else { | |
2198 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2199 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2200 | } | |
17638cd6 JB |
2201 | POSTING_READ(reg); |
2202 | ||
2203 | return 0; | |
2204 | } | |
2205 | ||
2206 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2207 | static int | |
2208 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2209 | int x, int y, enum mode_set_atomic state) | |
2210 | { | |
2211 | struct drm_device *dev = crtc->dev; | |
2212 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2213 | |
6b8e6ed0 CW |
2214 | if (dev_priv->display.disable_fbc) |
2215 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2216 | intel_increase_pllclock(crtc); |
81255565 | 2217 | |
6b8e6ed0 | 2218 | return dev_priv->display.update_plane(crtc, fb, x, y); |
81255565 JB |
2219 | } |
2220 | ||
14667a4b CW |
2221 | static int |
2222 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2223 | { | |
2224 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2225 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2226 | bool was_interruptible = dev_priv->mm.interruptible; | |
2227 | int ret; | |
2228 | ||
2c10d571 DV |
2229 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
2230 | ||
14667a4b | 2231 | wait_event(dev_priv->pending_flip_queue, |
1f83fee0 | 2232 | i915_reset_in_progress(&dev_priv->gpu_error) || |
14667a4b CW |
2233 | atomic_read(&obj->pending_flip) == 0); |
2234 | ||
2235 | /* Big Hammer, we also need to ensure that any pending | |
2236 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2237 | * current scanout is retired before unpinning the old | |
2238 | * framebuffer. | |
2239 | * | |
2240 | * This should only fail upon a hung GPU, in which case we | |
2241 | * can safely continue. | |
2242 | */ | |
2243 | dev_priv->mm.interruptible = false; | |
2244 | ret = i915_gem_object_finish_gpu(obj); | |
2245 | dev_priv->mm.interruptible = was_interruptible; | |
2246 | ||
2247 | return ret; | |
2248 | } | |
2249 | ||
198598d0 VS |
2250 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
2251 | { | |
2252 | struct drm_device *dev = crtc->dev; | |
2253 | struct drm_i915_master_private *master_priv; | |
2254 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2255 | ||
2256 | if (!dev->primary->master) | |
2257 | return; | |
2258 | ||
2259 | master_priv = dev->primary->master->driver_priv; | |
2260 | if (!master_priv->sarea_priv) | |
2261 | return; | |
2262 | ||
2263 | switch (intel_crtc->pipe) { | |
2264 | case 0: | |
2265 | master_priv->sarea_priv->pipeA_x = x; | |
2266 | master_priv->sarea_priv->pipeA_y = y; | |
2267 | break; | |
2268 | case 1: | |
2269 | master_priv->sarea_priv->pipeB_x = x; | |
2270 | master_priv->sarea_priv->pipeB_y = y; | |
2271 | break; | |
2272 | default: | |
2273 | break; | |
2274 | } | |
2275 | } | |
2276 | ||
5c3b82e2 | 2277 | static int |
3c4fdcfb | 2278 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2279 | struct drm_framebuffer *fb) |
79e53945 JB |
2280 | { |
2281 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2282 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2283 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2284 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2285 | int ret; |
79e53945 JB |
2286 | |
2287 | /* no fb bound */ | |
94352cf9 | 2288 | if (!fb) { |
a5071c2f | 2289 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2290 | return 0; |
2291 | } | |
2292 | ||
5826eca5 ED |
2293 | if(intel_crtc->plane > dev_priv->num_pipe) { |
2294 | DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n", | |
2295 | intel_crtc->plane, | |
2296 | dev_priv->num_pipe); | |
5c3b82e2 | 2297 | return -EINVAL; |
79e53945 JB |
2298 | } |
2299 | ||
5c3b82e2 | 2300 | mutex_lock(&dev->struct_mutex); |
265db958 | 2301 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2302 | to_intel_framebuffer(fb)->obj, |
919926ae | 2303 | NULL); |
5c3b82e2 CW |
2304 | if (ret != 0) { |
2305 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2306 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2307 | return ret; |
2308 | } | |
79e53945 | 2309 | |
94352cf9 DV |
2310 | if (crtc->fb) |
2311 | intel_finish_fb(crtc->fb); | |
265db958 | 2312 | |
94352cf9 | 2313 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
4e6cfefc | 2314 | if (ret) { |
94352cf9 | 2315 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
5c3b82e2 | 2316 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2317 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2318 | return ret; |
79e53945 | 2319 | } |
3c4fdcfb | 2320 | |
94352cf9 DV |
2321 | old_fb = crtc->fb; |
2322 | crtc->fb = fb; | |
6c4c86f5 DV |
2323 | crtc->x = x; |
2324 | crtc->y = y; | |
94352cf9 | 2325 | |
b7f1de28 CW |
2326 | if (old_fb) { |
2327 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2328 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2329 | } |
652c393a | 2330 | |
6b8e6ed0 | 2331 | intel_update_fbc(dev); |
5c3b82e2 | 2332 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2333 | |
198598d0 | 2334 | intel_crtc_update_sarea_pos(crtc, x, y); |
5c3b82e2 CW |
2335 | |
2336 | return 0; | |
79e53945 JB |
2337 | } |
2338 | ||
5e84e1a4 ZW |
2339 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2340 | { | |
2341 | struct drm_device *dev = crtc->dev; | |
2342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2343 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2344 | int pipe = intel_crtc->pipe; | |
2345 | u32 reg, temp; | |
2346 | ||
2347 | /* enable normal train */ | |
2348 | reg = FDI_TX_CTL(pipe); | |
2349 | temp = I915_READ(reg); | |
61e499bf | 2350 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2351 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2352 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2353 | } else { |
2354 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2355 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2356 | } |
5e84e1a4 ZW |
2357 | I915_WRITE(reg, temp); |
2358 | ||
2359 | reg = FDI_RX_CTL(pipe); | |
2360 | temp = I915_READ(reg); | |
2361 | if (HAS_PCH_CPT(dev)) { | |
2362 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2363 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2364 | } else { | |
2365 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2366 | temp |= FDI_LINK_TRAIN_NONE; | |
2367 | } | |
2368 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2369 | ||
2370 | /* wait one idle pattern time */ | |
2371 | POSTING_READ(reg); | |
2372 | udelay(1000); | |
357555c0 JB |
2373 | |
2374 | /* IVB wants error correction enabled */ | |
2375 | if (IS_IVYBRIDGE(dev)) | |
2376 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2377 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2378 | } |
2379 | ||
01a415fd DV |
2380 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2381 | { | |
2382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2383 | struct intel_crtc *pipe_B_crtc = | |
2384 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2385 | struct intel_crtc *pipe_C_crtc = | |
2386 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2387 | uint32_t temp; | |
2388 | ||
2389 | /* When everything is off disable fdi C so that we could enable fdi B | |
2390 | * with all lanes. XXX: This misses the case where a pipe is not using | |
2391 | * any pch resources and so doesn't need any fdi lanes. */ | |
2392 | if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) { | |
2393 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
2394 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2395 | ||
2396 | temp = I915_READ(SOUTH_CHICKEN1); | |
2397 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2398 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2399 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2400 | } | |
2401 | } | |
2402 | ||
8db9d77b ZW |
2403 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2404 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2405 | { | |
2406 | struct drm_device *dev = crtc->dev; | |
2407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2408 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2409 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2410 | int plane = intel_crtc->plane; |
5eddb70b | 2411 | u32 reg, temp, tries; |
8db9d77b | 2412 | |
0fc932b8 JB |
2413 | /* FDI needs bits from pipe & plane first */ |
2414 | assert_pipe_enabled(dev_priv, pipe); | |
2415 | assert_plane_enabled(dev_priv, plane); | |
2416 | ||
e1a44743 AJ |
2417 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2418 | for train result */ | |
5eddb70b CW |
2419 | reg = FDI_RX_IMR(pipe); |
2420 | temp = I915_READ(reg); | |
e1a44743 AJ |
2421 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2422 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2423 | I915_WRITE(reg, temp); |
2424 | I915_READ(reg); | |
e1a44743 AJ |
2425 | udelay(150); |
2426 | ||
8db9d77b | 2427 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2428 | reg = FDI_TX_CTL(pipe); |
2429 | temp = I915_READ(reg); | |
77ffb597 AJ |
2430 | temp &= ~(7 << 19); |
2431 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2432 | temp &= ~FDI_LINK_TRAIN_NONE; |
2433 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2434 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2435 | |
5eddb70b CW |
2436 | reg = FDI_RX_CTL(pipe); |
2437 | temp = I915_READ(reg); | |
8db9d77b ZW |
2438 | temp &= ~FDI_LINK_TRAIN_NONE; |
2439 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2440 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2441 | ||
2442 | POSTING_READ(reg); | |
8db9d77b ZW |
2443 | udelay(150); |
2444 | ||
5b2adf89 | 2445 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2446 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2447 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2448 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2449 | |
5eddb70b | 2450 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2451 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2452 | temp = I915_READ(reg); |
8db9d77b ZW |
2453 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2454 | ||
2455 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2456 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2457 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2458 | break; |
2459 | } | |
8db9d77b | 2460 | } |
e1a44743 | 2461 | if (tries == 5) |
5eddb70b | 2462 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2463 | |
2464 | /* Train 2 */ | |
5eddb70b CW |
2465 | reg = FDI_TX_CTL(pipe); |
2466 | temp = I915_READ(reg); | |
8db9d77b ZW |
2467 | temp &= ~FDI_LINK_TRAIN_NONE; |
2468 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2469 | I915_WRITE(reg, temp); |
8db9d77b | 2470 | |
5eddb70b CW |
2471 | reg = FDI_RX_CTL(pipe); |
2472 | temp = I915_READ(reg); | |
8db9d77b ZW |
2473 | temp &= ~FDI_LINK_TRAIN_NONE; |
2474 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2475 | I915_WRITE(reg, temp); |
8db9d77b | 2476 | |
5eddb70b CW |
2477 | POSTING_READ(reg); |
2478 | udelay(150); | |
8db9d77b | 2479 | |
5eddb70b | 2480 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2481 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2482 | temp = I915_READ(reg); |
8db9d77b ZW |
2483 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2484 | ||
2485 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2486 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2487 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2488 | break; | |
2489 | } | |
8db9d77b | 2490 | } |
e1a44743 | 2491 | if (tries == 5) |
5eddb70b | 2492 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2493 | |
2494 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2495 | |
8db9d77b ZW |
2496 | } |
2497 | ||
0206e353 | 2498 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2499 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2500 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2501 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2502 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2503 | }; | |
2504 | ||
2505 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2506 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2507 | { | |
2508 | struct drm_device *dev = crtc->dev; | |
2509 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2510 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2511 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2512 | u32 reg, temp, i, retry; |
8db9d77b | 2513 | |
e1a44743 AJ |
2514 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2515 | for train result */ | |
5eddb70b CW |
2516 | reg = FDI_RX_IMR(pipe); |
2517 | temp = I915_READ(reg); | |
e1a44743 AJ |
2518 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2519 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2520 | I915_WRITE(reg, temp); |
2521 | ||
2522 | POSTING_READ(reg); | |
e1a44743 AJ |
2523 | udelay(150); |
2524 | ||
8db9d77b | 2525 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2526 | reg = FDI_TX_CTL(pipe); |
2527 | temp = I915_READ(reg); | |
77ffb597 AJ |
2528 | temp &= ~(7 << 19); |
2529 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2530 | temp &= ~FDI_LINK_TRAIN_NONE; |
2531 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2532 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2533 | /* SNB-B */ | |
2534 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2535 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2536 | |
d74cf324 DV |
2537 | I915_WRITE(FDI_RX_MISC(pipe), |
2538 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2539 | ||
5eddb70b CW |
2540 | reg = FDI_RX_CTL(pipe); |
2541 | temp = I915_READ(reg); | |
8db9d77b ZW |
2542 | if (HAS_PCH_CPT(dev)) { |
2543 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2544 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2545 | } else { | |
2546 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2547 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2548 | } | |
5eddb70b CW |
2549 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2550 | ||
2551 | POSTING_READ(reg); | |
8db9d77b ZW |
2552 | udelay(150); |
2553 | ||
0206e353 | 2554 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2555 | reg = FDI_TX_CTL(pipe); |
2556 | temp = I915_READ(reg); | |
8db9d77b ZW |
2557 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2558 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2559 | I915_WRITE(reg, temp); |
2560 | ||
2561 | POSTING_READ(reg); | |
8db9d77b ZW |
2562 | udelay(500); |
2563 | ||
fa37d39e SP |
2564 | for (retry = 0; retry < 5; retry++) { |
2565 | reg = FDI_RX_IIR(pipe); | |
2566 | temp = I915_READ(reg); | |
2567 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2568 | if (temp & FDI_RX_BIT_LOCK) { | |
2569 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2570 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2571 | break; | |
2572 | } | |
2573 | udelay(50); | |
8db9d77b | 2574 | } |
fa37d39e SP |
2575 | if (retry < 5) |
2576 | break; | |
8db9d77b ZW |
2577 | } |
2578 | if (i == 4) | |
5eddb70b | 2579 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2580 | |
2581 | /* Train 2 */ | |
5eddb70b CW |
2582 | reg = FDI_TX_CTL(pipe); |
2583 | temp = I915_READ(reg); | |
8db9d77b ZW |
2584 | temp &= ~FDI_LINK_TRAIN_NONE; |
2585 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2586 | if (IS_GEN6(dev)) { | |
2587 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2588 | /* SNB-B */ | |
2589 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2590 | } | |
5eddb70b | 2591 | I915_WRITE(reg, temp); |
8db9d77b | 2592 | |
5eddb70b CW |
2593 | reg = FDI_RX_CTL(pipe); |
2594 | temp = I915_READ(reg); | |
8db9d77b ZW |
2595 | if (HAS_PCH_CPT(dev)) { |
2596 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2597 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2598 | } else { | |
2599 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2600 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2601 | } | |
5eddb70b CW |
2602 | I915_WRITE(reg, temp); |
2603 | ||
2604 | POSTING_READ(reg); | |
8db9d77b ZW |
2605 | udelay(150); |
2606 | ||
0206e353 | 2607 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2608 | reg = FDI_TX_CTL(pipe); |
2609 | temp = I915_READ(reg); | |
8db9d77b ZW |
2610 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2611 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2612 | I915_WRITE(reg, temp); |
2613 | ||
2614 | POSTING_READ(reg); | |
8db9d77b ZW |
2615 | udelay(500); |
2616 | ||
fa37d39e SP |
2617 | for (retry = 0; retry < 5; retry++) { |
2618 | reg = FDI_RX_IIR(pipe); | |
2619 | temp = I915_READ(reg); | |
2620 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2621 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2622 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2623 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2624 | break; | |
2625 | } | |
2626 | udelay(50); | |
8db9d77b | 2627 | } |
fa37d39e SP |
2628 | if (retry < 5) |
2629 | break; | |
8db9d77b ZW |
2630 | } |
2631 | if (i == 4) | |
5eddb70b | 2632 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2633 | |
2634 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2635 | } | |
2636 | ||
357555c0 JB |
2637 | /* Manual link training for Ivy Bridge A0 parts */ |
2638 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2639 | { | |
2640 | struct drm_device *dev = crtc->dev; | |
2641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2642 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2643 | int pipe = intel_crtc->pipe; | |
2644 | u32 reg, temp, i; | |
2645 | ||
2646 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2647 | for train result */ | |
2648 | reg = FDI_RX_IMR(pipe); | |
2649 | temp = I915_READ(reg); | |
2650 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2651 | temp &= ~FDI_RX_BIT_LOCK; | |
2652 | I915_WRITE(reg, temp); | |
2653 | ||
2654 | POSTING_READ(reg); | |
2655 | udelay(150); | |
2656 | ||
01a415fd DV |
2657 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2658 | I915_READ(FDI_RX_IIR(pipe))); | |
2659 | ||
357555c0 JB |
2660 | /* enable CPU FDI TX and PCH FDI RX */ |
2661 | reg = FDI_TX_CTL(pipe); | |
2662 | temp = I915_READ(reg); | |
2663 | temp &= ~(7 << 19); | |
2664 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
2665 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2666 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
2667 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2668 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
c4f9c4c2 | 2669 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2670 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2671 | ||
d74cf324 DV |
2672 | I915_WRITE(FDI_RX_MISC(pipe), |
2673 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2674 | ||
357555c0 JB |
2675 | reg = FDI_RX_CTL(pipe); |
2676 | temp = I915_READ(reg); | |
2677 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2678 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2679 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
c4f9c4c2 | 2680 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2681 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2682 | ||
2683 | POSTING_READ(reg); | |
2684 | udelay(150); | |
2685 | ||
0206e353 | 2686 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2687 | reg = FDI_TX_CTL(pipe); |
2688 | temp = I915_READ(reg); | |
2689 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2690 | temp |= snb_b_fdi_train_param[i]; | |
2691 | I915_WRITE(reg, temp); | |
2692 | ||
2693 | POSTING_READ(reg); | |
2694 | udelay(500); | |
2695 | ||
2696 | reg = FDI_RX_IIR(pipe); | |
2697 | temp = I915_READ(reg); | |
2698 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2699 | ||
2700 | if (temp & FDI_RX_BIT_LOCK || | |
2701 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2702 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
01a415fd | 2703 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i); |
357555c0 JB |
2704 | break; |
2705 | } | |
2706 | } | |
2707 | if (i == 4) | |
2708 | DRM_ERROR("FDI train 1 fail!\n"); | |
2709 | ||
2710 | /* Train 2 */ | |
2711 | reg = FDI_TX_CTL(pipe); | |
2712 | temp = I915_READ(reg); | |
2713 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; | |
2714 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2715 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2716 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2717 | I915_WRITE(reg, temp); | |
2718 | ||
2719 | reg = FDI_RX_CTL(pipe); | |
2720 | temp = I915_READ(reg); | |
2721 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2722 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2723 | I915_WRITE(reg, temp); | |
2724 | ||
2725 | POSTING_READ(reg); | |
2726 | udelay(150); | |
2727 | ||
0206e353 | 2728 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2729 | reg = FDI_TX_CTL(pipe); |
2730 | temp = I915_READ(reg); | |
2731 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2732 | temp |= snb_b_fdi_train_param[i]; | |
2733 | I915_WRITE(reg, temp); | |
2734 | ||
2735 | POSTING_READ(reg); | |
2736 | udelay(500); | |
2737 | ||
2738 | reg = FDI_RX_IIR(pipe); | |
2739 | temp = I915_READ(reg); | |
2740 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2741 | ||
2742 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2743 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
01a415fd | 2744 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i); |
357555c0 JB |
2745 | break; |
2746 | } | |
2747 | } | |
2748 | if (i == 4) | |
2749 | DRM_ERROR("FDI train 2 fail!\n"); | |
2750 | ||
2751 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2752 | } | |
2753 | ||
88cefb6c | 2754 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 2755 | { |
88cefb6c | 2756 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 2757 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 2758 | int pipe = intel_crtc->pipe; |
5eddb70b | 2759 | u32 reg, temp; |
79e53945 | 2760 | |
c64e311e | 2761 | |
c98e9dcf | 2762 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2763 | reg = FDI_RX_CTL(pipe); |
2764 | temp = I915_READ(reg); | |
2765 | temp &= ~((0x7 << 19) | (0x7 << 16)); | |
c98e9dcf | 2766 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
dfd07d72 | 2767 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
2768 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2769 | ||
2770 | POSTING_READ(reg); | |
c98e9dcf JB |
2771 | udelay(200); |
2772 | ||
2773 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2774 | temp = I915_READ(reg); |
2775 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2776 | ||
2777 | POSTING_READ(reg); | |
c98e9dcf JB |
2778 | udelay(200); |
2779 | ||
20749730 PZ |
2780 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2781 | reg = FDI_TX_CTL(pipe); | |
2782 | temp = I915_READ(reg); | |
2783 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
2784 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 2785 | |
20749730 PZ |
2786 | POSTING_READ(reg); |
2787 | udelay(100); | |
6be4a607 | 2788 | } |
0e23b99d JB |
2789 | } |
2790 | ||
88cefb6c DV |
2791 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2792 | { | |
2793 | struct drm_device *dev = intel_crtc->base.dev; | |
2794 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2795 | int pipe = intel_crtc->pipe; | |
2796 | u32 reg, temp; | |
2797 | ||
2798 | /* Switch from PCDclk to Rawclk */ | |
2799 | reg = FDI_RX_CTL(pipe); | |
2800 | temp = I915_READ(reg); | |
2801 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
2802 | ||
2803 | /* Disable CPU FDI TX PLL */ | |
2804 | reg = FDI_TX_CTL(pipe); | |
2805 | temp = I915_READ(reg); | |
2806 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2807 | ||
2808 | POSTING_READ(reg); | |
2809 | udelay(100); | |
2810 | ||
2811 | reg = FDI_RX_CTL(pipe); | |
2812 | temp = I915_READ(reg); | |
2813 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2814 | ||
2815 | /* Wait for the clocks to turn off. */ | |
2816 | POSTING_READ(reg); | |
2817 | udelay(100); | |
2818 | } | |
2819 | ||
0fc932b8 JB |
2820 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2821 | { | |
2822 | struct drm_device *dev = crtc->dev; | |
2823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2824 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2825 | int pipe = intel_crtc->pipe; | |
2826 | u32 reg, temp; | |
2827 | ||
2828 | /* disable CPU FDI tx and PCH FDI rx */ | |
2829 | reg = FDI_TX_CTL(pipe); | |
2830 | temp = I915_READ(reg); | |
2831 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2832 | POSTING_READ(reg); | |
2833 | ||
2834 | reg = FDI_RX_CTL(pipe); | |
2835 | temp = I915_READ(reg); | |
2836 | temp &= ~(0x7 << 16); | |
dfd07d72 | 2837 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2838 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2839 | ||
2840 | POSTING_READ(reg); | |
2841 | udelay(100); | |
2842 | ||
2843 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2844 | if (HAS_PCH_IBX(dev)) { |
2845 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
6f06ce18 | 2846 | } |
0fc932b8 JB |
2847 | |
2848 | /* still set train pattern 1 */ | |
2849 | reg = FDI_TX_CTL(pipe); | |
2850 | temp = I915_READ(reg); | |
2851 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2852 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2853 | I915_WRITE(reg, temp); | |
2854 | ||
2855 | reg = FDI_RX_CTL(pipe); | |
2856 | temp = I915_READ(reg); | |
2857 | if (HAS_PCH_CPT(dev)) { | |
2858 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2859 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2860 | } else { | |
2861 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2862 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2863 | } | |
2864 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2865 | temp &= ~(0x07 << 16); | |
dfd07d72 | 2866 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2867 | I915_WRITE(reg, temp); |
2868 | ||
2869 | POSTING_READ(reg); | |
2870 | udelay(100); | |
2871 | } | |
2872 | ||
5bb61643 CW |
2873 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2874 | { | |
2875 | struct drm_device *dev = crtc->dev; | |
2876 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2877 | unsigned long flags; | |
2878 | bool pending; | |
2879 | ||
1f83fee0 | 2880 | if (i915_reset_in_progress(&dev_priv->gpu_error)) |
5bb61643 CW |
2881 | return false; |
2882 | ||
2883 | spin_lock_irqsave(&dev->event_lock, flags); | |
2884 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2885 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2886 | ||
2887 | return pending; | |
2888 | } | |
2889 | ||
e6c3a2a6 CW |
2890 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2891 | { | |
0f91128d | 2892 | struct drm_device *dev = crtc->dev; |
5bb61643 | 2893 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 CW |
2894 | |
2895 | if (crtc->fb == NULL) | |
2896 | return; | |
2897 | ||
2c10d571 DV |
2898 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
2899 | ||
5bb61643 CW |
2900 | wait_event(dev_priv->pending_flip_queue, |
2901 | !intel_crtc_has_pending_flip(crtc)); | |
2902 | ||
0f91128d CW |
2903 | mutex_lock(&dev->struct_mutex); |
2904 | intel_finish_fb(crtc->fb); | |
2905 | mutex_unlock(&dev->struct_mutex); | |
e6c3a2a6 CW |
2906 | } |
2907 | ||
fc316cbe | 2908 | static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc) |
040484af JB |
2909 | { |
2910 | struct drm_device *dev = crtc->dev; | |
228d3e36 | 2911 | struct intel_encoder *intel_encoder; |
040484af JB |
2912 | |
2913 | /* | |
2914 | * If there's a non-PCH eDP on this crtc, it must be DP_A, and that | |
2915 | * must be driven by its own crtc; no sharing is possible. | |
2916 | */ | |
228d3e36 | 2917 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
228d3e36 | 2918 | switch (intel_encoder->type) { |
040484af | 2919 | case INTEL_OUTPUT_EDP: |
228d3e36 | 2920 | if (!intel_encoder_is_pch_edp(&intel_encoder->base)) |
040484af JB |
2921 | return false; |
2922 | continue; | |
2923 | } | |
2924 | } | |
2925 | ||
2926 | return true; | |
2927 | } | |
2928 | ||
fc316cbe PZ |
2929 | static bool haswell_crtc_driving_pch(struct drm_crtc *crtc) |
2930 | { | |
2931 | return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG); | |
2932 | } | |
2933 | ||
e615efe4 ED |
2934 | /* Program iCLKIP clock to the desired frequency */ |
2935 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
2936 | { | |
2937 | struct drm_device *dev = crtc->dev; | |
2938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2939 | u32 divsel, phaseinc, auxdiv, phasedir = 0; | |
2940 | u32 temp; | |
2941 | ||
09153000 DV |
2942 | mutex_lock(&dev_priv->dpio_lock); |
2943 | ||
e615efe4 ED |
2944 | /* It is necessary to ungate the pixclk gate prior to programming |
2945 | * the divisors, and gate it back when it is done. | |
2946 | */ | |
2947 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
2948 | ||
2949 | /* Disable SSCCTL */ | |
2950 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
2951 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
2952 | SBI_SSCCTL_DISABLE, | |
2953 | SBI_ICLK); | |
e615efe4 ED |
2954 | |
2955 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
2956 | if (crtc->mode.clock == 20000) { | |
2957 | auxdiv = 1; | |
2958 | divsel = 0x41; | |
2959 | phaseinc = 0x20; | |
2960 | } else { | |
2961 | /* The iCLK virtual clock root frequency is in MHz, | |
2962 | * but the crtc->mode.clock in in KHz. To get the divisors, | |
2963 | * it is necessary to divide one by another, so we | |
2964 | * convert the virtual clock precision to KHz here for higher | |
2965 | * precision. | |
2966 | */ | |
2967 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
2968 | u32 iclk_pi_range = 64; | |
2969 | u32 desired_divisor, msb_divisor_value, pi_value; | |
2970 | ||
2971 | desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock); | |
2972 | msb_divisor_value = desired_divisor / iclk_pi_range; | |
2973 | pi_value = desired_divisor % iclk_pi_range; | |
2974 | ||
2975 | auxdiv = 0; | |
2976 | divsel = msb_divisor_value - 2; | |
2977 | phaseinc = pi_value; | |
2978 | } | |
2979 | ||
2980 | /* This should not happen with any sane values */ | |
2981 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
2982 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
2983 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
2984 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
2985 | ||
2986 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
2987 | crtc->mode.clock, | |
2988 | auxdiv, | |
2989 | divsel, | |
2990 | phasedir, | |
2991 | phaseinc); | |
2992 | ||
2993 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 2994 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
2995 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
2996 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
2997 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
2998 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
2999 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3000 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3001 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3002 | |
3003 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3004 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3005 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3006 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3007 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3008 | |
3009 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3010 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3011 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3012 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3013 | |
3014 | /* Wait for initialization time */ | |
3015 | udelay(24); | |
3016 | ||
3017 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3018 | |
3019 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3020 | } |
3021 | ||
f67a559d JB |
3022 | /* |
3023 | * Enable PCH resources required for PCH ports: | |
3024 | * - PCH PLLs | |
3025 | * - FDI training & RX/TX | |
3026 | * - update transcoder timings | |
3027 | * - DP transcoding bits | |
3028 | * - transcoder | |
3029 | */ | |
3030 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3031 | { |
3032 | struct drm_device *dev = crtc->dev; | |
3033 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3034 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3035 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3036 | u32 reg, temp; |
2c07245f | 3037 | |
e7e164db CW |
3038 | assert_transcoder_disabled(dev_priv, pipe); |
3039 | ||
cd986abb DV |
3040 | /* Write the TU size bits before fdi link training, so that error |
3041 | * detection works. */ | |
3042 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3043 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3044 | ||
c98e9dcf | 3045 | /* For PCH output, training FDI link */ |
674cf967 | 3046 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3047 | |
572deb37 DV |
3048 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3049 | * transcoder, and we actually should do this to not upset any PCH | |
3050 | * transcoder that already use the clock when we share it. | |
3051 | * | |
3052 | * Note that enable_pch_pll tries to do the right thing, but get_pch_pll | |
3053 | * unconditionally resets the pll - we need that to have the right LVDS | |
3054 | * enable sequence. */ | |
b6b4e185 | 3055 | ironlake_enable_pch_pll(intel_crtc); |
6f13b7b5 | 3056 | |
303b81e0 | 3057 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3058 | u32 sel; |
4b645f14 | 3059 | |
c98e9dcf | 3060 | temp = I915_READ(PCH_DPLL_SEL); |
ee7b9f93 JB |
3061 | switch (pipe) { |
3062 | default: | |
3063 | case 0: | |
3064 | temp |= TRANSA_DPLL_ENABLE; | |
3065 | sel = TRANSA_DPLLB_SEL; | |
3066 | break; | |
3067 | case 1: | |
3068 | temp |= TRANSB_DPLL_ENABLE; | |
3069 | sel = TRANSB_DPLLB_SEL; | |
3070 | break; | |
3071 | case 2: | |
3072 | temp |= TRANSC_DPLL_ENABLE; | |
3073 | sel = TRANSC_DPLLB_SEL; | |
3074 | break; | |
d64311ab | 3075 | } |
ee7b9f93 JB |
3076 | if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B) |
3077 | temp |= sel; | |
3078 | else | |
3079 | temp &= ~sel; | |
c98e9dcf | 3080 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3081 | } |
5eddb70b | 3082 | |
d9b6cb56 JB |
3083 | /* set transcoder timing, panel must allow it */ |
3084 | assert_panel_unlocked(dev_priv, pipe); | |
5eddb70b CW |
3085 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
3086 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); | |
3087 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); | |
8db9d77b | 3088 | |
5eddb70b CW |
3089 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
3090 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); | |
3091 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); | |
0529a0d9 | 3092 | I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); |
8db9d77b | 3093 | |
303b81e0 | 3094 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3095 | |
c98e9dcf JB |
3096 | /* For PCH DP, enable TRANS_DP_CTL */ |
3097 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3098 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3099 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3100 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3101 | reg = TRANS_DP_CTL(pipe); |
3102 | temp = I915_READ(reg); | |
3103 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3104 | TRANS_DP_SYNC_MASK | |
3105 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3106 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3107 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3108 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3109 | |
3110 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3111 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3112 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3113 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3114 | |
3115 | switch (intel_trans_dp_port_sel(crtc)) { | |
3116 | case PCH_DP_B: | |
5eddb70b | 3117 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3118 | break; |
3119 | case PCH_DP_C: | |
5eddb70b | 3120 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3121 | break; |
3122 | case PCH_DP_D: | |
5eddb70b | 3123 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3124 | break; |
3125 | default: | |
e95d41e1 | 3126 | BUG(); |
32f9d658 | 3127 | } |
2c07245f | 3128 | |
5eddb70b | 3129 | I915_WRITE(reg, temp); |
6be4a607 | 3130 | } |
b52eb4dc | 3131 | |
b8a4f404 | 3132 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3133 | } |
3134 | ||
1507e5bd PZ |
3135 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3136 | { | |
3137 | struct drm_device *dev = crtc->dev; | |
3138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3139 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
daed2dbb | 3140 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
1507e5bd | 3141 | |
daed2dbb | 3142 | assert_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3143 | |
8c52b5e8 | 3144 | lpt_program_iclkip(crtc); |
1507e5bd | 3145 | |
0540e488 | 3146 | /* Set transcoder timing. */ |
daed2dbb PZ |
3147 | I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder))); |
3148 | I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder))); | |
3149 | I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder))); | |
1507e5bd | 3150 | |
daed2dbb PZ |
3151 | I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder))); |
3152 | I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder))); | |
3153 | I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder))); | |
3154 | I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
1507e5bd | 3155 | |
937bb610 | 3156 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3157 | } |
3158 | ||
ee7b9f93 JB |
3159 | static void intel_put_pch_pll(struct intel_crtc *intel_crtc) |
3160 | { | |
3161 | struct intel_pch_pll *pll = intel_crtc->pch_pll; | |
3162 | ||
3163 | if (pll == NULL) | |
3164 | return; | |
3165 | ||
3166 | if (pll->refcount == 0) { | |
3167 | WARN(1, "bad PCH PLL refcount\n"); | |
3168 | return; | |
3169 | } | |
3170 | ||
3171 | --pll->refcount; | |
3172 | intel_crtc->pch_pll = NULL; | |
3173 | } | |
3174 | ||
3175 | static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp) | |
3176 | { | |
3177 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
3178 | struct intel_pch_pll *pll; | |
3179 | int i; | |
3180 | ||
3181 | pll = intel_crtc->pch_pll; | |
3182 | if (pll) { | |
3183 | DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n", | |
3184 | intel_crtc->base.base.id, pll->pll_reg); | |
3185 | goto prepare; | |
3186 | } | |
3187 | ||
98b6bd99 DV |
3188 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3189 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
3190 | i = intel_crtc->pipe; | |
3191 | pll = &dev_priv->pch_plls[i]; | |
3192 | ||
3193 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n", | |
3194 | intel_crtc->base.base.id, pll->pll_reg); | |
3195 | ||
3196 | goto found; | |
3197 | } | |
3198 | ||
ee7b9f93 JB |
3199 | for (i = 0; i < dev_priv->num_pch_pll; i++) { |
3200 | pll = &dev_priv->pch_plls[i]; | |
3201 | ||
3202 | /* Only want to check enabled timings first */ | |
3203 | if (pll->refcount == 0) | |
3204 | continue; | |
3205 | ||
3206 | if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) && | |
3207 | fp == I915_READ(pll->fp0_reg)) { | |
3208 | DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n", | |
3209 | intel_crtc->base.base.id, | |
3210 | pll->pll_reg, pll->refcount, pll->active); | |
3211 | ||
3212 | goto found; | |
3213 | } | |
3214 | } | |
3215 | ||
3216 | /* Ok no matching timings, maybe there's a free one? */ | |
3217 | for (i = 0; i < dev_priv->num_pch_pll; i++) { | |
3218 | pll = &dev_priv->pch_plls[i]; | |
3219 | if (pll->refcount == 0) { | |
3220 | DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n", | |
3221 | intel_crtc->base.base.id, pll->pll_reg); | |
3222 | goto found; | |
3223 | } | |
3224 | } | |
3225 | ||
3226 | return NULL; | |
3227 | ||
3228 | found: | |
3229 | intel_crtc->pch_pll = pll; | |
3230 | pll->refcount++; | |
3231 | DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe); | |
3232 | prepare: /* separate function? */ | |
3233 | DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg); | |
ee7b9f93 | 3234 | |
e04c7350 CW |
3235 | /* Wait for the clocks to stabilize before rewriting the regs */ |
3236 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); | |
ee7b9f93 JB |
3237 | POSTING_READ(pll->pll_reg); |
3238 | udelay(150); | |
e04c7350 CW |
3239 | |
3240 | I915_WRITE(pll->fp0_reg, fp); | |
3241 | I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); | |
ee7b9f93 JB |
3242 | pll->on = false; |
3243 | return pll; | |
3244 | } | |
3245 | ||
d4270e57 JB |
3246 | void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) |
3247 | { | |
3248 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3249 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3250 | u32 temp; |
3251 | ||
3252 | temp = I915_READ(dslreg); | |
3253 | udelay(500); | |
3254 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 JB |
3255 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
3256 | DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); | |
3257 | } | |
3258 | } | |
3259 | ||
f67a559d JB |
3260 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3261 | { | |
3262 | struct drm_device *dev = crtc->dev; | |
3263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3264 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3265 | struct intel_encoder *encoder; |
f67a559d JB |
3266 | int pipe = intel_crtc->pipe; |
3267 | int plane = intel_crtc->plane; | |
3268 | u32 temp; | |
3269 | bool is_pch_port; | |
3270 | ||
08a48469 DV |
3271 | WARN_ON(!crtc->enabled); |
3272 | ||
f67a559d JB |
3273 | if (intel_crtc->active) |
3274 | return; | |
3275 | ||
3276 | intel_crtc->active = true; | |
3277 | intel_update_watermarks(dev); | |
3278 | ||
3279 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
3280 | temp = I915_READ(PCH_LVDS); | |
3281 | if ((temp & LVDS_PORT_EN) == 0) | |
3282 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); | |
3283 | } | |
3284 | ||
fc316cbe | 3285 | is_pch_port = ironlake_crtc_driving_pch(crtc); |
f67a559d | 3286 | |
46b6f814 | 3287 | if (is_pch_port) { |
fff367c7 DV |
3288 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3289 | * cpu pipes, hence this is separate from all the other fdi/pch | |
3290 | * enabling. */ | |
88cefb6c | 3291 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
3292 | } else { |
3293 | assert_fdi_tx_disabled(dev_priv, pipe); | |
3294 | assert_fdi_rx_disabled(dev_priv, pipe); | |
3295 | } | |
f67a559d | 3296 | |
bf49ec8c DV |
3297 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3298 | if (encoder->pre_enable) | |
3299 | encoder->pre_enable(encoder); | |
f67a559d JB |
3300 | |
3301 | /* Enable panel fitting for LVDS */ | |
3302 | if (dev_priv->pch_pf_size && | |
547dc041 JN |
3303 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
3304 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
f67a559d JB |
3305 | /* Force use of hard-coded filter coefficients |
3306 | * as some pre-programmed values are broken, | |
3307 | * e.g. x201. | |
3308 | */ | |
13888d78 PZ |
3309 | if (IS_IVYBRIDGE(dev)) |
3310 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3311 | PF_PIPE_SEL_IVB(pipe)); | |
3312 | else | |
3313 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
9db4a9c7 JB |
3314 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); |
3315 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); | |
f67a559d JB |
3316 | } |
3317 | ||
9c54c0dd JB |
3318 | /* |
3319 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3320 | * clocks enabled | |
3321 | */ | |
3322 | intel_crtc_load_lut(crtc); | |
3323 | ||
f67a559d JB |
3324 | intel_enable_pipe(dev_priv, pipe, is_pch_port); |
3325 | intel_enable_plane(dev_priv, plane, pipe); | |
3326 | ||
3327 | if (is_pch_port) | |
3328 | ironlake_pch_enable(crtc); | |
c98e9dcf | 3329 | |
d1ebd816 | 3330 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3331 | intel_update_fbc(dev); |
d1ebd816 BW |
3332 | mutex_unlock(&dev->struct_mutex); |
3333 | ||
6b383a7f | 3334 | intel_crtc_update_cursor(crtc, true); |
ef9c3aee | 3335 | |
fa5c73b1 DV |
3336 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3337 | encoder->enable(encoder); | |
61b77ddd DV |
3338 | |
3339 | if (HAS_PCH_CPT(dev)) | |
3340 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); | |
6ce94100 DV |
3341 | |
3342 | /* | |
3343 | * There seems to be a race in PCH platform hw (at least on some | |
3344 | * outputs) where an enabled pipe still completes any pageflip right | |
3345 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3346 | * as the first vblank happend, everything works as expected. Hence just | |
3347 | * wait for one vblank before returning to avoid strange things | |
3348 | * happening. | |
3349 | */ | |
3350 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
6be4a607 JB |
3351 | } |
3352 | ||
4f771f10 PZ |
3353 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3354 | { | |
3355 | struct drm_device *dev = crtc->dev; | |
3356 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3357 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3358 | struct intel_encoder *encoder; | |
3359 | int pipe = intel_crtc->pipe; | |
3360 | int plane = intel_crtc->plane; | |
4f771f10 PZ |
3361 | bool is_pch_port; |
3362 | ||
3363 | WARN_ON(!crtc->enabled); | |
3364 | ||
3365 | if (intel_crtc->active) | |
3366 | return; | |
3367 | ||
3368 | intel_crtc->active = true; | |
3369 | intel_update_watermarks(dev); | |
3370 | ||
fc316cbe | 3371 | is_pch_port = haswell_crtc_driving_pch(crtc); |
4f771f10 | 3372 | |
83616634 | 3373 | if (is_pch_port) |
04945641 | 3374 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
3375 | |
3376 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3377 | if (encoder->pre_enable) | |
3378 | encoder->pre_enable(encoder); | |
3379 | ||
1f544388 | 3380 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 3381 | |
1f544388 | 3382 | /* Enable panel fitting for eDP */ |
547dc041 JN |
3383 | if (dev_priv->pch_pf_size && |
3384 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { | |
4f771f10 PZ |
3385 | /* Force use of hard-coded filter coefficients |
3386 | * as some pre-programmed values are broken, | |
3387 | * e.g. x201. | |
3388 | */ | |
54075a7d PZ |
3389 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
3390 | PF_PIPE_SEL_IVB(pipe)); | |
4f771f10 PZ |
3391 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); |
3392 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); | |
3393 | } | |
3394 | ||
3395 | /* | |
3396 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3397 | * clocks enabled | |
3398 | */ | |
3399 | intel_crtc_load_lut(crtc); | |
3400 | ||
1f544388 PZ |
3401 | intel_ddi_set_pipe_settings(crtc); |
3402 | intel_ddi_enable_pipe_func(crtc); | |
4f771f10 PZ |
3403 | |
3404 | intel_enable_pipe(dev_priv, pipe, is_pch_port); | |
3405 | intel_enable_plane(dev_priv, plane, pipe); | |
3406 | ||
3407 | if (is_pch_port) | |
1507e5bd | 3408 | lpt_pch_enable(crtc); |
4f771f10 PZ |
3409 | |
3410 | mutex_lock(&dev->struct_mutex); | |
3411 | intel_update_fbc(dev); | |
3412 | mutex_unlock(&dev->struct_mutex); | |
3413 | ||
3414 | intel_crtc_update_cursor(crtc, true); | |
3415 | ||
3416 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3417 | encoder->enable(encoder); | |
3418 | ||
4f771f10 PZ |
3419 | /* |
3420 | * There seems to be a race in PCH platform hw (at least on some | |
3421 | * outputs) where an enabled pipe still completes any pageflip right | |
3422 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3423 | * as the first vblank happend, everything works as expected. Hence just | |
3424 | * wait for one vblank before returning to avoid strange things | |
3425 | * happening. | |
3426 | */ | |
3427 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
3428 | } | |
3429 | ||
6be4a607 JB |
3430 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3431 | { | |
3432 | struct drm_device *dev = crtc->dev; | |
3433 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3434 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3435 | struct intel_encoder *encoder; |
6be4a607 JB |
3436 | int pipe = intel_crtc->pipe; |
3437 | int plane = intel_crtc->plane; | |
5eddb70b | 3438 | u32 reg, temp; |
b52eb4dc | 3439 | |
ef9c3aee | 3440 | |
f7abfe8b CW |
3441 | if (!intel_crtc->active) |
3442 | return; | |
3443 | ||
ea9d758d DV |
3444 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3445 | encoder->disable(encoder); | |
3446 | ||
e6c3a2a6 | 3447 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3448 | drm_vblank_off(dev, pipe); |
6b383a7f | 3449 | intel_crtc_update_cursor(crtc, false); |
5eddb70b | 3450 | |
b24e7179 | 3451 | intel_disable_plane(dev_priv, plane, pipe); |
913d8d11 | 3452 | |
973d04f9 CW |
3453 | if (dev_priv->cfb_plane == plane) |
3454 | intel_disable_fbc(dev); | |
2c07245f | 3455 | |
b24e7179 | 3456 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3457 | |
6be4a607 | 3458 | /* Disable PF */ |
9db4a9c7 JB |
3459 | I915_WRITE(PF_CTL(pipe), 0); |
3460 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
2c07245f | 3461 | |
bf49ec8c DV |
3462 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3463 | if (encoder->post_disable) | |
3464 | encoder->post_disable(encoder); | |
2c07245f | 3465 | |
0fc932b8 | 3466 | ironlake_fdi_disable(crtc); |
249c0e64 | 3467 | |
b8a4f404 | 3468 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
913d8d11 | 3469 | |
6be4a607 JB |
3470 | if (HAS_PCH_CPT(dev)) { |
3471 | /* disable TRANS_DP_CTL */ | |
5eddb70b CW |
3472 | reg = TRANS_DP_CTL(pipe); |
3473 | temp = I915_READ(reg); | |
3474 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
cb3543c6 | 3475 | temp |= TRANS_DP_PORT_SEL_NONE; |
5eddb70b | 3476 | I915_WRITE(reg, temp); |
6be4a607 JB |
3477 | |
3478 | /* disable DPLL_SEL */ | |
3479 | temp = I915_READ(PCH_DPLL_SEL); | |
9db4a9c7 JB |
3480 | switch (pipe) { |
3481 | case 0: | |
d64311ab | 3482 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
9db4a9c7 JB |
3483 | break; |
3484 | case 1: | |
6be4a607 | 3485 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
9db4a9c7 JB |
3486 | break; |
3487 | case 2: | |
4b645f14 | 3488 | /* C shares PLL A or B */ |
d64311ab | 3489 | temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); |
9db4a9c7 JB |
3490 | break; |
3491 | default: | |
3492 | BUG(); /* wtf */ | |
3493 | } | |
6be4a607 | 3494 | I915_WRITE(PCH_DPLL_SEL, temp); |
6be4a607 | 3495 | } |
e3421a18 | 3496 | |
6be4a607 | 3497 | /* disable PCH DPLL */ |
ee7b9f93 | 3498 | intel_disable_pch_pll(intel_crtc); |
8db9d77b | 3499 | |
88cefb6c | 3500 | ironlake_fdi_pll_disable(intel_crtc); |
6b383a7f | 3501 | |
f7abfe8b | 3502 | intel_crtc->active = false; |
6b383a7f | 3503 | intel_update_watermarks(dev); |
d1ebd816 BW |
3504 | |
3505 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 3506 | intel_update_fbc(dev); |
d1ebd816 | 3507 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3508 | } |
1b3c7a47 | 3509 | |
4f771f10 | 3510 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 3511 | { |
4f771f10 PZ |
3512 | struct drm_device *dev = crtc->dev; |
3513 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 3514 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
3515 | struct intel_encoder *encoder; |
3516 | int pipe = intel_crtc->pipe; | |
3517 | int plane = intel_crtc->plane; | |
ad80a810 | 3518 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
83616634 | 3519 | bool is_pch_port; |
ee7b9f93 | 3520 | |
4f771f10 PZ |
3521 | if (!intel_crtc->active) |
3522 | return; | |
3523 | ||
83616634 PZ |
3524 | is_pch_port = haswell_crtc_driving_pch(crtc); |
3525 | ||
4f771f10 PZ |
3526 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3527 | encoder->disable(encoder); | |
3528 | ||
3529 | intel_crtc_wait_for_pending_flips(crtc); | |
3530 | drm_vblank_off(dev, pipe); | |
3531 | intel_crtc_update_cursor(crtc, false); | |
3532 | ||
3533 | intel_disable_plane(dev_priv, plane, pipe); | |
3534 | ||
3535 | if (dev_priv->cfb_plane == plane) | |
3536 | intel_disable_fbc(dev); | |
3537 | ||
3538 | intel_disable_pipe(dev_priv, pipe); | |
3539 | ||
ad80a810 | 3540 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 PZ |
3541 | |
3542 | /* Disable PF */ | |
3543 | I915_WRITE(PF_CTL(pipe), 0); | |
3544 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
3545 | ||
1f544388 | 3546 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
3547 | |
3548 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3549 | if (encoder->post_disable) | |
3550 | encoder->post_disable(encoder); | |
3551 | ||
83616634 | 3552 | if (is_pch_port) { |
ab4d966c | 3553 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 3554 | intel_ddi_fdi_disable(crtc); |
83616634 | 3555 | } |
4f771f10 PZ |
3556 | |
3557 | intel_crtc->active = false; | |
3558 | intel_update_watermarks(dev); | |
3559 | ||
3560 | mutex_lock(&dev->struct_mutex); | |
3561 | intel_update_fbc(dev); | |
3562 | mutex_unlock(&dev->struct_mutex); | |
3563 | } | |
3564 | ||
ee7b9f93 JB |
3565 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3566 | { | |
3567 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3568 | intel_put_pch_pll(intel_crtc); | |
3569 | } | |
3570 | ||
6441ab5f PZ |
3571 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3572 | { | |
a5c961d1 PZ |
3573 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3574 | ||
3575 | /* Stop saying we're using TRANSCODER_EDP because some other CRTC might | |
3576 | * start using it. */ | |
1a240d4d | 3577 | intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe; |
a5c961d1 | 3578 | |
6441ab5f PZ |
3579 | intel_ddi_put_crtc_pll(crtc); |
3580 | } | |
3581 | ||
02e792fb DV |
3582 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3583 | { | |
02e792fb | 3584 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3585 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3586 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3587 | |
23f09ce3 | 3588 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3589 | dev_priv->mm.interruptible = false; |
3590 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3591 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3592 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3593 | } |
02e792fb | 3594 | |
5dcdbcb0 CW |
3595 | /* Let userspace switch the overlay on again. In most cases userspace |
3596 | * has to recompute where to put it anyway. | |
3597 | */ | |
02e792fb DV |
3598 | } |
3599 | ||
0b8765c6 | 3600 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
3601 | { |
3602 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
3603 | struct drm_i915_private *dev_priv = dev->dev_private; |
3604 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3605 | struct intel_encoder *encoder; |
79e53945 | 3606 | int pipe = intel_crtc->pipe; |
80824003 | 3607 | int plane = intel_crtc->plane; |
79e53945 | 3608 | |
08a48469 DV |
3609 | WARN_ON(!crtc->enabled); |
3610 | ||
f7abfe8b CW |
3611 | if (intel_crtc->active) |
3612 | return; | |
3613 | ||
3614 | intel_crtc->active = true; | |
6b383a7f CW |
3615 | intel_update_watermarks(dev); |
3616 | ||
63d7bbe9 | 3617 | intel_enable_pll(dev_priv, pipe); |
040484af | 3618 | intel_enable_pipe(dev_priv, pipe, false); |
b24e7179 | 3619 | intel_enable_plane(dev_priv, plane, pipe); |
79e53945 | 3620 | |
0b8765c6 | 3621 | intel_crtc_load_lut(crtc); |
bed4a673 | 3622 | intel_update_fbc(dev); |
79e53945 | 3623 | |
0b8765c6 JB |
3624 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3625 | intel_crtc_dpms_overlay(intel_crtc, true); | |
6b383a7f | 3626 | intel_crtc_update_cursor(crtc, true); |
ef9c3aee | 3627 | |
fa5c73b1 DV |
3628 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3629 | encoder->enable(encoder); | |
0b8765c6 | 3630 | } |
79e53945 | 3631 | |
0b8765c6 JB |
3632 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3633 | { | |
3634 | struct drm_device *dev = crtc->dev; | |
3635 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3636 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3637 | struct intel_encoder *encoder; |
0b8765c6 JB |
3638 | int pipe = intel_crtc->pipe; |
3639 | int plane = intel_crtc->plane; | |
b690e96c | 3640 | |
ef9c3aee | 3641 | |
f7abfe8b CW |
3642 | if (!intel_crtc->active) |
3643 | return; | |
3644 | ||
ea9d758d DV |
3645 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3646 | encoder->disable(encoder); | |
3647 | ||
0b8765c6 | 3648 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
3649 | intel_crtc_wait_for_pending_flips(crtc); |
3650 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 3651 | intel_crtc_dpms_overlay(intel_crtc, false); |
6b383a7f | 3652 | intel_crtc_update_cursor(crtc, false); |
0b8765c6 | 3653 | |
973d04f9 CW |
3654 | if (dev_priv->cfb_plane == plane) |
3655 | intel_disable_fbc(dev); | |
79e53945 | 3656 | |
b24e7179 | 3657 | intel_disable_plane(dev_priv, plane, pipe); |
b24e7179 | 3658 | intel_disable_pipe(dev_priv, pipe); |
63d7bbe9 | 3659 | intel_disable_pll(dev_priv, pipe); |
0b8765c6 | 3660 | |
f7abfe8b | 3661 | intel_crtc->active = false; |
6b383a7f CW |
3662 | intel_update_fbc(dev); |
3663 | intel_update_watermarks(dev); | |
0b8765c6 JB |
3664 | } |
3665 | ||
ee7b9f93 JB |
3666 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
3667 | { | |
3668 | } | |
3669 | ||
976f8a20 DV |
3670 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
3671 | bool enabled) | |
2c07245f ZW |
3672 | { |
3673 | struct drm_device *dev = crtc->dev; | |
3674 | struct drm_i915_master_private *master_priv; | |
3675 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3676 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
3677 | |
3678 | if (!dev->primary->master) | |
3679 | return; | |
3680 | ||
3681 | master_priv = dev->primary->master->driver_priv; | |
3682 | if (!master_priv->sarea_priv) | |
3683 | return; | |
3684 | ||
79e53945 JB |
3685 | switch (pipe) { |
3686 | case 0: | |
3687 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
3688 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
3689 | break; | |
3690 | case 1: | |
3691 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
3692 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
3693 | break; | |
3694 | default: | |
9db4a9c7 | 3695 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
3696 | break; |
3697 | } | |
79e53945 JB |
3698 | } |
3699 | ||
976f8a20 DV |
3700 | /** |
3701 | * Sets the power management mode of the pipe and plane. | |
3702 | */ | |
3703 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
3704 | { | |
3705 | struct drm_device *dev = crtc->dev; | |
3706 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3707 | struct intel_encoder *intel_encoder; | |
3708 | bool enable = false; | |
3709 | ||
3710 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
3711 | enable |= intel_encoder->connectors_active; | |
3712 | ||
3713 | if (enable) | |
3714 | dev_priv->display.crtc_enable(crtc); | |
3715 | else | |
3716 | dev_priv->display.crtc_disable(crtc); | |
3717 | ||
3718 | intel_crtc_update_sarea(crtc, enable); | |
3719 | } | |
3720 | ||
cdd59983 CW |
3721 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3722 | { | |
cdd59983 | 3723 | struct drm_device *dev = crtc->dev; |
976f8a20 | 3724 | struct drm_connector *connector; |
ee7b9f93 | 3725 | struct drm_i915_private *dev_priv = dev->dev_private; |
7b9f35a6 | 3726 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cdd59983 | 3727 | |
976f8a20 DV |
3728 | /* crtc should still be enabled when we disable it. */ |
3729 | WARN_ON(!crtc->enabled); | |
3730 | ||
7b9f35a6 | 3731 | intel_crtc->eld_vld = false; |
976f8a20 DV |
3732 | dev_priv->display.crtc_disable(crtc); |
3733 | intel_crtc_update_sarea(crtc, false); | |
ee7b9f93 JB |
3734 | dev_priv->display.off(crtc); |
3735 | ||
931872fc CW |
3736 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
3737 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); | |
cdd59983 CW |
3738 | |
3739 | if (crtc->fb) { | |
3740 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 3741 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 | 3742 | mutex_unlock(&dev->struct_mutex); |
976f8a20 DV |
3743 | crtc->fb = NULL; |
3744 | } | |
3745 | ||
3746 | /* Update computed state. */ | |
3747 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3748 | if (!connector->encoder || !connector->encoder->crtc) | |
3749 | continue; | |
3750 | ||
3751 | if (connector->encoder->crtc != crtc) | |
3752 | continue; | |
3753 | ||
3754 | connector->dpms = DRM_MODE_DPMS_OFF; | |
3755 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
3756 | } |
3757 | } | |
3758 | ||
a261b246 | 3759 | void intel_modeset_disable(struct drm_device *dev) |
79e53945 | 3760 | { |
a261b246 DV |
3761 | struct drm_crtc *crtc; |
3762 | ||
3763 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3764 | if (crtc->enabled) | |
3765 | intel_crtc_disable(crtc); | |
3766 | } | |
79e53945 JB |
3767 | } |
3768 | ||
ea5b213a | 3769 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 3770 | { |
4ef69c7a | 3771 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 3772 | |
ea5b213a CW |
3773 | drm_encoder_cleanup(encoder); |
3774 | kfree(intel_encoder); | |
7e7d76c3 JB |
3775 | } |
3776 | ||
5ab432ef DV |
3777 | /* Simple dpms helper for encodres with just one connector, no cloning and only |
3778 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the | |
3779 | * state of the entire output pipe. */ | |
3780 | void intel_encoder_dpms(struct intel_encoder *encoder, int mode) | |
7e7d76c3 | 3781 | { |
5ab432ef DV |
3782 | if (mode == DRM_MODE_DPMS_ON) { |
3783 | encoder->connectors_active = true; | |
3784 | ||
b2cabb0e | 3785 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
3786 | } else { |
3787 | encoder->connectors_active = false; | |
3788 | ||
b2cabb0e | 3789 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 3790 | } |
79e53945 JB |
3791 | } |
3792 | ||
0a91ca29 DV |
3793 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
3794 | * internal consistency). */ | |
b980514c | 3795 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 3796 | { |
0a91ca29 DV |
3797 | if (connector->get_hw_state(connector)) { |
3798 | struct intel_encoder *encoder = connector->encoder; | |
3799 | struct drm_crtc *crtc; | |
3800 | bool encoder_enabled; | |
3801 | enum pipe pipe; | |
3802 | ||
3803 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
3804 | connector->base.base.id, | |
3805 | drm_get_connector_name(&connector->base)); | |
3806 | ||
3807 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
3808 | "wrong connector dpms state\n"); | |
3809 | WARN(connector->base.encoder != &encoder->base, | |
3810 | "active connector not linked to encoder\n"); | |
3811 | WARN(!encoder->connectors_active, | |
3812 | "encoder->connectors_active not set\n"); | |
3813 | ||
3814 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
3815 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
3816 | if (WARN_ON(!encoder->base.crtc)) | |
3817 | return; | |
3818 | ||
3819 | crtc = encoder->base.crtc; | |
3820 | ||
3821 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
3822 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
3823 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
3824 | "encoder active on the wrong pipe\n"); | |
3825 | } | |
79e53945 JB |
3826 | } |
3827 | ||
5ab432ef DV |
3828 | /* Even simpler default implementation, if there's really no special case to |
3829 | * consider. */ | |
3830 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 3831 | { |
5ab432ef | 3832 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
d4270e57 | 3833 | |
5ab432ef DV |
3834 | /* All the simple cases only support two dpms states. */ |
3835 | if (mode != DRM_MODE_DPMS_ON) | |
3836 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 3837 | |
5ab432ef DV |
3838 | if (mode == connector->dpms) |
3839 | return; | |
3840 | ||
3841 | connector->dpms = mode; | |
3842 | ||
3843 | /* Only need to change hw state when actually enabled */ | |
3844 | if (encoder->base.crtc) | |
3845 | intel_encoder_dpms(encoder, mode); | |
3846 | else | |
8af6cf88 | 3847 | WARN_ON(encoder->connectors_active != false); |
0a91ca29 | 3848 | |
b980514c | 3849 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
3850 | } |
3851 | ||
f0947c37 DV |
3852 | /* Simple connector->get_hw_state implementation for encoders that support only |
3853 | * one connector and no cloning and hence the encoder state determines the state | |
3854 | * of the connector. */ | |
3855 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 3856 | { |
24929352 | 3857 | enum pipe pipe = 0; |
f0947c37 | 3858 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 3859 | |
f0947c37 | 3860 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
3861 | } |
3862 | ||
79e53945 | 3863 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
35313cde | 3864 | const struct drm_display_mode *mode, |
79e53945 JB |
3865 | struct drm_display_mode *adjusted_mode) |
3866 | { | |
2c07245f | 3867 | struct drm_device *dev = crtc->dev; |
89749350 | 3868 | |
bad720ff | 3869 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 3870 | /* FDI link clock is fixed at 2.7G */ |
2377b741 JB |
3871 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
3872 | return false; | |
2c07245f | 3873 | } |
89749350 | 3874 | |
f9bef081 DV |
3875 | /* All interlaced capable intel hw wants timings in frames. Note though |
3876 | * that intel_lvds_mode_fixup does some funny tricks with the crtc | |
3877 | * timings, so we need to be careful not to clobber these.*/ | |
3878 | if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET)) | |
3879 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
89749350 | 3880 | |
44f46b42 CW |
3881 | /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes |
3882 | * with a hsync front porch of 0. | |
3883 | */ | |
3884 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
3885 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
3886 | return false; | |
3887 | ||
79e53945 JB |
3888 | return true; |
3889 | } | |
3890 | ||
25eb05fc JB |
3891 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
3892 | { | |
3893 | return 400000; /* FIXME */ | |
3894 | } | |
3895 | ||
e70236a8 JB |
3896 | static int i945_get_display_clock_speed(struct drm_device *dev) |
3897 | { | |
3898 | return 400000; | |
3899 | } | |
79e53945 | 3900 | |
e70236a8 | 3901 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 3902 | { |
e70236a8 JB |
3903 | return 333000; |
3904 | } | |
79e53945 | 3905 | |
e70236a8 JB |
3906 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
3907 | { | |
3908 | return 200000; | |
3909 | } | |
79e53945 | 3910 | |
e70236a8 JB |
3911 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
3912 | { | |
3913 | u16 gcfgc = 0; | |
79e53945 | 3914 | |
e70236a8 JB |
3915 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
3916 | ||
3917 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
3918 | return 133000; | |
3919 | else { | |
3920 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
3921 | case GC_DISPLAY_CLOCK_333_MHZ: | |
3922 | return 333000; | |
3923 | default: | |
3924 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
3925 | return 190000; | |
79e53945 | 3926 | } |
e70236a8 JB |
3927 | } |
3928 | } | |
3929 | ||
3930 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
3931 | { | |
3932 | return 266000; | |
3933 | } | |
3934 | ||
3935 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
3936 | { | |
3937 | u16 hpllcc = 0; | |
3938 | /* Assume that the hardware is in the high speed state. This | |
3939 | * should be the default. | |
3940 | */ | |
3941 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
3942 | case GC_CLOCK_133_200: | |
3943 | case GC_CLOCK_100_200: | |
3944 | return 200000; | |
3945 | case GC_CLOCK_166_250: | |
3946 | return 250000; | |
3947 | case GC_CLOCK_100_133: | |
79e53945 | 3948 | return 133000; |
e70236a8 | 3949 | } |
79e53945 | 3950 | |
e70236a8 JB |
3951 | /* Shouldn't happen */ |
3952 | return 0; | |
3953 | } | |
79e53945 | 3954 | |
e70236a8 JB |
3955 | static int i830_get_display_clock_speed(struct drm_device *dev) |
3956 | { | |
3957 | return 133000; | |
79e53945 JB |
3958 | } |
3959 | ||
2c07245f | 3960 | static void |
e69d0bc1 | 3961 | intel_reduce_ratio(uint32_t *num, uint32_t *den) |
2c07245f ZW |
3962 | { |
3963 | while (*num > 0xffffff || *den > 0xffffff) { | |
3964 | *num >>= 1; | |
3965 | *den >>= 1; | |
3966 | } | |
3967 | } | |
3968 | ||
e69d0bc1 DV |
3969 | void |
3970 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
3971 | int pixel_clock, int link_clock, | |
3972 | struct intel_link_m_n *m_n) | |
2c07245f | 3973 | { |
e69d0bc1 | 3974 | m_n->tu = 64; |
22ed1113 CW |
3975 | m_n->gmch_m = bits_per_pixel * pixel_clock; |
3976 | m_n->gmch_n = link_clock * nlanes * 8; | |
e69d0bc1 | 3977 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
22ed1113 CW |
3978 | m_n->link_m = pixel_clock; |
3979 | m_n->link_n = link_clock; | |
e69d0bc1 | 3980 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); |
2c07245f ZW |
3981 | } |
3982 | ||
a7615030 CW |
3983 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
3984 | { | |
72bbe58c KP |
3985 | if (i915_panel_use_ssc >= 0) |
3986 | return i915_panel_use_ssc != 0; | |
3987 | return dev_priv->lvds_use_ssc | |
435793df | 3988 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
3989 | } |
3990 | ||
5a354204 JB |
3991 | /** |
3992 | * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send | |
3993 | * @crtc: CRTC structure | |
3b5c78a3 | 3994 | * @mode: requested mode |
5a354204 JB |
3995 | * |
3996 | * A pipe may be connected to one or more outputs. Based on the depth of the | |
3997 | * attached framebuffer, choose a good color depth to use on the pipe. | |
3998 | * | |
3999 | * If possible, match the pipe depth to the fb depth. In some cases, this | |
4000 | * isn't ideal, because the connected output supports a lesser or restricted | |
4001 | * set of depths. Resolve that here: | |
4002 | * LVDS typically supports only 6bpc, so clamp down in that case | |
4003 | * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc | |
4004 | * Displays may support a restricted set as well, check EDID and clamp as | |
4005 | * appropriate. | |
3b5c78a3 | 4006 | * DP may want to dither down to 6bpc to fit larger modes |
5a354204 JB |
4007 | * |
4008 | * RETURNS: | |
4009 | * Dithering requirement (i.e. false if display bpc and pipe bpc match, | |
4010 | * true if they don't match). | |
4011 | */ | |
4012 | static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, | |
94352cf9 | 4013 | struct drm_framebuffer *fb, |
3b5c78a3 AJ |
4014 | unsigned int *pipe_bpp, |
4015 | struct drm_display_mode *mode) | |
5a354204 JB |
4016 | { |
4017 | struct drm_device *dev = crtc->dev; | |
4018 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5a354204 | 4019 | struct drm_connector *connector; |
6c2b7c12 | 4020 | struct intel_encoder *intel_encoder; |
5a354204 JB |
4021 | unsigned int display_bpc = UINT_MAX, bpc; |
4022 | ||
4023 | /* Walk the encoders & connectors on this crtc, get min bpc */ | |
6c2b7c12 | 4024 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5a354204 JB |
4025 | |
4026 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) { | |
4027 | unsigned int lvds_bpc; | |
4028 | ||
4029 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == | |
4030 | LVDS_A3_POWER_UP) | |
4031 | lvds_bpc = 8; | |
4032 | else | |
4033 | lvds_bpc = 6; | |
4034 | ||
4035 | if (lvds_bpc < display_bpc) { | |
82820490 | 4036 | DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); |
5a354204 JB |
4037 | display_bpc = lvds_bpc; |
4038 | } | |
4039 | continue; | |
4040 | } | |
4041 | ||
5a354204 JB |
4042 | /* Not one of the known troublemakers, check the EDID */ |
4043 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
4044 | head) { | |
6c2b7c12 | 4045 | if (connector->encoder != &intel_encoder->base) |
5a354204 JB |
4046 | continue; |
4047 | ||
62ac41a6 JB |
4048 | /* Don't use an invalid EDID bpc value */ |
4049 | if (connector->display_info.bpc && | |
4050 | connector->display_info.bpc < display_bpc) { | |
82820490 | 4051 | DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); |
5a354204 JB |
4052 | display_bpc = connector->display_info.bpc; |
4053 | } | |
4054 | } | |
4055 | ||
2f4f649a JN |
4056 | if (intel_encoder->type == INTEL_OUTPUT_EDP) { |
4057 | /* Use VBT settings if we have an eDP panel */ | |
4058 | unsigned int edp_bpc = dev_priv->edp.bpp / 3; | |
4059 | ||
9a30a61f | 4060 | if (edp_bpc && edp_bpc < display_bpc) { |
2f4f649a JN |
4061 | DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); |
4062 | display_bpc = edp_bpc; | |
4063 | } | |
4064 | continue; | |
4065 | } | |
4066 | ||
5a354204 JB |
4067 | /* |
4068 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
4069 | * through, clamp it down. (Note: >12bpc will be caught below.) | |
4070 | */ | |
4071 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { | |
4072 | if (display_bpc > 8 && display_bpc < 12) { | |
82820490 | 4073 | DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); |
5a354204 JB |
4074 | display_bpc = 12; |
4075 | } else { | |
82820490 | 4076 | DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); |
5a354204 JB |
4077 | display_bpc = 8; |
4078 | } | |
4079 | } | |
4080 | } | |
4081 | ||
3b5c78a3 AJ |
4082 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
4083 | DRM_DEBUG_KMS("Dithering DP to 6bpc\n"); | |
4084 | display_bpc = 6; | |
4085 | } | |
4086 | ||
5a354204 JB |
4087 | /* |
4088 | * We could just drive the pipe at the highest bpc all the time and | |
4089 | * enable dithering as needed, but that costs bandwidth. So choose | |
4090 | * the minimum value that expresses the full color range of the fb but | |
4091 | * also stays within the max display bpc discovered above. | |
4092 | */ | |
4093 | ||
94352cf9 | 4094 | switch (fb->depth) { |
5a354204 JB |
4095 | case 8: |
4096 | bpc = 8; /* since we go through a colormap */ | |
4097 | break; | |
4098 | case 15: | |
4099 | case 16: | |
4100 | bpc = 6; /* min is 18bpp */ | |
4101 | break; | |
4102 | case 24: | |
578393cd | 4103 | bpc = 8; |
5a354204 JB |
4104 | break; |
4105 | case 30: | |
578393cd | 4106 | bpc = 10; |
5a354204 JB |
4107 | break; |
4108 | case 48: | |
578393cd | 4109 | bpc = 12; |
5a354204 JB |
4110 | break; |
4111 | default: | |
4112 | DRM_DEBUG("unsupported depth, assuming 24 bits\n"); | |
4113 | bpc = min((unsigned int)8, display_bpc); | |
4114 | break; | |
4115 | } | |
4116 | ||
578393cd KP |
4117 | display_bpc = min(display_bpc, bpc); |
4118 | ||
82820490 AJ |
4119 | DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n", |
4120 | bpc, display_bpc); | |
5a354204 | 4121 | |
578393cd | 4122 | *pipe_bpp = display_bpc * 3; |
5a354204 JB |
4123 | |
4124 | return display_bpc != bpc; | |
4125 | } | |
4126 | ||
a0c4da24 JB |
4127 | static int vlv_get_refclk(struct drm_crtc *crtc) |
4128 | { | |
4129 | struct drm_device *dev = crtc->dev; | |
4130 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4131 | int refclk = 27000; /* for DP & HDMI */ | |
4132 | ||
4133 | return 100000; /* only one validated so far */ | |
4134 | ||
4135 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
4136 | refclk = 96000; | |
4137 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4138 | if (intel_panel_use_ssc(dev_priv)) | |
4139 | refclk = 100000; | |
4140 | else | |
4141 | refclk = 96000; | |
4142 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { | |
4143 | refclk = 100000; | |
4144 | } | |
4145 | ||
4146 | return refclk; | |
4147 | } | |
4148 | ||
c65d77d8 JB |
4149 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4150 | { | |
4151 | struct drm_device *dev = crtc->dev; | |
4152 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4153 | int refclk; | |
4154 | ||
a0c4da24 JB |
4155 | if (IS_VALLEYVIEW(dev)) { |
4156 | refclk = vlv_get_refclk(crtc); | |
4157 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
c65d77d8 JB |
4158 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
4159 | refclk = dev_priv->lvds_ssc_freq * 1000; | |
4160 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
4161 | refclk / 1000); | |
4162 | } else if (!IS_GEN2(dev)) { | |
4163 | refclk = 96000; | |
4164 | } else { | |
4165 | refclk = 48000; | |
4166 | } | |
4167 | ||
4168 | return refclk; | |
4169 | } | |
4170 | ||
4171 | static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, | |
4172 | intel_clock_t *clock) | |
4173 | { | |
4174 | /* SDVO TV has fixed PLL values depend on its clock range, | |
4175 | this mirrors vbios setting. */ | |
4176 | if (adjusted_mode->clock >= 100000 | |
4177 | && adjusted_mode->clock < 140500) { | |
4178 | clock->p1 = 2; | |
4179 | clock->p2 = 10; | |
4180 | clock->n = 3; | |
4181 | clock->m1 = 16; | |
4182 | clock->m2 = 8; | |
4183 | } else if (adjusted_mode->clock >= 140500 | |
4184 | && adjusted_mode->clock <= 200000) { | |
4185 | clock->p1 = 1; | |
4186 | clock->p2 = 10; | |
4187 | clock->n = 6; | |
4188 | clock->m1 = 12; | |
4189 | clock->m2 = 8; | |
4190 | } | |
4191 | } | |
4192 | ||
a7516a05 JB |
4193 | static void i9xx_update_pll_dividers(struct drm_crtc *crtc, |
4194 | intel_clock_t *clock, | |
4195 | intel_clock_t *reduced_clock) | |
4196 | { | |
4197 | struct drm_device *dev = crtc->dev; | |
4198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4199 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4200 | int pipe = intel_crtc->pipe; | |
4201 | u32 fp, fp2 = 0; | |
4202 | ||
4203 | if (IS_PINEVIEW(dev)) { | |
4204 | fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; | |
4205 | if (reduced_clock) | |
4206 | fp2 = (1 << reduced_clock->n) << 16 | | |
4207 | reduced_clock->m1 << 8 | reduced_clock->m2; | |
4208 | } else { | |
4209 | fp = clock->n << 16 | clock->m1 << 8 | clock->m2; | |
4210 | if (reduced_clock) | |
4211 | fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | | |
4212 | reduced_clock->m2; | |
4213 | } | |
4214 | ||
4215 | I915_WRITE(FP0(pipe), fp); | |
4216 | ||
4217 | intel_crtc->lowfreq_avail = false; | |
4218 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
4219 | reduced_clock && i915_powersave) { | |
4220 | I915_WRITE(FP1(pipe), fp2); | |
4221 | intel_crtc->lowfreq_avail = true; | |
4222 | } else { | |
4223 | I915_WRITE(FP1(pipe), fp); | |
4224 | } | |
4225 | } | |
4226 | ||
a0c4da24 JB |
4227 | static void vlv_update_pll(struct drm_crtc *crtc, |
4228 | struct drm_display_mode *mode, | |
4229 | struct drm_display_mode *adjusted_mode, | |
4230 | intel_clock_t *clock, intel_clock_t *reduced_clock, | |
2a8f64ca | 4231 | int num_connectors) |
a0c4da24 JB |
4232 | { |
4233 | struct drm_device *dev = crtc->dev; | |
4234 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4235 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4236 | int pipe = intel_crtc->pipe; | |
4237 | u32 dpll, mdiv, pdiv; | |
4238 | u32 bestn, bestm1, bestm2, bestp1, bestp2; | |
2a8f64ca VP |
4239 | bool is_sdvo; |
4240 | u32 temp; | |
a0c4da24 | 4241 | |
09153000 DV |
4242 | mutex_lock(&dev_priv->dpio_lock); |
4243 | ||
2a8f64ca VP |
4244 | is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) || |
4245 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); | |
a0c4da24 | 4246 | |
2a8f64ca VP |
4247 | dpll = DPLL_VGA_MODE_DIS; |
4248 | dpll |= DPLL_EXT_BUFFER_ENABLE_VLV; | |
4249 | dpll |= DPLL_REFA_CLK_ENABLE_VLV; | |
4250 | dpll |= DPLL_INTEGRATED_CLOCK_VLV; | |
4251 | ||
4252 | I915_WRITE(DPLL(pipe), dpll); | |
4253 | POSTING_READ(DPLL(pipe)); | |
a0c4da24 JB |
4254 | |
4255 | bestn = clock->n; | |
4256 | bestm1 = clock->m1; | |
4257 | bestm2 = clock->m2; | |
4258 | bestp1 = clock->p1; | |
4259 | bestp2 = clock->p2; | |
4260 | ||
2a8f64ca VP |
4261 | /* |
4262 | * In Valleyview PLL and program lane counter registers are exposed | |
4263 | * through DPIO interface | |
4264 | */ | |
a0c4da24 JB |
4265 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4266 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
4267 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
4268 | mdiv |= (1 << DPIO_POST_DIV_SHIFT); | |
4269 | mdiv |= (1 << DPIO_K_SHIFT); | |
4270 | mdiv |= DPIO_ENABLE_CALIBRATION; | |
4271 | intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); | |
4272 | ||
4273 | intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000); | |
4274 | ||
2a8f64ca | 4275 | pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) | |
a0c4da24 | 4276 | (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) | |
2a8f64ca VP |
4277 | (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) | |
4278 | (5 << DPIO_CLK_BIAS_CTL_SHIFT); | |
a0c4da24 JB |
4279 | intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv); |
4280 | ||
2a8f64ca | 4281 | intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b); |
a0c4da24 JB |
4282 | |
4283 | dpll |= DPLL_VCO_ENABLE; | |
4284 | I915_WRITE(DPLL(pipe), dpll); | |
4285 | POSTING_READ(DPLL(pipe)); | |
4286 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
4287 | DRM_ERROR("DPLL %d failed to lock\n", pipe); | |
4288 | ||
2a8f64ca VP |
4289 | intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620); |
4290 | ||
4291 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
4292 | intel_dp_set_m_n(crtc, mode, adjusted_mode); | |
4293 | ||
4294 | I915_WRITE(DPLL(pipe), dpll); | |
4295 | ||
4296 | /* Wait for the clocks to stabilize. */ | |
4297 | POSTING_READ(DPLL(pipe)); | |
4298 | udelay(150); | |
a0c4da24 | 4299 | |
2a8f64ca VP |
4300 | temp = 0; |
4301 | if (is_sdvo) { | |
4302 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); | |
a0c4da24 JB |
4303 | if (temp > 1) |
4304 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
4305 | else | |
4306 | temp = 0; | |
a0c4da24 | 4307 | } |
2a8f64ca VP |
4308 | I915_WRITE(DPLL_MD(pipe), temp); |
4309 | POSTING_READ(DPLL_MD(pipe)); | |
a0c4da24 | 4310 | |
2a8f64ca VP |
4311 | /* Now program lane control registers */ |
4312 | if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) | |
4313 | || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
4314 | { | |
4315 | temp = 0x1000C4; | |
4316 | if(pipe == 1) | |
4317 | temp |= (1 << 21); | |
4318 | intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp); | |
4319 | } | |
4320 | if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP)) | |
4321 | { | |
4322 | temp = 0x1000C4; | |
4323 | if(pipe == 1) | |
4324 | temp |= (1 << 21); | |
4325 | intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp); | |
4326 | } | |
09153000 DV |
4327 | |
4328 | mutex_unlock(&dev_priv->dpio_lock); | |
a0c4da24 JB |
4329 | } |
4330 | ||
eb1cbe48 DV |
4331 | static void i9xx_update_pll(struct drm_crtc *crtc, |
4332 | struct drm_display_mode *mode, | |
4333 | struct drm_display_mode *adjusted_mode, | |
4334 | intel_clock_t *clock, intel_clock_t *reduced_clock, | |
4335 | int num_connectors) | |
4336 | { | |
4337 | struct drm_device *dev = crtc->dev; | |
4338 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4339 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dafd226c | 4340 | struct intel_encoder *encoder; |
eb1cbe48 DV |
4341 | int pipe = intel_crtc->pipe; |
4342 | u32 dpll; | |
4343 | bool is_sdvo; | |
4344 | ||
2a8f64ca VP |
4345 | i9xx_update_pll_dividers(crtc, clock, reduced_clock); |
4346 | ||
eb1cbe48 DV |
4347 | is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) || |
4348 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); | |
4349 | ||
4350 | dpll = DPLL_VGA_MODE_DIS; | |
4351 | ||
4352 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
4353 | dpll |= DPLLB_MODE_LVDS; | |
4354 | else | |
4355 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
4356 | if (is_sdvo) { | |
4357 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); | |
4358 | if (pixel_multiplier > 1) { | |
4359 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
4360 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
4361 | } | |
4362 | dpll |= DPLL_DVO_HIGH_SPEED; | |
4363 | } | |
4364 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
4365 | dpll |= DPLL_DVO_HIGH_SPEED; | |
4366 | ||
4367 | /* compute bitmask from p1 value */ | |
4368 | if (IS_PINEVIEW(dev)) | |
4369 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
4370 | else { | |
4371 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4372 | if (IS_G4X(dev) && reduced_clock) | |
4373 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
4374 | } | |
4375 | switch (clock->p2) { | |
4376 | case 5: | |
4377 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
4378 | break; | |
4379 | case 7: | |
4380 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
4381 | break; | |
4382 | case 10: | |
4383 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
4384 | break; | |
4385 | case 14: | |
4386 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
4387 | break; | |
4388 | } | |
4389 | if (INTEL_INFO(dev)->gen >= 4) | |
4390 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
4391 | ||
4392 | if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
4393 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
4394 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
4395 | /* XXX: just matching BIOS for now */ | |
4396 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ | |
4397 | dpll |= 3; | |
4398 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
4399 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) | |
4400 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4401 | else | |
4402 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4403 | ||
4404 | dpll |= DPLL_VCO_ENABLE; | |
4405 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
4406 | POSTING_READ(DPLL(pipe)); | |
4407 | udelay(150); | |
4408 | ||
dafd226c DV |
4409 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4410 | if (encoder->pre_pll_enable) | |
4411 | encoder->pre_pll_enable(encoder); | |
eb1cbe48 DV |
4412 | |
4413 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
4414 | intel_dp_set_m_n(crtc, mode, adjusted_mode); | |
4415 | ||
4416 | I915_WRITE(DPLL(pipe), dpll); | |
4417 | ||
4418 | /* Wait for the clocks to stabilize. */ | |
4419 | POSTING_READ(DPLL(pipe)); | |
4420 | udelay(150); | |
4421 | ||
4422 | if (INTEL_INFO(dev)->gen >= 4) { | |
4423 | u32 temp = 0; | |
4424 | if (is_sdvo) { | |
4425 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); | |
4426 | if (temp > 1) | |
4427 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
4428 | else | |
4429 | temp = 0; | |
4430 | } | |
4431 | I915_WRITE(DPLL_MD(pipe), temp); | |
4432 | } else { | |
4433 | /* The pixel multiplier can only be updated once the | |
4434 | * DPLL is enabled and the clocks are stable. | |
4435 | * | |
4436 | * So write it again. | |
4437 | */ | |
4438 | I915_WRITE(DPLL(pipe), dpll); | |
4439 | } | |
4440 | } | |
4441 | ||
4442 | static void i8xx_update_pll(struct drm_crtc *crtc, | |
4443 | struct drm_display_mode *adjusted_mode, | |
2a8f64ca | 4444 | intel_clock_t *clock, intel_clock_t *reduced_clock, |
eb1cbe48 DV |
4445 | int num_connectors) |
4446 | { | |
4447 | struct drm_device *dev = crtc->dev; | |
4448 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4449 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dafd226c | 4450 | struct intel_encoder *encoder; |
eb1cbe48 DV |
4451 | int pipe = intel_crtc->pipe; |
4452 | u32 dpll; | |
4453 | ||
2a8f64ca VP |
4454 | i9xx_update_pll_dividers(crtc, clock, reduced_clock); |
4455 | ||
eb1cbe48 DV |
4456 | dpll = DPLL_VGA_MODE_DIS; |
4457 | ||
4458 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4459 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4460 | } else { | |
4461 | if (clock->p1 == 2) | |
4462 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
4463 | else | |
4464 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4465 | if (clock->p2 == 4) | |
4466 | dpll |= PLL_P2_DIVIDE_BY_4; | |
4467 | } | |
4468 | ||
4469 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
4470 | /* XXX: just matching BIOS for now */ | |
4471 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ | |
4472 | dpll |= 3; | |
4473 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
4474 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) | |
4475 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4476 | else | |
4477 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4478 | ||
4479 | dpll |= DPLL_VCO_ENABLE; | |
4480 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
4481 | POSTING_READ(DPLL(pipe)); | |
4482 | udelay(150); | |
4483 | ||
dafd226c DV |
4484 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4485 | if (encoder->pre_pll_enable) | |
4486 | encoder->pre_pll_enable(encoder); | |
eb1cbe48 | 4487 | |
5b5896e4 DV |
4488 | I915_WRITE(DPLL(pipe), dpll); |
4489 | ||
4490 | /* Wait for the clocks to stabilize. */ | |
4491 | POSTING_READ(DPLL(pipe)); | |
4492 | udelay(150); | |
4493 | ||
eb1cbe48 DV |
4494 | /* The pixel multiplier can only be updated once the |
4495 | * DPLL is enabled and the clocks are stable. | |
4496 | * | |
4497 | * So write it again. | |
4498 | */ | |
4499 | I915_WRITE(DPLL(pipe), dpll); | |
4500 | } | |
4501 | ||
b0e77b9c PZ |
4502 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc, |
4503 | struct drm_display_mode *mode, | |
4504 | struct drm_display_mode *adjusted_mode) | |
4505 | { | |
4506 | struct drm_device *dev = intel_crtc->base.dev; | |
4507 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4508 | enum pipe pipe = intel_crtc->pipe; | |
fe2b8f9d | 4509 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
b0e77b9c PZ |
4510 | uint32_t vsyncshift; |
4511 | ||
4512 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
4513 | /* the chip adds 2 halflines automatically */ | |
4514 | adjusted_mode->crtc_vtotal -= 1; | |
4515 | adjusted_mode->crtc_vblank_end -= 1; | |
4516 | vsyncshift = adjusted_mode->crtc_hsync_start | |
4517 | - adjusted_mode->crtc_htotal / 2; | |
4518 | } else { | |
4519 | vsyncshift = 0; | |
4520 | } | |
4521 | ||
4522 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 4523 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 4524 | |
fe2b8f9d | 4525 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
4526 | (adjusted_mode->crtc_hdisplay - 1) | |
4527 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 4528 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
4529 | (adjusted_mode->crtc_hblank_start - 1) | |
4530 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 4531 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
4532 | (adjusted_mode->crtc_hsync_start - 1) | |
4533 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
4534 | ||
fe2b8f9d | 4535 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c PZ |
4536 | (adjusted_mode->crtc_vdisplay - 1) | |
4537 | ((adjusted_mode->crtc_vtotal - 1) << 16)); | |
fe2b8f9d | 4538 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c PZ |
4539 | (adjusted_mode->crtc_vblank_start - 1) | |
4540 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); | |
fe2b8f9d | 4541 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
4542 | (adjusted_mode->crtc_vsync_start - 1) | |
4543 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
4544 | ||
b5e508d4 PZ |
4545 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
4546 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
4547 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
4548 | * bits. */ | |
4549 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
4550 | (pipe == PIPE_B || pipe == PIPE_C)) | |
4551 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
4552 | ||
b0e77b9c PZ |
4553 | /* pipesrc controls the size that is scaled from, which should |
4554 | * always be the user's requested size. | |
4555 | */ | |
4556 | I915_WRITE(PIPESRC(pipe), | |
4557 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
4558 | } | |
4559 | ||
f564048e EA |
4560 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
4561 | struct drm_display_mode *mode, | |
4562 | struct drm_display_mode *adjusted_mode, | |
4563 | int x, int y, | |
94352cf9 | 4564 | struct drm_framebuffer *fb) |
79e53945 JB |
4565 | { |
4566 | struct drm_device *dev = crtc->dev; | |
4567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4568 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4569 | int pipe = intel_crtc->pipe; | |
80824003 | 4570 | int plane = intel_crtc->plane; |
c751ce4f | 4571 | int refclk, num_connectors = 0; |
652c393a | 4572 | intel_clock_t clock, reduced_clock; |
b0e77b9c | 4573 | u32 dspcntr, pipeconf; |
eb1cbe48 DV |
4574 | bool ok, has_reduced_clock = false, is_sdvo = false; |
4575 | bool is_lvds = false, is_tv = false, is_dp = false; | |
5eddb70b | 4576 | struct intel_encoder *encoder; |
d4906093 | 4577 | const intel_limit_t *limit; |
5c3b82e2 | 4578 | int ret; |
79e53945 | 4579 | |
6c2b7c12 | 4580 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 4581 | switch (encoder->type) { |
79e53945 JB |
4582 | case INTEL_OUTPUT_LVDS: |
4583 | is_lvds = true; | |
4584 | break; | |
4585 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 4586 | case INTEL_OUTPUT_HDMI: |
79e53945 | 4587 | is_sdvo = true; |
5eddb70b | 4588 | if (encoder->needs_tv_clock) |
e2f0ba97 | 4589 | is_tv = true; |
79e53945 | 4590 | break; |
79e53945 JB |
4591 | case INTEL_OUTPUT_TVOUT: |
4592 | is_tv = true; | |
4593 | break; | |
a4fc5ed6 KP |
4594 | case INTEL_OUTPUT_DISPLAYPORT: |
4595 | is_dp = true; | |
4596 | break; | |
79e53945 | 4597 | } |
43565a06 | 4598 | |
c751ce4f | 4599 | num_connectors++; |
79e53945 JB |
4600 | } |
4601 | ||
c65d77d8 | 4602 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 4603 | |
d4906093 ML |
4604 | /* |
4605 | * Returns a set of divisors for the desired target clock with the given | |
4606 | * refclk, or FALSE. The returned values represent the clock equation: | |
4607 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
4608 | */ | |
1b894b59 | 4609 | limit = intel_limit(crtc, refclk); |
cec2f356 SP |
4610 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
4611 | &clock); | |
79e53945 JB |
4612 | if (!ok) { |
4613 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 4614 | return -EINVAL; |
79e53945 JB |
4615 | } |
4616 | ||
cda4b7d3 | 4617 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 4618 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 4619 | |
ddc9003c | 4620 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
4621 | /* |
4622 | * Ensure we match the reduced clock's P to the target clock. | |
4623 | * If the clocks don't match, we can't switch the display clock | |
4624 | * by using the FP0/FP1. In such case we will disable the LVDS | |
4625 | * downclock feature. | |
4626 | */ | |
ddc9003c | 4627 | has_reduced_clock = limit->find_pll(limit, crtc, |
5eddb70b CW |
4628 | dev_priv->lvds_downclock, |
4629 | refclk, | |
cec2f356 | 4630 | &clock, |
5eddb70b | 4631 | &reduced_clock); |
7026d4ac ZW |
4632 | } |
4633 | ||
c65d77d8 JB |
4634 | if (is_sdvo && is_tv) |
4635 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); | |
7026d4ac | 4636 | |
eb1cbe48 | 4637 | if (IS_GEN2(dev)) |
2a8f64ca VP |
4638 | i8xx_update_pll(crtc, adjusted_mode, &clock, |
4639 | has_reduced_clock ? &reduced_clock : NULL, | |
4640 | num_connectors); | |
a0c4da24 | 4641 | else if (IS_VALLEYVIEW(dev)) |
2a8f64ca VP |
4642 | vlv_update_pll(crtc, mode, adjusted_mode, &clock, |
4643 | has_reduced_clock ? &reduced_clock : NULL, | |
4644 | num_connectors); | |
79e53945 | 4645 | else |
eb1cbe48 DV |
4646 | i9xx_update_pll(crtc, mode, adjusted_mode, &clock, |
4647 | has_reduced_clock ? &reduced_clock : NULL, | |
4648 | num_connectors); | |
79e53945 JB |
4649 | |
4650 | /* setup pipeconf */ | |
5eddb70b | 4651 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
4652 | |
4653 | /* Set up the display plane register */ | |
4654 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4655 | ||
929c77fb EA |
4656 | if (pipe == 0) |
4657 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
4658 | else | |
4659 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
79e53945 | 4660 | |
a6c45cf0 | 4661 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
79e53945 JB |
4662 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
4663 | * core speed. | |
4664 | * | |
4665 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
4666 | * pipe == 0 check? | |
4667 | */ | |
e70236a8 JB |
4668 | if (mode->clock > |
4669 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
5eddb70b | 4670 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
79e53945 | 4671 | else |
5eddb70b | 4672 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
79e53945 JB |
4673 | } |
4674 | ||
3b5c78a3 | 4675 | /* default to 8bpc */ |
dfd07d72 | 4676 | pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN); |
3b5c78a3 | 4677 | if (is_dp) { |
0c96c65b | 4678 | if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
dfd07d72 | 4679 | pipeconf |= PIPECONF_6BPC | |
3b5c78a3 AJ |
4680 | PIPECONF_DITHER_EN | |
4681 | PIPECONF_DITHER_TYPE_SP; | |
4682 | } | |
4683 | } | |
4684 | ||
19c03924 GB |
4685 | if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { |
4686 | if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { | |
dfd07d72 | 4687 | pipeconf |= PIPECONF_6BPC | |
19c03924 GB |
4688 | PIPECONF_ENABLE | |
4689 | I965_PIPECONF_ACTIVE; | |
4690 | } | |
4691 | } | |
4692 | ||
28c97730 | 4693 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
4694 | drm_mode_debug_printmodeline(mode); |
4695 | ||
a7516a05 JB |
4696 | if (HAS_PIPE_CXSR(dev)) { |
4697 | if (intel_crtc->lowfreq_avail) { | |
28c97730 | 4698 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
652c393a | 4699 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
a7516a05 | 4700 | } else { |
28c97730 | 4701 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
652c393a JB |
4702 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
4703 | } | |
4704 | } | |
4705 | ||
617cf884 | 4706 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
dbb02575 | 4707 | if (!IS_GEN2(dev) && |
b0e77b9c | 4708 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
734b4157 | 4709 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
b0e77b9c | 4710 | else |
617cf884 | 4711 | pipeconf |= PIPECONF_PROGRESSIVE; |
734b4157 | 4712 | |
b0e77b9c | 4713 | intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); |
5eddb70b CW |
4714 | |
4715 | /* pipesrc and dspsize control the size that is scaled from, | |
4716 | * which should always be the user's requested size. | |
79e53945 | 4717 | */ |
929c77fb EA |
4718 | I915_WRITE(DSPSIZE(plane), |
4719 | ((mode->vdisplay - 1) << 16) | | |
4720 | (mode->hdisplay - 1)); | |
4721 | I915_WRITE(DSPPOS(plane), 0); | |
2c07245f | 4722 | |
f564048e EA |
4723 | I915_WRITE(PIPECONF(pipe), pipeconf); |
4724 | POSTING_READ(PIPECONF(pipe)); | |
929c77fb | 4725 | intel_enable_pipe(dev_priv, pipe, false); |
f564048e EA |
4726 | |
4727 | intel_wait_for_vblank(dev, pipe); | |
4728 | ||
f564048e EA |
4729 | I915_WRITE(DSPCNTR(plane), dspcntr); |
4730 | POSTING_READ(DSPCNTR(plane)); | |
4731 | ||
94352cf9 | 4732 | ret = intel_pipe_set_base(crtc, x, y, fb); |
f564048e EA |
4733 | |
4734 | intel_update_watermarks(dev); | |
4735 | ||
f564048e EA |
4736 | return ret; |
4737 | } | |
4738 | ||
dde86e2d | 4739 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
4740 | { |
4741 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4742 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 4743 | struct intel_encoder *encoder; |
13d83a67 JB |
4744 | u32 temp; |
4745 | bool has_lvds = false; | |
199e5d79 KP |
4746 | bool has_cpu_edp = false; |
4747 | bool has_pch_edp = false; | |
4748 | bool has_panel = false; | |
99eb6a01 KP |
4749 | bool has_ck505 = false; |
4750 | bool can_ssc = false; | |
13d83a67 JB |
4751 | |
4752 | /* We need to take the global config into account */ | |
199e5d79 KP |
4753 | list_for_each_entry(encoder, &mode_config->encoder_list, |
4754 | base.head) { | |
4755 | switch (encoder->type) { | |
4756 | case INTEL_OUTPUT_LVDS: | |
4757 | has_panel = true; | |
4758 | has_lvds = true; | |
4759 | break; | |
4760 | case INTEL_OUTPUT_EDP: | |
4761 | has_panel = true; | |
4762 | if (intel_encoder_is_pch_edp(&encoder->base)) | |
4763 | has_pch_edp = true; | |
4764 | else | |
4765 | has_cpu_edp = true; | |
4766 | break; | |
13d83a67 JB |
4767 | } |
4768 | } | |
4769 | ||
99eb6a01 KP |
4770 | if (HAS_PCH_IBX(dev)) { |
4771 | has_ck505 = dev_priv->display_clock_mode; | |
4772 | can_ssc = has_ck505; | |
4773 | } else { | |
4774 | has_ck505 = false; | |
4775 | can_ssc = true; | |
4776 | } | |
4777 | ||
4778 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", | |
4779 | has_panel, has_lvds, has_pch_edp, has_cpu_edp, | |
4780 | has_ck505); | |
13d83a67 JB |
4781 | |
4782 | /* Ironlake: try to setup display ref clock before DPLL | |
4783 | * enabling. This is only under driver's control after | |
4784 | * PCH B stepping, previous chipset stepping should be | |
4785 | * ignoring this setting. | |
4786 | */ | |
4787 | temp = I915_READ(PCH_DREF_CONTROL); | |
4788 | /* Always enable nonspread source */ | |
4789 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
13d83a67 | 4790 | |
99eb6a01 KP |
4791 | if (has_ck505) |
4792 | temp |= DREF_NONSPREAD_CK505_ENABLE; | |
4793 | else | |
4794 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | |
13d83a67 | 4795 | |
199e5d79 KP |
4796 | if (has_panel) { |
4797 | temp &= ~DREF_SSC_SOURCE_MASK; | |
4798 | temp |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 4799 | |
199e5d79 | 4800 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 4801 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 4802 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
13d83a67 | 4803 | temp |= DREF_SSC1_ENABLE; |
e77166b5 DV |
4804 | } else |
4805 | temp &= ~DREF_SSC1_ENABLE; | |
199e5d79 KP |
4806 | |
4807 | /* Get SSC going before enabling the outputs */ | |
4808 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
4809 | POSTING_READ(PCH_DREF_CONTROL); | |
4810 | udelay(200); | |
4811 | ||
13d83a67 JB |
4812 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
4813 | ||
4814 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 4815 | if (has_cpu_edp) { |
99eb6a01 | 4816 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 4817 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
13d83a67 | 4818 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 4819 | } |
13d83a67 JB |
4820 | else |
4821 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
199e5d79 KP |
4822 | } else |
4823 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
4824 | ||
4825 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
4826 | POSTING_READ(PCH_DREF_CONTROL); | |
4827 | udelay(200); | |
4828 | } else { | |
4829 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
4830 | ||
4831 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
4832 | ||
4833 | /* Turn off CPU output */ | |
4834 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
4835 | ||
4836 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
4837 | POSTING_READ(PCH_DREF_CONTROL); | |
4838 | udelay(200); | |
4839 | ||
4840 | /* Turn off the SSC source */ | |
4841 | temp &= ~DREF_SSC_SOURCE_MASK; | |
4842 | temp |= DREF_SSC_SOURCE_DISABLE; | |
4843 | ||
4844 | /* Turn off SSC1 */ | |
4845 | temp &= ~ DREF_SSC1_ENABLE; | |
4846 | ||
13d83a67 JB |
4847 | I915_WRITE(PCH_DREF_CONTROL, temp); |
4848 | POSTING_READ(PCH_DREF_CONTROL); | |
4849 | udelay(200); | |
4850 | } | |
4851 | } | |
4852 | ||
dde86e2d PZ |
4853 | /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */ |
4854 | static void lpt_init_pch_refclk(struct drm_device *dev) | |
4855 | { | |
4856 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4857 | struct drm_mode_config *mode_config = &dev->mode_config; | |
4858 | struct intel_encoder *encoder; | |
4859 | bool has_vga = false; | |
4860 | bool is_sdv = false; | |
4861 | u32 tmp; | |
4862 | ||
4863 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
4864 | switch (encoder->type) { | |
4865 | case INTEL_OUTPUT_ANALOG: | |
4866 | has_vga = true; | |
4867 | break; | |
4868 | } | |
4869 | } | |
4870 | ||
4871 | if (!has_vga) | |
4872 | return; | |
4873 | ||
c00db246 DV |
4874 | mutex_lock(&dev_priv->dpio_lock); |
4875 | ||
dde86e2d PZ |
4876 | /* XXX: Rip out SDV support once Haswell ships for real. */ |
4877 | if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00) | |
4878 | is_sdv = true; | |
4879 | ||
4880 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
4881 | tmp &= ~SBI_SSCCTL_DISABLE; | |
4882 | tmp |= SBI_SSCCTL_PATHALT; | |
4883 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
4884 | ||
4885 | udelay(24); | |
4886 | ||
4887 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
4888 | tmp &= ~SBI_SSCCTL_PATHALT; | |
4889 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
4890 | ||
4891 | if (!is_sdv) { | |
4892 | tmp = I915_READ(SOUTH_CHICKEN2); | |
4893 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
4894 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
4895 | ||
4896 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & | |
4897 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
4898 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
4899 | ||
4900 | tmp = I915_READ(SOUTH_CHICKEN2); | |
4901 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
4902 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
4903 | ||
4904 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & | |
4905 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, | |
4906 | 100)) | |
4907 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
4908 | } | |
4909 | ||
4910 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
4911 | tmp &= ~(0xFF << 24); | |
4912 | tmp |= (0x12 << 24); | |
4913 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
4914 | ||
4915 | if (!is_sdv) { | |
4916 | tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY); | |
4917 | tmp &= ~(0x3 << 6); | |
4918 | tmp |= (1 << 6) | (1 << 0); | |
4919 | intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY); | |
4920 | } | |
4921 | ||
4922 | if (is_sdv) { | |
4923 | tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY); | |
4924 | tmp |= 0x7FFF; | |
4925 | intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY); | |
4926 | } | |
4927 | ||
4928 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); | |
4929 | tmp |= (1 << 11); | |
4930 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
4931 | ||
4932 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
4933 | tmp |= (1 << 11); | |
4934 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
4935 | ||
4936 | if (is_sdv) { | |
4937 | tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY); | |
4938 | tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16); | |
4939 | intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY); | |
4940 | ||
4941 | tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY); | |
4942 | tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16); | |
4943 | intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY); | |
4944 | ||
4945 | tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY); | |
4946 | tmp |= (0x3F << 8); | |
4947 | intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY); | |
4948 | ||
4949 | tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY); | |
4950 | tmp |= (0x3F << 8); | |
4951 | intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY); | |
4952 | } | |
4953 | ||
4954 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); | |
4955 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
4956 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
4957 | ||
4958 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
4959 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
4960 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
4961 | ||
4962 | if (!is_sdv) { | |
4963 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); | |
4964 | tmp &= ~(7 << 13); | |
4965 | tmp |= (5 << 13); | |
4966 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
4967 | ||
4968 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); | |
4969 | tmp &= ~(7 << 13); | |
4970 | tmp |= (5 << 13); | |
4971 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
4972 | } | |
4973 | ||
4974 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
4975 | tmp &= ~0xFF; | |
4976 | tmp |= 0x1C; | |
4977 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
4978 | ||
4979 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
4980 | tmp &= ~0xFF; | |
4981 | tmp |= 0x1C; | |
4982 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
4983 | ||
4984 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
4985 | tmp &= ~(0xFF << 16); | |
4986 | tmp |= (0x1C << 16); | |
4987 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
4988 | ||
4989 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
4990 | tmp &= ~(0xFF << 16); | |
4991 | tmp |= (0x1C << 16); | |
4992 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
4993 | ||
4994 | if (!is_sdv) { | |
4995 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); | |
4996 | tmp |= (1 << 27); | |
4997 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
4998 | ||
4999 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); | |
5000 | tmp |= (1 << 27); | |
5001 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
5002 | ||
5003 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); | |
5004 | tmp &= ~(0xF << 28); | |
5005 | tmp |= (4 << 28); | |
5006 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
5007 | ||
5008 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); | |
5009 | tmp &= ~(0xF << 28); | |
5010 | tmp |= (4 << 28); | |
5011 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
5012 | } | |
5013 | ||
5014 | /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */ | |
5015 | tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK); | |
5016 | tmp |= SBI_DBUFF0_ENABLE; | |
5017 | intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK); | |
c00db246 DV |
5018 | |
5019 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
5020 | } |
5021 | ||
5022 | /* | |
5023 | * Initialize reference clocks when the driver loads | |
5024 | */ | |
5025 | void intel_init_pch_refclk(struct drm_device *dev) | |
5026 | { | |
5027 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
5028 | ironlake_init_pch_refclk(dev); | |
5029 | else if (HAS_PCH_LPT(dev)) | |
5030 | lpt_init_pch_refclk(dev); | |
5031 | } | |
5032 | ||
d9d444cb JB |
5033 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5034 | { | |
5035 | struct drm_device *dev = crtc->dev; | |
5036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5037 | struct intel_encoder *encoder; | |
d9d444cb JB |
5038 | struct intel_encoder *edp_encoder = NULL; |
5039 | int num_connectors = 0; | |
5040 | bool is_lvds = false; | |
5041 | ||
6c2b7c12 | 5042 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
5043 | switch (encoder->type) { |
5044 | case INTEL_OUTPUT_LVDS: | |
5045 | is_lvds = true; | |
5046 | break; | |
5047 | case INTEL_OUTPUT_EDP: | |
5048 | edp_encoder = encoder; | |
5049 | break; | |
5050 | } | |
5051 | num_connectors++; | |
5052 | } | |
5053 | ||
5054 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
5055 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
5056 | dev_priv->lvds_ssc_freq); | |
5057 | return dev_priv->lvds_ssc_freq * 1000; | |
5058 | } | |
5059 | ||
5060 | return 120000; | |
5061 | } | |
5062 | ||
c8203565 | 5063 | static void ironlake_set_pipeconf(struct drm_crtc *crtc, |
f564048e | 5064 | struct drm_display_mode *adjusted_mode, |
c8203565 | 5065 | bool dither) |
79e53945 | 5066 | { |
c8203565 | 5067 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
5068 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5069 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
5070 | uint32_t val; |
5071 | ||
5072 | val = I915_READ(PIPECONF(pipe)); | |
5073 | ||
dfd07d72 | 5074 | val &= ~PIPECONF_BPC_MASK; |
c8203565 PZ |
5075 | switch (intel_crtc->bpp) { |
5076 | case 18: | |
dfd07d72 | 5077 | val |= PIPECONF_6BPC; |
c8203565 PZ |
5078 | break; |
5079 | case 24: | |
dfd07d72 | 5080 | val |= PIPECONF_8BPC; |
c8203565 PZ |
5081 | break; |
5082 | case 30: | |
dfd07d72 | 5083 | val |= PIPECONF_10BPC; |
c8203565 PZ |
5084 | break; |
5085 | case 36: | |
dfd07d72 | 5086 | val |= PIPECONF_12BPC; |
c8203565 PZ |
5087 | break; |
5088 | default: | |
cc769b62 PZ |
5089 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5090 | BUG(); | |
c8203565 PZ |
5091 | } |
5092 | ||
5093 | val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); | |
5094 | if (dither) | |
5095 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); | |
5096 | ||
5097 | val &= ~PIPECONF_INTERLACE_MASK; | |
5098 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
5099 | val |= PIPECONF_INTERLACED_ILK; | |
5100 | else | |
5101 | val |= PIPECONF_PROGRESSIVE; | |
5102 | ||
3685a8f3 VS |
5103 | if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) |
5104 | val |= PIPECONF_COLOR_RANGE_SELECT; | |
5105 | else | |
5106 | val &= ~PIPECONF_COLOR_RANGE_SELECT; | |
5107 | ||
c8203565 PZ |
5108 | I915_WRITE(PIPECONF(pipe), val); |
5109 | POSTING_READ(PIPECONF(pipe)); | |
5110 | } | |
5111 | ||
ee2b0b38 PZ |
5112 | static void haswell_set_pipeconf(struct drm_crtc *crtc, |
5113 | struct drm_display_mode *adjusted_mode, | |
5114 | bool dither) | |
5115 | { | |
5116 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
5117 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
702e7a56 | 5118 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
ee2b0b38 PZ |
5119 | uint32_t val; |
5120 | ||
702e7a56 | 5121 | val = I915_READ(PIPECONF(cpu_transcoder)); |
ee2b0b38 PZ |
5122 | |
5123 | val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); | |
5124 | if (dither) | |
5125 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); | |
5126 | ||
5127 | val &= ~PIPECONF_INTERLACE_MASK_HSW; | |
5128 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
5129 | val |= PIPECONF_INTERLACED_ILK; | |
5130 | else | |
5131 | val |= PIPECONF_PROGRESSIVE; | |
5132 | ||
702e7a56 PZ |
5133 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
5134 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
ee2b0b38 PZ |
5135 | } |
5136 | ||
6591c6e4 PZ |
5137 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
5138 | struct drm_display_mode *adjusted_mode, | |
5139 | intel_clock_t *clock, | |
5140 | bool *has_reduced_clock, | |
5141 | intel_clock_t *reduced_clock) | |
5142 | { | |
5143 | struct drm_device *dev = crtc->dev; | |
5144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5145 | struct intel_encoder *intel_encoder; | |
5146 | int refclk; | |
d4906093 | 5147 | const intel_limit_t *limit; |
6591c6e4 | 5148 | bool ret, is_sdvo = false, is_tv = false, is_lvds = false; |
79e53945 | 5149 | |
6591c6e4 PZ |
5150 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5151 | switch (intel_encoder->type) { | |
79e53945 JB |
5152 | case INTEL_OUTPUT_LVDS: |
5153 | is_lvds = true; | |
5154 | break; | |
5155 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5156 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5157 | is_sdvo = true; |
6591c6e4 | 5158 | if (intel_encoder->needs_tv_clock) |
e2f0ba97 | 5159 | is_tv = true; |
79e53945 | 5160 | break; |
79e53945 JB |
5161 | case INTEL_OUTPUT_TVOUT: |
5162 | is_tv = true; | |
5163 | break; | |
79e53945 JB |
5164 | } |
5165 | } | |
5166 | ||
d9d444cb | 5167 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 5168 | |
d4906093 ML |
5169 | /* |
5170 | * Returns a set of divisors for the desired target clock with the given | |
5171 | * refclk, or FALSE. The returned values represent the clock equation: | |
5172 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
5173 | */ | |
1b894b59 | 5174 | limit = intel_limit(crtc, refclk); |
6591c6e4 PZ |
5175 | ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
5176 | clock); | |
5177 | if (!ret) | |
5178 | return false; | |
cda4b7d3 | 5179 | |
ddc9003c | 5180 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
5181 | /* |
5182 | * Ensure we match the reduced clock's P to the target clock. | |
5183 | * If the clocks don't match, we can't switch the display clock | |
5184 | * by using the FP0/FP1. In such case we will disable the LVDS | |
5185 | * downclock feature. | |
5186 | */ | |
6591c6e4 PZ |
5187 | *has_reduced_clock = limit->find_pll(limit, crtc, |
5188 | dev_priv->lvds_downclock, | |
5189 | refclk, | |
5190 | clock, | |
5191 | reduced_clock); | |
652c393a | 5192 | } |
61e9653f DV |
5193 | |
5194 | if (is_sdvo && is_tv) | |
6591c6e4 PZ |
5195 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock); |
5196 | ||
5197 | return true; | |
5198 | } | |
5199 | ||
01a415fd DV |
5200 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
5201 | { | |
5202 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5203 | uint32_t temp; | |
5204 | ||
5205 | temp = I915_READ(SOUTH_CHICKEN1); | |
5206 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
5207 | return; | |
5208 | ||
5209 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
5210 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
5211 | ||
5212 | temp |= FDI_BC_BIFURCATION_SELECT; | |
5213 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
5214 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
5215 | POSTING_READ(SOUTH_CHICKEN1); | |
5216 | } | |
5217 | ||
5218 | static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc) | |
5219 | { | |
5220 | struct drm_device *dev = intel_crtc->base.dev; | |
5221 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5222 | struct intel_crtc *pipe_B_crtc = | |
5223 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
5224 | ||
5225 | DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n", | |
5226 | intel_crtc->pipe, intel_crtc->fdi_lanes); | |
5227 | if (intel_crtc->fdi_lanes > 4) { | |
5228 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n", | |
5229 | intel_crtc->pipe, intel_crtc->fdi_lanes); | |
5230 | /* Clamp lanes to avoid programming the hw with bogus values. */ | |
5231 | intel_crtc->fdi_lanes = 4; | |
5232 | ||
5233 | return false; | |
5234 | } | |
5235 | ||
5236 | if (dev_priv->num_pipe == 2) | |
5237 | return true; | |
5238 | ||
5239 | switch (intel_crtc->pipe) { | |
5240 | case PIPE_A: | |
5241 | return true; | |
5242 | case PIPE_B: | |
5243 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
5244 | intel_crtc->fdi_lanes > 2) { | |
5245 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n", | |
5246 | intel_crtc->pipe, intel_crtc->fdi_lanes); | |
5247 | /* Clamp lanes to avoid programming the hw with bogus values. */ | |
5248 | intel_crtc->fdi_lanes = 2; | |
5249 | ||
5250 | return false; | |
5251 | } | |
5252 | ||
5253 | if (intel_crtc->fdi_lanes > 2) | |
5254 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
5255 | else | |
5256 | cpt_enable_fdi_bc_bifurcation(dev); | |
5257 | ||
5258 | return true; | |
5259 | case PIPE_C: | |
5260 | if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) { | |
5261 | if (intel_crtc->fdi_lanes > 2) { | |
5262 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n", | |
5263 | intel_crtc->pipe, intel_crtc->fdi_lanes); | |
5264 | /* Clamp lanes to avoid programming the hw with bogus values. */ | |
5265 | intel_crtc->fdi_lanes = 2; | |
5266 | ||
5267 | return false; | |
5268 | } | |
5269 | } else { | |
5270 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
5271 | return false; | |
5272 | } | |
5273 | ||
5274 | cpt_enable_fdi_bc_bifurcation(dev); | |
5275 | ||
5276 | return true; | |
5277 | default: | |
5278 | BUG(); | |
5279 | } | |
5280 | } | |
5281 | ||
d4b1931c PZ |
5282 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
5283 | { | |
5284 | /* | |
5285 | * Account for spread spectrum to avoid | |
5286 | * oversubscribing the link. Max center spread | |
5287 | * is 2.5%; use 5% for safety's sake. | |
5288 | */ | |
5289 | u32 bps = target_clock * bpp * 21 / 20; | |
5290 | return bps / (link_bw * 8) + 1; | |
5291 | } | |
5292 | ||
f48d8f23 PZ |
5293 | static void ironlake_set_m_n(struct drm_crtc *crtc, |
5294 | struct drm_display_mode *mode, | |
5295 | struct drm_display_mode *adjusted_mode) | |
79e53945 JB |
5296 | { |
5297 | struct drm_device *dev = crtc->dev; | |
5298 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5299 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
afe2fcf5 | 5300 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
f48d8f23 | 5301 | struct intel_encoder *intel_encoder, *edp_encoder = NULL; |
e69d0bc1 | 5302 | struct intel_link_m_n m_n = {0}; |
f48d8f23 PZ |
5303 | int target_clock, pixel_multiplier, lane, link_bw; |
5304 | bool is_dp = false, is_cpu_edp = false; | |
79e53945 | 5305 | |
f48d8f23 PZ |
5306 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5307 | switch (intel_encoder->type) { | |
a4fc5ed6 KP |
5308 | case INTEL_OUTPUT_DISPLAYPORT: |
5309 | is_dp = true; | |
5310 | break; | |
32f9d658 | 5311 | case INTEL_OUTPUT_EDP: |
e3aef172 | 5312 | is_dp = true; |
f48d8f23 | 5313 | if (!intel_encoder_is_pch_edp(&intel_encoder->base)) |
e3aef172 | 5314 | is_cpu_edp = true; |
f48d8f23 | 5315 | edp_encoder = intel_encoder; |
32f9d658 | 5316 | break; |
79e53945 | 5317 | } |
79e53945 | 5318 | } |
61e9653f | 5319 | |
2c07245f | 5320 | /* FDI link */ |
8febb297 EA |
5321 | pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
5322 | lane = 0; | |
5323 | /* CPU eDP doesn't require FDI link, so just set DP M/N | |
5324 | according to current link config */ | |
e3aef172 | 5325 | if (is_cpu_edp) { |
e3aef172 | 5326 | intel_edp_link_config(edp_encoder, &lane, &link_bw); |
8febb297 | 5327 | } else { |
8febb297 EA |
5328 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5329 | * each output octet as 10 bits. The actual frequency | |
5330 | * is stored as a divider into a 100MHz clock, and the | |
5331 | * mode pixel clock is stored in units of 1KHz. | |
5332 | * Hence the bw of each lane in terms of the mode signal | |
5333 | * is: | |
5334 | */ | |
5335 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5336 | } | |
58a27471 | 5337 | |
94bf2ced DV |
5338 | /* [e]DP over FDI requires target mode clock instead of link clock. */ |
5339 | if (edp_encoder) | |
5340 | target_clock = intel_edp_target_clock(edp_encoder, mode); | |
5341 | else if (is_dp) | |
5342 | target_clock = mode->clock; | |
5343 | else | |
5344 | target_clock = adjusted_mode->clock; | |
5345 | ||
d4b1931c PZ |
5346 | if (!lane) |
5347 | lane = ironlake_get_lanes_required(target_clock, link_bw, | |
5348 | intel_crtc->bpp); | |
2c07245f | 5349 | |
8febb297 EA |
5350 | intel_crtc->fdi_lanes = lane; |
5351 | ||
5352 | if (pixel_multiplier > 1) | |
5353 | link_bw *= pixel_multiplier; | |
e69d0bc1 | 5354 | intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n); |
8febb297 | 5355 | |
afe2fcf5 PZ |
5356 | I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m); |
5357 | I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n); | |
5358 | I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m); | |
5359 | I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n); | |
f48d8f23 PZ |
5360 | } |
5361 | ||
de13a2e3 PZ |
5362 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
5363 | struct drm_display_mode *adjusted_mode, | |
5364 | intel_clock_t *clock, u32 fp) | |
79e53945 | 5365 | { |
de13a2e3 | 5366 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
5367 | struct drm_device *dev = crtc->dev; |
5368 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
5369 | struct intel_encoder *intel_encoder; |
5370 | uint32_t dpll; | |
5371 | int factor, pixel_multiplier, num_connectors = 0; | |
5372 | bool is_lvds = false, is_sdvo = false, is_tv = false; | |
5373 | bool is_dp = false, is_cpu_edp = false; | |
79e53945 | 5374 | |
de13a2e3 PZ |
5375 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5376 | switch (intel_encoder->type) { | |
79e53945 JB |
5377 | case INTEL_OUTPUT_LVDS: |
5378 | is_lvds = true; | |
5379 | break; | |
5380 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5381 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5382 | is_sdvo = true; |
de13a2e3 | 5383 | if (intel_encoder->needs_tv_clock) |
e2f0ba97 | 5384 | is_tv = true; |
79e53945 | 5385 | break; |
79e53945 JB |
5386 | case INTEL_OUTPUT_TVOUT: |
5387 | is_tv = true; | |
5388 | break; | |
a4fc5ed6 KP |
5389 | case INTEL_OUTPUT_DISPLAYPORT: |
5390 | is_dp = true; | |
5391 | break; | |
32f9d658 | 5392 | case INTEL_OUTPUT_EDP: |
e3aef172 | 5393 | is_dp = true; |
de13a2e3 | 5394 | if (!intel_encoder_is_pch_edp(&intel_encoder->base)) |
e3aef172 | 5395 | is_cpu_edp = true; |
32f9d658 | 5396 | break; |
79e53945 | 5397 | } |
43565a06 | 5398 | |
c751ce4f | 5399 | num_connectors++; |
79e53945 | 5400 | } |
79e53945 | 5401 | |
c1858123 | 5402 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
5403 | factor = 21; |
5404 | if (is_lvds) { | |
5405 | if ((intel_panel_use_ssc(dev_priv) && | |
5406 | dev_priv->lvds_ssc_freq == 100) || | |
1974cad0 | 5407 | intel_is_dual_link_lvds(dev)) |
8febb297 EA |
5408 | factor = 25; |
5409 | } else if (is_sdvo && is_tv) | |
5410 | factor = 20; | |
c1858123 | 5411 | |
de13a2e3 | 5412 | if (clock->m < factor * clock->n) |
8febb297 | 5413 | fp |= FP_CB_TUNE; |
2c07245f | 5414 | |
5eddb70b | 5415 | dpll = 0; |
2c07245f | 5416 | |
a07d6787 EA |
5417 | if (is_lvds) |
5418 | dpll |= DPLLB_MODE_LVDS; | |
5419 | else | |
5420 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
5421 | if (is_sdvo) { | |
de13a2e3 | 5422 | pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
a07d6787 EA |
5423 | if (pixel_multiplier > 1) { |
5424 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
79e53945 | 5425 | } |
a07d6787 EA |
5426 | dpll |= DPLL_DVO_HIGH_SPEED; |
5427 | } | |
e3aef172 | 5428 | if (is_dp && !is_cpu_edp) |
a07d6787 | 5429 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 | 5430 | |
a07d6787 | 5431 | /* compute bitmask from p1 value */ |
de13a2e3 | 5432 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 5433 | /* also FPA1 */ |
de13a2e3 | 5434 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 5435 | |
de13a2e3 | 5436 | switch (clock->p2) { |
a07d6787 EA |
5437 | case 5: |
5438 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5439 | break; | |
5440 | case 7: | |
5441 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5442 | break; | |
5443 | case 10: | |
5444 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5445 | break; | |
5446 | case 14: | |
5447 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5448 | break; | |
79e53945 JB |
5449 | } |
5450 | ||
43565a06 KH |
5451 | if (is_sdvo && is_tv) |
5452 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
5453 | else if (is_tv) | |
79e53945 | 5454 | /* XXX: just matching BIOS for now */ |
43565a06 | 5455 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 5456 | dpll |= 3; |
a7615030 | 5457 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 5458 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
5459 | else |
5460 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5461 | ||
de13a2e3 PZ |
5462 | return dpll; |
5463 | } | |
5464 | ||
5465 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
5466 | struct drm_display_mode *mode, | |
5467 | struct drm_display_mode *adjusted_mode, | |
5468 | int x, int y, | |
5469 | struct drm_framebuffer *fb) | |
5470 | { | |
5471 | struct drm_device *dev = crtc->dev; | |
5472 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5473 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5474 | int pipe = intel_crtc->pipe; | |
5475 | int plane = intel_crtc->plane; | |
5476 | int num_connectors = 0; | |
5477 | intel_clock_t clock, reduced_clock; | |
5478 | u32 dpll, fp = 0, fp2 = 0; | |
e2f12b07 PZ |
5479 | bool ok, has_reduced_clock = false; |
5480 | bool is_lvds = false, is_dp = false, is_cpu_edp = false; | |
de13a2e3 | 5481 | struct intel_encoder *encoder; |
de13a2e3 | 5482 | int ret; |
01a415fd | 5483 | bool dither, fdi_config_ok; |
de13a2e3 PZ |
5484 | |
5485 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
5486 | switch (encoder->type) { | |
5487 | case INTEL_OUTPUT_LVDS: | |
5488 | is_lvds = true; | |
5489 | break; | |
de13a2e3 PZ |
5490 | case INTEL_OUTPUT_DISPLAYPORT: |
5491 | is_dp = true; | |
5492 | break; | |
5493 | case INTEL_OUTPUT_EDP: | |
5494 | is_dp = true; | |
e2f12b07 | 5495 | if (!intel_encoder_is_pch_edp(&encoder->base)) |
de13a2e3 PZ |
5496 | is_cpu_edp = true; |
5497 | break; | |
5498 | } | |
5499 | ||
5500 | num_connectors++; | |
a07d6787 | 5501 | } |
79e53945 | 5502 | |
5dc5298b PZ |
5503 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
5504 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 5505 | |
de13a2e3 PZ |
5506 | ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock, |
5507 | &has_reduced_clock, &reduced_clock); | |
5508 | if (!ok) { | |
5509 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5510 | return -EINVAL; | |
79e53945 JB |
5511 | } |
5512 | ||
de13a2e3 PZ |
5513 | /* Ensure that the cursor is valid for the new mode before changing... */ |
5514 | intel_crtc_update_cursor(crtc, true); | |
5515 | ||
5516 | /* determine panel color depth */ | |
c8241969 JN |
5517 | dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, |
5518 | adjusted_mode); | |
de13a2e3 PZ |
5519 | if (is_lvds && dev_priv->lvds_dither) |
5520 | dither = true; | |
5521 | ||
5522 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; | |
5523 | if (has_reduced_clock) | |
5524 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
5525 | reduced_clock.m2; | |
5526 | ||
5527 | dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp); | |
79e53945 | 5528 | |
f7cb34d4 | 5529 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
79e53945 JB |
5530 | drm_mode_debug_printmodeline(mode); |
5531 | ||
5dc5298b PZ |
5532 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
5533 | if (!is_cpu_edp) { | |
ee7b9f93 | 5534 | struct intel_pch_pll *pll; |
4b645f14 | 5535 | |
ee7b9f93 JB |
5536 | pll = intel_get_pch_pll(intel_crtc, dpll, fp); |
5537 | if (pll == NULL) { | |
5538 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n", | |
5539 | pipe); | |
4b645f14 JB |
5540 | return -EINVAL; |
5541 | } | |
ee7b9f93 JB |
5542 | } else |
5543 | intel_put_pch_pll(intel_crtc); | |
79e53945 | 5544 | |
2f0c2ad1 | 5545 | if (is_dp && !is_cpu_edp) |
a4fc5ed6 | 5546 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
79e53945 | 5547 | |
dafd226c DV |
5548 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5549 | if (encoder->pre_pll_enable) | |
5550 | encoder->pre_pll_enable(encoder); | |
79e53945 | 5551 | |
ee7b9f93 JB |
5552 | if (intel_crtc->pch_pll) { |
5553 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); | |
5eddb70b | 5554 | |
32f9d658 | 5555 | /* Wait for the clocks to stabilize. */ |
ee7b9f93 | 5556 | POSTING_READ(intel_crtc->pch_pll->pll_reg); |
32f9d658 ZW |
5557 | udelay(150); |
5558 | ||
8febb297 EA |
5559 | /* The pixel multiplier can only be updated once the |
5560 | * DPLL is enabled and the clocks are stable. | |
5561 | * | |
5562 | * So write it again. | |
5563 | */ | |
ee7b9f93 | 5564 | I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); |
79e53945 | 5565 | } |
79e53945 | 5566 | |
5eddb70b | 5567 | intel_crtc->lowfreq_avail = false; |
ee7b9f93 | 5568 | if (intel_crtc->pch_pll) { |
4b645f14 | 5569 | if (is_lvds && has_reduced_clock && i915_powersave) { |
ee7b9f93 | 5570 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2); |
4b645f14 | 5571 | intel_crtc->lowfreq_avail = true; |
4b645f14 | 5572 | } else { |
ee7b9f93 | 5573 | I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp); |
652c393a JB |
5574 | } |
5575 | } | |
5576 | ||
b0e77b9c | 5577 | intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); |
5eddb70b | 5578 | |
01a415fd DV |
5579 | /* Note, this also computes intel_crtc->fdi_lanes which is used below in |
5580 | * ironlake_check_fdi_lanes. */ | |
f48d8f23 | 5581 | ironlake_set_m_n(crtc, mode, adjusted_mode); |
2c07245f | 5582 | |
01a415fd | 5583 | fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc); |
2c07245f | 5584 | |
c8203565 | 5585 | ironlake_set_pipeconf(crtc, adjusted_mode, dither); |
79e53945 | 5586 | |
9d0498a2 | 5587 | intel_wait_for_vblank(dev, pipe); |
79e53945 | 5588 | |
a1f9e77e PZ |
5589 | /* Set up the display plane register */ |
5590 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
b24e7179 | 5591 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 5592 | |
94352cf9 | 5593 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7662c8bd SL |
5594 | |
5595 | intel_update_watermarks(dev); | |
5596 | ||
1f8eeabf ED |
5597 | intel_update_linetime_watermarks(dev, pipe, adjusted_mode); |
5598 | ||
01a415fd | 5599 | return fdi_config_ok ? ret : -EINVAL; |
79e53945 JB |
5600 | } |
5601 | ||
d6dd9eb1 DV |
5602 | static void haswell_modeset_global_resources(struct drm_device *dev) |
5603 | { | |
5604 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5605 | bool enable = false; | |
5606 | struct intel_crtc *crtc; | |
5607 | struct intel_encoder *encoder; | |
5608 | ||
5609 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
5610 | if (crtc->pipe != PIPE_A && crtc->base.enabled) | |
5611 | enable = true; | |
5612 | /* XXX: Should check for edp transcoder here, but thanks to init | |
5613 | * sequence that's not yet available. Just in case desktop eDP | |
5614 | * on PORT D is possible on haswell, too. */ | |
5615 | } | |
5616 | ||
5617 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
5618 | base.head) { | |
5619 | if (encoder->type != INTEL_OUTPUT_EDP && | |
5620 | encoder->connectors_active) | |
5621 | enable = true; | |
5622 | } | |
5623 | ||
5624 | /* Even the eDP panel fitter is outside the always-on well. */ | |
5625 | if (dev_priv->pch_pf_size) | |
5626 | enable = true; | |
5627 | ||
5628 | intel_set_power_well(dev, enable); | |
5629 | } | |
5630 | ||
09b4ddf9 PZ |
5631 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
5632 | struct drm_display_mode *mode, | |
5633 | struct drm_display_mode *adjusted_mode, | |
5634 | int x, int y, | |
5635 | struct drm_framebuffer *fb) | |
5636 | { | |
5637 | struct drm_device *dev = crtc->dev; | |
5638 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5639 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5640 | int pipe = intel_crtc->pipe; | |
5641 | int plane = intel_crtc->plane; | |
5642 | int num_connectors = 0; | |
ed7ef439 | 5643 | bool is_dp = false, is_cpu_edp = false; |
09b4ddf9 | 5644 | struct intel_encoder *encoder; |
09b4ddf9 PZ |
5645 | int ret; |
5646 | bool dither; | |
5647 | ||
5648 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
5649 | switch (encoder->type) { | |
09b4ddf9 PZ |
5650 | case INTEL_OUTPUT_DISPLAYPORT: |
5651 | is_dp = true; | |
5652 | break; | |
5653 | case INTEL_OUTPUT_EDP: | |
5654 | is_dp = true; | |
5655 | if (!intel_encoder_is_pch_edp(&encoder->base)) | |
5656 | is_cpu_edp = true; | |
5657 | break; | |
5658 | } | |
5659 | ||
5660 | num_connectors++; | |
5661 | } | |
5662 | ||
5dc5298b PZ |
5663 | /* We are not sure yet this won't happen. */ |
5664 | WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n", | |
5665 | INTEL_PCH_TYPE(dev)); | |
5666 | ||
5667 | WARN(num_connectors != 1, "%d connectors attached to pipe %c\n", | |
5668 | num_connectors, pipe_name(pipe)); | |
5669 | ||
702e7a56 | 5670 | WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) & |
1ce42920 PZ |
5671 | (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE)); |
5672 | ||
5673 | WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE); | |
5674 | ||
6441ab5f PZ |
5675 | if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock)) |
5676 | return -EINVAL; | |
5677 | ||
09b4ddf9 PZ |
5678 | /* Ensure that the cursor is valid for the new mode before changing... */ |
5679 | intel_crtc_update_cursor(crtc, true); | |
5680 | ||
5681 | /* determine panel color depth */ | |
c8241969 JN |
5682 | dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, |
5683 | adjusted_mode); | |
09b4ddf9 | 5684 | |
09b4ddf9 PZ |
5685 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
5686 | drm_mode_debug_printmodeline(mode); | |
5687 | ||
ed7ef439 | 5688 | if (is_dp && !is_cpu_edp) |
09b4ddf9 | 5689 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
09b4ddf9 PZ |
5690 | |
5691 | intel_crtc->lowfreq_avail = false; | |
09b4ddf9 PZ |
5692 | |
5693 | intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); | |
5694 | ||
1eb8dfec PZ |
5695 | if (!is_dp || is_cpu_edp) |
5696 | ironlake_set_m_n(crtc, mode, adjusted_mode); | |
09b4ddf9 | 5697 | |
ee2b0b38 | 5698 | haswell_set_pipeconf(crtc, adjusted_mode, dither); |
09b4ddf9 | 5699 | |
09b4ddf9 PZ |
5700 | /* Set up the display plane register */ |
5701 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
5702 | POSTING_READ(DSPCNTR(plane)); | |
5703 | ||
5704 | ret = intel_pipe_set_base(crtc, x, y, fb); | |
5705 | ||
5706 | intel_update_watermarks(dev); | |
5707 | ||
5708 | intel_update_linetime_watermarks(dev, pipe, adjusted_mode); | |
5709 | ||
1f803ee5 | 5710 | return ret; |
79e53945 JB |
5711 | } |
5712 | ||
f564048e EA |
5713 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
5714 | struct drm_display_mode *mode, | |
5715 | struct drm_display_mode *adjusted_mode, | |
5716 | int x, int y, | |
94352cf9 | 5717 | struct drm_framebuffer *fb) |
f564048e EA |
5718 | { |
5719 | struct drm_device *dev = crtc->dev; | |
5720 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9256aa19 DV |
5721 | struct drm_encoder_helper_funcs *encoder_funcs; |
5722 | struct intel_encoder *encoder; | |
0b701d27 EA |
5723 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5724 | int pipe = intel_crtc->pipe; | |
f564048e EA |
5725 | int ret; |
5726 | ||
cc464b2a PZ |
5727 | if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
5728 | intel_crtc->cpu_transcoder = TRANSCODER_EDP; | |
5729 | else | |
5730 | intel_crtc->cpu_transcoder = pipe; | |
5731 | ||
0b701d27 | 5732 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 5733 | |
f564048e | 5734 | ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, |
94352cf9 | 5735 | x, y, fb); |
79e53945 | 5736 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 5737 | |
9256aa19 DV |
5738 | if (ret != 0) |
5739 | return ret; | |
5740 | ||
5741 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
5742 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", | |
5743 | encoder->base.base.id, | |
5744 | drm_get_encoder_name(&encoder->base), | |
5745 | mode->base.id, mode->name); | |
5746 | encoder_funcs = encoder->base.helper_private; | |
5747 | encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode); | |
5748 | } | |
5749 | ||
5750 | return 0; | |
79e53945 JB |
5751 | } |
5752 | ||
3a9627f4 WF |
5753 | static bool intel_eld_uptodate(struct drm_connector *connector, |
5754 | int reg_eldv, uint32_t bits_eldv, | |
5755 | int reg_elda, uint32_t bits_elda, | |
5756 | int reg_edid) | |
5757 | { | |
5758 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5759 | uint8_t *eld = connector->eld; | |
5760 | uint32_t i; | |
5761 | ||
5762 | i = I915_READ(reg_eldv); | |
5763 | i &= bits_eldv; | |
5764 | ||
5765 | if (!eld[0]) | |
5766 | return !i; | |
5767 | ||
5768 | if (!i) | |
5769 | return false; | |
5770 | ||
5771 | i = I915_READ(reg_elda); | |
5772 | i &= ~bits_elda; | |
5773 | I915_WRITE(reg_elda, i); | |
5774 | ||
5775 | for (i = 0; i < eld[2]; i++) | |
5776 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
5777 | return false; | |
5778 | ||
5779 | return true; | |
5780 | } | |
5781 | ||
e0dac65e WF |
5782 | static void g4x_write_eld(struct drm_connector *connector, |
5783 | struct drm_crtc *crtc) | |
5784 | { | |
5785 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5786 | uint8_t *eld = connector->eld; | |
5787 | uint32_t eldv; | |
5788 | uint32_t len; | |
5789 | uint32_t i; | |
5790 | ||
5791 | i = I915_READ(G4X_AUD_VID_DID); | |
5792 | ||
5793 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
5794 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
5795 | else | |
5796 | eldv = G4X_ELDV_DEVCTG; | |
5797 | ||
3a9627f4 WF |
5798 | if (intel_eld_uptodate(connector, |
5799 | G4X_AUD_CNTL_ST, eldv, | |
5800 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
5801 | G4X_HDMIW_HDMIEDID)) | |
5802 | return; | |
5803 | ||
e0dac65e WF |
5804 | i = I915_READ(G4X_AUD_CNTL_ST); |
5805 | i &= ~(eldv | G4X_ELD_ADDR); | |
5806 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
5807 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
5808 | ||
5809 | if (!eld[0]) | |
5810 | return; | |
5811 | ||
5812 | len = min_t(uint8_t, eld[2], len); | |
5813 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
5814 | for (i = 0; i < len; i++) | |
5815 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
5816 | ||
5817 | i = I915_READ(G4X_AUD_CNTL_ST); | |
5818 | i |= eldv; | |
5819 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
5820 | } | |
5821 | ||
83358c85 WX |
5822 | static void haswell_write_eld(struct drm_connector *connector, |
5823 | struct drm_crtc *crtc) | |
5824 | { | |
5825 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5826 | uint8_t *eld = connector->eld; | |
5827 | struct drm_device *dev = crtc->dev; | |
7b9f35a6 | 5828 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83358c85 WX |
5829 | uint32_t eldv; |
5830 | uint32_t i; | |
5831 | int len; | |
5832 | int pipe = to_intel_crtc(crtc)->pipe; | |
5833 | int tmp; | |
5834 | ||
5835 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
5836 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
5837 | int aud_config = HSW_AUD_CFG(pipe); | |
5838 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
5839 | ||
5840 | ||
5841 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); | |
5842 | ||
5843 | /* Audio output enable */ | |
5844 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
5845 | tmp = I915_READ(aud_cntrl_st2); | |
5846 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
5847 | I915_WRITE(aud_cntrl_st2, tmp); | |
5848 | ||
5849 | /* Wait for 1 vertical blank */ | |
5850 | intel_wait_for_vblank(dev, pipe); | |
5851 | ||
5852 | /* Set ELD valid state */ | |
5853 | tmp = I915_READ(aud_cntrl_st2); | |
5854 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp); | |
5855 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); | |
5856 | I915_WRITE(aud_cntrl_st2, tmp); | |
5857 | tmp = I915_READ(aud_cntrl_st2); | |
5858 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp); | |
5859 | ||
5860 | /* Enable HDMI mode */ | |
5861 | tmp = I915_READ(aud_config); | |
5862 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp); | |
5863 | /* clear N_programing_enable and N_value_index */ | |
5864 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
5865 | I915_WRITE(aud_config, tmp); | |
5866 | ||
5867 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
5868 | ||
5869 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7b9f35a6 | 5870 | intel_crtc->eld_vld = true; |
83358c85 WX |
5871 | |
5872 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
5873 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
5874 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
5875 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
5876 | } else | |
5877 | I915_WRITE(aud_config, 0); | |
5878 | ||
5879 | if (intel_eld_uptodate(connector, | |
5880 | aud_cntrl_st2, eldv, | |
5881 | aud_cntl_st, IBX_ELD_ADDRESS, | |
5882 | hdmiw_hdmiedid)) | |
5883 | return; | |
5884 | ||
5885 | i = I915_READ(aud_cntrl_st2); | |
5886 | i &= ~eldv; | |
5887 | I915_WRITE(aud_cntrl_st2, i); | |
5888 | ||
5889 | if (!eld[0]) | |
5890 | return; | |
5891 | ||
5892 | i = I915_READ(aud_cntl_st); | |
5893 | i &= ~IBX_ELD_ADDRESS; | |
5894 | I915_WRITE(aud_cntl_st, i); | |
5895 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
5896 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
5897 | ||
5898 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
5899 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
5900 | for (i = 0; i < len; i++) | |
5901 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
5902 | ||
5903 | i = I915_READ(aud_cntrl_st2); | |
5904 | i |= eldv; | |
5905 | I915_WRITE(aud_cntrl_st2, i); | |
5906 | ||
5907 | } | |
5908 | ||
e0dac65e WF |
5909 | static void ironlake_write_eld(struct drm_connector *connector, |
5910 | struct drm_crtc *crtc) | |
5911 | { | |
5912 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
5913 | uint8_t *eld = connector->eld; | |
5914 | uint32_t eldv; | |
5915 | uint32_t i; | |
5916 | int len; | |
5917 | int hdmiw_hdmiedid; | |
b6daa025 | 5918 | int aud_config; |
e0dac65e WF |
5919 | int aud_cntl_st; |
5920 | int aud_cntrl_st2; | |
9b138a83 | 5921 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 5922 | |
b3f33cbf | 5923 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
5924 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
5925 | aud_config = IBX_AUD_CFG(pipe); | |
5926 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 5927 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
e0dac65e | 5928 | } else { |
9b138a83 WX |
5929 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
5930 | aud_config = CPT_AUD_CFG(pipe); | |
5931 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 5932 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
5933 | } |
5934 | ||
9b138a83 | 5935 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e WF |
5936 | |
5937 | i = I915_READ(aud_cntl_st); | |
9b138a83 | 5938 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
e0dac65e WF |
5939 | if (!i) { |
5940 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
5941 | /* operate blindly on all ports */ | |
1202b4c6 WF |
5942 | eldv = IBX_ELD_VALIDB; |
5943 | eldv |= IBX_ELD_VALIDB << 4; | |
5944 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e WF |
5945 | } else { |
5946 | DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); | |
1202b4c6 | 5947 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
5948 | } |
5949 | ||
3a9627f4 WF |
5950 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
5951 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
5952 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 WF |
5953 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
5954 | } else | |
5955 | I915_WRITE(aud_config, 0); | |
e0dac65e | 5956 | |
3a9627f4 WF |
5957 | if (intel_eld_uptodate(connector, |
5958 | aud_cntrl_st2, eldv, | |
5959 | aud_cntl_st, IBX_ELD_ADDRESS, | |
5960 | hdmiw_hdmiedid)) | |
5961 | return; | |
5962 | ||
e0dac65e WF |
5963 | i = I915_READ(aud_cntrl_st2); |
5964 | i &= ~eldv; | |
5965 | I915_WRITE(aud_cntrl_st2, i); | |
5966 | ||
5967 | if (!eld[0]) | |
5968 | return; | |
5969 | ||
e0dac65e | 5970 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 5971 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
5972 | I915_WRITE(aud_cntl_st, i); |
5973 | ||
5974 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
5975 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
5976 | for (i = 0; i < len; i++) | |
5977 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
5978 | ||
5979 | i = I915_READ(aud_cntrl_st2); | |
5980 | i |= eldv; | |
5981 | I915_WRITE(aud_cntrl_st2, i); | |
5982 | } | |
5983 | ||
5984 | void intel_write_eld(struct drm_encoder *encoder, | |
5985 | struct drm_display_mode *mode) | |
5986 | { | |
5987 | struct drm_crtc *crtc = encoder->crtc; | |
5988 | struct drm_connector *connector; | |
5989 | struct drm_device *dev = encoder->dev; | |
5990 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5991 | ||
5992 | connector = drm_select_eld(encoder, mode); | |
5993 | if (!connector) | |
5994 | return; | |
5995 | ||
5996 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
5997 | connector->base.id, | |
5998 | drm_get_connector_name(connector), | |
5999 | connector->encoder->base.id, | |
6000 | drm_get_encoder_name(connector->encoder)); | |
6001 | ||
6002 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
6003 | ||
6004 | if (dev_priv->display.write_eld) | |
6005 | dev_priv->display.write_eld(connector, crtc); | |
6006 | } | |
6007 | ||
79e53945 JB |
6008 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
6009 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
6010 | { | |
6011 | struct drm_device *dev = crtc->dev; | |
6012 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6013 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9db4a9c7 | 6014 | int palreg = PALETTE(intel_crtc->pipe); |
79e53945 JB |
6015 | int i; |
6016 | ||
6017 | /* The clocks have to be on to load the palette. */ | |
aed3f09d | 6018 | if (!crtc->enabled || !intel_crtc->active) |
79e53945 JB |
6019 | return; |
6020 | ||
f2b115e6 | 6021 | /* use legacy palette for Ironlake */ |
bad720ff | 6022 | if (HAS_PCH_SPLIT(dev)) |
9db4a9c7 | 6023 | palreg = LGC_PALETTE(intel_crtc->pipe); |
2c07245f | 6024 | |
79e53945 JB |
6025 | for (i = 0; i < 256; i++) { |
6026 | I915_WRITE(palreg + 4 * i, | |
6027 | (intel_crtc->lut_r[i] << 16) | | |
6028 | (intel_crtc->lut_g[i] << 8) | | |
6029 | intel_crtc->lut_b[i]); | |
6030 | } | |
6031 | } | |
6032 | ||
560b85bb CW |
6033 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
6034 | { | |
6035 | struct drm_device *dev = crtc->dev; | |
6036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6037 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6038 | bool visible = base != 0; | |
6039 | u32 cntl; | |
6040 | ||
6041 | if (intel_crtc->cursor_visible == visible) | |
6042 | return; | |
6043 | ||
9db4a9c7 | 6044 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
6045 | if (visible) { |
6046 | /* On these chipsets we can only modify the base whilst | |
6047 | * the cursor is disabled. | |
6048 | */ | |
9db4a9c7 | 6049 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
6050 | |
6051 | cntl &= ~(CURSOR_FORMAT_MASK); | |
6052 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
6053 | cntl |= CURSOR_ENABLE | | |
6054 | CURSOR_GAMMA_ENABLE | | |
6055 | CURSOR_FORMAT_ARGB; | |
6056 | } else | |
6057 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 6058 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
6059 | |
6060 | intel_crtc->cursor_visible = visible; | |
6061 | } | |
6062 | ||
6063 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
6064 | { | |
6065 | struct drm_device *dev = crtc->dev; | |
6066 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6067 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6068 | int pipe = intel_crtc->pipe; | |
6069 | bool visible = base != 0; | |
6070 | ||
6071 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 6072 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
6073 | if (base) { |
6074 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
6075 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6076 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
6077 | } else { | |
6078 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6079 | cntl |= CURSOR_MODE_DISABLE; | |
6080 | } | |
9db4a9c7 | 6081 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
6082 | |
6083 | intel_crtc->cursor_visible = visible; | |
6084 | } | |
6085 | /* and commit changes on next vblank */ | |
9db4a9c7 | 6086 | I915_WRITE(CURBASE(pipe), base); |
560b85bb CW |
6087 | } |
6088 | ||
65a21cd6 JB |
6089 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
6090 | { | |
6091 | struct drm_device *dev = crtc->dev; | |
6092 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6093 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6094 | int pipe = intel_crtc->pipe; | |
6095 | bool visible = base != 0; | |
6096 | ||
6097 | if (intel_crtc->cursor_visible != visible) { | |
6098 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
6099 | if (base) { | |
6100 | cntl &= ~CURSOR_MODE; | |
6101 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6102 | } else { | |
6103 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6104 | cntl |= CURSOR_MODE_DISABLE; | |
6105 | } | |
6106 | I915_WRITE(CURCNTR_IVB(pipe), cntl); | |
6107 | ||
6108 | intel_crtc->cursor_visible = visible; | |
6109 | } | |
6110 | /* and commit changes on next vblank */ | |
6111 | I915_WRITE(CURBASE_IVB(pipe), base); | |
6112 | } | |
6113 | ||
cda4b7d3 | 6114 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
6115 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
6116 | bool on) | |
cda4b7d3 CW |
6117 | { |
6118 | struct drm_device *dev = crtc->dev; | |
6119 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6120 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6121 | int pipe = intel_crtc->pipe; | |
6122 | int x = intel_crtc->cursor_x; | |
6123 | int y = intel_crtc->cursor_y; | |
560b85bb | 6124 | u32 base, pos; |
cda4b7d3 CW |
6125 | bool visible; |
6126 | ||
6127 | pos = 0; | |
6128 | ||
6b383a7f | 6129 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
6130 | base = intel_crtc->cursor_addr; |
6131 | if (x > (int) crtc->fb->width) | |
6132 | base = 0; | |
6133 | ||
6134 | if (y > (int) crtc->fb->height) | |
6135 | base = 0; | |
6136 | } else | |
6137 | base = 0; | |
6138 | ||
6139 | if (x < 0) { | |
6140 | if (x + intel_crtc->cursor_width < 0) | |
6141 | base = 0; | |
6142 | ||
6143 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
6144 | x = -x; | |
6145 | } | |
6146 | pos |= x << CURSOR_X_SHIFT; | |
6147 | ||
6148 | if (y < 0) { | |
6149 | if (y + intel_crtc->cursor_height < 0) | |
6150 | base = 0; | |
6151 | ||
6152 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
6153 | y = -y; | |
6154 | } | |
6155 | pos |= y << CURSOR_Y_SHIFT; | |
6156 | ||
6157 | visible = base != 0; | |
560b85bb | 6158 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
6159 | return; |
6160 | ||
0cd83aa9 | 6161 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
65a21cd6 JB |
6162 | I915_WRITE(CURPOS_IVB(pipe), pos); |
6163 | ivb_update_cursor(crtc, base); | |
6164 | } else { | |
6165 | I915_WRITE(CURPOS(pipe), pos); | |
6166 | if (IS_845G(dev) || IS_I865G(dev)) | |
6167 | i845_update_cursor(crtc, base); | |
6168 | else | |
6169 | i9xx_update_cursor(crtc, base); | |
6170 | } | |
cda4b7d3 CW |
6171 | } |
6172 | ||
79e53945 | 6173 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 6174 | struct drm_file *file, |
79e53945 JB |
6175 | uint32_t handle, |
6176 | uint32_t width, uint32_t height) | |
6177 | { | |
6178 | struct drm_device *dev = crtc->dev; | |
6179 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6180 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 6181 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 6182 | uint32_t addr; |
3f8bc370 | 6183 | int ret; |
79e53945 | 6184 | |
79e53945 JB |
6185 | /* if we want to turn off the cursor ignore width and height */ |
6186 | if (!handle) { | |
28c97730 | 6187 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 6188 | addr = 0; |
05394f39 | 6189 | obj = NULL; |
5004417d | 6190 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 6191 | goto finish; |
79e53945 JB |
6192 | } |
6193 | ||
6194 | /* Currently we only support 64x64 cursors */ | |
6195 | if (width != 64 || height != 64) { | |
6196 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
6197 | return -EINVAL; | |
6198 | } | |
6199 | ||
05394f39 | 6200 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 6201 | if (&obj->base == NULL) |
79e53945 JB |
6202 | return -ENOENT; |
6203 | ||
05394f39 | 6204 | if (obj->base.size < width * height * 4) { |
79e53945 | 6205 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
6206 | ret = -ENOMEM; |
6207 | goto fail; | |
79e53945 JB |
6208 | } |
6209 | ||
71acb5eb | 6210 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 6211 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 6212 | if (!dev_priv->info->cursor_needs_physical) { |
d9e86c0e CW |
6213 | if (obj->tiling_mode) { |
6214 | DRM_ERROR("cursor cannot be tiled\n"); | |
6215 | ret = -EINVAL; | |
6216 | goto fail_locked; | |
6217 | } | |
6218 | ||
2da3b9b9 | 6219 | ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); |
e7b526bb CW |
6220 | if (ret) { |
6221 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 6222 | goto fail_locked; |
e7b526bb CW |
6223 | } |
6224 | ||
d9e86c0e CW |
6225 | ret = i915_gem_object_put_fence(obj); |
6226 | if (ret) { | |
2da3b9b9 | 6227 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
6228 | goto fail_unpin; |
6229 | } | |
6230 | ||
05394f39 | 6231 | addr = obj->gtt_offset; |
71acb5eb | 6232 | } else { |
6eeefaf3 | 6233 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 6234 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
6235 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
6236 | align); | |
71acb5eb DA |
6237 | if (ret) { |
6238 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 6239 | goto fail_locked; |
71acb5eb | 6240 | } |
05394f39 | 6241 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
6242 | } |
6243 | ||
a6c45cf0 | 6244 | if (IS_GEN2(dev)) |
14b60391 JB |
6245 | I915_WRITE(CURSIZE, (height << 12) | width); |
6246 | ||
3f8bc370 | 6247 | finish: |
3f8bc370 | 6248 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 6249 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 6250 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
6251 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
6252 | } else | |
6253 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
05394f39 | 6254 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 6255 | } |
80824003 | 6256 | |
7f9872e0 | 6257 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
6258 | |
6259 | intel_crtc->cursor_addr = addr; | |
05394f39 | 6260 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
6261 | intel_crtc->cursor_width = width; |
6262 | intel_crtc->cursor_height = height; | |
6263 | ||
6b383a7f | 6264 | intel_crtc_update_cursor(crtc, true); |
3f8bc370 | 6265 | |
79e53945 | 6266 | return 0; |
e7b526bb | 6267 | fail_unpin: |
05394f39 | 6268 | i915_gem_object_unpin(obj); |
7f9872e0 | 6269 | fail_locked: |
34b8686e | 6270 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 6271 | fail: |
05394f39 | 6272 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 6273 | return ret; |
79e53945 JB |
6274 | } |
6275 | ||
6276 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
6277 | { | |
79e53945 | 6278 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6279 | |
cda4b7d3 CW |
6280 | intel_crtc->cursor_x = x; |
6281 | intel_crtc->cursor_y = y; | |
652c393a | 6282 | |
6b383a7f | 6283 | intel_crtc_update_cursor(crtc, true); |
79e53945 JB |
6284 | |
6285 | return 0; | |
6286 | } | |
6287 | ||
6288 | /** Sets the color ramps on behalf of RandR */ | |
6289 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
6290 | u16 blue, int regno) | |
6291 | { | |
6292 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6293 | ||
6294 | intel_crtc->lut_r[regno] = red >> 8; | |
6295 | intel_crtc->lut_g[regno] = green >> 8; | |
6296 | intel_crtc->lut_b[regno] = blue >> 8; | |
6297 | } | |
6298 | ||
b8c00ac5 DA |
6299 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
6300 | u16 *blue, int regno) | |
6301 | { | |
6302 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6303 | ||
6304 | *red = intel_crtc->lut_r[regno] << 8; | |
6305 | *green = intel_crtc->lut_g[regno] << 8; | |
6306 | *blue = intel_crtc->lut_b[regno] << 8; | |
6307 | } | |
6308 | ||
79e53945 | 6309 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 6310 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 6311 | { |
7203425a | 6312 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 6313 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6314 | |
7203425a | 6315 | for (i = start; i < end; i++) { |
79e53945 JB |
6316 | intel_crtc->lut_r[i] = red[i] >> 8; |
6317 | intel_crtc->lut_g[i] = green[i] >> 8; | |
6318 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
6319 | } | |
6320 | ||
6321 | intel_crtc_load_lut(crtc); | |
6322 | } | |
6323 | ||
6324 | /** | |
6325 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
6326 | * detection. | |
6327 | * | |
6328 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
c751ce4f | 6329 | * its requirements. The pipe will be connected to no other encoders. |
79e53945 | 6330 | * |
c751ce4f | 6331 | * Currently this code will only succeed if there is a pipe with no encoders |
79e53945 JB |
6332 | * configured for it. In the future, it could choose to temporarily disable |
6333 | * some outputs to free up a pipe for its use. | |
6334 | * | |
6335 | * \return crtc, or NULL if no pipes are available. | |
6336 | */ | |
6337 | ||
6338 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
6339 | static struct drm_display_mode load_detect_mode = { | |
6340 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
6341 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
6342 | }; | |
6343 | ||
d2dff872 CW |
6344 | static struct drm_framebuffer * |
6345 | intel_framebuffer_create(struct drm_device *dev, | |
308e5bcb | 6346 | struct drm_mode_fb_cmd2 *mode_cmd, |
d2dff872 CW |
6347 | struct drm_i915_gem_object *obj) |
6348 | { | |
6349 | struct intel_framebuffer *intel_fb; | |
6350 | int ret; | |
6351 | ||
6352 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
6353 | if (!intel_fb) { | |
6354 | drm_gem_object_unreference_unlocked(&obj->base); | |
6355 | return ERR_PTR(-ENOMEM); | |
6356 | } | |
6357 | ||
6358 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
6359 | if (ret) { | |
6360 | drm_gem_object_unreference_unlocked(&obj->base); | |
6361 | kfree(intel_fb); | |
6362 | return ERR_PTR(ret); | |
6363 | } | |
6364 | ||
6365 | return &intel_fb->base; | |
6366 | } | |
6367 | ||
6368 | static u32 | |
6369 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
6370 | { | |
6371 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
6372 | return ALIGN(pitch, 64); | |
6373 | } | |
6374 | ||
6375 | static u32 | |
6376 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
6377 | { | |
6378 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
6379 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
6380 | } | |
6381 | ||
6382 | static struct drm_framebuffer * | |
6383 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
6384 | struct drm_display_mode *mode, | |
6385 | int depth, int bpp) | |
6386 | { | |
6387 | struct drm_i915_gem_object *obj; | |
0fed39bd | 6388 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
6389 | |
6390 | obj = i915_gem_alloc_object(dev, | |
6391 | intel_framebuffer_size_for_mode(mode, bpp)); | |
6392 | if (obj == NULL) | |
6393 | return ERR_PTR(-ENOMEM); | |
6394 | ||
6395 | mode_cmd.width = mode->hdisplay; | |
6396 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
6397 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
6398 | bpp); | |
5ca0c34a | 6399 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
6400 | |
6401 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
6402 | } | |
6403 | ||
6404 | static struct drm_framebuffer * | |
6405 | mode_fits_in_fbdev(struct drm_device *dev, | |
6406 | struct drm_display_mode *mode) | |
6407 | { | |
6408 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6409 | struct drm_i915_gem_object *obj; | |
6410 | struct drm_framebuffer *fb; | |
6411 | ||
6412 | if (dev_priv->fbdev == NULL) | |
6413 | return NULL; | |
6414 | ||
6415 | obj = dev_priv->fbdev->ifb.obj; | |
6416 | if (obj == NULL) | |
6417 | return NULL; | |
6418 | ||
6419 | fb = &dev_priv->fbdev->ifb.base; | |
01f2c773 VS |
6420 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
6421 | fb->bits_per_pixel)) | |
d2dff872 CW |
6422 | return NULL; |
6423 | ||
01f2c773 | 6424 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
6425 | return NULL; |
6426 | ||
6427 | return fb; | |
6428 | } | |
6429 | ||
d2434ab7 | 6430 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 6431 | struct drm_display_mode *mode, |
8261b191 | 6432 | struct intel_load_detect_pipe *old) |
79e53945 JB |
6433 | { |
6434 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
6435 | struct intel_encoder *intel_encoder = |
6436 | intel_attached_encoder(connector); | |
79e53945 | 6437 | struct drm_crtc *possible_crtc; |
4ef69c7a | 6438 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
6439 | struct drm_crtc *crtc = NULL; |
6440 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 6441 | struct drm_framebuffer *fb; |
79e53945 JB |
6442 | int i = -1; |
6443 | ||
d2dff872 CW |
6444 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6445 | connector->base.id, drm_get_connector_name(connector), | |
6446 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6447 | ||
79e53945 JB |
6448 | /* |
6449 | * Algorithm gets a little messy: | |
7a5e4805 | 6450 | * |
79e53945 JB |
6451 | * - if the connector already has an assigned crtc, use it (but make |
6452 | * sure it's on first) | |
7a5e4805 | 6453 | * |
79e53945 JB |
6454 | * - try to find the first unused crtc that can drive this connector, |
6455 | * and use that if we find one | |
79e53945 JB |
6456 | */ |
6457 | ||
6458 | /* See if we already have a CRTC for this connector */ | |
6459 | if (encoder->crtc) { | |
6460 | crtc = encoder->crtc; | |
8261b191 | 6461 | |
7b24056b DV |
6462 | mutex_lock(&crtc->mutex); |
6463 | ||
24218aac | 6464 | old->dpms_mode = connector->dpms; |
8261b191 CW |
6465 | old->load_detect_temp = false; |
6466 | ||
6467 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
6468 | if (connector->dpms != DRM_MODE_DPMS_ON) |
6469 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 6470 | |
7173188d | 6471 | return true; |
79e53945 JB |
6472 | } |
6473 | ||
6474 | /* Find an unused one (if possible) */ | |
6475 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
6476 | i++; | |
6477 | if (!(encoder->possible_crtcs & (1 << i))) | |
6478 | continue; | |
6479 | if (!possible_crtc->enabled) { | |
6480 | crtc = possible_crtc; | |
6481 | break; | |
6482 | } | |
79e53945 JB |
6483 | } |
6484 | ||
6485 | /* | |
6486 | * If we didn't find an unused CRTC, don't use any. | |
6487 | */ | |
6488 | if (!crtc) { | |
7173188d CW |
6489 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
6490 | return false; | |
79e53945 JB |
6491 | } |
6492 | ||
7b24056b | 6493 | mutex_lock(&crtc->mutex); |
fc303101 DV |
6494 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
6495 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
6496 | |
6497 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 6498 | old->dpms_mode = connector->dpms; |
8261b191 | 6499 | old->load_detect_temp = true; |
d2dff872 | 6500 | old->release_fb = NULL; |
79e53945 | 6501 | |
6492711d CW |
6502 | if (!mode) |
6503 | mode = &load_detect_mode; | |
79e53945 | 6504 | |
d2dff872 CW |
6505 | /* We need a framebuffer large enough to accommodate all accesses |
6506 | * that the plane may generate whilst we perform load detection. | |
6507 | * We can not rely on the fbcon either being present (we get called | |
6508 | * during its initialisation to detect all boot displays, or it may | |
6509 | * not even exist) or that it is large enough to satisfy the | |
6510 | * requested mode. | |
6511 | */ | |
94352cf9 DV |
6512 | fb = mode_fits_in_fbdev(dev, mode); |
6513 | if (fb == NULL) { | |
d2dff872 | 6514 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
6515 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
6516 | old->release_fb = fb; | |
d2dff872 CW |
6517 | } else |
6518 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 6519 | if (IS_ERR(fb)) { |
d2dff872 | 6520 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
7b24056b | 6521 | mutex_unlock(&crtc->mutex); |
0e8b3d3e | 6522 | return false; |
79e53945 | 6523 | } |
79e53945 | 6524 | |
c0c36b94 | 6525 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 6526 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
6527 | if (old->release_fb) |
6528 | old->release_fb->funcs->destroy(old->release_fb); | |
7b24056b | 6529 | mutex_unlock(&crtc->mutex); |
0e8b3d3e | 6530 | return false; |
79e53945 | 6531 | } |
7173188d | 6532 | |
79e53945 | 6533 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 6534 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 6535 | return true; |
79e53945 JB |
6536 | } |
6537 | ||
d2434ab7 | 6538 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 6539 | struct intel_load_detect_pipe *old) |
79e53945 | 6540 | { |
d2434ab7 DV |
6541 | struct intel_encoder *intel_encoder = |
6542 | intel_attached_encoder(connector); | |
4ef69c7a | 6543 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 6544 | struct drm_crtc *crtc = encoder->crtc; |
79e53945 | 6545 | |
d2dff872 CW |
6546 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6547 | connector->base.id, drm_get_connector_name(connector), | |
6548 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6549 | ||
8261b191 | 6550 | if (old->load_detect_temp) { |
fc303101 DV |
6551 | to_intel_connector(connector)->new_encoder = NULL; |
6552 | intel_encoder->new_crtc = NULL; | |
6553 | intel_set_mode(crtc, NULL, 0, 0, NULL); | |
d2dff872 | 6554 | |
36206361 DV |
6555 | if (old->release_fb) { |
6556 | drm_framebuffer_unregister_private(old->release_fb); | |
6557 | drm_framebuffer_unreference(old->release_fb); | |
6558 | } | |
d2dff872 | 6559 | |
67c96400 | 6560 | mutex_unlock(&crtc->mutex); |
0622a53c | 6561 | return; |
79e53945 JB |
6562 | } |
6563 | ||
c751ce4f | 6564 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
6565 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
6566 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b DV |
6567 | |
6568 | mutex_unlock(&crtc->mutex); | |
79e53945 JB |
6569 | } |
6570 | ||
6571 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
6572 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
6573 | { | |
6574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6575 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6576 | int pipe = intel_crtc->pipe; | |
548f245b | 6577 | u32 dpll = I915_READ(DPLL(pipe)); |
79e53945 JB |
6578 | u32 fp; |
6579 | intel_clock_t clock; | |
6580 | ||
6581 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
39adb7a5 | 6582 | fp = I915_READ(FP0(pipe)); |
79e53945 | 6583 | else |
39adb7a5 | 6584 | fp = I915_READ(FP1(pipe)); |
79e53945 JB |
6585 | |
6586 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
6587 | if (IS_PINEVIEW(dev)) { |
6588 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
6589 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
6590 | } else { |
6591 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
6592 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
6593 | } | |
6594 | ||
a6c45cf0 | 6595 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
6596 | if (IS_PINEVIEW(dev)) |
6597 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
6598 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
6599 | else |
6600 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
6601 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
6602 | ||
6603 | switch (dpll & DPLL_MODE_MASK) { | |
6604 | case DPLLB_MODE_DAC_SERIAL: | |
6605 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
6606 | 5 : 10; | |
6607 | break; | |
6608 | case DPLLB_MODE_LVDS: | |
6609 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
6610 | 7 : 14; | |
6611 | break; | |
6612 | default: | |
28c97730 | 6613 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
6614 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
6615 | return 0; | |
6616 | } | |
6617 | ||
6618 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 6619 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
6620 | } else { |
6621 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
6622 | ||
6623 | if (is_lvds) { | |
6624 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
6625 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
6626 | clock.p2 = 14; | |
6627 | ||
6628 | if ((dpll & PLL_REF_INPUT_MASK) == | |
6629 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
6630 | /* XXX: might not be 66MHz */ | |
2177832f | 6631 | intel_clock(dev, 66000, &clock); |
79e53945 | 6632 | } else |
2177832f | 6633 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6634 | } else { |
6635 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
6636 | clock.p1 = 2; | |
6637 | else { | |
6638 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
6639 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
6640 | } | |
6641 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
6642 | clock.p2 = 4; | |
6643 | else | |
6644 | clock.p2 = 2; | |
6645 | ||
2177832f | 6646 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6647 | } |
6648 | } | |
6649 | ||
6650 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
6651 | * i830PllIsValid() because it relies on the xf86_config connector | |
6652 | * configuration being accurate, which it isn't necessarily. | |
6653 | */ | |
6654 | ||
6655 | return clock.dot; | |
6656 | } | |
6657 | ||
6658 | /** Returns the currently programmed mode of the given pipe. */ | |
6659 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
6660 | struct drm_crtc *crtc) | |
6661 | { | |
548f245b | 6662 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 6663 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
fe2b8f9d | 6664 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
79e53945 | 6665 | struct drm_display_mode *mode; |
fe2b8f9d PZ |
6666 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
6667 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
6668 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
6669 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
79e53945 JB |
6670 | |
6671 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
6672 | if (!mode) | |
6673 | return NULL; | |
6674 | ||
6675 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
6676 | mode->hdisplay = (htot & 0xffff) + 1; | |
6677 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
6678 | mode->hsync_start = (hsync & 0xffff) + 1; | |
6679 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
6680 | mode->vdisplay = (vtot & 0xffff) + 1; | |
6681 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
6682 | mode->vsync_start = (vsync & 0xffff) + 1; | |
6683 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
6684 | ||
6685 | drm_mode_set_name(mode); | |
79e53945 JB |
6686 | |
6687 | return mode; | |
6688 | } | |
6689 | ||
3dec0095 | 6690 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
6691 | { |
6692 | struct drm_device *dev = crtc->dev; | |
6693 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6694 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6695 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
6696 | int dpll_reg = DPLL(pipe); |
6697 | int dpll; | |
652c393a | 6698 | |
bad720ff | 6699 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
6700 | return; |
6701 | ||
6702 | if (!dev_priv->lvds_downclock_avail) | |
6703 | return; | |
6704 | ||
dbdc6479 | 6705 | dpll = I915_READ(dpll_reg); |
652c393a | 6706 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 6707 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 6708 | |
8ac5a6d5 | 6709 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
6710 | |
6711 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
6712 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 6713 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 6714 | |
652c393a JB |
6715 | dpll = I915_READ(dpll_reg); |
6716 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 6717 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 6718 | } |
652c393a JB |
6719 | } |
6720 | ||
6721 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
6722 | { | |
6723 | struct drm_device *dev = crtc->dev; | |
6724 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6725 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
652c393a | 6726 | |
bad720ff | 6727 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
6728 | return; |
6729 | ||
6730 | if (!dev_priv->lvds_downclock_avail) | |
6731 | return; | |
6732 | ||
6733 | /* | |
6734 | * Since this is called by a timer, we should never get here in | |
6735 | * the manual case. | |
6736 | */ | |
6737 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
6738 | int pipe = intel_crtc->pipe; |
6739 | int dpll_reg = DPLL(pipe); | |
6740 | int dpll; | |
f6e5b160 | 6741 | |
44d98a61 | 6742 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 6743 | |
8ac5a6d5 | 6744 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 6745 | |
dc257cf1 | 6746 | dpll = I915_READ(dpll_reg); |
652c393a JB |
6747 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
6748 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 6749 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
6750 | dpll = I915_READ(dpll_reg); |
6751 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 6752 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
6753 | } |
6754 | ||
6755 | } | |
6756 | ||
f047e395 CW |
6757 | void intel_mark_busy(struct drm_device *dev) |
6758 | { | |
f047e395 CW |
6759 | i915_update_gfx_val(dev->dev_private); |
6760 | } | |
6761 | ||
6762 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 6763 | { |
652c393a | 6764 | struct drm_crtc *crtc; |
652c393a JB |
6765 | |
6766 | if (!i915_powersave) | |
6767 | return; | |
6768 | ||
652c393a | 6769 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
652c393a JB |
6770 | if (!crtc->fb) |
6771 | continue; | |
6772 | ||
725a5b54 | 6773 | intel_decrease_pllclock(crtc); |
652c393a | 6774 | } |
652c393a JB |
6775 | } |
6776 | ||
725a5b54 | 6777 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj) |
652c393a | 6778 | { |
f047e395 CW |
6779 | struct drm_device *dev = obj->base.dev; |
6780 | struct drm_crtc *crtc; | |
652c393a | 6781 | |
f047e395 | 6782 | if (!i915_powersave) |
acb87dfb CW |
6783 | return; |
6784 | ||
652c393a JB |
6785 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6786 | if (!crtc->fb) | |
6787 | continue; | |
6788 | ||
f047e395 | 6789 | if (to_intel_framebuffer(crtc->fb)->obj == obj) |
725a5b54 | 6790 | intel_increase_pllclock(crtc); |
652c393a JB |
6791 | } |
6792 | } | |
6793 | ||
79e53945 JB |
6794 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
6795 | { | |
6796 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
6797 | struct drm_device *dev = crtc->dev; |
6798 | struct intel_unpin_work *work; | |
6799 | unsigned long flags; | |
6800 | ||
6801 | spin_lock_irqsave(&dev->event_lock, flags); | |
6802 | work = intel_crtc->unpin_work; | |
6803 | intel_crtc->unpin_work = NULL; | |
6804 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
6805 | ||
6806 | if (work) { | |
6807 | cancel_work_sync(&work->work); | |
6808 | kfree(work); | |
6809 | } | |
79e53945 JB |
6810 | |
6811 | drm_crtc_cleanup(crtc); | |
67e77c5a | 6812 | |
79e53945 JB |
6813 | kfree(intel_crtc); |
6814 | } | |
6815 | ||
6b95a207 KH |
6816 | static void intel_unpin_work_fn(struct work_struct *__work) |
6817 | { | |
6818 | struct intel_unpin_work *work = | |
6819 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 6820 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 6821 | |
b4a98e57 | 6822 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 6823 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
6824 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
6825 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 6826 | |
b4a98e57 CW |
6827 | intel_update_fbc(dev); |
6828 | mutex_unlock(&dev->struct_mutex); | |
6829 | ||
6830 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
6831 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
6832 | ||
6b95a207 KH |
6833 | kfree(work); |
6834 | } | |
6835 | ||
1afe3e9d | 6836 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 6837 | struct drm_crtc *crtc) |
6b95a207 KH |
6838 | { |
6839 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
6840 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6841 | struct intel_unpin_work *work; | |
05394f39 | 6842 | struct drm_i915_gem_object *obj; |
6b95a207 KH |
6843 | unsigned long flags; |
6844 | ||
6845 | /* Ignore early vblank irqs */ | |
6846 | if (intel_crtc == NULL) | |
6847 | return; | |
6848 | ||
6849 | spin_lock_irqsave(&dev->event_lock, flags); | |
6850 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
6851 | |
6852 | /* Ensure we don't miss a work->pending update ... */ | |
6853 | smp_rmb(); | |
6854 | ||
6855 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
6856 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6857 | return; | |
6858 | } | |
6859 | ||
e7d841ca CW |
6860 | /* and that the unpin work is consistent wrt ->pending. */ |
6861 | smp_rmb(); | |
6862 | ||
6b95a207 | 6863 | intel_crtc->unpin_work = NULL; |
6b95a207 | 6864 | |
45a066eb RC |
6865 | if (work->event) |
6866 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 6867 | |
0af7e4df MK |
6868 | drm_vblank_put(dev, intel_crtc->pipe); |
6869 | ||
6b95a207 KH |
6870 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6871 | ||
05394f39 | 6872 | obj = work->old_fb_obj; |
d9e86c0e | 6873 | |
2c10d571 | 6874 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
6875 | |
6876 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
6877 | |
6878 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
6879 | } |
6880 | ||
1afe3e9d JB |
6881 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
6882 | { | |
6883 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6884 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
6885 | ||
49b14a5c | 6886 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
6887 | } |
6888 | ||
6889 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
6890 | { | |
6891 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6892 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
6893 | ||
49b14a5c | 6894 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
6895 | } |
6896 | ||
6b95a207 KH |
6897 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
6898 | { | |
6899 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6900 | struct intel_crtc *intel_crtc = | |
6901 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
6902 | unsigned long flags; | |
6903 | ||
e7d841ca CW |
6904 | /* NB: An MMIO update of the plane base pointer will also |
6905 | * generate a page-flip completion irq, i.e. every modeset | |
6906 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
6907 | */ | |
6b95a207 | 6908 | spin_lock_irqsave(&dev->event_lock, flags); |
e7d841ca CW |
6909 | if (intel_crtc->unpin_work) |
6910 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); | |
6b95a207 KH |
6911 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6912 | } | |
6913 | ||
e7d841ca CW |
6914 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
6915 | { | |
6916 | /* Ensure that the work item is consistent when activating it ... */ | |
6917 | smp_wmb(); | |
6918 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
6919 | /* and that it is marked active as soon as the irq could fire. */ | |
6920 | smp_wmb(); | |
6921 | } | |
6922 | ||
8c9f3aaf JB |
6923 | static int intel_gen2_queue_flip(struct drm_device *dev, |
6924 | struct drm_crtc *crtc, | |
6925 | struct drm_framebuffer *fb, | |
6926 | struct drm_i915_gem_object *obj) | |
6927 | { | |
6928 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6929 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 6930 | u32 flip_mask; |
6d90c952 | 6931 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
6932 | int ret; |
6933 | ||
6d90c952 | 6934 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 6935 | if (ret) |
83d4092b | 6936 | goto err; |
8c9f3aaf | 6937 | |
6d90c952 | 6938 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 6939 | if (ret) |
83d4092b | 6940 | goto err_unpin; |
8c9f3aaf JB |
6941 | |
6942 | /* Can't queue multiple flips, so wait for the previous | |
6943 | * one to finish before executing the next. | |
6944 | */ | |
6945 | if (intel_crtc->plane) | |
6946 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
6947 | else | |
6948 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
6949 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
6950 | intel_ring_emit(ring, MI_NOOP); | |
6951 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
6952 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6953 | intel_ring_emit(ring, fb->pitches[0]); | |
e506a0c6 | 6954 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6d90c952 | 6955 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
6956 | |
6957 | intel_mark_page_flip_active(intel_crtc); | |
6d90c952 | 6958 | intel_ring_advance(ring); |
83d4092b CW |
6959 | return 0; |
6960 | ||
6961 | err_unpin: | |
6962 | intel_unpin_fb_obj(obj); | |
6963 | err: | |
8c9f3aaf JB |
6964 | return ret; |
6965 | } | |
6966 | ||
6967 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
6968 | struct drm_crtc *crtc, | |
6969 | struct drm_framebuffer *fb, | |
6970 | struct drm_i915_gem_object *obj) | |
6971 | { | |
6972 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6973 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 6974 | u32 flip_mask; |
6d90c952 | 6975 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
6976 | int ret; |
6977 | ||
6d90c952 | 6978 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 6979 | if (ret) |
83d4092b | 6980 | goto err; |
8c9f3aaf | 6981 | |
6d90c952 | 6982 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 6983 | if (ret) |
83d4092b | 6984 | goto err_unpin; |
8c9f3aaf JB |
6985 | |
6986 | if (intel_crtc->plane) | |
6987 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
6988 | else | |
6989 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
6990 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
6991 | intel_ring_emit(ring, MI_NOOP); | |
6992 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
6993 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
6994 | intel_ring_emit(ring, fb->pitches[0]); | |
e506a0c6 | 6995 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
6d90c952 DV |
6996 | intel_ring_emit(ring, MI_NOOP); |
6997 | ||
e7d841ca | 6998 | intel_mark_page_flip_active(intel_crtc); |
6d90c952 | 6999 | intel_ring_advance(ring); |
83d4092b CW |
7000 | return 0; |
7001 | ||
7002 | err_unpin: | |
7003 | intel_unpin_fb_obj(obj); | |
7004 | err: | |
8c9f3aaf JB |
7005 | return ret; |
7006 | } | |
7007 | ||
7008 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
7009 | struct drm_crtc *crtc, | |
7010 | struct drm_framebuffer *fb, | |
7011 | struct drm_i915_gem_object *obj) | |
7012 | { | |
7013 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7014 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7015 | uint32_t pf, pipesrc; | |
6d90c952 | 7016 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7017 | int ret; |
7018 | ||
6d90c952 | 7019 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7020 | if (ret) |
83d4092b | 7021 | goto err; |
8c9f3aaf | 7022 | |
6d90c952 | 7023 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 7024 | if (ret) |
83d4092b | 7025 | goto err_unpin; |
8c9f3aaf JB |
7026 | |
7027 | /* i965+ uses the linear or tiled offsets from the | |
7028 | * Display Registers (which do not change across a page-flip) | |
7029 | * so we need only reprogram the base address. | |
7030 | */ | |
6d90c952 DV |
7031 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7032 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7033 | intel_ring_emit(ring, fb->pitches[0]); | |
c2c75131 DV |
7034 | intel_ring_emit(ring, |
7035 | (obj->gtt_offset + intel_crtc->dspaddr_offset) | | |
7036 | obj->tiling_mode); | |
8c9f3aaf JB |
7037 | |
7038 | /* XXX Enabling the panel-fitter across page-flip is so far | |
7039 | * untested on non-native modes, so ignore it for now. | |
7040 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
7041 | */ | |
7042 | pf = 0; | |
7043 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 7044 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
7045 | |
7046 | intel_mark_page_flip_active(intel_crtc); | |
6d90c952 | 7047 | intel_ring_advance(ring); |
83d4092b CW |
7048 | return 0; |
7049 | ||
7050 | err_unpin: | |
7051 | intel_unpin_fb_obj(obj); | |
7052 | err: | |
8c9f3aaf JB |
7053 | return ret; |
7054 | } | |
7055 | ||
7056 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
7057 | struct drm_crtc *crtc, | |
7058 | struct drm_framebuffer *fb, | |
7059 | struct drm_i915_gem_object *obj) | |
7060 | { | |
7061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7062 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6d90c952 | 7063 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7064 | uint32_t pf, pipesrc; |
7065 | int ret; | |
7066 | ||
6d90c952 | 7067 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7068 | if (ret) |
83d4092b | 7069 | goto err; |
8c9f3aaf | 7070 | |
6d90c952 | 7071 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 7072 | if (ret) |
83d4092b | 7073 | goto err_unpin; |
8c9f3aaf | 7074 | |
6d90c952 DV |
7075 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7076 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7077 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
c2c75131 | 7078 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
8c9f3aaf | 7079 | |
dc257cf1 DV |
7080 | /* Contrary to the suggestions in the documentation, |
7081 | * "Enable Panel Fitter" does not seem to be required when page | |
7082 | * flipping with a non-native mode, and worse causes a normal | |
7083 | * modeset to fail. | |
7084 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
7085 | */ | |
7086 | pf = 0; | |
8c9f3aaf | 7087 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 7088 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
7089 | |
7090 | intel_mark_page_flip_active(intel_crtc); | |
6d90c952 | 7091 | intel_ring_advance(ring); |
83d4092b CW |
7092 | return 0; |
7093 | ||
7094 | err_unpin: | |
7095 | intel_unpin_fb_obj(obj); | |
7096 | err: | |
8c9f3aaf JB |
7097 | return ret; |
7098 | } | |
7099 | ||
7c9017e5 JB |
7100 | /* |
7101 | * On gen7 we currently use the blit ring because (in early silicon at least) | |
7102 | * the render ring doesn't give us interrpts for page flip completion, which | |
7103 | * means clients will hang after the first flip is queued. Fortunately the | |
7104 | * blit ring generates interrupts properly, so use it instead. | |
7105 | */ | |
7106 | static int intel_gen7_queue_flip(struct drm_device *dev, | |
7107 | struct drm_crtc *crtc, | |
7108 | struct drm_framebuffer *fb, | |
7109 | struct drm_i915_gem_object *obj) | |
7110 | { | |
7111 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7112 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7113 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; | |
cb05d8de | 7114 | uint32_t plane_bit = 0; |
7c9017e5 JB |
7115 | int ret; |
7116 | ||
7117 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
7118 | if (ret) | |
83d4092b | 7119 | goto err; |
7c9017e5 | 7120 | |
cb05d8de DV |
7121 | switch(intel_crtc->plane) { |
7122 | case PLANE_A: | |
7123 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
7124 | break; | |
7125 | case PLANE_B: | |
7126 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
7127 | break; | |
7128 | case PLANE_C: | |
7129 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
7130 | break; | |
7131 | default: | |
7132 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
7133 | ret = -ENODEV; | |
ab3951eb | 7134 | goto err_unpin; |
cb05d8de DV |
7135 | } |
7136 | ||
7c9017e5 JB |
7137 | ret = intel_ring_begin(ring, 4); |
7138 | if (ret) | |
83d4092b | 7139 | goto err_unpin; |
7c9017e5 | 7140 | |
cb05d8de | 7141 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 7142 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
c2c75131 | 7143 | intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); |
7c9017e5 | 7144 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
7145 | |
7146 | intel_mark_page_flip_active(intel_crtc); | |
7c9017e5 | 7147 | intel_ring_advance(ring); |
83d4092b CW |
7148 | return 0; |
7149 | ||
7150 | err_unpin: | |
7151 | intel_unpin_fb_obj(obj); | |
7152 | err: | |
7c9017e5 JB |
7153 | return ret; |
7154 | } | |
7155 | ||
8c9f3aaf JB |
7156 | static int intel_default_queue_flip(struct drm_device *dev, |
7157 | struct drm_crtc *crtc, | |
7158 | struct drm_framebuffer *fb, | |
7159 | struct drm_i915_gem_object *obj) | |
7160 | { | |
7161 | return -ENODEV; | |
7162 | } | |
7163 | ||
6b95a207 KH |
7164 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
7165 | struct drm_framebuffer *fb, | |
7166 | struct drm_pending_vblank_event *event) | |
7167 | { | |
7168 | struct drm_device *dev = crtc->dev; | |
7169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7170 | struct intel_framebuffer *intel_fb; | |
05394f39 | 7171 | struct drm_i915_gem_object *obj; |
6b95a207 KH |
7172 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7173 | struct intel_unpin_work *work; | |
8c9f3aaf | 7174 | unsigned long flags; |
52e68630 | 7175 | int ret; |
6b95a207 | 7176 | |
e6a595d2 VS |
7177 | /* Can't change pixel format via MI display flips. */ |
7178 | if (fb->pixel_format != crtc->fb->pixel_format) | |
7179 | return -EINVAL; | |
7180 | ||
7181 | /* | |
7182 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
7183 | * Note that pitch changes could also affect these register. | |
7184 | */ | |
7185 | if (INTEL_INFO(dev)->gen > 3 && | |
7186 | (fb->offsets[0] != crtc->fb->offsets[0] || | |
7187 | fb->pitches[0] != crtc->fb->pitches[0])) | |
7188 | return -EINVAL; | |
7189 | ||
6b95a207 KH |
7190 | work = kzalloc(sizeof *work, GFP_KERNEL); |
7191 | if (work == NULL) | |
7192 | return -ENOMEM; | |
7193 | ||
6b95a207 | 7194 | work->event = event; |
b4a98e57 | 7195 | work->crtc = crtc; |
6b95a207 | 7196 | intel_fb = to_intel_framebuffer(crtc->fb); |
b1b87f6b | 7197 | work->old_fb_obj = intel_fb->obj; |
6b95a207 KH |
7198 | INIT_WORK(&work->work, intel_unpin_work_fn); |
7199 | ||
7317c75e JB |
7200 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
7201 | if (ret) | |
7202 | goto free_work; | |
7203 | ||
6b95a207 KH |
7204 | /* We borrow the event spin lock for protecting unpin_work */ |
7205 | spin_lock_irqsave(&dev->event_lock, flags); | |
7206 | if (intel_crtc->unpin_work) { | |
7207 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7208 | kfree(work); | |
7317c75e | 7209 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
7210 | |
7211 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
7212 | return -EBUSY; |
7213 | } | |
7214 | intel_crtc->unpin_work = work; | |
7215 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7216 | ||
7217 | intel_fb = to_intel_framebuffer(fb); | |
7218 | obj = intel_fb->obj; | |
7219 | ||
b4a98e57 CW |
7220 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
7221 | flush_workqueue(dev_priv->wq); | |
7222 | ||
79158103 CW |
7223 | ret = i915_mutex_lock_interruptible(dev); |
7224 | if (ret) | |
7225 | goto cleanup; | |
6b95a207 | 7226 | |
75dfca80 | 7227 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
7228 | drm_gem_object_reference(&work->old_fb_obj->base); |
7229 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
7230 | |
7231 | crtc->fb = fb; | |
96b099fd | 7232 | |
e1f99ce6 | 7233 | work->pending_flip_obj = obj; |
e1f99ce6 | 7234 | |
4e5359cd SF |
7235 | work->enable_stall_check = true; |
7236 | ||
b4a98e57 | 7237 | atomic_inc(&intel_crtc->unpin_work_count); |
e1f99ce6 | 7238 | |
8c9f3aaf JB |
7239 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); |
7240 | if (ret) | |
7241 | goto cleanup_pending; | |
6b95a207 | 7242 | |
7782de3b | 7243 | intel_disable_fbc(dev); |
f047e395 | 7244 | intel_mark_fb_busy(obj); |
6b95a207 KH |
7245 | mutex_unlock(&dev->struct_mutex); |
7246 | ||
e5510fac JB |
7247 | trace_i915_flip_request(intel_crtc->plane, obj); |
7248 | ||
6b95a207 | 7249 | return 0; |
96b099fd | 7250 | |
8c9f3aaf | 7251 | cleanup_pending: |
b4a98e57 | 7252 | atomic_dec(&intel_crtc->unpin_work_count); |
05394f39 CW |
7253 | drm_gem_object_unreference(&work->old_fb_obj->base); |
7254 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
7255 | mutex_unlock(&dev->struct_mutex); |
7256 | ||
79158103 | 7257 | cleanup: |
96b099fd CW |
7258 | spin_lock_irqsave(&dev->event_lock, flags); |
7259 | intel_crtc->unpin_work = NULL; | |
7260 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7261 | ||
7317c75e JB |
7262 | drm_vblank_put(dev, intel_crtc->pipe); |
7263 | free_work: | |
96b099fd CW |
7264 | kfree(work); |
7265 | ||
7266 | return ret; | |
6b95a207 KH |
7267 | } |
7268 | ||
f6e5b160 | 7269 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
7270 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
7271 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
7272 | }; |
7273 | ||
6ed0f796 | 7274 | bool intel_encoder_check_is_cloned(struct intel_encoder *encoder) |
47f1c6c9 | 7275 | { |
6ed0f796 DV |
7276 | struct intel_encoder *other_encoder; |
7277 | struct drm_crtc *crtc = &encoder->new_crtc->base; | |
47f1c6c9 | 7278 | |
6ed0f796 DV |
7279 | if (WARN_ON(!crtc)) |
7280 | return false; | |
7281 | ||
7282 | list_for_each_entry(other_encoder, | |
7283 | &crtc->dev->mode_config.encoder_list, | |
7284 | base.head) { | |
7285 | ||
7286 | if (&other_encoder->new_crtc->base != crtc || | |
7287 | encoder == other_encoder) | |
7288 | continue; | |
7289 | else | |
7290 | return true; | |
f47166d2 CW |
7291 | } |
7292 | ||
6ed0f796 DV |
7293 | return false; |
7294 | } | |
47f1c6c9 | 7295 | |
50f56119 DV |
7296 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
7297 | struct drm_crtc *crtc) | |
7298 | { | |
7299 | struct drm_device *dev; | |
7300 | struct drm_crtc *tmp; | |
7301 | int crtc_mask = 1; | |
47f1c6c9 | 7302 | |
50f56119 | 7303 | WARN(!crtc, "checking null crtc?\n"); |
47f1c6c9 | 7304 | |
50f56119 | 7305 | dev = crtc->dev; |
47f1c6c9 | 7306 | |
50f56119 DV |
7307 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { |
7308 | if (tmp == crtc) | |
7309 | break; | |
7310 | crtc_mask <<= 1; | |
7311 | } | |
47f1c6c9 | 7312 | |
50f56119 DV |
7313 | if (encoder->possible_crtcs & crtc_mask) |
7314 | return true; | |
7315 | return false; | |
47f1c6c9 | 7316 | } |
79e53945 | 7317 | |
9a935856 DV |
7318 | /** |
7319 | * intel_modeset_update_staged_output_state | |
7320 | * | |
7321 | * Updates the staged output configuration state, e.g. after we've read out the | |
7322 | * current hw state. | |
7323 | */ | |
7324 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 7325 | { |
9a935856 DV |
7326 | struct intel_encoder *encoder; |
7327 | struct intel_connector *connector; | |
f6e5b160 | 7328 | |
9a935856 DV |
7329 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7330 | base.head) { | |
7331 | connector->new_encoder = | |
7332 | to_intel_encoder(connector->base.encoder); | |
7333 | } | |
f6e5b160 | 7334 | |
9a935856 DV |
7335 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7336 | base.head) { | |
7337 | encoder->new_crtc = | |
7338 | to_intel_crtc(encoder->base.crtc); | |
7339 | } | |
f6e5b160 CW |
7340 | } |
7341 | ||
9a935856 DV |
7342 | /** |
7343 | * intel_modeset_commit_output_state | |
7344 | * | |
7345 | * This function copies the stage display pipe configuration to the real one. | |
7346 | */ | |
7347 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
7348 | { | |
7349 | struct intel_encoder *encoder; | |
7350 | struct intel_connector *connector; | |
f6e5b160 | 7351 | |
9a935856 DV |
7352 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7353 | base.head) { | |
7354 | connector->base.encoder = &connector->new_encoder->base; | |
7355 | } | |
f6e5b160 | 7356 | |
9a935856 DV |
7357 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7358 | base.head) { | |
7359 | encoder->base.crtc = &encoder->new_crtc->base; | |
7360 | } | |
7361 | } | |
7362 | ||
7758a113 DV |
7363 | static struct drm_display_mode * |
7364 | intel_modeset_adjusted_mode(struct drm_crtc *crtc, | |
7365 | struct drm_display_mode *mode) | |
ee7b9f93 | 7366 | { |
7758a113 DV |
7367 | struct drm_device *dev = crtc->dev; |
7368 | struct drm_display_mode *adjusted_mode; | |
7369 | struct drm_encoder_helper_funcs *encoder_funcs; | |
7370 | struct intel_encoder *encoder; | |
ee7b9f93 | 7371 | |
7758a113 DV |
7372 | adjusted_mode = drm_mode_duplicate(dev, mode); |
7373 | if (!adjusted_mode) | |
7374 | return ERR_PTR(-ENOMEM); | |
7375 | ||
7376 | /* Pass our mode to the connectors and the CRTC to give them a chance to | |
7377 | * adjust it according to limitations or connector properties, and also | |
7378 | * a chance to reject the mode entirely. | |
47f1c6c9 | 7379 | */ |
7758a113 DV |
7380 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7381 | base.head) { | |
47f1c6c9 | 7382 | |
7758a113 DV |
7383 | if (&encoder->new_crtc->base != crtc) |
7384 | continue; | |
7385 | encoder_funcs = encoder->base.helper_private; | |
7386 | if (!(encoder_funcs->mode_fixup(&encoder->base, mode, | |
7387 | adjusted_mode))) { | |
7388 | DRM_DEBUG_KMS("Encoder fixup failed\n"); | |
7389 | goto fail; | |
7390 | } | |
ee7b9f93 | 7391 | } |
47f1c6c9 | 7392 | |
7758a113 DV |
7393 | if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) { |
7394 | DRM_DEBUG_KMS("CRTC fixup failed\n"); | |
7395 | goto fail; | |
ee7b9f93 | 7396 | } |
7758a113 | 7397 | DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id); |
47f1c6c9 | 7398 | |
7758a113 DV |
7399 | return adjusted_mode; |
7400 | fail: | |
7401 | drm_mode_destroy(dev, adjusted_mode); | |
7402 | return ERR_PTR(-EINVAL); | |
ee7b9f93 | 7403 | } |
47f1c6c9 | 7404 | |
e2e1ed41 DV |
7405 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
7406 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
7407 | static void | |
7408 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
7409 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
7410 | { |
7411 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
7412 | struct drm_device *dev = crtc->dev; |
7413 | struct intel_encoder *encoder; | |
7414 | struct intel_connector *connector; | |
7415 | struct drm_crtc *tmp_crtc; | |
79e53945 | 7416 | |
e2e1ed41 | 7417 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 7418 | |
e2e1ed41 DV |
7419 | /* Check which crtcs have changed outputs connected to them, these need |
7420 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
7421 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
7422 | * bit set at most. */ | |
7423 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
7424 | base.head) { | |
7425 | if (connector->base.encoder == &connector->new_encoder->base) | |
7426 | continue; | |
79e53945 | 7427 | |
e2e1ed41 DV |
7428 | if (connector->base.encoder) { |
7429 | tmp_crtc = connector->base.encoder->crtc; | |
7430 | ||
7431 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
7432 | } | |
7433 | ||
7434 | if (connector->new_encoder) | |
7435 | *prepare_pipes |= | |
7436 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
7437 | } |
7438 | ||
e2e1ed41 DV |
7439 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7440 | base.head) { | |
7441 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
7442 | continue; | |
7443 | ||
7444 | if (encoder->base.crtc) { | |
7445 | tmp_crtc = encoder->base.crtc; | |
7446 | ||
7447 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
7448 | } | |
7449 | ||
7450 | if (encoder->new_crtc) | |
7451 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
7452 | } |
7453 | ||
e2e1ed41 DV |
7454 | /* Check for any pipes that will be fully disabled ... */ |
7455 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
7456 | base.head) { | |
7457 | bool used = false; | |
22fd0fab | 7458 | |
e2e1ed41 DV |
7459 | /* Don't try to disable disabled crtcs. */ |
7460 | if (!intel_crtc->base.enabled) | |
7461 | continue; | |
7e7d76c3 | 7462 | |
e2e1ed41 DV |
7463 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
7464 | base.head) { | |
7465 | if (encoder->new_crtc == intel_crtc) | |
7466 | used = true; | |
7467 | } | |
7468 | ||
7469 | if (!used) | |
7470 | *disable_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
7471 | } |
7472 | ||
e2e1ed41 DV |
7473 | |
7474 | /* set_mode is also used to update properties on life display pipes. */ | |
7475 | intel_crtc = to_intel_crtc(crtc); | |
7476 | if (crtc->enabled) | |
7477 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7478 | ||
7479 | /* We only support modeset on one single crtc, hence we need to do that | |
7480 | * only for the passed in crtc iff we change anything else than just | |
7481 | * disable crtcs. | |
7482 | * | |
7483 | * This is actually not true, to be fully compatible with the old crtc | |
7484 | * helper we automatically disable _any_ output (i.e. doesn't need to be | |
7485 | * connected to the crtc we're modesetting on) if it's disconnected. | |
7486 | * Which is a rather nutty api (since changed the output configuration | |
7487 | * without userspace's explicit request can lead to confusion), but | |
7488 | * alas. Hence we currently need to modeset on all pipes we prepare. */ | |
7489 | if (*prepare_pipes) | |
7490 | *modeset_pipes = *prepare_pipes; | |
7491 | ||
7492 | /* ... and mask these out. */ | |
7493 | *modeset_pipes &= ~(*disable_pipes); | |
7494 | *prepare_pipes &= ~(*disable_pipes); | |
47f1c6c9 | 7495 | } |
79e53945 | 7496 | |
ea9d758d | 7497 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 7498 | { |
ea9d758d | 7499 | struct drm_encoder *encoder; |
f6e5b160 | 7500 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 7501 | |
ea9d758d DV |
7502 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
7503 | if (encoder->crtc == crtc) | |
7504 | return true; | |
7505 | ||
7506 | return false; | |
7507 | } | |
7508 | ||
7509 | static void | |
7510 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
7511 | { | |
7512 | struct intel_encoder *intel_encoder; | |
7513 | struct intel_crtc *intel_crtc; | |
7514 | struct drm_connector *connector; | |
7515 | ||
7516 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
7517 | base.head) { | |
7518 | if (!intel_encoder->base.crtc) | |
7519 | continue; | |
7520 | ||
7521 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
7522 | ||
7523 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
7524 | intel_encoder->connectors_active = false; | |
7525 | } | |
7526 | ||
7527 | intel_modeset_commit_output_state(dev); | |
7528 | ||
7529 | /* Update computed state. */ | |
7530 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
7531 | base.head) { | |
7532 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); | |
7533 | } | |
7534 | ||
7535 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
7536 | if (!connector->encoder || !connector->encoder->crtc) | |
7537 | continue; | |
7538 | ||
7539 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
7540 | ||
7541 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
7542 | struct drm_property *dpms_property = |
7543 | dev->mode_config.dpms_property; | |
7544 | ||
ea9d758d | 7545 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 7546 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
7547 | dpms_property, |
7548 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
7549 | |
7550 | intel_encoder = to_intel_encoder(connector->encoder); | |
7551 | intel_encoder->connectors_active = true; | |
7552 | } | |
7553 | } | |
7554 | ||
7555 | } | |
7556 | ||
25c5b266 DV |
7557 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
7558 | list_for_each_entry((intel_crtc), \ | |
7559 | &(dev)->mode_config.crtc_list, \ | |
7560 | base.head) \ | |
7561 | if (mask & (1 <<(intel_crtc)->pipe)) \ | |
7562 | ||
b980514c | 7563 | void |
8af6cf88 DV |
7564 | intel_modeset_check_state(struct drm_device *dev) |
7565 | { | |
7566 | struct intel_crtc *crtc; | |
7567 | struct intel_encoder *encoder; | |
7568 | struct intel_connector *connector; | |
7569 | ||
7570 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
7571 | base.head) { | |
7572 | /* This also checks the encoder/connector hw state with the | |
7573 | * ->get_hw_state callbacks. */ | |
7574 | intel_connector_check_state(connector); | |
7575 | ||
7576 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
7577 | "connector's staged encoder doesn't match current encoder\n"); | |
7578 | } | |
7579 | ||
7580 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
7581 | base.head) { | |
7582 | bool enabled = false; | |
7583 | bool active = false; | |
7584 | enum pipe pipe, tracked_pipe; | |
7585 | ||
7586 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
7587 | encoder->base.base.id, | |
7588 | drm_get_encoder_name(&encoder->base)); | |
7589 | ||
7590 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
7591 | "encoder's stage crtc doesn't match current crtc\n"); | |
7592 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
7593 | "encoder's active_connectors set, but no crtc\n"); | |
7594 | ||
7595 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
7596 | base.head) { | |
7597 | if (connector->base.encoder != &encoder->base) | |
7598 | continue; | |
7599 | enabled = true; | |
7600 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
7601 | active = true; | |
7602 | } | |
7603 | WARN(!!encoder->base.crtc != enabled, | |
7604 | "encoder's enabled state mismatch " | |
7605 | "(expected %i, found %i)\n", | |
7606 | !!encoder->base.crtc, enabled); | |
7607 | WARN(active && !encoder->base.crtc, | |
7608 | "active encoder with no crtc\n"); | |
7609 | ||
7610 | WARN(encoder->connectors_active != active, | |
7611 | "encoder's computed active state doesn't match tracked active state " | |
7612 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
7613 | ||
7614 | active = encoder->get_hw_state(encoder, &pipe); | |
7615 | WARN(active != encoder->connectors_active, | |
7616 | "encoder's hw state doesn't match sw tracking " | |
7617 | "(expected %i, found %i)\n", | |
7618 | encoder->connectors_active, active); | |
7619 | ||
7620 | if (!encoder->base.crtc) | |
7621 | continue; | |
7622 | ||
7623 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
7624 | WARN(active && pipe != tracked_pipe, | |
7625 | "active encoder's pipe doesn't match" | |
7626 | "(expected %i, found %i)\n", | |
7627 | tracked_pipe, pipe); | |
7628 | ||
7629 | } | |
7630 | ||
7631 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
7632 | base.head) { | |
7633 | bool enabled = false; | |
7634 | bool active = false; | |
7635 | ||
7636 | DRM_DEBUG_KMS("[CRTC:%d]\n", | |
7637 | crtc->base.base.id); | |
7638 | ||
7639 | WARN(crtc->active && !crtc->base.enabled, | |
7640 | "active crtc, but not enabled in sw tracking\n"); | |
7641 | ||
7642 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
7643 | base.head) { | |
7644 | if (encoder->base.crtc != &crtc->base) | |
7645 | continue; | |
7646 | enabled = true; | |
7647 | if (encoder->connectors_active) | |
7648 | active = true; | |
7649 | } | |
7650 | WARN(active != crtc->active, | |
7651 | "crtc's computed active state doesn't match tracked active state " | |
7652 | "(expected %i, found %i)\n", active, crtc->active); | |
7653 | WARN(enabled != crtc->base.enabled, | |
7654 | "crtc's computed enabled state doesn't match tracked enabled state " | |
7655 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
7656 | ||
7657 | assert_pipe(dev->dev_private, crtc->pipe, crtc->active); | |
7658 | } | |
7659 | } | |
7660 | ||
c0c36b94 CW |
7661 | int intel_set_mode(struct drm_crtc *crtc, |
7662 | struct drm_display_mode *mode, | |
7663 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
7664 | { |
7665 | struct drm_device *dev = crtc->dev; | |
dbf2b54e | 7666 | drm_i915_private_t *dev_priv = dev->dev_private; |
3ac18232 | 7667 | struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode; |
25c5b266 DV |
7668 | struct intel_crtc *intel_crtc; |
7669 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 7670 | int ret = 0; |
a6778b3c | 7671 | |
3ac18232 | 7672 | saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
7673 | if (!saved_mode) |
7674 | return -ENOMEM; | |
3ac18232 | 7675 | saved_hwmode = saved_mode + 1; |
a6778b3c | 7676 | |
e2e1ed41 | 7677 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
7678 | &prepare_pipes, &disable_pipes); |
7679 | ||
7680 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
7681 | modeset_pipes, prepare_pipes, disable_pipes); | |
e2e1ed41 | 7682 | |
976f8a20 DV |
7683 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
7684 | intel_crtc_disable(&intel_crtc->base); | |
87f1faa6 | 7685 | |
3ac18232 TG |
7686 | *saved_hwmode = crtc->hwmode; |
7687 | *saved_mode = crtc->mode; | |
a6778b3c | 7688 | |
25c5b266 DV |
7689 | /* Hack: Because we don't (yet) support global modeset on multiple |
7690 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
7691 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
7692 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
7693 | * changing their mode at the same time. */ | |
7694 | adjusted_mode = NULL; | |
7695 | if (modeset_pipes) { | |
7696 | adjusted_mode = intel_modeset_adjusted_mode(crtc, mode); | |
7697 | if (IS_ERR(adjusted_mode)) { | |
c0c36b94 | 7698 | ret = PTR_ERR(adjusted_mode); |
3ac18232 | 7699 | goto out; |
25c5b266 | 7700 | } |
25c5b266 | 7701 | } |
a6778b3c | 7702 | |
ea9d758d DV |
7703 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
7704 | if (intel_crtc->base.enabled) | |
7705 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
7706 | } | |
a6778b3c | 7707 | |
6c4c86f5 DV |
7708 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
7709 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 7710 | */ |
6c4c86f5 | 7711 | if (modeset_pipes) |
25c5b266 | 7712 | crtc->mode = *mode; |
7758a113 | 7713 | |
ea9d758d DV |
7714 | /* Only after disabling all output pipelines that will be changed can we |
7715 | * update the the output configuration. */ | |
7716 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 7717 | |
47fab737 DV |
7718 | if (dev_priv->display.modeset_global_resources) |
7719 | dev_priv->display.modeset_global_resources(dev); | |
7720 | ||
a6778b3c DV |
7721 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
7722 | * on the DPLL. | |
f6e5b160 | 7723 | */ |
25c5b266 | 7724 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
c0c36b94 CW |
7725 | ret = intel_crtc_mode_set(&intel_crtc->base, |
7726 | mode, adjusted_mode, | |
7727 | x, y, fb); | |
7728 | if (ret) | |
7729 | goto done; | |
a6778b3c DV |
7730 | } |
7731 | ||
7732 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
25c5b266 DV |
7733 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
7734 | dev_priv->display.crtc_enable(&intel_crtc->base); | |
a6778b3c | 7735 | |
25c5b266 DV |
7736 | if (modeset_pipes) { |
7737 | /* Store real post-adjustment hardware mode. */ | |
7738 | crtc->hwmode = *adjusted_mode; | |
a6778b3c | 7739 | |
25c5b266 DV |
7740 | /* Calculate and store various constants which |
7741 | * are later needed by vblank and swap-completion | |
7742 | * timestamping. They are derived from true hwmode. | |
7743 | */ | |
7744 | drm_calc_timestamping_constants(crtc); | |
7745 | } | |
a6778b3c DV |
7746 | |
7747 | /* FIXME: add subpixel order */ | |
7748 | done: | |
7749 | drm_mode_destroy(dev, adjusted_mode); | |
c0c36b94 | 7750 | if (ret && crtc->enabled) { |
3ac18232 TG |
7751 | crtc->hwmode = *saved_hwmode; |
7752 | crtc->mode = *saved_mode; | |
8af6cf88 DV |
7753 | } else { |
7754 | intel_modeset_check_state(dev); | |
a6778b3c DV |
7755 | } |
7756 | ||
3ac18232 TG |
7757 | out: |
7758 | kfree(saved_mode); | |
a6778b3c | 7759 | return ret; |
f6e5b160 CW |
7760 | } |
7761 | ||
c0c36b94 CW |
7762 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
7763 | { | |
7764 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); | |
7765 | } | |
7766 | ||
25c5b266 DV |
7767 | #undef for_each_intel_crtc_masked |
7768 | ||
d9e55608 DV |
7769 | static void intel_set_config_free(struct intel_set_config *config) |
7770 | { | |
7771 | if (!config) | |
7772 | return; | |
7773 | ||
1aa4b628 DV |
7774 | kfree(config->save_connector_encoders); |
7775 | kfree(config->save_encoder_crtcs); | |
d9e55608 DV |
7776 | kfree(config); |
7777 | } | |
7778 | ||
85f9eb71 DV |
7779 | static int intel_set_config_save_state(struct drm_device *dev, |
7780 | struct intel_set_config *config) | |
7781 | { | |
85f9eb71 DV |
7782 | struct drm_encoder *encoder; |
7783 | struct drm_connector *connector; | |
7784 | int count; | |
7785 | ||
1aa4b628 DV |
7786 | config->save_encoder_crtcs = |
7787 | kcalloc(dev->mode_config.num_encoder, | |
7788 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
7789 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
7790 | return -ENOMEM; |
7791 | ||
1aa4b628 DV |
7792 | config->save_connector_encoders = |
7793 | kcalloc(dev->mode_config.num_connector, | |
7794 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
7795 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
7796 | return -ENOMEM; |
7797 | ||
7798 | /* Copy data. Note that driver private data is not affected. | |
7799 | * Should anything bad happen only the expected state is | |
7800 | * restored, not the drivers personal bookkeeping. | |
7801 | */ | |
85f9eb71 DV |
7802 | count = 0; |
7803 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 7804 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
7805 | } |
7806 | ||
7807 | count = 0; | |
7808 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 7809 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
7810 | } |
7811 | ||
7812 | return 0; | |
7813 | } | |
7814 | ||
7815 | static void intel_set_config_restore_state(struct drm_device *dev, | |
7816 | struct intel_set_config *config) | |
7817 | { | |
9a935856 DV |
7818 | struct intel_encoder *encoder; |
7819 | struct intel_connector *connector; | |
85f9eb71 DV |
7820 | int count; |
7821 | ||
85f9eb71 | 7822 | count = 0; |
9a935856 DV |
7823 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7824 | encoder->new_crtc = | |
7825 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
7826 | } |
7827 | ||
7828 | count = 0; | |
9a935856 DV |
7829 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
7830 | connector->new_encoder = | |
7831 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
7832 | } |
7833 | } | |
7834 | ||
5e2b584e DV |
7835 | static void |
7836 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
7837 | struct intel_set_config *config) | |
7838 | { | |
7839 | ||
7840 | /* We should be able to check here if the fb has the same properties | |
7841 | * and then just flip_or_move it */ | |
7842 | if (set->crtc->fb != set->fb) { | |
7843 | /* If we have no fb then treat it as a full mode set */ | |
7844 | if (set->crtc->fb == NULL) { | |
7845 | DRM_DEBUG_KMS("crtc has no fb, full mode set\n"); | |
7846 | config->mode_changed = true; | |
7847 | } else if (set->fb == NULL) { | |
7848 | config->mode_changed = true; | |
7849 | } else if (set->fb->depth != set->crtc->fb->depth) { | |
7850 | config->mode_changed = true; | |
7851 | } else if (set->fb->bits_per_pixel != | |
7852 | set->crtc->fb->bits_per_pixel) { | |
7853 | config->mode_changed = true; | |
7854 | } else | |
7855 | config->fb_changed = true; | |
7856 | } | |
7857 | ||
835c5873 | 7858 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
7859 | config->fb_changed = true; |
7860 | ||
7861 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
7862 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
7863 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
7864 | drm_mode_debug_printmodeline(set->mode); | |
7865 | config->mode_changed = true; | |
7866 | } | |
7867 | } | |
7868 | ||
2e431051 | 7869 | static int |
9a935856 DV |
7870 | intel_modeset_stage_output_state(struct drm_device *dev, |
7871 | struct drm_mode_set *set, | |
7872 | struct intel_set_config *config) | |
50f56119 | 7873 | { |
85f9eb71 | 7874 | struct drm_crtc *new_crtc; |
9a935856 DV |
7875 | struct intel_connector *connector; |
7876 | struct intel_encoder *encoder; | |
2e431051 | 7877 | int count, ro; |
50f56119 | 7878 | |
9a935856 DV |
7879 | /* The upper layers ensure that we either disabl a crtc or have a list |
7880 | * of connectors. For paranoia, double-check this. */ | |
7881 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
7882 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
7883 | ||
50f56119 | 7884 | count = 0; |
9a935856 DV |
7885 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7886 | base.head) { | |
7887 | /* Otherwise traverse passed in connector list and get encoders | |
7888 | * for them. */ | |
50f56119 | 7889 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
7890 | if (set->connectors[ro] == &connector->base) { |
7891 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
7892 | break; |
7893 | } | |
7894 | } | |
7895 | ||
9a935856 DV |
7896 | /* If we disable the crtc, disable all its connectors. Also, if |
7897 | * the connector is on the changing crtc but not on the new | |
7898 | * connector list, disable it. */ | |
7899 | if ((!set->fb || ro == set->num_connectors) && | |
7900 | connector->base.encoder && | |
7901 | connector->base.encoder->crtc == set->crtc) { | |
7902 | connector->new_encoder = NULL; | |
7903 | ||
7904 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
7905 | connector->base.base.id, | |
7906 | drm_get_connector_name(&connector->base)); | |
7907 | } | |
7908 | ||
7909 | ||
7910 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 7911 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 7912 | config->mode_changed = true; |
50f56119 DV |
7913 | } |
7914 | } | |
9a935856 | 7915 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 7916 | |
9a935856 | 7917 | /* Update crtc of enabled connectors. */ |
50f56119 | 7918 | count = 0; |
9a935856 DV |
7919 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
7920 | base.head) { | |
7921 | if (!connector->new_encoder) | |
50f56119 DV |
7922 | continue; |
7923 | ||
9a935856 | 7924 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
7925 | |
7926 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 7927 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
7928 | new_crtc = set->crtc; |
7929 | } | |
7930 | ||
7931 | /* Make sure the new CRTC will work with the encoder */ | |
9a935856 DV |
7932 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
7933 | new_crtc)) { | |
5e2b584e | 7934 | return -EINVAL; |
50f56119 | 7935 | } |
9a935856 DV |
7936 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
7937 | ||
7938 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
7939 | connector->base.base.id, | |
7940 | drm_get_connector_name(&connector->base), | |
7941 | new_crtc->base.id); | |
7942 | } | |
7943 | ||
7944 | /* Check for any encoders that needs to be disabled. */ | |
7945 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
7946 | base.head) { | |
7947 | list_for_each_entry(connector, | |
7948 | &dev->mode_config.connector_list, | |
7949 | base.head) { | |
7950 | if (connector->new_encoder == encoder) { | |
7951 | WARN_ON(!connector->new_encoder->new_crtc); | |
7952 | ||
7953 | goto next_encoder; | |
7954 | } | |
7955 | } | |
7956 | encoder->new_crtc = NULL; | |
7957 | next_encoder: | |
7958 | /* Only now check for crtc changes so we don't miss encoders | |
7959 | * that will be disabled. */ | |
7960 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 7961 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 7962 | config->mode_changed = true; |
50f56119 DV |
7963 | } |
7964 | } | |
9a935856 | 7965 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 7966 | |
2e431051 DV |
7967 | return 0; |
7968 | } | |
7969 | ||
7970 | static int intel_crtc_set_config(struct drm_mode_set *set) | |
7971 | { | |
7972 | struct drm_device *dev; | |
2e431051 DV |
7973 | struct drm_mode_set save_set; |
7974 | struct intel_set_config *config; | |
7975 | int ret; | |
2e431051 | 7976 | |
8d3e375e DV |
7977 | BUG_ON(!set); |
7978 | BUG_ON(!set->crtc); | |
7979 | BUG_ON(!set->crtc->helper_private); | |
2e431051 DV |
7980 | |
7981 | if (!set->mode) | |
7982 | set->fb = NULL; | |
7983 | ||
431e50f7 DV |
7984 | /* The fb helper likes to play gross jokes with ->mode_set_config. |
7985 | * Unfortunately the crtc helper doesn't do much at all for this case, | |
7986 | * so we have to cope with this madness until the fb helper is fixed up. */ | |
7987 | if (set->fb && set->num_connectors == 0) | |
7988 | return 0; | |
7989 | ||
2e431051 DV |
7990 | if (set->fb) { |
7991 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
7992 | set->crtc->base.id, set->fb->base.id, | |
7993 | (int)set->num_connectors, set->x, set->y); | |
7994 | } else { | |
7995 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
7996 | } |
7997 | ||
7998 | dev = set->crtc->dev; | |
7999 | ||
8000 | ret = -ENOMEM; | |
8001 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
8002 | if (!config) | |
8003 | goto out_config; | |
8004 | ||
8005 | ret = intel_set_config_save_state(dev, config); | |
8006 | if (ret) | |
8007 | goto out_config; | |
8008 | ||
8009 | save_set.crtc = set->crtc; | |
8010 | save_set.mode = &set->crtc->mode; | |
8011 | save_set.x = set->crtc->x; | |
8012 | save_set.y = set->crtc->y; | |
8013 | save_set.fb = set->crtc->fb; | |
8014 | ||
8015 | /* Compute whether we need a full modeset, only an fb base update or no | |
8016 | * change at all. In the future we might also check whether only the | |
8017 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
8018 | * such cases. */ | |
8019 | intel_set_config_compute_mode_changes(set, config); | |
8020 | ||
9a935856 | 8021 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
8022 | if (ret) |
8023 | goto fail; | |
8024 | ||
5e2b584e | 8025 | if (config->mode_changed) { |
87f1faa6 | 8026 | if (set->mode) { |
50f56119 DV |
8027 | DRM_DEBUG_KMS("attempting to set mode from" |
8028 | " userspace\n"); | |
8029 | drm_mode_debug_printmodeline(set->mode); | |
87f1faa6 DV |
8030 | } |
8031 | ||
c0c36b94 CW |
8032 | ret = intel_set_mode(set->crtc, set->mode, |
8033 | set->x, set->y, set->fb); | |
8034 | if (ret) { | |
8035 | DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n", | |
8036 | set->crtc->base.id, ret); | |
87f1faa6 DV |
8037 | goto fail; |
8038 | } | |
5e2b584e | 8039 | } else if (config->fb_changed) { |
4f660f49 | 8040 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 8041 | set->x, set->y, set->fb); |
50f56119 DV |
8042 | } |
8043 | ||
d9e55608 DV |
8044 | intel_set_config_free(config); |
8045 | ||
50f56119 DV |
8046 | return 0; |
8047 | ||
8048 | fail: | |
85f9eb71 | 8049 | intel_set_config_restore_state(dev, config); |
50f56119 DV |
8050 | |
8051 | /* Try to restore the config */ | |
5e2b584e | 8052 | if (config->mode_changed && |
c0c36b94 CW |
8053 | intel_set_mode(save_set.crtc, save_set.mode, |
8054 | save_set.x, save_set.y, save_set.fb)) | |
50f56119 DV |
8055 | DRM_ERROR("failed to restore config after modeset failure\n"); |
8056 | ||
d9e55608 DV |
8057 | out_config: |
8058 | intel_set_config_free(config); | |
50f56119 DV |
8059 | return ret; |
8060 | } | |
f6e5b160 CW |
8061 | |
8062 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 CW |
8063 | .cursor_set = intel_crtc_cursor_set, |
8064 | .cursor_move = intel_crtc_cursor_move, | |
8065 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 8066 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
8067 | .destroy = intel_crtc_destroy, |
8068 | .page_flip = intel_crtc_page_flip, | |
8069 | }; | |
8070 | ||
79f689aa PZ |
8071 | static void intel_cpu_pll_init(struct drm_device *dev) |
8072 | { | |
affa9354 | 8073 | if (HAS_DDI(dev)) |
79f689aa PZ |
8074 | intel_ddi_pll_init(dev); |
8075 | } | |
8076 | ||
ee7b9f93 JB |
8077 | static void intel_pch_pll_init(struct drm_device *dev) |
8078 | { | |
8079 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8080 | int i; | |
8081 | ||
8082 | if (dev_priv->num_pch_pll == 0) { | |
8083 | DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n"); | |
8084 | return; | |
8085 | } | |
8086 | ||
8087 | for (i = 0; i < dev_priv->num_pch_pll; i++) { | |
8088 | dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i); | |
8089 | dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i); | |
8090 | dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i); | |
8091 | } | |
8092 | } | |
8093 | ||
b358d0a6 | 8094 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 8095 | { |
22fd0fab | 8096 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
8097 | struct intel_crtc *intel_crtc; |
8098 | int i; | |
8099 | ||
8100 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
8101 | if (intel_crtc == NULL) | |
8102 | return; | |
8103 | ||
8104 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
8105 | ||
8106 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
8107 | for (i = 0; i < 256; i++) { |
8108 | intel_crtc->lut_r[i] = i; | |
8109 | intel_crtc->lut_g[i] = i; | |
8110 | intel_crtc->lut_b[i] = i; | |
8111 | } | |
8112 | ||
80824003 JB |
8113 | /* Swap pipes & planes for FBC on pre-965 */ |
8114 | intel_crtc->pipe = pipe; | |
8115 | intel_crtc->plane = pipe; | |
a5c961d1 | 8116 | intel_crtc->cpu_transcoder = pipe; |
e2e767ab | 8117 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 8118 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 8119 | intel_crtc->plane = !pipe; |
80824003 JB |
8120 | } |
8121 | ||
22fd0fab JB |
8122 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
8123 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
8124 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
8125 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
8126 | ||
5a354204 | 8127 | intel_crtc->bpp = 24; /* default for pre-Ironlake */ |
7e7d76c3 | 8128 | |
79e53945 | 8129 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
79e53945 JB |
8130 | } |
8131 | ||
08d7b3d1 | 8132 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 8133 | struct drm_file *file) |
08d7b3d1 | 8134 | { |
08d7b3d1 | 8135 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
8136 | struct drm_mode_object *drmmode_obj; |
8137 | struct intel_crtc *crtc; | |
08d7b3d1 | 8138 | |
1cff8f6b DV |
8139 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
8140 | return -ENODEV; | |
08d7b3d1 | 8141 | |
c05422d5 DV |
8142 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
8143 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 8144 | |
c05422d5 | 8145 | if (!drmmode_obj) { |
08d7b3d1 CW |
8146 | DRM_ERROR("no such CRTC id\n"); |
8147 | return -EINVAL; | |
8148 | } | |
8149 | ||
c05422d5 DV |
8150 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
8151 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 8152 | |
c05422d5 | 8153 | return 0; |
08d7b3d1 CW |
8154 | } |
8155 | ||
66a9278e | 8156 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 8157 | { |
66a9278e DV |
8158 | struct drm_device *dev = encoder->base.dev; |
8159 | struct intel_encoder *source_encoder; | |
79e53945 | 8160 | int index_mask = 0; |
79e53945 JB |
8161 | int entry = 0; |
8162 | ||
66a9278e DV |
8163 | list_for_each_entry(source_encoder, |
8164 | &dev->mode_config.encoder_list, base.head) { | |
8165 | ||
8166 | if (encoder == source_encoder) | |
79e53945 | 8167 | index_mask |= (1 << entry); |
66a9278e DV |
8168 | |
8169 | /* Intel hw has only one MUX where enocoders could be cloned. */ | |
8170 | if (encoder->cloneable && source_encoder->cloneable) | |
8171 | index_mask |= (1 << entry); | |
8172 | ||
79e53945 JB |
8173 | entry++; |
8174 | } | |
4ef69c7a | 8175 | |
79e53945 JB |
8176 | return index_mask; |
8177 | } | |
8178 | ||
4d302442 CW |
8179 | static bool has_edp_a(struct drm_device *dev) |
8180 | { | |
8181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8182 | ||
8183 | if (!IS_MOBILE(dev)) | |
8184 | return false; | |
8185 | ||
8186 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
8187 | return false; | |
8188 | ||
8189 | if (IS_GEN5(dev) && | |
8190 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
8191 | return false; | |
8192 | ||
8193 | return true; | |
8194 | } | |
8195 | ||
79e53945 JB |
8196 | static void intel_setup_outputs(struct drm_device *dev) |
8197 | { | |
725e30ad | 8198 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 8199 | struct intel_encoder *encoder; |
cb0953d7 | 8200 | bool dpd_is_edp = false; |
f3cfcba6 | 8201 | bool has_lvds; |
79e53945 | 8202 | |
f3cfcba6 | 8203 | has_lvds = intel_lvds_init(dev); |
c5d1b51d CW |
8204 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { |
8205 | /* disable the panel fitter on everything but LVDS */ | |
8206 | I915_WRITE(PFIT_CONTROL, 0); | |
8207 | } | |
79e53945 | 8208 | |
affa9354 | 8209 | if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES))) |
79935fca | 8210 | intel_crt_init(dev); |
cb0953d7 | 8211 | |
affa9354 | 8212 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
8213 | int found; |
8214 | ||
8215 | /* Haswell uses DDI functions to detect digital outputs */ | |
8216 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
8217 | /* DDI A only supports eDP */ | |
8218 | if (found) | |
8219 | intel_ddi_init(dev, PORT_A); | |
8220 | ||
8221 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
8222 | * register */ | |
8223 | found = I915_READ(SFUSE_STRAP); | |
8224 | ||
8225 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
8226 | intel_ddi_init(dev, PORT_B); | |
8227 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
8228 | intel_ddi_init(dev, PORT_C); | |
8229 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
8230 | intel_ddi_init(dev, PORT_D); | |
8231 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 8232 | int found; |
270b3042 DV |
8233 | dpd_is_edp = intel_dpd_is_edp(dev); |
8234 | ||
8235 | if (has_edp_a(dev)) | |
8236 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 8237 | |
30ad48b7 | 8238 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
461ed3ca | 8239 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 8240 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 8241 | if (!found) |
08d644ad | 8242 | intel_hdmi_init(dev, HDMIB, PORT_B); |
5eb08b69 | 8243 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 8244 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
8245 | } |
8246 | ||
8247 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
08d644ad | 8248 | intel_hdmi_init(dev, HDMIC, PORT_C); |
30ad48b7 | 8249 | |
b708a1d5 | 8250 | if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED) |
08d644ad | 8251 | intel_hdmi_init(dev, HDMID, PORT_D); |
30ad48b7 | 8252 | |
5eb08b69 | 8253 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 8254 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 8255 | |
270b3042 | 8256 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 8257 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 8258 | } else if (IS_VALLEYVIEW(dev)) { |
19c03924 | 8259 | /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */ |
67cfc203 VS |
8260 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) |
8261 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 8262 | |
67cfc203 VS |
8263 | if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) { |
8264 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B); | |
8265 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) | |
8266 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
4a87d65d JB |
8267 | } |
8268 | ||
67cfc203 VS |
8269 | if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED) |
8270 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C); | |
5eb08b69 | 8271 | |
103a196f | 8272 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 8273 | bool found = false; |
7d57382e | 8274 | |
725e30ad | 8275 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 8276 | DRM_DEBUG_KMS("probing SDVOB\n"); |
eef4eacb | 8277 | found = intel_sdvo_init(dev, SDVOB, true); |
b01f2c3a JB |
8278 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
8279 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
08d644ad | 8280 | intel_hdmi_init(dev, SDVOB, PORT_B); |
b01f2c3a | 8281 | } |
27185ae1 | 8282 | |
b01f2c3a JB |
8283 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
8284 | DRM_DEBUG_KMS("probing DP_B\n"); | |
ab9d7c30 | 8285 | intel_dp_init(dev, DP_B, PORT_B); |
b01f2c3a | 8286 | } |
725e30ad | 8287 | } |
13520b05 KH |
8288 | |
8289 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 8290 | |
b01f2c3a JB |
8291 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
8292 | DRM_DEBUG_KMS("probing SDVOC\n"); | |
eef4eacb | 8293 | found = intel_sdvo_init(dev, SDVOC, false); |
b01f2c3a | 8294 | } |
27185ae1 ML |
8295 | |
8296 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { | |
8297 | ||
b01f2c3a JB |
8298 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
8299 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
08d644ad | 8300 | intel_hdmi_init(dev, SDVOC, PORT_C); |
b01f2c3a JB |
8301 | } |
8302 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
8303 | DRM_DEBUG_KMS("probing DP_C\n"); | |
ab9d7c30 | 8304 | intel_dp_init(dev, DP_C, PORT_C); |
b01f2c3a | 8305 | } |
725e30ad | 8306 | } |
27185ae1 | 8307 | |
b01f2c3a JB |
8308 | if (SUPPORTS_INTEGRATED_DP(dev) && |
8309 | (I915_READ(DP_D) & DP_DETECTED)) { | |
8310 | DRM_DEBUG_KMS("probing DP_D\n"); | |
ab9d7c30 | 8311 | intel_dp_init(dev, DP_D, PORT_D); |
b01f2c3a | 8312 | } |
bad720ff | 8313 | } else if (IS_GEN2(dev)) |
79e53945 JB |
8314 | intel_dvo_init(dev); |
8315 | ||
103a196f | 8316 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
8317 | intel_tv_init(dev); |
8318 | ||
4ef69c7a CW |
8319 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
8320 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
8321 | encoder->base.possible_clones = | |
66a9278e | 8322 | intel_encoder_clones(encoder); |
79e53945 | 8323 | } |
47356eb6 | 8324 | |
dde86e2d | 8325 | intel_init_pch_refclk(dev); |
270b3042 DV |
8326 | |
8327 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
8328 | } |
8329 | ||
8330 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
8331 | { | |
8332 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
8333 | |
8334 | drm_framebuffer_cleanup(fb); | |
05394f39 | 8335 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
79e53945 JB |
8336 | |
8337 | kfree(intel_fb); | |
8338 | } | |
8339 | ||
8340 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 8341 | struct drm_file *file, |
79e53945 JB |
8342 | unsigned int *handle) |
8343 | { | |
8344 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 8345 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 8346 | |
05394f39 | 8347 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
8348 | } |
8349 | ||
8350 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
8351 | .destroy = intel_user_framebuffer_destroy, | |
8352 | .create_handle = intel_user_framebuffer_create_handle, | |
8353 | }; | |
8354 | ||
38651674 DA |
8355 | int intel_framebuffer_init(struct drm_device *dev, |
8356 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 8357 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 8358 | struct drm_i915_gem_object *obj) |
79e53945 | 8359 | { |
79e53945 JB |
8360 | int ret; |
8361 | ||
c16ed4be CW |
8362 | if (obj->tiling_mode == I915_TILING_Y) { |
8363 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 8364 | return -EINVAL; |
c16ed4be | 8365 | } |
57cd6508 | 8366 | |
c16ed4be CW |
8367 | if (mode_cmd->pitches[0] & 63) { |
8368 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
8369 | mode_cmd->pitches[0]); | |
57cd6508 | 8370 | return -EINVAL; |
c16ed4be | 8371 | } |
57cd6508 | 8372 | |
5d7bd705 | 8373 | /* FIXME <= Gen4 stride limits are bit unclear */ |
c16ed4be CW |
8374 | if (mode_cmd->pitches[0] > 32768) { |
8375 | DRM_DEBUG("pitch (%d) must be at less than 32768\n", | |
8376 | mode_cmd->pitches[0]); | |
5d7bd705 | 8377 | return -EINVAL; |
c16ed4be | 8378 | } |
5d7bd705 VS |
8379 | |
8380 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
8381 | mode_cmd->pitches[0] != obj->stride) { |
8382 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
8383 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 8384 | return -EINVAL; |
c16ed4be | 8385 | } |
5d7bd705 | 8386 | |
57779d06 | 8387 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 8388 | switch (mode_cmd->pixel_format) { |
57779d06 | 8389 | case DRM_FORMAT_C8: |
04b3924d VS |
8390 | case DRM_FORMAT_RGB565: |
8391 | case DRM_FORMAT_XRGB8888: | |
8392 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
8393 | break; |
8394 | case DRM_FORMAT_XRGB1555: | |
8395 | case DRM_FORMAT_ARGB1555: | |
c16ed4be CW |
8396 | if (INTEL_INFO(dev)->gen > 3) { |
8397 | DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format); | |
57779d06 | 8398 | return -EINVAL; |
c16ed4be | 8399 | } |
57779d06 VS |
8400 | break; |
8401 | case DRM_FORMAT_XBGR8888: | |
8402 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
8403 | case DRM_FORMAT_XRGB2101010: |
8404 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
8405 | case DRM_FORMAT_XBGR2101010: |
8406 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be CW |
8407 | if (INTEL_INFO(dev)->gen < 4) { |
8408 | DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format); | |
57779d06 | 8409 | return -EINVAL; |
c16ed4be | 8410 | } |
b5626747 | 8411 | break; |
04b3924d VS |
8412 | case DRM_FORMAT_YUYV: |
8413 | case DRM_FORMAT_UYVY: | |
8414 | case DRM_FORMAT_YVYU: | |
8415 | case DRM_FORMAT_VYUY: | |
c16ed4be CW |
8416 | if (INTEL_INFO(dev)->gen < 5) { |
8417 | DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format); | |
57779d06 | 8418 | return -EINVAL; |
c16ed4be | 8419 | } |
57cd6508 CW |
8420 | break; |
8421 | default: | |
c16ed4be | 8422 | DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format); |
57cd6508 CW |
8423 | return -EINVAL; |
8424 | } | |
8425 | ||
90f9a336 VS |
8426 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
8427 | if (mode_cmd->offsets[0] != 0) | |
8428 | return -EINVAL; | |
8429 | ||
c7d73f6a DV |
8430 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
8431 | intel_fb->obj = obj; | |
8432 | ||
79e53945 JB |
8433 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
8434 | if (ret) { | |
8435 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
8436 | return ret; | |
8437 | } | |
8438 | ||
79e53945 JB |
8439 | return 0; |
8440 | } | |
8441 | ||
79e53945 JB |
8442 | static struct drm_framebuffer * |
8443 | intel_user_framebuffer_create(struct drm_device *dev, | |
8444 | struct drm_file *filp, | |
308e5bcb | 8445 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 8446 | { |
05394f39 | 8447 | struct drm_i915_gem_object *obj; |
79e53945 | 8448 | |
308e5bcb JB |
8449 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
8450 | mode_cmd->handles[0])); | |
c8725226 | 8451 | if (&obj->base == NULL) |
cce13ff7 | 8452 | return ERR_PTR(-ENOENT); |
79e53945 | 8453 | |
d2dff872 | 8454 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
8455 | } |
8456 | ||
79e53945 | 8457 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 8458 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 8459 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
8460 | }; |
8461 | ||
e70236a8 JB |
8462 | /* Set up chip specific display functions */ |
8463 | static void intel_init_display(struct drm_device *dev) | |
8464 | { | |
8465 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8466 | ||
8467 | /* We always want a DPMS function */ | |
affa9354 | 8468 | if (HAS_DDI(dev)) { |
09b4ddf9 | 8469 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
8470 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
8471 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 8472 | dev_priv->display.off = haswell_crtc_off; |
09b4ddf9 PZ |
8473 | dev_priv->display.update_plane = ironlake_update_plane; |
8474 | } else if (HAS_PCH_SPLIT(dev)) { | |
f564048e | 8475 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
8476 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
8477 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 8478 | dev_priv->display.off = ironlake_crtc_off; |
17638cd6 | 8479 | dev_priv->display.update_plane = ironlake_update_plane; |
f564048e | 8480 | } else { |
f564048e | 8481 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
8482 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
8483 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 8484 | dev_priv->display.off = i9xx_crtc_off; |
17638cd6 | 8485 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 8486 | } |
e70236a8 | 8487 | |
e70236a8 | 8488 | /* Returns the core display clock speed */ |
25eb05fc JB |
8489 | if (IS_VALLEYVIEW(dev)) |
8490 | dev_priv->display.get_display_clock_speed = | |
8491 | valleyview_get_display_clock_speed; | |
8492 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
8493 | dev_priv->display.get_display_clock_speed = |
8494 | i945_get_display_clock_speed; | |
8495 | else if (IS_I915G(dev)) | |
8496 | dev_priv->display.get_display_clock_speed = | |
8497 | i915_get_display_clock_speed; | |
f2b115e6 | 8498 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
8499 | dev_priv->display.get_display_clock_speed = |
8500 | i9xx_misc_get_display_clock_speed; | |
8501 | else if (IS_I915GM(dev)) | |
8502 | dev_priv->display.get_display_clock_speed = | |
8503 | i915gm_get_display_clock_speed; | |
8504 | else if (IS_I865G(dev)) | |
8505 | dev_priv->display.get_display_clock_speed = | |
8506 | i865_get_display_clock_speed; | |
f0f8a9ce | 8507 | else if (IS_I85X(dev)) |
e70236a8 JB |
8508 | dev_priv->display.get_display_clock_speed = |
8509 | i855_get_display_clock_speed; | |
8510 | else /* 852, 830 */ | |
8511 | dev_priv->display.get_display_clock_speed = | |
8512 | i830_get_display_clock_speed; | |
8513 | ||
7f8a8569 | 8514 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 8515 | if (IS_GEN5(dev)) { |
674cf967 | 8516 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 8517 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 8518 | } else if (IS_GEN6(dev)) { |
674cf967 | 8519 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 8520 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
8521 | } else if (IS_IVYBRIDGE(dev)) { |
8522 | /* FIXME: detect B0+ stepping and use auto training */ | |
8523 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 8524 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
8525 | dev_priv->display.modeset_global_resources = |
8526 | ivb_modeset_global_resources; | |
c82e4d26 ED |
8527 | } else if (IS_HASWELL(dev)) { |
8528 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; | |
83358c85 | 8529 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
8530 | dev_priv->display.modeset_global_resources = |
8531 | haswell_modeset_global_resources; | |
a0e63c22 | 8532 | } |
6067aaea | 8533 | } else if (IS_G4X(dev)) { |
e0dac65e | 8534 | dev_priv->display.write_eld = g4x_write_eld; |
e70236a8 | 8535 | } |
8c9f3aaf JB |
8536 | |
8537 | /* Default just returns -ENODEV to indicate unsupported */ | |
8538 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8539 | ||
8540 | switch (INTEL_INFO(dev)->gen) { | |
8541 | case 2: | |
8542 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
8543 | break; | |
8544 | ||
8545 | case 3: | |
8546 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
8547 | break; | |
8548 | ||
8549 | case 4: | |
8550 | case 5: | |
8551 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
8552 | break; | |
8553 | ||
8554 | case 6: | |
8555 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
8556 | break; | |
7c9017e5 JB |
8557 | case 7: |
8558 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
8559 | break; | |
8c9f3aaf | 8560 | } |
e70236a8 JB |
8561 | } |
8562 | ||
b690e96c JB |
8563 | /* |
8564 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
8565 | * resume, or other times. This quirk makes sure that's the case for | |
8566 | * affected systems. | |
8567 | */ | |
0206e353 | 8568 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
8569 | { |
8570 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8571 | ||
8572 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 8573 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
8574 | } |
8575 | ||
435793df KP |
8576 | /* |
8577 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
8578 | */ | |
8579 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
8580 | { | |
8581 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8582 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 8583 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
8584 | } |
8585 | ||
4dca20ef | 8586 | /* |
5a15ab5b CE |
8587 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
8588 | * brightness value | |
4dca20ef CE |
8589 | */ |
8590 | static void quirk_invert_brightness(struct drm_device *dev) | |
8591 | { | |
8592 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8593 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 8594 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
8595 | } |
8596 | ||
b690e96c JB |
8597 | struct intel_quirk { |
8598 | int device; | |
8599 | int subsystem_vendor; | |
8600 | int subsystem_device; | |
8601 | void (*hook)(struct drm_device *dev); | |
8602 | }; | |
8603 | ||
5f85f176 EE |
8604 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
8605 | struct intel_dmi_quirk { | |
8606 | void (*hook)(struct drm_device *dev); | |
8607 | const struct dmi_system_id (*dmi_id_list)[]; | |
8608 | }; | |
8609 | ||
8610 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
8611 | { | |
8612 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
8613 | return 1; | |
8614 | } | |
8615 | ||
8616 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
8617 | { | |
8618 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
8619 | { | |
8620 | .callback = intel_dmi_reverse_brightness, | |
8621 | .ident = "NCR Corporation", | |
8622 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
8623 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
8624 | }, | |
8625 | }, | |
8626 | { } /* terminating entry */ | |
8627 | }, | |
8628 | .hook = quirk_invert_brightness, | |
8629 | }, | |
8630 | }; | |
8631 | ||
c43b5634 | 8632 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 8633 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 8634 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 8635 | |
b690e96c JB |
8636 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
8637 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
8638 | ||
b690e96c JB |
8639 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
8640 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
8641 | ||
ccd0d36e | 8642 | /* 830/845 need to leave pipe A & dpll A up */ |
b690e96c | 8643 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
dcdaed6e | 8644 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
435793df KP |
8645 | |
8646 | /* Lenovo U160 cannot use SSC on LVDS */ | |
8647 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
8648 | |
8649 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
8650 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b CE |
8651 | |
8652 | /* Acer Aspire 5734Z must invert backlight brightness */ | |
8653 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
1ffff603 JN |
8654 | |
8655 | /* Acer/eMachines G725 */ | |
8656 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
01e3a8fe JN |
8657 | |
8658 | /* Acer/eMachines e725 */ | |
8659 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
5559ecad JN |
8660 | |
8661 | /* Acer/Packard Bell NCL20 */ | |
8662 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
b690e96c JB |
8663 | }; |
8664 | ||
8665 | static void intel_init_quirks(struct drm_device *dev) | |
8666 | { | |
8667 | struct pci_dev *d = dev->pdev; | |
8668 | int i; | |
8669 | ||
8670 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
8671 | struct intel_quirk *q = &intel_quirks[i]; | |
8672 | ||
8673 | if (d->device == q->device && | |
8674 | (d->subsystem_vendor == q->subsystem_vendor || | |
8675 | q->subsystem_vendor == PCI_ANY_ID) && | |
8676 | (d->subsystem_device == q->subsystem_device || | |
8677 | q->subsystem_device == PCI_ANY_ID)) | |
8678 | q->hook(dev); | |
8679 | } | |
5f85f176 EE |
8680 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
8681 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
8682 | intel_dmi_quirks[i].hook(dev); | |
8683 | } | |
b690e96c JB |
8684 | } |
8685 | ||
9cce37f4 JB |
8686 | /* Disable the VGA plane that we never use */ |
8687 | static void i915_disable_vga(struct drm_device *dev) | |
8688 | { | |
8689 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8690 | u8 sr1; | |
766aa1c4 | 8691 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 JB |
8692 | |
8693 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
3fdcf431 | 8694 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
8695 | sr1 = inb(VGA_SR_DATA); |
8696 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
8697 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
8698 | udelay(300); | |
8699 | ||
8700 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
8701 | POSTING_READ(vga_reg); | |
8702 | } | |
8703 | ||
f817586c DV |
8704 | void intel_modeset_init_hw(struct drm_device *dev) |
8705 | { | |
fa42e23c | 8706 | intel_init_power_well(dev); |
0232e927 | 8707 | |
a8f78b58 ED |
8708 | intel_prepare_ddi(dev); |
8709 | ||
f817586c DV |
8710 | intel_init_clock_gating(dev); |
8711 | ||
79f5b2c7 | 8712 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 8713 | intel_enable_gt_powersave(dev); |
79f5b2c7 | 8714 | mutex_unlock(&dev->struct_mutex); |
f817586c DV |
8715 | } |
8716 | ||
79e53945 JB |
8717 | void intel_modeset_init(struct drm_device *dev) |
8718 | { | |
652c393a | 8719 | struct drm_i915_private *dev_priv = dev->dev_private; |
b840d907 | 8720 | int i, ret; |
79e53945 JB |
8721 | |
8722 | drm_mode_config_init(dev); | |
8723 | ||
8724 | dev->mode_config.min_width = 0; | |
8725 | dev->mode_config.min_height = 0; | |
8726 | ||
019d96cb DA |
8727 | dev->mode_config.preferred_depth = 24; |
8728 | dev->mode_config.prefer_shadow = 1; | |
8729 | ||
e6ecefaa | 8730 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 8731 | |
b690e96c JB |
8732 | intel_init_quirks(dev); |
8733 | ||
1fa61106 ED |
8734 | intel_init_pm(dev); |
8735 | ||
e70236a8 JB |
8736 | intel_init_display(dev); |
8737 | ||
a6c45cf0 CW |
8738 | if (IS_GEN2(dev)) { |
8739 | dev->mode_config.max_width = 2048; | |
8740 | dev->mode_config.max_height = 2048; | |
8741 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
8742 | dev->mode_config.max_width = 4096; |
8743 | dev->mode_config.max_height = 4096; | |
79e53945 | 8744 | } else { |
a6c45cf0 CW |
8745 | dev->mode_config.max_width = 8192; |
8746 | dev->mode_config.max_height = 8192; | |
79e53945 | 8747 | } |
5d4545ae | 8748 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 8749 | |
28c97730 | 8750 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
a3524f1b | 8751 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
79e53945 | 8752 | |
a3524f1b | 8753 | for (i = 0; i < dev_priv->num_pipe; i++) { |
79e53945 | 8754 | intel_crtc_init(dev, i); |
00c2064b JB |
8755 | ret = intel_plane_init(dev, i); |
8756 | if (ret) | |
8757 | DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); | |
79e53945 JB |
8758 | } |
8759 | ||
79f689aa | 8760 | intel_cpu_pll_init(dev); |
ee7b9f93 JB |
8761 | intel_pch_pll_init(dev); |
8762 | ||
9cce37f4 JB |
8763 | /* Just disable it once at startup */ |
8764 | i915_disable_vga(dev); | |
79e53945 | 8765 | intel_setup_outputs(dev); |
11be49eb CW |
8766 | |
8767 | /* Just in case the BIOS is doing something questionable. */ | |
8768 | intel_disable_fbc(dev); | |
2c7111db CW |
8769 | } |
8770 | ||
24929352 DV |
8771 | static void |
8772 | intel_connector_break_all_links(struct intel_connector *connector) | |
8773 | { | |
8774 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
8775 | connector->base.encoder = NULL; | |
8776 | connector->encoder->connectors_active = false; | |
8777 | connector->encoder->base.crtc = NULL; | |
8778 | } | |
8779 | ||
7fad798e DV |
8780 | static void intel_enable_pipe_a(struct drm_device *dev) |
8781 | { | |
8782 | struct intel_connector *connector; | |
8783 | struct drm_connector *crt = NULL; | |
8784 | struct intel_load_detect_pipe load_detect_temp; | |
8785 | ||
8786 | /* We can't just switch on the pipe A, we need to set things up with a | |
8787 | * proper mode and output configuration. As a gross hack, enable pipe A | |
8788 | * by enabling the load detect pipe once. */ | |
8789 | list_for_each_entry(connector, | |
8790 | &dev->mode_config.connector_list, | |
8791 | base.head) { | |
8792 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
8793 | crt = &connector->base; | |
8794 | break; | |
8795 | } | |
8796 | } | |
8797 | ||
8798 | if (!crt) | |
8799 | return; | |
8800 | ||
8801 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) | |
8802 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
8803 | ||
652c393a | 8804 | |
7fad798e DV |
8805 | } |
8806 | ||
fa555837 DV |
8807 | static bool |
8808 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
8809 | { | |
8810 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
8811 | u32 reg, val; | |
8812 | ||
8813 | if (dev_priv->num_pipe == 1) | |
8814 | return true; | |
8815 | ||
8816 | reg = DSPCNTR(!crtc->plane); | |
8817 | val = I915_READ(reg); | |
8818 | ||
8819 | if ((val & DISPLAY_PLANE_ENABLE) && | |
8820 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
8821 | return false; | |
8822 | ||
8823 | return true; | |
8824 | } | |
8825 | ||
24929352 DV |
8826 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
8827 | { | |
8828 | struct drm_device *dev = crtc->base.dev; | |
8829 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 8830 | u32 reg; |
24929352 | 8831 | |
24929352 | 8832 | /* Clear any frame start delays used for debugging left by the BIOS */ |
702e7a56 | 8833 | reg = PIPECONF(crtc->cpu_transcoder); |
24929352 DV |
8834 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
8835 | ||
8836 | /* We need to sanitize the plane -> pipe mapping first because this will | |
fa555837 DV |
8837 | * disable the crtc (and hence change the state) if it is wrong. Note |
8838 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
8839 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
8840 | struct intel_connector *connector; |
8841 | bool plane; | |
8842 | ||
24929352 DV |
8843 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
8844 | crtc->base.base.id); | |
8845 | ||
8846 | /* Pipe has the wrong plane attached and the plane is active. | |
8847 | * Temporarily change the plane mapping and disable everything | |
8848 | * ... */ | |
8849 | plane = crtc->plane; | |
8850 | crtc->plane = !plane; | |
8851 | dev_priv->display.crtc_disable(&crtc->base); | |
8852 | crtc->plane = plane; | |
8853 | ||
8854 | /* ... and break all links. */ | |
8855 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
8856 | base.head) { | |
8857 | if (connector->encoder->base.crtc != &crtc->base) | |
8858 | continue; | |
8859 | ||
8860 | intel_connector_break_all_links(connector); | |
8861 | } | |
8862 | ||
8863 | WARN_ON(crtc->active); | |
8864 | crtc->base.enabled = false; | |
8865 | } | |
24929352 | 8866 | |
7fad798e DV |
8867 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
8868 | crtc->pipe == PIPE_A && !crtc->active) { | |
8869 | /* BIOS forgot to enable pipe A, this mostly happens after | |
8870 | * resume. Force-enable the pipe to fix this, the update_dpms | |
8871 | * call below we restore the pipe to the right state, but leave | |
8872 | * the required bits on. */ | |
8873 | intel_enable_pipe_a(dev); | |
8874 | } | |
8875 | ||
24929352 DV |
8876 | /* Adjust the state of the output pipe according to whether we |
8877 | * have active connectors/encoders. */ | |
8878 | intel_crtc_update_dpms(&crtc->base); | |
8879 | ||
8880 | if (crtc->active != crtc->base.enabled) { | |
8881 | struct intel_encoder *encoder; | |
8882 | ||
8883 | /* This can happen either due to bugs in the get_hw_state | |
8884 | * functions or because the pipe is force-enabled due to the | |
8885 | * pipe A quirk. */ | |
8886 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
8887 | crtc->base.base.id, | |
8888 | crtc->base.enabled ? "enabled" : "disabled", | |
8889 | crtc->active ? "enabled" : "disabled"); | |
8890 | ||
8891 | crtc->base.enabled = crtc->active; | |
8892 | ||
8893 | /* Because we only establish the connector -> encoder -> | |
8894 | * crtc links if something is active, this means the | |
8895 | * crtc is now deactivated. Break the links. connector | |
8896 | * -> encoder links are only establish when things are | |
8897 | * actually up, hence no need to break them. */ | |
8898 | WARN_ON(crtc->active); | |
8899 | ||
8900 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
8901 | WARN_ON(encoder->connectors_active); | |
8902 | encoder->base.crtc = NULL; | |
8903 | } | |
8904 | } | |
8905 | } | |
8906 | ||
8907 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
8908 | { | |
8909 | struct intel_connector *connector; | |
8910 | struct drm_device *dev = encoder->base.dev; | |
8911 | ||
8912 | /* We need to check both for a crtc link (meaning that the | |
8913 | * encoder is active and trying to read from a pipe) and the | |
8914 | * pipe itself being active. */ | |
8915 | bool has_active_crtc = encoder->base.crtc && | |
8916 | to_intel_crtc(encoder->base.crtc)->active; | |
8917 | ||
8918 | if (encoder->connectors_active && !has_active_crtc) { | |
8919 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
8920 | encoder->base.base.id, | |
8921 | drm_get_encoder_name(&encoder->base)); | |
8922 | ||
8923 | /* Connector is active, but has no active pipe. This is | |
8924 | * fallout from our resume register restoring. Disable | |
8925 | * the encoder manually again. */ | |
8926 | if (encoder->base.crtc) { | |
8927 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
8928 | encoder->base.base.id, | |
8929 | drm_get_encoder_name(&encoder->base)); | |
8930 | encoder->disable(encoder); | |
8931 | } | |
8932 | ||
8933 | /* Inconsistent output/port/pipe state happens presumably due to | |
8934 | * a bug in one of the get_hw_state functions. Or someplace else | |
8935 | * in our code, like the register restore mess on resume. Clamp | |
8936 | * things to off as a safer default. */ | |
8937 | list_for_each_entry(connector, | |
8938 | &dev->mode_config.connector_list, | |
8939 | base.head) { | |
8940 | if (connector->encoder != encoder) | |
8941 | continue; | |
8942 | ||
8943 | intel_connector_break_all_links(connector); | |
8944 | } | |
8945 | } | |
8946 | /* Enabled encoders without active connectors will be fixed in | |
8947 | * the crtc fixup. */ | |
8948 | } | |
8949 | ||
44cec740 | 8950 | void i915_redisable_vga(struct drm_device *dev) |
0fde901f KM |
8951 | { |
8952 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 8953 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f KM |
8954 | |
8955 | if (I915_READ(vga_reg) != VGA_DISP_DISABLE) { | |
8956 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
209d5211 | 8957 | i915_disable_vga(dev); |
0fde901f KM |
8958 | } |
8959 | } | |
8960 | ||
24929352 DV |
8961 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm |
8962 | * and i915 state tracking structures. */ | |
45e2b5f6 DV |
8963 | void intel_modeset_setup_hw_state(struct drm_device *dev, |
8964 | bool force_restore) | |
24929352 DV |
8965 | { |
8966 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8967 | enum pipe pipe; | |
8968 | u32 tmp; | |
8969 | struct intel_crtc *crtc; | |
8970 | struct intel_encoder *encoder; | |
8971 | struct intel_connector *connector; | |
8972 | ||
affa9354 | 8973 | if (HAS_DDI(dev)) { |
e28d54cb PZ |
8974 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
8975 | ||
8976 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
8977 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
8978 | case TRANS_DDI_EDP_INPUT_A_ON: | |
8979 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
8980 | pipe = PIPE_A; | |
8981 | break; | |
8982 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
8983 | pipe = PIPE_B; | |
8984 | break; | |
8985 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
8986 | pipe = PIPE_C; | |
8987 | break; | |
8988 | } | |
8989 | ||
8990 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
8991 | crtc->cpu_transcoder = TRANSCODER_EDP; | |
8992 | ||
8993 | DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n", | |
8994 | pipe_name(pipe)); | |
8995 | } | |
8996 | } | |
8997 | ||
24929352 DV |
8998 | for_each_pipe(pipe) { |
8999 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
9000 | ||
702e7a56 | 9001 | tmp = I915_READ(PIPECONF(crtc->cpu_transcoder)); |
24929352 DV |
9002 | if (tmp & PIPECONF_ENABLE) |
9003 | crtc->active = true; | |
9004 | else | |
9005 | crtc->active = false; | |
9006 | ||
9007 | crtc->base.enabled = crtc->active; | |
9008 | ||
9009 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
9010 | crtc->base.base.id, | |
9011 | crtc->active ? "enabled" : "disabled"); | |
9012 | } | |
9013 | ||
affa9354 | 9014 | if (HAS_DDI(dev)) |
6441ab5f PZ |
9015 | intel_ddi_setup_hw_pll_state(dev); |
9016 | ||
24929352 DV |
9017 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9018 | base.head) { | |
9019 | pipe = 0; | |
9020 | ||
9021 | if (encoder->get_hw_state(encoder, &pipe)) { | |
9022 | encoder->base.crtc = | |
9023 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
9024 | } else { | |
9025 | encoder->base.crtc = NULL; | |
9026 | } | |
9027 | ||
9028 | encoder->connectors_active = false; | |
9029 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", | |
9030 | encoder->base.base.id, | |
9031 | drm_get_encoder_name(&encoder->base), | |
9032 | encoder->base.crtc ? "enabled" : "disabled", | |
9033 | pipe); | |
9034 | } | |
9035 | ||
9036 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9037 | base.head) { | |
9038 | if (connector->get_hw_state(connector)) { | |
9039 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
9040 | connector->encoder->connectors_active = true; | |
9041 | connector->base.encoder = &connector->encoder->base; | |
9042 | } else { | |
9043 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
9044 | connector->base.encoder = NULL; | |
9045 | } | |
9046 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
9047 | connector->base.base.id, | |
9048 | drm_get_connector_name(&connector->base), | |
9049 | connector->base.encoder ? "enabled" : "disabled"); | |
9050 | } | |
9051 | ||
9052 | /* HW state is read out, now we need to sanitize this mess. */ | |
9053 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9054 | base.head) { | |
9055 | intel_sanitize_encoder(encoder); | |
9056 | } | |
9057 | ||
9058 | for_each_pipe(pipe) { | |
9059 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
9060 | intel_sanitize_crtc(crtc); | |
9061 | } | |
9a935856 | 9062 | |
45e2b5f6 DV |
9063 | if (force_restore) { |
9064 | for_each_pipe(pipe) { | |
c0c36b94 | 9065 | intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]); |
45e2b5f6 | 9066 | } |
0fde901f KM |
9067 | |
9068 | i915_redisable_vga(dev); | |
45e2b5f6 DV |
9069 | } else { |
9070 | intel_modeset_update_staged_output_state(dev); | |
9071 | } | |
8af6cf88 DV |
9072 | |
9073 | intel_modeset_check_state(dev); | |
2e938892 DV |
9074 | |
9075 | drm_mode_config_reset(dev); | |
2c7111db CW |
9076 | } |
9077 | ||
9078 | void intel_modeset_gem_init(struct drm_device *dev) | |
9079 | { | |
1833b134 | 9080 | intel_modeset_init_hw(dev); |
02e792fb DV |
9081 | |
9082 | intel_setup_overlay(dev); | |
24929352 | 9083 | |
45e2b5f6 | 9084 | intel_modeset_setup_hw_state(dev, false); |
79e53945 JB |
9085 | } |
9086 | ||
9087 | void intel_modeset_cleanup(struct drm_device *dev) | |
9088 | { | |
652c393a JB |
9089 | struct drm_i915_private *dev_priv = dev->dev_private; |
9090 | struct drm_crtc *crtc; | |
9091 | struct intel_crtc *intel_crtc; | |
9092 | ||
f87ea761 | 9093 | drm_kms_helper_poll_fini(dev); |
652c393a JB |
9094 | mutex_lock(&dev->struct_mutex); |
9095 | ||
723bfd70 JB |
9096 | intel_unregister_dsm_handler(); |
9097 | ||
9098 | ||
652c393a JB |
9099 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
9100 | /* Skip inactive CRTCs */ | |
9101 | if (!crtc->fb) | |
9102 | continue; | |
9103 | ||
9104 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 9105 | intel_increase_pllclock(crtc); |
652c393a JB |
9106 | } |
9107 | ||
973d04f9 | 9108 | intel_disable_fbc(dev); |
e70236a8 | 9109 | |
8090c6b9 | 9110 | intel_disable_gt_powersave(dev); |
0cdab21f | 9111 | |
930ebb46 DV |
9112 | ironlake_teardown_rc6(dev); |
9113 | ||
57f350b6 JB |
9114 | if (IS_VALLEYVIEW(dev)) |
9115 | vlv_init_dpio(dev); | |
9116 | ||
69341a5e KH |
9117 | mutex_unlock(&dev->struct_mutex); |
9118 | ||
6c0d9350 DV |
9119 | /* Disable the irq before mode object teardown, for the irq might |
9120 | * enqueue unpin/hotplug work. */ | |
9121 | drm_irq_uninstall(dev); | |
9122 | cancel_work_sync(&dev_priv->hotplug_work); | |
c6a828d3 | 9123 | cancel_work_sync(&dev_priv->rps.work); |
6c0d9350 | 9124 | |
1630fe75 CW |
9125 | /* flush any delayed tasks or pending work */ |
9126 | flush_scheduled_work(); | |
9127 | ||
79e53945 | 9128 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
9129 | |
9130 | intel_cleanup_overlay(dev); | |
79e53945 JB |
9131 | } |
9132 | ||
f1c79df3 ZW |
9133 | /* |
9134 | * Return which encoder is currently attached for connector. | |
9135 | */ | |
df0e9248 | 9136 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 9137 | { |
df0e9248 CW |
9138 | return &intel_attached_encoder(connector)->base; |
9139 | } | |
f1c79df3 | 9140 | |
df0e9248 CW |
9141 | void intel_connector_attach_encoder(struct intel_connector *connector, |
9142 | struct intel_encoder *encoder) | |
9143 | { | |
9144 | connector->encoder = encoder; | |
9145 | drm_mode_connector_attach_encoder(&connector->base, | |
9146 | &encoder->base); | |
79e53945 | 9147 | } |
28d52043 DA |
9148 | |
9149 | /* | |
9150 | * set vga decode state - true == enable VGA decode | |
9151 | */ | |
9152 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
9153 | { | |
9154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9155 | u16 gmch_ctrl; | |
9156 | ||
9157 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
9158 | if (state) | |
9159 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
9160 | else | |
9161 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
9162 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
9163 | return 0; | |
9164 | } | |
c4a1d9e4 CW |
9165 | |
9166 | #ifdef CONFIG_DEBUG_FS | |
9167 | #include <linux/seq_file.h> | |
9168 | ||
9169 | struct intel_display_error_state { | |
9170 | struct intel_cursor_error_state { | |
9171 | u32 control; | |
9172 | u32 position; | |
9173 | u32 base; | |
9174 | u32 size; | |
52331309 | 9175 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
9176 | |
9177 | struct intel_pipe_error_state { | |
9178 | u32 conf; | |
9179 | u32 source; | |
9180 | ||
9181 | u32 htotal; | |
9182 | u32 hblank; | |
9183 | u32 hsync; | |
9184 | u32 vtotal; | |
9185 | u32 vblank; | |
9186 | u32 vsync; | |
52331309 | 9187 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
9188 | |
9189 | struct intel_plane_error_state { | |
9190 | u32 control; | |
9191 | u32 stride; | |
9192 | u32 size; | |
9193 | u32 pos; | |
9194 | u32 addr; | |
9195 | u32 surface; | |
9196 | u32 tile_offset; | |
52331309 | 9197 | } plane[I915_MAX_PIPES]; |
c4a1d9e4 CW |
9198 | }; |
9199 | ||
9200 | struct intel_display_error_state * | |
9201 | intel_display_capture_error_state(struct drm_device *dev) | |
9202 | { | |
0206e353 | 9203 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 | 9204 | struct intel_display_error_state *error; |
702e7a56 | 9205 | enum transcoder cpu_transcoder; |
c4a1d9e4 CW |
9206 | int i; |
9207 | ||
9208 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
9209 | if (error == NULL) | |
9210 | return NULL; | |
9211 | ||
52331309 | 9212 | for_each_pipe(i) { |
702e7a56 PZ |
9213 | cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i); |
9214 | ||
c4a1d9e4 CW |
9215 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
9216 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
9217 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
9218 | ||
9219 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
9220 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
9221 | error->plane[i].size = I915_READ(DSPSIZE(i)); | |
0206e353 | 9222 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
c4a1d9e4 CW |
9223 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
9224 | if (INTEL_INFO(dev)->gen >= 4) { | |
9225 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
9226 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
9227 | } | |
9228 | ||
702e7a56 | 9229 | error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder)); |
c4a1d9e4 | 9230 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
fe2b8f9d PZ |
9231 | error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); |
9232 | error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
9233 | error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
9234 | error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
9235 | error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
9236 | error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
9237 | } |
9238 | ||
9239 | return error; | |
9240 | } | |
9241 | ||
9242 | void | |
9243 | intel_display_print_error_state(struct seq_file *m, | |
9244 | struct drm_device *dev, | |
9245 | struct intel_display_error_state *error) | |
9246 | { | |
52331309 | 9247 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
9248 | int i; |
9249 | ||
52331309 DL |
9250 | seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe); |
9251 | for_each_pipe(i) { | |
c4a1d9e4 CW |
9252 | seq_printf(m, "Pipe [%d]:\n", i); |
9253 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); | |
9254 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); | |
9255 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); | |
9256 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); | |
9257 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); | |
9258 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); | |
9259 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); | |
9260 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); | |
9261 | ||
9262 | seq_printf(m, "Plane [%d]:\n", i); | |
9263 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
9264 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
9265 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); | |
9266 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); | |
9267 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); | |
9268 | if (INTEL_INFO(dev)->gen >= 4) { | |
9269 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); | |
9270 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
9271 | } | |
9272 | ||
9273 | seq_printf(m, "Cursor [%d]:\n", i); | |
9274 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
9275 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); | |
9276 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
9277 | } | |
9278 | } | |
9279 | #endif |