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drm/i915: proper use of forcewake
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
c1c7af60
JB		 27#include <linux/module.h>
28#include <linux/input.h>
79e53945 29#include <linux/i2c.h>
7662c8bd 30#include <linux/kernel.h>
5a0e3ad6 31#include <linux/slab.h>
9cce37f4 32#include <linux/vgaarb.h>
79e53945
JB		 33#include "drmP.h"
34#include "intel_drv.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
e5510fac 37#include "i915_trace.h"
ab2c0672 38#include "drm_dp_helper.h"
79e53945
JB		 39
40#include "drm_crtc_helper.h"
41
32f9d658
ZW		 42#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
79e53945 44bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
7662c8bd 45static void intel_update_watermarks(struct drm_device *dev);
3dec0095 46static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 47static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 48
49typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59} intel_clock_t;
60
61typedef struct {
62 int min, max;
63} intel_range_t;
64
65typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68} intel_p2_t;
69
70#define INTEL_P2_NUM 2
d4906093
ML		 71typedef struct intel_limit intel_limit_t;
72struct intel_limit {
79e53945
JB		 73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
d4906093
ML		 75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77};
79e53945 78
2377b741
JB		 79/* FDI */
80#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
81
d4906093
ML		 82static bool
83intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
84 int target, int refclk, intel_clock_t *best_clock);
85static bool
86intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
87 int target, int refclk, intel_clock_t *best_clock);
79e53945 88
a4fc5ed6
KP		 89static bool
90intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
91 int target, int refclk, intel_clock_t *best_clock);
5eb08b69 92static bool
f2b115e6
AJ		 93intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *best_clock);
a4fc5ed6 95
021357ac
CW		 96static inline u32 /* units of 100MHz */
97intel_fdi_link_freq(struct drm_device *dev)
98{
8b99e68c
CW		 99 if (IS_GEN5(dev)) {
100 struct drm_i915_private *dev_priv = dev->dev_private;
101 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
102 } else
103 return 27;
021357ac
CW		 104}
105
e4b36699 106static const intel_limit_t intel_limits_i8xx_dvo = {
273e27ca
EA		 107 .dot = { .min = 25000, .max = 350000 },
108 .vco = { .min = 930000, .max = 1400000 },
109 .n = { .min = 3, .max = 16 },
110 .m = { .min = 96, .max = 140 },
111 .m1 = { .min = 18, .max = 26 },
112 .m2 = { .min = 6, .max = 16 },
113 .p = { .min = 4, .max = 128 },
114 .p1 = { .min = 2, .max = 33 },
115 .p2 = { .dot_limit = 165000,
116 .p2_slow = 4, .p2_fast = 2 },
d4906093 117 .find_pll = intel_find_best_PLL,
e4b36699
KP		 118};
119
120static const intel_limit_t intel_limits_i8xx_lvds = {
273e27ca
EA		 121 .dot = { .min = 25000, .max = 350000 },
122 .vco = { .min = 930000, .max = 1400000 },
123 .n = { .min = 3, .max = 16 },
124 .m = { .min = 96, .max = 140 },
125 .m1 = { .min = 18, .max = 26 },
126 .m2 = { .min = 6, .max = 16 },
127 .p = { .min = 4, .max = 128 },
128 .p1 = { .min = 1, .max = 6 },
129 .p2 = { .dot_limit = 165000,
130 .p2_slow = 14, .p2_fast = 7 },
d4906093 131 .find_pll = intel_find_best_PLL,
e4b36699 132};
273e27ca 133
e4b36699 134static const intel_limit_t intel_limits_i9xx_sdvo = {
273e27ca
EA		 135 .dot = { .min = 20000, .max = 400000 },
136 .vco = { .min = 1400000, .max = 2800000 },
137 .n = { .min = 1, .max = 6 },
138 .m = { .min = 70, .max = 120 },
139 .m1 = { .min = 10, .max = 22 },
140 .m2 = { .min = 5, .max = 9 },
141 .p = { .min = 5, .max = 80 },
142 .p1 = { .min = 1, .max = 8 },
143 .p2 = { .dot_limit = 200000,
144 .p2_slow = 10, .p2_fast = 5 },
d4906093 145 .find_pll = intel_find_best_PLL,
e4b36699
KP		 146};
147
148static const intel_limit_t intel_limits_i9xx_lvds = {
273e27ca
EA		 149 .dot = { .min = 20000, .max = 400000 },
150 .vco = { .min = 1400000, .max = 2800000 },
151 .n = { .min = 1, .max = 6 },
152 .m = { .min = 70, .max = 120 },
153 .m1 = { .min = 10, .max = 22 },
154 .m2 = { .min = 5, .max = 9 },
155 .p = { .min = 7, .max = 98 },
156 .p1 = { .min = 1, .max = 8 },
157 .p2 = { .dot_limit = 112000,
158 .p2_slow = 14, .p2_fast = 7 },
d4906093 159 .find_pll = intel_find_best_PLL,
e4b36699
KP		 160};
161
273e27ca 162
e4b36699 163static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 164 .dot = { .min = 25000, .max = 270000 },
165 .vco = { .min = 1750000, .max = 3500000},
166 .n = { .min = 1, .max = 4 },
167 .m = { .min = 104, .max = 138 },
168 .m1 = { .min = 17, .max = 23 },
169 .m2 = { .min = 5, .max = 11 },
170 .p = { .min = 10, .max = 30 },
171 .p1 = { .min = 1, .max = 3},
172 .p2 = { .dot_limit = 270000,
173 .p2_slow = 10,
174 .p2_fast = 10
044c7c41 175 },
d4906093 176 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 177};
178
179static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 180 .dot = { .min = 22000, .max = 400000 },
181 .vco = { .min = 1750000, .max = 3500000},
182 .n = { .min = 1, .max = 4 },
183 .m = { .min = 104, .max = 138 },
184 .m1 = { .min = 16, .max = 23 },
185 .m2 = { .min = 5, .max = 11 },
186 .p = { .min = 5, .max = 80 },
187 .p1 = { .min = 1, .max = 8},
188 .p2 = { .dot_limit = 165000,
189 .p2_slow = 10, .p2_fast = 5 },
d4906093 190 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 191};
192
193static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 194 .dot = { .min = 20000, .max = 115000 },
195 .vco = { .min = 1750000, .max = 3500000 },
196 .n = { .min = 1, .max = 3 },
197 .m = { .min = 104, .max = 138 },
198 .m1 = { .min = 17, .max = 23 },
199 .m2 = { .min = 5, .max = 11 },
200 .p = { .min = 28, .max = 112 },
201 .p1 = { .min = 2, .max = 8 },
202 .p2 = { .dot_limit = 0,
203 .p2_slow = 14, .p2_fast = 14
044c7c41 204 },
d4906093 205 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 206};
207
208static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 209 .dot = { .min = 80000, .max = 224000 },
210 .vco = { .min = 1750000, .max = 3500000 },
211 .n = { .min = 1, .max = 3 },
212 .m = { .min = 104, .max = 138 },
213 .m1 = { .min = 17, .max = 23 },
214 .m2 = { .min = 5, .max = 11 },
215 .p = { .min = 14, .max = 42 },
216 .p1 = { .min = 2, .max = 6 },
217 .p2 = { .dot_limit = 0,
218 .p2_slow = 7, .p2_fast = 7
044c7c41 219 },
d4906093 220 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 221};
222
223static const intel_limit_t intel_limits_g4x_display_port = {
273e27ca
EA		 224 .dot = { .min = 161670, .max = 227000 },
225 .vco = { .min = 1750000, .max = 3500000},
226 .n = { .min = 1, .max = 2 },
227 .m = { .min = 97, .max = 108 },
228 .m1 = { .min = 0x10, .max = 0x12 },
229 .m2 = { .min = 0x05, .max = 0x06 },
230 .p = { .min = 10, .max = 20 },
231 .p1 = { .min = 1, .max = 2},
232 .p2 = { .dot_limit = 0,
233 .p2_slow = 10, .p2_fast = 10 },
a4fc5ed6 234 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 235};
236
f2b115e6 237static const intel_limit_t intel_limits_pineview_sdvo = {
273e27ca
EA		 238 .dot = { .min = 20000, .max = 400000},
239 .vco = { .min = 1700000, .max = 3500000 },
240 /* Pineview's Ncounter is a ring counter */
241 .n = { .min = 3, .max = 6 },
242 .m = { .min = 2, .max = 256 },
243 /* Pineview only has one combined m divider, which we treat as m2. */
244 .m1 = { .min = 0, .max = 0 },
245 .m2 = { .min = 0, .max = 254 },
246 .p = { .min = 5, .max = 80 },
247 .p1 = { .min = 1, .max = 8 },
248 .p2 = { .dot_limit = 200000,
249 .p2_slow = 10, .p2_fast = 5 },
6115707b 250 .find_pll = intel_find_best_PLL,
e4b36699
KP		 251};
252
f2b115e6 253static const intel_limit_t intel_limits_pineview_lvds = {
273e27ca
EA		 254 .dot = { .min = 20000, .max = 400000 },
255 .vco = { .min = 1700000, .max = 3500000 },
256 .n = { .min = 3, .max = 6 },
257 .m = { .min = 2, .max = 256 },
258 .m1 = { .min = 0, .max = 0 },
259 .m2 = { .min = 0, .max = 254 },
260 .p = { .min = 7, .max = 112 },
261 .p1 = { .min = 1, .max = 8 },
262 .p2 = { .dot_limit = 112000,
263 .p2_slow = 14, .p2_fast = 14 },
6115707b 264 .find_pll = intel_find_best_PLL,
e4b36699
KP		 265};
266
273e27ca
EA		 267/* Ironlake / Sandybridge
268 *
269 * We calculate clock using (register_value + 2) for N/M1/M2, so here
270 * the range value for them is (actual_value - 2).
271 */
b91ad0ec 272static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 5 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 10, .p2_fast = 5 },
4547668a 283 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 284};
285
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 3 },
290 .m = { .min = 79, .max = 118 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
294 .p1 = { .min = 2, .max = 8 },
295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297 .find_pll = intel_g4x_find_best_PLL,
298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 127 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 56 },
308 .p1 = { .min = 2, .max = 8 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 311 .find_pll = intel_g4x_find_best_PLL,
312};
313
273e27ca 314/* LVDS 100mhz refclk limits. */
b91ad0ec 315static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 316 .dot = { .min = 25000, .max = 350000 },
317 .vco = { .min = 1760000, .max = 3510000 },
318 .n = { .min = 1, .max = 2 },
319 .m = { .min = 79, .max = 126 },
320 .m1 = { .min = 12, .max = 22 },
321 .m2 = { .min = 5, .max = 9 },
322 .p = { .min = 28, .max = 112 },
323 .p1 = { .min = 2,.max = 8 },
324 .p2 = { .dot_limit = 225000,
325 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 326 .find_pll = intel_g4x_find_best_PLL,
327};
328
329static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 126 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 42 },
337 .p1 = { .min = 2,.max = 6 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 340 .find_pll = intel_g4x_find_best_PLL,
341};
342
343static const intel_limit_t intel_limits_ironlake_display_port = {
273e27ca
EA		 344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000},
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 81, .max = 90 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 10, .max = 20 },
351 .p1 = { .min = 1, .max = 2},
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 10, .p2_fast = 10 },
4547668a 354 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 355};
356
1b894b59
CW		 357static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
358 int refclk)
2c07245f 359{
b91ad0ec
ZW		 360 struct drm_device *dev = crtc->dev;
361 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 362 const intel_limit_t *limit;
b91ad0ec
ZW		 363
364 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 365 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
366 LVDS_CLKB_POWER_UP) {
367 /* LVDS dual channel */
1b894b59 368 if (refclk == 100000)
b91ad0ec
ZW		 369 limit = &intel_limits_ironlake_dual_lvds_100m;
370 else
371 limit = &intel_limits_ironlake_dual_lvds;
372 } else {
1b894b59 373 if (refclk == 100000)
b91ad0ec
ZW		 374 limit = &intel_limits_ironlake_single_lvds_100m;
375 else
376 limit = &intel_limits_ironlake_single_lvds;
377 }
378 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 379 HAS_eDP)
380 limit = &intel_limits_ironlake_display_port;
2c07245f 381 else
b91ad0ec 382 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 383
384 return limit;
385}
386
044c7c41
ML		 387static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
388{
389 struct drm_device *dev = crtc->dev;
390 struct drm_i915_private *dev_priv = dev->dev_private;
391 const intel_limit_t *limit;
392
393 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
394 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
395 LVDS_CLKB_POWER_UP)
396 /* LVDS with dual channel */
e4b36699 397 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 398 else
399 /* LVDS with dual channel */
e4b36699 400 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 401 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
402 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 403 limit = &intel_limits_g4x_hdmi;
044c7c41 404 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 405 limit = &intel_limits_g4x_sdvo;
a4fc5ed6 406 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 407 limit = &intel_limits_g4x_display_port;
044c7c41 408 } else /* The option is for other outputs */
e4b36699 409 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 410
411 return limit;
412}
413
1b894b59 414static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 415{
416 struct drm_device *dev = crtc->dev;
417 const intel_limit_t *limit;
418
bad720ff 419 if (HAS_PCH_SPLIT(dev))
1b894b59 420 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 421 else if (IS_G4X(dev)) {
044c7c41 422 limit = intel_g4x_limit(crtc);
f2b115e6 423 } else if (IS_PINEVIEW(dev)) {
2177832f 424 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 425 limit = &intel_limits_pineview_lvds;
2177832f 426 else
f2b115e6 427 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 428 } else if (!IS_GEN2(dev)) {
429 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
430 limit = &intel_limits_i9xx_lvds;
431 else
432 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 433 } else {
434 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 435 limit = &intel_limits_i8xx_lvds;
79e53945 436 else
e4b36699 437 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 438 }
439 return limit;
440}
441
f2b115e6
AJ		 442/* m1 is reserved as 0 in Pineview, n is a ring counter */
443static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 444{
2177832f
SL		 445 clock->m = clock->m2 + 2;
446 clock->p = clock->p1 * clock->p2;
447 clock->vco = refclk * clock->m / clock->n;
448 clock->dot = clock->vco / clock->p;
449}
450
451static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
452{
f2b115e6
AJ		 453 if (IS_PINEVIEW(dev)) {
454 pineview_clock(refclk, clock);
2177832f
SL		 455 return;
456 }
79e53945
JB		 457 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
458 clock->p = clock->p1 * clock->p2;
459 clock->vco = refclk * clock->m / (clock->n + 2);
460 clock->dot = clock->vco / clock->p;
461}
462
79e53945
JB		 463/**
464 * Returns whether any output on the specified pipe is of the specified type
465 */
4ef69c7a 466bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 467{
4ef69c7a
CW		 468 struct drm_device *dev = crtc->dev;
469 struct drm_mode_config *mode_config = &dev->mode_config;
470 struct intel_encoder *encoder;
471
472 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
473 if (encoder->base.crtc == crtc && encoder->type == type)
474 return true;
475
476 return false;
79e53945
JB		 477}
478
7c04d1d9 479#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 480/**
481 * Returns whether the given set of divisors are valid for a given refclk with
482 * the given connectors.
483 */
484
1b894b59
CW		 485static bool intel_PLL_is_valid(struct drm_device *dev,
486 const intel_limit_t *limit,
487 const intel_clock_t *clock)
79e53945 488{
79e53945
JB		 489 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
490 INTELPllInvalid ("p1 out of range\n");
491 if (clock->p < limit->p.min || limit->p.max < clock->p)
492 INTELPllInvalid ("p out of range\n");
493 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
494 INTELPllInvalid ("m2 out of range\n");
495 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
496 INTELPllInvalid ("m1 out of range\n");
f2b115e6 497 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
79e53945
JB		 498 INTELPllInvalid ("m1 <= m2\n");
499 if (clock->m < limit->m.min || limit->m.max < clock->m)
500 INTELPllInvalid ("m out of range\n");
501 if (clock->n < limit->n.min || limit->n.max < clock->n)
502 INTELPllInvalid ("n out of range\n");
503 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
504 INTELPllInvalid ("vco out of range\n");
505 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
506 * connector, etc., rather than just a single range.
507 */
508 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
509 INTELPllInvalid ("dot out of range\n");
510
511 return true;
512}
513
d4906093
ML		 514static bool
515intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
516 int target, int refclk, intel_clock_t *best_clock)
517
79e53945
JB		 518{
519 struct drm_device *dev = crtc->dev;
520 struct drm_i915_private *dev_priv = dev->dev_private;
521 intel_clock_t clock;
79e53945
JB		 522 int err = target;
523
bc5e5718 524 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 525 (I915_READ(LVDS)) != 0) {
79e53945
JB		 526 /*
527 * For LVDS, if the panel is on, just rely on its current
528 * settings for dual-channel. We haven't figured out how to
529 * reliably set up different single/dual channel state, if we
530 * even can.
531 */
532 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
533 LVDS_CLKB_POWER_UP)
534 clock.p2 = limit->p2.p2_fast;
535 else
536 clock.p2 = limit->p2.p2_slow;
537 } else {
538 if (target < limit->p2.dot_limit)
539 clock.p2 = limit->p2.p2_slow;
540 else
541 clock.p2 = limit->p2.p2_fast;
542 }
543
544 memset (best_clock, 0, sizeof (*best_clock));
545
42158660
ZY		 546 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
547 clock.m1++) {
548 for (clock.m2 = limit->m2.min;
549 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 550 /* m1 is always 0 in Pineview */
551 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 552 break;
553 for (clock.n = limit->n.min;
554 clock.n <= limit->n.max; clock.n++) {
555 for (clock.p1 = limit->p1.min;
556 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 557 int this_err;
558
2177832f 559 intel_clock(dev, refclk, &clock);
1b894b59
CW		 560 if (!intel_PLL_is_valid(dev, limit,
561 &clock))
79e53945
JB		 562 continue;
563
564 this_err = abs(clock.dot - target);
565 if (this_err < err) {
566 *best_clock = clock;
567 err = this_err;
568 }
569 }
570 }
571 }
572 }
573
574 return (err != target);
575}
576
d4906093
ML		 577static bool
578intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
579 int target, int refclk, intel_clock_t *best_clock)
580{
581 struct drm_device *dev = crtc->dev;
582 struct drm_i915_private *dev_priv = dev->dev_private;
583 intel_clock_t clock;
584 int max_n;
585 bool found;
6ba770dc
AJ		 586 /* approximately equals target * 0.00585 */
587 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 588 found = false;
589
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 591 int lvds_reg;
592
c619eed4 593 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 594 lvds_reg = PCH_LVDS;
595 else
596 lvds_reg = LVDS;
597 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 598 LVDS_CLKB_POWER_UP)
599 clock.p2 = limit->p2.p2_fast;
600 else
601 clock.p2 = limit->p2.p2_slow;
602 } else {
603 if (target < limit->p2.dot_limit)
604 clock.p2 = limit->p2.p2_slow;
605 else
606 clock.p2 = limit->p2.p2_fast;
607 }
608
609 memset(best_clock, 0, sizeof(*best_clock));
610 max_n = limit->n.max;
f77f13e2 611 /* based on hardware requirement, prefer smaller n to precision */
d4906093 612 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 613 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 614 for (clock.m1 = limit->m1.max;
615 clock.m1 >= limit->m1.min; clock.m1--) {
616 for (clock.m2 = limit->m2.max;
617 clock.m2 >= limit->m2.min; clock.m2--) {
618 for (clock.p1 = limit->p1.max;
619 clock.p1 >= limit->p1.min; clock.p1--) {
620 int this_err;
621
2177832f 622 intel_clock(dev, refclk, &clock);
1b894b59
CW		 623 if (!intel_PLL_is_valid(dev, limit,
624 &clock))
d4906093 625 continue;
1b894b59
CW		 626
627 this_err = abs(clock.dot - target);
d4906093
ML		 628 if (this_err < err_most) {
629 *best_clock = clock;
630 err_most = this_err;
631 max_n = clock.n;
632 found = true;
633 }
634 }
635 }
636 }
637 }
2c07245f
ZW		 638 return found;
639}
640
5eb08b69 641static bool
f2b115e6
AJ		 642intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
643 int target, int refclk, intel_clock_t *best_clock)
5eb08b69
ZW		 644{
645 struct drm_device *dev = crtc->dev;
646 intel_clock_t clock;
4547668a 647
5eb08b69
ZW		 648 if (target < 200000) {
649 clock.n = 1;
650 clock.p1 = 2;
651 clock.p2 = 10;
652 clock.m1 = 12;
653 clock.m2 = 9;
654 } else {
655 clock.n = 2;
656 clock.p1 = 1;
657 clock.p2 = 10;
658 clock.m1 = 14;
659 clock.m2 = 8;
660 }
661 intel_clock(dev, refclk, &clock);
662 memcpy(best_clock, &clock, sizeof(intel_clock_t));
663 return true;
664}
665
a4fc5ed6
KP		 666/* DisplayPort has only two frequencies, 162MHz and 270MHz */
667static bool
668intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
669 int target, int refclk, intel_clock_t *best_clock)
670{
5eddb70b
CW		 671 intel_clock_t clock;
672 if (target < 200000) {
673 clock.p1 = 2;
674 clock.p2 = 10;
675 clock.n = 2;
676 clock.m1 = 23;
677 clock.m2 = 8;
678 } else {
679 clock.p1 = 1;
680 clock.p2 = 10;
681 clock.n = 1;
682 clock.m1 = 14;
683 clock.m2 = 2;
684 }
685 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
686 clock.p = (clock.p1 * clock.p2);
687 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
688 clock.vco = 0;
689 memcpy(best_clock, &clock, sizeof(intel_clock_t));
690 return true;
a4fc5ed6
KP		 691}
692
9d0498a2
JB		 693/**
694 * intel_wait_for_vblank - wait for vblank on a given pipe
695 * @dev: drm device
696 * @pipe: pipe to wait for
697 *
698 * Wait for vblank to occur on a given pipe. Needed for various bits of
699 * mode setting code.
700 */
701void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 702{
9d0498a2 703 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 704 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 705
300387c0
CW		 706 /* Clear existing vblank status. Note this will clear any other
707 * sticky status fields as well.
708 *
709 * This races with i915_driver_irq_handler() with the result
710 * that either function could miss a vblank event. Here it is not
711 * fatal, as we will either wait upon the next vblank interrupt or
712 * timeout. Generally speaking intel_wait_for_vblank() is only
713 * called during modeset at which time the GPU should be idle and
714 * should *not* be performing page flips and thus not waiting on
715 * vblanks...
716 * Currently, the result of us stealing a vblank from the irq
717 * handler is that a single frame will be skipped during swapbuffers.
718 */
719 I915_WRITE(pipestat_reg,
720 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
721
9d0498a2 722 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 723 if (wait_for(I915_READ(pipestat_reg) &
724 PIPE_VBLANK_INTERRUPT_STATUS,
725 50))
9d0498a2
JB		 726 DRM_DEBUG_KMS("vblank wait timed out\n");
727}
728
ab7ad7f6
KP		 729/*
730 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 731 * @dev: drm device
732 * @pipe: pipe to wait for
733 *
734 * After disabling a pipe, we can't wait for vblank in the usual way,
735 * spinning on the vblank interrupt status bit, since we won't actually
736 * see an interrupt when the pipe is disabled.
737 *
ab7ad7f6
KP		 738 * On Gen4 and above:
739 * wait for the pipe register state bit to turn off
740 *
741 * Otherwise:
742 * wait for the display line value to settle (it usually
743 * ends up stopping at the start of the next frame).
58e10eb9 744 *
9d0498a2 745 */
58e10eb9 746void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 747{
748 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 749
750 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 751 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 752
753 /* Wait for the Pipe State to go off */
58e10eb9
CW		 754 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
755 100))
ab7ad7f6
KP		 756 DRM_DEBUG_KMS("pipe_off wait timed out\n");
757 } else {
758 u32 last_line;
58e10eb9 759 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 760 unsigned long timeout = jiffies + msecs_to_jiffies(100);
761
762 /* Wait for the display line to settle */
763 do {
58e10eb9 764 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 765 mdelay(5);
58e10eb9 766 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 767 time_after(timeout, jiffies));
768 if (time_after(jiffies, timeout))
769 DRM_DEBUG_KMS("pipe_off wait timed out\n");
770 }
79e53945
JB		 771}
772
b24e7179
JB		 773static const char *state_string(bool enabled)
774{
775 return enabled ? "on" : "off";
776}
777
778/* Only for pre-ILK configs */
779static void assert_pll(struct drm_i915_private *dev_priv,
780 enum pipe pipe, bool state)
781{
782 int reg;
783 u32 val;
784 bool cur_state;
785
786 reg = DPLL(pipe);
787 val = I915_READ(reg);
788 cur_state = !!(val & DPLL_VCO_ENABLE);
789 WARN(cur_state != state,
790 "PLL state assertion failure (expected %s, current %s)\n",
791 state_string(state), state_string(cur_state));
792}
793#define assert_pll_enabled(d, p) assert_pll(d, p, true)
794#define assert_pll_disabled(d, p) assert_pll(d, p, false)
795
040484af
JB		 796/* For ILK+ */
797static void assert_pch_pll(struct drm_i915_private *dev_priv,
798 enum pipe pipe, bool state)
799{
800 int reg;
801 u32 val;
802 bool cur_state;
803
804 reg = PCH_DPLL(pipe);
805 val = I915_READ(reg);
806 cur_state = !!(val & DPLL_VCO_ENABLE);
807 WARN(cur_state != state,
808 "PCH PLL state assertion failure (expected %s, current %s)\n",
809 state_string(state), state_string(cur_state));
810}
811#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
812#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
813
814static void assert_fdi_tx(struct drm_i915_private *dev_priv,
815 enum pipe pipe, bool state)
816{
817 int reg;
818 u32 val;
819 bool cur_state;
820
821 reg = FDI_TX_CTL(pipe);
822 val = I915_READ(reg);
823 cur_state = !!(val & FDI_TX_ENABLE);
824 WARN(cur_state != state,
825 "FDI TX state assertion failure (expected %s, current %s)\n",
826 state_string(state), state_string(cur_state));
827}
828#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
829#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
830
831static void assert_fdi_rx(struct drm_i915_private *dev_priv,
832 enum pipe pipe, bool state)
833{
834 int reg;
835 u32 val;
836 bool cur_state;
837
838 reg = FDI_RX_CTL(pipe);
839 val = I915_READ(reg);
840 cur_state = !!(val & FDI_RX_ENABLE);
841 WARN(cur_state != state,
842 "FDI RX state assertion failure (expected %s, current %s)\n",
843 state_string(state), state_string(cur_state));
844}
845#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
846#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
847
848static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
849 enum pipe pipe)
850{
851 int reg;
852 u32 val;
853
854 /* ILK FDI PLL is always enabled */
855 if (dev_priv->info->gen == 5)
856 return;
857
858 reg = FDI_TX_CTL(pipe);
859 val = I915_READ(reg);
860 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
861}
862
863static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
864 enum pipe pipe)
865{
866 int reg;
867 u32 val;
868
869 reg = FDI_RX_CTL(pipe);
870 val = I915_READ(reg);
871 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
872}
873
ea0760cf
JB		 874static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
875 enum pipe pipe)
876{
877 int pp_reg, lvds_reg;
878 u32 val;
879 enum pipe panel_pipe = PIPE_A;
880 bool locked = locked;
881
882 if (HAS_PCH_SPLIT(dev_priv->dev)) {
883 pp_reg = PCH_PP_CONTROL;
884 lvds_reg = PCH_LVDS;
885 } else {
886 pp_reg = PP_CONTROL;
887 lvds_reg = LVDS;
888 }
889
890 val = I915_READ(pp_reg);
891 if (!(val & PANEL_POWER_ON) ||
892 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
893 locked = false;
894
895 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
896 panel_pipe = PIPE_B;
897
898 WARN(panel_pipe == pipe && locked,
899 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 900 pipe_name(pipe));
ea0760cf
JB		 901}
902
63d7bbe9
JB		 903static void assert_pipe(struct drm_i915_private *dev_priv,
904 enum pipe pipe, bool state)
b24e7179
JB		 905{
906 int reg;
907 u32 val;
63d7bbe9 908 bool cur_state;
b24e7179
JB		 909
910 reg = PIPECONF(pipe);
911 val = I915_READ(reg);
63d7bbe9
JB		 912 cur_state = !!(val & PIPECONF_ENABLE);
913 WARN(cur_state != state,
914 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 915 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179 916}
63d7bbe9
JB		 917#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
918#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
b24e7179
JB		 919
920static void assert_plane_enabled(struct drm_i915_private *dev_priv,
921 enum plane plane)
922{
923 int reg;
924 u32 val;
925
926 reg = DSPCNTR(plane);
927 val = I915_READ(reg);
928 WARN(!(val & DISPLAY_PLANE_ENABLE),
929 "plane %c assertion failure, should be active but is disabled\n",
9db4a9c7 930 plane_name(plane));
b24e7179
JB		 931}
932
933static void assert_planes_disabled(struct drm_i915_private *dev_priv,
934 enum pipe pipe)
935{
936 int reg, i;
937 u32 val;
938 int cur_pipe;
939
19ec1358
JB		 940 /* Planes are fixed to pipes on ILK+ */
941 if (HAS_PCH_SPLIT(dev_priv->dev))
942 return;
943
b24e7179
JB		 944 /* Need to check both planes against the pipe */
945 for (i = 0; i < 2; i++) {
946 reg = DSPCNTR(i);
947 val = I915_READ(reg);
948 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
949 DISPPLANE_SEL_PIPE_SHIFT;
950 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 951 "plane %c assertion failure, should be off on pipe %c but is still active\n",
952 plane_name(i), pipe_name(pipe));
b24e7179
JB		 953 }
954}
955
92f2584a
JB		 956static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
957{
958 u32 val;
959 bool enabled;
960
961 val = I915_READ(PCH_DREF_CONTROL);
962 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
963 DREF_SUPERSPREAD_SOURCE_MASK));
964 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
965}
966
967static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
968 enum pipe pipe)
969{
970 int reg;
971 u32 val;
972 bool enabled;
973
974 reg = TRANSCONF(pipe);
975 val = I915_READ(reg);
976 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 977 WARN(enabled,
978 "transcoder assertion failed, should be off on pipe %c but is still active\n",
979 pipe_name(pipe));
92f2584a
JB		 980}
981
291906f1
JB		 982static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
983 enum pipe pipe, int reg)
984{
47a05eca
JB		 985 u32 val = I915_READ(reg);
986 WARN(DP_PIPE_ENABLED(val, pipe),
291906f1 987 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 988 reg, pipe_name(pipe));
291906f1
JB		 989}
990
991static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
992 enum pipe pipe, int reg)
993{
47a05eca
JB		 994 u32 val = I915_READ(reg);
995 WARN(HDMI_PIPE_ENABLED(val, pipe),
291906f1 996 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 997 reg, pipe_name(pipe));
291906f1
JB		 998}
999
1000static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1001 enum pipe pipe)
1002{
1003 int reg;
1004 u32 val;
291906f1
JB		 1005
1006 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1007 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1008 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1009
1010 reg = PCH_ADPA;
1011 val = I915_READ(reg);
47a05eca 1012 WARN(ADPA_PIPE_ENABLED(val, pipe),
291906f1 1013 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1014 pipe_name(pipe));
291906f1
JB		 1015
1016 reg = PCH_LVDS;
1017 val = I915_READ(reg);
47a05eca 1018 WARN(LVDS_PIPE_ENABLED(val, pipe),
291906f1 1019 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1020 pipe_name(pipe));
291906f1
JB		 1021
1022 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1023 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1024 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1025}
1026
63d7bbe9
JB		 1027/**
1028 * intel_enable_pll - enable a PLL
1029 * @dev_priv: i915 private structure
1030 * @pipe: pipe PLL to enable
1031 *
1032 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1033 * make sure the PLL reg is writable first though, since the panel write
1034 * protect mechanism may be enabled.
1035 *
1036 * Note! This is for pre-ILK only.
1037 */
1038static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1039{
1040 int reg;
1041 u32 val;
1042
1043 /* No really, not for ILK+ */
1044 BUG_ON(dev_priv->info->gen >= 5);
1045
1046 /* PLL is protected by panel, make sure we can write it */
1047 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1048 assert_panel_unlocked(dev_priv, pipe);
1049
1050 reg = DPLL(pipe);
1051 val = I915_READ(reg);
1052 val |= DPLL_VCO_ENABLE;
1053
1054 /* We do this three times for luck */
1055 I915_WRITE(reg, val);
1056 POSTING_READ(reg);
1057 udelay(150); /* wait for warmup */
1058 I915_WRITE(reg, val);
1059 POSTING_READ(reg);
1060 udelay(150); /* wait for warmup */
1061 I915_WRITE(reg, val);
1062 POSTING_READ(reg);
1063 udelay(150); /* wait for warmup */
1064}
1065
1066/**
1067 * intel_disable_pll - disable a PLL
1068 * @dev_priv: i915 private structure
1069 * @pipe: pipe PLL to disable
1070 *
1071 * Disable the PLL for @pipe, making sure the pipe is off first.
1072 *
1073 * Note! This is for pre-ILK only.
1074 */
1075static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1076{
1077 int reg;
1078 u32 val;
1079
1080 /* Don't disable pipe A or pipe A PLLs if needed */
1081 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1082 return;
1083
1084 /* Make sure the pipe isn't still relying on us */
1085 assert_pipe_disabled(dev_priv, pipe);
1086
1087 reg = DPLL(pipe);
1088 val = I915_READ(reg);
1089 val &= ~DPLL_VCO_ENABLE;
1090 I915_WRITE(reg, val);
1091 POSTING_READ(reg);
1092}
1093
92f2584a
JB		 1094/**
1095 * intel_enable_pch_pll - enable PCH PLL
1096 * @dev_priv: i915 private structure
1097 * @pipe: pipe PLL to enable
1098 *
1099 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1100 * drives the transcoder clock.
1101 */
1102static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1103 enum pipe pipe)
1104{
1105 int reg;
1106 u32 val;
1107
1108 /* PCH only available on ILK+ */
1109 BUG_ON(dev_priv->info->gen < 5);
1110
1111 /* PCH refclock must be enabled first */
1112 assert_pch_refclk_enabled(dev_priv);
1113
1114 reg = PCH_DPLL(pipe);
1115 val = I915_READ(reg);
1116 val |= DPLL_VCO_ENABLE;
1117 I915_WRITE(reg, val);
1118 POSTING_READ(reg);
1119 udelay(200);
1120}
1121
1122static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1123 enum pipe pipe)
1124{
1125 int reg;
1126 u32 val;
1127
1128 /* PCH only available on ILK+ */
1129 BUG_ON(dev_priv->info->gen < 5);
1130
1131 /* Make sure transcoder isn't still depending on us */
1132 assert_transcoder_disabled(dev_priv, pipe);
1133
1134 reg = PCH_DPLL(pipe);
1135 val = I915_READ(reg);
1136 val &= ~DPLL_VCO_ENABLE;
1137 I915_WRITE(reg, val);
1138 POSTING_READ(reg);
1139 udelay(200);
1140}
1141
040484af
JB		 1142static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1143 enum pipe pipe)
1144{
1145 int reg;
1146 u32 val;
1147
1148 /* PCH only available on ILK+ */
1149 BUG_ON(dev_priv->info->gen < 5);
1150
1151 /* Make sure PCH DPLL is enabled */
1152 assert_pch_pll_enabled(dev_priv, pipe);
1153
1154 /* FDI must be feeding us bits for PCH ports */
1155 assert_fdi_tx_enabled(dev_priv, pipe);
1156 assert_fdi_rx_enabled(dev_priv, pipe);
1157
1158 reg = TRANSCONF(pipe);
1159 val = I915_READ(reg);
1160 /*
1161 * make the BPC in transcoder be consistent with
1162 * that in pipeconf reg.
1163 */
1164 val &= ~PIPE_BPC_MASK;
1165 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1166 I915_WRITE(reg, val | TRANS_ENABLE);
1167 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1168 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1169}
1170
1171static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1172 enum pipe pipe)
1173{
1174 int reg;
1175 u32 val;
1176
1177 /* FDI relies on the transcoder */
1178 assert_fdi_tx_disabled(dev_priv, pipe);
1179 assert_fdi_rx_disabled(dev_priv, pipe);
1180
291906f1
JB		 1181 /* Ports must be off as well */
1182 assert_pch_ports_disabled(dev_priv, pipe);
1183
040484af
JB		 1184 reg = TRANSCONF(pipe);
1185 val = I915_READ(reg);
1186 val &= ~TRANS_ENABLE;
1187 I915_WRITE(reg, val);
1188 /* wait for PCH transcoder off, transcoder state */
1189 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1190 DRM_ERROR("failed to disable transcoder\n");
1191}
1192
b24e7179 1193/**
309cfea8 1194 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1195 * @dev_priv: i915 private structure
1196 * @pipe: pipe to enable
040484af 1197 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1198 *
1199 * Enable @pipe, making sure that various hardware specific requirements
1200 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1201 *
1202 * @pipe should be %PIPE_A or %PIPE_B.
1203 *
1204 * Will wait until the pipe is actually running (i.e. first vblank) before
1205 * returning.
1206 */
040484af
JB		 1207static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1208 bool pch_port)
b24e7179
JB		 1209{
1210 int reg;
1211 u32 val;
1212
1213 /*
1214 * A pipe without a PLL won't actually be able to drive bits from
1215 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1216 * need the check.
1217 */
1218 if (!HAS_PCH_SPLIT(dev_priv->dev))
1219 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1220 else {
1221 if (pch_port) {
1222 /* if driving the PCH, we need FDI enabled */
1223 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1224 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1225 }
1226 /* FIXME: assert CPU port conditions for SNB+ */
1227 }
b24e7179
JB		 1228
1229 reg = PIPECONF(pipe);
1230 val = I915_READ(reg);
00d70b15
CW		 1231 if (val & PIPECONF_ENABLE)
1232 return;
1233
1234 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1235 intel_wait_for_vblank(dev_priv->dev, pipe);
1236}
1237
1238/**
309cfea8 1239 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1240 * @dev_priv: i915 private structure
1241 * @pipe: pipe to disable
1242 *
1243 * Disable @pipe, making sure that various hardware specific requirements
1244 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1245 *
1246 * @pipe should be %PIPE_A or %PIPE_B.
1247 *
1248 * Will wait until the pipe has shut down before returning.
1249 */
1250static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1251 enum pipe pipe)
1252{
1253 int reg;
1254 u32 val;
1255
1256 /*
1257 * Make sure planes won't keep trying to pump pixels to us,
1258 * or we might hang the display.
1259 */
1260 assert_planes_disabled(dev_priv, pipe);
1261
1262 /* Don't disable pipe A or pipe A PLLs if needed */
1263 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1264 return;
1265
1266 reg = PIPECONF(pipe);
1267 val = I915_READ(reg);
00d70b15
CW		 1268 if ((val & PIPECONF_ENABLE) == 0)
1269 return;
1270
1271 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1272 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1273}
1274
1275/**
1276 * intel_enable_plane - enable a display plane on a given pipe
1277 * @dev_priv: i915 private structure
1278 * @plane: plane to enable
1279 * @pipe: pipe being fed
1280 *
1281 * Enable @plane on @pipe, making sure that @pipe is running first.
1282 */
1283static void intel_enable_plane(struct drm_i915_private *dev_priv,
1284 enum plane plane, enum pipe pipe)
1285{
1286 int reg;
1287 u32 val;
1288
1289 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1290 assert_pipe_enabled(dev_priv, pipe);
1291
1292 reg = DSPCNTR(plane);
1293 val = I915_READ(reg);
00d70b15
CW		 1294 if (val & DISPLAY_PLANE_ENABLE)
1295 return;
1296
1297 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1298 intel_wait_for_vblank(dev_priv->dev, pipe);
1299}
1300
1301/*
1302 * Plane regs are double buffered, going from enabled->disabled needs a
1303 * trigger in order to latch. The display address reg provides this.
1304 */
1305static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1306 enum plane plane)
1307{
1308 u32 reg = DSPADDR(plane);
1309 I915_WRITE(reg, I915_READ(reg));
1310}
1311
1312/**
1313 * intel_disable_plane - disable a display plane
1314 * @dev_priv: i915 private structure
1315 * @plane: plane to disable
1316 * @pipe: pipe consuming the data
1317 *
1318 * Disable @plane; should be an independent operation.
1319 */
1320static void intel_disable_plane(struct drm_i915_private *dev_priv,
1321 enum plane plane, enum pipe pipe)
1322{
1323 int reg;
1324 u32 val;
1325
1326 reg = DSPCNTR(plane);
1327 val = I915_READ(reg);
00d70b15
CW		 1328 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1329 return;
1330
1331 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1332 intel_flush_display_plane(dev_priv, plane);
1333 intel_wait_for_vblank(dev_priv->dev, pipe);
1334}
1335
47a05eca
JB		 1336static void disable_pch_dp(struct drm_i915_private *dev_priv,
1337 enum pipe pipe, int reg)
1338{
1339 u32 val = I915_READ(reg);
1340 if (DP_PIPE_ENABLED(val, pipe))
1341 I915_WRITE(reg, val & ~DP_PORT_EN);
1342}
1343
1344static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1345 enum pipe pipe, int reg)
1346{
1347 u32 val = I915_READ(reg);
1348 if (HDMI_PIPE_ENABLED(val, pipe))
1349 I915_WRITE(reg, val & ~PORT_ENABLE);
1350}
1351
1352/* Disable any ports connected to this transcoder */
1353static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1354 enum pipe pipe)
1355{
1356 u32 reg, val;
1357
1358 val = I915_READ(PCH_PP_CONTROL);
1359 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1360
1361 disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1362 disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1363 disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1364
1365 reg = PCH_ADPA;
1366 val = I915_READ(reg);
1367 if (ADPA_PIPE_ENABLED(val, pipe))
1368 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1369
1370 reg = PCH_LVDS;
1371 val = I915_READ(reg);
1372 if (LVDS_PIPE_ENABLED(val, pipe)) {
1373 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1374 POSTING_READ(reg);
1375 udelay(100);
1376 }
1377
1378 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1379 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1380 disable_pch_hdmi(dev_priv, pipe, HDMID);
1381}
1382
80824003
JB		 1383static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1384{
1385 struct drm_device *dev = crtc->dev;
1386 struct drm_i915_private *dev_priv = dev->dev_private;
1387 struct drm_framebuffer *fb = crtc->fb;
1388 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1389 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003
JB		 1390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1391 int plane, i;
1392 u32 fbc_ctl, fbc_ctl2;
1393
bed4a673 1394 if (fb->pitch == dev_priv->cfb_pitch &&
05394f39 1395 obj->fence_reg == dev_priv->cfb_fence &&
bed4a673
CW		 1396 intel_crtc->plane == dev_priv->cfb_plane &&
1397 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1398 return;
1399
1400 i8xx_disable_fbc(dev);
1401
80824003
JB		 1402 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1403
1404 if (fb->pitch < dev_priv->cfb_pitch)
1405 dev_priv->cfb_pitch = fb->pitch;
1406
1407 /* FBC_CTL wants 64B units */
1408 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1409 dev_priv->cfb_fence = obj->fence_reg;
80824003
JB		 1410 dev_priv->cfb_plane = intel_crtc->plane;
1411 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1412
1413 /* Clear old tags */
1414 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1415 I915_WRITE(FBC_TAG + (i * 4), 0);
1416
1417 /* Set it up... */
1418 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
05394f39 1419 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB		 1420 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1421 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1422 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1423
1424 /* enable it... */
1425 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1426 if (IS_I945GM(dev))
49677901 1427 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
80824003
JB		 1428 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1429 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
05394f39 1430 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB		 1431 fbc_ctl |= dev_priv->cfb_fence;
1432 I915_WRITE(FBC_CONTROL, fbc_ctl);
1433
28c97730 1434 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
5eddb70b 1435 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
80824003
JB		 1436}
1437
1438void i8xx_disable_fbc(struct drm_device *dev)
1439{
1440 struct drm_i915_private *dev_priv = dev->dev_private;
1441 u32 fbc_ctl;
1442
1443 /* Disable compression */
1444 fbc_ctl = I915_READ(FBC_CONTROL);
a5cad620
CW		 1445 if ((fbc_ctl & FBC_CTL_EN) == 0)
1446 return;
1447
80824003
JB		 1448 fbc_ctl &= ~FBC_CTL_EN;
1449 I915_WRITE(FBC_CONTROL, fbc_ctl);
1450
1451 /* Wait for compressing bit to clear */
481b6af3 1452 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
913d8d11
CW		 1453 DRM_DEBUG_KMS("FBC idle timed out\n");
1454 return;
9517a92f 1455 }
80824003 1456
28c97730 1457 DRM_DEBUG_KMS("disabled FBC\n");
80824003
JB		 1458}
1459
ee5382ae 1460static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1461{
80824003
JB		 1462 struct drm_i915_private *dev_priv = dev->dev_private;
1463
1464 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1465}
1466
74dff282
JB		 1467static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1468{
1469 struct drm_device *dev = crtc->dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471 struct drm_framebuffer *fb = crtc->fb;
1472 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1473 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1475 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1476 unsigned long stall_watermark = 200;
1477 u32 dpfc_ctl;
1478
bed4a673
CW		 1479 dpfc_ctl = I915_READ(DPFC_CONTROL);
1480 if (dpfc_ctl & DPFC_CTL_EN) {
1481 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
05394f39 1482 dev_priv->cfb_fence == obj->fence_reg &&
bed4a673
CW		 1483 dev_priv->cfb_plane == intel_crtc->plane &&
1484 dev_priv->cfb_y == crtc->y)
1485 return;
1486
1487 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1488 intel_wait_for_vblank(dev, intel_crtc->pipe);
1489 }
1490
74dff282 1491 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1492 dev_priv->cfb_fence = obj->fence_reg;
74dff282 1493 dev_priv->cfb_plane = intel_crtc->plane;
bed4a673 1494 dev_priv->cfb_y = crtc->y;
74dff282
JB		 1495
1496 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
05394f39 1497 if (obj->tiling_mode != I915_TILING_NONE) {
74dff282
JB		 1498 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1499 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1500 } else {
1501 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1502 }
1503
74dff282
JB		 1504 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1505 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1506 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1507 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1508
1509 /* enable it... */
1510 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1511
28c97730 1512 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1513}
1514
1515void g4x_disable_fbc(struct drm_device *dev)
1516{
1517 struct drm_i915_private *dev_priv = dev->dev_private;
1518 u32 dpfc_ctl;
1519
1520 /* Disable compression */
1521 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1522 if (dpfc_ctl & DPFC_CTL_EN) {
1523 dpfc_ctl &= ~DPFC_CTL_EN;
1524 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1525
bed4a673
CW		 1526 DRM_DEBUG_KMS("disabled FBC\n");
1527 }
74dff282
JB		 1528}
1529
ee5382ae 1530static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1531{
74dff282
JB		 1532 struct drm_i915_private *dev_priv = dev->dev_private;
1533
1534 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1535}
1536
4efe0708
JB		 1537static void sandybridge_blit_fbc_update(struct drm_device *dev)
1538{
1539 struct drm_i915_private *dev_priv = dev->dev_private;
1540 u32 blt_ecoskpd;
1541
1542 /* Make sure blitter notifies FBC of writes */
91355834 1543 __gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1544 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1545 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1546 GEN6_BLITTER_LOCK_SHIFT;
1547 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1548 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1549 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1550 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1551 GEN6_BLITTER_LOCK_SHIFT);
1552 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1553 POSTING_READ(GEN6_BLITTER_ECOSKPD);
91355834 1554 __gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1555}
1556
b52eb4dc
ZY		 1557static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1558{
1559 struct drm_device *dev = crtc->dev;
1560 struct drm_i915_private *dev_priv = dev->dev_private;
1561 struct drm_framebuffer *fb = crtc->fb;
1562 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1563 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1565 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1566 unsigned long stall_watermark = 200;
1567 u32 dpfc_ctl;
1568
bed4a673
CW		 1569 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1570 if (dpfc_ctl & DPFC_CTL_EN) {
1571 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
05394f39 1572 dev_priv->cfb_fence == obj->fence_reg &&
bed4a673 1573 dev_priv->cfb_plane == intel_crtc->plane &&
05394f39 1574 dev_priv->cfb_offset == obj->gtt_offset &&
bed4a673
CW		 1575 dev_priv->cfb_y == crtc->y)
1576 return;
1577
1578 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1579 intel_wait_for_vblank(dev, intel_crtc->pipe);
1580 }
1581
b52eb4dc 1582 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1583 dev_priv->cfb_fence = obj->fence_reg;
b52eb4dc 1584 dev_priv->cfb_plane = intel_crtc->plane;
05394f39 1585 dev_priv->cfb_offset = obj->gtt_offset;
bed4a673 1586 dev_priv->cfb_y = crtc->y;
b52eb4dc 1587
b52eb4dc
ZY		 1588 dpfc_ctl &= DPFC_RESERVED;
1589 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
05394f39 1590 if (obj->tiling_mode != I915_TILING_NONE) {
b52eb4dc
ZY		 1591 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1592 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1593 } else {
1594 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1595 }
1596
b52eb4dc
ZY		 1597 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1598 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1599 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1600 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1601 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1602 /* enable it... */
bed4a673 1603 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1604
9c04f015
YL		 1605 if (IS_GEN6(dev)) {
1606 I915_WRITE(SNB_DPFC_CTL_SA,
1607 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1608 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1609 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1610 }
1611
b52eb4dc
ZY		 1612 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1613}
1614
1615void ironlake_disable_fbc(struct drm_device *dev)
1616{
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 u32 dpfc_ctl;
1619
1620 /* Disable compression */
1621 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1622 if (dpfc_ctl & DPFC_CTL_EN) {
1623 dpfc_ctl &= ~DPFC_CTL_EN;
1624 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1625
bed4a673
CW		 1626 DRM_DEBUG_KMS("disabled FBC\n");
1627 }
b52eb4dc
ZY		 1628}
1629
1630static bool ironlake_fbc_enabled(struct drm_device *dev)
1631{
1632 struct drm_i915_private *dev_priv = dev->dev_private;
1633
1634 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1635}
1636
ee5382ae
AJ		 1637bool intel_fbc_enabled(struct drm_device *dev)
1638{
1639 struct drm_i915_private *dev_priv = dev->dev_private;
1640
1641 if (!dev_priv->display.fbc_enabled)
1642 return false;
1643
1644 return dev_priv->display.fbc_enabled(dev);
1645}
1646
1647void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1648{
1649 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1650
1651 if (!dev_priv->display.enable_fbc)
1652 return;
1653
1654 dev_priv->display.enable_fbc(crtc, interval);
1655}
1656
1657void intel_disable_fbc(struct drm_device *dev)
1658{
1659 struct drm_i915_private *dev_priv = dev->dev_private;
1660
1661 if (!dev_priv->display.disable_fbc)
1662 return;
1663
1664 dev_priv->display.disable_fbc(dev);
1665}
1666
80824003
JB		 1667/**
1668 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1669 * @dev: the drm_device
80824003
JB		 1670 *
1671 * Set up the framebuffer compression hardware at mode set time. We
1672 * enable it if possible:
1673 * - plane A only (on pre-965)
1674 * - no pixel mulitply/line duplication
1675 * - no alpha buffer discard
1676 * - no dual wide
1677 * - framebuffer <= 2048 in width, 1536 in height
1678 *
1679 * We can't assume that any compression will take place (worst case),
1680 * so the compressed buffer has to be the same size as the uncompressed
1681 * one. It also must reside (along with the line length buffer) in
1682 * stolen memory.
1683 *
1684 * We need to enable/disable FBC on a global basis.
1685 */
bed4a673 1686static void intel_update_fbc(struct drm_device *dev)
80824003 1687{
80824003 1688 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1689 struct drm_crtc *crtc = NULL, *tmp_crtc;
1690 struct intel_crtc *intel_crtc;
1691 struct drm_framebuffer *fb;
80824003 1692 struct intel_framebuffer *intel_fb;
05394f39 1693 struct drm_i915_gem_object *obj;
9c928d16
JB		 1694
1695 DRM_DEBUG_KMS("\n");
80824003
JB		 1696
1697 if (!i915_powersave)
1698 return;
1699
ee5382ae 1700 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1701 return;
1702
80824003
JB		 1703 /*
1704 * If FBC is already on, we just have to verify that we can
1705 * keep it that way...
1706 * Need to disable if:
9c928d16 1707 * - more than one pipe is active
80824003
JB		 1708 * - changing FBC params (stride, fence, mode)
1709 * - new fb is too large to fit in compressed buffer
1710 * - going to an unsupported config (interlace, pixel multiply, etc.)
1711 */
9c928d16 1712 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1713 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1714 if (crtc) {
1715 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1716 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1717 goto out_disable;
1718 }
1719 crtc = tmp_crtc;
1720 }
9c928d16 1721 }
bed4a673
CW		 1722
1723 if (!crtc || crtc->fb == NULL) {
1724 DRM_DEBUG_KMS("no output, disabling\n");
1725 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1726 goto out_disable;
1727 }
bed4a673
CW		 1728
1729 intel_crtc = to_intel_crtc(crtc);
1730 fb = crtc->fb;
1731 intel_fb = to_intel_framebuffer(fb);
05394f39 1732 obj = intel_fb->obj;
bed4a673 1733
05394f39 1734 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1735 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1736 "compression\n");
b5e50c3f 1737 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1738 goto out_disable;
1739 }
bed4a673
CW		 1740 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1741 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1742 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1743 "disabling\n");
b5e50c3f 1744 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1745 goto out_disable;
1746 }
bed4a673
CW		 1747 if ((crtc->mode.hdisplay > 2048) ||
1748 (crtc->mode.vdisplay > 1536)) {
28c97730 1749 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1750 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1751 goto out_disable;
1752 }
bed4a673 1753 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1754 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1755 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1756 goto out_disable;
1757 }
05394f39 1758 if (obj->tiling_mode != I915_TILING_X) {
28c97730 1759 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
b5e50c3f 1760 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1761 goto out_disable;
1762 }
1763
c924b934
JW		 1764 /* If the kernel debugger is active, always disable compression */
1765 if (in_dbg_master())
1766 goto out_disable;
1767
bed4a673 1768 intel_enable_fbc(crtc, 500);
80824003
JB		 1769 return;
1770
1771out_disable:
80824003 1772 /* Multiple disables should be harmless */
a939406f
CW		 1773 if (intel_fbc_enabled(dev)) {
1774 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1775 intel_disable_fbc(dev);
a939406f 1776 }
80824003
JB		 1777}
1778
127bd2ac 1779int
48b956c5 1780intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1781 struct drm_i915_gem_object *obj,
919926ae 1782 struct intel_ring_buffer *pipelined)
6b95a207 1783{
ce453d81 1784 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1785 u32 alignment;
1786 int ret;
1787
05394f39 1788 switch (obj->tiling_mode) {
6b95a207 1789 case I915_TILING_NONE:
534843da
CW		 1790 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1791 alignment = 128 * 1024;
a6c45cf0 1792 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1793 alignment = 4 * 1024;
1794 else
1795 alignment = 64 * 1024;
6b95a207
KH		 1796 break;
1797 case I915_TILING_X:
1798 /* pin() will align the object as required by fence */
1799 alignment = 0;
1800 break;
1801 case I915_TILING_Y:
1802 /* FIXME: Is this true? */
1803 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1804 return -EINVAL;
1805 default:
1806 BUG();
1807 }
1808
ce453d81 1809 dev_priv->mm.interruptible = false;
75e9e915 1810 ret = i915_gem_object_pin(obj, alignment, true);
48b956c5 1811 if (ret)
ce453d81 1812 goto err_interruptible;
6b95a207 1813
48b956c5
CW		 1814 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1815 if (ret)
1816 goto err_unpin;
7213342d 1817
6b95a207
KH		 1818 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1819 * fence, whereas 965+ only requires a fence if using
1820 * framebuffer compression. For simplicity, we always install
1821 * a fence as the cost is not that onerous.
1822 */
05394f39 1823 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 1824 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 1825 if (ret)
1826 goto err_unpin;
6b95a207
KH		 1827 }
1828
ce453d81 1829 dev_priv->mm.interruptible = true;
6b95a207 1830 return 0;
48b956c5
CW		 1831
1832err_unpin:
1833 i915_gem_object_unpin(obj);
ce453d81
CW		 1834err_interruptible:
1835 dev_priv->mm.interruptible = true;
48b956c5 1836 return ret;
6b95a207
KH		 1837}
1838
81255565
JB		 1839/* Assume fb object is pinned & idle & fenced and just update base pointers */
1840static int
1841intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
21c74a8e 1842 int x, int y, enum mode_set_atomic state)
81255565
JB		 1843{
1844 struct drm_device *dev = crtc->dev;
1845 struct drm_i915_private *dev_priv = dev->dev_private;
1846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1847 struct intel_framebuffer *intel_fb;
05394f39 1848 struct drm_i915_gem_object *obj;
81255565
JB		 1849 int plane = intel_crtc->plane;
1850 unsigned long Start, Offset;
81255565 1851 u32 dspcntr;
5eddb70b 1852 u32 reg;
81255565
JB		 1853
1854 switch (plane) {
1855 case 0:
1856 case 1:
1857 break;
1858 default:
1859 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1860 return -EINVAL;
1861 }
1862
1863 intel_fb = to_intel_framebuffer(fb);
1864 obj = intel_fb->obj;
81255565 1865
5eddb70b
CW		 1866 reg = DSPCNTR(plane);
1867 dspcntr = I915_READ(reg);
81255565
JB		 1868 /* Mask out pixel format bits in case we change it */
1869 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1870 switch (fb->bits_per_pixel) {
1871 case 8:
1872 dspcntr |= DISPPLANE_8BPP;
1873 break;
1874 case 16:
1875 if (fb->depth == 15)
1876 dspcntr |= DISPPLANE_15_16BPP;
1877 else
1878 dspcntr |= DISPPLANE_16BPP;
1879 break;
1880 case 24:
1881 case 32:
1882 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1883 break;
1884 default:
1885 DRM_ERROR("Unknown color depth\n");
1886 return -EINVAL;
1887 }
a6c45cf0 1888 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1889 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1890 dspcntr |= DISPPLANE_TILED;
1891 else
1892 dspcntr &= ~DISPPLANE_TILED;
1893 }
1894
4e6cfefc 1895 if (HAS_PCH_SPLIT(dev))
81255565
JB		 1896 /* must disable */
1897 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1898
5eddb70b 1899 I915_WRITE(reg, dspcntr);
81255565 1900
05394f39 1901 Start = obj->gtt_offset;
81255565
JB		 1902 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1903
4e6cfefc
CW		 1904 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1905 Start, Offset, x, y, fb->pitch);
5eddb70b 1906 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
a6c45cf0 1907 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 1908 I915_WRITE(DSPSURF(plane), Start);
1909 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1910 I915_WRITE(DSPADDR(plane), Offset);
1911 } else
1912 I915_WRITE(DSPADDR(plane), Start + Offset);
1913 POSTING_READ(reg);
81255565 1914
bed4a673 1915 intel_update_fbc(dev);
3dec0095 1916 intel_increase_pllclock(crtc);
81255565
JB		 1917
1918 return 0;
1919}
1920
5c3b82e2 1921static int
3c4fdcfb
KH		 1922intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1923 struct drm_framebuffer *old_fb)
79e53945
JB		 1924{
1925 struct drm_device *dev = crtc->dev;
79e53945
JB		 1926 struct drm_i915_master_private *master_priv;
1927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 1928 int ret;
79e53945
JB		 1929
1930 /* no fb bound */
1931 if (!crtc->fb) {
28c97730 1932 DRM_DEBUG_KMS("No FB bound\n");
5c3b82e2
CW		 1933 return 0;
1934 }
1935
265db958 1936 switch (intel_crtc->plane) {
5c3b82e2
CW		 1937 case 0:
1938 case 1:
1939 break;
1940 default:
5c3b82e2 1941 return -EINVAL;
79e53945
JB		 1942 }
1943
5c3b82e2 1944 mutex_lock(&dev->struct_mutex);
265db958
CW		 1945 ret = intel_pin_and_fence_fb_obj(dev,
1946 to_intel_framebuffer(crtc->fb)->obj,
919926ae 1947 NULL);
5c3b82e2
CW		 1948 if (ret != 0) {
1949 mutex_unlock(&dev->struct_mutex);
1950 return ret;
1951 }
79e53945 1952
265db958 1953 if (old_fb) {
e6c3a2a6 1954 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1955 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 1956
e6c3a2a6 1957 wait_event(dev_priv->pending_flip_queue,
01eec727 1958 atomic_read(&dev_priv->mm.wedged) ||
05394f39 1959 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 1960
1961 /* Big Hammer, we also need to ensure that any pending
1962 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1963 * current scanout is retired before unpinning the old
1964 * framebuffer.
01eec727
CW		 1965 *
1966 * This should only fail upon a hung GPU, in which case we
1967 * can safely continue.
85345517 1968 */
ce453d81 1969 ret = i915_gem_object_flush_gpu(obj);
01eec727 1970 (void) ret;
265db958
CW		 1971 }
1972
21c74a8e
JW		 1973 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1974 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 1975 if (ret) {
265db958 1976 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 1977 mutex_unlock(&dev->struct_mutex);
4e6cfefc 1978 return ret;
79e53945 1979 }
3c4fdcfb 1980
b7f1de28
CW		 1981 if (old_fb) {
1982 intel_wait_for_vblank(dev, intel_crtc->pipe);
265db958 1983 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
b7f1de28 1984 }
652c393a 1985
5c3b82e2 1986 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 1987
1988 if (!dev->primary->master)
5c3b82e2 1989 return 0;
79e53945
JB		 1990
1991 master_priv = dev->primary->master->driver_priv;
1992 if (!master_priv->sarea_priv)
5c3b82e2 1993 return 0;
79e53945 1994
265db958 1995 if (intel_crtc->pipe) {
79e53945
JB		 1996 master_priv->sarea_priv->pipeB_x = x;
1997 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 1998 } else {
1999 master_priv->sarea_priv->pipeA_x = x;
2000 master_priv->sarea_priv->pipeA_y = y;
79e53945 2001 }
5c3b82e2
CW		 2002
2003 return 0;
79e53945
JB		 2004}
2005
5eddb70b 2006static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2007{
2008 struct drm_device *dev = crtc->dev;
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 u32 dpa_ctl;
2011
28c97730 2012 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2013 dpa_ctl = I915_READ(DP_A);
2014 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2015
2016 if (clock < 200000) {
2017 u32 temp;
2018 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2019 /* workaround for 160Mhz:
2020 1) program 0x4600c bits 15:0 = 0x8124
2021 2) program 0x46010 bit 0 = 1
2022 3) program 0x46034 bit 24 = 1
2023 4) program 0x64000 bit 14 = 1
2024 */
2025 temp = I915_READ(0x4600c);
2026 temp &= 0xffff0000;
2027 I915_WRITE(0x4600c, temp | 0x8124);
2028
2029 temp = I915_READ(0x46010);
2030 I915_WRITE(0x46010, temp | 1);
2031
2032 temp = I915_READ(0x46034);
2033 I915_WRITE(0x46034, temp | (1 << 24));
2034 } else {
2035 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2036 }
2037 I915_WRITE(DP_A, dpa_ctl);
2038
5eddb70b 2039 POSTING_READ(DP_A);
32f9d658
ZW		 2040 udelay(500);
2041}
2042
5e84e1a4
ZW		 2043static void intel_fdi_normal_train(struct drm_crtc *crtc)
2044{
2045 struct drm_device *dev = crtc->dev;
2046 struct drm_i915_private *dev_priv = dev->dev_private;
2047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2048 int pipe = intel_crtc->pipe;
2049 u32 reg, temp;
2050
2051 /* enable normal train */
2052 reg = FDI_TX_CTL(pipe);
2053 temp = I915_READ(reg);
2054 temp &= ~FDI_LINK_TRAIN_NONE;
2055 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2056 I915_WRITE(reg, temp);
2057
2058 reg = FDI_RX_CTL(pipe);
2059 temp = I915_READ(reg);
2060 if (HAS_PCH_CPT(dev)) {
2061 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2062 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2063 } else {
2064 temp &= ~FDI_LINK_TRAIN_NONE;
2065 temp |= FDI_LINK_TRAIN_NONE;
2066 }
2067 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2068
2069 /* wait one idle pattern time */
2070 POSTING_READ(reg);
2071 udelay(1000);
2072}
2073
8db9d77b
ZW		 2074/* The FDI link training functions for ILK/Ibexpeak. */
2075static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2076{
2077 struct drm_device *dev = crtc->dev;
2078 struct drm_i915_private *dev_priv = dev->dev_private;
2079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2080 int pipe = intel_crtc->pipe;
0fc932b8 2081 int plane = intel_crtc->plane;
5eddb70b 2082 u32 reg, temp, tries;
8db9d77b 2083
0fc932b8
JB		 2084 /* FDI needs bits from pipe & plane first */
2085 assert_pipe_enabled(dev_priv, pipe);
2086 assert_plane_enabled(dev_priv, plane);
2087
e1a44743
AJ		 2088 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2089 for train result */
5eddb70b
CW		 2090 reg = FDI_RX_IMR(pipe);
2091 temp = I915_READ(reg);
e1a44743
AJ		 2092 temp &= ~FDI_RX_SYMBOL_LOCK;
2093 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2094 I915_WRITE(reg, temp);
2095 I915_READ(reg);
e1a44743
AJ		 2096 udelay(150);
2097
8db9d77b 2098 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2099 reg = FDI_TX_CTL(pipe);
2100 temp = I915_READ(reg);
77ffb597
AJ		 2101 temp &= ~(7 << 19);
2102 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2103 temp &= ~FDI_LINK_TRAIN_NONE;
2104 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2105 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2106
5eddb70b
CW		 2107 reg = FDI_RX_CTL(pipe);
2108 temp = I915_READ(reg);
8db9d77b
ZW		 2109 temp &= ~FDI_LINK_TRAIN_NONE;
2110 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2111 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2112
2113 POSTING_READ(reg);
8db9d77b
ZW		 2114 udelay(150);
2115
5b2adf89 2116 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2117 if (HAS_PCH_IBX(dev)) {
2118 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2119 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2120 FDI_RX_PHASE_SYNC_POINTER_EN);
2121 }
5b2adf89 2122
5eddb70b 2123 reg = FDI_RX_IIR(pipe);
e1a44743 2124 for (tries = 0; tries < 5; tries++) {
5eddb70b 2125 temp = I915_READ(reg);
8db9d77b
ZW		 2126 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2127
2128 if ((temp & FDI_RX_BIT_LOCK)) {
2129 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2130 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2131 break;
2132 }
8db9d77b 2133 }
e1a44743 2134 if (tries == 5)
5eddb70b 2135 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2136
2137 /* Train 2 */
5eddb70b
CW		 2138 reg = FDI_TX_CTL(pipe);
2139 temp = I915_READ(reg);
8db9d77b
ZW		 2140 temp &= ~FDI_LINK_TRAIN_NONE;
2141 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2142 I915_WRITE(reg, temp);
8db9d77b 2143
5eddb70b
CW		 2144 reg = FDI_RX_CTL(pipe);
2145 temp = I915_READ(reg);
8db9d77b
ZW		 2146 temp &= ~FDI_LINK_TRAIN_NONE;
2147 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2148 I915_WRITE(reg, temp);
8db9d77b 2149
5eddb70b
CW		 2150 POSTING_READ(reg);
2151 udelay(150);
8db9d77b 2152
5eddb70b 2153 reg = FDI_RX_IIR(pipe);
e1a44743 2154 for (tries = 0; tries < 5; tries++) {
5eddb70b 2155 temp = I915_READ(reg);
8db9d77b
ZW		 2156 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2157
2158 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2159 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2160 DRM_DEBUG_KMS("FDI train 2 done.\n");
2161 break;
2162 }
8db9d77b 2163 }
e1a44743 2164 if (tries == 5)
5eddb70b 2165 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2166
2167 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2168
8db9d77b
ZW		 2169}
2170
311bd68e 2171static const int snb_b_fdi_train_param [] = {
8db9d77b
ZW		 2172 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2173 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2174 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2175 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2176};
2177
2178/* The FDI link training functions for SNB/Cougarpoint. */
2179static void gen6_fdi_link_train(struct drm_crtc *crtc)
2180{
2181 struct drm_device *dev = crtc->dev;
2182 struct drm_i915_private *dev_priv = dev->dev_private;
2183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2184 int pipe = intel_crtc->pipe;
5eddb70b 2185 u32 reg, temp, i;
8db9d77b 2186
e1a44743
AJ		 2187 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2188 for train result */
5eddb70b
CW		 2189 reg = FDI_RX_IMR(pipe);
2190 temp = I915_READ(reg);
e1a44743
AJ		 2191 temp &= ~FDI_RX_SYMBOL_LOCK;
2192 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2193 I915_WRITE(reg, temp);
2194
2195 POSTING_READ(reg);
e1a44743
AJ		 2196 udelay(150);
2197
8db9d77b 2198 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2199 reg = FDI_TX_CTL(pipe);
2200 temp = I915_READ(reg);
77ffb597
AJ		 2201 temp &= ~(7 << 19);
2202 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2203 temp &= ~FDI_LINK_TRAIN_NONE;
2204 temp |= FDI_LINK_TRAIN_PATTERN_1;
2205 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2206 /* SNB-B */
2207 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2208 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2209
5eddb70b
CW		 2210 reg = FDI_RX_CTL(pipe);
2211 temp = I915_READ(reg);
8db9d77b
ZW		 2212 if (HAS_PCH_CPT(dev)) {
2213 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2214 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2215 } else {
2216 temp &= ~FDI_LINK_TRAIN_NONE;
2217 temp |= FDI_LINK_TRAIN_PATTERN_1;
2218 }
5eddb70b
CW		 2219 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2220
2221 POSTING_READ(reg);
8db9d77b
ZW		 2222 udelay(150);
2223
8db9d77b 2224 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2225 reg = FDI_TX_CTL(pipe);
2226 temp = I915_READ(reg);
8db9d77b
ZW		 2227 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2228 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2229 I915_WRITE(reg, temp);
2230
2231 POSTING_READ(reg);
8db9d77b
ZW		 2232 udelay(500);
2233
5eddb70b
CW		 2234 reg = FDI_RX_IIR(pipe);
2235 temp = I915_READ(reg);
8db9d77b
ZW		 2236 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2237
2238 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2239 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2240 DRM_DEBUG_KMS("FDI train 1 done.\n");
2241 break;
2242 }
2243 }
2244 if (i == 4)
5eddb70b 2245 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2246
2247 /* Train 2 */
5eddb70b
CW		 2248 reg = FDI_TX_CTL(pipe);
2249 temp = I915_READ(reg);
8db9d77b
ZW		 2250 temp &= ~FDI_LINK_TRAIN_NONE;
2251 temp |= FDI_LINK_TRAIN_PATTERN_2;
2252 if (IS_GEN6(dev)) {
2253 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2254 /* SNB-B */
2255 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2256 }
5eddb70b 2257 I915_WRITE(reg, temp);
8db9d77b 2258
5eddb70b
CW		 2259 reg = FDI_RX_CTL(pipe);
2260 temp = I915_READ(reg);
8db9d77b
ZW		 2261 if (HAS_PCH_CPT(dev)) {
2262 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2263 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2264 } else {
2265 temp &= ~FDI_LINK_TRAIN_NONE;
2266 temp |= FDI_LINK_TRAIN_PATTERN_2;
2267 }
5eddb70b
CW		 2268 I915_WRITE(reg, temp);
2269
2270 POSTING_READ(reg);
8db9d77b
ZW		 2271 udelay(150);
2272
2273 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2274 reg = FDI_TX_CTL(pipe);
2275 temp = I915_READ(reg);
8db9d77b
ZW		 2276 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2277 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2278 I915_WRITE(reg, temp);
2279
2280 POSTING_READ(reg);
8db9d77b
ZW		 2281 udelay(500);
2282
5eddb70b
CW		 2283 reg = FDI_RX_IIR(pipe);
2284 temp = I915_READ(reg);
8db9d77b
ZW		 2285 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2286
2287 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2288 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2289 DRM_DEBUG_KMS("FDI train 2 done.\n");
2290 break;
2291 }
2292 }
2293 if (i == 4)
5eddb70b 2294 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2295
2296 DRM_DEBUG_KMS("FDI train done.\n");
2297}
2298
0e23b99d 2299static void ironlake_fdi_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2300{
2301 struct drm_device *dev = crtc->dev;
2302 struct drm_i915_private *dev_priv = dev->dev_private;
2303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2304 int pipe = intel_crtc->pipe;
5eddb70b 2305 u32 reg, temp;
79e53945 2306
c64e311e 2307 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2308 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2309 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2310
c98e9dcf 2311 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2312 reg = FDI_RX_CTL(pipe);
2313 temp = I915_READ(reg);
2314 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2315 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2316 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2317 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2318
2319 POSTING_READ(reg);
c98e9dcf
JB		 2320 udelay(200);
2321
2322 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2323 temp = I915_READ(reg);
2324 I915_WRITE(reg, temp | FDI_PCDCLK);
2325
2326 POSTING_READ(reg);
c98e9dcf
JB		 2327 udelay(200);
2328
2329 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2330 reg = FDI_TX_CTL(pipe);
2331 temp = I915_READ(reg);
c98e9dcf 2332 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2333 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2334
2335 POSTING_READ(reg);
c98e9dcf 2336 udelay(100);
6be4a607 2337 }
0e23b99d
JB		 2338}
2339
0fc932b8
JB		 2340static void ironlake_fdi_disable(struct drm_crtc *crtc)
2341{
2342 struct drm_device *dev = crtc->dev;
2343 struct drm_i915_private *dev_priv = dev->dev_private;
2344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2345 int pipe = intel_crtc->pipe;
2346 u32 reg, temp;
2347
2348 /* disable CPU FDI tx and PCH FDI rx */
2349 reg = FDI_TX_CTL(pipe);
2350 temp = I915_READ(reg);
2351 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2352 POSTING_READ(reg);
2353
2354 reg = FDI_RX_CTL(pipe);
2355 temp = I915_READ(reg);
2356 temp &= ~(0x7 << 16);
2357 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2358 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2359
2360 POSTING_READ(reg);
2361 udelay(100);
2362
2363 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2364 if (HAS_PCH_IBX(dev)) {
2365 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2366 I915_WRITE(FDI_RX_CHICKEN(pipe),
2367 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18
JB		 2368 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2369 }
0fc932b8
JB		 2370
2371 /* still set train pattern 1 */
2372 reg = FDI_TX_CTL(pipe);
2373 temp = I915_READ(reg);
2374 temp &= ~FDI_LINK_TRAIN_NONE;
2375 temp |= FDI_LINK_TRAIN_PATTERN_1;
2376 I915_WRITE(reg, temp);
2377
2378 reg = FDI_RX_CTL(pipe);
2379 temp = I915_READ(reg);
2380 if (HAS_PCH_CPT(dev)) {
2381 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2382 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2383 } else {
2384 temp &= ~FDI_LINK_TRAIN_NONE;
2385 temp |= FDI_LINK_TRAIN_PATTERN_1;
2386 }
2387 /* BPC in FDI rx is consistent with that in PIPECONF */
2388 temp &= ~(0x07 << 16);
2389 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2390 I915_WRITE(reg, temp);
2391
2392 POSTING_READ(reg);
2393 udelay(100);
2394}
2395
6b383a7f
CW		 2396/*
2397 * When we disable a pipe, we need to clear any pending scanline wait events
2398 * to avoid hanging the ring, which we assume we are waiting on.
2399 */
2400static void intel_clear_scanline_wait(struct drm_device *dev)
2401{
2402 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2403 struct intel_ring_buffer *ring;
6b383a7f
CW		 2404 u32 tmp;
2405
2406 if (IS_GEN2(dev))
2407 /* Can't break the hang on i8xx */
2408 return;
2409
1ec14ad3 2410 ring = LP_RING(dev_priv);
8168bd48
CW		 2411 tmp = I915_READ_CTL(ring);
2412 if (tmp & RING_WAIT)
2413 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2414}
2415
e6c3a2a6
CW		 2416static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2417{
05394f39 2418 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2419 struct drm_i915_private *dev_priv;
2420
2421 if (crtc->fb == NULL)
2422 return;
2423
05394f39 2424 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2425 dev_priv = crtc->dev->dev_private;
2426 wait_event(dev_priv->pending_flip_queue,
05394f39 2427 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2428}
2429
040484af
JB		 2430static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2431{
2432 struct drm_device *dev = crtc->dev;
2433 struct drm_mode_config *mode_config = &dev->mode_config;
2434 struct intel_encoder *encoder;
2435
2436 /*
2437 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2438 * must be driven by its own crtc; no sharing is possible.
2439 */
2440 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2441 if (encoder->base.crtc != crtc)
2442 continue;
2443
2444 switch (encoder->type) {
2445 case INTEL_OUTPUT_EDP:
2446 if (!intel_encoder_is_pch_edp(&encoder->base))
2447 return false;
2448 continue;
2449 }
2450 }
2451
2452 return true;
2453}
2454
f67a559d
JB		 2455/*
2456 * Enable PCH resources required for PCH ports:
2457 * - PCH PLLs
2458 * - FDI training & RX/TX
2459 * - update transcoder timings
2460 * - DP transcoding bits
2461 * - transcoder
2462 */
2463static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2464{
2465 struct drm_device *dev = crtc->dev;
2466 struct drm_i915_private *dev_priv = dev->dev_private;
2467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2468 int pipe = intel_crtc->pipe;
5eddb70b 2469 u32 reg, temp;
2c07245f 2470
c98e9dcf
JB		 2471 /* For PCH output, training FDI link */
2472 if (IS_GEN6(dev))
2473 gen6_fdi_link_train(crtc);
2474 else
2475 ironlake_fdi_link_train(crtc);
2c07245f 2476
92f2584a 2477 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2478
c98e9dcf
JB		 2479 if (HAS_PCH_CPT(dev)) {
2480 /* Be sure PCH DPLL SEL is set */
2481 temp = I915_READ(PCH_DPLL_SEL);
5eddb70b 2482 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
c98e9dcf 2483 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
5eddb70b 2484 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
c98e9dcf
JB		 2485 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2486 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2487 }
5eddb70b 2488
d9b6cb56
JB		 2489 /* set transcoder timing, panel must allow it */
2490 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2491 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2492 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2493 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2494
5eddb70b
CW		 2495 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2496 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2497 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2498
5e84e1a4
ZW		 2499 intel_fdi_normal_train(crtc);
2500
c98e9dcf
JB		 2501 /* For PCH DP, enable TRANS_DP_CTL */
2502 if (HAS_PCH_CPT(dev) &&
2503 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5eddb70b
CW		 2504 reg = TRANS_DP_CTL(pipe);
2505 temp = I915_READ(reg);
2506 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2507 TRANS_DP_SYNC_MASK |
2508 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2509 temp |= (TRANS_DP_OUTPUT_ENABLE |
2510 TRANS_DP_ENH_FRAMING);
220cad3c 2511 temp |= TRANS_DP_8BPC;
c98e9dcf
JB		 2512
2513 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2514 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2515 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2516 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2517
2518 switch (intel_trans_dp_port_sel(crtc)) {
2519 case PCH_DP_B:
5eddb70b 2520 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2521 break;
2522 case PCH_DP_C:
5eddb70b 2523 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2524 break;
2525 case PCH_DP_D:
5eddb70b 2526 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2527 break;
2528 default:
2529 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2530 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2531 break;
32f9d658 2532 }
2c07245f 2533
5eddb70b 2534 I915_WRITE(reg, temp);
6be4a607 2535 }
b52eb4dc 2536
040484af 2537 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2538}
2539
2540static void ironlake_crtc_enable(struct drm_crtc *crtc)
2541{
2542 struct drm_device *dev = crtc->dev;
2543 struct drm_i915_private *dev_priv = dev->dev_private;
2544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2545 int pipe = intel_crtc->pipe;
2546 int plane = intel_crtc->plane;
2547 u32 temp;
2548 bool is_pch_port;
2549
2550 if (intel_crtc->active)
2551 return;
2552
2553 intel_crtc->active = true;
2554 intel_update_watermarks(dev);
2555
2556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2557 temp = I915_READ(PCH_LVDS);
2558 if ((temp & LVDS_PORT_EN) == 0)
2559 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2560 }
2561
2562 is_pch_port = intel_crtc_driving_pch(crtc);
2563
2564 if (is_pch_port)
2565 ironlake_fdi_enable(crtc);
2566 else
2567 ironlake_fdi_disable(crtc);
2568
2569 /* Enable panel fitting for LVDS */
2570 if (dev_priv->pch_pf_size &&
2571 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2572 /* Force use of hard-coded filter coefficients
2573 * as some pre-programmed values are broken,
2574 * e.g. x201.
2575 */
9db4a9c7
JB		 2576 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2577 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2578 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 2579 }
2580
2581 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2582 intel_enable_plane(dev_priv, plane, pipe);
2583
2584 if (is_pch_port)
2585 ironlake_pch_enable(crtc);
c98e9dcf 2586
6be4a607 2587 intel_crtc_load_lut(crtc);
bed4a673 2588 intel_update_fbc(dev);
6b383a7f 2589 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 2590}
2591
2592static void ironlake_crtc_disable(struct drm_crtc *crtc)
2593{
2594 struct drm_device *dev = crtc->dev;
2595 struct drm_i915_private *dev_priv = dev->dev_private;
2596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2597 int pipe = intel_crtc->pipe;
2598 int plane = intel_crtc->plane;
5eddb70b 2599 u32 reg, temp;
b52eb4dc 2600
f7abfe8b
CW		 2601 if (!intel_crtc->active)
2602 return;
2603
e6c3a2a6 2604 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 2605 drm_vblank_off(dev, pipe);
6b383a7f 2606 intel_crtc_update_cursor(crtc, false);
5eddb70b 2607
b24e7179 2608 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 2609
6be4a607
JB		 2610 if (dev_priv->cfb_plane == plane &&
2611 dev_priv->display.disable_fbc)
2612 dev_priv->display.disable_fbc(dev);
2c07245f 2613
b24e7179 2614 intel_disable_pipe(dev_priv, pipe);
32f9d658 2615
6be4a607 2616 /* Disable PF */
9db4a9c7
JB		 2617 I915_WRITE(PF_CTL(pipe), 0);
2618 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 2619
0fc932b8 2620 ironlake_fdi_disable(crtc);
2c07245f 2621
47a05eca
JB		 2622 /* This is a horrible layering violation; we should be doing this in
2623 * the connector/encoder ->prepare instead, but we don't always have
2624 * enough information there about the config to know whether it will
2625 * actually be necessary or just cause undesired flicker.
2626 */
2627 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 2628
040484af 2629 intel_disable_transcoder(dev_priv, pipe);
913d8d11 2630
6be4a607
JB		 2631 if (HAS_PCH_CPT(dev)) {
2632 /* disable TRANS_DP_CTL */
5eddb70b
CW		 2633 reg = TRANS_DP_CTL(pipe);
2634 temp = I915_READ(reg);
2635 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 2636 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 2637 I915_WRITE(reg, temp);
6be4a607
JB		 2638
2639 /* disable DPLL_SEL */
2640 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 2641 switch (pipe) {
2642 case 0:
2643 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2644 break;
2645 case 1:
6be4a607 2646 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 2647 break;
2648 case 2:
2649 /* FIXME: manage transcoder PLLs? */
2650 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2651 break;
2652 default:
2653 BUG(); /* wtf */
2654 }
6be4a607 2655 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 2656 }
e3421a18 2657
6be4a607 2658 /* disable PCH DPLL */
92f2584a 2659 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 2660
6be4a607 2661 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 2662 reg = FDI_RX_CTL(pipe);
2663 temp = I915_READ(reg);
2664 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 2665
6be4a607 2666 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 2667 reg = FDI_TX_CTL(pipe);
2668 temp = I915_READ(reg);
2669 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2670
2671 POSTING_READ(reg);
6be4a607 2672 udelay(100);
8db9d77b 2673
5eddb70b
CW		 2674 reg = FDI_RX_CTL(pipe);
2675 temp = I915_READ(reg);
2676 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 2677
6be4a607 2678 /* Wait for the clocks to turn off. */
5eddb70b 2679 POSTING_READ(reg);
6be4a607 2680 udelay(100);
6b383a7f 2681
f7abfe8b 2682 intel_crtc->active = false;
6b383a7f
CW		 2683 intel_update_watermarks(dev);
2684 intel_update_fbc(dev);
2685 intel_clear_scanline_wait(dev);
6be4a607 2686}
1b3c7a47 2687
6be4a607
JB		 2688static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2689{
2690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2691 int pipe = intel_crtc->pipe;
2692 int plane = intel_crtc->plane;
8db9d77b 2693
6be4a607
JB		 2694 /* XXX: When our outputs are all unaware of DPMS modes other than off
2695 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2696 */
2697 switch (mode) {
2698 case DRM_MODE_DPMS_ON:
2699 case DRM_MODE_DPMS_STANDBY:
2700 case DRM_MODE_DPMS_SUSPEND:
2701 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2702 ironlake_crtc_enable(crtc);
2703 break;
1b3c7a47 2704
6be4a607
JB		 2705 case DRM_MODE_DPMS_OFF:
2706 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2707 ironlake_crtc_disable(crtc);
2c07245f
ZW		 2708 break;
2709 }
2710}
2711
02e792fb
DV		 2712static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2713{
02e792fb 2714 if (!enable && intel_crtc->overlay) {
23f09ce3 2715 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 2716 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 2717
23f09ce3 2718 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 2719 dev_priv->mm.interruptible = false;
2720 (void) intel_overlay_switch_off(intel_crtc->overlay);
2721 dev_priv->mm.interruptible = true;
23f09ce3 2722 mutex_unlock(&dev->struct_mutex);
02e792fb 2723 }
02e792fb 2724
5dcdbcb0
CW		 2725 /* Let userspace switch the overlay on again. In most cases userspace
2726 * has to recompute where to put it anyway.
2727 */
02e792fb
DV		 2728}
2729
0b8765c6 2730static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 2731{
2732 struct drm_device *dev = crtc->dev;
79e53945
JB		 2733 struct drm_i915_private *dev_priv = dev->dev_private;
2734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2735 int pipe = intel_crtc->pipe;
80824003 2736 int plane = intel_crtc->plane;
79e53945 2737
f7abfe8b
CW		 2738 if (intel_crtc->active)
2739 return;
2740
2741 intel_crtc->active = true;
6b383a7f
CW		 2742 intel_update_watermarks(dev);
2743
63d7bbe9 2744 intel_enable_pll(dev_priv, pipe);
040484af 2745 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 2746 intel_enable_plane(dev_priv, plane, pipe);
79e53945 2747
0b8765c6 2748 intel_crtc_load_lut(crtc);
bed4a673 2749 intel_update_fbc(dev);
79e53945 2750
0b8765c6
JB		 2751 /* Give the overlay scaler a chance to enable if it's on this pipe */
2752 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 2753 intel_crtc_update_cursor(crtc, true);
0b8765c6 2754}
79e53945 2755
0b8765c6
JB		 2756static void i9xx_crtc_disable(struct drm_crtc *crtc)
2757{
2758 struct drm_device *dev = crtc->dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2761 int pipe = intel_crtc->pipe;
2762 int plane = intel_crtc->plane;
b690e96c 2763
f7abfe8b
CW		 2764 if (!intel_crtc->active)
2765 return;
2766
0b8765c6 2767 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 2768 intel_crtc_wait_for_pending_flips(crtc);
2769 drm_vblank_off(dev, pipe);
0b8765c6 2770 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 2771 intel_crtc_update_cursor(crtc, false);
0b8765c6
JB		 2772
2773 if (dev_priv->cfb_plane == plane &&
2774 dev_priv->display.disable_fbc)
2775 dev_priv->display.disable_fbc(dev);
79e53945 2776
b24e7179 2777 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 2778 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 2779 intel_disable_pll(dev_priv, pipe);
0b8765c6 2780
f7abfe8b 2781 intel_crtc->active = false;
6b383a7f
CW		 2782 intel_update_fbc(dev);
2783 intel_update_watermarks(dev);
2784 intel_clear_scanline_wait(dev);
0b8765c6
JB		 2785}
2786
2787static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2788{
2789 /* XXX: When our outputs are all unaware of DPMS modes other than off
2790 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2791 */
2792 switch (mode) {
2793 case DRM_MODE_DPMS_ON:
2794 case DRM_MODE_DPMS_STANDBY:
2795 case DRM_MODE_DPMS_SUSPEND:
2796 i9xx_crtc_enable(crtc);
2797 break;
2798 case DRM_MODE_DPMS_OFF:
2799 i9xx_crtc_disable(crtc);
79e53945
JB		 2800 break;
2801 }
2c07245f
ZW		 2802}
2803
2804/**
2805 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 2806 */
2807static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2808{
2809 struct drm_device *dev = crtc->dev;
e70236a8 2810 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 2811 struct drm_i915_master_private *master_priv;
2812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2813 int pipe = intel_crtc->pipe;
2814 bool enabled;
2815
032d2a0d
CW		 2816 if (intel_crtc->dpms_mode == mode)
2817 return;
2818
65655d4a 2819 intel_crtc->dpms_mode = mode;
debcaddc 2820
e70236a8 2821 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 2822
2823 if (!dev->primary->master)
2824 return;
2825
2826 master_priv = dev->primary->master->driver_priv;
2827 if (!master_priv->sarea_priv)
2828 return;
2829
2830 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2831
2832 switch (pipe) {
2833 case 0:
2834 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2835 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2836 break;
2837 case 1:
2838 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2839 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2840 break;
2841 default:
9db4a9c7 2842 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 2843 break;
2844 }
79e53945
JB		 2845}
2846
cdd59983
CW		 2847static void intel_crtc_disable(struct drm_crtc *crtc)
2848{
2849 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2850 struct drm_device *dev = crtc->dev;
2851
2852 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2853
2854 if (crtc->fb) {
2855 mutex_lock(&dev->struct_mutex);
2856 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2857 mutex_unlock(&dev->struct_mutex);
2858 }
2859}
2860
7e7d76c3
JB		 2861/* Prepare for a mode set.
2862 *
2863 * Note we could be a lot smarter here. We need to figure out which outputs
2864 * will be enabled, which disabled (in short, how the config will changes)
2865 * and perform the minimum necessary steps to accomplish that, e.g. updating
2866 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2867 * panel fitting is in the proper state, etc.
2868 */
2869static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 2870{
7e7d76c3 2871 i9xx_crtc_disable(crtc);
79e53945
JB		 2872}
2873
7e7d76c3 2874static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 2875{
7e7d76c3 2876 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 2877}
2878
2879static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2880{
7e7d76c3 2881 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 2882}
2883
2884static void ironlake_crtc_commit(struct drm_crtc *crtc)
2885{
7e7d76c3 2886 ironlake_crtc_enable(crtc);
79e53945
JB		 2887}
2888
2889void intel_encoder_prepare (struct drm_encoder *encoder)
2890{
2891 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2892 /* lvds has its own version of prepare see intel_lvds_prepare */
2893 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2894}
2895
2896void intel_encoder_commit (struct drm_encoder *encoder)
2897{
2898 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2899 /* lvds has its own version of commit see intel_lvds_commit */
2900 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2901}
2902
ea5b213a
CW		 2903void intel_encoder_destroy(struct drm_encoder *encoder)
2904{
4ef69c7a 2905 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 2906
ea5b213a
CW		 2907 drm_encoder_cleanup(encoder);
2908 kfree(intel_encoder);
2909}
2910
79e53945
JB		 2911static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2912 struct drm_display_mode *mode,
2913 struct drm_display_mode *adjusted_mode)
2914{
2c07245f 2915 struct drm_device *dev = crtc->dev;
89749350 2916
bad720ff 2917 if (HAS_PCH_SPLIT(dev)) {
2c07245f 2918 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 2919 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2920 return false;
2c07245f 2921 }
89749350
CW		 2922
2923 /* XXX some encoders set the crtcinfo, others don't.
2924 * Obviously we need some form of conflict resolution here...
2925 */
2926 if (adjusted_mode->crtc_htotal == 0)
2927 drm_mode_set_crtcinfo(adjusted_mode, 0);
2928
79e53945
JB		 2929 return true;
2930}
2931
e70236a8
JB		 2932static int i945_get_display_clock_speed(struct drm_device *dev)
2933{
2934 return 400000;
2935}
79e53945 2936
e70236a8 2937static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 2938{
e70236a8
JB		 2939 return 333000;
2940}
79e53945 2941
e70236a8
JB		 2942static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2943{
2944 return 200000;
2945}
79e53945 2946
e70236a8
JB		 2947static int i915gm_get_display_clock_speed(struct drm_device *dev)
2948{
2949 u16 gcfgc = 0;
79e53945 2950
e70236a8
JB		 2951 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2952
2953 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2954 return 133000;
2955 else {
2956 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2957 case GC_DISPLAY_CLOCK_333_MHZ:
2958 return 333000;
2959 default:
2960 case GC_DISPLAY_CLOCK_190_200_MHZ:
2961 return 190000;
79e53945 2962 }
e70236a8
JB		 2963 }
2964}
2965
2966static int i865_get_display_clock_speed(struct drm_device *dev)
2967{
2968 return 266000;
2969}
2970
2971static int i855_get_display_clock_speed(struct drm_device *dev)
2972{
2973 u16 hpllcc = 0;
2974 /* Assume that the hardware is in the high speed state. This
2975 * should be the default.
2976 */
2977 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2978 case GC_CLOCK_133_200:
2979 case GC_CLOCK_100_200:
2980 return 200000;
2981 case GC_CLOCK_166_250:
2982 return 250000;
2983 case GC_CLOCK_100_133:
79e53945 2984 return 133000;
e70236a8 2985 }
79e53945 2986
e70236a8
JB		 2987 /* Shouldn't happen */
2988 return 0;
2989}
79e53945 2990
e70236a8
JB		 2991static int i830_get_display_clock_speed(struct drm_device *dev)
2992{
2993 return 133000;
79e53945
JB		 2994}
2995
2c07245f
ZW		 2996struct fdi_m_n {
2997 u32 tu;
2998 u32 gmch_m;
2999 u32 gmch_n;
3000 u32 link_m;
3001 u32 link_n;
3002};
3003
3004static void
3005fdi_reduce_ratio(u32 *num, u32 *den)
3006{
3007 while (*num > 0xffffff || *den > 0xffffff) {
3008 *num >>= 1;
3009 *den >>= 1;
3010 }
3011}
3012
2c07245f 3013static void
f2b115e6
AJ		 3014ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3015 int link_clock, struct fdi_m_n *m_n)
2c07245f 3016{
2c07245f
ZW		 3017 m_n->tu = 64; /* default size */
3018
22ed1113
CW		 3019 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3020 m_n->gmch_m = bits_per_pixel * pixel_clock;
3021 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3022 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3023
22ed1113
CW		 3024 m_n->link_m = pixel_clock;
3025 m_n->link_n = link_clock;
2c07245f
ZW		 3026 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3027}
3028
3029
7662c8bd
SL		 3030struct intel_watermark_params {
3031 unsigned long fifo_size;
3032 unsigned long max_wm;
3033 unsigned long default_wm;
3034 unsigned long guard_size;
3035 unsigned long cacheline_size;
3036};
3037
f2b115e6 3038/* Pineview has different values for various configs */
d210246a 3039static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3040 PINEVIEW_DISPLAY_FIFO,
3041 PINEVIEW_MAX_WM,
3042 PINEVIEW_DFT_WM,
3043 PINEVIEW_GUARD_WM,
3044 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3045};
d210246a 3046static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3047 PINEVIEW_DISPLAY_FIFO,
3048 PINEVIEW_MAX_WM,
3049 PINEVIEW_DFT_HPLLOFF_WM,
3050 PINEVIEW_GUARD_WM,
3051 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3052};
d210246a 3053static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3054 PINEVIEW_CURSOR_FIFO,
3055 PINEVIEW_CURSOR_MAX_WM,
3056 PINEVIEW_CURSOR_DFT_WM,
3057 PINEVIEW_CURSOR_GUARD_WM,
3058 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3059};
d210246a 3060static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3061 PINEVIEW_CURSOR_FIFO,
3062 PINEVIEW_CURSOR_MAX_WM,
3063 PINEVIEW_CURSOR_DFT_WM,
3064 PINEVIEW_CURSOR_GUARD_WM,
3065 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3066};
d210246a 3067static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3068 G4X_FIFO_SIZE,
3069 G4X_MAX_WM,
3070 G4X_MAX_WM,
3071 2,
3072 G4X_FIFO_LINE_SIZE,
3073};
d210246a 3074static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3075 I965_CURSOR_FIFO,
3076 I965_CURSOR_MAX_WM,
3077 I965_CURSOR_DFT_WM,
3078 2,
3079 G4X_FIFO_LINE_SIZE,
3080};
d210246a 3081static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3082 I965_CURSOR_FIFO,
3083 I965_CURSOR_MAX_WM,
3084 I965_CURSOR_DFT_WM,
3085 2,
3086 I915_FIFO_LINE_SIZE,
3087};
d210246a 3088static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3089 I945_FIFO_SIZE,
7662c8bd
SL		 3090 I915_MAX_WM,
3091 1,
dff33cfc
JB		 3092 2,
3093 I915_FIFO_LINE_SIZE
7662c8bd 3094};
d210246a 3095static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3096 I915_FIFO_SIZE,
7662c8bd
SL		 3097 I915_MAX_WM,
3098 1,
dff33cfc 3099 2,
7662c8bd
SL		 3100 I915_FIFO_LINE_SIZE
3101};
d210246a 3102static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3103 I855GM_FIFO_SIZE,
3104 I915_MAX_WM,
3105 1,
dff33cfc 3106 2,
7662c8bd
SL		 3107 I830_FIFO_LINE_SIZE
3108};
d210246a 3109static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3110 I830_FIFO_SIZE,
3111 I915_MAX_WM,
3112 1,
dff33cfc 3113 2,
7662c8bd
SL		 3114 I830_FIFO_LINE_SIZE
3115};
3116
d210246a 3117static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3118 ILK_DISPLAY_FIFO,
3119 ILK_DISPLAY_MAXWM,
3120 ILK_DISPLAY_DFTWM,
3121 2,
3122 ILK_FIFO_LINE_SIZE
3123};
d210246a 3124static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3125 ILK_CURSOR_FIFO,
3126 ILK_CURSOR_MAXWM,
3127 ILK_CURSOR_DFTWM,
3128 2,
3129 ILK_FIFO_LINE_SIZE
3130};
d210246a 3131static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3132 ILK_DISPLAY_SR_FIFO,
3133 ILK_DISPLAY_MAX_SRWM,
3134 ILK_DISPLAY_DFT_SRWM,
3135 2,
3136 ILK_FIFO_LINE_SIZE
3137};
d210246a 3138static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3139 ILK_CURSOR_SR_FIFO,
3140 ILK_CURSOR_MAX_SRWM,
3141 ILK_CURSOR_DFT_SRWM,
3142 2,
3143 ILK_FIFO_LINE_SIZE
3144};
3145
d210246a 3146static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3147 SNB_DISPLAY_FIFO,
3148 SNB_DISPLAY_MAXWM,
3149 SNB_DISPLAY_DFTWM,
3150 2,
3151 SNB_FIFO_LINE_SIZE
3152};
d210246a 3153static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3154 SNB_CURSOR_FIFO,
3155 SNB_CURSOR_MAXWM,
3156 SNB_CURSOR_DFTWM,
3157 2,
3158 SNB_FIFO_LINE_SIZE
3159};
d210246a 3160static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3161 SNB_DISPLAY_SR_FIFO,
3162 SNB_DISPLAY_MAX_SRWM,
3163 SNB_DISPLAY_DFT_SRWM,
3164 2,
3165 SNB_FIFO_LINE_SIZE
3166};
d210246a 3167static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3168 SNB_CURSOR_SR_FIFO,
3169 SNB_CURSOR_MAX_SRWM,
3170 SNB_CURSOR_DFT_SRWM,
3171 2,
3172 SNB_FIFO_LINE_SIZE
3173};
3174
3175
dff33cfc
JB		 3176/**
3177 * intel_calculate_wm - calculate watermark level
3178 * @clock_in_khz: pixel clock
3179 * @wm: chip FIFO params
3180 * @pixel_size: display pixel size
3181 * @latency_ns: memory latency for the platform
3182 *
3183 * Calculate the watermark level (the level at which the display plane will
3184 * start fetching from memory again). Each chip has a different display
3185 * FIFO size and allocation, so the caller needs to figure that out and pass
3186 * in the correct intel_watermark_params structure.
3187 *
3188 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3189 * on the pixel size. When it reaches the watermark level, it'll start
3190 * fetching FIFO line sized based chunks from memory until the FIFO fills
3191 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3192 * will occur, and a display engine hang could result.
3193 */
7662c8bd 3194static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3195 const struct intel_watermark_params *wm,
3196 int fifo_size,
7662c8bd
SL		 3197 int pixel_size,
3198 unsigned long latency_ns)
3199{
390c4dd4 3200 long entries_required, wm_size;
dff33cfc 3201
d660467c
JB		 3202 /*
3203 * Note: we need to make sure we don't overflow for various clock &
3204 * latency values.
3205 * clocks go from a few thousand to several hundred thousand.
3206 * latency is usually a few thousand
3207 */
3208 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3209 1000;
8de9b311 3210 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3211
28c97730 3212 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
dff33cfc 3213
d210246a 3214 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3215
28c97730 3216 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
7662c8bd 3217
390c4dd4
JB		 3218 /* Don't promote wm_size to unsigned... */
3219 if (wm_size > (long)wm->max_wm)
7662c8bd 3220 wm_size = wm->max_wm;
c3add4b6 3221 if (wm_size <= 0)
7662c8bd
SL		 3222 wm_size = wm->default_wm;
3223 return wm_size;
3224}
3225
3226struct cxsr_latency {
3227 int is_desktop;
95534263 3228 int is_ddr3;
7662c8bd
SL		 3229 unsigned long fsb_freq;
3230 unsigned long mem_freq;
3231 unsigned long display_sr;
3232 unsigned long display_hpll_disable;
3233 unsigned long cursor_sr;
3234 unsigned long cursor_hpll_disable;
3235};
3236
403c89ff 3237static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3238 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3239 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3240 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3241 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3242 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3243
3244 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3245 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3246 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3247 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3248 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3249
3250 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3251 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3252 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3253 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3254 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3255
3256 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3257 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3258 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3259 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3260 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3261
3262 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3263 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3264 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3265 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3266 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3267
3268 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3269 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3270 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3271 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3272 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3273};
3274
403c89ff
CW		 3275static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3276 int is_ddr3,
3277 int fsb,
3278 int mem)
7662c8bd 3279{
403c89ff 3280 const struct cxsr_latency *latency;
7662c8bd 3281 int i;
7662c8bd
SL		 3282
3283 if (fsb == 0 || mem == 0)
3284 return NULL;
3285
3286 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3287 latency = &cxsr_latency_table[i];
3288 if (is_desktop == latency->is_desktop &&
95534263 3289 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3290 fsb == latency->fsb_freq && mem == latency->mem_freq)
3291 return latency;
7662c8bd 3292 }
decbbcda 3293
28c97730 3294 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3295
3296 return NULL;
7662c8bd
SL		 3297}
3298
f2b115e6 3299static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3300{
3301 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3302
3303 /* deactivate cxsr */
3e33d94d 3304 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3305}
3306
bcc24fb4
JB		 3307/*
3308 * Latency for FIFO fetches is dependent on several factors:
3309 * - memory configuration (speed, channels)
3310 * - chipset
3311 * - current MCH state
3312 * It can be fairly high in some situations, so here we assume a fairly
3313 * pessimal value. It's a tradeoff between extra memory fetches (if we
3314 * set this value too high, the FIFO will fetch frequently to stay full)
3315 * and power consumption (set it too low to save power and we might see
3316 * FIFO underruns and display "flicker").
3317 *
3318 * A value of 5us seems to be a good balance; safe for very low end
3319 * platforms but not overly aggressive on lower latency configs.
3320 */
69e302a9 3321static const int latency_ns = 5000;
7662c8bd 3322
e70236a8 3323static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3324{
3325 struct drm_i915_private *dev_priv = dev->dev_private;
3326 uint32_t dsparb = I915_READ(DSPARB);
3327 int size;
3328
8de9b311
CW		 3329 size = dsparb & 0x7f;
3330 if (plane)
3331 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3332
28c97730 3333 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3334 plane ? "B" : "A", size);
dff33cfc
JB		 3335
3336 return size;
3337}
7662c8bd 3338
e70236a8
JB		 3339static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3340{
3341 struct drm_i915_private *dev_priv = dev->dev_private;
3342 uint32_t dsparb = I915_READ(DSPARB);
3343 int size;
3344
8de9b311
CW		 3345 size = dsparb & 0x1ff;
3346 if (plane)
3347 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3348 size >>= 1; /* Convert to cachelines */
dff33cfc 3349
28c97730 3350 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3351 plane ? "B" : "A", size);
dff33cfc
JB		 3352
3353 return size;
3354}
7662c8bd 3355
e70236a8
JB		 3356static int i845_get_fifo_size(struct drm_device *dev, int plane)
3357{
3358 struct drm_i915_private *dev_priv = dev->dev_private;
3359 uint32_t dsparb = I915_READ(DSPARB);
3360 int size;
3361
3362 size = dsparb & 0x7f;
3363 size >>= 2; /* Convert to cachelines */
3364
28c97730 3365 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3366 plane ? "B" : "A",
3367 size);
e70236a8
JB		 3368
3369 return size;
3370}
3371
3372static int i830_get_fifo_size(struct drm_device *dev, int plane)
3373{
3374 struct drm_i915_private *dev_priv = dev->dev_private;
3375 uint32_t dsparb = I915_READ(DSPARB);
3376 int size;
3377
3378 size = dsparb & 0x7f;
3379 size >>= 1; /* Convert to cachelines */
3380
28c97730 3381 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3382 plane ? "B" : "A", size);
e70236a8
JB		 3383
3384 return size;
3385}
3386
d210246a
CW		 3387static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3388{
3389 struct drm_crtc *crtc, *enabled = NULL;
3390
3391 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3392 if (crtc->enabled && crtc->fb) {
3393 if (enabled)
3394 return NULL;
3395 enabled = crtc;
3396 }
3397 }
3398
3399 return enabled;
3400}
3401
3402static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3403{
3404 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3405 struct drm_crtc *crtc;
403c89ff 3406 const struct cxsr_latency *latency;
d4294342
ZY		 3407 u32 reg;
3408 unsigned long wm;
d4294342 3409
403c89ff 3410 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3411 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3412 if (!latency) {
3413 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3414 pineview_disable_cxsr(dev);
3415 return;
3416 }
3417
d210246a
CW		 3418 crtc = single_enabled_crtc(dev);
3419 if (crtc) {
3420 int clock = crtc->mode.clock;
3421 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3422
3423 /* Display SR */
d210246a
CW		 3424 wm = intel_calculate_wm(clock, &pineview_display_wm,
3425 pineview_display_wm.fifo_size,
d4294342
ZY		 3426 pixel_size, latency->display_sr);
3427 reg = I915_READ(DSPFW1);
3428 reg &= ~DSPFW_SR_MASK;
3429 reg |= wm << DSPFW_SR_SHIFT;
3430 I915_WRITE(DSPFW1, reg);
3431 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3432
3433 /* cursor SR */
d210246a
CW		 3434 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3435 pineview_display_wm.fifo_size,
d4294342
ZY		 3436 pixel_size, latency->cursor_sr);
3437 reg = I915_READ(DSPFW3);
3438 reg &= ~DSPFW_CURSOR_SR_MASK;
3439 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3440 I915_WRITE(DSPFW3, reg);
3441
3442 /* Display HPLL off SR */
d210246a
CW		 3443 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3444 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3445 pixel_size, latency->display_hpll_disable);
3446 reg = I915_READ(DSPFW3);
3447 reg &= ~DSPFW_HPLL_SR_MASK;
3448 reg |= wm & DSPFW_HPLL_SR_MASK;
3449 I915_WRITE(DSPFW3, reg);
3450
3451 /* cursor HPLL off SR */
d210246a
CW		 3452 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3453 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3454 pixel_size, latency->cursor_hpll_disable);
3455 reg = I915_READ(DSPFW3);
3456 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3457 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3458 I915_WRITE(DSPFW3, reg);
3459 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3460
3461 /* activate cxsr */
3e33d94d
CW		 3462 I915_WRITE(DSPFW3,
3463 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3464 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3465 } else {
3466 pineview_disable_cxsr(dev);
3467 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3468 }
3469}
3470
417ae147
CW		 3471static bool g4x_compute_wm0(struct drm_device *dev,
3472 int plane,
3473 const struct intel_watermark_params *display,
3474 int display_latency_ns,
3475 const struct intel_watermark_params *cursor,
3476 int cursor_latency_ns,
3477 int *plane_wm,
3478 int *cursor_wm)
3479{
3480 struct drm_crtc *crtc;
3481 int htotal, hdisplay, clock, pixel_size;
3482 int line_time_us, line_count;
3483 int entries, tlb_miss;
3484
3485 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 3486 if (crtc->fb == NULL || !crtc->enabled) {
3487 *cursor_wm = cursor->guard_size;
3488 *plane_wm = display->guard_size;
417ae147 3489 return false;
5c72d064 3490 }
417ae147
CW		 3491
3492 htotal = crtc->mode.htotal;
3493 hdisplay = crtc->mode.hdisplay;
3494 clock = crtc->mode.clock;
3495 pixel_size = crtc->fb->bits_per_pixel / 8;
3496
3497 /* Use the small buffer method to calculate plane watermark */
3498 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3499 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3500 if (tlb_miss > 0)
3501 entries += tlb_miss;
3502 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3503 *plane_wm = entries + display->guard_size;
3504 if (*plane_wm > (int)display->max_wm)
3505 *plane_wm = display->max_wm;
3506
3507 /* Use the large buffer method to calculate cursor watermark */
3508 line_time_us = ((htotal * 1000) / clock);
3509 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3510 entries = line_count * 64 * pixel_size;
3511 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3512 if (tlb_miss > 0)
3513 entries += tlb_miss;
3514 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3515 *cursor_wm = entries + cursor->guard_size;
3516 if (*cursor_wm > (int)cursor->max_wm)
3517 *cursor_wm = (int)cursor->max_wm;
3518
3519 return true;
3520}
3521
3522/*
3523 * Check the wm result.
3524 *
3525 * If any calculated watermark values is larger than the maximum value that
3526 * can be programmed into the associated watermark register, that watermark
3527 * must be disabled.
3528 */
3529static bool g4x_check_srwm(struct drm_device *dev,
3530 int display_wm, int cursor_wm,
3531 const struct intel_watermark_params *display,
3532 const struct intel_watermark_params *cursor)
652c393a 3533{
417ae147
CW		 3534 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3535 display_wm, cursor_wm);
652c393a 3536
417ae147
CW		 3537 if (display_wm > display->max_wm) {
3538 DRM_DEBUG_KMS("display watermark is too large(%d), disabling\n",
3539 display_wm, display->max_wm);
3540 return false;
3541 }
0e442c60 3542
417ae147
CW		 3543 if (cursor_wm > cursor->max_wm) {
3544 DRM_DEBUG_KMS("cursor watermark is too large(%d), disabling\n",
3545 cursor_wm, cursor->max_wm);
3546 return false;
3547 }
0e442c60 3548
417ae147
CW		 3549 if (!(display_wm || cursor_wm)) {
3550 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3551 return false;
3552 }
0e442c60 3553
417ae147
CW		 3554 return true;
3555}
0e442c60 3556
417ae147 3557static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 3558 int plane,
3559 int latency_ns,
417ae147
CW		 3560 const struct intel_watermark_params *display,
3561 const struct intel_watermark_params *cursor,
3562 int *display_wm, int *cursor_wm)
3563{
d210246a
CW		 3564 struct drm_crtc *crtc;
3565 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 3566 unsigned long line_time_us;
3567 int line_count, line_size;
3568 int small, large;
3569 int entries;
0e442c60 3570
417ae147
CW		 3571 if (!latency_ns) {
3572 *display_wm = *cursor_wm = 0;
3573 return false;
3574 }
0e442c60 3575
d210246a
CW		 3576 crtc = intel_get_crtc_for_plane(dev, plane);
3577 hdisplay = crtc->mode.hdisplay;
3578 htotal = crtc->mode.htotal;
3579 clock = crtc->mode.clock;
3580 pixel_size = crtc->fb->bits_per_pixel / 8;
3581
417ae147
CW		 3582 line_time_us = (htotal * 1000) / clock;
3583 line_count = (latency_ns / line_time_us + 1000) / 1000;
3584 line_size = hdisplay * pixel_size;
0e442c60 3585
417ae147
CW		 3586 /* Use the minimum of the small and large buffer method for primary */
3587 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3588 large = line_count * line_size;
0e442c60 3589
417ae147
CW		 3590 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3591 *display_wm = entries + display->guard_size;
4fe5e611 3592
417ae147
CW		 3593 /* calculate the self-refresh watermark for display cursor */
3594 entries = line_count * pixel_size * 64;
3595 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3596 *cursor_wm = entries + cursor->guard_size;
4fe5e611 3597
417ae147
CW		 3598 return g4x_check_srwm(dev,
3599 *display_wm, *cursor_wm,
3600 display, cursor);
3601}
4fe5e611 3602
7ccb4a53 3603#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 3604
3605static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 3606{
3607 static const int sr_latency_ns = 12000;
3608 struct drm_i915_private *dev_priv = dev->dev_private;
3609 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 3610 int plane_sr, cursor_sr;
3611 unsigned int enabled = 0;
417ae147
CW		 3612
3613 if (g4x_compute_wm0(dev, 0,
3614 &g4x_wm_info, latency_ns,
3615 &g4x_cursor_wm_info, latency_ns,
3616 &planea_wm, &cursora_wm))
d210246a 3617 enabled |= 1;
417ae147
CW		 3618
3619 if (g4x_compute_wm0(dev, 1,
3620 &g4x_wm_info, latency_ns,
3621 &g4x_cursor_wm_info, latency_ns,
3622 &planeb_wm, &cursorb_wm))
d210246a 3623 enabled |= 2;
417ae147
CW		 3624
3625 plane_sr = cursor_sr = 0;
d210246a
CW		 3626 if (single_plane_enabled(enabled) &&
3627 g4x_compute_srwm(dev, ffs(enabled) - 1,
3628 sr_latency_ns,
417ae147
CW		 3629 &g4x_wm_info,
3630 &g4x_cursor_wm_info,
3631 &plane_sr, &cursor_sr))
0e442c60 3632 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 3633 else
3634 I915_WRITE(FW_BLC_SELF,
3635 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 3636
308977ac
CW		 3637 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3638 planea_wm, cursora_wm,
3639 planeb_wm, cursorb_wm,
3640 plane_sr, cursor_sr);
0e442c60 3641
417ae147
CW		 3642 I915_WRITE(DSPFW1,
3643 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 3644 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 3645 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3646 planea_wm);
3647 I915_WRITE(DSPFW2,
3648 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 3649 (cursora_wm << DSPFW_CURSORA_SHIFT));
3650 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 3651 I915_WRITE(DSPFW3,
3652 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 3653 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 3654}
3655
d210246a 3656static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 3657{
3658 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 3659 struct drm_crtc *crtc;
3660 int srwm = 1;
4fe5e611 3661 int cursor_sr = 16;
1dc7546d
JB		 3662
3663 /* Calc sr entries for one plane configs */
d210246a
CW		 3664 crtc = single_enabled_crtc(dev);
3665 if (crtc) {
1dc7546d 3666 /* self-refresh has much higher latency */
69e302a9 3667 static const int sr_latency_ns = 12000;
d210246a
CW		 3668 int clock = crtc->mode.clock;
3669 int htotal = crtc->mode.htotal;
3670 int hdisplay = crtc->mode.hdisplay;
3671 int pixel_size = crtc->fb->bits_per_pixel / 8;
3672 unsigned long line_time_us;
3673 int entries;
1dc7546d 3674
d210246a 3675 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 3676
3677 /* Use ns/us then divide to preserve precision */
d210246a
CW		 3678 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3679 pixel_size * hdisplay;
3680 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 3681 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 3682 if (srwm < 0)
3683 srwm = 1;
1b07e04e 3684 srwm &= 0x1ff;
308977ac
CW		 3685 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3686 entries, srwm);
4fe5e611 3687
d210246a 3688 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 3689 pixel_size * 64;
d210246a 3690 entries = DIV_ROUND_UP(entries,
8de9b311 3691 i965_cursor_wm_info.cacheline_size);
4fe5e611 3692 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 3693 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 3694
3695 if (cursor_sr > i965_cursor_wm_info.max_wm)
3696 cursor_sr = i965_cursor_wm_info.max_wm;
3697
3698 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3699 "cursor %d\n", srwm, cursor_sr);
3700
a6c45cf0 3701 if (IS_CRESTLINE(dev))
adcdbc66 3702 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 3703 } else {
3704 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 3705 if (IS_CRESTLINE(dev))
adcdbc66
JB		 3706 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3707 & ~FW_BLC_SELF_EN);
1dc7546d 3708 }
7662c8bd 3709
1dc7546d
JB		 3710 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3711 srwm);
7662c8bd
SL		 3712
3713 /* 965 has limitations... */
417ae147
CW		 3714 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3715 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 3716 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 3717 /* update cursor SR watermark */
3718 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 3719}
3720
d210246a 3721static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 3722{
3723 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3724 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 3725 uint32_t fwater_lo;
3726 uint32_t fwater_hi;
d210246a
CW		 3727 int cwm, srwm = 1;
3728 int fifo_size;
dff33cfc 3729 int planea_wm, planeb_wm;
d210246a 3730 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 3731
72557b4f 3732 if (IS_I945GM(dev))
d210246a 3733 wm_info = &i945_wm_info;
a6c45cf0 3734 else if (!IS_GEN2(dev))
d210246a 3735 wm_info = &i915_wm_info;
7662c8bd 3736 else
d210246a
CW		 3737 wm_info = &i855_wm_info;
3738
3739 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3740 crtc = intel_get_crtc_for_plane(dev, 0);
3741 if (crtc->enabled && crtc->fb) {
3742 planea_wm = intel_calculate_wm(crtc->mode.clock,
3743 wm_info, fifo_size,
3744 crtc->fb->bits_per_pixel / 8,
3745 latency_ns);
3746 enabled = crtc;
3747 } else
3748 planea_wm = fifo_size - wm_info->guard_size;
3749
3750 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3751 crtc = intel_get_crtc_for_plane(dev, 1);
3752 if (crtc->enabled && crtc->fb) {
3753 planeb_wm = intel_calculate_wm(crtc->mode.clock,
3754 wm_info, fifo_size,
3755 crtc->fb->bits_per_pixel / 8,
3756 latency_ns);
3757 if (enabled == NULL)
3758 enabled = crtc;
3759 else
3760 enabled = NULL;
3761 } else
3762 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 3763
28c97730 3764 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 3765
3766 /*
3767 * Overlay gets an aggressive default since video jitter is bad.
3768 */
3769 cwm = 2;
3770
18b2190c
AL		 3771 /* Play safe and disable self-refresh before adjusting watermarks. */
3772 if (IS_I945G(dev) || IS_I945GM(dev))
3773 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3774 else if (IS_I915GM(dev))
3775 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3776
dff33cfc 3777 /* Calc sr entries for one plane configs */
d210246a 3778 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 3779 /* self-refresh has much higher latency */
69e302a9 3780 static const int sr_latency_ns = 6000;
d210246a
CW		 3781 int clock = enabled->mode.clock;
3782 int htotal = enabled->mode.htotal;
3783 int hdisplay = enabled->mode.hdisplay;
3784 int pixel_size = enabled->fb->bits_per_pixel / 8;
3785 unsigned long line_time_us;
3786 int entries;
dff33cfc 3787
d210246a 3788 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 3789
3790 /* Use ns/us then divide to preserve precision */
d210246a
CW		 3791 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3792 pixel_size * hdisplay;
3793 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
3794 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
3795 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 3796 if (srwm < 0)
3797 srwm = 1;
ee980b80
LP		 3798
3799 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 3800 I915_WRITE(FW_BLC_SELF,
3801 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3802 else if (IS_I915GM(dev))
ee980b80 3803 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 3804 }
3805
28c97730 3806 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 3807 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 3808
dff33cfc
JB		 3809 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3810 fwater_hi = (cwm & 0x1f);
3811
3812 /* Set request length to 8 cachelines per fetch */
3813 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3814 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 3815
3816 I915_WRITE(FW_BLC, fwater_lo);
3817 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 3818
d210246a
CW		 3819 if (HAS_FW_BLC(dev)) {
3820 if (enabled) {
3821 if (IS_I945G(dev) || IS_I945GM(dev))
3822 I915_WRITE(FW_BLC_SELF,
3823 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
3824 else if (IS_I915GM(dev))
3825 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3826 DRM_DEBUG_KMS("memory self refresh enabled\n");
3827 } else
3828 DRM_DEBUG_KMS("memory self refresh disabled\n");
3829 }
7662c8bd
SL		 3830}
3831
d210246a 3832static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 3833{
3834 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 3835 struct drm_crtc *crtc;
3836 uint32_t fwater_lo;
dff33cfc 3837 int planea_wm;
7662c8bd 3838
d210246a
CW		 3839 crtc = single_enabled_crtc(dev);
3840 if (crtc == NULL)
3841 return;
7662c8bd 3842
d210246a
CW		 3843 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
3844 dev_priv->display.get_fifo_size(dev, 0),
3845 crtc->fb->bits_per_pixel / 8,
3846 latency_ns);
3847 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 3848 fwater_lo |= (3<<8) | planea_wm;
3849
28c97730 3850 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 3851
3852 I915_WRITE(FW_BLC, fwater_lo);
3853}
3854
7f8a8569 3855#define ILK_LP0_PLANE_LATENCY 700
c936f44d 3856#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 3857
4ed765f9
CW		 3858static bool ironlake_compute_wm0(struct drm_device *dev,
3859 int pipe,
1398261a 3860 const struct intel_watermark_params *display,
a0fa62d3 3861 int display_latency_ns,
1398261a 3862 const struct intel_watermark_params *cursor,
a0fa62d3 3863 int cursor_latency_ns,
4ed765f9
CW		 3864 int *plane_wm,
3865 int *cursor_wm)
7f8a8569 3866{
c936f44d 3867 struct drm_crtc *crtc;
db66e37d
CW		 3868 int htotal, hdisplay, clock, pixel_size;
3869 int line_time_us, line_count;
3870 int entries, tlb_miss;
c936f44d 3871
4ed765f9
CW		 3872 crtc = intel_get_crtc_for_pipe(dev, pipe);
3873 if (crtc->fb == NULL || !crtc->enabled)
3874 return false;
7f8a8569 3875
4ed765f9
CW		 3876 htotal = crtc->mode.htotal;
3877 hdisplay = crtc->mode.hdisplay;
3878 clock = crtc->mode.clock;
3879 pixel_size = crtc->fb->bits_per_pixel / 8;
3880
3881 /* Use the small buffer method to calculate plane watermark */
a0fa62d3 3882 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
db66e37d
CW		 3883 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3884 if (tlb_miss > 0)
3885 entries += tlb_miss;
1398261a
YL		 3886 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3887 *plane_wm = entries + display->guard_size;
3888 if (*plane_wm > (int)display->max_wm)
3889 *plane_wm = display->max_wm;
4ed765f9
CW		 3890
3891 /* Use the large buffer method to calculate cursor watermark */
3892 line_time_us = ((htotal * 1000) / clock);
a0fa62d3 3893 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4ed765f9 3894 entries = line_count * 64 * pixel_size;
db66e37d
CW		 3895 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3896 if (tlb_miss > 0)
3897 entries += tlb_miss;
1398261a
YL		 3898 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3899 *cursor_wm = entries + cursor->guard_size;
3900 if (*cursor_wm > (int)cursor->max_wm)
3901 *cursor_wm = (int)cursor->max_wm;
7f8a8569 3902
4ed765f9
CW		 3903 return true;
3904}
c936f44d 3905
1398261a
YL		 3906/*
3907 * Check the wm result.
3908 *
3909 * If any calculated watermark values is larger than the maximum value that
3910 * can be programmed into the associated watermark register, that watermark
3911 * must be disabled.
1398261a 3912 */
b79d4990
JB		 3913static bool ironlake_check_srwm(struct drm_device *dev, int level,
3914 int fbc_wm, int display_wm, int cursor_wm,
3915 const struct intel_watermark_params *display,
3916 const struct intel_watermark_params *cursor)
1398261a
YL		 3917{
3918 struct drm_i915_private *dev_priv = dev->dev_private;
3919
3920 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
3921 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
3922
3923 if (fbc_wm > SNB_FBC_MAX_SRWM) {
3924 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 3925 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 3926
3927 /* fbc has it's own way to disable FBC WM */
3928 I915_WRITE(DISP_ARB_CTL,
3929 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
3930 return false;
3931 }
3932
b79d4990 3933 if (display_wm > display->max_wm) {
1398261a 3934 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 3935 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 3936 return false;
3937 }
3938
b79d4990 3939 if (cursor_wm > cursor->max_wm) {
1398261a 3940 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 3941 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 3942 return false;
3943 }
3944
3945 if (!(fbc_wm || display_wm || cursor_wm)) {
3946 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
3947 return false;
3948 }
3949
3950 return true;
3951}
3952
3953/*
3954 * Compute watermark values of WM[1-3],
3955 */
d210246a
CW		 3956static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
3957 int latency_ns,
b79d4990
JB		 3958 const struct intel_watermark_params *display,
3959 const struct intel_watermark_params *cursor,
3960 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 3961{
d210246a 3962 struct drm_crtc *crtc;
1398261a 3963 unsigned long line_time_us;
d210246a 3964 int hdisplay, htotal, pixel_size, clock;
b79d4990 3965 int line_count, line_size;
1398261a
YL		 3966 int small, large;
3967 int entries;
1398261a
YL		 3968
3969 if (!latency_ns) {
3970 *fbc_wm = *display_wm = *cursor_wm = 0;
3971 return false;
3972 }
3973
d210246a
CW		 3974 crtc = intel_get_crtc_for_plane(dev, plane);
3975 hdisplay = crtc->mode.hdisplay;
3976 htotal = crtc->mode.htotal;
3977 clock = crtc->mode.clock;
3978 pixel_size = crtc->fb->bits_per_pixel / 8;
3979
1398261a
YL		 3980 line_time_us = (htotal * 1000) / clock;
3981 line_count = (latency_ns / line_time_us + 1000) / 1000;
3982 line_size = hdisplay * pixel_size;
3983
3984 /* Use the minimum of the small and large buffer method for primary */
3985 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3986 large = line_count * line_size;
3987
b79d4990
JB		 3988 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3989 *display_wm = entries + display->guard_size;
1398261a
YL		 3990
3991 /*
b79d4990 3992 * Spec says:
1398261a
YL		 3993 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
3994 */
3995 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
3996
3997 /* calculate the self-refresh watermark for display cursor */
3998 entries = line_count * pixel_size * 64;
b79d4990
JB		 3999 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4000 *cursor_wm = entries + cursor->guard_size;
1398261a 4001
b79d4990
JB		 4002 return ironlake_check_srwm(dev, level,
4003 *fbc_wm, *display_wm, *cursor_wm,
4004 display, cursor);
4005}
4006
d210246a 4007static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4008{
4009 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4010 int fbc_wm, plane_wm, cursor_wm;
4011 unsigned int enabled;
b79d4990
JB		 4012
4013 enabled = 0;
4014 if (ironlake_compute_wm0(dev, 0,
4015 &ironlake_display_wm_info,
4016 ILK_LP0_PLANE_LATENCY,
4017 &ironlake_cursor_wm_info,
4018 ILK_LP0_CURSOR_LATENCY,
4019 &plane_wm, &cursor_wm)) {
4020 I915_WRITE(WM0_PIPEA_ILK,
4021 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4022 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4023 " plane %d, " "cursor: %d\n",
4024 plane_wm, cursor_wm);
d210246a 4025 enabled |= 1;
b79d4990
JB		 4026 }
4027
4028 if (ironlake_compute_wm0(dev, 1,
4029 &ironlake_display_wm_info,
4030 ILK_LP0_PLANE_LATENCY,
4031 &ironlake_cursor_wm_info,
4032 ILK_LP0_CURSOR_LATENCY,
4033 &plane_wm, &cursor_wm)) {
4034 I915_WRITE(WM0_PIPEB_ILK,
4035 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4036 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4037 " plane %d, cursor: %d\n",
4038 plane_wm, cursor_wm);
d210246a 4039 enabled |= 2;
b79d4990
JB		 4040 }
4041
4042 /*
4043 * Calculate and update the self-refresh watermark only when one
4044 * display plane is used.
4045 */
4046 I915_WRITE(WM3_LP_ILK, 0);
4047 I915_WRITE(WM2_LP_ILK, 0);
4048 I915_WRITE(WM1_LP_ILK, 0);
4049
d210246a 4050 if (!single_plane_enabled(enabled))
b79d4990 4051 return;
d210246a 4052 enabled = ffs(enabled) - 1;
b79d4990
JB		 4053
4054 /* WM1 */
d210246a
CW		 4055 if (!ironlake_compute_srwm(dev, 1, enabled,
4056 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4057 &ironlake_display_srwm_info,
4058 &ironlake_cursor_srwm_info,
4059 &fbc_wm, &plane_wm, &cursor_wm))
4060 return;
4061
4062 I915_WRITE(WM1_LP_ILK,
4063 WM1_LP_SR_EN |
4064 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4065 (fbc_wm << WM1_LP_FBC_SHIFT) |
4066 (plane_wm << WM1_LP_SR_SHIFT) |
4067 cursor_wm);
4068
4069 /* WM2 */
d210246a
CW		 4070 if (!ironlake_compute_srwm(dev, 2, enabled,
4071 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4072 &ironlake_display_srwm_info,
4073 &ironlake_cursor_srwm_info,
4074 &fbc_wm, &plane_wm, &cursor_wm))
4075 return;
4076
4077 I915_WRITE(WM2_LP_ILK,
4078 WM2_LP_EN |
4079 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4080 (fbc_wm << WM1_LP_FBC_SHIFT) |
4081 (plane_wm << WM1_LP_SR_SHIFT) |
4082 cursor_wm);
4083
4084 /*
4085 * WM3 is unsupported on ILK, probably because we don't have latency
4086 * data for that power state
4087 */
1398261a
YL		 4088}
4089
d210246a 4090static void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4091{
4092 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4093 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
d210246a
CW		 4094 int fbc_wm, plane_wm, cursor_wm;
4095 unsigned int enabled;
1398261a
YL		 4096
4097 enabled = 0;
4098 if (ironlake_compute_wm0(dev, 0,
4099 &sandybridge_display_wm_info, latency,
4100 &sandybridge_cursor_wm_info, latency,
4101 &plane_wm, &cursor_wm)) {
4102 I915_WRITE(WM0_PIPEA_ILK,
4103 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4104 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4105 " plane %d, " "cursor: %d\n",
4106 plane_wm, cursor_wm);
d210246a 4107 enabled |= 1;
1398261a
YL		 4108 }
4109
4110 if (ironlake_compute_wm0(dev, 1,
4111 &sandybridge_display_wm_info, latency,
4112 &sandybridge_cursor_wm_info, latency,
4113 &plane_wm, &cursor_wm)) {
4114 I915_WRITE(WM0_PIPEB_ILK,
4115 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4116 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4117 " plane %d, cursor: %d\n",
4118 plane_wm, cursor_wm);
d210246a 4119 enabled |= 2;
1398261a
YL		 4120 }
4121
4122 /*
4123 * Calculate and update the self-refresh watermark only when one
4124 * display plane is used.
4125 *
4126 * SNB support 3 levels of watermark.
4127 *
4128 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4129 * and disabled in the descending order
4130 *
4131 */
4132 I915_WRITE(WM3_LP_ILK, 0);
4133 I915_WRITE(WM2_LP_ILK, 0);
4134 I915_WRITE(WM1_LP_ILK, 0);
4135
d210246a 4136 if (!single_plane_enabled(enabled))
1398261a 4137 return;
d210246a 4138 enabled = ffs(enabled) - 1;
1398261a
YL		 4139
4140 /* WM1 */
d210246a
CW		 4141 if (!ironlake_compute_srwm(dev, 1, enabled,
4142 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4143 &sandybridge_display_srwm_info,
4144 &sandybridge_cursor_srwm_info,
4145 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4146 return;
4147
4148 I915_WRITE(WM1_LP_ILK,
4149 WM1_LP_SR_EN |
4150 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4151 (fbc_wm << WM1_LP_FBC_SHIFT) |
4152 (plane_wm << WM1_LP_SR_SHIFT) |
4153 cursor_wm);
4154
4155 /* WM2 */
d210246a
CW		 4156 if (!ironlake_compute_srwm(dev, 2, enabled,
4157 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4158 &sandybridge_display_srwm_info,
4159 &sandybridge_cursor_srwm_info,
4160 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4161 return;
4162
4163 I915_WRITE(WM2_LP_ILK,
4164 WM2_LP_EN |
4165 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4166 (fbc_wm << WM1_LP_FBC_SHIFT) |
4167 (plane_wm << WM1_LP_SR_SHIFT) |
4168 cursor_wm);
4169
4170 /* WM3 */
d210246a
CW		 4171 if (!ironlake_compute_srwm(dev, 3, enabled,
4172 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4173 &sandybridge_display_srwm_info,
4174 &sandybridge_cursor_srwm_info,
4175 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4176 return;
4177
4178 I915_WRITE(WM3_LP_ILK,
4179 WM3_LP_EN |
4180 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4181 (fbc_wm << WM1_LP_FBC_SHIFT) |
4182 (plane_wm << WM1_LP_SR_SHIFT) |
4183 cursor_wm);
4184}
4185
7662c8bd
SL		 4186/**
4187 * intel_update_watermarks - update FIFO watermark values based on current modes
4188 *
4189 * Calculate watermark values for the various WM regs based on current mode
4190 * and plane configuration.
4191 *
4192 * There are several cases to deal with here:
4193 * - normal (i.e. non-self-refresh)
4194 * - self-refresh (SR) mode
4195 * - lines are large relative to FIFO size (buffer can hold up to 2)
4196 * - lines are small relative to FIFO size (buffer can hold more than 2
4197 * lines), so need to account for TLB latency
4198 *
4199 * The normal calculation is:
4200 * watermark = dotclock * bytes per pixel * latency
4201 * where latency is platform & configuration dependent (we assume pessimal
4202 * values here).
4203 *
4204 * The SR calculation is:
4205 * watermark = (trunc(latency/line time)+1) * surface width *
4206 * bytes per pixel
4207 * where
4208 * line time = htotal / dotclock
fa143215 4209 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4210 * and latency is assumed to be high, as above.
4211 *
4212 * The final value programmed to the register should always be rounded up,
4213 * and include an extra 2 entries to account for clock crossings.
4214 *
4215 * We don't use the sprite, so we can ignore that. And on Crestline we have
4216 * to set the non-SR watermarks to 8.
5eddb70b 4217 */
7662c8bd
SL		 4218static void intel_update_watermarks(struct drm_device *dev)
4219{
e70236a8 4220 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4221
d210246a
CW		 4222 if (dev_priv->display.update_wm)
4223 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4224}
4225
a7615030
CW		 4226static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4227{
4228 return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4229}
4230
f564048e
EA		 4231static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4232 struct drm_display_mode *mode,
4233 struct drm_display_mode *adjusted_mode,
4234 int x, int y,
4235 struct drm_framebuffer *old_fb)
4236{
4237 struct drm_device *dev = crtc->dev;
4238 struct drm_i915_private *dev_priv = dev->dev_private;
4239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4240 int pipe = intel_crtc->pipe;
4241 int plane = intel_crtc->plane;
f564048e
EA		 4242 int refclk, num_connectors = 0;
4243 intel_clock_t clock, reduced_clock;
4244 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4245 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4246 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
f564048e
EA		 4247 struct drm_mode_config *mode_config = &dev->mode_config;
4248 struct intel_encoder *encoder;
4249 const intel_limit_t *limit;
4250 int ret;
fae14981 4251 u32 temp;
f564048e 4252 u32 lvds_sync = 0;
f564048e 4253
f564048e
EA		 4254 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4255 if (encoder->base.crtc != crtc)
4256 continue;
4257
4258 switch (encoder->type) {
4259 case INTEL_OUTPUT_LVDS:
4260 is_lvds = true;
4261 break;
4262 case INTEL_OUTPUT_SDVO:
4263 case INTEL_OUTPUT_HDMI:
4264 is_sdvo = true;
4265 if (encoder->needs_tv_clock)
4266 is_tv = true;
4267 break;
4268 case INTEL_OUTPUT_DVO:
4269 is_dvo = true;
4270 break;
4271 case INTEL_OUTPUT_TVOUT:
4272 is_tv = true;
4273 break;
4274 case INTEL_OUTPUT_ANALOG:
4275 is_crt = true;
4276 break;
4277 case INTEL_OUTPUT_DISPLAYPORT:
4278 is_dp = true;
4279 break;
f564048e
EA		 4280 }
4281
4282 num_connectors++;
4283 }
4284
4285 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4286 refclk = dev_priv->lvds_ssc_freq * 1000;
4287 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4288 refclk / 1000);
4289 } else if (!IS_GEN2(dev)) {
4290 refclk = 96000;
f564048e
EA		 4291 } else {
4292 refclk = 48000;
4293 }
4294
4295 /*
4296 * Returns a set of divisors for the desired target clock with the given
4297 * refclk, or FALSE. The returned values represent the clock equation:
4298 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4299 */
4300 limit = intel_limit(crtc, refclk);
4301 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4302 if (!ok) {
4303 DRM_ERROR("Couldn't find PLL settings for mode!\n");
f564048e
EA		 4304 return -EINVAL;
4305 }
4306
4307 /* Ensure that the cursor is valid for the new mode before changing... */
4308 intel_crtc_update_cursor(crtc, true);
4309
4310 if (is_lvds && dev_priv->lvds_downclock_avail) {
4311 has_reduced_clock = limit->find_pll(limit, crtc,
4312 dev_priv->lvds_downclock,
4313 refclk,
4314 &reduced_clock);
4315 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4316 /*
4317 * If the different P is found, it means that we can't
4318 * switch the display clock by using the FP0/FP1.
4319 * In such case we will disable the LVDS downclock
4320 * feature.
4321 */
4322 DRM_DEBUG_KMS("Different P is found for "
4323 "LVDS clock/downclock\n");
4324 has_reduced_clock = 0;
4325 }
4326 }
4327 /* SDVO TV has fixed PLL values depend on its clock range,
4328 this mirrors vbios setting. */
4329 if (is_sdvo && is_tv) {
4330 if (adjusted_mode->clock >= 100000
4331 && adjusted_mode->clock < 140500) {
4332 clock.p1 = 2;
4333 clock.p2 = 10;
4334 clock.n = 3;
4335 clock.m1 = 16;
4336 clock.m2 = 8;
4337 } else if (adjusted_mode->clock >= 140500
4338 && adjusted_mode->clock <= 200000) {
4339 clock.p1 = 1;
4340 clock.p2 = 10;
4341 clock.n = 6;
4342 clock.m1 = 12;
4343 clock.m2 = 8;
4344 }
4345 }
4346
f564048e
EA		 4347 if (IS_PINEVIEW(dev)) {
4348 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4349 if (has_reduced_clock)
4350 fp2 = (1 << reduced_clock.n) << 16 |
4351 reduced_clock.m1 << 8 | reduced_clock.m2;
4352 } else {
4353 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4354 if (has_reduced_clock)
4355 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4356 reduced_clock.m2;
4357 }
4358
929c77fb 4359 dpll = DPLL_VGA_MODE_DIS;
f564048e
EA		 4360
4361 if (!IS_GEN2(dev)) {
4362 if (is_lvds)
4363 dpll |= DPLLB_MODE_LVDS;
4364 else
4365 dpll |= DPLLB_MODE_DAC_SERIAL;
4366 if (is_sdvo) {
4367 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4368 if (pixel_multiplier > 1) {
4369 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4370 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
f564048e
EA		 4371 }
4372 dpll |= DPLL_DVO_HIGH_SPEED;
4373 }
929c77fb 4374 if (is_dp)
f564048e
EA		 4375 dpll |= DPLL_DVO_HIGH_SPEED;
4376
4377 /* compute bitmask from p1 value */
4378 if (IS_PINEVIEW(dev))
4379 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4380 else {
4381 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
f564048e
EA		 4382 if (IS_G4X(dev) && has_reduced_clock)
4383 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4384 }
4385 switch (clock.p2) {
4386 case 5:
4387 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4388 break;
4389 case 7:
4390 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4391 break;
4392 case 10:
4393 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4394 break;
4395 case 14:
4396 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4397 break;
4398 }
929c77fb 4399 if (INTEL_INFO(dev)->gen >= 4)
f564048e
EA		 4400 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4401 } else {
4402 if (is_lvds) {
4403 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4404 } else {
4405 if (clock.p1 == 2)
4406 dpll |= PLL_P1_DIVIDE_BY_TWO;
4407 else
4408 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4409 if (clock.p2 == 4)
4410 dpll |= PLL_P2_DIVIDE_BY_4;
4411 }
4412 }
4413
4414 if (is_sdvo && is_tv)
4415 dpll |= PLL_REF_INPUT_TVCLKINBC;
4416 else if (is_tv)
4417 /* XXX: just matching BIOS for now */
4418 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4419 dpll |= 3;
4420 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4421 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4422 else
4423 dpll |= PLL_REF_INPUT_DREFCLK;
4424
4425 /* setup pipeconf */
4426 pipeconf = I915_READ(PIPECONF(pipe));
4427
4428 /* Set up the display plane register */
4429 dspcntr = DISPPLANE_GAMMA_ENABLE;
4430
4431 /* Ironlake's plane is forced to pipe, bit 24 is to
4432 enable color space conversion */
929c77fb
EA		 4433 if (pipe == 0)
4434 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4435 else
4436 dspcntr |= DISPPLANE_SEL_PIPE_B;
f564048e
EA		 4437
4438 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4439 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4440 * core speed.
4441 *
4442 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4443 * pipe == 0 check?
4444 */
4445 if (mode->clock >
4446 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4447 pipeconf |= PIPECONF_DOUBLE_WIDE;
4448 else
4449 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4450 }
4451
929c77fb 4452 dpll |= DPLL_VCO_ENABLE;
f564048e
EA		 4453
4454 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4455 drm_mode_debug_printmodeline(mode);
4456
fae14981
EA		 4457 I915_WRITE(FP0(pipe), fp);
4458 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
f564048e 4459
fae14981 4460 POSTING_READ(DPLL(pipe));
c713bb08 4461 udelay(150);
f564048e 4462
f564048e
EA		 4463 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4464 * This is an exception to the general rule that mode_set doesn't turn
4465 * things on.
4466 */
4467 if (is_lvds) {
fae14981 4468 temp = I915_READ(LVDS);
f564048e
EA		 4469 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4470 if (pipe == 1) {
929c77fb 4471 temp |= LVDS_PIPEB_SELECT;
f564048e 4472 } else {
929c77fb 4473 temp &= ~LVDS_PIPEB_SELECT;
f564048e
EA		 4474 }
4475 /* set the corresponsding LVDS_BORDER bit */
4476 temp |= dev_priv->lvds_border_bits;
4477 /* Set the B0-B3 data pairs corresponding to whether we're going to
4478 * set the DPLLs for dual-channel mode or not.
4479 */
4480 if (clock.p2 == 7)
4481 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4482 else
4483 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4484
4485 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4486 * appropriately here, but we need to look more thoroughly into how
4487 * panels behave in the two modes.
4488 */
929c77fb
EA		 4489 /* set the dithering flag on LVDS as needed */
4490 if (INTEL_INFO(dev)->gen >= 4) {
f564048e
EA		 4491 if (dev_priv->lvds_dither)
4492 temp |= LVDS_ENABLE_DITHER;
4493 else
4494 temp &= ~LVDS_ENABLE_DITHER;
4495 }
4496 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4497 lvds_sync |= LVDS_HSYNC_POLARITY;
4498 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4499 lvds_sync |= LVDS_VSYNC_POLARITY;
4500 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4501 != lvds_sync) {
4502 char flags[2] = "-+";
4503 DRM_INFO("Changing LVDS panel from "
4504 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4505 flags[!(temp & LVDS_HSYNC_POLARITY)],
4506 flags[!(temp & LVDS_VSYNC_POLARITY)],
4507 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4508 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4509 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4510 temp |= lvds_sync;
4511 }
fae14981 4512 I915_WRITE(LVDS, temp);
f564048e
EA		 4513 }
4514
929c77fb 4515 if (is_dp) {
f564048e 4516 intel_dp_set_m_n(crtc, mode, adjusted_mode);
f564048e
EA		 4517 }
4518
fae14981 4519 I915_WRITE(DPLL(pipe), dpll);
f564048e 4520
c713bb08 4521 /* Wait for the clocks to stabilize. */
fae14981 4522 POSTING_READ(DPLL(pipe));
c713bb08 4523 udelay(150);
f564048e 4524
c713bb08
EA		 4525 if (INTEL_INFO(dev)->gen >= 4) {
4526 temp = 0;
4527 if (is_sdvo) {
4528 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4529 if (temp > 1)
4530 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4531 else
4532 temp = 0;
f564048e 4533 }
c713bb08
EA		 4534 I915_WRITE(DPLL_MD(pipe), temp);
4535 } else {
4536 /* The pixel multiplier can only be updated once the
4537 * DPLL is enabled and the clocks are stable.
4538 *
4539 * So write it again.
4540 */
fae14981 4541 I915_WRITE(DPLL(pipe), dpll);
f564048e
EA		 4542 }
4543
4544 intel_crtc->lowfreq_avail = false;
4545 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 4546 I915_WRITE(FP1(pipe), fp2);
f564048e
EA		 4547 intel_crtc->lowfreq_avail = true;
4548 if (HAS_PIPE_CXSR(dev)) {
4549 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4550 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4551 }
4552 } else {
fae14981 4553 I915_WRITE(FP1(pipe), fp);
f564048e
EA		 4554 if (HAS_PIPE_CXSR(dev)) {
4555 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4556 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4557 }
4558 }
4559
4560 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4561 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4562 /* the chip adds 2 halflines automatically */
4563 adjusted_mode->crtc_vdisplay -= 1;
4564 adjusted_mode->crtc_vtotal -= 1;
4565 adjusted_mode->crtc_vblank_start -= 1;
4566 adjusted_mode->crtc_vblank_end -= 1;
4567 adjusted_mode->crtc_vsync_end -= 1;
4568 adjusted_mode->crtc_vsync_start -= 1;
4569 } else
4570 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4571
4572 I915_WRITE(HTOTAL(pipe),
4573 (adjusted_mode->crtc_hdisplay - 1) |
4574 ((adjusted_mode->crtc_htotal - 1) << 16));
4575 I915_WRITE(HBLANK(pipe),
4576 (adjusted_mode->crtc_hblank_start - 1) |
4577 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4578 I915_WRITE(HSYNC(pipe),
4579 (adjusted_mode->crtc_hsync_start - 1) |
4580 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4581
4582 I915_WRITE(VTOTAL(pipe),
4583 (adjusted_mode->crtc_vdisplay - 1) |
4584 ((adjusted_mode->crtc_vtotal - 1) << 16));
4585 I915_WRITE(VBLANK(pipe),
4586 (adjusted_mode->crtc_vblank_start - 1) |
4587 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4588 I915_WRITE(VSYNC(pipe),
4589 (adjusted_mode->crtc_vsync_start - 1) |
4590 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4591
4592 /* pipesrc and dspsize control the size that is scaled from,
4593 * which should always be the user's requested size.
4594 */
929c77fb
EA		 4595 I915_WRITE(DSPSIZE(plane),
4596 ((mode->vdisplay - 1) << 16) |
4597 (mode->hdisplay - 1));
4598 I915_WRITE(DSPPOS(plane), 0);
f564048e
EA		 4599 I915_WRITE(PIPESRC(pipe),
4600 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4601
f564048e
EA		 4602 I915_WRITE(PIPECONF(pipe), pipeconf);
4603 POSTING_READ(PIPECONF(pipe));
929c77fb 4604 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4605
4606 intel_wait_for_vblank(dev, pipe);
4607
f564048e
EA		 4608 I915_WRITE(DSPCNTR(plane), dspcntr);
4609 POSTING_READ(DSPCNTR(plane));
4610
4611 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4612
4613 intel_update_watermarks(dev);
4614
f564048e
EA		 4615 return ret;
4616}
4617
4618static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4619 struct drm_display_mode *mode,
4620 struct drm_display_mode *adjusted_mode,
4621 int x, int y,
4622 struct drm_framebuffer *old_fb)
79e53945
JB		 4623{
4624 struct drm_device *dev = crtc->dev;
4625 struct drm_i915_private *dev_priv = dev->dev_private;
4626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4627 int pipe = intel_crtc->pipe;
80824003 4628 int plane = intel_crtc->plane;
c751ce4f 4629 int refclk, num_connectors = 0;
652c393a 4630 intel_clock_t clock, reduced_clock;
5eddb70b 4631 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4632 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4633 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 4634 struct intel_encoder *has_edp_encoder = NULL;
79e53945 4635 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4636 struct intel_encoder *encoder;
d4906093 4637 const intel_limit_t *limit;
5c3b82e2 4638 int ret;
2c07245f 4639 struct fdi_m_n m_n = {0};
fae14981 4640 u32 temp;
aa9b500d 4641 u32 lvds_sync = 0;
8febb297 4642 int target_clock, pixel_multiplier, lane, link_bw, bpp, factor;
79e53945 4643
5eddb70b
CW		 4644 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4645 if (encoder->base.crtc != crtc)
79e53945
JB		 4646 continue;
4647
5eddb70b 4648 switch (encoder->type) {
79e53945
JB		 4649 case INTEL_OUTPUT_LVDS:
4650 is_lvds = true;
4651 break;
4652 case INTEL_OUTPUT_SDVO:
7d57382e 4653 case INTEL_OUTPUT_HDMI:
79e53945 4654 is_sdvo = true;
5eddb70b 4655 if (encoder->needs_tv_clock)
e2f0ba97 4656 is_tv = true;
79e53945 4657 break;
79e53945
JB		 4658 case INTEL_OUTPUT_TVOUT:
4659 is_tv = true;
4660 break;
4661 case INTEL_OUTPUT_ANALOG:
4662 is_crt = true;
4663 break;
a4fc5ed6
KP		 4664 case INTEL_OUTPUT_DISPLAYPORT:
4665 is_dp = true;
4666 break;
32f9d658 4667 case INTEL_OUTPUT_EDP:
5eddb70b 4668 has_edp_encoder = encoder;
32f9d658 4669 break;
79e53945 4670 }
43565a06 4671
c751ce4f 4672 num_connectors++;
79e53945
JB		 4673 }
4674
a7615030 4675 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4676 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4677 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4678 refclk / 1000);
a07d6787 4679 } else {
79e53945 4680 refclk = 96000;
8febb297
EA		 4681 if (!has_edp_encoder ||
4682 intel_encoder_is_pch_edp(&has_edp_encoder->base))
2c07245f 4683 refclk = 120000; /* 120Mhz refclk */
79e53945
JB		 4684 }
4685
d4906093
ML		 4686 /*
4687 * Returns a set of divisors for the desired target clock with the given
4688 * refclk, or FALSE. The returned values represent the clock equation:
4689 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4690 */
1b894b59 4691 limit = intel_limit(crtc, refclk);
d4906093 4692 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4693 if (!ok) {
4694 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4695 return -EINVAL;
79e53945
JB		 4696 }
4697
cda4b7d3 4698 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4699 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4700
ddc9003c
ZY		 4701 if (is_lvds && dev_priv->lvds_downclock_avail) {
4702 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4703 dev_priv->lvds_downclock,
4704 refclk,
4705 &reduced_clock);
18f9ed12
ZY		 4706 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4707 /*
4708 * If the different P is found, it means that we can't
4709 * switch the display clock by using the FP0/FP1.
4710 * In such case we will disable the LVDS downclock
4711 * feature.
4712 */
4713 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4714 "LVDS clock/downclock\n");
18f9ed12
ZY		 4715 has_reduced_clock = 0;
4716 }
652c393a 4717 }
7026d4ac
ZW		 4718 /* SDVO TV has fixed PLL values depend on its clock range,
4719 this mirrors vbios setting. */
4720 if (is_sdvo && is_tv) {
4721 if (adjusted_mode->clock >= 100000
5eddb70b 4722 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4723 clock.p1 = 2;
4724 clock.p2 = 10;
4725 clock.n = 3;
4726 clock.m1 = 16;
4727 clock.m2 = 8;
4728 } else if (adjusted_mode->clock >= 140500
5eddb70b 4729 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4730 clock.p1 = 1;
4731 clock.p2 = 10;
4732 clock.n = 6;
4733 clock.m1 = 12;
4734 clock.m2 = 8;
4735 }
4736 }
4737
2c07245f 4738 /* FDI link */
8febb297
EA		 4739 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4740 lane = 0;
4741 /* CPU eDP doesn't require FDI link, so just set DP M/N
4742 according to current link config */
4743 if (has_edp_encoder &&
4744 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4745 target_clock = mode->clock;
4746 intel_edp_link_config(has_edp_encoder,
4747 &lane, &link_bw);
4748 } else {
4749 /* [e]DP over FDI requires target mode clock
4750 instead of link clock */
4751 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 4752 target_clock = mode->clock;
8febb297
EA		 4753 else
4754 target_clock = adjusted_mode->clock;
4755
4756 /* FDI is a binary signal running at ~2.7GHz, encoding
4757 * each output octet as 10 bits. The actual frequency
4758 * is stored as a divider into a 100MHz clock, and the
4759 * mode pixel clock is stored in units of 1KHz.
4760 * Hence the bw of each lane in terms of the mode signal
4761 * is:
4762 */
4763 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4764 }
58a27471 4765
8febb297
EA		 4766 /* determine panel color depth */
4767 temp = I915_READ(PIPECONF(pipe));
4768 temp &= ~PIPE_BPC_MASK;
4769 if (is_lvds) {
4770 /* the BPC will be 6 if it is 18-bit LVDS panel */
4771 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4772 temp |= PIPE_8BPC;
4773 else
4774 temp |= PIPE_6BPC;
4775 } else if (has_edp_encoder) {
4776 switch (dev_priv->edp.bpp/3) {
4777 case 8:
e5a95eb7 4778 temp |= PIPE_8BPC;
58a27471 4779 break;
8febb297
EA		 4780 case 10:
4781 temp |= PIPE_10BPC;
58a27471 4782 break;
8febb297
EA		 4783 case 6:
4784 temp |= PIPE_6BPC;
58a27471 4785 break;
8febb297
EA		 4786 case 12:
4787 temp |= PIPE_12BPC;
58a27471 4788 break;
77ffb597 4789 }
8febb297
EA		 4790 } else
4791 temp |= PIPE_8BPC;
4792 I915_WRITE(PIPECONF(pipe), temp);
77ffb597 4793
8febb297
EA		 4794 switch (temp & PIPE_BPC_MASK) {
4795 case PIPE_8BPC:
4796 bpp = 24;
4797 break;
4798 case PIPE_10BPC:
4799 bpp = 30;
4800 break;
4801 case PIPE_6BPC:
4802 bpp = 18;
4803 break;
4804 case PIPE_12BPC:
4805 bpp = 36;
4806 break;
4807 default:
4808 DRM_ERROR("unknown pipe bpc value\n");
4809 bpp = 24;
4810 }
77ffb597 4811
8febb297
EA		 4812 if (!lane) {
4813 /*
4814 * Account for spread spectrum to avoid
4815 * oversubscribing the link. Max center spread
4816 * is 2.5%; use 5% for safety's sake.
4817 */
4818 u32 bps = target_clock * bpp * 21 / 20;
4819 lane = bps / (link_bw * 8) + 1;
5eb08b69 4820 }
2c07245f 4821
8febb297
EA		 4822 intel_crtc->fdi_lanes = lane;
4823
4824 if (pixel_multiplier > 1)
4825 link_bw *= pixel_multiplier;
4826 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4827
c038e51e
ZW		 4828 /* Ironlake: try to setup display ref clock before DPLL
4829 * enabling. This is only under driver's control after
4830 * PCH B stepping, previous chipset stepping should be
4831 * ignoring this setting.
4832 */
8febb297
EA		 4833 temp = I915_READ(PCH_DREF_CONTROL);
4834 /* Always enable nonspread source */
4835 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4836 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4837 temp &= ~DREF_SSC_SOURCE_MASK;
4838 temp |= DREF_SSC_SOURCE_ENABLE;
4839 I915_WRITE(PCH_DREF_CONTROL, temp);
4840
4841 POSTING_READ(PCH_DREF_CONTROL);
4842 udelay(200);
fc9a2228 4843
8febb297
EA		 4844 if (has_edp_encoder) {
4845 if (intel_panel_use_ssc(dev_priv)) {
4846 temp |= DREF_SSC1_ENABLE;
fc9a2228 4847 I915_WRITE(PCH_DREF_CONTROL, temp);
8febb297 4848
fc9a2228
CW		 4849 POSTING_READ(PCH_DREF_CONTROL);
4850 udelay(200);
4851 }
8febb297
EA		 4852 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4853
4854 /* Enable CPU source on CPU attached eDP */
4855 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4856 if (intel_panel_use_ssc(dev_priv))
4857 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4858 else
4859 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4860 } else {
4861 /* Enable SSC on PCH eDP if needed */
4862 if (intel_panel_use_ssc(dev_priv)) {
4863 DRM_ERROR("enabling SSC on PCH\n");
4864 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4865 }
4866 }
4867 I915_WRITE(PCH_DREF_CONTROL, temp);
4868 POSTING_READ(PCH_DREF_CONTROL);
4869 udelay(200);
fc9a2228 4870 }
c038e51e 4871
a07d6787
EA		 4872 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4873 if (has_reduced_clock)
4874 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4875 reduced_clock.m2;
79e53945 4876
c1858123 4877 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4878 factor = 21;
4879 if (is_lvds) {
4880 if ((intel_panel_use_ssc(dev_priv) &&
4881 dev_priv->lvds_ssc_freq == 100) ||
4882 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4883 factor = 25;
4884 } else if (is_sdvo && is_tv)
4885 factor = 20;
c1858123 4886
8febb297
EA		 4887 if (clock.m1 < factor * clock.n)
4888 fp |= FP_CB_TUNE;
c1858123 4889
5eddb70b 4890 dpll = 0;
2c07245f 4891
a07d6787
EA		 4892 if (is_lvds)
4893 dpll |= DPLLB_MODE_LVDS;
4894 else
4895 dpll |= DPLLB_MODE_DAC_SERIAL;
4896 if (is_sdvo) {
4897 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4898 if (pixel_multiplier > 1) {
4899 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4900 }
a07d6787
EA		 4901 dpll |= DPLL_DVO_HIGH_SPEED;
4902 }
4903 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4904 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4905
a07d6787
EA		 4906 /* compute bitmask from p1 value */
4907 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4908 /* also FPA1 */
4909 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4910
4911 switch (clock.p2) {
4912 case 5:
4913 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4914 break;
4915 case 7:
4916 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4917 break;
4918 case 10:
4919 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4920 break;
4921 case 14:
4922 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4923 break;
79e53945
JB		 4924 }
4925
43565a06
KH		 4926 if (is_sdvo && is_tv)
4927 dpll |= PLL_REF_INPUT_TVCLKINBC;
4928 else if (is_tv)
79e53945 4929 /* XXX: just matching BIOS for now */
43565a06 4930 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4931 dpll |= 3;
a7615030 4932 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4933 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4934 else
4935 dpll |= PLL_REF_INPUT_DREFCLK;
4936
4937 /* setup pipeconf */
5eddb70b 4938 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4939
4940 /* Set up the display plane register */
4941 dspcntr = DISPPLANE_GAMMA_ENABLE;
4942
28c97730 4943 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4944 drm_mode_debug_printmodeline(mode);
4945
5c5313c8
JB		 4946 /* PCH eDP needs FDI, but CPU eDP does not */
4947 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981
EA		 4948 I915_WRITE(PCH_FP0(pipe), fp);
4949 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 4950
fae14981 4951 POSTING_READ(PCH_DPLL(pipe));
79e53945
JB		 4952 udelay(150);
4953 }
4954
8db9d77b
ZW		 4955 /* enable transcoder DPLL */
4956 if (HAS_PCH_CPT(dev)) {
4957 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 4958 switch (pipe) {
4959 case 0:
5eddb70b 4960 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
9db4a9c7
JB		 4961 break;
4962 case 1:
5eddb70b 4963 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
9db4a9c7
JB		 4964 break;
4965 case 2:
4966 /* FIXME: manage transcoder PLLs? */
4967 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
4968 break;
4969 default:
4970 BUG();
4971 }
8db9d77b 4972 I915_WRITE(PCH_DPLL_SEL, temp);
5eddb70b
CW		 4973
4974 POSTING_READ(PCH_DPLL_SEL);
8db9d77b
ZW		 4975 udelay(150);
4976 }
4977
79e53945
JB		 4978 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4979 * This is an exception to the general rule that mode_set doesn't turn
4980 * things on.
4981 */
4982 if (is_lvds) {
fae14981 4983 temp = I915_READ(PCH_LVDS);
5eddb70b 4984 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3
ZW		 4985 if (pipe == 1) {
4986 if (HAS_PCH_CPT(dev))
5eddb70b 4987 temp |= PORT_TRANS_B_SEL_CPT;
b3b095b3 4988 else
5eddb70b 4989 temp |= LVDS_PIPEB_SELECT;
b3b095b3
ZW		 4990 } else {
4991 if (HAS_PCH_CPT(dev))
5eddb70b 4992 temp &= ~PORT_TRANS_SEL_MASK;
b3b095b3 4993 else
5eddb70b 4994 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 4995 }
a3e17eb8 4996 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4997 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4998 /* Set the B0-B3 data pairs corresponding to whether we're going to
4999 * set the DPLLs for dual-channel mode or not.
5000 */
5001 if (clock.p2 == 7)
5eddb70b 5002 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5003 else
5eddb70b 5004 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5005
5006 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5007 * appropriately here, but we need to look more thoroughly into how
5008 * panels behave in the two modes.
5009 */
aa9b500d
BF		 5010 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5011 lvds_sync |= LVDS_HSYNC_POLARITY;
5012 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5013 lvds_sync |= LVDS_VSYNC_POLARITY;
5014 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5015 != lvds_sync) {
5016 char flags[2] = "-+";
5017 DRM_INFO("Changing LVDS panel from "
5018 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5019 flags[!(temp & LVDS_HSYNC_POLARITY)],
5020 flags[!(temp & LVDS_VSYNC_POLARITY)],
5021 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5022 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5023 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5024 temp |= lvds_sync;
5025 }
fae14981 5026 I915_WRITE(PCH_LVDS, temp);
79e53945 5027 }
434ed097
JB		 5028
5029 /* set the dithering flag and clear for anything other than a panel. */
8febb297
EA		 5030 pipeconf &= ~PIPECONF_DITHER_EN;
5031 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5032 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5033 pipeconf |= PIPECONF_DITHER_EN;
5034 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
434ed097
JB		 5035 }
5036
5c5313c8 5037 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5038 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5039 } else {
8db9d77b 5040 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5041 I915_WRITE(TRANSDATA_M1(pipe), 0);
5042 I915_WRITE(TRANSDATA_N1(pipe), 0);
5043 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5044 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5045 }
79e53945 5046
8febb297
EA		 5047 if (!has_edp_encoder ||
5048 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981 5049 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5050
32f9d658 5051 /* Wait for the clocks to stabilize. */
fae14981 5052 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5053 udelay(150);
5054
8febb297
EA		 5055 /* The pixel multiplier can only be updated once the
5056 * DPLL is enabled and the clocks are stable.
5057 *
5058 * So write it again.
5059 */
fae14981 5060 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5061 }
79e53945 5062
5eddb70b 5063 intel_crtc->lowfreq_avail = false;
652c393a 5064 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 5065 I915_WRITE(PCH_FP1(pipe), fp2);
652c393a
JB		 5066 intel_crtc->lowfreq_avail = true;
5067 if (HAS_PIPE_CXSR(dev)) {
28c97730 5068 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 5069 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5070 }
5071 } else {
fae14981 5072 I915_WRITE(PCH_FP1(pipe), fp);
652c393a 5073 if (HAS_PIPE_CXSR(dev)) {
28c97730 5074 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5075 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5076 }
5077 }
5078
734b4157
KH		 5079 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5080 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5081 /* the chip adds 2 halflines automatically */
5082 adjusted_mode->crtc_vdisplay -= 1;
5083 adjusted_mode->crtc_vtotal -= 1;
5084 adjusted_mode->crtc_vblank_start -= 1;
5085 adjusted_mode->crtc_vblank_end -= 1;
5086 adjusted_mode->crtc_vsync_end -= 1;
5087 adjusted_mode->crtc_vsync_start -= 1;
5088 } else
5089 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5090
5eddb70b
CW		 5091 I915_WRITE(HTOTAL(pipe),
5092 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5093 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5094 I915_WRITE(HBLANK(pipe),
5095 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5096 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5097 I915_WRITE(HSYNC(pipe),
5098 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5099 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5100
5101 I915_WRITE(VTOTAL(pipe),
5102 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5103 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5104 I915_WRITE(VBLANK(pipe),
5105 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5106 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5107 I915_WRITE(VSYNC(pipe),
5108 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5109 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5110
8febb297
EA		 5111 /* pipesrc controls the size that is scaled from, which should
5112 * always be the user's requested size.
79e53945 5113 */
5eddb70b
CW		 5114 I915_WRITE(PIPESRC(pipe),
5115 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5116
8febb297
EA		 5117 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5118 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5119 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5120 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5121
8febb297
EA		 5122 if (has_edp_encoder &&
5123 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5124 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 5125 }
5126
5eddb70b
CW		 5127 I915_WRITE(PIPECONF(pipe), pipeconf);
5128 POSTING_READ(PIPECONF(pipe));
79e53945 5129
9d0498a2 5130 intel_wait_for_vblank(dev, pipe);
79e53945 5131
f00a3ddf 5132 if (IS_GEN5(dev)) {
553bd149
ZW		 5133 /* enable address swizzle for tiling buffer */
5134 temp = I915_READ(DISP_ARB_CTL);
5135 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5136 }
5137
5eddb70b 5138 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 5139 POSTING_READ(DSPCNTR(plane));
79e53945 5140
5c3b82e2 5141 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 5142
5143 intel_update_watermarks(dev);
5144
1f803ee5 5145 return ret;
79e53945
JB		 5146}
5147
f564048e
EA		 5148static int intel_crtc_mode_set(struct drm_crtc *crtc,
5149 struct drm_display_mode *mode,
5150 struct drm_display_mode *adjusted_mode,
5151 int x, int y,
5152 struct drm_framebuffer *old_fb)
5153{
5154 struct drm_device *dev = crtc->dev;
5155 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5157 int pipe = intel_crtc->pipe;
f564048e
EA		 5158 int ret;
5159
0b701d27
EA		 5160 drm_vblank_pre_modeset(dev, pipe);
5161
f564048e
EA		 5162 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5163 x, y, old_fb);
5164
0b701d27
EA		 5165 drm_vblank_post_modeset(dev, pipe);
5166
f564048e
EA		 5167 return ret;
5168}
5169
79e53945
JB		 5170/** Loads the palette/gamma unit for the CRTC with the prepared values */
5171void intel_crtc_load_lut(struct drm_crtc *crtc)
5172{
5173 struct drm_device *dev = crtc->dev;
5174 struct drm_i915_private *dev_priv = dev->dev_private;
5175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5176 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5177 int i;
5178
5179 /* The clocks have to be on to load the palette. */
5180 if (!crtc->enabled)
5181 return;
5182
f2b115e6 5183 /* use legacy palette for Ironlake */
bad720ff 5184 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5185 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5186
79e53945
JB		 5187 for (i = 0; i < 256; i++) {
5188 I915_WRITE(palreg + 4 * i,
5189 (intel_crtc->lut_r[i] << 16) |
5190 (intel_crtc->lut_g[i] << 8) |
5191 intel_crtc->lut_b[i]);
5192 }
5193}
5194
560b85bb
CW		 5195static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5196{
5197 struct drm_device *dev = crtc->dev;
5198 struct drm_i915_private *dev_priv = dev->dev_private;
5199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5200 bool visible = base != 0;
5201 u32 cntl;
5202
5203 if (intel_crtc->cursor_visible == visible)
5204 return;
5205
9db4a9c7 5206 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5207 if (visible) {
5208 /* On these chipsets we can only modify the base whilst
5209 * the cursor is disabled.
5210 */
9db4a9c7 5211 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5212
5213 cntl &= ~(CURSOR_FORMAT_MASK);
5214 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5215 cntl |= CURSOR_ENABLE |
5216 CURSOR_GAMMA_ENABLE |
5217 CURSOR_FORMAT_ARGB;
5218 } else
5219 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5220 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5221
5222 intel_crtc->cursor_visible = visible;
5223}
5224
5225static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5226{
5227 struct drm_device *dev = crtc->dev;
5228 struct drm_i915_private *dev_priv = dev->dev_private;
5229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5230 int pipe = intel_crtc->pipe;
5231 bool visible = base != 0;
5232
5233 if (intel_crtc->cursor_visible != visible) {
548f245b 5234 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5235 if (base) {
5236 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5237 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5238 cntl |= pipe << 28; /* Connect to correct pipe */
5239 } else {
5240 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5241 cntl |= CURSOR_MODE_DISABLE;
5242 }
9db4a9c7 5243 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5244
5245 intel_crtc->cursor_visible = visible;
5246 }
5247 /* and commit changes on next vblank */
9db4a9c7 5248 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5249}
5250
cda4b7d3 5251/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5252static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5253 bool on)
cda4b7d3
CW		 5254{
5255 struct drm_device *dev = crtc->dev;
5256 struct drm_i915_private *dev_priv = dev->dev_private;
5257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5258 int pipe = intel_crtc->pipe;
5259 int x = intel_crtc->cursor_x;
5260 int y = intel_crtc->cursor_y;
560b85bb 5261 u32 base, pos;
cda4b7d3
CW		 5262 bool visible;
5263
5264 pos = 0;
5265
6b383a7f 5266 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5267 base = intel_crtc->cursor_addr;
5268 if (x > (int) crtc->fb->width)
5269 base = 0;
5270
5271 if (y > (int) crtc->fb->height)
5272 base = 0;
5273 } else
5274 base = 0;
5275
5276 if (x < 0) {
5277 if (x + intel_crtc->cursor_width < 0)
5278 base = 0;
5279
5280 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5281 x = -x;
5282 }
5283 pos |= x << CURSOR_X_SHIFT;
5284
5285 if (y < 0) {
5286 if (y + intel_crtc->cursor_height < 0)
5287 base = 0;
5288
5289 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5290 y = -y;
5291 }
5292 pos |= y << CURSOR_Y_SHIFT;
5293
5294 visible = base != 0;
560b85bb 5295 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5296 return;
5297
9db4a9c7 5298 I915_WRITE(CURPOS(pipe), pos);
560b85bb
CW		 5299 if (IS_845G(dev) || IS_I865G(dev))
5300 i845_update_cursor(crtc, base);
5301 else
5302 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 5303
5304 if (visible)
5305 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5306}
5307
79e53945 5308static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5309 struct drm_file *file,
79e53945
JB		 5310 uint32_t handle,
5311 uint32_t width, uint32_t height)
5312{
5313 struct drm_device *dev = crtc->dev;
5314 struct drm_i915_private *dev_priv = dev->dev_private;
5315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5316 struct drm_i915_gem_object *obj;
cda4b7d3 5317 uint32_t addr;
3f8bc370 5318 int ret;
79e53945 5319
28c97730 5320 DRM_DEBUG_KMS("\n");
79e53945
JB		 5321
5322 /* if we want to turn off the cursor ignore width and height */
5323 if (!handle) {
28c97730 5324 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5325 addr = 0;
05394f39 5326 obj = NULL;
5004417d 5327 mutex_lock(&dev->struct_mutex);
3f8bc370 5328 goto finish;
79e53945
JB		 5329 }
5330
5331 /* Currently we only support 64x64 cursors */
5332 if (width != 64 || height != 64) {
5333 DRM_ERROR("we currently only support 64x64 cursors\n");
5334 return -EINVAL;
5335 }
5336
05394f39 5337 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5338 if (&obj->base == NULL)
79e53945
JB		 5339 return -ENOENT;
5340
05394f39 5341 if (obj->base.size < width * height * 4) {
79e53945 5342 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5343 ret = -ENOMEM;
5344 goto fail;
79e53945
JB		 5345 }
5346
71acb5eb 5347 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5348 mutex_lock(&dev->struct_mutex);
b295d1b6 5349 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5350 if (obj->tiling_mode) {
5351 DRM_ERROR("cursor cannot be tiled\n");
5352 ret = -EINVAL;
5353 goto fail_locked;
5354 }
5355
05394f39 5356 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
71acb5eb
DA		 5357 if (ret) {
5358 DRM_ERROR("failed to pin cursor bo\n");
7f9872e0 5359 goto fail_locked;
71acb5eb 5360 }
e7b526bb 5361
05394f39 5362 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
e7b526bb
CW		 5363 if (ret) {
5364 DRM_ERROR("failed to move cursor bo into the GTT\n");
5365 goto fail_unpin;
5366 }
5367
d9e86c0e
CW		 5368 ret = i915_gem_object_put_fence(obj);
5369 if (ret) {
5370 DRM_ERROR("failed to move cursor bo into the GTT\n");
5371 goto fail_unpin;
5372 }
5373
05394f39 5374 addr = obj->gtt_offset;
71acb5eb 5375 } else {
6eeefaf3 5376 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5377 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5378 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5379 align);
71acb5eb
DA		 5380 if (ret) {
5381 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5382 goto fail_locked;
71acb5eb 5383 }
05394f39 5384 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5385 }
5386
a6c45cf0 5387 if (IS_GEN2(dev))
14b60391
JB		 5388 I915_WRITE(CURSIZE, (height << 12) | width);
5389
3f8bc370 5390 finish:
3f8bc370 5391 if (intel_crtc->cursor_bo) {
b295d1b6 5392 if (dev_priv->info->cursor_needs_physical) {
05394f39 5393 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5394 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5395 } else
5396 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5397 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5398 }
80824003 5399
7f9872e0 5400 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5401
5402 intel_crtc->cursor_addr = addr;
05394f39 5403 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5404 intel_crtc->cursor_width = width;
5405 intel_crtc->cursor_height = height;
5406
6b383a7f 5407 intel_crtc_update_cursor(crtc, true);
3f8bc370 5408
79e53945 5409 return 0;
e7b526bb 5410fail_unpin:
05394f39 5411 i915_gem_object_unpin(obj);
7f9872e0 5412fail_locked:
34b8686e 5413 mutex_unlock(&dev->struct_mutex);
bc9025bd 5414fail:
05394f39 5415 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5416 return ret;
79e53945
JB		 5417}
5418
5419static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5420{
79e53945 5421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5422
cda4b7d3
CW		 5423 intel_crtc->cursor_x = x;
5424 intel_crtc->cursor_y = y;
652c393a 5425
6b383a7f 5426 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5427
5428 return 0;
5429}
5430
5431/** Sets the color ramps on behalf of RandR */
5432void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5433 u16 blue, int regno)
5434{
5435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5436
5437 intel_crtc->lut_r[regno] = red >> 8;
5438 intel_crtc->lut_g[regno] = green >> 8;
5439 intel_crtc->lut_b[regno] = blue >> 8;
5440}
5441
b8c00ac5
DA		 5442void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5443 u16 *blue, int regno)
5444{
5445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5446
5447 *red = intel_crtc->lut_r[regno] << 8;
5448 *green = intel_crtc->lut_g[regno] << 8;
5449 *blue = intel_crtc->lut_b[regno] << 8;
5450}
5451
79e53945 5452static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5453 u16 *blue, uint32_t start, uint32_t size)
79e53945 5454{
7203425a 5455 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5457
7203425a 5458 for (i = start; i < end; i++) {
79e53945
JB		 5459 intel_crtc->lut_r[i] = red[i] >> 8;
5460 intel_crtc->lut_g[i] = green[i] >> 8;
5461 intel_crtc->lut_b[i] = blue[i] >> 8;
5462 }
5463
5464 intel_crtc_load_lut(crtc);
5465}
5466
5467/**
5468 * Get a pipe with a simple mode set on it for doing load-based monitor
5469 * detection.
5470 *
5471 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5472 * its requirements. The pipe will be connected to no other encoders.
79e53945 5473 *
c751ce4f 5474 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5475 * configured for it. In the future, it could choose to temporarily disable
5476 * some outputs to free up a pipe for its use.
5477 *
5478 * \return crtc, or NULL if no pipes are available.
5479 */
5480
5481/* VESA 640x480x72Hz mode to set on the pipe */
5482static struct drm_display_mode load_detect_mode = {
5483 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5484 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5485};
5486
d2dff872
CW		 5487static struct drm_framebuffer *
5488intel_framebuffer_create(struct drm_device *dev,
5489 struct drm_mode_fb_cmd *mode_cmd,
5490 struct drm_i915_gem_object *obj)
5491{
5492 struct intel_framebuffer *intel_fb;
5493 int ret;
5494
5495 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5496 if (!intel_fb) {
5497 drm_gem_object_unreference_unlocked(&obj->base);
5498 return ERR_PTR(-ENOMEM);
5499 }
5500
5501 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5502 if (ret) {
5503 drm_gem_object_unreference_unlocked(&obj->base);
5504 kfree(intel_fb);
5505 return ERR_PTR(ret);
5506 }
5507
5508 return &intel_fb->base;
5509}
5510
5511static u32
5512intel_framebuffer_pitch_for_width(int width, int bpp)
5513{
5514 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5515 return ALIGN(pitch, 64);
5516}
5517
5518static u32
5519intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5520{
5521 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5522 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5523}
5524
5525static struct drm_framebuffer *
5526intel_framebuffer_create_for_mode(struct drm_device *dev,
5527 struct drm_display_mode *mode,
5528 int depth, int bpp)
5529{
5530 struct drm_i915_gem_object *obj;
5531 struct drm_mode_fb_cmd mode_cmd;
5532
5533 obj = i915_gem_alloc_object(dev,
5534 intel_framebuffer_size_for_mode(mode, bpp));
5535 if (obj == NULL)
5536 return ERR_PTR(-ENOMEM);
5537
5538 mode_cmd.width = mode->hdisplay;
5539 mode_cmd.height = mode->vdisplay;
5540 mode_cmd.depth = depth;
5541 mode_cmd.bpp = bpp;
5542 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5543
5544 return intel_framebuffer_create(dev, &mode_cmd, obj);
5545}
5546
5547static struct drm_framebuffer *
5548mode_fits_in_fbdev(struct drm_device *dev,
5549 struct drm_display_mode *mode)
5550{
5551 struct drm_i915_private *dev_priv = dev->dev_private;
5552 struct drm_i915_gem_object *obj;
5553 struct drm_framebuffer *fb;
5554
5555 if (dev_priv->fbdev == NULL)
5556 return NULL;
5557
5558 obj = dev_priv->fbdev->ifb.obj;
5559 if (obj == NULL)
5560 return NULL;
5561
5562 fb = &dev_priv->fbdev->ifb.base;
5563 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5564 fb->bits_per_pixel))
5565 return NULL;
5566
5567 if (obj->base.size < mode->vdisplay * fb->pitch)
5568 return NULL;
5569
5570 return fb;
5571}
5572
7173188d
CW		 5573bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5574 struct drm_connector *connector,
5575 struct drm_display_mode *mode,
8261b191 5576 struct intel_load_detect_pipe *old)
79e53945
JB		 5577{
5578 struct intel_crtc *intel_crtc;
5579 struct drm_crtc *possible_crtc;
4ef69c7a 5580 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5581 struct drm_crtc *crtc = NULL;
5582 struct drm_device *dev = encoder->dev;
d2dff872 5583 struct drm_framebuffer *old_fb;
79e53945
JB		 5584 int i = -1;
5585
d2dff872
CW		 5586 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5587 connector->base.id, drm_get_connector_name(connector),
5588 encoder->base.id, drm_get_encoder_name(encoder));
5589
79e53945
JB		 5590 /*
5591 * Algorithm gets a little messy:
7a5e4805 5592 *
79e53945
JB		 5593 * - if the connector already has an assigned crtc, use it (but make
5594 * sure it's on first)
7a5e4805 5595 *
79e53945
JB		 5596 * - try to find the first unused crtc that can drive this connector,
5597 * and use that if we find one
79e53945
JB		 5598 */
5599
5600 /* See if we already have a CRTC for this connector */
5601 if (encoder->crtc) {
5602 crtc = encoder->crtc;
8261b191 5603
79e53945 5604 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5605 old->dpms_mode = intel_crtc->dpms_mode;
5606 old->load_detect_temp = false;
5607
5608 /* Make sure the crtc and connector are running */
79e53945 5609 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5610 struct drm_encoder_helper_funcs *encoder_funcs;
5611 struct drm_crtc_helper_funcs *crtc_funcs;
5612
79e53945
JB		 5613 crtc_funcs = crtc->helper_private;
5614 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5615
5616 encoder_funcs = encoder->helper_private;
79e53945
JB		 5617 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5618 }
8261b191 5619
7173188d 5620 return true;
79e53945
JB		 5621 }
5622
5623 /* Find an unused one (if possible) */
5624 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5625 i++;
5626 if (!(encoder->possible_crtcs & (1 << i)))
5627 continue;
5628 if (!possible_crtc->enabled) {
5629 crtc = possible_crtc;
5630 break;
5631 }
79e53945
JB		 5632 }
5633
5634 /*
5635 * If we didn't find an unused CRTC, don't use any.
5636 */
5637 if (!crtc) {
7173188d
CW		 5638 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5639 return false;
79e53945
JB		 5640 }
5641
5642 encoder->crtc = crtc;
c1c43977 5643 connector->encoder = encoder;
79e53945
JB		 5644
5645 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5646 old->dpms_mode = intel_crtc->dpms_mode;
5647 old->load_detect_temp = true;
d2dff872 5648 old->release_fb = NULL;
79e53945 5649
6492711d
CW		 5650 if (!mode)
5651 mode = &load_detect_mode;
79e53945 5652
d2dff872
CW		 5653 old_fb = crtc->fb;
5654
5655 /* We need a framebuffer large enough to accommodate all accesses
5656 * that the plane may generate whilst we perform load detection.
5657 * We can not rely on the fbcon either being present (we get called
5658 * during its initialisation to detect all boot displays, or it may
5659 * not even exist) or that it is large enough to satisfy the
5660 * requested mode.
5661 */
5662 crtc->fb = mode_fits_in_fbdev(dev, mode);
5663 if (crtc->fb == NULL) {
5664 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5665 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5666 old->release_fb = crtc->fb;
5667 } else
5668 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5669 if (IS_ERR(crtc->fb)) {
5670 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5671 crtc->fb = old_fb;
5672 return false;
5673 }
5674
5675 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5676 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5677 if (old->release_fb)
5678 old->release_fb->funcs->destroy(old->release_fb);
5679 crtc->fb = old_fb;
6492711d 5680 return false;
79e53945 5681 }
7173188d 5682
79e53945 5683 /* let the connector get through one full cycle before testing */
9d0498a2 5684 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5685
7173188d 5686 return true;
79e53945
JB		 5687}
5688
c1c43977 5689void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5690 struct drm_connector *connector,
5691 struct intel_load_detect_pipe *old)
79e53945 5692{
4ef69c7a 5693 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5694 struct drm_device *dev = encoder->dev;
5695 struct drm_crtc *crtc = encoder->crtc;
5696 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5697 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5698
d2dff872
CW		 5699 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5700 connector->base.id, drm_get_connector_name(connector),
5701 encoder->base.id, drm_get_encoder_name(encoder));
5702
8261b191 5703 if (old->load_detect_temp) {
c1c43977 5704 connector->encoder = NULL;
79e53945 5705 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5706
5707 if (old->release_fb)
5708 old->release_fb->funcs->destroy(old->release_fb);
5709
0622a53c 5710 return;
79e53945
JB		 5711 }
5712
c751ce4f 5713 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5714 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5715 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5716 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5717 }
5718}
5719
5720/* Returns the clock of the currently programmed mode of the given pipe. */
5721static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5722{
5723 struct drm_i915_private *dev_priv = dev->dev_private;
5724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5725 int pipe = intel_crtc->pipe;
548f245b 5726 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5727 u32 fp;
5728 intel_clock_t clock;
5729
5730 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5731 fp = I915_READ(FP0(pipe));
79e53945 5732 else
39adb7a5 5733 fp = I915_READ(FP1(pipe));
79e53945
JB		 5734
5735 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5736 if (IS_PINEVIEW(dev)) {
5737 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5738 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5739 } else {
5740 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5741 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5742 }
5743
a6c45cf0 5744 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5745 if (IS_PINEVIEW(dev))
5746 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5747 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5748 else
5749 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5750 DPLL_FPA01_P1_POST_DIV_SHIFT);
5751
5752 switch (dpll & DPLL_MODE_MASK) {
5753 case DPLLB_MODE_DAC_SERIAL:
5754 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5755 5 : 10;
5756 break;
5757 case DPLLB_MODE_LVDS:
5758 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5759 7 : 14;
5760 break;
5761 default:
28c97730 5762 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5763 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5764 return 0;
5765 }
5766
5767 /* XXX: Handle the 100Mhz refclk */
2177832f 5768 intel_clock(dev, 96000, &clock);
79e53945
JB		 5769 } else {
5770 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5771
5772 if (is_lvds) {
5773 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5774 DPLL_FPA01_P1_POST_DIV_SHIFT);
5775 clock.p2 = 14;
5776
5777 if ((dpll & PLL_REF_INPUT_MASK) ==
5778 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5779 /* XXX: might not be 66MHz */
2177832f 5780 intel_clock(dev, 66000, &clock);
79e53945 5781 } else
2177832f 5782 intel_clock(dev, 48000, &clock);
79e53945
JB		 5783 } else {
5784 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5785 clock.p1 = 2;
5786 else {
5787 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5788 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5789 }
5790 if (dpll & PLL_P2_DIVIDE_BY_4)
5791 clock.p2 = 4;
5792 else
5793 clock.p2 = 2;
5794
2177832f 5795 intel_clock(dev, 48000, &clock);
79e53945
JB		 5796 }
5797 }
5798
5799 /* XXX: It would be nice to validate the clocks, but we can't reuse
5800 * i830PllIsValid() because it relies on the xf86_config connector
5801 * configuration being accurate, which it isn't necessarily.
5802 */
5803
5804 return clock.dot;
5805}
5806
5807/** Returns the currently programmed mode of the given pipe. */
5808struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5809 struct drm_crtc *crtc)
5810{
548f245b 5811 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5813 int pipe = intel_crtc->pipe;
5814 struct drm_display_mode *mode;
548f245b
JB		 5815 int htot = I915_READ(HTOTAL(pipe));
5816 int hsync = I915_READ(HSYNC(pipe));
5817 int vtot = I915_READ(VTOTAL(pipe));
5818 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5819
5820 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5821 if (!mode)
5822 return NULL;
5823
5824 mode->clock = intel_crtc_clock_get(dev, crtc);
5825 mode->hdisplay = (htot & 0xffff) + 1;
5826 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5827 mode->hsync_start = (hsync & 0xffff) + 1;
5828 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5829 mode->vdisplay = (vtot & 0xffff) + 1;
5830 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5831 mode->vsync_start = (vsync & 0xffff) + 1;
5832 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5833
5834 drm_mode_set_name(mode);
5835 drm_mode_set_crtcinfo(mode, 0);
5836
5837 return mode;
5838}
5839
652c393a
JB		 5840#define GPU_IDLE_TIMEOUT 500 /* ms */
5841
5842/* When this timer fires, we've been idle for awhile */
5843static void intel_gpu_idle_timer(unsigned long arg)
5844{
5845 struct drm_device *dev = (struct drm_device *)arg;
5846 drm_i915_private_t *dev_priv = dev->dev_private;
5847
ff7ea4c0
CW		 5848 if (!list_empty(&dev_priv->mm.active_list)) {
5849 /* Still processing requests, so just re-arm the timer. */
5850 mod_timer(&dev_priv->idle_timer, jiffies +
5851 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5852 return;
5853 }
652c393a 5854
ff7ea4c0 5855 dev_priv->busy = false;
01dfba93 5856 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5857}
5858
652c393a
JB		 5859#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5860
5861static void intel_crtc_idle_timer(unsigned long arg)
5862{
5863 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5864 struct drm_crtc *crtc = &intel_crtc->base;
5865 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 5866 struct intel_framebuffer *intel_fb;
652c393a 5867
ff7ea4c0
CW		 5868 intel_fb = to_intel_framebuffer(crtc->fb);
5869 if (intel_fb && intel_fb->obj->active) {
5870 /* The framebuffer is still being accessed by the GPU. */
5871 mod_timer(&intel_crtc->idle_timer, jiffies +
5872 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5873 return;
5874 }
652c393a 5875
ff7ea4c0 5876 intel_crtc->busy = false;
01dfba93 5877 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5878}
5879
3dec0095 5880static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5881{
5882 struct drm_device *dev = crtc->dev;
5883 drm_i915_private_t *dev_priv = dev->dev_private;
5884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5885 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5886 int dpll_reg = DPLL(pipe);
5887 int dpll;
652c393a 5888
bad720ff 5889 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5890 return;
5891
5892 if (!dev_priv->lvds_downclock_avail)
5893 return;
5894
dbdc6479 5895 dpll = I915_READ(dpll_reg);
652c393a 5896 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 5897 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 5898
5899 /* Unlock panel regs */
dbdc6479
JB		 5900 I915_WRITE(PP_CONTROL,
5901 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 5902
5903 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5904 I915_WRITE(dpll_reg, dpll);
9d0498a2 5905 intel_wait_for_vblank(dev, pipe);
dbdc6479 5906
652c393a
JB		 5907 dpll = I915_READ(dpll_reg);
5908 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 5909 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 5910
5911 /* ...and lock them again */
5912 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5913 }
5914
5915 /* Schedule downclock */
3dec0095
DV		 5916 mod_timer(&intel_crtc->idle_timer, jiffies +
5917 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 5918}
5919
5920static void intel_decrease_pllclock(struct drm_crtc *crtc)
5921{
5922 struct drm_device *dev = crtc->dev;
5923 drm_i915_private_t *dev_priv = dev->dev_private;
5924 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5925 int pipe = intel_crtc->pipe;
9db4a9c7 5926 int dpll_reg = DPLL(pipe);
652c393a
JB		 5927 int dpll = I915_READ(dpll_reg);
5928
bad720ff 5929 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5930 return;
5931
5932 if (!dev_priv->lvds_downclock_avail)
5933 return;
5934
5935 /*
5936 * Since this is called by a timer, we should never get here in
5937 * the manual case.
5938 */
5939 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 5940 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 5941
5942 /* Unlock panel regs */
4a655f04
JB		 5943 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
5944 PANEL_UNLOCK_REGS);
652c393a
JB		 5945
5946 dpll |= DISPLAY_RATE_SELECT_FPA1;
5947 I915_WRITE(dpll_reg, dpll);
9d0498a2 5948 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 5949 dpll = I915_READ(dpll_reg);
5950 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 5951 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 5952
5953 /* ...and lock them again */
5954 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5955 }
5956
5957}
5958
5959/**
5960 * intel_idle_update - adjust clocks for idleness
5961 * @work: work struct
5962 *
5963 * Either the GPU or display (or both) went idle. Check the busy status
5964 * here and adjust the CRTC and GPU clocks as necessary.
5965 */
5966static void intel_idle_update(struct work_struct *work)
5967{
5968 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5969 idle_work);
5970 struct drm_device *dev = dev_priv->dev;
5971 struct drm_crtc *crtc;
5972 struct intel_crtc *intel_crtc;
5973
5974 if (!i915_powersave)
5975 return;
5976
5977 mutex_lock(&dev->struct_mutex);
5978
7648fa99
JB		 5979 i915_update_gfx_val(dev_priv);
5980
652c393a
JB		 5981 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5982 /* Skip inactive CRTCs */
5983 if (!crtc->fb)
5984 continue;
5985
5986 intel_crtc = to_intel_crtc(crtc);
5987 if (!intel_crtc->busy)
5988 intel_decrease_pllclock(crtc);
5989 }
5990
45ac22c8 5991
652c393a
JB		 5992 mutex_unlock(&dev->struct_mutex);
5993}
5994
5995/**
5996 * intel_mark_busy - mark the GPU and possibly the display busy
5997 * @dev: drm device
5998 * @obj: object we're operating on
5999 *
6000 * Callers can use this function to indicate that the GPU is busy processing
6001 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6002 * buffer), we'll also mark the display as busy, so we know to increase its
6003 * clock frequency.
6004 */
05394f39 6005void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 6006{
6007 drm_i915_private_t *dev_priv = dev->dev_private;
6008 struct drm_crtc *crtc = NULL;
6009 struct intel_framebuffer *intel_fb;
6010 struct intel_crtc *intel_crtc;
6011
5e17ee74
ZW		 6012 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6013 return;
6014
18b2190c 6015 if (!dev_priv->busy)
28cf798f 6016 dev_priv->busy = true;
18b2190c 6017 else
28cf798f
CW		 6018 mod_timer(&dev_priv->idle_timer, jiffies +
6019 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 6020
6021 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6022 if (!crtc->fb)
6023 continue;
6024
6025 intel_crtc = to_intel_crtc(crtc);
6026 intel_fb = to_intel_framebuffer(crtc->fb);
6027 if (intel_fb->obj == obj) {
6028 if (!intel_crtc->busy) {
6029 /* Non-busy -> busy, upclock */
3dec0095 6030 intel_increase_pllclock(crtc);
652c393a
JB		 6031 intel_crtc->busy = true;
6032 } else {
6033 /* Busy -> busy, put off timer */
6034 mod_timer(&intel_crtc->idle_timer, jiffies +
6035 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6036 }
6037 }
6038 }
6039}
6040
79e53945
JB		 6041static void intel_crtc_destroy(struct drm_crtc *crtc)
6042{
6043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6044 struct drm_device *dev = crtc->dev;
6045 struct intel_unpin_work *work;
6046 unsigned long flags;
6047
6048 spin_lock_irqsave(&dev->event_lock, flags);
6049 work = intel_crtc->unpin_work;
6050 intel_crtc->unpin_work = NULL;
6051 spin_unlock_irqrestore(&dev->event_lock, flags);
6052
6053 if (work) {
6054 cancel_work_sync(&work->work);
6055 kfree(work);
6056 }
79e53945
JB		 6057
6058 drm_crtc_cleanup(crtc);
67e77c5a 6059
79e53945
JB		 6060 kfree(intel_crtc);
6061}
6062
6b95a207
KH		 6063static void intel_unpin_work_fn(struct work_struct *__work)
6064{
6065 struct intel_unpin_work *work =
6066 container_of(__work, struct intel_unpin_work, work);
6067
6068 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 6069 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW		 6070 drm_gem_object_unreference(&work->pending_flip_obj->base);
6071 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6072
6b95a207
KH		 6073 mutex_unlock(&work->dev->struct_mutex);
6074 kfree(work);
6075}
6076
1afe3e9d 6077static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6078 struct drm_crtc *crtc)
6b95a207
KH		 6079{
6080 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6082 struct intel_unpin_work *work;
05394f39 6083 struct drm_i915_gem_object *obj;
6b95a207 6084 struct drm_pending_vblank_event *e;
49b14a5c 6085 struct timeval tnow, tvbl;
6b95a207
KH		 6086 unsigned long flags;
6087
6088 /* Ignore early vblank irqs */
6089 if (intel_crtc == NULL)
6090 return;
6091
49b14a5c
MK		 6092 do_gettimeofday(&tnow);
6093
6b95a207
KH		 6094 spin_lock_irqsave(&dev->event_lock, flags);
6095 work = intel_crtc->unpin_work;
6096 if (work == NULL || !work->pending) {
6097 spin_unlock_irqrestore(&dev->event_lock, flags);
6098 return;
6099 }
6100
6101 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6102
6103 if (work->event) {
6104 e = work->event;
49b14a5c 6105 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6106
6107 /* Called before vblank count and timestamps have
6108 * been updated for the vblank interval of flip
6109 * completion? Need to increment vblank count and
6110 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6111 * to account for this. We assume this happened if we
6112 * get called over 0.9 frame durations after the last
6113 * timestamped vblank.
6114 *
6115 * This calculation can not be used with vrefresh rates
6116 * below 5Hz (10Hz to be on the safe side) without
6117 * promoting to 64 integers.
0af7e4df 6118 */
49b14a5c
MK		 6119 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6120 9 * crtc->framedur_ns) {
0af7e4df 6121 e->event.sequence++;
49b14a5c
MK		 6122 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6123 crtc->framedur_ns);
0af7e4df
MK		 6124 }
6125
49b14a5c
MK		 6126 e->event.tv_sec = tvbl.tv_sec;
6127 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6128
6b95a207
KH		 6129 list_add_tail(&e->base.link,
6130 &e->base.file_priv->event_list);
6131 wake_up_interruptible(&e->base.file_priv->event_wait);
6132 }
6133
0af7e4df
MK		 6134 drm_vblank_put(dev, intel_crtc->pipe);
6135
6b95a207
KH		 6136 spin_unlock_irqrestore(&dev->event_lock, flags);
6137
05394f39 6138 obj = work->old_fb_obj;
d9e86c0e 6139
e59f2bac 6140 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6141 &obj->pending_flip.counter);
6142 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6143 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6144
6b95a207 6145 schedule_work(&work->work);
e5510fac
JB		 6146
6147 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6148}
6149
1afe3e9d
JB		 6150void intel_finish_page_flip(struct drm_device *dev, int pipe)
6151{
6152 drm_i915_private_t *dev_priv = dev->dev_private;
6153 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6154
49b14a5c 6155 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6156}
6157
6158void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6159{
6160 drm_i915_private_t *dev_priv = dev->dev_private;
6161 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6162
49b14a5c 6163 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6164}
6165
6b95a207
KH		 6166void intel_prepare_page_flip(struct drm_device *dev, int plane)
6167{
6168 drm_i915_private_t *dev_priv = dev->dev_private;
6169 struct intel_crtc *intel_crtc =
6170 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6171 unsigned long flags;
6172
6173 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6174 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6175 if ((++intel_crtc->unpin_work->pending) > 1)
6176 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6177 } else {
6178 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6179 }
6b95a207
KH		 6180 spin_unlock_irqrestore(&dev->event_lock, flags);
6181}
6182
6183static int intel_crtc_page_flip(struct drm_crtc *crtc,
6184 struct drm_framebuffer *fb,
6185 struct drm_pending_vblank_event *event)
6186{
6187 struct drm_device *dev = crtc->dev;
6188 struct drm_i915_private *dev_priv = dev->dev_private;
6189 struct intel_framebuffer *intel_fb;
05394f39 6190 struct drm_i915_gem_object *obj;
6b95a207
KH		 6191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6192 struct intel_unpin_work *work;
be9a3dbf 6193 unsigned long flags, offset;
52e68630 6194 int pipe = intel_crtc->pipe;
20f0cd55 6195 u32 pf, pipesrc;
52e68630 6196 int ret;
6b95a207
KH		 6197
6198 work = kzalloc(sizeof *work, GFP_KERNEL);
6199 if (work == NULL)
6200 return -ENOMEM;
6201
6b95a207
KH		 6202 work->event = event;
6203 work->dev = crtc->dev;
6204 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6205 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6206 INIT_WORK(&work->work, intel_unpin_work_fn);
6207
6208 /* We borrow the event spin lock for protecting unpin_work */
6209 spin_lock_irqsave(&dev->event_lock, flags);
6210 if (intel_crtc->unpin_work) {
6211 spin_unlock_irqrestore(&dev->event_lock, flags);
6212 kfree(work);
468f0b44
CW		 6213
6214 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6215 return -EBUSY;
6216 }
6217 intel_crtc->unpin_work = work;
6218 spin_unlock_irqrestore(&dev->event_lock, flags);
6219
6220 intel_fb = to_intel_framebuffer(fb);
6221 obj = intel_fb->obj;
6222
468f0b44 6223 mutex_lock(&dev->struct_mutex);
1ec14ad3 6224 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
96b099fd
CW		 6225 if (ret)
6226 goto cleanup_work;
6b95a207 6227
75dfca80 6228 /* Reference the objects for the scheduled work. */
05394f39
CW		 6229 drm_gem_object_reference(&work->old_fb_obj->base);
6230 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6231
6232 crtc->fb = fb;
96b099fd
CW		 6233
6234 ret = drm_vblank_get(dev, intel_crtc->pipe);
6235 if (ret)
6236 goto cleanup_objs;
6237
c7f9f9a8
CW		 6238 if (IS_GEN3(dev) || IS_GEN2(dev)) {
6239 u32 flip_mask;
48b956c5 6240
c7f9f9a8
CW		 6241 /* Can't queue multiple flips, so wait for the previous
6242 * one to finish before executing the next.
6243 */
e1f99ce6
CW		 6244 ret = BEGIN_LP_RING(2);
6245 if (ret)
6246 goto cleanup_objs;
6247
c7f9f9a8
CW		 6248 if (intel_crtc->plane)
6249 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6250 else
6251 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6252 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6253 OUT_RING(MI_NOOP);
6146b3d6
DV		 6254 ADVANCE_LP_RING();
6255 }
83f7fd05 6256
e1f99ce6 6257 work->pending_flip_obj = obj;
e1f99ce6 6258
4e5359cd
SF		 6259 work->enable_stall_check = true;
6260
be9a3dbf 6261 /* Offset into the new buffer for cases of shared fbs between CRTCs */
52e68630 6262 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
be9a3dbf 6263
e1f99ce6
CW		 6264 ret = BEGIN_LP_RING(4);
6265 if (ret)
6266 goto cleanup_objs;
6267
6268 /* Block clients from rendering to the new back buffer until
6269 * the flip occurs and the object is no longer visible.
6270 */
05394f39 6271 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6
CW		 6272
6273 switch (INTEL_INFO(dev)->gen) {
52e68630 6274 case 2:
1afe3e9d
JB		 6275 OUT_RING(MI_DISPLAY_FLIP |
6276 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6277 OUT_RING(fb->pitch);
05394f39 6278 OUT_RING(obj->gtt_offset + offset);
52e68630
CW		 6279 OUT_RING(MI_NOOP);
6280 break;
6281
6282 case 3:
1afe3e9d
JB		 6283 OUT_RING(MI_DISPLAY_FLIP_I915 |
6284 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6285 OUT_RING(fb->pitch);
05394f39 6286 OUT_RING(obj->gtt_offset + offset);
22fd0fab 6287 OUT_RING(MI_NOOP);
52e68630
CW		 6288 break;
6289
6290 case 4:
6291 case 5:
6292 /* i965+ uses the linear or tiled offsets from the
6293 * Display Registers (which do not change across a page-flip)
6294 * so we need only reprogram the base address.
6295 */
69d0b96c
DV		 6296 OUT_RING(MI_DISPLAY_FLIP |
6297 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6298 OUT_RING(fb->pitch);
05394f39 6299 OUT_RING(obj->gtt_offset | obj->tiling_mode);
52e68630
CW		 6300
6301 /* XXX Enabling the panel-fitter across page-flip is so far
6302 * untested on non-native modes, so ignore it for now.
6303 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6304 */
6305 pf = 0;
9db4a9c7 6306 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
52e68630
CW		 6307 OUT_RING(pf | pipesrc);
6308 break;
6309
6310 case 6:
6311 OUT_RING(MI_DISPLAY_FLIP |
6312 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
05394f39
CW		 6313 OUT_RING(fb->pitch | obj->tiling_mode);
6314 OUT_RING(obj->gtt_offset);
52e68630 6315
9db4a9c7
JB		 6316 pf = I915_READ(PF_CTL(pipe)) & PF_ENABLE;
6317 pipesrc = I915_READ(PIPESRC(pipe)) & 0x0fff0fff;
52e68630
CW		 6318 OUT_RING(pf | pipesrc);
6319 break;
22fd0fab 6320 }
6b95a207
KH		 6321 ADVANCE_LP_RING();
6322
6323 mutex_unlock(&dev->struct_mutex);
6324
e5510fac
JB		 6325 trace_i915_flip_request(intel_crtc->plane, obj);
6326
6b95a207 6327 return 0;
96b099fd
CW		 6328
6329cleanup_objs:
05394f39
CW		 6330 drm_gem_object_unreference(&work->old_fb_obj->base);
6331 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6332cleanup_work:
6333 mutex_unlock(&dev->struct_mutex);
6334
6335 spin_lock_irqsave(&dev->event_lock, flags);
6336 intel_crtc->unpin_work = NULL;
6337 spin_unlock_irqrestore(&dev->event_lock, flags);
6338
6339 kfree(work);
6340
6341 return ret;
6b95a207
KH		 6342}
6343
47f1c6c9
CW		 6344static void intel_sanitize_modesetting(struct drm_device *dev,
6345 int pipe, int plane)
6346{
6347 struct drm_i915_private *dev_priv = dev->dev_private;
6348 u32 reg, val;
6349
6350 if (HAS_PCH_SPLIT(dev))
6351 return;
6352
6353 /* Who knows what state these registers were left in by the BIOS or
6354 * grub?
6355 *
6356 * If we leave the registers in a conflicting state (e.g. with the
6357 * display plane reading from the other pipe than the one we intend
6358 * to use) then when we attempt to teardown the active mode, we will
6359 * not disable the pipes and planes in the correct order -- leaving
6360 * a plane reading from a disabled pipe and possibly leading to
6361 * undefined behaviour.
6362 */
6363
6364 reg = DSPCNTR(plane);
6365 val = I915_READ(reg);
6366
6367 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6368 return;
6369 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6370 return;
6371
6372 /* This display plane is active and attached to the other CPU pipe. */
6373 pipe = !pipe;
6374
6375 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6376 intel_disable_plane(dev_priv, plane, pipe);
6377 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6378}
79e53945 6379
f6e5b160
CW		 6380static void intel_crtc_reset(struct drm_crtc *crtc)
6381{
6382 struct drm_device *dev = crtc->dev;
6383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6384
6385 /* Reset flags back to the 'unknown' status so that they
6386 * will be correctly set on the initial modeset.
6387 */
6388 intel_crtc->dpms_mode = -1;
6389
6390 /* We need to fix up any BIOS configuration that conflicts with
6391 * our expectations.
6392 */
6393 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6394}
6395
6396static struct drm_crtc_helper_funcs intel_helper_funcs = {
6397 .dpms = intel_crtc_dpms,
6398 .mode_fixup = intel_crtc_mode_fixup,
6399 .mode_set = intel_crtc_mode_set,
6400 .mode_set_base = intel_pipe_set_base,
6401 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6402 .load_lut = intel_crtc_load_lut,
6403 .disable = intel_crtc_disable,
6404};
6405
6406static const struct drm_crtc_funcs intel_crtc_funcs = {
6407 .reset = intel_crtc_reset,
6408 .cursor_set = intel_crtc_cursor_set,
6409 .cursor_move = intel_crtc_cursor_move,
6410 .gamma_set = intel_crtc_gamma_set,
6411 .set_config = drm_crtc_helper_set_config,
6412 .destroy = intel_crtc_destroy,
6413 .page_flip = intel_crtc_page_flip,
6414};
6415
b358d0a6 6416static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6417{
22fd0fab 6418 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6419 struct intel_crtc *intel_crtc;
6420 int i;
6421
6422 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6423 if (intel_crtc == NULL)
6424 return;
6425
6426 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6427
6428 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6429 for (i = 0; i < 256; i++) {
6430 intel_crtc->lut_r[i] = i;
6431 intel_crtc->lut_g[i] = i;
6432 intel_crtc->lut_b[i] = i;
6433 }
6434
80824003
JB		 6435 /* Swap pipes & planes for FBC on pre-965 */
6436 intel_crtc->pipe = pipe;
6437 intel_crtc->plane = pipe;
e2e767ab 6438 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6439 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6440 intel_crtc->plane = !pipe;
80824003
JB		 6441 }
6442
22fd0fab
JB		 6443 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6444 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6445 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6446 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6447
5d1d0cc8 6448 intel_crtc_reset(&intel_crtc->base);
04dbff52 6449 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7e7d76c3
JB		 6450
6451 if (HAS_PCH_SPLIT(dev)) {
6452 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6453 intel_helper_funcs.commit = ironlake_crtc_commit;
6454 } else {
6455 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6456 intel_helper_funcs.commit = i9xx_crtc_commit;
6457 }
6458
79e53945
JB		 6459 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6460
652c393a
JB		 6461 intel_crtc->busy = false;
6462
6463 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6464 (unsigned long)intel_crtc);
79e53945
JB		 6465}
6466
08d7b3d1 6467int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6468 struct drm_file *file)
08d7b3d1
CW		 6469{
6470 drm_i915_private_t *dev_priv = dev->dev_private;
6471 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6472 struct drm_mode_object *drmmode_obj;
6473 struct intel_crtc *crtc;
08d7b3d1
CW		 6474
6475 if (!dev_priv) {
6476 DRM_ERROR("called with no initialization\n");
6477 return -EINVAL;
6478 }
6479
c05422d5
DV		 6480 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6481 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6482
c05422d5 6483 if (!drmmode_obj) {
08d7b3d1
CW		 6484 DRM_ERROR("no such CRTC id\n");
6485 return -EINVAL;
6486 }
6487
c05422d5
DV		 6488 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6489 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6490
c05422d5 6491 return 0;
08d7b3d1
CW		 6492}
6493
c5e4df33 6494static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6495{
4ef69c7a 6496 struct intel_encoder *encoder;
79e53945 6497 int index_mask = 0;
79e53945
JB		 6498 int entry = 0;
6499
4ef69c7a
CW		 6500 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6501 if (type_mask & encoder->clone_mask)
79e53945
JB		 6502 index_mask |= (1 << entry);
6503 entry++;
6504 }
4ef69c7a 6505
79e53945
JB		 6506 return index_mask;
6507}
6508
4d302442
CW		 6509static bool has_edp_a(struct drm_device *dev)
6510{
6511 struct drm_i915_private *dev_priv = dev->dev_private;
6512
6513 if (!IS_MOBILE(dev))
6514 return false;
6515
6516 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6517 return false;
6518
6519 if (IS_GEN5(dev) &&
6520 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6521 return false;
6522
6523 return true;
6524}
6525
79e53945
JB		 6526static void intel_setup_outputs(struct drm_device *dev)
6527{
725e30ad 6528 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6529 struct intel_encoder *encoder;
cb0953d7 6530 bool dpd_is_edp = false;
c5d1b51d 6531 bool has_lvds = false;
79e53945 6532
541998a1 6533 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 6534 has_lvds = intel_lvds_init(dev);
6535 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6536 /* disable the panel fitter on everything but LVDS */
6537 I915_WRITE(PFIT_CONTROL, 0);
6538 }
79e53945 6539
bad720ff 6540 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6541 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6542
4d302442 6543 if (has_edp_a(dev))
32f9d658
ZW		 6544 intel_dp_init(dev, DP_A);
6545
cb0953d7
AJ		 6546 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6547 intel_dp_init(dev, PCH_DP_D);
6548 }
6549
6550 intel_crt_init(dev);
6551
6552 if (HAS_PCH_SPLIT(dev)) {
6553 int found;
6554
30ad48b7 6555 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 6556 /* PCH SDVOB multiplex with HDMIB */
6557 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 6558 if (!found)
6559 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6560 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6561 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6562 }
6563
6564 if (I915_READ(HDMIC) & PORT_DETECTED)
6565 intel_hdmi_init(dev, HDMIC);
6566
6567 if (I915_READ(HDMID) & PORT_DETECTED)
6568 intel_hdmi_init(dev, HDMID);
6569
5eb08b69
ZW		 6570 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6571 intel_dp_init(dev, PCH_DP_C);
6572
cb0953d7 6573 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 6574 intel_dp_init(dev, PCH_DP_D);
6575
103a196f 6576 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6577 bool found = false;
7d57382e 6578
725e30ad 6579 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6580 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 6581 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 6582 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6583 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6584 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6585 }
27185ae1 6586
b01f2c3a
JB		 6587 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6588 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6589 intel_dp_init(dev, DP_B);
b01f2c3a 6590 }
725e30ad 6591 }
13520b05
KH		 6592
6593 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6594
b01f2c3a
JB		 6595 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6596 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 6597 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 6598 }
27185ae1
ML		 6599
6600 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6601
b01f2c3a
JB		 6602 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6603 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6604 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6605 }
6606 if (SUPPORTS_INTEGRATED_DP(dev)) {
6607 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6608 intel_dp_init(dev, DP_C);
b01f2c3a 6609 }
725e30ad 6610 }
27185ae1 6611
b01f2c3a
JB		 6612 if (SUPPORTS_INTEGRATED_DP(dev) &&
6613 (I915_READ(DP_D) & DP_DETECTED)) {
6614 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 6615 intel_dp_init(dev, DP_D);
b01f2c3a 6616 }
bad720ff 6617 } else if (IS_GEN2(dev))
79e53945
JB		 6618 intel_dvo_init(dev);
6619
103a196f 6620 if (SUPPORTS_TV(dev))
79e53945
JB		 6621 intel_tv_init(dev);
6622
4ef69c7a
CW		 6623 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6624 encoder->base.possible_crtcs = encoder->crtc_mask;
6625 encoder->base.possible_clones =
6626 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 6627 }
47356eb6
CW		 6628
6629 intel_panel_setup_backlight(dev);
2c7111db
CW		 6630
6631 /* disable all the possible outputs/crtcs before entering KMS mode */
6632 drm_helper_disable_unused_functions(dev);
79e53945
JB		 6633}
6634
6635static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6636{
6637 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6638
6639 drm_framebuffer_cleanup(fb);
05394f39 6640 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6641
6642 kfree(intel_fb);
6643}
6644
6645static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6646 struct drm_file *file,
79e53945
JB		 6647 unsigned int *handle)
6648{
6649 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6650 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6651
05394f39 6652 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6653}
6654
6655static const struct drm_framebuffer_funcs intel_fb_funcs = {
6656 .destroy = intel_user_framebuffer_destroy,
6657 .create_handle = intel_user_framebuffer_create_handle,
6658};
6659
38651674
DA		 6660int intel_framebuffer_init(struct drm_device *dev,
6661 struct intel_framebuffer *intel_fb,
6662 struct drm_mode_fb_cmd *mode_cmd,
05394f39 6663 struct drm_i915_gem_object *obj)
79e53945 6664{
79e53945
JB		 6665 int ret;
6666
05394f39 6667 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6668 return -EINVAL;
6669
6670 if (mode_cmd->pitch & 63)
6671 return -EINVAL;
6672
6673 switch (mode_cmd->bpp) {
6674 case 8:
6675 case 16:
6676 case 24:
6677 case 32:
6678 break;
6679 default:
6680 return -EINVAL;
6681 }
6682
79e53945
JB		 6683 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6684 if (ret) {
6685 DRM_ERROR("framebuffer init failed %d\n", ret);
6686 return ret;
6687 }
6688
6689 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6690 intel_fb->obj = obj;
79e53945
JB		 6691 return 0;
6692}
6693
79e53945
JB		 6694static struct drm_framebuffer *
6695intel_user_framebuffer_create(struct drm_device *dev,
6696 struct drm_file *filp,
6697 struct drm_mode_fb_cmd *mode_cmd)
6698{
05394f39 6699 struct drm_i915_gem_object *obj;
79e53945 6700
05394f39 6701 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
c8725226 6702 if (&obj->base == NULL)
cce13ff7 6703 return ERR_PTR(-ENOENT);
79e53945 6704
d2dff872 6705 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6706}
6707
79e53945 6708static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6709 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6710 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6711};
6712
05394f39 6713static struct drm_i915_gem_object *
aa40d6bb 6714intel_alloc_context_page(struct drm_device *dev)
9ea8d059 6715{
05394f39 6716 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 6717 int ret;
6718
2c34b850
BW		 6719 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
6720
aa40d6bb
ZN		 6721 ctx = i915_gem_alloc_object(dev, 4096);
6722 if (!ctx) {
9ea8d059
CW		 6723 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6724 return NULL;
6725 }
6726
75e9e915 6727 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 6728 if (ret) {
6729 DRM_ERROR("failed to pin power context: %d\n", ret);
6730 goto err_unref;
6731 }
6732
aa40d6bb 6733 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 6734 if (ret) {
6735 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6736 goto err_unpin;
6737 }
9ea8d059 6738
aa40d6bb 6739 return ctx;
9ea8d059
CW		 6740
6741err_unpin:
aa40d6bb 6742 i915_gem_object_unpin(ctx);
9ea8d059 6743err_unref:
05394f39 6744 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 6745 mutex_unlock(&dev->struct_mutex);
6746 return NULL;
6747}
6748
7648fa99
JB		 6749bool ironlake_set_drps(struct drm_device *dev, u8 val)
6750{
6751 struct drm_i915_private *dev_priv = dev->dev_private;
6752 u16 rgvswctl;
6753
6754 rgvswctl = I915_READ16(MEMSWCTL);
6755 if (rgvswctl & MEMCTL_CMD_STS) {
6756 DRM_DEBUG("gpu busy, RCS change rejected\n");
6757 return false; /* still busy with another command */
6758 }
6759
6760 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6761 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6762 I915_WRITE16(MEMSWCTL, rgvswctl);
6763 POSTING_READ16(MEMSWCTL);
6764
6765 rgvswctl |= MEMCTL_CMD_STS;
6766 I915_WRITE16(MEMSWCTL, rgvswctl);
6767
6768 return true;
6769}
6770
f97108d1
JB		 6771void ironlake_enable_drps(struct drm_device *dev)
6772{
6773 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 6774 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 6775 u8 fmax, fmin, fstart, vstart;
f97108d1 6776
ea056c14
JB		 6777 /* Enable temp reporting */
6778 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6779 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6780
f97108d1
JB		 6781 /* 100ms RC evaluation intervals */
6782 I915_WRITE(RCUPEI, 100000);
6783 I915_WRITE(RCDNEI, 100000);
6784
6785 /* Set max/min thresholds to 90ms and 80ms respectively */
6786 I915_WRITE(RCBMAXAVG, 90000);
6787 I915_WRITE(RCBMINAVG, 80000);
6788
6789 I915_WRITE(MEMIHYST, 1);
6790
6791 /* Set up min, max, and cur for interrupt handling */
6792 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6793 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6794 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6795 MEMMODE_FSTART_SHIFT;
7648fa99 6796
f97108d1
JB		 6797 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6798 PXVFREQ_PX_SHIFT;
6799
80dbf4b7 6800 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 6801 dev_priv->fstart = fstart;
6802
80dbf4b7 6803 dev_priv->max_delay = fstart;
f97108d1
JB		 6804 dev_priv->min_delay = fmin;
6805 dev_priv->cur_delay = fstart;
6806
80dbf4b7
JB		 6807 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6808 fmax, fmin, fstart);
7648fa99 6809
f97108d1
JB		 6810 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6811
6812 /*
6813 * Interrupts will be enabled in ironlake_irq_postinstall
6814 */
6815
6816 I915_WRITE(VIDSTART, vstart);
6817 POSTING_READ(VIDSTART);
6818
6819 rgvmodectl |= MEMMODE_SWMODE_EN;
6820 I915_WRITE(MEMMODECTL, rgvmodectl);
6821
481b6af3 6822 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 6823 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 6824 msleep(1);
6825
7648fa99 6826 ironlake_set_drps(dev, fstart);
f97108d1 6827
7648fa99
JB		 6828 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
6829 I915_READ(0x112e0);
6830 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
6831 dev_priv->last_count2 = I915_READ(0x112f4);
6832 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 6833}
6834
6835void ironlake_disable_drps(struct drm_device *dev)
6836{
6837 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 6838 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 6839
6840 /* Ack interrupts, disable EFC interrupt */
6841 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6842 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6843 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6844 I915_WRITE(DEIIR, DE_PCU_EVENT);
6845 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
6846
6847 /* Go back to the starting frequency */
7648fa99 6848 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 6849 msleep(1);
6850 rgvswctl |= MEMCTL_CMD_STS;
6851 I915_WRITE(MEMSWCTL, rgvswctl);
6852 msleep(1);
6853
6854}
6855
3b8d8d91
JB		 6856void gen6_set_rps(struct drm_device *dev, u8 val)
6857{
6858 struct drm_i915_private *dev_priv = dev->dev_private;
6859 u32 swreq;
6860
6861 swreq = (val & 0x3ff) << 25;
6862 I915_WRITE(GEN6_RPNSWREQ, swreq);
6863}
6864
6865void gen6_disable_rps(struct drm_device *dev)
6866{
6867 struct drm_i915_private *dev_priv = dev->dev_private;
6868
6869 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6870 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6871 I915_WRITE(GEN6_PMIER, 0);
6872 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
6873}
6874
7648fa99
JB		 6875static unsigned long intel_pxfreq(u32 vidfreq)
6876{
6877 unsigned long freq;
6878 int div = (vidfreq & 0x3f0000) >> 16;
6879 int post = (vidfreq & 0x3000) >> 12;
6880 int pre = (vidfreq & 0x7);
6881
6882 if (!pre)
6883 return 0;
6884
6885 freq = ((div * 133333) / ((1<<post) * pre));
6886
6887 return freq;
6888}
6889
6890void intel_init_emon(struct drm_device *dev)
6891{
6892 struct drm_i915_private *dev_priv = dev->dev_private;
6893 u32 lcfuse;
6894 u8 pxw[16];
6895 int i;
6896
6897 /* Disable to program */
6898 I915_WRITE(ECR, 0);
6899 POSTING_READ(ECR);
6900
6901 /* Program energy weights for various events */
6902 I915_WRITE(SDEW, 0x15040d00);
6903 I915_WRITE(CSIEW0, 0x007f0000);
6904 I915_WRITE(CSIEW1, 0x1e220004);
6905 I915_WRITE(CSIEW2, 0x04000004);
6906
6907 for (i = 0; i < 5; i++)
6908 I915_WRITE(PEW + (i * 4), 0);
6909 for (i = 0; i < 3; i++)
6910 I915_WRITE(DEW + (i * 4), 0);
6911
6912 /* Program P-state weights to account for frequency power adjustment */
6913 for (i = 0; i < 16; i++) {
6914 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6915 unsigned long freq = intel_pxfreq(pxvidfreq);
6916 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6917 PXVFREQ_PX_SHIFT;
6918 unsigned long val;
6919
6920 val = vid * vid;
6921 val *= (freq / 1000);
6922 val *= 255;
6923 val /= (127*127*900);
6924 if (val > 0xff)
6925 DRM_ERROR("bad pxval: %ld\n", val);
6926 pxw[i] = val;
6927 }
6928 /* Render standby states get 0 weight */
6929 pxw[14] = 0;
6930 pxw[15] = 0;
6931
6932 for (i = 0; i < 4; i++) {
6933 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6934 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6935 I915_WRITE(PXW + (i * 4), val);
6936 }
6937
6938 /* Adjust magic regs to magic values (more experimental results) */
6939 I915_WRITE(OGW0, 0);
6940 I915_WRITE(OGW1, 0);
6941 I915_WRITE(EG0, 0x00007f00);
6942 I915_WRITE(EG1, 0x0000000e);
6943 I915_WRITE(EG2, 0x000e0000);
6944 I915_WRITE(EG3, 0x68000300);
6945 I915_WRITE(EG4, 0x42000000);
6946 I915_WRITE(EG5, 0x00140031);
6947 I915_WRITE(EG6, 0);
6948 I915_WRITE(EG7, 0);
6949
6950 for (i = 0; i < 8; i++)
6951 I915_WRITE(PXWL + (i * 4), 0);
6952
6953 /* Enable PMON + select events */
6954 I915_WRITE(ECR, 0x80000019);
6955
6956 lcfuse = I915_READ(LCFUSE02);
6957
6958 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
6959}
6960
3b8d8d91 6961void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 6962{
a6044e23
JB		 6963 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6964 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 6965 u32 pcu_mbox, rc6_mask = 0;
a6044e23 6966 int cur_freq, min_freq, max_freq;
8fd26859
CW		 6967 int i;
6968
6969 /* Here begins a magic sequence of register writes to enable
6970 * auto-downclocking.
6971 *
6972 * Perhaps there might be some value in exposing these to
6973 * userspace...
6974 */
6975 I915_WRITE(GEN6_RC_STATE, 0);
91355834 6976 __gen6_gt_force_wake_get(dev_priv);
8fd26859 6977
3b8d8d91 6978 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 6979 I915_WRITE(GEN6_RC_CONTROL, 0);
6980
6981 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6982 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6983 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6984 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6985 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6986
6987 for (i = 0; i < I915_NUM_RINGS; i++)
6988 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
6989
6990 I915_WRITE(GEN6_RC_SLEEP, 0);
6991 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6992 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6993 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
6994 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6995
7df8721b
JB		 6996 if (i915_enable_rc6)
6997 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
6998 GEN6_RC_CTL_RC6_ENABLE;
6999
8fd26859 7000 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 7001 rc6_mask |
9c3d2f7f 7002 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 7003 GEN6_RC_CTL_HW_ENABLE);
7004
3b8d8d91 7005 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 7006 GEN6_FREQUENCY(10) |
7007 GEN6_OFFSET(0) |
7008 GEN6_AGGRESSIVE_TURBO);
7009 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7010 GEN6_FREQUENCY(12));
7011
7012 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7013 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7014 18 << 24 |
7015 6 << 16);
ccab5c82
JB		 7016 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7017 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 7018 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 7019 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 7020 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7021 I915_WRITE(GEN6_RP_CONTROL,
7022 GEN6_RP_MEDIA_TURBO |
7023 GEN6_RP_USE_NORMAL_FREQ |
7024 GEN6_RP_MEDIA_IS_GFX |
7025 GEN6_RP_ENABLE |
ccab5c82
JB		 7026 GEN6_RP_UP_BUSY_AVG |
7027 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 7028
7029 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7030 500))
7031 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7032
7033 I915_WRITE(GEN6_PCODE_DATA, 0);
7034 I915_WRITE(GEN6_PCODE_MAILBOX,
7035 GEN6_PCODE_READY |
7036 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7037 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7038 500))
7039 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7040
a6044e23
JB		 7041 min_freq = (rp_state_cap & 0xff0000) >> 16;
7042 max_freq = rp_state_cap & 0xff;
7043 cur_freq = (gt_perf_status & 0xff00) >> 8;
7044
7045 /* Check for overclock support */
7046 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7047 500))
7048 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7049 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7050 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7051 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7052 500))
7053 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7054 if (pcu_mbox & (1<<31)) { /* OC supported */
7055 max_freq = pcu_mbox & 0xff;
e281fcaa 7056 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 7057 }
7058
7059 /* In units of 100MHz */
7060 dev_priv->max_delay = max_freq;
7061 dev_priv->min_delay = min_freq;
7062 dev_priv->cur_delay = cur_freq;
7063
8fd26859
CW		 7064 /* requires MSI enabled */
7065 I915_WRITE(GEN6_PMIER,
7066 GEN6_PM_MBOX_EVENT |
7067 GEN6_PM_THERMAL_EVENT |
7068 GEN6_PM_RP_DOWN_TIMEOUT |
7069 GEN6_PM_RP_UP_THRESHOLD |
7070 GEN6_PM_RP_DOWN_THRESHOLD |
7071 GEN6_PM_RP_UP_EI_EXPIRED |
7072 GEN6_PM_RP_DOWN_EI_EXPIRED);
3b8d8d91
JB		 7073 I915_WRITE(GEN6_PMIMR, 0);
7074 /* enable all PM interrupts */
7075 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 7076
91355834 7077 __gen6_gt_force_wake_put(dev_priv);
8fd26859
CW		 7078}
7079
0cdab21f 7080void intel_enable_clock_gating(struct drm_device *dev)
652c393a
JB		 7081{
7082 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 7083 int pipe;
652c393a
JB		 7084
7085 /*
7086 * Disable clock gating reported to work incorrectly according to the
7087 * specs, but enable as much else as we can.
7088 */
bad720ff 7089 if (HAS_PCH_SPLIT(dev)) {
8956c8bb
EA		 7090 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7091
f00a3ddf 7092 if (IS_GEN5(dev)) {
8956c8bb 7093 /* Required for FBC */
1ffa325b
JB		 7094 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7095 DPFCRUNIT_CLOCK_GATE_DISABLE |
7096 DPFDUNIT_CLOCK_GATE_DISABLE;
8956c8bb
EA		 7097 /* Required for CxSR */
7098 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7099
7100 I915_WRITE(PCH_3DCGDIS0,
7101 MARIUNIT_CLOCK_GATE_DISABLE |
7102 SVSMUNIT_CLOCK_GATE_DISABLE);
06f37751
EA		 7103 I915_WRITE(PCH_3DCGDIS1,
7104 VFMUNIT_CLOCK_GATE_DISABLE);
8956c8bb
EA		 7105 }
7106
7107 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7f8a8569 7108
382b0936
JB		 7109 /*
7110 * On Ibex Peak and Cougar Point, we need to disable clock
7111 * gating for the panel power sequencer or it will fail to
7112 * start up when no ports are active.
7113 */
7114 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7115
7f8a8569
ZW		 7116 /*
7117 * According to the spec the following bits should be set in
7118 * order to enable memory self-refresh
7119 * The bit 22/21 of 0x42004
7120 * The bit 5 of 0x42020
7121 * The bit 15 of 0x45000
7122 */
f00a3ddf 7123 if (IS_GEN5(dev)) {
7f8a8569
ZW		 7124 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7125 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7126 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7127 I915_WRITE(ILK_DSPCLK_GATE,
7128 (I915_READ(ILK_DSPCLK_GATE) |
7129 ILK_DPARB_CLK_GATE));
7130 I915_WRITE(DISP_ARB_CTL,
7131 (I915_READ(DISP_ARB_CTL) |
7132 DISP_FBC_WM_DIS));
1398261a
YL		 7133 I915_WRITE(WM3_LP_ILK, 0);
7134 I915_WRITE(WM2_LP_ILK, 0);
7135 I915_WRITE(WM1_LP_ILK, 0);
7f8a8569 7136 }
b52eb4dc
ZY		 7137 /*
7138 * Based on the document from hardware guys the following bits
7139 * should be set unconditionally in order to enable FBC.
7140 * The bit 22 of 0x42000
7141 * The bit 22 of 0x42004
7142 * The bit 7,8,9 of 0x42020.
7143 */
7144 if (IS_IRONLAKE_M(dev)) {
7145 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7146 I915_READ(ILK_DISPLAY_CHICKEN1) |
7147 ILK_FBCQ_DIS);
7148 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7149 I915_READ(ILK_DISPLAY_CHICKEN2) |
7150 ILK_DPARB_GATE);
7151 I915_WRITE(ILK_DSPCLK_GATE,
7152 I915_READ(ILK_DSPCLK_GATE) |
7153 ILK_DPFC_DIS1 |
7154 ILK_DPFC_DIS2 |
7155 ILK_CLK_FBC);
7156 }
de6e2eaf 7157
67e92af0
EA		 7158 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7159 I915_READ(ILK_DISPLAY_CHICKEN2) |
7160 ILK_ELPIN_409_SELECT);
7161
de6e2eaf
EA		 7162 if (IS_GEN5(dev)) {
7163 I915_WRITE(_3D_CHICKEN2,
7164 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7165 _3D_CHICKEN2_WM_READ_PIPELINED);
7166 }
8fd26859 7167
1398261a
YL		 7168 if (IS_GEN6(dev)) {
7169 I915_WRITE(WM3_LP_ILK, 0);
7170 I915_WRITE(WM2_LP_ILK, 0);
7171 I915_WRITE(WM1_LP_ILK, 0);
7172
7173 /*
7174 * According to the spec the following bits should be
7175 * set in order to enable memory self-refresh and fbc:
7176 * The bit21 and bit22 of 0x42000
7177 * The bit21 and bit22 of 0x42004
7178 * The bit5 and bit7 of 0x42020
7179 * The bit14 of 0x70180
7180 * The bit14 of 0x71180
7181 */
7182 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7183 I915_READ(ILK_DISPLAY_CHICKEN1) |
7184 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7185 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7186 I915_READ(ILK_DISPLAY_CHICKEN2) |
7187 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7188 I915_WRITE(ILK_DSPCLK_GATE,
7189 I915_READ(ILK_DSPCLK_GATE) |
7190 ILK_DPARB_CLK_GATE |
7191 ILK_DPFD_CLK_GATE);
7192
9db4a9c7
JB		 7193 for_each_pipe(pipe)
7194 I915_WRITE(DSPCNTR(pipe),
7195 I915_READ(DSPCNTR(pipe)) |
7196 DISPPLANE_TRICKLE_FEED_DISABLE);
1398261a 7197 }
c03342fa 7198 } else if (IS_G4X(dev)) {
652c393a
JB		 7199 uint32_t dspclk_gate;
7200 I915_WRITE(RENCLK_GATE_D1, 0);
7201 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7202 GS_UNIT_CLOCK_GATE_DISABLE |
7203 CL_UNIT_CLOCK_GATE_DISABLE);
7204 I915_WRITE(RAMCLK_GATE_D, 0);
7205 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7206 OVRUNIT_CLOCK_GATE_DISABLE |
7207 OVCUNIT_CLOCK_GATE_DISABLE;
7208 if (IS_GM45(dev))
7209 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7210 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
a6c45cf0 7211 } else if (IS_CRESTLINE(dev)) {
652c393a
JB		 7212 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7213 I915_WRITE(RENCLK_GATE_D2, 0);
7214 I915_WRITE(DSPCLK_GATE_D, 0);
7215 I915_WRITE(RAMCLK_GATE_D, 0);
7216 I915_WRITE16(DEUC, 0);
a6c45cf0 7217 } else if (IS_BROADWATER(dev)) {
652c393a
JB		 7218 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7219 I965_RCC_CLOCK_GATE_DISABLE |
7220 I965_RCPB_CLOCK_GATE_DISABLE |
7221 I965_ISC_CLOCK_GATE_DISABLE |
7222 I965_FBC_CLOCK_GATE_DISABLE);
7223 I915_WRITE(RENCLK_GATE_D2, 0);
a6c45cf0 7224 } else if (IS_GEN3(dev)) {
652c393a
JB		 7225 u32 dstate = I915_READ(D_STATE);
7226
7227 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7228 DSTATE_DOT_CLOCK_GATING;
7229 I915_WRITE(D_STATE, dstate);
f0f8a9ce 7230 } else if (IS_I85X(dev) || IS_I865G(dev)) {
652c393a
JB		 7231 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7232 } else if (IS_I830(dev)) {
7233 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
7234 }
7235}
7236
ac668088 7237static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 7238{
7239 struct drm_i915_private *dev_priv = dev->dev_private;
7240
7241 if (dev_priv->renderctx) {
ac668088
CW		 7242 i915_gem_object_unpin(dev_priv->renderctx);
7243 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 7244 dev_priv->renderctx = NULL;
7245 }
7246
7247 if (dev_priv->pwrctx) {
ac668088
CW		 7248 i915_gem_object_unpin(dev_priv->pwrctx);
7249 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7250 dev_priv->pwrctx = NULL;
7251 }
7252}
7253
7254static void ironlake_disable_rc6(struct drm_device *dev)
7255{
7256 struct drm_i915_private *dev_priv = dev->dev_private;
7257
7258 if (I915_READ(PWRCTXA)) {
7259 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7260 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7261 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7262 50);
0cdab21f
CW		 7263
7264 I915_WRITE(PWRCTXA, 0);
7265 POSTING_READ(PWRCTXA);
7266
ac668088
CW		 7267 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7268 POSTING_READ(RSTDBYCTL);
0cdab21f 7269 }
ac668088 7270
99507307 7271 ironlake_teardown_rc6(dev);
0cdab21f
CW		 7272}
7273
ac668088 7274static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 7275{
7276 struct drm_i915_private *dev_priv = dev->dev_private;
7277
ac668088
CW		 7278 if (dev_priv->renderctx == NULL)
7279 dev_priv->renderctx = intel_alloc_context_page(dev);
7280 if (!dev_priv->renderctx)
7281 return -ENOMEM;
7282
7283 if (dev_priv->pwrctx == NULL)
7284 dev_priv->pwrctx = intel_alloc_context_page(dev);
7285 if (!dev_priv->pwrctx) {
7286 ironlake_teardown_rc6(dev);
7287 return -ENOMEM;
7288 }
7289
7290 return 0;
d5bb081b
JB		 7291}
7292
7293void ironlake_enable_rc6(struct drm_device *dev)
7294{
7295 struct drm_i915_private *dev_priv = dev->dev_private;
7296 int ret;
7297
ac668088
CW		 7298 /* rc6 disabled by default due to repeated reports of hanging during
7299 * boot and resume.
7300 */
7301 if (!i915_enable_rc6)
7302 return;
7303
2c34b850 7304 mutex_lock(&dev->struct_mutex);
ac668088 7305 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 7306 if (ret) {
7307 mutex_unlock(&dev->struct_mutex);
ac668088 7308 return;
2c34b850 7309 }
ac668088 7310
d5bb081b
JB		 7311 /*
7312 * GPU can automatically power down the render unit if given a page
7313 * to save state.
7314 */
7315 ret = BEGIN_LP_RING(6);
7316 if (ret) {
ac668088 7317 ironlake_teardown_rc6(dev);
2c34b850 7318 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7319 return;
7320 }
ac668088 7321
d5bb081b
JB		 7322 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7323 OUT_RING(MI_SET_CONTEXT);
7324 OUT_RING(dev_priv->renderctx->gtt_offset |
7325 MI_MM_SPACE_GTT |
7326 MI_SAVE_EXT_STATE_EN |
7327 MI_RESTORE_EXT_STATE_EN |
7328 MI_RESTORE_INHIBIT);
7329 OUT_RING(MI_SUSPEND_FLUSH);
7330 OUT_RING(MI_NOOP);
7331 OUT_RING(MI_FLUSH);
7332 ADVANCE_LP_RING();
7333
4a246cfc
BW		 7334 /*
7335 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7336 * does an implicit flush, combined with MI_FLUSH above, it should be
7337 * safe to assume that renderctx is valid
7338 */
7339 ret = intel_wait_ring_idle(LP_RING(dev_priv));
7340 if (ret) {
7341 DRM_ERROR("failed to enable ironlake power power savings\n");
7342 ironlake_teardown_rc6(dev);
7343 mutex_unlock(&dev->struct_mutex);
7344 return;
7345 }
7346
d5bb081b
JB		 7347 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7348 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 7349 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7350}
7351
ac668088 7352
e70236a8
JB		 7353/* Set up chip specific display functions */
7354static void intel_init_display(struct drm_device *dev)
7355{
7356 struct drm_i915_private *dev_priv = dev->dev_private;
7357
7358 /* We always want a DPMS function */
f564048e 7359 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 7360 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e
EA		 7361 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7362 } else {
e70236a8 7363 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e
EA		 7364 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7365 }
e70236a8 7366
ee5382ae 7367 if (I915_HAS_FBC(dev)) {
9c04f015 7368 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 7369 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7370 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7371 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7372 } else if (IS_GM45(dev)) {
74dff282
JB		 7373 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7374 dev_priv->display.enable_fbc = g4x_enable_fbc;
7375 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 7376 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 7377 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7378 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7379 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7380 }
74dff282 7381 /* 855GM needs testing */
e70236a8
JB		 7382 }
7383
7384 /* Returns the core display clock speed */
f2b115e6 7385 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
e70236a8
JB		 7386 dev_priv->display.get_display_clock_speed =
7387 i945_get_display_clock_speed;
7388 else if (IS_I915G(dev))
7389 dev_priv->display.get_display_clock_speed =
7390 i915_get_display_clock_speed;
f2b115e6 7391 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7392 dev_priv->display.get_display_clock_speed =
7393 i9xx_misc_get_display_clock_speed;
7394 else if (IS_I915GM(dev))
7395 dev_priv->display.get_display_clock_speed =
7396 i915gm_get_display_clock_speed;
7397 else if (IS_I865G(dev))
7398 dev_priv->display.get_display_clock_speed =
7399 i865_get_display_clock_speed;
f0f8a9ce 7400 else if (IS_I85X(dev))
e70236a8
JB		 7401 dev_priv->display.get_display_clock_speed =
7402 i855_get_display_clock_speed;
7403 else /* 852, 830 */
7404 dev_priv->display.get_display_clock_speed =
7405 i830_get_display_clock_speed;
7406
7407 /* For FIFO watermark updates */
7f8a8569 7408 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 7409 if (IS_GEN5(dev)) {
7f8a8569
ZW		 7410 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7411 dev_priv->display.update_wm = ironlake_update_wm;
7412 else {
7413 DRM_DEBUG_KMS("Failed to get proper latency. "
7414 "Disable CxSR\n");
7415 dev_priv->display.update_wm = NULL;
1398261a
YL		 7416 }
7417 } else if (IS_GEN6(dev)) {
7418 if (SNB_READ_WM0_LATENCY()) {
7419 dev_priv->display.update_wm = sandybridge_update_wm;
7420 } else {
7421 DRM_DEBUG_KMS("Failed to read display plane latency. "
7422 "Disable CxSR\n");
7423 dev_priv->display.update_wm = NULL;
7f8a8569
ZW		 7424 }
7425 } else
7426 dev_priv->display.update_wm = NULL;
7427 } else if (IS_PINEVIEW(dev)) {
d4294342 7428 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 7429 dev_priv->is_ddr3,
d4294342
ZY		 7430 dev_priv->fsb_freq,
7431 dev_priv->mem_freq)) {
7432 DRM_INFO("failed to find known CxSR latency "
95534263 7433 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 7434 "disabling CxSR\n",
95534263 7435 (dev_priv->is_ddr3 == 1) ? "3": "2",
d4294342
ZY		 7436 dev_priv->fsb_freq, dev_priv->mem_freq);
7437 /* Disable CxSR and never update its watermark again */
7438 pineview_disable_cxsr(dev);
7439 dev_priv->display.update_wm = NULL;
7440 } else
7441 dev_priv->display.update_wm = pineview_update_wm;
7442 } else if (IS_G4X(dev))
e70236a8 7443 dev_priv->display.update_wm = g4x_update_wm;
a6c45cf0 7444 else if (IS_GEN4(dev))
e70236a8 7445 dev_priv->display.update_wm = i965_update_wm;
a6c45cf0 7446 else if (IS_GEN3(dev)) {
e70236a8
JB		 7447 dev_priv->display.update_wm = i9xx_update_wm;
7448 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8f4695ed
AJ		 7449 } else if (IS_I85X(dev)) {
7450 dev_priv->display.update_wm = i9xx_update_wm;
7451 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
e70236a8 7452 } else {
8f4695ed
AJ		 7453 dev_priv->display.update_wm = i830_update_wm;
7454 if (IS_845G(dev))
e70236a8
JB		 7455 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7456 else
7457 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8
JB		 7458 }
7459}
7460
b690e96c
JB		 7461/*
7462 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7463 * resume, or other times. This quirk makes sure that's the case for
7464 * affected systems.
7465 */
7466static void quirk_pipea_force (struct drm_device *dev)
7467{
7468 struct drm_i915_private *dev_priv = dev->dev_private;
7469
7470 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7471 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7472}
7473
7474struct intel_quirk {
7475 int device;
7476 int subsystem_vendor;
7477 int subsystem_device;
7478 void (*hook)(struct drm_device *dev);
7479};
7480
7481struct intel_quirk intel_quirks[] = {
7482 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7483 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7484 /* HP Mini needs pipe A force quirk (LP: #322104) */
7485 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7486
7487 /* Thinkpad R31 needs pipe A force quirk */
7488 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7489 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7490 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7491
7492 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7493 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7494 /* ThinkPad X40 needs pipe A force quirk */
7495
7496 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7497 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7498
7499 /* 855 & before need to leave pipe A & dpll A up */
7500 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7501 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7502};
7503
7504static void intel_init_quirks(struct drm_device *dev)
7505{
7506 struct pci_dev *d = dev->pdev;
7507 int i;
7508
7509 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7510 struct intel_quirk *q = &intel_quirks[i];
7511
7512 if (d->device == q->device &&
7513 (d->subsystem_vendor == q->subsystem_vendor ||
7514 q->subsystem_vendor == PCI_ANY_ID) &&
7515 (d->subsystem_device == q->subsystem_device ||
7516 q->subsystem_device == PCI_ANY_ID))
7517 q->hook(dev);
7518 }
7519}
7520
9cce37f4
JB		 7521/* Disable the VGA plane that we never use */
7522static void i915_disable_vga(struct drm_device *dev)
7523{
7524 struct drm_i915_private *dev_priv = dev->dev_private;
7525 u8 sr1;
7526 u32 vga_reg;
7527
7528 if (HAS_PCH_SPLIT(dev))
7529 vga_reg = CPU_VGACNTRL;
7530 else
7531 vga_reg = VGACNTRL;
7532
7533 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7534 outb(1, VGA_SR_INDEX);
7535 sr1 = inb(VGA_SR_DATA);
7536 outb(sr1 | 1<<5, VGA_SR_DATA);
7537 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7538 udelay(300);
7539
7540 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7541 POSTING_READ(vga_reg);
7542}
7543
79e53945
JB		 7544void intel_modeset_init(struct drm_device *dev)
7545{
652c393a 7546 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 7547 int i;
7548
7549 drm_mode_config_init(dev);
7550
7551 dev->mode_config.min_width = 0;
7552 dev->mode_config.min_height = 0;
7553
7554 dev->mode_config.funcs = (void *)&intel_mode_funcs;
7555
b690e96c
JB		 7556 intel_init_quirks(dev);
7557
e70236a8
JB		 7558 intel_init_display(dev);
7559
a6c45cf0
CW		 7560 if (IS_GEN2(dev)) {
7561 dev->mode_config.max_width = 2048;
7562 dev->mode_config.max_height = 2048;
7563 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 7564 dev->mode_config.max_width = 4096;
7565 dev->mode_config.max_height = 4096;
79e53945 7566 } else {
a6c45cf0
CW		 7567 dev->mode_config.max_width = 8192;
7568 dev->mode_config.max_height = 8192;
79e53945 7569 }
35c3047a 7570 dev->mode_config.fb_base = dev->agp->base;
79e53945 7571
28c97730 7572 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 7573 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 7574
a3524f1b 7575 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945
JB		 7576 intel_crtc_init(dev, i);
7577 }
7578
2c7111db
CW		 7579 /* Just disable it once at startup */
7580 i915_disable_vga(dev);
79e53945 7581 intel_setup_outputs(dev);
652c393a 7582
0cdab21f 7583 intel_enable_clock_gating(dev);
652c393a 7584
7648fa99 7585 if (IS_IRONLAKE_M(dev)) {
f97108d1 7586 ironlake_enable_drps(dev);
7648fa99
JB		 7587 intel_init_emon(dev);
7588 }
f97108d1 7589
3b8d8d91
JB		 7590 if (IS_GEN6(dev))
7591 gen6_enable_rps(dev_priv);
7592
652c393a
JB		 7593 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7594 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7595 (unsigned long)dev);
2c7111db
CW		 7596}
7597
7598void intel_modeset_gem_init(struct drm_device *dev)
7599{
7600 if (IS_IRONLAKE_M(dev))
7601 ironlake_enable_rc6(dev);
02e792fb
DV		 7602
7603 intel_setup_overlay(dev);
79e53945
JB		 7604}
7605
7606void intel_modeset_cleanup(struct drm_device *dev)
7607{
652c393a
JB		 7608 struct drm_i915_private *dev_priv = dev->dev_private;
7609 struct drm_crtc *crtc;
7610 struct intel_crtc *intel_crtc;
7611
f87ea761 7612 drm_kms_helper_poll_fini(dev);
652c393a
JB		 7613 mutex_lock(&dev->struct_mutex);
7614
723bfd70
JB		 7615 intel_unregister_dsm_handler();
7616
7617
652c393a
JB		 7618 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7619 /* Skip inactive CRTCs */
7620 if (!crtc->fb)
7621 continue;
7622
7623 intel_crtc = to_intel_crtc(crtc);
3dec0095 7624 intel_increase_pllclock(crtc);
652c393a
JB		 7625 }
7626
e70236a8
JB		 7627 if (dev_priv->display.disable_fbc)
7628 dev_priv->display.disable_fbc(dev);
7629
f97108d1
JB		 7630 if (IS_IRONLAKE_M(dev))
7631 ironlake_disable_drps(dev);
3b8d8d91
JB		 7632 if (IS_GEN6(dev))
7633 gen6_disable_rps(dev);
f97108d1 7634
d5bb081b
JB		 7635 if (IS_IRONLAKE_M(dev))
7636 ironlake_disable_rc6(dev);
0cdab21f 7637
69341a5e
KH		 7638 mutex_unlock(&dev->struct_mutex);
7639
6c0d9350
DV		 7640 /* Disable the irq before mode object teardown, for the irq might
7641 * enqueue unpin/hotplug work. */
7642 drm_irq_uninstall(dev);
7643 cancel_work_sync(&dev_priv->hotplug_work);
7644
3dec0095
DV		 7645 /* Shut off idle work before the crtcs get freed. */
7646 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7647 intel_crtc = to_intel_crtc(crtc);
7648 del_timer_sync(&intel_crtc->idle_timer);
7649 }
7650 del_timer_sync(&dev_priv->idle_timer);
7651 cancel_work_sync(&dev_priv->idle_work);
7652
79e53945
JB		 7653 drm_mode_config_cleanup(dev);
7654}
7655
f1c79df3
ZW		 7656/*
7657 * Return which encoder is currently attached for connector.
7658 */
df0e9248 7659struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 7660{
df0e9248
CW		 7661 return &intel_attached_encoder(connector)->base;
7662}
f1c79df3 7663
df0e9248
CW		 7664void intel_connector_attach_encoder(struct intel_connector *connector,
7665 struct intel_encoder *encoder)
7666{
7667 connector->encoder = encoder;
7668 drm_mode_connector_attach_encoder(&connector->base,
7669 &encoder->base);
79e53945 7670}
28d52043
DA		 7671
7672/*
7673 * set vga decode state - true == enable VGA decode
7674 */
7675int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7676{
7677 struct drm_i915_private *dev_priv = dev->dev_private;
7678 u16 gmch_ctrl;
7679
7680 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7681 if (state)
7682 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7683 else
7684 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7685 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7686 return 0;
7687}
c4a1d9e4
CW		 7688
7689#ifdef CONFIG_DEBUG_FS
7690#include <linux/seq_file.h>
7691
7692struct intel_display_error_state {
7693 struct intel_cursor_error_state {
7694 u32 control;
7695 u32 position;
7696 u32 base;
7697 u32 size;
7698 } cursor[2];
7699
7700 struct intel_pipe_error_state {
7701 u32 conf;
7702 u32 source;
7703
7704 u32 htotal;
7705 u32 hblank;
7706 u32 hsync;
7707 u32 vtotal;
7708 u32 vblank;
7709 u32 vsync;
7710 } pipe[2];
7711
7712 struct intel_plane_error_state {
7713 u32 control;
7714 u32 stride;
7715 u32 size;
7716 u32 pos;
7717 u32 addr;
7718 u32 surface;
7719 u32 tile_offset;
7720 } plane[2];
7721};
7722
7723struct intel_display_error_state *
7724intel_display_capture_error_state(struct drm_device *dev)
7725{
7726 drm_i915_private_t *dev_priv = dev->dev_private;
7727 struct intel_display_error_state *error;
7728 int i;
7729
7730 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7731 if (error == NULL)
7732 return NULL;
7733
7734 for (i = 0; i < 2; i++) {
7735 error->cursor[i].control = I915_READ(CURCNTR(i));
7736 error->cursor[i].position = I915_READ(CURPOS(i));
7737 error->cursor[i].base = I915_READ(CURBASE(i));
7738
7739 error->plane[i].control = I915_READ(DSPCNTR(i));
7740 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7741 error->plane[i].size = I915_READ(DSPSIZE(i));
7742 error->plane[i].pos= I915_READ(DSPPOS(i));
7743 error->plane[i].addr = I915_READ(DSPADDR(i));
7744 if (INTEL_INFO(dev)->gen >= 4) {
7745 error->plane[i].surface = I915_READ(DSPSURF(i));
7746 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7747 }
7748
7749 error->pipe[i].conf = I915_READ(PIPECONF(i));
7750 error->pipe[i].source = I915_READ(PIPESRC(i));
7751 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7752 error->pipe[i].hblank = I915_READ(HBLANK(i));
7753 error->pipe[i].hsync = I915_READ(HSYNC(i));
7754 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7755 error->pipe[i].vblank = I915_READ(VBLANK(i));
7756 error->pipe[i].vsync = I915_READ(VSYNC(i));
7757 }
7758
7759 return error;
7760}
7761
7762void
7763intel_display_print_error_state(struct seq_file *m,
7764 struct drm_device *dev,
7765 struct intel_display_error_state *error)
7766{
7767 int i;
7768
7769 for (i = 0; i < 2; i++) {
7770 seq_printf(m, "Pipe [%d]:\n", i);
7771 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7772 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7773 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7774 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7775 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7776 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7777 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7778 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7779
7780 seq_printf(m, "Plane [%d]:\n", i);
7781 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7782 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7783 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7784 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7785 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7786 if (INTEL_INFO(dev)->gen >= 4) {
7787 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7788 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7789 }
7790
7791 seq_printf(m, "Cursor [%d]:\n", i);
7792 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7793 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7794 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7795 }
7796}
7797#endif
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