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drm/i915: Disable/restore all sprite planes around modeset
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
d4906093 62};
79e53945 63
2377b741
JB		 64/* FDI */
65#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
d2acd215
DV		 67int
68intel_pch_rawclk(struct drm_device *dev)
69{
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75}
76
021357ac
CW		 77static inline u32 /* units of 100MHz */
78intel_fdi_link_freq(struct drm_device *dev)
79{
8b99e68c
CW		 80 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
021357ac
CW		 85}
86
e4b36699 87static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 98};
99
100static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
e4b36699 111};
273e27ca 112
e4b36699 113static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 137};
138
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
044c7c41 152 },
e4b36699
KP		 153};
154
155static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
044c7c41 179 },
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
044c7c41 193 },
e4b36699
KP		 194};
195
f2b115e6 196static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 199 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
273e27ca 202 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
f2b115e6 211static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 222};
223
273e27ca
EA		 224/* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
b91ad0ec 229static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
b91ad0ec 242static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 253};
254
255static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 266};
267
273e27ca 268/* LVDS 100mhz refclk limits. */
b91ad0ec 269static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
0206e353 277 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 280};
281
282static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
0206e353 290 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 293};
294
a0c4da24
JB		 295static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
75e53986 303 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 306};
307
308static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 319};
320
321static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 324 .n = { .min = 1, .max = 7 },
74a4dd2e 325 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
75e53986 329 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 332};
333
1b894b59
CW		 334static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
2c07245f 336{
b91ad0ec 337 struct drm_device *dev = crtc->dev;
2c07245f 338 const intel_limit_t *limit;
b91ad0ec
ZW		 339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 341 if (intel_is_dual_link_lvds(dev)) {
1b894b59 342 if (refclk == 100000)
b91ad0ec
ZW		 343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
c6bb3538 352 } else
b91ad0ec 353 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 354
355 return limit;
356}
357
044c7c41
ML		 358static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359{
360 struct drm_device *dev = crtc->dev;
044c7c41
ML		 361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 364 if (intel_is_dual_link_lvds(dev))
e4b36699 365 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 366 else
e4b36699 367 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 370 limit = &intel_limits_g4x_hdmi;
044c7c41 371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 372 limit = &intel_limits_g4x_sdvo;
044c7c41 373 } else /* The option is for other outputs */
e4b36699 374 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 375
376 return limit;
377}
378
1b894b59 379static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 380{
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
bad720ff 384 if (HAS_PCH_SPLIT(dev))
1b894b59 385 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 386 else if (IS_G4X(dev)) {
044c7c41 387 limit = intel_g4x_limit(crtc);
f2b115e6 388 } else if (IS_PINEVIEW(dev)) {
2177832f 389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 390 limit = &intel_limits_pineview_lvds;
2177832f 391 else
f2b115e6 392 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 407 limit = &intel_limits_i8xx_lvds;
79e53945 408 else
e4b36699 409 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 410 }
411 return limit;
412}
413
f2b115e6
AJ		 414/* m1 is reserved as 0 in Pineview, n is a ring counter */
415static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 416{
2177832f
SL		 417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421}
422
7429e9d4
DV		 423static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424{
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426}
427
ac58c3f0 428static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 429{
7429e9d4 430 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434}
435
79e53945
JB		 436/**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
4ef69c7a 439bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 440{
4ef69c7a 441 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 442 struct intel_encoder *encoder;
443
6c2b7c12
DV		 444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
4ef69c7a
CW		 446 return true;
447
448 return false;
79e53945
JB		 449}
450
7c04d1d9 451#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 452/**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
1b894b59
CW		 457static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
79e53945 460{
79e53945 461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 462 INTELPllInvalid("p1 out of range\n");
79e53945 463 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 464 INTELPllInvalid("p out of range\n");
79e53945 465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 466 INTELPllInvalid("m2 out of range\n");
79e53945 467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 468 INTELPllInvalid("m1 out of range\n");
f2b115e6 469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 470 INTELPllInvalid("m1 <= m2\n");
79e53945 471 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 472 INTELPllInvalid("m out of range\n");
79e53945 473 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 474 INTELPllInvalid("n out of range\n");
79e53945 475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 476 INTELPllInvalid("vco out of range\n");
79e53945
JB		 477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 481 INTELPllInvalid("dot out of range\n");
79e53945
JB		 482
483 return true;
484}
485
d4906093 486static bool
ee9300bb 487i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
ac58c3f0
DV		 490{
491 struct drm_device *dev = crtc->dev;
492 intel_clock_t clock;
493 int err = target;
494
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
496 /*
497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
500 */
501 if (intel_is_dual_link_lvds(dev))
502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
512 memset(best_clock, 0, sizeof(*best_clock));
513
514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 518 if (clock.m2 >= clock.m1)
ac58c3f0
DV		 519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
524 int this_err;
d4906093 525
ac58c3f0
DV		 526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545}
546
547static bool
ee9300bb
DV		 548pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
79e53945
JB		 551{
552 struct drm_device *dev = crtc->dev;
79e53945 553 intel_clock_t clock;
79e53945
JB		 554 int err = target;
555
a210b028 556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 557 /*
a210b028
DV		 558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
79e53945 561 */
1974cad0 562 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
0206e353 573 memset(best_clock, 0, sizeof(*best_clock));
79e53945 574
42158660
ZY		 575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 583 int this_err;
584
ac58c3f0 585 pineview_clock(refclk, &clock);
1b894b59
CW		 586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
79e53945 588 continue;
cec2f356
SP		 589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
79e53945
JB		 592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604}
605
d4906093 606static bool
ee9300bb
DV		 607g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
d4906093
ML		 610{
611 struct drm_device *dev = crtc->dev;
d4906093
ML		 612 intel_clock_t clock;
613 int max_n;
614 bool found;
6ba770dc
AJ		 615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 620 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
f77f13e2 633 /* based on hardware requirement, prefer smaller n to precision */
d4906093 634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 635 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
ac58c3f0 644 i9xx_clock(refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
d4906093 647 continue;
1b894b59
CW		 648
649 this_err = abs(clock.dot - target);
d4906093
ML		 650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
2c07245f
ZW		 660 return found;
661}
662
a0c4da24 663static bool
ee9300bb
DV		 664vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
a0c4da24
JB		 667{
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
af447bd3 674 flag = 0;
a0c4da24
JB		 675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730}
a4fc5ed6 731
a5c961d1
PZ		 732enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734{
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
3b117c8f 738 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 739}
740
a928d536
PZ		 741static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742{
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750}
751
9d0498a2
JB		 752/**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 761{
9d0498a2 762 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 763 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 764
a928d536
PZ		 765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
300387c0
CW		 770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
9d0498a2 786 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
9d0498a2
JB		 790 DRM_DEBUG_KMS("vblank wait timed out\n");
791}
792
ab7ad7f6
KP		 793/*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
ab7ad7f6
KP		 802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
58e10eb9 808 *
9d0498a2 809 */
58e10eb9 810void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 811{
812 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
ab7ad7f6
KP		 815
816 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 817 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 818
819 /* Wait for the Pipe State to go off */
58e10eb9
CW		 820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
284637d9 822 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 823 } else {
837ba00f 824 u32 last_line, line_mask;
58e10eb9 825 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
837ba00f
PZ		 828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
ab7ad7f6
KP		 833 /* Wait for the display line to settle */
834 do {
837ba00f 835 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 836 mdelay(5);
837ba00f 837 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
284637d9 840 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 841 }
79e53945
JB		 842}
843
b0ea7d37
DL		 844/*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853{
854 u32 bit;
855
c36346e3
DL		 856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
b0ea7d37
DL		 884 }
885
886 return I915_READ(SDEISR) & bit;
887}
888
b24e7179
JB		 889static const char *state_string(bool enabled)
890{
891 return enabled ? "on" : "off";
892}
893
894/* Only for pre-ILK configs */
895static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897{
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908}
909#define assert_pll_enabled(d, p) assert_pll(d, p, true)
910#define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
040484af
JB		 912/* For ILK+ */
913static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 914 struct intel_pch_pll *pll,
915 struct intel_crtc *crtc,
916 bool state)
040484af 917{
040484af
JB		 918 u32 val;
919 bool cur_state;
920
9d82aa17
ED		 921 if (HAS_PCH_LPT(dev_priv->dev)) {
922 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
923 return;
924 }
925
92b27b08
CW		 926 if (WARN (!pll,
927 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 928 return;
ee7b9f93 929
92b27b08
CW		 930 val = I915_READ(pll->pll_reg);
931 cur_state = !!(val & DPLL_VCO_ENABLE);
932 WARN(cur_state != state,
933 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
934 pll->pll_reg, state_string(state), state_string(cur_state), val);
935
936 /* Make sure the selected PLL is correctly attached to the transcoder */
937 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 938 u32 pch_dpll;
939
940 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 941 cur_state = pll->pll_reg == _PCH_DPLL_B;
942 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 943 "PLL[%d] not attached to this transcoder %c: %08x\n",
944 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 945 cur_state = !!(val >> (4*crtc->pipe + 3));
946 WARN(cur_state != state,
4bb6f1f3 947 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 948 pll->pll_reg == _PCH_DPLL_B,
949 state_string(state),
4bb6f1f3 950 pipe_name(crtc->pipe),
92b27b08
CW		 951 val);
952 }
d3ccbe86 953 }
040484af 954}
92b27b08
CW		 955#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
956#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 957
958static void assert_fdi_tx(struct drm_i915_private *dev_priv,
959 enum pipe pipe, bool state)
960{
961 int reg;
962 u32 val;
963 bool cur_state;
ad80a810
PZ		 964 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
965 pipe);
040484af 966
affa9354
PZ		 967 if (HAS_DDI(dev_priv->dev)) {
968 /* DDI does not have a specific FDI_TX register */
ad80a810 969 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 970 val = I915_READ(reg);
ad80a810 971 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 972 } else {
973 reg = FDI_TX_CTL(pipe);
974 val = I915_READ(reg);
975 cur_state = !!(val & FDI_TX_ENABLE);
976 }
040484af
JB		 977 WARN(cur_state != state,
978 "FDI TX state assertion failure (expected %s, current %s)\n",
979 state_string(state), state_string(cur_state));
980}
981#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
982#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
983
984static void assert_fdi_rx(struct drm_i915_private *dev_priv,
985 enum pipe pipe, bool state)
986{
987 int reg;
988 u32 val;
989 bool cur_state;
990
d63fa0dc
PZ		 991 reg = FDI_RX_CTL(pipe);
992 val = I915_READ(reg);
993 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 994 WARN(cur_state != state,
995 "FDI RX state assertion failure (expected %s, current %s)\n",
996 state_string(state), state_string(cur_state));
997}
998#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
999#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1000
1001static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe)
1003{
1004 int reg;
1005 u32 val;
1006
1007 /* ILK FDI PLL is always enabled */
1008 if (dev_priv->info->gen == 5)
1009 return;
1010
bf507ef7 1011 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1012 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1013 return;
1014
040484af
JB		 1015 reg = FDI_TX_CTL(pipe);
1016 val = I915_READ(reg);
1017 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1018}
1019
1020static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1021 enum pipe pipe)
1022{
1023 int reg;
1024 u32 val;
1025
1026 reg = FDI_RX_CTL(pipe);
1027 val = I915_READ(reg);
1028 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1029}
1030
ea0760cf
JB		 1031static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1032 enum pipe pipe)
1033{
1034 int pp_reg, lvds_reg;
1035 u32 val;
1036 enum pipe panel_pipe = PIPE_A;
0de3b485 1037 bool locked = true;
ea0760cf
JB		 1038
1039 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1040 pp_reg = PCH_PP_CONTROL;
1041 lvds_reg = PCH_LVDS;
1042 } else {
1043 pp_reg = PP_CONTROL;
1044 lvds_reg = LVDS;
1045 }
1046
1047 val = I915_READ(pp_reg);
1048 if (!(val & PANEL_POWER_ON) ||
1049 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1050 locked = false;
1051
1052 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1053 panel_pipe = PIPE_B;
1054
1055 WARN(panel_pipe == pipe && locked,
1056 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1057 pipe_name(pipe));
ea0760cf
JB		 1058}
1059
b840d907
JB		 1060void assert_pipe(struct drm_i915_private *dev_priv,
1061 enum pipe pipe, bool state)
b24e7179
JB		 1062{
1063 int reg;
1064 u32 val;
63d7bbe9 1065 bool cur_state;
702e7a56
PZ		 1066 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1067 pipe);
b24e7179 1068
8e636784
DV		 1069 /* if we need the pipe A quirk it must be always on */
1070 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1071 state = true;
1072
b97186f0
PZ		 1073 if (!intel_display_power_enabled(dev_priv->dev,
1074 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1075 cur_state = false;
1076 } else {
1077 reg = PIPECONF(cpu_transcoder);
1078 val = I915_READ(reg);
1079 cur_state = !!(val & PIPECONF_ENABLE);
1080 }
1081
63d7bbe9
JB		 1082 WARN(cur_state != state,
1083 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1084 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1085}
1086
931872fc
CW		 1087static void assert_plane(struct drm_i915_private *dev_priv,
1088 enum plane plane, bool state)
b24e7179
JB		 1089{
1090 int reg;
1091 u32 val;
931872fc 1092 bool cur_state;
b24e7179
JB		 1093
1094 reg = DSPCNTR(plane);
1095 val = I915_READ(reg);
931872fc
CW		 1096 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1097 WARN(cur_state != state,
1098 "plane %c assertion failure (expected %s, current %s)\n",
1099 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1100}
1101
931872fc
CW		 1102#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1103#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1104
b24e7179
JB		 1105static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1106 enum pipe pipe)
1107{
1108 int reg, i;
1109 u32 val;
1110 int cur_pipe;
1111
19ec1358 1112 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1113 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1114 reg = DSPCNTR(pipe);
1115 val = I915_READ(reg);
1116 WARN((val & DISPLAY_PLANE_ENABLE),
1117 "plane %c assertion failure, should be disabled but not\n",
1118 plane_name(pipe));
19ec1358 1119 return;
28c05794 1120 }
19ec1358 1121
b24e7179
JB		 1122 /* Need to check both planes against the pipe */
1123 for (i = 0; i < 2; i++) {
1124 reg = DSPCNTR(i);
1125 val = I915_READ(reg);
1126 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1127 DISPPLANE_SEL_PIPE_SHIFT;
1128 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1129 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1130 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1131 }
1132}
1133
19332d7a
JB		 1134static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1135 enum pipe pipe)
1136{
1137 int reg, i;
1138 u32 val;
1139
1140 if (!IS_VALLEYVIEW(dev_priv->dev))
1141 return;
1142
1143 /* Need to check both planes against the pipe */
1144 for (i = 0; i < dev_priv->num_plane; i++) {
1145 reg = SPCNTR(pipe, i);
1146 val = I915_READ(reg);
1147 WARN((val & SP_ENABLE),
06da8da2
VS		 1148 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1149 sprite_name(pipe, i), pipe_name(pipe));
19332d7a
JB		 1150 }
1151}
1152
92f2584a
JB		 1153static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1154{
1155 u32 val;
1156 bool enabled;
1157
9d82aa17
ED		 1158 if (HAS_PCH_LPT(dev_priv->dev)) {
1159 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1160 return;
1161 }
1162
92f2584a
JB		 1163 val = I915_READ(PCH_DREF_CONTROL);
1164 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1165 DREF_SUPERSPREAD_SOURCE_MASK));
1166 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1167}
1168
ab9412ba
DV		 1169static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
92f2584a
JB		 1171{
1172 int reg;
1173 u32 val;
1174 bool enabled;
1175
ab9412ba 1176 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1177 val = I915_READ(reg);
1178 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1179 WARN(enabled,
1180 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1181 pipe_name(pipe));
92f2584a
JB		 1182}
1183
4e634389
KP		 1184static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1186{
1187 if ((val & DP_PORT_EN) == 0)
1188 return false;
1189
1190 if (HAS_PCH_CPT(dev_priv->dev)) {
1191 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1192 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1193 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1194 return false;
1195 } else {
1196 if ((val & DP_PIPE_MASK) != (pipe << 30))
1197 return false;
1198 }
1199 return true;
1200}
1201
1519b995
KP		 1202static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1203 enum pipe pipe, u32 val)
1204{
dc0fa718 1205 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1206 return false;
1207
1208 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1209 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1210 return false;
1211 } else {
dc0fa718 1212 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1213 return false;
1214 }
1215 return true;
1216}
1217
1218static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, u32 val)
1220{
1221 if ((val & LVDS_PORT_EN) == 0)
1222 return false;
1223
1224 if (HAS_PCH_CPT(dev_priv->dev)) {
1225 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1226 return false;
1227 } else {
1228 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1229 return false;
1230 }
1231 return true;
1232}
1233
1234static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1235 enum pipe pipe, u32 val)
1236{
1237 if ((val & ADPA_DAC_ENABLE) == 0)
1238 return false;
1239 if (HAS_PCH_CPT(dev_priv->dev)) {
1240 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1241 return false;
1242 } else {
1243 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1244 return false;
1245 }
1246 return true;
1247}
1248
291906f1 1249static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1250 enum pipe pipe, int reg, u32 port_sel)
291906f1 1251{
47a05eca 1252 u32 val = I915_READ(reg);
4e634389 1253 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1254 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1255 reg, pipe_name(pipe));
de9a35ab 1256
75c5da27
DV		 1257 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1258 && (val & DP_PIPEB_SELECT),
de9a35ab 1259 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1260}
1261
1262static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe, int reg)
1264{
47a05eca 1265 u32 val = I915_READ(reg);
b70ad586 1266 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1267 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1268 reg, pipe_name(pipe));
de9a35ab 1269
dc0fa718 1270 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1271 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1272 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1273}
1274
1275static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1276 enum pipe pipe)
1277{
1278 int reg;
1279 u32 val;
291906f1 1280
f0575e92
KP		 1281 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1282 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1283 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1284
1285 reg = PCH_ADPA;
1286 val = I915_READ(reg);
b70ad586 1287 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1288 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1289 pipe_name(pipe));
291906f1
JB		 1290
1291 reg = PCH_LVDS;
1292 val = I915_READ(reg);
b70ad586 1293 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1294 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1295 pipe_name(pipe));
291906f1 1296
e2debe91
PZ		 1297 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1298 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1299 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1300}
1301
63d7bbe9
JB		 1302/**
1303 * intel_enable_pll - enable a PLL
1304 * @dev_priv: i915 private structure
1305 * @pipe: pipe PLL to enable
1306 *
1307 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1308 * make sure the PLL reg is writable first though, since the panel write
1309 * protect mechanism may be enabled.
1310 *
1311 * Note! This is for pre-ILK only.
7434a255
TR		 1312 *
1313 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1314 */
1315static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1316{
1317 int reg;
1318 u32 val;
1319
58c6eaa2
DV		 1320 assert_pipe_disabled(dev_priv, pipe);
1321
63d7bbe9 1322 /* No really, not for ILK+ */
a0c4da24 1323 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1324
1325 /* PLL is protected by panel, make sure we can write it */
1326 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1327 assert_panel_unlocked(dev_priv, pipe);
1328
1329 reg = DPLL(pipe);
1330 val = I915_READ(reg);
1331 val |= DPLL_VCO_ENABLE;
1332
1333 /* We do this three times for luck */
1334 I915_WRITE(reg, val);
1335 POSTING_READ(reg);
1336 udelay(150); /* wait for warmup */
1337 I915_WRITE(reg, val);
1338 POSTING_READ(reg);
1339 udelay(150); /* wait for warmup */
1340 I915_WRITE(reg, val);
1341 POSTING_READ(reg);
1342 udelay(150); /* wait for warmup */
1343}
1344
1345/**
1346 * intel_disable_pll - disable a PLL
1347 * @dev_priv: i915 private structure
1348 * @pipe: pipe PLL to disable
1349 *
1350 * Disable the PLL for @pipe, making sure the pipe is off first.
1351 *
1352 * Note! This is for pre-ILK only.
1353 */
1354static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1355{
1356 int reg;
1357 u32 val;
1358
1359 /* Don't disable pipe A or pipe A PLLs if needed */
1360 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1361 return;
1362
1363 /* Make sure the pipe isn't still relying on us */
1364 assert_pipe_disabled(dev_priv, pipe);
1365
1366 reg = DPLL(pipe);
1367 val = I915_READ(reg);
1368 val &= ~DPLL_VCO_ENABLE;
1369 I915_WRITE(reg, val);
1370 POSTING_READ(reg);
1371}
1372
89b667f8
JB		 1373void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1374{
1375 u32 port_mask;
1376
1377 if (!port)
1378 port_mask = DPLL_PORTB_READY_MASK;
1379 else
1380 port_mask = DPLL_PORTC_READY_MASK;
1381
1382 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1383 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1384 'B' + port, I915_READ(DPLL(0)));
1385}
1386
92f2584a 1387/**
b6b4e185 1388 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1389 * @dev_priv: i915 private structure
1390 * @pipe: pipe PLL to enable
1391 *
1392 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1393 * drives the transcoder clock.
1394 */
b6b4e185 1395static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1396{
ee7b9f93 1397 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1398 struct intel_pch_pll *pll;
92f2584a
JB		 1399 int reg;
1400 u32 val;
1401
48da64a8 1402 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1403 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1404 pll = intel_crtc->pch_pll;
1405 if (pll == NULL)
1406 return;
1407
1408 if (WARN_ON(pll->refcount == 0))
1409 return;
ee7b9f93
JB		 1410
1411 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1412 pll->pll_reg, pll->active, pll->on,
1413 intel_crtc->base.base.id);
92f2584a
JB		 1414
1415 /* PCH refclock must be enabled first */
1416 assert_pch_refclk_enabled(dev_priv);
1417
ee7b9f93 1418 if (pll->active++ && pll->on) {
92b27b08 1419 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1420 return;
1421 }
1422
1423 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1424
1425 reg = pll->pll_reg;
92f2584a
JB		 1426 val = I915_READ(reg);
1427 val |= DPLL_VCO_ENABLE;
1428 I915_WRITE(reg, val);
1429 POSTING_READ(reg);
1430 udelay(200);
ee7b9f93
JB		 1431
1432 pll->on = true;
92f2584a
JB		 1433}
1434
ee7b9f93 1435static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1436{
ee7b9f93
JB		 1437 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1438 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1439 int reg;
ee7b9f93 1440 u32 val;
4c609cb8 1441
92f2584a
JB		 1442 /* PCH only available on ILK+ */
1443 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1444 if (pll == NULL)
1445 return;
92f2584a 1446
48da64a8
CW		 1447 if (WARN_ON(pll->refcount == 0))
1448 return;
7a419866 1449
ee7b9f93
JB		 1450 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1451 pll->pll_reg, pll->active, pll->on,
1452 intel_crtc->base.base.id);
7a419866 1453
48da64a8 1454 if (WARN_ON(pll->active == 0)) {
92b27b08 1455 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1456 return;
1457 }
1458
ee7b9f93 1459 if (--pll->active) {
92b27b08 1460 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1461 return;
ee7b9f93
JB		 1462 }
1463
1464 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1465
1466 /* Make sure transcoder isn't still depending on us */
ab9412ba 1467 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1468
ee7b9f93 1469 reg = pll->pll_reg;
92f2584a
JB		 1470 val = I915_READ(reg);
1471 val &= ~DPLL_VCO_ENABLE;
1472 I915_WRITE(reg, val);
1473 POSTING_READ(reg);
1474 udelay(200);
ee7b9f93
JB		 1475
1476 pll->on = false;
92f2584a
JB		 1477}
1478
b8a4f404
PZ		 1479static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1480 enum pipe pipe)
040484af 1481{
23670b32 1482 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1483 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1484 uint32_t reg, val, pipeconf_val;
040484af
JB		 1485
1486 /* PCH only available on ILK+ */
1487 BUG_ON(dev_priv->info->gen < 5);
1488
1489 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1490 assert_pch_pll_enabled(dev_priv,
1491 to_intel_crtc(crtc)->pch_pll,
1492 to_intel_crtc(crtc));
040484af
JB		 1493
1494 /* FDI must be feeding us bits for PCH ports */
1495 assert_fdi_tx_enabled(dev_priv, pipe);
1496 assert_fdi_rx_enabled(dev_priv, pipe);
1497
23670b32
DV		 1498 if (HAS_PCH_CPT(dev)) {
1499 /* Workaround: Set the timing override bit before enabling the
1500 * pch transcoder. */
1501 reg = TRANS_CHICKEN2(pipe);
1502 val = I915_READ(reg);
1503 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1504 I915_WRITE(reg, val);
59c859d6 1505 }
23670b32 1506
ab9412ba 1507 reg = PCH_TRANSCONF(pipe);
040484af 1508 val = I915_READ(reg);
5f7f726d 1509 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1510
1511 if (HAS_PCH_IBX(dev_priv->dev)) {
1512 /*
1513 * make the BPC in transcoder be consistent with
1514 * that in pipeconf reg.
1515 */
dfd07d72
DV		 1516 val &= ~PIPECONF_BPC_MASK;
1517 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1518 }
5f7f726d
PZ		 1519
1520 val &= ~TRANS_INTERLACE_MASK;
1521 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1522 if (HAS_PCH_IBX(dev_priv->dev) &&
1523 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1524 val |= TRANS_LEGACY_INTERLACED_ILK;
1525 else
1526 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1527 else
1528 val |= TRANS_PROGRESSIVE;
1529
040484af
JB		 1530 I915_WRITE(reg, val | TRANS_ENABLE);
1531 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1532 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1533}
1534
8fb033d7 1535static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1536 enum transcoder cpu_transcoder)
040484af 1537{
8fb033d7 1538 u32 val, pipeconf_val;
8fb033d7
PZ		 1539
1540 /* PCH only available on ILK+ */
1541 BUG_ON(dev_priv->info->gen < 5);
1542
8fb033d7 1543 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1544 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1545 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1546
223a6fdf
PZ		 1547 /* Workaround: set timing override bit. */
1548 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1549 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1550 I915_WRITE(_TRANSA_CHICKEN2, val);
1551
25f3ef11 1552 val = TRANS_ENABLE;
937bb610 1553 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1554
9a76b1c6
PZ		 1555 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1556 PIPECONF_INTERLACED_ILK)
a35f2679 1557 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1558 else
1559 val |= TRANS_PROGRESSIVE;
1560
ab9412ba
DV		 1561 I915_WRITE(LPT_TRANSCONF, val);
1562 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1563 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1564}
1565
b8a4f404
PZ		 1566static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1567 enum pipe pipe)
040484af 1568{
23670b32
DV		 1569 struct drm_device *dev = dev_priv->dev;
1570 uint32_t reg, val;
040484af
JB		 1571
1572 /* FDI relies on the transcoder */
1573 assert_fdi_tx_disabled(dev_priv, pipe);
1574 assert_fdi_rx_disabled(dev_priv, pipe);
1575
291906f1
JB		 1576 /* Ports must be off as well */
1577 assert_pch_ports_disabled(dev_priv, pipe);
1578
ab9412ba 1579 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1580 val = I915_READ(reg);
1581 val &= ~TRANS_ENABLE;
1582 I915_WRITE(reg, val);
1583 /* wait for PCH transcoder off, transcoder state */
1584 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1585 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1586
1587 if (!HAS_PCH_IBX(dev)) {
1588 /* Workaround: Clear the timing override chicken bit again. */
1589 reg = TRANS_CHICKEN2(pipe);
1590 val = I915_READ(reg);
1591 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1592 I915_WRITE(reg, val);
1593 }
040484af
JB		 1594}
1595
ab4d966c 1596static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1597{
8fb033d7
PZ		 1598 u32 val;
1599
ab9412ba 1600 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1601 val &= ~TRANS_ENABLE;
ab9412ba 1602 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1603 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1604 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1605 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1606
1607 /* Workaround: clear timing override bit. */
1608 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1609 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1610 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1611}
1612
b24e7179 1613/**
309cfea8 1614 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1615 * @dev_priv: i915 private structure
1616 * @pipe: pipe to enable
040484af 1617 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1618 *
1619 * Enable @pipe, making sure that various hardware specific requirements
1620 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1621 *
1622 * @pipe should be %PIPE_A or %PIPE_B.
1623 *
1624 * Will wait until the pipe is actually running (i.e. first vblank) before
1625 * returning.
1626 */
040484af
JB		 1627static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1628 bool pch_port)
b24e7179 1629{
702e7a56
PZ		 1630 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1631 pipe);
1a240d4d 1632 enum pipe pch_transcoder;
b24e7179
JB		 1633 int reg;
1634 u32 val;
1635
58c6eaa2
DV		 1636 assert_planes_disabled(dev_priv, pipe);
1637 assert_sprites_disabled(dev_priv, pipe);
1638
681e5811 1639 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1640 pch_transcoder = TRANSCODER_A;
1641 else
1642 pch_transcoder = pipe;
1643
b24e7179
JB		 1644 /*
1645 * A pipe without a PLL won't actually be able to drive bits from
1646 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1647 * need the check.
1648 */
1649 if (!HAS_PCH_SPLIT(dev_priv->dev))
1650 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1651 else {
1652 if (pch_port) {
1653 /* if driving the PCH, we need FDI enabled */
cc391bbb 1654 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1655 assert_fdi_tx_pll_enabled(dev_priv,
1656 (enum pipe) cpu_transcoder);
040484af
JB		 1657 }
1658 /* FIXME: assert CPU port conditions for SNB+ */
1659 }
b24e7179 1660
702e7a56 1661 reg = PIPECONF(cpu_transcoder);
b24e7179 1662 val = I915_READ(reg);
00d70b15
CW		 1663 if (val & PIPECONF_ENABLE)
1664 return;
1665
1666 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1667 intel_wait_for_vblank(dev_priv->dev, pipe);
1668}
1669
1670/**
309cfea8 1671 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1672 * @dev_priv: i915 private structure
1673 * @pipe: pipe to disable
1674 *
1675 * Disable @pipe, making sure that various hardware specific requirements
1676 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1677 *
1678 * @pipe should be %PIPE_A or %PIPE_B.
1679 *
1680 * Will wait until the pipe has shut down before returning.
1681 */
1682static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1683 enum pipe pipe)
1684{
702e7a56
PZ		 1685 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1686 pipe);
b24e7179
JB		 1687 int reg;
1688 u32 val;
1689
1690 /*
1691 * Make sure planes won't keep trying to pump pixels to us,
1692 * or we might hang the display.
1693 */
1694 assert_planes_disabled(dev_priv, pipe);
19332d7a 1695 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1696
1697 /* Don't disable pipe A or pipe A PLLs if needed */
1698 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1699 return;
1700
702e7a56 1701 reg = PIPECONF(cpu_transcoder);
b24e7179 1702 val = I915_READ(reg);
00d70b15
CW		 1703 if ((val & PIPECONF_ENABLE) == 0)
1704 return;
1705
1706 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1707 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1708}
1709
d74362c9
KP		 1710/*
1711 * Plane regs are double buffered, going from enabled->disabled needs a
1712 * trigger in order to latch. The display address reg provides this.
1713 */
6f1d69b0 1714void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1715 enum plane plane)
1716{
14f86147
DL		 1717 if (dev_priv->info->gen >= 4)
1718 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1719 else
1720 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1721}
1722
b24e7179
JB		 1723/**
1724 * intel_enable_plane - enable a display plane on a given pipe
1725 * @dev_priv: i915 private structure
1726 * @plane: plane to enable
1727 * @pipe: pipe being fed
1728 *
1729 * Enable @plane on @pipe, making sure that @pipe is running first.
1730 */
1731static void intel_enable_plane(struct drm_i915_private *dev_priv,
1732 enum plane plane, enum pipe pipe)
1733{
1734 int reg;
1735 u32 val;
1736
1737 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1738 assert_pipe_enabled(dev_priv, pipe);
1739
1740 reg = DSPCNTR(plane);
1741 val = I915_READ(reg);
00d70b15
CW		 1742 if (val & DISPLAY_PLANE_ENABLE)
1743 return;
1744
1745 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1746 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1747 intel_wait_for_vblank(dev_priv->dev, pipe);
1748}
1749
b24e7179
JB		 1750/**
1751 * intel_disable_plane - disable a display plane
1752 * @dev_priv: i915 private structure
1753 * @plane: plane to disable
1754 * @pipe: pipe consuming the data
1755 *
1756 * Disable @plane; should be an independent operation.
1757 */
1758static void intel_disable_plane(struct drm_i915_private *dev_priv,
1759 enum plane plane, enum pipe pipe)
1760{
1761 int reg;
1762 u32 val;
1763
1764 reg = DSPCNTR(plane);
1765 val = I915_READ(reg);
00d70b15
CW		 1766 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1767 return;
1768
1769 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1770 intel_flush_display_plane(dev_priv, plane);
1771 intel_wait_for_vblank(dev_priv->dev, pipe);
1772}
1773
693db184
CW		 1774static bool need_vtd_wa(struct drm_device *dev)
1775{
1776#ifdef CONFIG_INTEL_IOMMU
1777 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1778 return true;
1779#endif
1780 return false;
1781}
1782
127bd2ac 1783int
48b956c5 1784intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1785 struct drm_i915_gem_object *obj,
919926ae 1786 struct intel_ring_buffer *pipelined)
6b95a207 1787{
ce453d81 1788 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1789 u32 alignment;
1790 int ret;
1791
05394f39 1792 switch (obj->tiling_mode) {
6b95a207 1793 case I915_TILING_NONE:
534843da
CW		 1794 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1795 alignment = 128 * 1024;
a6c45cf0 1796 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1797 alignment = 4 * 1024;
1798 else
1799 alignment = 64 * 1024;
6b95a207
KH		 1800 break;
1801 case I915_TILING_X:
1802 /* pin() will align the object as required by fence */
1803 alignment = 0;
1804 break;
1805 case I915_TILING_Y:
8bb6e959
DV		 1806 /* Despite that we check this in framebuffer_init userspace can
1807 * screw us over and change the tiling after the fact. Only
1808 * pinned buffers can't change their tiling. */
1809 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1810 return -EINVAL;
1811 default:
1812 BUG();
1813 }
1814
693db184
CW		 1815 /* Note that the w/a also requires 64 PTE of padding following the
1816 * bo. We currently fill all unused PTE with the shadow page and so
1817 * we should always have valid PTE following the scanout preventing
1818 * the VT-d warning.
1819 */
1820 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1821 alignment = 256 * 1024;
1822
ce453d81 1823 dev_priv->mm.interruptible = false;
2da3b9b9 1824 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1825 if (ret)
ce453d81 1826 goto err_interruptible;
6b95a207
KH		 1827
1828 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1829 * fence, whereas 965+ only requires a fence if using
1830 * framebuffer compression. For simplicity, we always install
1831 * a fence as the cost is not that onerous.
1832 */
06d98131 1833 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1834 if (ret)
1835 goto err_unpin;
1690e1eb 1836
9a5a53b3 1837 i915_gem_object_pin_fence(obj);
6b95a207 1838
ce453d81 1839 dev_priv->mm.interruptible = true;
6b95a207 1840 return 0;
48b956c5
CW		 1841
1842err_unpin:
1843 i915_gem_object_unpin(obj);
ce453d81
CW		 1844err_interruptible:
1845 dev_priv->mm.interruptible = true;
48b956c5 1846 return ret;
6b95a207
KH		 1847}
1848
1690e1eb
CW		 1849void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1850{
1851 i915_gem_object_unpin_fence(obj);
1852 i915_gem_object_unpin(obj);
1853}
1854
c2c75131
DV		 1855/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1856 * is assumed to be a power-of-two. */
bc752862
CW		 1857unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1858 unsigned int tiling_mode,
1859 unsigned int cpp,
1860 unsigned int pitch)
c2c75131 1861{
bc752862
CW		 1862 if (tiling_mode != I915_TILING_NONE) {
1863 unsigned int tile_rows, tiles;
c2c75131 1864
bc752862
CW		 1865 tile_rows = *y / 8;
1866 *y %= 8;
c2c75131 1867
bc752862
CW		 1868 tiles = *x / (512/cpp);
1869 *x %= 512/cpp;
1870
1871 return tile_rows * pitch * 8 + tiles * 4096;
1872 } else {
1873 unsigned int offset;
1874
1875 offset = *y * pitch + *x * cpp;
1876 *y = 0;
1877 *x = (offset & 4095) / cpp;
1878 return offset & -4096;
1879 }
c2c75131
DV		 1880}
1881
17638cd6
JB		 1882static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1883 int x, int y)
81255565
JB		 1884{
1885 struct drm_device *dev = crtc->dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1888 struct intel_framebuffer *intel_fb;
05394f39 1889 struct drm_i915_gem_object *obj;
81255565 1890 int plane = intel_crtc->plane;
e506a0c6 1891 unsigned long linear_offset;
81255565 1892 u32 dspcntr;
5eddb70b 1893 u32 reg;
81255565
JB		 1894
1895 switch (plane) {
1896 case 0:
1897 case 1:
1898 break;
1899 default:
84f44ce7 1900 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1901 return -EINVAL;
1902 }
1903
1904 intel_fb = to_intel_framebuffer(fb);
1905 obj = intel_fb->obj;
81255565 1906
5eddb70b
CW		 1907 reg = DSPCNTR(plane);
1908 dspcntr = I915_READ(reg);
81255565
JB		 1909 /* Mask out pixel format bits in case we change it */
1910 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1911 switch (fb->pixel_format) {
1912 case DRM_FORMAT_C8:
81255565
JB		 1913 dspcntr |= DISPPLANE_8BPP;
1914 break;
57779d06
VS		 1915 case DRM_FORMAT_XRGB1555:
1916 case DRM_FORMAT_ARGB1555:
1917 dspcntr |= DISPPLANE_BGRX555;
81255565 1918 break;
57779d06
VS		 1919 case DRM_FORMAT_RGB565:
1920 dspcntr |= DISPPLANE_BGRX565;
1921 break;
1922 case DRM_FORMAT_XRGB8888:
1923 case DRM_FORMAT_ARGB8888:
1924 dspcntr |= DISPPLANE_BGRX888;
1925 break;
1926 case DRM_FORMAT_XBGR8888:
1927 case DRM_FORMAT_ABGR8888:
1928 dspcntr |= DISPPLANE_RGBX888;
1929 break;
1930 case DRM_FORMAT_XRGB2101010:
1931 case DRM_FORMAT_ARGB2101010:
1932 dspcntr |= DISPPLANE_BGRX101010;
1933 break;
1934 case DRM_FORMAT_XBGR2101010:
1935 case DRM_FORMAT_ABGR2101010:
1936 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1937 break;
1938 default:
baba133a 1939 BUG();
81255565 1940 }
57779d06 1941
a6c45cf0 1942 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1943 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1944 dspcntr |= DISPPLANE_TILED;
1945 else
1946 dspcntr &= ~DISPPLANE_TILED;
1947 }
1948
5eddb70b 1949 I915_WRITE(reg, dspcntr);
81255565 1950
e506a0c6 1951 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1952
c2c75131
DV		 1953 if (INTEL_INFO(dev)->gen >= 4) {
1954 intel_crtc->dspaddr_offset =
bc752862
CW		 1955 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1956 fb->bits_per_pixel / 8,
1957 fb->pitches[0]);
c2c75131
DV		 1958 linear_offset -= intel_crtc->dspaddr_offset;
1959 } else {
e506a0c6 1960 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1961 }
e506a0c6
DV		 1962
1963 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1964 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1965 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1966 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1967 I915_MODIFY_DISPBASE(DSPSURF(plane),
1968 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1969 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1970 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1971 } else
e506a0c6 1972 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 1973 POSTING_READ(reg);
81255565 1974
17638cd6
JB		 1975 return 0;
1976}
1977
1978static int ironlake_update_plane(struct drm_crtc *crtc,
1979 struct drm_framebuffer *fb, int x, int y)
1980{
1981 struct drm_device *dev = crtc->dev;
1982 struct drm_i915_private *dev_priv = dev->dev_private;
1983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1984 struct intel_framebuffer *intel_fb;
1985 struct drm_i915_gem_object *obj;
1986 int plane = intel_crtc->plane;
e506a0c6 1987 unsigned long linear_offset;
17638cd6
JB		 1988 u32 dspcntr;
1989 u32 reg;
1990
1991 switch (plane) {
1992 case 0:
1993 case 1:
27f8227b 1994 case 2:
17638cd6
JB		 1995 break;
1996 default:
84f44ce7 1997 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 1998 return -EINVAL;
1999 }
2000
2001 intel_fb = to_intel_framebuffer(fb);
2002 obj = intel_fb->obj;
2003
2004 reg = DSPCNTR(plane);
2005 dspcntr = I915_READ(reg);
2006 /* Mask out pixel format bits in case we change it */
2007 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2008 switch (fb->pixel_format) {
2009 case DRM_FORMAT_C8:
17638cd6
JB		 2010 dspcntr |= DISPPLANE_8BPP;
2011 break;
57779d06
VS		 2012 case DRM_FORMAT_RGB565:
2013 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2014 break;
57779d06
VS		 2015 case DRM_FORMAT_XRGB8888:
2016 case DRM_FORMAT_ARGB8888:
2017 dspcntr |= DISPPLANE_BGRX888;
2018 break;
2019 case DRM_FORMAT_XBGR8888:
2020 case DRM_FORMAT_ABGR8888:
2021 dspcntr |= DISPPLANE_RGBX888;
2022 break;
2023 case DRM_FORMAT_XRGB2101010:
2024 case DRM_FORMAT_ARGB2101010:
2025 dspcntr |= DISPPLANE_BGRX101010;
2026 break;
2027 case DRM_FORMAT_XBGR2101010:
2028 case DRM_FORMAT_ABGR2101010:
2029 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2030 break;
2031 default:
baba133a 2032 BUG();
17638cd6
JB		 2033 }
2034
2035 if (obj->tiling_mode != I915_TILING_NONE)
2036 dspcntr |= DISPPLANE_TILED;
2037 else
2038 dspcntr &= ~DISPPLANE_TILED;
2039
2040 /* must disable */
2041 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2042
2043 I915_WRITE(reg, dspcntr);
2044
e506a0c6 2045 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2046 intel_crtc->dspaddr_offset =
bc752862
CW		 2047 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2048 fb->bits_per_pixel / 8,
2049 fb->pitches[0]);
c2c75131 2050 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2051
e506a0c6
DV		 2052 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2053 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2054 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2055 I915_MODIFY_DISPBASE(DSPSURF(plane),
2056 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2057 if (IS_HASWELL(dev)) {
2058 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2059 } else {
2060 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2061 I915_WRITE(DSPLINOFF(plane), linear_offset);
2062 }
17638cd6
JB		 2063 POSTING_READ(reg);
2064
2065 return 0;
2066}
2067
2068/* Assume fb object is pinned & idle & fenced and just update base pointers */
2069static int
2070intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2071 int x, int y, enum mode_set_atomic state)
2072{
2073 struct drm_device *dev = crtc->dev;
2074 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2075
6b8e6ed0
CW		 2076 if (dev_priv->display.disable_fbc)
2077 dev_priv->display.disable_fbc(dev);
3dec0095 2078 intel_increase_pllclock(crtc);
81255565 2079
6b8e6ed0 2080 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2081}
2082
96a02917
VS		 2083void intel_display_handle_reset(struct drm_device *dev)
2084{
2085 struct drm_i915_private *dev_priv = dev->dev_private;
2086 struct drm_crtc *crtc;
2087
2088 /*
2089 * Flips in the rings have been nuked by the reset,
2090 * so complete all pending flips so that user space
2091 * will get its events and not get stuck.
2092 *
2093 * Also update the base address of all primary
2094 * planes to the the last fb to make sure we're
2095 * showing the correct fb after a reset.
2096 *
2097 * Need to make two loops over the crtcs so that we
2098 * don't try to grab a crtc mutex before the
2099 * pending_flip_queue really got woken up.
2100 */
2101
2102 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2104 enum plane plane = intel_crtc->plane;
2105
2106 intel_prepare_page_flip(dev, plane);
2107 intel_finish_page_flip_plane(dev, plane);
2108 }
2109
2110 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2112
2113 mutex_lock(&crtc->mutex);
2114 if (intel_crtc->active)
2115 dev_priv->display.update_plane(crtc, crtc->fb,
2116 crtc->x, crtc->y);
2117 mutex_unlock(&crtc->mutex);
2118 }
2119}
2120
14667a4b
CW		 2121static int
2122intel_finish_fb(struct drm_framebuffer *old_fb)
2123{
2124 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2125 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2126 bool was_interruptible = dev_priv->mm.interruptible;
2127 int ret;
2128
14667a4b
CW		 2129 /* Big Hammer, we also need to ensure that any pending
2130 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2131 * current scanout is retired before unpinning the old
2132 * framebuffer.
2133 *
2134 * This should only fail upon a hung GPU, in which case we
2135 * can safely continue.
2136 */
2137 dev_priv->mm.interruptible = false;
2138 ret = i915_gem_object_finish_gpu(obj);
2139 dev_priv->mm.interruptible = was_interruptible;
2140
2141 return ret;
2142}
2143
198598d0
VS		 2144static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2145{
2146 struct drm_device *dev = crtc->dev;
2147 struct drm_i915_master_private *master_priv;
2148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2149
2150 if (!dev->primary->master)
2151 return;
2152
2153 master_priv = dev->primary->master->driver_priv;
2154 if (!master_priv->sarea_priv)
2155 return;
2156
2157 switch (intel_crtc->pipe) {
2158 case 0:
2159 master_priv->sarea_priv->pipeA_x = x;
2160 master_priv->sarea_priv->pipeA_y = y;
2161 break;
2162 case 1:
2163 master_priv->sarea_priv->pipeB_x = x;
2164 master_priv->sarea_priv->pipeB_y = y;
2165 break;
2166 default:
2167 break;
2168 }
2169}
2170
5c3b82e2 2171static int
3c4fdcfb 2172intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2173 struct drm_framebuffer *fb)
79e53945
JB		 2174{
2175 struct drm_device *dev = crtc->dev;
6b8e6ed0 2176 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2178 struct drm_framebuffer *old_fb;
5c3b82e2 2179 int ret;
79e53945
JB		 2180
2181 /* no fb bound */
94352cf9 2182 if (!fb) {
a5071c2f 2183 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2184 return 0;
2185 }
2186
7eb552ae 2187 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2188 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2189 plane_name(intel_crtc->plane),
2190 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2191 return -EINVAL;
79e53945
JB		 2192 }
2193
5c3b82e2 2194 mutex_lock(&dev->struct_mutex);
265db958 2195 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2196 to_intel_framebuffer(fb)->obj,
919926ae 2197 NULL);
5c3b82e2
CW		 2198 if (ret != 0) {
2199 mutex_unlock(&dev->struct_mutex);
a5071c2f 2200 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2201 return ret;
2202 }
79e53945 2203
94352cf9 2204 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2205 if (ret) {
94352cf9 2206 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2207 mutex_unlock(&dev->struct_mutex);
a5071c2f 2208 DRM_ERROR("failed to update base address\n");
4e6cfefc 2209 return ret;
79e53945 2210 }
3c4fdcfb 2211
94352cf9
DV		 2212 old_fb = crtc->fb;
2213 crtc->fb = fb;
6c4c86f5
DV		 2214 crtc->x = x;
2215 crtc->y = y;
94352cf9 2216
b7f1de28 2217 if (old_fb) {
d7697eea
DV		 2218 if (intel_crtc->active && old_fb != fb)
2219 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2220 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2221 }
652c393a 2222
6b8e6ed0 2223 intel_update_fbc(dev);
5c3b82e2 2224 mutex_unlock(&dev->struct_mutex);
79e53945 2225
198598d0 2226 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2227
2228 return 0;
79e53945
JB		 2229}
2230
5e84e1a4
ZW		 2231static void intel_fdi_normal_train(struct drm_crtc *crtc)
2232{
2233 struct drm_device *dev = crtc->dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2236 int pipe = intel_crtc->pipe;
2237 u32 reg, temp;
2238
2239 /* enable normal train */
2240 reg = FDI_TX_CTL(pipe);
2241 temp = I915_READ(reg);
61e499bf 2242 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2243 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2244 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2245 } else {
2246 temp &= ~FDI_LINK_TRAIN_NONE;
2247 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2248 }
5e84e1a4
ZW		 2249 I915_WRITE(reg, temp);
2250
2251 reg = FDI_RX_CTL(pipe);
2252 temp = I915_READ(reg);
2253 if (HAS_PCH_CPT(dev)) {
2254 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2255 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2256 } else {
2257 temp &= ~FDI_LINK_TRAIN_NONE;
2258 temp |= FDI_LINK_TRAIN_NONE;
2259 }
2260 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2261
2262 /* wait one idle pattern time */
2263 POSTING_READ(reg);
2264 udelay(1000);
357555c0
JB		 2265
2266 /* IVB wants error correction enabled */
2267 if (IS_IVYBRIDGE(dev))
2268 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2269 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2270}
2271
1e833f40
DV		 2272static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2273{
2274 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2275}
2276
01a415fd
DV		 2277static void ivb_modeset_global_resources(struct drm_device *dev)
2278{
2279 struct drm_i915_private *dev_priv = dev->dev_private;
2280 struct intel_crtc *pipe_B_crtc =
2281 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2282 struct intel_crtc *pipe_C_crtc =
2283 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2284 uint32_t temp;
2285
1e833f40
DV		 2286 /*
2287 * When everything is off disable fdi C so that we could enable fdi B
2288 * with all lanes. Note that we don't care about enabled pipes without
2289 * an enabled pch encoder.
2290 */
2291 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2292 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2293 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2294 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2295
2296 temp = I915_READ(SOUTH_CHICKEN1);
2297 temp &= ~FDI_BC_BIFURCATION_SELECT;
2298 DRM_DEBUG_KMS("disabling fdi C rx\n");
2299 I915_WRITE(SOUTH_CHICKEN1, temp);
2300 }
2301}
2302
8db9d77b
ZW		 2303/* The FDI link training functions for ILK/Ibexpeak. */
2304static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2305{
2306 struct drm_device *dev = crtc->dev;
2307 struct drm_i915_private *dev_priv = dev->dev_private;
2308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2309 int pipe = intel_crtc->pipe;
0fc932b8 2310 int plane = intel_crtc->plane;
5eddb70b 2311 u32 reg, temp, tries;
8db9d77b 2312
0fc932b8
JB		 2313 /* FDI needs bits from pipe & plane first */
2314 assert_pipe_enabled(dev_priv, pipe);
2315 assert_plane_enabled(dev_priv, plane);
2316
e1a44743
AJ		 2317 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2318 for train result */
5eddb70b
CW		 2319 reg = FDI_RX_IMR(pipe);
2320 temp = I915_READ(reg);
e1a44743
AJ		 2321 temp &= ~FDI_RX_SYMBOL_LOCK;
2322 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2323 I915_WRITE(reg, temp);
2324 I915_READ(reg);
e1a44743
AJ		 2325 udelay(150);
2326
8db9d77b 2327 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2328 reg = FDI_TX_CTL(pipe);
2329 temp = I915_READ(reg);
627eb5a3
DV		 2330 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2331 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2332 temp &= ~FDI_LINK_TRAIN_NONE;
2333 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2334 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2335
5eddb70b
CW		 2336 reg = FDI_RX_CTL(pipe);
2337 temp = I915_READ(reg);
8db9d77b
ZW		 2338 temp &= ~FDI_LINK_TRAIN_NONE;
2339 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2340 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2341
2342 POSTING_READ(reg);
8db9d77b
ZW		 2343 udelay(150);
2344
5b2adf89 2345 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2346 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2347 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2348 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2349
5eddb70b 2350 reg = FDI_RX_IIR(pipe);
e1a44743 2351 for (tries = 0; tries < 5; tries++) {
5eddb70b 2352 temp = I915_READ(reg);
8db9d77b
ZW		 2353 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2354
2355 if ((temp & FDI_RX_BIT_LOCK)) {
2356 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2357 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2358 break;
2359 }
8db9d77b 2360 }
e1a44743 2361 if (tries == 5)
5eddb70b 2362 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2363
2364 /* Train 2 */
5eddb70b
CW		 2365 reg = FDI_TX_CTL(pipe);
2366 temp = I915_READ(reg);
8db9d77b
ZW		 2367 temp &= ~FDI_LINK_TRAIN_NONE;
2368 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2369 I915_WRITE(reg, temp);
8db9d77b 2370
5eddb70b
CW		 2371 reg = FDI_RX_CTL(pipe);
2372 temp = I915_READ(reg);
8db9d77b
ZW		 2373 temp &= ~FDI_LINK_TRAIN_NONE;
2374 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2375 I915_WRITE(reg, temp);
8db9d77b 2376
5eddb70b
CW		 2377 POSTING_READ(reg);
2378 udelay(150);
8db9d77b 2379
5eddb70b 2380 reg = FDI_RX_IIR(pipe);
e1a44743 2381 for (tries = 0; tries < 5; tries++) {
5eddb70b 2382 temp = I915_READ(reg);
8db9d77b
ZW		 2383 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2384
2385 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2386 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2387 DRM_DEBUG_KMS("FDI train 2 done.\n");
2388 break;
2389 }
8db9d77b 2390 }
e1a44743 2391 if (tries == 5)
5eddb70b 2392 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2393
2394 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2395
8db9d77b
ZW		 2396}
2397
0206e353 2398static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2399 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2400 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2401 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2402 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2403};
2404
2405/* The FDI link training functions for SNB/Cougarpoint. */
2406static void gen6_fdi_link_train(struct drm_crtc *crtc)
2407{
2408 struct drm_device *dev = crtc->dev;
2409 struct drm_i915_private *dev_priv = dev->dev_private;
2410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2411 int pipe = intel_crtc->pipe;
fa37d39e 2412 u32 reg, temp, i, retry;
8db9d77b 2413
e1a44743
AJ		 2414 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2415 for train result */
5eddb70b
CW		 2416 reg = FDI_RX_IMR(pipe);
2417 temp = I915_READ(reg);
e1a44743
AJ		 2418 temp &= ~FDI_RX_SYMBOL_LOCK;
2419 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2420 I915_WRITE(reg, temp);
2421
2422 POSTING_READ(reg);
e1a44743
AJ		 2423 udelay(150);
2424
8db9d77b 2425 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2426 reg = FDI_TX_CTL(pipe);
2427 temp = I915_READ(reg);
627eb5a3
DV		 2428 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2429 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2430 temp &= ~FDI_LINK_TRAIN_NONE;
2431 temp |= FDI_LINK_TRAIN_PATTERN_1;
2432 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2433 /* SNB-B */
2434 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2435 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2436
d74cf324
DV		 2437 I915_WRITE(FDI_RX_MISC(pipe),
2438 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2439
5eddb70b
CW		 2440 reg = FDI_RX_CTL(pipe);
2441 temp = I915_READ(reg);
8db9d77b
ZW		 2442 if (HAS_PCH_CPT(dev)) {
2443 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2444 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2445 } else {
2446 temp &= ~FDI_LINK_TRAIN_NONE;
2447 temp |= FDI_LINK_TRAIN_PATTERN_1;
2448 }
5eddb70b
CW		 2449 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2450
2451 POSTING_READ(reg);
8db9d77b
ZW		 2452 udelay(150);
2453
0206e353 2454 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2455 reg = FDI_TX_CTL(pipe);
2456 temp = I915_READ(reg);
8db9d77b
ZW		 2457 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2458 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2459 I915_WRITE(reg, temp);
2460
2461 POSTING_READ(reg);
8db9d77b
ZW		 2462 udelay(500);
2463
fa37d39e
SP		 2464 for (retry = 0; retry < 5; retry++) {
2465 reg = FDI_RX_IIR(pipe);
2466 temp = I915_READ(reg);
2467 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2468 if (temp & FDI_RX_BIT_LOCK) {
2469 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2470 DRM_DEBUG_KMS("FDI train 1 done.\n");
2471 break;
2472 }
2473 udelay(50);
8db9d77b 2474 }
fa37d39e
SP		 2475 if (retry < 5)
2476 break;
8db9d77b
ZW		 2477 }
2478 if (i == 4)
5eddb70b 2479 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2480
2481 /* Train 2 */
5eddb70b
CW		 2482 reg = FDI_TX_CTL(pipe);
2483 temp = I915_READ(reg);
8db9d77b
ZW		 2484 temp &= ~FDI_LINK_TRAIN_NONE;
2485 temp |= FDI_LINK_TRAIN_PATTERN_2;
2486 if (IS_GEN6(dev)) {
2487 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2488 /* SNB-B */
2489 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2490 }
5eddb70b 2491 I915_WRITE(reg, temp);
8db9d77b 2492
5eddb70b
CW		 2493 reg = FDI_RX_CTL(pipe);
2494 temp = I915_READ(reg);
8db9d77b
ZW		 2495 if (HAS_PCH_CPT(dev)) {
2496 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2497 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2498 } else {
2499 temp &= ~FDI_LINK_TRAIN_NONE;
2500 temp |= FDI_LINK_TRAIN_PATTERN_2;
2501 }
5eddb70b
CW		 2502 I915_WRITE(reg, temp);
2503
2504 POSTING_READ(reg);
8db9d77b
ZW		 2505 udelay(150);
2506
0206e353 2507 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2508 reg = FDI_TX_CTL(pipe);
2509 temp = I915_READ(reg);
8db9d77b
ZW		 2510 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2511 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2512 I915_WRITE(reg, temp);
2513
2514 POSTING_READ(reg);
8db9d77b
ZW		 2515 udelay(500);
2516
fa37d39e
SP		 2517 for (retry = 0; retry < 5; retry++) {
2518 reg = FDI_RX_IIR(pipe);
2519 temp = I915_READ(reg);
2520 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2521 if (temp & FDI_RX_SYMBOL_LOCK) {
2522 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2523 DRM_DEBUG_KMS("FDI train 2 done.\n");
2524 break;
2525 }
2526 udelay(50);
8db9d77b 2527 }
fa37d39e
SP		 2528 if (retry < 5)
2529 break;
8db9d77b
ZW		 2530 }
2531 if (i == 4)
5eddb70b 2532 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2533
2534 DRM_DEBUG_KMS("FDI train done.\n");
2535}
2536
357555c0
JB		 2537/* Manual link training for Ivy Bridge A0 parts */
2538static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2539{
2540 struct drm_device *dev = crtc->dev;
2541 struct drm_i915_private *dev_priv = dev->dev_private;
2542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2543 int pipe = intel_crtc->pipe;
2544 u32 reg, temp, i;
2545
2546 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2547 for train result */
2548 reg = FDI_RX_IMR(pipe);
2549 temp = I915_READ(reg);
2550 temp &= ~FDI_RX_SYMBOL_LOCK;
2551 temp &= ~FDI_RX_BIT_LOCK;
2552 I915_WRITE(reg, temp);
2553
2554 POSTING_READ(reg);
2555 udelay(150);
2556
01a415fd
DV		 2557 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2558 I915_READ(FDI_RX_IIR(pipe)));
2559
357555c0
JB		 2560 /* enable CPU FDI TX and PCH FDI RX */
2561 reg = FDI_TX_CTL(pipe);
2562 temp = I915_READ(reg);
627eb5a3
DV		 2563 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2564 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2565 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2566 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2567 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2568 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2569 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2570 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2571
d74cf324
DV		 2572 I915_WRITE(FDI_RX_MISC(pipe),
2573 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2574
357555c0
JB		 2575 reg = FDI_RX_CTL(pipe);
2576 temp = I915_READ(reg);
2577 temp &= ~FDI_LINK_TRAIN_AUTO;
2578 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2579 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2580 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2581 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2582
2583 POSTING_READ(reg);
2584 udelay(150);
2585
0206e353 2586 for (i = 0; i < 4; i++) {
357555c0
JB		 2587 reg = FDI_TX_CTL(pipe);
2588 temp = I915_READ(reg);
2589 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2590 temp |= snb_b_fdi_train_param[i];
2591 I915_WRITE(reg, temp);
2592
2593 POSTING_READ(reg);
2594 udelay(500);
2595
2596 reg = FDI_RX_IIR(pipe);
2597 temp = I915_READ(reg);
2598 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2599
2600 if (temp & FDI_RX_BIT_LOCK ||
2601 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2602 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2603 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2604 break;
2605 }
2606 }
2607 if (i == 4)
2608 DRM_ERROR("FDI train 1 fail!\n");
2609
2610 /* Train 2 */
2611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2614 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2615 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2616 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2617 I915_WRITE(reg, temp);
2618
2619 reg = FDI_RX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2622 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2623 I915_WRITE(reg, temp);
2624
2625 POSTING_READ(reg);
2626 udelay(150);
2627
0206e353 2628 for (i = 0; i < 4; i++) {
357555c0
JB		 2629 reg = FDI_TX_CTL(pipe);
2630 temp = I915_READ(reg);
2631 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2632 temp |= snb_b_fdi_train_param[i];
2633 I915_WRITE(reg, temp);
2634
2635 POSTING_READ(reg);
2636 udelay(500);
2637
2638 reg = FDI_RX_IIR(pipe);
2639 temp = I915_READ(reg);
2640 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2641
2642 if (temp & FDI_RX_SYMBOL_LOCK) {
2643 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2644 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2645 break;
2646 }
2647 }
2648 if (i == 4)
2649 DRM_ERROR("FDI train 2 fail!\n");
2650
2651 DRM_DEBUG_KMS("FDI train done.\n");
2652}
2653
88cefb6c 2654static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2655{
88cefb6c 2656 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2657 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2658 int pipe = intel_crtc->pipe;
5eddb70b 2659 u32 reg, temp;
79e53945 2660
c64e311e 2661
c98e9dcf 2662 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2663 reg = FDI_RX_CTL(pipe);
2664 temp = I915_READ(reg);
627eb5a3
DV		 2665 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2666 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2667 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2668 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2669
2670 POSTING_READ(reg);
c98e9dcf
JB		 2671 udelay(200);
2672
2673 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2674 temp = I915_READ(reg);
2675 I915_WRITE(reg, temp | FDI_PCDCLK);
2676
2677 POSTING_READ(reg);
c98e9dcf
JB		 2678 udelay(200);
2679
20749730
PZ		 2680 /* Enable CPU FDI TX PLL, always on for Ironlake */
2681 reg = FDI_TX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2684 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2685
20749730
PZ		 2686 POSTING_READ(reg);
2687 udelay(100);
6be4a607 2688 }
0e23b99d
JB		 2689}
2690
88cefb6c
DV		 2691static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2692{
2693 struct drm_device *dev = intel_crtc->base.dev;
2694 struct drm_i915_private *dev_priv = dev->dev_private;
2695 int pipe = intel_crtc->pipe;
2696 u32 reg, temp;
2697
2698 /* Switch from PCDclk to Rawclk */
2699 reg = FDI_RX_CTL(pipe);
2700 temp = I915_READ(reg);
2701 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2702
2703 /* Disable CPU FDI TX PLL */
2704 reg = FDI_TX_CTL(pipe);
2705 temp = I915_READ(reg);
2706 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2707
2708 POSTING_READ(reg);
2709 udelay(100);
2710
2711 reg = FDI_RX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2714
2715 /* Wait for the clocks to turn off. */
2716 POSTING_READ(reg);
2717 udelay(100);
2718}
2719
0fc932b8
JB		 2720static void ironlake_fdi_disable(struct drm_crtc *crtc)
2721{
2722 struct drm_device *dev = crtc->dev;
2723 struct drm_i915_private *dev_priv = dev->dev_private;
2724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2725 int pipe = intel_crtc->pipe;
2726 u32 reg, temp;
2727
2728 /* disable CPU FDI tx and PCH FDI rx */
2729 reg = FDI_TX_CTL(pipe);
2730 temp = I915_READ(reg);
2731 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2732 POSTING_READ(reg);
2733
2734 reg = FDI_RX_CTL(pipe);
2735 temp = I915_READ(reg);
2736 temp &= ~(0x7 << 16);
dfd07d72 2737 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2738 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2739
2740 POSTING_READ(reg);
2741 udelay(100);
2742
2743 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2744 if (HAS_PCH_IBX(dev)) {
2745 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2746 }
0fc932b8
JB		 2747
2748 /* still set train pattern 1 */
2749 reg = FDI_TX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 temp &= ~FDI_LINK_TRAIN_NONE;
2752 temp |= FDI_LINK_TRAIN_PATTERN_1;
2753 I915_WRITE(reg, temp);
2754
2755 reg = FDI_RX_CTL(pipe);
2756 temp = I915_READ(reg);
2757 if (HAS_PCH_CPT(dev)) {
2758 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2759 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2760 } else {
2761 temp &= ~FDI_LINK_TRAIN_NONE;
2762 temp |= FDI_LINK_TRAIN_PATTERN_1;
2763 }
2764 /* BPC in FDI rx is consistent with that in PIPECONF */
2765 temp &= ~(0x07 << 16);
dfd07d72 2766 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2767 I915_WRITE(reg, temp);
2768
2769 POSTING_READ(reg);
2770 udelay(100);
2771}
2772
5bb61643
CW		 2773static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2774{
2775 struct drm_device *dev = crtc->dev;
2776 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2778 unsigned long flags;
2779 bool pending;
2780
10d83730
VS		 2781 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2782 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2783 return false;
2784
2785 spin_lock_irqsave(&dev->event_lock, flags);
2786 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2787 spin_unlock_irqrestore(&dev->event_lock, flags);
2788
2789 return pending;
2790}
2791
e6c3a2a6
CW		 2792static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2793{
0f91128d 2794 struct drm_device *dev = crtc->dev;
5bb61643 2795 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2796
2797 if (crtc->fb == NULL)
2798 return;
2799
2c10d571
DV		 2800 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2801
5bb61643
CW		 2802 wait_event(dev_priv->pending_flip_queue,
2803 !intel_crtc_has_pending_flip(crtc));
2804
0f91128d
CW		 2805 mutex_lock(&dev->struct_mutex);
2806 intel_finish_fb(crtc->fb);
2807 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2808}
2809
e615efe4
ED		 2810/* Program iCLKIP clock to the desired frequency */
2811static void lpt_program_iclkip(struct drm_crtc *crtc)
2812{
2813 struct drm_device *dev = crtc->dev;
2814 struct drm_i915_private *dev_priv = dev->dev_private;
2815 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2816 u32 temp;
2817
09153000
DV		 2818 mutex_lock(&dev_priv->dpio_lock);
2819
e615efe4
ED		 2820 /* It is necessary to ungate the pixclk gate prior to programming
2821 * the divisors, and gate it back when it is done.
2822 */
2823 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2824
2825 /* Disable SSCCTL */
2826 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2827 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2828 SBI_SSCCTL_DISABLE,
2829 SBI_ICLK);
e615efe4
ED		 2830
2831 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2832 if (crtc->mode.clock == 20000) {
2833 auxdiv = 1;
2834 divsel = 0x41;
2835 phaseinc = 0x20;
2836 } else {
2837 /* The iCLK virtual clock root frequency is in MHz,
2838 * but the crtc->mode.clock in in KHz. To get the divisors,
2839 * it is necessary to divide one by another, so we
2840 * convert the virtual clock precision to KHz here for higher
2841 * precision.
2842 */
2843 u32 iclk_virtual_root_freq = 172800 * 1000;
2844 u32 iclk_pi_range = 64;
2845 u32 desired_divisor, msb_divisor_value, pi_value;
2846
2847 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2848 msb_divisor_value = desired_divisor / iclk_pi_range;
2849 pi_value = desired_divisor % iclk_pi_range;
2850
2851 auxdiv = 0;
2852 divsel = msb_divisor_value - 2;
2853 phaseinc = pi_value;
2854 }
2855
2856 /* This should not happen with any sane values */
2857 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2858 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2859 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2860 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2861
2862 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2863 crtc->mode.clock,
2864 auxdiv,
2865 divsel,
2866 phasedir,
2867 phaseinc);
2868
2869 /* Program SSCDIVINTPHASE6 */
988d6ee8 2870 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2871 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2872 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2873 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2874 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2875 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2876 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2877 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2878
2879 /* Program SSCAUXDIV */
988d6ee8 2880 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2881 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2882 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2883 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2884
2885 /* Enable modulator and associated divider */
988d6ee8 2886 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2887 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2888 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2889
2890 /* Wait for initialization time */
2891 udelay(24);
2892
2893 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2894
2895 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2896}
2897
275f01b2
DV		 2898static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2899 enum pipe pch_transcoder)
2900{
2901 struct drm_device *dev = crtc->base.dev;
2902 struct drm_i915_private *dev_priv = dev->dev_private;
2903 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2904
2905 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2906 I915_READ(HTOTAL(cpu_transcoder)));
2907 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2908 I915_READ(HBLANK(cpu_transcoder)));
2909 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2910 I915_READ(HSYNC(cpu_transcoder)));
2911
2912 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2913 I915_READ(VTOTAL(cpu_transcoder)));
2914 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2915 I915_READ(VBLANK(cpu_transcoder)));
2916 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2917 I915_READ(VSYNC(cpu_transcoder)));
2918 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2919 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2920}
2921
f67a559d
JB		 2922/*
2923 * Enable PCH resources required for PCH ports:
2924 * - PCH PLLs
2925 * - FDI training & RX/TX
2926 * - update transcoder timings
2927 * - DP transcoding bits
2928 * - transcoder
2929 */
2930static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2931{
2932 struct drm_device *dev = crtc->dev;
2933 struct drm_i915_private *dev_priv = dev->dev_private;
2934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2935 int pipe = intel_crtc->pipe;
ee7b9f93 2936 u32 reg, temp;
2c07245f 2937
ab9412ba 2938 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2939
cd986abb
DV		 2940 /* Write the TU size bits before fdi link training, so that error
2941 * detection works. */
2942 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2943 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2944
c98e9dcf 2945 /* For PCH output, training FDI link */
674cf967 2946 dev_priv->display.fdi_link_train(crtc);
2c07245f 2947
572deb37
DV		 2948 /* XXX: pch pll's can be enabled any time before we enable the PCH
2949 * transcoder, and we actually should do this to not upset any PCH
2950 * transcoder that already use the clock when we share it.
2951 *
2952 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
2953 * unconditionally resets the pll - we need that to have the right LVDS
2954 * enable sequence. */
b6b4e185 2955 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 2956
303b81e0 2957 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2958 u32 sel;
4b645f14 2959
c98e9dcf 2960 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2961 switch (pipe) {
2962 default:
2963 case 0:
2964 temp |= TRANSA_DPLL_ENABLE;
2965 sel = TRANSA_DPLLB_SEL;
2966 break;
2967 case 1:
2968 temp |= TRANSB_DPLL_ENABLE;
2969 sel = TRANSB_DPLLB_SEL;
2970 break;
2971 case 2:
2972 temp |= TRANSC_DPLL_ENABLE;
2973 sel = TRANSC_DPLLB_SEL;
2974 break;
d64311ab 2975 }
ee7b9f93
JB		 2976 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2977 temp |= sel;
2978 else
2979 temp &= ~sel;
c98e9dcf 2980 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2981 }
5eddb70b 2982
d9b6cb56
JB		 2983 /* set transcoder timing, panel must allow it */
2984 assert_panel_unlocked(dev_priv, pipe);
275f01b2 2985 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 2986
303b81e0 2987 intel_fdi_normal_train(crtc);
5e84e1a4 2988
c98e9dcf
JB		 2989 /* For PCH DP, enable TRANS_DP_CTL */
2990 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2991 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2992 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 2993 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 2994 reg = TRANS_DP_CTL(pipe);
2995 temp = I915_READ(reg);
2996 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2997 TRANS_DP_SYNC_MASK |
2998 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2999 temp |= (TRANS_DP_OUTPUT_ENABLE |
3000 TRANS_DP_ENH_FRAMING);
9325c9f0 3001 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3002
3003 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3004 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3005 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3006 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3007
3008 switch (intel_trans_dp_port_sel(crtc)) {
3009 case PCH_DP_B:
5eddb70b 3010 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3011 break;
3012 case PCH_DP_C:
5eddb70b 3013 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3014 break;
3015 case PCH_DP_D:
5eddb70b 3016 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3017 break;
3018 default:
e95d41e1 3019 BUG();
32f9d658 3020 }
2c07245f 3021
5eddb70b 3022 I915_WRITE(reg, temp);
6be4a607 3023 }
b52eb4dc 3024
b8a4f404 3025 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3026}
3027
1507e5bd
PZ		 3028static void lpt_pch_enable(struct drm_crtc *crtc)
3029{
3030 struct drm_device *dev = crtc->dev;
3031 struct drm_i915_private *dev_priv = dev->dev_private;
3032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3033 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3034
ab9412ba 3035 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3036
8c52b5e8 3037 lpt_program_iclkip(crtc);
1507e5bd 3038
0540e488 3039 /* Set transcoder timing. */
275f01b2 3040 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3041
937bb610 3042 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3043}
3044
ee7b9f93
JB		 3045static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3046{
3047 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3048
3049 if (pll == NULL)
3050 return;
3051
3052 if (pll->refcount == 0) {
3053 WARN(1, "bad PCH PLL refcount\n");
3054 return;
3055 }
3056
3057 --pll->refcount;
3058 intel_crtc->pch_pll = NULL;
3059}
3060
3061static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3062{
3063 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3064 struct intel_pch_pll *pll;
3065 int i;
3066
3067 pll = intel_crtc->pch_pll;
3068 if (pll) {
3069 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3070 intel_crtc->base.base.id, pll->pll_reg);
3071 goto prepare;
3072 }
3073
98b6bd99
DV		 3074 if (HAS_PCH_IBX(dev_priv->dev)) {
3075 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3076 i = intel_crtc->pipe;
3077 pll = &dev_priv->pch_plls[i];
3078
3079 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3080 intel_crtc->base.base.id, pll->pll_reg);
3081
3082 goto found;
3083 }
3084
ee7b9f93
JB		 3085 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3086 pll = &dev_priv->pch_plls[i];
3087
3088 /* Only want to check enabled timings first */
3089 if (pll->refcount == 0)
3090 continue;
3091
3092 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3093 fp == I915_READ(pll->fp0_reg)) {
3094 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3095 intel_crtc->base.base.id,
3096 pll->pll_reg, pll->refcount, pll->active);
3097
3098 goto found;
3099 }
3100 }
3101
3102 /* Ok no matching timings, maybe there's a free one? */
3103 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3104 pll = &dev_priv->pch_plls[i];
3105 if (pll->refcount == 0) {
3106 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3107 intel_crtc->base.base.id, pll->pll_reg);
3108 goto found;
3109 }
3110 }
3111
3112 return NULL;
3113
3114found:
3115 intel_crtc->pch_pll = pll;
3116 pll->refcount++;
84f44ce7 3117 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3118prepare: /* separate function? */
3119 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3120
e04c7350
CW		 3121 /* Wait for the clocks to stabilize before rewriting the regs */
3122 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3123 POSTING_READ(pll->pll_reg);
3124 udelay(150);
e04c7350
CW		 3125
3126 I915_WRITE(pll->fp0_reg, fp);
3127 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3128 pll->on = false;
3129 return pll;
3130}
3131
a1520318 3132static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3133{
3134 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3135 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3136 u32 temp;
3137
3138 temp = I915_READ(dslreg);
3139 udelay(500);
3140 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3141 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3142 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3143 }
3144}
3145
b074cec8
JB		 3146static void ironlake_pfit_enable(struct intel_crtc *crtc)
3147{
3148 struct drm_device *dev = crtc->base.dev;
3149 struct drm_i915_private *dev_priv = dev->dev_private;
3150 int pipe = crtc->pipe;
3151
0ef37f3f 3152 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3153 /* Force use of hard-coded filter coefficients
3154 * as some pre-programmed values are broken,
3155 * e.g. x201.
3156 */
3157 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3158 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3159 PF_PIPE_SEL_IVB(pipe));
3160 else
3161 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3162 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3163 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3164 }
3165}
3166
bb53d4ae
VS		 3167static void intel_enable_planes(struct drm_crtc *crtc)
3168{
3169 struct drm_device *dev = crtc->dev;
3170 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3171 struct intel_plane *intel_plane;
3172
3173 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3174 if (intel_plane->pipe == pipe)
3175 intel_plane_restore(&intel_plane->base);
3176}
3177
3178static void intel_disable_planes(struct drm_crtc *crtc)
3179{
3180 struct drm_device *dev = crtc->dev;
3181 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3182 struct intel_plane *intel_plane;
3183
3184 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3185 if (intel_plane->pipe == pipe)
3186 intel_plane_disable(&intel_plane->base);
3187}
3188
f67a559d
JB		 3189static void ironlake_crtc_enable(struct drm_crtc *crtc)
3190{
3191 struct drm_device *dev = crtc->dev;
3192 struct drm_i915_private *dev_priv = dev->dev_private;
3193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3194 struct intel_encoder *encoder;
f67a559d
JB		 3195 int pipe = intel_crtc->pipe;
3196 int plane = intel_crtc->plane;
3197 u32 temp;
f67a559d 3198
08a48469
DV		 3199 WARN_ON(!crtc->enabled);
3200
f67a559d
JB		 3201 if (intel_crtc->active)
3202 return;
3203
3204 intel_crtc->active = true;
8664281b
PZ		 3205
3206 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3207 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3208
f67a559d
JB		 3209 intel_update_watermarks(dev);
3210
3211 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3212 temp = I915_READ(PCH_LVDS);
3213 if ((temp & LVDS_PORT_EN) == 0)
3214 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3215 }
3216
f67a559d 3217
5bfe2ac0 3218 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3219 /* Note: FDI PLL enabling _must_ be done before we enable the
3220 * cpu pipes, hence this is separate from all the other fdi/pch
3221 * enabling. */
88cefb6c 3222 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3223 } else {
3224 assert_fdi_tx_disabled(dev_priv, pipe);
3225 assert_fdi_rx_disabled(dev_priv, pipe);
3226 }
f67a559d 3227
bf49ec8c
DV		 3228 for_each_encoder_on_crtc(dev, crtc, encoder)
3229 if (encoder->pre_enable)
3230 encoder->pre_enable(encoder);
f67a559d
JB		 3231
3232 /* Enable panel fitting for LVDS */
b074cec8 3233 ironlake_pfit_enable(intel_crtc);
f67a559d 3234
9c54c0dd
JB		 3235 /*
3236 * On ILK+ LUT must be loaded before the pipe is running but with
3237 * clocks enabled
3238 */
3239 intel_crtc_load_lut(crtc);
3240
5bfe2ac0
DV		 3241 intel_enable_pipe(dev_priv, pipe,
3242 intel_crtc->config.has_pch_encoder);
f67a559d 3243 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3244 intel_enable_planes(crtc);
5c38d48c 3245 intel_crtc_update_cursor(crtc, true);
f67a559d 3246
5bfe2ac0 3247 if (intel_crtc->config.has_pch_encoder)
f67a559d 3248 ironlake_pch_enable(crtc);
c98e9dcf 3249
d1ebd816 3250 mutex_lock(&dev->struct_mutex);
bed4a673 3251 intel_update_fbc(dev);
d1ebd816
BW		 3252 mutex_unlock(&dev->struct_mutex);
3253
fa5c73b1
DV		 3254 for_each_encoder_on_crtc(dev, crtc, encoder)
3255 encoder->enable(encoder);
61b77ddd
DV		 3256
3257 if (HAS_PCH_CPT(dev))
a1520318 3258 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3259
3260 /*
3261 * There seems to be a race in PCH platform hw (at least on some
3262 * outputs) where an enabled pipe still completes any pageflip right
3263 * away (as if the pipe is off) instead of waiting for vblank. As soon
3264 * as the first vblank happend, everything works as expected. Hence just
3265 * wait for one vblank before returning to avoid strange things
3266 * happening.
3267 */
3268 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3269}
3270
42db64ef
PZ		 3271/* IPS only exists on ULT machines and is tied to pipe A. */
3272static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3273{
3274 return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3275}
3276
3277static void hsw_enable_ips(struct intel_crtc *crtc)
3278{
3279 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3280
3281 if (!crtc->config.ips_enabled)
3282 return;
3283
3284 /* We can only enable IPS after we enable a plane and wait for a vblank.
3285 * We guarantee that the plane is enabled by calling intel_enable_ips
3286 * only after intel_enable_plane. And intel_enable_plane already waits
3287 * for a vblank, so all we need to do here is to enable the IPS bit. */
3288 assert_plane_enabled(dev_priv, crtc->plane);
3289 I915_WRITE(IPS_CTL, IPS_ENABLE);
3290}
3291
3292static void hsw_disable_ips(struct intel_crtc *crtc)
3293{
3294 struct drm_device *dev = crtc->base.dev;
3295 struct drm_i915_private *dev_priv = dev->dev_private;
3296
3297 if (!crtc->config.ips_enabled)
3298 return;
3299
3300 assert_plane_enabled(dev_priv, crtc->plane);
3301 I915_WRITE(IPS_CTL, 0);
3302
3303 /* We need to wait for a vblank before we can disable the plane. */
3304 intel_wait_for_vblank(dev, crtc->pipe);
3305}
3306
4f771f10
PZ		 3307static void haswell_crtc_enable(struct drm_crtc *crtc)
3308{
3309 struct drm_device *dev = crtc->dev;
3310 struct drm_i915_private *dev_priv = dev->dev_private;
3311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3312 struct intel_encoder *encoder;
3313 int pipe = intel_crtc->pipe;
3314 int plane = intel_crtc->plane;
4f771f10
PZ		 3315
3316 WARN_ON(!crtc->enabled);
3317
3318 if (intel_crtc->active)
3319 return;
3320
3321 intel_crtc->active = true;
8664281b
PZ		 3322
3323 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3324 if (intel_crtc->config.has_pch_encoder)
3325 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3326
4f771f10
PZ		 3327 intel_update_watermarks(dev);
3328
5bfe2ac0 3329 if (intel_crtc->config.has_pch_encoder)
04945641 3330 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3331
3332 for_each_encoder_on_crtc(dev, crtc, encoder)
3333 if (encoder->pre_enable)
3334 encoder->pre_enable(encoder);
3335
1f544388 3336 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3337
1f544388 3338 /* Enable panel fitting for eDP */
b074cec8 3339 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3340
3341 /*
3342 * On ILK+ LUT must be loaded before the pipe is running but with
3343 * clocks enabled
3344 */
3345 intel_crtc_load_lut(crtc);
3346
1f544388 3347 intel_ddi_set_pipe_settings(crtc);
8228c251 3348 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3349
5bfe2ac0
DV		 3350 intel_enable_pipe(dev_priv, pipe,
3351 intel_crtc->config.has_pch_encoder);
4f771f10 3352 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3353 intel_enable_planes(crtc);
5c38d48c 3354 intel_crtc_update_cursor(crtc, true);
4f771f10 3355
42db64ef
PZ		 3356 hsw_enable_ips(intel_crtc);
3357
5bfe2ac0 3358 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3359 lpt_pch_enable(crtc);
4f771f10
PZ		 3360
3361 mutex_lock(&dev->struct_mutex);
3362 intel_update_fbc(dev);
3363 mutex_unlock(&dev->struct_mutex);
3364
4f771f10
PZ		 3365 for_each_encoder_on_crtc(dev, crtc, encoder)
3366 encoder->enable(encoder);
3367
4f771f10
PZ		 3368 /*
3369 * There seems to be a race in PCH platform hw (at least on some
3370 * outputs) where an enabled pipe still completes any pageflip right
3371 * away (as if the pipe is off) instead of waiting for vblank. As soon
3372 * as the first vblank happend, everything works as expected. Hence just
3373 * wait for one vblank before returning to avoid strange things
3374 * happening.
3375 */
3376 intel_wait_for_vblank(dev, intel_crtc->pipe);
3377}
3378
3f8dce3a
DV		 3379static void ironlake_pfit_disable(struct intel_crtc *crtc)
3380{
3381 struct drm_device *dev = crtc->base.dev;
3382 struct drm_i915_private *dev_priv = dev->dev_private;
3383 int pipe = crtc->pipe;
3384
3385 /* To avoid upsetting the power well on haswell only disable the pfit if
3386 * it's in use. The hw state code will make sure we get this right. */
3387 if (crtc->config.pch_pfit.size) {
3388 I915_WRITE(PF_CTL(pipe), 0);
3389 I915_WRITE(PF_WIN_POS(pipe), 0);
3390 I915_WRITE(PF_WIN_SZ(pipe), 0);
3391 }
3392}
3393
6be4a607
JB		 3394static void ironlake_crtc_disable(struct drm_crtc *crtc)
3395{
3396 struct drm_device *dev = crtc->dev;
3397 struct drm_i915_private *dev_priv = dev->dev_private;
3398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3399 struct intel_encoder *encoder;
6be4a607
JB		 3400 int pipe = intel_crtc->pipe;
3401 int plane = intel_crtc->plane;
5eddb70b 3402 u32 reg, temp;
b52eb4dc 3403
ef9c3aee 3404
f7abfe8b
CW		 3405 if (!intel_crtc->active)
3406 return;
3407
ea9d758d
DV		 3408 for_each_encoder_on_crtc(dev, crtc, encoder)
3409 encoder->disable(encoder);
3410
e6c3a2a6 3411 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3412 drm_vblank_off(dev, pipe);
913d8d11 3413
973d04f9
CW		 3414 if (dev_priv->cfb_plane == plane)
3415 intel_disable_fbc(dev);
2c07245f 3416
0d5b8c61 3417 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3418 intel_disable_planes(crtc);
0d5b8c61
VS		 3419 intel_disable_plane(dev_priv, plane, pipe);
3420
8664281b 3421 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3422 intel_disable_pipe(dev_priv, pipe);
32f9d658 3423
3f8dce3a 3424 ironlake_pfit_disable(intel_crtc);
2c07245f 3425
bf49ec8c
DV		 3426 for_each_encoder_on_crtc(dev, crtc, encoder)
3427 if (encoder->post_disable)
3428 encoder->post_disable(encoder);
2c07245f 3429
0fc932b8 3430 ironlake_fdi_disable(crtc);
249c0e64 3431
b8a4f404 3432 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3433 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3434
6be4a607
JB		 3435 if (HAS_PCH_CPT(dev)) {
3436 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3437 reg = TRANS_DP_CTL(pipe);
3438 temp = I915_READ(reg);
3439 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3440 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3441 I915_WRITE(reg, temp);
6be4a607
JB		 3442
3443 /* disable DPLL_SEL */
3444 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3445 switch (pipe) {
3446 case 0:
d64311ab 3447 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3448 break;
3449 case 1:
6be4a607 3450 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3451 break;
3452 case 2:
4b645f14 3453 /* C shares PLL A or B */
d64311ab 3454 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3455 break;
3456 default:
3457 BUG(); /* wtf */
3458 }
6be4a607 3459 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3460 }
e3421a18 3461
6be4a607 3462 /* disable PCH DPLL */
ee7b9f93 3463 intel_disable_pch_pll(intel_crtc);
8db9d77b 3464
88cefb6c 3465 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3466
f7abfe8b 3467 intel_crtc->active = false;
6b383a7f 3468 intel_update_watermarks(dev);
d1ebd816
BW		 3469
3470 mutex_lock(&dev->struct_mutex);
6b383a7f 3471 intel_update_fbc(dev);
d1ebd816 3472 mutex_unlock(&dev->struct_mutex);
6be4a607 3473}
1b3c7a47 3474
4f771f10 3475static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3476{
4f771f10
PZ		 3477 struct drm_device *dev = crtc->dev;
3478 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3480 struct intel_encoder *encoder;
3481 int pipe = intel_crtc->pipe;
3482 int plane = intel_crtc->plane;
3b117c8f 3483 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3484
4f771f10
PZ		 3485 if (!intel_crtc->active)
3486 return;
3487
3488 for_each_encoder_on_crtc(dev, crtc, encoder)
3489 encoder->disable(encoder);
3490
3491 intel_crtc_wait_for_pending_flips(crtc);
3492 drm_vblank_off(dev, pipe);
4f771f10 3493
891348b2 3494 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3495 if (dev_priv->cfb_plane == plane)
3496 intel_disable_fbc(dev);
3497
42db64ef
PZ		 3498 hsw_disable_ips(intel_crtc);
3499
0d5b8c61 3500 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3501 intel_disable_planes(crtc);
891348b2
RV		 3502 intel_disable_plane(dev_priv, plane, pipe);
3503
8664281b
PZ		 3504 if (intel_crtc->config.has_pch_encoder)
3505 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3506 intel_disable_pipe(dev_priv, pipe);
3507
ad80a810 3508 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3509
3f8dce3a 3510 ironlake_pfit_disable(intel_crtc);
4f771f10 3511
1f544388 3512 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3513
3514 for_each_encoder_on_crtc(dev, crtc, encoder)
3515 if (encoder->post_disable)
3516 encoder->post_disable(encoder);
3517
88adfff1 3518 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3519 lpt_disable_pch_transcoder(dev_priv);
8664281b 3520 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3521 intel_ddi_fdi_disable(crtc);
83616634 3522 }
4f771f10
PZ		 3523
3524 intel_crtc->active = false;
3525 intel_update_watermarks(dev);
3526
3527 mutex_lock(&dev->struct_mutex);
3528 intel_update_fbc(dev);
3529 mutex_unlock(&dev->struct_mutex);
3530}
3531
ee7b9f93
JB		 3532static void ironlake_crtc_off(struct drm_crtc *crtc)
3533{
3534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3535 intel_put_pch_pll(intel_crtc);
3536}
3537
6441ab5f
PZ		 3538static void haswell_crtc_off(struct drm_crtc *crtc)
3539{
3540 intel_ddi_put_crtc_pll(crtc);
3541}
3542
02e792fb
DV		 3543static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3544{
02e792fb 3545 if (!enable && intel_crtc->overlay) {
23f09ce3 3546 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3547 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3548
23f09ce3 3549 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3550 dev_priv->mm.interruptible = false;
3551 (void) intel_overlay_switch_off(intel_crtc->overlay);
3552 dev_priv->mm.interruptible = true;
23f09ce3 3553 mutex_unlock(&dev->struct_mutex);
02e792fb 3554 }
02e792fb 3555
5dcdbcb0
CW		 3556 /* Let userspace switch the overlay on again. In most cases userspace
3557 * has to recompute where to put it anyway.
3558 */
02e792fb
DV		 3559}
3560
61bc95c1
EE		 3561/**
3562 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3563 * cursor plane briefly if not already running after enabling the display
3564 * plane.
3565 * This workaround avoids occasional blank screens when self refresh is
3566 * enabled.
3567 */
3568static void
3569g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3570{
3571 u32 cntl = I915_READ(CURCNTR(pipe));
3572
3573 if ((cntl & CURSOR_MODE) == 0) {
3574 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3575
3576 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3577 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3578 intel_wait_for_vblank(dev_priv->dev, pipe);
3579 I915_WRITE(CURCNTR(pipe), cntl);
3580 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3581 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3582 }
3583}
3584
2dd24552
JB		 3585static void i9xx_pfit_enable(struct intel_crtc *crtc)
3586{
3587 struct drm_device *dev = crtc->base.dev;
3588 struct drm_i915_private *dev_priv = dev->dev_private;
3589 struct intel_crtc_config *pipe_config = &crtc->config;
3590
328d8e82 3591 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3592 return;
3593
2dd24552 3594 /*
c0b03411
DV		 3595 * The panel fitter should only be adjusted whilst the pipe is disabled,
3596 * according to register description and PRM.
2dd24552 3597 */
c0b03411
DV		 3598 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3599 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3600
b074cec8
JB		 3601 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3602 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3603
3604 /* Border color in case we don't scale up to the full screen. Black by
3605 * default, change to something else for debugging. */
3606 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3607}
3608
89b667f8
JB		 3609static void valleyview_crtc_enable(struct drm_crtc *crtc)
3610{
3611 struct drm_device *dev = crtc->dev;
3612 struct drm_i915_private *dev_priv = dev->dev_private;
3613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3614 struct intel_encoder *encoder;
3615 int pipe = intel_crtc->pipe;
3616 int plane = intel_crtc->plane;
3617
3618 WARN_ON(!crtc->enabled);
3619
3620 if (intel_crtc->active)
3621 return;
3622
3623 intel_crtc->active = true;
3624 intel_update_watermarks(dev);
3625
3626 mutex_lock(&dev_priv->dpio_lock);
3627
3628 for_each_encoder_on_crtc(dev, crtc, encoder)
3629 if (encoder->pre_pll_enable)
3630 encoder->pre_pll_enable(encoder);
3631
3632 intel_enable_pll(dev_priv, pipe);
3633
3634 for_each_encoder_on_crtc(dev, crtc, encoder)
3635 if (encoder->pre_enable)
3636 encoder->pre_enable(encoder);
3637
3638 /* VLV wants encoder enabling _before_ the pipe is up. */
3639 for_each_encoder_on_crtc(dev, crtc, encoder)
3640 encoder->enable(encoder);
3641
2dd24552
JB		 3642 /* Enable panel fitting for eDP */
3643 i9xx_pfit_enable(intel_crtc);
3644
63cbb074
VS		 3645 intel_crtc_load_lut(crtc);
3646
89b667f8
JB		 3647 intel_enable_pipe(dev_priv, pipe, false);
3648 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3649 intel_enable_planes(crtc);
5c38d48c 3650 intel_crtc_update_cursor(crtc, true);
89b667f8 3651
f440eb13
VS		 3652 intel_update_fbc(dev);
3653
89b667f8
JB		 3654 mutex_unlock(&dev_priv->dpio_lock);
3655}
3656
0b8765c6 3657static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3658{
3659 struct drm_device *dev = crtc->dev;
79e53945
JB		 3660 struct drm_i915_private *dev_priv = dev->dev_private;
3661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3662 struct intel_encoder *encoder;
79e53945 3663 int pipe = intel_crtc->pipe;
80824003 3664 int plane = intel_crtc->plane;
79e53945 3665
08a48469
DV		 3666 WARN_ON(!crtc->enabled);
3667
f7abfe8b
CW		 3668 if (intel_crtc->active)
3669 return;
3670
3671 intel_crtc->active = true;
6b383a7f
CW		 3672 intel_update_watermarks(dev);
3673
63d7bbe9 3674 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3675
3676 for_each_encoder_on_crtc(dev, crtc, encoder)
3677 if (encoder->pre_enable)
3678 encoder->pre_enable(encoder);
3679
2dd24552
JB		 3680 /* Enable panel fitting for LVDS */
3681 i9xx_pfit_enable(intel_crtc);
3682
63cbb074
VS		 3683 intel_crtc_load_lut(crtc);
3684
040484af 3685 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3686 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3687 intel_enable_planes(crtc);
5c38d48c 3688 intel_crtc_update_cursor(crtc, true);
61bc95c1
EE		 3689 if (IS_G4X(dev))
3690 g4x_fixup_plane(dev_priv, pipe);
79e53945 3691
0b8765c6
JB		 3692 /* Give the overlay scaler a chance to enable if it's on this pipe */
3693 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3694
f440eb13
VS		 3695 intel_update_fbc(dev);
3696
fa5c73b1
DV		 3697 for_each_encoder_on_crtc(dev, crtc, encoder)
3698 encoder->enable(encoder);
0b8765c6 3699}
79e53945 3700
87476d63
DV		 3701static void i9xx_pfit_disable(struct intel_crtc *crtc)
3702{
3703 struct drm_device *dev = crtc->base.dev;
3704 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3705
328d8e82
DV		 3706 if (!crtc->config.gmch_pfit.control)
3707 return;
87476d63 3708
328d8e82 3709 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3710
328d8e82
DV		 3711 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3712 I915_READ(PFIT_CONTROL));
3713 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3714}
3715
0b8765c6
JB		 3716static void i9xx_crtc_disable(struct drm_crtc *crtc)
3717{
3718 struct drm_device *dev = crtc->dev;
3719 struct drm_i915_private *dev_priv = dev->dev_private;
3720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3721 struct intel_encoder *encoder;
0b8765c6
JB		 3722 int pipe = intel_crtc->pipe;
3723 int plane = intel_crtc->plane;
ef9c3aee 3724
f7abfe8b
CW		 3725 if (!intel_crtc->active)
3726 return;
3727
ea9d758d
DV		 3728 for_each_encoder_on_crtc(dev, crtc, encoder)
3729 encoder->disable(encoder);
3730
0b8765c6 3731 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3732 intel_crtc_wait_for_pending_flips(crtc);
3733 drm_vblank_off(dev, pipe);
0b8765c6 3734
973d04f9
CW		 3735 if (dev_priv->cfb_plane == plane)
3736 intel_disable_fbc(dev);
79e53945 3737
0d5b8c61
VS		 3738 intel_crtc_dpms_overlay(intel_crtc, false);
3739 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3740 intel_disable_planes(crtc);
b24e7179 3741 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3742
b24e7179 3743 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3744
87476d63 3745 i9xx_pfit_disable(intel_crtc);
24a1f16d 3746
89b667f8
JB		 3747 for_each_encoder_on_crtc(dev, crtc, encoder)
3748 if (encoder->post_disable)
3749 encoder->post_disable(encoder);
3750
63d7bbe9 3751 intel_disable_pll(dev_priv, pipe);
0b8765c6 3752
f7abfe8b 3753 intel_crtc->active = false;
6b383a7f
CW		 3754 intel_update_fbc(dev);
3755 intel_update_watermarks(dev);
0b8765c6
JB		 3756}
3757
ee7b9f93
JB		 3758static void i9xx_crtc_off(struct drm_crtc *crtc)
3759{
3760}
3761
976f8a20
DV		 3762static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3763 bool enabled)
2c07245f
ZW		 3764{
3765 struct drm_device *dev = crtc->dev;
3766 struct drm_i915_master_private *master_priv;
3767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3768 int pipe = intel_crtc->pipe;
79e53945
JB		 3769
3770 if (!dev->primary->master)
3771 return;
3772
3773 master_priv = dev->primary->master->driver_priv;
3774 if (!master_priv->sarea_priv)
3775 return;
3776
79e53945
JB		 3777 switch (pipe) {
3778 case 0:
3779 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3780 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3781 break;
3782 case 1:
3783 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3784 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3785 break;
3786 default:
9db4a9c7 3787 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3788 break;
3789 }
79e53945
JB		 3790}
3791
976f8a20
DV		 3792/**
3793 * Sets the power management mode of the pipe and plane.
3794 */
3795void intel_crtc_update_dpms(struct drm_crtc *crtc)
3796{
3797 struct drm_device *dev = crtc->dev;
3798 struct drm_i915_private *dev_priv = dev->dev_private;
3799 struct intel_encoder *intel_encoder;
3800 bool enable = false;
3801
3802 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3803 enable |= intel_encoder->connectors_active;
3804
3805 if (enable)
3806 dev_priv->display.crtc_enable(crtc);
3807 else
3808 dev_priv->display.crtc_disable(crtc);
3809
3810 intel_crtc_update_sarea(crtc, enable);
3811}
3812
cdd59983
CW		 3813static void intel_crtc_disable(struct drm_crtc *crtc)
3814{
cdd59983 3815 struct drm_device *dev = crtc->dev;
976f8a20 3816 struct drm_connector *connector;
ee7b9f93 3817 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3819
976f8a20
DV		 3820 /* crtc should still be enabled when we disable it. */
3821 WARN_ON(!crtc->enabled);
3822
3823 dev_priv->display.crtc_disable(crtc);
c77bf565 3824 intel_crtc->eld_vld = false;
976f8a20 3825 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3826 dev_priv->display.off(crtc);
3827
931872fc
CW		 3828 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3829 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3830
3831 if (crtc->fb) {
3832 mutex_lock(&dev->struct_mutex);
1690e1eb 3833 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3834 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3835 crtc->fb = NULL;
3836 }
3837
3838 /* Update computed state. */
3839 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3840 if (!connector->encoder || !connector->encoder->crtc)
3841 continue;
3842
3843 if (connector->encoder->crtc != crtc)
3844 continue;
3845
3846 connector->dpms = DRM_MODE_DPMS_OFF;
3847 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3848 }
3849}
3850
a261b246 3851void intel_modeset_disable(struct drm_device *dev)
79e53945 3852{
a261b246
DV		 3853 struct drm_crtc *crtc;
3854
3855 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3856 if (crtc->enabled)
3857 intel_crtc_disable(crtc);
3858 }
79e53945
JB		 3859}
3860
ea5b213a 3861void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3862{
4ef69c7a 3863 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3864
ea5b213a
CW		 3865 drm_encoder_cleanup(encoder);
3866 kfree(intel_encoder);
7e7d76c3
JB		 3867}
3868
5ab432ef
DV		 3869/* Simple dpms helper for encodres with just one connector, no cloning and only
3870 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3871 * state of the entire output pipe. */
3872void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3873{
5ab432ef
DV		 3874 if (mode == DRM_MODE_DPMS_ON) {
3875 encoder->connectors_active = true;
3876
b2cabb0e 3877 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3878 } else {
3879 encoder->connectors_active = false;
3880
b2cabb0e 3881 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3882 }
79e53945
JB		 3883}
3884
0a91ca29
DV		 3885/* Cross check the actual hw state with our own modeset state tracking (and it's
3886 * internal consistency). */
b980514c 3887static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3888{
0a91ca29
DV		 3889 if (connector->get_hw_state(connector)) {
3890 struct intel_encoder *encoder = connector->encoder;
3891 struct drm_crtc *crtc;
3892 bool encoder_enabled;
3893 enum pipe pipe;
3894
3895 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3896 connector->base.base.id,
3897 drm_get_connector_name(&connector->base));
3898
3899 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3900 "wrong connector dpms state\n");
3901 WARN(connector->base.encoder != &encoder->base,
3902 "active connector not linked to encoder\n");
3903 WARN(!encoder->connectors_active,
3904 "encoder->connectors_active not set\n");
3905
3906 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3907 WARN(!encoder_enabled, "encoder not enabled\n");
3908 if (WARN_ON(!encoder->base.crtc))
3909 return;
3910
3911 crtc = encoder->base.crtc;
3912
3913 WARN(!crtc->enabled, "crtc not enabled\n");
3914 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3915 WARN(pipe != to_intel_crtc(crtc)->pipe,
3916 "encoder active on the wrong pipe\n");
3917 }
79e53945
JB		 3918}
3919
5ab432ef
DV		 3920/* Even simpler default implementation, if there's really no special case to
3921 * consider. */
3922void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3923{
5ab432ef 3924 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3925
5ab432ef
DV		 3926 /* All the simple cases only support two dpms states. */
3927 if (mode != DRM_MODE_DPMS_ON)
3928 mode = DRM_MODE_DPMS_OFF;
d4270e57 3929
5ab432ef
DV		 3930 if (mode == connector->dpms)
3931 return;
3932
3933 connector->dpms = mode;
3934
3935 /* Only need to change hw state when actually enabled */
3936 if (encoder->base.crtc)
3937 intel_encoder_dpms(encoder, mode);
3938 else
8af6cf88 3939 WARN_ON(encoder->connectors_active != false);
0a91ca29 3940
b980514c 3941 intel_modeset_check_state(connector->dev);
79e53945
JB		 3942}
3943
f0947c37
DV		 3944/* Simple connector->get_hw_state implementation for encoders that support only
3945 * one connector and no cloning and hence the encoder state determines the state
3946 * of the connector. */
3947bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3948{
24929352 3949 enum pipe pipe = 0;
f0947c37 3950 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3951
f0947c37 3952 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3953}
3954
1857e1da
DV		 3955static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3956 struct intel_crtc_config *pipe_config)
3957{
3958 struct drm_i915_private *dev_priv = dev->dev_private;
3959 struct intel_crtc *pipe_B_crtc =
3960 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3961
3962 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3963 pipe_name(pipe), pipe_config->fdi_lanes);
3964 if (pipe_config->fdi_lanes > 4) {
3965 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3966 pipe_name(pipe), pipe_config->fdi_lanes);
3967 return false;
3968 }
3969
3970 if (IS_HASWELL(dev)) {
3971 if (pipe_config->fdi_lanes > 2) {
3972 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3973 pipe_config->fdi_lanes);
3974 return false;
3975 } else {
3976 return true;
3977 }
3978 }
3979
3980 if (INTEL_INFO(dev)->num_pipes == 2)
3981 return true;
3982
3983 /* Ivybridge 3 pipe is really complicated */
3984 switch (pipe) {
3985 case PIPE_A:
3986 return true;
3987 case PIPE_B:
3988 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3989 pipe_config->fdi_lanes > 2) {
3990 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3991 pipe_name(pipe), pipe_config->fdi_lanes);
3992 return false;
3993 }
3994 return true;
3995 case PIPE_C:
1e833f40 3996 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 3997 pipe_B_crtc->config.fdi_lanes <= 2) {
3998 if (pipe_config->fdi_lanes > 2) {
3999 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4000 pipe_name(pipe), pipe_config->fdi_lanes);
4001 return false;
4002 }
4003 } else {
4004 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4005 return false;
4006 }
4007 return true;
4008 default:
4009 BUG();
4010 }
4011}
4012
e29c22c0
DV		 4013#define RETRY 1
4014static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4015 struct intel_crtc_config *pipe_config)
877d48d5 4016{
1857e1da 4017 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4018 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4019 int lane, link_bw, fdi_dotclock;
e29c22c0 4020 bool setup_ok, needs_recompute = false;
877d48d5 4021
e29c22c0 4022retry:
877d48d5
DV		 4023 /* FDI is a binary signal running at ~2.7GHz, encoding
4024 * each output octet as 10 bits. The actual frequency
4025 * is stored as a divider into a 100MHz clock, and the
4026 * mode pixel clock is stored in units of 1KHz.
4027 * Hence the bw of each lane in terms of the mode signal
4028 * is:
4029 */
4030 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4031
ff9a6750 4032 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4033 fdi_dotclock /= pipe_config->pixel_multiplier;
2bd89a07
DV		 4034
4035 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4036 pipe_config->pipe_bpp);
4037
4038 pipe_config->fdi_lanes = lane;
4039
2bd89a07 4040 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4041 link_bw, &pipe_config->fdi_m_n);
1857e1da 4042
e29c22c0
DV		 4043 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4044 intel_crtc->pipe, pipe_config);
4045 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4046 pipe_config->pipe_bpp -= 2*3;
4047 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4048 pipe_config->pipe_bpp);
4049 needs_recompute = true;
4050 pipe_config->bw_constrained = true;
4051
4052 goto retry;
4053 }
4054
4055 if (needs_recompute)
4056 return RETRY;
4057
4058 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4059}
4060
42db64ef
PZ		 4061static void hsw_compute_ips_config(struct intel_crtc *crtc,
4062 struct intel_crtc_config *pipe_config)
4063{
3c4ca58c
PZ		 4064 pipe_config->ips_enabled = i915_enable_ips &&
4065 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4066 pipe_config->pipe_bpp == 24;
4067}
4068
e29c22c0
DV		 4069static int intel_crtc_compute_config(struct drm_crtc *crtc,
4070 struct intel_crtc_config *pipe_config)
79e53945 4071{
2c07245f 4072 struct drm_device *dev = crtc->dev;
b8cecdf5 4073 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
42db64ef 4074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
89749350 4075
bad720ff 4076 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4077 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4078 if (pipe_config->requested_mode.clock * 3
4079 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4080 return -EINVAL;
2c07245f 4081 }
89749350 4082
f9bef081
DV		 4083 /* All interlaced capable intel hw wants timings in frames. Note though
4084 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4085 * timings, so we need to be careful not to clobber these.*/
7ae89233 4086 if (!pipe_config->timings_set)
f9bef081 4087 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4088
8693a824
DL		 4089 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4090 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4091 */
4092 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4093 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4094 return -EINVAL;
44f46b42 4095
bd080ee5 4096 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4097 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4098 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4099 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4100 * for lvds. */
4101 pipe_config->pipe_bpp = 8*3;
4102 }
4103
42db64ef
PZ		 4104 if (IS_HASWELL(dev))
4105 hsw_compute_ips_config(intel_crtc, pipe_config);
4106
877d48d5 4107 if (pipe_config->has_pch_encoder)
42db64ef 4108 return ironlake_fdi_compute_config(intel_crtc, pipe_config);
877d48d5 4109
e29c22c0 4110 return 0;
79e53945
JB		 4111}
4112
25eb05fc
JB		 4113static int valleyview_get_display_clock_speed(struct drm_device *dev)
4114{
4115 return 400000; /* FIXME */
4116}
4117
e70236a8
JB		 4118static int i945_get_display_clock_speed(struct drm_device *dev)
4119{
4120 return 400000;
4121}
79e53945 4122
e70236a8 4123static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4124{
e70236a8
JB		 4125 return 333000;
4126}
79e53945 4127
e70236a8
JB		 4128static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4129{
4130 return 200000;
4131}
79e53945 4132
e70236a8
JB		 4133static int i915gm_get_display_clock_speed(struct drm_device *dev)
4134{
4135 u16 gcfgc = 0;
79e53945 4136
e70236a8
JB		 4137 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4138
4139 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4140 return 133000;
4141 else {
4142 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4143 case GC_DISPLAY_CLOCK_333_MHZ:
4144 return 333000;
4145 default:
4146 case GC_DISPLAY_CLOCK_190_200_MHZ:
4147 return 190000;
79e53945 4148 }
e70236a8
JB		 4149 }
4150}
4151
4152static int i865_get_display_clock_speed(struct drm_device *dev)
4153{
4154 return 266000;
4155}
4156
4157static int i855_get_display_clock_speed(struct drm_device *dev)
4158{
4159 u16 hpllcc = 0;
4160 /* Assume that the hardware is in the high speed state. This
4161 * should be the default.
4162 */
4163 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4164 case GC_CLOCK_133_200:
4165 case GC_CLOCK_100_200:
4166 return 200000;
4167 case GC_CLOCK_166_250:
4168 return 250000;
4169 case GC_CLOCK_100_133:
79e53945 4170 return 133000;
e70236a8 4171 }
79e53945 4172
e70236a8
JB		 4173 /* Shouldn't happen */
4174 return 0;
4175}
79e53945 4176
e70236a8
JB		 4177static int i830_get_display_clock_speed(struct drm_device *dev)
4178{
4179 return 133000;
79e53945
JB		 4180}
4181
2c07245f 4182static void
a65851af 4183intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4184{
a65851af
VS		 4185 while (*num > DATA_LINK_M_N_MASK ||
4186 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4187 *num >>= 1;
4188 *den >>= 1;
4189 }
4190}
4191
a65851af
VS		 4192static void compute_m_n(unsigned int m, unsigned int n,
4193 uint32_t *ret_m, uint32_t *ret_n)
4194{
4195 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4196 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4197 intel_reduce_m_n_ratio(ret_m, ret_n);
4198}
4199
e69d0bc1
DV		 4200void
4201intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4202 int pixel_clock, int link_clock,
4203 struct intel_link_m_n *m_n)
2c07245f 4204{
e69d0bc1 4205 m_n->tu = 64;
a65851af
VS		 4206
4207 compute_m_n(bits_per_pixel * pixel_clock,
4208 link_clock * nlanes * 8,
4209 &m_n->gmch_m, &m_n->gmch_n);
4210
4211 compute_m_n(pixel_clock, link_clock,
4212 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4213}
4214
a7615030
CW		 4215static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4216{
72bbe58c
KP		 4217 if (i915_panel_use_ssc >= 0)
4218 return i915_panel_use_ssc != 0;
41aa3448 4219 return dev_priv->vbt.lvds_use_ssc
435793df 4220 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4221}
4222
a0c4da24
JB		 4223static int vlv_get_refclk(struct drm_crtc *crtc)
4224{
4225 struct drm_device *dev = crtc->dev;
4226 struct drm_i915_private *dev_priv = dev->dev_private;
4227 int refclk = 27000; /* for DP & HDMI */
4228
4229 return 100000; /* only one validated so far */
4230
4231 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4232 refclk = 96000;
4233 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4234 if (intel_panel_use_ssc(dev_priv))
4235 refclk = 100000;
4236 else
4237 refclk = 96000;
4238 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4239 refclk = 100000;
4240 }
4241
4242 return refclk;
4243}
4244
c65d77d8
JB		 4245static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4246{
4247 struct drm_device *dev = crtc->dev;
4248 struct drm_i915_private *dev_priv = dev->dev_private;
4249 int refclk;
4250
a0c4da24
JB		 4251 if (IS_VALLEYVIEW(dev)) {
4252 refclk = vlv_get_refclk(crtc);
4253 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4254 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4255 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4256 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4257 refclk / 1000);
4258 } else if (!IS_GEN2(dev)) {
4259 refclk = 96000;
4260 } else {
4261 refclk = 48000;
4262 }
4263
4264 return refclk;
4265}
4266
7429e9d4
DV		 4267static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4268{
4269 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4270}
4271
4272static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4273{
4274 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4275}
4276
f47709a9 4277static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4278 intel_clock_t *reduced_clock)
4279{
f47709a9 4280 struct drm_device *dev = crtc->base.dev;
a7516a05 4281 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4282 int pipe = crtc->pipe;
a7516a05
JB		 4283 u32 fp, fp2 = 0;
4284
4285 if (IS_PINEVIEW(dev)) {
7429e9d4 4286 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4287 if (reduced_clock)
7429e9d4 4288 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4289 } else {
7429e9d4 4290 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4291 if (reduced_clock)
7429e9d4 4292 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4293 }
4294
4295 I915_WRITE(FP0(pipe), fp);
4296
f47709a9
DV		 4297 crtc->lowfreq_avail = false;
4298 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4299 reduced_clock && i915_powersave) {
4300 I915_WRITE(FP1(pipe), fp2);
f47709a9 4301 crtc->lowfreq_avail = true;
a7516a05
JB		 4302 } else {
4303 I915_WRITE(FP1(pipe), fp);
4304 }
4305}
4306
89b667f8
JB		 4307static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4308{
4309 u32 reg_val;
4310
4311 /*
4312 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4313 * and set it to a reasonable value instead.
4314 */
ae99258f 4315 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4316 reg_val &= 0xffffff00;
4317 reg_val |= 0x00000030;
ae99258f 4318 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4319
ae99258f 4320 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4321 reg_val &= 0x8cffffff;
4322 reg_val = 0x8c000000;
ae99258f 4323 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4324
ae99258f 4325 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4326 reg_val &= 0xffffff00;
ae99258f 4327 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4328
ae99258f 4329 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4330 reg_val &= 0x00ffffff;
4331 reg_val |= 0xb0000000;
ae99258f 4332 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4333}
4334
b551842d
DV		 4335static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4336 struct intel_link_m_n *m_n)
4337{
4338 struct drm_device *dev = crtc->base.dev;
4339 struct drm_i915_private *dev_priv = dev->dev_private;
4340 int pipe = crtc->pipe;
4341
e3b95f1e
DV		 4342 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4343 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4344 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4345 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4346}
4347
4348static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4349 struct intel_link_m_n *m_n)
4350{
4351 struct drm_device *dev = crtc->base.dev;
4352 struct drm_i915_private *dev_priv = dev->dev_private;
4353 int pipe = crtc->pipe;
4354 enum transcoder transcoder = crtc->config.cpu_transcoder;
4355
4356 if (INTEL_INFO(dev)->gen >= 5) {
4357 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4358 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4359 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4360 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4361 } else {
e3b95f1e
DV		 4362 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4363 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4364 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4365 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4366 }
4367}
4368
03afc4a2
DV		 4369static void intel_dp_set_m_n(struct intel_crtc *crtc)
4370{
4371 if (crtc->config.has_pch_encoder)
4372 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4373 else
4374 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4375}
4376
f47709a9 4377static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4378{
f47709a9 4379 struct drm_device *dev = crtc->base.dev;
a0c4da24 4380 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8 4381 struct intel_encoder *encoder;
f47709a9 4382 int pipe = crtc->pipe;
89b667f8 4383 u32 dpll, mdiv;
a0c4da24 4384 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4385 bool is_hdmi;
198a037f 4386 u32 coreclk, reg_val, dpll_md;
a0c4da24 4387
09153000
DV		 4388 mutex_lock(&dev_priv->dpio_lock);
4389
89b667f8 4390 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4391
f47709a9
DV		 4392 bestn = crtc->config.dpll.n;
4393 bestm1 = crtc->config.dpll.m1;
4394 bestm2 = crtc->config.dpll.m2;
4395 bestp1 = crtc->config.dpll.p1;
4396 bestp2 = crtc->config.dpll.p2;
a0c4da24 4397
89b667f8
JB		 4398 /* See eDP HDMI DPIO driver vbios notes doc */
4399
4400 /* PLL B needs special handling */
4401 if (pipe)
4402 vlv_pllb_recal_opamp(dev_priv);
4403
4404 /* Set up Tx target for periodic Rcomp update */
ae99258f 4405 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4406
4407 /* Disable target IRef on PLL */
ae99258f 4408 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4409 reg_val &= 0x00ffffff;
ae99258f 4410 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4411
4412 /* Disable fast lock */
ae99258f 4413 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4414
4415 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4416 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4417 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4418 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4419 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4420
4421 /*
4422 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4423 * but we don't support that).
4424 * Note: don't use the DAC post divider as it seems unstable.
4425 */
4426 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4427 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4428
89b667f8 4429 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4430 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4431
89b667f8 4432 /* Set HBR and RBR LPF coefficients */
ff9a6750 4433 if (crtc->config.port_clock == 162000 ||
89b667f8 4434 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
ae99258f 4435 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4436 0x005f0021);
4437 else
ae99258f 4438 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4439 0x00d0000f);
4440
4441 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4442 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4443 /* Use SSC source */
4444 if (!pipe)
ae99258f 4445 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4446 0x0df40000);
4447 else
ae99258f 4448 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4449 0x0df70000);
4450 } else { /* HDMI or VGA */
4451 /* Use bend source */
4452 if (!pipe)
ae99258f 4453 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4454 0x0df70000);
4455 else
ae99258f 4456 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4457 0x0df40000);
4458 }
a0c4da24 4459
ae99258f 4460 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4461 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4462 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4463 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4464 coreclk |= 0x01000000;
ae99258f 4465 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4466
ae99258f 4467 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4468
89b667f8
JB		 4469 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4470 if (encoder->pre_pll_enable)
4471 encoder->pre_pll_enable(encoder);
2a8f64ca 4472
89b667f8
JB		 4473 /* Enable DPIO clock input */
4474 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4475 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4476 if (pipe)
4477 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4478
89b667f8 4479 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4480 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4481 POSTING_READ(DPLL(pipe));
4482 udelay(150);
a0c4da24 4483
89b667f8
JB		 4484 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4485 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4486
ef1b460d
DV		 4487 dpll_md = (crtc->config.pixel_multiplier - 1)
4488 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f
DV		 4489 I915_WRITE(DPLL_MD(pipe), dpll_md);
4490 POSTING_READ(DPLL_MD(pipe));
f47709a9 4491
89b667f8
JB		 4492 if (crtc->config.has_dp_encoder)
4493 intel_dp_set_m_n(crtc);
09153000
DV		 4494
4495 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4496}
4497
f47709a9
DV		 4498static void i9xx_update_pll(struct intel_crtc *crtc,
4499 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4500 int num_connectors)
4501{
f47709a9 4502 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4503 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4504 struct intel_encoder *encoder;
f47709a9 4505 int pipe = crtc->pipe;
eb1cbe48
DV		 4506 u32 dpll;
4507 bool is_sdvo;
f47709a9 4508 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4509
f47709a9 4510 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4511
f47709a9
DV		 4512 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4513 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4514
4515 dpll = DPLL_VGA_MODE_DIS;
4516
f47709a9 4517 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4518 dpll |= DPLLB_MODE_LVDS;
4519 else
4520 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4521
ef1b460d 4522 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4523 dpll |= (crtc->config.pixel_multiplier - 1)
4524 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4525 }
198a037f
DV		 4526
4527 if (is_sdvo)
4528 dpll |= DPLL_DVO_HIGH_SPEED;
4529
f47709a9 4530 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4531 dpll |= DPLL_DVO_HIGH_SPEED;
4532
4533 /* compute bitmask from p1 value */
4534 if (IS_PINEVIEW(dev))
4535 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4536 else {
4537 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4538 if (IS_G4X(dev) && reduced_clock)
4539 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4540 }
4541 switch (clock->p2) {
4542 case 5:
4543 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4544 break;
4545 case 7:
4546 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4547 break;
4548 case 10:
4549 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4550 break;
4551 case 14:
4552 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4553 break;
4554 }
4555 if (INTEL_INFO(dev)->gen >= 4)
4556 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4557
09ede541 4558 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4559 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4560 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4561 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4562 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4563 else
4564 dpll |= PLL_REF_INPUT_DREFCLK;
4565
4566 dpll |= DPLL_VCO_ENABLE;
4567 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4568 POSTING_READ(DPLL(pipe));
4569 udelay(150);
4570
f47709a9 4571 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4572 if (encoder->pre_pll_enable)
4573 encoder->pre_pll_enable(encoder);
eb1cbe48 4574
f47709a9
DV		 4575 if (crtc->config.has_dp_encoder)
4576 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4577
4578 I915_WRITE(DPLL(pipe), dpll);
4579
4580 /* Wait for the clocks to stabilize. */
4581 POSTING_READ(DPLL(pipe));
4582 udelay(150);
4583
4584 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4585 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4586 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f 4587 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4588 } else {
4589 /* The pixel multiplier can only be updated once the
4590 * DPLL is enabled and the clocks are stable.
4591 *
4592 * So write it again.
4593 */
4594 I915_WRITE(DPLL(pipe), dpll);
4595 }
4596}
4597
f47709a9 4598static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4599 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4600 int num_connectors)
4601{
f47709a9 4602 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4603 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4604 struct intel_encoder *encoder;
f47709a9 4605 int pipe = crtc->pipe;
eb1cbe48 4606 u32 dpll;
f47709a9 4607 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4608
f47709a9 4609 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4610
eb1cbe48
DV		 4611 dpll = DPLL_VGA_MODE_DIS;
4612
f47709a9 4613 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4614 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4615 } else {
4616 if (clock->p1 == 2)
4617 dpll |= PLL_P1_DIVIDE_BY_TWO;
4618 else
4619 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4620 if (clock->p2 == 4)
4621 dpll |= PLL_P2_DIVIDE_BY_4;
4622 }
4623
f47709a9 4624 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4625 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4626 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4627 else
4628 dpll |= PLL_REF_INPUT_DREFCLK;
4629
4630 dpll |= DPLL_VCO_ENABLE;
4631 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4632 POSTING_READ(DPLL(pipe));
4633 udelay(150);
4634
f47709a9 4635 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4636 if (encoder->pre_pll_enable)
4637 encoder->pre_pll_enable(encoder);
eb1cbe48 4638
5b5896e4
DV		 4639 I915_WRITE(DPLL(pipe), dpll);
4640
4641 /* Wait for the clocks to stabilize. */
4642 POSTING_READ(DPLL(pipe));
4643 udelay(150);
4644
eb1cbe48
DV		 4645 /* The pixel multiplier can only be updated once the
4646 * DPLL is enabled and the clocks are stable.
4647 *
4648 * So write it again.
4649 */
4650 I915_WRITE(DPLL(pipe), dpll);
4651}
4652
8a654f3b 4653static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4654{
4655 struct drm_device *dev = intel_crtc->base.dev;
4656 struct drm_i915_private *dev_priv = dev->dev_private;
4657 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4658 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4659 struct drm_display_mode *adjusted_mode =
4660 &intel_crtc->config.adjusted_mode;
4661 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4662 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4663
4664 /* We need to be careful not to changed the adjusted mode, for otherwise
4665 * the hw state checker will get angry at the mismatch. */
4666 crtc_vtotal = adjusted_mode->crtc_vtotal;
4667 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4668
4669 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4670 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4671 crtc_vtotal -= 1;
4672 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4673 vsyncshift = adjusted_mode->crtc_hsync_start
4674 - adjusted_mode->crtc_htotal / 2;
4675 } else {
4676 vsyncshift = 0;
4677 }
4678
4679 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4680 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4681
fe2b8f9d 4682 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4683 (adjusted_mode->crtc_hdisplay - 1) |
4684 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4685 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4686 (adjusted_mode->crtc_hblank_start - 1) |
4687 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4688 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4689 (adjusted_mode->crtc_hsync_start - 1) |
4690 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4691
fe2b8f9d 4692 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4693 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4694 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4695 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4696 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4697 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4698 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4699 (adjusted_mode->crtc_vsync_start - 1) |
4700 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4701
b5e508d4
PZ		 4702 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4703 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4704 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4705 * bits. */
4706 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4707 (pipe == PIPE_B || pipe == PIPE_C))
4708 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4709
b0e77b9c
PZ		 4710 /* pipesrc controls the size that is scaled from, which should
4711 * always be the user's requested size.
4712 */
4713 I915_WRITE(PIPESRC(pipe),
4714 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4715}
4716
1bd1bd80
DV		 4717static void intel_get_pipe_timings(struct intel_crtc *crtc,
4718 struct intel_crtc_config *pipe_config)
4719{
4720 struct drm_device *dev = crtc->base.dev;
4721 struct drm_i915_private *dev_priv = dev->dev_private;
4722 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4723 uint32_t tmp;
4724
4725 tmp = I915_READ(HTOTAL(cpu_transcoder));
4726 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4727 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4728 tmp = I915_READ(HBLANK(cpu_transcoder));
4729 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4730 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4731 tmp = I915_READ(HSYNC(cpu_transcoder));
4732 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4733 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4734
4735 tmp = I915_READ(VTOTAL(cpu_transcoder));
4736 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4737 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4738 tmp = I915_READ(VBLANK(cpu_transcoder));
4739 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4740 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4741 tmp = I915_READ(VSYNC(cpu_transcoder));
4742 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4743 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4744
4745 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4746 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4747 pipe_config->adjusted_mode.crtc_vtotal += 1;
4748 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4749 }
4750
4751 tmp = I915_READ(PIPESRC(crtc->pipe));
4752 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4753 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4754}
4755
84b046f3
DV		 4756static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4757{
4758 struct drm_device *dev = intel_crtc->base.dev;
4759 struct drm_i915_private *dev_priv = dev->dev_private;
4760 uint32_t pipeconf;
4761
4762 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4763
4764 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4765 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4766 * core speed.
4767 *
4768 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4769 * pipe == 0 check?
4770 */
4771 if (intel_crtc->config.requested_mode.clock >
4772 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4773 pipeconf |= PIPECONF_DOUBLE_WIDE;
4774 else
4775 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4776 }
4777
ff9ce46e
DV		 4778 /* only g4x and later have fancy bpc/dither controls */
4779 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4780 pipeconf &= ~(PIPECONF_BPC_MASK |
4781 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4782
4783 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4784 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4785 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4786 PIPECONF_DITHER_TYPE_SP;
84b046f3 4787
ff9ce46e
DV		 4788 switch (intel_crtc->config.pipe_bpp) {
4789 case 18:
4790 pipeconf |= PIPECONF_6BPC;
4791 break;
4792 case 24:
4793 pipeconf |= PIPECONF_8BPC;
4794 break;
4795 case 30:
4796 pipeconf |= PIPECONF_10BPC;
4797 break;
4798 default:
4799 /* Case prevented by intel_choose_pipe_bpp_dither. */
4800 BUG();
84b046f3
DV		 4801 }
4802 }
4803
4804 if (HAS_PIPE_CXSR(dev)) {
4805 if (intel_crtc->lowfreq_avail) {
4806 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4807 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4808 } else {
4809 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4810 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4811 }
4812 }
4813
4814 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4815 if (!IS_GEN2(dev) &&
4816 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4817 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4818 else
4819 pipeconf |= PIPECONF_PROGRESSIVE;
4820
9c8e09b7
VS		 4821 if (IS_VALLEYVIEW(dev)) {
4822 if (intel_crtc->config.limited_color_range)
4823 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4824 else
4825 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4826 }
4827
84b046f3
DV		 4828 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4829 POSTING_READ(PIPECONF(intel_crtc->pipe));
4830}
4831
f564048e 4832static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4833 int x, int y,
94352cf9 4834 struct drm_framebuffer *fb)
79e53945
JB		 4835{
4836 struct drm_device *dev = crtc->dev;
4837 struct drm_i915_private *dev_priv = dev->dev_private;
4838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4839 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4840 int pipe = intel_crtc->pipe;
80824003 4841 int plane = intel_crtc->plane;
c751ce4f 4842 int refclk, num_connectors = 0;
652c393a 4843 intel_clock_t clock, reduced_clock;
84b046f3 4844 u32 dspcntr;
a16af721
DV		 4845 bool ok, has_reduced_clock = false;
4846 bool is_lvds = false;
5eddb70b 4847 struct intel_encoder *encoder;
d4906093 4848 const intel_limit_t *limit;
5c3b82e2 4849 int ret;
79e53945 4850
6c2b7c12 4851 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4852 switch (encoder->type) {
79e53945
JB		 4853 case INTEL_OUTPUT_LVDS:
4854 is_lvds = true;
4855 break;
79e53945 4856 }
43565a06 4857
c751ce4f 4858 num_connectors++;
79e53945
JB		 4859 }
4860
c65d77d8 4861 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4862
d4906093
ML		 4863 /*
4864 * Returns a set of divisors for the desired target clock with the given
4865 * refclk, or FALSE. The returned values represent the clock equation:
4866 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4867 */
1b894b59 4868 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4869 ok = dev_priv->display.find_dpll(limit, crtc,
4870 intel_crtc->config.port_clock,
ee9300bb
DV		 4871 refclk, NULL, &clock);
4872 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4873 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4874 return -EINVAL;
79e53945
JB		 4875 }
4876
cda4b7d3 4877 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4878 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4879
ddc9003c 4880 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4881 /*
4882 * Ensure we match the reduced clock's P to the target clock.
4883 * If the clocks don't match, we can't switch the display clock
4884 * by using the FP0/FP1. In such case we will disable the LVDS
4885 * downclock feature.
4886 */
ee9300bb
DV		 4887 has_reduced_clock =
4888 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4889 dev_priv->lvds_downclock,
ee9300bb 4890 refclk, &clock,
5eddb70b 4891 &reduced_clock);
7026d4ac 4892 }
f47709a9
DV		 4893 /* Compat-code for transition, will disappear. */
4894 if (!intel_crtc->config.clock_set) {
4895 intel_crtc->config.dpll.n = clock.n;
4896 intel_crtc->config.dpll.m1 = clock.m1;
4897 intel_crtc->config.dpll.m2 = clock.m2;
4898 intel_crtc->config.dpll.p1 = clock.p1;
4899 intel_crtc->config.dpll.p2 = clock.p2;
4900 }
7026d4ac 4901
eb1cbe48 4902 if (IS_GEN2(dev))
8a654f3b 4903 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4904 has_reduced_clock ? &reduced_clock : NULL,
4905 num_connectors);
a0c4da24 4906 else if (IS_VALLEYVIEW(dev))
f47709a9 4907 vlv_update_pll(intel_crtc);
79e53945 4908 else
f47709a9 4909 i9xx_update_pll(intel_crtc,
eb1cbe48 4910 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4911 num_connectors);
79e53945 4912
79e53945
JB		 4913 /* Set up the display plane register */
4914 dspcntr = DISPPLANE_GAMMA_ENABLE;
4915
da6ecc5d
JB		 4916 if (!IS_VALLEYVIEW(dev)) {
4917 if (pipe == 0)
4918 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4919 else
4920 dspcntr |= DISPPLANE_SEL_PIPE_B;
4921 }
79e53945 4922
8a654f3b 4923 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4924
4925 /* pipesrc and dspsize control the size that is scaled from,
4926 * which should always be the user's requested size.
79e53945 4927 */
929c77fb
EA		 4928 I915_WRITE(DSPSIZE(plane),
4929 ((mode->vdisplay - 1) << 16) |
4930 (mode->hdisplay - 1));
4931 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4932
84b046f3
DV		 4933 i9xx_set_pipeconf(intel_crtc);
4934
f564048e
EA		 4935 I915_WRITE(DSPCNTR(plane), dspcntr);
4936 POSTING_READ(DSPCNTR(plane));
4937
94352cf9 4938 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4939
4940 intel_update_watermarks(dev);
4941
f564048e
EA		 4942 return ret;
4943}
4944
2fa2fe9a
DV		 4945static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4946 struct intel_crtc_config *pipe_config)
4947{
4948 struct drm_device *dev = crtc->base.dev;
4949 struct drm_i915_private *dev_priv = dev->dev_private;
4950 uint32_t tmp;
4951
4952 tmp = I915_READ(PFIT_CONTROL);
4953
4954 if (INTEL_INFO(dev)->gen < 4) {
4955 if (crtc->pipe != PIPE_B)
4956 return;
4957
4958 /* gen2/3 store dither state in pfit control, needs to match */
4959 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4960 } else {
4961 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4962 return;
4963 }
4964
4965 if (!(tmp & PFIT_ENABLE))
4966 return;
4967
4968 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4969 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4970 if (INTEL_INFO(dev)->gen < 5)
4971 pipe_config->gmch_pfit.lvds_border_bits =
4972 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4973}
4974
0e8ffe1b
DV		 4975static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4976 struct intel_crtc_config *pipe_config)
4977{
4978 struct drm_device *dev = crtc->base.dev;
4979 struct drm_i915_private *dev_priv = dev->dev_private;
4980 uint32_t tmp;
4981
eccb140b
DV		 4982 pipe_config->cpu_transcoder = crtc->pipe;
4983
0e8ffe1b
DV		 4984 tmp = I915_READ(PIPECONF(crtc->pipe));
4985 if (!(tmp & PIPECONF_ENABLE))
4986 return false;
4987
1bd1bd80
DV		 4988 intel_get_pipe_timings(crtc, pipe_config);
4989
2fa2fe9a
DV		 4990 i9xx_get_pfit_config(crtc, pipe_config);
4991
0e8ffe1b
DV		 4992 return true;
4993}
4994
dde86e2d 4995static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4996{
4997 struct drm_i915_private *dev_priv = dev->dev_private;
4998 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4999 struct intel_encoder *encoder;
74cfd7ac 5000 u32 val, final;
13d83a67 5001 bool has_lvds = false;
199e5d79 5002 bool has_cpu_edp = false;
199e5d79 5003 bool has_panel = false;
99eb6a01
KP		 5004 bool has_ck505 = false;
5005 bool can_ssc = false;
13d83a67
JB		 5006
5007 /* We need to take the global config into account */
199e5d79
KP		 5008 list_for_each_entry(encoder, &mode_config->encoder_list,
5009 base.head) {
5010 switch (encoder->type) {
5011 case INTEL_OUTPUT_LVDS:
5012 has_panel = true;
5013 has_lvds = true;
5014 break;
5015 case INTEL_OUTPUT_EDP:
5016 has_panel = true;
2de6905f 5017 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5018 has_cpu_edp = true;
5019 break;
13d83a67
JB		 5020 }
5021 }
5022
99eb6a01 5023 if (HAS_PCH_IBX(dev)) {
41aa3448 5024 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5025 can_ssc = has_ck505;
5026 } else {
5027 has_ck505 = false;
5028 can_ssc = true;
5029 }
5030
2de6905f
ID		 5031 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5032 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5033
5034 /* Ironlake: try to setup display ref clock before DPLL
5035 * enabling. This is only under driver's control after
5036 * PCH B stepping, previous chipset stepping should be
5037 * ignoring this setting.
5038 */
74cfd7ac
CW		 5039 val = I915_READ(PCH_DREF_CONTROL);
5040
5041 /* As we must carefully and slowly disable/enable each source in turn,
5042 * compute the final state we want first and check if we need to
5043 * make any changes at all.
5044 */
5045 final = val;
5046 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5047 if (has_ck505)
5048 final |= DREF_NONSPREAD_CK505_ENABLE;
5049 else
5050 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5051
5052 final &= ~DREF_SSC_SOURCE_MASK;
5053 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5054 final &= ~DREF_SSC1_ENABLE;
5055
5056 if (has_panel) {
5057 final |= DREF_SSC_SOURCE_ENABLE;
5058
5059 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5060 final |= DREF_SSC1_ENABLE;
5061
5062 if (has_cpu_edp) {
5063 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5064 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5065 else
5066 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5067 } else
5068 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5069 } else {
5070 final |= DREF_SSC_SOURCE_DISABLE;
5071 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5072 }
5073
5074 if (final == val)
5075 return;
5076
13d83a67 5077 /* Always enable nonspread source */
74cfd7ac 5078 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5079
99eb6a01 5080 if (has_ck505)
74cfd7ac 5081 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5082 else
74cfd7ac 5083 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5084
199e5d79 5085 if (has_panel) {
74cfd7ac
CW		 5086 val &= ~DREF_SSC_SOURCE_MASK;
5087 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5088
199e5d79 5089 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5090 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5091 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5092 val |= DREF_SSC1_ENABLE;
e77166b5 5093 } else
74cfd7ac 5094 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5095
5096 /* Get SSC going before enabling the outputs */
74cfd7ac 5097 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5098 POSTING_READ(PCH_DREF_CONTROL);
5099 udelay(200);
5100
74cfd7ac 5101 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5102
5103 /* Enable CPU source on CPU attached eDP */
199e5d79 5104 if (has_cpu_edp) {
99eb6a01 5105 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5106 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5107 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5108 }
13d83a67 5109 else
74cfd7ac 5110 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5111 } else
74cfd7ac 5112 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5113
74cfd7ac 5114 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5115 POSTING_READ(PCH_DREF_CONTROL);
5116 udelay(200);
5117 } else {
5118 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5119
74cfd7ac 5120 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5121
5122 /* Turn off CPU output */
74cfd7ac 5123 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5124
74cfd7ac 5125 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5126 POSTING_READ(PCH_DREF_CONTROL);
5127 udelay(200);
5128
5129 /* Turn off the SSC source */
74cfd7ac
CW		 5130 val &= ~DREF_SSC_SOURCE_MASK;
5131 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5132
5133 /* Turn off SSC1 */
74cfd7ac 5134 val &= ~DREF_SSC1_ENABLE;
199e5d79 5135
74cfd7ac 5136 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5137 POSTING_READ(PCH_DREF_CONTROL);
5138 udelay(200);
5139 }
74cfd7ac
CW		 5140
5141 BUG_ON(val != final);
13d83a67
JB		 5142}
5143
dde86e2d
PZ		 5144/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5145static void lpt_init_pch_refclk(struct drm_device *dev)
5146{
5147 struct drm_i915_private *dev_priv = dev->dev_private;
5148 struct drm_mode_config *mode_config = &dev->mode_config;
5149 struct intel_encoder *encoder;
5150 bool has_vga = false;
5151 bool is_sdv = false;
5152 u32 tmp;
5153
5154 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5155 switch (encoder->type) {
5156 case INTEL_OUTPUT_ANALOG:
5157 has_vga = true;
5158 break;
5159 }
5160 }
5161
5162 if (!has_vga)
5163 return;
5164
c00db246
DV		 5165 mutex_lock(&dev_priv->dpio_lock);
5166
dde86e2d
PZ		 5167 /* XXX: Rip out SDV support once Haswell ships for real. */
5168 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5169 is_sdv = true;
5170
5171 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5172 tmp &= ~SBI_SSCCTL_DISABLE;
5173 tmp |= SBI_SSCCTL_PATHALT;
5174 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5175
5176 udelay(24);
5177
5178 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5179 tmp &= ~SBI_SSCCTL_PATHALT;
5180 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5181
5182 if (!is_sdv) {
5183 tmp = I915_READ(SOUTH_CHICKEN2);
5184 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5185 I915_WRITE(SOUTH_CHICKEN2, tmp);
5186
5187 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5188 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5189 DRM_ERROR("FDI mPHY reset assert timeout\n");
5190
5191 tmp = I915_READ(SOUTH_CHICKEN2);
5192 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5193 I915_WRITE(SOUTH_CHICKEN2, tmp);
5194
5195 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5196 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5197 100))
5198 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5199 }
5200
5201 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5202 tmp &= ~(0xFF << 24);
5203 tmp |= (0x12 << 24);
5204 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5205
dde86e2d
PZ		 5206 if (is_sdv) {
5207 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5208 tmp |= 0x7FFF;
5209 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5210 }
5211
5212 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5213 tmp |= (1 << 11);
5214 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5215
5216 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5217 tmp |= (1 << 11);
5218 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5219
5220 if (is_sdv) {
5221 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5222 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5223 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5224
5225 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5226 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5227 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5228
5229 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5230 tmp |= (0x3F << 8);
5231 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5232
5233 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5234 tmp |= (0x3F << 8);
5235 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5236 }
5237
5238 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5239 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5240 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5241
5242 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5243 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5244 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5245
5246 if (!is_sdv) {
5247 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5248 tmp &= ~(7 << 13);
5249 tmp |= (5 << 13);
5250 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5251
5252 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5253 tmp &= ~(7 << 13);
5254 tmp |= (5 << 13);
5255 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5256 }
5257
5258 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5259 tmp &= ~0xFF;
5260 tmp |= 0x1C;
5261 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5262
5263 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5264 tmp &= ~0xFF;
5265 tmp |= 0x1C;
5266 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5267
5268 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5269 tmp &= ~(0xFF << 16);
5270 tmp |= (0x1C << 16);
5271 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5272
5273 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5274 tmp &= ~(0xFF << 16);
5275 tmp |= (0x1C << 16);
5276 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5277
5278 if (!is_sdv) {
5279 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5280 tmp |= (1 << 27);
5281 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5282
5283 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5284 tmp |= (1 << 27);
5285 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5286
5287 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5288 tmp &= ~(0xF << 28);
5289 tmp |= (4 << 28);
5290 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5291
5292 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5293 tmp &= ~(0xF << 28);
5294 tmp |= (4 << 28);
5295 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5296 }
5297
5298 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5299 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5300 tmp |= SBI_DBUFF0_ENABLE;
5301 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5302
5303 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5304}
5305
5306/*
5307 * Initialize reference clocks when the driver loads
5308 */
5309void intel_init_pch_refclk(struct drm_device *dev)
5310{
5311 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5312 ironlake_init_pch_refclk(dev);
5313 else if (HAS_PCH_LPT(dev))
5314 lpt_init_pch_refclk(dev);
5315}
5316
d9d444cb
JB		 5317static int ironlake_get_refclk(struct drm_crtc *crtc)
5318{
5319 struct drm_device *dev = crtc->dev;
5320 struct drm_i915_private *dev_priv = dev->dev_private;
5321 struct intel_encoder *encoder;
d9d444cb
JB		 5322 int num_connectors = 0;
5323 bool is_lvds = false;
5324
6c2b7c12 5325 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5326 switch (encoder->type) {
5327 case INTEL_OUTPUT_LVDS:
5328 is_lvds = true;
5329 break;
d9d444cb
JB		 5330 }
5331 num_connectors++;
5332 }
5333
5334 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5335 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5336 dev_priv->vbt.lvds_ssc_freq);
5337 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5338 }
5339
5340 return 120000;
5341}
5342
6ff93609 5343static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5344{
c8203565 5345 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5347 int pipe = intel_crtc->pipe;
c8203565
PZ		 5348 uint32_t val;
5349
5350 val = I915_READ(PIPECONF(pipe));
5351
dfd07d72 5352 val &= ~PIPECONF_BPC_MASK;
965e0c48 5353 switch (intel_crtc->config.pipe_bpp) {
c8203565 5354 case 18:
dfd07d72 5355 val |= PIPECONF_6BPC;
c8203565
PZ		 5356 break;
5357 case 24:
dfd07d72 5358 val |= PIPECONF_8BPC;
c8203565
PZ		 5359 break;
5360 case 30:
dfd07d72 5361 val |= PIPECONF_10BPC;
c8203565
PZ		 5362 break;
5363 case 36:
dfd07d72 5364 val |= PIPECONF_12BPC;
c8203565
PZ		 5365 break;
5366 default:
cc769b62
PZ		 5367 /* Case prevented by intel_choose_pipe_bpp_dither. */
5368 BUG();
c8203565
PZ		 5369 }
5370
5371 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5372 if (intel_crtc->config.dither)
c8203565
PZ		 5373 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5374
5375 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5376 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5377 val |= PIPECONF_INTERLACED_ILK;
5378 else
5379 val |= PIPECONF_PROGRESSIVE;
5380
50f3b016 5381 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5382 val |= PIPECONF_COLOR_RANGE_SELECT;
5383 else
5384 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5385
c8203565
PZ		 5386 I915_WRITE(PIPECONF(pipe), val);
5387 POSTING_READ(PIPECONF(pipe));
5388}
5389
86d3efce
VS		 5390/*
5391 * Set up the pipe CSC unit.
5392 *
5393 * Currently only full range RGB to limited range RGB conversion
5394 * is supported, but eventually this should handle various
5395 * RGB<->YCbCr scenarios as well.
5396 */
50f3b016 5397static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5398{
5399 struct drm_device *dev = crtc->dev;
5400 struct drm_i915_private *dev_priv = dev->dev_private;
5401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5402 int pipe = intel_crtc->pipe;
5403 uint16_t coeff = 0x7800; /* 1.0 */
5404
5405 /*
5406 * TODO: Check what kind of values actually come out of the pipe
5407 * with these coeff/postoff values and adjust to get the best
5408 * accuracy. Perhaps we even need to take the bpc value into
5409 * consideration.
5410 */
5411
50f3b016 5412 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5413 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5414
5415 /*
5416 * GY/GU and RY/RU should be the other way around according
5417 * to BSpec, but reality doesn't agree. Just set them up in
5418 * a way that results in the correct picture.
5419 */
5420 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5421 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5422
5423 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5424 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5425
5426 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5427 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5428
5429 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5430 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5431 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5432
5433 if (INTEL_INFO(dev)->gen > 6) {
5434 uint16_t postoff = 0;
5435
50f3b016 5436 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5437 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5438
5439 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5440 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5441 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5442
5443 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5444 } else {
5445 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5446
50f3b016 5447 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5448 mode |= CSC_BLACK_SCREEN_OFFSET;
5449
5450 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5451 }
5452}
5453
6ff93609 5454static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5455{
5456 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5458 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5459 uint32_t val;
5460
702e7a56 5461 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5462
5463 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5464 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5465 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5466
5467 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5468 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5469 val |= PIPECONF_INTERLACED_ILK;
5470 else
5471 val |= PIPECONF_PROGRESSIVE;
5472
702e7a56
PZ		 5473 I915_WRITE(PIPECONF(cpu_transcoder), val);
5474 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5475}
5476
6591c6e4 5477static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5478 intel_clock_t *clock,
5479 bool *has_reduced_clock,
5480 intel_clock_t *reduced_clock)
5481{
5482 struct drm_device *dev = crtc->dev;
5483 struct drm_i915_private *dev_priv = dev->dev_private;
5484 struct intel_encoder *intel_encoder;
5485 int refclk;
d4906093 5486 const intel_limit_t *limit;
a16af721 5487 bool ret, is_lvds = false;
79e53945 5488
6591c6e4
PZ		 5489 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5490 switch (intel_encoder->type) {
79e53945
JB		 5491 case INTEL_OUTPUT_LVDS:
5492 is_lvds = true;
5493 break;
79e53945
JB		 5494 }
5495 }
5496
d9d444cb 5497 refclk = ironlake_get_refclk(crtc);
79e53945 5498
d4906093
ML		 5499 /*
5500 * Returns a set of divisors for the desired target clock with the given
5501 * refclk, or FALSE. The returned values represent the clock equation:
5502 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5503 */
1b894b59 5504 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5505 ret = dev_priv->display.find_dpll(limit, crtc,
5506 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5507 refclk, NULL, clock);
6591c6e4
PZ		 5508 if (!ret)
5509 return false;
cda4b7d3 5510
ddc9003c 5511 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5512 /*
5513 * Ensure we match the reduced clock's P to the target clock.
5514 * If the clocks don't match, we can't switch the display clock
5515 * by using the FP0/FP1. In such case we will disable the LVDS
5516 * downclock feature.
5517 */
ee9300bb
DV		 5518 *has_reduced_clock =
5519 dev_priv->display.find_dpll(limit, crtc,
5520 dev_priv->lvds_downclock,
5521 refclk, clock,
5522 reduced_clock);
652c393a 5523 }
61e9653f 5524
6591c6e4
PZ		 5525 return true;
5526}
5527
01a415fd
DV		 5528static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5529{
5530 struct drm_i915_private *dev_priv = dev->dev_private;
5531 uint32_t temp;
5532
5533 temp = I915_READ(SOUTH_CHICKEN1);
5534 if (temp & FDI_BC_BIFURCATION_SELECT)
5535 return;
5536
5537 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5538 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5539
5540 temp |= FDI_BC_BIFURCATION_SELECT;
5541 DRM_DEBUG_KMS("enabling fdi C rx\n");
5542 I915_WRITE(SOUTH_CHICKEN1, temp);
5543 POSTING_READ(SOUTH_CHICKEN1);
5544}
5545
ebfd86fd
DV		 5546static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5547{
5548 struct drm_device *dev = intel_crtc->base.dev;
5549 struct drm_i915_private *dev_priv = dev->dev_private;
5550
5551 switch (intel_crtc->pipe) {
5552 case PIPE_A:
5553 break;
5554 case PIPE_B:
5555 if (intel_crtc->config.fdi_lanes > 2)
5556 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5557 else
5558 cpt_enable_fdi_bc_bifurcation(dev);
5559
5560 break;
5561 case PIPE_C:
01a415fd
DV		 5562 cpt_enable_fdi_bc_bifurcation(dev);
5563
ebfd86fd 5564 break;
01a415fd
DV		 5565 default:
5566 BUG();
5567 }
5568}
5569
d4b1931c
PZ		 5570int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5571{
5572 /*
5573 * Account for spread spectrum to avoid
5574 * oversubscribing the link. Max center spread
5575 * is 2.5%; use 5% for safety's sake.
5576 */
5577 u32 bps = target_clock * bpp * 21 / 20;
5578 return bps / (link_bw * 8) + 1;
5579}
5580
7429e9d4
DV		 5581static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5582{
5583 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5584}
5585
de13a2e3 5586static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5587 u32 *fp,
9a7c7890 5588 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5589{
de13a2e3 5590 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5591 struct drm_device *dev = crtc->dev;
5592 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5593 struct intel_encoder *intel_encoder;
5594 uint32_t dpll;
6cc5f341 5595 int factor, num_connectors = 0;
09ede541 5596 bool is_lvds = false, is_sdvo = false;
79e53945 5597
de13a2e3
PZ		 5598 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5599 switch (intel_encoder->type) {
79e53945
JB		 5600 case INTEL_OUTPUT_LVDS:
5601 is_lvds = true;
5602 break;
5603 case INTEL_OUTPUT_SDVO:
7d57382e 5604 case INTEL_OUTPUT_HDMI:
79e53945
JB		 5605 is_sdvo = true;
5606 break;
79e53945 5607 }
43565a06 5608
c751ce4f 5609 num_connectors++;
79e53945 5610 }
79e53945 5611
c1858123 5612 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5613 factor = 21;
5614 if (is_lvds) {
5615 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5616 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5617 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5618 factor = 25;
09ede541 5619 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5620 factor = 20;
c1858123 5621
7429e9d4 5622 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5623 *fp |= FP_CB_TUNE;
2c07245f 5624
9a7c7890
DV		 5625 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5626 *fp2 |= FP_CB_TUNE;
5627
5eddb70b 5628 dpll = 0;
2c07245f 5629
a07d6787
EA		 5630 if (is_lvds)
5631 dpll |= DPLLB_MODE_LVDS;
5632 else
5633 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5634
ef1b460d
DV		 5635 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5636 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5637
5638 if (is_sdvo)
5639 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5640 if (intel_crtc->config.has_dp_encoder)
a07d6787 5641 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5642
a07d6787 5643 /* compute bitmask from p1 value */
7429e9d4 5644 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5645 /* also FPA1 */
7429e9d4 5646 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5647
7429e9d4 5648 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5649 case 5:
5650 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5651 break;
5652 case 7:
5653 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5654 break;
5655 case 10:
5656 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5657 break;
5658 case 14:
5659 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5660 break;
79e53945
JB		 5661 }
5662
b4c09f3b 5663 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5664 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5665 else
5666 dpll |= PLL_REF_INPUT_DREFCLK;
5667
de13a2e3
PZ		 5668 return dpll;
5669}
5670
5671static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5672 int x, int y,
5673 struct drm_framebuffer *fb)
5674{
5675 struct drm_device *dev = crtc->dev;
5676 struct drm_i915_private *dev_priv = dev->dev_private;
5677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5678 int pipe = intel_crtc->pipe;
5679 int plane = intel_crtc->plane;
5680 int num_connectors = 0;
5681 intel_clock_t clock, reduced_clock;
cbbab5bd 5682 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5683 bool ok, has_reduced_clock = false;
8b47047b 5684 bool is_lvds = false;
de13a2e3 5685 struct intel_encoder *encoder;
de13a2e3 5686 int ret;
de13a2e3
PZ		 5687
5688 for_each_encoder_on_crtc(dev, crtc, encoder) {
5689 switch (encoder->type) {
5690 case INTEL_OUTPUT_LVDS:
5691 is_lvds = true;
5692 break;
de13a2e3
PZ		 5693 }
5694
5695 num_connectors++;
a07d6787 5696 }
79e53945 5697
5dc5298b
PZ		 5698 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5699 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5700
ff9a6750 5701 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5702 &has_reduced_clock, &reduced_clock);
ee9300bb 5703 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5704 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5705 return -EINVAL;
79e53945 5706 }
f47709a9
DV		 5707 /* Compat-code for transition, will disappear. */
5708 if (!intel_crtc->config.clock_set) {
5709 intel_crtc->config.dpll.n = clock.n;
5710 intel_crtc->config.dpll.m1 = clock.m1;
5711 intel_crtc->config.dpll.m2 = clock.m2;
5712 intel_crtc->config.dpll.p1 = clock.p1;
5713 intel_crtc->config.dpll.p2 = clock.p2;
5714 }
79e53945 5715
de13a2e3
PZ		 5716 /* Ensure that the cursor is valid for the new mode before changing... */
5717 intel_crtc_update_cursor(crtc, true);
5718
5dc5298b 5719 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5720 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5721 struct intel_pch_pll *pll;
4b645f14 5722
7429e9d4 5723 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5724 if (has_reduced_clock)
7429e9d4 5725 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5726
7429e9d4 5727 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5728 &fp, &reduced_clock,
5729 has_reduced_clock ? &fp2 : NULL);
5730
ee7b9f93
JB		 5731 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5732 if (pll == NULL) {
84f44ce7
VS		 5733 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5734 pipe_name(pipe));
4b645f14
JB		 5735 return -EINVAL;
5736 }
ee7b9f93
JB		 5737 } else
5738 intel_put_pch_pll(intel_crtc);
79e53945 5739
03afc4a2
DV		 5740 if (intel_crtc->config.has_dp_encoder)
5741 intel_dp_set_m_n(intel_crtc);
79e53945 5742
dafd226c
DV		 5743 for_each_encoder_on_crtc(dev, crtc, encoder)
5744 if (encoder->pre_pll_enable)
5745 encoder->pre_pll_enable(encoder);
79e53945 5746
ee7b9f93
JB		 5747 if (intel_crtc->pch_pll) {
5748 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5749
32f9d658 5750 /* Wait for the clocks to stabilize. */
ee7b9f93 5751 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5752 udelay(150);
5753
8febb297
EA		 5754 /* The pixel multiplier can only be updated once the
5755 * DPLL is enabled and the clocks are stable.
5756 *
5757 * So write it again.
5758 */
ee7b9f93 5759 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5760 }
79e53945 5761
5eddb70b 5762 intel_crtc->lowfreq_avail = false;
ee7b9f93 5763 if (intel_crtc->pch_pll) {
4b645f14 5764 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5765 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5766 intel_crtc->lowfreq_avail = true;
4b645f14 5767 } else {
ee7b9f93 5768 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5769 }
5770 }
5771
8a654f3b 5772 intel_set_pipe_timings(intel_crtc);
5eddb70b 5773
ca3a0ff8 5774 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5775 intel_cpu_transcoder_set_m_n(intel_crtc,
5776 &intel_crtc->config.fdi_m_n);
5777 }
2c07245f 5778
ebfd86fd
DV		 5779 if (IS_IVYBRIDGE(dev))
5780 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5781
6ff93609 5782 ironlake_set_pipeconf(crtc);
79e53945 5783
a1f9e77e
PZ		 5784 /* Set up the display plane register */
5785 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5786 POSTING_READ(DSPCNTR(plane));
79e53945 5787
94352cf9 5788 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5789
5790 intel_update_watermarks(dev);
5791
1857e1da 5792 return ret;
79e53945
JB		 5793}
5794
72419203
DV		 5795static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5796 struct intel_crtc_config *pipe_config)
5797{
5798 struct drm_device *dev = crtc->base.dev;
5799 struct drm_i915_private *dev_priv = dev->dev_private;
5800 enum transcoder transcoder = pipe_config->cpu_transcoder;
5801
5802 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5803 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5804 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5805 & ~TU_SIZE_MASK;
5806 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5807 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5808 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5809}
5810
2fa2fe9a
DV		 5811static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5812 struct intel_crtc_config *pipe_config)
5813{
5814 struct drm_device *dev = crtc->base.dev;
5815 struct drm_i915_private *dev_priv = dev->dev_private;
5816 uint32_t tmp;
5817
5818 tmp = I915_READ(PF_CTL(crtc->pipe));
5819
5820 if (tmp & PF_ENABLE) {
5821 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5822 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5823
5824 /* We currently do not free assignements of panel fitters on
5825 * ivb/hsw (since we don't use the higher upscaling modes which
5826 * differentiates them) so just WARN about this case for now. */
5827 if (IS_GEN7(dev)) {
5828 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5829 PF_PIPE_SEL_IVB(crtc->pipe));
5830 }
2fa2fe9a
DV		 5831 }
5832}
5833
0e8ffe1b
DV		 5834static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5835 struct intel_crtc_config *pipe_config)
5836{
5837 struct drm_device *dev = crtc->base.dev;
5838 struct drm_i915_private *dev_priv = dev->dev_private;
5839 uint32_t tmp;
5840
eccb140b
DV		 5841 pipe_config->cpu_transcoder = crtc->pipe;
5842
0e8ffe1b
DV		 5843 tmp = I915_READ(PIPECONF(crtc->pipe));
5844 if (!(tmp & PIPECONF_ENABLE))
5845 return false;
5846
ab9412ba 5847 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5848 pipe_config->has_pch_encoder = true;
5849
627eb5a3
DV		 5850 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5851 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5852 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5853
5854 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5855 }
5856
1bd1bd80
DV		 5857 intel_get_pipe_timings(crtc, pipe_config);
5858
2fa2fe9a
DV		 5859 ironlake_get_pfit_config(crtc, pipe_config);
5860
0e8ffe1b
DV		 5861 return true;
5862}
5863
d6dd9eb1
DV		 5864static void haswell_modeset_global_resources(struct drm_device *dev)
5865{
d6dd9eb1
DV		 5866 bool enable = false;
5867 struct intel_crtc *crtc;
d6dd9eb1
DV		 5868
5869 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5870 if (!crtc->base.enabled)
5871 continue;
d6dd9eb1 5872
e7a639c4
DV		 5873 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5874 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5875 enable = true;
5876 }
5877
d6dd9eb1
DV		 5878 intel_set_power_well(dev, enable);
5879}
5880
09b4ddf9 5881static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5882 int x, int y,
5883 struct drm_framebuffer *fb)
5884{
5885 struct drm_device *dev = crtc->dev;
5886 struct drm_i915_private *dev_priv = dev->dev_private;
5887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5888 int plane = intel_crtc->plane;
09b4ddf9 5889 int ret;
09b4ddf9 5890
ff9a6750 5891 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5892 return -EINVAL;
5893
09b4ddf9
PZ		 5894 /* Ensure that the cursor is valid for the new mode before changing... */
5895 intel_crtc_update_cursor(crtc, true);
5896
03afc4a2
DV		 5897 if (intel_crtc->config.has_dp_encoder)
5898 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5899
5900 intel_crtc->lowfreq_avail = false;
09b4ddf9 5901
8a654f3b 5902 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5903
ca3a0ff8 5904 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5905 intel_cpu_transcoder_set_m_n(intel_crtc,
5906 &intel_crtc->config.fdi_m_n);
5907 }
09b4ddf9 5908
6ff93609 5909 haswell_set_pipeconf(crtc);
09b4ddf9 5910
50f3b016 5911 intel_set_pipe_csc(crtc);
86d3efce 5912
09b4ddf9 5913 /* Set up the display plane register */
86d3efce 5914 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5915 POSTING_READ(DSPCNTR(plane));
5916
5917 ret = intel_pipe_set_base(crtc, x, y, fb);
5918
5919 intel_update_watermarks(dev);
5920
1f803ee5 5921 return ret;
79e53945
JB		 5922}
5923
0e8ffe1b
DV		 5924static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5925 struct intel_crtc_config *pipe_config)
5926{
5927 struct drm_device *dev = crtc->base.dev;
5928 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5929 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5930 uint32_t tmp;
5931
eccb140b
DV		 5932 pipe_config->cpu_transcoder = crtc->pipe;
5933 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5934 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5935 enum pipe trans_edp_pipe;
5936 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5937 default:
5938 WARN(1, "unknown pipe linked to edp transcoder\n");
5939 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5940 case TRANS_DDI_EDP_INPUT_A_ON:
5941 trans_edp_pipe = PIPE_A;
5942 break;
5943 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5944 trans_edp_pipe = PIPE_B;
5945 break;
5946 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5947 trans_edp_pipe = PIPE_C;
5948 break;
5949 }
5950
5951 if (trans_edp_pipe == crtc->pipe)
5952 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5953 }
5954
b97186f0 5955 if (!intel_display_power_enabled(dev,
eccb140b 5956 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 5957 return false;
5958
eccb140b 5959 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 5960 if (!(tmp & PIPECONF_ENABLE))
5961 return false;
5962
88adfff1 5963 /*
f196e6be 5964 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5965 * DDI E. So just check whether this pipe is wired to DDI E and whether
5966 * the PCH transcoder is on.
5967 */
eccb140b 5968 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 5969 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 5970 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 5971 pipe_config->has_pch_encoder = true;
5972
627eb5a3
DV		 5973 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5974 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5975 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5976
5977 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5978 }
5979
1bd1bd80
DV		 5980 intel_get_pipe_timings(crtc, pipe_config);
5981
2fa2fe9a
DV		 5982 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5983 if (intel_display_power_enabled(dev, pfit_domain))
5984 ironlake_get_pfit_config(crtc, pipe_config);
5985
42db64ef
PZ		 5986 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5987 (I915_READ(IPS_CTL) & IPS_ENABLE);
5988
0e8ffe1b
DV		 5989 return true;
5990}
5991
f564048e 5992static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5993 int x, int y,
94352cf9 5994 struct drm_framebuffer *fb)
f564048e
EA		 5995{
5996 struct drm_device *dev = crtc->dev;
5997 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5998 struct drm_encoder_helper_funcs *encoder_funcs;
5999 struct intel_encoder *encoder;
0b701d27 6000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6001 struct drm_display_mode *adjusted_mode =
6002 &intel_crtc->config.adjusted_mode;
6003 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6004 int pipe = intel_crtc->pipe;
f564048e
EA		 6005 int ret;
6006
0b701d27 6007 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6008
b8cecdf5
DV		 6009 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6010
79e53945 6011 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6012
9256aa19
DV		 6013 if (ret != 0)
6014 return ret;
6015
6016 for_each_encoder_on_crtc(dev, crtc, encoder) {
6017 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6018 encoder->base.base.id,
6019 drm_get_encoder_name(&encoder->base),
6020 mode->base.id, mode->name);
6cc5f341
DV		 6021 if (encoder->mode_set) {
6022 encoder->mode_set(encoder);
6023 } else {
6024 encoder_funcs = encoder->base.helper_private;
6025 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6026 }
9256aa19
DV		 6027 }
6028
6029 return 0;
79e53945
JB		 6030}
6031
3a9627f4
WF		 6032static bool intel_eld_uptodate(struct drm_connector *connector,
6033 int reg_eldv, uint32_t bits_eldv,
6034 int reg_elda, uint32_t bits_elda,
6035 int reg_edid)
6036{
6037 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6038 uint8_t *eld = connector->eld;
6039 uint32_t i;
6040
6041 i = I915_READ(reg_eldv);
6042 i &= bits_eldv;
6043
6044 if (!eld[0])
6045 return !i;
6046
6047 if (!i)
6048 return false;
6049
6050 i = I915_READ(reg_elda);
6051 i &= ~bits_elda;
6052 I915_WRITE(reg_elda, i);
6053
6054 for (i = 0; i < eld[2]; i++)
6055 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6056 return false;
6057
6058 return true;
6059}
6060
e0dac65e
WF		 6061static void g4x_write_eld(struct drm_connector *connector,
6062 struct drm_crtc *crtc)
6063{
6064 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6065 uint8_t *eld = connector->eld;
6066 uint32_t eldv;
6067 uint32_t len;
6068 uint32_t i;
6069
6070 i = I915_READ(G4X_AUD_VID_DID);
6071
6072 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6073 eldv = G4X_ELDV_DEVCL_DEVBLC;
6074 else
6075 eldv = G4X_ELDV_DEVCTG;
6076
3a9627f4
WF		 6077 if (intel_eld_uptodate(connector,
6078 G4X_AUD_CNTL_ST, eldv,
6079 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6080 G4X_HDMIW_HDMIEDID))
6081 return;
6082
e0dac65e
WF		 6083 i = I915_READ(G4X_AUD_CNTL_ST);
6084 i &= ~(eldv | G4X_ELD_ADDR);
6085 len = (i >> 9) & 0x1f; /* ELD buffer size */
6086 I915_WRITE(G4X_AUD_CNTL_ST, i);
6087
6088 if (!eld[0])
6089 return;
6090
6091 len = min_t(uint8_t, eld[2], len);
6092 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6093 for (i = 0; i < len; i++)
6094 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6095
6096 i = I915_READ(G4X_AUD_CNTL_ST);
6097 i |= eldv;
6098 I915_WRITE(G4X_AUD_CNTL_ST, i);
6099}
6100
83358c85
WX		 6101static void haswell_write_eld(struct drm_connector *connector,
6102 struct drm_crtc *crtc)
6103{
6104 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6105 uint8_t *eld = connector->eld;
6106 struct drm_device *dev = crtc->dev;
7b9f35a6 6107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6108 uint32_t eldv;
6109 uint32_t i;
6110 int len;
6111 int pipe = to_intel_crtc(crtc)->pipe;
6112 int tmp;
6113
6114 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6115 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6116 int aud_config = HSW_AUD_CFG(pipe);
6117 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6118
6119
6120 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6121
6122 /* Audio output enable */
6123 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6124 tmp = I915_READ(aud_cntrl_st2);
6125 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6126 I915_WRITE(aud_cntrl_st2, tmp);
6127
6128 /* Wait for 1 vertical blank */
6129 intel_wait_for_vblank(dev, pipe);
6130
6131 /* Set ELD valid state */
6132 tmp = I915_READ(aud_cntrl_st2);
6133 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6134 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6135 I915_WRITE(aud_cntrl_st2, tmp);
6136 tmp = I915_READ(aud_cntrl_st2);
6137 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6138
6139 /* Enable HDMI mode */
6140 tmp = I915_READ(aud_config);
6141 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6142 /* clear N_programing_enable and N_value_index */
6143 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6144 I915_WRITE(aud_config, tmp);
6145
6146 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6147
6148 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6149 intel_crtc->eld_vld = true;
83358c85
WX		 6150
6151 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6152 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6153 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6154 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6155 } else
6156 I915_WRITE(aud_config, 0);
6157
6158 if (intel_eld_uptodate(connector,
6159 aud_cntrl_st2, eldv,
6160 aud_cntl_st, IBX_ELD_ADDRESS,
6161 hdmiw_hdmiedid))
6162 return;
6163
6164 i = I915_READ(aud_cntrl_st2);
6165 i &= ~eldv;
6166 I915_WRITE(aud_cntrl_st2, i);
6167
6168 if (!eld[0])
6169 return;
6170
6171 i = I915_READ(aud_cntl_st);
6172 i &= ~IBX_ELD_ADDRESS;
6173 I915_WRITE(aud_cntl_st, i);
6174 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6175 DRM_DEBUG_DRIVER("port num:%d\n", i);
6176
6177 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6178 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6179 for (i = 0; i < len; i++)
6180 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6181
6182 i = I915_READ(aud_cntrl_st2);
6183 i |= eldv;
6184 I915_WRITE(aud_cntrl_st2, i);
6185
6186}
6187
e0dac65e
WF		 6188static void ironlake_write_eld(struct drm_connector *connector,
6189 struct drm_crtc *crtc)
6190{
6191 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6192 uint8_t *eld = connector->eld;
6193 uint32_t eldv;
6194 uint32_t i;
6195 int len;
6196 int hdmiw_hdmiedid;
b6daa025 6197 int aud_config;
e0dac65e
WF		 6198 int aud_cntl_st;
6199 int aud_cntrl_st2;
9b138a83 6200 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6201
b3f33cbf 6202 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6203 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6204 aud_config = IBX_AUD_CFG(pipe);
6205 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6206 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6207 } else {
9b138a83
WX		 6208 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6209 aud_config = CPT_AUD_CFG(pipe);
6210 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6211 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6212 }
6213
9b138a83 6214 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6215
6216 i = I915_READ(aud_cntl_st);
9b138a83 6217 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6218 if (!i) {
6219 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6220 /* operate blindly on all ports */
1202b4c6
WF		 6221 eldv = IBX_ELD_VALIDB;
6222 eldv |= IBX_ELD_VALIDB << 4;
6223 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6224 } else {
2582a850 6225 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6226 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6227 }
6228
3a9627f4
WF		 6229 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6230 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6231 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6232 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6233 } else
6234 I915_WRITE(aud_config, 0);
e0dac65e 6235
3a9627f4
WF		 6236 if (intel_eld_uptodate(connector,
6237 aud_cntrl_st2, eldv,
6238 aud_cntl_st, IBX_ELD_ADDRESS,
6239 hdmiw_hdmiedid))
6240 return;
6241
e0dac65e
WF		 6242 i = I915_READ(aud_cntrl_st2);
6243 i &= ~eldv;
6244 I915_WRITE(aud_cntrl_st2, i);
6245
6246 if (!eld[0])
6247 return;
6248
e0dac65e 6249 i = I915_READ(aud_cntl_st);
1202b4c6 6250 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6251 I915_WRITE(aud_cntl_st, i);
6252
6253 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6254 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6255 for (i = 0; i < len; i++)
6256 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6257
6258 i = I915_READ(aud_cntrl_st2);
6259 i |= eldv;
6260 I915_WRITE(aud_cntrl_st2, i);
6261}
6262
6263void intel_write_eld(struct drm_encoder *encoder,
6264 struct drm_display_mode *mode)
6265{
6266 struct drm_crtc *crtc = encoder->crtc;
6267 struct drm_connector *connector;
6268 struct drm_device *dev = encoder->dev;
6269 struct drm_i915_private *dev_priv = dev->dev_private;
6270
6271 connector = drm_select_eld(encoder, mode);
6272 if (!connector)
6273 return;
6274
6275 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6276 connector->base.id,
6277 drm_get_connector_name(connector),
6278 connector->encoder->base.id,
6279 drm_get_encoder_name(connector->encoder));
6280
6281 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6282
6283 if (dev_priv->display.write_eld)
6284 dev_priv->display.write_eld(connector, crtc);
6285}
6286
79e53945
JB		 6287/** Loads the palette/gamma unit for the CRTC with the prepared values */
6288void intel_crtc_load_lut(struct drm_crtc *crtc)
6289{
6290 struct drm_device *dev = crtc->dev;
6291 struct drm_i915_private *dev_priv = dev->dev_private;
6292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6293 enum pipe pipe = intel_crtc->pipe;
6294 int palreg = PALETTE(pipe);
79e53945 6295 int i;
42db64ef 6296 bool reenable_ips = false;
79e53945
JB		 6297
6298 /* The clocks have to be on to load the palette. */
aed3f09d 6299 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6300 return;
6301
f2b115e6 6302 /* use legacy palette for Ironlake */
bad720ff 6303 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6304 palreg = LGC_PALETTE(pipe);
6305
6306 /* Workaround : Do not read or write the pipe palette/gamma data while
6307 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6308 */
6309 if (intel_crtc->config.ips_enabled &&
6310 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6311 GAMMA_MODE_MODE_SPLIT)) {
6312 hsw_disable_ips(intel_crtc);
6313 reenable_ips = true;
6314 }
2c07245f 6315
79e53945
JB		 6316 for (i = 0; i < 256; i++) {
6317 I915_WRITE(palreg + 4 * i,
6318 (intel_crtc->lut_r[i] << 16) |
6319 (intel_crtc->lut_g[i] << 8) |
6320 intel_crtc->lut_b[i]);
6321 }
42db64ef
PZ		 6322
6323 if (reenable_ips)
6324 hsw_enable_ips(intel_crtc);
79e53945
JB		 6325}
6326
560b85bb
CW		 6327static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6328{
6329 struct drm_device *dev = crtc->dev;
6330 struct drm_i915_private *dev_priv = dev->dev_private;
6331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6332 bool visible = base != 0;
6333 u32 cntl;
6334
6335 if (intel_crtc->cursor_visible == visible)
6336 return;
6337
9db4a9c7 6338 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6339 if (visible) {
6340 /* On these chipsets we can only modify the base whilst
6341 * the cursor is disabled.
6342 */
9db4a9c7 6343 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6344
6345 cntl &= ~(CURSOR_FORMAT_MASK);
6346 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6347 cntl |= CURSOR_ENABLE |
6348 CURSOR_GAMMA_ENABLE |
6349 CURSOR_FORMAT_ARGB;
6350 } else
6351 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6352 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6353
6354 intel_crtc->cursor_visible = visible;
6355}
6356
6357static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6358{
6359 struct drm_device *dev = crtc->dev;
6360 struct drm_i915_private *dev_priv = dev->dev_private;
6361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6362 int pipe = intel_crtc->pipe;
6363 bool visible = base != 0;
6364
6365 if (intel_crtc->cursor_visible != visible) {
548f245b 6366 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6367 if (base) {
6368 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6369 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6370 cntl |= pipe << 28; /* Connect to correct pipe */
6371 } else {
6372 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6373 cntl |= CURSOR_MODE_DISABLE;
6374 }
9db4a9c7 6375 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6376
6377 intel_crtc->cursor_visible = visible;
6378 }
6379 /* and commit changes on next vblank */
9db4a9c7 6380 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6381}
6382
65a21cd6
JB		 6383static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6384{
6385 struct drm_device *dev = crtc->dev;
6386 struct drm_i915_private *dev_priv = dev->dev_private;
6387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6388 int pipe = intel_crtc->pipe;
6389 bool visible = base != 0;
6390
6391 if (intel_crtc->cursor_visible != visible) {
6392 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6393 if (base) {
6394 cntl &= ~CURSOR_MODE;
6395 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6396 } else {
6397 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6398 cntl |= CURSOR_MODE_DISABLE;
6399 }
86d3efce
VS		 6400 if (IS_HASWELL(dev))
6401 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6402 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6403
6404 intel_crtc->cursor_visible = visible;
6405 }
6406 /* and commit changes on next vblank */
6407 I915_WRITE(CURBASE_IVB(pipe), base);
6408}
6409
cda4b7d3 6410/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6411static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6412 bool on)
cda4b7d3
CW		 6413{
6414 struct drm_device *dev = crtc->dev;
6415 struct drm_i915_private *dev_priv = dev->dev_private;
6416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6417 int pipe = intel_crtc->pipe;
6418 int x = intel_crtc->cursor_x;
6419 int y = intel_crtc->cursor_y;
560b85bb 6420 u32 base, pos;
cda4b7d3
CW		 6421 bool visible;
6422
6423 pos = 0;
6424
6b383a7f 6425 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6426 base = intel_crtc->cursor_addr;
6427 if (x > (int) crtc->fb->width)
6428 base = 0;
6429
6430 if (y > (int) crtc->fb->height)
6431 base = 0;
6432 } else
6433 base = 0;
6434
6435 if (x < 0) {
6436 if (x + intel_crtc->cursor_width < 0)
6437 base = 0;
6438
6439 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6440 x = -x;
6441 }
6442 pos |= x << CURSOR_X_SHIFT;
6443
6444 if (y < 0) {
6445 if (y + intel_crtc->cursor_height < 0)
6446 base = 0;
6447
6448 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6449 y = -y;
6450 }
6451 pos |= y << CURSOR_Y_SHIFT;
6452
6453 visible = base != 0;
560b85bb 6454 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6455 return;
6456
0cd83aa9 6457 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6458 I915_WRITE(CURPOS_IVB(pipe), pos);
6459 ivb_update_cursor(crtc, base);
6460 } else {
6461 I915_WRITE(CURPOS(pipe), pos);
6462 if (IS_845G(dev) || IS_I865G(dev))
6463 i845_update_cursor(crtc, base);
6464 else
6465 i9xx_update_cursor(crtc, base);
6466 }
cda4b7d3
CW		 6467}
6468
79e53945 6469static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6470 struct drm_file *file,
79e53945
JB		 6471 uint32_t handle,
6472 uint32_t width, uint32_t height)
6473{
6474 struct drm_device *dev = crtc->dev;
6475 struct drm_i915_private *dev_priv = dev->dev_private;
6476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6477 struct drm_i915_gem_object *obj;
cda4b7d3 6478 uint32_t addr;
3f8bc370 6479 int ret;
79e53945 6480
79e53945
JB		 6481 /* if we want to turn off the cursor ignore width and height */
6482 if (!handle) {
28c97730 6483 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6484 addr = 0;
05394f39 6485 obj = NULL;
5004417d 6486 mutex_lock(&dev->struct_mutex);
3f8bc370 6487 goto finish;
79e53945
JB		 6488 }
6489
6490 /* Currently we only support 64x64 cursors */
6491 if (width != 64 || height != 64) {
6492 DRM_ERROR("we currently only support 64x64 cursors\n");
6493 return -EINVAL;
6494 }
6495
05394f39 6496 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6497 if (&obj->base == NULL)
79e53945
JB		 6498 return -ENOENT;
6499
05394f39 6500 if (obj->base.size < width * height * 4) {
79e53945 6501 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6502 ret = -ENOMEM;
6503 goto fail;
79e53945
JB		 6504 }
6505
71acb5eb 6506 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6507 mutex_lock(&dev->struct_mutex);
b295d1b6 6508 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6509 unsigned alignment;
6510
d9e86c0e
CW		 6511 if (obj->tiling_mode) {
6512 DRM_ERROR("cursor cannot be tiled\n");
6513 ret = -EINVAL;
6514 goto fail_locked;
6515 }
6516
693db184
CW		 6517 /* Note that the w/a also requires 2 PTE of padding following
6518 * the bo. We currently fill all unused PTE with the shadow
6519 * page and so we should always have valid PTE following the
6520 * cursor preventing the VT-d warning.
6521 */
6522 alignment = 0;
6523 if (need_vtd_wa(dev))
6524 alignment = 64*1024;
6525
6526 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6527 if (ret) {
6528 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6529 goto fail_locked;
e7b526bb
CW		 6530 }
6531
d9e86c0e
CW		 6532 ret = i915_gem_object_put_fence(obj);
6533 if (ret) {
2da3b9b9 6534 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6535 goto fail_unpin;
6536 }
6537
05394f39 6538 addr = obj->gtt_offset;
71acb5eb 6539 } else {
6eeefaf3 6540 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6541 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6542 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6543 align);
71acb5eb
DA		 6544 if (ret) {
6545 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6546 goto fail_locked;
71acb5eb 6547 }
05394f39 6548 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6549 }
6550
a6c45cf0 6551 if (IS_GEN2(dev))
14b60391
JB		 6552 I915_WRITE(CURSIZE, (height << 12) | width);
6553
3f8bc370 6554 finish:
3f8bc370 6555 if (intel_crtc->cursor_bo) {
b295d1b6 6556 if (dev_priv->info->cursor_needs_physical) {
05394f39 6557 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6558 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6559 } else
6560 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6561 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6562 }
80824003 6563
7f9872e0 6564 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6565
6566 intel_crtc->cursor_addr = addr;
05394f39 6567 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6568 intel_crtc->cursor_width = width;
6569 intel_crtc->cursor_height = height;
6570
40ccc72b 6571 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6572
79e53945 6573 return 0;
e7b526bb 6574fail_unpin:
05394f39 6575 i915_gem_object_unpin(obj);
7f9872e0 6576fail_locked:
34b8686e 6577 mutex_unlock(&dev->struct_mutex);
bc9025bd 6578fail:
05394f39 6579 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6580 return ret;
79e53945
JB		 6581}
6582
6583static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6584{
79e53945 6585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6586
cda4b7d3
CW		 6587 intel_crtc->cursor_x = x;
6588 intel_crtc->cursor_y = y;
652c393a 6589
40ccc72b 6590 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6591
6592 return 0;
6593}
6594
6595/** Sets the color ramps on behalf of RandR */
6596void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6597 u16 blue, int regno)
6598{
6599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6600
6601 intel_crtc->lut_r[regno] = red >> 8;
6602 intel_crtc->lut_g[regno] = green >> 8;
6603 intel_crtc->lut_b[regno] = blue >> 8;
6604}
6605
b8c00ac5
DA		 6606void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6607 u16 *blue, int regno)
6608{
6609 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6610
6611 *red = intel_crtc->lut_r[regno] << 8;
6612 *green = intel_crtc->lut_g[regno] << 8;
6613 *blue = intel_crtc->lut_b[regno] << 8;
6614}
6615
79e53945 6616static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6617 u16 *blue, uint32_t start, uint32_t size)
79e53945 6618{
7203425a 6619 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6621
7203425a 6622 for (i = start; i < end; i++) {
79e53945
JB		 6623 intel_crtc->lut_r[i] = red[i] >> 8;
6624 intel_crtc->lut_g[i] = green[i] >> 8;
6625 intel_crtc->lut_b[i] = blue[i] >> 8;
6626 }
6627
6628 intel_crtc_load_lut(crtc);
6629}
6630
79e53945
JB		 6631/* VESA 640x480x72Hz mode to set on the pipe */
6632static struct drm_display_mode load_detect_mode = {
6633 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6634 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6635};
6636
d2dff872
CW		 6637static struct drm_framebuffer *
6638intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6639 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6640 struct drm_i915_gem_object *obj)
6641{
6642 struct intel_framebuffer *intel_fb;
6643 int ret;
6644
6645 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6646 if (!intel_fb) {
6647 drm_gem_object_unreference_unlocked(&obj->base);
6648 return ERR_PTR(-ENOMEM);
6649 }
6650
6651 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6652 if (ret) {
6653 drm_gem_object_unreference_unlocked(&obj->base);
6654 kfree(intel_fb);
6655 return ERR_PTR(ret);
6656 }
6657
6658 return &intel_fb->base;
6659}
6660
6661static u32
6662intel_framebuffer_pitch_for_width(int width, int bpp)
6663{
6664 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6665 return ALIGN(pitch, 64);
6666}
6667
6668static u32
6669intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6670{
6671 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6672 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6673}
6674
6675static struct drm_framebuffer *
6676intel_framebuffer_create_for_mode(struct drm_device *dev,
6677 struct drm_display_mode *mode,
6678 int depth, int bpp)
6679{
6680 struct drm_i915_gem_object *obj;
0fed39bd 6681 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6682
6683 obj = i915_gem_alloc_object(dev,
6684 intel_framebuffer_size_for_mode(mode, bpp));
6685 if (obj == NULL)
6686 return ERR_PTR(-ENOMEM);
6687
6688 mode_cmd.width = mode->hdisplay;
6689 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6690 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6691 bpp);
5ca0c34a 6692 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6693
6694 return intel_framebuffer_create(dev, &mode_cmd, obj);
6695}
6696
6697static struct drm_framebuffer *
6698mode_fits_in_fbdev(struct drm_device *dev,
6699 struct drm_display_mode *mode)
6700{
6701 struct drm_i915_private *dev_priv = dev->dev_private;
6702 struct drm_i915_gem_object *obj;
6703 struct drm_framebuffer *fb;
6704
6705 if (dev_priv->fbdev == NULL)
6706 return NULL;
6707
6708 obj = dev_priv->fbdev->ifb.obj;
6709 if (obj == NULL)
6710 return NULL;
6711
6712 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6713 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6714 fb->bits_per_pixel))
d2dff872
CW		 6715 return NULL;
6716
01f2c773 6717 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6718 return NULL;
6719
6720 return fb;
6721}
6722
d2434ab7 6723bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6724 struct drm_display_mode *mode,
8261b191 6725 struct intel_load_detect_pipe *old)
79e53945
JB		 6726{
6727 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6728 struct intel_encoder *intel_encoder =
6729 intel_attached_encoder(connector);
79e53945 6730 struct drm_crtc *possible_crtc;
4ef69c7a 6731 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6732 struct drm_crtc *crtc = NULL;
6733 struct drm_device *dev = encoder->dev;
94352cf9 6734 struct drm_framebuffer *fb;
79e53945
JB		 6735 int i = -1;
6736
d2dff872
CW		 6737 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6738 connector->base.id, drm_get_connector_name(connector),
6739 encoder->base.id, drm_get_encoder_name(encoder));
6740
79e53945
JB		 6741 /*
6742 * Algorithm gets a little messy:
7a5e4805 6743 *
79e53945
JB		 6744 * - if the connector already has an assigned crtc, use it (but make
6745 * sure it's on first)
7a5e4805 6746 *
79e53945
JB		 6747 * - try to find the first unused crtc that can drive this connector,
6748 * and use that if we find one
79e53945
JB		 6749 */
6750
6751 /* See if we already have a CRTC for this connector */
6752 if (encoder->crtc) {
6753 crtc = encoder->crtc;
8261b191 6754
7b24056b
DV		 6755 mutex_lock(&crtc->mutex);
6756
24218aac 6757 old->dpms_mode = connector->dpms;
8261b191
CW		 6758 old->load_detect_temp = false;
6759
6760 /* Make sure the crtc and connector are running */
24218aac
DV		 6761 if (connector->dpms != DRM_MODE_DPMS_ON)
6762 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6763
7173188d 6764 return true;
79e53945
JB		 6765 }
6766
6767 /* Find an unused one (if possible) */
6768 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6769 i++;
6770 if (!(encoder->possible_crtcs & (1 << i)))
6771 continue;
6772 if (!possible_crtc->enabled) {
6773 crtc = possible_crtc;
6774 break;
6775 }
79e53945
JB		 6776 }
6777
6778 /*
6779 * If we didn't find an unused CRTC, don't use any.
6780 */
6781 if (!crtc) {
7173188d
CW		 6782 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6783 return false;
79e53945
JB		 6784 }
6785
7b24056b 6786 mutex_lock(&crtc->mutex);
fc303101
DV		 6787 intel_encoder->new_crtc = to_intel_crtc(crtc);
6788 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6789
6790 intel_crtc = to_intel_crtc(crtc);
24218aac 6791 old->dpms_mode = connector->dpms;
8261b191 6792 old->load_detect_temp = true;
d2dff872 6793 old->release_fb = NULL;
79e53945 6794
6492711d
CW		 6795 if (!mode)
6796 mode = &load_detect_mode;
79e53945 6797
d2dff872
CW		 6798 /* We need a framebuffer large enough to accommodate all accesses
6799 * that the plane may generate whilst we perform load detection.
6800 * We can not rely on the fbcon either being present (we get called
6801 * during its initialisation to detect all boot displays, or it may
6802 * not even exist) or that it is large enough to satisfy the
6803 * requested mode.
6804 */
94352cf9
DV		 6805 fb = mode_fits_in_fbdev(dev, mode);
6806 if (fb == NULL) {
d2dff872 6807 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6808 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6809 old->release_fb = fb;
d2dff872
CW		 6810 } else
6811 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6812 if (IS_ERR(fb)) {
d2dff872 6813 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6814 mutex_unlock(&crtc->mutex);
0e8b3d3e 6815 return false;
79e53945 6816 }
79e53945 6817
c0c36b94 6818 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6819 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6820 if (old->release_fb)
6821 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6822 mutex_unlock(&crtc->mutex);
0e8b3d3e 6823 return false;
79e53945 6824 }
7173188d 6825
79e53945 6826 /* let the connector get through one full cycle before testing */
9d0498a2 6827 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6828 return true;
79e53945
JB		 6829}
6830
d2434ab7 6831void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6832 struct intel_load_detect_pipe *old)
79e53945 6833{
d2434ab7
DV		 6834 struct intel_encoder *intel_encoder =
6835 intel_attached_encoder(connector);
4ef69c7a 6836 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6837 struct drm_crtc *crtc = encoder->crtc;
79e53945 6838
d2dff872
CW		 6839 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6840 connector->base.id, drm_get_connector_name(connector),
6841 encoder->base.id, drm_get_encoder_name(encoder));
6842
8261b191 6843 if (old->load_detect_temp) {
fc303101
DV		 6844 to_intel_connector(connector)->new_encoder = NULL;
6845 intel_encoder->new_crtc = NULL;
6846 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6847
36206361
DV		 6848 if (old->release_fb) {
6849 drm_framebuffer_unregister_private(old->release_fb);
6850 drm_framebuffer_unreference(old->release_fb);
6851 }
d2dff872 6852
67c96400 6853 mutex_unlock(&crtc->mutex);
0622a53c 6854 return;
79e53945
JB		 6855 }
6856
c751ce4f 6857 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6858 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6859 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6860
6861 mutex_unlock(&crtc->mutex);
79e53945
JB		 6862}
6863
6864/* Returns the clock of the currently programmed mode of the given pipe. */
6865static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6866{
6867 struct drm_i915_private *dev_priv = dev->dev_private;
6868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6869 int pipe = intel_crtc->pipe;
548f245b 6870 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6871 u32 fp;
6872 intel_clock_t clock;
6873
6874 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6875 fp = I915_READ(FP0(pipe));
79e53945 6876 else
39adb7a5 6877 fp = I915_READ(FP1(pipe));
79e53945
JB		 6878
6879 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6880 if (IS_PINEVIEW(dev)) {
6881 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6882 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6883 } else {
6884 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6885 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6886 }
6887
a6c45cf0 6888 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6889 if (IS_PINEVIEW(dev))
6890 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6891 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6892 else
6893 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6894 DPLL_FPA01_P1_POST_DIV_SHIFT);
6895
6896 switch (dpll & DPLL_MODE_MASK) {
6897 case DPLLB_MODE_DAC_SERIAL:
6898 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6899 5 : 10;
6900 break;
6901 case DPLLB_MODE_LVDS:
6902 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6903 7 : 14;
6904 break;
6905 default:
28c97730 6906 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6907 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6908 return 0;
6909 }
6910
ac58c3f0
DV		 6911 if (IS_PINEVIEW(dev))
6912 pineview_clock(96000, &clock);
6913 else
6914 i9xx_clock(96000, &clock);
79e53945
JB		 6915 } else {
6916 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6917
6918 if (is_lvds) {
6919 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6920 DPLL_FPA01_P1_POST_DIV_SHIFT);
6921 clock.p2 = 14;
6922
6923 if ((dpll & PLL_REF_INPUT_MASK) ==
6924 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6925 /* XXX: might not be 66MHz */
ac58c3f0 6926 i9xx_clock(66000, &clock);
79e53945 6927 } else
ac58c3f0 6928 i9xx_clock(48000, &clock);
79e53945
JB		 6929 } else {
6930 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6931 clock.p1 = 2;
6932 else {
6933 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6934 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6935 }
6936 if (dpll & PLL_P2_DIVIDE_BY_4)
6937 clock.p2 = 4;
6938 else
6939 clock.p2 = 2;
6940
ac58c3f0 6941 i9xx_clock(48000, &clock);
79e53945
JB		 6942 }
6943 }
6944
6945 /* XXX: It would be nice to validate the clocks, but we can't reuse
6946 * i830PllIsValid() because it relies on the xf86_config connector
6947 * configuration being accurate, which it isn't necessarily.
6948 */
6949
6950 return clock.dot;
6951}
6952
6953/** Returns the currently programmed mode of the given pipe. */
6954struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6955 struct drm_crtc *crtc)
6956{
548f245b 6957 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6959 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6960 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6961 int htot = I915_READ(HTOTAL(cpu_transcoder));
6962 int hsync = I915_READ(HSYNC(cpu_transcoder));
6963 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6964 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6965
6966 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6967 if (!mode)
6968 return NULL;
6969
6970 mode->clock = intel_crtc_clock_get(dev, crtc);
6971 mode->hdisplay = (htot & 0xffff) + 1;
6972 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6973 mode->hsync_start = (hsync & 0xffff) + 1;
6974 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6975 mode->vdisplay = (vtot & 0xffff) + 1;
6976 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6977 mode->vsync_start = (vsync & 0xffff) + 1;
6978 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6979
6980 drm_mode_set_name(mode);
79e53945
JB		 6981
6982 return mode;
6983}
6984
3dec0095 6985static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6986{
6987 struct drm_device *dev = crtc->dev;
6988 drm_i915_private_t *dev_priv = dev->dev_private;
6989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6990 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6991 int dpll_reg = DPLL(pipe);
6992 int dpll;
652c393a 6993
bad720ff 6994 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6995 return;
6996
6997 if (!dev_priv->lvds_downclock_avail)
6998 return;
6999
dbdc6479 7000 dpll = I915_READ(dpll_reg);
652c393a 7001 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7002 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7003
8ac5a6d5 7004 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7005
7006 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7007 I915_WRITE(dpll_reg, dpll);
9d0498a2 7008 intel_wait_for_vblank(dev, pipe);
dbdc6479 7009
652c393a
JB		 7010 dpll = I915_READ(dpll_reg);
7011 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7012 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7013 }
652c393a
JB		 7014}
7015
7016static void intel_decrease_pllclock(struct drm_crtc *crtc)
7017{
7018 struct drm_device *dev = crtc->dev;
7019 drm_i915_private_t *dev_priv = dev->dev_private;
7020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7021
bad720ff 7022 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7023 return;
7024
7025 if (!dev_priv->lvds_downclock_avail)
7026 return;
7027
7028 /*
7029 * Since this is called by a timer, we should never get here in
7030 * the manual case.
7031 */
7032 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7033 int pipe = intel_crtc->pipe;
7034 int dpll_reg = DPLL(pipe);
7035 int dpll;
f6e5b160 7036
44d98a61 7037 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7038
8ac5a6d5 7039 assert_panel_unlocked(dev_priv, pipe);
652c393a 7040
dc257cf1 7041 dpll = I915_READ(dpll_reg);
652c393a
JB		 7042 dpll |= DISPLAY_RATE_SELECT_FPA1;
7043 I915_WRITE(dpll_reg, dpll);
9d0498a2 7044 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7045 dpll = I915_READ(dpll_reg);
7046 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7047 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7048 }
7049
7050}
7051
f047e395
CW		 7052void intel_mark_busy(struct drm_device *dev)
7053{
f047e395
CW		 7054 i915_update_gfx_val(dev->dev_private);
7055}
7056
7057void intel_mark_idle(struct drm_device *dev)
652c393a 7058{
652c393a 7059 struct drm_crtc *crtc;
652c393a
JB		 7060
7061 if (!i915_powersave)
7062 return;
7063
652c393a 7064 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7065 if (!crtc->fb)
7066 continue;
7067
725a5b54 7068 intel_decrease_pllclock(crtc);
652c393a 7069 }
652c393a
JB		 7070}
7071
725a5b54 7072void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 7073{
f047e395
CW		 7074 struct drm_device *dev = obj->base.dev;
7075 struct drm_crtc *crtc;
652c393a 7076
f047e395 7077 if (!i915_powersave)
acb87dfb
CW		 7078 return;
7079
652c393a
JB		 7080 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7081 if (!crtc->fb)
7082 continue;
7083
f047e395 7084 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 7085 intel_increase_pllclock(crtc);
652c393a
JB		 7086 }
7087}
7088
79e53945
JB		 7089static void intel_crtc_destroy(struct drm_crtc *crtc)
7090{
7091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7092 struct drm_device *dev = crtc->dev;
7093 struct intel_unpin_work *work;
7094 unsigned long flags;
7095
7096 spin_lock_irqsave(&dev->event_lock, flags);
7097 work = intel_crtc->unpin_work;
7098 intel_crtc->unpin_work = NULL;
7099 spin_unlock_irqrestore(&dev->event_lock, flags);
7100
7101 if (work) {
7102 cancel_work_sync(&work->work);
7103 kfree(work);
7104 }
79e53945 7105
40ccc72b
MK		 7106 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7107
79e53945 7108 drm_crtc_cleanup(crtc);
67e77c5a 7109
79e53945
JB		 7110 kfree(intel_crtc);
7111}
7112
6b95a207
KH		 7113static void intel_unpin_work_fn(struct work_struct *__work)
7114{
7115 struct intel_unpin_work *work =
7116 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7117 struct drm_device *dev = work->crtc->dev;
6b95a207 7118
b4a98e57 7119 mutex_lock(&dev->struct_mutex);
1690e1eb 7120 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7121 drm_gem_object_unreference(&work->pending_flip_obj->base);
7122 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7123
b4a98e57
CW		 7124 intel_update_fbc(dev);
7125 mutex_unlock(&dev->struct_mutex);
7126
7127 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7128 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7129
6b95a207
KH		 7130 kfree(work);
7131}
7132
1afe3e9d 7133static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7134 struct drm_crtc *crtc)
6b95a207
KH		 7135{
7136 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7138 struct intel_unpin_work *work;
6b95a207
KH		 7139 unsigned long flags;
7140
7141 /* Ignore early vblank irqs */
7142 if (intel_crtc == NULL)
7143 return;
7144
7145 spin_lock_irqsave(&dev->event_lock, flags);
7146 work = intel_crtc->unpin_work;
e7d841ca
CW		 7147
7148 /* Ensure we don't miss a work->pending update ... */
7149 smp_rmb();
7150
7151 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7152 spin_unlock_irqrestore(&dev->event_lock, flags);
7153 return;
7154 }
7155
e7d841ca
CW		 7156 /* and that the unpin work is consistent wrt ->pending. */
7157 smp_rmb();
7158
6b95a207 7159 intel_crtc->unpin_work = NULL;
6b95a207 7160
45a066eb
RC		 7161 if (work->event)
7162 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7163
0af7e4df
MK		 7164 drm_vblank_put(dev, intel_crtc->pipe);
7165
6b95a207
KH		 7166 spin_unlock_irqrestore(&dev->event_lock, flags);
7167
2c10d571 7168 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7169
7170 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7171
7172 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7173}
7174
1afe3e9d
JB		 7175void intel_finish_page_flip(struct drm_device *dev, int pipe)
7176{
7177 drm_i915_private_t *dev_priv = dev->dev_private;
7178 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7179
49b14a5c 7180 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7181}
7182
7183void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7184{
7185 drm_i915_private_t *dev_priv = dev->dev_private;
7186 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7187
49b14a5c 7188 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7189}
7190
6b95a207
KH		 7191void intel_prepare_page_flip(struct drm_device *dev, int plane)
7192{
7193 drm_i915_private_t *dev_priv = dev->dev_private;
7194 struct intel_crtc *intel_crtc =
7195 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7196 unsigned long flags;
7197
e7d841ca
CW		 7198 /* NB: An MMIO update of the plane base pointer will also
7199 * generate a page-flip completion irq, i.e. every modeset
7200 * is also accompanied by a spurious intel_prepare_page_flip().
7201 */
6b95a207 7202 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7203 if (intel_crtc->unpin_work)
7204 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7205 spin_unlock_irqrestore(&dev->event_lock, flags);
7206}
7207
e7d841ca
CW		 7208inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7209{
7210 /* Ensure that the work item is consistent when activating it ... */
7211 smp_wmb();
7212 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7213 /* and that it is marked active as soon as the irq could fire. */
7214 smp_wmb();
7215}
7216
8c9f3aaf
JB		 7217static int intel_gen2_queue_flip(struct drm_device *dev,
7218 struct drm_crtc *crtc,
7219 struct drm_framebuffer *fb,
7220 struct drm_i915_gem_object *obj)
7221{
7222 struct drm_i915_private *dev_priv = dev->dev_private;
7223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7224 u32 flip_mask;
6d90c952 7225 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7226 int ret;
7227
6d90c952 7228 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7229 if (ret)
83d4092b 7230 goto err;
8c9f3aaf 7231
6d90c952 7232 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7233 if (ret)
83d4092b 7234 goto err_unpin;
8c9f3aaf
JB		 7235
7236 /* Can't queue multiple flips, so wait for the previous
7237 * one to finish before executing the next.
7238 */
7239 if (intel_crtc->plane)
7240 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7241 else
7242 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7243 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7244 intel_ring_emit(ring, MI_NOOP);
7245 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7246 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7247 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7248 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7249 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7250
7251 intel_mark_page_flip_active(intel_crtc);
6d90c952 7252 intel_ring_advance(ring);
83d4092b
CW		 7253 return 0;
7254
7255err_unpin:
7256 intel_unpin_fb_obj(obj);
7257err:
8c9f3aaf
JB		 7258 return ret;
7259}
7260
7261static int intel_gen3_queue_flip(struct drm_device *dev,
7262 struct drm_crtc *crtc,
7263 struct drm_framebuffer *fb,
7264 struct drm_i915_gem_object *obj)
7265{
7266 struct drm_i915_private *dev_priv = dev->dev_private;
7267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7268 u32 flip_mask;
6d90c952 7269 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7270 int ret;
7271
6d90c952 7272 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7273 if (ret)
83d4092b 7274 goto err;
8c9f3aaf 7275
6d90c952 7276 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7277 if (ret)
83d4092b 7278 goto err_unpin;
8c9f3aaf
JB		 7279
7280 if (intel_crtc->plane)
7281 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7282 else
7283 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7284 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7285 intel_ring_emit(ring, MI_NOOP);
7286 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7287 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7288 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7289 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7290 intel_ring_emit(ring, MI_NOOP);
7291
e7d841ca 7292 intel_mark_page_flip_active(intel_crtc);
6d90c952 7293 intel_ring_advance(ring);
83d4092b
CW		 7294 return 0;
7295
7296err_unpin:
7297 intel_unpin_fb_obj(obj);
7298err:
8c9f3aaf
JB		 7299 return ret;
7300}
7301
7302static int intel_gen4_queue_flip(struct drm_device *dev,
7303 struct drm_crtc *crtc,
7304 struct drm_framebuffer *fb,
7305 struct drm_i915_gem_object *obj)
7306{
7307 struct drm_i915_private *dev_priv = dev->dev_private;
7308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7309 uint32_t pf, pipesrc;
6d90c952 7310 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7311 int ret;
7312
6d90c952 7313 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7314 if (ret)
83d4092b 7315 goto err;
8c9f3aaf 7316
6d90c952 7317 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7318 if (ret)
83d4092b 7319 goto err_unpin;
8c9f3aaf
JB		 7320
7321 /* i965+ uses the linear or tiled offsets from the
7322 * Display Registers (which do not change across a page-flip)
7323 * so we need only reprogram the base address.
7324 */
6d90c952
DV		 7325 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7326 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7327 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7328 intel_ring_emit(ring,
7329 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7330 obj->tiling_mode);
8c9f3aaf
JB		 7331
7332 /* XXX Enabling the panel-fitter across page-flip is so far
7333 * untested on non-native modes, so ignore it for now.
7334 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7335 */
7336 pf = 0;
7337 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7338 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7339
7340 intel_mark_page_flip_active(intel_crtc);
6d90c952 7341 intel_ring_advance(ring);
83d4092b
CW		 7342 return 0;
7343
7344err_unpin:
7345 intel_unpin_fb_obj(obj);
7346err:
8c9f3aaf
JB		 7347 return ret;
7348}
7349
7350static int intel_gen6_queue_flip(struct drm_device *dev,
7351 struct drm_crtc *crtc,
7352 struct drm_framebuffer *fb,
7353 struct drm_i915_gem_object *obj)
7354{
7355 struct drm_i915_private *dev_priv = dev->dev_private;
7356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7357 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7358 uint32_t pf, pipesrc;
7359 int ret;
7360
6d90c952 7361 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7362 if (ret)
83d4092b 7363 goto err;
8c9f3aaf 7364
6d90c952 7365 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7366 if (ret)
83d4092b 7367 goto err_unpin;
8c9f3aaf 7368
6d90c952
DV		 7369 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7370 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7371 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7372 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7373
dc257cf1
DV		 7374 /* Contrary to the suggestions in the documentation,
7375 * "Enable Panel Fitter" does not seem to be required when page
7376 * flipping with a non-native mode, and worse causes a normal
7377 * modeset to fail.
7378 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7379 */
7380 pf = 0;
8c9f3aaf 7381 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7382 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7383
7384 intel_mark_page_flip_active(intel_crtc);
6d90c952 7385 intel_ring_advance(ring);
83d4092b
CW		 7386 return 0;
7387
7388err_unpin:
7389 intel_unpin_fb_obj(obj);
7390err:
8c9f3aaf
JB		 7391 return ret;
7392}
7393
7c9017e5
JB		 7394/*
7395 * On gen7 we currently use the blit ring because (in early silicon at least)
7396 * the render ring doesn't give us interrpts for page flip completion, which
7397 * means clients will hang after the first flip is queued. Fortunately the
7398 * blit ring generates interrupts properly, so use it instead.
7399 */
7400static int intel_gen7_queue_flip(struct drm_device *dev,
7401 struct drm_crtc *crtc,
7402 struct drm_framebuffer *fb,
7403 struct drm_i915_gem_object *obj)
7404{
7405 struct drm_i915_private *dev_priv = dev->dev_private;
7406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7407 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7408 uint32_t plane_bit = 0;
7c9017e5
JB		 7409 int ret;
7410
7411 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7412 if (ret)
83d4092b 7413 goto err;
7c9017e5 7414
cb05d8de
DV		 7415 switch(intel_crtc->plane) {
7416 case PLANE_A:
7417 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7418 break;
7419 case PLANE_B:
7420 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7421 break;
7422 case PLANE_C:
7423 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7424 break;
7425 default:
7426 WARN_ONCE(1, "unknown plane in flip command\n");
7427 ret = -ENODEV;
ab3951eb 7428 goto err_unpin;
cb05d8de
DV		 7429 }
7430
7c9017e5
JB		 7431 ret = intel_ring_begin(ring, 4);
7432 if (ret)
83d4092b 7433 goto err_unpin;
7c9017e5 7434
cb05d8de 7435 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7436 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7437 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7438 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7439
7440 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7441 intel_ring_advance(ring);
83d4092b
CW		 7442 return 0;
7443
7444err_unpin:
7445 intel_unpin_fb_obj(obj);
7446err:
7c9017e5
JB		 7447 return ret;
7448}
7449
8c9f3aaf
JB		 7450static int intel_default_queue_flip(struct drm_device *dev,
7451 struct drm_crtc *crtc,
7452 struct drm_framebuffer *fb,
7453 struct drm_i915_gem_object *obj)
7454{
7455 return -ENODEV;
7456}
7457
6b95a207
KH		 7458static int intel_crtc_page_flip(struct drm_crtc *crtc,
7459 struct drm_framebuffer *fb,
7460 struct drm_pending_vblank_event *event)
7461{
7462 struct drm_device *dev = crtc->dev;
7463 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7464 struct drm_framebuffer *old_fb = crtc->fb;
7465 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7467 struct intel_unpin_work *work;
8c9f3aaf 7468 unsigned long flags;
52e68630 7469 int ret;
6b95a207 7470
e6a595d2
VS		 7471 /* Can't change pixel format via MI display flips. */
7472 if (fb->pixel_format != crtc->fb->pixel_format)
7473 return -EINVAL;
7474
7475 /*
7476 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7477 * Note that pitch changes could also affect these register.
7478 */
7479 if (INTEL_INFO(dev)->gen > 3 &&
7480 (fb->offsets[0] != crtc->fb->offsets[0] ||
7481 fb->pitches[0] != crtc->fb->pitches[0]))
7482 return -EINVAL;
7483
6b95a207
KH		 7484 work = kzalloc(sizeof *work, GFP_KERNEL);
7485 if (work == NULL)
7486 return -ENOMEM;
7487
6b95a207 7488 work->event = event;
b4a98e57 7489 work->crtc = crtc;
4a35f83b 7490 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7491 INIT_WORK(&work->work, intel_unpin_work_fn);
7492
7317c75e
JB		 7493 ret = drm_vblank_get(dev, intel_crtc->pipe);
7494 if (ret)
7495 goto free_work;
7496
6b95a207
KH		 7497 /* We borrow the event spin lock for protecting unpin_work */
7498 spin_lock_irqsave(&dev->event_lock, flags);
7499 if (intel_crtc->unpin_work) {
7500 spin_unlock_irqrestore(&dev->event_lock, flags);
7501 kfree(work);
7317c75e 7502 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7503
7504 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7505 return -EBUSY;
7506 }
7507 intel_crtc->unpin_work = work;
7508 spin_unlock_irqrestore(&dev->event_lock, flags);
7509
b4a98e57
CW		 7510 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7511 flush_workqueue(dev_priv->wq);
7512
79158103
CW		 7513 ret = i915_mutex_lock_interruptible(dev);
7514 if (ret)
7515 goto cleanup;
6b95a207 7516
75dfca80 7517 /* Reference the objects for the scheduled work. */
05394f39
CW		 7518 drm_gem_object_reference(&work->old_fb_obj->base);
7519 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7520
7521 crtc->fb = fb;
96b099fd 7522
e1f99ce6 7523 work->pending_flip_obj = obj;
e1f99ce6 7524
4e5359cd
SF		 7525 work->enable_stall_check = true;
7526
b4a98e57 7527 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7528 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7529
8c9f3aaf
JB		 7530 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7531 if (ret)
7532 goto cleanup_pending;
6b95a207 7533
7782de3b 7534 intel_disable_fbc(dev);
f047e395 7535 intel_mark_fb_busy(obj);
6b95a207
KH		 7536 mutex_unlock(&dev->struct_mutex);
7537
e5510fac
JB		 7538 trace_i915_flip_request(intel_crtc->plane, obj);
7539
6b95a207 7540 return 0;
96b099fd 7541
8c9f3aaf 7542cleanup_pending:
b4a98e57 7543 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7544 crtc->fb = old_fb;
05394f39
CW		 7545 drm_gem_object_unreference(&work->old_fb_obj->base);
7546 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7547 mutex_unlock(&dev->struct_mutex);
7548
79158103 7549cleanup:
96b099fd
CW		 7550 spin_lock_irqsave(&dev->event_lock, flags);
7551 intel_crtc->unpin_work = NULL;
7552 spin_unlock_irqrestore(&dev->event_lock, flags);
7553
7317c75e
JB		 7554 drm_vblank_put(dev, intel_crtc->pipe);
7555free_work:
96b099fd
CW		 7556 kfree(work);
7557
7558 return ret;
6b95a207
KH		 7559}
7560
f6e5b160 7561static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7562 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7563 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7564};
7565
50f56119
DV		 7566static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7567 struct drm_crtc *crtc)
7568{
7569 struct drm_device *dev;
7570 struct drm_crtc *tmp;
7571 int crtc_mask = 1;
47f1c6c9 7572
50f56119 7573 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7574
50f56119 7575 dev = crtc->dev;
47f1c6c9 7576
50f56119
DV		 7577 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7578 if (tmp == crtc)
7579 break;
7580 crtc_mask <<= 1;
7581 }
47f1c6c9 7582
50f56119
DV		 7583 if (encoder->possible_crtcs & crtc_mask)
7584 return true;
7585 return false;
47f1c6c9 7586}
79e53945 7587
9a935856
DV		 7588/**
7589 * intel_modeset_update_staged_output_state
7590 *
7591 * Updates the staged output configuration state, e.g. after we've read out the
7592 * current hw state.
7593 */
7594static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7595{
9a935856
DV		 7596 struct intel_encoder *encoder;
7597 struct intel_connector *connector;
f6e5b160 7598
9a935856
DV		 7599 list_for_each_entry(connector, &dev->mode_config.connector_list,
7600 base.head) {
7601 connector->new_encoder =
7602 to_intel_encoder(connector->base.encoder);
7603 }
f6e5b160 7604
9a935856
DV		 7605 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7606 base.head) {
7607 encoder->new_crtc =
7608 to_intel_crtc(encoder->base.crtc);
7609 }
f6e5b160
CW		 7610}
7611
9a935856
DV		 7612/**
7613 * intel_modeset_commit_output_state
7614 *
7615 * This function copies the stage display pipe configuration to the real one.
7616 */
7617static void intel_modeset_commit_output_state(struct drm_device *dev)
7618{
7619 struct intel_encoder *encoder;
7620 struct intel_connector *connector;
f6e5b160 7621
9a935856
DV		 7622 list_for_each_entry(connector, &dev->mode_config.connector_list,
7623 base.head) {
7624 connector->base.encoder = &connector->new_encoder->base;
7625 }
f6e5b160 7626
9a935856
DV		 7627 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7628 base.head) {
7629 encoder->base.crtc = &encoder->new_crtc->base;
7630 }
7631}
7632
050f7aeb
DV		 7633static void
7634connected_sink_compute_bpp(struct intel_connector * connector,
7635 struct intel_crtc_config *pipe_config)
7636{
7637 int bpp = pipe_config->pipe_bpp;
7638
7639 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7640 connector->base.base.id,
7641 drm_get_connector_name(&connector->base));
7642
7643 /* Don't use an invalid EDID bpc value */
7644 if (connector->base.display_info.bpc &&
7645 connector->base.display_info.bpc * 3 < bpp) {
7646 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7647 bpp, connector->base.display_info.bpc*3);
7648 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7649 }
7650
7651 /* Clamp bpp to 8 on screens without EDID 1.4 */
7652 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7653 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7654 bpp);
7655 pipe_config->pipe_bpp = 24;
7656 }
7657}
7658
4e53c2e0 7659static int
050f7aeb
DV		 7660compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7661 struct drm_framebuffer *fb,
7662 struct intel_crtc_config *pipe_config)
4e53c2e0 7663{
050f7aeb
DV		 7664 struct drm_device *dev = crtc->base.dev;
7665 struct intel_connector *connector;
4e53c2e0
DV		 7666 int bpp;
7667
d42264b1
DV		 7668 switch (fb->pixel_format) {
7669 case DRM_FORMAT_C8:
4e53c2e0
DV		 7670 bpp = 8*3; /* since we go through a colormap */
7671 break;
d42264b1
DV		 7672 case DRM_FORMAT_XRGB1555:
7673 case DRM_FORMAT_ARGB1555:
7674 /* checked in intel_framebuffer_init already */
7675 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7676 return -EINVAL;
7677 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7678 bpp = 6*3; /* min is 18bpp */
7679 break;
d42264b1
DV		 7680 case DRM_FORMAT_XBGR8888:
7681 case DRM_FORMAT_ABGR8888:
7682 /* checked in intel_framebuffer_init already */
7683 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7684 return -EINVAL;
7685 case DRM_FORMAT_XRGB8888:
7686 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7687 bpp = 8*3;
7688 break;
d42264b1
DV		 7689 case DRM_FORMAT_XRGB2101010:
7690 case DRM_FORMAT_ARGB2101010:
7691 case DRM_FORMAT_XBGR2101010:
7692 case DRM_FORMAT_ABGR2101010:
7693 /* checked in intel_framebuffer_init already */
7694 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7695 return -EINVAL;
4e53c2e0
DV		 7696 bpp = 10*3;
7697 break;
baba133a 7698 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7699 default:
7700 DRM_DEBUG_KMS("unsupported depth\n");
7701 return -EINVAL;
7702 }
7703
4e53c2e0
DV		 7704 pipe_config->pipe_bpp = bpp;
7705
7706 /* Clamp display bpp to EDID value */
7707 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7708 base.head) {
1b829e05
DV		 7709 if (!connector->new_encoder ||
7710 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7711 continue;
7712
050f7aeb 7713 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7714 }
7715
7716 return bpp;
7717}
7718
c0b03411
DV		 7719static void intel_dump_pipe_config(struct intel_crtc *crtc,
7720 struct intel_crtc_config *pipe_config,
7721 const char *context)
7722{
7723 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7724 context, pipe_name(crtc->pipe));
7725
7726 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7727 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7728 pipe_config->pipe_bpp, pipe_config->dither);
7729 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7730 pipe_config->has_pch_encoder,
7731 pipe_config->fdi_lanes,
7732 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7733 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7734 pipe_config->fdi_m_n.tu);
7735 DRM_DEBUG_KMS("requested mode:\n");
7736 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7737 DRM_DEBUG_KMS("adjusted mode:\n");
7738 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7739 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7740 pipe_config->gmch_pfit.control,
7741 pipe_config->gmch_pfit.pgm_ratios,
7742 pipe_config->gmch_pfit.lvds_border_bits);
7743 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7744 pipe_config->pch_pfit.pos,
7745 pipe_config->pch_pfit.size);
42db64ef 7746 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7747}
7748
accfc0c5
DV		 7749static bool check_encoder_cloning(struct drm_crtc *crtc)
7750{
7751 int num_encoders = 0;
7752 bool uncloneable_encoders = false;
7753 struct intel_encoder *encoder;
7754
7755 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7756 base.head) {
7757 if (&encoder->new_crtc->base != crtc)
7758 continue;
7759
7760 num_encoders++;
7761 if (!encoder->cloneable)
7762 uncloneable_encoders = true;
7763 }
7764
7765 return !(num_encoders > 1 && uncloneable_encoders);
7766}
7767
b8cecdf5
DV		 7768static struct intel_crtc_config *
7769intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7770 struct drm_framebuffer *fb,
b8cecdf5 7771 struct drm_display_mode *mode)
ee7b9f93 7772{
7758a113 7773 struct drm_device *dev = crtc->dev;
7758a113
DV		 7774 struct drm_encoder_helper_funcs *encoder_funcs;
7775 struct intel_encoder *encoder;
b8cecdf5 7776 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7777 int plane_bpp, ret = -EINVAL;
7778 bool retry = true;
ee7b9f93 7779
accfc0c5
DV		 7780 if (!check_encoder_cloning(crtc)) {
7781 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7782 return ERR_PTR(-EINVAL);
7783 }
7784
b8cecdf5
DV		 7785 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7786 if (!pipe_config)
7758a113
DV		 7787 return ERR_PTR(-ENOMEM);
7788
b8cecdf5
DV		 7789 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7790 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7791 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
b8cecdf5 7792
050f7aeb
DV		 7793 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7794 * plane pixel format and any sink constraints into account. Returns the
7795 * source plane bpp so that dithering can be selected on mismatches
7796 * after encoders and crtc also have had their say. */
7797 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7798 fb, pipe_config);
4e53c2e0
DV		 7799 if (plane_bpp < 0)
7800 goto fail;
7801
e29c22c0 7802encoder_retry:
ef1b460d 7803 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 7804 pipe_config->port_clock = 0;
ef1b460d 7805 pipe_config->pixel_multiplier = 1;
ff9a6750 7806
7758a113
DV		 7807 /* Pass our mode to the connectors and the CRTC to give them a chance to
7808 * adjust it according to limitations or connector properties, and also
7809 * a chance to reject the mode entirely.
47f1c6c9 7810 */
7758a113
DV		 7811 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7812 base.head) {
47f1c6c9 7813
7758a113
DV		 7814 if (&encoder->new_crtc->base != crtc)
7815 continue;
7ae89233
DV		 7816
7817 if (encoder->compute_config) {
7818 if (!(encoder->compute_config(encoder, pipe_config))) {
7819 DRM_DEBUG_KMS("Encoder config failure\n");
7820 goto fail;
7821 }
7822
7823 continue;
7824 }
7825
7758a113 7826 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7827 if (!(encoder_funcs->mode_fixup(&encoder->base,
7828 &pipe_config->requested_mode,
7829 &pipe_config->adjusted_mode))) {
7758a113
DV		 7830 DRM_DEBUG_KMS("Encoder fixup failed\n");
7831 goto fail;
7832 }
ee7b9f93 7833 }
47f1c6c9 7834
ff9a6750
DV		 7835 /* Set default port clock if not overwritten by the encoder. Needs to be
7836 * done afterwards in case the encoder adjusts the mode. */
7837 if (!pipe_config->port_clock)
7838 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7839
e29c22c0
DV		 7840 ret = intel_crtc_compute_config(crtc, pipe_config);
7841 if (ret < 0) {
7758a113
DV		 7842 DRM_DEBUG_KMS("CRTC fixup failed\n");
7843 goto fail;
ee7b9f93 7844 }
e29c22c0
DV		 7845
7846 if (ret == RETRY) {
7847 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7848 ret = -EINVAL;
7849 goto fail;
7850 }
7851
7852 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7853 retry = false;
7854 goto encoder_retry;
7855 }
7856
4e53c2e0
DV		 7857 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7858 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7859 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7860
b8cecdf5 7861 return pipe_config;
7758a113 7862fail:
b8cecdf5 7863 kfree(pipe_config);
e29c22c0 7864 return ERR_PTR(ret);
ee7b9f93 7865}
47f1c6c9 7866
e2e1ed41
DV		 7867/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7868 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7869static void
7870intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7871 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7872{
7873 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7874 struct drm_device *dev = crtc->dev;
7875 struct intel_encoder *encoder;
7876 struct intel_connector *connector;
7877 struct drm_crtc *tmp_crtc;
79e53945 7878
e2e1ed41 7879 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7880
e2e1ed41
DV		 7881 /* Check which crtcs have changed outputs connected to them, these need
7882 * to be part of the prepare_pipes mask. We don't (yet) support global
7883 * modeset across multiple crtcs, so modeset_pipes will only have one
7884 * bit set at most. */
7885 list_for_each_entry(connector, &dev->mode_config.connector_list,
7886 base.head) {
7887 if (connector->base.encoder == &connector->new_encoder->base)
7888 continue;
79e53945 7889
e2e1ed41
DV		 7890 if (connector->base.encoder) {
7891 tmp_crtc = connector->base.encoder->crtc;
7892
7893 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7894 }
7895
7896 if (connector->new_encoder)
7897 *prepare_pipes |=
7898 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7899 }
7900
e2e1ed41
DV		 7901 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7902 base.head) {
7903 if (encoder->base.crtc == &encoder->new_crtc->base)
7904 continue;
7905
7906 if (encoder->base.crtc) {
7907 tmp_crtc = encoder->base.crtc;
7908
7909 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7910 }
7911
7912 if (encoder->new_crtc)
7913 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7914 }
7915
e2e1ed41
DV		 7916 /* Check for any pipes that will be fully disabled ... */
7917 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7918 base.head) {
7919 bool used = false;
22fd0fab 7920
e2e1ed41
DV		 7921 /* Don't try to disable disabled crtcs. */
7922 if (!intel_crtc->base.enabled)
7923 continue;
7e7d76c3 7924
e2e1ed41
DV		 7925 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7926 base.head) {
7927 if (encoder->new_crtc == intel_crtc)
7928 used = true;
7929 }
7930
7931 if (!used)
7932 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7933 }
7934
e2e1ed41
DV		 7935
7936 /* set_mode is also used to update properties on life display pipes. */
7937 intel_crtc = to_intel_crtc(crtc);
7938 if (crtc->enabled)
7939 *prepare_pipes |= 1 << intel_crtc->pipe;
7940
b6c5164d
DV		 7941 /*
7942 * For simplicity do a full modeset on any pipe where the output routing
7943 * changed. We could be more clever, but that would require us to be
7944 * more careful with calling the relevant encoder->mode_set functions.
7945 */
e2e1ed41
DV		 7946 if (*prepare_pipes)
7947 *modeset_pipes = *prepare_pipes;
7948
7949 /* ... and mask these out. */
7950 *modeset_pipes &= ~(*disable_pipes);
7951 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7952
7953 /*
7954 * HACK: We don't (yet) fully support global modesets. intel_set_config
7955 * obies this rule, but the modeset restore mode of
7956 * intel_modeset_setup_hw_state does not.
7957 */
7958 *modeset_pipes &= 1 << intel_crtc->pipe;
7959 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7960
7961 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7962 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7963}
79e53945 7964
ea9d758d 7965static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7966{
ea9d758d 7967 struct drm_encoder *encoder;
f6e5b160 7968 struct drm_device *dev = crtc->dev;
f6e5b160 7969
ea9d758d
DV		 7970 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7971 if (encoder->crtc == crtc)
7972 return true;
7973
7974 return false;
7975}
7976
7977static void
7978intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7979{
7980 struct intel_encoder *intel_encoder;
7981 struct intel_crtc *intel_crtc;
7982 struct drm_connector *connector;
7983
7984 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7985 base.head) {
7986 if (!intel_encoder->base.crtc)
7987 continue;
7988
7989 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7990
7991 if (prepare_pipes & (1 << intel_crtc->pipe))
7992 intel_encoder->connectors_active = false;
7993 }
7994
7995 intel_modeset_commit_output_state(dev);
7996
7997 /* Update computed state. */
7998 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7999 base.head) {
8000 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8001 }
8002
8003 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8004 if (!connector->encoder || !connector->encoder->crtc)
8005 continue;
8006
8007 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8008
8009 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8010 struct drm_property *dpms_property =
8011 dev->mode_config.dpms_property;
8012
ea9d758d 8013 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8014 drm_object_property_set_value(&connector->base,
68d34720
DV		 8015 dpms_property,
8016 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8017
8018 intel_encoder = to_intel_encoder(connector->encoder);
8019 intel_encoder->connectors_active = true;
8020 }
8021 }
8022
8023}
8024
25c5b266
DV		 8025#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8026 list_for_each_entry((intel_crtc), \
8027 &(dev)->mode_config.crtc_list, \
8028 base.head) \
0973f18f 8029 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8030
0e8ffe1b 8031static bool
2fa2fe9a
DV		 8032intel_pipe_config_compare(struct drm_device *dev,
8033 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8034 struct intel_crtc_config *pipe_config)
8035{
08a24034
DV		 8036#define PIPE_CONF_CHECK_I(name) \
8037 if (current_config->name != pipe_config->name) { \
8038 DRM_ERROR("mismatch in " #name " " \
8039 "(expected %i, found %i)\n", \
8040 current_config->name, \
8041 pipe_config->name); \
8042 return false; \
88adfff1
DV		 8043 }
8044
1bd1bd80
DV		 8045#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8046 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8047 DRM_ERROR("mismatch in " #name " " \
8048 "(expected %i, found %i)\n", \
8049 current_config->name & (mask), \
8050 pipe_config->name & (mask)); \
8051 return false; \
8052 }
8053
eccb140b
DV		 8054 PIPE_CONF_CHECK_I(cpu_transcoder);
8055
08a24034
DV		 8056 PIPE_CONF_CHECK_I(has_pch_encoder);
8057 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8058 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8059 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8060 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8061 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8062 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8063
1bd1bd80
DV		 8064 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8065 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8066 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8067 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8068 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8069 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8070
8071 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8072 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8073 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8074 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8075 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8076 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8077
8078 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8079 DRM_MODE_FLAG_INTERLACE);
8080
045ac3b5
JB		 8081 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8082 DRM_MODE_FLAG_PHSYNC);
8083 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8084 DRM_MODE_FLAG_NHSYNC);
8085 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8086 DRM_MODE_FLAG_PVSYNC);
8087 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8088 DRM_MODE_FLAG_NVSYNC);
8089
1bd1bd80
DV		 8090 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8091 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8092
2fa2fe9a
DV		 8093 PIPE_CONF_CHECK_I(gmch_pfit.control);
8094 /* pfit ratios are autocomputed by the hw on gen4+ */
8095 if (INTEL_INFO(dev)->gen < 4)
8096 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8097 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8098 PIPE_CONF_CHECK_I(pch_pfit.pos);
8099 PIPE_CONF_CHECK_I(pch_pfit.size);
8100
42db64ef
PZ		 8101 PIPE_CONF_CHECK_I(ips_enabled);
8102
08a24034 8103#undef PIPE_CONF_CHECK_I
1bd1bd80 8104#undef PIPE_CONF_CHECK_FLAGS
627eb5a3 8105
0e8ffe1b
DV		 8106 return true;
8107}
8108
b980514c 8109void
8af6cf88
DV		 8110intel_modeset_check_state(struct drm_device *dev)
8111{
0e8ffe1b 8112 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 8113 struct intel_crtc *crtc;
8114 struct intel_encoder *encoder;
8115 struct intel_connector *connector;
0e8ffe1b 8116 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8117
8118 list_for_each_entry(connector, &dev->mode_config.connector_list,
8119 base.head) {
8120 /* This also checks the encoder/connector hw state with the
8121 * ->get_hw_state callbacks. */
8122 intel_connector_check_state(connector);
8123
8124 WARN(&connector->new_encoder->base != connector->base.encoder,
8125 "connector's staged encoder doesn't match current encoder\n");
8126 }
8127
8128 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8129 base.head) {
8130 bool enabled = false;
8131 bool active = false;
8132 enum pipe pipe, tracked_pipe;
8133
8134 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8135 encoder->base.base.id,
8136 drm_get_encoder_name(&encoder->base));
8137
8138 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8139 "encoder's stage crtc doesn't match current crtc\n");
8140 WARN(encoder->connectors_active && !encoder->base.crtc,
8141 "encoder's active_connectors set, but no crtc\n");
8142
8143 list_for_each_entry(connector, &dev->mode_config.connector_list,
8144 base.head) {
8145 if (connector->base.encoder != &encoder->base)
8146 continue;
8147 enabled = true;
8148 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8149 active = true;
8150 }
8151 WARN(!!encoder->base.crtc != enabled,
8152 "encoder's enabled state mismatch "
8153 "(expected %i, found %i)\n",
8154 !!encoder->base.crtc, enabled);
8155 WARN(active && !encoder->base.crtc,
8156 "active encoder with no crtc\n");
8157
8158 WARN(encoder->connectors_active != active,
8159 "encoder's computed active state doesn't match tracked active state "
8160 "(expected %i, found %i)\n", active, encoder->connectors_active);
8161
8162 active = encoder->get_hw_state(encoder, &pipe);
8163 WARN(active != encoder->connectors_active,
8164 "encoder's hw state doesn't match sw tracking "
8165 "(expected %i, found %i)\n",
8166 encoder->connectors_active, active);
8167
8168 if (!encoder->base.crtc)
8169 continue;
8170
8171 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8172 WARN(active && pipe != tracked_pipe,
8173 "active encoder's pipe doesn't match"
8174 "(expected %i, found %i)\n",
8175 tracked_pipe, pipe);
8176
8177 }
8178
8179 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8180 base.head) {
8181 bool enabled = false;
8182 bool active = false;
8183
045ac3b5
JB		 8184 memset(&pipe_config, 0, sizeof(pipe_config));
8185
8af6cf88
DV		 8186 DRM_DEBUG_KMS("[CRTC:%d]\n",
8187 crtc->base.base.id);
8188
8189 WARN(crtc->active && !crtc->base.enabled,
8190 "active crtc, but not enabled in sw tracking\n");
8191
8192 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8193 base.head) {
8194 if (encoder->base.crtc != &crtc->base)
8195 continue;
8196 enabled = true;
8197 if (encoder->connectors_active)
8198 active = true;
045ac3b5
JB		 8199 if (encoder->get_config)
8200 encoder->get_config(encoder, &pipe_config);
8af6cf88
DV		 8201 }
8202 WARN(active != crtc->active,
8203 "crtc's computed active state doesn't match tracked active state "
8204 "(expected %i, found %i)\n", active, crtc->active);
8205 WARN(enabled != crtc->base.enabled,
8206 "crtc's computed enabled state doesn't match tracked enabled state "
8207 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8208
0e8ffe1b
DV		 8209 active = dev_priv->display.get_pipe_config(crtc,
8210 &pipe_config);
8211 WARN(crtc->active != active,
8212 "crtc active state doesn't match with hw state "
8213 "(expected %i, found %i)\n", crtc->active, active);
8214
c0b03411
DV		 8215 if (active &&
8216 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8217 WARN(1, "pipe state doesn't match!\n");
8218 intel_dump_pipe_config(crtc, &pipe_config,
8219 "[hw state]");
8220 intel_dump_pipe_config(crtc, &crtc->config,
8221 "[sw state]");
8222 }
8af6cf88
DV		 8223 }
8224}
8225
f30da187
DV		 8226static int __intel_set_mode(struct drm_crtc *crtc,
8227 struct drm_display_mode *mode,
8228 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8229{
8230 struct drm_device *dev = crtc->dev;
dbf2b54e 8231 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8232 struct drm_display_mode *saved_mode, *saved_hwmode;
8233 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8234 struct intel_crtc *intel_crtc;
8235 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8236 int ret = 0;
a6778b3c 8237
3ac18232 8238 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8239 if (!saved_mode)
8240 return -ENOMEM;
3ac18232 8241 saved_hwmode = saved_mode + 1;
a6778b3c 8242
e2e1ed41 8243 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8244 &prepare_pipes, &disable_pipes);
8245
3ac18232
TG		 8246 *saved_hwmode = crtc->hwmode;
8247 *saved_mode = crtc->mode;
a6778b3c 8248
25c5b266
DV		 8249 /* Hack: Because we don't (yet) support global modeset on multiple
8250 * crtcs, we don't keep track of the new mode for more than one crtc.
8251 * Hence simply check whether any bit is set in modeset_pipes in all the
8252 * pieces of code that are not yet converted to deal with mutliple crtcs
8253 * changing their mode at the same time. */
25c5b266 8254 if (modeset_pipes) {
4e53c2e0 8255 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8256 if (IS_ERR(pipe_config)) {
8257 ret = PTR_ERR(pipe_config);
8258 pipe_config = NULL;
8259
3ac18232 8260 goto out;
25c5b266 8261 }
c0b03411
DV		 8262 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8263 "[modeset]");
25c5b266 8264 }
a6778b3c 8265
460da916
DV		 8266 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8267 intel_crtc_disable(&intel_crtc->base);
8268
ea9d758d
DV		 8269 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8270 if (intel_crtc->base.enabled)
8271 dev_priv->display.crtc_disable(&intel_crtc->base);
8272 }
a6778b3c 8273
6c4c86f5
DV		 8274 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8275 * to set it here already despite that we pass it down the callchain.
f6e5b160 8276 */
b8cecdf5 8277 if (modeset_pipes) {
25c5b266 8278 crtc->mode = *mode;
b8cecdf5
DV		 8279 /* mode_set/enable/disable functions rely on a correct pipe
8280 * config. */
8281 to_intel_crtc(crtc)->config = *pipe_config;
8282 }
7758a113 8283
ea9d758d
DV		 8284 /* Only after disabling all output pipelines that will be changed can we
8285 * update the the output configuration. */
8286 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8287
47fab737
DV		 8288 if (dev_priv->display.modeset_global_resources)
8289 dev_priv->display.modeset_global_resources(dev);
8290
a6778b3c
DV		 8291 /* Set up the DPLL and any encoders state that needs to adjust or depend
8292 * on the DPLL.
f6e5b160 8293 */
25c5b266 8294 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8295 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8296 x, y, fb);
8297 if (ret)
8298 goto done;
a6778b3c
DV		 8299 }
8300
8301 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8302 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8303 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8304
25c5b266
DV		 8305 if (modeset_pipes) {
8306 /* Store real post-adjustment hardware mode. */
b8cecdf5 8307 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8308
25c5b266
DV		 8309 /* Calculate and store various constants which
8310 * are later needed by vblank and swap-completion
8311 * timestamping. They are derived from true hwmode.
8312 */
8313 drm_calc_timestamping_constants(crtc);
8314 }
a6778b3c
DV		 8315
8316 /* FIXME: add subpixel order */
8317done:
c0c36b94 8318 if (ret && crtc->enabled) {
3ac18232
TG		 8319 crtc->hwmode = *saved_hwmode;
8320 crtc->mode = *saved_mode;
a6778b3c
DV		 8321 }
8322
3ac18232 8323out:
b8cecdf5 8324 kfree(pipe_config);
3ac18232 8325 kfree(saved_mode);
a6778b3c 8326 return ret;
f6e5b160
CW		 8327}
8328
f30da187
DV		 8329int intel_set_mode(struct drm_crtc *crtc,
8330 struct drm_display_mode *mode,
8331 int x, int y, struct drm_framebuffer *fb)
8332{
8333 int ret;
8334
8335 ret = __intel_set_mode(crtc, mode, x, y, fb);
8336
8337 if (ret == 0)
8338 intel_modeset_check_state(crtc->dev);
8339
8340 return ret;
8341}
8342
c0c36b94
CW		 8343void intel_crtc_restore_mode(struct drm_crtc *crtc)
8344{
8345 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8346}
8347
25c5b266
DV		 8348#undef for_each_intel_crtc_masked
8349
d9e55608
DV		 8350static void intel_set_config_free(struct intel_set_config *config)
8351{
8352 if (!config)
8353 return;
8354
1aa4b628
DV		 8355 kfree(config->save_connector_encoders);
8356 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8357 kfree(config);
8358}
8359
85f9eb71
DV		 8360static int intel_set_config_save_state(struct drm_device *dev,
8361 struct intel_set_config *config)
8362{
85f9eb71
DV		 8363 struct drm_encoder *encoder;
8364 struct drm_connector *connector;
8365 int count;
8366
1aa4b628
DV		 8367 config->save_encoder_crtcs =
8368 kcalloc(dev->mode_config.num_encoder,
8369 sizeof(struct drm_crtc *), GFP_KERNEL);
8370 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8371 return -ENOMEM;
8372
1aa4b628
DV		 8373 config->save_connector_encoders =
8374 kcalloc(dev->mode_config.num_connector,
8375 sizeof(struct drm_encoder *), GFP_KERNEL);
8376 if (!config->save_connector_encoders)
85f9eb71
DV		 8377 return -ENOMEM;
8378
8379 /* Copy data. Note that driver private data is not affected.
8380 * Should anything bad happen only the expected state is
8381 * restored, not the drivers personal bookkeeping.
8382 */
85f9eb71
DV		 8383 count = 0;
8384 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8385 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8386 }
8387
8388 count = 0;
8389 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8390 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8391 }
8392
8393 return 0;
8394}
8395
8396static void intel_set_config_restore_state(struct drm_device *dev,
8397 struct intel_set_config *config)
8398{
9a935856
DV		 8399 struct intel_encoder *encoder;
8400 struct intel_connector *connector;
85f9eb71
DV		 8401 int count;
8402
85f9eb71 8403 count = 0;
9a935856
DV		 8404 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8405 encoder->new_crtc =
8406 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8407 }
8408
8409 count = 0;
9a935856
DV		 8410 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8411 connector->new_encoder =
8412 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8413 }
8414}
8415
5e2b584e
DV		 8416static void
8417intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8418 struct intel_set_config *config)
8419{
8420
8421 /* We should be able to check here if the fb has the same properties
8422 * and then just flip_or_move it */
8423 if (set->crtc->fb != set->fb) {
8424 /* If we have no fb then treat it as a full mode set */
8425 if (set->crtc->fb == NULL) {
8426 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8427 config->mode_changed = true;
8428 } else if (set->fb == NULL) {
8429 config->mode_changed = true;
72f4901e
DV		 8430 } else if (set->fb->pixel_format !=
8431 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8432 config->mode_changed = true;
8433 } else
8434 config->fb_changed = true;
8435 }
8436
835c5873 8437 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8438 config->fb_changed = true;
8439
8440 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8441 DRM_DEBUG_KMS("modes are different, full mode set\n");
8442 drm_mode_debug_printmodeline(&set->crtc->mode);
8443 drm_mode_debug_printmodeline(set->mode);
8444 config->mode_changed = true;
8445 }
8446}
8447
2e431051 8448static int
9a935856
DV		 8449intel_modeset_stage_output_state(struct drm_device *dev,
8450 struct drm_mode_set *set,
8451 struct intel_set_config *config)
50f56119 8452{
85f9eb71 8453 struct drm_crtc *new_crtc;
9a935856
DV		 8454 struct intel_connector *connector;
8455 struct intel_encoder *encoder;
2e431051 8456 int count, ro;
50f56119 8457
9abdda74 8458 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8459 * of connectors. For paranoia, double-check this. */
8460 WARN_ON(!set->fb && (set->num_connectors != 0));
8461 WARN_ON(set->fb && (set->num_connectors == 0));
8462
50f56119 8463 count = 0;
9a935856
DV		 8464 list_for_each_entry(connector, &dev->mode_config.connector_list,
8465 base.head) {
8466 /* Otherwise traverse passed in connector list and get encoders
8467 * for them. */
50f56119 8468 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8469 if (set->connectors[ro] == &connector->base) {
8470 connector->new_encoder = connector->encoder;
50f56119
DV		 8471 break;
8472 }
8473 }
8474
9a935856
DV		 8475 /* If we disable the crtc, disable all its connectors. Also, if
8476 * the connector is on the changing crtc but not on the new
8477 * connector list, disable it. */
8478 if ((!set->fb || ro == set->num_connectors) &&
8479 connector->base.encoder &&
8480 connector->base.encoder->crtc == set->crtc) {
8481 connector->new_encoder = NULL;
8482
8483 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8484 connector->base.base.id,
8485 drm_get_connector_name(&connector->base));
8486 }
8487
8488
8489 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8490 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8491 config->mode_changed = true;
50f56119
DV		 8492 }
8493 }
9a935856 8494 /* connector->new_encoder is now updated for all connectors. */
50f56119 8495
9a935856 8496 /* Update crtc of enabled connectors. */
50f56119 8497 count = 0;
9a935856
DV		 8498 list_for_each_entry(connector, &dev->mode_config.connector_list,
8499 base.head) {
8500 if (!connector->new_encoder)
50f56119
DV		 8501 continue;
8502
9a935856 8503 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8504
8505 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8506 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8507 new_crtc = set->crtc;
8508 }
8509
8510 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8511 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8512 new_crtc)) {
5e2b584e 8513 return -EINVAL;
50f56119 8514 }
9a935856
DV		 8515 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8516
8517 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8518 connector->base.base.id,
8519 drm_get_connector_name(&connector->base),
8520 new_crtc->base.id);
8521 }
8522
8523 /* Check for any encoders that needs to be disabled. */
8524 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8525 base.head) {
8526 list_for_each_entry(connector,
8527 &dev->mode_config.connector_list,
8528 base.head) {
8529 if (connector->new_encoder == encoder) {
8530 WARN_ON(!connector->new_encoder->new_crtc);
8531
8532 goto next_encoder;
8533 }
8534 }
8535 encoder->new_crtc = NULL;
8536next_encoder:
8537 /* Only now check for crtc changes so we don't miss encoders
8538 * that will be disabled. */
8539 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8540 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8541 config->mode_changed = true;
50f56119
DV		 8542 }
8543 }
9a935856 8544 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8545
2e431051
DV		 8546 return 0;
8547}
8548
8549static int intel_crtc_set_config(struct drm_mode_set *set)
8550{
8551 struct drm_device *dev;
2e431051
DV		 8552 struct drm_mode_set save_set;
8553 struct intel_set_config *config;
8554 int ret;
2e431051 8555
8d3e375e
DV		 8556 BUG_ON(!set);
8557 BUG_ON(!set->crtc);
8558 BUG_ON(!set->crtc->helper_private);
2e431051 8559
7e53f3a4
DV		 8560 /* Enforce sane interface api - has been abused by the fb helper. */
8561 BUG_ON(!set->mode && set->fb);
8562 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8563
2e431051
DV		 8564 if (set->fb) {
8565 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8566 set->crtc->base.id, set->fb->base.id,
8567 (int)set->num_connectors, set->x, set->y);
8568 } else {
8569 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8570 }
8571
8572 dev = set->crtc->dev;
8573
8574 ret = -ENOMEM;
8575 config = kzalloc(sizeof(*config), GFP_KERNEL);
8576 if (!config)
8577 goto out_config;
8578
8579 ret = intel_set_config_save_state(dev, config);
8580 if (ret)
8581 goto out_config;
8582
8583 save_set.crtc = set->crtc;
8584 save_set.mode = &set->crtc->mode;
8585 save_set.x = set->crtc->x;
8586 save_set.y = set->crtc->y;
8587 save_set.fb = set->crtc->fb;
8588
8589 /* Compute whether we need a full modeset, only an fb base update or no
8590 * change at all. In the future we might also check whether only the
8591 * mode changed, e.g. for LVDS where we only change the panel fitter in
8592 * such cases. */
8593 intel_set_config_compute_mode_changes(set, config);
8594
9a935856 8595 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8596 if (ret)
8597 goto fail;
8598
5e2b584e 8599 if (config->mode_changed) {
c0c36b94
CW		 8600 ret = intel_set_mode(set->crtc, set->mode,
8601 set->x, set->y, set->fb);
8602 if (ret) {
8603 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8604 set->crtc->base.id, ret);
87f1faa6
DV		 8605 goto fail;
8606 }
5e2b584e 8607 } else if (config->fb_changed) {
4878cae2
VS		 8608 intel_crtc_wait_for_pending_flips(set->crtc);
8609
4f660f49 8610 ret = intel_pipe_set_base(set->crtc,
94352cf9 8611 set->x, set->y, set->fb);
50f56119
DV		 8612 }
8613
d9e55608
DV		 8614 intel_set_config_free(config);
8615
50f56119
DV		 8616 return 0;
8617
8618fail:
85f9eb71 8619 intel_set_config_restore_state(dev, config);
50f56119
DV		 8620
8621 /* Try to restore the config */
5e2b584e 8622 if (config->mode_changed &&
c0c36b94
CW		 8623 intel_set_mode(save_set.crtc, save_set.mode,
8624 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8625 DRM_ERROR("failed to restore config after modeset failure\n");
8626
d9e55608
DV		 8627out_config:
8628 intel_set_config_free(config);
50f56119
DV		 8629 return ret;
8630}
f6e5b160
CW		 8631
8632static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8633 .cursor_set = intel_crtc_cursor_set,
8634 .cursor_move = intel_crtc_cursor_move,
8635 .gamma_set = intel_crtc_gamma_set,
50f56119 8636 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8637 .destroy = intel_crtc_destroy,
8638 .page_flip = intel_crtc_page_flip,
8639};
8640
79f689aa
PZ		 8641static void intel_cpu_pll_init(struct drm_device *dev)
8642{
affa9354 8643 if (HAS_DDI(dev))
79f689aa
PZ		 8644 intel_ddi_pll_init(dev);
8645}
8646
ee7b9f93
JB		 8647static void intel_pch_pll_init(struct drm_device *dev)
8648{
8649 drm_i915_private_t *dev_priv = dev->dev_private;
8650 int i;
8651
8652 if (dev_priv->num_pch_pll == 0) {
8653 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8654 return;
8655 }
8656
8657 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8658 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8659 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8660 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8661 }
8662}
8663
b358d0a6 8664static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8665{
22fd0fab 8666 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8667 struct intel_crtc *intel_crtc;
8668 int i;
8669
8670 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8671 if (intel_crtc == NULL)
8672 return;
8673
8674 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8675
8676 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8677 for (i = 0; i < 256; i++) {
8678 intel_crtc->lut_r[i] = i;
8679 intel_crtc->lut_g[i] = i;
8680 intel_crtc->lut_b[i] = i;
8681 }
8682
80824003
JB		 8683 /* Swap pipes & planes for FBC on pre-965 */
8684 intel_crtc->pipe = pipe;
8685 intel_crtc->plane = pipe;
e2e767ab 8686 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8687 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8688 intel_crtc->plane = !pipe;
80824003
JB		 8689 }
8690
22fd0fab
JB		 8691 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8692 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8693 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8694 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8695
79e53945 8696 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8697}
8698
08d7b3d1 8699int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8700 struct drm_file *file)
08d7b3d1 8701{
08d7b3d1 8702 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8703 struct drm_mode_object *drmmode_obj;
8704 struct intel_crtc *crtc;
08d7b3d1 8705
1cff8f6b
DV		 8706 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8707 return -ENODEV;
08d7b3d1 8708
c05422d5
DV		 8709 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8710 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8711
c05422d5 8712 if (!drmmode_obj) {
08d7b3d1
CW		 8713 DRM_ERROR("no such CRTC id\n");
8714 return -EINVAL;
8715 }
8716
c05422d5
DV		 8717 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8718 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8719
c05422d5 8720 return 0;
08d7b3d1
CW		 8721}
8722
66a9278e 8723static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8724{
66a9278e
DV		 8725 struct drm_device *dev = encoder->base.dev;
8726 struct intel_encoder *source_encoder;
79e53945 8727 int index_mask = 0;
79e53945
JB		 8728 int entry = 0;
8729
66a9278e
DV		 8730 list_for_each_entry(source_encoder,
8731 &dev->mode_config.encoder_list, base.head) {
8732
8733 if (encoder == source_encoder)
79e53945 8734 index_mask |= (1 << entry);
66a9278e
DV		 8735
8736 /* Intel hw has only one MUX where enocoders could be cloned. */
8737 if (encoder->cloneable && source_encoder->cloneable)
8738 index_mask |= (1 << entry);
8739
79e53945
JB		 8740 entry++;
8741 }
4ef69c7a 8742
79e53945
JB		 8743 return index_mask;
8744}
8745
4d302442
CW		 8746static bool has_edp_a(struct drm_device *dev)
8747{
8748 struct drm_i915_private *dev_priv = dev->dev_private;
8749
8750 if (!IS_MOBILE(dev))
8751 return false;
8752
8753 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8754 return false;
8755
8756 if (IS_GEN5(dev) &&
8757 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8758 return false;
8759
8760 return true;
8761}
8762
79e53945
JB		 8763static void intel_setup_outputs(struct drm_device *dev)
8764{
725e30ad 8765 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8766 struct intel_encoder *encoder;
cb0953d7 8767 bool dpd_is_edp = false;
f3cfcba6 8768 bool has_lvds;
79e53945 8769
f3cfcba6 8770 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8771 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8772 /* disable the panel fitter on everything but LVDS */
8773 I915_WRITE(PFIT_CONTROL, 0);
8774 }
79e53945 8775
c40c0f5b 8776 if (!IS_ULT(dev))
79935fca 8777 intel_crt_init(dev);
cb0953d7 8778
affa9354 8779 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8780 int found;
8781
8782 /* Haswell uses DDI functions to detect digital outputs */
8783 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8784 /* DDI A only supports eDP */
8785 if (found)
8786 intel_ddi_init(dev, PORT_A);
8787
8788 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8789 * register */
8790 found = I915_READ(SFUSE_STRAP);
8791
8792 if (found & SFUSE_STRAP_DDIB_DETECTED)
8793 intel_ddi_init(dev, PORT_B);
8794 if (found & SFUSE_STRAP_DDIC_DETECTED)
8795 intel_ddi_init(dev, PORT_C);
8796 if (found & SFUSE_STRAP_DDID_DETECTED)
8797 intel_ddi_init(dev, PORT_D);
8798 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8799 int found;
270b3042
DV		 8800 dpd_is_edp = intel_dpd_is_edp(dev);
8801
8802 if (has_edp_a(dev))
8803 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8804
dc0fa718 8805 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8806 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8807 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8808 if (!found)
e2debe91 8809 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8810 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8811 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8812 }
8813
dc0fa718 8814 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8815 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8816
dc0fa718 8817 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8818 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8819
5eb08b69 8820 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8821 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8822
270b3042 8823 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8824 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8825 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8826 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8827 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8828 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8829
dc0fa718 8830 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8831 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8832 PORT_B);
67cfc203
VS		 8833 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8834 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8835 }
103a196f 8836 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8837 bool found = false;
7d57382e 8838
e2debe91 8839 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8840 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8841 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8842 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8843 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8844 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8845 }
27185ae1 8846
e7281eab 8847 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8848 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 8849 }
13520b05
KH		 8850
8851 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8852
e2debe91 8853 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8854 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8855 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8856 }
27185ae1 8857
e2debe91 8858 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8859
b01f2c3a
JB		 8860 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8861 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8862 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 8863 }
e7281eab 8864 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8865 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 8866 }
27185ae1 8867
b01f2c3a 8868 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 8869 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 8870 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 8871 } else if (IS_GEN2(dev))
79e53945
JB		 8872 intel_dvo_init(dev);
8873
103a196f 8874 if (SUPPORTS_TV(dev))
79e53945
JB		 8875 intel_tv_init(dev);
8876
4ef69c7a
CW		 8877 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8878 encoder->base.possible_crtcs = encoder->crtc_mask;
8879 encoder->base.possible_clones =
66a9278e 8880 intel_encoder_clones(encoder);
79e53945 8881 }
47356eb6 8882
dde86e2d 8883 intel_init_pch_refclk(dev);
270b3042
DV		 8884
8885 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8886}
8887
8888static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8889{
8890 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8891
8892 drm_framebuffer_cleanup(fb);
05394f39 8893 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8894
8895 kfree(intel_fb);
8896}
8897
8898static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8899 struct drm_file *file,
79e53945
JB		 8900 unsigned int *handle)
8901{
8902 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8903 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8904
05394f39 8905 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8906}
8907
8908static const struct drm_framebuffer_funcs intel_fb_funcs = {
8909 .destroy = intel_user_framebuffer_destroy,
8910 .create_handle = intel_user_framebuffer_create_handle,
8911};
8912
38651674
DA		 8913int intel_framebuffer_init(struct drm_device *dev,
8914 struct intel_framebuffer *intel_fb,
308e5bcb 8915 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8916 struct drm_i915_gem_object *obj)
79e53945 8917{
79e53945
JB		 8918 int ret;
8919
c16ed4be
CW		 8920 if (obj->tiling_mode == I915_TILING_Y) {
8921 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8922 return -EINVAL;
c16ed4be 8923 }
57cd6508 8924
c16ed4be
CW		 8925 if (mode_cmd->pitches[0] & 63) {
8926 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8927 mode_cmd->pitches[0]);
57cd6508 8928 return -EINVAL;
c16ed4be 8929 }
57cd6508 8930
5d7bd705 8931 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8932 if (mode_cmd->pitches[0] > 32768) {
8933 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8934 mode_cmd->pitches[0]);
5d7bd705 8935 return -EINVAL;
c16ed4be 8936 }
5d7bd705
VS		 8937
8938 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8939 mode_cmd->pitches[0] != obj->stride) {
8940 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8941 mode_cmd->pitches[0], obj->stride);
5d7bd705 8942 return -EINVAL;
c16ed4be 8943 }
5d7bd705 8944
57779d06 8945 /* Reject formats not supported by any plane early. */
308e5bcb 8946 switch (mode_cmd->pixel_format) {
57779d06 8947 case DRM_FORMAT_C8:
04b3924d
VS		 8948 case DRM_FORMAT_RGB565:
8949 case DRM_FORMAT_XRGB8888:
8950 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8951 break;
8952 case DRM_FORMAT_XRGB1555:
8953 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8954 if (INTEL_INFO(dev)->gen > 3) {
8955 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8956 return -EINVAL;
c16ed4be 8957 }
57779d06
VS		 8958 break;
8959 case DRM_FORMAT_XBGR8888:
8960 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8961 case DRM_FORMAT_XRGB2101010:
8962 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8963 case DRM_FORMAT_XBGR2101010:
8964 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8965 if (INTEL_INFO(dev)->gen < 4) {
8966 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8967 return -EINVAL;
c16ed4be 8968 }
b5626747 8969 break;
04b3924d
VS		 8970 case DRM_FORMAT_YUYV:
8971 case DRM_FORMAT_UYVY:
8972 case DRM_FORMAT_YVYU:
8973 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8974 if (INTEL_INFO(dev)->gen < 5) {
8975 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8976 return -EINVAL;
c16ed4be 8977 }
57cd6508
CW		 8978 break;
8979 default:
c16ed4be 8980 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8981 return -EINVAL;
8982 }
8983
90f9a336
VS		 8984 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8985 if (mode_cmd->offsets[0] != 0)
8986 return -EINVAL;
8987
c7d73f6a
DV		 8988 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8989 intel_fb->obj = obj;
8990
79e53945
JB		 8991 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8992 if (ret) {
8993 DRM_ERROR("framebuffer init failed %d\n", ret);
8994 return ret;
8995 }
8996
79e53945
JB		 8997 return 0;
8998}
8999
79e53945
JB		 9000static struct drm_framebuffer *
9001intel_user_framebuffer_create(struct drm_device *dev,
9002 struct drm_file *filp,
308e5bcb 9003 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9004{
05394f39 9005 struct drm_i915_gem_object *obj;
79e53945 9006
308e5bcb
JB		 9007 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9008 mode_cmd->handles[0]));
c8725226 9009 if (&obj->base == NULL)
cce13ff7 9010 return ERR_PTR(-ENOENT);
79e53945 9011
d2dff872 9012 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9013}
9014
79e53945 9015static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9016 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9017 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9018};
9019
e70236a8
JB		 9020/* Set up chip specific display functions */
9021static void intel_init_display(struct drm_device *dev)
9022{
9023 struct drm_i915_private *dev_priv = dev->dev_private;
9024
ee9300bb
DV		 9025 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9026 dev_priv->display.find_dpll = g4x_find_best_dpll;
9027 else if (IS_VALLEYVIEW(dev))
9028 dev_priv->display.find_dpll = vlv_find_best_dpll;
9029 else if (IS_PINEVIEW(dev))
9030 dev_priv->display.find_dpll = pnv_find_best_dpll;
9031 else
9032 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9033
affa9354 9034 if (HAS_DDI(dev)) {
0e8ffe1b 9035 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9036 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9037 dev_priv->display.crtc_enable = haswell_crtc_enable;
9038 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9039 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9040 dev_priv->display.update_plane = ironlake_update_plane;
9041 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9042 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9043 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9044 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9045 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9046 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9047 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9048 } else if (IS_VALLEYVIEW(dev)) {
9049 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9050 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9051 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9052 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9053 dev_priv->display.off = i9xx_crtc_off;
9054 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9055 } else {
0e8ffe1b 9056 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9057 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9058 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9059 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9060 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9061 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9062 }
e70236a8 9063
e70236a8 9064 /* Returns the core display clock speed */
25eb05fc
JB		 9065 if (IS_VALLEYVIEW(dev))
9066 dev_priv->display.get_display_clock_speed =
9067 valleyview_get_display_clock_speed;
9068 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9069 dev_priv->display.get_display_clock_speed =
9070 i945_get_display_clock_speed;
9071 else if (IS_I915G(dev))
9072 dev_priv->display.get_display_clock_speed =
9073 i915_get_display_clock_speed;
f2b115e6 9074 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9075 dev_priv->display.get_display_clock_speed =
9076 i9xx_misc_get_display_clock_speed;
9077 else if (IS_I915GM(dev))
9078 dev_priv->display.get_display_clock_speed =
9079 i915gm_get_display_clock_speed;
9080 else if (IS_I865G(dev))
9081 dev_priv->display.get_display_clock_speed =
9082 i865_get_display_clock_speed;
f0f8a9ce 9083 else if (IS_I85X(dev))
e70236a8
JB		 9084 dev_priv->display.get_display_clock_speed =
9085 i855_get_display_clock_speed;
9086 else /* 852, 830 */
9087 dev_priv->display.get_display_clock_speed =
9088 i830_get_display_clock_speed;
9089
7f8a8569 9090 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9091 if (IS_GEN5(dev)) {
674cf967 9092 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9093 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9094 } else if (IS_GEN6(dev)) {
674cf967 9095 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9096 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9097 } else if (IS_IVYBRIDGE(dev)) {
9098 /* FIXME: detect B0+ stepping and use auto training */
9099 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9100 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9101 dev_priv->display.modeset_global_resources =
9102 ivb_modeset_global_resources;
c82e4d26
ED		 9103 } else if (IS_HASWELL(dev)) {
9104 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9105 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9106 dev_priv->display.modeset_global_resources =
9107 haswell_modeset_global_resources;
a0e63c22 9108 }
6067aaea 9109 } else if (IS_G4X(dev)) {
e0dac65e 9110 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9111 }
8c9f3aaf
JB		 9112
9113 /* Default just returns -ENODEV to indicate unsupported */
9114 dev_priv->display.queue_flip = intel_default_queue_flip;
9115
9116 switch (INTEL_INFO(dev)->gen) {
9117 case 2:
9118 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9119 break;
9120
9121 case 3:
9122 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9123 break;
9124
9125 case 4:
9126 case 5:
9127 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9128 break;
9129
9130 case 6:
9131 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9132 break;
7c9017e5
JB		 9133 case 7:
9134 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9135 break;
8c9f3aaf 9136 }
e70236a8
JB		 9137}
9138
b690e96c
JB		 9139/*
9140 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9141 * resume, or other times. This quirk makes sure that's the case for
9142 * affected systems.
9143 */
0206e353 9144static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9145{
9146 struct drm_i915_private *dev_priv = dev->dev_private;
9147
9148 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9149 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9150}
9151
435793df
KP		 9152/*
9153 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9154 */
9155static void quirk_ssc_force_disable(struct drm_device *dev)
9156{
9157 struct drm_i915_private *dev_priv = dev->dev_private;
9158 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9159 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9160}
9161
4dca20ef 9162/*
5a15ab5b
CE		 9163 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9164 * brightness value
4dca20ef
CE		 9165 */
9166static void quirk_invert_brightness(struct drm_device *dev)
9167{
9168 struct drm_i915_private *dev_priv = dev->dev_private;
9169 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9170 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9171}
9172
b690e96c
JB		 9173struct intel_quirk {
9174 int device;
9175 int subsystem_vendor;
9176 int subsystem_device;
9177 void (*hook)(struct drm_device *dev);
9178};
9179
5f85f176
EE		 9180/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9181struct intel_dmi_quirk {
9182 void (*hook)(struct drm_device *dev);
9183 const struct dmi_system_id (*dmi_id_list)[];
9184};
9185
9186static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9187{
9188 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9189 return 1;
9190}
9191
9192static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9193 {
9194 .dmi_id_list = &(const struct dmi_system_id[]) {
9195 {
9196 .callback = intel_dmi_reverse_brightness,
9197 .ident = "NCR Corporation",
9198 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9199 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9200 },
9201 },
9202 { } /* terminating entry */
9203 },
9204 .hook = quirk_invert_brightness,
9205 },
9206};
9207
c43b5634 9208static struct intel_quirk intel_quirks[] = {
b690e96c 9209 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9210 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9211
b690e96c
JB		 9212 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9213 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9214
b690e96c
JB		 9215 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9216 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9217
ccd0d36e 9218 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9219 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9220 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9221
9222 /* Lenovo U160 cannot use SSC on LVDS */
9223 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9224
9225 /* Sony Vaio Y cannot use SSC on LVDS */
9226 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9227
9228 /* Acer Aspire 5734Z must invert backlight brightness */
9229 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9230
9231 /* Acer/eMachines G725 */
9232 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9233
9234 /* Acer/eMachines e725 */
9235 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9236
9237 /* Acer/Packard Bell NCL20 */
9238 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9239
9240 /* Acer Aspire 4736Z */
9241 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9242};
9243
9244static void intel_init_quirks(struct drm_device *dev)
9245{
9246 struct pci_dev *d = dev->pdev;
9247 int i;
9248
9249 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9250 struct intel_quirk *q = &intel_quirks[i];
9251
9252 if (d->device == q->device &&
9253 (d->subsystem_vendor == q->subsystem_vendor ||
9254 q->subsystem_vendor == PCI_ANY_ID) &&
9255 (d->subsystem_device == q->subsystem_device ||
9256 q->subsystem_device == PCI_ANY_ID))
9257 q->hook(dev);
9258 }
5f85f176
EE		 9259 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9260 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9261 intel_dmi_quirks[i].hook(dev);
9262 }
b690e96c
JB		 9263}
9264
9cce37f4
JB		 9265/* Disable the VGA plane that we never use */
9266static void i915_disable_vga(struct drm_device *dev)
9267{
9268 struct drm_i915_private *dev_priv = dev->dev_private;
9269 u8 sr1;
766aa1c4 9270 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9271
9272 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9273 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9274 sr1 = inb(VGA_SR_DATA);
9275 outb(sr1 | 1<<5, VGA_SR_DATA);
9276 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9277 udelay(300);
9278
9279 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9280 POSTING_READ(vga_reg);
9281}
9282
f817586c
DV		 9283void intel_modeset_init_hw(struct drm_device *dev)
9284{
fa42e23c 9285 intel_init_power_well(dev);
0232e927 9286
a8f78b58
ED		 9287 intel_prepare_ddi(dev);
9288
f817586c
DV		 9289 intel_init_clock_gating(dev);
9290
79f5b2c7 9291 mutex_lock(&dev->struct_mutex);
8090c6b9 9292 intel_enable_gt_powersave(dev);
79f5b2c7 9293 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9294}
9295
7d708ee4
ID		 9296void intel_modeset_suspend_hw(struct drm_device *dev)
9297{
9298 intel_suspend_hw(dev);
9299}
9300
79e53945
JB		 9301void intel_modeset_init(struct drm_device *dev)
9302{
652c393a 9303 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9304 int i, j, ret;
79e53945
JB		 9305
9306 drm_mode_config_init(dev);
9307
9308 dev->mode_config.min_width = 0;
9309 dev->mode_config.min_height = 0;
9310
019d96cb
DA		 9311 dev->mode_config.preferred_depth = 24;
9312 dev->mode_config.prefer_shadow = 1;
9313
e6ecefaa 9314 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9315
b690e96c
JB		 9316 intel_init_quirks(dev);
9317
1fa61106
ED		 9318 intel_init_pm(dev);
9319
e3c74757
BW		 9320 if (INTEL_INFO(dev)->num_pipes == 0)
9321 return;
9322
e70236a8
JB		 9323 intel_init_display(dev);
9324
a6c45cf0
CW		 9325 if (IS_GEN2(dev)) {
9326 dev->mode_config.max_width = 2048;
9327 dev->mode_config.max_height = 2048;
9328 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9329 dev->mode_config.max_width = 4096;
9330 dev->mode_config.max_height = 4096;
79e53945 9331 } else {
a6c45cf0
CW		 9332 dev->mode_config.max_width = 8192;
9333 dev->mode_config.max_height = 8192;
79e53945 9334 }
5d4545ae 9335 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9336
28c97730 9337 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9338 INTEL_INFO(dev)->num_pipes,
9339 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9340
7eb552ae 9341 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9342 intel_crtc_init(dev, i);
7f1f3851
JB		 9343 for (j = 0; j < dev_priv->num_plane; j++) {
9344 ret = intel_plane_init(dev, i, j);
9345 if (ret)
06da8da2
VS		 9346 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9347 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9348 }
79e53945
JB		 9349 }
9350
79f689aa 9351 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9352 intel_pch_pll_init(dev);
9353
9cce37f4
JB		 9354 /* Just disable it once at startup */
9355 i915_disable_vga(dev);
79e53945 9356 intel_setup_outputs(dev);
11be49eb
CW		 9357
9358 /* Just in case the BIOS is doing something questionable. */
9359 intel_disable_fbc(dev);
2c7111db
CW		 9360}
9361
24929352
DV		 9362static void
9363intel_connector_break_all_links(struct intel_connector *connector)
9364{
9365 connector->base.dpms = DRM_MODE_DPMS_OFF;
9366 connector->base.encoder = NULL;
9367 connector->encoder->connectors_active = false;
9368 connector->encoder->base.crtc = NULL;
9369}
9370
7fad798e
DV		 9371static void intel_enable_pipe_a(struct drm_device *dev)
9372{
9373 struct intel_connector *connector;
9374 struct drm_connector *crt = NULL;
9375 struct intel_load_detect_pipe load_detect_temp;
9376
9377 /* We can't just switch on the pipe A, we need to set things up with a
9378 * proper mode and output configuration. As a gross hack, enable pipe A
9379 * by enabling the load detect pipe once. */
9380 list_for_each_entry(connector,
9381 &dev->mode_config.connector_list,
9382 base.head) {
9383 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9384 crt = &connector->base;
9385 break;
9386 }
9387 }
9388
9389 if (!crt)
9390 return;
9391
9392 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9393 intel_release_load_detect_pipe(crt, &load_detect_temp);
9394
652c393a 9395
7fad798e
DV		 9396}
9397
fa555837
DV		 9398static bool
9399intel_check_plane_mapping(struct intel_crtc *crtc)
9400{
7eb552ae
BW		 9401 struct drm_device *dev = crtc->base.dev;
9402 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9403 u32 reg, val;
9404
7eb552ae 9405 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9406 return true;
9407
9408 reg = DSPCNTR(!crtc->plane);
9409 val = I915_READ(reg);
9410
9411 if ((val & DISPLAY_PLANE_ENABLE) &&
9412 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9413 return false;
9414
9415 return true;
9416}
9417
24929352
DV		 9418static void intel_sanitize_crtc(struct intel_crtc *crtc)
9419{
9420 struct drm_device *dev = crtc->base.dev;
9421 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9422 u32 reg;
24929352 9423
24929352 9424 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9425 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9426 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9427
9428 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9429 * disable the crtc (and hence change the state) if it is wrong. Note
9430 * that gen4+ has a fixed plane -> pipe mapping. */
9431 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9432 struct intel_connector *connector;
9433 bool plane;
9434
24929352
DV		 9435 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9436 crtc->base.base.id);
9437
9438 /* Pipe has the wrong plane attached and the plane is active.
9439 * Temporarily change the plane mapping and disable everything
9440 * ... */
9441 plane = crtc->plane;
9442 crtc->plane = !plane;
9443 dev_priv->display.crtc_disable(&crtc->base);
9444 crtc->plane = plane;
9445
9446 /* ... and break all links. */
9447 list_for_each_entry(connector, &dev->mode_config.connector_list,
9448 base.head) {
9449 if (connector->encoder->base.crtc != &crtc->base)
9450 continue;
9451
9452 intel_connector_break_all_links(connector);
9453 }
9454
9455 WARN_ON(crtc->active);
9456 crtc->base.enabled = false;
9457 }
24929352 9458
7fad798e
DV		 9459 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9460 crtc->pipe == PIPE_A && !crtc->active) {
9461 /* BIOS forgot to enable pipe A, this mostly happens after
9462 * resume. Force-enable the pipe to fix this, the update_dpms
9463 * call below we restore the pipe to the right state, but leave
9464 * the required bits on. */
9465 intel_enable_pipe_a(dev);
9466 }
9467
24929352
DV		 9468 /* Adjust the state of the output pipe according to whether we
9469 * have active connectors/encoders. */
9470 intel_crtc_update_dpms(&crtc->base);
9471
9472 if (crtc->active != crtc->base.enabled) {
9473 struct intel_encoder *encoder;
9474
9475 /* This can happen either due to bugs in the get_hw_state
9476 * functions or because the pipe is force-enabled due to the
9477 * pipe A quirk. */
9478 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9479 crtc->base.base.id,
9480 crtc->base.enabled ? "enabled" : "disabled",
9481 crtc->active ? "enabled" : "disabled");
9482
9483 crtc->base.enabled = crtc->active;
9484
9485 /* Because we only establish the connector -> encoder ->
9486 * crtc links if something is active, this means the
9487 * crtc is now deactivated. Break the links. connector
9488 * -> encoder links are only establish when things are
9489 * actually up, hence no need to break them. */
9490 WARN_ON(crtc->active);
9491
9492 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9493 WARN_ON(encoder->connectors_active);
9494 encoder->base.crtc = NULL;
9495 }
9496 }
9497}
9498
9499static void intel_sanitize_encoder(struct intel_encoder *encoder)
9500{
9501 struct intel_connector *connector;
9502 struct drm_device *dev = encoder->base.dev;
9503
9504 /* We need to check both for a crtc link (meaning that the
9505 * encoder is active and trying to read from a pipe) and the
9506 * pipe itself being active. */
9507 bool has_active_crtc = encoder->base.crtc &&
9508 to_intel_crtc(encoder->base.crtc)->active;
9509
9510 if (encoder->connectors_active && !has_active_crtc) {
9511 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9512 encoder->base.base.id,
9513 drm_get_encoder_name(&encoder->base));
9514
9515 /* Connector is active, but has no active pipe. This is
9516 * fallout from our resume register restoring. Disable
9517 * the encoder manually again. */
9518 if (encoder->base.crtc) {
9519 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9520 encoder->base.base.id,
9521 drm_get_encoder_name(&encoder->base));
9522 encoder->disable(encoder);
9523 }
9524
9525 /* Inconsistent output/port/pipe state happens presumably due to
9526 * a bug in one of the get_hw_state functions. Or someplace else
9527 * in our code, like the register restore mess on resume. Clamp
9528 * things to off as a safer default. */
9529 list_for_each_entry(connector,
9530 &dev->mode_config.connector_list,
9531 base.head) {
9532 if (connector->encoder != encoder)
9533 continue;
9534
9535 intel_connector_break_all_links(connector);
9536 }
9537 }
9538 /* Enabled encoders without active connectors will be fixed in
9539 * the crtc fixup. */
9540}
9541
44cec740 9542void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9543{
9544 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9545 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9546
9547 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9548 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9549 i915_disable_vga(dev);
0fde901f
KM		 9550 }
9551}
9552
24929352
DV		 9553/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9554 * and i915 state tracking structures. */
45e2b5f6
DV		 9555void intel_modeset_setup_hw_state(struct drm_device *dev,
9556 bool force_restore)
24929352
DV		 9557{
9558 struct drm_i915_private *dev_priv = dev->dev_private;
9559 enum pipe pipe;
b5644d05 9560 struct drm_plane *plane;
24929352
DV		 9561 struct intel_crtc *crtc;
9562 struct intel_encoder *encoder;
9563 struct intel_connector *connector;
9564
0e8ffe1b
DV		 9565 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9566 base.head) {
88adfff1 9567 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9568
0e8ffe1b
DV		 9569 crtc->active = dev_priv->display.get_pipe_config(crtc,
9570 &crtc->config);
24929352
DV		 9571
9572 crtc->base.enabled = crtc->active;
9573
9574 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9575 crtc->base.base.id,
9576 crtc->active ? "enabled" : "disabled");
9577 }
9578
affa9354 9579 if (HAS_DDI(dev))
6441ab5f
PZ		 9580 intel_ddi_setup_hw_pll_state(dev);
9581
24929352
DV		 9582 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9583 base.head) {
9584 pipe = 0;
9585
9586 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9587 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9588 encoder->base.crtc = &crtc->base;
9589 if (encoder->get_config)
9590 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9591 } else {
9592 encoder->base.crtc = NULL;
9593 }
9594
9595 encoder->connectors_active = false;
9596 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9597 encoder->base.base.id,
9598 drm_get_encoder_name(&encoder->base),
9599 encoder->base.crtc ? "enabled" : "disabled",
9600 pipe);
9601 }
9602
9603 list_for_each_entry(connector, &dev->mode_config.connector_list,
9604 base.head) {
9605 if (connector->get_hw_state(connector)) {
9606 connector->base.dpms = DRM_MODE_DPMS_ON;
9607 connector->encoder->connectors_active = true;
9608 connector->base.encoder = &connector->encoder->base;
9609 } else {
9610 connector->base.dpms = DRM_MODE_DPMS_OFF;
9611 connector->base.encoder = NULL;
9612 }
9613 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9614 connector->base.base.id,
9615 drm_get_connector_name(&connector->base),
9616 connector->base.encoder ? "enabled" : "disabled");
9617 }
9618
9619 /* HW state is read out, now we need to sanitize this mess. */
9620 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9621 base.head) {
9622 intel_sanitize_encoder(encoder);
9623 }
9624
9625 for_each_pipe(pipe) {
9626 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9627 intel_sanitize_crtc(crtc);
c0b03411 9628 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 9629 }
9a935856 9630
45e2b5f6 9631 if (force_restore) {
f30da187
DV		 9632 /*
9633 * We need to use raw interfaces for restoring state to avoid
9634 * checking (bogus) intermediate states.
9635 */
45e2b5f6 9636 for_each_pipe(pipe) {
b5644d05
JB		 9637 struct drm_crtc *crtc =
9638 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9639
9640 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9641 crtc->fb);
45e2b5f6 9642 }
b5644d05
JB		 9643 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9644 intel_plane_restore(plane);
0fde901f
KM		 9645
9646 i915_redisable_vga(dev);
45e2b5f6
DV		 9647 } else {
9648 intel_modeset_update_staged_output_state(dev);
9649 }
8af6cf88
DV		 9650
9651 intel_modeset_check_state(dev);
2e938892
DV		 9652
9653 drm_mode_config_reset(dev);
2c7111db
CW		 9654}
9655
9656void intel_modeset_gem_init(struct drm_device *dev)
9657{
1833b134 9658 intel_modeset_init_hw(dev);
02e792fb
DV		 9659
9660 intel_setup_overlay(dev);
24929352 9661
45e2b5f6 9662 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9663}
9664
9665void intel_modeset_cleanup(struct drm_device *dev)
9666{
652c393a
JB		 9667 struct drm_i915_private *dev_priv = dev->dev_private;
9668 struct drm_crtc *crtc;
9669 struct intel_crtc *intel_crtc;
9670
fd0c0642
DV		 9671 /*
9672 * Interrupts and polling as the first thing to avoid creating havoc.
9673 * Too much stuff here (turning of rps, connectors, ...) would
9674 * experience fancy races otherwise.
9675 */
9676 drm_irq_uninstall(dev);
9677 cancel_work_sync(&dev_priv->hotplug_work);
9678 /*
9679 * Due to the hpd irq storm handling the hotplug work can re-arm the
9680 * poll handlers. Hence disable polling after hpd handling is shut down.
9681 */
f87ea761 9682 drm_kms_helper_poll_fini(dev);
fd0c0642 9683
652c393a
JB		 9684 mutex_lock(&dev->struct_mutex);
9685
723bfd70
JB		 9686 intel_unregister_dsm_handler();
9687
652c393a
JB		 9688 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9689 /* Skip inactive CRTCs */
9690 if (!crtc->fb)
9691 continue;
9692
9693 intel_crtc = to_intel_crtc(crtc);
3dec0095 9694 intel_increase_pllclock(crtc);
652c393a
JB		 9695 }
9696
973d04f9 9697 intel_disable_fbc(dev);
e70236a8 9698
8090c6b9 9699 intel_disable_gt_powersave(dev);
0cdab21f 9700
930ebb46
DV		 9701 ironlake_teardown_rc6(dev);
9702
69341a5e
KH		 9703 mutex_unlock(&dev->struct_mutex);
9704
1630fe75
CW		 9705 /* flush any delayed tasks or pending work */
9706 flush_scheduled_work();
9707
dc652f90
JN		 9708 /* destroy backlight, if any, before the connectors */
9709 intel_panel_destroy_backlight(dev);
9710
79e53945 9711 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9712
9713 intel_cleanup_overlay(dev);
79e53945
JB		 9714}
9715
f1c79df3
ZW		 9716/*
9717 * Return which encoder is currently attached for connector.
9718 */
df0e9248 9719struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9720{
df0e9248
CW		 9721 return &intel_attached_encoder(connector)->base;
9722}
f1c79df3 9723
df0e9248
CW		 9724void intel_connector_attach_encoder(struct intel_connector *connector,
9725 struct intel_encoder *encoder)
9726{
9727 connector->encoder = encoder;
9728 drm_mode_connector_attach_encoder(&connector->base,
9729 &encoder->base);
79e53945 9730}
28d52043
DA		 9731
9732/*
9733 * set vga decode state - true == enable VGA decode
9734 */
9735int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9736{
9737 struct drm_i915_private *dev_priv = dev->dev_private;
9738 u16 gmch_ctrl;
9739
9740 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9741 if (state)
9742 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9743 else
9744 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9745 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9746 return 0;
9747}
c4a1d9e4
CW		 9748
9749#ifdef CONFIG_DEBUG_FS
9750#include <linux/seq_file.h>
9751
9752struct intel_display_error_state {
ff57f1b0
PZ		 9753
9754 u32 power_well_driver;
9755
c4a1d9e4
CW		 9756 struct intel_cursor_error_state {
9757 u32 control;
9758 u32 position;
9759 u32 base;
9760 u32 size;
52331309 9761 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9762
9763 struct intel_pipe_error_state {
ff57f1b0 9764 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9765 u32 conf;
9766 u32 source;
9767
9768 u32 htotal;
9769 u32 hblank;
9770 u32 hsync;
9771 u32 vtotal;
9772 u32 vblank;
9773 u32 vsync;
52331309 9774 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9775
9776 struct intel_plane_error_state {
9777 u32 control;
9778 u32 stride;
9779 u32 size;
9780 u32 pos;
9781 u32 addr;
9782 u32 surface;
9783 u32 tile_offset;
52331309 9784 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9785};
9786
9787struct intel_display_error_state *
9788intel_display_capture_error_state(struct drm_device *dev)
9789{
0206e353 9790 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9791 struct intel_display_error_state *error;
702e7a56 9792 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9793 int i;
9794
9795 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9796 if (error == NULL)
9797 return NULL;
9798
ff57f1b0
PZ		 9799 if (HAS_POWER_WELL(dev))
9800 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9801
52331309 9802 for_each_pipe(i) {
702e7a56 9803 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 9804 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 9805
a18c4c3d
PZ		 9806 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9807 error->cursor[i].control = I915_READ(CURCNTR(i));
9808 error->cursor[i].position = I915_READ(CURPOS(i));
9809 error->cursor[i].base = I915_READ(CURBASE(i));
9810 } else {
9811 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9812 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9813 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9814 }
c4a1d9e4
CW		 9815
9816 error->plane[i].control = I915_READ(DSPCNTR(i));
9817 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9818 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9819 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9820 error->plane[i].pos = I915_READ(DSPPOS(i));
9821 }
ca291363
PZ		 9822 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9823 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9824 if (INTEL_INFO(dev)->gen >= 4) {
9825 error->plane[i].surface = I915_READ(DSPSURF(i));
9826 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9827 }
9828
702e7a56 9829 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9830 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9831 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9832 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9833 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9834 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9835 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9836 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9837 }
9838
12d217c7
PZ		 9839 /* In the code above we read the registers without checking if the power
9840 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9841 * prevent the next I915_WRITE from detecting it and printing an error
9842 * message. */
9843 if (HAS_POWER_WELL(dev))
9844 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9845
c4a1d9e4
CW		 9846 return error;
9847}
9848
edc3d884
MK		 9849#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9850
c4a1d9e4 9851void
edc3d884 9852intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 9853 struct drm_device *dev,
9854 struct intel_display_error_state *error)
9855{
9856 int i;
9857
edc3d884 9858 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 9859 if (HAS_POWER_WELL(dev))
edc3d884 9860 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 9861 error->power_well_driver);
52331309 9862 for_each_pipe(i) {
edc3d884
MK		 9863 err_printf(m, "Pipe [%d]:\n", i);
9864 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 9865 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 9866 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9867 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
9868 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9869 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9870 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9871 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9872 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9873 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9874
9875 err_printf(m, "Plane [%d]:\n", i);
9876 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
9877 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9878 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 9879 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
9880 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 9881 }
4b71a570 9882 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 9883 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 9884 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 9885 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
9886 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 9887 }
9888
edc3d884
MK		 9889 err_printf(m, "Cursor [%d]:\n", i);
9890 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9891 err_printf(m, " POS: %08x\n", error->cursor[i].position);
9892 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 9893 }
9894}
9895#endif
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