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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
79e53945 JB |
35 | #include "drmP.h" |
36 | #include "intel_drv.h" | |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
e5510fac | 39 | #include "i915_trace.h" |
ab2c0672 | 40 | #include "drm_dp_helper.h" |
79e53945 | 41 | #include "drm_crtc_helper.h" |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
32f9d658 ZW |
44 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
45 | ||
0206e353 | 46 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
3dec0095 | 47 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 48 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 JB |
49 | |
50 | typedef struct { | |
0206e353 AJ |
51 | /* given values */ |
52 | int n; | |
53 | int m1, m2; | |
54 | int p1, p2; | |
55 | /* derived values */ | |
56 | int dot; | |
57 | int vco; | |
58 | int m; | |
59 | int p; | |
79e53945 JB |
60 | } intel_clock_t; |
61 | ||
62 | typedef struct { | |
0206e353 | 63 | int min, max; |
79e53945 JB |
64 | } intel_range_t; |
65 | ||
66 | typedef struct { | |
0206e353 AJ |
67 | int dot_limit; |
68 | int p2_slow, p2_fast; | |
79e53945 JB |
69 | } intel_p2_t; |
70 | ||
71 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
72 | typedef struct intel_limit intel_limit_t; |
73 | struct intel_limit { | |
0206e353 AJ |
74 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
75 | intel_p2_t p2; | |
76 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, | |
cec2f356 | 77 | int, int, intel_clock_t *, intel_clock_t *); |
d4906093 | 78 | }; |
79e53945 | 79 | |
2377b741 JB |
80 | /* FDI */ |
81 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
82 | ||
d4906093 ML |
83 | static bool |
84 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
85 | int target, int refclk, intel_clock_t *match_clock, |
86 | intel_clock_t *best_clock); | |
d4906093 ML |
87 | static bool |
88 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
89 | int target, int refclk, intel_clock_t *match_clock, |
90 | intel_clock_t *best_clock); | |
79e53945 | 91 | |
a4fc5ed6 KP |
92 | static bool |
93 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
cec2f356 SP |
94 | int target, int refclk, intel_clock_t *match_clock, |
95 | intel_clock_t *best_clock); | |
5eb08b69 | 96 | static bool |
f2b115e6 | 97 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
cec2f356 SP |
98 | int target, int refclk, intel_clock_t *match_clock, |
99 | intel_clock_t *best_clock); | |
a4fc5ed6 | 100 | |
021357ac CW |
101 | static inline u32 /* units of 100MHz */ |
102 | intel_fdi_link_freq(struct drm_device *dev) | |
103 | { | |
8b99e68c CW |
104 | if (IS_GEN5(dev)) { |
105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
106 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
107 | } else | |
108 | return 27; | |
021357ac CW |
109 | } |
110 | ||
e4b36699 | 111 | static const intel_limit_t intel_limits_i8xx_dvo = { |
0206e353 AJ |
112 | .dot = { .min = 25000, .max = 350000 }, |
113 | .vco = { .min = 930000, .max = 1400000 }, | |
114 | .n = { .min = 3, .max = 16 }, | |
115 | .m = { .min = 96, .max = 140 }, | |
116 | .m1 = { .min = 18, .max = 26 }, | |
117 | .m2 = { .min = 6, .max = 16 }, | |
118 | .p = { .min = 4, .max = 128 }, | |
119 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
120 | .p2 = { .dot_limit = 165000, |
121 | .p2_slow = 4, .p2_fast = 2 }, | |
d4906093 | 122 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
123 | }; |
124 | ||
125 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
0206e353 AJ |
126 | .dot = { .min = 25000, .max = 350000 }, |
127 | .vco = { .min = 930000, .max = 1400000 }, | |
128 | .n = { .min = 3, .max = 16 }, | |
129 | .m = { .min = 96, .max = 140 }, | |
130 | .m1 = { .min = 18, .max = 26 }, | |
131 | .m2 = { .min = 6, .max = 16 }, | |
132 | .p = { .min = 4, .max = 128 }, | |
133 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
134 | .p2 = { .dot_limit = 165000, |
135 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 136 | .find_pll = intel_find_best_PLL, |
e4b36699 | 137 | }; |
273e27ca | 138 | |
e4b36699 | 139 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
140 | .dot = { .min = 20000, .max = 400000 }, |
141 | .vco = { .min = 1400000, .max = 2800000 }, | |
142 | .n = { .min = 1, .max = 6 }, | |
143 | .m = { .min = 70, .max = 120 }, | |
144 | .m1 = { .min = 10, .max = 22 }, | |
145 | .m2 = { .min = 5, .max = 9 }, | |
146 | .p = { .min = 5, .max = 80 }, | |
147 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
148 | .p2 = { .dot_limit = 200000, |
149 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 150 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
151 | }; |
152 | ||
153 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
154 | .dot = { .min = 20000, .max = 400000 }, |
155 | .vco = { .min = 1400000, .max = 2800000 }, | |
156 | .n = { .min = 1, .max = 6 }, | |
157 | .m = { .min = 70, .max = 120 }, | |
158 | .m1 = { .min = 10, .max = 22 }, | |
159 | .m2 = { .min = 5, .max = 9 }, | |
160 | .p = { .min = 7, .max = 98 }, | |
161 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
162 | .p2 = { .dot_limit = 112000, |
163 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 164 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
165 | }; |
166 | ||
273e27ca | 167 | |
e4b36699 | 168 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
169 | .dot = { .min = 25000, .max = 270000 }, |
170 | .vco = { .min = 1750000, .max = 3500000}, | |
171 | .n = { .min = 1, .max = 4 }, | |
172 | .m = { .min = 104, .max = 138 }, | |
173 | .m1 = { .min = 17, .max = 23 }, | |
174 | .m2 = { .min = 5, .max = 11 }, | |
175 | .p = { .min = 10, .max = 30 }, | |
176 | .p1 = { .min = 1, .max = 3}, | |
177 | .p2 = { .dot_limit = 270000, | |
178 | .p2_slow = 10, | |
179 | .p2_fast = 10 | |
044c7c41 | 180 | }, |
d4906093 | 181 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
182 | }; |
183 | ||
184 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
185 | .dot = { .min = 22000, .max = 400000 }, |
186 | .vco = { .min = 1750000, .max = 3500000}, | |
187 | .n = { .min = 1, .max = 4 }, | |
188 | .m = { .min = 104, .max = 138 }, | |
189 | .m1 = { .min = 16, .max = 23 }, | |
190 | .m2 = { .min = 5, .max = 11 }, | |
191 | .p = { .min = 5, .max = 80 }, | |
192 | .p1 = { .min = 1, .max = 8}, | |
193 | .p2 = { .dot_limit = 165000, | |
194 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 195 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
196 | }; |
197 | ||
198 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
199 | .dot = { .min = 20000, .max = 115000 }, |
200 | .vco = { .min = 1750000, .max = 3500000 }, | |
201 | .n = { .min = 1, .max = 3 }, | |
202 | .m = { .min = 104, .max = 138 }, | |
203 | .m1 = { .min = 17, .max = 23 }, | |
204 | .m2 = { .min = 5, .max = 11 }, | |
205 | .p = { .min = 28, .max = 112 }, | |
206 | .p1 = { .min = 2, .max = 8 }, | |
207 | .p2 = { .dot_limit = 0, | |
208 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 209 | }, |
d4906093 | 210 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
211 | }; |
212 | ||
213 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
214 | .dot = { .min = 80000, .max = 224000 }, |
215 | .vco = { .min = 1750000, .max = 3500000 }, | |
216 | .n = { .min = 1, .max = 3 }, | |
217 | .m = { .min = 104, .max = 138 }, | |
218 | .m1 = { .min = 17, .max = 23 }, | |
219 | .m2 = { .min = 5, .max = 11 }, | |
220 | .p = { .min = 14, .max = 42 }, | |
221 | .p1 = { .min = 2, .max = 6 }, | |
222 | .p2 = { .dot_limit = 0, | |
223 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 224 | }, |
d4906093 | 225 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
226 | }; |
227 | ||
228 | static const intel_limit_t intel_limits_g4x_display_port = { | |
0206e353 AJ |
229 | .dot = { .min = 161670, .max = 227000 }, |
230 | .vco = { .min = 1750000, .max = 3500000}, | |
231 | .n = { .min = 1, .max = 2 }, | |
232 | .m = { .min = 97, .max = 108 }, | |
233 | .m1 = { .min = 0x10, .max = 0x12 }, | |
234 | .m2 = { .min = 0x05, .max = 0x06 }, | |
235 | .p = { .min = 10, .max = 20 }, | |
236 | .p1 = { .min = 1, .max = 2}, | |
237 | .p2 = { .dot_limit = 0, | |
273e27ca | 238 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 239 | .find_pll = intel_find_pll_g4x_dp, |
e4b36699 KP |
240 | }; |
241 | ||
f2b115e6 | 242 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
243 | .dot = { .min = 20000, .max = 400000}, |
244 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 245 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
246 | .n = { .min = 3, .max = 6 }, |
247 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 248 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
249 | .m1 = { .min = 0, .max = 0 }, |
250 | .m2 = { .min = 0, .max = 254 }, | |
251 | .p = { .min = 5, .max = 80 }, | |
252 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
253 | .p2 = { .dot_limit = 200000, |
254 | .p2_slow = 10, .p2_fast = 5 }, | |
6115707b | 255 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
256 | }; |
257 | ||
f2b115e6 | 258 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
259 | .dot = { .min = 20000, .max = 400000 }, |
260 | .vco = { .min = 1700000, .max = 3500000 }, | |
261 | .n = { .min = 3, .max = 6 }, | |
262 | .m = { .min = 2, .max = 256 }, | |
263 | .m1 = { .min = 0, .max = 0 }, | |
264 | .m2 = { .min = 0, .max = 254 }, | |
265 | .p = { .min = 7, .max = 112 }, | |
266 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
267 | .p2 = { .dot_limit = 112000, |
268 | .p2_slow = 14, .p2_fast = 14 }, | |
6115707b | 269 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
270 | }; |
271 | ||
273e27ca EA |
272 | /* Ironlake / Sandybridge |
273 | * | |
274 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
275 | * the range value for them is (actual_value - 2). | |
276 | */ | |
b91ad0ec | 277 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
278 | .dot = { .min = 25000, .max = 350000 }, |
279 | .vco = { .min = 1760000, .max = 3510000 }, | |
280 | .n = { .min = 1, .max = 5 }, | |
281 | .m = { .min = 79, .max = 127 }, | |
282 | .m1 = { .min = 12, .max = 22 }, | |
283 | .m2 = { .min = 5, .max = 9 }, | |
284 | .p = { .min = 5, .max = 80 }, | |
285 | .p1 = { .min = 1, .max = 8 }, | |
286 | .p2 = { .dot_limit = 225000, | |
287 | .p2_slow = 10, .p2_fast = 5 }, | |
4547668a | 288 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
289 | }; |
290 | ||
b91ad0ec | 291 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
292 | .dot = { .min = 25000, .max = 350000 }, |
293 | .vco = { .min = 1760000, .max = 3510000 }, | |
294 | .n = { .min = 1, .max = 3 }, | |
295 | .m = { .min = 79, .max = 118 }, | |
296 | .m1 = { .min = 12, .max = 22 }, | |
297 | .m2 = { .min = 5, .max = 9 }, | |
298 | .p = { .min = 28, .max = 112 }, | |
299 | .p1 = { .min = 2, .max = 8 }, | |
300 | .p2 = { .dot_limit = 225000, | |
301 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
302 | .find_pll = intel_g4x_find_best_PLL, |
303 | }; | |
304 | ||
305 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
306 | .dot = { .min = 25000, .max = 350000 }, |
307 | .vco = { .min = 1760000, .max = 3510000 }, | |
308 | .n = { .min = 1, .max = 3 }, | |
309 | .m = { .min = 79, .max = 127 }, | |
310 | .m1 = { .min = 12, .max = 22 }, | |
311 | .m2 = { .min = 5, .max = 9 }, | |
312 | .p = { .min = 14, .max = 56 }, | |
313 | .p1 = { .min = 2, .max = 8 }, | |
314 | .p2 = { .dot_limit = 225000, | |
315 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
316 | .find_pll = intel_g4x_find_best_PLL, |
317 | }; | |
318 | ||
273e27ca | 319 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 320 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
321 | .dot = { .min = 25000, .max = 350000 }, |
322 | .vco = { .min = 1760000, .max = 3510000 }, | |
323 | .n = { .min = 1, .max = 2 }, | |
324 | .m = { .min = 79, .max = 126 }, | |
325 | .m1 = { .min = 12, .max = 22 }, | |
326 | .m2 = { .min = 5, .max = 9 }, | |
327 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 328 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
329 | .p2 = { .dot_limit = 225000, |
330 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
331 | .find_pll = intel_g4x_find_best_PLL, |
332 | }; | |
333 | ||
334 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
335 | .dot = { .min = 25000, .max = 350000 }, |
336 | .vco = { .min = 1760000, .max = 3510000 }, | |
337 | .n = { .min = 1, .max = 3 }, | |
338 | .m = { .min = 79, .max = 126 }, | |
339 | .m1 = { .min = 12, .max = 22 }, | |
340 | .m2 = { .min = 5, .max = 9 }, | |
341 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 342 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
343 | .p2 = { .dot_limit = 225000, |
344 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
345 | .find_pll = intel_g4x_find_best_PLL, |
346 | }; | |
347 | ||
348 | static const intel_limit_t intel_limits_ironlake_display_port = { | |
0206e353 AJ |
349 | .dot = { .min = 25000, .max = 350000 }, |
350 | .vco = { .min = 1760000, .max = 3510000}, | |
351 | .n = { .min = 1, .max = 2 }, | |
352 | .m = { .min = 81, .max = 90 }, | |
353 | .m1 = { .min = 12, .max = 22 }, | |
354 | .m2 = { .min = 5, .max = 9 }, | |
355 | .p = { .min = 10, .max = 20 }, | |
356 | .p1 = { .min = 1, .max = 2}, | |
357 | .p2 = { .dot_limit = 0, | |
273e27ca | 358 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 359 | .find_pll = intel_find_pll_ironlake_dp, |
79e53945 JB |
360 | }; |
361 | ||
57f350b6 JB |
362 | u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) |
363 | { | |
364 | unsigned long flags; | |
365 | u32 val = 0; | |
366 | ||
367 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); | |
368 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { | |
369 | DRM_ERROR("DPIO idle wait timed out\n"); | |
370 | goto out_unlock; | |
371 | } | |
372 | ||
373 | I915_WRITE(DPIO_REG, reg); | |
374 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID | | |
375 | DPIO_BYTE); | |
376 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { | |
377 | DRM_ERROR("DPIO read wait timed out\n"); | |
378 | goto out_unlock; | |
379 | } | |
380 | val = I915_READ(DPIO_DATA); | |
381 | ||
382 | out_unlock: | |
383 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); | |
384 | return val; | |
385 | } | |
386 | ||
387 | static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, | |
388 | u32 val) | |
389 | { | |
390 | unsigned long flags; | |
391 | ||
392 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); | |
393 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { | |
394 | DRM_ERROR("DPIO idle wait timed out\n"); | |
395 | goto out_unlock; | |
396 | } | |
397 | ||
398 | I915_WRITE(DPIO_DATA, val); | |
399 | I915_WRITE(DPIO_REG, reg); | |
400 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID | | |
401 | DPIO_BYTE); | |
402 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) | |
403 | DRM_ERROR("DPIO write wait timed out\n"); | |
404 | ||
405 | out_unlock: | |
406 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); | |
407 | } | |
408 | ||
409 | static void vlv_init_dpio(struct drm_device *dev) | |
410 | { | |
411 | struct drm_i915_private *dev_priv = dev->dev_private; | |
412 | ||
413 | /* Reset the DPIO config */ | |
414 | I915_WRITE(DPIO_CTL, 0); | |
415 | POSTING_READ(DPIO_CTL); | |
416 | I915_WRITE(DPIO_CTL, 1); | |
417 | POSTING_READ(DPIO_CTL); | |
418 | } | |
419 | ||
618563e3 DV |
420 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
421 | { | |
422 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); | |
423 | return 1; | |
424 | } | |
425 | ||
426 | static const struct dmi_system_id intel_dual_link_lvds[] = { | |
427 | { | |
428 | .callback = intel_dual_link_lvds_callback, | |
429 | .ident = "Apple MacBook Pro (Core i5/i7 Series)", | |
430 | .matches = { | |
431 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
432 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), | |
433 | }, | |
434 | }, | |
435 | { } /* terminating entry */ | |
436 | }; | |
437 | ||
b0354385 TI |
438 | static bool is_dual_link_lvds(struct drm_i915_private *dev_priv, |
439 | unsigned int reg) | |
440 | { | |
441 | unsigned int val; | |
442 | ||
121d527a TI |
443 | /* use the module option value if specified */ |
444 | if (i915_lvds_channel_mode > 0) | |
445 | return i915_lvds_channel_mode == 2; | |
446 | ||
618563e3 DV |
447 | if (dmi_check_system(intel_dual_link_lvds)) |
448 | return true; | |
449 | ||
b0354385 TI |
450 | if (dev_priv->lvds_val) |
451 | val = dev_priv->lvds_val; | |
452 | else { | |
453 | /* BIOS should set the proper LVDS register value at boot, but | |
454 | * in reality, it doesn't set the value when the lid is closed; | |
455 | * we need to check "the value to be set" in VBT when LVDS | |
456 | * register is uninitialized. | |
457 | */ | |
458 | val = I915_READ(reg); | |
459 | if (!(val & ~LVDS_DETECTED)) | |
460 | val = dev_priv->bios_lvds_val; | |
461 | dev_priv->lvds_val = val; | |
462 | } | |
463 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; | |
464 | } | |
465 | ||
1b894b59 CW |
466 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
467 | int refclk) | |
2c07245f | 468 | { |
b91ad0ec ZW |
469 | struct drm_device *dev = crtc->dev; |
470 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2c07245f | 471 | const intel_limit_t *limit; |
b91ad0ec ZW |
472 | |
473 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
b0354385 | 474 | if (is_dual_link_lvds(dev_priv, PCH_LVDS)) { |
b91ad0ec | 475 | /* LVDS dual channel */ |
1b894b59 | 476 | if (refclk == 100000) |
b91ad0ec ZW |
477 | limit = &intel_limits_ironlake_dual_lvds_100m; |
478 | else | |
479 | limit = &intel_limits_ironlake_dual_lvds; | |
480 | } else { | |
1b894b59 | 481 | if (refclk == 100000) |
b91ad0ec ZW |
482 | limit = &intel_limits_ironlake_single_lvds_100m; |
483 | else | |
484 | limit = &intel_limits_ironlake_single_lvds; | |
485 | } | |
486 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
4547668a ZY |
487 | HAS_eDP) |
488 | limit = &intel_limits_ironlake_display_port; | |
2c07245f | 489 | else |
b91ad0ec | 490 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
491 | |
492 | return limit; | |
493 | } | |
494 | ||
044c7c41 ML |
495 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
496 | { | |
497 | struct drm_device *dev = crtc->dev; | |
498 | struct drm_i915_private *dev_priv = dev->dev_private; | |
499 | const intel_limit_t *limit; | |
500 | ||
501 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
b0354385 | 502 | if (is_dual_link_lvds(dev_priv, LVDS)) |
044c7c41 | 503 | /* LVDS with dual channel */ |
e4b36699 | 504 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
505 | else |
506 | /* LVDS with dual channel */ | |
e4b36699 | 507 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
508 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
509 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 510 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 511 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 512 | limit = &intel_limits_g4x_sdvo; |
0206e353 | 513 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 514 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 515 | } else /* The option is for other outputs */ |
e4b36699 | 516 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
517 | |
518 | return limit; | |
519 | } | |
520 | ||
1b894b59 | 521 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
522 | { |
523 | struct drm_device *dev = crtc->dev; | |
524 | const intel_limit_t *limit; | |
525 | ||
bad720ff | 526 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 527 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 528 | else if (IS_G4X(dev)) { |
044c7c41 | 529 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 530 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 531 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 532 | limit = &intel_limits_pineview_lvds; |
2177832f | 533 | else |
f2b115e6 | 534 | limit = &intel_limits_pineview_sdvo; |
a6c45cf0 CW |
535 | } else if (!IS_GEN2(dev)) { |
536 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
537 | limit = &intel_limits_i9xx_lvds; | |
538 | else | |
539 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
540 | } else { |
541 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 542 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 543 | else |
e4b36699 | 544 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
545 | } |
546 | return limit; | |
547 | } | |
548 | ||
f2b115e6 AJ |
549 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
550 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 551 | { |
2177832f SL |
552 | clock->m = clock->m2 + 2; |
553 | clock->p = clock->p1 * clock->p2; | |
554 | clock->vco = refclk * clock->m / clock->n; | |
555 | clock->dot = clock->vco / clock->p; | |
556 | } | |
557 | ||
558 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
559 | { | |
f2b115e6 AJ |
560 | if (IS_PINEVIEW(dev)) { |
561 | pineview_clock(refclk, clock); | |
2177832f SL |
562 | return; |
563 | } | |
79e53945 JB |
564 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
565 | clock->p = clock->p1 * clock->p2; | |
566 | clock->vco = refclk * clock->m / (clock->n + 2); | |
567 | clock->dot = clock->vco / clock->p; | |
568 | } | |
569 | ||
79e53945 JB |
570 | /** |
571 | * Returns whether any output on the specified pipe is of the specified type | |
572 | */ | |
4ef69c7a | 573 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 574 | { |
4ef69c7a CW |
575 | struct drm_device *dev = crtc->dev; |
576 | struct drm_mode_config *mode_config = &dev->mode_config; | |
577 | struct intel_encoder *encoder; | |
578 | ||
579 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
580 | if (encoder->base.crtc == crtc && encoder->type == type) | |
581 | return true; | |
582 | ||
583 | return false; | |
79e53945 JB |
584 | } |
585 | ||
7c04d1d9 | 586 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
587 | /** |
588 | * Returns whether the given set of divisors are valid for a given refclk with | |
589 | * the given connectors. | |
590 | */ | |
591 | ||
1b894b59 CW |
592 | static bool intel_PLL_is_valid(struct drm_device *dev, |
593 | const intel_limit_t *limit, | |
594 | const intel_clock_t *clock) | |
79e53945 | 595 | { |
79e53945 | 596 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 597 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 598 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
0206e353 | 599 | INTELPllInvalid("p out of range\n"); |
79e53945 | 600 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 601 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 602 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 603 | INTELPllInvalid("m1 out of range\n"); |
f2b115e6 | 604 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
0206e353 | 605 | INTELPllInvalid("m1 <= m2\n"); |
79e53945 | 606 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
0206e353 | 607 | INTELPllInvalid("m out of range\n"); |
79e53945 | 608 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
0206e353 | 609 | INTELPllInvalid("n out of range\n"); |
79e53945 | 610 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 611 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
612 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
613 | * connector, etc., rather than just a single range. | |
614 | */ | |
615 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 616 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
617 | |
618 | return true; | |
619 | } | |
620 | ||
d4906093 ML |
621 | static bool |
622 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
623 | int target, int refclk, intel_clock_t *match_clock, |
624 | intel_clock_t *best_clock) | |
d4906093 | 625 | |
79e53945 JB |
626 | { |
627 | struct drm_device *dev = crtc->dev; | |
628 | struct drm_i915_private *dev_priv = dev->dev_private; | |
629 | intel_clock_t clock; | |
79e53945 JB |
630 | int err = target; |
631 | ||
bc5e5718 | 632 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
832cc28d | 633 | (I915_READ(LVDS)) != 0) { |
79e53945 JB |
634 | /* |
635 | * For LVDS, if the panel is on, just rely on its current | |
636 | * settings for dual-channel. We haven't figured out how to | |
637 | * reliably set up different single/dual channel state, if we | |
638 | * even can. | |
639 | */ | |
b0354385 | 640 | if (is_dual_link_lvds(dev_priv, LVDS)) |
79e53945 JB |
641 | clock.p2 = limit->p2.p2_fast; |
642 | else | |
643 | clock.p2 = limit->p2.p2_slow; | |
644 | } else { | |
645 | if (target < limit->p2.dot_limit) | |
646 | clock.p2 = limit->p2.p2_slow; | |
647 | else | |
648 | clock.p2 = limit->p2.p2_fast; | |
649 | } | |
650 | ||
0206e353 | 651 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 652 | |
42158660 ZY |
653 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
654 | clock.m1++) { | |
655 | for (clock.m2 = limit->m2.min; | |
656 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
657 | /* m1 is always 0 in Pineview */ |
658 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
659 | break; |
660 | for (clock.n = limit->n.min; | |
661 | clock.n <= limit->n.max; clock.n++) { | |
662 | for (clock.p1 = limit->p1.min; | |
663 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
664 | int this_err; |
665 | ||
2177832f | 666 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
667 | if (!intel_PLL_is_valid(dev, limit, |
668 | &clock)) | |
79e53945 | 669 | continue; |
cec2f356 SP |
670 | if (match_clock && |
671 | clock.p != match_clock->p) | |
672 | continue; | |
79e53945 JB |
673 | |
674 | this_err = abs(clock.dot - target); | |
675 | if (this_err < err) { | |
676 | *best_clock = clock; | |
677 | err = this_err; | |
678 | } | |
679 | } | |
680 | } | |
681 | } | |
682 | } | |
683 | ||
684 | return (err != target); | |
685 | } | |
686 | ||
d4906093 ML |
687 | static bool |
688 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
689 | int target, int refclk, intel_clock_t *match_clock, |
690 | intel_clock_t *best_clock) | |
d4906093 ML |
691 | { |
692 | struct drm_device *dev = crtc->dev; | |
693 | struct drm_i915_private *dev_priv = dev->dev_private; | |
694 | intel_clock_t clock; | |
695 | int max_n; | |
696 | bool found; | |
6ba770dc AJ |
697 | /* approximately equals target * 0.00585 */ |
698 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
699 | found = false; |
700 | ||
701 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
702 | int lvds_reg; |
703 | ||
c619eed4 | 704 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
705 | lvds_reg = PCH_LVDS; |
706 | else | |
707 | lvds_reg = LVDS; | |
708 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == | |
d4906093 ML |
709 | LVDS_CLKB_POWER_UP) |
710 | clock.p2 = limit->p2.p2_fast; | |
711 | else | |
712 | clock.p2 = limit->p2.p2_slow; | |
713 | } else { | |
714 | if (target < limit->p2.dot_limit) | |
715 | clock.p2 = limit->p2.p2_slow; | |
716 | else | |
717 | clock.p2 = limit->p2.p2_fast; | |
718 | } | |
719 | ||
720 | memset(best_clock, 0, sizeof(*best_clock)); | |
721 | max_n = limit->n.max; | |
f77f13e2 | 722 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 723 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 724 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
725 | for (clock.m1 = limit->m1.max; |
726 | clock.m1 >= limit->m1.min; clock.m1--) { | |
727 | for (clock.m2 = limit->m2.max; | |
728 | clock.m2 >= limit->m2.min; clock.m2--) { | |
729 | for (clock.p1 = limit->p1.max; | |
730 | clock.p1 >= limit->p1.min; clock.p1--) { | |
731 | int this_err; | |
732 | ||
2177832f | 733 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
734 | if (!intel_PLL_is_valid(dev, limit, |
735 | &clock)) | |
d4906093 | 736 | continue; |
cec2f356 SP |
737 | if (match_clock && |
738 | clock.p != match_clock->p) | |
739 | continue; | |
1b894b59 CW |
740 | |
741 | this_err = abs(clock.dot - target); | |
d4906093 ML |
742 | if (this_err < err_most) { |
743 | *best_clock = clock; | |
744 | err_most = this_err; | |
745 | max_n = clock.n; | |
746 | found = true; | |
747 | } | |
748 | } | |
749 | } | |
750 | } | |
751 | } | |
2c07245f ZW |
752 | return found; |
753 | } | |
754 | ||
5eb08b69 | 755 | static bool |
f2b115e6 | 756 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
757 | int target, int refclk, intel_clock_t *match_clock, |
758 | intel_clock_t *best_clock) | |
5eb08b69 ZW |
759 | { |
760 | struct drm_device *dev = crtc->dev; | |
761 | intel_clock_t clock; | |
4547668a | 762 | |
5eb08b69 ZW |
763 | if (target < 200000) { |
764 | clock.n = 1; | |
765 | clock.p1 = 2; | |
766 | clock.p2 = 10; | |
767 | clock.m1 = 12; | |
768 | clock.m2 = 9; | |
769 | } else { | |
770 | clock.n = 2; | |
771 | clock.p1 = 1; | |
772 | clock.p2 = 10; | |
773 | clock.m1 = 14; | |
774 | clock.m2 = 8; | |
775 | } | |
776 | intel_clock(dev, refclk, &clock); | |
777 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
778 | return true; | |
779 | } | |
780 | ||
a4fc5ed6 KP |
781 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
782 | static bool | |
783 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
784 | int target, int refclk, intel_clock_t *match_clock, |
785 | intel_clock_t *best_clock) | |
a4fc5ed6 | 786 | { |
5eddb70b CW |
787 | intel_clock_t clock; |
788 | if (target < 200000) { | |
789 | clock.p1 = 2; | |
790 | clock.p2 = 10; | |
791 | clock.n = 2; | |
792 | clock.m1 = 23; | |
793 | clock.m2 = 8; | |
794 | } else { | |
795 | clock.p1 = 1; | |
796 | clock.p2 = 10; | |
797 | clock.n = 1; | |
798 | clock.m1 = 14; | |
799 | clock.m2 = 2; | |
800 | } | |
801 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); | |
802 | clock.p = (clock.p1 * clock.p2); | |
803 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
804 | clock.vco = 0; | |
805 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
806 | return true; | |
a4fc5ed6 KP |
807 | } |
808 | ||
9d0498a2 JB |
809 | /** |
810 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
811 | * @dev: drm device | |
812 | * @pipe: pipe to wait for | |
813 | * | |
814 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
815 | * mode setting code. | |
816 | */ | |
817 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 818 | { |
9d0498a2 | 819 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 820 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 821 | |
300387c0 CW |
822 | /* Clear existing vblank status. Note this will clear any other |
823 | * sticky status fields as well. | |
824 | * | |
825 | * This races with i915_driver_irq_handler() with the result | |
826 | * that either function could miss a vblank event. Here it is not | |
827 | * fatal, as we will either wait upon the next vblank interrupt or | |
828 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
829 | * called during modeset at which time the GPU should be idle and | |
830 | * should *not* be performing page flips and thus not waiting on | |
831 | * vblanks... | |
832 | * Currently, the result of us stealing a vblank from the irq | |
833 | * handler is that a single frame will be skipped during swapbuffers. | |
834 | */ | |
835 | I915_WRITE(pipestat_reg, | |
836 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
837 | ||
9d0498a2 | 838 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
839 | if (wait_for(I915_READ(pipestat_reg) & |
840 | PIPE_VBLANK_INTERRUPT_STATUS, | |
841 | 50)) | |
9d0498a2 JB |
842 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
843 | } | |
844 | ||
ab7ad7f6 KP |
845 | /* |
846 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
847 | * @dev: drm device |
848 | * @pipe: pipe to wait for | |
849 | * | |
850 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
851 | * spinning on the vblank interrupt status bit, since we won't actually | |
852 | * see an interrupt when the pipe is disabled. | |
853 | * | |
ab7ad7f6 KP |
854 | * On Gen4 and above: |
855 | * wait for the pipe register state bit to turn off | |
856 | * | |
857 | * Otherwise: | |
858 | * wait for the display line value to settle (it usually | |
859 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 860 | * |
9d0498a2 | 861 | */ |
58e10eb9 | 862 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
863 | { |
864 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ab7ad7f6 KP |
865 | |
866 | if (INTEL_INFO(dev)->gen >= 4) { | |
58e10eb9 | 867 | int reg = PIPECONF(pipe); |
ab7ad7f6 KP |
868 | |
869 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
870 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
871 | 100)) | |
ab7ad7f6 KP |
872 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); |
873 | } else { | |
874 | u32 last_line; | |
58e10eb9 | 875 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
876 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
877 | ||
878 | /* Wait for the display line to settle */ | |
879 | do { | |
58e10eb9 | 880 | last_line = I915_READ(reg) & DSL_LINEMASK; |
ab7ad7f6 | 881 | mdelay(5); |
58e10eb9 | 882 | } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) && |
ab7ad7f6 KP |
883 | time_after(timeout, jiffies)); |
884 | if (time_after(jiffies, timeout)) | |
885 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); | |
886 | } | |
79e53945 JB |
887 | } |
888 | ||
b24e7179 JB |
889 | static const char *state_string(bool enabled) |
890 | { | |
891 | return enabled ? "on" : "off"; | |
892 | } | |
893 | ||
894 | /* Only for pre-ILK configs */ | |
895 | static void assert_pll(struct drm_i915_private *dev_priv, | |
896 | enum pipe pipe, bool state) | |
897 | { | |
898 | int reg; | |
899 | u32 val; | |
900 | bool cur_state; | |
901 | ||
902 | reg = DPLL(pipe); | |
903 | val = I915_READ(reg); | |
904 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
905 | WARN(cur_state != state, | |
906 | "PLL state assertion failure (expected %s, current %s)\n", | |
907 | state_string(state), state_string(cur_state)); | |
908 | } | |
909 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
910 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
911 | ||
040484af JB |
912 | /* For ILK+ */ |
913 | static void assert_pch_pll(struct drm_i915_private *dev_priv, | |
914 | enum pipe pipe, bool state) | |
915 | { | |
916 | int reg; | |
917 | u32 val; | |
918 | bool cur_state; | |
919 | ||
d3ccbe86 JB |
920 | if (HAS_PCH_CPT(dev_priv->dev)) { |
921 | u32 pch_dpll; | |
922 | ||
923 | pch_dpll = I915_READ(PCH_DPLL_SEL); | |
924 | ||
925 | /* Make sure the selected PLL is enabled to the transcoder */ | |
926 | WARN(!((pch_dpll >> (4 * pipe)) & 8), | |
927 | "transcoder %d PLL not enabled\n", pipe); | |
928 | ||
929 | /* Convert the transcoder pipe number to a pll pipe number */ | |
930 | pipe = (pch_dpll >> (4 * pipe)) & 1; | |
931 | } | |
932 | ||
040484af JB |
933 | reg = PCH_DPLL(pipe); |
934 | val = I915_READ(reg); | |
935 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
936 | WARN(cur_state != state, | |
937 | "PCH PLL state assertion failure (expected %s, current %s)\n", | |
938 | state_string(state), state_string(cur_state)); | |
939 | } | |
940 | #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true) | |
941 | #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false) | |
942 | ||
943 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
944 | enum pipe pipe, bool state) | |
945 | { | |
946 | int reg; | |
947 | u32 val; | |
948 | bool cur_state; | |
949 | ||
950 | reg = FDI_TX_CTL(pipe); | |
951 | val = I915_READ(reg); | |
952 | cur_state = !!(val & FDI_TX_ENABLE); | |
953 | WARN(cur_state != state, | |
954 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
955 | state_string(state), state_string(cur_state)); | |
956 | } | |
957 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
958 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
959 | ||
960 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
961 | enum pipe pipe, bool state) | |
962 | { | |
963 | int reg; | |
964 | u32 val; | |
965 | bool cur_state; | |
966 | ||
967 | reg = FDI_RX_CTL(pipe); | |
968 | val = I915_READ(reg); | |
969 | cur_state = !!(val & FDI_RX_ENABLE); | |
970 | WARN(cur_state != state, | |
971 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
972 | state_string(state), state_string(cur_state)); | |
973 | } | |
974 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
975 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
976 | ||
977 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
978 | enum pipe pipe) | |
979 | { | |
980 | int reg; | |
981 | u32 val; | |
982 | ||
983 | /* ILK FDI PLL is always enabled */ | |
984 | if (dev_priv->info->gen == 5) | |
985 | return; | |
986 | ||
987 | reg = FDI_TX_CTL(pipe); | |
988 | val = I915_READ(reg); | |
989 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
990 | } | |
991 | ||
992 | static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, | |
993 | enum pipe pipe) | |
994 | { | |
995 | int reg; | |
996 | u32 val; | |
997 | ||
998 | reg = FDI_RX_CTL(pipe); | |
999 | val = I915_READ(reg); | |
1000 | WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); | |
1001 | } | |
1002 | ||
ea0760cf JB |
1003 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1004 | enum pipe pipe) | |
1005 | { | |
1006 | int pp_reg, lvds_reg; | |
1007 | u32 val; | |
1008 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1009 | bool locked = true; |
ea0760cf JB |
1010 | |
1011 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1012 | pp_reg = PCH_PP_CONTROL; | |
1013 | lvds_reg = PCH_LVDS; | |
1014 | } else { | |
1015 | pp_reg = PP_CONTROL; | |
1016 | lvds_reg = LVDS; | |
1017 | } | |
1018 | ||
1019 | val = I915_READ(pp_reg); | |
1020 | if (!(val & PANEL_POWER_ON) || | |
1021 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1022 | locked = false; | |
1023 | ||
1024 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1025 | panel_pipe = PIPE_B; | |
1026 | ||
1027 | WARN(panel_pipe == pipe && locked, | |
1028 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1029 | pipe_name(pipe)); |
ea0760cf JB |
1030 | } |
1031 | ||
b840d907 JB |
1032 | void assert_pipe(struct drm_i915_private *dev_priv, |
1033 | enum pipe pipe, bool state) | |
b24e7179 JB |
1034 | { |
1035 | int reg; | |
1036 | u32 val; | |
63d7bbe9 | 1037 | bool cur_state; |
b24e7179 | 1038 | |
8e636784 DV |
1039 | /* if we need the pipe A quirk it must be always on */ |
1040 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1041 | state = true; | |
1042 | ||
b24e7179 JB |
1043 | reg = PIPECONF(pipe); |
1044 | val = I915_READ(reg); | |
63d7bbe9 JB |
1045 | cur_state = !!(val & PIPECONF_ENABLE); |
1046 | WARN(cur_state != state, | |
1047 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1048 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1049 | } |
1050 | ||
931872fc CW |
1051 | static void assert_plane(struct drm_i915_private *dev_priv, |
1052 | enum plane plane, bool state) | |
b24e7179 JB |
1053 | { |
1054 | int reg; | |
1055 | u32 val; | |
931872fc | 1056 | bool cur_state; |
b24e7179 JB |
1057 | |
1058 | reg = DSPCNTR(plane); | |
1059 | val = I915_READ(reg); | |
931872fc CW |
1060 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1061 | WARN(cur_state != state, | |
1062 | "plane %c assertion failure (expected %s, current %s)\n", | |
1063 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1064 | } |
1065 | ||
931872fc CW |
1066 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1067 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1068 | ||
b24e7179 JB |
1069 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1070 | enum pipe pipe) | |
1071 | { | |
1072 | int reg, i; | |
1073 | u32 val; | |
1074 | int cur_pipe; | |
1075 | ||
19ec1358 | 1076 | /* Planes are fixed to pipes on ILK+ */ |
28c05794 AJ |
1077 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
1078 | reg = DSPCNTR(pipe); | |
1079 | val = I915_READ(reg); | |
1080 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1081 | "plane %c assertion failure, should be disabled but not\n", | |
1082 | plane_name(pipe)); | |
19ec1358 | 1083 | return; |
28c05794 | 1084 | } |
19ec1358 | 1085 | |
b24e7179 JB |
1086 | /* Need to check both planes against the pipe */ |
1087 | for (i = 0; i < 2; i++) { | |
1088 | reg = DSPCNTR(i); | |
1089 | val = I915_READ(reg); | |
1090 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1091 | DISPPLANE_SEL_PIPE_SHIFT; | |
1092 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1093 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1094 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1095 | } |
1096 | } | |
1097 | ||
92f2584a JB |
1098 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1099 | { | |
1100 | u32 val; | |
1101 | bool enabled; | |
1102 | ||
1103 | val = I915_READ(PCH_DREF_CONTROL); | |
1104 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1105 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1106 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1107 | } | |
1108 | ||
1109 | static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, | |
1110 | enum pipe pipe) | |
1111 | { | |
1112 | int reg; | |
1113 | u32 val; | |
1114 | bool enabled; | |
1115 | ||
1116 | reg = TRANSCONF(pipe); | |
1117 | val = I915_READ(reg); | |
1118 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1119 | WARN(enabled, |
1120 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1121 | pipe_name(pipe)); | |
92f2584a JB |
1122 | } |
1123 | ||
4e634389 KP |
1124 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1125 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1126 | { |
1127 | if ((val & DP_PORT_EN) == 0) | |
1128 | return false; | |
1129 | ||
1130 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1131 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1132 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1133 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1134 | return false; | |
1135 | } else { | |
1136 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1137 | return false; | |
1138 | } | |
1139 | return true; | |
1140 | } | |
1141 | ||
1519b995 KP |
1142 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1143 | enum pipe pipe, u32 val) | |
1144 | { | |
1145 | if ((val & PORT_ENABLE) == 0) | |
1146 | return false; | |
1147 | ||
1148 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1149 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1150 | return false; | |
1151 | } else { | |
1152 | if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) | |
1153 | return false; | |
1154 | } | |
1155 | return true; | |
1156 | } | |
1157 | ||
1158 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1159 | enum pipe pipe, u32 val) | |
1160 | { | |
1161 | if ((val & LVDS_PORT_EN) == 0) | |
1162 | return false; | |
1163 | ||
1164 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1165 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1166 | return false; | |
1167 | } else { | |
1168 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1169 | return false; | |
1170 | } | |
1171 | return true; | |
1172 | } | |
1173 | ||
1174 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1175 | enum pipe pipe, u32 val) | |
1176 | { | |
1177 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1178 | return false; | |
1179 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1180 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1181 | return false; | |
1182 | } else { | |
1183 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1184 | return false; | |
1185 | } | |
1186 | return true; | |
1187 | } | |
1188 | ||
291906f1 | 1189 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1190 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1191 | { |
47a05eca | 1192 | u32 val = I915_READ(reg); |
4e634389 | 1193 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1194 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1195 | reg, pipe_name(pipe)); |
291906f1 JB |
1196 | } |
1197 | ||
1198 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1199 | enum pipe pipe, int reg) | |
1200 | { | |
47a05eca | 1201 | u32 val = I915_READ(reg); |
1519b995 | 1202 | WARN(hdmi_pipe_enabled(dev_priv, val, pipe), |
23c99e77 | 1203 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1204 | reg, pipe_name(pipe)); |
291906f1 JB |
1205 | } |
1206 | ||
1207 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1208 | enum pipe pipe) | |
1209 | { | |
1210 | int reg; | |
1211 | u32 val; | |
291906f1 | 1212 | |
f0575e92 KP |
1213 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1214 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1215 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1216 | |
1217 | reg = PCH_ADPA; | |
1218 | val = I915_READ(reg); | |
1519b995 | 1219 | WARN(adpa_pipe_enabled(dev_priv, val, pipe), |
291906f1 | 1220 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1221 | pipe_name(pipe)); |
291906f1 JB |
1222 | |
1223 | reg = PCH_LVDS; | |
1224 | val = I915_READ(reg); | |
1519b995 | 1225 | WARN(lvds_pipe_enabled(dev_priv, val, pipe), |
291906f1 | 1226 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1227 | pipe_name(pipe)); |
291906f1 JB |
1228 | |
1229 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); | |
1230 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); | |
1231 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); | |
1232 | } | |
1233 | ||
63d7bbe9 JB |
1234 | /** |
1235 | * intel_enable_pll - enable a PLL | |
1236 | * @dev_priv: i915 private structure | |
1237 | * @pipe: pipe PLL to enable | |
1238 | * | |
1239 | * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to | |
1240 | * make sure the PLL reg is writable first though, since the panel write | |
1241 | * protect mechanism may be enabled. | |
1242 | * | |
1243 | * Note! This is for pre-ILK only. | |
1244 | */ | |
1245 | static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1246 | { | |
1247 | int reg; | |
1248 | u32 val; | |
1249 | ||
1250 | /* No really, not for ILK+ */ | |
1251 | BUG_ON(dev_priv->info->gen >= 5); | |
1252 | ||
1253 | /* PLL is protected by panel, make sure we can write it */ | |
1254 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
1255 | assert_panel_unlocked(dev_priv, pipe); | |
1256 | ||
1257 | reg = DPLL(pipe); | |
1258 | val = I915_READ(reg); | |
1259 | val |= DPLL_VCO_ENABLE; | |
1260 | ||
1261 | /* We do this three times for luck */ | |
1262 | I915_WRITE(reg, val); | |
1263 | POSTING_READ(reg); | |
1264 | udelay(150); /* wait for warmup */ | |
1265 | I915_WRITE(reg, val); | |
1266 | POSTING_READ(reg); | |
1267 | udelay(150); /* wait for warmup */ | |
1268 | I915_WRITE(reg, val); | |
1269 | POSTING_READ(reg); | |
1270 | udelay(150); /* wait for warmup */ | |
1271 | } | |
1272 | ||
1273 | /** | |
1274 | * intel_disable_pll - disable a PLL | |
1275 | * @dev_priv: i915 private structure | |
1276 | * @pipe: pipe PLL to disable | |
1277 | * | |
1278 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1279 | * | |
1280 | * Note! This is for pre-ILK only. | |
1281 | */ | |
1282 | static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1283 | { | |
1284 | int reg; | |
1285 | u32 val; | |
1286 | ||
1287 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1288 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1289 | return; | |
1290 | ||
1291 | /* Make sure the pipe isn't still relying on us */ | |
1292 | assert_pipe_disabled(dev_priv, pipe); | |
1293 | ||
1294 | reg = DPLL(pipe); | |
1295 | val = I915_READ(reg); | |
1296 | val &= ~DPLL_VCO_ENABLE; | |
1297 | I915_WRITE(reg, val); | |
1298 | POSTING_READ(reg); | |
1299 | } | |
1300 | ||
92f2584a JB |
1301 | /** |
1302 | * intel_enable_pch_pll - enable PCH PLL | |
1303 | * @dev_priv: i915 private structure | |
1304 | * @pipe: pipe PLL to enable | |
1305 | * | |
1306 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1307 | * drives the transcoder clock. | |
1308 | */ | |
1309 | static void intel_enable_pch_pll(struct drm_i915_private *dev_priv, | |
1310 | enum pipe pipe) | |
1311 | { | |
1312 | int reg; | |
1313 | u32 val; | |
1314 | ||
4c609cb8 JB |
1315 | if (pipe > 1) |
1316 | return; | |
1317 | ||
92f2584a JB |
1318 | /* PCH only available on ILK+ */ |
1319 | BUG_ON(dev_priv->info->gen < 5); | |
1320 | ||
1321 | /* PCH refclock must be enabled first */ | |
1322 | assert_pch_refclk_enabled(dev_priv); | |
1323 | ||
1324 | reg = PCH_DPLL(pipe); | |
1325 | val = I915_READ(reg); | |
1326 | val |= DPLL_VCO_ENABLE; | |
1327 | I915_WRITE(reg, val); | |
1328 | POSTING_READ(reg); | |
1329 | udelay(200); | |
1330 | } | |
1331 | ||
1332 | static void intel_disable_pch_pll(struct drm_i915_private *dev_priv, | |
1333 | enum pipe pipe) | |
1334 | { | |
1335 | int reg; | |
7a419866 JB |
1336 | u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL, |
1337 | pll_sel = TRANSC_DPLL_ENABLE; | |
92f2584a | 1338 | |
4c609cb8 JB |
1339 | if (pipe > 1) |
1340 | return; | |
1341 | ||
92f2584a JB |
1342 | /* PCH only available on ILK+ */ |
1343 | BUG_ON(dev_priv->info->gen < 5); | |
1344 | ||
1345 | /* Make sure transcoder isn't still depending on us */ | |
1346 | assert_transcoder_disabled(dev_priv, pipe); | |
1347 | ||
7a419866 JB |
1348 | if (pipe == 0) |
1349 | pll_sel |= TRANSC_DPLLA_SEL; | |
1350 | else if (pipe == 1) | |
1351 | pll_sel |= TRANSC_DPLLB_SEL; | |
1352 | ||
1353 | ||
1354 | if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel) | |
1355 | return; | |
1356 | ||
92f2584a JB |
1357 | reg = PCH_DPLL(pipe); |
1358 | val = I915_READ(reg); | |
1359 | val &= ~DPLL_VCO_ENABLE; | |
1360 | I915_WRITE(reg, val); | |
1361 | POSTING_READ(reg); | |
1362 | udelay(200); | |
1363 | } | |
1364 | ||
040484af JB |
1365 | static void intel_enable_transcoder(struct drm_i915_private *dev_priv, |
1366 | enum pipe pipe) | |
1367 | { | |
1368 | int reg; | |
5f7f726d | 1369 | u32 val, pipeconf_val; |
7c26e5c6 | 1370 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
040484af JB |
1371 | |
1372 | /* PCH only available on ILK+ */ | |
1373 | BUG_ON(dev_priv->info->gen < 5); | |
1374 | ||
1375 | /* Make sure PCH DPLL is enabled */ | |
1376 | assert_pch_pll_enabled(dev_priv, pipe); | |
1377 | ||
1378 | /* FDI must be feeding us bits for PCH ports */ | |
1379 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1380 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1381 | ||
1382 | reg = TRANSCONF(pipe); | |
1383 | val = I915_READ(reg); | |
5f7f726d | 1384 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1385 | |
1386 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1387 | /* | |
1388 | * make the BPC in transcoder be consistent with | |
1389 | * that in pipeconf reg. | |
1390 | */ | |
1391 | val &= ~PIPE_BPC_MASK; | |
5f7f726d | 1392 | val |= pipeconf_val & PIPE_BPC_MASK; |
e9bcff5c | 1393 | } |
5f7f726d PZ |
1394 | |
1395 | val &= ~TRANS_INTERLACE_MASK; | |
1396 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1397 | if (HAS_PCH_IBX(dev_priv->dev) && |
1398 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1399 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1400 | else | |
1401 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1402 | else |
1403 | val |= TRANS_PROGRESSIVE; | |
1404 | ||
040484af JB |
1405 | I915_WRITE(reg, val | TRANS_ENABLE); |
1406 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
1407 | DRM_ERROR("failed to enable transcoder %d\n", pipe); | |
1408 | } | |
1409 | ||
1410 | static void intel_disable_transcoder(struct drm_i915_private *dev_priv, | |
1411 | enum pipe pipe) | |
1412 | { | |
1413 | int reg; | |
1414 | u32 val; | |
1415 | ||
1416 | /* FDI relies on the transcoder */ | |
1417 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1418 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1419 | ||
291906f1 JB |
1420 | /* Ports must be off as well */ |
1421 | assert_pch_ports_disabled(dev_priv, pipe); | |
1422 | ||
040484af JB |
1423 | reg = TRANSCONF(pipe); |
1424 | val = I915_READ(reg); | |
1425 | val &= ~TRANS_ENABLE; | |
1426 | I915_WRITE(reg, val); | |
1427 | /* wait for PCH transcoder off, transcoder state */ | |
1428 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4c9c18c2 | 1429 | DRM_ERROR("failed to disable transcoder %d\n", pipe); |
040484af JB |
1430 | } |
1431 | ||
b24e7179 | 1432 | /** |
309cfea8 | 1433 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1434 | * @dev_priv: i915 private structure |
1435 | * @pipe: pipe to enable | |
040484af | 1436 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1437 | * |
1438 | * Enable @pipe, making sure that various hardware specific requirements | |
1439 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1440 | * | |
1441 | * @pipe should be %PIPE_A or %PIPE_B. | |
1442 | * | |
1443 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1444 | * returning. | |
1445 | */ | |
040484af JB |
1446 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1447 | bool pch_port) | |
b24e7179 JB |
1448 | { |
1449 | int reg; | |
1450 | u32 val; | |
1451 | ||
1452 | /* | |
1453 | * A pipe without a PLL won't actually be able to drive bits from | |
1454 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1455 | * need the check. | |
1456 | */ | |
1457 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
1458 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1459 | else { |
1460 | if (pch_port) { | |
1461 | /* if driving the PCH, we need FDI enabled */ | |
1462 | assert_fdi_rx_pll_enabled(dev_priv, pipe); | |
1463 | assert_fdi_tx_pll_enabled(dev_priv, pipe); | |
1464 | } | |
1465 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1466 | } | |
b24e7179 JB |
1467 | |
1468 | reg = PIPECONF(pipe); | |
1469 | val = I915_READ(reg); | |
00d70b15 CW |
1470 | if (val & PIPECONF_ENABLE) |
1471 | return; | |
1472 | ||
1473 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1474 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1475 | } | |
1476 | ||
1477 | /** | |
309cfea8 | 1478 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1479 | * @dev_priv: i915 private structure |
1480 | * @pipe: pipe to disable | |
1481 | * | |
1482 | * Disable @pipe, making sure that various hardware specific requirements | |
1483 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1484 | * | |
1485 | * @pipe should be %PIPE_A or %PIPE_B. | |
1486 | * | |
1487 | * Will wait until the pipe has shut down before returning. | |
1488 | */ | |
1489 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1490 | enum pipe pipe) | |
1491 | { | |
1492 | int reg; | |
1493 | u32 val; | |
1494 | ||
1495 | /* | |
1496 | * Make sure planes won't keep trying to pump pixels to us, | |
1497 | * or we might hang the display. | |
1498 | */ | |
1499 | assert_planes_disabled(dev_priv, pipe); | |
1500 | ||
1501 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1502 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1503 | return; | |
1504 | ||
1505 | reg = PIPECONF(pipe); | |
1506 | val = I915_READ(reg); | |
00d70b15 CW |
1507 | if ((val & PIPECONF_ENABLE) == 0) |
1508 | return; | |
1509 | ||
1510 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1511 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1512 | } | |
1513 | ||
d74362c9 KP |
1514 | /* |
1515 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1516 | * trigger in order to latch. The display address reg provides this. | |
1517 | */ | |
6f1d69b0 | 1518 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
d74362c9 KP |
1519 | enum plane plane) |
1520 | { | |
1521 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); | |
1522 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); | |
1523 | } | |
1524 | ||
b24e7179 JB |
1525 | /** |
1526 | * intel_enable_plane - enable a display plane on a given pipe | |
1527 | * @dev_priv: i915 private structure | |
1528 | * @plane: plane to enable | |
1529 | * @pipe: pipe being fed | |
1530 | * | |
1531 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1532 | */ | |
1533 | static void intel_enable_plane(struct drm_i915_private *dev_priv, | |
1534 | enum plane plane, enum pipe pipe) | |
1535 | { | |
1536 | int reg; | |
1537 | u32 val; | |
1538 | ||
1539 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1540 | assert_pipe_enabled(dev_priv, pipe); | |
1541 | ||
1542 | reg = DSPCNTR(plane); | |
1543 | val = I915_READ(reg); | |
00d70b15 CW |
1544 | if (val & DISPLAY_PLANE_ENABLE) |
1545 | return; | |
1546 | ||
1547 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
d74362c9 | 1548 | intel_flush_display_plane(dev_priv, plane); |
b24e7179 JB |
1549 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1550 | } | |
1551 | ||
b24e7179 JB |
1552 | /** |
1553 | * intel_disable_plane - disable a display plane | |
1554 | * @dev_priv: i915 private structure | |
1555 | * @plane: plane to disable | |
1556 | * @pipe: pipe consuming the data | |
1557 | * | |
1558 | * Disable @plane; should be an independent operation. | |
1559 | */ | |
1560 | static void intel_disable_plane(struct drm_i915_private *dev_priv, | |
1561 | enum plane plane, enum pipe pipe) | |
1562 | { | |
1563 | int reg; | |
1564 | u32 val; | |
1565 | ||
1566 | reg = DSPCNTR(plane); | |
1567 | val = I915_READ(reg); | |
00d70b15 CW |
1568 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1569 | return; | |
1570 | ||
1571 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
b24e7179 JB |
1572 | intel_flush_display_plane(dev_priv, plane); |
1573 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1574 | } | |
1575 | ||
47a05eca | 1576 | static void disable_pch_dp(struct drm_i915_private *dev_priv, |
f0575e92 | 1577 | enum pipe pipe, int reg, u32 port_sel) |
47a05eca JB |
1578 | { |
1579 | u32 val = I915_READ(reg); | |
4e634389 | 1580 | if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) { |
f0575e92 | 1581 | DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe); |
47a05eca | 1582 | I915_WRITE(reg, val & ~DP_PORT_EN); |
f0575e92 | 1583 | } |
47a05eca JB |
1584 | } |
1585 | ||
1586 | static void disable_pch_hdmi(struct drm_i915_private *dev_priv, | |
1587 | enum pipe pipe, int reg) | |
1588 | { | |
1589 | u32 val = I915_READ(reg); | |
1519b995 | 1590 | if (hdmi_pipe_enabled(dev_priv, val, pipe)) { |
f0575e92 KP |
1591 | DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n", |
1592 | reg, pipe); | |
47a05eca | 1593 | I915_WRITE(reg, val & ~PORT_ENABLE); |
f0575e92 | 1594 | } |
47a05eca JB |
1595 | } |
1596 | ||
1597 | /* Disable any ports connected to this transcoder */ | |
1598 | static void intel_disable_pch_ports(struct drm_i915_private *dev_priv, | |
1599 | enum pipe pipe) | |
1600 | { | |
1601 | u32 reg, val; | |
1602 | ||
1603 | val = I915_READ(PCH_PP_CONTROL); | |
1604 | I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS); | |
1605 | ||
f0575e92 KP |
1606 | disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1607 | disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1608 | disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
47a05eca JB |
1609 | |
1610 | reg = PCH_ADPA; | |
1611 | val = I915_READ(reg); | |
1519b995 | 1612 | if (adpa_pipe_enabled(dev_priv, val, pipe)) |
47a05eca JB |
1613 | I915_WRITE(reg, val & ~ADPA_DAC_ENABLE); |
1614 | ||
1615 | reg = PCH_LVDS; | |
1616 | val = I915_READ(reg); | |
1519b995 KP |
1617 | if (lvds_pipe_enabled(dev_priv, val, pipe)) { |
1618 | DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val); | |
47a05eca JB |
1619 | I915_WRITE(reg, val & ~LVDS_PORT_EN); |
1620 | POSTING_READ(reg); | |
1621 | udelay(100); | |
1622 | } | |
1623 | ||
1624 | disable_pch_hdmi(dev_priv, pipe, HDMIB); | |
1625 | disable_pch_hdmi(dev_priv, pipe, HDMIC); | |
1626 | disable_pch_hdmi(dev_priv, pipe, HDMID); | |
1627 | } | |
1628 | ||
127bd2ac | 1629 | int |
48b956c5 | 1630 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1631 | struct drm_i915_gem_object *obj, |
919926ae | 1632 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1633 | { |
ce453d81 | 1634 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1635 | u32 alignment; |
1636 | int ret; | |
1637 | ||
05394f39 | 1638 | switch (obj->tiling_mode) { |
6b95a207 | 1639 | case I915_TILING_NONE: |
534843da CW |
1640 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1641 | alignment = 128 * 1024; | |
a6c45cf0 | 1642 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1643 | alignment = 4 * 1024; |
1644 | else | |
1645 | alignment = 64 * 1024; | |
6b95a207 KH |
1646 | break; |
1647 | case I915_TILING_X: | |
1648 | /* pin() will align the object as required by fence */ | |
1649 | alignment = 0; | |
1650 | break; | |
1651 | case I915_TILING_Y: | |
1652 | /* FIXME: Is this true? */ | |
1653 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
1654 | return -EINVAL; | |
1655 | default: | |
1656 | BUG(); | |
1657 | } | |
1658 | ||
ce453d81 | 1659 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 1660 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 1661 | if (ret) |
ce453d81 | 1662 | goto err_interruptible; |
6b95a207 KH |
1663 | |
1664 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1665 | * fence, whereas 965+ only requires a fence if using | |
1666 | * framebuffer compression. For simplicity, we always install | |
1667 | * a fence as the cost is not that onerous. | |
1668 | */ | |
06d98131 | 1669 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
1670 | if (ret) |
1671 | goto err_unpin; | |
1690e1eb | 1672 | |
9a5a53b3 | 1673 | i915_gem_object_pin_fence(obj); |
6b95a207 | 1674 | |
ce453d81 | 1675 | dev_priv->mm.interruptible = true; |
6b95a207 | 1676 | return 0; |
48b956c5 CW |
1677 | |
1678 | err_unpin: | |
1679 | i915_gem_object_unpin(obj); | |
ce453d81 CW |
1680 | err_interruptible: |
1681 | dev_priv->mm.interruptible = true; | |
48b956c5 | 1682 | return ret; |
6b95a207 KH |
1683 | } |
1684 | ||
1690e1eb CW |
1685 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1686 | { | |
1687 | i915_gem_object_unpin_fence(obj); | |
1688 | i915_gem_object_unpin(obj); | |
1689 | } | |
1690 | ||
17638cd6 JB |
1691 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
1692 | int x, int y) | |
81255565 JB |
1693 | { |
1694 | struct drm_device *dev = crtc->dev; | |
1695 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1696 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1697 | struct intel_framebuffer *intel_fb; | |
05394f39 | 1698 | struct drm_i915_gem_object *obj; |
81255565 JB |
1699 | int plane = intel_crtc->plane; |
1700 | unsigned long Start, Offset; | |
81255565 | 1701 | u32 dspcntr; |
5eddb70b | 1702 | u32 reg; |
81255565 JB |
1703 | |
1704 | switch (plane) { | |
1705 | case 0: | |
1706 | case 1: | |
1707 | break; | |
1708 | default: | |
1709 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
1710 | return -EINVAL; | |
1711 | } | |
1712 | ||
1713 | intel_fb = to_intel_framebuffer(fb); | |
1714 | obj = intel_fb->obj; | |
81255565 | 1715 | |
5eddb70b CW |
1716 | reg = DSPCNTR(plane); |
1717 | dspcntr = I915_READ(reg); | |
81255565 JB |
1718 | /* Mask out pixel format bits in case we change it */ |
1719 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
1720 | switch (fb->bits_per_pixel) { | |
1721 | case 8: | |
1722 | dspcntr |= DISPPLANE_8BPP; | |
1723 | break; | |
1724 | case 16: | |
1725 | if (fb->depth == 15) | |
1726 | dspcntr |= DISPPLANE_15_16BPP; | |
1727 | else | |
1728 | dspcntr |= DISPPLANE_16BPP; | |
1729 | break; | |
1730 | case 24: | |
1731 | case 32: | |
1732 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
1733 | break; | |
1734 | default: | |
17638cd6 | 1735 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); |
81255565 JB |
1736 | return -EINVAL; |
1737 | } | |
a6c45cf0 | 1738 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 1739 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
1740 | dspcntr |= DISPPLANE_TILED; |
1741 | else | |
1742 | dspcntr &= ~DISPPLANE_TILED; | |
1743 | } | |
1744 | ||
5eddb70b | 1745 | I915_WRITE(reg, dspcntr); |
81255565 | 1746 | |
05394f39 | 1747 | Start = obj->gtt_offset; |
01f2c773 | 1748 | Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 1749 | |
4e6cfefc | 1750 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
01f2c773 VS |
1751 | Start, Offset, x, y, fb->pitches[0]); |
1752 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); | |
a6c45cf0 | 1753 | if (INTEL_INFO(dev)->gen >= 4) { |
446f2545 | 1754 | I915_MODIFY_DISPBASE(DSPSURF(plane), Start); |
5eddb70b CW |
1755 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
1756 | I915_WRITE(DSPADDR(plane), Offset); | |
1757 | } else | |
1758 | I915_WRITE(DSPADDR(plane), Start + Offset); | |
1759 | POSTING_READ(reg); | |
81255565 | 1760 | |
17638cd6 JB |
1761 | return 0; |
1762 | } | |
1763 | ||
1764 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
1765 | struct drm_framebuffer *fb, int x, int y) | |
1766 | { | |
1767 | struct drm_device *dev = crtc->dev; | |
1768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1769 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1770 | struct intel_framebuffer *intel_fb; | |
1771 | struct drm_i915_gem_object *obj; | |
1772 | int plane = intel_crtc->plane; | |
1773 | unsigned long Start, Offset; | |
1774 | u32 dspcntr; | |
1775 | u32 reg; | |
1776 | ||
1777 | switch (plane) { | |
1778 | case 0: | |
1779 | case 1: | |
27f8227b | 1780 | case 2: |
17638cd6 JB |
1781 | break; |
1782 | default: | |
1783 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
1784 | return -EINVAL; | |
1785 | } | |
1786 | ||
1787 | intel_fb = to_intel_framebuffer(fb); | |
1788 | obj = intel_fb->obj; | |
1789 | ||
1790 | reg = DSPCNTR(plane); | |
1791 | dspcntr = I915_READ(reg); | |
1792 | /* Mask out pixel format bits in case we change it */ | |
1793 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
1794 | switch (fb->bits_per_pixel) { | |
1795 | case 8: | |
1796 | dspcntr |= DISPPLANE_8BPP; | |
1797 | break; | |
1798 | case 16: | |
1799 | if (fb->depth != 16) | |
1800 | return -EINVAL; | |
1801 | ||
1802 | dspcntr |= DISPPLANE_16BPP; | |
1803 | break; | |
1804 | case 24: | |
1805 | case 32: | |
1806 | if (fb->depth == 24) | |
1807 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
1808 | else if (fb->depth == 30) | |
1809 | dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA; | |
1810 | else | |
1811 | return -EINVAL; | |
1812 | break; | |
1813 | default: | |
1814 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); | |
1815 | return -EINVAL; | |
1816 | } | |
1817 | ||
1818 | if (obj->tiling_mode != I915_TILING_NONE) | |
1819 | dspcntr |= DISPPLANE_TILED; | |
1820 | else | |
1821 | dspcntr &= ~DISPPLANE_TILED; | |
1822 | ||
1823 | /* must disable */ | |
1824 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
1825 | ||
1826 | I915_WRITE(reg, dspcntr); | |
1827 | ||
1828 | Start = obj->gtt_offset; | |
01f2c773 | 1829 | Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
17638cd6 JB |
1830 | |
1831 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", | |
01f2c773 VS |
1832 | Start, Offset, x, y, fb->pitches[0]); |
1833 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); | |
446f2545 | 1834 | I915_MODIFY_DISPBASE(DSPSURF(plane), Start); |
17638cd6 JB |
1835 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
1836 | I915_WRITE(DSPADDR(plane), Offset); | |
1837 | POSTING_READ(reg); | |
1838 | ||
1839 | return 0; | |
1840 | } | |
1841 | ||
1842 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
1843 | static int | |
1844 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
1845 | int x, int y, enum mode_set_atomic state) | |
1846 | { | |
1847 | struct drm_device *dev = crtc->dev; | |
1848 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 1849 | |
6b8e6ed0 CW |
1850 | if (dev_priv->display.disable_fbc) |
1851 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 1852 | intel_increase_pllclock(crtc); |
81255565 | 1853 | |
6b8e6ed0 | 1854 | return dev_priv->display.update_plane(crtc, fb, x, y); |
81255565 JB |
1855 | } |
1856 | ||
14667a4b CW |
1857 | static int |
1858 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
1859 | { | |
1860 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
1861 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1862 | bool was_interruptible = dev_priv->mm.interruptible; | |
1863 | int ret; | |
1864 | ||
1865 | wait_event(dev_priv->pending_flip_queue, | |
1866 | atomic_read(&dev_priv->mm.wedged) || | |
1867 | atomic_read(&obj->pending_flip) == 0); | |
1868 | ||
1869 | /* Big Hammer, we also need to ensure that any pending | |
1870 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
1871 | * current scanout is retired before unpinning the old | |
1872 | * framebuffer. | |
1873 | * | |
1874 | * This should only fail upon a hung GPU, in which case we | |
1875 | * can safely continue. | |
1876 | */ | |
1877 | dev_priv->mm.interruptible = false; | |
1878 | ret = i915_gem_object_finish_gpu(obj); | |
1879 | dev_priv->mm.interruptible = was_interruptible; | |
1880 | ||
1881 | return ret; | |
1882 | } | |
1883 | ||
5c3b82e2 | 1884 | static int |
3c4fdcfb KH |
1885 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
1886 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
1887 | { |
1888 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 1889 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
1890 | struct drm_i915_master_private *master_priv; |
1891 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5c3b82e2 | 1892 | int ret; |
79e53945 JB |
1893 | |
1894 | /* no fb bound */ | |
1895 | if (!crtc->fb) { | |
a5071c2f | 1896 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
1897 | return 0; |
1898 | } | |
1899 | ||
265db958 | 1900 | switch (intel_crtc->plane) { |
5c3b82e2 CW |
1901 | case 0: |
1902 | case 1: | |
1903 | break; | |
27f8227b JB |
1904 | case 2: |
1905 | if (IS_IVYBRIDGE(dev)) | |
1906 | break; | |
1907 | /* fall through otherwise */ | |
5c3b82e2 | 1908 | default: |
a5071c2f | 1909 | DRM_ERROR("no plane for crtc\n"); |
5c3b82e2 | 1910 | return -EINVAL; |
79e53945 JB |
1911 | } |
1912 | ||
5c3b82e2 | 1913 | mutex_lock(&dev->struct_mutex); |
265db958 CW |
1914 | ret = intel_pin_and_fence_fb_obj(dev, |
1915 | to_intel_framebuffer(crtc->fb)->obj, | |
919926ae | 1916 | NULL); |
5c3b82e2 CW |
1917 | if (ret != 0) { |
1918 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 1919 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
1920 | return ret; |
1921 | } | |
79e53945 | 1922 | |
14667a4b CW |
1923 | if (old_fb) |
1924 | intel_finish_fb(old_fb); | |
265db958 | 1925 | |
6b8e6ed0 | 1926 | ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y); |
4e6cfefc | 1927 | if (ret) { |
1690e1eb | 1928 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
5c3b82e2 | 1929 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 1930 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 1931 | return ret; |
79e53945 | 1932 | } |
3c4fdcfb | 1933 | |
b7f1de28 CW |
1934 | if (old_fb) { |
1935 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 1936 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 1937 | } |
652c393a | 1938 | |
6b8e6ed0 | 1939 | intel_update_fbc(dev); |
5c3b82e2 | 1940 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
1941 | |
1942 | if (!dev->primary->master) | |
5c3b82e2 | 1943 | return 0; |
79e53945 JB |
1944 | |
1945 | master_priv = dev->primary->master->driver_priv; | |
1946 | if (!master_priv->sarea_priv) | |
5c3b82e2 | 1947 | return 0; |
79e53945 | 1948 | |
265db958 | 1949 | if (intel_crtc->pipe) { |
79e53945 JB |
1950 | master_priv->sarea_priv->pipeB_x = x; |
1951 | master_priv->sarea_priv->pipeB_y = y; | |
5c3b82e2 CW |
1952 | } else { |
1953 | master_priv->sarea_priv->pipeA_x = x; | |
1954 | master_priv->sarea_priv->pipeA_y = y; | |
79e53945 | 1955 | } |
5c3b82e2 CW |
1956 | |
1957 | return 0; | |
79e53945 JB |
1958 | } |
1959 | ||
5eddb70b | 1960 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
32f9d658 ZW |
1961 | { |
1962 | struct drm_device *dev = crtc->dev; | |
1963 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1964 | u32 dpa_ctl; | |
1965 | ||
28c97730 | 1966 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
32f9d658 ZW |
1967 | dpa_ctl = I915_READ(DP_A); |
1968 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
1969 | ||
1970 | if (clock < 200000) { | |
1971 | u32 temp; | |
1972 | dpa_ctl |= DP_PLL_FREQ_160MHZ; | |
1973 | /* workaround for 160Mhz: | |
1974 | 1) program 0x4600c bits 15:0 = 0x8124 | |
1975 | 2) program 0x46010 bit 0 = 1 | |
1976 | 3) program 0x46034 bit 24 = 1 | |
1977 | 4) program 0x64000 bit 14 = 1 | |
1978 | */ | |
1979 | temp = I915_READ(0x4600c); | |
1980 | temp &= 0xffff0000; | |
1981 | I915_WRITE(0x4600c, temp | 0x8124); | |
1982 | ||
1983 | temp = I915_READ(0x46010); | |
1984 | I915_WRITE(0x46010, temp | 1); | |
1985 | ||
1986 | temp = I915_READ(0x46034); | |
1987 | I915_WRITE(0x46034, temp | (1 << 24)); | |
1988 | } else { | |
1989 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
1990 | } | |
1991 | I915_WRITE(DP_A, dpa_ctl); | |
1992 | ||
5eddb70b | 1993 | POSTING_READ(DP_A); |
32f9d658 ZW |
1994 | udelay(500); |
1995 | } | |
1996 | ||
5e84e1a4 ZW |
1997 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
1998 | { | |
1999 | struct drm_device *dev = crtc->dev; | |
2000 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2001 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2002 | int pipe = intel_crtc->pipe; | |
2003 | u32 reg, temp; | |
2004 | ||
2005 | /* enable normal train */ | |
2006 | reg = FDI_TX_CTL(pipe); | |
2007 | temp = I915_READ(reg); | |
61e499bf | 2008 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2009 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2010 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2011 | } else { |
2012 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2013 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2014 | } |
5e84e1a4 ZW |
2015 | I915_WRITE(reg, temp); |
2016 | ||
2017 | reg = FDI_RX_CTL(pipe); | |
2018 | temp = I915_READ(reg); | |
2019 | if (HAS_PCH_CPT(dev)) { | |
2020 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2021 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2022 | } else { | |
2023 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2024 | temp |= FDI_LINK_TRAIN_NONE; | |
2025 | } | |
2026 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2027 | ||
2028 | /* wait one idle pattern time */ | |
2029 | POSTING_READ(reg); | |
2030 | udelay(1000); | |
357555c0 JB |
2031 | |
2032 | /* IVB wants error correction enabled */ | |
2033 | if (IS_IVYBRIDGE(dev)) | |
2034 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2035 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2036 | } |
2037 | ||
291427f5 JB |
2038 | static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe) |
2039 | { | |
2040 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2041 | u32 flags = I915_READ(SOUTH_CHICKEN1); | |
2042 | ||
2043 | flags |= FDI_PHASE_SYNC_OVR(pipe); | |
2044 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ | |
2045 | flags |= FDI_PHASE_SYNC_EN(pipe); | |
2046 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ | |
2047 | POSTING_READ(SOUTH_CHICKEN1); | |
2048 | } | |
2049 | ||
8db9d77b ZW |
2050 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2051 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2052 | { | |
2053 | struct drm_device *dev = crtc->dev; | |
2054 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2055 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2056 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2057 | int plane = intel_crtc->plane; |
5eddb70b | 2058 | u32 reg, temp, tries; |
8db9d77b | 2059 | |
0fc932b8 JB |
2060 | /* FDI needs bits from pipe & plane first */ |
2061 | assert_pipe_enabled(dev_priv, pipe); | |
2062 | assert_plane_enabled(dev_priv, plane); | |
2063 | ||
e1a44743 AJ |
2064 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2065 | for train result */ | |
5eddb70b CW |
2066 | reg = FDI_RX_IMR(pipe); |
2067 | temp = I915_READ(reg); | |
e1a44743 AJ |
2068 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2069 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2070 | I915_WRITE(reg, temp); |
2071 | I915_READ(reg); | |
e1a44743 AJ |
2072 | udelay(150); |
2073 | ||
8db9d77b | 2074 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2075 | reg = FDI_TX_CTL(pipe); |
2076 | temp = I915_READ(reg); | |
77ffb597 AJ |
2077 | temp &= ~(7 << 19); |
2078 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2079 | temp &= ~FDI_LINK_TRAIN_NONE; |
2080 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2081 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2082 | |
5eddb70b CW |
2083 | reg = FDI_RX_CTL(pipe); |
2084 | temp = I915_READ(reg); | |
8db9d77b ZW |
2085 | temp &= ~FDI_LINK_TRAIN_NONE; |
2086 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2087 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2088 | ||
2089 | POSTING_READ(reg); | |
8db9d77b ZW |
2090 | udelay(150); |
2091 | ||
5b2adf89 | 2092 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
6f06ce18 JB |
2093 | if (HAS_PCH_IBX(dev)) { |
2094 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
2095 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2096 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
2097 | } | |
5b2adf89 | 2098 | |
5eddb70b | 2099 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2100 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2101 | temp = I915_READ(reg); |
8db9d77b ZW |
2102 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2103 | ||
2104 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2105 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2106 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2107 | break; |
2108 | } | |
8db9d77b | 2109 | } |
e1a44743 | 2110 | if (tries == 5) |
5eddb70b | 2111 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2112 | |
2113 | /* Train 2 */ | |
5eddb70b CW |
2114 | reg = FDI_TX_CTL(pipe); |
2115 | temp = I915_READ(reg); | |
8db9d77b ZW |
2116 | temp &= ~FDI_LINK_TRAIN_NONE; |
2117 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2118 | I915_WRITE(reg, temp); |
8db9d77b | 2119 | |
5eddb70b CW |
2120 | reg = FDI_RX_CTL(pipe); |
2121 | temp = I915_READ(reg); | |
8db9d77b ZW |
2122 | temp &= ~FDI_LINK_TRAIN_NONE; |
2123 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2124 | I915_WRITE(reg, temp); |
8db9d77b | 2125 | |
5eddb70b CW |
2126 | POSTING_READ(reg); |
2127 | udelay(150); | |
8db9d77b | 2128 | |
5eddb70b | 2129 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2130 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2131 | temp = I915_READ(reg); |
8db9d77b ZW |
2132 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2133 | ||
2134 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2135 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2136 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2137 | break; | |
2138 | } | |
8db9d77b | 2139 | } |
e1a44743 | 2140 | if (tries == 5) |
5eddb70b | 2141 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2142 | |
2143 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2144 | |
8db9d77b ZW |
2145 | } |
2146 | ||
0206e353 | 2147 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2148 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2149 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2150 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2151 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2152 | }; | |
2153 | ||
2154 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2155 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2156 | { | |
2157 | struct drm_device *dev = crtc->dev; | |
2158 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2159 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2160 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2161 | u32 reg, temp, i, retry; |
8db9d77b | 2162 | |
e1a44743 AJ |
2163 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2164 | for train result */ | |
5eddb70b CW |
2165 | reg = FDI_RX_IMR(pipe); |
2166 | temp = I915_READ(reg); | |
e1a44743 AJ |
2167 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2168 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2169 | I915_WRITE(reg, temp); |
2170 | ||
2171 | POSTING_READ(reg); | |
e1a44743 AJ |
2172 | udelay(150); |
2173 | ||
8db9d77b | 2174 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2175 | reg = FDI_TX_CTL(pipe); |
2176 | temp = I915_READ(reg); | |
77ffb597 AJ |
2177 | temp &= ~(7 << 19); |
2178 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2179 | temp &= ~FDI_LINK_TRAIN_NONE; |
2180 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2181 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2182 | /* SNB-B */ | |
2183 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2184 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2185 | |
5eddb70b CW |
2186 | reg = FDI_RX_CTL(pipe); |
2187 | temp = I915_READ(reg); | |
8db9d77b ZW |
2188 | if (HAS_PCH_CPT(dev)) { |
2189 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2190 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2191 | } else { | |
2192 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2193 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2194 | } | |
5eddb70b CW |
2195 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2196 | ||
2197 | POSTING_READ(reg); | |
8db9d77b ZW |
2198 | udelay(150); |
2199 | ||
291427f5 JB |
2200 | if (HAS_PCH_CPT(dev)) |
2201 | cpt_phase_pointer_enable(dev, pipe); | |
2202 | ||
0206e353 | 2203 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2204 | reg = FDI_TX_CTL(pipe); |
2205 | temp = I915_READ(reg); | |
8db9d77b ZW |
2206 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2207 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2208 | I915_WRITE(reg, temp); |
2209 | ||
2210 | POSTING_READ(reg); | |
8db9d77b ZW |
2211 | udelay(500); |
2212 | ||
fa37d39e SP |
2213 | for (retry = 0; retry < 5; retry++) { |
2214 | reg = FDI_RX_IIR(pipe); | |
2215 | temp = I915_READ(reg); | |
2216 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2217 | if (temp & FDI_RX_BIT_LOCK) { | |
2218 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2219 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2220 | break; | |
2221 | } | |
2222 | udelay(50); | |
8db9d77b | 2223 | } |
fa37d39e SP |
2224 | if (retry < 5) |
2225 | break; | |
8db9d77b ZW |
2226 | } |
2227 | if (i == 4) | |
5eddb70b | 2228 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2229 | |
2230 | /* Train 2 */ | |
5eddb70b CW |
2231 | reg = FDI_TX_CTL(pipe); |
2232 | temp = I915_READ(reg); | |
8db9d77b ZW |
2233 | temp &= ~FDI_LINK_TRAIN_NONE; |
2234 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2235 | if (IS_GEN6(dev)) { | |
2236 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2237 | /* SNB-B */ | |
2238 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2239 | } | |
5eddb70b | 2240 | I915_WRITE(reg, temp); |
8db9d77b | 2241 | |
5eddb70b CW |
2242 | reg = FDI_RX_CTL(pipe); |
2243 | temp = I915_READ(reg); | |
8db9d77b ZW |
2244 | if (HAS_PCH_CPT(dev)) { |
2245 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2246 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2247 | } else { | |
2248 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2249 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2250 | } | |
5eddb70b CW |
2251 | I915_WRITE(reg, temp); |
2252 | ||
2253 | POSTING_READ(reg); | |
8db9d77b ZW |
2254 | udelay(150); |
2255 | ||
0206e353 | 2256 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2257 | reg = FDI_TX_CTL(pipe); |
2258 | temp = I915_READ(reg); | |
8db9d77b ZW |
2259 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2260 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2261 | I915_WRITE(reg, temp); |
2262 | ||
2263 | POSTING_READ(reg); | |
8db9d77b ZW |
2264 | udelay(500); |
2265 | ||
fa37d39e SP |
2266 | for (retry = 0; retry < 5; retry++) { |
2267 | reg = FDI_RX_IIR(pipe); | |
2268 | temp = I915_READ(reg); | |
2269 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2270 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2271 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2272 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2273 | break; | |
2274 | } | |
2275 | udelay(50); | |
8db9d77b | 2276 | } |
fa37d39e SP |
2277 | if (retry < 5) |
2278 | break; | |
8db9d77b ZW |
2279 | } |
2280 | if (i == 4) | |
5eddb70b | 2281 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2282 | |
2283 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2284 | } | |
2285 | ||
357555c0 JB |
2286 | /* Manual link training for Ivy Bridge A0 parts */ |
2287 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2288 | { | |
2289 | struct drm_device *dev = crtc->dev; | |
2290 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2291 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2292 | int pipe = intel_crtc->pipe; | |
2293 | u32 reg, temp, i; | |
2294 | ||
2295 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2296 | for train result */ | |
2297 | reg = FDI_RX_IMR(pipe); | |
2298 | temp = I915_READ(reg); | |
2299 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2300 | temp &= ~FDI_RX_BIT_LOCK; | |
2301 | I915_WRITE(reg, temp); | |
2302 | ||
2303 | POSTING_READ(reg); | |
2304 | udelay(150); | |
2305 | ||
2306 | /* enable CPU FDI TX and PCH FDI RX */ | |
2307 | reg = FDI_TX_CTL(pipe); | |
2308 | temp = I915_READ(reg); | |
2309 | temp &= ~(7 << 19); | |
2310 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
2311 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2312 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
2313 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2314 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
c4f9c4c2 | 2315 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2316 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2317 | ||
2318 | reg = FDI_RX_CTL(pipe); | |
2319 | temp = I915_READ(reg); | |
2320 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2321 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2322 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
c4f9c4c2 | 2323 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2324 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2325 | ||
2326 | POSTING_READ(reg); | |
2327 | udelay(150); | |
2328 | ||
291427f5 JB |
2329 | if (HAS_PCH_CPT(dev)) |
2330 | cpt_phase_pointer_enable(dev, pipe); | |
2331 | ||
0206e353 | 2332 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2333 | reg = FDI_TX_CTL(pipe); |
2334 | temp = I915_READ(reg); | |
2335 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2336 | temp |= snb_b_fdi_train_param[i]; | |
2337 | I915_WRITE(reg, temp); | |
2338 | ||
2339 | POSTING_READ(reg); | |
2340 | udelay(500); | |
2341 | ||
2342 | reg = FDI_RX_IIR(pipe); | |
2343 | temp = I915_READ(reg); | |
2344 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2345 | ||
2346 | if (temp & FDI_RX_BIT_LOCK || | |
2347 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2348 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2349 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2350 | break; | |
2351 | } | |
2352 | } | |
2353 | if (i == 4) | |
2354 | DRM_ERROR("FDI train 1 fail!\n"); | |
2355 | ||
2356 | /* Train 2 */ | |
2357 | reg = FDI_TX_CTL(pipe); | |
2358 | temp = I915_READ(reg); | |
2359 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; | |
2360 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2361 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2362 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2363 | I915_WRITE(reg, temp); | |
2364 | ||
2365 | reg = FDI_RX_CTL(pipe); | |
2366 | temp = I915_READ(reg); | |
2367 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2368 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2369 | I915_WRITE(reg, temp); | |
2370 | ||
2371 | POSTING_READ(reg); | |
2372 | udelay(150); | |
2373 | ||
0206e353 | 2374 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2375 | reg = FDI_TX_CTL(pipe); |
2376 | temp = I915_READ(reg); | |
2377 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2378 | temp |= snb_b_fdi_train_param[i]; | |
2379 | I915_WRITE(reg, temp); | |
2380 | ||
2381 | POSTING_READ(reg); | |
2382 | udelay(500); | |
2383 | ||
2384 | reg = FDI_RX_IIR(pipe); | |
2385 | temp = I915_READ(reg); | |
2386 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2387 | ||
2388 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2389 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2390 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2391 | break; | |
2392 | } | |
2393 | } | |
2394 | if (i == 4) | |
2395 | DRM_ERROR("FDI train 2 fail!\n"); | |
2396 | ||
2397 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2398 | } | |
2399 | ||
2400 | static void ironlake_fdi_pll_enable(struct drm_crtc *crtc) | |
2c07245f ZW |
2401 | { |
2402 | struct drm_device *dev = crtc->dev; | |
2403 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2404 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2405 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2406 | u32 reg, temp; |
79e53945 | 2407 | |
c64e311e | 2408 | /* Write the TU size bits so error detection works */ |
5eddb70b CW |
2409 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
2410 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
c64e311e | 2411 | |
c98e9dcf | 2412 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2413 | reg = FDI_RX_CTL(pipe); |
2414 | temp = I915_READ(reg); | |
2415 | temp &= ~((0x7 << 19) | (0x7 << 16)); | |
c98e9dcf | 2416 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
5eddb70b CW |
2417 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
2418 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); | |
2419 | ||
2420 | POSTING_READ(reg); | |
c98e9dcf JB |
2421 | udelay(200); |
2422 | ||
2423 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2424 | temp = I915_READ(reg); |
2425 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2426 | ||
2427 | POSTING_READ(reg); | |
c98e9dcf JB |
2428 | udelay(200); |
2429 | ||
2430 | /* Enable CPU FDI TX PLL, always on for Ironlake */ | |
5eddb70b CW |
2431 | reg = FDI_TX_CTL(pipe); |
2432 | temp = I915_READ(reg); | |
c98e9dcf | 2433 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
5eddb70b CW |
2434 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
2435 | ||
2436 | POSTING_READ(reg); | |
c98e9dcf | 2437 | udelay(100); |
6be4a607 | 2438 | } |
0e23b99d JB |
2439 | } |
2440 | ||
291427f5 JB |
2441 | static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe) |
2442 | { | |
2443 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2444 | u32 flags = I915_READ(SOUTH_CHICKEN1); | |
2445 | ||
2446 | flags &= ~(FDI_PHASE_SYNC_EN(pipe)); | |
2447 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */ | |
2448 | flags &= ~(FDI_PHASE_SYNC_OVR(pipe)); | |
2449 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */ | |
2450 | POSTING_READ(SOUTH_CHICKEN1); | |
2451 | } | |
0fc932b8 JB |
2452 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2453 | { | |
2454 | struct drm_device *dev = crtc->dev; | |
2455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2456 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2457 | int pipe = intel_crtc->pipe; | |
2458 | u32 reg, temp; | |
2459 | ||
2460 | /* disable CPU FDI tx and PCH FDI rx */ | |
2461 | reg = FDI_TX_CTL(pipe); | |
2462 | temp = I915_READ(reg); | |
2463 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2464 | POSTING_READ(reg); | |
2465 | ||
2466 | reg = FDI_RX_CTL(pipe); | |
2467 | temp = I915_READ(reg); | |
2468 | temp &= ~(0x7 << 16); | |
2469 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2470 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); | |
2471 | ||
2472 | POSTING_READ(reg); | |
2473 | udelay(100); | |
2474 | ||
2475 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2476 | if (HAS_PCH_IBX(dev)) { |
2477 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
0fc932b8 JB |
2478 | I915_WRITE(FDI_RX_CHICKEN(pipe), |
2479 | I915_READ(FDI_RX_CHICKEN(pipe) & | |
6f06ce18 | 2480 | ~FDI_RX_PHASE_SYNC_POINTER_EN)); |
291427f5 JB |
2481 | } else if (HAS_PCH_CPT(dev)) { |
2482 | cpt_phase_pointer_disable(dev, pipe); | |
6f06ce18 | 2483 | } |
0fc932b8 JB |
2484 | |
2485 | /* still set train pattern 1 */ | |
2486 | reg = FDI_TX_CTL(pipe); | |
2487 | temp = I915_READ(reg); | |
2488 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2489 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2490 | I915_WRITE(reg, temp); | |
2491 | ||
2492 | reg = FDI_RX_CTL(pipe); | |
2493 | temp = I915_READ(reg); | |
2494 | if (HAS_PCH_CPT(dev)) { | |
2495 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2496 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2497 | } else { | |
2498 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2499 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2500 | } | |
2501 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2502 | temp &= ~(0x07 << 16); | |
2503 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2504 | I915_WRITE(reg, temp); | |
2505 | ||
2506 | POSTING_READ(reg); | |
2507 | udelay(100); | |
2508 | } | |
2509 | ||
6b383a7f CW |
2510 | /* |
2511 | * When we disable a pipe, we need to clear any pending scanline wait events | |
2512 | * to avoid hanging the ring, which we assume we are waiting on. | |
2513 | */ | |
2514 | static void intel_clear_scanline_wait(struct drm_device *dev) | |
2515 | { | |
2516 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8168bd48 | 2517 | struct intel_ring_buffer *ring; |
6b383a7f CW |
2518 | u32 tmp; |
2519 | ||
2520 | if (IS_GEN2(dev)) | |
2521 | /* Can't break the hang on i8xx */ | |
2522 | return; | |
2523 | ||
1ec14ad3 | 2524 | ring = LP_RING(dev_priv); |
8168bd48 CW |
2525 | tmp = I915_READ_CTL(ring); |
2526 | if (tmp & RING_WAIT) | |
2527 | I915_WRITE_CTL(ring, tmp); | |
6b383a7f CW |
2528 | } |
2529 | ||
e6c3a2a6 CW |
2530 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2531 | { | |
0f91128d | 2532 | struct drm_device *dev = crtc->dev; |
e6c3a2a6 CW |
2533 | |
2534 | if (crtc->fb == NULL) | |
2535 | return; | |
2536 | ||
0f91128d CW |
2537 | mutex_lock(&dev->struct_mutex); |
2538 | intel_finish_fb(crtc->fb); | |
2539 | mutex_unlock(&dev->struct_mutex); | |
e6c3a2a6 CW |
2540 | } |
2541 | ||
040484af JB |
2542 | static bool intel_crtc_driving_pch(struct drm_crtc *crtc) |
2543 | { | |
2544 | struct drm_device *dev = crtc->dev; | |
2545 | struct drm_mode_config *mode_config = &dev->mode_config; | |
2546 | struct intel_encoder *encoder; | |
2547 | ||
2548 | /* | |
2549 | * If there's a non-PCH eDP on this crtc, it must be DP_A, and that | |
2550 | * must be driven by its own crtc; no sharing is possible. | |
2551 | */ | |
2552 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
2553 | if (encoder->base.crtc != crtc) | |
2554 | continue; | |
2555 | ||
2556 | switch (encoder->type) { | |
2557 | case INTEL_OUTPUT_EDP: | |
2558 | if (!intel_encoder_is_pch_edp(&encoder->base)) | |
2559 | return false; | |
2560 | continue; | |
2561 | } | |
2562 | } | |
2563 | ||
2564 | return true; | |
2565 | } | |
2566 | ||
f67a559d JB |
2567 | /* |
2568 | * Enable PCH resources required for PCH ports: | |
2569 | * - PCH PLLs | |
2570 | * - FDI training & RX/TX | |
2571 | * - update transcoder timings | |
2572 | * - DP transcoding bits | |
2573 | * - transcoder | |
2574 | */ | |
2575 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
2576 | { |
2577 | struct drm_device *dev = crtc->dev; | |
2578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2579 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2580 | int pipe = intel_crtc->pipe; | |
4b645f14 | 2581 | u32 reg, temp, transc_sel; |
2c07245f | 2582 | |
c98e9dcf | 2583 | /* For PCH output, training FDI link */ |
674cf967 | 2584 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 2585 | |
92f2584a | 2586 | intel_enable_pch_pll(dev_priv, pipe); |
8db9d77b | 2587 | |
c98e9dcf | 2588 | if (HAS_PCH_CPT(dev)) { |
4b645f14 JB |
2589 | transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL : |
2590 | TRANSC_DPLLB_SEL; | |
2591 | ||
c98e9dcf JB |
2592 | /* Be sure PCH DPLL SEL is set */ |
2593 | temp = I915_READ(PCH_DPLL_SEL); | |
d64311ab JB |
2594 | if (pipe == 0) { |
2595 | temp &= ~(TRANSA_DPLLB_SEL); | |
c98e9dcf | 2596 | temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); |
d64311ab JB |
2597 | } else if (pipe == 1) { |
2598 | temp &= ~(TRANSB_DPLLB_SEL); | |
c98e9dcf | 2599 | temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
d64311ab JB |
2600 | } else if (pipe == 2) { |
2601 | temp &= ~(TRANSC_DPLLB_SEL); | |
4b645f14 | 2602 | temp |= (TRANSC_DPLL_ENABLE | transc_sel); |
d64311ab | 2603 | } |
c98e9dcf | 2604 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 2605 | } |
5eddb70b | 2606 | |
d9b6cb56 JB |
2607 | /* set transcoder timing, panel must allow it */ |
2608 | assert_panel_unlocked(dev_priv, pipe); | |
5eddb70b CW |
2609 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
2610 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); | |
2611 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); | |
8db9d77b | 2612 | |
5eddb70b CW |
2613 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
2614 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); | |
2615 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); | |
0529a0d9 | 2616 | I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); |
8db9d77b | 2617 | |
5e84e1a4 ZW |
2618 | intel_fdi_normal_train(crtc); |
2619 | ||
c98e9dcf JB |
2620 | /* For PCH DP, enable TRANS_DP_CTL */ |
2621 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
2622 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
2623 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
9325c9f0 | 2624 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; |
5eddb70b CW |
2625 | reg = TRANS_DP_CTL(pipe); |
2626 | temp = I915_READ(reg); | |
2627 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
2628 | TRANS_DP_SYNC_MASK | |
2629 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
2630 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
2631 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 2632 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
2633 | |
2634 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 2635 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 2636 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 2637 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
2638 | |
2639 | switch (intel_trans_dp_port_sel(crtc)) { | |
2640 | case PCH_DP_B: | |
5eddb70b | 2641 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
2642 | break; |
2643 | case PCH_DP_C: | |
5eddb70b | 2644 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
2645 | break; |
2646 | case PCH_DP_D: | |
5eddb70b | 2647 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
2648 | break; |
2649 | default: | |
2650 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); | |
5eddb70b | 2651 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 2652 | break; |
32f9d658 | 2653 | } |
2c07245f | 2654 | |
5eddb70b | 2655 | I915_WRITE(reg, temp); |
6be4a607 | 2656 | } |
b52eb4dc | 2657 | |
040484af | 2658 | intel_enable_transcoder(dev_priv, pipe); |
f67a559d JB |
2659 | } |
2660 | ||
d4270e57 JB |
2661 | void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) |
2662 | { | |
2663 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2664 | int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe); | |
2665 | u32 temp; | |
2666 | ||
2667 | temp = I915_READ(dslreg); | |
2668 | udelay(500); | |
2669 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
2670 | /* Without this, mode sets may fail silently on FDI */ | |
2671 | I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS); | |
2672 | udelay(250); | |
2673 | I915_WRITE(tc2reg, 0); | |
2674 | if (wait_for(I915_READ(dslreg) != temp, 5)) | |
2675 | DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); | |
2676 | } | |
2677 | } | |
2678 | ||
f67a559d JB |
2679 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
2680 | { | |
2681 | struct drm_device *dev = crtc->dev; | |
2682 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2683 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2684 | int pipe = intel_crtc->pipe; | |
2685 | int plane = intel_crtc->plane; | |
2686 | u32 temp; | |
2687 | bool is_pch_port; | |
2688 | ||
2689 | if (intel_crtc->active) | |
2690 | return; | |
2691 | ||
2692 | intel_crtc->active = true; | |
2693 | intel_update_watermarks(dev); | |
2694 | ||
2695 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
2696 | temp = I915_READ(PCH_LVDS); | |
2697 | if ((temp & LVDS_PORT_EN) == 0) | |
2698 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); | |
2699 | } | |
2700 | ||
2701 | is_pch_port = intel_crtc_driving_pch(crtc); | |
2702 | ||
2703 | if (is_pch_port) | |
357555c0 | 2704 | ironlake_fdi_pll_enable(crtc); |
f67a559d JB |
2705 | else |
2706 | ironlake_fdi_disable(crtc); | |
2707 | ||
2708 | /* Enable panel fitting for LVDS */ | |
2709 | if (dev_priv->pch_pf_size && | |
2710 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { | |
2711 | /* Force use of hard-coded filter coefficients | |
2712 | * as some pre-programmed values are broken, | |
2713 | * e.g. x201. | |
2714 | */ | |
9db4a9c7 JB |
2715 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
2716 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); | |
2717 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); | |
f67a559d JB |
2718 | } |
2719 | ||
9c54c0dd JB |
2720 | /* |
2721 | * On ILK+ LUT must be loaded before the pipe is running but with | |
2722 | * clocks enabled | |
2723 | */ | |
2724 | intel_crtc_load_lut(crtc); | |
2725 | ||
f67a559d JB |
2726 | intel_enable_pipe(dev_priv, pipe, is_pch_port); |
2727 | intel_enable_plane(dev_priv, plane, pipe); | |
2728 | ||
2729 | if (is_pch_port) | |
2730 | ironlake_pch_enable(crtc); | |
c98e9dcf | 2731 | |
d1ebd816 | 2732 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 2733 | intel_update_fbc(dev); |
d1ebd816 BW |
2734 | mutex_unlock(&dev->struct_mutex); |
2735 | ||
6b383a7f | 2736 | intel_crtc_update_cursor(crtc, true); |
6be4a607 JB |
2737 | } |
2738 | ||
2739 | static void ironlake_crtc_disable(struct drm_crtc *crtc) | |
2740 | { | |
2741 | struct drm_device *dev = crtc->dev; | |
2742 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2743 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2744 | int pipe = intel_crtc->pipe; | |
2745 | int plane = intel_crtc->plane; | |
5eddb70b | 2746 | u32 reg, temp; |
b52eb4dc | 2747 | |
f7abfe8b CW |
2748 | if (!intel_crtc->active) |
2749 | return; | |
2750 | ||
e6c3a2a6 | 2751 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 2752 | drm_vblank_off(dev, pipe); |
6b383a7f | 2753 | intel_crtc_update_cursor(crtc, false); |
5eddb70b | 2754 | |
b24e7179 | 2755 | intel_disable_plane(dev_priv, plane, pipe); |
913d8d11 | 2756 | |
973d04f9 CW |
2757 | if (dev_priv->cfb_plane == plane) |
2758 | intel_disable_fbc(dev); | |
2c07245f | 2759 | |
b24e7179 | 2760 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 2761 | |
6be4a607 | 2762 | /* Disable PF */ |
9db4a9c7 JB |
2763 | I915_WRITE(PF_CTL(pipe), 0); |
2764 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
2c07245f | 2765 | |
0fc932b8 | 2766 | ironlake_fdi_disable(crtc); |
2c07245f | 2767 | |
47a05eca JB |
2768 | /* This is a horrible layering violation; we should be doing this in |
2769 | * the connector/encoder ->prepare instead, but we don't always have | |
2770 | * enough information there about the config to know whether it will | |
2771 | * actually be necessary or just cause undesired flicker. | |
2772 | */ | |
2773 | intel_disable_pch_ports(dev_priv, pipe); | |
249c0e64 | 2774 | |
040484af | 2775 | intel_disable_transcoder(dev_priv, pipe); |
913d8d11 | 2776 | |
6be4a607 JB |
2777 | if (HAS_PCH_CPT(dev)) { |
2778 | /* disable TRANS_DP_CTL */ | |
5eddb70b CW |
2779 | reg = TRANS_DP_CTL(pipe); |
2780 | temp = I915_READ(reg); | |
2781 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
cb3543c6 | 2782 | temp |= TRANS_DP_PORT_SEL_NONE; |
5eddb70b | 2783 | I915_WRITE(reg, temp); |
6be4a607 JB |
2784 | |
2785 | /* disable DPLL_SEL */ | |
2786 | temp = I915_READ(PCH_DPLL_SEL); | |
9db4a9c7 JB |
2787 | switch (pipe) { |
2788 | case 0: | |
d64311ab | 2789 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
9db4a9c7 JB |
2790 | break; |
2791 | case 1: | |
6be4a607 | 2792 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
9db4a9c7 JB |
2793 | break; |
2794 | case 2: | |
4b645f14 | 2795 | /* C shares PLL A or B */ |
d64311ab | 2796 | temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); |
9db4a9c7 JB |
2797 | break; |
2798 | default: | |
2799 | BUG(); /* wtf */ | |
2800 | } | |
6be4a607 | 2801 | I915_WRITE(PCH_DPLL_SEL, temp); |
6be4a607 | 2802 | } |
e3421a18 | 2803 | |
6be4a607 | 2804 | /* disable PCH DPLL */ |
4b645f14 JB |
2805 | if (!intel_crtc->no_pll) |
2806 | intel_disable_pch_pll(dev_priv, pipe); | |
8db9d77b | 2807 | |
6be4a607 | 2808 | /* Switch from PCDclk to Rawclk */ |
5eddb70b CW |
2809 | reg = FDI_RX_CTL(pipe); |
2810 | temp = I915_READ(reg); | |
2811 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
8db9d77b | 2812 | |
6be4a607 | 2813 | /* Disable CPU FDI TX PLL */ |
5eddb70b CW |
2814 | reg = FDI_TX_CTL(pipe); |
2815 | temp = I915_READ(reg); | |
2816 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2817 | ||
2818 | POSTING_READ(reg); | |
6be4a607 | 2819 | udelay(100); |
8db9d77b | 2820 | |
5eddb70b CW |
2821 | reg = FDI_RX_CTL(pipe); |
2822 | temp = I915_READ(reg); | |
2823 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2c07245f | 2824 | |
6be4a607 | 2825 | /* Wait for the clocks to turn off. */ |
5eddb70b | 2826 | POSTING_READ(reg); |
6be4a607 | 2827 | udelay(100); |
6b383a7f | 2828 | |
f7abfe8b | 2829 | intel_crtc->active = false; |
6b383a7f | 2830 | intel_update_watermarks(dev); |
d1ebd816 BW |
2831 | |
2832 | mutex_lock(&dev->struct_mutex); | |
6b383a7f CW |
2833 | intel_update_fbc(dev); |
2834 | intel_clear_scanline_wait(dev); | |
d1ebd816 | 2835 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 2836 | } |
1b3c7a47 | 2837 | |
6be4a607 JB |
2838 | static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) |
2839 | { | |
2840 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2841 | int pipe = intel_crtc->pipe; | |
2842 | int plane = intel_crtc->plane; | |
8db9d77b | 2843 | |
6be4a607 JB |
2844 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
2845 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
2846 | */ | |
2847 | switch (mode) { | |
2848 | case DRM_MODE_DPMS_ON: | |
2849 | case DRM_MODE_DPMS_STANDBY: | |
2850 | case DRM_MODE_DPMS_SUSPEND: | |
2851 | DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); | |
2852 | ironlake_crtc_enable(crtc); | |
2853 | break; | |
1b3c7a47 | 2854 | |
6be4a607 JB |
2855 | case DRM_MODE_DPMS_OFF: |
2856 | DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); | |
2857 | ironlake_crtc_disable(crtc); | |
2c07245f ZW |
2858 | break; |
2859 | } | |
2860 | } | |
2861 | ||
02e792fb DV |
2862 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
2863 | { | |
02e792fb | 2864 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 2865 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 2866 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 2867 | |
23f09ce3 | 2868 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
2869 | dev_priv->mm.interruptible = false; |
2870 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
2871 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 2872 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 2873 | } |
02e792fb | 2874 | |
5dcdbcb0 CW |
2875 | /* Let userspace switch the overlay on again. In most cases userspace |
2876 | * has to recompute where to put it anyway. | |
2877 | */ | |
02e792fb DV |
2878 | } |
2879 | ||
0b8765c6 | 2880 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
2881 | { |
2882 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
2883 | struct drm_i915_private *dev_priv = dev->dev_private; |
2884 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2885 | int pipe = intel_crtc->pipe; | |
80824003 | 2886 | int plane = intel_crtc->plane; |
79e53945 | 2887 | |
f7abfe8b CW |
2888 | if (intel_crtc->active) |
2889 | return; | |
2890 | ||
2891 | intel_crtc->active = true; | |
6b383a7f CW |
2892 | intel_update_watermarks(dev); |
2893 | ||
63d7bbe9 | 2894 | intel_enable_pll(dev_priv, pipe); |
040484af | 2895 | intel_enable_pipe(dev_priv, pipe, false); |
b24e7179 | 2896 | intel_enable_plane(dev_priv, plane, pipe); |
79e53945 | 2897 | |
0b8765c6 | 2898 | intel_crtc_load_lut(crtc); |
bed4a673 | 2899 | intel_update_fbc(dev); |
79e53945 | 2900 | |
0b8765c6 JB |
2901 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
2902 | intel_crtc_dpms_overlay(intel_crtc, true); | |
6b383a7f | 2903 | intel_crtc_update_cursor(crtc, true); |
0b8765c6 | 2904 | } |
79e53945 | 2905 | |
0b8765c6 JB |
2906 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
2907 | { | |
2908 | struct drm_device *dev = crtc->dev; | |
2909 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2910 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2911 | int pipe = intel_crtc->pipe; | |
2912 | int plane = intel_crtc->plane; | |
b690e96c | 2913 | |
f7abfe8b CW |
2914 | if (!intel_crtc->active) |
2915 | return; | |
2916 | ||
0b8765c6 | 2917 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
2918 | intel_crtc_wait_for_pending_flips(crtc); |
2919 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 2920 | intel_crtc_dpms_overlay(intel_crtc, false); |
6b383a7f | 2921 | intel_crtc_update_cursor(crtc, false); |
0b8765c6 | 2922 | |
973d04f9 CW |
2923 | if (dev_priv->cfb_plane == plane) |
2924 | intel_disable_fbc(dev); | |
79e53945 | 2925 | |
b24e7179 | 2926 | intel_disable_plane(dev_priv, plane, pipe); |
b24e7179 | 2927 | intel_disable_pipe(dev_priv, pipe); |
63d7bbe9 | 2928 | intel_disable_pll(dev_priv, pipe); |
0b8765c6 | 2929 | |
f7abfe8b | 2930 | intel_crtc->active = false; |
6b383a7f CW |
2931 | intel_update_fbc(dev); |
2932 | intel_update_watermarks(dev); | |
2933 | intel_clear_scanline_wait(dev); | |
0b8765c6 JB |
2934 | } |
2935 | ||
2936 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) | |
2937 | { | |
2938 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
2939 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
2940 | */ | |
2941 | switch (mode) { | |
2942 | case DRM_MODE_DPMS_ON: | |
2943 | case DRM_MODE_DPMS_STANDBY: | |
2944 | case DRM_MODE_DPMS_SUSPEND: | |
2945 | i9xx_crtc_enable(crtc); | |
2946 | break; | |
2947 | case DRM_MODE_DPMS_OFF: | |
2948 | i9xx_crtc_disable(crtc); | |
79e53945 JB |
2949 | break; |
2950 | } | |
2c07245f ZW |
2951 | } |
2952 | ||
2953 | /** | |
2954 | * Sets the power management mode of the pipe and plane. | |
2c07245f ZW |
2955 | */ |
2956 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
2957 | { | |
2958 | struct drm_device *dev = crtc->dev; | |
e70236a8 | 2959 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f ZW |
2960 | struct drm_i915_master_private *master_priv; |
2961 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2962 | int pipe = intel_crtc->pipe; | |
2963 | bool enabled; | |
2964 | ||
032d2a0d CW |
2965 | if (intel_crtc->dpms_mode == mode) |
2966 | return; | |
2967 | ||
65655d4a | 2968 | intel_crtc->dpms_mode = mode; |
debcaddc | 2969 | |
e70236a8 | 2970 | dev_priv->display.dpms(crtc, mode); |
79e53945 JB |
2971 | |
2972 | if (!dev->primary->master) | |
2973 | return; | |
2974 | ||
2975 | master_priv = dev->primary->master->driver_priv; | |
2976 | if (!master_priv->sarea_priv) | |
2977 | return; | |
2978 | ||
2979 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; | |
2980 | ||
2981 | switch (pipe) { | |
2982 | case 0: | |
2983 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
2984 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
2985 | break; | |
2986 | case 1: | |
2987 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
2988 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
2989 | break; | |
2990 | default: | |
9db4a9c7 | 2991 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
2992 | break; |
2993 | } | |
79e53945 JB |
2994 | } |
2995 | ||
cdd59983 CW |
2996 | static void intel_crtc_disable(struct drm_crtc *crtc) |
2997 | { | |
2998 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
2999 | struct drm_device *dev = crtc->dev; | |
3000 | ||
3001 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
931872fc CW |
3002 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
3003 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); | |
cdd59983 CW |
3004 | |
3005 | if (crtc->fb) { | |
3006 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 3007 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 CW |
3008 | mutex_unlock(&dev->struct_mutex); |
3009 | } | |
3010 | } | |
3011 | ||
7e7d76c3 JB |
3012 | /* Prepare for a mode set. |
3013 | * | |
3014 | * Note we could be a lot smarter here. We need to figure out which outputs | |
3015 | * will be enabled, which disabled (in short, how the config will changes) | |
3016 | * and perform the minimum necessary steps to accomplish that, e.g. updating | |
3017 | * watermarks, FBC configuration, making sure PLLs are programmed correctly, | |
3018 | * panel fitting is in the proper state, etc. | |
3019 | */ | |
3020 | static void i9xx_crtc_prepare(struct drm_crtc *crtc) | |
79e53945 | 3021 | { |
7e7d76c3 | 3022 | i9xx_crtc_disable(crtc); |
79e53945 JB |
3023 | } |
3024 | ||
7e7d76c3 | 3025 | static void i9xx_crtc_commit(struct drm_crtc *crtc) |
79e53945 | 3026 | { |
7e7d76c3 | 3027 | i9xx_crtc_enable(crtc); |
7e7d76c3 JB |
3028 | } |
3029 | ||
3030 | static void ironlake_crtc_prepare(struct drm_crtc *crtc) | |
3031 | { | |
7e7d76c3 | 3032 | ironlake_crtc_disable(crtc); |
7e7d76c3 JB |
3033 | } |
3034 | ||
3035 | static void ironlake_crtc_commit(struct drm_crtc *crtc) | |
3036 | { | |
7e7d76c3 | 3037 | ironlake_crtc_enable(crtc); |
79e53945 JB |
3038 | } |
3039 | ||
0206e353 | 3040 | void intel_encoder_prepare(struct drm_encoder *encoder) |
79e53945 JB |
3041 | { |
3042 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
3043 | /* lvds has its own version of prepare see intel_lvds_prepare */ | |
3044 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | |
3045 | } | |
3046 | ||
0206e353 | 3047 | void intel_encoder_commit(struct drm_encoder *encoder) |
79e53945 JB |
3048 | { |
3049 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
d4270e57 JB |
3050 | struct drm_device *dev = encoder->dev; |
3051 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
3052 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
3053 | ||
79e53945 JB |
3054 | /* lvds has its own version of commit see intel_lvds_commit */ |
3055 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
d4270e57 JB |
3056 | |
3057 | if (HAS_PCH_CPT(dev)) | |
3058 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); | |
79e53945 JB |
3059 | } |
3060 | ||
ea5b213a CW |
3061 | void intel_encoder_destroy(struct drm_encoder *encoder) |
3062 | { | |
4ef69c7a | 3063 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 3064 | |
ea5b213a CW |
3065 | drm_encoder_cleanup(encoder); |
3066 | kfree(intel_encoder); | |
3067 | } | |
3068 | ||
79e53945 JB |
3069 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
3070 | struct drm_display_mode *mode, | |
3071 | struct drm_display_mode *adjusted_mode) | |
3072 | { | |
2c07245f | 3073 | struct drm_device *dev = crtc->dev; |
89749350 | 3074 | |
bad720ff | 3075 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 3076 | /* FDI link clock is fixed at 2.7G */ |
2377b741 JB |
3077 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
3078 | return false; | |
2c07245f | 3079 | } |
89749350 | 3080 | |
ca9bfa7e DV |
3081 | /* All interlaced capable intel hw wants timings in frames. */ |
3082 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
89749350 | 3083 | |
79e53945 JB |
3084 | return true; |
3085 | } | |
3086 | ||
25eb05fc JB |
3087 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
3088 | { | |
3089 | return 400000; /* FIXME */ | |
3090 | } | |
3091 | ||
e70236a8 JB |
3092 | static int i945_get_display_clock_speed(struct drm_device *dev) |
3093 | { | |
3094 | return 400000; | |
3095 | } | |
79e53945 | 3096 | |
e70236a8 | 3097 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 3098 | { |
e70236a8 JB |
3099 | return 333000; |
3100 | } | |
79e53945 | 3101 | |
e70236a8 JB |
3102 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
3103 | { | |
3104 | return 200000; | |
3105 | } | |
79e53945 | 3106 | |
e70236a8 JB |
3107 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
3108 | { | |
3109 | u16 gcfgc = 0; | |
79e53945 | 3110 | |
e70236a8 JB |
3111 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
3112 | ||
3113 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
3114 | return 133000; | |
3115 | else { | |
3116 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
3117 | case GC_DISPLAY_CLOCK_333_MHZ: | |
3118 | return 333000; | |
3119 | default: | |
3120 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
3121 | return 190000; | |
79e53945 | 3122 | } |
e70236a8 JB |
3123 | } |
3124 | } | |
3125 | ||
3126 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
3127 | { | |
3128 | return 266000; | |
3129 | } | |
3130 | ||
3131 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
3132 | { | |
3133 | u16 hpllcc = 0; | |
3134 | /* Assume that the hardware is in the high speed state. This | |
3135 | * should be the default. | |
3136 | */ | |
3137 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
3138 | case GC_CLOCK_133_200: | |
3139 | case GC_CLOCK_100_200: | |
3140 | return 200000; | |
3141 | case GC_CLOCK_166_250: | |
3142 | return 250000; | |
3143 | case GC_CLOCK_100_133: | |
79e53945 | 3144 | return 133000; |
e70236a8 | 3145 | } |
79e53945 | 3146 | |
e70236a8 JB |
3147 | /* Shouldn't happen */ |
3148 | return 0; | |
3149 | } | |
79e53945 | 3150 | |
e70236a8 JB |
3151 | static int i830_get_display_clock_speed(struct drm_device *dev) |
3152 | { | |
3153 | return 133000; | |
79e53945 JB |
3154 | } |
3155 | ||
2c07245f ZW |
3156 | struct fdi_m_n { |
3157 | u32 tu; | |
3158 | u32 gmch_m; | |
3159 | u32 gmch_n; | |
3160 | u32 link_m; | |
3161 | u32 link_n; | |
3162 | }; | |
3163 | ||
3164 | static void | |
3165 | fdi_reduce_ratio(u32 *num, u32 *den) | |
3166 | { | |
3167 | while (*num > 0xffffff || *den > 0xffffff) { | |
3168 | *num >>= 1; | |
3169 | *den >>= 1; | |
3170 | } | |
3171 | } | |
3172 | ||
2c07245f | 3173 | static void |
f2b115e6 AJ |
3174 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
3175 | int link_clock, struct fdi_m_n *m_n) | |
2c07245f | 3176 | { |
2c07245f ZW |
3177 | m_n->tu = 64; /* default size */ |
3178 | ||
22ed1113 CW |
3179 | /* BUG_ON(pixel_clock > INT_MAX / 36); */ |
3180 | m_n->gmch_m = bits_per_pixel * pixel_clock; | |
3181 | m_n->gmch_n = link_clock * nlanes * 8; | |
2c07245f ZW |
3182 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
3183 | ||
22ed1113 CW |
3184 | m_n->link_m = pixel_clock; |
3185 | m_n->link_n = link_clock; | |
2c07245f ZW |
3186 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
3187 | } | |
3188 | ||
a7615030 CW |
3189 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
3190 | { | |
72bbe58c KP |
3191 | if (i915_panel_use_ssc >= 0) |
3192 | return i915_panel_use_ssc != 0; | |
3193 | return dev_priv->lvds_use_ssc | |
435793df | 3194 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
3195 | } |
3196 | ||
5a354204 JB |
3197 | /** |
3198 | * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send | |
3199 | * @crtc: CRTC structure | |
3b5c78a3 | 3200 | * @mode: requested mode |
5a354204 JB |
3201 | * |
3202 | * A pipe may be connected to one or more outputs. Based on the depth of the | |
3203 | * attached framebuffer, choose a good color depth to use on the pipe. | |
3204 | * | |
3205 | * If possible, match the pipe depth to the fb depth. In some cases, this | |
3206 | * isn't ideal, because the connected output supports a lesser or restricted | |
3207 | * set of depths. Resolve that here: | |
3208 | * LVDS typically supports only 6bpc, so clamp down in that case | |
3209 | * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc | |
3210 | * Displays may support a restricted set as well, check EDID and clamp as | |
3211 | * appropriate. | |
3b5c78a3 | 3212 | * DP may want to dither down to 6bpc to fit larger modes |
5a354204 JB |
3213 | * |
3214 | * RETURNS: | |
3215 | * Dithering requirement (i.e. false if display bpc and pipe bpc match, | |
3216 | * true if they don't match). | |
3217 | */ | |
3218 | static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, | |
3b5c78a3 AJ |
3219 | unsigned int *pipe_bpp, |
3220 | struct drm_display_mode *mode) | |
5a354204 JB |
3221 | { |
3222 | struct drm_device *dev = crtc->dev; | |
3223 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3224 | struct drm_encoder *encoder; | |
3225 | struct drm_connector *connector; | |
3226 | unsigned int display_bpc = UINT_MAX, bpc; | |
3227 | ||
3228 | /* Walk the encoders & connectors on this crtc, get min bpc */ | |
3229 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
3230 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
3231 | ||
3232 | if (encoder->crtc != crtc) | |
3233 | continue; | |
3234 | ||
3235 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) { | |
3236 | unsigned int lvds_bpc; | |
3237 | ||
3238 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == | |
3239 | LVDS_A3_POWER_UP) | |
3240 | lvds_bpc = 8; | |
3241 | else | |
3242 | lvds_bpc = 6; | |
3243 | ||
3244 | if (lvds_bpc < display_bpc) { | |
82820490 | 3245 | DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); |
5a354204 JB |
3246 | display_bpc = lvds_bpc; |
3247 | } | |
3248 | continue; | |
3249 | } | |
3250 | ||
3251 | if (intel_encoder->type == INTEL_OUTPUT_EDP) { | |
3252 | /* Use VBT settings if we have an eDP panel */ | |
3253 | unsigned int edp_bpc = dev_priv->edp.bpp / 3; | |
3254 | ||
3255 | if (edp_bpc < display_bpc) { | |
82820490 | 3256 | DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); |
5a354204 JB |
3257 | display_bpc = edp_bpc; |
3258 | } | |
3259 | continue; | |
3260 | } | |
3261 | ||
3262 | /* Not one of the known troublemakers, check the EDID */ | |
3263 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
3264 | head) { | |
3265 | if (connector->encoder != encoder) | |
3266 | continue; | |
3267 | ||
62ac41a6 JB |
3268 | /* Don't use an invalid EDID bpc value */ |
3269 | if (connector->display_info.bpc && | |
3270 | connector->display_info.bpc < display_bpc) { | |
82820490 | 3271 | DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); |
5a354204 JB |
3272 | display_bpc = connector->display_info.bpc; |
3273 | } | |
3274 | } | |
3275 | ||
3276 | /* | |
3277 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
3278 | * through, clamp it down. (Note: >12bpc will be caught below.) | |
3279 | */ | |
3280 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { | |
3281 | if (display_bpc > 8 && display_bpc < 12) { | |
82820490 | 3282 | DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); |
5a354204 JB |
3283 | display_bpc = 12; |
3284 | } else { | |
82820490 | 3285 | DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); |
5a354204 JB |
3286 | display_bpc = 8; |
3287 | } | |
3288 | } | |
3289 | } | |
3290 | ||
3b5c78a3 AJ |
3291 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
3292 | DRM_DEBUG_KMS("Dithering DP to 6bpc\n"); | |
3293 | display_bpc = 6; | |
3294 | } | |
3295 | ||
5a354204 JB |
3296 | /* |
3297 | * We could just drive the pipe at the highest bpc all the time and | |
3298 | * enable dithering as needed, but that costs bandwidth. So choose | |
3299 | * the minimum value that expresses the full color range of the fb but | |
3300 | * also stays within the max display bpc discovered above. | |
3301 | */ | |
3302 | ||
3303 | switch (crtc->fb->depth) { | |
3304 | case 8: | |
3305 | bpc = 8; /* since we go through a colormap */ | |
3306 | break; | |
3307 | case 15: | |
3308 | case 16: | |
3309 | bpc = 6; /* min is 18bpp */ | |
3310 | break; | |
3311 | case 24: | |
578393cd | 3312 | bpc = 8; |
5a354204 JB |
3313 | break; |
3314 | case 30: | |
578393cd | 3315 | bpc = 10; |
5a354204 JB |
3316 | break; |
3317 | case 48: | |
578393cd | 3318 | bpc = 12; |
5a354204 JB |
3319 | break; |
3320 | default: | |
3321 | DRM_DEBUG("unsupported depth, assuming 24 bits\n"); | |
3322 | bpc = min((unsigned int)8, display_bpc); | |
3323 | break; | |
3324 | } | |
3325 | ||
578393cd KP |
3326 | display_bpc = min(display_bpc, bpc); |
3327 | ||
82820490 AJ |
3328 | DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n", |
3329 | bpc, display_bpc); | |
5a354204 | 3330 | |
578393cd | 3331 | *pipe_bpp = display_bpc * 3; |
5a354204 JB |
3332 | |
3333 | return display_bpc != bpc; | |
3334 | } | |
3335 | ||
c65d77d8 JB |
3336 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
3337 | { | |
3338 | struct drm_device *dev = crtc->dev; | |
3339 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3340 | int refclk; | |
3341 | ||
3342 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
3343 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
3344 | refclk = dev_priv->lvds_ssc_freq * 1000; | |
3345 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
3346 | refclk / 1000); | |
3347 | } else if (!IS_GEN2(dev)) { | |
3348 | refclk = 96000; | |
3349 | } else { | |
3350 | refclk = 48000; | |
3351 | } | |
3352 | ||
3353 | return refclk; | |
3354 | } | |
3355 | ||
3356 | static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, | |
3357 | intel_clock_t *clock) | |
3358 | { | |
3359 | /* SDVO TV has fixed PLL values depend on its clock range, | |
3360 | this mirrors vbios setting. */ | |
3361 | if (adjusted_mode->clock >= 100000 | |
3362 | && adjusted_mode->clock < 140500) { | |
3363 | clock->p1 = 2; | |
3364 | clock->p2 = 10; | |
3365 | clock->n = 3; | |
3366 | clock->m1 = 16; | |
3367 | clock->m2 = 8; | |
3368 | } else if (adjusted_mode->clock >= 140500 | |
3369 | && adjusted_mode->clock <= 200000) { | |
3370 | clock->p1 = 1; | |
3371 | clock->p2 = 10; | |
3372 | clock->n = 6; | |
3373 | clock->m1 = 12; | |
3374 | clock->m2 = 8; | |
3375 | } | |
3376 | } | |
3377 | ||
a7516a05 JB |
3378 | static void i9xx_update_pll_dividers(struct drm_crtc *crtc, |
3379 | intel_clock_t *clock, | |
3380 | intel_clock_t *reduced_clock) | |
3381 | { | |
3382 | struct drm_device *dev = crtc->dev; | |
3383 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3384 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3385 | int pipe = intel_crtc->pipe; | |
3386 | u32 fp, fp2 = 0; | |
3387 | ||
3388 | if (IS_PINEVIEW(dev)) { | |
3389 | fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; | |
3390 | if (reduced_clock) | |
3391 | fp2 = (1 << reduced_clock->n) << 16 | | |
3392 | reduced_clock->m1 << 8 | reduced_clock->m2; | |
3393 | } else { | |
3394 | fp = clock->n << 16 | clock->m1 << 8 | clock->m2; | |
3395 | if (reduced_clock) | |
3396 | fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | | |
3397 | reduced_clock->m2; | |
3398 | } | |
3399 | ||
3400 | I915_WRITE(FP0(pipe), fp); | |
3401 | ||
3402 | intel_crtc->lowfreq_avail = false; | |
3403 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
3404 | reduced_clock && i915_powersave) { | |
3405 | I915_WRITE(FP1(pipe), fp2); | |
3406 | intel_crtc->lowfreq_avail = true; | |
3407 | } else { | |
3408 | I915_WRITE(FP1(pipe), fp); | |
3409 | } | |
3410 | } | |
3411 | ||
93e537a1 DV |
3412 | static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock, |
3413 | struct drm_display_mode *adjusted_mode) | |
3414 | { | |
3415 | struct drm_device *dev = crtc->dev; | |
3416 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3417 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3418 | int pipe = intel_crtc->pipe; | |
284d5df5 | 3419 | u32 temp; |
93e537a1 DV |
3420 | |
3421 | temp = I915_READ(LVDS); | |
3422 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
3423 | if (pipe == 1) { | |
3424 | temp |= LVDS_PIPEB_SELECT; | |
3425 | } else { | |
3426 | temp &= ~LVDS_PIPEB_SELECT; | |
3427 | } | |
3428 | /* set the corresponsding LVDS_BORDER bit */ | |
3429 | temp |= dev_priv->lvds_border_bits; | |
3430 | /* Set the B0-B3 data pairs corresponding to whether we're going to | |
3431 | * set the DPLLs for dual-channel mode or not. | |
3432 | */ | |
3433 | if (clock->p2 == 7) | |
3434 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
3435 | else | |
3436 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
3437 | ||
3438 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
3439 | * appropriately here, but we need to look more thoroughly into how | |
3440 | * panels behave in the two modes. | |
3441 | */ | |
3442 | /* set the dithering flag on LVDS as needed */ | |
3443 | if (INTEL_INFO(dev)->gen >= 4) { | |
3444 | if (dev_priv->lvds_dither) | |
3445 | temp |= LVDS_ENABLE_DITHER; | |
3446 | else | |
3447 | temp &= ~LVDS_ENABLE_DITHER; | |
3448 | } | |
284d5df5 | 3449 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); |
93e537a1 | 3450 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
284d5df5 | 3451 | temp |= LVDS_HSYNC_POLARITY; |
93e537a1 | 3452 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
284d5df5 | 3453 | temp |= LVDS_VSYNC_POLARITY; |
93e537a1 DV |
3454 | I915_WRITE(LVDS, temp); |
3455 | } | |
3456 | ||
eb1cbe48 DV |
3457 | static void i9xx_update_pll(struct drm_crtc *crtc, |
3458 | struct drm_display_mode *mode, | |
3459 | struct drm_display_mode *adjusted_mode, | |
3460 | intel_clock_t *clock, intel_clock_t *reduced_clock, | |
3461 | int num_connectors) | |
3462 | { | |
3463 | struct drm_device *dev = crtc->dev; | |
3464 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3465 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3466 | int pipe = intel_crtc->pipe; | |
3467 | u32 dpll; | |
3468 | bool is_sdvo; | |
3469 | ||
3470 | is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) || | |
3471 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); | |
3472 | ||
3473 | dpll = DPLL_VGA_MODE_DIS; | |
3474 | ||
3475 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
3476 | dpll |= DPLLB_MODE_LVDS; | |
3477 | else | |
3478 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
3479 | if (is_sdvo) { | |
3480 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); | |
3481 | if (pixel_multiplier > 1) { | |
3482 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
3483 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
3484 | } | |
3485 | dpll |= DPLL_DVO_HIGH_SPEED; | |
3486 | } | |
3487 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
3488 | dpll |= DPLL_DVO_HIGH_SPEED; | |
3489 | ||
3490 | /* compute bitmask from p1 value */ | |
3491 | if (IS_PINEVIEW(dev)) | |
3492 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
3493 | else { | |
3494 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
3495 | if (IS_G4X(dev) && reduced_clock) | |
3496 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
3497 | } | |
3498 | switch (clock->p2) { | |
3499 | case 5: | |
3500 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
3501 | break; | |
3502 | case 7: | |
3503 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
3504 | break; | |
3505 | case 10: | |
3506 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
3507 | break; | |
3508 | case 14: | |
3509 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
3510 | break; | |
3511 | } | |
3512 | if (INTEL_INFO(dev)->gen >= 4) | |
3513 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
3514 | ||
3515 | if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
3516 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
3517 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
3518 | /* XXX: just matching BIOS for now */ | |
3519 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ | |
3520 | dpll |= 3; | |
3521 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
3522 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) | |
3523 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
3524 | else | |
3525 | dpll |= PLL_REF_INPUT_DREFCLK; | |
3526 | ||
3527 | dpll |= DPLL_VCO_ENABLE; | |
3528 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
3529 | POSTING_READ(DPLL(pipe)); | |
3530 | udelay(150); | |
3531 | ||
3532 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. | |
3533 | * This is an exception to the general rule that mode_set doesn't turn | |
3534 | * things on. | |
3535 | */ | |
3536 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
3537 | intel_update_lvds(crtc, clock, adjusted_mode); | |
3538 | ||
3539 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
3540 | intel_dp_set_m_n(crtc, mode, adjusted_mode); | |
3541 | ||
3542 | I915_WRITE(DPLL(pipe), dpll); | |
3543 | ||
3544 | /* Wait for the clocks to stabilize. */ | |
3545 | POSTING_READ(DPLL(pipe)); | |
3546 | udelay(150); | |
3547 | ||
3548 | if (INTEL_INFO(dev)->gen >= 4) { | |
3549 | u32 temp = 0; | |
3550 | if (is_sdvo) { | |
3551 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); | |
3552 | if (temp > 1) | |
3553 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
3554 | else | |
3555 | temp = 0; | |
3556 | } | |
3557 | I915_WRITE(DPLL_MD(pipe), temp); | |
3558 | } else { | |
3559 | /* The pixel multiplier can only be updated once the | |
3560 | * DPLL is enabled and the clocks are stable. | |
3561 | * | |
3562 | * So write it again. | |
3563 | */ | |
3564 | I915_WRITE(DPLL(pipe), dpll); | |
3565 | } | |
3566 | } | |
3567 | ||
3568 | static void i8xx_update_pll(struct drm_crtc *crtc, | |
3569 | struct drm_display_mode *adjusted_mode, | |
3570 | intel_clock_t *clock, | |
3571 | int num_connectors) | |
3572 | { | |
3573 | struct drm_device *dev = crtc->dev; | |
3574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3575 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3576 | int pipe = intel_crtc->pipe; | |
3577 | u32 dpll; | |
3578 | ||
3579 | dpll = DPLL_VGA_MODE_DIS; | |
3580 | ||
3581 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
3582 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
3583 | } else { | |
3584 | if (clock->p1 == 2) | |
3585 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
3586 | else | |
3587 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
3588 | if (clock->p2 == 4) | |
3589 | dpll |= PLL_P2_DIVIDE_BY_4; | |
3590 | } | |
3591 | ||
3592 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
3593 | /* XXX: just matching BIOS for now */ | |
3594 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ | |
3595 | dpll |= 3; | |
3596 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
3597 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) | |
3598 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
3599 | else | |
3600 | dpll |= PLL_REF_INPUT_DREFCLK; | |
3601 | ||
3602 | dpll |= DPLL_VCO_ENABLE; | |
3603 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
3604 | POSTING_READ(DPLL(pipe)); | |
3605 | udelay(150); | |
3606 | ||
3607 | I915_WRITE(DPLL(pipe), dpll); | |
3608 | ||
3609 | /* Wait for the clocks to stabilize. */ | |
3610 | POSTING_READ(DPLL(pipe)); | |
3611 | udelay(150); | |
3612 | ||
3613 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. | |
3614 | * This is an exception to the general rule that mode_set doesn't turn | |
3615 | * things on. | |
3616 | */ | |
3617 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
3618 | intel_update_lvds(crtc, clock, adjusted_mode); | |
3619 | ||
3620 | /* The pixel multiplier can only be updated once the | |
3621 | * DPLL is enabled and the clocks are stable. | |
3622 | * | |
3623 | * So write it again. | |
3624 | */ | |
3625 | I915_WRITE(DPLL(pipe), dpll); | |
3626 | } | |
3627 | ||
f564048e EA |
3628 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
3629 | struct drm_display_mode *mode, | |
3630 | struct drm_display_mode *adjusted_mode, | |
3631 | int x, int y, | |
3632 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
3633 | { |
3634 | struct drm_device *dev = crtc->dev; | |
3635 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3636 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3637 | int pipe = intel_crtc->pipe; | |
80824003 | 3638 | int plane = intel_crtc->plane; |
c751ce4f | 3639 | int refclk, num_connectors = 0; |
652c393a | 3640 | intel_clock_t clock, reduced_clock; |
eb1cbe48 DV |
3641 | u32 dspcntr, pipeconf, vsyncshift; |
3642 | bool ok, has_reduced_clock = false, is_sdvo = false; | |
3643 | bool is_lvds = false, is_tv = false, is_dp = false; | |
79e53945 | 3644 | struct drm_mode_config *mode_config = &dev->mode_config; |
5eddb70b | 3645 | struct intel_encoder *encoder; |
d4906093 | 3646 | const intel_limit_t *limit; |
5c3b82e2 | 3647 | int ret; |
79e53945 | 3648 | |
5eddb70b CW |
3649 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
3650 | if (encoder->base.crtc != crtc) | |
79e53945 JB |
3651 | continue; |
3652 | ||
5eddb70b | 3653 | switch (encoder->type) { |
79e53945 JB |
3654 | case INTEL_OUTPUT_LVDS: |
3655 | is_lvds = true; | |
3656 | break; | |
3657 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 3658 | case INTEL_OUTPUT_HDMI: |
79e53945 | 3659 | is_sdvo = true; |
5eddb70b | 3660 | if (encoder->needs_tv_clock) |
e2f0ba97 | 3661 | is_tv = true; |
79e53945 | 3662 | break; |
79e53945 JB |
3663 | case INTEL_OUTPUT_TVOUT: |
3664 | is_tv = true; | |
3665 | break; | |
a4fc5ed6 KP |
3666 | case INTEL_OUTPUT_DISPLAYPORT: |
3667 | is_dp = true; | |
3668 | break; | |
79e53945 | 3669 | } |
43565a06 | 3670 | |
c751ce4f | 3671 | num_connectors++; |
79e53945 JB |
3672 | } |
3673 | ||
c65d77d8 | 3674 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 3675 | |
d4906093 ML |
3676 | /* |
3677 | * Returns a set of divisors for the desired target clock with the given | |
3678 | * refclk, or FALSE. The returned values represent the clock equation: | |
3679 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
3680 | */ | |
1b894b59 | 3681 | limit = intel_limit(crtc, refclk); |
cec2f356 SP |
3682 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
3683 | &clock); | |
79e53945 JB |
3684 | if (!ok) { |
3685 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 3686 | return -EINVAL; |
79e53945 JB |
3687 | } |
3688 | ||
cda4b7d3 | 3689 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 3690 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 3691 | |
ddc9003c | 3692 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
3693 | /* |
3694 | * Ensure we match the reduced clock's P to the target clock. | |
3695 | * If the clocks don't match, we can't switch the display clock | |
3696 | * by using the FP0/FP1. In such case we will disable the LVDS | |
3697 | * downclock feature. | |
3698 | */ | |
ddc9003c | 3699 | has_reduced_clock = limit->find_pll(limit, crtc, |
5eddb70b CW |
3700 | dev_priv->lvds_downclock, |
3701 | refclk, | |
cec2f356 | 3702 | &clock, |
5eddb70b | 3703 | &reduced_clock); |
7026d4ac ZW |
3704 | } |
3705 | ||
c65d77d8 JB |
3706 | if (is_sdvo && is_tv) |
3707 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); | |
7026d4ac | 3708 | |
a7516a05 JB |
3709 | i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ? |
3710 | &reduced_clock : NULL); | |
79e53945 | 3711 | |
eb1cbe48 DV |
3712 | if (IS_GEN2(dev)) |
3713 | i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors); | |
79e53945 | 3714 | else |
eb1cbe48 DV |
3715 | i9xx_update_pll(crtc, mode, adjusted_mode, &clock, |
3716 | has_reduced_clock ? &reduced_clock : NULL, | |
3717 | num_connectors); | |
79e53945 JB |
3718 | |
3719 | /* setup pipeconf */ | |
5eddb70b | 3720 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
3721 | |
3722 | /* Set up the display plane register */ | |
3723 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
3724 | ||
929c77fb EA |
3725 | if (pipe == 0) |
3726 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
3727 | else | |
3728 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
79e53945 | 3729 | |
a6c45cf0 | 3730 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
79e53945 JB |
3731 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
3732 | * core speed. | |
3733 | * | |
3734 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
3735 | * pipe == 0 check? | |
3736 | */ | |
e70236a8 JB |
3737 | if (mode->clock > |
3738 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
5eddb70b | 3739 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
79e53945 | 3740 | else |
5eddb70b | 3741 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
79e53945 JB |
3742 | } |
3743 | ||
3b5c78a3 AJ |
3744 | /* default to 8bpc */ |
3745 | pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN); | |
3746 | if (is_dp) { | |
3747 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { | |
3748 | pipeconf |= PIPECONF_BPP_6 | | |
3749 | PIPECONF_DITHER_EN | | |
3750 | PIPECONF_DITHER_TYPE_SP; | |
3751 | } | |
3752 | } | |
3753 | ||
28c97730 | 3754 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
3755 | drm_mode_debug_printmodeline(mode); |
3756 | ||
a7516a05 JB |
3757 | if (HAS_PIPE_CXSR(dev)) { |
3758 | if (intel_crtc->lowfreq_avail) { | |
28c97730 | 3759 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
652c393a | 3760 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
a7516a05 | 3761 | } else { |
28c97730 | 3762 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
652c393a JB |
3763 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
3764 | } | |
3765 | } | |
3766 | ||
617cf884 | 3767 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
dbb02575 DV |
3768 | if (!IS_GEN2(dev) && |
3769 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
734b4157 KH |
3770 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
3771 | /* the chip adds 2 halflines automatically */ | |
734b4157 | 3772 | adjusted_mode->crtc_vtotal -= 1; |
734b4157 | 3773 | adjusted_mode->crtc_vblank_end -= 1; |
0529a0d9 DV |
3774 | vsyncshift = adjusted_mode->crtc_hsync_start |
3775 | - adjusted_mode->crtc_htotal/2; | |
3776 | } else { | |
617cf884 | 3777 | pipeconf |= PIPECONF_PROGRESSIVE; |
0529a0d9 DV |
3778 | vsyncshift = 0; |
3779 | } | |
3780 | ||
3781 | if (!IS_GEN3(dev)) | |
3782 | I915_WRITE(VSYNCSHIFT(pipe), vsyncshift); | |
734b4157 | 3783 | |
5eddb70b CW |
3784 | I915_WRITE(HTOTAL(pipe), |
3785 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 3786 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
3787 | I915_WRITE(HBLANK(pipe), |
3788 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 3789 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
3790 | I915_WRITE(HSYNC(pipe), |
3791 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 3792 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
3793 | |
3794 | I915_WRITE(VTOTAL(pipe), | |
3795 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 3796 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
3797 | I915_WRITE(VBLANK(pipe), |
3798 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 3799 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
3800 | I915_WRITE(VSYNC(pipe), |
3801 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 3802 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b CW |
3803 | |
3804 | /* pipesrc and dspsize control the size that is scaled from, | |
3805 | * which should always be the user's requested size. | |
79e53945 | 3806 | */ |
929c77fb EA |
3807 | I915_WRITE(DSPSIZE(plane), |
3808 | ((mode->vdisplay - 1) << 16) | | |
3809 | (mode->hdisplay - 1)); | |
3810 | I915_WRITE(DSPPOS(plane), 0); | |
5eddb70b CW |
3811 | I915_WRITE(PIPESRC(pipe), |
3812 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 3813 | |
f564048e EA |
3814 | I915_WRITE(PIPECONF(pipe), pipeconf); |
3815 | POSTING_READ(PIPECONF(pipe)); | |
929c77fb | 3816 | intel_enable_pipe(dev_priv, pipe, false); |
f564048e EA |
3817 | |
3818 | intel_wait_for_vblank(dev, pipe); | |
3819 | ||
f564048e EA |
3820 | I915_WRITE(DSPCNTR(plane), dspcntr); |
3821 | POSTING_READ(DSPCNTR(plane)); | |
284d9529 | 3822 | intel_enable_plane(dev_priv, plane, pipe); |
f564048e EA |
3823 | |
3824 | ret = intel_pipe_set_base(crtc, x, y, old_fb); | |
3825 | ||
3826 | intel_update_watermarks(dev); | |
3827 | ||
f564048e EA |
3828 | return ret; |
3829 | } | |
3830 | ||
9fb526db KP |
3831 | /* |
3832 | * Initialize reference clocks when the driver loads | |
3833 | */ | |
3834 | void ironlake_init_pch_refclk(struct drm_device *dev) | |
13d83a67 JB |
3835 | { |
3836 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3837 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 3838 | struct intel_encoder *encoder; |
13d83a67 JB |
3839 | u32 temp; |
3840 | bool has_lvds = false; | |
199e5d79 KP |
3841 | bool has_cpu_edp = false; |
3842 | bool has_pch_edp = false; | |
3843 | bool has_panel = false; | |
99eb6a01 KP |
3844 | bool has_ck505 = false; |
3845 | bool can_ssc = false; | |
13d83a67 JB |
3846 | |
3847 | /* We need to take the global config into account */ | |
199e5d79 KP |
3848 | list_for_each_entry(encoder, &mode_config->encoder_list, |
3849 | base.head) { | |
3850 | switch (encoder->type) { | |
3851 | case INTEL_OUTPUT_LVDS: | |
3852 | has_panel = true; | |
3853 | has_lvds = true; | |
3854 | break; | |
3855 | case INTEL_OUTPUT_EDP: | |
3856 | has_panel = true; | |
3857 | if (intel_encoder_is_pch_edp(&encoder->base)) | |
3858 | has_pch_edp = true; | |
3859 | else | |
3860 | has_cpu_edp = true; | |
3861 | break; | |
13d83a67 JB |
3862 | } |
3863 | } | |
3864 | ||
99eb6a01 KP |
3865 | if (HAS_PCH_IBX(dev)) { |
3866 | has_ck505 = dev_priv->display_clock_mode; | |
3867 | can_ssc = has_ck505; | |
3868 | } else { | |
3869 | has_ck505 = false; | |
3870 | can_ssc = true; | |
3871 | } | |
3872 | ||
3873 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", | |
3874 | has_panel, has_lvds, has_pch_edp, has_cpu_edp, | |
3875 | has_ck505); | |
13d83a67 JB |
3876 | |
3877 | /* Ironlake: try to setup display ref clock before DPLL | |
3878 | * enabling. This is only under driver's control after | |
3879 | * PCH B stepping, previous chipset stepping should be | |
3880 | * ignoring this setting. | |
3881 | */ | |
3882 | temp = I915_READ(PCH_DREF_CONTROL); | |
3883 | /* Always enable nonspread source */ | |
3884 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
13d83a67 | 3885 | |
99eb6a01 KP |
3886 | if (has_ck505) |
3887 | temp |= DREF_NONSPREAD_CK505_ENABLE; | |
3888 | else | |
3889 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | |
13d83a67 | 3890 | |
199e5d79 KP |
3891 | if (has_panel) { |
3892 | temp &= ~DREF_SSC_SOURCE_MASK; | |
3893 | temp |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 3894 | |
199e5d79 | 3895 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 3896 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 3897 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
13d83a67 | 3898 | temp |= DREF_SSC1_ENABLE; |
e77166b5 DV |
3899 | } else |
3900 | temp &= ~DREF_SSC1_ENABLE; | |
199e5d79 KP |
3901 | |
3902 | /* Get SSC going before enabling the outputs */ | |
3903 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
3904 | POSTING_READ(PCH_DREF_CONTROL); | |
3905 | udelay(200); | |
3906 | ||
13d83a67 JB |
3907 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
3908 | ||
3909 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 3910 | if (has_cpu_edp) { |
99eb6a01 | 3911 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 3912 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
13d83a67 | 3913 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 3914 | } |
13d83a67 JB |
3915 | else |
3916 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
199e5d79 KP |
3917 | } else |
3918 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
3919 | ||
3920 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
3921 | POSTING_READ(PCH_DREF_CONTROL); | |
3922 | udelay(200); | |
3923 | } else { | |
3924 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
3925 | ||
3926 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
3927 | ||
3928 | /* Turn off CPU output */ | |
3929 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
3930 | ||
3931 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
3932 | POSTING_READ(PCH_DREF_CONTROL); | |
3933 | udelay(200); | |
3934 | ||
3935 | /* Turn off the SSC source */ | |
3936 | temp &= ~DREF_SSC_SOURCE_MASK; | |
3937 | temp |= DREF_SSC_SOURCE_DISABLE; | |
3938 | ||
3939 | /* Turn off SSC1 */ | |
3940 | temp &= ~ DREF_SSC1_ENABLE; | |
3941 | ||
13d83a67 JB |
3942 | I915_WRITE(PCH_DREF_CONTROL, temp); |
3943 | POSTING_READ(PCH_DREF_CONTROL); | |
3944 | udelay(200); | |
3945 | } | |
3946 | } | |
3947 | ||
d9d444cb JB |
3948 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
3949 | { | |
3950 | struct drm_device *dev = crtc->dev; | |
3951 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3952 | struct intel_encoder *encoder; | |
3953 | struct drm_mode_config *mode_config = &dev->mode_config; | |
3954 | struct intel_encoder *edp_encoder = NULL; | |
3955 | int num_connectors = 0; | |
3956 | bool is_lvds = false; | |
3957 | ||
3958 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
3959 | if (encoder->base.crtc != crtc) | |
3960 | continue; | |
3961 | ||
3962 | switch (encoder->type) { | |
3963 | case INTEL_OUTPUT_LVDS: | |
3964 | is_lvds = true; | |
3965 | break; | |
3966 | case INTEL_OUTPUT_EDP: | |
3967 | edp_encoder = encoder; | |
3968 | break; | |
3969 | } | |
3970 | num_connectors++; | |
3971 | } | |
3972 | ||
3973 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
3974 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
3975 | dev_priv->lvds_ssc_freq); | |
3976 | return dev_priv->lvds_ssc_freq * 1000; | |
3977 | } | |
3978 | ||
3979 | return 120000; | |
3980 | } | |
3981 | ||
f564048e EA |
3982 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
3983 | struct drm_display_mode *mode, | |
3984 | struct drm_display_mode *adjusted_mode, | |
3985 | int x, int y, | |
3986 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
3987 | { |
3988 | struct drm_device *dev = crtc->dev; | |
3989 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3990 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3991 | int pipe = intel_crtc->pipe; | |
80824003 | 3992 | int plane = intel_crtc->plane; |
c751ce4f | 3993 | int refclk, num_connectors = 0; |
652c393a | 3994 | intel_clock_t clock, reduced_clock; |
5eddb70b | 3995 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; |
a07d6787 | 3996 | bool ok, has_reduced_clock = false, is_sdvo = false; |
a4fc5ed6 | 3997 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
79e53945 | 3998 | struct drm_mode_config *mode_config = &dev->mode_config; |
e3aef172 | 3999 | struct intel_encoder *encoder, *edp_encoder = NULL; |
d4906093 | 4000 | const intel_limit_t *limit; |
5c3b82e2 | 4001 | int ret; |
2c07245f | 4002 | struct fdi_m_n m_n = {0}; |
fae14981 | 4003 | u32 temp; |
5a354204 JB |
4004 | int target_clock, pixel_multiplier, lane, link_bw, factor; |
4005 | unsigned int pipe_bpp; | |
4006 | bool dither; | |
e3aef172 | 4007 | bool is_cpu_edp = false, is_pch_edp = false; |
79e53945 | 4008 | |
5eddb70b CW |
4009 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
4010 | if (encoder->base.crtc != crtc) | |
79e53945 JB |
4011 | continue; |
4012 | ||
5eddb70b | 4013 | switch (encoder->type) { |
79e53945 JB |
4014 | case INTEL_OUTPUT_LVDS: |
4015 | is_lvds = true; | |
4016 | break; | |
4017 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 4018 | case INTEL_OUTPUT_HDMI: |
79e53945 | 4019 | is_sdvo = true; |
5eddb70b | 4020 | if (encoder->needs_tv_clock) |
e2f0ba97 | 4021 | is_tv = true; |
79e53945 | 4022 | break; |
79e53945 JB |
4023 | case INTEL_OUTPUT_TVOUT: |
4024 | is_tv = true; | |
4025 | break; | |
4026 | case INTEL_OUTPUT_ANALOG: | |
4027 | is_crt = true; | |
4028 | break; | |
a4fc5ed6 KP |
4029 | case INTEL_OUTPUT_DISPLAYPORT: |
4030 | is_dp = true; | |
4031 | break; | |
32f9d658 | 4032 | case INTEL_OUTPUT_EDP: |
e3aef172 JB |
4033 | is_dp = true; |
4034 | if (intel_encoder_is_pch_edp(&encoder->base)) | |
4035 | is_pch_edp = true; | |
4036 | else | |
4037 | is_cpu_edp = true; | |
4038 | edp_encoder = encoder; | |
32f9d658 | 4039 | break; |
79e53945 | 4040 | } |
43565a06 | 4041 | |
c751ce4f | 4042 | num_connectors++; |
79e53945 JB |
4043 | } |
4044 | ||
d9d444cb | 4045 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 4046 | |
d4906093 ML |
4047 | /* |
4048 | * Returns a set of divisors for the desired target clock with the given | |
4049 | * refclk, or FALSE. The returned values represent the clock equation: | |
4050 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
4051 | */ | |
1b894b59 | 4052 | limit = intel_limit(crtc, refclk); |
cec2f356 SP |
4053 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
4054 | &clock); | |
79e53945 JB |
4055 | if (!ok) { |
4056 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 4057 | return -EINVAL; |
79e53945 JB |
4058 | } |
4059 | ||
cda4b7d3 | 4060 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 4061 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 4062 | |
ddc9003c | 4063 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
4064 | /* |
4065 | * Ensure we match the reduced clock's P to the target clock. | |
4066 | * If the clocks don't match, we can't switch the display clock | |
4067 | * by using the FP0/FP1. In such case we will disable the LVDS | |
4068 | * downclock feature. | |
4069 | */ | |
ddc9003c | 4070 | has_reduced_clock = limit->find_pll(limit, crtc, |
5eddb70b CW |
4071 | dev_priv->lvds_downclock, |
4072 | refclk, | |
cec2f356 | 4073 | &clock, |
5eddb70b | 4074 | &reduced_clock); |
652c393a | 4075 | } |
7026d4ac ZW |
4076 | /* SDVO TV has fixed PLL values depend on its clock range, |
4077 | this mirrors vbios setting. */ | |
4078 | if (is_sdvo && is_tv) { | |
4079 | if (adjusted_mode->clock >= 100000 | |
5eddb70b | 4080 | && adjusted_mode->clock < 140500) { |
7026d4ac ZW |
4081 | clock.p1 = 2; |
4082 | clock.p2 = 10; | |
4083 | clock.n = 3; | |
4084 | clock.m1 = 16; | |
4085 | clock.m2 = 8; | |
4086 | } else if (adjusted_mode->clock >= 140500 | |
5eddb70b | 4087 | && adjusted_mode->clock <= 200000) { |
7026d4ac ZW |
4088 | clock.p1 = 1; |
4089 | clock.p2 = 10; | |
4090 | clock.n = 6; | |
4091 | clock.m1 = 12; | |
4092 | clock.m2 = 8; | |
4093 | } | |
4094 | } | |
4095 | ||
2c07245f | 4096 | /* FDI link */ |
8febb297 EA |
4097 | pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
4098 | lane = 0; | |
4099 | /* CPU eDP doesn't require FDI link, so just set DP M/N | |
4100 | according to current link config */ | |
e3aef172 | 4101 | if (is_cpu_edp) { |
8febb297 | 4102 | target_clock = mode->clock; |
e3aef172 | 4103 | intel_edp_link_config(edp_encoder, &lane, &link_bw); |
8febb297 EA |
4104 | } else { |
4105 | /* [e]DP over FDI requires target mode clock | |
4106 | instead of link clock */ | |
e3aef172 | 4107 | if (is_dp) |
5eb08b69 | 4108 | target_clock = mode->clock; |
8febb297 EA |
4109 | else |
4110 | target_clock = adjusted_mode->clock; | |
4111 | ||
4112 | /* FDI is a binary signal running at ~2.7GHz, encoding | |
4113 | * each output octet as 10 bits. The actual frequency | |
4114 | * is stored as a divider into a 100MHz clock, and the | |
4115 | * mode pixel clock is stored in units of 1KHz. | |
4116 | * Hence the bw of each lane in terms of the mode signal | |
4117 | * is: | |
4118 | */ | |
4119 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
4120 | } | |
58a27471 | 4121 | |
8febb297 EA |
4122 | /* determine panel color depth */ |
4123 | temp = I915_READ(PIPECONF(pipe)); | |
4124 | temp &= ~PIPE_BPC_MASK; | |
3b5c78a3 | 4125 | dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode); |
5a354204 JB |
4126 | switch (pipe_bpp) { |
4127 | case 18: | |
4128 | temp |= PIPE_6BPC; | |
8febb297 | 4129 | break; |
5a354204 JB |
4130 | case 24: |
4131 | temp |= PIPE_8BPC; | |
8febb297 | 4132 | break; |
5a354204 JB |
4133 | case 30: |
4134 | temp |= PIPE_10BPC; | |
8febb297 | 4135 | break; |
5a354204 JB |
4136 | case 36: |
4137 | temp |= PIPE_12BPC; | |
8febb297 EA |
4138 | break; |
4139 | default: | |
62ac41a6 JB |
4140 | WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n", |
4141 | pipe_bpp); | |
5a354204 JB |
4142 | temp |= PIPE_8BPC; |
4143 | pipe_bpp = 24; | |
4144 | break; | |
8febb297 | 4145 | } |
77ffb597 | 4146 | |
5a354204 JB |
4147 | intel_crtc->bpp = pipe_bpp; |
4148 | I915_WRITE(PIPECONF(pipe), temp); | |
4149 | ||
8febb297 EA |
4150 | if (!lane) { |
4151 | /* | |
4152 | * Account for spread spectrum to avoid | |
4153 | * oversubscribing the link. Max center spread | |
4154 | * is 2.5%; use 5% for safety's sake. | |
4155 | */ | |
5a354204 | 4156 | u32 bps = target_clock * intel_crtc->bpp * 21 / 20; |
8febb297 | 4157 | lane = bps / (link_bw * 8) + 1; |
5eb08b69 | 4158 | } |
2c07245f | 4159 | |
8febb297 EA |
4160 | intel_crtc->fdi_lanes = lane; |
4161 | ||
4162 | if (pixel_multiplier > 1) | |
4163 | link_bw *= pixel_multiplier; | |
5a354204 JB |
4164 | ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, |
4165 | &m_n); | |
8febb297 | 4166 | |
a07d6787 EA |
4167 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
4168 | if (has_reduced_clock) | |
4169 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
4170 | reduced_clock.m2; | |
79e53945 | 4171 | |
c1858123 | 4172 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
4173 | factor = 21; |
4174 | if (is_lvds) { | |
4175 | if ((intel_panel_use_ssc(dev_priv) && | |
4176 | dev_priv->lvds_ssc_freq == 100) || | |
4177 | (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) | |
4178 | factor = 25; | |
4179 | } else if (is_sdvo && is_tv) | |
4180 | factor = 20; | |
c1858123 | 4181 | |
cb0e0931 | 4182 | if (clock.m < factor * clock.n) |
8febb297 | 4183 | fp |= FP_CB_TUNE; |
2c07245f | 4184 | |
5eddb70b | 4185 | dpll = 0; |
2c07245f | 4186 | |
a07d6787 EA |
4187 | if (is_lvds) |
4188 | dpll |= DPLLB_MODE_LVDS; | |
4189 | else | |
4190 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
4191 | if (is_sdvo) { | |
4192 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); | |
4193 | if (pixel_multiplier > 1) { | |
4194 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
79e53945 | 4195 | } |
a07d6787 EA |
4196 | dpll |= DPLL_DVO_HIGH_SPEED; |
4197 | } | |
e3aef172 | 4198 | if (is_dp && !is_cpu_edp) |
a07d6787 | 4199 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 | 4200 | |
a07d6787 EA |
4201 | /* compute bitmask from p1 value */ |
4202 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4203 | /* also FPA1 */ | |
4204 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
4205 | ||
4206 | switch (clock.p2) { | |
4207 | case 5: | |
4208 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
4209 | break; | |
4210 | case 7: | |
4211 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
4212 | break; | |
4213 | case 10: | |
4214 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
4215 | break; | |
4216 | case 14: | |
4217 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
4218 | break; | |
79e53945 JB |
4219 | } |
4220 | ||
43565a06 KH |
4221 | if (is_sdvo && is_tv) |
4222 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
4223 | else if (is_tv) | |
79e53945 | 4224 | /* XXX: just matching BIOS for now */ |
43565a06 | 4225 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 4226 | dpll |= 3; |
a7615030 | 4227 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 4228 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
4229 | else |
4230 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4231 | ||
4232 | /* setup pipeconf */ | |
5eddb70b | 4233 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
4234 | |
4235 | /* Set up the display plane register */ | |
4236 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4237 | ||
f7cb34d4 | 4238 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
79e53945 JB |
4239 | drm_mode_debug_printmodeline(mode); |
4240 | ||
5c5313c8 | 4241 | /* PCH eDP needs FDI, but CPU eDP does not */ |
4b645f14 | 4242 | if (!intel_crtc->no_pll) { |
e3aef172 | 4243 | if (!is_cpu_edp) { |
4b645f14 JB |
4244 | I915_WRITE(PCH_FP0(pipe), fp); |
4245 | I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
4246 | ||
4247 | POSTING_READ(PCH_DPLL(pipe)); | |
4248 | udelay(150); | |
4249 | } | |
4250 | } else { | |
4251 | if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) && | |
4252 | fp == I915_READ(PCH_FP0(0))) { | |
4253 | intel_crtc->use_pll_a = true; | |
4254 | DRM_DEBUG_KMS("using pipe a dpll\n"); | |
4255 | } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) && | |
4256 | fp == I915_READ(PCH_FP0(1))) { | |
4257 | intel_crtc->use_pll_a = false; | |
4258 | DRM_DEBUG_KMS("using pipe b dpll\n"); | |
4259 | } else { | |
4260 | DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n"); | |
4261 | return -EINVAL; | |
4262 | } | |
79e53945 JB |
4263 | } |
4264 | ||
4265 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. | |
4266 | * This is an exception to the general rule that mode_set doesn't turn | |
4267 | * things on. | |
4268 | */ | |
4269 | if (is_lvds) { | |
fae14981 | 4270 | temp = I915_READ(PCH_LVDS); |
5eddb70b | 4271 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
7885d205 JB |
4272 | if (HAS_PCH_CPT(dev)) { |
4273 | temp &= ~PORT_TRANS_SEL_MASK; | |
4b645f14 | 4274 | temp |= PORT_TRANS_SEL_CPT(pipe); |
7885d205 JB |
4275 | } else { |
4276 | if (pipe == 1) | |
4277 | temp |= LVDS_PIPEB_SELECT; | |
4278 | else | |
4279 | temp &= ~LVDS_PIPEB_SELECT; | |
4280 | } | |
4b645f14 | 4281 | |
a3e17eb8 | 4282 | /* set the corresponsding LVDS_BORDER bit */ |
5eddb70b | 4283 | temp |= dev_priv->lvds_border_bits; |
79e53945 JB |
4284 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
4285 | * set the DPLLs for dual-channel mode or not. | |
4286 | */ | |
4287 | if (clock.p2 == 7) | |
5eddb70b | 4288 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
79e53945 | 4289 | else |
5eddb70b | 4290 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
79e53945 JB |
4291 | |
4292 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
4293 | * appropriately here, but we need to look more thoroughly into how | |
4294 | * panels behave in the two modes. | |
4295 | */ | |
284d5df5 | 4296 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); |
aa9b500d | 4297 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
284d5df5 | 4298 | temp |= LVDS_HSYNC_POLARITY; |
aa9b500d | 4299 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
284d5df5 | 4300 | temp |= LVDS_VSYNC_POLARITY; |
fae14981 | 4301 | I915_WRITE(PCH_LVDS, temp); |
79e53945 | 4302 | } |
434ed097 | 4303 | |
8febb297 EA |
4304 | pipeconf &= ~PIPECONF_DITHER_EN; |
4305 | pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; | |
5a354204 | 4306 | if ((is_lvds && dev_priv->lvds_dither) || dither) { |
8febb297 | 4307 | pipeconf |= PIPECONF_DITHER_EN; |
f74974c7 | 4308 | pipeconf |= PIPECONF_DITHER_TYPE_SP; |
434ed097 | 4309 | } |
e3aef172 | 4310 | if (is_dp && !is_cpu_edp) { |
a4fc5ed6 | 4311 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
8febb297 | 4312 | } else { |
8db9d77b | 4313 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
9db4a9c7 JB |
4314 | I915_WRITE(TRANSDATA_M1(pipe), 0); |
4315 | I915_WRITE(TRANSDATA_N1(pipe), 0); | |
4316 | I915_WRITE(TRANSDPLINK_M1(pipe), 0); | |
4317 | I915_WRITE(TRANSDPLINK_N1(pipe), 0); | |
8db9d77b | 4318 | } |
79e53945 | 4319 | |
e3aef172 | 4320 | if (!intel_crtc->no_pll && (!edp_encoder || is_pch_edp)) { |
fae14981 | 4321 | I915_WRITE(PCH_DPLL(pipe), dpll); |
5eddb70b | 4322 | |
32f9d658 | 4323 | /* Wait for the clocks to stabilize. */ |
fae14981 | 4324 | POSTING_READ(PCH_DPLL(pipe)); |
32f9d658 ZW |
4325 | udelay(150); |
4326 | ||
8febb297 EA |
4327 | /* The pixel multiplier can only be updated once the |
4328 | * DPLL is enabled and the clocks are stable. | |
4329 | * | |
4330 | * So write it again. | |
4331 | */ | |
fae14981 | 4332 | I915_WRITE(PCH_DPLL(pipe), dpll); |
79e53945 | 4333 | } |
79e53945 | 4334 | |
5eddb70b | 4335 | intel_crtc->lowfreq_avail = false; |
4b645f14 JB |
4336 | if (!intel_crtc->no_pll) { |
4337 | if (is_lvds && has_reduced_clock && i915_powersave) { | |
4338 | I915_WRITE(PCH_FP1(pipe), fp2); | |
4339 | intel_crtc->lowfreq_avail = true; | |
4340 | if (HAS_PIPE_CXSR(dev)) { | |
4341 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
4342 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
4343 | } | |
4344 | } else { | |
4345 | I915_WRITE(PCH_FP1(pipe), fp); | |
4346 | if (HAS_PIPE_CXSR(dev)) { | |
4347 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
4348 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; | |
4349 | } | |
652c393a JB |
4350 | } |
4351 | } | |
4352 | ||
617cf884 | 4353 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
734b4157 | 4354 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5def474e | 4355 | pipeconf |= PIPECONF_INTERLACED_ILK; |
734b4157 | 4356 | /* the chip adds 2 halflines automatically */ |
734b4157 | 4357 | adjusted_mode->crtc_vtotal -= 1; |
734b4157 | 4358 | adjusted_mode->crtc_vblank_end -= 1; |
0529a0d9 DV |
4359 | I915_WRITE(VSYNCSHIFT(pipe), |
4360 | adjusted_mode->crtc_hsync_start | |
4361 | - adjusted_mode->crtc_htotal/2); | |
4362 | } else { | |
617cf884 | 4363 | pipeconf |= PIPECONF_PROGRESSIVE; |
0529a0d9 DV |
4364 | I915_WRITE(VSYNCSHIFT(pipe), 0); |
4365 | } | |
734b4157 | 4366 | |
5eddb70b CW |
4367 | I915_WRITE(HTOTAL(pipe), |
4368 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 4369 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
4370 | I915_WRITE(HBLANK(pipe), |
4371 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 4372 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
4373 | I915_WRITE(HSYNC(pipe), |
4374 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 4375 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
4376 | |
4377 | I915_WRITE(VTOTAL(pipe), | |
4378 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 4379 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
4380 | I915_WRITE(VBLANK(pipe), |
4381 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 4382 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
4383 | I915_WRITE(VSYNC(pipe), |
4384 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 4385 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b | 4386 | |
8febb297 EA |
4387 | /* pipesrc controls the size that is scaled from, which should |
4388 | * always be the user's requested size. | |
79e53945 | 4389 | */ |
5eddb70b CW |
4390 | I915_WRITE(PIPESRC(pipe), |
4391 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 4392 | |
8febb297 EA |
4393 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
4394 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); | |
4395 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); | |
4396 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); | |
2c07245f | 4397 | |
e3aef172 | 4398 | if (is_cpu_edp) |
8febb297 | 4399 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
2c07245f | 4400 | |
5eddb70b CW |
4401 | I915_WRITE(PIPECONF(pipe), pipeconf); |
4402 | POSTING_READ(PIPECONF(pipe)); | |
79e53945 | 4403 | |
9d0498a2 | 4404 | intel_wait_for_vblank(dev, pipe); |
79e53945 | 4405 | |
5eddb70b | 4406 | I915_WRITE(DSPCNTR(plane), dspcntr); |
b24e7179 | 4407 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 4408 | |
5c3b82e2 | 4409 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
7662c8bd SL |
4410 | |
4411 | intel_update_watermarks(dev); | |
4412 | ||
1f803ee5 | 4413 | return ret; |
79e53945 JB |
4414 | } |
4415 | ||
f564048e EA |
4416 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
4417 | struct drm_display_mode *mode, | |
4418 | struct drm_display_mode *adjusted_mode, | |
4419 | int x, int y, | |
4420 | struct drm_framebuffer *old_fb) | |
4421 | { | |
4422 | struct drm_device *dev = crtc->dev; | |
4423 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b701d27 EA |
4424 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4425 | int pipe = intel_crtc->pipe; | |
f564048e EA |
4426 | int ret; |
4427 | ||
0b701d27 | 4428 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 4429 | |
f564048e EA |
4430 | ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, |
4431 | x, y, old_fb); | |
79e53945 | 4432 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 4433 | |
d8e70a25 JB |
4434 | if (ret) |
4435 | intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; | |
4436 | else | |
4437 | intel_crtc->dpms_mode = DRM_MODE_DPMS_ON; | |
120eced9 | 4438 | |
1f803ee5 | 4439 | return ret; |
79e53945 JB |
4440 | } |
4441 | ||
3a9627f4 WF |
4442 | static bool intel_eld_uptodate(struct drm_connector *connector, |
4443 | int reg_eldv, uint32_t bits_eldv, | |
4444 | int reg_elda, uint32_t bits_elda, | |
4445 | int reg_edid) | |
4446 | { | |
4447 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
4448 | uint8_t *eld = connector->eld; | |
4449 | uint32_t i; | |
4450 | ||
4451 | i = I915_READ(reg_eldv); | |
4452 | i &= bits_eldv; | |
4453 | ||
4454 | if (!eld[0]) | |
4455 | return !i; | |
4456 | ||
4457 | if (!i) | |
4458 | return false; | |
4459 | ||
4460 | i = I915_READ(reg_elda); | |
4461 | i &= ~bits_elda; | |
4462 | I915_WRITE(reg_elda, i); | |
4463 | ||
4464 | for (i = 0; i < eld[2]; i++) | |
4465 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
4466 | return false; | |
4467 | ||
4468 | return true; | |
4469 | } | |
4470 | ||
e0dac65e WF |
4471 | static void g4x_write_eld(struct drm_connector *connector, |
4472 | struct drm_crtc *crtc) | |
4473 | { | |
4474 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
4475 | uint8_t *eld = connector->eld; | |
4476 | uint32_t eldv; | |
4477 | uint32_t len; | |
4478 | uint32_t i; | |
4479 | ||
4480 | i = I915_READ(G4X_AUD_VID_DID); | |
4481 | ||
4482 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
4483 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
4484 | else | |
4485 | eldv = G4X_ELDV_DEVCTG; | |
4486 | ||
3a9627f4 WF |
4487 | if (intel_eld_uptodate(connector, |
4488 | G4X_AUD_CNTL_ST, eldv, | |
4489 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
4490 | G4X_HDMIW_HDMIEDID)) | |
4491 | return; | |
4492 | ||
e0dac65e WF |
4493 | i = I915_READ(G4X_AUD_CNTL_ST); |
4494 | i &= ~(eldv | G4X_ELD_ADDR); | |
4495 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
4496 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
4497 | ||
4498 | if (!eld[0]) | |
4499 | return; | |
4500 | ||
4501 | len = min_t(uint8_t, eld[2], len); | |
4502 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
4503 | for (i = 0; i < len; i++) | |
4504 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
4505 | ||
4506 | i = I915_READ(G4X_AUD_CNTL_ST); | |
4507 | i |= eldv; | |
4508 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
4509 | } | |
4510 | ||
4511 | static void ironlake_write_eld(struct drm_connector *connector, | |
4512 | struct drm_crtc *crtc) | |
4513 | { | |
4514 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
4515 | uint8_t *eld = connector->eld; | |
4516 | uint32_t eldv; | |
4517 | uint32_t i; | |
4518 | int len; | |
4519 | int hdmiw_hdmiedid; | |
b6daa025 | 4520 | int aud_config; |
e0dac65e WF |
4521 | int aud_cntl_st; |
4522 | int aud_cntrl_st2; | |
4523 | ||
b3f33cbf | 4524 | if (HAS_PCH_IBX(connector->dev)) { |
1202b4c6 | 4525 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A; |
b6daa025 | 4526 | aud_config = IBX_AUD_CONFIG_A; |
1202b4c6 WF |
4527 | aud_cntl_st = IBX_AUD_CNTL_ST_A; |
4528 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; | |
e0dac65e | 4529 | } else { |
1202b4c6 | 4530 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A; |
b6daa025 | 4531 | aud_config = CPT_AUD_CONFIG_A; |
1202b4c6 WF |
4532 | aud_cntl_st = CPT_AUD_CNTL_ST_A; |
4533 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; | |
e0dac65e WF |
4534 | } |
4535 | ||
4536 | i = to_intel_crtc(crtc)->pipe; | |
4537 | hdmiw_hdmiedid += i * 0x100; | |
4538 | aud_cntl_st += i * 0x100; | |
b6daa025 | 4539 | aud_config += i * 0x100; |
e0dac65e WF |
4540 | |
4541 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i)); | |
4542 | ||
4543 | i = I915_READ(aud_cntl_st); | |
4544 | i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */ | |
4545 | if (!i) { | |
4546 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
4547 | /* operate blindly on all ports */ | |
1202b4c6 WF |
4548 | eldv = IBX_ELD_VALIDB; |
4549 | eldv |= IBX_ELD_VALIDB << 4; | |
4550 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e WF |
4551 | } else { |
4552 | DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); | |
1202b4c6 | 4553 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
4554 | } |
4555 | ||
3a9627f4 WF |
4556 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
4557 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
4558 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 WF |
4559 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
4560 | } else | |
4561 | I915_WRITE(aud_config, 0); | |
e0dac65e | 4562 | |
3a9627f4 WF |
4563 | if (intel_eld_uptodate(connector, |
4564 | aud_cntrl_st2, eldv, | |
4565 | aud_cntl_st, IBX_ELD_ADDRESS, | |
4566 | hdmiw_hdmiedid)) | |
4567 | return; | |
4568 | ||
e0dac65e WF |
4569 | i = I915_READ(aud_cntrl_st2); |
4570 | i &= ~eldv; | |
4571 | I915_WRITE(aud_cntrl_st2, i); | |
4572 | ||
4573 | if (!eld[0]) | |
4574 | return; | |
4575 | ||
e0dac65e | 4576 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 4577 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
4578 | I915_WRITE(aud_cntl_st, i); |
4579 | ||
4580 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
4581 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
4582 | for (i = 0; i < len; i++) | |
4583 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
4584 | ||
4585 | i = I915_READ(aud_cntrl_st2); | |
4586 | i |= eldv; | |
4587 | I915_WRITE(aud_cntrl_st2, i); | |
4588 | } | |
4589 | ||
4590 | void intel_write_eld(struct drm_encoder *encoder, | |
4591 | struct drm_display_mode *mode) | |
4592 | { | |
4593 | struct drm_crtc *crtc = encoder->crtc; | |
4594 | struct drm_connector *connector; | |
4595 | struct drm_device *dev = encoder->dev; | |
4596 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4597 | ||
4598 | connector = drm_select_eld(encoder, mode); | |
4599 | if (!connector) | |
4600 | return; | |
4601 | ||
4602 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
4603 | connector->base.id, | |
4604 | drm_get_connector_name(connector), | |
4605 | connector->encoder->base.id, | |
4606 | drm_get_encoder_name(connector->encoder)); | |
4607 | ||
4608 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
4609 | ||
4610 | if (dev_priv->display.write_eld) | |
4611 | dev_priv->display.write_eld(connector, crtc); | |
4612 | } | |
4613 | ||
79e53945 JB |
4614 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
4615 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4616 | { | |
4617 | struct drm_device *dev = crtc->dev; | |
4618 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4619 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9db4a9c7 | 4620 | int palreg = PALETTE(intel_crtc->pipe); |
79e53945 JB |
4621 | int i; |
4622 | ||
4623 | /* The clocks have to be on to load the palette. */ | |
aed3f09d | 4624 | if (!crtc->enabled || !intel_crtc->active) |
79e53945 JB |
4625 | return; |
4626 | ||
f2b115e6 | 4627 | /* use legacy palette for Ironlake */ |
bad720ff | 4628 | if (HAS_PCH_SPLIT(dev)) |
9db4a9c7 | 4629 | palreg = LGC_PALETTE(intel_crtc->pipe); |
2c07245f | 4630 | |
79e53945 JB |
4631 | for (i = 0; i < 256; i++) { |
4632 | I915_WRITE(palreg + 4 * i, | |
4633 | (intel_crtc->lut_r[i] << 16) | | |
4634 | (intel_crtc->lut_g[i] << 8) | | |
4635 | intel_crtc->lut_b[i]); | |
4636 | } | |
4637 | } | |
4638 | ||
560b85bb CW |
4639 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
4640 | { | |
4641 | struct drm_device *dev = crtc->dev; | |
4642 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4643 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4644 | bool visible = base != 0; | |
4645 | u32 cntl; | |
4646 | ||
4647 | if (intel_crtc->cursor_visible == visible) | |
4648 | return; | |
4649 | ||
9db4a9c7 | 4650 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
4651 | if (visible) { |
4652 | /* On these chipsets we can only modify the base whilst | |
4653 | * the cursor is disabled. | |
4654 | */ | |
9db4a9c7 | 4655 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
4656 | |
4657 | cntl &= ~(CURSOR_FORMAT_MASK); | |
4658 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
4659 | cntl |= CURSOR_ENABLE | | |
4660 | CURSOR_GAMMA_ENABLE | | |
4661 | CURSOR_FORMAT_ARGB; | |
4662 | } else | |
4663 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 4664 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
4665 | |
4666 | intel_crtc->cursor_visible = visible; | |
4667 | } | |
4668 | ||
4669 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
4670 | { | |
4671 | struct drm_device *dev = crtc->dev; | |
4672 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4673 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4674 | int pipe = intel_crtc->pipe; | |
4675 | bool visible = base != 0; | |
4676 | ||
4677 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 4678 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
4679 | if (base) { |
4680 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
4681 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
4682 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
4683 | } else { | |
4684 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
4685 | cntl |= CURSOR_MODE_DISABLE; | |
4686 | } | |
9db4a9c7 | 4687 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
4688 | |
4689 | intel_crtc->cursor_visible = visible; | |
4690 | } | |
4691 | /* and commit changes on next vblank */ | |
9db4a9c7 | 4692 | I915_WRITE(CURBASE(pipe), base); |
560b85bb CW |
4693 | } |
4694 | ||
65a21cd6 JB |
4695 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
4696 | { | |
4697 | struct drm_device *dev = crtc->dev; | |
4698 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4699 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4700 | int pipe = intel_crtc->pipe; | |
4701 | bool visible = base != 0; | |
4702 | ||
4703 | if (intel_crtc->cursor_visible != visible) { | |
4704 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
4705 | if (base) { | |
4706 | cntl &= ~CURSOR_MODE; | |
4707 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
4708 | } else { | |
4709 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
4710 | cntl |= CURSOR_MODE_DISABLE; | |
4711 | } | |
4712 | I915_WRITE(CURCNTR_IVB(pipe), cntl); | |
4713 | ||
4714 | intel_crtc->cursor_visible = visible; | |
4715 | } | |
4716 | /* and commit changes on next vblank */ | |
4717 | I915_WRITE(CURBASE_IVB(pipe), base); | |
4718 | } | |
4719 | ||
cda4b7d3 | 4720 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
4721 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
4722 | bool on) | |
cda4b7d3 CW |
4723 | { |
4724 | struct drm_device *dev = crtc->dev; | |
4725 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4726 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4727 | int pipe = intel_crtc->pipe; | |
4728 | int x = intel_crtc->cursor_x; | |
4729 | int y = intel_crtc->cursor_y; | |
560b85bb | 4730 | u32 base, pos; |
cda4b7d3 CW |
4731 | bool visible; |
4732 | ||
4733 | pos = 0; | |
4734 | ||
6b383a7f | 4735 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
4736 | base = intel_crtc->cursor_addr; |
4737 | if (x > (int) crtc->fb->width) | |
4738 | base = 0; | |
4739 | ||
4740 | if (y > (int) crtc->fb->height) | |
4741 | base = 0; | |
4742 | } else | |
4743 | base = 0; | |
4744 | ||
4745 | if (x < 0) { | |
4746 | if (x + intel_crtc->cursor_width < 0) | |
4747 | base = 0; | |
4748 | ||
4749 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
4750 | x = -x; | |
4751 | } | |
4752 | pos |= x << CURSOR_X_SHIFT; | |
4753 | ||
4754 | if (y < 0) { | |
4755 | if (y + intel_crtc->cursor_height < 0) | |
4756 | base = 0; | |
4757 | ||
4758 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
4759 | y = -y; | |
4760 | } | |
4761 | pos |= y << CURSOR_Y_SHIFT; | |
4762 | ||
4763 | visible = base != 0; | |
560b85bb | 4764 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
4765 | return; |
4766 | ||
0cd83aa9 | 4767 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
65a21cd6 JB |
4768 | I915_WRITE(CURPOS_IVB(pipe), pos); |
4769 | ivb_update_cursor(crtc, base); | |
4770 | } else { | |
4771 | I915_WRITE(CURPOS(pipe), pos); | |
4772 | if (IS_845G(dev) || IS_I865G(dev)) | |
4773 | i845_update_cursor(crtc, base); | |
4774 | else | |
4775 | i9xx_update_cursor(crtc, base); | |
4776 | } | |
cda4b7d3 CW |
4777 | |
4778 | if (visible) | |
4779 | intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); | |
4780 | } | |
4781 | ||
79e53945 | 4782 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 4783 | struct drm_file *file, |
79e53945 JB |
4784 | uint32_t handle, |
4785 | uint32_t width, uint32_t height) | |
4786 | { | |
4787 | struct drm_device *dev = crtc->dev; | |
4788 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4789 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 4790 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 4791 | uint32_t addr; |
3f8bc370 | 4792 | int ret; |
79e53945 | 4793 | |
28c97730 | 4794 | DRM_DEBUG_KMS("\n"); |
79e53945 JB |
4795 | |
4796 | /* if we want to turn off the cursor ignore width and height */ | |
4797 | if (!handle) { | |
28c97730 | 4798 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 4799 | addr = 0; |
05394f39 | 4800 | obj = NULL; |
5004417d | 4801 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 4802 | goto finish; |
79e53945 JB |
4803 | } |
4804 | ||
4805 | /* Currently we only support 64x64 cursors */ | |
4806 | if (width != 64 || height != 64) { | |
4807 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
4808 | return -EINVAL; | |
4809 | } | |
4810 | ||
05394f39 | 4811 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 4812 | if (&obj->base == NULL) |
79e53945 JB |
4813 | return -ENOENT; |
4814 | ||
05394f39 | 4815 | if (obj->base.size < width * height * 4) { |
79e53945 | 4816 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
4817 | ret = -ENOMEM; |
4818 | goto fail; | |
79e53945 JB |
4819 | } |
4820 | ||
71acb5eb | 4821 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 4822 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 4823 | if (!dev_priv->info->cursor_needs_physical) { |
d9e86c0e CW |
4824 | if (obj->tiling_mode) { |
4825 | DRM_ERROR("cursor cannot be tiled\n"); | |
4826 | ret = -EINVAL; | |
4827 | goto fail_locked; | |
4828 | } | |
4829 | ||
2da3b9b9 | 4830 | ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); |
e7b526bb CW |
4831 | if (ret) { |
4832 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 4833 | goto fail_locked; |
e7b526bb CW |
4834 | } |
4835 | ||
d9e86c0e CW |
4836 | ret = i915_gem_object_put_fence(obj); |
4837 | if (ret) { | |
2da3b9b9 | 4838 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
4839 | goto fail_unpin; |
4840 | } | |
4841 | ||
05394f39 | 4842 | addr = obj->gtt_offset; |
71acb5eb | 4843 | } else { |
6eeefaf3 | 4844 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 4845 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
4846 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
4847 | align); | |
71acb5eb DA |
4848 | if (ret) { |
4849 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 4850 | goto fail_locked; |
71acb5eb | 4851 | } |
05394f39 | 4852 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
4853 | } |
4854 | ||
a6c45cf0 | 4855 | if (IS_GEN2(dev)) |
14b60391 JB |
4856 | I915_WRITE(CURSIZE, (height << 12) | width); |
4857 | ||
3f8bc370 | 4858 | finish: |
3f8bc370 | 4859 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 4860 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 4861 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
4862 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
4863 | } else | |
4864 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
05394f39 | 4865 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 4866 | } |
80824003 | 4867 | |
7f9872e0 | 4868 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
4869 | |
4870 | intel_crtc->cursor_addr = addr; | |
05394f39 | 4871 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
4872 | intel_crtc->cursor_width = width; |
4873 | intel_crtc->cursor_height = height; | |
4874 | ||
6b383a7f | 4875 | intel_crtc_update_cursor(crtc, true); |
3f8bc370 | 4876 | |
79e53945 | 4877 | return 0; |
e7b526bb | 4878 | fail_unpin: |
05394f39 | 4879 | i915_gem_object_unpin(obj); |
7f9872e0 | 4880 | fail_locked: |
34b8686e | 4881 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 4882 | fail: |
05394f39 | 4883 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 4884 | return ret; |
79e53945 JB |
4885 | } |
4886 | ||
4887 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
4888 | { | |
79e53945 | 4889 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 4890 | |
cda4b7d3 CW |
4891 | intel_crtc->cursor_x = x; |
4892 | intel_crtc->cursor_y = y; | |
652c393a | 4893 | |
6b383a7f | 4894 | intel_crtc_update_cursor(crtc, true); |
79e53945 JB |
4895 | |
4896 | return 0; | |
4897 | } | |
4898 | ||
4899 | /** Sets the color ramps on behalf of RandR */ | |
4900 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
4901 | u16 blue, int regno) | |
4902 | { | |
4903 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4904 | ||
4905 | intel_crtc->lut_r[regno] = red >> 8; | |
4906 | intel_crtc->lut_g[regno] = green >> 8; | |
4907 | intel_crtc->lut_b[regno] = blue >> 8; | |
4908 | } | |
4909 | ||
b8c00ac5 DA |
4910 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
4911 | u16 *blue, int regno) | |
4912 | { | |
4913 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4914 | ||
4915 | *red = intel_crtc->lut_r[regno] << 8; | |
4916 | *green = intel_crtc->lut_g[regno] << 8; | |
4917 | *blue = intel_crtc->lut_b[regno] << 8; | |
4918 | } | |
4919 | ||
79e53945 | 4920 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 4921 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 4922 | { |
7203425a | 4923 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 4924 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 4925 | |
7203425a | 4926 | for (i = start; i < end; i++) { |
79e53945 JB |
4927 | intel_crtc->lut_r[i] = red[i] >> 8; |
4928 | intel_crtc->lut_g[i] = green[i] >> 8; | |
4929 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
4930 | } | |
4931 | ||
4932 | intel_crtc_load_lut(crtc); | |
4933 | } | |
4934 | ||
4935 | /** | |
4936 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
4937 | * detection. | |
4938 | * | |
4939 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
c751ce4f | 4940 | * its requirements. The pipe will be connected to no other encoders. |
79e53945 | 4941 | * |
c751ce4f | 4942 | * Currently this code will only succeed if there is a pipe with no encoders |
79e53945 JB |
4943 | * configured for it. In the future, it could choose to temporarily disable |
4944 | * some outputs to free up a pipe for its use. | |
4945 | * | |
4946 | * \return crtc, or NULL if no pipes are available. | |
4947 | */ | |
4948 | ||
4949 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
4950 | static struct drm_display_mode load_detect_mode = { | |
4951 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
4952 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
4953 | }; | |
4954 | ||
d2dff872 CW |
4955 | static struct drm_framebuffer * |
4956 | intel_framebuffer_create(struct drm_device *dev, | |
308e5bcb | 4957 | struct drm_mode_fb_cmd2 *mode_cmd, |
d2dff872 CW |
4958 | struct drm_i915_gem_object *obj) |
4959 | { | |
4960 | struct intel_framebuffer *intel_fb; | |
4961 | int ret; | |
4962 | ||
4963 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
4964 | if (!intel_fb) { | |
4965 | drm_gem_object_unreference_unlocked(&obj->base); | |
4966 | return ERR_PTR(-ENOMEM); | |
4967 | } | |
4968 | ||
4969 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
4970 | if (ret) { | |
4971 | drm_gem_object_unreference_unlocked(&obj->base); | |
4972 | kfree(intel_fb); | |
4973 | return ERR_PTR(ret); | |
4974 | } | |
4975 | ||
4976 | return &intel_fb->base; | |
4977 | } | |
4978 | ||
4979 | static u32 | |
4980 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
4981 | { | |
4982 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
4983 | return ALIGN(pitch, 64); | |
4984 | } | |
4985 | ||
4986 | static u32 | |
4987 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
4988 | { | |
4989 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
4990 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
4991 | } | |
4992 | ||
4993 | static struct drm_framebuffer * | |
4994 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
4995 | struct drm_display_mode *mode, | |
4996 | int depth, int bpp) | |
4997 | { | |
4998 | struct drm_i915_gem_object *obj; | |
308e5bcb | 4999 | struct drm_mode_fb_cmd2 mode_cmd; |
d2dff872 CW |
5000 | |
5001 | obj = i915_gem_alloc_object(dev, | |
5002 | intel_framebuffer_size_for_mode(mode, bpp)); | |
5003 | if (obj == NULL) | |
5004 | return ERR_PTR(-ENOMEM); | |
5005 | ||
5006 | mode_cmd.width = mode->hdisplay; | |
5007 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
5008 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
5009 | bpp); | |
5ca0c34a | 5010 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
5011 | |
5012 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
5013 | } | |
5014 | ||
5015 | static struct drm_framebuffer * | |
5016 | mode_fits_in_fbdev(struct drm_device *dev, | |
5017 | struct drm_display_mode *mode) | |
5018 | { | |
5019 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5020 | struct drm_i915_gem_object *obj; | |
5021 | struct drm_framebuffer *fb; | |
5022 | ||
5023 | if (dev_priv->fbdev == NULL) | |
5024 | return NULL; | |
5025 | ||
5026 | obj = dev_priv->fbdev->ifb.obj; | |
5027 | if (obj == NULL) | |
5028 | return NULL; | |
5029 | ||
5030 | fb = &dev_priv->fbdev->ifb.base; | |
01f2c773 VS |
5031 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
5032 | fb->bits_per_pixel)) | |
d2dff872 CW |
5033 | return NULL; |
5034 | ||
01f2c773 | 5035 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
5036 | return NULL; |
5037 | ||
5038 | return fb; | |
5039 | } | |
5040 | ||
7173188d CW |
5041 | bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
5042 | struct drm_connector *connector, | |
5043 | struct drm_display_mode *mode, | |
8261b191 | 5044 | struct intel_load_detect_pipe *old) |
79e53945 JB |
5045 | { |
5046 | struct intel_crtc *intel_crtc; | |
5047 | struct drm_crtc *possible_crtc; | |
4ef69c7a | 5048 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
5049 | struct drm_crtc *crtc = NULL; |
5050 | struct drm_device *dev = encoder->dev; | |
d2dff872 | 5051 | struct drm_framebuffer *old_fb; |
79e53945 JB |
5052 | int i = -1; |
5053 | ||
d2dff872 CW |
5054 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
5055 | connector->base.id, drm_get_connector_name(connector), | |
5056 | encoder->base.id, drm_get_encoder_name(encoder)); | |
5057 | ||
79e53945 JB |
5058 | /* |
5059 | * Algorithm gets a little messy: | |
7a5e4805 | 5060 | * |
79e53945 JB |
5061 | * - if the connector already has an assigned crtc, use it (but make |
5062 | * sure it's on first) | |
7a5e4805 | 5063 | * |
79e53945 JB |
5064 | * - try to find the first unused crtc that can drive this connector, |
5065 | * and use that if we find one | |
79e53945 JB |
5066 | */ |
5067 | ||
5068 | /* See if we already have a CRTC for this connector */ | |
5069 | if (encoder->crtc) { | |
5070 | crtc = encoder->crtc; | |
8261b191 | 5071 | |
79e53945 | 5072 | intel_crtc = to_intel_crtc(crtc); |
8261b191 CW |
5073 | old->dpms_mode = intel_crtc->dpms_mode; |
5074 | old->load_detect_temp = false; | |
5075 | ||
5076 | /* Make sure the crtc and connector are running */ | |
79e53945 | 5077 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { |
6492711d CW |
5078 | struct drm_encoder_helper_funcs *encoder_funcs; |
5079 | struct drm_crtc_helper_funcs *crtc_funcs; | |
5080 | ||
79e53945 JB |
5081 | crtc_funcs = crtc->helper_private; |
5082 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
6492711d CW |
5083 | |
5084 | encoder_funcs = encoder->helper_private; | |
79e53945 JB |
5085 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
5086 | } | |
8261b191 | 5087 | |
7173188d | 5088 | return true; |
79e53945 JB |
5089 | } |
5090 | ||
5091 | /* Find an unused one (if possible) */ | |
5092 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
5093 | i++; | |
5094 | if (!(encoder->possible_crtcs & (1 << i))) | |
5095 | continue; | |
5096 | if (!possible_crtc->enabled) { | |
5097 | crtc = possible_crtc; | |
5098 | break; | |
5099 | } | |
79e53945 JB |
5100 | } |
5101 | ||
5102 | /* | |
5103 | * If we didn't find an unused CRTC, don't use any. | |
5104 | */ | |
5105 | if (!crtc) { | |
7173188d CW |
5106 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
5107 | return false; | |
79e53945 JB |
5108 | } |
5109 | ||
5110 | encoder->crtc = crtc; | |
c1c43977 | 5111 | connector->encoder = encoder; |
79e53945 JB |
5112 | |
5113 | intel_crtc = to_intel_crtc(crtc); | |
8261b191 CW |
5114 | old->dpms_mode = intel_crtc->dpms_mode; |
5115 | old->load_detect_temp = true; | |
d2dff872 | 5116 | old->release_fb = NULL; |
79e53945 | 5117 | |
6492711d CW |
5118 | if (!mode) |
5119 | mode = &load_detect_mode; | |
79e53945 | 5120 | |
d2dff872 CW |
5121 | old_fb = crtc->fb; |
5122 | ||
5123 | /* We need a framebuffer large enough to accommodate all accesses | |
5124 | * that the plane may generate whilst we perform load detection. | |
5125 | * We can not rely on the fbcon either being present (we get called | |
5126 | * during its initialisation to detect all boot displays, or it may | |
5127 | * not even exist) or that it is large enough to satisfy the | |
5128 | * requested mode. | |
5129 | */ | |
5130 | crtc->fb = mode_fits_in_fbdev(dev, mode); | |
5131 | if (crtc->fb == NULL) { | |
5132 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); | |
5133 | crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); | |
5134 | old->release_fb = crtc->fb; | |
5135 | } else | |
5136 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
5137 | if (IS_ERR(crtc->fb)) { | |
5138 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); | |
5139 | crtc->fb = old_fb; | |
5140 | return false; | |
79e53945 | 5141 | } |
79e53945 | 5142 | |
d2dff872 | 5143 | if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) { |
6492711d | 5144 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
5145 | if (old->release_fb) |
5146 | old->release_fb->funcs->destroy(old->release_fb); | |
5147 | crtc->fb = old_fb; | |
6492711d | 5148 | return false; |
79e53945 | 5149 | } |
7173188d | 5150 | |
79e53945 | 5151 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 5152 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
79e53945 | 5153 | |
7173188d | 5154 | return true; |
79e53945 JB |
5155 | } |
5156 | ||
c1c43977 | 5157 | void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
8261b191 CW |
5158 | struct drm_connector *connector, |
5159 | struct intel_load_detect_pipe *old) | |
79e53945 | 5160 | { |
4ef69c7a | 5161 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
5162 | struct drm_device *dev = encoder->dev; |
5163 | struct drm_crtc *crtc = encoder->crtc; | |
5164 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
5165 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
5166 | ||
d2dff872 CW |
5167 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
5168 | connector->base.id, drm_get_connector_name(connector), | |
5169 | encoder->base.id, drm_get_encoder_name(encoder)); | |
5170 | ||
8261b191 | 5171 | if (old->load_detect_temp) { |
c1c43977 | 5172 | connector->encoder = NULL; |
79e53945 | 5173 | drm_helper_disable_unused_functions(dev); |
d2dff872 CW |
5174 | |
5175 | if (old->release_fb) | |
5176 | old->release_fb->funcs->destroy(old->release_fb); | |
5177 | ||
0622a53c | 5178 | return; |
79e53945 JB |
5179 | } |
5180 | ||
c751ce4f | 5181 | /* Switch crtc and encoder back off if necessary */ |
0622a53c CW |
5182 | if (old->dpms_mode != DRM_MODE_DPMS_ON) { |
5183 | encoder_funcs->dpms(encoder, old->dpms_mode); | |
8261b191 | 5184 | crtc_funcs->dpms(crtc, old->dpms_mode); |
79e53945 JB |
5185 | } |
5186 | } | |
5187 | ||
5188 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
5189 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
5190 | { | |
5191 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5192 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5193 | int pipe = intel_crtc->pipe; | |
548f245b | 5194 | u32 dpll = I915_READ(DPLL(pipe)); |
79e53945 JB |
5195 | u32 fp; |
5196 | intel_clock_t clock; | |
5197 | ||
5198 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
39adb7a5 | 5199 | fp = I915_READ(FP0(pipe)); |
79e53945 | 5200 | else |
39adb7a5 | 5201 | fp = I915_READ(FP1(pipe)); |
79e53945 JB |
5202 | |
5203 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
5204 | if (IS_PINEVIEW(dev)) { |
5205 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
5206 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
5207 | } else { |
5208 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
5209 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
5210 | } | |
5211 | ||
a6c45cf0 | 5212 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
5213 | if (IS_PINEVIEW(dev)) |
5214 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
5215 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
5216 | else |
5217 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
5218 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
5219 | ||
5220 | switch (dpll & DPLL_MODE_MASK) { | |
5221 | case DPLLB_MODE_DAC_SERIAL: | |
5222 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
5223 | 5 : 10; | |
5224 | break; | |
5225 | case DPLLB_MODE_LVDS: | |
5226 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
5227 | 7 : 14; | |
5228 | break; | |
5229 | default: | |
28c97730 | 5230 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
5231 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
5232 | return 0; | |
5233 | } | |
5234 | ||
5235 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 5236 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
5237 | } else { |
5238 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
5239 | ||
5240 | if (is_lvds) { | |
5241 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
5242 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
5243 | clock.p2 = 14; | |
5244 | ||
5245 | if ((dpll & PLL_REF_INPUT_MASK) == | |
5246 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
5247 | /* XXX: might not be 66MHz */ | |
2177832f | 5248 | intel_clock(dev, 66000, &clock); |
79e53945 | 5249 | } else |
2177832f | 5250 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
5251 | } else { |
5252 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
5253 | clock.p1 = 2; | |
5254 | else { | |
5255 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
5256 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
5257 | } | |
5258 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
5259 | clock.p2 = 4; | |
5260 | else | |
5261 | clock.p2 = 2; | |
5262 | ||
2177832f | 5263 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
5264 | } |
5265 | } | |
5266 | ||
5267 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
5268 | * i830PllIsValid() because it relies on the xf86_config connector | |
5269 | * configuration being accurate, which it isn't necessarily. | |
5270 | */ | |
5271 | ||
5272 | return clock.dot; | |
5273 | } | |
5274 | ||
5275 | /** Returns the currently programmed mode of the given pipe. */ | |
5276 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
5277 | struct drm_crtc *crtc) | |
5278 | { | |
548f245b | 5279 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
5280 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5281 | int pipe = intel_crtc->pipe; | |
5282 | struct drm_display_mode *mode; | |
548f245b JB |
5283 | int htot = I915_READ(HTOTAL(pipe)); |
5284 | int hsync = I915_READ(HSYNC(pipe)); | |
5285 | int vtot = I915_READ(VTOTAL(pipe)); | |
5286 | int vsync = I915_READ(VSYNC(pipe)); | |
79e53945 JB |
5287 | |
5288 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
5289 | if (!mode) | |
5290 | return NULL; | |
5291 | ||
5292 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
5293 | mode->hdisplay = (htot & 0xffff) + 1; | |
5294 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
5295 | mode->hsync_start = (hsync & 0xffff) + 1; | |
5296 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
5297 | mode->vdisplay = (vtot & 0xffff) + 1; | |
5298 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
5299 | mode->vsync_start = (vsync & 0xffff) + 1; | |
5300 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
5301 | ||
5302 | drm_mode_set_name(mode); | |
5303 | drm_mode_set_crtcinfo(mode, 0); | |
5304 | ||
5305 | return mode; | |
5306 | } | |
5307 | ||
652c393a JB |
5308 | #define GPU_IDLE_TIMEOUT 500 /* ms */ |
5309 | ||
5310 | /* When this timer fires, we've been idle for awhile */ | |
5311 | static void intel_gpu_idle_timer(unsigned long arg) | |
5312 | { | |
5313 | struct drm_device *dev = (struct drm_device *)arg; | |
5314 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5315 | ||
ff7ea4c0 CW |
5316 | if (!list_empty(&dev_priv->mm.active_list)) { |
5317 | /* Still processing requests, so just re-arm the timer. */ | |
5318 | mod_timer(&dev_priv->idle_timer, jiffies + | |
5319 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
5320 | return; | |
5321 | } | |
652c393a | 5322 | |
ff7ea4c0 | 5323 | dev_priv->busy = false; |
01dfba93 | 5324 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
5325 | } |
5326 | ||
652c393a JB |
5327 | #define CRTC_IDLE_TIMEOUT 1000 /* ms */ |
5328 | ||
5329 | static void intel_crtc_idle_timer(unsigned long arg) | |
5330 | { | |
5331 | struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; | |
5332 | struct drm_crtc *crtc = &intel_crtc->base; | |
5333 | drm_i915_private_t *dev_priv = crtc->dev->dev_private; | |
ff7ea4c0 | 5334 | struct intel_framebuffer *intel_fb; |
652c393a | 5335 | |
ff7ea4c0 CW |
5336 | intel_fb = to_intel_framebuffer(crtc->fb); |
5337 | if (intel_fb && intel_fb->obj->active) { | |
5338 | /* The framebuffer is still being accessed by the GPU. */ | |
5339 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
5340 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
5341 | return; | |
5342 | } | |
652c393a | 5343 | |
ff7ea4c0 | 5344 | intel_crtc->busy = false; |
01dfba93 | 5345 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
5346 | } |
5347 | ||
3dec0095 | 5348 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
5349 | { |
5350 | struct drm_device *dev = crtc->dev; | |
5351 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5352 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5353 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
5354 | int dpll_reg = DPLL(pipe); |
5355 | int dpll; | |
652c393a | 5356 | |
bad720ff | 5357 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
5358 | return; |
5359 | ||
5360 | if (!dev_priv->lvds_downclock_avail) | |
5361 | return; | |
5362 | ||
dbdc6479 | 5363 | dpll = I915_READ(dpll_reg); |
652c393a | 5364 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 5365 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 5366 | |
8ac5a6d5 | 5367 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
5368 | |
5369 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
5370 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 5371 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 5372 | |
652c393a JB |
5373 | dpll = I915_READ(dpll_reg); |
5374 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 5375 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a JB |
5376 | } |
5377 | ||
5378 | /* Schedule downclock */ | |
3dec0095 DV |
5379 | mod_timer(&intel_crtc->idle_timer, jiffies + |
5380 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
652c393a JB |
5381 | } |
5382 | ||
5383 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
5384 | { | |
5385 | struct drm_device *dev = crtc->dev; | |
5386 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5387 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5388 | int pipe = intel_crtc->pipe; | |
9db4a9c7 | 5389 | int dpll_reg = DPLL(pipe); |
652c393a JB |
5390 | int dpll = I915_READ(dpll_reg); |
5391 | ||
bad720ff | 5392 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
5393 | return; |
5394 | ||
5395 | if (!dev_priv->lvds_downclock_avail) | |
5396 | return; | |
5397 | ||
5398 | /* | |
5399 | * Since this is called by a timer, we should never get here in | |
5400 | * the manual case. | |
5401 | */ | |
5402 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
44d98a61 | 5403 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 5404 | |
8ac5a6d5 | 5405 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
5406 | |
5407 | dpll |= DISPLAY_RATE_SELECT_FPA1; | |
5408 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 5409 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
5410 | dpll = I915_READ(dpll_reg); |
5411 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 5412 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
5413 | } |
5414 | ||
5415 | } | |
5416 | ||
5417 | /** | |
5418 | * intel_idle_update - adjust clocks for idleness | |
5419 | * @work: work struct | |
5420 | * | |
5421 | * Either the GPU or display (or both) went idle. Check the busy status | |
5422 | * here and adjust the CRTC and GPU clocks as necessary. | |
5423 | */ | |
5424 | static void intel_idle_update(struct work_struct *work) | |
5425 | { | |
5426 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
5427 | idle_work); | |
5428 | struct drm_device *dev = dev_priv->dev; | |
5429 | struct drm_crtc *crtc; | |
5430 | struct intel_crtc *intel_crtc; | |
5431 | ||
5432 | if (!i915_powersave) | |
5433 | return; | |
5434 | ||
5435 | mutex_lock(&dev->struct_mutex); | |
5436 | ||
7648fa99 JB |
5437 | i915_update_gfx_val(dev_priv); |
5438 | ||
652c393a JB |
5439 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
5440 | /* Skip inactive CRTCs */ | |
5441 | if (!crtc->fb) | |
5442 | continue; | |
5443 | ||
5444 | intel_crtc = to_intel_crtc(crtc); | |
5445 | if (!intel_crtc->busy) | |
5446 | intel_decrease_pllclock(crtc); | |
5447 | } | |
5448 | ||
45ac22c8 | 5449 | |
652c393a JB |
5450 | mutex_unlock(&dev->struct_mutex); |
5451 | } | |
5452 | ||
5453 | /** | |
5454 | * intel_mark_busy - mark the GPU and possibly the display busy | |
5455 | * @dev: drm device | |
5456 | * @obj: object we're operating on | |
5457 | * | |
5458 | * Callers can use this function to indicate that the GPU is busy processing | |
5459 | * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout | |
5460 | * buffer), we'll also mark the display as busy, so we know to increase its | |
5461 | * clock frequency. | |
5462 | */ | |
05394f39 | 5463 | void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj) |
652c393a JB |
5464 | { |
5465 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5466 | struct drm_crtc *crtc = NULL; | |
5467 | struct intel_framebuffer *intel_fb; | |
5468 | struct intel_crtc *intel_crtc; | |
5469 | ||
5e17ee74 ZW |
5470 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
5471 | return; | |
5472 | ||
18b2190c | 5473 | if (!dev_priv->busy) |
28cf798f | 5474 | dev_priv->busy = true; |
18b2190c | 5475 | else |
28cf798f CW |
5476 | mod_timer(&dev_priv->idle_timer, jiffies + |
5477 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
652c393a JB |
5478 | |
5479 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
5480 | if (!crtc->fb) | |
5481 | continue; | |
5482 | ||
5483 | intel_crtc = to_intel_crtc(crtc); | |
5484 | intel_fb = to_intel_framebuffer(crtc->fb); | |
5485 | if (intel_fb->obj == obj) { | |
5486 | if (!intel_crtc->busy) { | |
5487 | /* Non-busy -> busy, upclock */ | |
3dec0095 | 5488 | intel_increase_pllclock(crtc); |
652c393a JB |
5489 | intel_crtc->busy = true; |
5490 | } else { | |
5491 | /* Busy -> busy, put off timer */ | |
5492 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
5493 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
5494 | } | |
5495 | } | |
5496 | } | |
5497 | } | |
5498 | ||
79e53945 JB |
5499 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
5500 | { | |
5501 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
5502 | struct drm_device *dev = crtc->dev; |
5503 | struct intel_unpin_work *work; | |
5504 | unsigned long flags; | |
5505 | ||
5506 | spin_lock_irqsave(&dev->event_lock, flags); | |
5507 | work = intel_crtc->unpin_work; | |
5508 | intel_crtc->unpin_work = NULL; | |
5509 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5510 | ||
5511 | if (work) { | |
5512 | cancel_work_sync(&work->work); | |
5513 | kfree(work); | |
5514 | } | |
79e53945 JB |
5515 | |
5516 | drm_crtc_cleanup(crtc); | |
67e77c5a | 5517 | |
79e53945 JB |
5518 | kfree(intel_crtc); |
5519 | } | |
5520 | ||
6b95a207 KH |
5521 | static void intel_unpin_work_fn(struct work_struct *__work) |
5522 | { | |
5523 | struct intel_unpin_work *work = | |
5524 | container_of(__work, struct intel_unpin_work, work); | |
5525 | ||
5526 | mutex_lock(&work->dev->struct_mutex); | |
1690e1eb | 5527 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
5528 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
5529 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 5530 | |
7782de3b | 5531 | intel_update_fbc(work->dev); |
6b95a207 KH |
5532 | mutex_unlock(&work->dev->struct_mutex); |
5533 | kfree(work); | |
5534 | } | |
5535 | ||
1afe3e9d | 5536 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 5537 | struct drm_crtc *crtc) |
6b95a207 KH |
5538 | { |
5539 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
5540 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5541 | struct intel_unpin_work *work; | |
05394f39 | 5542 | struct drm_i915_gem_object *obj; |
6b95a207 | 5543 | struct drm_pending_vblank_event *e; |
49b14a5c | 5544 | struct timeval tnow, tvbl; |
6b95a207 KH |
5545 | unsigned long flags; |
5546 | ||
5547 | /* Ignore early vblank irqs */ | |
5548 | if (intel_crtc == NULL) | |
5549 | return; | |
5550 | ||
49b14a5c MK |
5551 | do_gettimeofday(&tnow); |
5552 | ||
6b95a207 KH |
5553 | spin_lock_irqsave(&dev->event_lock, flags); |
5554 | work = intel_crtc->unpin_work; | |
5555 | if (work == NULL || !work->pending) { | |
5556 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5557 | return; | |
5558 | } | |
5559 | ||
5560 | intel_crtc->unpin_work = NULL; | |
6b95a207 KH |
5561 | |
5562 | if (work->event) { | |
5563 | e = work->event; | |
49b14a5c | 5564 | e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl); |
0af7e4df MK |
5565 | |
5566 | /* Called before vblank count and timestamps have | |
5567 | * been updated for the vblank interval of flip | |
5568 | * completion? Need to increment vblank count and | |
5569 | * add one videorefresh duration to returned timestamp | |
49b14a5c MK |
5570 | * to account for this. We assume this happened if we |
5571 | * get called over 0.9 frame durations after the last | |
5572 | * timestamped vblank. | |
5573 | * | |
5574 | * This calculation can not be used with vrefresh rates | |
5575 | * below 5Hz (10Hz to be on the safe side) without | |
5576 | * promoting to 64 integers. | |
0af7e4df | 5577 | */ |
49b14a5c MK |
5578 | if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) > |
5579 | 9 * crtc->framedur_ns) { | |
0af7e4df | 5580 | e->event.sequence++; |
49b14a5c MK |
5581 | tvbl = ns_to_timeval(timeval_to_ns(&tvbl) + |
5582 | crtc->framedur_ns); | |
0af7e4df MK |
5583 | } |
5584 | ||
49b14a5c MK |
5585 | e->event.tv_sec = tvbl.tv_sec; |
5586 | e->event.tv_usec = tvbl.tv_usec; | |
0af7e4df | 5587 | |
6b95a207 KH |
5588 | list_add_tail(&e->base.link, |
5589 | &e->base.file_priv->event_list); | |
5590 | wake_up_interruptible(&e->base.file_priv->event_wait); | |
5591 | } | |
5592 | ||
0af7e4df MK |
5593 | drm_vblank_put(dev, intel_crtc->pipe); |
5594 | ||
6b95a207 KH |
5595 | spin_unlock_irqrestore(&dev->event_lock, flags); |
5596 | ||
05394f39 | 5597 | obj = work->old_fb_obj; |
d9e86c0e | 5598 | |
e59f2bac | 5599 | atomic_clear_mask(1 << intel_crtc->plane, |
05394f39 CW |
5600 | &obj->pending_flip.counter); |
5601 | if (atomic_read(&obj->pending_flip) == 0) | |
f787a5f5 | 5602 | wake_up(&dev_priv->pending_flip_queue); |
d9e86c0e | 5603 | |
6b95a207 | 5604 | schedule_work(&work->work); |
e5510fac JB |
5605 | |
5606 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
5607 | } |
5608 | ||
1afe3e9d JB |
5609 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
5610 | { | |
5611 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5612 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
5613 | ||
49b14a5c | 5614 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
5615 | } |
5616 | ||
5617 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
5618 | { | |
5619 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5620 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
5621 | ||
49b14a5c | 5622 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
5623 | } |
5624 | ||
6b95a207 KH |
5625 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
5626 | { | |
5627 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5628 | struct intel_crtc *intel_crtc = | |
5629 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
5630 | unsigned long flags; | |
5631 | ||
5632 | spin_lock_irqsave(&dev->event_lock, flags); | |
de3f440f | 5633 | if (intel_crtc->unpin_work) { |
4e5359cd SF |
5634 | if ((++intel_crtc->unpin_work->pending) > 1) |
5635 | DRM_ERROR("Prepared flip multiple times\n"); | |
de3f440f JB |
5636 | } else { |
5637 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); | |
5638 | } | |
6b95a207 KH |
5639 | spin_unlock_irqrestore(&dev->event_lock, flags); |
5640 | } | |
5641 | ||
8c9f3aaf JB |
5642 | static int intel_gen2_queue_flip(struct drm_device *dev, |
5643 | struct drm_crtc *crtc, | |
5644 | struct drm_framebuffer *fb, | |
5645 | struct drm_i915_gem_object *obj) | |
5646 | { | |
5647 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5648 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5649 | unsigned long offset; | |
5650 | u32 flip_mask; | |
5651 | int ret; | |
5652 | ||
5653 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
5654 | if (ret) | |
83d4092b | 5655 | goto err; |
8c9f3aaf JB |
5656 | |
5657 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ | |
01f2c773 | 5658 | offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; |
8c9f3aaf JB |
5659 | |
5660 | ret = BEGIN_LP_RING(6); | |
5661 | if (ret) | |
83d4092b | 5662 | goto err_unpin; |
8c9f3aaf JB |
5663 | |
5664 | /* Can't queue multiple flips, so wait for the previous | |
5665 | * one to finish before executing the next. | |
5666 | */ | |
5667 | if (intel_crtc->plane) | |
5668 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
5669 | else | |
5670 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
5671 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
5672 | OUT_RING(MI_NOOP); | |
5673 | OUT_RING(MI_DISPLAY_FLIP | | |
5674 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
01f2c773 | 5675 | OUT_RING(fb->pitches[0]); |
8c9f3aaf | 5676 | OUT_RING(obj->gtt_offset + offset); |
c6a32fcb | 5677 | OUT_RING(0); /* aux display base address, unused */ |
8c9f3aaf | 5678 | ADVANCE_LP_RING(); |
83d4092b CW |
5679 | return 0; |
5680 | ||
5681 | err_unpin: | |
5682 | intel_unpin_fb_obj(obj); | |
5683 | err: | |
8c9f3aaf JB |
5684 | return ret; |
5685 | } | |
5686 | ||
5687 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
5688 | struct drm_crtc *crtc, | |
5689 | struct drm_framebuffer *fb, | |
5690 | struct drm_i915_gem_object *obj) | |
5691 | { | |
5692 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5693 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5694 | unsigned long offset; | |
5695 | u32 flip_mask; | |
5696 | int ret; | |
5697 | ||
5698 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
5699 | if (ret) | |
83d4092b | 5700 | goto err; |
8c9f3aaf JB |
5701 | |
5702 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ | |
01f2c773 | 5703 | offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; |
8c9f3aaf JB |
5704 | |
5705 | ret = BEGIN_LP_RING(6); | |
5706 | if (ret) | |
83d4092b | 5707 | goto err_unpin; |
8c9f3aaf JB |
5708 | |
5709 | if (intel_crtc->plane) | |
5710 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
5711 | else | |
5712 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
5713 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
5714 | OUT_RING(MI_NOOP); | |
5715 | OUT_RING(MI_DISPLAY_FLIP_I915 | | |
5716 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
01f2c773 | 5717 | OUT_RING(fb->pitches[0]); |
8c9f3aaf JB |
5718 | OUT_RING(obj->gtt_offset + offset); |
5719 | OUT_RING(MI_NOOP); | |
5720 | ||
5721 | ADVANCE_LP_RING(); | |
83d4092b CW |
5722 | return 0; |
5723 | ||
5724 | err_unpin: | |
5725 | intel_unpin_fb_obj(obj); | |
5726 | err: | |
8c9f3aaf JB |
5727 | return ret; |
5728 | } | |
5729 | ||
5730 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
5731 | struct drm_crtc *crtc, | |
5732 | struct drm_framebuffer *fb, | |
5733 | struct drm_i915_gem_object *obj) | |
5734 | { | |
5735 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5736 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5737 | uint32_t pf, pipesrc; | |
5738 | int ret; | |
5739 | ||
5740 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
5741 | if (ret) | |
83d4092b | 5742 | goto err; |
8c9f3aaf JB |
5743 | |
5744 | ret = BEGIN_LP_RING(4); | |
5745 | if (ret) | |
83d4092b | 5746 | goto err_unpin; |
8c9f3aaf JB |
5747 | |
5748 | /* i965+ uses the linear or tiled offsets from the | |
5749 | * Display Registers (which do not change across a page-flip) | |
5750 | * so we need only reprogram the base address. | |
5751 | */ | |
5752 | OUT_RING(MI_DISPLAY_FLIP | | |
5753 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
01f2c773 | 5754 | OUT_RING(fb->pitches[0]); |
8c9f3aaf JB |
5755 | OUT_RING(obj->gtt_offset | obj->tiling_mode); |
5756 | ||
5757 | /* XXX Enabling the panel-fitter across page-flip is so far | |
5758 | * untested on non-native modes, so ignore it for now. | |
5759 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
5760 | */ | |
5761 | pf = 0; | |
5762 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
5763 | OUT_RING(pf | pipesrc); | |
5764 | ADVANCE_LP_RING(); | |
83d4092b CW |
5765 | return 0; |
5766 | ||
5767 | err_unpin: | |
5768 | intel_unpin_fb_obj(obj); | |
5769 | err: | |
8c9f3aaf JB |
5770 | return ret; |
5771 | } | |
5772 | ||
5773 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
5774 | struct drm_crtc *crtc, | |
5775 | struct drm_framebuffer *fb, | |
5776 | struct drm_i915_gem_object *obj) | |
5777 | { | |
5778 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5779 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5780 | uint32_t pf, pipesrc; | |
5781 | int ret; | |
5782 | ||
5783 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
5784 | if (ret) | |
83d4092b | 5785 | goto err; |
8c9f3aaf JB |
5786 | |
5787 | ret = BEGIN_LP_RING(4); | |
5788 | if (ret) | |
83d4092b | 5789 | goto err_unpin; |
8c9f3aaf JB |
5790 | |
5791 | OUT_RING(MI_DISPLAY_FLIP | | |
5792 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
01f2c773 | 5793 | OUT_RING(fb->pitches[0] | obj->tiling_mode); |
8c9f3aaf JB |
5794 | OUT_RING(obj->gtt_offset); |
5795 | ||
5796 | pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
5797 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
5798 | OUT_RING(pf | pipesrc); | |
5799 | ADVANCE_LP_RING(); | |
83d4092b CW |
5800 | return 0; |
5801 | ||
5802 | err_unpin: | |
5803 | intel_unpin_fb_obj(obj); | |
5804 | err: | |
8c9f3aaf JB |
5805 | return ret; |
5806 | } | |
5807 | ||
7c9017e5 JB |
5808 | /* |
5809 | * On gen7 we currently use the blit ring because (in early silicon at least) | |
5810 | * the render ring doesn't give us interrpts for page flip completion, which | |
5811 | * means clients will hang after the first flip is queued. Fortunately the | |
5812 | * blit ring generates interrupts properly, so use it instead. | |
5813 | */ | |
5814 | static int intel_gen7_queue_flip(struct drm_device *dev, | |
5815 | struct drm_crtc *crtc, | |
5816 | struct drm_framebuffer *fb, | |
5817 | struct drm_i915_gem_object *obj) | |
5818 | { | |
5819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5820 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5821 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; | |
5822 | int ret; | |
5823 | ||
5824 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
5825 | if (ret) | |
83d4092b | 5826 | goto err; |
7c9017e5 JB |
5827 | |
5828 | ret = intel_ring_begin(ring, 4); | |
5829 | if (ret) | |
83d4092b | 5830 | goto err_unpin; |
7c9017e5 JB |
5831 | |
5832 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19)); | |
01f2c773 | 5833 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
7c9017e5 JB |
5834 | intel_ring_emit(ring, (obj->gtt_offset)); |
5835 | intel_ring_emit(ring, (MI_NOOP)); | |
5836 | intel_ring_advance(ring); | |
83d4092b CW |
5837 | return 0; |
5838 | ||
5839 | err_unpin: | |
5840 | intel_unpin_fb_obj(obj); | |
5841 | err: | |
7c9017e5 JB |
5842 | return ret; |
5843 | } | |
5844 | ||
8c9f3aaf JB |
5845 | static int intel_default_queue_flip(struct drm_device *dev, |
5846 | struct drm_crtc *crtc, | |
5847 | struct drm_framebuffer *fb, | |
5848 | struct drm_i915_gem_object *obj) | |
5849 | { | |
5850 | return -ENODEV; | |
5851 | } | |
5852 | ||
6b95a207 KH |
5853 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
5854 | struct drm_framebuffer *fb, | |
5855 | struct drm_pending_vblank_event *event) | |
5856 | { | |
5857 | struct drm_device *dev = crtc->dev; | |
5858 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5859 | struct intel_framebuffer *intel_fb; | |
05394f39 | 5860 | struct drm_i915_gem_object *obj; |
6b95a207 KH |
5861 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5862 | struct intel_unpin_work *work; | |
8c9f3aaf | 5863 | unsigned long flags; |
52e68630 | 5864 | int ret; |
6b95a207 KH |
5865 | |
5866 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
5867 | if (work == NULL) | |
5868 | return -ENOMEM; | |
5869 | ||
6b95a207 KH |
5870 | work->event = event; |
5871 | work->dev = crtc->dev; | |
5872 | intel_fb = to_intel_framebuffer(crtc->fb); | |
b1b87f6b | 5873 | work->old_fb_obj = intel_fb->obj; |
6b95a207 KH |
5874 | INIT_WORK(&work->work, intel_unpin_work_fn); |
5875 | ||
7317c75e JB |
5876 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
5877 | if (ret) | |
5878 | goto free_work; | |
5879 | ||
6b95a207 KH |
5880 | /* We borrow the event spin lock for protecting unpin_work */ |
5881 | spin_lock_irqsave(&dev->event_lock, flags); | |
5882 | if (intel_crtc->unpin_work) { | |
5883 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5884 | kfree(work); | |
7317c75e | 5885 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
5886 | |
5887 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
5888 | return -EBUSY; |
5889 | } | |
5890 | intel_crtc->unpin_work = work; | |
5891 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5892 | ||
5893 | intel_fb = to_intel_framebuffer(fb); | |
5894 | obj = intel_fb->obj; | |
5895 | ||
468f0b44 | 5896 | mutex_lock(&dev->struct_mutex); |
6b95a207 | 5897 | |
75dfca80 | 5898 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
5899 | drm_gem_object_reference(&work->old_fb_obj->base); |
5900 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
5901 | |
5902 | crtc->fb = fb; | |
96b099fd | 5903 | |
e1f99ce6 | 5904 | work->pending_flip_obj = obj; |
e1f99ce6 | 5905 | |
4e5359cd SF |
5906 | work->enable_stall_check = true; |
5907 | ||
e1f99ce6 CW |
5908 | /* Block clients from rendering to the new back buffer until |
5909 | * the flip occurs and the object is no longer visible. | |
5910 | */ | |
05394f39 | 5911 | atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
e1f99ce6 | 5912 | |
8c9f3aaf JB |
5913 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); |
5914 | if (ret) | |
5915 | goto cleanup_pending; | |
6b95a207 | 5916 | |
7782de3b | 5917 | intel_disable_fbc(dev); |
6b95a207 KH |
5918 | mutex_unlock(&dev->struct_mutex); |
5919 | ||
e5510fac JB |
5920 | trace_i915_flip_request(intel_crtc->plane, obj); |
5921 | ||
6b95a207 | 5922 | return 0; |
96b099fd | 5923 | |
8c9f3aaf JB |
5924 | cleanup_pending: |
5925 | atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); | |
05394f39 CW |
5926 | drm_gem_object_unreference(&work->old_fb_obj->base); |
5927 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
5928 | mutex_unlock(&dev->struct_mutex); |
5929 | ||
5930 | spin_lock_irqsave(&dev->event_lock, flags); | |
5931 | intel_crtc->unpin_work = NULL; | |
5932 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
5933 | ||
7317c75e JB |
5934 | drm_vblank_put(dev, intel_crtc->pipe); |
5935 | free_work: | |
96b099fd CW |
5936 | kfree(work); |
5937 | ||
5938 | return ret; | |
6b95a207 KH |
5939 | } |
5940 | ||
47f1c6c9 CW |
5941 | static void intel_sanitize_modesetting(struct drm_device *dev, |
5942 | int pipe, int plane) | |
5943 | { | |
5944 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5945 | u32 reg, val; | |
5946 | ||
f47166d2 CW |
5947 | /* Clear any frame start delays used for debugging left by the BIOS */ |
5948 | for_each_pipe(pipe) { | |
5949 | reg = PIPECONF(pipe); | |
5950 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
5951 | } | |
5952 | ||
47f1c6c9 CW |
5953 | if (HAS_PCH_SPLIT(dev)) |
5954 | return; | |
5955 | ||
5956 | /* Who knows what state these registers were left in by the BIOS or | |
5957 | * grub? | |
5958 | * | |
5959 | * If we leave the registers in a conflicting state (e.g. with the | |
5960 | * display plane reading from the other pipe than the one we intend | |
5961 | * to use) then when we attempt to teardown the active mode, we will | |
5962 | * not disable the pipes and planes in the correct order -- leaving | |
5963 | * a plane reading from a disabled pipe and possibly leading to | |
5964 | * undefined behaviour. | |
5965 | */ | |
5966 | ||
5967 | reg = DSPCNTR(plane); | |
5968 | val = I915_READ(reg); | |
5969 | ||
5970 | if ((val & DISPLAY_PLANE_ENABLE) == 0) | |
5971 | return; | |
5972 | if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe) | |
5973 | return; | |
5974 | ||
5975 | /* This display plane is active and attached to the other CPU pipe. */ | |
5976 | pipe = !pipe; | |
5977 | ||
5978 | /* Disable the plane and wait for it to stop reading from the pipe. */ | |
b24e7179 JB |
5979 | intel_disable_plane(dev_priv, plane, pipe); |
5980 | intel_disable_pipe(dev_priv, pipe); | |
47f1c6c9 | 5981 | } |
79e53945 | 5982 | |
f6e5b160 CW |
5983 | static void intel_crtc_reset(struct drm_crtc *crtc) |
5984 | { | |
5985 | struct drm_device *dev = crtc->dev; | |
5986 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5987 | ||
5988 | /* Reset flags back to the 'unknown' status so that they | |
5989 | * will be correctly set on the initial modeset. | |
5990 | */ | |
5991 | intel_crtc->dpms_mode = -1; | |
5992 | ||
5993 | /* We need to fix up any BIOS configuration that conflicts with | |
5994 | * our expectations. | |
5995 | */ | |
5996 | intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane); | |
5997 | } | |
5998 | ||
5999 | static struct drm_crtc_helper_funcs intel_helper_funcs = { | |
6000 | .dpms = intel_crtc_dpms, | |
6001 | .mode_fixup = intel_crtc_mode_fixup, | |
6002 | .mode_set = intel_crtc_mode_set, | |
6003 | .mode_set_base = intel_pipe_set_base, | |
6004 | .mode_set_base_atomic = intel_pipe_set_base_atomic, | |
6005 | .load_lut = intel_crtc_load_lut, | |
6006 | .disable = intel_crtc_disable, | |
6007 | }; | |
6008 | ||
6009 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
6010 | .reset = intel_crtc_reset, | |
6011 | .cursor_set = intel_crtc_cursor_set, | |
6012 | .cursor_move = intel_crtc_cursor_move, | |
6013 | .gamma_set = intel_crtc_gamma_set, | |
6014 | .set_config = drm_crtc_helper_set_config, | |
6015 | .destroy = intel_crtc_destroy, | |
6016 | .page_flip = intel_crtc_page_flip, | |
6017 | }; | |
6018 | ||
b358d0a6 | 6019 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 6020 | { |
22fd0fab | 6021 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
6022 | struct intel_crtc *intel_crtc; |
6023 | int i; | |
6024 | ||
6025 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
6026 | if (intel_crtc == NULL) | |
6027 | return; | |
6028 | ||
6029 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
6030 | ||
6031 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
6032 | for (i = 0; i < 256; i++) { |
6033 | intel_crtc->lut_r[i] = i; | |
6034 | intel_crtc->lut_g[i] = i; | |
6035 | intel_crtc->lut_b[i] = i; | |
6036 | } | |
6037 | ||
80824003 JB |
6038 | /* Swap pipes & planes for FBC on pre-965 */ |
6039 | intel_crtc->pipe = pipe; | |
6040 | intel_crtc->plane = pipe; | |
e2e767ab | 6041 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 6042 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 6043 | intel_crtc->plane = !pipe; |
80824003 JB |
6044 | } |
6045 | ||
22fd0fab JB |
6046 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
6047 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
6048 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
6049 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
6050 | ||
5d1d0cc8 | 6051 | intel_crtc_reset(&intel_crtc->base); |
04dbff52 | 6052 | intel_crtc->active = true; /* force the pipe off on setup_init_config */ |
5a354204 | 6053 | intel_crtc->bpp = 24; /* default for pre-Ironlake */ |
7e7d76c3 JB |
6054 | |
6055 | if (HAS_PCH_SPLIT(dev)) { | |
4b645f14 JB |
6056 | if (pipe == 2 && IS_IVYBRIDGE(dev)) |
6057 | intel_crtc->no_pll = true; | |
7e7d76c3 JB |
6058 | intel_helper_funcs.prepare = ironlake_crtc_prepare; |
6059 | intel_helper_funcs.commit = ironlake_crtc_commit; | |
6060 | } else { | |
6061 | intel_helper_funcs.prepare = i9xx_crtc_prepare; | |
6062 | intel_helper_funcs.commit = i9xx_crtc_commit; | |
6063 | } | |
6064 | ||
79e53945 JB |
6065 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
6066 | ||
652c393a JB |
6067 | intel_crtc->busy = false; |
6068 | ||
6069 | setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, | |
6070 | (unsigned long)intel_crtc); | |
79e53945 JB |
6071 | } |
6072 | ||
08d7b3d1 | 6073 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 6074 | struct drm_file *file) |
08d7b3d1 CW |
6075 | { |
6076 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6077 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; | |
c05422d5 DV |
6078 | struct drm_mode_object *drmmode_obj; |
6079 | struct intel_crtc *crtc; | |
08d7b3d1 CW |
6080 | |
6081 | if (!dev_priv) { | |
6082 | DRM_ERROR("called with no initialization\n"); | |
6083 | return -EINVAL; | |
6084 | } | |
6085 | ||
c05422d5 DV |
6086 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
6087 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 6088 | |
c05422d5 | 6089 | if (!drmmode_obj) { |
08d7b3d1 CW |
6090 | DRM_ERROR("no such CRTC id\n"); |
6091 | return -EINVAL; | |
6092 | } | |
6093 | ||
c05422d5 DV |
6094 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
6095 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 6096 | |
c05422d5 | 6097 | return 0; |
08d7b3d1 CW |
6098 | } |
6099 | ||
c5e4df33 | 6100 | static int intel_encoder_clones(struct drm_device *dev, int type_mask) |
79e53945 | 6101 | { |
4ef69c7a | 6102 | struct intel_encoder *encoder; |
79e53945 | 6103 | int index_mask = 0; |
79e53945 JB |
6104 | int entry = 0; |
6105 | ||
4ef69c7a CW |
6106 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
6107 | if (type_mask & encoder->clone_mask) | |
79e53945 JB |
6108 | index_mask |= (1 << entry); |
6109 | entry++; | |
6110 | } | |
4ef69c7a | 6111 | |
79e53945 JB |
6112 | return index_mask; |
6113 | } | |
6114 | ||
4d302442 CW |
6115 | static bool has_edp_a(struct drm_device *dev) |
6116 | { | |
6117 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6118 | ||
6119 | if (!IS_MOBILE(dev)) | |
6120 | return false; | |
6121 | ||
6122 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
6123 | return false; | |
6124 | ||
6125 | if (IS_GEN5(dev) && | |
6126 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
6127 | return false; | |
6128 | ||
6129 | return true; | |
6130 | } | |
6131 | ||
79e53945 JB |
6132 | static void intel_setup_outputs(struct drm_device *dev) |
6133 | { | |
725e30ad | 6134 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 6135 | struct intel_encoder *encoder; |
cb0953d7 | 6136 | bool dpd_is_edp = false; |
f3cfcba6 | 6137 | bool has_lvds; |
79e53945 | 6138 | |
f3cfcba6 | 6139 | has_lvds = intel_lvds_init(dev); |
c5d1b51d CW |
6140 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { |
6141 | /* disable the panel fitter on everything but LVDS */ | |
6142 | I915_WRITE(PFIT_CONTROL, 0); | |
6143 | } | |
79e53945 | 6144 | |
bad720ff | 6145 | if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 6146 | dpd_is_edp = intel_dpd_is_edp(dev); |
30ad48b7 | 6147 | |
4d302442 | 6148 | if (has_edp_a(dev)) |
32f9d658 ZW |
6149 | intel_dp_init(dev, DP_A); |
6150 | ||
cb0953d7 AJ |
6151 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
6152 | intel_dp_init(dev, PCH_DP_D); | |
6153 | } | |
6154 | ||
6155 | intel_crt_init(dev); | |
6156 | ||
6157 | if (HAS_PCH_SPLIT(dev)) { | |
6158 | int found; | |
6159 | ||
30ad48b7 | 6160 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
461ed3ca | 6161 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 6162 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 ZW |
6163 | if (!found) |
6164 | intel_hdmi_init(dev, HDMIB); | |
5eb08b69 ZW |
6165 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
6166 | intel_dp_init(dev, PCH_DP_B); | |
30ad48b7 ZW |
6167 | } |
6168 | ||
6169 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
6170 | intel_hdmi_init(dev, HDMIC); | |
6171 | ||
6172 | if (I915_READ(HDMID) & PORT_DETECTED) | |
6173 | intel_hdmi_init(dev, HDMID); | |
6174 | ||
5eb08b69 ZW |
6175 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
6176 | intel_dp_init(dev, PCH_DP_C); | |
6177 | ||
cb0953d7 | 6178 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5eb08b69 ZW |
6179 | intel_dp_init(dev, PCH_DP_D); |
6180 | ||
103a196f | 6181 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 6182 | bool found = false; |
7d57382e | 6183 | |
725e30ad | 6184 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 6185 | DRM_DEBUG_KMS("probing SDVOB\n"); |
eef4eacb | 6186 | found = intel_sdvo_init(dev, SDVOB, true); |
b01f2c3a JB |
6187 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
6188 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
725e30ad | 6189 | intel_hdmi_init(dev, SDVOB); |
b01f2c3a | 6190 | } |
27185ae1 | 6191 | |
b01f2c3a JB |
6192 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
6193 | DRM_DEBUG_KMS("probing DP_B\n"); | |
a4fc5ed6 | 6194 | intel_dp_init(dev, DP_B); |
b01f2c3a | 6195 | } |
725e30ad | 6196 | } |
13520b05 KH |
6197 | |
6198 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 6199 | |
b01f2c3a JB |
6200 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
6201 | DRM_DEBUG_KMS("probing SDVOC\n"); | |
eef4eacb | 6202 | found = intel_sdvo_init(dev, SDVOC, false); |
b01f2c3a | 6203 | } |
27185ae1 ML |
6204 | |
6205 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { | |
6206 | ||
b01f2c3a JB |
6207 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
6208 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
725e30ad | 6209 | intel_hdmi_init(dev, SDVOC); |
b01f2c3a JB |
6210 | } |
6211 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
6212 | DRM_DEBUG_KMS("probing DP_C\n"); | |
a4fc5ed6 | 6213 | intel_dp_init(dev, DP_C); |
b01f2c3a | 6214 | } |
725e30ad | 6215 | } |
27185ae1 | 6216 | |
b01f2c3a JB |
6217 | if (SUPPORTS_INTEGRATED_DP(dev) && |
6218 | (I915_READ(DP_D) & DP_DETECTED)) { | |
6219 | DRM_DEBUG_KMS("probing DP_D\n"); | |
a4fc5ed6 | 6220 | intel_dp_init(dev, DP_D); |
b01f2c3a | 6221 | } |
bad720ff | 6222 | } else if (IS_GEN2(dev)) |
79e53945 JB |
6223 | intel_dvo_init(dev); |
6224 | ||
103a196f | 6225 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
6226 | intel_tv_init(dev); |
6227 | ||
4ef69c7a CW |
6228 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
6229 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
6230 | encoder->base.possible_clones = | |
6231 | intel_encoder_clones(dev, encoder->clone_mask); | |
79e53945 | 6232 | } |
47356eb6 | 6233 | |
2c7111db CW |
6234 | /* disable all the possible outputs/crtcs before entering KMS mode */ |
6235 | drm_helper_disable_unused_functions(dev); | |
9fb526db KP |
6236 | |
6237 | if (HAS_PCH_SPLIT(dev)) | |
6238 | ironlake_init_pch_refclk(dev); | |
79e53945 JB |
6239 | } |
6240 | ||
6241 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
6242 | { | |
6243 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
6244 | |
6245 | drm_framebuffer_cleanup(fb); | |
05394f39 | 6246 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
79e53945 JB |
6247 | |
6248 | kfree(intel_fb); | |
6249 | } | |
6250 | ||
6251 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 6252 | struct drm_file *file, |
79e53945 JB |
6253 | unsigned int *handle) |
6254 | { | |
6255 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 6256 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 6257 | |
05394f39 | 6258 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
6259 | } |
6260 | ||
6261 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
6262 | .destroy = intel_user_framebuffer_destroy, | |
6263 | .create_handle = intel_user_framebuffer_create_handle, | |
6264 | }; | |
6265 | ||
38651674 DA |
6266 | int intel_framebuffer_init(struct drm_device *dev, |
6267 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 6268 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 6269 | struct drm_i915_gem_object *obj) |
79e53945 | 6270 | { |
79e53945 JB |
6271 | int ret; |
6272 | ||
05394f39 | 6273 | if (obj->tiling_mode == I915_TILING_Y) |
57cd6508 CW |
6274 | return -EINVAL; |
6275 | ||
308e5bcb | 6276 | if (mode_cmd->pitches[0] & 63) |
57cd6508 CW |
6277 | return -EINVAL; |
6278 | ||
308e5bcb | 6279 | switch (mode_cmd->pixel_format) { |
04b3924d VS |
6280 | case DRM_FORMAT_RGB332: |
6281 | case DRM_FORMAT_RGB565: | |
6282 | case DRM_FORMAT_XRGB8888: | |
b250da79 | 6283 | case DRM_FORMAT_XBGR8888: |
04b3924d VS |
6284 | case DRM_FORMAT_ARGB8888: |
6285 | case DRM_FORMAT_XRGB2101010: | |
6286 | case DRM_FORMAT_ARGB2101010: | |
308e5bcb | 6287 | /* RGB formats are common across chipsets */ |
b5626747 | 6288 | break; |
04b3924d VS |
6289 | case DRM_FORMAT_YUYV: |
6290 | case DRM_FORMAT_UYVY: | |
6291 | case DRM_FORMAT_YVYU: | |
6292 | case DRM_FORMAT_VYUY: | |
57cd6508 CW |
6293 | break; |
6294 | default: | |
aca25848 ED |
6295 | DRM_DEBUG_KMS("unsupported pixel format %u\n", |
6296 | mode_cmd->pixel_format); | |
57cd6508 CW |
6297 | return -EINVAL; |
6298 | } | |
6299 | ||
79e53945 JB |
6300 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
6301 | if (ret) { | |
6302 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
6303 | return ret; | |
6304 | } | |
6305 | ||
6306 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
79e53945 | 6307 | intel_fb->obj = obj; |
79e53945 JB |
6308 | return 0; |
6309 | } | |
6310 | ||
79e53945 JB |
6311 | static struct drm_framebuffer * |
6312 | intel_user_framebuffer_create(struct drm_device *dev, | |
6313 | struct drm_file *filp, | |
308e5bcb | 6314 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 6315 | { |
05394f39 | 6316 | struct drm_i915_gem_object *obj; |
79e53945 | 6317 | |
308e5bcb JB |
6318 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
6319 | mode_cmd->handles[0])); | |
c8725226 | 6320 | if (&obj->base == NULL) |
cce13ff7 | 6321 | return ERR_PTR(-ENOENT); |
79e53945 | 6322 | |
d2dff872 | 6323 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
6324 | } |
6325 | ||
79e53945 | 6326 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 6327 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 6328 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
6329 | }; |
6330 | ||
e70236a8 JB |
6331 | /* Set up chip specific display functions */ |
6332 | static void intel_init_display(struct drm_device *dev) | |
6333 | { | |
6334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6335 | ||
6336 | /* We always want a DPMS function */ | |
f564048e | 6337 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 6338 | dev_priv->display.dpms = ironlake_crtc_dpms; |
f564048e | 6339 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
17638cd6 | 6340 | dev_priv->display.update_plane = ironlake_update_plane; |
f564048e | 6341 | } else { |
e70236a8 | 6342 | dev_priv->display.dpms = i9xx_crtc_dpms; |
f564048e | 6343 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
17638cd6 | 6344 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 6345 | } |
e70236a8 | 6346 | |
e70236a8 | 6347 | /* Returns the core display clock speed */ |
25eb05fc JB |
6348 | if (IS_VALLEYVIEW(dev)) |
6349 | dev_priv->display.get_display_clock_speed = | |
6350 | valleyview_get_display_clock_speed; | |
6351 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
6352 | dev_priv->display.get_display_clock_speed = |
6353 | i945_get_display_clock_speed; | |
6354 | else if (IS_I915G(dev)) | |
6355 | dev_priv->display.get_display_clock_speed = | |
6356 | i915_get_display_clock_speed; | |
f2b115e6 | 6357 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
6358 | dev_priv->display.get_display_clock_speed = |
6359 | i9xx_misc_get_display_clock_speed; | |
6360 | else if (IS_I915GM(dev)) | |
6361 | dev_priv->display.get_display_clock_speed = | |
6362 | i915gm_get_display_clock_speed; | |
6363 | else if (IS_I865G(dev)) | |
6364 | dev_priv->display.get_display_clock_speed = | |
6365 | i865_get_display_clock_speed; | |
f0f8a9ce | 6366 | else if (IS_I85X(dev)) |
e70236a8 JB |
6367 | dev_priv->display.get_display_clock_speed = |
6368 | i855_get_display_clock_speed; | |
6369 | else /* 852, 830 */ | |
6370 | dev_priv->display.get_display_clock_speed = | |
6371 | i830_get_display_clock_speed; | |
6372 | ||
7f8a8569 | 6373 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 6374 | if (IS_GEN5(dev)) { |
674cf967 | 6375 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 6376 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 6377 | } else if (IS_GEN6(dev)) { |
674cf967 | 6378 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 6379 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
6380 | } else if (IS_IVYBRIDGE(dev)) { |
6381 | /* FIXME: detect B0+ stepping and use auto training */ | |
6382 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 6383 | dev_priv->display.write_eld = ironlake_write_eld; |
7f8a8569 ZW |
6384 | } else |
6385 | dev_priv->display.update_wm = NULL; | |
ceb04246 | 6386 | } else if (IS_VALLEYVIEW(dev)) { |
575155a9 JB |
6387 | dev_priv->display.force_wake_get = vlv_force_wake_get; |
6388 | dev_priv->display.force_wake_put = vlv_force_wake_put; | |
6067aaea | 6389 | } else if (IS_G4X(dev)) { |
e0dac65e | 6390 | dev_priv->display.write_eld = g4x_write_eld; |
e70236a8 | 6391 | } |
8c9f3aaf JB |
6392 | |
6393 | /* Default just returns -ENODEV to indicate unsupported */ | |
6394 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
6395 | ||
6396 | switch (INTEL_INFO(dev)->gen) { | |
6397 | case 2: | |
6398 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
6399 | break; | |
6400 | ||
6401 | case 3: | |
6402 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
6403 | break; | |
6404 | ||
6405 | case 4: | |
6406 | case 5: | |
6407 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
6408 | break; | |
6409 | ||
6410 | case 6: | |
6411 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
6412 | break; | |
7c9017e5 JB |
6413 | case 7: |
6414 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
6415 | break; | |
8c9f3aaf | 6416 | } |
e70236a8 JB |
6417 | } |
6418 | ||
b690e96c JB |
6419 | /* |
6420 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
6421 | * resume, or other times. This quirk makes sure that's the case for | |
6422 | * affected systems. | |
6423 | */ | |
0206e353 | 6424 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
6425 | { |
6426 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6427 | ||
6428 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 6429 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
6430 | } |
6431 | ||
435793df KP |
6432 | /* |
6433 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
6434 | */ | |
6435 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
6436 | { | |
6437 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6438 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 6439 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
6440 | } |
6441 | ||
4dca20ef | 6442 | /* |
5a15ab5b CE |
6443 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
6444 | * brightness value | |
4dca20ef CE |
6445 | */ |
6446 | static void quirk_invert_brightness(struct drm_device *dev) | |
6447 | { | |
6448 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6449 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 6450 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
6451 | } |
6452 | ||
b690e96c JB |
6453 | struct intel_quirk { |
6454 | int device; | |
6455 | int subsystem_vendor; | |
6456 | int subsystem_device; | |
6457 | void (*hook)(struct drm_device *dev); | |
6458 | }; | |
6459 | ||
c43b5634 | 6460 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 6461 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 6462 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c JB |
6463 | |
6464 | /* Thinkpad R31 needs pipe A force quirk */ | |
6465 | { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, | |
6466 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ | |
6467 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
6468 | ||
6469 | /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ | |
6470 | { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, | |
6471 | /* ThinkPad X40 needs pipe A force quirk */ | |
6472 | ||
6473 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ | |
6474 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
6475 | ||
6476 | /* 855 & before need to leave pipe A & dpll A up */ | |
6477 | { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
6478 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
435793df KP |
6479 | |
6480 | /* Lenovo U160 cannot use SSC on LVDS */ | |
6481 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
6482 | |
6483 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
6484 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b CE |
6485 | |
6486 | /* Acer Aspire 5734Z must invert backlight brightness */ | |
6487 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
b690e96c JB |
6488 | }; |
6489 | ||
6490 | static void intel_init_quirks(struct drm_device *dev) | |
6491 | { | |
6492 | struct pci_dev *d = dev->pdev; | |
6493 | int i; | |
6494 | ||
6495 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
6496 | struct intel_quirk *q = &intel_quirks[i]; | |
6497 | ||
6498 | if (d->device == q->device && | |
6499 | (d->subsystem_vendor == q->subsystem_vendor || | |
6500 | q->subsystem_vendor == PCI_ANY_ID) && | |
6501 | (d->subsystem_device == q->subsystem_device || | |
6502 | q->subsystem_device == PCI_ANY_ID)) | |
6503 | q->hook(dev); | |
6504 | } | |
6505 | } | |
6506 | ||
9cce37f4 JB |
6507 | /* Disable the VGA plane that we never use */ |
6508 | static void i915_disable_vga(struct drm_device *dev) | |
6509 | { | |
6510 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6511 | u8 sr1; | |
6512 | u32 vga_reg; | |
6513 | ||
6514 | if (HAS_PCH_SPLIT(dev)) | |
6515 | vga_reg = CPU_VGACNTRL; | |
6516 | else | |
6517 | vga_reg = VGACNTRL; | |
6518 | ||
6519 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
3fdcf431 | 6520 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
6521 | sr1 = inb(VGA_SR_DATA); |
6522 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
6523 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
6524 | udelay(300); | |
6525 | ||
6526 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
6527 | POSTING_READ(vga_reg); | |
6528 | } | |
6529 | ||
f82cfb6b JB |
6530 | static void ivb_pch_pwm_override(struct drm_device *dev) |
6531 | { | |
6532 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6533 | ||
6534 | /* | |
6535 | * IVB has CPU eDP backlight regs too, set things up to let the | |
6536 | * PCH regs control the backlight | |
6537 | */ | |
6538 | I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE); | |
6539 | I915_WRITE(BLC_PWM_CPU_CTL, 0); | |
6540 | I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30)); | |
6541 | } | |
6542 | ||
f817586c DV |
6543 | void intel_modeset_init_hw(struct drm_device *dev) |
6544 | { | |
6545 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6546 | ||
6547 | intel_init_clock_gating(dev); | |
6548 | ||
6549 | if (IS_IRONLAKE_M(dev)) { | |
6550 | ironlake_enable_drps(dev); | |
6551 | intel_init_emon(dev); | |
6552 | } | |
6553 | ||
b6834bd6 | 6554 | if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) { |
f817586c DV |
6555 | gen6_enable_rps(dev_priv); |
6556 | gen6_update_ring_freq(dev_priv); | |
6557 | } | |
f82cfb6b JB |
6558 | |
6559 | if (IS_IVYBRIDGE(dev)) | |
6560 | ivb_pch_pwm_override(dev); | |
f817586c DV |
6561 | } |
6562 | ||
79e53945 JB |
6563 | void intel_modeset_init(struct drm_device *dev) |
6564 | { | |
652c393a | 6565 | struct drm_i915_private *dev_priv = dev->dev_private; |
b840d907 | 6566 | int i, ret; |
79e53945 JB |
6567 | |
6568 | drm_mode_config_init(dev); | |
6569 | ||
6570 | dev->mode_config.min_width = 0; | |
6571 | dev->mode_config.min_height = 0; | |
6572 | ||
019d96cb DA |
6573 | dev->mode_config.preferred_depth = 24; |
6574 | dev->mode_config.prefer_shadow = 1; | |
6575 | ||
79e53945 JB |
6576 | dev->mode_config.funcs = (void *)&intel_mode_funcs; |
6577 | ||
b690e96c JB |
6578 | intel_init_quirks(dev); |
6579 | ||
1fa61106 ED |
6580 | intel_init_pm(dev); |
6581 | ||
e70236a8 JB |
6582 | intel_init_display(dev); |
6583 | ||
a6c45cf0 CW |
6584 | if (IS_GEN2(dev)) { |
6585 | dev->mode_config.max_width = 2048; | |
6586 | dev->mode_config.max_height = 2048; | |
6587 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
6588 | dev->mode_config.max_width = 4096; |
6589 | dev->mode_config.max_height = 4096; | |
79e53945 | 6590 | } else { |
a6c45cf0 CW |
6591 | dev->mode_config.max_width = 8192; |
6592 | dev->mode_config.max_height = 8192; | |
79e53945 | 6593 | } |
35c3047a | 6594 | dev->mode_config.fb_base = dev->agp->base; |
79e53945 | 6595 | |
28c97730 | 6596 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
a3524f1b | 6597 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
79e53945 | 6598 | |
a3524f1b | 6599 | for (i = 0; i < dev_priv->num_pipe; i++) { |
79e53945 | 6600 | intel_crtc_init(dev, i); |
00c2064b JB |
6601 | ret = intel_plane_init(dev, i); |
6602 | if (ret) | |
6603 | DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); | |
79e53945 JB |
6604 | } |
6605 | ||
9cce37f4 JB |
6606 | /* Just disable it once at startup */ |
6607 | i915_disable_vga(dev); | |
79e53945 | 6608 | intel_setup_outputs(dev); |
652c393a | 6609 | |
f817586c | 6610 | intel_modeset_init_hw(dev); |
3b8d8d91 | 6611 | |
652c393a JB |
6612 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
6613 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, | |
6614 | (unsigned long)dev); | |
2c7111db CW |
6615 | } |
6616 | ||
6617 | void intel_modeset_gem_init(struct drm_device *dev) | |
6618 | { | |
6619 | if (IS_IRONLAKE_M(dev)) | |
6620 | ironlake_enable_rc6(dev); | |
02e792fb DV |
6621 | |
6622 | intel_setup_overlay(dev); | |
79e53945 JB |
6623 | } |
6624 | ||
6625 | void intel_modeset_cleanup(struct drm_device *dev) | |
6626 | { | |
652c393a JB |
6627 | struct drm_i915_private *dev_priv = dev->dev_private; |
6628 | struct drm_crtc *crtc; | |
6629 | struct intel_crtc *intel_crtc; | |
6630 | ||
f87ea761 | 6631 | drm_kms_helper_poll_fini(dev); |
652c393a JB |
6632 | mutex_lock(&dev->struct_mutex); |
6633 | ||
723bfd70 JB |
6634 | intel_unregister_dsm_handler(); |
6635 | ||
6636 | ||
652c393a JB |
6637 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
6638 | /* Skip inactive CRTCs */ | |
6639 | if (!crtc->fb) | |
6640 | continue; | |
6641 | ||
6642 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 6643 | intel_increase_pllclock(crtc); |
652c393a JB |
6644 | } |
6645 | ||
973d04f9 | 6646 | intel_disable_fbc(dev); |
e70236a8 | 6647 | |
f97108d1 JB |
6648 | if (IS_IRONLAKE_M(dev)) |
6649 | ironlake_disable_drps(dev); | |
b6834bd6 | 6650 | if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) |
3b8d8d91 | 6651 | gen6_disable_rps(dev); |
f97108d1 | 6652 | |
d5bb081b JB |
6653 | if (IS_IRONLAKE_M(dev)) |
6654 | ironlake_disable_rc6(dev); | |
0cdab21f | 6655 | |
57f350b6 JB |
6656 | if (IS_VALLEYVIEW(dev)) |
6657 | vlv_init_dpio(dev); | |
6658 | ||
69341a5e KH |
6659 | mutex_unlock(&dev->struct_mutex); |
6660 | ||
6c0d9350 DV |
6661 | /* Disable the irq before mode object teardown, for the irq might |
6662 | * enqueue unpin/hotplug work. */ | |
6663 | drm_irq_uninstall(dev); | |
6664 | cancel_work_sync(&dev_priv->hotplug_work); | |
6fdd4d98 | 6665 | cancel_work_sync(&dev_priv->rps_work); |
6c0d9350 | 6666 | |
1630fe75 CW |
6667 | /* flush any delayed tasks or pending work */ |
6668 | flush_scheduled_work(); | |
6669 | ||
3dec0095 DV |
6670 | /* Shut off idle work before the crtcs get freed. */ |
6671 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
6672 | intel_crtc = to_intel_crtc(crtc); | |
6673 | del_timer_sync(&intel_crtc->idle_timer); | |
6674 | } | |
6675 | del_timer_sync(&dev_priv->idle_timer); | |
6676 | cancel_work_sync(&dev_priv->idle_work); | |
6677 | ||
79e53945 JB |
6678 | drm_mode_config_cleanup(dev); |
6679 | } | |
6680 | ||
f1c79df3 ZW |
6681 | /* |
6682 | * Return which encoder is currently attached for connector. | |
6683 | */ | |
df0e9248 | 6684 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 6685 | { |
df0e9248 CW |
6686 | return &intel_attached_encoder(connector)->base; |
6687 | } | |
f1c79df3 | 6688 | |
df0e9248 CW |
6689 | void intel_connector_attach_encoder(struct intel_connector *connector, |
6690 | struct intel_encoder *encoder) | |
6691 | { | |
6692 | connector->encoder = encoder; | |
6693 | drm_mode_connector_attach_encoder(&connector->base, | |
6694 | &encoder->base); | |
79e53945 | 6695 | } |
28d52043 DA |
6696 | |
6697 | /* | |
6698 | * set vga decode state - true == enable VGA decode | |
6699 | */ | |
6700 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
6701 | { | |
6702 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6703 | u16 gmch_ctrl; | |
6704 | ||
6705 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
6706 | if (state) | |
6707 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
6708 | else | |
6709 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
6710 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
6711 | return 0; | |
6712 | } | |
c4a1d9e4 CW |
6713 | |
6714 | #ifdef CONFIG_DEBUG_FS | |
6715 | #include <linux/seq_file.h> | |
6716 | ||
6717 | struct intel_display_error_state { | |
6718 | struct intel_cursor_error_state { | |
6719 | u32 control; | |
6720 | u32 position; | |
6721 | u32 base; | |
6722 | u32 size; | |
6723 | } cursor[2]; | |
6724 | ||
6725 | struct intel_pipe_error_state { | |
6726 | u32 conf; | |
6727 | u32 source; | |
6728 | ||
6729 | u32 htotal; | |
6730 | u32 hblank; | |
6731 | u32 hsync; | |
6732 | u32 vtotal; | |
6733 | u32 vblank; | |
6734 | u32 vsync; | |
6735 | } pipe[2]; | |
6736 | ||
6737 | struct intel_plane_error_state { | |
6738 | u32 control; | |
6739 | u32 stride; | |
6740 | u32 size; | |
6741 | u32 pos; | |
6742 | u32 addr; | |
6743 | u32 surface; | |
6744 | u32 tile_offset; | |
6745 | } plane[2]; | |
6746 | }; | |
6747 | ||
6748 | struct intel_display_error_state * | |
6749 | intel_display_capture_error_state(struct drm_device *dev) | |
6750 | { | |
0206e353 | 6751 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
6752 | struct intel_display_error_state *error; |
6753 | int i; | |
6754 | ||
6755 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
6756 | if (error == NULL) | |
6757 | return NULL; | |
6758 | ||
6759 | for (i = 0; i < 2; i++) { | |
6760 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
6761 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
6762 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
6763 | ||
6764 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
6765 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
6766 | error->plane[i].size = I915_READ(DSPSIZE(i)); | |
0206e353 | 6767 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
c4a1d9e4 CW |
6768 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
6769 | if (INTEL_INFO(dev)->gen >= 4) { | |
6770 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
6771 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
6772 | } | |
6773 | ||
6774 | error->pipe[i].conf = I915_READ(PIPECONF(i)); | |
6775 | error->pipe[i].source = I915_READ(PIPESRC(i)); | |
6776 | error->pipe[i].htotal = I915_READ(HTOTAL(i)); | |
6777 | error->pipe[i].hblank = I915_READ(HBLANK(i)); | |
6778 | error->pipe[i].hsync = I915_READ(HSYNC(i)); | |
6779 | error->pipe[i].vtotal = I915_READ(VTOTAL(i)); | |
6780 | error->pipe[i].vblank = I915_READ(VBLANK(i)); | |
6781 | error->pipe[i].vsync = I915_READ(VSYNC(i)); | |
6782 | } | |
6783 | ||
6784 | return error; | |
6785 | } | |
6786 | ||
6787 | void | |
6788 | intel_display_print_error_state(struct seq_file *m, | |
6789 | struct drm_device *dev, | |
6790 | struct intel_display_error_state *error) | |
6791 | { | |
6792 | int i; | |
6793 | ||
6794 | for (i = 0; i < 2; i++) { | |
6795 | seq_printf(m, "Pipe [%d]:\n", i); | |
6796 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); | |
6797 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); | |
6798 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); | |
6799 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); | |
6800 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); | |
6801 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); | |
6802 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); | |
6803 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); | |
6804 | ||
6805 | seq_printf(m, "Plane [%d]:\n", i); | |
6806 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
6807 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
6808 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); | |
6809 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); | |
6810 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); | |
6811 | if (INTEL_INFO(dev)->gen >= 4) { | |
6812 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); | |
6813 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
6814 | } | |
6815 | ||
6816 | seq_printf(m, "Cursor [%d]:\n", i); | |
6817 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
6818 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); | |
6819 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
6820 | } | |
6821 | } | |
6822 | #endif |