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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
3dec0095 | 44 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 45 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 46 | |
f1f644dc JB |
47 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
48 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
49 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
50 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 51 | |
e7457a9a DL |
52 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
53 | int x, int y, struct drm_framebuffer *old_fb); | |
54 | ||
55 | ||
79e53945 | 56 | typedef struct { |
0206e353 | 57 | int min, max; |
79e53945 JB |
58 | } intel_range_t; |
59 | ||
60 | typedef struct { | |
0206e353 AJ |
61 | int dot_limit; |
62 | int p2_slow, p2_fast; | |
79e53945 JB |
63 | } intel_p2_t; |
64 | ||
d4906093 ML |
65 | typedef struct intel_limit intel_limit_t; |
66 | struct intel_limit { | |
0206e353 AJ |
67 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
68 | intel_p2_t p2; | |
d4906093 | 69 | }; |
79e53945 | 70 | |
d2acd215 DV |
71 | int |
72 | intel_pch_rawclk(struct drm_device *dev) | |
73 | { | |
74 | struct drm_i915_private *dev_priv = dev->dev_private; | |
75 | ||
76 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
77 | ||
78 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
79 | } | |
80 | ||
021357ac CW |
81 | static inline u32 /* units of 100MHz */ |
82 | intel_fdi_link_freq(struct drm_device *dev) | |
83 | { | |
8b99e68c CW |
84 | if (IS_GEN5(dev)) { |
85 | struct drm_i915_private *dev_priv = dev->dev_private; | |
86 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
87 | } else | |
88 | return 27; | |
021357ac CW |
89 | } |
90 | ||
5d536e28 | 91 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 92 | .dot = { .min = 25000, .max = 350000 }, |
c7721d32 | 93 | .vco = { .min = 930000, .max = 1512000 }, |
91dbe5fb | 94 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
95 | .m = { .min = 96, .max = 140 }, |
96 | .m1 = { .min = 18, .max = 26 }, | |
97 | .m2 = { .min = 6, .max = 16 }, | |
98 | .p = { .min = 4, .max = 128 }, | |
99 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
100 | .p2 = { .dot_limit = 165000, |
101 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
102 | }; |
103 | ||
5d536e28 DV |
104 | static const intel_limit_t intel_limits_i8xx_dvo = { |
105 | .dot = { .min = 25000, .max = 350000 }, | |
c7721d32 | 106 | .vco = { .min = 930000, .max = 1512000 }, |
91dbe5fb | 107 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
108 | .m = { .min = 96, .max = 140 }, |
109 | .m1 = { .min = 18, .max = 26 }, | |
110 | .m2 = { .min = 6, .max = 16 }, | |
111 | .p = { .min = 4, .max = 128 }, | |
112 | .p1 = { .min = 2, .max = 33 }, | |
113 | .p2 = { .dot_limit = 165000, | |
114 | .p2_slow = 4, .p2_fast = 4 }, | |
115 | }; | |
116 | ||
e4b36699 | 117 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 118 | .dot = { .min = 25000, .max = 350000 }, |
c7721d32 | 119 | .vco = { .min = 930000, .max = 1512000 }, |
91dbe5fb | 120 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
121 | .m = { .min = 96, .max = 140 }, |
122 | .m1 = { .min = 18, .max = 26 }, | |
123 | .m2 = { .min = 6, .max = 16 }, | |
124 | .p = { .min = 4, .max = 128 }, | |
125 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
126 | .p2 = { .dot_limit = 165000, |
127 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 128 | }; |
273e27ca | 129 | |
e4b36699 | 130 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
131 | .dot = { .min = 20000, .max = 400000 }, |
132 | .vco = { .min = 1400000, .max = 2800000 }, | |
133 | .n = { .min = 1, .max = 6 }, | |
134 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
135 | .m1 = { .min = 8, .max = 18 }, |
136 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
137 | .p = { .min = 5, .max = 80 }, |
138 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
139 | .p2 = { .dot_limit = 200000, |
140 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
141 | }; |
142 | ||
143 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
144 | .dot = { .min = 20000, .max = 400000 }, |
145 | .vco = { .min = 1400000, .max = 2800000 }, | |
146 | .n = { .min = 1, .max = 6 }, | |
147 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
148 | .m1 = { .min = 8, .max = 18 }, |
149 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
150 | .p = { .min = 7, .max = 98 }, |
151 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
152 | .p2 = { .dot_limit = 112000, |
153 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
154 | }; |
155 | ||
273e27ca | 156 | |
e4b36699 | 157 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
158 | .dot = { .min = 25000, .max = 270000 }, |
159 | .vco = { .min = 1750000, .max = 3500000}, | |
160 | .n = { .min = 1, .max = 4 }, | |
161 | .m = { .min = 104, .max = 138 }, | |
162 | .m1 = { .min = 17, .max = 23 }, | |
163 | .m2 = { .min = 5, .max = 11 }, | |
164 | .p = { .min = 10, .max = 30 }, | |
165 | .p1 = { .min = 1, .max = 3}, | |
166 | .p2 = { .dot_limit = 270000, | |
167 | .p2_slow = 10, | |
168 | .p2_fast = 10 | |
044c7c41 | 169 | }, |
e4b36699 KP |
170 | }; |
171 | ||
172 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
173 | .dot = { .min = 22000, .max = 400000 }, |
174 | .vco = { .min = 1750000, .max = 3500000}, | |
175 | .n = { .min = 1, .max = 4 }, | |
176 | .m = { .min = 104, .max = 138 }, | |
177 | .m1 = { .min = 16, .max = 23 }, | |
178 | .m2 = { .min = 5, .max = 11 }, | |
179 | .p = { .min = 5, .max = 80 }, | |
180 | .p1 = { .min = 1, .max = 8}, | |
181 | .p2 = { .dot_limit = 165000, | |
182 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
183 | }; |
184 | ||
185 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
186 | .dot = { .min = 20000, .max = 115000 }, |
187 | .vco = { .min = 1750000, .max = 3500000 }, | |
188 | .n = { .min = 1, .max = 3 }, | |
189 | .m = { .min = 104, .max = 138 }, | |
190 | .m1 = { .min = 17, .max = 23 }, | |
191 | .m2 = { .min = 5, .max = 11 }, | |
192 | .p = { .min = 28, .max = 112 }, | |
193 | .p1 = { .min = 2, .max = 8 }, | |
194 | .p2 = { .dot_limit = 0, | |
195 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 196 | }, |
e4b36699 KP |
197 | }; |
198 | ||
199 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
200 | .dot = { .min = 80000, .max = 224000 }, |
201 | .vco = { .min = 1750000, .max = 3500000 }, | |
202 | .n = { .min = 1, .max = 3 }, | |
203 | .m = { .min = 104, .max = 138 }, | |
204 | .m1 = { .min = 17, .max = 23 }, | |
205 | .m2 = { .min = 5, .max = 11 }, | |
206 | .p = { .min = 14, .max = 42 }, | |
207 | .p1 = { .min = 2, .max = 6 }, | |
208 | .p2 = { .dot_limit = 0, | |
209 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 210 | }, |
e4b36699 KP |
211 | }; |
212 | ||
f2b115e6 | 213 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
214 | .dot = { .min = 20000, .max = 400000}, |
215 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 216 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
217 | .n = { .min = 3, .max = 6 }, |
218 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 219 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
220 | .m1 = { .min = 0, .max = 0 }, |
221 | .m2 = { .min = 0, .max = 254 }, | |
222 | .p = { .min = 5, .max = 80 }, | |
223 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
224 | .p2 = { .dot_limit = 200000, |
225 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
226 | }; |
227 | ||
f2b115e6 | 228 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
229 | .dot = { .min = 20000, .max = 400000 }, |
230 | .vco = { .min = 1700000, .max = 3500000 }, | |
231 | .n = { .min = 3, .max = 6 }, | |
232 | .m = { .min = 2, .max = 256 }, | |
233 | .m1 = { .min = 0, .max = 0 }, | |
234 | .m2 = { .min = 0, .max = 254 }, | |
235 | .p = { .min = 7, .max = 112 }, | |
236 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
237 | .p2 = { .dot_limit = 112000, |
238 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
239 | }; |
240 | ||
273e27ca EA |
241 | /* Ironlake / Sandybridge |
242 | * | |
243 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
244 | * the range value for them is (actual_value - 2). | |
245 | */ | |
b91ad0ec | 246 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
247 | .dot = { .min = 25000, .max = 350000 }, |
248 | .vco = { .min = 1760000, .max = 3510000 }, | |
249 | .n = { .min = 1, .max = 5 }, | |
250 | .m = { .min = 79, .max = 127 }, | |
251 | .m1 = { .min = 12, .max = 22 }, | |
252 | .m2 = { .min = 5, .max = 9 }, | |
253 | .p = { .min = 5, .max = 80 }, | |
254 | .p1 = { .min = 1, .max = 8 }, | |
255 | .p2 = { .dot_limit = 225000, | |
256 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
257 | }; |
258 | ||
b91ad0ec | 259 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
260 | .dot = { .min = 25000, .max = 350000 }, |
261 | .vco = { .min = 1760000, .max = 3510000 }, | |
262 | .n = { .min = 1, .max = 3 }, | |
263 | .m = { .min = 79, .max = 118 }, | |
264 | .m1 = { .min = 12, .max = 22 }, | |
265 | .m2 = { .min = 5, .max = 9 }, | |
266 | .p = { .min = 28, .max = 112 }, | |
267 | .p1 = { .min = 2, .max = 8 }, | |
268 | .p2 = { .dot_limit = 225000, | |
269 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
270 | }; |
271 | ||
272 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
273 | .dot = { .min = 25000, .max = 350000 }, |
274 | .vco = { .min = 1760000, .max = 3510000 }, | |
275 | .n = { .min = 1, .max = 3 }, | |
276 | .m = { .min = 79, .max = 127 }, | |
277 | .m1 = { .min = 12, .max = 22 }, | |
278 | .m2 = { .min = 5, .max = 9 }, | |
279 | .p = { .min = 14, .max = 56 }, | |
280 | .p1 = { .min = 2, .max = 8 }, | |
281 | .p2 = { .dot_limit = 225000, | |
282 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
283 | }; |
284 | ||
273e27ca | 285 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 286 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
287 | .dot = { .min = 25000, .max = 350000 }, |
288 | .vco = { .min = 1760000, .max = 3510000 }, | |
289 | .n = { .min = 1, .max = 2 }, | |
290 | .m = { .min = 79, .max = 126 }, | |
291 | .m1 = { .min = 12, .max = 22 }, | |
292 | .m2 = { .min = 5, .max = 9 }, | |
293 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 294 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
295 | .p2 = { .dot_limit = 225000, |
296 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
297 | }; |
298 | ||
299 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
300 | .dot = { .min = 25000, .max = 350000 }, |
301 | .vco = { .min = 1760000, .max = 3510000 }, | |
302 | .n = { .min = 1, .max = 3 }, | |
303 | .m = { .min = 79, .max = 126 }, | |
304 | .m1 = { .min = 12, .max = 22 }, | |
305 | .m2 = { .min = 5, .max = 9 }, | |
306 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 307 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
308 | .p2 = { .dot_limit = 225000, |
309 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
310 | }; |
311 | ||
dc730512 | 312 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
313 | /* |
314 | * These are the data rate limits (measured in fast clocks) | |
315 | * since those are the strictest limits we have. The fast | |
316 | * clock and actual rate limits are more relaxed, so checking | |
317 | * them would make no difference. | |
318 | */ | |
319 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 320 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 321 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
322 | .m1 = { .min = 2, .max = 3 }, |
323 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 324 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 325 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
326 | }; |
327 | ||
6b4bf1c4 VS |
328 | static void vlv_clock(int refclk, intel_clock_t *clock) |
329 | { | |
330 | clock->m = clock->m1 * clock->m2; | |
331 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
332 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
333 | return; | |
fb03ac01 VS |
334 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
335 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
336 | } |
337 | ||
e0638cdf PZ |
338 | /** |
339 | * Returns whether any output on the specified pipe is of the specified type | |
340 | */ | |
341 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |
342 | { | |
343 | struct drm_device *dev = crtc->dev; | |
344 | struct intel_encoder *encoder; | |
345 | ||
346 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
347 | if (encoder->type == type) | |
348 | return true; | |
349 | ||
350 | return false; | |
351 | } | |
352 | ||
1b894b59 CW |
353 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
354 | int refclk) | |
2c07245f | 355 | { |
b91ad0ec | 356 | struct drm_device *dev = crtc->dev; |
2c07245f | 357 | const intel_limit_t *limit; |
b91ad0ec ZW |
358 | |
359 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 360 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 361 | if (refclk == 100000) |
b91ad0ec ZW |
362 | limit = &intel_limits_ironlake_dual_lvds_100m; |
363 | else | |
364 | limit = &intel_limits_ironlake_dual_lvds; | |
365 | } else { | |
1b894b59 | 366 | if (refclk == 100000) |
b91ad0ec ZW |
367 | limit = &intel_limits_ironlake_single_lvds_100m; |
368 | else | |
369 | limit = &intel_limits_ironlake_single_lvds; | |
370 | } | |
c6bb3538 | 371 | } else |
b91ad0ec | 372 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
373 | |
374 | return limit; | |
375 | } | |
376 | ||
044c7c41 ML |
377 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
378 | { | |
379 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
380 | const intel_limit_t *limit; |
381 | ||
382 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 383 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 384 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 385 | else |
e4b36699 | 386 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
387 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
388 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 389 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 390 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 391 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 392 | } else /* The option is for other outputs */ |
e4b36699 | 393 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
394 | |
395 | return limit; | |
396 | } | |
397 | ||
1b894b59 | 398 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
399 | { |
400 | struct drm_device *dev = crtc->dev; | |
401 | const intel_limit_t *limit; | |
402 | ||
bad720ff | 403 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 404 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 405 | else if (IS_G4X(dev)) { |
044c7c41 | 406 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 407 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 408 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 409 | limit = &intel_limits_pineview_lvds; |
2177832f | 410 | else |
f2b115e6 | 411 | limit = &intel_limits_pineview_sdvo; |
a0c4da24 | 412 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 413 | limit = &intel_limits_vlv; |
a6c45cf0 CW |
414 | } else if (!IS_GEN2(dev)) { |
415 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
416 | limit = &intel_limits_i9xx_lvds; | |
417 | else | |
418 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
419 | } else { |
420 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 421 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 422 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 423 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
424 | else |
425 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
426 | } |
427 | return limit; | |
428 | } | |
429 | ||
f2b115e6 AJ |
430 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
431 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 432 | { |
2177832f SL |
433 | clock->m = clock->m2 + 2; |
434 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
435 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
436 | return; | |
fb03ac01 VS |
437 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
438 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
439 | } |
440 | ||
7429e9d4 DV |
441 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
442 | { | |
443 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
444 | } | |
445 | ||
ac58c3f0 | 446 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 447 | { |
7429e9d4 | 448 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 449 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
450 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
451 | return; | |
fb03ac01 VS |
452 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
453 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
454 | } |
455 | ||
7c04d1d9 | 456 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
457 | /** |
458 | * Returns whether the given set of divisors are valid for a given refclk with | |
459 | * the given connectors. | |
460 | */ | |
461 | ||
1b894b59 CW |
462 | static bool intel_PLL_is_valid(struct drm_device *dev, |
463 | const intel_limit_t *limit, | |
464 | const intel_clock_t *clock) | |
79e53945 | 465 | { |
f01b7962 VS |
466 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
467 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 468 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 469 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 470 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 471 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 472 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 473 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
474 | |
475 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
476 | if (clock->m1 <= clock->m2) | |
477 | INTELPllInvalid("m1 <= m2\n"); | |
478 | ||
479 | if (!IS_VALLEYVIEW(dev)) { | |
480 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
481 | INTELPllInvalid("p out of range\n"); | |
482 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
483 | INTELPllInvalid("m out of range\n"); | |
484 | } | |
485 | ||
79e53945 | 486 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 487 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
488 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
489 | * connector, etc., rather than just a single range. | |
490 | */ | |
491 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 492 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
493 | |
494 | return true; | |
495 | } | |
496 | ||
d4906093 | 497 | static bool |
ee9300bb | 498 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
499 | int target, int refclk, intel_clock_t *match_clock, |
500 | intel_clock_t *best_clock) | |
79e53945 JB |
501 | { |
502 | struct drm_device *dev = crtc->dev; | |
79e53945 | 503 | intel_clock_t clock; |
79e53945 JB |
504 | int err = target; |
505 | ||
a210b028 | 506 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 507 | /* |
a210b028 DV |
508 | * For LVDS just rely on its current settings for dual-channel. |
509 | * We haven't figured out how to reliably set up different | |
510 | * single/dual channel state, if we even can. | |
79e53945 | 511 | */ |
1974cad0 | 512 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
513 | clock.p2 = limit->p2.p2_fast; |
514 | else | |
515 | clock.p2 = limit->p2.p2_slow; | |
516 | } else { | |
517 | if (target < limit->p2.dot_limit) | |
518 | clock.p2 = limit->p2.p2_slow; | |
519 | else | |
520 | clock.p2 = limit->p2.p2_fast; | |
521 | } | |
522 | ||
0206e353 | 523 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 524 | |
42158660 ZY |
525 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
526 | clock.m1++) { | |
527 | for (clock.m2 = limit->m2.min; | |
528 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 529 | if (clock.m2 >= clock.m1) |
42158660 ZY |
530 | break; |
531 | for (clock.n = limit->n.min; | |
532 | clock.n <= limit->n.max; clock.n++) { | |
533 | for (clock.p1 = limit->p1.min; | |
534 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
535 | int this_err; |
536 | ||
ac58c3f0 DV |
537 | i9xx_clock(refclk, &clock); |
538 | if (!intel_PLL_is_valid(dev, limit, | |
539 | &clock)) | |
540 | continue; | |
541 | if (match_clock && | |
542 | clock.p != match_clock->p) | |
543 | continue; | |
544 | ||
545 | this_err = abs(clock.dot - target); | |
546 | if (this_err < err) { | |
547 | *best_clock = clock; | |
548 | err = this_err; | |
549 | } | |
550 | } | |
551 | } | |
552 | } | |
553 | } | |
554 | ||
555 | return (err != target); | |
556 | } | |
557 | ||
558 | static bool | |
ee9300bb DV |
559 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
560 | int target, int refclk, intel_clock_t *match_clock, | |
561 | intel_clock_t *best_clock) | |
79e53945 JB |
562 | { |
563 | struct drm_device *dev = crtc->dev; | |
79e53945 | 564 | intel_clock_t clock; |
79e53945 JB |
565 | int err = target; |
566 | ||
a210b028 | 567 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 568 | /* |
a210b028 DV |
569 | * For LVDS just rely on its current settings for dual-channel. |
570 | * We haven't figured out how to reliably set up different | |
571 | * single/dual channel state, if we even can. | |
79e53945 | 572 | */ |
1974cad0 | 573 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
574 | clock.p2 = limit->p2.p2_fast; |
575 | else | |
576 | clock.p2 = limit->p2.p2_slow; | |
577 | } else { | |
578 | if (target < limit->p2.dot_limit) | |
579 | clock.p2 = limit->p2.p2_slow; | |
580 | else | |
581 | clock.p2 = limit->p2.p2_fast; | |
582 | } | |
583 | ||
0206e353 | 584 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 585 | |
42158660 ZY |
586 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
587 | clock.m1++) { | |
588 | for (clock.m2 = limit->m2.min; | |
589 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
590 | for (clock.n = limit->n.min; |
591 | clock.n <= limit->n.max; clock.n++) { | |
592 | for (clock.p1 = limit->p1.min; | |
593 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
594 | int this_err; |
595 | ||
ac58c3f0 | 596 | pineview_clock(refclk, &clock); |
1b894b59 CW |
597 | if (!intel_PLL_is_valid(dev, limit, |
598 | &clock)) | |
79e53945 | 599 | continue; |
cec2f356 SP |
600 | if (match_clock && |
601 | clock.p != match_clock->p) | |
602 | continue; | |
79e53945 JB |
603 | |
604 | this_err = abs(clock.dot - target); | |
605 | if (this_err < err) { | |
606 | *best_clock = clock; | |
607 | err = this_err; | |
608 | } | |
609 | } | |
610 | } | |
611 | } | |
612 | } | |
613 | ||
614 | return (err != target); | |
615 | } | |
616 | ||
d4906093 | 617 | static bool |
ee9300bb DV |
618 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
619 | int target, int refclk, intel_clock_t *match_clock, | |
620 | intel_clock_t *best_clock) | |
d4906093 ML |
621 | { |
622 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
623 | intel_clock_t clock; |
624 | int max_n; | |
625 | bool found; | |
6ba770dc AJ |
626 | /* approximately equals target * 0.00585 */ |
627 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
628 | found = false; |
629 | ||
630 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 631 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
632 | clock.p2 = limit->p2.p2_fast; |
633 | else | |
634 | clock.p2 = limit->p2.p2_slow; | |
635 | } else { | |
636 | if (target < limit->p2.dot_limit) | |
637 | clock.p2 = limit->p2.p2_slow; | |
638 | else | |
639 | clock.p2 = limit->p2.p2_fast; | |
640 | } | |
641 | ||
642 | memset(best_clock, 0, sizeof(*best_clock)); | |
643 | max_n = limit->n.max; | |
f77f13e2 | 644 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 645 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 646 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
647 | for (clock.m1 = limit->m1.max; |
648 | clock.m1 >= limit->m1.min; clock.m1--) { | |
649 | for (clock.m2 = limit->m2.max; | |
650 | clock.m2 >= limit->m2.min; clock.m2--) { | |
651 | for (clock.p1 = limit->p1.max; | |
652 | clock.p1 >= limit->p1.min; clock.p1--) { | |
653 | int this_err; | |
654 | ||
ac58c3f0 | 655 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
656 | if (!intel_PLL_is_valid(dev, limit, |
657 | &clock)) | |
d4906093 | 658 | continue; |
1b894b59 CW |
659 | |
660 | this_err = abs(clock.dot - target); | |
d4906093 ML |
661 | if (this_err < err_most) { |
662 | *best_clock = clock; | |
663 | err_most = this_err; | |
664 | max_n = clock.n; | |
665 | found = true; | |
666 | } | |
667 | } | |
668 | } | |
669 | } | |
670 | } | |
2c07245f ZW |
671 | return found; |
672 | } | |
673 | ||
a0c4da24 | 674 | static bool |
ee9300bb DV |
675 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
676 | int target, int refclk, intel_clock_t *match_clock, | |
677 | intel_clock_t *best_clock) | |
a0c4da24 | 678 | { |
f01b7962 | 679 | struct drm_device *dev = crtc->dev; |
6b4bf1c4 | 680 | intel_clock_t clock; |
69e4f900 | 681 | unsigned int bestppm = 1000000; |
27e639bf VS |
682 | /* min update 19.2 MHz */ |
683 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 684 | bool found = false; |
a0c4da24 | 685 | |
6b4bf1c4 VS |
686 | target *= 5; /* fast clock */ |
687 | ||
688 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
689 | |
690 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 691 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 692 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 693 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 694 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 695 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 696 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 697 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
698 | unsigned int ppm, diff; |
699 | ||
6b4bf1c4 VS |
700 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
701 | refclk * clock.m1); | |
702 | ||
703 | vlv_clock(refclk, &clock); | |
43b0ac53 | 704 | |
f01b7962 VS |
705 | if (!intel_PLL_is_valid(dev, limit, |
706 | &clock)) | |
43b0ac53 VS |
707 | continue; |
708 | ||
6b4bf1c4 VS |
709 | diff = abs(clock.dot - target); |
710 | ppm = div_u64(1000000ULL * diff, target); | |
711 | ||
712 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 713 | bestppm = 0; |
6b4bf1c4 | 714 | *best_clock = clock; |
49e497ef | 715 | found = true; |
43b0ac53 | 716 | } |
6b4bf1c4 | 717 | |
c686122c | 718 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 719 | bestppm = ppm; |
6b4bf1c4 | 720 | *best_clock = clock; |
49e497ef | 721 | found = true; |
a0c4da24 JB |
722 | } |
723 | } | |
724 | } | |
725 | } | |
726 | } | |
a0c4da24 | 727 | |
49e497ef | 728 | return found; |
a0c4da24 | 729 | } |
a4fc5ed6 | 730 | |
20ddf665 VS |
731 | bool intel_crtc_active(struct drm_crtc *crtc) |
732 | { | |
733 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
734 | ||
735 | /* Be paranoid as we can arrive here with only partial | |
736 | * state retrieved from the hardware during setup. | |
737 | * | |
241bfc38 | 738 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
739 | * as Haswell has gained clock readout/fastboot support. |
740 | * | |
741 | * We can ditch the crtc->fb check as soon as we can | |
742 | * properly reconstruct framebuffers. | |
743 | */ | |
744 | return intel_crtc->active && crtc->fb && | |
241bfc38 | 745 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
746 | } |
747 | ||
a5c961d1 PZ |
748 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
749 | enum pipe pipe) | |
750 | { | |
751 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
752 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
753 | ||
3b117c8f | 754 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
755 | } |
756 | ||
57e22f4a | 757 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
a928d536 PZ |
758 | { |
759 | struct drm_i915_private *dev_priv = dev->dev_private; | |
57e22f4a | 760 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
a928d536 PZ |
761 | |
762 | frame = I915_READ(frame_reg); | |
763 | ||
764 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
765 | DRM_DEBUG_KMS("vblank wait timed out\n"); | |
766 | } | |
767 | ||
9d0498a2 JB |
768 | /** |
769 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
770 | * @dev: drm device | |
771 | * @pipe: pipe to wait for | |
772 | * | |
773 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
774 | * mode setting code. | |
775 | */ | |
776 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 777 | { |
9d0498a2 | 778 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 779 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 780 | |
57e22f4a VS |
781 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
782 | g4x_wait_for_vblank(dev, pipe); | |
a928d536 PZ |
783 | return; |
784 | } | |
785 | ||
300387c0 CW |
786 | /* Clear existing vblank status. Note this will clear any other |
787 | * sticky status fields as well. | |
788 | * | |
789 | * This races with i915_driver_irq_handler() with the result | |
790 | * that either function could miss a vblank event. Here it is not | |
791 | * fatal, as we will either wait upon the next vblank interrupt or | |
792 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
793 | * called during modeset at which time the GPU should be idle and | |
794 | * should *not* be performing page flips and thus not waiting on | |
795 | * vblanks... | |
796 | * Currently, the result of us stealing a vblank from the irq | |
797 | * handler is that a single frame will be skipped during swapbuffers. | |
798 | */ | |
799 | I915_WRITE(pipestat_reg, | |
800 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
801 | ||
9d0498a2 | 802 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
803 | if (wait_for(I915_READ(pipestat_reg) & |
804 | PIPE_VBLANK_INTERRUPT_STATUS, | |
805 | 50)) | |
9d0498a2 JB |
806 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
807 | } | |
808 | ||
fbf49ea2 VS |
809 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
810 | { | |
811 | struct drm_i915_private *dev_priv = dev->dev_private; | |
812 | u32 reg = PIPEDSL(pipe); | |
813 | u32 line1, line2; | |
814 | u32 line_mask; | |
815 | ||
816 | if (IS_GEN2(dev)) | |
817 | line_mask = DSL_LINEMASK_GEN2; | |
818 | else | |
819 | line_mask = DSL_LINEMASK_GEN3; | |
820 | ||
821 | line1 = I915_READ(reg) & line_mask; | |
822 | mdelay(5); | |
823 | line2 = I915_READ(reg) & line_mask; | |
824 | ||
825 | return line1 == line2; | |
826 | } | |
827 | ||
ab7ad7f6 KP |
828 | /* |
829 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
830 | * @dev: drm device |
831 | * @pipe: pipe to wait for | |
832 | * | |
833 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
834 | * spinning on the vblank interrupt status bit, since we won't actually | |
835 | * see an interrupt when the pipe is disabled. | |
836 | * | |
ab7ad7f6 KP |
837 | * On Gen4 and above: |
838 | * wait for the pipe register state bit to turn off | |
839 | * | |
840 | * Otherwise: | |
841 | * wait for the display line value to settle (it usually | |
842 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 843 | * |
9d0498a2 | 844 | */ |
58e10eb9 | 845 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
846 | { |
847 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
848 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
849 | pipe); | |
ab7ad7f6 KP |
850 | |
851 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 852 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
853 | |
854 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
855 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
856 | 100)) | |
284637d9 | 857 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 858 | } else { |
ab7ad7f6 | 859 | /* Wait for the display line to settle */ |
fbf49ea2 | 860 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 861 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 862 | } |
79e53945 JB |
863 | } |
864 | ||
b0ea7d37 DL |
865 | /* |
866 | * ibx_digital_port_connected - is the specified port connected? | |
867 | * @dev_priv: i915 private structure | |
868 | * @port: the port to test | |
869 | * | |
870 | * Returns true if @port is connected, false otherwise. | |
871 | */ | |
872 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
873 | struct intel_digital_port *port) | |
874 | { | |
875 | u32 bit; | |
876 | ||
c36346e3 DL |
877 | if (HAS_PCH_IBX(dev_priv->dev)) { |
878 | switch(port->port) { | |
879 | case PORT_B: | |
880 | bit = SDE_PORTB_HOTPLUG; | |
881 | break; | |
882 | case PORT_C: | |
883 | bit = SDE_PORTC_HOTPLUG; | |
884 | break; | |
885 | case PORT_D: | |
886 | bit = SDE_PORTD_HOTPLUG; | |
887 | break; | |
888 | default: | |
889 | return true; | |
890 | } | |
891 | } else { | |
892 | switch(port->port) { | |
893 | case PORT_B: | |
894 | bit = SDE_PORTB_HOTPLUG_CPT; | |
895 | break; | |
896 | case PORT_C: | |
897 | bit = SDE_PORTC_HOTPLUG_CPT; | |
898 | break; | |
899 | case PORT_D: | |
900 | bit = SDE_PORTD_HOTPLUG_CPT; | |
901 | break; | |
902 | default: | |
903 | return true; | |
904 | } | |
b0ea7d37 DL |
905 | } |
906 | ||
907 | return I915_READ(SDEISR) & bit; | |
908 | } | |
909 | ||
b24e7179 JB |
910 | static const char *state_string(bool enabled) |
911 | { | |
912 | return enabled ? "on" : "off"; | |
913 | } | |
914 | ||
915 | /* Only for pre-ILK configs */ | |
55607e8a DV |
916 | void assert_pll(struct drm_i915_private *dev_priv, |
917 | enum pipe pipe, bool state) | |
b24e7179 JB |
918 | { |
919 | int reg; | |
920 | u32 val; | |
921 | bool cur_state; | |
922 | ||
923 | reg = DPLL(pipe); | |
924 | val = I915_READ(reg); | |
925 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
926 | WARN(cur_state != state, | |
927 | "PLL state assertion failure (expected %s, current %s)\n", | |
928 | state_string(state), state_string(cur_state)); | |
929 | } | |
b24e7179 | 930 | |
23538ef1 JN |
931 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
932 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
933 | { | |
934 | u32 val; | |
935 | bool cur_state; | |
936 | ||
937 | mutex_lock(&dev_priv->dpio_lock); | |
938 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
939 | mutex_unlock(&dev_priv->dpio_lock); | |
940 | ||
941 | cur_state = val & DSI_PLL_VCO_EN; | |
942 | WARN(cur_state != state, | |
943 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
944 | state_string(state), state_string(cur_state)); | |
945 | } | |
946 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
947 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
948 | ||
55607e8a | 949 | struct intel_shared_dpll * |
e2b78267 DV |
950 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
951 | { | |
952 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
953 | ||
a43f6e0f | 954 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
955 | return NULL; |
956 | ||
a43f6e0f | 957 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
958 | } |
959 | ||
040484af | 960 | /* For ILK+ */ |
55607e8a DV |
961 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
962 | struct intel_shared_dpll *pll, | |
963 | bool state) | |
040484af | 964 | { |
040484af | 965 | bool cur_state; |
5358901f | 966 | struct intel_dpll_hw_state hw_state; |
040484af | 967 | |
9d82aa17 ED |
968 | if (HAS_PCH_LPT(dev_priv->dev)) { |
969 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
970 | return; | |
971 | } | |
972 | ||
92b27b08 | 973 | if (WARN (!pll, |
46edb027 | 974 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 975 | return; |
ee7b9f93 | 976 | |
5358901f | 977 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 978 | WARN(cur_state != state, |
5358901f DV |
979 | "%s assertion failure (expected %s, current %s)\n", |
980 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 981 | } |
040484af JB |
982 | |
983 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
984 | enum pipe pipe, bool state) | |
985 | { | |
986 | int reg; | |
987 | u32 val; | |
988 | bool cur_state; | |
ad80a810 PZ |
989 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
990 | pipe); | |
040484af | 991 | |
affa9354 PZ |
992 | if (HAS_DDI(dev_priv->dev)) { |
993 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 994 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 995 | val = I915_READ(reg); |
ad80a810 | 996 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
997 | } else { |
998 | reg = FDI_TX_CTL(pipe); | |
999 | val = I915_READ(reg); | |
1000 | cur_state = !!(val & FDI_TX_ENABLE); | |
1001 | } | |
040484af JB |
1002 | WARN(cur_state != state, |
1003 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1004 | state_string(state), state_string(cur_state)); | |
1005 | } | |
1006 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1007 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1008 | ||
1009 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1010 | enum pipe pipe, bool state) | |
1011 | { | |
1012 | int reg; | |
1013 | u32 val; | |
1014 | bool cur_state; | |
1015 | ||
d63fa0dc PZ |
1016 | reg = FDI_RX_CTL(pipe); |
1017 | val = I915_READ(reg); | |
1018 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1019 | WARN(cur_state != state, |
1020 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1021 | state_string(state), state_string(cur_state)); | |
1022 | } | |
1023 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1024 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1025 | ||
1026 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1027 | enum pipe pipe) | |
1028 | { | |
1029 | int reg; | |
1030 | u32 val; | |
1031 | ||
1032 | /* ILK FDI PLL is always enabled */ | |
1033 | if (dev_priv->info->gen == 5) | |
1034 | return; | |
1035 | ||
bf507ef7 | 1036 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1037 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1038 | return; |
1039 | ||
040484af JB |
1040 | reg = FDI_TX_CTL(pipe); |
1041 | val = I915_READ(reg); | |
1042 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1043 | } | |
1044 | ||
55607e8a DV |
1045 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1046 | enum pipe pipe, bool state) | |
040484af JB |
1047 | { |
1048 | int reg; | |
1049 | u32 val; | |
55607e8a | 1050 | bool cur_state; |
040484af JB |
1051 | |
1052 | reg = FDI_RX_CTL(pipe); | |
1053 | val = I915_READ(reg); | |
55607e8a DV |
1054 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1055 | WARN(cur_state != state, | |
1056 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1057 | state_string(state), state_string(cur_state)); | |
040484af JB |
1058 | } |
1059 | ||
ea0760cf JB |
1060 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1061 | enum pipe pipe) | |
1062 | { | |
1063 | int pp_reg, lvds_reg; | |
1064 | u32 val; | |
1065 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1066 | bool locked = true; |
ea0760cf JB |
1067 | |
1068 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1069 | pp_reg = PCH_PP_CONTROL; | |
1070 | lvds_reg = PCH_LVDS; | |
1071 | } else { | |
1072 | pp_reg = PP_CONTROL; | |
1073 | lvds_reg = LVDS; | |
1074 | } | |
1075 | ||
1076 | val = I915_READ(pp_reg); | |
1077 | if (!(val & PANEL_POWER_ON) || | |
1078 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1079 | locked = false; | |
1080 | ||
1081 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1082 | panel_pipe = PIPE_B; | |
1083 | ||
1084 | WARN(panel_pipe == pipe && locked, | |
1085 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1086 | pipe_name(pipe)); |
ea0760cf JB |
1087 | } |
1088 | ||
93ce0ba6 JN |
1089 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1090 | enum pipe pipe, bool state) | |
1091 | { | |
1092 | struct drm_device *dev = dev_priv->dev; | |
1093 | bool cur_state; | |
1094 | ||
1095 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
1096 | cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE; | |
1097 | else if (IS_845G(dev) || IS_I865G(dev)) | |
1098 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; | |
1099 | else | |
1100 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; | |
1101 | ||
1102 | WARN(cur_state != state, | |
1103 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1104 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1105 | } | |
1106 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1107 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1108 | ||
b840d907 JB |
1109 | void assert_pipe(struct drm_i915_private *dev_priv, |
1110 | enum pipe pipe, bool state) | |
b24e7179 JB |
1111 | { |
1112 | int reg; | |
1113 | u32 val; | |
63d7bbe9 | 1114 | bool cur_state; |
702e7a56 PZ |
1115 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1116 | pipe); | |
b24e7179 | 1117 | |
8e636784 DV |
1118 | /* if we need the pipe A quirk it must be always on */ |
1119 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1120 | state = true; | |
1121 | ||
b97186f0 PZ |
1122 | if (!intel_display_power_enabled(dev_priv->dev, |
1123 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { | |
69310161 PZ |
1124 | cur_state = false; |
1125 | } else { | |
1126 | reg = PIPECONF(cpu_transcoder); | |
1127 | val = I915_READ(reg); | |
1128 | cur_state = !!(val & PIPECONF_ENABLE); | |
1129 | } | |
1130 | ||
63d7bbe9 JB |
1131 | WARN(cur_state != state, |
1132 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1133 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1134 | } |
1135 | ||
931872fc CW |
1136 | static void assert_plane(struct drm_i915_private *dev_priv, |
1137 | enum plane plane, bool state) | |
b24e7179 JB |
1138 | { |
1139 | int reg; | |
1140 | u32 val; | |
931872fc | 1141 | bool cur_state; |
b24e7179 JB |
1142 | |
1143 | reg = DSPCNTR(plane); | |
1144 | val = I915_READ(reg); | |
931872fc CW |
1145 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1146 | WARN(cur_state != state, | |
1147 | "plane %c assertion failure (expected %s, current %s)\n", | |
1148 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1149 | } |
1150 | ||
931872fc CW |
1151 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1152 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1153 | ||
b24e7179 JB |
1154 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1155 | enum pipe pipe) | |
1156 | { | |
653e1026 | 1157 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1158 | int reg, i; |
1159 | u32 val; | |
1160 | int cur_pipe; | |
1161 | ||
653e1026 VS |
1162 | /* Primary planes are fixed to pipes on gen4+ */ |
1163 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1164 | reg = DSPCNTR(pipe); |
1165 | val = I915_READ(reg); | |
1166 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1167 | "plane %c assertion failure, should be disabled but not\n", | |
1168 | plane_name(pipe)); | |
19ec1358 | 1169 | return; |
28c05794 | 1170 | } |
19ec1358 | 1171 | |
b24e7179 | 1172 | /* Need to check both planes against the pipe */ |
08e2a7de | 1173 | for_each_pipe(i) { |
b24e7179 JB |
1174 | reg = DSPCNTR(i); |
1175 | val = I915_READ(reg); | |
1176 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1177 | DISPPLANE_SEL_PIPE_SHIFT; | |
1178 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1179 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1180 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1181 | } |
1182 | } | |
1183 | ||
19332d7a JB |
1184 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1185 | enum pipe pipe) | |
1186 | { | |
20674eef | 1187 | struct drm_device *dev = dev_priv->dev; |
19332d7a JB |
1188 | int reg, i; |
1189 | u32 val; | |
1190 | ||
20674eef VS |
1191 | if (IS_VALLEYVIEW(dev)) { |
1192 | for (i = 0; i < dev_priv->num_plane; i++) { | |
1193 | reg = SPCNTR(pipe, i); | |
1194 | val = I915_READ(reg); | |
1195 | WARN((val & SP_ENABLE), | |
1196 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", | |
1197 | sprite_name(pipe, i), pipe_name(pipe)); | |
1198 | } | |
1199 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1200 | reg = SPRCTL(pipe); | |
19332d7a | 1201 | val = I915_READ(reg); |
20674eef | 1202 | WARN((val & SPRITE_ENABLE), |
06da8da2 | 1203 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1204 | plane_name(pipe), pipe_name(pipe)); |
1205 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1206 | reg = DVSCNTR(pipe); | |
19332d7a | 1207 | val = I915_READ(reg); |
20674eef | 1208 | WARN((val & DVS_ENABLE), |
06da8da2 | 1209 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1210 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1211 | } |
1212 | } | |
1213 | ||
92f2584a JB |
1214 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1215 | { | |
1216 | u32 val; | |
1217 | bool enabled; | |
1218 | ||
9d82aa17 ED |
1219 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1220 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); | |
1221 | return; | |
1222 | } | |
1223 | ||
92f2584a JB |
1224 | val = I915_READ(PCH_DREF_CONTROL); |
1225 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1226 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1227 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1228 | } | |
1229 | ||
ab9412ba DV |
1230 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1231 | enum pipe pipe) | |
92f2584a JB |
1232 | { |
1233 | int reg; | |
1234 | u32 val; | |
1235 | bool enabled; | |
1236 | ||
ab9412ba | 1237 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1238 | val = I915_READ(reg); |
1239 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1240 | WARN(enabled, |
1241 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1242 | pipe_name(pipe)); | |
92f2584a JB |
1243 | } |
1244 | ||
4e634389 KP |
1245 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1246 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1247 | { |
1248 | if ((val & DP_PORT_EN) == 0) | |
1249 | return false; | |
1250 | ||
1251 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1252 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1253 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1254 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1255 | return false; | |
1256 | } else { | |
1257 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1258 | return false; | |
1259 | } | |
1260 | return true; | |
1261 | } | |
1262 | ||
1519b995 KP |
1263 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1264 | enum pipe pipe, u32 val) | |
1265 | { | |
dc0fa718 | 1266 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1267 | return false; |
1268 | ||
1269 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1270 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 KP |
1271 | return false; |
1272 | } else { | |
dc0fa718 | 1273 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1274 | return false; |
1275 | } | |
1276 | return true; | |
1277 | } | |
1278 | ||
1279 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1280 | enum pipe pipe, u32 val) | |
1281 | { | |
1282 | if ((val & LVDS_PORT_EN) == 0) | |
1283 | return false; | |
1284 | ||
1285 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1286 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1287 | return false; | |
1288 | } else { | |
1289 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1290 | return false; | |
1291 | } | |
1292 | return true; | |
1293 | } | |
1294 | ||
1295 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1296 | enum pipe pipe, u32 val) | |
1297 | { | |
1298 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1299 | return false; | |
1300 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1301 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1302 | return false; | |
1303 | } else { | |
1304 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1305 | return false; | |
1306 | } | |
1307 | return true; | |
1308 | } | |
1309 | ||
291906f1 | 1310 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1311 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1312 | { |
47a05eca | 1313 | u32 val = I915_READ(reg); |
4e634389 | 1314 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1315 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1316 | reg, pipe_name(pipe)); |
de9a35ab | 1317 | |
75c5da27 DV |
1318 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1319 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1320 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1321 | } |
1322 | ||
1323 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1324 | enum pipe pipe, int reg) | |
1325 | { | |
47a05eca | 1326 | u32 val = I915_READ(reg); |
b70ad586 | 1327 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1328 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1329 | reg, pipe_name(pipe)); |
de9a35ab | 1330 | |
dc0fa718 | 1331 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1332 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1333 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1334 | } |
1335 | ||
1336 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1337 | enum pipe pipe) | |
1338 | { | |
1339 | int reg; | |
1340 | u32 val; | |
291906f1 | 1341 | |
f0575e92 KP |
1342 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1343 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1344 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1345 | |
1346 | reg = PCH_ADPA; | |
1347 | val = I915_READ(reg); | |
b70ad586 | 1348 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1349 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1350 | pipe_name(pipe)); |
291906f1 JB |
1351 | |
1352 | reg = PCH_LVDS; | |
1353 | val = I915_READ(reg); | |
b70ad586 | 1354 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1355 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1356 | pipe_name(pipe)); |
291906f1 | 1357 | |
e2debe91 PZ |
1358 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1359 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1360 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1361 | } |
1362 | ||
40e9cf64 JB |
1363 | static void intel_init_dpio(struct drm_device *dev) |
1364 | { | |
1365 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1366 | ||
1367 | if (!IS_VALLEYVIEW(dev)) | |
1368 | return; | |
1369 | ||
8212d563 VS |
1370 | /* Enable the CRI clock source so we can get at the display */ |
1371 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | | |
1372 | DPLL_INTEGRATED_CRI_CLK_VLV); | |
1373 | ||
e4607fcf | 1374 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; |
40e9cf64 JB |
1375 | /* |
1376 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - | |
1377 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. | |
1378 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) | |
1379 | * b. The other bits such as sfr settings / modesel may all be set | |
1380 | * to 0. | |
1381 | * | |
1382 | * This should only be done on init and resume from S3 with both | |
1383 | * PLLs disabled, or we risk losing DPIO and PLL synchronization. | |
1384 | */ | |
1385 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); | |
1386 | } | |
1387 | ||
426115cf | 1388 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1389 | { |
426115cf DV |
1390 | struct drm_device *dev = crtc->base.dev; |
1391 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1392 | int reg = DPLL(crtc->pipe); | |
1393 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1394 | |
426115cf | 1395 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1396 | |
1397 | /* No really, not for ILK+ */ | |
1398 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1399 | ||
1400 | /* PLL is protected by panel, make sure we can write it */ | |
1401 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
426115cf | 1402 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1403 | |
426115cf DV |
1404 | I915_WRITE(reg, dpll); |
1405 | POSTING_READ(reg); | |
1406 | udelay(150); | |
1407 | ||
1408 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1409 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1410 | ||
1411 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1412 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1413 | |
1414 | /* We do this three times for luck */ | |
426115cf | 1415 | I915_WRITE(reg, dpll); |
87442f73 DV |
1416 | POSTING_READ(reg); |
1417 | udelay(150); /* wait for warmup */ | |
426115cf | 1418 | I915_WRITE(reg, dpll); |
87442f73 DV |
1419 | POSTING_READ(reg); |
1420 | udelay(150); /* wait for warmup */ | |
426115cf | 1421 | I915_WRITE(reg, dpll); |
87442f73 DV |
1422 | POSTING_READ(reg); |
1423 | udelay(150); /* wait for warmup */ | |
1424 | } | |
1425 | ||
66e3d5c0 | 1426 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1427 | { |
66e3d5c0 DV |
1428 | struct drm_device *dev = crtc->base.dev; |
1429 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1430 | int reg = DPLL(crtc->pipe); | |
1431 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1432 | |
66e3d5c0 | 1433 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1434 | |
63d7bbe9 | 1435 | /* No really, not for ILK+ */ |
87442f73 | 1436 | BUG_ON(dev_priv->info->gen >= 5); |
63d7bbe9 JB |
1437 | |
1438 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1439 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1440 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1441 | |
66e3d5c0 DV |
1442 | I915_WRITE(reg, dpll); |
1443 | ||
1444 | /* Wait for the clocks to stabilize. */ | |
1445 | POSTING_READ(reg); | |
1446 | udelay(150); | |
1447 | ||
1448 | if (INTEL_INFO(dev)->gen >= 4) { | |
1449 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1450 | crtc->config.dpll_hw_state.dpll_md); | |
1451 | } else { | |
1452 | /* The pixel multiplier can only be updated once the | |
1453 | * DPLL is enabled and the clocks are stable. | |
1454 | * | |
1455 | * So write it again. | |
1456 | */ | |
1457 | I915_WRITE(reg, dpll); | |
1458 | } | |
63d7bbe9 JB |
1459 | |
1460 | /* We do this three times for luck */ | |
66e3d5c0 | 1461 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1462 | POSTING_READ(reg); |
1463 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1464 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1465 | POSTING_READ(reg); |
1466 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1467 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1468 | POSTING_READ(reg); |
1469 | udelay(150); /* wait for warmup */ | |
1470 | } | |
1471 | ||
1472 | /** | |
50b44a44 | 1473 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1474 | * @dev_priv: i915 private structure |
1475 | * @pipe: pipe PLL to disable | |
1476 | * | |
1477 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1478 | * | |
1479 | * Note! This is for pre-ILK only. | |
1480 | */ | |
50b44a44 | 1481 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1482 | { |
63d7bbe9 JB |
1483 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1484 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1485 | return; | |
1486 | ||
1487 | /* Make sure the pipe isn't still relying on us */ | |
1488 | assert_pipe_disabled(dev_priv, pipe); | |
1489 | ||
50b44a44 DV |
1490 | I915_WRITE(DPLL(pipe), 0); |
1491 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1492 | } |
1493 | ||
f6071166 JB |
1494 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1495 | { | |
1496 | u32 val = 0; | |
1497 | ||
1498 | /* Make sure the pipe isn't still relying on us */ | |
1499 | assert_pipe_disabled(dev_priv, pipe); | |
1500 | ||
1501 | /* Leave integrated clock source enabled */ | |
1502 | if (pipe == PIPE_B) | |
1503 | val = DPLL_INTEGRATED_CRI_CLK_VLV; | |
1504 | I915_WRITE(DPLL(pipe), val); | |
1505 | POSTING_READ(DPLL(pipe)); | |
1506 | } | |
1507 | ||
e4607fcf CML |
1508 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1509 | struct intel_digital_port *dport) | |
89b667f8 JB |
1510 | { |
1511 | u32 port_mask; | |
1512 | ||
e4607fcf CML |
1513 | switch (dport->port) { |
1514 | case PORT_B: | |
89b667f8 | 1515 | port_mask = DPLL_PORTB_READY_MASK; |
e4607fcf CML |
1516 | break; |
1517 | case PORT_C: | |
89b667f8 | 1518 | port_mask = DPLL_PORTC_READY_MASK; |
e4607fcf CML |
1519 | break; |
1520 | default: | |
1521 | BUG(); | |
1522 | } | |
89b667f8 JB |
1523 | |
1524 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) | |
1525 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", | |
be46ffd4 | 1526 | port_name(dport->port), I915_READ(DPLL(0))); |
89b667f8 JB |
1527 | } |
1528 | ||
92f2584a | 1529 | /** |
e72f9fbf | 1530 | * ironlake_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1531 | * @dev_priv: i915 private structure |
1532 | * @pipe: pipe PLL to enable | |
1533 | * | |
1534 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1535 | * drives the transcoder clock. | |
1536 | */ | |
e2b78267 | 1537 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1538 | { |
e2b78267 DV |
1539 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1540 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
92f2584a | 1541 | |
48da64a8 | 1542 | /* PCH PLLs only available on ILK, SNB and IVB */ |
92f2584a | 1543 | BUG_ON(dev_priv->info->gen < 5); |
87a875bb | 1544 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1545 | return; |
1546 | ||
1547 | if (WARN_ON(pll->refcount == 0)) | |
1548 | return; | |
ee7b9f93 | 1549 | |
46edb027 DV |
1550 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1551 | pll->name, pll->active, pll->on, | |
e2b78267 | 1552 | crtc->base.base.id); |
92f2584a | 1553 | |
cdbd2316 DV |
1554 | if (pll->active++) { |
1555 | WARN_ON(!pll->on); | |
e9d6944e | 1556 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1557 | return; |
1558 | } | |
f4a091c7 | 1559 | WARN_ON(pll->on); |
ee7b9f93 | 1560 | |
46edb027 | 1561 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1562 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1563 | pll->on = true; |
92f2584a JB |
1564 | } |
1565 | ||
e2b78267 | 1566 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1567 | { |
e2b78267 DV |
1568 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1569 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
4c609cb8 | 1570 | |
92f2584a JB |
1571 | /* PCH only available on ILK+ */ |
1572 | BUG_ON(dev_priv->info->gen < 5); | |
87a875bb | 1573 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1574 | return; |
92f2584a | 1575 | |
48da64a8 CW |
1576 | if (WARN_ON(pll->refcount == 0)) |
1577 | return; | |
7a419866 | 1578 | |
46edb027 DV |
1579 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1580 | pll->name, pll->active, pll->on, | |
e2b78267 | 1581 | crtc->base.base.id); |
7a419866 | 1582 | |
48da64a8 | 1583 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1584 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1585 | return; |
1586 | } | |
1587 | ||
e9d6944e | 1588 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1589 | WARN_ON(!pll->on); |
cdbd2316 | 1590 | if (--pll->active) |
7a419866 | 1591 | return; |
ee7b9f93 | 1592 | |
46edb027 | 1593 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1594 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1595 | pll->on = false; |
92f2584a JB |
1596 | } |
1597 | ||
b8a4f404 PZ |
1598 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1599 | enum pipe pipe) | |
040484af | 1600 | { |
23670b32 | 1601 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1602 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1603 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1604 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1605 | |
1606 | /* PCH only available on ILK+ */ | |
1607 | BUG_ON(dev_priv->info->gen < 5); | |
1608 | ||
1609 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1610 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1611 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1612 | |
1613 | /* FDI must be feeding us bits for PCH ports */ | |
1614 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1615 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1616 | ||
23670b32 DV |
1617 | if (HAS_PCH_CPT(dev)) { |
1618 | /* Workaround: Set the timing override bit before enabling the | |
1619 | * pch transcoder. */ | |
1620 | reg = TRANS_CHICKEN2(pipe); | |
1621 | val = I915_READ(reg); | |
1622 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1623 | I915_WRITE(reg, val); | |
59c859d6 | 1624 | } |
23670b32 | 1625 | |
ab9412ba | 1626 | reg = PCH_TRANSCONF(pipe); |
040484af | 1627 | val = I915_READ(reg); |
5f7f726d | 1628 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1629 | |
1630 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1631 | /* | |
1632 | * make the BPC in transcoder be consistent with | |
1633 | * that in pipeconf reg. | |
1634 | */ | |
dfd07d72 DV |
1635 | val &= ~PIPECONF_BPC_MASK; |
1636 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1637 | } |
5f7f726d PZ |
1638 | |
1639 | val &= ~TRANS_INTERLACE_MASK; | |
1640 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1641 | if (HAS_PCH_IBX(dev_priv->dev) && |
1642 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1643 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1644 | else | |
1645 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1646 | else |
1647 | val |= TRANS_PROGRESSIVE; | |
1648 | ||
040484af JB |
1649 | I915_WRITE(reg, val | TRANS_ENABLE); |
1650 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1651 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1652 | } |
1653 | ||
8fb033d7 | 1654 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1655 | enum transcoder cpu_transcoder) |
040484af | 1656 | { |
8fb033d7 | 1657 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1658 | |
1659 | /* PCH only available on ILK+ */ | |
1660 | BUG_ON(dev_priv->info->gen < 5); | |
1661 | ||
8fb033d7 | 1662 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1663 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1664 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1665 | |
223a6fdf PZ |
1666 | /* Workaround: set timing override bit. */ |
1667 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1668 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1669 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1670 | ||
25f3ef11 | 1671 | val = TRANS_ENABLE; |
937bb610 | 1672 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1673 | |
9a76b1c6 PZ |
1674 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1675 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1676 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1677 | else |
1678 | val |= TRANS_PROGRESSIVE; | |
1679 | ||
ab9412ba DV |
1680 | I915_WRITE(LPT_TRANSCONF, val); |
1681 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1682 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1683 | } |
1684 | ||
b8a4f404 PZ |
1685 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1686 | enum pipe pipe) | |
040484af | 1687 | { |
23670b32 DV |
1688 | struct drm_device *dev = dev_priv->dev; |
1689 | uint32_t reg, val; | |
040484af JB |
1690 | |
1691 | /* FDI relies on the transcoder */ | |
1692 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1693 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1694 | ||
291906f1 JB |
1695 | /* Ports must be off as well */ |
1696 | assert_pch_ports_disabled(dev_priv, pipe); | |
1697 | ||
ab9412ba | 1698 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1699 | val = I915_READ(reg); |
1700 | val &= ~TRANS_ENABLE; | |
1701 | I915_WRITE(reg, val); | |
1702 | /* wait for PCH transcoder off, transcoder state */ | |
1703 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1704 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1705 | |
1706 | if (!HAS_PCH_IBX(dev)) { | |
1707 | /* Workaround: Clear the timing override chicken bit again. */ | |
1708 | reg = TRANS_CHICKEN2(pipe); | |
1709 | val = I915_READ(reg); | |
1710 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1711 | I915_WRITE(reg, val); | |
1712 | } | |
040484af JB |
1713 | } |
1714 | ||
ab4d966c | 1715 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1716 | { |
8fb033d7 PZ |
1717 | u32 val; |
1718 | ||
ab9412ba | 1719 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1720 | val &= ~TRANS_ENABLE; |
ab9412ba | 1721 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1722 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1723 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1724 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1725 | |
1726 | /* Workaround: clear timing override bit. */ | |
1727 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1728 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1729 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1730 | } |
1731 | ||
b24e7179 | 1732 | /** |
309cfea8 | 1733 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1734 | * @dev_priv: i915 private structure |
1735 | * @pipe: pipe to enable | |
040484af | 1736 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1737 | * |
1738 | * Enable @pipe, making sure that various hardware specific requirements | |
1739 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1740 | * | |
1741 | * @pipe should be %PIPE_A or %PIPE_B. | |
1742 | * | |
1743 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1744 | * returning. | |
1745 | */ | |
040484af | 1746 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
23538ef1 | 1747 | bool pch_port, bool dsi) |
b24e7179 | 1748 | { |
702e7a56 PZ |
1749 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1750 | pipe); | |
1a240d4d | 1751 | enum pipe pch_transcoder; |
b24e7179 JB |
1752 | int reg; |
1753 | u32 val; | |
1754 | ||
58c6eaa2 | 1755 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1756 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1757 | assert_sprites_disabled(dev_priv, pipe); |
1758 | ||
681e5811 | 1759 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1760 | pch_transcoder = TRANSCODER_A; |
1761 | else | |
1762 | pch_transcoder = pipe; | |
1763 | ||
b24e7179 JB |
1764 | /* |
1765 | * A pipe without a PLL won't actually be able to drive bits from | |
1766 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1767 | * need the check. | |
1768 | */ | |
1769 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
23538ef1 JN |
1770 | if (dsi) |
1771 | assert_dsi_pll_enabled(dev_priv); | |
1772 | else | |
1773 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1774 | else { |
1775 | if (pch_port) { | |
1776 | /* if driving the PCH, we need FDI enabled */ | |
cc391bbb | 1777 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1778 | assert_fdi_tx_pll_enabled(dev_priv, |
1779 | (enum pipe) cpu_transcoder); | |
040484af JB |
1780 | } |
1781 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1782 | } | |
b24e7179 | 1783 | |
702e7a56 | 1784 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1785 | val = I915_READ(reg); |
00d70b15 CW |
1786 | if (val & PIPECONF_ENABLE) |
1787 | return; | |
1788 | ||
1789 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1790 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1791 | } | |
1792 | ||
1793 | /** | |
309cfea8 | 1794 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1795 | * @dev_priv: i915 private structure |
1796 | * @pipe: pipe to disable | |
1797 | * | |
1798 | * Disable @pipe, making sure that various hardware specific requirements | |
1799 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1800 | * | |
1801 | * @pipe should be %PIPE_A or %PIPE_B. | |
1802 | * | |
1803 | * Will wait until the pipe has shut down before returning. | |
1804 | */ | |
1805 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1806 | enum pipe pipe) | |
1807 | { | |
702e7a56 PZ |
1808 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1809 | pipe); | |
b24e7179 JB |
1810 | int reg; |
1811 | u32 val; | |
1812 | ||
1813 | /* | |
1814 | * Make sure planes won't keep trying to pump pixels to us, | |
1815 | * or we might hang the display. | |
1816 | */ | |
1817 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1818 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1819 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
1820 | |
1821 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1822 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1823 | return; | |
1824 | ||
702e7a56 | 1825 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1826 | val = I915_READ(reg); |
00d70b15 CW |
1827 | if ((val & PIPECONF_ENABLE) == 0) |
1828 | return; | |
1829 | ||
1830 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1831 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1832 | } | |
1833 | ||
d74362c9 KP |
1834 | /* |
1835 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1836 | * trigger in order to latch. The display address reg provides this. | |
1837 | */ | |
1dba99f4 VS |
1838 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
1839 | enum plane plane) | |
d74362c9 | 1840 | { |
1dba99f4 VS |
1841 | u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); |
1842 | ||
1843 | I915_WRITE(reg, I915_READ(reg)); | |
1844 | POSTING_READ(reg); | |
d74362c9 KP |
1845 | } |
1846 | ||
b24e7179 | 1847 | /** |
d1de00ef | 1848 | * intel_enable_primary_plane - enable the primary plane on a given pipe |
b24e7179 JB |
1849 | * @dev_priv: i915 private structure |
1850 | * @plane: plane to enable | |
1851 | * @pipe: pipe being fed | |
1852 | * | |
1853 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1854 | */ | |
d1de00ef VS |
1855 | static void intel_enable_primary_plane(struct drm_i915_private *dev_priv, |
1856 | enum plane plane, enum pipe pipe) | |
b24e7179 | 1857 | { |
939c2fe8 VS |
1858 | struct intel_crtc *intel_crtc = |
1859 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
1860 | int reg; |
1861 | u32 val; | |
1862 | ||
1863 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1864 | assert_pipe_enabled(dev_priv, pipe); | |
1865 | ||
4c445e0e | 1866 | WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n"); |
0037f71c | 1867 | |
4c445e0e | 1868 | intel_crtc->primary_enabled = true; |
939c2fe8 | 1869 | |
b24e7179 JB |
1870 | reg = DSPCNTR(plane); |
1871 | val = I915_READ(reg); | |
00d70b15 CW |
1872 | if (val & DISPLAY_PLANE_ENABLE) |
1873 | return; | |
1874 | ||
1875 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 1876 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
1877 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1878 | } | |
1879 | ||
b24e7179 | 1880 | /** |
d1de00ef | 1881 | * intel_disable_primary_plane - disable the primary plane |
b24e7179 JB |
1882 | * @dev_priv: i915 private structure |
1883 | * @plane: plane to disable | |
1884 | * @pipe: pipe consuming the data | |
1885 | * | |
1886 | * Disable @plane; should be an independent operation. | |
1887 | */ | |
d1de00ef VS |
1888 | static void intel_disable_primary_plane(struct drm_i915_private *dev_priv, |
1889 | enum plane plane, enum pipe pipe) | |
b24e7179 | 1890 | { |
939c2fe8 VS |
1891 | struct intel_crtc *intel_crtc = |
1892 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
b24e7179 JB |
1893 | int reg; |
1894 | u32 val; | |
1895 | ||
4c445e0e | 1896 | WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n"); |
0037f71c | 1897 | |
4c445e0e | 1898 | intel_crtc->primary_enabled = false; |
939c2fe8 | 1899 | |
b24e7179 JB |
1900 | reg = DSPCNTR(plane); |
1901 | val = I915_READ(reg); | |
00d70b15 CW |
1902 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1903 | return; | |
1904 | ||
1905 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
1dba99f4 | 1906 | intel_flush_primary_plane(dev_priv, plane); |
b24e7179 JB |
1907 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1908 | } | |
1909 | ||
693db184 CW |
1910 | static bool need_vtd_wa(struct drm_device *dev) |
1911 | { | |
1912 | #ifdef CONFIG_INTEL_IOMMU | |
1913 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
1914 | return true; | |
1915 | #endif | |
1916 | return false; | |
1917 | } | |
1918 | ||
127bd2ac | 1919 | int |
48b956c5 | 1920 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1921 | struct drm_i915_gem_object *obj, |
919926ae | 1922 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1923 | { |
ce453d81 | 1924 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1925 | u32 alignment; |
1926 | int ret; | |
1927 | ||
05394f39 | 1928 | switch (obj->tiling_mode) { |
6b95a207 | 1929 | case I915_TILING_NONE: |
534843da CW |
1930 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1931 | alignment = 128 * 1024; | |
a6c45cf0 | 1932 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1933 | alignment = 4 * 1024; |
1934 | else | |
1935 | alignment = 64 * 1024; | |
6b95a207 KH |
1936 | break; |
1937 | case I915_TILING_X: | |
1938 | /* pin() will align the object as required by fence */ | |
1939 | alignment = 0; | |
1940 | break; | |
1941 | case I915_TILING_Y: | |
80075d49 | 1942 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
1943 | return -EINVAL; |
1944 | default: | |
1945 | BUG(); | |
1946 | } | |
1947 | ||
693db184 CW |
1948 | /* Note that the w/a also requires 64 PTE of padding following the |
1949 | * bo. We currently fill all unused PTE with the shadow page and so | |
1950 | * we should always have valid PTE following the scanout preventing | |
1951 | * the VT-d warning. | |
1952 | */ | |
1953 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
1954 | alignment = 256 * 1024; | |
1955 | ||
ce453d81 | 1956 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 1957 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 1958 | if (ret) |
ce453d81 | 1959 | goto err_interruptible; |
6b95a207 KH |
1960 | |
1961 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1962 | * fence, whereas 965+ only requires a fence if using | |
1963 | * framebuffer compression. For simplicity, we always install | |
1964 | * a fence as the cost is not that onerous. | |
1965 | */ | |
06d98131 | 1966 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
1967 | if (ret) |
1968 | goto err_unpin; | |
1690e1eb | 1969 | |
9a5a53b3 | 1970 | i915_gem_object_pin_fence(obj); |
6b95a207 | 1971 | |
ce453d81 | 1972 | dev_priv->mm.interruptible = true; |
6b95a207 | 1973 | return 0; |
48b956c5 CW |
1974 | |
1975 | err_unpin: | |
cc98b413 | 1976 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
1977 | err_interruptible: |
1978 | dev_priv->mm.interruptible = true; | |
48b956c5 | 1979 | return ret; |
6b95a207 KH |
1980 | } |
1981 | ||
1690e1eb CW |
1982 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1983 | { | |
1984 | i915_gem_object_unpin_fence(obj); | |
cc98b413 | 1985 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
1986 | } |
1987 | ||
c2c75131 DV |
1988 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
1989 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
1990 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
1991 | unsigned int tiling_mode, | |
1992 | unsigned int cpp, | |
1993 | unsigned int pitch) | |
c2c75131 | 1994 | { |
bc752862 CW |
1995 | if (tiling_mode != I915_TILING_NONE) { |
1996 | unsigned int tile_rows, tiles; | |
c2c75131 | 1997 | |
bc752862 CW |
1998 | tile_rows = *y / 8; |
1999 | *y %= 8; | |
c2c75131 | 2000 | |
bc752862 CW |
2001 | tiles = *x / (512/cpp); |
2002 | *x %= 512/cpp; | |
2003 | ||
2004 | return tile_rows * pitch * 8 + tiles * 4096; | |
2005 | } else { | |
2006 | unsigned int offset; | |
2007 | ||
2008 | offset = *y * pitch + *x * cpp; | |
2009 | *y = 0; | |
2010 | *x = (offset & 4095) / cpp; | |
2011 | return offset & -4096; | |
2012 | } | |
c2c75131 DV |
2013 | } |
2014 | ||
17638cd6 JB |
2015 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2016 | int x, int y) | |
81255565 JB |
2017 | { |
2018 | struct drm_device *dev = crtc->dev; | |
2019 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2020 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2021 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2022 | struct drm_i915_gem_object *obj; |
81255565 | 2023 | int plane = intel_crtc->plane; |
e506a0c6 | 2024 | unsigned long linear_offset; |
81255565 | 2025 | u32 dspcntr; |
5eddb70b | 2026 | u32 reg; |
81255565 JB |
2027 | |
2028 | switch (plane) { | |
2029 | case 0: | |
2030 | case 1: | |
2031 | break; | |
2032 | default: | |
84f44ce7 | 2033 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
81255565 JB |
2034 | return -EINVAL; |
2035 | } | |
2036 | ||
2037 | intel_fb = to_intel_framebuffer(fb); | |
2038 | obj = intel_fb->obj; | |
81255565 | 2039 | |
5eddb70b CW |
2040 | reg = DSPCNTR(plane); |
2041 | dspcntr = I915_READ(reg); | |
81255565 JB |
2042 | /* Mask out pixel format bits in case we change it */ |
2043 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2044 | switch (fb->pixel_format) { |
2045 | case DRM_FORMAT_C8: | |
81255565 JB |
2046 | dspcntr |= DISPPLANE_8BPP; |
2047 | break; | |
57779d06 VS |
2048 | case DRM_FORMAT_XRGB1555: |
2049 | case DRM_FORMAT_ARGB1555: | |
2050 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2051 | break; |
57779d06 VS |
2052 | case DRM_FORMAT_RGB565: |
2053 | dspcntr |= DISPPLANE_BGRX565; | |
2054 | break; | |
2055 | case DRM_FORMAT_XRGB8888: | |
2056 | case DRM_FORMAT_ARGB8888: | |
2057 | dspcntr |= DISPPLANE_BGRX888; | |
2058 | break; | |
2059 | case DRM_FORMAT_XBGR8888: | |
2060 | case DRM_FORMAT_ABGR8888: | |
2061 | dspcntr |= DISPPLANE_RGBX888; | |
2062 | break; | |
2063 | case DRM_FORMAT_XRGB2101010: | |
2064 | case DRM_FORMAT_ARGB2101010: | |
2065 | dspcntr |= DISPPLANE_BGRX101010; | |
2066 | break; | |
2067 | case DRM_FORMAT_XBGR2101010: | |
2068 | case DRM_FORMAT_ABGR2101010: | |
2069 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2070 | break; |
2071 | default: | |
baba133a | 2072 | BUG(); |
81255565 | 2073 | } |
57779d06 | 2074 | |
a6c45cf0 | 2075 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2076 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2077 | dspcntr |= DISPPLANE_TILED; |
2078 | else | |
2079 | dspcntr &= ~DISPPLANE_TILED; | |
2080 | } | |
2081 | ||
de1aa629 VS |
2082 | if (IS_G4X(dev)) |
2083 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2084 | ||
5eddb70b | 2085 | I915_WRITE(reg, dspcntr); |
81255565 | 2086 | |
e506a0c6 | 2087 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2088 | |
c2c75131 DV |
2089 | if (INTEL_INFO(dev)->gen >= 4) { |
2090 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2091 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2092 | fb->bits_per_pixel / 8, | |
2093 | fb->pitches[0]); | |
c2c75131 DV |
2094 | linear_offset -= intel_crtc->dspaddr_offset; |
2095 | } else { | |
e506a0c6 | 2096 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2097 | } |
e506a0c6 | 2098 | |
f343c5f6 BW |
2099 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2100 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2101 | fb->pitches[0]); | |
01f2c773 | 2102 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2103 | if (INTEL_INFO(dev)->gen >= 4) { |
c2c75131 | 2104 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
f343c5f6 | 2105 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
5eddb70b | 2106 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2107 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2108 | } else |
f343c5f6 | 2109 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2110 | POSTING_READ(reg); |
81255565 | 2111 | |
17638cd6 JB |
2112 | return 0; |
2113 | } | |
2114 | ||
2115 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2116 | struct drm_framebuffer *fb, int x, int y) | |
2117 | { | |
2118 | struct drm_device *dev = crtc->dev; | |
2119 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2120 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2121 | struct intel_framebuffer *intel_fb; | |
2122 | struct drm_i915_gem_object *obj; | |
2123 | int plane = intel_crtc->plane; | |
e506a0c6 | 2124 | unsigned long linear_offset; |
17638cd6 JB |
2125 | u32 dspcntr; |
2126 | u32 reg; | |
2127 | ||
2128 | switch (plane) { | |
2129 | case 0: | |
2130 | case 1: | |
27f8227b | 2131 | case 2: |
17638cd6 JB |
2132 | break; |
2133 | default: | |
84f44ce7 | 2134 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
17638cd6 JB |
2135 | return -EINVAL; |
2136 | } | |
2137 | ||
2138 | intel_fb = to_intel_framebuffer(fb); | |
2139 | obj = intel_fb->obj; | |
2140 | ||
2141 | reg = DSPCNTR(plane); | |
2142 | dspcntr = I915_READ(reg); | |
2143 | /* Mask out pixel format bits in case we change it */ | |
2144 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2145 | switch (fb->pixel_format) { |
2146 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2147 | dspcntr |= DISPPLANE_8BPP; |
2148 | break; | |
57779d06 VS |
2149 | case DRM_FORMAT_RGB565: |
2150 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2151 | break; |
57779d06 VS |
2152 | case DRM_FORMAT_XRGB8888: |
2153 | case DRM_FORMAT_ARGB8888: | |
2154 | dspcntr |= DISPPLANE_BGRX888; | |
2155 | break; | |
2156 | case DRM_FORMAT_XBGR8888: | |
2157 | case DRM_FORMAT_ABGR8888: | |
2158 | dspcntr |= DISPPLANE_RGBX888; | |
2159 | break; | |
2160 | case DRM_FORMAT_XRGB2101010: | |
2161 | case DRM_FORMAT_ARGB2101010: | |
2162 | dspcntr |= DISPPLANE_BGRX101010; | |
2163 | break; | |
2164 | case DRM_FORMAT_XBGR2101010: | |
2165 | case DRM_FORMAT_ABGR2101010: | |
2166 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2167 | break; |
2168 | default: | |
baba133a | 2169 | BUG(); |
17638cd6 JB |
2170 | } |
2171 | ||
2172 | if (obj->tiling_mode != I915_TILING_NONE) | |
2173 | dspcntr |= DISPPLANE_TILED; | |
2174 | else | |
2175 | dspcntr &= ~DISPPLANE_TILED; | |
2176 | ||
b42c6009 | 2177 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
1f5d76db PZ |
2178 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; |
2179 | else | |
2180 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
17638cd6 JB |
2181 | |
2182 | I915_WRITE(reg, dspcntr); | |
2183 | ||
e506a0c6 | 2184 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2185 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2186 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2187 | fb->bits_per_pixel / 8, | |
2188 | fb->pitches[0]); | |
c2c75131 | 2189 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2190 | |
f343c5f6 BW |
2191 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2192 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2193 | fb->pitches[0]); | |
01f2c773 | 2194 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
c2c75131 | 2195 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
f343c5f6 | 2196 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
b3dc685e | 2197 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2198 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2199 | } else { | |
2200 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2201 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2202 | } | |
17638cd6 JB |
2203 | POSTING_READ(reg); |
2204 | ||
2205 | return 0; | |
2206 | } | |
2207 | ||
2208 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2209 | static int | |
2210 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2211 | int x, int y, enum mode_set_atomic state) | |
2212 | { | |
2213 | struct drm_device *dev = crtc->dev; | |
2214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2215 | |
6b8e6ed0 CW |
2216 | if (dev_priv->display.disable_fbc) |
2217 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2218 | intel_increase_pllclock(crtc); |
81255565 | 2219 | |
6b8e6ed0 | 2220 | return dev_priv->display.update_plane(crtc, fb, x, y); |
81255565 JB |
2221 | } |
2222 | ||
96a02917 VS |
2223 | void intel_display_handle_reset(struct drm_device *dev) |
2224 | { | |
2225 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2226 | struct drm_crtc *crtc; | |
2227 | ||
2228 | /* | |
2229 | * Flips in the rings have been nuked by the reset, | |
2230 | * so complete all pending flips so that user space | |
2231 | * will get its events and not get stuck. | |
2232 | * | |
2233 | * Also update the base address of all primary | |
2234 | * planes to the the last fb to make sure we're | |
2235 | * showing the correct fb after a reset. | |
2236 | * | |
2237 | * Need to make two loops over the crtcs so that we | |
2238 | * don't try to grab a crtc mutex before the | |
2239 | * pending_flip_queue really got woken up. | |
2240 | */ | |
2241 | ||
2242 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2243 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2244 | enum plane plane = intel_crtc->plane; | |
2245 | ||
2246 | intel_prepare_page_flip(dev, plane); | |
2247 | intel_finish_page_flip_plane(dev, plane); | |
2248 | } | |
2249 | ||
2250 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2251 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2252 | ||
2253 | mutex_lock(&crtc->mutex); | |
947fdaad CW |
2254 | /* |
2255 | * FIXME: Once we have proper support for primary planes (and | |
2256 | * disabling them without disabling the entire crtc) allow again | |
2257 | * a NULL crtc->fb. | |
2258 | */ | |
2259 | if (intel_crtc->active && crtc->fb) | |
96a02917 VS |
2260 | dev_priv->display.update_plane(crtc, crtc->fb, |
2261 | crtc->x, crtc->y); | |
2262 | mutex_unlock(&crtc->mutex); | |
2263 | } | |
2264 | } | |
2265 | ||
14667a4b CW |
2266 | static int |
2267 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2268 | { | |
2269 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2270 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2271 | bool was_interruptible = dev_priv->mm.interruptible; | |
2272 | int ret; | |
2273 | ||
14667a4b CW |
2274 | /* Big Hammer, we also need to ensure that any pending |
2275 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2276 | * current scanout is retired before unpinning the old | |
2277 | * framebuffer. | |
2278 | * | |
2279 | * This should only fail upon a hung GPU, in which case we | |
2280 | * can safely continue. | |
2281 | */ | |
2282 | dev_priv->mm.interruptible = false; | |
2283 | ret = i915_gem_object_finish_gpu(obj); | |
2284 | dev_priv->mm.interruptible = was_interruptible; | |
2285 | ||
2286 | return ret; | |
2287 | } | |
2288 | ||
198598d0 VS |
2289 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
2290 | { | |
2291 | struct drm_device *dev = crtc->dev; | |
2292 | struct drm_i915_master_private *master_priv; | |
2293 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2294 | ||
2295 | if (!dev->primary->master) | |
2296 | return; | |
2297 | ||
2298 | master_priv = dev->primary->master->driver_priv; | |
2299 | if (!master_priv->sarea_priv) | |
2300 | return; | |
2301 | ||
2302 | switch (intel_crtc->pipe) { | |
2303 | case 0: | |
2304 | master_priv->sarea_priv->pipeA_x = x; | |
2305 | master_priv->sarea_priv->pipeA_y = y; | |
2306 | break; | |
2307 | case 1: | |
2308 | master_priv->sarea_priv->pipeB_x = x; | |
2309 | master_priv->sarea_priv->pipeB_y = y; | |
2310 | break; | |
2311 | default: | |
2312 | break; | |
2313 | } | |
2314 | } | |
2315 | ||
5c3b82e2 | 2316 | static int |
3c4fdcfb | 2317 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2318 | struct drm_framebuffer *fb) |
79e53945 JB |
2319 | { |
2320 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2321 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2322 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2323 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2324 | int ret; |
79e53945 JB |
2325 | |
2326 | /* no fb bound */ | |
94352cf9 | 2327 | if (!fb) { |
a5071c2f | 2328 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2329 | return 0; |
2330 | } | |
2331 | ||
7eb552ae | 2332 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2333 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2334 | plane_name(intel_crtc->plane), | |
2335 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2336 | return -EINVAL; |
79e53945 JB |
2337 | } |
2338 | ||
5c3b82e2 | 2339 | mutex_lock(&dev->struct_mutex); |
265db958 | 2340 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2341 | to_intel_framebuffer(fb)->obj, |
919926ae | 2342 | NULL); |
5c3b82e2 CW |
2343 | if (ret != 0) { |
2344 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2345 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2346 | return ret; |
2347 | } | |
79e53945 | 2348 | |
bb2043de DL |
2349 | /* |
2350 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2351 | * that in compute_mode_changes we check the native mode (not the pfit | |
2352 | * mode) to see if we can flip rather than do a full mode set. In the | |
2353 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2354 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2355 | * sized surface. | |
2356 | * | |
2357 | * To fix this properly, we need to hoist the checks up into | |
2358 | * compute_mode_changes (or above), check the actual pfit state and | |
2359 | * whether the platform allows pfit disable with pipe active, and only | |
2360 | * then update the pipesrc and pfit state, even on the flip path. | |
2361 | */ | |
4d6a3e63 | 2362 | if (i915_fastboot) { |
d7bf63f2 DL |
2363 | const struct drm_display_mode *adjusted_mode = |
2364 | &intel_crtc->config.adjusted_mode; | |
2365 | ||
4d6a3e63 | 2366 | I915_WRITE(PIPESRC(intel_crtc->pipe), |
d7bf63f2 DL |
2367 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | |
2368 | (adjusted_mode->crtc_vdisplay - 1)); | |
fd4daa9c | 2369 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2370 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2371 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2372 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2373 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2374 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2375 | } | |
2376 | } | |
2377 | ||
94352cf9 | 2378 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
4e6cfefc | 2379 | if (ret) { |
94352cf9 | 2380 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
5c3b82e2 | 2381 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2382 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2383 | return ret; |
79e53945 | 2384 | } |
3c4fdcfb | 2385 | |
94352cf9 DV |
2386 | old_fb = crtc->fb; |
2387 | crtc->fb = fb; | |
6c4c86f5 DV |
2388 | crtc->x = x; |
2389 | crtc->y = y; | |
94352cf9 | 2390 | |
b7f1de28 | 2391 | if (old_fb) { |
d7697eea DV |
2392 | if (intel_crtc->active && old_fb != fb) |
2393 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2394 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2395 | } |
652c393a | 2396 | |
6b8e6ed0 | 2397 | intel_update_fbc(dev); |
4906557e | 2398 | intel_edp_psr_update(dev); |
5c3b82e2 | 2399 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2400 | |
198598d0 | 2401 | intel_crtc_update_sarea_pos(crtc, x, y); |
5c3b82e2 CW |
2402 | |
2403 | return 0; | |
79e53945 JB |
2404 | } |
2405 | ||
5e84e1a4 ZW |
2406 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2407 | { | |
2408 | struct drm_device *dev = crtc->dev; | |
2409 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2410 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2411 | int pipe = intel_crtc->pipe; | |
2412 | u32 reg, temp; | |
2413 | ||
2414 | /* enable normal train */ | |
2415 | reg = FDI_TX_CTL(pipe); | |
2416 | temp = I915_READ(reg); | |
61e499bf | 2417 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2418 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2419 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2420 | } else { |
2421 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2422 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2423 | } |
5e84e1a4 ZW |
2424 | I915_WRITE(reg, temp); |
2425 | ||
2426 | reg = FDI_RX_CTL(pipe); | |
2427 | temp = I915_READ(reg); | |
2428 | if (HAS_PCH_CPT(dev)) { | |
2429 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2430 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2431 | } else { | |
2432 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2433 | temp |= FDI_LINK_TRAIN_NONE; | |
2434 | } | |
2435 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2436 | ||
2437 | /* wait one idle pattern time */ | |
2438 | POSTING_READ(reg); | |
2439 | udelay(1000); | |
357555c0 JB |
2440 | |
2441 | /* IVB wants error correction enabled */ | |
2442 | if (IS_IVYBRIDGE(dev)) | |
2443 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2444 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2445 | } |
2446 | ||
1fbc0d78 | 2447 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 2448 | { |
1fbc0d78 DV |
2449 | return crtc->base.enabled && crtc->active && |
2450 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
2451 | } |
2452 | ||
01a415fd DV |
2453 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2454 | { | |
2455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2456 | struct intel_crtc *pipe_B_crtc = | |
2457 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2458 | struct intel_crtc *pipe_C_crtc = | |
2459 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2460 | uint32_t temp; | |
2461 | ||
1e833f40 DV |
2462 | /* |
2463 | * When everything is off disable fdi C so that we could enable fdi B | |
2464 | * with all lanes. Note that we don't care about enabled pipes without | |
2465 | * an enabled pch encoder. | |
2466 | */ | |
2467 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2468 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2469 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2470 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2471 | ||
2472 | temp = I915_READ(SOUTH_CHICKEN1); | |
2473 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2474 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2475 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2476 | } | |
2477 | } | |
2478 | ||
8db9d77b ZW |
2479 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2480 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2481 | { | |
2482 | struct drm_device *dev = crtc->dev; | |
2483 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2484 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2485 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2486 | int plane = intel_crtc->plane; |
5eddb70b | 2487 | u32 reg, temp, tries; |
8db9d77b | 2488 | |
0fc932b8 JB |
2489 | /* FDI needs bits from pipe & plane first */ |
2490 | assert_pipe_enabled(dev_priv, pipe); | |
2491 | assert_plane_enabled(dev_priv, plane); | |
2492 | ||
e1a44743 AJ |
2493 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2494 | for train result */ | |
5eddb70b CW |
2495 | reg = FDI_RX_IMR(pipe); |
2496 | temp = I915_READ(reg); | |
e1a44743 AJ |
2497 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2498 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2499 | I915_WRITE(reg, temp); |
2500 | I915_READ(reg); | |
e1a44743 AJ |
2501 | udelay(150); |
2502 | ||
8db9d77b | 2503 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2504 | reg = FDI_TX_CTL(pipe); |
2505 | temp = I915_READ(reg); | |
627eb5a3 DV |
2506 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2507 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2508 | temp &= ~FDI_LINK_TRAIN_NONE; |
2509 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2510 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2511 | |
5eddb70b CW |
2512 | reg = FDI_RX_CTL(pipe); |
2513 | temp = I915_READ(reg); | |
8db9d77b ZW |
2514 | temp &= ~FDI_LINK_TRAIN_NONE; |
2515 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2516 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2517 | ||
2518 | POSTING_READ(reg); | |
8db9d77b ZW |
2519 | udelay(150); |
2520 | ||
5b2adf89 | 2521 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2522 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2523 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2524 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2525 | |
5eddb70b | 2526 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2527 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2528 | temp = I915_READ(reg); |
8db9d77b ZW |
2529 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2530 | ||
2531 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2532 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2533 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2534 | break; |
2535 | } | |
8db9d77b | 2536 | } |
e1a44743 | 2537 | if (tries == 5) |
5eddb70b | 2538 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2539 | |
2540 | /* Train 2 */ | |
5eddb70b CW |
2541 | reg = FDI_TX_CTL(pipe); |
2542 | temp = I915_READ(reg); | |
8db9d77b ZW |
2543 | temp &= ~FDI_LINK_TRAIN_NONE; |
2544 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2545 | I915_WRITE(reg, temp); |
8db9d77b | 2546 | |
5eddb70b CW |
2547 | reg = FDI_RX_CTL(pipe); |
2548 | temp = I915_READ(reg); | |
8db9d77b ZW |
2549 | temp &= ~FDI_LINK_TRAIN_NONE; |
2550 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2551 | I915_WRITE(reg, temp); |
8db9d77b | 2552 | |
5eddb70b CW |
2553 | POSTING_READ(reg); |
2554 | udelay(150); | |
8db9d77b | 2555 | |
5eddb70b | 2556 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2557 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2558 | temp = I915_READ(reg); |
8db9d77b ZW |
2559 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2560 | ||
2561 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2562 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2563 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2564 | break; | |
2565 | } | |
8db9d77b | 2566 | } |
e1a44743 | 2567 | if (tries == 5) |
5eddb70b | 2568 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2569 | |
2570 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2571 | |
8db9d77b ZW |
2572 | } |
2573 | ||
0206e353 | 2574 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2575 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2576 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2577 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2578 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2579 | }; | |
2580 | ||
2581 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2582 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2583 | { | |
2584 | struct drm_device *dev = crtc->dev; | |
2585 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2586 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2587 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2588 | u32 reg, temp, i, retry; |
8db9d77b | 2589 | |
e1a44743 AJ |
2590 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2591 | for train result */ | |
5eddb70b CW |
2592 | reg = FDI_RX_IMR(pipe); |
2593 | temp = I915_READ(reg); | |
e1a44743 AJ |
2594 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2595 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2596 | I915_WRITE(reg, temp); |
2597 | ||
2598 | POSTING_READ(reg); | |
e1a44743 AJ |
2599 | udelay(150); |
2600 | ||
8db9d77b | 2601 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2602 | reg = FDI_TX_CTL(pipe); |
2603 | temp = I915_READ(reg); | |
627eb5a3 DV |
2604 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2605 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2606 | temp &= ~FDI_LINK_TRAIN_NONE; |
2607 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2608 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2609 | /* SNB-B */ | |
2610 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2611 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2612 | |
d74cf324 DV |
2613 | I915_WRITE(FDI_RX_MISC(pipe), |
2614 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2615 | ||
5eddb70b CW |
2616 | reg = FDI_RX_CTL(pipe); |
2617 | temp = I915_READ(reg); | |
8db9d77b ZW |
2618 | if (HAS_PCH_CPT(dev)) { |
2619 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2620 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2621 | } else { | |
2622 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2623 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2624 | } | |
5eddb70b CW |
2625 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2626 | ||
2627 | POSTING_READ(reg); | |
8db9d77b ZW |
2628 | udelay(150); |
2629 | ||
0206e353 | 2630 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2631 | reg = FDI_TX_CTL(pipe); |
2632 | temp = I915_READ(reg); | |
8db9d77b ZW |
2633 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2634 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2635 | I915_WRITE(reg, temp); |
2636 | ||
2637 | POSTING_READ(reg); | |
8db9d77b ZW |
2638 | udelay(500); |
2639 | ||
fa37d39e SP |
2640 | for (retry = 0; retry < 5; retry++) { |
2641 | reg = FDI_RX_IIR(pipe); | |
2642 | temp = I915_READ(reg); | |
2643 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2644 | if (temp & FDI_RX_BIT_LOCK) { | |
2645 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2646 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2647 | break; | |
2648 | } | |
2649 | udelay(50); | |
8db9d77b | 2650 | } |
fa37d39e SP |
2651 | if (retry < 5) |
2652 | break; | |
8db9d77b ZW |
2653 | } |
2654 | if (i == 4) | |
5eddb70b | 2655 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2656 | |
2657 | /* Train 2 */ | |
5eddb70b CW |
2658 | reg = FDI_TX_CTL(pipe); |
2659 | temp = I915_READ(reg); | |
8db9d77b ZW |
2660 | temp &= ~FDI_LINK_TRAIN_NONE; |
2661 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2662 | if (IS_GEN6(dev)) { | |
2663 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2664 | /* SNB-B */ | |
2665 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2666 | } | |
5eddb70b | 2667 | I915_WRITE(reg, temp); |
8db9d77b | 2668 | |
5eddb70b CW |
2669 | reg = FDI_RX_CTL(pipe); |
2670 | temp = I915_READ(reg); | |
8db9d77b ZW |
2671 | if (HAS_PCH_CPT(dev)) { |
2672 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2673 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2674 | } else { | |
2675 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2676 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2677 | } | |
5eddb70b CW |
2678 | I915_WRITE(reg, temp); |
2679 | ||
2680 | POSTING_READ(reg); | |
8db9d77b ZW |
2681 | udelay(150); |
2682 | ||
0206e353 | 2683 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2684 | reg = FDI_TX_CTL(pipe); |
2685 | temp = I915_READ(reg); | |
8db9d77b ZW |
2686 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2687 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2688 | I915_WRITE(reg, temp); |
2689 | ||
2690 | POSTING_READ(reg); | |
8db9d77b ZW |
2691 | udelay(500); |
2692 | ||
fa37d39e SP |
2693 | for (retry = 0; retry < 5; retry++) { |
2694 | reg = FDI_RX_IIR(pipe); | |
2695 | temp = I915_READ(reg); | |
2696 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2697 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2698 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2699 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2700 | break; | |
2701 | } | |
2702 | udelay(50); | |
8db9d77b | 2703 | } |
fa37d39e SP |
2704 | if (retry < 5) |
2705 | break; | |
8db9d77b ZW |
2706 | } |
2707 | if (i == 4) | |
5eddb70b | 2708 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2709 | |
2710 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2711 | } | |
2712 | ||
357555c0 JB |
2713 | /* Manual link training for Ivy Bridge A0 parts */ |
2714 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2715 | { | |
2716 | struct drm_device *dev = crtc->dev; | |
2717 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2718 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2719 | int pipe = intel_crtc->pipe; | |
139ccd3f | 2720 | u32 reg, temp, i, j; |
357555c0 JB |
2721 | |
2722 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2723 | for train result */ | |
2724 | reg = FDI_RX_IMR(pipe); | |
2725 | temp = I915_READ(reg); | |
2726 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2727 | temp &= ~FDI_RX_BIT_LOCK; | |
2728 | I915_WRITE(reg, temp); | |
2729 | ||
2730 | POSTING_READ(reg); | |
2731 | udelay(150); | |
2732 | ||
01a415fd DV |
2733 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2734 | I915_READ(FDI_RX_IIR(pipe))); | |
2735 | ||
139ccd3f JB |
2736 | /* Try each vswing and preemphasis setting twice before moving on */ |
2737 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
2738 | /* disable first in case we need to retry */ | |
2739 | reg = FDI_TX_CTL(pipe); | |
2740 | temp = I915_READ(reg); | |
2741 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2742 | temp &= ~FDI_TX_ENABLE; | |
2743 | I915_WRITE(reg, temp); | |
357555c0 | 2744 | |
139ccd3f JB |
2745 | reg = FDI_RX_CTL(pipe); |
2746 | temp = I915_READ(reg); | |
2747 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2748 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2749 | temp &= ~FDI_RX_ENABLE; | |
2750 | I915_WRITE(reg, temp); | |
357555c0 | 2751 | |
139ccd3f | 2752 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
2753 | reg = FDI_TX_CTL(pipe); |
2754 | temp = I915_READ(reg); | |
139ccd3f JB |
2755 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2756 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
2757 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 2758 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
2759 | temp |= snb_b_fdi_train_param[j/2]; |
2760 | temp |= FDI_COMPOSITE_SYNC; | |
2761 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 2762 | |
139ccd3f JB |
2763 | I915_WRITE(FDI_RX_MISC(pipe), |
2764 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 2765 | |
139ccd3f | 2766 | reg = FDI_RX_CTL(pipe); |
357555c0 | 2767 | temp = I915_READ(reg); |
139ccd3f JB |
2768 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2769 | temp |= FDI_COMPOSITE_SYNC; | |
2770 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 2771 | |
139ccd3f JB |
2772 | POSTING_READ(reg); |
2773 | udelay(1); /* should be 0.5us */ | |
357555c0 | 2774 | |
139ccd3f JB |
2775 | for (i = 0; i < 4; i++) { |
2776 | reg = FDI_RX_IIR(pipe); | |
2777 | temp = I915_READ(reg); | |
2778 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2779 | |
139ccd3f JB |
2780 | if (temp & FDI_RX_BIT_LOCK || |
2781 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2782 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2783 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
2784 | i); | |
2785 | break; | |
2786 | } | |
2787 | udelay(1); /* should be 0.5us */ | |
2788 | } | |
2789 | if (i == 4) { | |
2790 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
2791 | continue; | |
2792 | } | |
357555c0 | 2793 | |
139ccd3f | 2794 | /* Train 2 */ |
357555c0 JB |
2795 | reg = FDI_TX_CTL(pipe); |
2796 | temp = I915_READ(reg); | |
139ccd3f JB |
2797 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2798 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2799 | I915_WRITE(reg, temp); | |
2800 | ||
2801 | reg = FDI_RX_CTL(pipe); | |
2802 | temp = I915_READ(reg); | |
2803 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2804 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
2805 | I915_WRITE(reg, temp); |
2806 | ||
2807 | POSTING_READ(reg); | |
139ccd3f | 2808 | udelay(2); /* should be 1.5us */ |
357555c0 | 2809 | |
139ccd3f JB |
2810 | for (i = 0; i < 4; i++) { |
2811 | reg = FDI_RX_IIR(pipe); | |
2812 | temp = I915_READ(reg); | |
2813 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2814 | |
139ccd3f JB |
2815 | if (temp & FDI_RX_SYMBOL_LOCK || |
2816 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
2817 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2818 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
2819 | i); | |
2820 | goto train_done; | |
2821 | } | |
2822 | udelay(2); /* should be 1.5us */ | |
357555c0 | 2823 | } |
139ccd3f JB |
2824 | if (i == 4) |
2825 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 2826 | } |
357555c0 | 2827 | |
139ccd3f | 2828 | train_done: |
357555c0 JB |
2829 | DRM_DEBUG_KMS("FDI train done.\n"); |
2830 | } | |
2831 | ||
88cefb6c | 2832 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 2833 | { |
88cefb6c | 2834 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 2835 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 2836 | int pipe = intel_crtc->pipe; |
5eddb70b | 2837 | u32 reg, temp; |
79e53945 | 2838 | |
c64e311e | 2839 | |
c98e9dcf | 2840 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2841 | reg = FDI_RX_CTL(pipe); |
2842 | temp = I915_READ(reg); | |
627eb5a3 DV |
2843 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
2844 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 2845 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
2846 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2847 | ||
2848 | POSTING_READ(reg); | |
c98e9dcf JB |
2849 | udelay(200); |
2850 | ||
2851 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2852 | temp = I915_READ(reg); |
2853 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2854 | ||
2855 | POSTING_READ(reg); | |
c98e9dcf JB |
2856 | udelay(200); |
2857 | ||
20749730 PZ |
2858 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2859 | reg = FDI_TX_CTL(pipe); | |
2860 | temp = I915_READ(reg); | |
2861 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
2862 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 2863 | |
20749730 PZ |
2864 | POSTING_READ(reg); |
2865 | udelay(100); | |
6be4a607 | 2866 | } |
0e23b99d JB |
2867 | } |
2868 | ||
88cefb6c DV |
2869 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2870 | { | |
2871 | struct drm_device *dev = intel_crtc->base.dev; | |
2872 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2873 | int pipe = intel_crtc->pipe; | |
2874 | u32 reg, temp; | |
2875 | ||
2876 | /* Switch from PCDclk to Rawclk */ | |
2877 | reg = FDI_RX_CTL(pipe); | |
2878 | temp = I915_READ(reg); | |
2879 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
2880 | ||
2881 | /* Disable CPU FDI TX PLL */ | |
2882 | reg = FDI_TX_CTL(pipe); | |
2883 | temp = I915_READ(reg); | |
2884 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2885 | ||
2886 | POSTING_READ(reg); | |
2887 | udelay(100); | |
2888 | ||
2889 | reg = FDI_RX_CTL(pipe); | |
2890 | temp = I915_READ(reg); | |
2891 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2892 | ||
2893 | /* Wait for the clocks to turn off. */ | |
2894 | POSTING_READ(reg); | |
2895 | udelay(100); | |
2896 | } | |
2897 | ||
0fc932b8 JB |
2898 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2899 | { | |
2900 | struct drm_device *dev = crtc->dev; | |
2901 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2902 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2903 | int pipe = intel_crtc->pipe; | |
2904 | u32 reg, temp; | |
2905 | ||
2906 | /* disable CPU FDI tx and PCH FDI rx */ | |
2907 | reg = FDI_TX_CTL(pipe); | |
2908 | temp = I915_READ(reg); | |
2909 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2910 | POSTING_READ(reg); | |
2911 | ||
2912 | reg = FDI_RX_CTL(pipe); | |
2913 | temp = I915_READ(reg); | |
2914 | temp &= ~(0x7 << 16); | |
dfd07d72 | 2915 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2916 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2917 | ||
2918 | POSTING_READ(reg); | |
2919 | udelay(100); | |
2920 | ||
2921 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2922 | if (HAS_PCH_IBX(dev)) { |
2923 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
6f06ce18 | 2924 | } |
0fc932b8 JB |
2925 | |
2926 | /* still set train pattern 1 */ | |
2927 | reg = FDI_TX_CTL(pipe); | |
2928 | temp = I915_READ(reg); | |
2929 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2930 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2931 | I915_WRITE(reg, temp); | |
2932 | ||
2933 | reg = FDI_RX_CTL(pipe); | |
2934 | temp = I915_READ(reg); | |
2935 | if (HAS_PCH_CPT(dev)) { | |
2936 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2937 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2938 | } else { | |
2939 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2940 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2941 | } | |
2942 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2943 | temp &= ~(0x07 << 16); | |
dfd07d72 | 2944 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2945 | I915_WRITE(reg, temp); |
2946 | ||
2947 | POSTING_READ(reg); | |
2948 | udelay(100); | |
2949 | } | |
2950 | ||
5bb61643 CW |
2951 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2952 | { | |
2953 | struct drm_device *dev = crtc->dev; | |
2954 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10d83730 | 2955 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5bb61643 CW |
2956 | unsigned long flags; |
2957 | bool pending; | |
2958 | ||
10d83730 VS |
2959 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
2960 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
5bb61643 CW |
2961 | return false; |
2962 | ||
2963 | spin_lock_irqsave(&dev->event_lock, flags); | |
2964 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2965 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2966 | ||
2967 | return pending; | |
2968 | } | |
2969 | ||
e6c3a2a6 CW |
2970 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2971 | { | |
0f91128d | 2972 | struct drm_device *dev = crtc->dev; |
5bb61643 | 2973 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 CW |
2974 | |
2975 | if (crtc->fb == NULL) | |
2976 | return; | |
2977 | ||
2c10d571 DV |
2978 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
2979 | ||
5bb61643 CW |
2980 | wait_event(dev_priv->pending_flip_queue, |
2981 | !intel_crtc_has_pending_flip(crtc)); | |
2982 | ||
0f91128d CW |
2983 | mutex_lock(&dev->struct_mutex); |
2984 | intel_finish_fb(crtc->fb); | |
2985 | mutex_unlock(&dev->struct_mutex); | |
e6c3a2a6 CW |
2986 | } |
2987 | ||
e615efe4 ED |
2988 | /* Program iCLKIP clock to the desired frequency */ |
2989 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
2990 | { | |
2991 | struct drm_device *dev = crtc->dev; | |
2992 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 2993 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
2994 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
2995 | u32 temp; | |
2996 | ||
09153000 DV |
2997 | mutex_lock(&dev_priv->dpio_lock); |
2998 | ||
e615efe4 ED |
2999 | /* It is necessary to ungate the pixclk gate prior to programming |
3000 | * the divisors, and gate it back when it is done. | |
3001 | */ | |
3002 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3003 | ||
3004 | /* Disable SSCCTL */ | |
3005 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3006 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3007 | SBI_SSCCTL_DISABLE, | |
3008 | SBI_ICLK); | |
e615efe4 ED |
3009 | |
3010 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3011 | if (clock == 20000) { |
e615efe4 ED |
3012 | auxdiv = 1; |
3013 | divsel = 0x41; | |
3014 | phaseinc = 0x20; | |
3015 | } else { | |
3016 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3017 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3018 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3019 | * convert the virtual clock precision to KHz here for higher |
3020 | * precision. | |
3021 | */ | |
3022 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3023 | u32 iclk_pi_range = 64; | |
3024 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3025 | ||
12d7ceed | 3026 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3027 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3028 | pi_value = desired_divisor % iclk_pi_range; | |
3029 | ||
3030 | auxdiv = 0; | |
3031 | divsel = msb_divisor_value - 2; | |
3032 | phaseinc = pi_value; | |
3033 | } | |
3034 | ||
3035 | /* This should not happen with any sane values */ | |
3036 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3037 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3038 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3039 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3040 | ||
3041 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3042 | clock, |
e615efe4 ED |
3043 | auxdiv, |
3044 | divsel, | |
3045 | phasedir, | |
3046 | phaseinc); | |
3047 | ||
3048 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3049 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3050 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3051 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3052 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3053 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3054 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3055 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3056 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3057 | |
3058 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3059 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3060 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3061 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3062 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3063 | |
3064 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3065 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3066 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3067 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3068 | |
3069 | /* Wait for initialization time */ | |
3070 | udelay(24); | |
3071 | ||
3072 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3073 | |
3074 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3075 | } |
3076 | ||
275f01b2 DV |
3077 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3078 | enum pipe pch_transcoder) | |
3079 | { | |
3080 | struct drm_device *dev = crtc->base.dev; | |
3081 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3082 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3083 | ||
3084 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3085 | I915_READ(HTOTAL(cpu_transcoder))); | |
3086 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3087 | I915_READ(HBLANK(cpu_transcoder))); | |
3088 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3089 | I915_READ(HSYNC(cpu_transcoder))); | |
3090 | ||
3091 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3092 | I915_READ(VTOTAL(cpu_transcoder))); | |
3093 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3094 | I915_READ(VBLANK(cpu_transcoder))); | |
3095 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3096 | I915_READ(VSYNC(cpu_transcoder))); | |
3097 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3098 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3099 | } | |
3100 | ||
1fbc0d78 DV |
3101 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3102 | { | |
3103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3104 | uint32_t temp; | |
3105 | ||
3106 | temp = I915_READ(SOUTH_CHICKEN1); | |
3107 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3108 | return; | |
3109 | ||
3110 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3111 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3112 | ||
3113 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3114 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3115 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3116 | POSTING_READ(SOUTH_CHICKEN1); | |
3117 | } | |
3118 | ||
3119 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3120 | { | |
3121 | struct drm_device *dev = intel_crtc->base.dev; | |
3122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3123 | ||
3124 | switch (intel_crtc->pipe) { | |
3125 | case PIPE_A: | |
3126 | break; | |
3127 | case PIPE_B: | |
3128 | if (intel_crtc->config.fdi_lanes > 2) | |
3129 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3130 | else | |
3131 | cpt_enable_fdi_bc_bifurcation(dev); | |
3132 | ||
3133 | break; | |
3134 | case PIPE_C: | |
3135 | cpt_enable_fdi_bc_bifurcation(dev); | |
3136 | ||
3137 | break; | |
3138 | default: | |
3139 | BUG(); | |
3140 | } | |
3141 | } | |
3142 | ||
f67a559d JB |
3143 | /* |
3144 | * Enable PCH resources required for PCH ports: | |
3145 | * - PCH PLLs | |
3146 | * - FDI training & RX/TX | |
3147 | * - update transcoder timings | |
3148 | * - DP transcoding bits | |
3149 | * - transcoder | |
3150 | */ | |
3151 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3152 | { |
3153 | struct drm_device *dev = crtc->dev; | |
3154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3155 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3156 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3157 | u32 reg, temp; |
2c07245f | 3158 | |
ab9412ba | 3159 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3160 | |
1fbc0d78 DV |
3161 | if (IS_IVYBRIDGE(dev)) |
3162 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3163 | ||
cd986abb DV |
3164 | /* Write the TU size bits before fdi link training, so that error |
3165 | * detection works. */ | |
3166 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3167 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3168 | ||
c98e9dcf | 3169 | /* For PCH output, training FDI link */ |
674cf967 | 3170 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3171 | |
3ad8a208 DV |
3172 | /* We need to program the right clock selection before writing the pixel |
3173 | * mutliplier into the DPLL. */ | |
303b81e0 | 3174 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3175 | u32 sel; |
4b645f14 | 3176 | |
c98e9dcf | 3177 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3178 | temp |= TRANS_DPLL_ENABLE(pipe); |
3179 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3180 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3181 | temp |= sel; |
3182 | else | |
3183 | temp &= ~sel; | |
c98e9dcf | 3184 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3185 | } |
5eddb70b | 3186 | |
3ad8a208 DV |
3187 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3188 | * transcoder, and we actually should do this to not upset any PCH | |
3189 | * transcoder that already use the clock when we share it. | |
3190 | * | |
3191 | * Note that enable_shared_dpll tries to do the right thing, but | |
3192 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3193 | * the right LVDS enable sequence. */ | |
3194 | ironlake_enable_shared_dpll(intel_crtc); | |
3195 | ||
d9b6cb56 JB |
3196 | /* set transcoder timing, panel must allow it */ |
3197 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3198 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3199 | |
303b81e0 | 3200 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3201 | |
c98e9dcf JB |
3202 | /* For PCH DP, enable TRANS_DP_CTL */ |
3203 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3204 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3205 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3206 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3207 | reg = TRANS_DP_CTL(pipe); |
3208 | temp = I915_READ(reg); | |
3209 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3210 | TRANS_DP_SYNC_MASK | |
3211 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3212 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3213 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3214 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3215 | |
3216 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3217 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3218 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3219 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3220 | |
3221 | switch (intel_trans_dp_port_sel(crtc)) { | |
3222 | case PCH_DP_B: | |
5eddb70b | 3223 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3224 | break; |
3225 | case PCH_DP_C: | |
5eddb70b | 3226 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3227 | break; |
3228 | case PCH_DP_D: | |
5eddb70b | 3229 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3230 | break; |
3231 | default: | |
e95d41e1 | 3232 | BUG(); |
32f9d658 | 3233 | } |
2c07245f | 3234 | |
5eddb70b | 3235 | I915_WRITE(reg, temp); |
6be4a607 | 3236 | } |
b52eb4dc | 3237 | |
b8a4f404 | 3238 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3239 | } |
3240 | ||
1507e5bd PZ |
3241 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3242 | { | |
3243 | struct drm_device *dev = crtc->dev; | |
3244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3245 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3246 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3247 | |
ab9412ba | 3248 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3249 | |
8c52b5e8 | 3250 | lpt_program_iclkip(crtc); |
1507e5bd | 3251 | |
0540e488 | 3252 | /* Set transcoder timing. */ |
275f01b2 | 3253 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3254 | |
937bb610 | 3255 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3256 | } |
3257 | ||
e2b78267 | 3258 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3259 | { |
e2b78267 | 3260 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3261 | |
3262 | if (pll == NULL) | |
3263 | return; | |
3264 | ||
3265 | if (pll->refcount == 0) { | |
46edb027 | 3266 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3267 | return; |
3268 | } | |
3269 | ||
f4a091c7 DV |
3270 | if (--pll->refcount == 0) { |
3271 | WARN_ON(pll->on); | |
3272 | WARN_ON(pll->active); | |
3273 | } | |
3274 | ||
a43f6e0f | 3275 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3276 | } |
3277 | ||
b89a1d39 | 3278 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3279 | { |
e2b78267 DV |
3280 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3281 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3282 | enum intel_dpll_id i; | |
ee7b9f93 | 3283 | |
ee7b9f93 | 3284 | if (pll) { |
46edb027 DV |
3285 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3286 | crtc->base.base.id, pll->name); | |
e2b78267 | 3287 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3288 | } |
3289 | ||
98b6bd99 DV |
3290 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3291 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3292 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3293 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3294 | |
46edb027 DV |
3295 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3296 | crtc->base.base.id, pll->name); | |
98b6bd99 DV |
3297 | |
3298 | goto found; | |
3299 | } | |
3300 | ||
e72f9fbf DV |
3301 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3302 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3303 | |
3304 | /* Only want to check enabled timings first */ | |
3305 | if (pll->refcount == 0) | |
3306 | continue; | |
3307 | ||
b89a1d39 DV |
3308 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3309 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3310 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3311 | crtc->base.base.id, |
46edb027 | 3312 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3313 | |
3314 | goto found; | |
3315 | } | |
3316 | } | |
3317 | ||
3318 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3319 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3320 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3321 | if (pll->refcount == 0) { |
46edb027 DV |
3322 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3323 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3324 | goto found; |
3325 | } | |
3326 | } | |
3327 | ||
3328 | return NULL; | |
3329 | ||
3330 | found: | |
a43f6e0f | 3331 | crtc->config.shared_dpll = i; |
46edb027 DV |
3332 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3333 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3334 | |
cdbd2316 | 3335 | if (pll->active == 0) { |
66e985c0 DV |
3336 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
3337 | sizeof(pll->hw_state)); | |
3338 | ||
46edb027 | 3339 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
cdbd2316 | 3340 | WARN_ON(pll->on); |
e9d6944e | 3341 | assert_shared_dpll_disabled(dev_priv, pll); |
ee7b9f93 | 3342 | |
15bdd4cf | 3343 | pll->mode_set(dev_priv, pll); |
cdbd2316 DV |
3344 | } |
3345 | pll->refcount++; | |
e04c7350 | 3346 | |
ee7b9f93 JB |
3347 | return pll; |
3348 | } | |
3349 | ||
a1520318 | 3350 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3351 | { |
3352 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3353 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3354 | u32 temp; |
3355 | ||
3356 | temp = I915_READ(dslreg); | |
3357 | udelay(500); | |
3358 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3359 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3360 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3361 | } |
3362 | } | |
3363 | ||
b074cec8 JB |
3364 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3365 | { | |
3366 | struct drm_device *dev = crtc->base.dev; | |
3367 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3368 | int pipe = crtc->pipe; | |
3369 | ||
fd4daa9c | 3370 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3371 | /* Force use of hard-coded filter coefficients |
3372 | * as some pre-programmed values are broken, | |
3373 | * e.g. x201. | |
3374 | */ | |
3375 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3376 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3377 | PF_PIPE_SEL_IVB(pipe)); | |
3378 | else | |
3379 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3380 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3381 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3382 | } |
3383 | } | |
3384 | ||
bb53d4ae VS |
3385 | static void intel_enable_planes(struct drm_crtc *crtc) |
3386 | { | |
3387 | struct drm_device *dev = crtc->dev; | |
3388 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3389 | struct intel_plane *intel_plane; | |
3390 | ||
3391 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3392 | if (intel_plane->pipe == pipe) | |
3393 | intel_plane_restore(&intel_plane->base); | |
3394 | } | |
3395 | ||
3396 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3397 | { | |
3398 | struct drm_device *dev = crtc->dev; | |
3399 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3400 | struct intel_plane *intel_plane; | |
3401 | ||
3402 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3403 | if (intel_plane->pipe == pipe) | |
3404 | intel_plane_disable(&intel_plane->base); | |
3405 | } | |
3406 | ||
20bc8673 | 3407 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3408 | { |
3409 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
3410 | ||
3411 | if (!crtc->config.ips_enabled) | |
3412 | return; | |
3413 | ||
3414 | /* We can only enable IPS after we enable a plane and wait for a vblank. | |
3415 | * We guarantee that the plane is enabled by calling intel_enable_ips | |
3416 | * only after intel_enable_plane. And intel_enable_plane already waits | |
3417 | * for a vblank, so all we need to do here is to enable the IPS bit. */ | |
3418 | assert_plane_enabled(dev_priv, crtc->plane); | |
2a114cc1 BW |
3419 | if (IS_BROADWELL(crtc->base.dev)) { |
3420 | mutex_lock(&dev_priv->rps.hw_lock); | |
3421 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
3422 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3423 | /* Quoting Art Runyan: "its not safe to expect any particular | |
3424 | * value in IPS_CTL bit 31 after enabling IPS through the | |
3425 | * mailbox." Therefore we need to defer waiting on the state | |
3426 | * change. | |
3427 | * TODO: need to fix this for state checker | |
3428 | */ | |
3429 | } else { | |
3430 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3431 | /* The bit only becomes 1 in the next vblank, so this wait here | |
3432 | * is essentially intel_wait_for_vblank. If we don't have this | |
3433 | * and don't wait for vblanks until the end of crtc_enable, then | |
3434 | * the HW state readout code will complain that the expected | |
3435 | * IPS_CTL value is not the one we read. */ | |
3436 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
3437 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
3438 | } | |
d77e4531 PZ |
3439 | } |
3440 | ||
20bc8673 | 3441 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3442 | { |
3443 | struct drm_device *dev = crtc->base.dev; | |
3444 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3445 | ||
3446 | if (!crtc->config.ips_enabled) | |
3447 | return; | |
3448 | ||
3449 | assert_plane_enabled(dev_priv, crtc->plane); | |
2a114cc1 BW |
3450 | if (IS_BROADWELL(crtc->base.dev)) { |
3451 | mutex_lock(&dev_priv->rps.hw_lock); | |
3452 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
3453 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3454 | } else | |
3455 | I915_WRITE(IPS_CTL, 0); | |
d77e4531 PZ |
3456 | POSTING_READ(IPS_CTL); |
3457 | ||
3458 | /* We need to wait for a vblank before we can disable the plane. */ | |
3459 | intel_wait_for_vblank(dev, crtc->pipe); | |
3460 | } | |
3461 | ||
3462 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
3463 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
3464 | { | |
3465 | struct drm_device *dev = crtc->dev; | |
3466 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3467 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3468 | enum pipe pipe = intel_crtc->pipe; | |
3469 | int palreg = PALETTE(pipe); | |
3470 | int i; | |
3471 | bool reenable_ips = false; | |
3472 | ||
3473 | /* The clocks have to be on to load the palette. */ | |
3474 | if (!crtc->enabled || !intel_crtc->active) | |
3475 | return; | |
3476 | ||
3477 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
3478 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
3479 | assert_dsi_pll_enabled(dev_priv); | |
3480 | else | |
3481 | assert_pll_enabled(dev_priv, pipe); | |
3482 | } | |
3483 | ||
3484 | /* use legacy palette for Ironlake */ | |
3485 | if (HAS_PCH_SPLIT(dev)) | |
3486 | palreg = LGC_PALETTE(pipe); | |
3487 | ||
3488 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
3489 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
3490 | */ | |
3491 | if (intel_crtc->config.ips_enabled && | |
3492 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == | |
3493 | GAMMA_MODE_MODE_SPLIT)) { | |
3494 | hsw_disable_ips(intel_crtc); | |
3495 | reenable_ips = true; | |
3496 | } | |
3497 | ||
3498 | for (i = 0; i < 256; i++) { | |
3499 | I915_WRITE(palreg + 4 * i, | |
3500 | (intel_crtc->lut_r[i] << 16) | | |
3501 | (intel_crtc->lut_g[i] << 8) | | |
3502 | intel_crtc->lut_b[i]); | |
3503 | } | |
3504 | ||
3505 | if (reenable_ips) | |
3506 | hsw_enable_ips(intel_crtc); | |
3507 | } | |
3508 | ||
f67a559d JB |
3509 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3510 | { | |
3511 | struct drm_device *dev = crtc->dev; | |
3512 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3513 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3514 | struct intel_encoder *encoder; |
f67a559d JB |
3515 | int pipe = intel_crtc->pipe; |
3516 | int plane = intel_crtc->plane; | |
f67a559d | 3517 | |
08a48469 DV |
3518 | WARN_ON(!crtc->enabled); |
3519 | ||
f67a559d JB |
3520 | if (intel_crtc->active) |
3521 | return; | |
3522 | ||
3523 | intel_crtc->active = true; | |
8664281b PZ |
3524 | |
3525 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3526 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
3527 | ||
f6736a1a | 3528 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
3529 | if (encoder->pre_enable) |
3530 | encoder->pre_enable(encoder); | |
f67a559d | 3531 | |
5bfe2ac0 | 3532 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
3533 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3534 | * cpu pipes, hence this is separate from all the other fdi/pch | |
3535 | * enabling. */ | |
88cefb6c | 3536 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
3537 | } else { |
3538 | assert_fdi_tx_disabled(dev_priv, pipe); | |
3539 | assert_fdi_rx_disabled(dev_priv, pipe); | |
3540 | } | |
f67a559d | 3541 | |
b074cec8 | 3542 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 3543 | |
9c54c0dd JB |
3544 | /* |
3545 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3546 | * clocks enabled | |
3547 | */ | |
3548 | intel_crtc_load_lut(crtc); | |
3549 | ||
f37fcc2a | 3550 | intel_update_watermarks(crtc); |
5bfe2ac0 | 3551 | intel_enable_pipe(dev_priv, pipe, |
23538ef1 | 3552 | intel_crtc->config.has_pch_encoder, false); |
d1de00ef | 3553 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 3554 | intel_enable_planes(crtc); |
5c38d48c | 3555 | intel_crtc_update_cursor(crtc, true); |
f67a559d | 3556 | |
5bfe2ac0 | 3557 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 3558 | ironlake_pch_enable(crtc); |
c98e9dcf | 3559 | |
d1ebd816 | 3560 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3561 | intel_update_fbc(dev); |
d1ebd816 BW |
3562 | mutex_unlock(&dev->struct_mutex); |
3563 | ||
fa5c73b1 DV |
3564 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3565 | encoder->enable(encoder); | |
61b77ddd DV |
3566 | |
3567 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 3568 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 DV |
3569 | |
3570 | /* | |
3571 | * There seems to be a race in PCH platform hw (at least on some | |
3572 | * outputs) where an enabled pipe still completes any pageflip right | |
3573 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3574 | * as the first vblank happend, everything works as expected. Hence just | |
3575 | * wait for one vblank before returning to avoid strange things | |
3576 | * happening. | |
3577 | */ | |
3578 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
6be4a607 JB |
3579 | } |
3580 | ||
42db64ef PZ |
3581 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
3582 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
3583 | { | |
f5adf94e | 3584 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
3585 | } |
3586 | ||
dda9a66a VS |
3587 | static void haswell_crtc_enable_planes(struct drm_crtc *crtc) |
3588 | { | |
3589 | struct drm_device *dev = crtc->dev; | |
3590 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3591 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3592 | int pipe = intel_crtc->pipe; | |
3593 | int plane = intel_crtc->plane; | |
3594 | ||
d1de00ef | 3595 | intel_enable_primary_plane(dev_priv, plane, pipe); |
dda9a66a VS |
3596 | intel_enable_planes(crtc); |
3597 | intel_crtc_update_cursor(crtc, true); | |
3598 | ||
3599 | hsw_enable_ips(intel_crtc); | |
3600 | ||
3601 | mutex_lock(&dev->struct_mutex); | |
3602 | intel_update_fbc(dev); | |
3603 | mutex_unlock(&dev->struct_mutex); | |
3604 | } | |
3605 | ||
3606 | static void haswell_crtc_disable_planes(struct drm_crtc *crtc) | |
3607 | { | |
3608 | struct drm_device *dev = crtc->dev; | |
3609 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3610 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3611 | int pipe = intel_crtc->pipe; | |
3612 | int plane = intel_crtc->plane; | |
3613 | ||
3614 | intel_crtc_wait_for_pending_flips(crtc); | |
3615 | drm_vblank_off(dev, pipe); | |
3616 | ||
3617 | /* FBC must be disabled before disabling the plane on HSW. */ | |
3618 | if (dev_priv->fbc.plane == plane) | |
3619 | intel_disable_fbc(dev); | |
3620 | ||
3621 | hsw_disable_ips(intel_crtc); | |
3622 | ||
3623 | intel_crtc_update_cursor(crtc, false); | |
3624 | intel_disable_planes(crtc); | |
d1de00ef | 3625 | intel_disable_primary_plane(dev_priv, plane, pipe); |
dda9a66a VS |
3626 | } |
3627 | ||
e4916946 PZ |
3628 | /* |
3629 | * This implements the workaround described in the "notes" section of the mode | |
3630 | * set sequence documentation. When going from no pipes or single pipe to | |
3631 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
3632 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
3633 | */ | |
3634 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
3635 | { | |
3636 | struct drm_device *dev = crtc->base.dev; | |
3637 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
3638 | ||
3639 | /* We want to get the other_active_crtc only if there's only 1 other | |
3640 | * active crtc. */ | |
3641 | list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) { | |
3642 | if (!crtc_it->active || crtc_it == crtc) | |
3643 | continue; | |
3644 | ||
3645 | if (other_active_crtc) | |
3646 | return; | |
3647 | ||
3648 | other_active_crtc = crtc_it; | |
3649 | } | |
3650 | if (!other_active_crtc) | |
3651 | return; | |
3652 | ||
3653 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
3654 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
3655 | } | |
3656 | ||
4f771f10 PZ |
3657 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3658 | { | |
3659 | struct drm_device *dev = crtc->dev; | |
3660 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3661 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3662 | struct intel_encoder *encoder; | |
3663 | int pipe = intel_crtc->pipe; | |
4f771f10 PZ |
3664 | |
3665 | WARN_ON(!crtc->enabled); | |
3666 | ||
3667 | if (intel_crtc->active) | |
3668 | return; | |
3669 | ||
3670 | intel_crtc->active = true; | |
8664281b PZ |
3671 | |
3672 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3673 | if (intel_crtc->config.has_pch_encoder) | |
3674 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
3675 | ||
5bfe2ac0 | 3676 | if (intel_crtc->config.has_pch_encoder) |
04945641 | 3677 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
3678 | |
3679 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3680 | if (encoder->pre_enable) | |
3681 | encoder->pre_enable(encoder); | |
3682 | ||
1f544388 | 3683 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 3684 | |
b074cec8 | 3685 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
3686 | |
3687 | /* | |
3688 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3689 | * clocks enabled | |
3690 | */ | |
3691 | intel_crtc_load_lut(crtc); | |
3692 | ||
1f544388 | 3693 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 3694 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 3695 | |
f37fcc2a | 3696 | intel_update_watermarks(crtc); |
5bfe2ac0 | 3697 | intel_enable_pipe(dev_priv, pipe, |
23538ef1 | 3698 | intel_crtc->config.has_pch_encoder, false); |
42db64ef | 3699 | |
5bfe2ac0 | 3700 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 3701 | lpt_pch_enable(crtc); |
4f771f10 | 3702 | |
8807e55b | 3703 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 3704 | encoder->enable(encoder); |
8807e55b JN |
3705 | intel_opregion_notify_encoder(encoder, true); |
3706 | } | |
4f771f10 | 3707 | |
e4916946 PZ |
3708 | /* If we change the relative order between pipe/planes enabling, we need |
3709 | * to change the workaround. */ | |
3710 | haswell_mode_set_planes_workaround(intel_crtc); | |
dda9a66a VS |
3711 | haswell_crtc_enable_planes(crtc); |
3712 | ||
4f771f10 PZ |
3713 | /* |
3714 | * There seems to be a race in PCH platform hw (at least on some | |
3715 | * outputs) where an enabled pipe still completes any pageflip right | |
3716 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3717 | * as the first vblank happend, everything works as expected. Hence just | |
3718 | * wait for one vblank before returning to avoid strange things | |
3719 | * happening. | |
3720 | */ | |
3721 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
3722 | } | |
3723 | ||
3f8dce3a DV |
3724 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
3725 | { | |
3726 | struct drm_device *dev = crtc->base.dev; | |
3727 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3728 | int pipe = crtc->pipe; | |
3729 | ||
3730 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
3731 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 3732 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
3733 | I915_WRITE(PF_CTL(pipe), 0); |
3734 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
3735 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
3736 | } | |
3737 | } | |
3738 | ||
6be4a607 JB |
3739 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3740 | { | |
3741 | struct drm_device *dev = crtc->dev; | |
3742 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3743 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3744 | struct intel_encoder *encoder; |
6be4a607 JB |
3745 | int pipe = intel_crtc->pipe; |
3746 | int plane = intel_crtc->plane; | |
5eddb70b | 3747 | u32 reg, temp; |
b52eb4dc | 3748 | |
ef9c3aee | 3749 | |
f7abfe8b CW |
3750 | if (!intel_crtc->active) |
3751 | return; | |
3752 | ||
ea9d758d DV |
3753 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3754 | encoder->disable(encoder); | |
3755 | ||
e6c3a2a6 | 3756 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3757 | drm_vblank_off(dev, pipe); |
913d8d11 | 3758 | |
5c3fe8b0 | 3759 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 3760 | intel_disable_fbc(dev); |
2c07245f | 3761 | |
0d5b8c61 | 3762 | intel_crtc_update_cursor(crtc, false); |
bb53d4ae | 3763 | intel_disable_planes(crtc); |
d1de00ef | 3764 | intel_disable_primary_plane(dev_priv, plane, pipe); |
0d5b8c61 | 3765 | |
d925c59a DV |
3766 | if (intel_crtc->config.has_pch_encoder) |
3767 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
3768 | ||
b24e7179 | 3769 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3770 | |
3f8dce3a | 3771 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 3772 | |
bf49ec8c DV |
3773 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3774 | if (encoder->post_disable) | |
3775 | encoder->post_disable(encoder); | |
2c07245f | 3776 | |
d925c59a DV |
3777 | if (intel_crtc->config.has_pch_encoder) { |
3778 | ironlake_fdi_disable(crtc); | |
913d8d11 | 3779 | |
d925c59a DV |
3780 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
3781 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 3782 | |
d925c59a DV |
3783 | if (HAS_PCH_CPT(dev)) { |
3784 | /* disable TRANS_DP_CTL */ | |
3785 | reg = TRANS_DP_CTL(pipe); | |
3786 | temp = I915_READ(reg); | |
3787 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
3788 | TRANS_DP_PORT_SEL_MASK); | |
3789 | temp |= TRANS_DP_PORT_SEL_NONE; | |
3790 | I915_WRITE(reg, temp); | |
3791 | ||
3792 | /* disable DPLL_SEL */ | |
3793 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 3794 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 3795 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 3796 | } |
e3421a18 | 3797 | |
d925c59a | 3798 | /* disable PCH DPLL */ |
e72f9fbf | 3799 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 3800 | |
d925c59a DV |
3801 | ironlake_fdi_pll_disable(intel_crtc); |
3802 | } | |
6b383a7f | 3803 | |
f7abfe8b | 3804 | intel_crtc->active = false; |
46ba614c | 3805 | intel_update_watermarks(crtc); |
d1ebd816 BW |
3806 | |
3807 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 3808 | intel_update_fbc(dev); |
d1ebd816 | 3809 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3810 | } |
1b3c7a47 | 3811 | |
4f771f10 | 3812 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 3813 | { |
4f771f10 PZ |
3814 | struct drm_device *dev = crtc->dev; |
3815 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 3816 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
3817 | struct intel_encoder *encoder; |
3818 | int pipe = intel_crtc->pipe; | |
3b117c8f | 3819 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 3820 | |
4f771f10 PZ |
3821 | if (!intel_crtc->active) |
3822 | return; | |
3823 | ||
dda9a66a VS |
3824 | haswell_crtc_disable_planes(crtc); |
3825 | ||
8807e55b JN |
3826 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
3827 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 3828 | encoder->disable(encoder); |
8807e55b | 3829 | } |
4f771f10 | 3830 | |
8664281b PZ |
3831 | if (intel_crtc->config.has_pch_encoder) |
3832 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
3833 | intel_disable_pipe(dev_priv, pipe); |
3834 | ||
ad80a810 | 3835 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 3836 | |
3f8dce3a | 3837 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 3838 | |
1f544388 | 3839 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
3840 | |
3841 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3842 | if (encoder->post_disable) | |
3843 | encoder->post_disable(encoder); | |
3844 | ||
88adfff1 | 3845 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 3846 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 3847 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 3848 | intel_ddi_fdi_disable(crtc); |
83616634 | 3849 | } |
4f771f10 PZ |
3850 | |
3851 | intel_crtc->active = false; | |
46ba614c | 3852 | intel_update_watermarks(crtc); |
4f771f10 PZ |
3853 | |
3854 | mutex_lock(&dev->struct_mutex); | |
3855 | intel_update_fbc(dev); | |
3856 | mutex_unlock(&dev->struct_mutex); | |
3857 | } | |
3858 | ||
ee7b9f93 JB |
3859 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3860 | { | |
3861 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 3862 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
3863 | } |
3864 | ||
6441ab5f PZ |
3865 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3866 | { | |
3867 | intel_ddi_put_crtc_pll(crtc); | |
3868 | } | |
3869 | ||
02e792fb DV |
3870 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3871 | { | |
02e792fb | 3872 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3873 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3874 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3875 | |
23f09ce3 | 3876 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3877 | dev_priv->mm.interruptible = false; |
3878 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3879 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3880 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3881 | } |
02e792fb | 3882 | |
5dcdbcb0 CW |
3883 | /* Let userspace switch the overlay on again. In most cases userspace |
3884 | * has to recompute where to put it anyway. | |
3885 | */ | |
02e792fb DV |
3886 | } |
3887 | ||
61bc95c1 EE |
3888 | /** |
3889 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware | |
3890 | * cursor plane briefly if not already running after enabling the display | |
3891 | * plane. | |
3892 | * This workaround avoids occasional blank screens when self refresh is | |
3893 | * enabled. | |
3894 | */ | |
3895 | static void | |
3896 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) | |
3897 | { | |
3898 | u32 cntl = I915_READ(CURCNTR(pipe)); | |
3899 | ||
3900 | if ((cntl & CURSOR_MODE) == 0) { | |
3901 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); | |
3902 | ||
3903 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); | |
3904 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); | |
3905 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
3906 | I915_WRITE(CURCNTR(pipe), cntl); | |
3907 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3908 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); | |
3909 | } | |
3910 | } | |
3911 | ||
2dd24552 JB |
3912 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
3913 | { | |
3914 | struct drm_device *dev = crtc->base.dev; | |
3915 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3916 | struct intel_crtc_config *pipe_config = &crtc->config; | |
3917 | ||
328d8e82 | 3918 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
3919 | return; |
3920 | ||
2dd24552 | 3921 | /* |
c0b03411 DV |
3922 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
3923 | * according to register description and PRM. | |
2dd24552 | 3924 | */ |
c0b03411 DV |
3925 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
3926 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 3927 | |
b074cec8 JB |
3928 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
3929 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
3930 | |
3931 | /* Border color in case we don't scale up to the full screen. Black by | |
3932 | * default, change to something else for debugging. */ | |
3933 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
3934 | } |
3935 | ||
586f49dc | 3936 | int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 3937 | { |
586f49dc | 3938 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 3939 | |
586f49dc JB |
3940 | /* Obtain SKU information */ |
3941 | mutex_lock(&dev_priv->dpio_lock); | |
3942 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
3943 | CCK_FUSE_HPLL_FREQ_MASK; | |
3944 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 3945 | |
586f49dc | 3946 | return vco_freq[hpll_freq]; |
30a970c6 JB |
3947 | } |
3948 | ||
3949 | /* Adjust CDclk dividers to allow high res or save power if possible */ | |
3950 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
3951 | { | |
3952 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3953 | u32 val, cmd; | |
3954 | ||
3955 | if (cdclk >= 320) /* jump to highest voltage for 400MHz too */ | |
3956 | cmd = 2; | |
3957 | else if (cdclk == 266) | |
3958 | cmd = 1; | |
3959 | else | |
3960 | cmd = 0; | |
3961 | ||
3962 | mutex_lock(&dev_priv->rps.hw_lock); | |
3963 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
3964 | val &= ~DSPFREQGUAR_MASK; | |
3965 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
3966 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
3967 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
3968 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
3969 | 50)) { | |
3970 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
3971 | } | |
3972 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3973 | ||
3974 | if (cdclk == 400) { | |
3975 | u32 divider, vco; | |
3976 | ||
3977 | vco = valleyview_get_vco(dev_priv); | |
3978 | divider = ((vco << 1) / cdclk) - 1; | |
3979 | ||
3980 | mutex_lock(&dev_priv->dpio_lock); | |
3981 | /* adjust cdclk divider */ | |
3982 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
3983 | val &= ~0xf; | |
3984 | val |= divider; | |
3985 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
3986 | mutex_unlock(&dev_priv->dpio_lock); | |
3987 | } | |
3988 | ||
3989 | mutex_lock(&dev_priv->dpio_lock); | |
3990 | /* adjust self-refresh exit latency value */ | |
3991 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
3992 | val &= ~0x7f; | |
3993 | ||
3994 | /* | |
3995 | * For high bandwidth configs, we set a higher latency in the bunit | |
3996 | * so that the core display fetch happens in time to avoid underruns. | |
3997 | */ | |
3998 | if (cdclk == 400) | |
3999 | val |= 4500 / 250; /* 4.5 usec */ | |
4000 | else | |
4001 | val |= 3000 / 250; /* 3.0 usec */ | |
4002 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4003 | mutex_unlock(&dev_priv->dpio_lock); | |
4004 | ||
4005 | /* Since we changed the CDclk, we need to update the GMBUSFREQ too */ | |
4006 | intel_i2c_reset(dev); | |
4007 | } | |
4008 | ||
4009 | static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv) | |
4010 | { | |
4011 | int cur_cdclk, vco; | |
4012 | int divider; | |
4013 | ||
4014 | vco = valleyview_get_vco(dev_priv); | |
4015 | ||
4016 | mutex_lock(&dev_priv->dpio_lock); | |
4017 | divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
4018 | mutex_unlock(&dev_priv->dpio_lock); | |
4019 | ||
4020 | divider &= 0xf; | |
4021 | ||
4022 | cur_cdclk = (vco << 1) / (divider + 1); | |
4023 | ||
4024 | return cur_cdclk; | |
4025 | } | |
4026 | ||
4027 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, | |
4028 | int max_pixclk) | |
4029 | { | |
4030 | int cur_cdclk; | |
4031 | ||
4032 | cur_cdclk = valleyview_cur_cdclk(dev_priv); | |
4033 | ||
4034 | /* | |
4035 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4036 | * 200MHz | |
4037 | * 267MHz | |
4038 | * 320MHz | |
4039 | * 400MHz | |
4040 | * So we check to see whether we're above 90% of the lower bin and | |
4041 | * adjust if needed. | |
4042 | */ | |
4043 | if (max_pixclk > 288000) { | |
4044 | return 400; | |
4045 | } else if (max_pixclk > 240000) { | |
4046 | return 320; | |
4047 | } else | |
4048 | return 266; | |
4049 | /* Looks like the 200MHz CDclk freq doesn't work on some configs */ | |
4050 | } | |
4051 | ||
4052 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv, | |
4053 | unsigned modeset_pipes, | |
4054 | struct intel_crtc_config *pipe_config) | |
4055 | { | |
4056 | struct drm_device *dev = dev_priv->dev; | |
4057 | struct intel_crtc *intel_crtc; | |
4058 | int max_pixclk = 0; | |
4059 | ||
4060 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
4061 | base.head) { | |
4062 | if (modeset_pipes & (1 << intel_crtc->pipe)) | |
4063 | max_pixclk = max(max_pixclk, | |
4064 | pipe_config->adjusted_mode.crtc_clock); | |
4065 | else if (intel_crtc->base.enabled) | |
4066 | max_pixclk = max(max_pixclk, | |
4067 | intel_crtc->config.adjusted_mode.crtc_clock); | |
4068 | } | |
4069 | ||
4070 | return max_pixclk; | |
4071 | } | |
4072 | ||
4073 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
4074 | unsigned *prepare_pipes, | |
4075 | unsigned modeset_pipes, | |
4076 | struct intel_crtc_config *pipe_config) | |
4077 | { | |
4078 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4079 | struct intel_crtc *intel_crtc; | |
4080 | int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes, | |
4081 | pipe_config); | |
4082 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); | |
4083 | ||
4084 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk) | |
4085 | return; | |
4086 | ||
4087 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
4088 | base.head) | |
4089 | if (intel_crtc->base.enabled) | |
4090 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4091 | } | |
4092 | ||
4093 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4094 | { | |
4095 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4096 | int max_pixclk = intel_mode_max_pixclk(dev_priv, 0, NULL); | |
4097 | int cur_cdclk = valleyview_cur_cdclk(dev_priv); | |
4098 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
4099 | ||
4100 | if (req_cdclk != cur_cdclk) | |
4101 | valleyview_set_cdclk(dev, req_cdclk); | |
4102 | } | |
4103 | ||
89b667f8 JB |
4104 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4105 | { | |
4106 | struct drm_device *dev = crtc->dev; | |
4107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4108 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4109 | struct intel_encoder *encoder; | |
4110 | int pipe = intel_crtc->pipe; | |
4111 | int plane = intel_crtc->plane; | |
23538ef1 | 4112 | bool is_dsi; |
89b667f8 JB |
4113 | |
4114 | WARN_ON(!crtc->enabled); | |
4115 | ||
4116 | if (intel_crtc->active) | |
4117 | return; | |
4118 | ||
4119 | intel_crtc->active = true; | |
89b667f8 | 4120 | |
89b667f8 JB |
4121 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4122 | if (encoder->pre_pll_enable) | |
4123 | encoder->pre_pll_enable(encoder); | |
4124 | ||
23538ef1 JN |
4125 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4126 | ||
e9fd1c02 JN |
4127 | if (!is_dsi) |
4128 | vlv_enable_pll(intel_crtc); | |
89b667f8 JB |
4129 | |
4130 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4131 | if (encoder->pre_enable) | |
4132 | encoder->pre_enable(encoder); | |
4133 | ||
2dd24552 JB |
4134 | i9xx_pfit_enable(intel_crtc); |
4135 | ||
63cbb074 VS |
4136 | intel_crtc_load_lut(crtc); |
4137 | ||
f37fcc2a | 4138 | intel_update_watermarks(crtc); |
23538ef1 | 4139 | intel_enable_pipe(dev_priv, pipe, false, is_dsi); |
d1de00ef | 4140 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 4141 | intel_enable_planes(crtc); |
5c38d48c | 4142 | intel_crtc_update_cursor(crtc, true); |
89b667f8 | 4143 | |
89b667f8 | 4144 | intel_update_fbc(dev); |
5004945f JN |
4145 | |
4146 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4147 | encoder->enable(encoder); | |
89b667f8 JB |
4148 | } |
4149 | ||
0b8765c6 | 4150 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
4151 | { |
4152 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
4153 | struct drm_i915_private *dev_priv = dev->dev_private; |
4154 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4155 | struct intel_encoder *encoder; |
79e53945 | 4156 | int pipe = intel_crtc->pipe; |
80824003 | 4157 | int plane = intel_crtc->plane; |
79e53945 | 4158 | |
08a48469 DV |
4159 | WARN_ON(!crtc->enabled); |
4160 | ||
f7abfe8b CW |
4161 | if (intel_crtc->active) |
4162 | return; | |
4163 | ||
4164 | intel_crtc->active = true; | |
6b383a7f | 4165 | |
9d6d9f19 MK |
4166 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4167 | if (encoder->pre_enable) | |
4168 | encoder->pre_enable(encoder); | |
4169 | ||
f6736a1a DV |
4170 | i9xx_enable_pll(intel_crtc); |
4171 | ||
2dd24552 JB |
4172 | i9xx_pfit_enable(intel_crtc); |
4173 | ||
63cbb074 VS |
4174 | intel_crtc_load_lut(crtc); |
4175 | ||
f37fcc2a | 4176 | intel_update_watermarks(crtc); |
23538ef1 | 4177 | intel_enable_pipe(dev_priv, pipe, false, false); |
d1de00ef | 4178 | intel_enable_primary_plane(dev_priv, plane, pipe); |
bb53d4ae | 4179 | intel_enable_planes(crtc); |
22e407d7 | 4180 | /* The fixup needs to happen before cursor is enabled */ |
61bc95c1 EE |
4181 | if (IS_G4X(dev)) |
4182 | g4x_fixup_plane(dev_priv, pipe); | |
22e407d7 | 4183 | intel_crtc_update_cursor(crtc, true); |
79e53945 | 4184 | |
0b8765c6 JB |
4185 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
4186 | intel_crtc_dpms_overlay(intel_crtc, true); | |
ef9c3aee | 4187 | |
f440eb13 | 4188 | intel_update_fbc(dev); |
ef9c3aee | 4189 | |
fa5c73b1 DV |
4190 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4191 | encoder->enable(encoder); | |
0b8765c6 | 4192 | } |
79e53945 | 4193 | |
87476d63 DV |
4194 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4195 | { | |
4196 | struct drm_device *dev = crtc->base.dev; | |
4197 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 4198 | |
328d8e82 DV |
4199 | if (!crtc->config.gmch_pfit.control) |
4200 | return; | |
87476d63 | 4201 | |
328d8e82 | 4202 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 4203 | |
328d8e82 DV |
4204 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4205 | I915_READ(PFIT_CONTROL)); | |
4206 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
4207 | } |
4208 | ||
0b8765c6 JB |
4209 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4210 | { | |
4211 | struct drm_device *dev = crtc->dev; | |
4212 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4213 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4214 | struct intel_encoder *encoder; |
0b8765c6 JB |
4215 | int pipe = intel_crtc->pipe; |
4216 | int plane = intel_crtc->plane; | |
ef9c3aee | 4217 | |
f7abfe8b CW |
4218 | if (!intel_crtc->active) |
4219 | return; | |
4220 | ||
ea9d758d DV |
4221 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4222 | encoder->disable(encoder); | |
4223 | ||
0b8765c6 | 4224 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
4225 | intel_crtc_wait_for_pending_flips(crtc); |
4226 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 4227 | |
5c3fe8b0 | 4228 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 4229 | intel_disable_fbc(dev); |
79e53945 | 4230 | |
0d5b8c61 VS |
4231 | intel_crtc_dpms_overlay(intel_crtc, false); |
4232 | intel_crtc_update_cursor(crtc, false); | |
bb53d4ae | 4233 | intel_disable_planes(crtc); |
d1de00ef | 4234 | intel_disable_primary_plane(dev_priv, plane, pipe); |
0d5b8c61 | 4235 | |
b24e7179 | 4236 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 4237 | |
87476d63 | 4238 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 4239 | |
89b667f8 JB |
4240 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4241 | if (encoder->post_disable) | |
4242 | encoder->post_disable(encoder); | |
4243 | ||
f6071166 JB |
4244 | if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
4245 | vlv_disable_pll(dev_priv, pipe); | |
4246 | else if (!IS_VALLEYVIEW(dev)) | |
e9fd1c02 | 4247 | i9xx_disable_pll(dev_priv, pipe); |
0b8765c6 | 4248 | |
f7abfe8b | 4249 | intel_crtc->active = false; |
46ba614c | 4250 | intel_update_watermarks(crtc); |
f37fcc2a | 4251 | |
6b383a7f | 4252 | intel_update_fbc(dev); |
0b8765c6 JB |
4253 | } |
4254 | ||
ee7b9f93 JB |
4255 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
4256 | { | |
4257 | } | |
4258 | ||
976f8a20 DV |
4259 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
4260 | bool enabled) | |
2c07245f ZW |
4261 | { |
4262 | struct drm_device *dev = crtc->dev; | |
4263 | struct drm_i915_master_private *master_priv; | |
4264 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4265 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
4266 | |
4267 | if (!dev->primary->master) | |
4268 | return; | |
4269 | ||
4270 | master_priv = dev->primary->master->driver_priv; | |
4271 | if (!master_priv->sarea_priv) | |
4272 | return; | |
4273 | ||
79e53945 JB |
4274 | switch (pipe) { |
4275 | case 0: | |
4276 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
4277 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
4278 | break; | |
4279 | case 1: | |
4280 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
4281 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
4282 | break; | |
4283 | default: | |
9db4a9c7 | 4284 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
4285 | break; |
4286 | } | |
79e53945 JB |
4287 | } |
4288 | ||
976f8a20 DV |
4289 | /** |
4290 | * Sets the power management mode of the pipe and plane. | |
4291 | */ | |
4292 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
4293 | { | |
4294 | struct drm_device *dev = crtc->dev; | |
4295 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4296 | struct intel_encoder *intel_encoder; | |
4297 | bool enable = false; | |
4298 | ||
4299 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
4300 | enable |= intel_encoder->connectors_active; | |
4301 | ||
4302 | if (enable) | |
4303 | dev_priv->display.crtc_enable(crtc); | |
4304 | else | |
4305 | dev_priv->display.crtc_disable(crtc); | |
4306 | ||
4307 | intel_crtc_update_sarea(crtc, enable); | |
4308 | } | |
4309 | ||
cdd59983 CW |
4310 | static void intel_crtc_disable(struct drm_crtc *crtc) |
4311 | { | |
cdd59983 | 4312 | struct drm_device *dev = crtc->dev; |
976f8a20 | 4313 | struct drm_connector *connector; |
ee7b9f93 | 4314 | struct drm_i915_private *dev_priv = dev->dev_private; |
7b9f35a6 | 4315 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cdd59983 | 4316 | |
976f8a20 DV |
4317 | /* crtc should still be enabled when we disable it. */ |
4318 | WARN_ON(!crtc->enabled); | |
4319 | ||
4320 | dev_priv->display.crtc_disable(crtc); | |
c77bf565 | 4321 | intel_crtc->eld_vld = false; |
976f8a20 | 4322 | intel_crtc_update_sarea(crtc, false); |
ee7b9f93 JB |
4323 | dev_priv->display.off(crtc); |
4324 | ||
931872fc | 4325 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
93ce0ba6 | 4326 | assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
931872fc | 4327 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
cdd59983 CW |
4328 | |
4329 | if (crtc->fb) { | |
4330 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 4331 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 | 4332 | mutex_unlock(&dev->struct_mutex); |
976f8a20 DV |
4333 | crtc->fb = NULL; |
4334 | } | |
4335 | ||
4336 | /* Update computed state. */ | |
4337 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4338 | if (!connector->encoder || !connector->encoder->crtc) | |
4339 | continue; | |
4340 | ||
4341 | if (connector->encoder->crtc != crtc) | |
4342 | continue; | |
4343 | ||
4344 | connector->dpms = DRM_MODE_DPMS_OFF; | |
4345 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
4346 | } |
4347 | } | |
4348 | ||
ea5b213a | 4349 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 4350 | { |
4ef69c7a | 4351 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 4352 | |
ea5b213a CW |
4353 | drm_encoder_cleanup(encoder); |
4354 | kfree(intel_encoder); | |
7e7d76c3 JB |
4355 | } |
4356 | ||
9237329d | 4357 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
4358 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
4359 | * state of the entire output pipe. */ | |
9237329d | 4360 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 4361 | { |
5ab432ef DV |
4362 | if (mode == DRM_MODE_DPMS_ON) { |
4363 | encoder->connectors_active = true; | |
4364 | ||
b2cabb0e | 4365 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
4366 | } else { |
4367 | encoder->connectors_active = false; | |
4368 | ||
b2cabb0e | 4369 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 4370 | } |
79e53945 JB |
4371 | } |
4372 | ||
0a91ca29 DV |
4373 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
4374 | * internal consistency). */ | |
b980514c | 4375 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 4376 | { |
0a91ca29 DV |
4377 | if (connector->get_hw_state(connector)) { |
4378 | struct intel_encoder *encoder = connector->encoder; | |
4379 | struct drm_crtc *crtc; | |
4380 | bool encoder_enabled; | |
4381 | enum pipe pipe; | |
4382 | ||
4383 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4384 | connector->base.base.id, | |
4385 | drm_get_connector_name(&connector->base)); | |
4386 | ||
4387 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
4388 | "wrong connector dpms state\n"); | |
4389 | WARN(connector->base.encoder != &encoder->base, | |
4390 | "active connector not linked to encoder\n"); | |
4391 | WARN(!encoder->connectors_active, | |
4392 | "encoder->connectors_active not set\n"); | |
4393 | ||
4394 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
4395 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
4396 | if (WARN_ON(!encoder->base.crtc)) | |
4397 | return; | |
4398 | ||
4399 | crtc = encoder->base.crtc; | |
4400 | ||
4401 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
4402 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
4403 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
4404 | "encoder active on the wrong pipe\n"); | |
4405 | } | |
79e53945 JB |
4406 | } |
4407 | ||
5ab432ef DV |
4408 | /* Even simpler default implementation, if there's really no special case to |
4409 | * consider. */ | |
4410 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 4411 | { |
5ab432ef DV |
4412 | /* All the simple cases only support two dpms states. */ |
4413 | if (mode != DRM_MODE_DPMS_ON) | |
4414 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 4415 | |
5ab432ef DV |
4416 | if (mode == connector->dpms) |
4417 | return; | |
4418 | ||
4419 | connector->dpms = mode; | |
4420 | ||
4421 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
4422 | if (connector->encoder) |
4423 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 4424 | |
b980514c | 4425 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
4426 | } |
4427 | ||
f0947c37 DV |
4428 | /* Simple connector->get_hw_state implementation for encoders that support only |
4429 | * one connector and no cloning and hence the encoder state determines the state | |
4430 | * of the connector. */ | |
4431 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 4432 | { |
24929352 | 4433 | enum pipe pipe = 0; |
f0947c37 | 4434 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 4435 | |
f0947c37 | 4436 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
4437 | } |
4438 | ||
1857e1da DV |
4439 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
4440 | struct intel_crtc_config *pipe_config) | |
4441 | { | |
4442 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4443 | struct intel_crtc *pipe_B_crtc = | |
4444 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
4445 | ||
4446 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
4447 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4448 | if (pipe_config->fdi_lanes > 4) { | |
4449 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
4450 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4451 | return false; | |
4452 | } | |
4453 | ||
bafb6553 | 4454 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
4455 | if (pipe_config->fdi_lanes > 2) { |
4456 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
4457 | pipe_config->fdi_lanes); | |
4458 | return false; | |
4459 | } else { | |
4460 | return true; | |
4461 | } | |
4462 | } | |
4463 | ||
4464 | if (INTEL_INFO(dev)->num_pipes == 2) | |
4465 | return true; | |
4466 | ||
4467 | /* Ivybridge 3 pipe is really complicated */ | |
4468 | switch (pipe) { | |
4469 | case PIPE_A: | |
4470 | return true; | |
4471 | case PIPE_B: | |
4472 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
4473 | pipe_config->fdi_lanes > 2) { | |
4474 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4475 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4476 | return false; | |
4477 | } | |
4478 | return true; | |
4479 | case PIPE_C: | |
1e833f40 | 4480 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
4481 | pipe_B_crtc->config.fdi_lanes <= 2) { |
4482 | if (pipe_config->fdi_lanes > 2) { | |
4483 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4484 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4485 | return false; | |
4486 | } | |
4487 | } else { | |
4488 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
4489 | return false; | |
4490 | } | |
4491 | return true; | |
4492 | default: | |
4493 | BUG(); | |
4494 | } | |
4495 | } | |
4496 | ||
e29c22c0 DV |
4497 | #define RETRY 1 |
4498 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
4499 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 4500 | { |
1857e1da | 4501 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 4502 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 4503 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 4504 | bool setup_ok, needs_recompute = false; |
877d48d5 | 4505 | |
e29c22c0 | 4506 | retry: |
877d48d5 DV |
4507 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4508 | * each output octet as 10 bits. The actual frequency | |
4509 | * is stored as a divider into a 100MHz clock, and the | |
4510 | * mode pixel clock is stored in units of 1KHz. | |
4511 | * Hence the bw of each lane in terms of the mode signal | |
4512 | * is: | |
4513 | */ | |
4514 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
4515 | ||
241bfc38 | 4516 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 4517 | |
2bd89a07 | 4518 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
4519 | pipe_config->pipe_bpp); |
4520 | ||
4521 | pipe_config->fdi_lanes = lane; | |
4522 | ||
2bd89a07 | 4523 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 4524 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 4525 | |
e29c22c0 DV |
4526 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
4527 | intel_crtc->pipe, pipe_config); | |
4528 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
4529 | pipe_config->pipe_bpp -= 2*3; | |
4530 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
4531 | pipe_config->pipe_bpp); | |
4532 | needs_recompute = true; | |
4533 | pipe_config->bw_constrained = true; | |
4534 | ||
4535 | goto retry; | |
4536 | } | |
4537 | ||
4538 | if (needs_recompute) | |
4539 | return RETRY; | |
4540 | ||
4541 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
4542 | } |
4543 | ||
42db64ef PZ |
4544 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
4545 | struct intel_crtc_config *pipe_config) | |
4546 | { | |
3c4ca58c PZ |
4547 | pipe_config->ips_enabled = i915_enable_ips && |
4548 | hsw_crtc_supports_ips(crtc) && | |
b6dfdc9b | 4549 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
4550 | } |
4551 | ||
a43f6e0f | 4552 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 4553 | struct intel_crtc_config *pipe_config) |
79e53945 | 4554 | { |
a43f6e0f | 4555 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 4556 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 4557 | |
ad3a4479 | 4558 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
4559 | if (INTEL_INFO(dev)->gen < 4) { |
4560 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4561 | int clock_limit = | |
4562 | dev_priv->display.get_display_clock_speed(dev); | |
4563 | ||
4564 | /* | |
4565 | * Enable pixel doubling when the dot clock | |
4566 | * is > 90% of the (display) core speed. | |
4567 | * | |
b397c96b VS |
4568 | * GDG double wide on either pipe, |
4569 | * otherwise pipe A only. | |
cf532bb2 | 4570 | */ |
b397c96b | 4571 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 4572 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 4573 | clock_limit *= 2; |
cf532bb2 | 4574 | pipe_config->double_wide = true; |
ad3a4479 VS |
4575 | } |
4576 | ||
241bfc38 | 4577 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 4578 | return -EINVAL; |
2c07245f | 4579 | } |
89749350 | 4580 | |
1d1d0e27 VS |
4581 | /* |
4582 | * Pipe horizontal size must be even in: | |
4583 | * - DVO ganged mode | |
4584 | * - LVDS dual channel mode | |
4585 | * - Double wide pipe | |
4586 | */ | |
4587 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
4588 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
4589 | pipe_config->pipe_src_w &= ~1; | |
4590 | ||
8693a824 DL |
4591 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4592 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
4593 | */ |
4594 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
4595 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 4596 | return -EINVAL; |
44f46b42 | 4597 | |
bd080ee5 | 4598 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 4599 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 4600 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
4601 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
4602 | * for lvds. */ | |
4603 | pipe_config->pipe_bpp = 8*3; | |
4604 | } | |
4605 | ||
f5adf94e | 4606 | if (HAS_IPS(dev)) |
a43f6e0f DV |
4607 | hsw_compute_ips_config(crtc, pipe_config); |
4608 | ||
4609 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old | |
4610 | * clock survives for now. */ | |
4611 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
4612 | pipe_config->shared_dpll = crtc->config.shared_dpll; | |
42db64ef | 4613 | |
877d48d5 | 4614 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 4615 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 4616 | |
e29c22c0 | 4617 | return 0; |
79e53945 JB |
4618 | } |
4619 | ||
25eb05fc JB |
4620 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4621 | { | |
4622 | return 400000; /* FIXME */ | |
4623 | } | |
4624 | ||
e70236a8 JB |
4625 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4626 | { | |
4627 | return 400000; | |
4628 | } | |
79e53945 | 4629 | |
e70236a8 | 4630 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 4631 | { |
e70236a8 JB |
4632 | return 333000; |
4633 | } | |
79e53945 | 4634 | |
e70236a8 JB |
4635 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
4636 | { | |
4637 | return 200000; | |
4638 | } | |
79e53945 | 4639 | |
257a7ffc DV |
4640 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
4641 | { | |
4642 | u16 gcfgc = 0; | |
4643 | ||
4644 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
4645 | ||
4646 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4647 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
4648 | return 267000; | |
4649 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
4650 | return 333000; | |
4651 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
4652 | return 444000; | |
4653 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
4654 | return 200000; | |
4655 | default: | |
4656 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
4657 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
4658 | return 133000; | |
4659 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
4660 | return 167000; | |
4661 | } | |
4662 | } | |
4663 | ||
e70236a8 JB |
4664 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
4665 | { | |
4666 | u16 gcfgc = 0; | |
79e53945 | 4667 | |
e70236a8 JB |
4668 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4669 | ||
4670 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
4671 | return 133000; | |
4672 | else { | |
4673 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4674 | case GC_DISPLAY_CLOCK_333_MHZ: | |
4675 | return 333000; | |
4676 | default: | |
4677 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
4678 | return 190000; | |
79e53945 | 4679 | } |
e70236a8 JB |
4680 | } |
4681 | } | |
4682 | ||
4683 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
4684 | { | |
4685 | return 266000; | |
4686 | } | |
4687 | ||
4688 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
4689 | { | |
4690 | u16 hpllcc = 0; | |
4691 | /* Assume that the hardware is in the high speed state. This | |
4692 | * should be the default. | |
4693 | */ | |
4694 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
4695 | case GC_CLOCK_133_200: | |
4696 | case GC_CLOCK_100_200: | |
4697 | return 200000; | |
4698 | case GC_CLOCK_166_250: | |
4699 | return 250000; | |
4700 | case GC_CLOCK_100_133: | |
79e53945 | 4701 | return 133000; |
e70236a8 | 4702 | } |
79e53945 | 4703 | |
e70236a8 JB |
4704 | /* Shouldn't happen */ |
4705 | return 0; | |
4706 | } | |
79e53945 | 4707 | |
e70236a8 JB |
4708 | static int i830_get_display_clock_speed(struct drm_device *dev) |
4709 | { | |
4710 | return 133000; | |
79e53945 JB |
4711 | } |
4712 | ||
2c07245f | 4713 | static void |
a65851af | 4714 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 4715 | { |
a65851af VS |
4716 | while (*num > DATA_LINK_M_N_MASK || |
4717 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
4718 | *num >>= 1; |
4719 | *den >>= 1; | |
4720 | } | |
4721 | } | |
4722 | ||
a65851af VS |
4723 | static void compute_m_n(unsigned int m, unsigned int n, |
4724 | uint32_t *ret_m, uint32_t *ret_n) | |
4725 | { | |
4726 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
4727 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
4728 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
4729 | } | |
4730 | ||
e69d0bc1 DV |
4731 | void |
4732 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
4733 | int pixel_clock, int link_clock, | |
4734 | struct intel_link_m_n *m_n) | |
2c07245f | 4735 | { |
e69d0bc1 | 4736 | m_n->tu = 64; |
a65851af VS |
4737 | |
4738 | compute_m_n(bits_per_pixel * pixel_clock, | |
4739 | link_clock * nlanes * 8, | |
4740 | &m_n->gmch_m, &m_n->gmch_n); | |
4741 | ||
4742 | compute_m_n(pixel_clock, link_clock, | |
4743 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
4744 | } |
4745 | ||
a7615030 CW |
4746 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4747 | { | |
72bbe58c KP |
4748 | if (i915_panel_use_ssc >= 0) |
4749 | return i915_panel_use_ssc != 0; | |
41aa3448 | 4750 | return dev_priv->vbt.lvds_use_ssc |
435793df | 4751 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
4752 | } |
4753 | ||
c65d77d8 JB |
4754 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4755 | { | |
4756 | struct drm_device *dev = crtc->dev; | |
4757 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4758 | int refclk; | |
4759 | ||
a0c4da24 | 4760 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 4761 | refclk = 100000; |
a0c4da24 | 4762 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 4763 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
41aa3448 | 4764 | refclk = dev_priv->vbt.lvds_ssc_freq * 1000; |
c65d77d8 JB |
4765 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
4766 | refclk / 1000); | |
4767 | } else if (!IS_GEN2(dev)) { | |
4768 | refclk = 96000; | |
4769 | } else { | |
4770 | refclk = 48000; | |
4771 | } | |
4772 | ||
4773 | return refclk; | |
4774 | } | |
4775 | ||
7429e9d4 | 4776 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 4777 | { |
7df00d7a | 4778 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 4779 | } |
f47709a9 | 4780 | |
7429e9d4 DV |
4781 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
4782 | { | |
4783 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
4784 | } |
4785 | ||
f47709a9 | 4786 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
4787 | intel_clock_t *reduced_clock) |
4788 | { | |
f47709a9 | 4789 | struct drm_device *dev = crtc->base.dev; |
a7516a05 | 4790 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4791 | int pipe = crtc->pipe; |
a7516a05 JB |
4792 | u32 fp, fp2 = 0; |
4793 | ||
4794 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 4795 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4796 | if (reduced_clock) |
7429e9d4 | 4797 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 4798 | } else { |
7429e9d4 | 4799 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4800 | if (reduced_clock) |
7429e9d4 | 4801 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
4802 | } |
4803 | ||
4804 | I915_WRITE(FP0(pipe), fp); | |
8bcc2795 | 4805 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 4806 | |
f47709a9 DV |
4807 | crtc->lowfreq_avail = false; |
4808 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
a7516a05 JB |
4809 | reduced_clock && i915_powersave) { |
4810 | I915_WRITE(FP1(pipe), fp2); | |
8bcc2795 | 4811 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 4812 | crtc->lowfreq_avail = true; |
a7516a05 JB |
4813 | } else { |
4814 | I915_WRITE(FP1(pipe), fp); | |
8bcc2795 | 4815 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
4816 | } |
4817 | } | |
4818 | ||
5e69f97f CML |
4819 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
4820 | pipe) | |
89b667f8 JB |
4821 | { |
4822 | u32 reg_val; | |
4823 | ||
4824 | /* | |
4825 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
4826 | * and set it to a reasonable value instead. | |
4827 | */ | |
ab3c759a | 4828 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
4829 | reg_val &= 0xffffff00; |
4830 | reg_val |= 0x00000030; | |
ab3c759a | 4831 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 4832 | |
ab3c759a | 4833 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
4834 | reg_val &= 0x8cffffff; |
4835 | reg_val = 0x8c000000; | |
ab3c759a | 4836 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 4837 | |
ab3c759a | 4838 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 4839 | reg_val &= 0xffffff00; |
ab3c759a | 4840 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 4841 | |
ab3c759a | 4842 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
4843 | reg_val &= 0x00ffffff; |
4844 | reg_val |= 0xb0000000; | |
ab3c759a | 4845 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
4846 | } |
4847 | ||
b551842d DV |
4848 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
4849 | struct intel_link_m_n *m_n) | |
4850 | { | |
4851 | struct drm_device *dev = crtc->base.dev; | |
4852 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4853 | int pipe = crtc->pipe; | |
4854 | ||
e3b95f1e DV |
4855 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4856 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
4857 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
4858 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
4859 | } |
4860 | ||
4861 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
4862 | struct intel_link_m_n *m_n) | |
4863 | { | |
4864 | struct drm_device *dev = crtc->base.dev; | |
4865 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4866 | int pipe = crtc->pipe; | |
4867 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
4868 | ||
4869 | if (INTEL_INFO(dev)->gen >= 5) { | |
4870 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
4871 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
4872 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
4873 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
4874 | } else { | |
e3b95f1e DV |
4875 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4876 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
4877 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
4878 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
4879 | } |
4880 | } | |
4881 | ||
03afc4a2 DV |
4882 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
4883 | { | |
4884 | if (crtc->config.has_pch_encoder) | |
4885 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4886 | else | |
4887 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4888 | } | |
4889 | ||
f47709a9 | 4890 | static void vlv_update_pll(struct intel_crtc *crtc) |
a0c4da24 | 4891 | { |
f47709a9 | 4892 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 4893 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4894 | int pipe = crtc->pipe; |
89b667f8 | 4895 | u32 dpll, mdiv; |
a0c4da24 | 4896 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
198a037f | 4897 | u32 coreclk, reg_val, dpll_md; |
a0c4da24 | 4898 | |
09153000 DV |
4899 | mutex_lock(&dev_priv->dpio_lock); |
4900 | ||
f47709a9 DV |
4901 | bestn = crtc->config.dpll.n; |
4902 | bestm1 = crtc->config.dpll.m1; | |
4903 | bestm2 = crtc->config.dpll.m2; | |
4904 | bestp1 = crtc->config.dpll.p1; | |
4905 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 4906 | |
89b667f8 JB |
4907 | /* See eDP HDMI DPIO driver vbios notes doc */ |
4908 | ||
4909 | /* PLL B needs special handling */ | |
4910 | if (pipe) | |
5e69f97f | 4911 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
4912 | |
4913 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 4914 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
4915 | |
4916 | /* Disable target IRef on PLL */ | |
ab3c759a | 4917 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 4918 | reg_val &= 0x00ffffff; |
ab3c759a | 4919 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
4920 | |
4921 | /* Disable fast lock */ | |
ab3c759a | 4922 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
4923 | |
4924 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
4925 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4926 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
4927 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 4928 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
4929 | |
4930 | /* | |
4931 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
4932 | * but we don't support that). | |
4933 | * Note: don't use the DAC post divider as it seems unstable. | |
4934 | */ | |
4935 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 4936 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 4937 | |
a0c4da24 | 4938 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 4939 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 4940 | |
89b667f8 | 4941 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 4942 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 4943 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 4944 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
ab3c759a | 4945 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 4946 | 0x009f0003); |
89b667f8 | 4947 | else |
ab3c759a | 4948 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
4949 | 0x00d0000f); |
4950 | ||
4951 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
4952 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
4953 | /* Use SSC source */ | |
4954 | if (!pipe) | |
ab3c759a | 4955 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
4956 | 0x0df40000); |
4957 | else | |
ab3c759a | 4958 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
4959 | 0x0df70000); |
4960 | } else { /* HDMI or VGA */ | |
4961 | /* Use bend source */ | |
4962 | if (!pipe) | |
ab3c759a | 4963 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
4964 | 0x0df70000); |
4965 | else | |
ab3c759a | 4966 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
4967 | 0x0df40000); |
4968 | } | |
a0c4da24 | 4969 | |
ab3c759a | 4970 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 JB |
4971 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
4972 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
4973 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
4974 | coreclk |= 0x01000000; | |
ab3c759a | 4975 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 4976 | |
ab3c759a | 4977 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a0c4da24 | 4978 | |
89b667f8 JB |
4979 | /* Enable DPIO clock input */ |
4980 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
4981 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
f6071166 JB |
4982 | /* We should never disable this, set it here for state tracking */ |
4983 | if (pipe == PIPE_B) | |
89b667f8 | 4984 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
a0c4da24 | 4985 | dpll |= DPLL_VCO_ENABLE; |
8bcc2795 DV |
4986 | crtc->config.dpll_hw_state.dpll = dpll; |
4987 | ||
ef1b460d DV |
4988 | dpll_md = (crtc->config.pixel_multiplier - 1) |
4989 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 DV |
4990 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
4991 | ||
89b667f8 JB |
4992 | if (crtc->config.has_dp_encoder) |
4993 | intel_dp_set_m_n(crtc); | |
09153000 DV |
4994 | |
4995 | mutex_unlock(&dev_priv->dpio_lock); | |
a0c4da24 JB |
4996 | } |
4997 | ||
f47709a9 DV |
4998 | static void i9xx_update_pll(struct intel_crtc *crtc, |
4999 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
5000 | int num_connectors) |
5001 | { | |
f47709a9 | 5002 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5003 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
5004 | u32 dpll; |
5005 | bool is_sdvo; | |
f47709a9 | 5006 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5007 | |
f47709a9 | 5008 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5009 | |
f47709a9 DV |
5010 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5011 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
5012 | |
5013 | dpll = DPLL_VGA_MODE_DIS; | |
5014 | ||
f47709a9 | 5015 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
5016 | dpll |= DPLLB_MODE_LVDS; |
5017 | else | |
5018 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 5019 | |
ef1b460d | 5020 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
5021 | dpll |= (crtc->config.pixel_multiplier - 1) |
5022 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 5023 | } |
198a037f DV |
5024 | |
5025 | if (is_sdvo) | |
4a33e48d | 5026 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 5027 | |
f47709a9 | 5028 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 5029 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
5030 | |
5031 | /* compute bitmask from p1 value */ | |
5032 | if (IS_PINEVIEW(dev)) | |
5033 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
5034 | else { | |
5035 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5036 | if (IS_G4X(dev) && reduced_clock) | |
5037 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5038 | } | |
5039 | switch (clock->p2) { | |
5040 | case 5: | |
5041 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5042 | break; | |
5043 | case 7: | |
5044 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5045 | break; | |
5046 | case 10: | |
5047 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5048 | break; | |
5049 | case 14: | |
5050 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5051 | break; | |
5052 | } | |
5053 | if (INTEL_INFO(dev)->gen >= 4) | |
5054 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
5055 | ||
09ede541 | 5056 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 5057 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 5058 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5059 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5060 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5061 | else | |
5062 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5063 | ||
5064 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
5065 | crtc->config.dpll_hw_state.dpll = dpll; |
5066 | ||
eb1cbe48 | 5067 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
5068 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5069 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 5070 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 | 5071 | } |
66e3d5c0 DV |
5072 | |
5073 | if (crtc->config.has_dp_encoder) | |
5074 | intel_dp_set_m_n(crtc); | |
eb1cbe48 DV |
5075 | } |
5076 | ||
f47709a9 | 5077 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 5078 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
5079 | int num_connectors) |
5080 | { | |
f47709a9 | 5081 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5082 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 5083 | u32 dpll; |
f47709a9 | 5084 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5085 | |
f47709a9 | 5086 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5087 | |
eb1cbe48 DV |
5088 | dpll = DPLL_VGA_MODE_DIS; |
5089 | ||
f47709a9 | 5090 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
5091 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5092 | } else { | |
5093 | if (clock->p1 == 2) | |
5094 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5095 | else | |
5096 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5097 | if (clock->p2 == 4) | |
5098 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5099 | } | |
5100 | ||
4a33e48d DV |
5101 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
5102 | dpll |= DPLL_DVO_2X_MODE; | |
5103 | ||
f47709a9 | 5104 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5105 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5106 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5107 | else | |
5108 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5109 | ||
5110 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 5111 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
5112 | } |
5113 | ||
8a654f3b | 5114 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
5115 | { |
5116 | struct drm_device *dev = intel_crtc->base.dev; | |
5117 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5118 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 5119 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
5120 | struct drm_display_mode *adjusted_mode = |
5121 | &intel_crtc->config.adjusted_mode; | |
4d8a62ea DV |
5122 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
5123 | ||
5124 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
5125 | * the hw state checker will get angry at the mismatch. */ | |
5126 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
5127 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c PZ |
5128 | |
5129 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
5130 | /* the chip adds 2 halflines automatically */ | |
4d8a62ea DV |
5131 | crtc_vtotal -= 1; |
5132 | crtc_vblank_end -= 1; | |
b0e77b9c PZ |
5133 | vsyncshift = adjusted_mode->crtc_hsync_start |
5134 | - adjusted_mode->crtc_htotal / 2; | |
5135 | } else { | |
5136 | vsyncshift = 0; | |
5137 | } | |
5138 | ||
5139 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 5140 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 5141 | |
fe2b8f9d | 5142 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
5143 | (adjusted_mode->crtc_hdisplay - 1) | |
5144 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 5145 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
5146 | (adjusted_mode->crtc_hblank_start - 1) | |
5147 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 5148 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
5149 | (adjusted_mode->crtc_hsync_start - 1) | |
5150 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
5151 | ||
fe2b8f9d | 5152 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 5153 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 5154 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 5155 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 5156 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 5157 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 5158 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
5159 | (adjusted_mode->crtc_vsync_start - 1) | |
5160 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
5161 | ||
b5e508d4 PZ |
5162 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
5163 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
5164 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
5165 | * bits. */ | |
5166 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
5167 | (pipe == PIPE_B || pipe == PIPE_C)) | |
5168 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
5169 | ||
b0e77b9c PZ |
5170 | /* pipesrc controls the size that is scaled from, which should |
5171 | * always be the user's requested size. | |
5172 | */ | |
5173 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
5174 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
5175 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
5176 | } |
5177 | ||
1bd1bd80 DV |
5178 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5179 | struct intel_crtc_config *pipe_config) | |
5180 | { | |
5181 | struct drm_device *dev = crtc->base.dev; | |
5182 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5183 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
5184 | uint32_t tmp; | |
5185 | ||
5186 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
5187 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
5188 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
5189 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
5190 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
5191 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5192 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
5193 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
5194 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5195 | ||
5196 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
5197 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
5198 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
5199 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
5200 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
5201 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
5202 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
5203 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
5204 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
5205 | ||
5206 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
5207 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
5208 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
5209 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
5210 | } | |
5211 | ||
5212 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
5213 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
5214 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
5215 | ||
5216 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
5217 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
5218 | } |
5219 | ||
babea61d JB |
5220 | static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc, |
5221 | struct intel_crtc_config *pipe_config) | |
5222 | { | |
5223 | struct drm_crtc *crtc = &intel_crtc->base; | |
5224 | ||
5225 | crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; | |
5226 | crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal; | |
5227 | crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
5228 | crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
5229 | ||
5230 | crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; | |
5231 | crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
5232 | crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
5233 | crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
5234 | ||
5235 | crtc->mode.flags = pipe_config->adjusted_mode.flags; | |
5236 | ||
241bfc38 | 5237 | crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock; |
babea61d JB |
5238 | crtc->mode.flags |= pipe_config->adjusted_mode.flags; |
5239 | } | |
5240 | ||
84b046f3 DV |
5241 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
5242 | { | |
5243 | struct drm_device *dev = intel_crtc->base.dev; | |
5244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5245 | uint32_t pipeconf; | |
5246 | ||
9f11a9e4 | 5247 | pipeconf = 0; |
84b046f3 | 5248 | |
67c72a12 DV |
5249 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
5250 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) | |
5251 | pipeconf |= PIPECONF_ENABLE; | |
5252 | ||
cf532bb2 VS |
5253 | if (intel_crtc->config.double_wide) |
5254 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 5255 | |
ff9ce46e DV |
5256 | /* only g4x and later have fancy bpc/dither controls */ |
5257 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
5258 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
5259 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
5260 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 5261 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 5262 | |
ff9ce46e DV |
5263 | switch (intel_crtc->config.pipe_bpp) { |
5264 | case 18: | |
5265 | pipeconf |= PIPECONF_6BPC; | |
5266 | break; | |
5267 | case 24: | |
5268 | pipeconf |= PIPECONF_8BPC; | |
5269 | break; | |
5270 | case 30: | |
5271 | pipeconf |= PIPECONF_10BPC; | |
5272 | break; | |
5273 | default: | |
5274 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
5275 | BUG(); | |
84b046f3 DV |
5276 | } |
5277 | } | |
5278 | ||
5279 | if (HAS_PIPE_CXSR(dev)) { | |
5280 | if (intel_crtc->lowfreq_avail) { | |
5281 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
5282 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
5283 | } else { | |
5284 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
5285 | } |
5286 | } | |
5287 | ||
84b046f3 DV |
5288 | if (!IS_GEN2(dev) && |
5289 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) | |
5290 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
5291 | else | |
5292 | pipeconf |= PIPECONF_PROGRESSIVE; | |
5293 | ||
9f11a9e4 DV |
5294 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
5295 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 5296 | |
84b046f3 DV |
5297 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
5298 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
5299 | } | |
5300 | ||
f564048e | 5301 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 5302 | int x, int y, |
94352cf9 | 5303 | struct drm_framebuffer *fb) |
79e53945 JB |
5304 | { |
5305 | struct drm_device *dev = crtc->dev; | |
5306 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5307 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5308 | int pipe = intel_crtc->pipe; | |
80824003 | 5309 | int plane = intel_crtc->plane; |
c751ce4f | 5310 | int refclk, num_connectors = 0; |
652c393a | 5311 | intel_clock_t clock, reduced_clock; |
84b046f3 | 5312 | u32 dspcntr; |
a16af721 | 5313 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 5314 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 5315 | struct intel_encoder *encoder; |
d4906093 | 5316 | const intel_limit_t *limit; |
5c3b82e2 | 5317 | int ret; |
79e53945 | 5318 | |
6c2b7c12 | 5319 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 5320 | switch (encoder->type) { |
79e53945 JB |
5321 | case INTEL_OUTPUT_LVDS: |
5322 | is_lvds = true; | |
5323 | break; | |
e9fd1c02 JN |
5324 | case INTEL_OUTPUT_DSI: |
5325 | is_dsi = true; | |
5326 | break; | |
79e53945 | 5327 | } |
43565a06 | 5328 | |
c751ce4f | 5329 | num_connectors++; |
79e53945 JB |
5330 | } |
5331 | ||
f2335330 JN |
5332 | if (is_dsi) |
5333 | goto skip_dpll; | |
5334 | ||
5335 | if (!intel_crtc->config.clock_set) { | |
5336 | refclk = i9xx_get_refclk(crtc, num_connectors); | |
79e53945 | 5337 | |
e9fd1c02 JN |
5338 | /* |
5339 | * Returns a set of divisors for the desired target clock with | |
5340 | * the given refclk, or FALSE. The returned values represent | |
5341 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
5342 | * 2) / p1 / p2. | |
5343 | */ | |
5344 | limit = intel_limit(crtc, refclk); | |
5345 | ok = dev_priv->display.find_dpll(limit, crtc, | |
5346 | intel_crtc->config.port_clock, | |
5347 | refclk, NULL, &clock); | |
f2335330 | 5348 | if (!ok) { |
e9fd1c02 JN |
5349 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5350 | return -EINVAL; | |
5351 | } | |
79e53945 | 5352 | |
f2335330 JN |
5353 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
5354 | /* | |
5355 | * Ensure we match the reduced clock's P to the target | |
5356 | * clock. If the clocks don't match, we can't switch | |
5357 | * the display clock by using the FP0/FP1. In such case | |
5358 | * we will disable the LVDS downclock feature. | |
5359 | */ | |
5360 | has_reduced_clock = | |
5361 | dev_priv->display.find_dpll(limit, crtc, | |
5362 | dev_priv->lvds_downclock, | |
5363 | refclk, &clock, | |
5364 | &reduced_clock); | |
5365 | } | |
5366 | /* Compat-code for transition, will disappear. */ | |
f47709a9 DV |
5367 | intel_crtc->config.dpll.n = clock.n; |
5368 | intel_crtc->config.dpll.m1 = clock.m1; | |
5369 | intel_crtc->config.dpll.m2 = clock.m2; | |
5370 | intel_crtc->config.dpll.p1 = clock.p1; | |
5371 | intel_crtc->config.dpll.p2 = clock.p2; | |
5372 | } | |
7026d4ac | 5373 | |
e9fd1c02 | 5374 | if (IS_GEN2(dev)) { |
8a654f3b | 5375 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
5376 | has_reduced_clock ? &reduced_clock : NULL, |
5377 | num_connectors); | |
e9fd1c02 | 5378 | } else if (IS_VALLEYVIEW(dev)) { |
f2335330 | 5379 | vlv_update_pll(intel_crtc); |
e9fd1c02 | 5380 | } else { |
f47709a9 | 5381 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 5382 | has_reduced_clock ? &reduced_clock : NULL, |
89b667f8 | 5383 | num_connectors); |
e9fd1c02 | 5384 | } |
79e53945 | 5385 | |
f2335330 | 5386 | skip_dpll: |
79e53945 JB |
5387 | /* Set up the display plane register */ |
5388 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
5389 | ||
da6ecc5d JB |
5390 | if (!IS_VALLEYVIEW(dev)) { |
5391 | if (pipe == 0) | |
5392 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
5393 | else | |
5394 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
5395 | } | |
79e53945 | 5396 | |
8a654f3b | 5397 | intel_set_pipe_timings(intel_crtc); |
5eddb70b CW |
5398 | |
5399 | /* pipesrc and dspsize control the size that is scaled from, | |
5400 | * which should always be the user's requested size. | |
79e53945 | 5401 | */ |
929c77fb | 5402 | I915_WRITE(DSPSIZE(plane), |
37327abd VS |
5403 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
5404 | (intel_crtc->config.pipe_src_w - 1)); | |
929c77fb | 5405 | I915_WRITE(DSPPOS(plane), 0); |
2c07245f | 5406 | |
84b046f3 DV |
5407 | i9xx_set_pipeconf(intel_crtc); |
5408 | ||
f564048e EA |
5409 | I915_WRITE(DSPCNTR(plane), dspcntr); |
5410 | POSTING_READ(DSPCNTR(plane)); | |
5411 | ||
94352cf9 | 5412 | ret = intel_pipe_set_base(crtc, x, y, fb); |
f564048e | 5413 | |
f564048e EA |
5414 | return ret; |
5415 | } | |
5416 | ||
2fa2fe9a DV |
5417 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5418 | struct intel_crtc_config *pipe_config) | |
5419 | { | |
5420 | struct drm_device *dev = crtc->base.dev; | |
5421 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5422 | uint32_t tmp; | |
5423 | ||
5424 | tmp = I915_READ(PFIT_CONTROL); | |
06922821 DV |
5425 | if (!(tmp & PFIT_ENABLE)) |
5426 | return; | |
2fa2fe9a | 5427 | |
06922821 | 5428 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
5429 | if (INTEL_INFO(dev)->gen < 4) { |
5430 | if (crtc->pipe != PIPE_B) | |
5431 | return; | |
2fa2fe9a DV |
5432 | } else { |
5433 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
5434 | return; | |
5435 | } | |
5436 | ||
06922821 | 5437 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
5438 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
5439 | if (INTEL_INFO(dev)->gen < 5) | |
5440 | pipe_config->gmch_pfit.lvds_border_bits = | |
5441 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
5442 | } | |
5443 | ||
acbec814 JB |
5444 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5445 | struct intel_crtc_config *pipe_config) | |
5446 | { | |
5447 | struct drm_device *dev = crtc->base.dev; | |
5448 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5449 | int pipe = pipe_config->cpu_transcoder; | |
5450 | intel_clock_t clock; | |
5451 | u32 mdiv; | |
662c6ecb | 5452 | int refclk = 100000; |
acbec814 JB |
5453 | |
5454 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a | 5455 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
5456 | mutex_unlock(&dev_priv->dpio_lock); |
5457 | ||
5458 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
5459 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
5460 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
5461 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
5462 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
5463 | ||
f646628b | 5464 | vlv_clock(refclk, &clock); |
acbec814 | 5465 | |
f646628b VS |
5466 | /* clock.dot is the fast clock */ |
5467 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
5468 | } |
5469 | ||
0e8ffe1b DV |
5470 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5471 | struct intel_crtc_config *pipe_config) | |
5472 | { | |
5473 | struct drm_device *dev = crtc->base.dev; | |
5474 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5475 | uint32_t tmp; | |
5476 | ||
e143a21c | 5477 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 5478 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 5479 | |
0e8ffe1b DV |
5480 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5481 | if (!(tmp & PIPECONF_ENABLE)) | |
5482 | return false; | |
5483 | ||
42571aef VS |
5484 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
5485 | switch (tmp & PIPECONF_BPC_MASK) { | |
5486 | case PIPECONF_6BPC: | |
5487 | pipe_config->pipe_bpp = 18; | |
5488 | break; | |
5489 | case PIPECONF_8BPC: | |
5490 | pipe_config->pipe_bpp = 24; | |
5491 | break; | |
5492 | case PIPECONF_10BPC: | |
5493 | pipe_config->pipe_bpp = 30; | |
5494 | break; | |
5495 | default: | |
5496 | break; | |
5497 | } | |
5498 | } | |
5499 | ||
282740f7 VS |
5500 | if (INTEL_INFO(dev)->gen < 4) |
5501 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
5502 | ||
1bd1bd80 DV |
5503 | intel_get_pipe_timings(crtc, pipe_config); |
5504 | ||
2fa2fe9a DV |
5505 | i9xx_get_pfit_config(crtc, pipe_config); |
5506 | ||
6c49f241 DV |
5507 | if (INTEL_INFO(dev)->gen >= 4) { |
5508 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
5509 | pipe_config->pixel_multiplier = | |
5510 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
5511 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 5512 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
5513 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
5514 | tmp = I915_READ(DPLL(crtc->pipe)); | |
5515 | pipe_config->pixel_multiplier = | |
5516 | ((tmp & SDVO_MULTIPLIER_MASK) | |
5517 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
5518 | } else { | |
5519 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
5520 | * port and will be fixed up in the encoder->get_config | |
5521 | * function. */ | |
5522 | pipe_config->pixel_multiplier = 1; | |
5523 | } | |
8bcc2795 DV |
5524 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
5525 | if (!IS_VALLEYVIEW(dev)) { | |
5526 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
5527 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
5528 | } else { |
5529 | /* Mask out read-only status bits. */ | |
5530 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
5531 | DPLL_PORTC_READY_MASK | | |
5532 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 5533 | } |
6c49f241 | 5534 | |
acbec814 JB |
5535 | if (IS_VALLEYVIEW(dev)) |
5536 | vlv_crtc_clock_get(crtc, pipe_config); | |
5537 | else | |
5538 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 5539 | |
0e8ffe1b DV |
5540 | return true; |
5541 | } | |
5542 | ||
dde86e2d | 5543 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
5544 | { |
5545 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5546 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 5547 | struct intel_encoder *encoder; |
74cfd7ac | 5548 | u32 val, final; |
13d83a67 | 5549 | bool has_lvds = false; |
199e5d79 | 5550 | bool has_cpu_edp = false; |
199e5d79 | 5551 | bool has_panel = false; |
99eb6a01 KP |
5552 | bool has_ck505 = false; |
5553 | bool can_ssc = false; | |
13d83a67 JB |
5554 | |
5555 | /* We need to take the global config into account */ | |
199e5d79 KP |
5556 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5557 | base.head) { | |
5558 | switch (encoder->type) { | |
5559 | case INTEL_OUTPUT_LVDS: | |
5560 | has_panel = true; | |
5561 | has_lvds = true; | |
5562 | break; | |
5563 | case INTEL_OUTPUT_EDP: | |
5564 | has_panel = true; | |
2de6905f | 5565 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
5566 | has_cpu_edp = true; |
5567 | break; | |
13d83a67 JB |
5568 | } |
5569 | } | |
5570 | ||
99eb6a01 | 5571 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 5572 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
5573 | can_ssc = has_ck505; |
5574 | } else { | |
5575 | has_ck505 = false; | |
5576 | can_ssc = true; | |
5577 | } | |
5578 | ||
2de6905f ID |
5579 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
5580 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
5581 | |
5582 | /* Ironlake: try to setup display ref clock before DPLL | |
5583 | * enabling. This is only under driver's control after | |
5584 | * PCH B stepping, previous chipset stepping should be | |
5585 | * ignoring this setting. | |
5586 | */ | |
74cfd7ac CW |
5587 | val = I915_READ(PCH_DREF_CONTROL); |
5588 | ||
5589 | /* As we must carefully and slowly disable/enable each source in turn, | |
5590 | * compute the final state we want first and check if we need to | |
5591 | * make any changes at all. | |
5592 | */ | |
5593 | final = val; | |
5594 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
5595 | if (has_ck505) | |
5596 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
5597 | else | |
5598 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
5599 | ||
5600 | final &= ~DREF_SSC_SOURCE_MASK; | |
5601 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
5602 | final &= ~DREF_SSC1_ENABLE; | |
5603 | ||
5604 | if (has_panel) { | |
5605 | final |= DREF_SSC_SOURCE_ENABLE; | |
5606 | ||
5607 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5608 | final |= DREF_SSC1_ENABLE; | |
5609 | ||
5610 | if (has_cpu_edp) { | |
5611 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5612 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
5613 | else | |
5614 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
5615 | } else | |
5616 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5617 | } else { | |
5618 | final |= DREF_SSC_SOURCE_DISABLE; | |
5619 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5620 | } | |
5621 | ||
5622 | if (final == val) | |
5623 | return; | |
5624 | ||
13d83a67 | 5625 | /* Always enable nonspread source */ |
74cfd7ac | 5626 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 5627 | |
99eb6a01 | 5628 | if (has_ck505) |
74cfd7ac | 5629 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 5630 | else |
74cfd7ac | 5631 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 5632 | |
199e5d79 | 5633 | if (has_panel) { |
74cfd7ac CW |
5634 | val &= ~DREF_SSC_SOURCE_MASK; |
5635 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 5636 | |
199e5d79 | 5637 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 5638 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5639 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 5640 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 5641 | } else |
74cfd7ac | 5642 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
5643 | |
5644 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 5645 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5646 | POSTING_READ(PCH_DREF_CONTROL); |
5647 | udelay(200); | |
5648 | ||
74cfd7ac | 5649 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
5650 | |
5651 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 5652 | if (has_cpu_edp) { |
99eb6a01 | 5653 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5654 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 5655 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 5656 | } |
13d83a67 | 5657 | else |
74cfd7ac | 5658 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 5659 | } else |
74cfd7ac | 5660 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5661 | |
74cfd7ac | 5662 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5663 | POSTING_READ(PCH_DREF_CONTROL); |
5664 | udelay(200); | |
5665 | } else { | |
5666 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
5667 | ||
74cfd7ac | 5668 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
5669 | |
5670 | /* Turn off CPU output */ | |
74cfd7ac | 5671 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5672 | |
74cfd7ac | 5673 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5674 | POSTING_READ(PCH_DREF_CONTROL); |
5675 | udelay(200); | |
5676 | ||
5677 | /* Turn off the SSC source */ | |
74cfd7ac CW |
5678 | val &= ~DREF_SSC_SOURCE_MASK; |
5679 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
5680 | |
5681 | /* Turn off SSC1 */ | |
74cfd7ac | 5682 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 5683 | |
74cfd7ac | 5684 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
5685 | POSTING_READ(PCH_DREF_CONTROL); |
5686 | udelay(200); | |
5687 | } | |
74cfd7ac CW |
5688 | |
5689 | BUG_ON(val != final); | |
13d83a67 JB |
5690 | } |
5691 | ||
f31f2d55 | 5692 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 5693 | { |
f31f2d55 | 5694 | uint32_t tmp; |
dde86e2d | 5695 | |
0ff066a9 PZ |
5696 | tmp = I915_READ(SOUTH_CHICKEN2); |
5697 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
5698 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5699 | |
0ff066a9 PZ |
5700 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
5701 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
5702 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 5703 | |
0ff066a9 PZ |
5704 | tmp = I915_READ(SOUTH_CHICKEN2); |
5705 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
5706 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5707 | |
0ff066a9 PZ |
5708 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
5709 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
5710 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
5711 | } |
5712 | ||
5713 | /* WaMPhyProgramming:hsw */ | |
5714 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
5715 | { | |
5716 | uint32_t tmp; | |
dde86e2d PZ |
5717 | |
5718 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
5719 | tmp &= ~(0xFF << 24); | |
5720 | tmp |= (0x12 << 24); | |
5721 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
5722 | ||
dde86e2d PZ |
5723 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
5724 | tmp |= (1 << 11); | |
5725 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
5726 | ||
5727 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
5728 | tmp |= (1 << 11); | |
5729 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
5730 | ||
dde86e2d PZ |
5731 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
5732 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5733 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
5734 | ||
5735 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
5736 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5737 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
5738 | ||
0ff066a9 PZ |
5739 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
5740 | tmp &= ~(7 << 13); | |
5741 | tmp |= (5 << 13); | |
5742 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 5743 | |
0ff066a9 PZ |
5744 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
5745 | tmp &= ~(7 << 13); | |
5746 | tmp |= (5 << 13); | |
5747 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
5748 | |
5749 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
5750 | tmp &= ~0xFF; | |
5751 | tmp |= 0x1C; | |
5752 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
5753 | ||
5754 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
5755 | tmp &= ~0xFF; | |
5756 | tmp |= 0x1C; | |
5757 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
5758 | ||
5759 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
5760 | tmp &= ~(0xFF << 16); | |
5761 | tmp |= (0x1C << 16); | |
5762 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
5763 | ||
5764 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
5765 | tmp &= ~(0xFF << 16); | |
5766 | tmp |= (0x1C << 16); | |
5767 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
5768 | ||
0ff066a9 PZ |
5769 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
5770 | tmp |= (1 << 27); | |
5771 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 5772 | |
0ff066a9 PZ |
5773 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
5774 | tmp |= (1 << 27); | |
5775 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 5776 | |
0ff066a9 PZ |
5777 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
5778 | tmp &= ~(0xF << 28); | |
5779 | tmp |= (4 << 28); | |
5780 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 5781 | |
0ff066a9 PZ |
5782 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
5783 | tmp &= ~(0xF << 28); | |
5784 | tmp |= (4 << 28); | |
5785 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
5786 | } |
5787 | ||
2fa86a1f PZ |
5788 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
5789 | * Programming" based on the parameters passed: | |
5790 | * - Sequence to enable CLKOUT_DP | |
5791 | * - Sequence to enable CLKOUT_DP without spread | |
5792 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
5793 | */ | |
5794 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
5795 | bool with_fdi) | |
f31f2d55 PZ |
5796 | { |
5797 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
5798 | uint32_t reg, tmp; |
5799 | ||
5800 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
5801 | with_spread = true; | |
5802 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
5803 | with_fdi, "LP PCH doesn't have FDI\n")) | |
5804 | with_fdi = false; | |
f31f2d55 PZ |
5805 | |
5806 | mutex_lock(&dev_priv->dpio_lock); | |
5807 | ||
5808 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5809 | tmp &= ~SBI_SSCCTL_DISABLE; | |
5810 | tmp |= SBI_SSCCTL_PATHALT; | |
5811 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5812 | ||
5813 | udelay(24); | |
5814 | ||
2fa86a1f PZ |
5815 | if (with_spread) { |
5816 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5817 | tmp &= ~SBI_SSCCTL_PATHALT; | |
5818 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 5819 | |
2fa86a1f PZ |
5820 | if (with_fdi) { |
5821 | lpt_reset_fdi_mphy(dev_priv); | |
5822 | lpt_program_fdi_mphy(dev_priv); | |
5823 | } | |
5824 | } | |
dde86e2d | 5825 | |
2fa86a1f PZ |
5826 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
5827 | SBI_GEN0 : SBI_DBUFF0; | |
5828 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
5829 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
5830 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
5831 | |
5832 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
5833 | } |
5834 | ||
47701c3b PZ |
5835 | /* Sequence to disable CLKOUT_DP */ |
5836 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
5837 | { | |
5838 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5839 | uint32_t reg, tmp; | |
5840 | ||
5841 | mutex_lock(&dev_priv->dpio_lock); | |
5842 | ||
5843 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
5844 | SBI_GEN0 : SBI_DBUFF0; | |
5845 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
5846 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
5847 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
5848 | ||
5849 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5850 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
5851 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
5852 | tmp |= SBI_SSCCTL_PATHALT; | |
5853 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5854 | udelay(32); | |
5855 | } | |
5856 | tmp |= SBI_SSCCTL_DISABLE; | |
5857 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5858 | } | |
5859 | ||
5860 | mutex_unlock(&dev_priv->dpio_lock); | |
5861 | } | |
5862 | ||
bf8fa3d3 PZ |
5863 | static void lpt_init_pch_refclk(struct drm_device *dev) |
5864 | { | |
5865 | struct drm_mode_config *mode_config = &dev->mode_config; | |
5866 | struct intel_encoder *encoder; | |
5867 | bool has_vga = false; | |
5868 | ||
5869 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
5870 | switch (encoder->type) { | |
5871 | case INTEL_OUTPUT_ANALOG: | |
5872 | has_vga = true; | |
5873 | break; | |
5874 | } | |
5875 | } | |
5876 | ||
47701c3b PZ |
5877 | if (has_vga) |
5878 | lpt_enable_clkout_dp(dev, true, true); | |
5879 | else | |
5880 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
5881 | } |
5882 | ||
dde86e2d PZ |
5883 | /* |
5884 | * Initialize reference clocks when the driver loads | |
5885 | */ | |
5886 | void intel_init_pch_refclk(struct drm_device *dev) | |
5887 | { | |
5888 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
5889 | ironlake_init_pch_refclk(dev); | |
5890 | else if (HAS_PCH_LPT(dev)) | |
5891 | lpt_init_pch_refclk(dev); | |
5892 | } | |
5893 | ||
d9d444cb JB |
5894 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5895 | { | |
5896 | struct drm_device *dev = crtc->dev; | |
5897 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5898 | struct intel_encoder *encoder; | |
d9d444cb JB |
5899 | int num_connectors = 0; |
5900 | bool is_lvds = false; | |
5901 | ||
6c2b7c12 | 5902 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
5903 | switch (encoder->type) { |
5904 | case INTEL_OUTPUT_LVDS: | |
5905 | is_lvds = true; | |
5906 | break; | |
d9d444cb JB |
5907 | } |
5908 | num_connectors++; | |
5909 | } | |
5910 | ||
5911 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
5912 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
41aa3448 RV |
5913 | dev_priv->vbt.lvds_ssc_freq); |
5914 | return dev_priv->vbt.lvds_ssc_freq * 1000; | |
d9d444cb JB |
5915 | } |
5916 | ||
5917 | return 120000; | |
5918 | } | |
5919 | ||
6ff93609 | 5920 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 5921 | { |
c8203565 | 5922 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
5923 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5924 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
5925 | uint32_t val; |
5926 | ||
78114071 | 5927 | val = 0; |
c8203565 | 5928 | |
965e0c48 | 5929 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 5930 | case 18: |
dfd07d72 | 5931 | val |= PIPECONF_6BPC; |
c8203565 PZ |
5932 | break; |
5933 | case 24: | |
dfd07d72 | 5934 | val |= PIPECONF_8BPC; |
c8203565 PZ |
5935 | break; |
5936 | case 30: | |
dfd07d72 | 5937 | val |= PIPECONF_10BPC; |
c8203565 PZ |
5938 | break; |
5939 | case 36: | |
dfd07d72 | 5940 | val |= PIPECONF_12BPC; |
c8203565 PZ |
5941 | break; |
5942 | default: | |
cc769b62 PZ |
5943 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5944 | BUG(); | |
c8203565 PZ |
5945 | } |
5946 | ||
d8b32247 | 5947 | if (intel_crtc->config.dither) |
c8203565 PZ |
5948 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5949 | ||
6ff93609 | 5950 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
5951 | val |= PIPECONF_INTERLACED_ILK; |
5952 | else | |
5953 | val |= PIPECONF_PROGRESSIVE; | |
5954 | ||
50f3b016 | 5955 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 5956 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 5957 | |
c8203565 PZ |
5958 | I915_WRITE(PIPECONF(pipe), val); |
5959 | POSTING_READ(PIPECONF(pipe)); | |
5960 | } | |
5961 | ||
86d3efce VS |
5962 | /* |
5963 | * Set up the pipe CSC unit. | |
5964 | * | |
5965 | * Currently only full range RGB to limited range RGB conversion | |
5966 | * is supported, but eventually this should handle various | |
5967 | * RGB<->YCbCr scenarios as well. | |
5968 | */ | |
50f3b016 | 5969 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
5970 | { |
5971 | struct drm_device *dev = crtc->dev; | |
5972 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5973 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5974 | int pipe = intel_crtc->pipe; | |
5975 | uint16_t coeff = 0x7800; /* 1.0 */ | |
5976 | ||
5977 | /* | |
5978 | * TODO: Check what kind of values actually come out of the pipe | |
5979 | * with these coeff/postoff values and adjust to get the best | |
5980 | * accuracy. Perhaps we even need to take the bpc value into | |
5981 | * consideration. | |
5982 | */ | |
5983 | ||
50f3b016 | 5984 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
5985 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
5986 | ||
5987 | /* | |
5988 | * GY/GU and RY/RU should be the other way around according | |
5989 | * to BSpec, but reality doesn't agree. Just set them up in | |
5990 | * a way that results in the correct picture. | |
5991 | */ | |
5992 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
5993 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
5994 | ||
5995 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
5996 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
5997 | ||
5998 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
5999 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
6000 | ||
6001 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
6002 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
6003 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
6004 | ||
6005 | if (INTEL_INFO(dev)->gen > 6) { | |
6006 | uint16_t postoff = 0; | |
6007 | ||
50f3b016 | 6008 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6009 | postoff = (16 * (1 << 13) / 255) & 0x1fff; |
6010 | ||
6011 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
6012 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
6013 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
6014 | ||
6015 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
6016 | } else { | |
6017 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
6018 | ||
50f3b016 | 6019 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6020 | mode |= CSC_BLACK_SCREEN_OFFSET; |
6021 | ||
6022 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
6023 | } | |
6024 | } | |
6025 | ||
6ff93609 | 6026 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 6027 | { |
756f85cf PZ |
6028 | struct drm_device *dev = crtc->dev; |
6029 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 6030 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 6031 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 6032 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
6033 | uint32_t val; |
6034 | ||
3eff4faa | 6035 | val = 0; |
ee2b0b38 | 6036 | |
756f85cf | 6037 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
6038 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6039 | ||
6ff93609 | 6040 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
6041 | val |= PIPECONF_INTERLACED_ILK; |
6042 | else | |
6043 | val |= PIPECONF_PROGRESSIVE; | |
6044 | ||
702e7a56 PZ |
6045 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
6046 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
6047 | |
6048 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
6049 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf PZ |
6050 | |
6051 | if (IS_BROADWELL(dev)) { | |
6052 | val = 0; | |
6053 | ||
6054 | switch (intel_crtc->config.pipe_bpp) { | |
6055 | case 18: | |
6056 | val |= PIPEMISC_DITHER_6_BPC; | |
6057 | break; | |
6058 | case 24: | |
6059 | val |= PIPEMISC_DITHER_8_BPC; | |
6060 | break; | |
6061 | case 30: | |
6062 | val |= PIPEMISC_DITHER_10_BPC; | |
6063 | break; | |
6064 | case 36: | |
6065 | val |= PIPEMISC_DITHER_12_BPC; | |
6066 | break; | |
6067 | default: | |
6068 | /* Case prevented by pipe_config_set_bpp. */ | |
6069 | BUG(); | |
6070 | } | |
6071 | ||
6072 | if (intel_crtc->config.dither) | |
6073 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
6074 | ||
6075 | I915_WRITE(PIPEMISC(pipe), val); | |
6076 | } | |
ee2b0b38 PZ |
6077 | } |
6078 | ||
6591c6e4 | 6079 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
6080 | intel_clock_t *clock, |
6081 | bool *has_reduced_clock, | |
6082 | intel_clock_t *reduced_clock) | |
6083 | { | |
6084 | struct drm_device *dev = crtc->dev; | |
6085 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6086 | struct intel_encoder *intel_encoder; | |
6087 | int refclk; | |
d4906093 | 6088 | const intel_limit_t *limit; |
a16af721 | 6089 | bool ret, is_lvds = false; |
79e53945 | 6090 | |
6591c6e4 PZ |
6091 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6092 | switch (intel_encoder->type) { | |
79e53945 JB |
6093 | case INTEL_OUTPUT_LVDS: |
6094 | is_lvds = true; | |
6095 | break; | |
79e53945 JB |
6096 | } |
6097 | } | |
6098 | ||
d9d444cb | 6099 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 6100 | |
d4906093 ML |
6101 | /* |
6102 | * Returns a set of divisors for the desired target clock with the given | |
6103 | * refclk, or FALSE. The returned values represent the clock equation: | |
6104 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
6105 | */ | |
1b894b59 | 6106 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
6107 | ret = dev_priv->display.find_dpll(limit, crtc, |
6108 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 6109 | refclk, NULL, clock); |
6591c6e4 PZ |
6110 | if (!ret) |
6111 | return false; | |
cda4b7d3 | 6112 | |
ddc9003c | 6113 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
6114 | /* |
6115 | * Ensure we match the reduced clock's P to the target clock. | |
6116 | * If the clocks don't match, we can't switch the display clock | |
6117 | * by using the FP0/FP1. In such case we will disable the LVDS | |
6118 | * downclock feature. | |
6119 | */ | |
ee9300bb DV |
6120 | *has_reduced_clock = |
6121 | dev_priv->display.find_dpll(limit, crtc, | |
6122 | dev_priv->lvds_downclock, | |
6123 | refclk, clock, | |
6124 | reduced_clock); | |
652c393a | 6125 | } |
61e9653f | 6126 | |
6591c6e4 PZ |
6127 | return true; |
6128 | } | |
6129 | ||
d4b1931c PZ |
6130 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
6131 | { | |
6132 | /* | |
6133 | * Account for spread spectrum to avoid | |
6134 | * oversubscribing the link. Max center spread | |
6135 | * is 2.5%; use 5% for safety's sake. | |
6136 | */ | |
6137 | u32 bps = target_clock * bpp * 21 / 20; | |
6138 | return bps / (link_bw * 8) + 1; | |
6139 | } | |
6140 | ||
7429e9d4 | 6141 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 6142 | { |
7429e9d4 | 6143 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
6144 | } |
6145 | ||
de13a2e3 | 6146 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 6147 | u32 *fp, |
9a7c7890 | 6148 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 6149 | { |
de13a2e3 | 6150 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
6151 | struct drm_device *dev = crtc->dev; |
6152 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
6153 | struct intel_encoder *intel_encoder; |
6154 | uint32_t dpll; | |
6cc5f341 | 6155 | int factor, num_connectors = 0; |
09ede541 | 6156 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 6157 | |
de13a2e3 PZ |
6158 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
6159 | switch (intel_encoder->type) { | |
79e53945 JB |
6160 | case INTEL_OUTPUT_LVDS: |
6161 | is_lvds = true; | |
6162 | break; | |
6163 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 6164 | case INTEL_OUTPUT_HDMI: |
79e53945 | 6165 | is_sdvo = true; |
79e53945 | 6166 | break; |
79e53945 | 6167 | } |
43565a06 | 6168 | |
c751ce4f | 6169 | num_connectors++; |
79e53945 | 6170 | } |
79e53945 | 6171 | |
c1858123 | 6172 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
6173 | factor = 21; |
6174 | if (is_lvds) { | |
6175 | if ((intel_panel_use_ssc(dev_priv) && | |
41aa3448 | 6176 | dev_priv->vbt.lvds_ssc_freq == 100) || |
f0b44056 | 6177 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 6178 | factor = 25; |
09ede541 | 6179 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 6180 | factor = 20; |
c1858123 | 6181 | |
7429e9d4 | 6182 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 6183 | *fp |= FP_CB_TUNE; |
2c07245f | 6184 | |
9a7c7890 DV |
6185 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
6186 | *fp2 |= FP_CB_TUNE; | |
6187 | ||
5eddb70b | 6188 | dpll = 0; |
2c07245f | 6189 | |
a07d6787 EA |
6190 | if (is_lvds) |
6191 | dpll |= DPLLB_MODE_LVDS; | |
6192 | else | |
6193 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 6194 | |
ef1b460d DV |
6195 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
6196 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
6197 | |
6198 | if (is_sdvo) | |
4a33e48d | 6199 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 6200 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 6201 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 6202 | |
a07d6787 | 6203 | /* compute bitmask from p1 value */ |
7429e9d4 | 6204 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 6205 | /* also FPA1 */ |
7429e9d4 | 6206 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 6207 | |
7429e9d4 | 6208 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
6209 | case 5: |
6210 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6211 | break; | |
6212 | case 7: | |
6213 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6214 | break; | |
6215 | case 10: | |
6216 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6217 | break; | |
6218 | case 14: | |
6219 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6220 | break; | |
79e53945 JB |
6221 | } |
6222 | ||
b4c09f3b | 6223 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 6224 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
6225 | else |
6226 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6227 | ||
959e16d6 | 6228 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
6229 | } |
6230 | ||
6231 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
6232 | int x, int y, |
6233 | struct drm_framebuffer *fb) | |
6234 | { | |
6235 | struct drm_device *dev = crtc->dev; | |
6236 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6237 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6238 | int pipe = intel_crtc->pipe; | |
6239 | int plane = intel_crtc->plane; | |
6240 | int num_connectors = 0; | |
6241 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 6242 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 6243 | bool ok, has_reduced_clock = false; |
8b47047b | 6244 | bool is_lvds = false; |
de13a2e3 | 6245 | struct intel_encoder *encoder; |
e2b78267 | 6246 | struct intel_shared_dpll *pll; |
de13a2e3 | 6247 | int ret; |
de13a2e3 PZ |
6248 | |
6249 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
6250 | switch (encoder->type) { | |
6251 | case INTEL_OUTPUT_LVDS: | |
6252 | is_lvds = true; | |
6253 | break; | |
de13a2e3 PZ |
6254 | } |
6255 | ||
6256 | num_connectors++; | |
a07d6787 | 6257 | } |
79e53945 | 6258 | |
5dc5298b PZ |
6259 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
6260 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 6261 | |
ff9a6750 | 6262 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 6263 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 6264 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
6265 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6266 | return -EINVAL; | |
79e53945 | 6267 | } |
f47709a9 DV |
6268 | /* Compat-code for transition, will disappear. */ |
6269 | if (!intel_crtc->config.clock_set) { | |
6270 | intel_crtc->config.dpll.n = clock.n; | |
6271 | intel_crtc->config.dpll.m1 = clock.m1; | |
6272 | intel_crtc->config.dpll.m2 = clock.m2; | |
6273 | intel_crtc->config.dpll.p1 = clock.p1; | |
6274 | intel_crtc->config.dpll.p2 = clock.p2; | |
6275 | } | |
79e53945 | 6276 | |
5dc5298b | 6277 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 6278 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 6279 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 6280 | if (has_reduced_clock) |
7429e9d4 | 6281 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 6282 | |
7429e9d4 | 6283 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
6284 | &fp, &reduced_clock, |
6285 | has_reduced_clock ? &fp2 : NULL); | |
6286 | ||
959e16d6 | 6287 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
6288 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
6289 | if (has_reduced_clock) | |
6290 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
6291 | else | |
6292 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
6293 | ||
b89a1d39 | 6294 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 6295 | if (pll == NULL) { |
84f44ce7 VS |
6296 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
6297 | pipe_name(pipe)); | |
4b645f14 JB |
6298 | return -EINVAL; |
6299 | } | |
ee7b9f93 | 6300 | } else |
e72f9fbf | 6301 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 6302 | |
03afc4a2 DV |
6303 | if (intel_crtc->config.has_dp_encoder) |
6304 | intel_dp_set_m_n(intel_crtc); | |
79e53945 | 6305 | |
bcd644e0 DV |
6306 | if (is_lvds && has_reduced_clock && i915_powersave) |
6307 | intel_crtc->lowfreq_avail = true; | |
6308 | else | |
6309 | intel_crtc->lowfreq_avail = false; | |
e2b78267 | 6310 | |
8a654f3b | 6311 | intel_set_pipe_timings(intel_crtc); |
5eddb70b | 6312 | |
ca3a0ff8 | 6313 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6314 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6315 | &intel_crtc->config.fdi_m_n); | |
6316 | } | |
2c07245f | 6317 | |
6ff93609 | 6318 | ironlake_set_pipeconf(crtc); |
79e53945 | 6319 | |
a1f9e77e PZ |
6320 | /* Set up the display plane register */ |
6321 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
b24e7179 | 6322 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 6323 | |
94352cf9 | 6324 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7662c8bd | 6325 | |
1857e1da | 6326 | return ret; |
79e53945 JB |
6327 | } |
6328 | ||
eb14cb74 VS |
6329 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
6330 | struct intel_link_m_n *m_n) | |
6331 | { | |
6332 | struct drm_device *dev = crtc->base.dev; | |
6333 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6334 | enum pipe pipe = crtc->pipe; | |
6335 | ||
6336 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
6337 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
6338 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6339 | & ~TU_SIZE_MASK; | |
6340 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
6341 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
6342 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6343 | } | |
6344 | ||
6345 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
6346 | enum transcoder transcoder, | |
6347 | struct intel_link_m_n *m_n) | |
72419203 DV |
6348 | { |
6349 | struct drm_device *dev = crtc->base.dev; | |
6350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 6351 | enum pipe pipe = crtc->pipe; |
72419203 | 6352 | |
eb14cb74 VS |
6353 | if (INTEL_INFO(dev)->gen >= 5) { |
6354 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
6355 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
6356 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
6357 | & ~TU_SIZE_MASK; | |
6358 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
6359 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
6360 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6361 | } else { | |
6362 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
6363 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
6364 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
6365 | & ~TU_SIZE_MASK; | |
6366 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
6367 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
6368 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
6369 | } | |
6370 | } | |
6371 | ||
6372 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
6373 | struct intel_crtc_config *pipe_config) | |
6374 | { | |
6375 | if (crtc->config.has_pch_encoder) | |
6376 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
6377 | else | |
6378 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
6379 | &pipe_config->dp_m_n); | |
6380 | } | |
72419203 | 6381 | |
eb14cb74 VS |
6382 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
6383 | struct intel_crtc_config *pipe_config) | |
6384 | { | |
6385 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
6386 | &pipe_config->fdi_m_n); | |
72419203 DV |
6387 | } |
6388 | ||
2fa2fe9a DV |
6389 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
6390 | struct intel_crtc_config *pipe_config) | |
6391 | { | |
6392 | struct drm_device *dev = crtc->base.dev; | |
6393 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6394 | uint32_t tmp; | |
6395 | ||
6396 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
6397 | ||
6398 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 6399 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
6400 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
6401 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
6402 | |
6403 | /* We currently do not free assignements of panel fitters on | |
6404 | * ivb/hsw (since we don't use the higher upscaling modes which | |
6405 | * differentiates them) so just WARN about this case for now. */ | |
6406 | if (IS_GEN7(dev)) { | |
6407 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
6408 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
6409 | } | |
2fa2fe9a | 6410 | } |
79e53945 JB |
6411 | } |
6412 | ||
0e8ffe1b DV |
6413 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
6414 | struct intel_crtc_config *pipe_config) | |
6415 | { | |
6416 | struct drm_device *dev = crtc->base.dev; | |
6417 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6418 | uint32_t tmp; | |
6419 | ||
e143a21c | 6420 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6421 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6422 | |
0e8ffe1b DV |
6423 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6424 | if (!(tmp & PIPECONF_ENABLE)) | |
6425 | return false; | |
6426 | ||
42571aef VS |
6427 | switch (tmp & PIPECONF_BPC_MASK) { |
6428 | case PIPECONF_6BPC: | |
6429 | pipe_config->pipe_bpp = 18; | |
6430 | break; | |
6431 | case PIPECONF_8BPC: | |
6432 | pipe_config->pipe_bpp = 24; | |
6433 | break; | |
6434 | case PIPECONF_10BPC: | |
6435 | pipe_config->pipe_bpp = 30; | |
6436 | break; | |
6437 | case PIPECONF_12BPC: | |
6438 | pipe_config->pipe_bpp = 36; | |
6439 | break; | |
6440 | default: | |
6441 | break; | |
6442 | } | |
6443 | ||
ab9412ba | 6444 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
6445 | struct intel_shared_dpll *pll; |
6446 | ||
88adfff1 DV |
6447 | pipe_config->has_pch_encoder = true; |
6448 | ||
627eb5a3 DV |
6449 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
6450 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
6451 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
6452 | |
6453 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 6454 | |
c0d43d62 | 6455 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
6456 | pipe_config->shared_dpll = |
6457 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
6458 | } else { |
6459 | tmp = I915_READ(PCH_DPLL_SEL); | |
6460 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
6461 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
6462 | else | |
6463 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
6464 | } | |
66e985c0 DV |
6465 | |
6466 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
6467 | ||
6468 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
6469 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
6470 | |
6471 | tmp = pipe_config->dpll_hw_state.dpll; | |
6472 | pipe_config->pixel_multiplier = | |
6473 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
6474 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
6475 | |
6476 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
6477 | } else { |
6478 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
6479 | } |
6480 | ||
1bd1bd80 DV |
6481 | intel_get_pipe_timings(crtc, pipe_config); |
6482 | ||
2fa2fe9a DV |
6483 | ironlake_get_pfit_config(crtc, pipe_config); |
6484 | ||
0e8ffe1b DV |
6485 | return true; |
6486 | } | |
6487 | ||
be256dc7 PZ |
6488 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
6489 | { | |
6490 | struct drm_device *dev = dev_priv->dev; | |
6491 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
6492 | struct intel_crtc *crtc; | |
6493 | unsigned long irqflags; | |
bd633a7c | 6494 | uint32_t val; |
be256dc7 PZ |
6495 | |
6496 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
798183c5 | 6497 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
6498 | pipe_name(crtc->pipe)); |
6499 | ||
6500 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
6501 | WARN(plls->spll_refcount, "SPLL enabled\n"); | |
6502 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); | |
6503 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); | |
6504 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
6505 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
6506 | "CPU PWM1 enabled\n"); | |
6507 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
6508 | "CPU PWM2 enabled\n"); | |
6509 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, | |
6510 | "PCH PWM1 enabled\n"); | |
6511 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
6512 | "Utility pin enabled\n"); | |
6513 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
6514 | ||
6515 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
6516 | val = I915_READ(DEIMR); | |
6806e63f | 6517 | WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff, |
be256dc7 PZ |
6518 | "Unexpected DEIMR bits enabled: 0x%x\n", val); |
6519 | val = I915_READ(SDEIMR); | |
bd633a7c | 6520 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
be256dc7 PZ |
6521 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
6522 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
6523 | } | |
6524 | ||
6525 | /* | |
6526 | * This function implements pieces of two sequences from BSpec: | |
6527 | * - Sequence for display software to disable LCPLL | |
6528 | * - Sequence for display software to allow package C8+ | |
6529 | * The steps implemented here are just the steps that actually touch the LCPLL | |
6530 | * register. Callers should take care of disabling all the display engine | |
6531 | * functions, doing the mode unset, fixing interrupts, etc. | |
6532 | */ | |
6ff58d53 PZ |
6533 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
6534 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
6535 | { |
6536 | uint32_t val; | |
6537 | ||
6538 | assert_can_disable_lcpll(dev_priv); | |
6539 | ||
6540 | val = I915_READ(LCPLL_CTL); | |
6541 | ||
6542 | if (switch_to_fclk) { | |
6543 | val |= LCPLL_CD_SOURCE_FCLK; | |
6544 | I915_WRITE(LCPLL_CTL, val); | |
6545 | ||
6546 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
6547 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
6548 | DRM_ERROR("Switching to FCLK failed\n"); | |
6549 | ||
6550 | val = I915_READ(LCPLL_CTL); | |
6551 | } | |
6552 | ||
6553 | val |= LCPLL_PLL_DISABLE; | |
6554 | I915_WRITE(LCPLL_CTL, val); | |
6555 | POSTING_READ(LCPLL_CTL); | |
6556 | ||
6557 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
6558 | DRM_ERROR("LCPLL still locked\n"); | |
6559 | ||
6560 | val = I915_READ(D_COMP); | |
6561 | val |= D_COMP_COMP_DISABLE; | |
515b2392 PZ |
6562 | mutex_lock(&dev_priv->rps.hw_lock); |
6563 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | |
6564 | DRM_ERROR("Failed to disable D_COMP\n"); | |
6565 | mutex_unlock(&dev_priv->rps.hw_lock); | |
be256dc7 PZ |
6566 | POSTING_READ(D_COMP); |
6567 | ndelay(100); | |
6568 | ||
6569 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) | |
6570 | DRM_ERROR("D_COMP RCOMP still in progress\n"); | |
6571 | ||
6572 | if (allow_power_down) { | |
6573 | val = I915_READ(LCPLL_CTL); | |
6574 | val |= LCPLL_POWER_DOWN_ALLOW; | |
6575 | I915_WRITE(LCPLL_CTL, val); | |
6576 | POSTING_READ(LCPLL_CTL); | |
6577 | } | |
6578 | } | |
6579 | ||
6580 | /* | |
6581 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
6582 | * source. | |
6583 | */ | |
6ff58d53 | 6584 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
6585 | { |
6586 | uint32_t val; | |
6587 | ||
6588 | val = I915_READ(LCPLL_CTL); | |
6589 | ||
6590 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
6591 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
6592 | return; | |
6593 | ||
215733fa PZ |
6594 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6595 | * we'll hang the machine! */ | |
c8d9a590 | 6596 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 6597 | |
be256dc7 PZ |
6598 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6599 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
6600 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 6601 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
6602 | } |
6603 | ||
6604 | val = I915_READ(D_COMP); | |
6605 | val |= D_COMP_COMP_FORCE; | |
6606 | val &= ~D_COMP_COMP_DISABLE; | |
515b2392 PZ |
6607 | mutex_lock(&dev_priv->rps.hw_lock); |
6608 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | |
6609 | DRM_ERROR("Failed to enable D_COMP\n"); | |
6610 | mutex_unlock(&dev_priv->rps.hw_lock); | |
35d8f2eb | 6611 | POSTING_READ(D_COMP); |
be256dc7 PZ |
6612 | |
6613 | val = I915_READ(LCPLL_CTL); | |
6614 | val &= ~LCPLL_PLL_DISABLE; | |
6615 | I915_WRITE(LCPLL_CTL, val); | |
6616 | ||
6617 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
6618 | DRM_ERROR("LCPLL not locked yet\n"); | |
6619 | ||
6620 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
6621 | val = I915_READ(LCPLL_CTL); | |
6622 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
6623 | I915_WRITE(LCPLL_CTL, val); | |
6624 | ||
6625 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
6626 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
6627 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
6628 | } | |
215733fa | 6629 | |
c8d9a590 | 6630 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); |
be256dc7 PZ |
6631 | } |
6632 | ||
c67a470b PZ |
6633 | void hsw_enable_pc8_work(struct work_struct *__work) |
6634 | { | |
6635 | struct drm_i915_private *dev_priv = | |
6636 | container_of(to_delayed_work(__work), struct drm_i915_private, | |
6637 | pc8.enable_work); | |
6638 | struct drm_device *dev = dev_priv->dev; | |
6639 | uint32_t val; | |
6640 | ||
7125ecb8 PZ |
6641 | WARN_ON(!HAS_PC8(dev)); |
6642 | ||
c67a470b PZ |
6643 | if (dev_priv->pc8.enabled) |
6644 | return; | |
6645 | ||
6646 | DRM_DEBUG_KMS("Enabling package C8+\n"); | |
6647 | ||
6648 | dev_priv->pc8.enabled = true; | |
6649 | ||
6650 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6651 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6652 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
6653 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6654 | } | |
6655 | ||
6656 | lpt_disable_clkout_dp(dev); | |
6657 | hsw_pc8_disable_interrupts(dev); | |
6658 | hsw_disable_lcpll(dev_priv, true, true); | |
8771a7f8 PZ |
6659 | |
6660 | intel_runtime_pm_put(dev_priv); | |
c67a470b PZ |
6661 | } |
6662 | ||
6663 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6664 | { | |
6665 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6666 | WARN(dev_priv->pc8.disable_count < 1, | |
6667 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6668 | ||
6669 | dev_priv->pc8.disable_count--; | |
6670 | if (dev_priv->pc8.disable_count != 0) | |
6671 | return; | |
6672 | ||
6673 | schedule_delayed_work(&dev_priv->pc8.enable_work, | |
90058745 | 6674 | msecs_to_jiffies(i915_pc8_timeout)); |
c67a470b PZ |
6675 | } |
6676 | ||
6677 | static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
6678 | { | |
6679 | struct drm_device *dev = dev_priv->dev; | |
6680 | uint32_t val; | |
6681 | ||
6682 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6683 | WARN(dev_priv->pc8.disable_count < 0, | |
6684 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6685 | ||
6686 | dev_priv->pc8.disable_count++; | |
6687 | if (dev_priv->pc8.disable_count != 1) | |
6688 | return; | |
6689 | ||
7125ecb8 PZ |
6690 | WARN_ON(!HAS_PC8(dev)); |
6691 | ||
c67a470b PZ |
6692 | cancel_delayed_work_sync(&dev_priv->pc8.enable_work); |
6693 | if (!dev_priv->pc8.enabled) | |
6694 | return; | |
6695 | ||
6696 | DRM_DEBUG_KMS("Disabling package C8+\n"); | |
6697 | ||
8771a7f8 PZ |
6698 | intel_runtime_pm_get(dev_priv); |
6699 | ||
c67a470b PZ |
6700 | hsw_restore_lcpll(dev_priv); |
6701 | hsw_pc8_restore_interrupts(dev); | |
6702 | lpt_init_pch_refclk(dev); | |
6703 | ||
6704 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6705 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6706 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
6707 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6708 | } | |
6709 | ||
6710 | intel_prepare_ddi(dev); | |
6711 | i915_gem_init_swizzling(dev); | |
6712 | mutex_lock(&dev_priv->rps.hw_lock); | |
6713 | gen6_update_ring_freq(dev); | |
6714 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6715 | dev_priv->pc8.enabled = false; | |
6716 | } | |
6717 | ||
6718 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6719 | { | |
7c6c2652 CW |
6720 | if (!HAS_PC8(dev_priv->dev)) |
6721 | return; | |
6722 | ||
c67a470b PZ |
6723 | mutex_lock(&dev_priv->pc8.lock); |
6724 | __hsw_enable_package_c8(dev_priv); | |
6725 | mutex_unlock(&dev_priv->pc8.lock); | |
6726 | } | |
6727 | ||
6728 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
6729 | { | |
7c6c2652 CW |
6730 | if (!HAS_PC8(dev_priv->dev)) |
6731 | return; | |
6732 | ||
c67a470b PZ |
6733 | mutex_lock(&dev_priv->pc8.lock); |
6734 | __hsw_disable_package_c8(dev_priv); | |
6735 | mutex_unlock(&dev_priv->pc8.lock); | |
6736 | } | |
6737 | ||
6738 | static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv) | |
6739 | { | |
6740 | struct drm_device *dev = dev_priv->dev; | |
6741 | struct intel_crtc *crtc; | |
6742 | uint32_t val; | |
6743 | ||
6744 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
6745 | if (crtc->base.enabled) | |
6746 | return false; | |
6747 | ||
6748 | /* This case is still possible since we have the i915.disable_power_well | |
6749 | * parameter and also the KVMr or something else might be requesting the | |
6750 | * power well. */ | |
6751 | val = I915_READ(HSW_PWR_WELL_DRIVER); | |
6752 | if (val != 0) { | |
6753 | DRM_DEBUG_KMS("Not enabling PC8: power well on\n"); | |
6754 | return false; | |
6755 | } | |
6756 | ||
6757 | return true; | |
6758 | } | |
6759 | ||
6760 | /* Since we're called from modeset_global_resources there's no way to | |
6761 | * symmetrically increase and decrease the refcount, so we use | |
6762 | * dev_priv->pc8.requirements_met to track whether we already have the refcount | |
6763 | * or not. | |
6764 | */ | |
6765 | static void hsw_update_package_c8(struct drm_device *dev) | |
6766 | { | |
6767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6768 | bool allow; | |
6769 | ||
7c6c2652 CW |
6770 | if (!HAS_PC8(dev_priv->dev)) |
6771 | return; | |
6772 | ||
c67a470b PZ |
6773 | if (!i915_enable_pc8) |
6774 | return; | |
6775 | ||
6776 | mutex_lock(&dev_priv->pc8.lock); | |
6777 | ||
6778 | allow = hsw_can_enable_package_c8(dev_priv); | |
6779 | ||
6780 | if (allow == dev_priv->pc8.requirements_met) | |
6781 | goto done; | |
6782 | ||
6783 | dev_priv->pc8.requirements_met = allow; | |
6784 | ||
6785 | if (allow) | |
6786 | __hsw_enable_package_c8(dev_priv); | |
6787 | else | |
6788 | __hsw_disable_package_c8(dev_priv); | |
6789 | ||
6790 | done: | |
6791 | mutex_unlock(&dev_priv->pc8.lock); | |
6792 | } | |
6793 | ||
6794 | static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv) | |
6795 | { | |
7c6c2652 CW |
6796 | if (!HAS_PC8(dev_priv->dev)) |
6797 | return; | |
6798 | ||
3458122e | 6799 | mutex_lock(&dev_priv->pc8.lock); |
c67a470b PZ |
6800 | if (!dev_priv->pc8.gpu_idle) { |
6801 | dev_priv->pc8.gpu_idle = true; | |
3458122e | 6802 | __hsw_enable_package_c8(dev_priv); |
c67a470b | 6803 | } |
3458122e | 6804 | mutex_unlock(&dev_priv->pc8.lock); |
c67a470b PZ |
6805 | } |
6806 | ||
6807 | static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) | |
6808 | { | |
7c6c2652 CW |
6809 | if (!HAS_PC8(dev_priv->dev)) |
6810 | return; | |
6811 | ||
3458122e | 6812 | mutex_lock(&dev_priv->pc8.lock); |
c67a470b PZ |
6813 | if (dev_priv->pc8.gpu_idle) { |
6814 | dev_priv->pc8.gpu_idle = false; | |
3458122e | 6815 | __hsw_disable_package_c8(dev_priv); |
c67a470b | 6816 | } |
3458122e | 6817 | mutex_unlock(&dev_priv->pc8.lock); |
be256dc7 PZ |
6818 | } |
6819 | ||
6efdf354 ID |
6820 | #define for_each_power_domain(domain, mask) \ |
6821 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
6822 | if ((1 << (domain)) & (mask)) | |
6823 | ||
6824 | static unsigned long get_pipe_power_domains(struct drm_device *dev, | |
6825 | enum pipe pipe, bool pfit_enabled) | |
6826 | { | |
6827 | unsigned long mask; | |
6828 | enum transcoder transcoder; | |
6829 | ||
6830 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
6831 | ||
6832 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
6833 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6834 | if (pfit_enabled) | |
6835 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); | |
6836 | ||
6837 | return mask; | |
6838 | } | |
6839 | ||
baa70707 ID |
6840 | void intel_display_set_init_power(struct drm_device *dev, bool enable) |
6841 | { | |
6842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6843 | ||
6844 | if (dev_priv->power_domains.init_power_on == enable) | |
6845 | return; | |
6846 | ||
6847 | if (enable) | |
6848 | intel_display_power_get(dev, POWER_DOMAIN_INIT); | |
6849 | else | |
6850 | intel_display_power_put(dev, POWER_DOMAIN_INIT); | |
6851 | ||
6852 | dev_priv->power_domains.init_power_on = enable; | |
6853 | } | |
6854 | ||
4f074129 | 6855 | static void modeset_update_power_wells(struct drm_device *dev) |
d6dd9eb1 | 6856 | { |
6efdf354 | 6857 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; |
d6dd9eb1 | 6858 | struct intel_crtc *crtc; |
d6dd9eb1 | 6859 | |
6efdf354 ID |
6860 | /* |
6861 | * First get all needed power domains, then put all unneeded, to avoid | |
6862 | * any unnecessary toggling of the power wells. | |
6863 | */ | |
d6dd9eb1 | 6864 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
6efdf354 ID |
6865 | enum intel_display_power_domain domain; |
6866 | ||
e7a639c4 DV |
6867 | if (!crtc->base.enabled) |
6868 | continue; | |
d6dd9eb1 | 6869 | |
6efdf354 ID |
6870 | pipe_domains[crtc->pipe] = get_pipe_power_domains(dev, |
6871 | crtc->pipe, | |
6872 | crtc->config.pch_pfit.enabled); | |
6873 | ||
6874 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
6875 | intel_display_power_get(dev, domain); | |
d6dd9eb1 DV |
6876 | } |
6877 | ||
6efdf354 ID |
6878 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { |
6879 | enum intel_display_power_domain domain; | |
6880 | ||
6881 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
6882 | intel_display_power_put(dev, domain); | |
6883 | ||
6884 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
6885 | } | |
baa70707 ID |
6886 | |
6887 | intel_display_set_init_power(dev, false); | |
4f074129 | 6888 | } |
c67a470b | 6889 | |
4f074129 ID |
6890 | static void haswell_modeset_global_resources(struct drm_device *dev) |
6891 | { | |
6892 | modeset_update_power_wells(dev); | |
c67a470b | 6893 | hsw_update_package_c8(dev); |
d6dd9eb1 DV |
6894 | } |
6895 | ||
09b4ddf9 | 6896 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
6897 | int x, int y, |
6898 | struct drm_framebuffer *fb) | |
6899 | { | |
6900 | struct drm_device *dev = crtc->dev; | |
6901 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6902 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
09b4ddf9 | 6903 | int plane = intel_crtc->plane; |
09b4ddf9 | 6904 | int ret; |
09b4ddf9 | 6905 | |
ff9a6750 | 6906 | if (!intel_ddi_pll_mode_set(crtc)) |
6441ab5f PZ |
6907 | return -EINVAL; |
6908 | ||
03afc4a2 DV |
6909 | if (intel_crtc->config.has_dp_encoder) |
6910 | intel_dp_set_m_n(intel_crtc); | |
09b4ddf9 PZ |
6911 | |
6912 | intel_crtc->lowfreq_avail = false; | |
09b4ddf9 | 6913 | |
8a654f3b | 6914 | intel_set_pipe_timings(intel_crtc); |
09b4ddf9 | 6915 | |
ca3a0ff8 | 6916 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6917 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6918 | &intel_crtc->config.fdi_m_n); | |
6919 | } | |
09b4ddf9 | 6920 | |
6ff93609 | 6921 | haswell_set_pipeconf(crtc); |
09b4ddf9 | 6922 | |
50f3b016 | 6923 | intel_set_pipe_csc(crtc); |
86d3efce | 6924 | |
09b4ddf9 | 6925 | /* Set up the display plane register */ |
86d3efce | 6926 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
09b4ddf9 PZ |
6927 | POSTING_READ(DSPCNTR(plane)); |
6928 | ||
6929 | ret = intel_pipe_set_base(crtc, x, y, fb); | |
6930 | ||
1f803ee5 | 6931 | return ret; |
79e53945 JB |
6932 | } |
6933 | ||
0e8ffe1b DV |
6934 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
6935 | struct intel_crtc_config *pipe_config) | |
6936 | { | |
6937 | struct drm_device *dev = crtc->base.dev; | |
6938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 6939 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
6940 | uint32_t tmp; |
6941 | ||
e143a21c | 6942 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
6943 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
6944 | ||
eccb140b DV |
6945 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
6946 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
6947 | enum pipe trans_edp_pipe; | |
6948 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
6949 | default: | |
6950 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
6951 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
6952 | case TRANS_DDI_EDP_INPUT_A_ON: | |
6953 | trans_edp_pipe = PIPE_A; | |
6954 | break; | |
6955 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
6956 | trans_edp_pipe = PIPE_B; | |
6957 | break; | |
6958 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
6959 | trans_edp_pipe = PIPE_C; | |
6960 | break; | |
6961 | } | |
6962 | ||
6963 | if (trans_edp_pipe == crtc->pipe) | |
6964 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
6965 | } | |
6966 | ||
b97186f0 | 6967 | if (!intel_display_power_enabled(dev, |
eccb140b | 6968 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
6969 | return false; |
6970 | ||
eccb140b | 6971 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
6972 | if (!(tmp & PIPECONF_ENABLE)) |
6973 | return false; | |
6974 | ||
88adfff1 | 6975 | /* |
f196e6be | 6976 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
88adfff1 DV |
6977 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
6978 | * the PCH transcoder is on. | |
6979 | */ | |
eccb140b | 6980 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
88adfff1 | 6981 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
ab9412ba | 6982 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
88adfff1 DV |
6983 | pipe_config->has_pch_encoder = true; |
6984 | ||
627eb5a3 DV |
6985 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
6986 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
6987 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
6988 | |
6989 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
627eb5a3 DV |
6990 | } |
6991 | ||
1bd1bd80 DV |
6992 | intel_get_pipe_timings(crtc, pipe_config); |
6993 | ||
2fa2fe9a DV |
6994 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
6995 | if (intel_display_power_enabled(dev, pfit_domain)) | |
6996 | ironlake_get_pfit_config(crtc, pipe_config); | |
88adfff1 | 6997 | |
42db64ef PZ |
6998 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
6999 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
7000 | ||
6c49f241 DV |
7001 | pipe_config->pixel_multiplier = 1; |
7002 | ||
0e8ffe1b DV |
7003 | return true; |
7004 | } | |
7005 | ||
f564048e | 7006 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 7007 | int x, int y, |
94352cf9 | 7008 | struct drm_framebuffer *fb) |
f564048e EA |
7009 | { |
7010 | struct drm_device *dev = crtc->dev; | |
7011 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9256aa19 | 7012 | struct intel_encoder *encoder; |
0b701d27 | 7013 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b8cecdf5 | 7014 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
0b701d27 | 7015 | int pipe = intel_crtc->pipe; |
f564048e EA |
7016 | int ret; |
7017 | ||
0b701d27 | 7018 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 7019 | |
b8cecdf5 DV |
7020 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
7021 | ||
79e53945 | 7022 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 7023 | |
9256aa19 DV |
7024 | if (ret != 0) |
7025 | return ret; | |
7026 | ||
7027 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
7028 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", | |
7029 | encoder->base.base.id, | |
7030 | drm_get_encoder_name(&encoder->base), | |
7031 | mode->base.id, mode->name); | |
36f2d1f1 | 7032 | encoder->mode_set(encoder); |
9256aa19 DV |
7033 | } |
7034 | ||
7035 | return 0; | |
79e53945 JB |
7036 | } |
7037 | ||
1a91510d JN |
7038 | static struct { |
7039 | int clock; | |
7040 | u32 config; | |
7041 | } hdmi_audio_clock[] = { | |
7042 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
7043 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
7044 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
7045 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
7046 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
7047 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
7048 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7049 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
7050 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
7051 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
7052 | }; | |
7053 | ||
7054 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
7055 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) | |
7056 | { | |
7057 | int i; | |
7058 | ||
7059 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
7060 | if (mode->clock == hdmi_audio_clock[i].clock) | |
7061 | break; | |
7062 | } | |
7063 | ||
7064 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
7065 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); | |
7066 | i = 1; | |
7067 | } | |
7068 | ||
7069 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
7070 | hdmi_audio_clock[i].clock, | |
7071 | hdmi_audio_clock[i].config); | |
7072 | ||
7073 | return hdmi_audio_clock[i].config; | |
7074 | } | |
7075 | ||
3a9627f4 WF |
7076 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7077 | int reg_eldv, uint32_t bits_eldv, | |
7078 | int reg_elda, uint32_t bits_elda, | |
7079 | int reg_edid) | |
7080 | { | |
7081 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7082 | uint8_t *eld = connector->eld; | |
7083 | uint32_t i; | |
7084 | ||
7085 | i = I915_READ(reg_eldv); | |
7086 | i &= bits_eldv; | |
7087 | ||
7088 | if (!eld[0]) | |
7089 | return !i; | |
7090 | ||
7091 | if (!i) | |
7092 | return false; | |
7093 | ||
7094 | i = I915_READ(reg_elda); | |
7095 | i &= ~bits_elda; | |
7096 | I915_WRITE(reg_elda, i); | |
7097 | ||
7098 | for (i = 0; i < eld[2]; i++) | |
7099 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
7100 | return false; | |
7101 | ||
7102 | return true; | |
7103 | } | |
7104 | ||
e0dac65e | 7105 | static void g4x_write_eld(struct drm_connector *connector, |
34427052 JN |
7106 | struct drm_crtc *crtc, |
7107 | struct drm_display_mode *mode) | |
e0dac65e WF |
7108 | { |
7109 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7110 | uint8_t *eld = connector->eld; | |
7111 | uint32_t eldv; | |
7112 | uint32_t len; | |
7113 | uint32_t i; | |
7114 | ||
7115 | i = I915_READ(G4X_AUD_VID_DID); | |
7116 | ||
7117 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
7118 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
7119 | else | |
7120 | eldv = G4X_ELDV_DEVCTG; | |
7121 | ||
3a9627f4 WF |
7122 | if (intel_eld_uptodate(connector, |
7123 | G4X_AUD_CNTL_ST, eldv, | |
7124 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
7125 | G4X_HDMIW_HDMIEDID)) | |
7126 | return; | |
7127 | ||
e0dac65e WF |
7128 | i = I915_READ(G4X_AUD_CNTL_ST); |
7129 | i &= ~(eldv | G4X_ELD_ADDR); | |
7130 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
7131 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7132 | ||
7133 | if (!eld[0]) | |
7134 | return; | |
7135 | ||
7136 | len = min_t(uint8_t, eld[2], len); | |
7137 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7138 | for (i = 0; i < len; i++) | |
7139 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
7140 | ||
7141 | i = I915_READ(G4X_AUD_CNTL_ST); | |
7142 | i |= eldv; | |
7143 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
7144 | } | |
7145 | ||
83358c85 | 7146 | static void haswell_write_eld(struct drm_connector *connector, |
34427052 JN |
7147 | struct drm_crtc *crtc, |
7148 | struct drm_display_mode *mode) | |
83358c85 WX |
7149 | { |
7150 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7151 | uint8_t *eld = connector->eld; | |
7152 | struct drm_device *dev = crtc->dev; | |
7b9f35a6 | 7153 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83358c85 WX |
7154 | uint32_t eldv; |
7155 | uint32_t i; | |
7156 | int len; | |
7157 | int pipe = to_intel_crtc(crtc)->pipe; | |
7158 | int tmp; | |
7159 | ||
7160 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
7161 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
7162 | int aud_config = HSW_AUD_CFG(pipe); | |
7163 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
7164 | ||
7165 | ||
7166 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); | |
7167 | ||
7168 | /* Audio output enable */ | |
7169 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
7170 | tmp = I915_READ(aud_cntrl_st2); | |
7171 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
7172 | I915_WRITE(aud_cntrl_st2, tmp); | |
7173 | ||
7174 | /* Wait for 1 vertical blank */ | |
7175 | intel_wait_for_vblank(dev, pipe); | |
7176 | ||
7177 | /* Set ELD valid state */ | |
7178 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7179 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7180 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
7181 | I915_WRITE(aud_cntrl_st2, tmp); | |
7182 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 7183 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
7184 | |
7185 | /* Enable HDMI mode */ | |
7186 | tmp = I915_READ(aud_config); | |
7e7cb34f | 7187 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
7188 | /* clear N_programing_enable and N_value_index */ |
7189 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
7190 | I915_WRITE(aud_config, tmp); | |
7191 | ||
7192 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
7193 | ||
7194 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7b9f35a6 | 7195 | intel_crtc->eld_vld = true; |
83358c85 WX |
7196 | |
7197 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
7198 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7199 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
7200 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
1a91510d JN |
7201 | } else { |
7202 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7203 | } | |
83358c85 WX |
7204 | |
7205 | if (intel_eld_uptodate(connector, | |
7206 | aud_cntrl_st2, eldv, | |
7207 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7208 | hdmiw_hdmiedid)) | |
7209 | return; | |
7210 | ||
7211 | i = I915_READ(aud_cntrl_st2); | |
7212 | i &= ~eldv; | |
7213 | I915_WRITE(aud_cntrl_st2, i); | |
7214 | ||
7215 | if (!eld[0]) | |
7216 | return; | |
7217 | ||
7218 | i = I915_READ(aud_cntl_st); | |
7219 | i &= ~IBX_ELD_ADDRESS; | |
7220 | I915_WRITE(aud_cntl_st, i); | |
7221 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
7222 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
7223 | ||
7224 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7225 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7226 | for (i = 0; i < len; i++) | |
7227 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7228 | ||
7229 | i = I915_READ(aud_cntrl_st2); | |
7230 | i |= eldv; | |
7231 | I915_WRITE(aud_cntrl_st2, i); | |
7232 | ||
7233 | } | |
7234 | ||
e0dac65e | 7235 | static void ironlake_write_eld(struct drm_connector *connector, |
34427052 JN |
7236 | struct drm_crtc *crtc, |
7237 | struct drm_display_mode *mode) | |
e0dac65e WF |
7238 | { |
7239 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7240 | uint8_t *eld = connector->eld; | |
7241 | uint32_t eldv; | |
7242 | uint32_t i; | |
7243 | int len; | |
7244 | int hdmiw_hdmiedid; | |
b6daa025 | 7245 | int aud_config; |
e0dac65e WF |
7246 | int aud_cntl_st; |
7247 | int aud_cntrl_st2; | |
9b138a83 | 7248 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 7249 | |
b3f33cbf | 7250 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
7251 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
7252 | aud_config = IBX_AUD_CFG(pipe); | |
7253 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7254 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
9ca2fe73 ML |
7255 | } else if (IS_VALLEYVIEW(connector->dev)) { |
7256 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
7257 | aud_config = VLV_AUD_CFG(pipe); | |
7258 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
7259 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
e0dac65e | 7260 | } else { |
9b138a83 WX |
7261 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
7262 | aud_config = CPT_AUD_CFG(pipe); | |
7263 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 7264 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
7265 | } |
7266 | ||
9b138a83 | 7267 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e | 7268 | |
9ca2fe73 ML |
7269 | if (IS_VALLEYVIEW(connector->dev)) { |
7270 | struct intel_encoder *intel_encoder; | |
7271 | struct intel_digital_port *intel_dig_port; | |
7272 | ||
7273 | intel_encoder = intel_attached_encoder(connector); | |
7274 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
7275 | i = intel_dig_port->port; | |
7276 | } else { | |
7277 | i = I915_READ(aud_cntl_st); | |
7278 | i = (i >> 29) & DIP_PORT_SEL_MASK; | |
7279 | /* DIP_Port_Select, 0x1 = PortB */ | |
7280 | } | |
7281 | ||
e0dac65e WF |
7282 | if (!i) { |
7283 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
7284 | /* operate blindly on all ports */ | |
1202b4c6 WF |
7285 | eldv = IBX_ELD_VALIDB; |
7286 | eldv |= IBX_ELD_VALIDB << 4; | |
7287 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 7288 | } else { |
2582a850 | 7289 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 7290 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
7291 | } |
7292 | ||
3a9627f4 WF |
7293 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
7294 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
7295 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 | 7296 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
1a91510d JN |
7297 | } else { |
7298 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
7299 | } | |
e0dac65e | 7300 | |
3a9627f4 WF |
7301 | if (intel_eld_uptodate(connector, |
7302 | aud_cntrl_st2, eldv, | |
7303 | aud_cntl_st, IBX_ELD_ADDRESS, | |
7304 | hdmiw_hdmiedid)) | |
7305 | return; | |
7306 | ||
e0dac65e WF |
7307 | i = I915_READ(aud_cntrl_st2); |
7308 | i &= ~eldv; | |
7309 | I915_WRITE(aud_cntrl_st2, i); | |
7310 | ||
7311 | if (!eld[0]) | |
7312 | return; | |
7313 | ||
e0dac65e | 7314 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 7315 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
7316 | I915_WRITE(aud_cntl_st, i); |
7317 | ||
7318 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
7319 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
7320 | for (i = 0; i < len; i++) | |
7321 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
7322 | ||
7323 | i = I915_READ(aud_cntrl_st2); | |
7324 | i |= eldv; | |
7325 | I915_WRITE(aud_cntrl_st2, i); | |
7326 | } | |
7327 | ||
7328 | void intel_write_eld(struct drm_encoder *encoder, | |
7329 | struct drm_display_mode *mode) | |
7330 | { | |
7331 | struct drm_crtc *crtc = encoder->crtc; | |
7332 | struct drm_connector *connector; | |
7333 | struct drm_device *dev = encoder->dev; | |
7334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7335 | ||
7336 | connector = drm_select_eld(encoder, mode); | |
7337 | if (!connector) | |
7338 | return; | |
7339 | ||
7340 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
7341 | connector->base.id, | |
7342 | drm_get_connector_name(connector), | |
7343 | connector->encoder->base.id, | |
7344 | drm_get_encoder_name(connector->encoder)); | |
7345 | ||
7346 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
7347 | ||
7348 | if (dev_priv->display.write_eld) | |
34427052 | 7349 | dev_priv->display.write_eld(connector, crtc, mode); |
e0dac65e WF |
7350 | } |
7351 | ||
560b85bb CW |
7352 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
7353 | { | |
7354 | struct drm_device *dev = crtc->dev; | |
7355 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7356 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7357 | bool visible = base != 0; | |
7358 | u32 cntl; | |
7359 | ||
7360 | if (intel_crtc->cursor_visible == visible) | |
7361 | return; | |
7362 | ||
9db4a9c7 | 7363 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
7364 | if (visible) { |
7365 | /* On these chipsets we can only modify the base whilst | |
7366 | * the cursor is disabled. | |
7367 | */ | |
9db4a9c7 | 7368 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
7369 | |
7370 | cntl &= ~(CURSOR_FORMAT_MASK); | |
7371 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
7372 | cntl |= CURSOR_ENABLE | | |
7373 | CURSOR_GAMMA_ENABLE | | |
7374 | CURSOR_FORMAT_ARGB; | |
7375 | } else | |
7376 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 7377 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
7378 | |
7379 | intel_crtc->cursor_visible = visible; | |
7380 | } | |
7381 | ||
7382 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
7383 | { | |
7384 | struct drm_device *dev = crtc->dev; | |
7385 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7386 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7387 | int pipe = intel_crtc->pipe; | |
7388 | bool visible = base != 0; | |
7389 | ||
7390 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 7391 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
7392 | if (base) { |
7393 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
7394 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
7395 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
7396 | } else { | |
7397 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7398 | cntl |= CURSOR_MODE_DISABLE; | |
7399 | } | |
9db4a9c7 | 7400 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
7401 | |
7402 | intel_crtc->cursor_visible = visible; | |
7403 | } | |
7404 | /* and commit changes on next vblank */ | |
b2ea8ef5 | 7405 | POSTING_READ(CURCNTR(pipe)); |
9db4a9c7 | 7406 | I915_WRITE(CURBASE(pipe), base); |
b2ea8ef5 | 7407 | POSTING_READ(CURBASE(pipe)); |
560b85bb CW |
7408 | } |
7409 | ||
65a21cd6 JB |
7410 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
7411 | { | |
7412 | struct drm_device *dev = crtc->dev; | |
7413 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7414 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7415 | int pipe = intel_crtc->pipe; | |
7416 | bool visible = base != 0; | |
7417 | ||
7418 | if (intel_crtc->cursor_visible != visible) { | |
7419 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
7420 | if (base) { | |
7421 | cntl &= ~CURSOR_MODE; | |
7422 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
7423 | } else { | |
7424 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
7425 | cntl |= CURSOR_MODE_DISABLE; | |
7426 | } | |
6bbfa1c5 | 7427 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
86d3efce | 7428 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
1f5d76db PZ |
7429 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
7430 | } | |
65a21cd6 JB |
7431 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
7432 | ||
7433 | intel_crtc->cursor_visible = visible; | |
7434 | } | |
7435 | /* and commit changes on next vblank */ | |
b2ea8ef5 | 7436 | POSTING_READ(CURCNTR_IVB(pipe)); |
65a21cd6 | 7437 | I915_WRITE(CURBASE_IVB(pipe), base); |
b2ea8ef5 | 7438 | POSTING_READ(CURBASE_IVB(pipe)); |
65a21cd6 JB |
7439 | } |
7440 | ||
cda4b7d3 | 7441 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
7442 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
7443 | bool on) | |
cda4b7d3 CW |
7444 | { |
7445 | struct drm_device *dev = crtc->dev; | |
7446 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7447 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7448 | int pipe = intel_crtc->pipe; | |
7449 | int x = intel_crtc->cursor_x; | |
7450 | int y = intel_crtc->cursor_y; | |
d6e4db15 | 7451 | u32 base = 0, pos = 0; |
cda4b7d3 CW |
7452 | bool visible; |
7453 | ||
d6e4db15 | 7454 | if (on) |
cda4b7d3 | 7455 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 7456 | |
d6e4db15 VS |
7457 | if (x >= intel_crtc->config.pipe_src_w) |
7458 | base = 0; | |
7459 | ||
7460 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
7461 | base = 0; |
7462 | ||
7463 | if (x < 0) { | |
efc9064e | 7464 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
7465 | base = 0; |
7466 | ||
7467 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
7468 | x = -x; | |
7469 | } | |
7470 | pos |= x << CURSOR_X_SHIFT; | |
7471 | ||
7472 | if (y < 0) { | |
efc9064e | 7473 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
7474 | base = 0; |
7475 | ||
7476 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
7477 | y = -y; | |
7478 | } | |
7479 | pos |= y << CURSOR_Y_SHIFT; | |
7480 | ||
7481 | visible = base != 0; | |
560b85bb | 7482 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
7483 | return; |
7484 | ||
b3dc685e | 7485 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
65a21cd6 JB |
7486 | I915_WRITE(CURPOS_IVB(pipe), pos); |
7487 | ivb_update_cursor(crtc, base); | |
7488 | } else { | |
7489 | I915_WRITE(CURPOS(pipe), pos); | |
7490 | if (IS_845G(dev) || IS_I865G(dev)) | |
7491 | i845_update_cursor(crtc, base); | |
7492 | else | |
7493 | i9xx_update_cursor(crtc, base); | |
7494 | } | |
cda4b7d3 CW |
7495 | } |
7496 | ||
79e53945 | 7497 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 7498 | struct drm_file *file, |
79e53945 JB |
7499 | uint32_t handle, |
7500 | uint32_t width, uint32_t height) | |
7501 | { | |
7502 | struct drm_device *dev = crtc->dev; | |
7503 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7504 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 7505 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 7506 | uint32_t addr; |
3f8bc370 | 7507 | int ret; |
79e53945 | 7508 | |
79e53945 JB |
7509 | /* if we want to turn off the cursor ignore width and height */ |
7510 | if (!handle) { | |
28c97730 | 7511 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 7512 | addr = 0; |
05394f39 | 7513 | obj = NULL; |
5004417d | 7514 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 7515 | goto finish; |
79e53945 JB |
7516 | } |
7517 | ||
7518 | /* Currently we only support 64x64 cursors */ | |
7519 | if (width != 64 || height != 64) { | |
7520 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
7521 | return -EINVAL; | |
7522 | } | |
7523 | ||
05394f39 | 7524 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 7525 | if (&obj->base == NULL) |
79e53945 JB |
7526 | return -ENOENT; |
7527 | ||
05394f39 | 7528 | if (obj->base.size < width * height * 4) { |
79e53945 | 7529 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
7530 | ret = -ENOMEM; |
7531 | goto fail; | |
79e53945 JB |
7532 | } |
7533 | ||
71acb5eb | 7534 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 7535 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 7536 | if (!dev_priv->info->cursor_needs_physical) { |
693db184 CW |
7537 | unsigned alignment; |
7538 | ||
d9e86c0e CW |
7539 | if (obj->tiling_mode) { |
7540 | DRM_ERROR("cursor cannot be tiled\n"); | |
7541 | ret = -EINVAL; | |
7542 | goto fail_locked; | |
7543 | } | |
7544 | ||
693db184 CW |
7545 | /* Note that the w/a also requires 2 PTE of padding following |
7546 | * the bo. We currently fill all unused PTE with the shadow | |
7547 | * page and so we should always have valid PTE following the | |
7548 | * cursor preventing the VT-d warning. | |
7549 | */ | |
7550 | alignment = 0; | |
7551 | if (need_vtd_wa(dev)) | |
7552 | alignment = 64*1024; | |
7553 | ||
7554 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb CW |
7555 | if (ret) { |
7556 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 7557 | goto fail_locked; |
e7b526bb CW |
7558 | } |
7559 | ||
d9e86c0e CW |
7560 | ret = i915_gem_object_put_fence(obj); |
7561 | if (ret) { | |
2da3b9b9 | 7562 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
7563 | goto fail_unpin; |
7564 | } | |
7565 | ||
f343c5f6 | 7566 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 7567 | } else { |
6eeefaf3 | 7568 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 7569 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
7570 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
7571 | align); | |
71acb5eb DA |
7572 | if (ret) { |
7573 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 7574 | goto fail_locked; |
71acb5eb | 7575 | } |
05394f39 | 7576 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
7577 | } |
7578 | ||
a6c45cf0 | 7579 | if (IS_GEN2(dev)) |
14b60391 JB |
7580 | I915_WRITE(CURSIZE, (height << 12) | width); |
7581 | ||
3f8bc370 | 7582 | finish: |
3f8bc370 | 7583 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 7584 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 7585 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
7586 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
7587 | } else | |
cc98b413 | 7588 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
05394f39 | 7589 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 7590 | } |
80824003 | 7591 | |
7f9872e0 | 7592 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
7593 | |
7594 | intel_crtc->cursor_addr = addr; | |
05394f39 | 7595 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
7596 | intel_crtc->cursor_width = width; |
7597 | intel_crtc->cursor_height = height; | |
7598 | ||
f2f5f771 VS |
7599 | if (intel_crtc->active) |
7600 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
3f8bc370 | 7601 | |
79e53945 | 7602 | return 0; |
e7b526bb | 7603 | fail_unpin: |
cc98b413 | 7604 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 7605 | fail_locked: |
34b8686e | 7606 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 7607 | fail: |
05394f39 | 7608 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 7609 | return ret; |
79e53945 JB |
7610 | } |
7611 | ||
7612 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
7613 | { | |
79e53945 | 7614 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7615 | |
92e76c8c VS |
7616 | intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX); |
7617 | intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX); | |
652c393a | 7618 | |
f2f5f771 VS |
7619 | if (intel_crtc->active) |
7620 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
79e53945 JB |
7621 | |
7622 | return 0; | |
b8c00ac5 DA |
7623 | } |
7624 | ||
79e53945 | 7625 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 7626 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 7627 | { |
7203425a | 7628 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 7629 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7630 | |
7203425a | 7631 | for (i = start; i < end; i++) { |
79e53945 JB |
7632 | intel_crtc->lut_r[i] = red[i] >> 8; |
7633 | intel_crtc->lut_g[i] = green[i] >> 8; | |
7634 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
7635 | } | |
7636 | ||
7637 | intel_crtc_load_lut(crtc); | |
7638 | } | |
7639 | ||
79e53945 JB |
7640 | /* VESA 640x480x72Hz mode to set on the pipe */ |
7641 | static struct drm_display_mode load_detect_mode = { | |
7642 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
7643 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
7644 | }; | |
7645 | ||
d2dff872 CW |
7646 | static struct drm_framebuffer * |
7647 | intel_framebuffer_create(struct drm_device *dev, | |
308e5bcb | 7648 | struct drm_mode_fb_cmd2 *mode_cmd, |
d2dff872 CW |
7649 | struct drm_i915_gem_object *obj) |
7650 | { | |
7651 | struct intel_framebuffer *intel_fb; | |
7652 | int ret; | |
7653 | ||
7654 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
7655 | if (!intel_fb) { | |
7656 | drm_gem_object_unreference_unlocked(&obj->base); | |
7657 | return ERR_PTR(-ENOMEM); | |
7658 | } | |
7659 | ||
dd4916c5 DV |
7660 | ret = i915_mutex_lock_interruptible(dev); |
7661 | if (ret) | |
7662 | goto err; | |
7663 | ||
d2dff872 | 7664 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); |
dd4916c5 DV |
7665 | mutex_unlock(&dev->struct_mutex); |
7666 | if (ret) | |
7667 | goto err; | |
d2dff872 CW |
7668 | |
7669 | return &intel_fb->base; | |
dd4916c5 DV |
7670 | err: |
7671 | drm_gem_object_unreference_unlocked(&obj->base); | |
7672 | kfree(intel_fb); | |
7673 | ||
7674 | return ERR_PTR(ret); | |
d2dff872 CW |
7675 | } |
7676 | ||
7677 | static u32 | |
7678 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
7679 | { | |
7680 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
7681 | return ALIGN(pitch, 64); | |
7682 | } | |
7683 | ||
7684 | static u32 | |
7685 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
7686 | { | |
7687 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
7688 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
7689 | } | |
7690 | ||
7691 | static struct drm_framebuffer * | |
7692 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
7693 | struct drm_display_mode *mode, | |
7694 | int depth, int bpp) | |
7695 | { | |
7696 | struct drm_i915_gem_object *obj; | |
0fed39bd | 7697 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
7698 | |
7699 | obj = i915_gem_alloc_object(dev, | |
7700 | intel_framebuffer_size_for_mode(mode, bpp)); | |
7701 | if (obj == NULL) | |
7702 | return ERR_PTR(-ENOMEM); | |
7703 | ||
7704 | mode_cmd.width = mode->hdisplay; | |
7705 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
7706 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
7707 | bpp); | |
5ca0c34a | 7708 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
7709 | |
7710 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
7711 | } | |
7712 | ||
7713 | static struct drm_framebuffer * | |
7714 | mode_fits_in_fbdev(struct drm_device *dev, | |
7715 | struct drm_display_mode *mode) | |
7716 | { | |
4520f53a | 7717 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
7718 | struct drm_i915_private *dev_priv = dev->dev_private; |
7719 | struct drm_i915_gem_object *obj; | |
7720 | struct drm_framebuffer *fb; | |
7721 | ||
7722 | if (dev_priv->fbdev == NULL) | |
7723 | return NULL; | |
7724 | ||
7725 | obj = dev_priv->fbdev->ifb.obj; | |
7726 | if (obj == NULL) | |
7727 | return NULL; | |
7728 | ||
7729 | fb = &dev_priv->fbdev->ifb.base; | |
01f2c773 VS |
7730 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
7731 | fb->bits_per_pixel)) | |
d2dff872 CW |
7732 | return NULL; |
7733 | ||
01f2c773 | 7734 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
7735 | return NULL; |
7736 | ||
7737 | return fb; | |
4520f53a DV |
7738 | #else |
7739 | return NULL; | |
7740 | #endif | |
d2dff872 CW |
7741 | } |
7742 | ||
d2434ab7 | 7743 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 7744 | struct drm_display_mode *mode, |
8261b191 | 7745 | struct intel_load_detect_pipe *old) |
79e53945 JB |
7746 | { |
7747 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
7748 | struct intel_encoder *intel_encoder = |
7749 | intel_attached_encoder(connector); | |
79e53945 | 7750 | struct drm_crtc *possible_crtc; |
4ef69c7a | 7751 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
7752 | struct drm_crtc *crtc = NULL; |
7753 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 7754 | struct drm_framebuffer *fb; |
79e53945 JB |
7755 | int i = -1; |
7756 | ||
d2dff872 CW |
7757 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7758 | connector->base.id, drm_get_connector_name(connector), | |
7759 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7760 | ||
79e53945 JB |
7761 | /* |
7762 | * Algorithm gets a little messy: | |
7a5e4805 | 7763 | * |
79e53945 JB |
7764 | * - if the connector already has an assigned crtc, use it (but make |
7765 | * sure it's on first) | |
7a5e4805 | 7766 | * |
79e53945 JB |
7767 | * - try to find the first unused crtc that can drive this connector, |
7768 | * and use that if we find one | |
79e53945 JB |
7769 | */ |
7770 | ||
7771 | /* See if we already have a CRTC for this connector */ | |
7772 | if (encoder->crtc) { | |
7773 | crtc = encoder->crtc; | |
8261b191 | 7774 | |
7b24056b DV |
7775 | mutex_lock(&crtc->mutex); |
7776 | ||
24218aac | 7777 | old->dpms_mode = connector->dpms; |
8261b191 CW |
7778 | old->load_detect_temp = false; |
7779 | ||
7780 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
7781 | if (connector->dpms != DRM_MODE_DPMS_ON) |
7782 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 7783 | |
7173188d | 7784 | return true; |
79e53945 JB |
7785 | } |
7786 | ||
7787 | /* Find an unused one (if possible) */ | |
7788 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
7789 | i++; | |
7790 | if (!(encoder->possible_crtcs & (1 << i))) | |
7791 | continue; | |
7792 | if (!possible_crtc->enabled) { | |
7793 | crtc = possible_crtc; | |
7794 | break; | |
7795 | } | |
79e53945 JB |
7796 | } |
7797 | ||
7798 | /* | |
7799 | * If we didn't find an unused CRTC, don't use any. | |
7800 | */ | |
7801 | if (!crtc) { | |
7173188d CW |
7802 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
7803 | return false; | |
79e53945 JB |
7804 | } |
7805 | ||
7b24056b | 7806 | mutex_lock(&crtc->mutex); |
fc303101 DV |
7807 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
7808 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
7809 | |
7810 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 7811 | old->dpms_mode = connector->dpms; |
8261b191 | 7812 | old->load_detect_temp = true; |
d2dff872 | 7813 | old->release_fb = NULL; |
79e53945 | 7814 | |
6492711d CW |
7815 | if (!mode) |
7816 | mode = &load_detect_mode; | |
79e53945 | 7817 | |
d2dff872 CW |
7818 | /* We need a framebuffer large enough to accommodate all accesses |
7819 | * that the plane may generate whilst we perform load detection. | |
7820 | * We can not rely on the fbcon either being present (we get called | |
7821 | * during its initialisation to detect all boot displays, or it may | |
7822 | * not even exist) or that it is large enough to satisfy the | |
7823 | * requested mode. | |
7824 | */ | |
94352cf9 DV |
7825 | fb = mode_fits_in_fbdev(dev, mode); |
7826 | if (fb == NULL) { | |
d2dff872 | 7827 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
7828 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
7829 | old->release_fb = fb; | |
d2dff872 CW |
7830 | } else |
7831 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 7832 | if (IS_ERR(fb)) { |
d2dff872 | 7833 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
7b24056b | 7834 | mutex_unlock(&crtc->mutex); |
0e8b3d3e | 7835 | return false; |
79e53945 | 7836 | } |
79e53945 | 7837 | |
c0c36b94 | 7838 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 7839 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
7840 | if (old->release_fb) |
7841 | old->release_fb->funcs->destroy(old->release_fb); | |
7b24056b | 7842 | mutex_unlock(&crtc->mutex); |
0e8b3d3e | 7843 | return false; |
79e53945 | 7844 | } |
7173188d | 7845 | |
79e53945 | 7846 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 7847 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 7848 | return true; |
79e53945 JB |
7849 | } |
7850 | ||
d2434ab7 | 7851 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 7852 | struct intel_load_detect_pipe *old) |
79e53945 | 7853 | { |
d2434ab7 DV |
7854 | struct intel_encoder *intel_encoder = |
7855 | intel_attached_encoder(connector); | |
4ef69c7a | 7856 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 7857 | struct drm_crtc *crtc = encoder->crtc; |
79e53945 | 7858 | |
d2dff872 CW |
7859 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7860 | connector->base.id, drm_get_connector_name(connector), | |
7861 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7862 | ||
8261b191 | 7863 | if (old->load_detect_temp) { |
fc303101 DV |
7864 | to_intel_connector(connector)->new_encoder = NULL; |
7865 | intel_encoder->new_crtc = NULL; | |
7866 | intel_set_mode(crtc, NULL, 0, 0, NULL); | |
d2dff872 | 7867 | |
36206361 DV |
7868 | if (old->release_fb) { |
7869 | drm_framebuffer_unregister_private(old->release_fb); | |
7870 | drm_framebuffer_unreference(old->release_fb); | |
7871 | } | |
d2dff872 | 7872 | |
67c96400 | 7873 | mutex_unlock(&crtc->mutex); |
0622a53c | 7874 | return; |
79e53945 JB |
7875 | } |
7876 | ||
c751ce4f | 7877 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
7878 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
7879 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b DV |
7880 | |
7881 | mutex_unlock(&crtc->mutex); | |
79e53945 JB |
7882 | } |
7883 | ||
da4a1efa VS |
7884 | static int i9xx_pll_refclk(struct drm_device *dev, |
7885 | const struct intel_crtc_config *pipe_config) | |
7886 | { | |
7887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7888 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
7889 | ||
7890 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
7891 | return dev_priv->vbt.lvds_ssc_freq * 1000; | |
7892 | else if (HAS_PCH_SPLIT(dev)) | |
7893 | return 120000; | |
7894 | else if (!IS_GEN2(dev)) | |
7895 | return 96000; | |
7896 | else | |
7897 | return 48000; | |
7898 | } | |
7899 | ||
79e53945 | 7900 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
7901 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
7902 | struct intel_crtc_config *pipe_config) | |
79e53945 | 7903 | { |
f1f644dc | 7904 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7905 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 7906 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 7907 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
7908 | u32 fp; |
7909 | intel_clock_t clock; | |
da4a1efa | 7910 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
7911 | |
7912 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 7913 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 7914 | else |
293623f7 | 7915 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
7916 | |
7917 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
7918 | if (IS_PINEVIEW(dev)) { |
7919 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
7920 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
7921 | } else { |
7922 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
7923 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
7924 | } | |
7925 | ||
a6c45cf0 | 7926 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
7927 | if (IS_PINEVIEW(dev)) |
7928 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
7929 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
7930 | else |
7931 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
7932 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
7933 | ||
7934 | switch (dpll & DPLL_MODE_MASK) { | |
7935 | case DPLLB_MODE_DAC_SERIAL: | |
7936 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
7937 | 5 : 10; | |
7938 | break; | |
7939 | case DPLLB_MODE_LVDS: | |
7940 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
7941 | 7 : 14; | |
7942 | break; | |
7943 | default: | |
28c97730 | 7944 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 7945 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 7946 | return; |
79e53945 JB |
7947 | } |
7948 | ||
ac58c3f0 | 7949 | if (IS_PINEVIEW(dev)) |
da4a1efa | 7950 | pineview_clock(refclk, &clock); |
ac58c3f0 | 7951 | else |
da4a1efa | 7952 | i9xx_clock(refclk, &clock); |
79e53945 | 7953 | } else { |
b1c560d1 VS |
7954 | u32 lvds = I915_READ(LVDS); |
7955 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); | |
79e53945 JB |
7956 | |
7957 | if (is_lvds) { | |
7958 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
7959 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
7960 | |
7961 | if (lvds & LVDS_CLKB_POWER_UP) | |
7962 | clock.p2 = 7; | |
7963 | else | |
7964 | clock.p2 = 14; | |
79e53945 JB |
7965 | } else { |
7966 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
7967 | clock.p1 = 2; | |
7968 | else { | |
7969 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
7970 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
7971 | } | |
7972 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
7973 | clock.p2 = 4; | |
7974 | else | |
7975 | clock.p2 = 2; | |
79e53945 | 7976 | } |
da4a1efa VS |
7977 | |
7978 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
7979 | } |
7980 | ||
18442d08 VS |
7981 | /* |
7982 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 7983 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
7984 | * encoder's get_config() function. |
7985 | */ | |
7986 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
7987 | } |
7988 | ||
6878da05 VS |
7989 | int intel_dotclock_calculate(int link_freq, |
7990 | const struct intel_link_m_n *m_n) | |
f1f644dc | 7991 | { |
f1f644dc JB |
7992 | /* |
7993 | * The calculation for the data clock is: | |
1041a02f | 7994 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 7995 | * But we want to avoid losing precison if possible, so: |
1041a02f | 7996 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
7997 | * |
7998 | * and the link clock is simpler: | |
1041a02f | 7999 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
8000 | */ |
8001 | ||
6878da05 VS |
8002 | if (!m_n->link_n) |
8003 | return 0; | |
f1f644dc | 8004 | |
6878da05 VS |
8005 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8006 | } | |
f1f644dc | 8007 | |
18442d08 VS |
8008 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8009 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
8010 | { |
8011 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 8012 | |
18442d08 VS |
8013 | /* read out port_clock from the DPLL */ |
8014 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 8015 | |
f1f644dc | 8016 | /* |
18442d08 | 8017 | * This value does not include pixel_multiplier. |
241bfc38 | 8018 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
8019 | * agree once we know their relationship in the encoder's |
8020 | * get_config() function. | |
79e53945 | 8021 | */ |
241bfc38 | 8022 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
8023 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8024 | &pipe_config->fdi_m_n); | |
79e53945 JB |
8025 | } |
8026 | ||
8027 | /** Returns the currently programmed mode of the given pipe. */ | |
8028 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
8029 | struct drm_crtc *crtc) | |
8030 | { | |
548f245b | 8031 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 8032 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 8033 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 8034 | struct drm_display_mode *mode; |
f1f644dc | 8035 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
8036 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8037 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8038 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
8039 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 8040 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
8041 | |
8042 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
8043 | if (!mode) | |
8044 | return NULL; | |
8045 | ||
f1f644dc JB |
8046 | /* |
8047 | * Construct a pipe_config sufficient for getting the clock info | |
8048 | * back out of crtc_clock_get. | |
8049 | * | |
8050 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8051 | * to use a real value here instead. | |
8052 | */ | |
293623f7 | 8053 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8054 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8055 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8056 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8057 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8058 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8059 | ||
773ae034 | 8060 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8061 | mode->hdisplay = (htot & 0xffff) + 1; |
8062 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8063 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8064 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8065 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8066 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8067 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8068 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8069 | ||
8070 | drm_mode_set_name(mode); | |
79e53945 JB |
8071 | |
8072 | return mode; | |
8073 | } | |
8074 | ||
3dec0095 | 8075 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
8076 | { |
8077 | struct drm_device *dev = crtc->dev; | |
8078 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8079 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8080 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
8081 | int dpll_reg = DPLL(pipe); |
8082 | int dpll; | |
652c393a | 8083 | |
bad720ff | 8084 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8085 | return; |
8086 | ||
8087 | if (!dev_priv->lvds_downclock_avail) | |
8088 | return; | |
8089 | ||
dbdc6479 | 8090 | dpll = I915_READ(dpll_reg); |
652c393a | 8091 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 8092 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 8093 | |
8ac5a6d5 | 8094 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
8095 | |
8096 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
8097 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8098 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 8099 | |
652c393a JB |
8100 | dpll = I915_READ(dpll_reg); |
8101 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 8102 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 8103 | } |
652c393a JB |
8104 | } |
8105 | ||
8106 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
8107 | { | |
8108 | struct drm_device *dev = crtc->dev; | |
8109 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8110 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
652c393a | 8111 | |
bad720ff | 8112 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
8113 | return; |
8114 | ||
8115 | if (!dev_priv->lvds_downclock_avail) | |
8116 | return; | |
8117 | ||
8118 | /* | |
8119 | * Since this is called by a timer, we should never get here in | |
8120 | * the manual case. | |
8121 | */ | |
8122 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8123 | int pipe = intel_crtc->pipe; |
8124 | int dpll_reg = DPLL(pipe); | |
8125 | int dpll; | |
f6e5b160 | 8126 | |
44d98a61 | 8127 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8128 | |
8ac5a6d5 | 8129 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8130 | |
dc257cf1 | 8131 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8132 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8133 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8134 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8135 | dpll = I915_READ(dpll_reg); |
8136 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8137 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8138 | } |
8139 | ||
8140 | } | |
8141 | ||
f047e395 CW |
8142 | void intel_mark_busy(struct drm_device *dev) |
8143 | { | |
c67a470b PZ |
8144 | struct drm_i915_private *dev_priv = dev->dev_private; |
8145 | ||
8146 | hsw_package_c8_gpu_busy(dev_priv); | |
8147 | i915_update_gfx_val(dev_priv); | |
f047e395 CW |
8148 | } |
8149 | ||
8150 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8151 | { |
c67a470b | 8152 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8153 | struct drm_crtc *crtc; |
652c393a | 8154 | |
c67a470b PZ |
8155 | hsw_package_c8_gpu_idle(dev_priv); |
8156 | ||
652c393a JB |
8157 | if (!i915_powersave) |
8158 | return; | |
8159 | ||
652c393a | 8160 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
652c393a JB |
8161 | if (!crtc->fb) |
8162 | continue; | |
8163 | ||
725a5b54 | 8164 | intel_decrease_pllclock(crtc); |
652c393a | 8165 | } |
b29c19b6 CW |
8166 | |
8167 | if (dev_priv->info->gen >= 6) | |
8168 | gen6_rps_idle(dev->dev_private); | |
652c393a JB |
8169 | } |
8170 | ||
c65355bb CW |
8171 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
8172 | struct intel_ring_buffer *ring) | |
652c393a | 8173 | { |
f047e395 CW |
8174 | struct drm_device *dev = obj->base.dev; |
8175 | struct drm_crtc *crtc; | |
652c393a | 8176 | |
f047e395 | 8177 | if (!i915_powersave) |
acb87dfb CW |
8178 | return; |
8179 | ||
652c393a JB |
8180 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
8181 | if (!crtc->fb) | |
8182 | continue; | |
8183 | ||
c65355bb CW |
8184 | if (to_intel_framebuffer(crtc->fb)->obj != obj) |
8185 | continue; | |
8186 | ||
8187 | intel_increase_pllclock(crtc); | |
8188 | if (ring && intel_fbc_enabled(dev)) | |
8189 | ring->fbc_dirty = true; | |
652c393a JB |
8190 | } |
8191 | } | |
8192 | ||
79e53945 JB |
8193 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
8194 | { | |
8195 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
8196 | struct drm_device *dev = crtc->dev; |
8197 | struct intel_unpin_work *work; | |
8198 | unsigned long flags; | |
8199 | ||
8200 | spin_lock_irqsave(&dev->event_lock, flags); | |
8201 | work = intel_crtc->unpin_work; | |
8202 | intel_crtc->unpin_work = NULL; | |
8203 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8204 | ||
8205 | if (work) { | |
8206 | cancel_work_sync(&work->work); | |
8207 | kfree(work); | |
8208 | } | |
79e53945 | 8209 | |
40ccc72b MK |
8210 | intel_crtc_cursor_set(crtc, NULL, 0, 0, 0); |
8211 | ||
79e53945 | 8212 | drm_crtc_cleanup(crtc); |
67e77c5a | 8213 | |
79e53945 JB |
8214 | kfree(intel_crtc); |
8215 | } | |
8216 | ||
6b95a207 KH |
8217 | static void intel_unpin_work_fn(struct work_struct *__work) |
8218 | { | |
8219 | struct intel_unpin_work *work = | |
8220 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 8221 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 8222 | |
b4a98e57 | 8223 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 8224 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
8225 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
8226 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 8227 | |
b4a98e57 CW |
8228 | intel_update_fbc(dev); |
8229 | mutex_unlock(&dev->struct_mutex); | |
8230 | ||
8231 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
8232 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
8233 | ||
6b95a207 KH |
8234 | kfree(work); |
8235 | } | |
8236 | ||
1afe3e9d | 8237 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 8238 | struct drm_crtc *crtc) |
6b95a207 KH |
8239 | { |
8240 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
8241 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8242 | struct intel_unpin_work *work; | |
6b95a207 KH |
8243 | unsigned long flags; |
8244 | ||
8245 | /* Ignore early vblank irqs */ | |
8246 | if (intel_crtc == NULL) | |
8247 | return; | |
8248 | ||
8249 | spin_lock_irqsave(&dev->event_lock, flags); | |
8250 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
8251 | |
8252 | /* Ensure we don't miss a work->pending update ... */ | |
8253 | smp_rmb(); | |
8254 | ||
8255 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
8256 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8257 | return; | |
8258 | } | |
8259 | ||
e7d841ca CW |
8260 | /* and that the unpin work is consistent wrt ->pending. */ |
8261 | smp_rmb(); | |
8262 | ||
6b95a207 | 8263 | intel_crtc->unpin_work = NULL; |
6b95a207 | 8264 | |
45a066eb RC |
8265 | if (work->event) |
8266 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 8267 | |
0af7e4df MK |
8268 | drm_vblank_put(dev, intel_crtc->pipe); |
8269 | ||
6b95a207 KH |
8270 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8271 | ||
2c10d571 | 8272 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
8273 | |
8274 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
8275 | |
8276 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
8277 | } |
8278 | ||
1afe3e9d JB |
8279 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
8280 | { | |
8281 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8282 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
8283 | ||
49b14a5c | 8284 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8285 | } |
8286 | ||
8287 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
8288 | { | |
8289 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8290 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
8291 | ||
49b14a5c | 8292 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
8293 | } |
8294 | ||
6b95a207 KH |
8295 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
8296 | { | |
8297 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8298 | struct intel_crtc *intel_crtc = | |
8299 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
8300 | unsigned long flags; | |
8301 | ||
e7d841ca CW |
8302 | /* NB: An MMIO update of the plane base pointer will also |
8303 | * generate a page-flip completion irq, i.e. every modeset | |
8304 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
8305 | */ | |
6b95a207 | 8306 | spin_lock_irqsave(&dev->event_lock, flags); |
e7d841ca CW |
8307 | if (intel_crtc->unpin_work) |
8308 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); | |
6b95a207 KH |
8309 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8310 | } | |
8311 | ||
e7d841ca CW |
8312 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
8313 | { | |
8314 | /* Ensure that the work item is consistent when activating it ... */ | |
8315 | smp_wmb(); | |
8316 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
8317 | /* and that it is marked active as soon as the irq could fire. */ | |
8318 | smp_wmb(); | |
8319 | } | |
8320 | ||
8c9f3aaf JB |
8321 | static int intel_gen2_queue_flip(struct drm_device *dev, |
8322 | struct drm_crtc *crtc, | |
8323 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8324 | struct drm_i915_gem_object *obj, |
8325 | uint32_t flags) | |
8c9f3aaf JB |
8326 | { |
8327 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8328 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 8329 | u32 flip_mask; |
6d90c952 | 8330 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8331 | int ret; |
8332 | ||
6d90c952 | 8333 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8334 | if (ret) |
83d4092b | 8335 | goto err; |
8c9f3aaf | 8336 | |
6d90c952 | 8337 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8338 | if (ret) |
83d4092b | 8339 | goto err_unpin; |
8c9f3aaf JB |
8340 | |
8341 | /* Can't queue multiple flips, so wait for the previous | |
8342 | * one to finish before executing the next. | |
8343 | */ | |
8344 | if (intel_crtc->plane) | |
8345 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8346 | else | |
8347 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8348 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8349 | intel_ring_emit(ring, MI_NOOP); | |
8350 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
8351 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8352 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 8353 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 | 8354 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
8355 | |
8356 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8357 | __intel_ring_advance(ring); |
83d4092b CW |
8358 | return 0; |
8359 | ||
8360 | err_unpin: | |
8361 | intel_unpin_fb_obj(obj); | |
8362 | err: | |
8c9f3aaf JB |
8363 | return ret; |
8364 | } | |
8365 | ||
8366 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
8367 | struct drm_crtc *crtc, | |
8368 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8369 | struct drm_i915_gem_object *obj, |
8370 | uint32_t flags) | |
8c9f3aaf JB |
8371 | { |
8372 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8373 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 8374 | u32 flip_mask; |
6d90c952 | 8375 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8376 | int ret; |
8377 | ||
6d90c952 | 8378 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8379 | if (ret) |
83d4092b | 8380 | goto err; |
8c9f3aaf | 8381 | |
6d90c952 | 8382 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 8383 | if (ret) |
83d4092b | 8384 | goto err_unpin; |
8c9f3aaf JB |
8385 | |
8386 | if (intel_crtc->plane) | |
8387 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
8388 | else | |
8389 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
8390 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
8391 | intel_ring_emit(ring, MI_NOOP); | |
8392 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
8393 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8394 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 8395 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 DV |
8396 | intel_ring_emit(ring, MI_NOOP); |
8397 | ||
e7d841ca | 8398 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 8399 | __intel_ring_advance(ring); |
83d4092b CW |
8400 | return 0; |
8401 | ||
8402 | err_unpin: | |
8403 | intel_unpin_fb_obj(obj); | |
8404 | err: | |
8c9f3aaf JB |
8405 | return ret; |
8406 | } | |
8407 | ||
8408 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
8409 | struct drm_crtc *crtc, | |
8410 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8411 | struct drm_i915_gem_object *obj, |
8412 | uint32_t flags) | |
8c9f3aaf JB |
8413 | { |
8414 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8415 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8416 | uint32_t pf, pipesrc; | |
6d90c952 | 8417 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8418 | int ret; |
8419 | ||
6d90c952 | 8420 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8421 | if (ret) |
83d4092b | 8422 | goto err; |
8c9f3aaf | 8423 | |
6d90c952 | 8424 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 8425 | if (ret) |
83d4092b | 8426 | goto err_unpin; |
8c9f3aaf JB |
8427 | |
8428 | /* i965+ uses the linear or tiled offsets from the | |
8429 | * Display Registers (which do not change across a page-flip) | |
8430 | * so we need only reprogram the base address. | |
8431 | */ | |
6d90c952 DV |
8432 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8433 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8434 | intel_ring_emit(ring, fb->pitches[0]); | |
c2c75131 | 8435 | intel_ring_emit(ring, |
f343c5f6 | 8436 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
c2c75131 | 8437 | obj->tiling_mode); |
8c9f3aaf JB |
8438 | |
8439 | /* XXX Enabling the panel-fitter across page-flip is so far | |
8440 | * untested on non-native modes, so ignore it for now. | |
8441 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
8442 | */ | |
8443 | pf = 0; | |
8444 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 8445 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
8446 | |
8447 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8448 | __intel_ring_advance(ring); |
83d4092b CW |
8449 | return 0; |
8450 | ||
8451 | err_unpin: | |
8452 | intel_unpin_fb_obj(obj); | |
8453 | err: | |
8c9f3aaf JB |
8454 | return ret; |
8455 | } | |
8456 | ||
8457 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
8458 | struct drm_crtc *crtc, | |
8459 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8460 | struct drm_i915_gem_object *obj, |
8461 | uint32_t flags) | |
8c9f3aaf JB |
8462 | { |
8463 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8464 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6d90c952 | 8465 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
8466 | uint32_t pf, pipesrc; |
8467 | int ret; | |
8468 | ||
6d90c952 | 8469 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 8470 | if (ret) |
83d4092b | 8471 | goto err; |
8c9f3aaf | 8472 | |
6d90c952 | 8473 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 8474 | if (ret) |
83d4092b | 8475 | goto err_unpin; |
8c9f3aaf | 8476 | |
6d90c952 DV |
8477 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
8478 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
8479 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
f343c5f6 | 8480 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
8c9f3aaf | 8481 | |
dc257cf1 DV |
8482 | /* Contrary to the suggestions in the documentation, |
8483 | * "Enable Panel Fitter" does not seem to be required when page | |
8484 | * flipping with a non-native mode, and worse causes a normal | |
8485 | * modeset to fail. | |
8486 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
8487 | */ | |
8488 | pf = 0; | |
8c9f3aaf | 8489 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 8490 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
8491 | |
8492 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8493 | __intel_ring_advance(ring); |
83d4092b CW |
8494 | return 0; |
8495 | ||
8496 | err_unpin: | |
8497 | intel_unpin_fb_obj(obj); | |
8498 | err: | |
8c9f3aaf JB |
8499 | return ret; |
8500 | } | |
8501 | ||
7c9017e5 JB |
8502 | static int intel_gen7_queue_flip(struct drm_device *dev, |
8503 | struct drm_crtc *crtc, | |
8504 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8505 | struct drm_i915_gem_object *obj, |
8506 | uint32_t flags) | |
7c9017e5 JB |
8507 | { |
8508 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8509 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ffe74d75 | 8510 | struct intel_ring_buffer *ring; |
cb05d8de | 8511 | uint32_t plane_bit = 0; |
ffe74d75 CW |
8512 | int len, ret; |
8513 | ||
8514 | ring = obj->ring; | |
1c5fd085 | 8515 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
ffe74d75 | 8516 | ring = &dev_priv->ring[BCS]; |
7c9017e5 JB |
8517 | |
8518 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
8519 | if (ret) | |
83d4092b | 8520 | goto err; |
7c9017e5 | 8521 | |
cb05d8de DV |
8522 | switch(intel_crtc->plane) { |
8523 | case PLANE_A: | |
8524 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
8525 | break; | |
8526 | case PLANE_B: | |
8527 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
8528 | break; | |
8529 | case PLANE_C: | |
8530 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
8531 | break; | |
8532 | default: | |
8533 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
8534 | ret = -ENODEV; | |
ab3951eb | 8535 | goto err_unpin; |
cb05d8de DV |
8536 | } |
8537 | ||
ffe74d75 CW |
8538 | len = 4; |
8539 | if (ring->id == RCS) | |
8540 | len += 6; | |
8541 | ||
8542 | ret = intel_ring_begin(ring, len); | |
7c9017e5 | 8543 | if (ret) |
83d4092b | 8544 | goto err_unpin; |
7c9017e5 | 8545 | |
ffe74d75 CW |
8546 | /* Unmask the flip-done completion message. Note that the bspec says that |
8547 | * we should do this for both the BCS and RCS, and that we must not unmask | |
8548 | * more than one flip event at any time (or ensure that one flip message | |
8549 | * can be sent by waiting for flip-done prior to queueing new flips). | |
8550 | * Experimentation says that BCS works despite DERRMR masking all | |
8551 | * flip-done completion events and that unmasking all planes at once | |
8552 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
8553 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
8554 | */ | |
8555 | if (ring->id == RCS) { | |
8556 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
8557 | intel_ring_emit(ring, DERRMR); | |
8558 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
8559 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
8560 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
8561 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1)); | |
8562 | intel_ring_emit(ring, DERRMR); | |
8563 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
8564 | } | |
8565 | ||
cb05d8de | 8566 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 8567 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
f343c5f6 | 8568 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7c9017e5 | 8569 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
8570 | |
8571 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8572 | __intel_ring_advance(ring); |
83d4092b CW |
8573 | return 0; |
8574 | ||
8575 | err_unpin: | |
8576 | intel_unpin_fb_obj(obj); | |
8577 | err: | |
7c9017e5 JB |
8578 | return ret; |
8579 | } | |
8580 | ||
8c9f3aaf JB |
8581 | static int intel_default_queue_flip(struct drm_device *dev, |
8582 | struct drm_crtc *crtc, | |
8583 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8584 | struct drm_i915_gem_object *obj, |
8585 | uint32_t flags) | |
8c9f3aaf JB |
8586 | { |
8587 | return -ENODEV; | |
8588 | } | |
8589 | ||
6b95a207 KH |
8590 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
8591 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8592 | struct drm_pending_vblank_event *event, |
8593 | uint32_t page_flip_flags) | |
6b95a207 KH |
8594 | { |
8595 | struct drm_device *dev = crtc->dev; | |
8596 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a35f83b VS |
8597 | struct drm_framebuffer *old_fb = crtc->fb; |
8598 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; | |
6b95a207 KH |
8599 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8600 | struct intel_unpin_work *work; | |
8c9f3aaf | 8601 | unsigned long flags; |
52e68630 | 8602 | int ret; |
6b95a207 | 8603 | |
e6a595d2 VS |
8604 | /* Can't change pixel format via MI display flips. */ |
8605 | if (fb->pixel_format != crtc->fb->pixel_format) | |
8606 | return -EINVAL; | |
8607 | ||
8608 | /* | |
8609 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
8610 | * Note that pitch changes could also affect these register. | |
8611 | */ | |
8612 | if (INTEL_INFO(dev)->gen > 3 && | |
8613 | (fb->offsets[0] != crtc->fb->offsets[0] || | |
8614 | fb->pitches[0] != crtc->fb->pitches[0])) | |
8615 | return -EINVAL; | |
8616 | ||
b14c5679 | 8617 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
8618 | if (work == NULL) |
8619 | return -ENOMEM; | |
8620 | ||
6b95a207 | 8621 | work->event = event; |
b4a98e57 | 8622 | work->crtc = crtc; |
4a35f83b | 8623 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
6b95a207 KH |
8624 | INIT_WORK(&work->work, intel_unpin_work_fn); |
8625 | ||
7317c75e JB |
8626 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
8627 | if (ret) | |
8628 | goto free_work; | |
8629 | ||
6b95a207 KH |
8630 | /* We borrow the event spin lock for protecting unpin_work */ |
8631 | spin_lock_irqsave(&dev->event_lock, flags); | |
8632 | if (intel_crtc->unpin_work) { | |
8633 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8634 | kfree(work); | |
7317c75e | 8635 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
8636 | |
8637 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
8638 | return -EBUSY; |
8639 | } | |
8640 | intel_crtc->unpin_work = work; | |
8641 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8642 | ||
b4a98e57 CW |
8643 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
8644 | flush_workqueue(dev_priv->wq); | |
8645 | ||
79158103 CW |
8646 | ret = i915_mutex_lock_interruptible(dev); |
8647 | if (ret) | |
8648 | goto cleanup; | |
6b95a207 | 8649 | |
75dfca80 | 8650 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
8651 | drm_gem_object_reference(&work->old_fb_obj->base); |
8652 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
8653 | |
8654 | crtc->fb = fb; | |
96b099fd | 8655 | |
e1f99ce6 | 8656 | work->pending_flip_obj = obj; |
e1f99ce6 | 8657 | |
4e5359cd SF |
8658 | work->enable_stall_check = true; |
8659 | ||
b4a98e57 | 8660 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 8661 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 8662 | |
ed8d1975 | 8663 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
8c9f3aaf JB |
8664 | if (ret) |
8665 | goto cleanup_pending; | |
6b95a207 | 8666 | |
7782de3b | 8667 | intel_disable_fbc(dev); |
c65355bb | 8668 | intel_mark_fb_busy(obj, NULL); |
6b95a207 KH |
8669 | mutex_unlock(&dev->struct_mutex); |
8670 | ||
e5510fac JB |
8671 | trace_i915_flip_request(intel_crtc->plane, obj); |
8672 | ||
6b95a207 | 8673 | return 0; |
96b099fd | 8674 | |
8c9f3aaf | 8675 | cleanup_pending: |
b4a98e57 | 8676 | atomic_dec(&intel_crtc->unpin_work_count); |
4a35f83b | 8677 | crtc->fb = old_fb; |
05394f39 CW |
8678 | drm_gem_object_unreference(&work->old_fb_obj->base); |
8679 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
8680 | mutex_unlock(&dev->struct_mutex); |
8681 | ||
79158103 | 8682 | cleanup: |
96b099fd CW |
8683 | spin_lock_irqsave(&dev->event_lock, flags); |
8684 | intel_crtc->unpin_work = NULL; | |
8685 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8686 | ||
7317c75e JB |
8687 | drm_vblank_put(dev, intel_crtc->pipe); |
8688 | free_work: | |
96b099fd CW |
8689 | kfree(work); |
8690 | ||
8691 | return ret; | |
6b95a207 KH |
8692 | } |
8693 | ||
f6e5b160 | 8694 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
8695 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
8696 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
8697 | }; |
8698 | ||
50f56119 DV |
8699 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
8700 | struct drm_crtc *crtc) | |
8701 | { | |
8702 | struct drm_device *dev; | |
8703 | struct drm_crtc *tmp; | |
8704 | int crtc_mask = 1; | |
47f1c6c9 | 8705 | |
50f56119 | 8706 | WARN(!crtc, "checking null crtc?\n"); |
47f1c6c9 | 8707 | |
50f56119 | 8708 | dev = crtc->dev; |
47f1c6c9 | 8709 | |
50f56119 DV |
8710 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { |
8711 | if (tmp == crtc) | |
8712 | break; | |
8713 | crtc_mask <<= 1; | |
8714 | } | |
47f1c6c9 | 8715 | |
50f56119 DV |
8716 | if (encoder->possible_crtcs & crtc_mask) |
8717 | return true; | |
8718 | return false; | |
47f1c6c9 | 8719 | } |
79e53945 | 8720 | |
9a935856 DV |
8721 | /** |
8722 | * intel_modeset_update_staged_output_state | |
8723 | * | |
8724 | * Updates the staged output configuration state, e.g. after we've read out the | |
8725 | * current hw state. | |
8726 | */ | |
8727 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 8728 | { |
9a935856 DV |
8729 | struct intel_encoder *encoder; |
8730 | struct intel_connector *connector; | |
f6e5b160 | 8731 | |
9a935856 DV |
8732 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8733 | base.head) { | |
8734 | connector->new_encoder = | |
8735 | to_intel_encoder(connector->base.encoder); | |
8736 | } | |
f6e5b160 | 8737 | |
9a935856 DV |
8738 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8739 | base.head) { | |
8740 | encoder->new_crtc = | |
8741 | to_intel_crtc(encoder->base.crtc); | |
8742 | } | |
f6e5b160 CW |
8743 | } |
8744 | ||
9a935856 DV |
8745 | /** |
8746 | * intel_modeset_commit_output_state | |
8747 | * | |
8748 | * This function copies the stage display pipe configuration to the real one. | |
8749 | */ | |
8750 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
8751 | { | |
8752 | struct intel_encoder *encoder; | |
8753 | struct intel_connector *connector; | |
f6e5b160 | 8754 | |
9a935856 DV |
8755 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8756 | base.head) { | |
8757 | connector->base.encoder = &connector->new_encoder->base; | |
8758 | } | |
f6e5b160 | 8759 | |
9a935856 DV |
8760 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8761 | base.head) { | |
8762 | encoder->base.crtc = &encoder->new_crtc->base; | |
8763 | } | |
8764 | } | |
8765 | ||
050f7aeb DV |
8766 | static void |
8767 | connected_sink_compute_bpp(struct intel_connector * connector, | |
8768 | struct intel_crtc_config *pipe_config) | |
8769 | { | |
8770 | int bpp = pipe_config->pipe_bpp; | |
8771 | ||
8772 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
8773 | connector->base.base.id, | |
8774 | drm_get_connector_name(&connector->base)); | |
8775 | ||
8776 | /* Don't use an invalid EDID bpc value */ | |
8777 | if (connector->base.display_info.bpc && | |
8778 | connector->base.display_info.bpc * 3 < bpp) { | |
8779 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
8780 | bpp, connector->base.display_info.bpc*3); | |
8781 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
8782 | } | |
8783 | ||
8784 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
8785 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
8786 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
8787 | bpp); | |
8788 | pipe_config->pipe_bpp = 24; | |
8789 | } | |
8790 | } | |
8791 | ||
4e53c2e0 | 8792 | static int |
050f7aeb DV |
8793 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
8794 | struct drm_framebuffer *fb, | |
8795 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 8796 | { |
050f7aeb DV |
8797 | struct drm_device *dev = crtc->base.dev; |
8798 | struct intel_connector *connector; | |
4e53c2e0 DV |
8799 | int bpp; |
8800 | ||
d42264b1 DV |
8801 | switch (fb->pixel_format) { |
8802 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
8803 | bpp = 8*3; /* since we go through a colormap */ |
8804 | break; | |
d42264b1 DV |
8805 | case DRM_FORMAT_XRGB1555: |
8806 | case DRM_FORMAT_ARGB1555: | |
8807 | /* checked in intel_framebuffer_init already */ | |
8808 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
8809 | return -EINVAL; | |
8810 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
8811 | bpp = 6*3; /* min is 18bpp */ |
8812 | break; | |
d42264b1 DV |
8813 | case DRM_FORMAT_XBGR8888: |
8814 | case DRM_FORMAT_ABGR8888: | |
8815 | /* checked in intel_framebuffer_init already */ | |
8816 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
8817 | return -EINVAL; | |
8818 | case DRM_FORMAT_XRGB8888: | |
8819 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
8820 | bpp = 8*3; |
8821 | break; | |
d42264b1 DV |
8822 | case DRM_FORMAT_XRGB2101010: |
8823 | case DRM_FORMAT_ARGB2101010: | |
8824 | case DRM_FORMAT_XBGR2101010: | |
8825 | case DRM_FORMAT_ABGR2101010: | |
8826 | /* checked in intel_framebuffer_init already */ | |
8827 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 8828 | return -EINVAL; |
4e53c2e0 DV |
8829 | bpp = 10*3; |
8830 | break; | |
baba133a | 8831 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
8832 | default: |
8833 | DRM_DEBUG_KMS("unsupported depth\n"); | |
8834 | return -EINVAL; | |
8835 | } | |
8836 | ||
4e53c2e0 DV |
8837 | pipe_config->pipe_bpp = bpp; |
8838 | ||
8839 | /* Clamp display bpp to EDID value */ | |
8840 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 8841 | base.head) { |
1b829e05 DV |
8842 | if (!connector->new_encoder || |
8843 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
8844 | continue; |
8845 | ||
050f7aeb | 8846 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
8847 | } |
8848 | ||
8849 | return bpp; | |
8850 | } | |
8851 | ||
644db711 DV |
8852 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
8853 | { | |
8854 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
8855 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 8856 | mode->crtc_clock, |
644db711 DV |
8857 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
8858 | mode->crtc_hsync_end, mode->crtc_htotal, | |
8859 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
8860 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
8861 | } | |
8862 | ||
c0b03411 DV |
8863 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
8864 | struct intel_crtc_config *pipe_config, | |
8865 | const char *context) | |
8866 | { | |
8867 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
8868 | context, pipe_name(crtc->pipe)); | |
8869 | ||
8870 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
8871 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
8872 | pipe_config->pipe_bpp, pipe_config->dither); | |
8873 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
8874 | pipe_config->has_pch_encoder, | |
8875 | pipe_config->fdi_lanes, | |
8876 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
8877 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
8878 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
8879 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
8880 | pipe_config->has_dp_encoder, | |
8881 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
8882 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
8883 | pipe_config->dp_m_n.tu); | |
c0b03411 DV |
8884 | DRM_DEBUG_KMS("requested mode:\n"); |
8885 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
8886 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
8887 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 8888 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 8889 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
8890 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
8891 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
8892 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
8893 | pipe_config->gmch_pfit.control, | |
8894 | pipe_config->gmch_pfit.pgm_ratios, | |
8895 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 8896 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 8897 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
8898 | pipe_config->pch_pfit.size, |
8899 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 8900 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 8901 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
8902 | } |
8903 | ||
accfc0c5 DV |
8904 | static bool check_encoder_cloning(struct drm_crtc *crtc) |
8905 | { | |
8906 | int num_encoders = 0; | |
8907 | bool uncloneable_encoders = false; | |
8908 | struct intel_encoder *encoder; | |
8909 | ||
8910 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, | |
8911 | base.head) { | |
8912 | if (&encoder->new_crtc->base != crtc) | |
8913 | continue; | |
8914 | ||
8915 | num_encoders++; | |
8916 | if (!encoder->cloneable) | |
8917 | uncloneable_encoders = true; | |
8918 | } | |
8919 | ||
8920 | return !(num_encoders > 1 && uncloneable_encoders); | |
8921 | } | |
8922 | ||
b8cecdf5 DV |
8923 | static struct intel_crtc_config * |
8924 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 8925 | struct drm_framebuffer *fb, |
b8cecdf5 | 8926 | struct drm_display_mode *mode) |
ee7b9f93 | 8927 | { |
7758a113 | 8928 | struct drm_device *dev = crtc->dev; |
7758a113 | 8929 | struct intel_encoder *encoder; |
b8cecdf5 | 8930 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
8931 | int plane_bpp, ret = -EINVAL; |
8932 | bool retry = true; | |
ee7b9f93 | 8933 | |
accfc0c5 DV |
8934 | if (!check_encoder_cloning(crtc)) { |
8935 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
8936 | return ERR_PTR(-EINVAL); | |
8937 | } | |
8938 | ||
b8cecdf5 DV |
8939 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
8940 | if (!pipe_config) | |
7758a113 DV |
8941 | return ERR_PTR(-ENOMEM); |
8942 | ||
b8cecdf5 DV |
8943 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
8944 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 8945 | |
e143a21c DV |
8946 | pipe_config->cpu_transcoder = |
8947 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 8948 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 8949 | |
2960bc9c ID |
8950 | /* |
8951 | * Sanitize sync polarity flags based on requested ones. If neither | |
8952 | * positive or negative polarity is requested, treat this as meaning | |
8953 | * negative polarity. | |
8954 | */ | |
8955 | if (!(pipe_config->adjusted_mode.flags & | |
8956 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
8957 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
8958 | ||
8959 | if (!(pipe_config->adjusted_mode.flags & | |
8960 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
8961 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
8962 | ||
050f7aeb DV |
8963 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
8964 | * plane pixel format and any sink constraints into account. Returns the | |
8965 | * source plane bpp so that dithering can be selected on mismatches | |
8966 | * after encoders and crtc also have had their say. */ | |
8967 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
8968 | fb, pipe_config); | |
4e53c2e0 DV |
8969 | if (plane_bpp < 0) |
8970 | goto fail; | |
8971 | ||
e41a56be VS |
8972 | /* |
8973 | * Determine the real pipe dimensions. Note that stereo modes can | |
8974 | * increase the actual pipe size due to the frame doubling and | |
8975 | * insertion of additional space for blanks between the frame. This | |
8976 | * is stored in the crtc timings. We use the requested mode to do this | |
8977 | * computation to clearly distinguish it from the adjusted mode, which | |
8978 | * can be changed by the connectors in the below retry loop. | |
8979 | */ | |
8980 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
8981 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
8982 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
8983 | ||
e29c22c0 | 8984 | encoder_retry: |
ef1b460d | 8985 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 8986 | pipe_config->port_clock = 0; |
ef1b460d | 8987 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 8988 | |
135c81b8 | 8989 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 8990 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 8991 | |
7758a113 DV |
8992 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
8993 | * adjust it according to limitations or connector properties, and also | |
8994 | * a chance to reject the mode entirely. | |
47f1c6c9 | 8995 | */ |
7758a113 DV |
8996 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8997 | base.head) { | |
47f1c6c9 | 8998 | |
7758a113 DV |
8999 | if (&encoder->new_crtc->base != crtc) |
9000 | continue; | |
7ae89233 | 9001 | |
efea6e8e DV |
9002 | if (!(encoder->compute_config(encoder, pipe_config))) { |
9003 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
9004 | goto fail; |
9005 | } | |
ee7b9f93 | 9006 | } |
47f1c6c9 | 9007 | |
ff9a6750 DV |
9008 | /* Set default port clock if not overwritten by the encoder. Needs to be |
9009 | * done afterwards in case the encoder adjusts the mode. */ | |
9010 | if (!pipe_config->port_clock) | |
241bfc38 DL |
9011 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
9012 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 9013 | |
a43f6e0f | 9014 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 9015 | if (ret < 0) { |
7758a113 DV |
9016 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
9017 | goto fail; | |
ee7b9f93 | 9018 | } |
e29c22c0 DV |
9019 | |
9020 | if (ret == RETRY) { | |
9021 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
9022 | ret = -EINVAL; | |
9023 | goto fail; | |
9024 | } | |
9025 | ||
9026 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
9027 | retry = false; | |
9028 | goto encoder_retry; | |
9029 | } | |
9030 | ||
4e53c2e0 DV |
9031 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
9032 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
9033 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
9034 | ||
b8cecdf5 | 9035 | return pipe_config; |
7758a113 | 9036 | fail: |
b8cecdf5 | 9037 | kfree(pipe_config); |
e29c22c0 | 9038 | return ERR_PTR(ret); |
ee7b9f93 | 9039 | } |
47f1c6c9 | 9040 | |
e2e1ed41 DV |
9041 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
9042 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
9043 | static void | |
9044 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
9045 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
9046 | { |
9047 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
9048 | struct drm_device *dev = crtc->dev; |
9049 | struct intel_encoder *encoder; | |
9050 | struct intel_connector *connector; | |
9051 | struct drm_crtc *tmp_crtc; | |
79e53945 | 9052 | |
e2e1ed41 | 9053 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 9054 | |
e2e1ed41 DV |
9055 | /* Check which crtcs have changed outputs connected to them, these need |
9056 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
9057 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
9058 | * bit set at most. */ | |
9059 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9060 | base.head) { | |
9061 | if (connector->base.encoder == &connector->new_encoder->base) | |
9062 | continue; | |
79e53945 | 9063 | |
e2e1ed41 DV |
9064 | if (connector->base.encoder) { |
9065 | tmp_crtc = connector->base.encoder->crtc; | |
9066 | ||
9067 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9068 | } | |
9069 | ||
9070 | if (connector->new_encoder) | |
9071 | *prepare_pipes |= | |
9072 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
9073 | } |
9074 | ||
e2e1ed41 DV |
9075 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9076 | base.head) { | |
9077 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
9078 | continue; | |
9079 | ||
9080 | if (encoder->base.crtc) { | |
9081 | tmp_crtc = encoder->base.crtc; | |
9082 | ||
9083 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
9084 | } | |
9085 | ||
9086 | if (encoder->new_crtc) | |
9087 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
9088 | } |
9089 | ||
e2e1ed41 DV |
9090 | /* Check for any pipes that will be fully disabled ... */ |
9091 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
9092 | base.head) { | |
9093 | bool used = false; | |
22fd0fab | 9094 | |
e2e1ed41 DV |
9095 | /* Don't try to disable disabled crtcs. */ |
9096 | if (!intel_crtc->base.enabled) | |
9097 | continue; | |
7e7d76c3 | 9098 | |
e2e1ed41 DV |
9099 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9100 | base.head) { | |
9101 | if (encoder->new_crtc == intel_crtc) | |
9102 | used = true; | |
9103 | } | |
9104 | ||
9105 | if (!used) | |
9106 | *disable_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
9107 | } |
9108 | ||
e2e1ed41 DV |
9109 | |
9110 | /* set_mode is also used to update properties on life display pipes. */ | |
9111 | intel_crtc = to_intel_crtc(crtc); | |
9112 | if (crtc->enabled) | |
9113 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
9114 | ||
b6c5164d DV |
9115 | /* |
9116 | * For simplicity do a full modeset on any pipe where the output routing | |
9117 | * changed. We could be more clever, but that would require us to be | |
9118 | * more careful with calling the relevant encoder->mode_set functions. | |
9119 | */ | |
e2e1ed41 DV |
9120 | if (*prepare_pipes) |
9121 | *modeset_pipes = *prepare_pipes; | |
9122 | ||
9123 | /* ... and mask these out. */ | |
9124 | *modeset_pipes &= ~(*disable_pipes); | |
9125 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
9126 | |
9127 | /* | |
9128 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
9129 | * obies this rule, but the modeset restore mode of | |
9130 | * intel_modeset_setup_hw_state does not. | |
9131 | */ | |
9132 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
9133 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
9134 | |
9135 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
9136 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 9137 | } |
79e53945 | 9138 | |
ea9d758d | 9139 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 9140 | { |
ea9d758d | 9141 | struct drm_encoder *encoder; |
f6e5b160 | 9142 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 9143 | |
ea9d758d DV |
9144 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
9145 | if (encoder->crtc == crtc) | |
9146 | return true; | |
9147 | ||
9148 | return false; | |
9149 | } | |
9150 | ||
9151 | static void | |
9152 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
9153 | { | |
9154 | struct intel_encoder *intel_encoder; | |
9155 | struct intel_crtc *intel_crtc; | |
9156 | struct drm_connector *connector; | |
9157 | ||
9158 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
9159 | base.head) { | |
9160 | if (!intel_encoder->base.crtc) | |
9161 | continue; | |
9162 | ||
9163 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
9164 | ||
9165 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
9166 | intel_encoder->connectors_active = false; | |
9167 | } | |
9168 | ||
9169 | intel_modeset_commit_output_state(dev); | |
9170 | ||
9171 | /* Update computed state. */ | |
9172 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
9173 | base.head) { | |
9174 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); | |
9175 | } | |
9176 | ||
9177 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
9178 | if (!connector->encoder || !connector->encoder->crtc) | |
9179 | continue; | |
9180 | ||
9181 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
9182 | ||
9183 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
9184 | struct drm_property *dpms_property = |
9185 | dev->mode_config.dpms_property; | |
9186 | ||
ea9d758d | 9187 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 9188 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
9189 | dpms_property, |
9190 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
9191 | |
9192 | intel_encoder = to_intel_encoder(connector->encoder); | |
9193 | intel_encoder->connectors_active = true; | |
9194 | } | |
9195 | } | |
9196 | ||
9197 | } | |
9198 | ||
3bd26263 | 9199 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 9200 | { |
3bd26263 | 9201 | int diff; |
f1f644dc JB |
9202 | |
9203 | if (clock1 == clock2) | |
9204 | return true; | |
9205 | ||
9206 | if (!clock1 || !clock2) | |
9207 | return false; | |
9208 | ||
9209 | diff = abs(clock1 - clock2); | |
9210 | ||
9211 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
9212 | return true; | |
9213 | ||
9214 | return false; | |
9215 | } | |
9216 | ||
25c5b266 DV |
9217 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
9218 | list_for_each_entry((intel_crtc), \ | |
9219 | &(dev)->mode_config.crtc_list, \ | |
9220 | base.head) \ | |
0973f18f | 9221 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 9222 | |
0e8ffe1b | 9223 | static bool |
2fa2fe9a DV |
9224 | intel_pipe_config_compare(struct drm_device *dev, |
9225 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
9226 | struct intel_crtc_config *pipe_config) |
9227 | { | |
66e985c0 DV |
9228 | #define PIPE_CONF_CHECK_X(name) \ |
9229 | if (current_config->name != pipe_config->name) { \ | |
9230 | DRM_ERROR("mismatch in " #name " " \ | |
9231 | "(expected 0x%08x, found 0x%08x)\n", \ | |
9232 | current_config->name, \ | |
9233 | pipe_config->name); \ | |
9234 | return false; \ | |
9235 | } | |
9236 | ||
08a24034 DV |
9237 | #define PIPE_CONF_CHECK_I(name) \ |
9238 | if (current_config->name != pipe_config->name) { \ | |
9239 | DRM_ERROR("mismatch in " #name " " \ | |
9240 | "(expected %i, found %i)\n", \ | |
9241 | current_config->name, \ | |
9242 | pipe_config->name); \ | |
9243 | return false; \ | |
88adfff1 DV |
9244 | } |
9245 | ||
1bd1bd80 DV |
9246 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
9247 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 9248 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
9249 | "(expected %i, found %i)\n", \ |
9250 | current_config->name & (mask), \ | |
9251 | pipe_config->name & (mask)); \ | |
9252 | return false; \ | |
9253 | } | |
9254 | ||
5e550656 VS |
9255 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
9256 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
9257 | DRM_ERROR("mismatch in " #name " " \ | |
9258 | "(expected %i, found %i)\n", \ | |
9259 | current_config->name, \ | |
9260 | pipe_config->name); \ | |
9261 | return false; \ | |
9262 | } | |
9263 | ||
bb760063 DV |
9264 | #define PIPE_CONF_QUIRK(quirk) \ |
9265 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
9266 | ||
eccb140b DV |
9267 | PIPE_CONF_CHECK_I(cpu_transcoder); |
9268 | ||
08a24034 DV |
9269 | PIPE_CONF_CHECK_I(has_pch_encoder); |
9270 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
9271 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
9272 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
9273 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
9274 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
9275 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 9276 | |
eb14cb74 VS |
9277 | PIPE_CONF_CHECK_I(has_dp_encoder); |
9278 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
9279 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
9280 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
9281 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
9282 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
9283 | ||
1bd1bd80 DV |
9284 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
9285 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
9286 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
9287 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
9288 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
9289 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
9290 | ||
9291 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
9292 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
9293 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
9294 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
9295 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
9296 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
9297 | ||
c93f54cf | 9298 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6c49f241 | 9299 | |
1bd1bd80 DV |
9300 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
9301 | DRM_MODE_FLAG_INTERLACE); | |
9302 | ||
bb760063 DV |
9303 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
9304 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9305 | DRM_MODE_FLAG_PHSYNC); | |
9306 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9307 | DRM_MODE_FLAG_NHSYNC); | |
9308 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9309 | DRM_MODE_FLAG_PVSYNC); | |
9310 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
9311 | DRM_MODE_FLAG_NVSYNC); | |
9312 | } | |
045ac3b5 | 9313 | |
37327abd VS |
9314 | PIPE_CONF_CHECK_I(pipe_src_w); |
9315 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 9316 | |
2fa2fe9a DV |
9317 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
9318 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
9319 | if (INTEL_INFO(dev)->gen < 4) | |
9320 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
9321 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
fd4daa9c CW |
9322 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
9323 | if (current_config->pch_pfit.enabled) { | |
9324 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
9325 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
9326 | } | |
2fa2fe9a | 9327 | |
42db64ef PZ |
9328 | PIPE_CONF_CHECK_I(ips_enabled); |
9329 | ||
282740f7 VS |
9330 | PIPE_CONF_CHECK_I(double_wide); |
9331 | ||
c0d43d62 | 9332 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 9333 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 9334 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
9335 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
9336 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
c0d43d62 | 9337 | |
42571aef VS |
9338 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
9339 | PIPE_CONF_CHECK_I(pipe_bpp); | |
9340 | ||
d71b8d4a | 9341 | if (!IS_HASWELL(dev)) { |
241bfc38 | 9342 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
d71b8d4a VS |
9343 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
9344 | } | |
5e550656 | 9345 | |
66e985c0 | 9346 | #undef PIPE_CONF_CHECK_X |
08a24034 | 9347 | #undef PIPE_CONF_CHECK_I |
1bd1bd80 | 9348 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 9349 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 9350 | #undef PIPE_CONF_QUIRK |
88adfff1 | 9351 | |
0e8ffe1b DV |
9352 | return true; |
9353 | } | |
9354 | ||
91d1b4bd DV |
9355 | static void |
9356 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 9357 | { |
8af6cf88 DV |
9358 | struct intel_connector *connector; |
9359 | ||
9360 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9361 | base.head) { | |
9362 | /* This also checks the encoder/connector hw state with the | |
9363 | * ->get_hw_state callbacks. */ | |
9364 | intel_connector_check_state(connector); | |
9365 | ||
9366 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
9367 | "connector's staged encoder doesn't match current encoder\n"); | |
9368 | } | |
91d1b4bd DV |
9369 | } |
9370 | ||
9371 | static void | |
9372 | check_encoder_state(struct drm_device *dev) | |
9373 | { | |
9374 | struct intel_encoder *encoder; | |
9375 | struct intel_connector *connector; | |
8af6cf88 DV |
9376 | |
9377 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9378 | base.head) { | |
9379 | bool enabled = false; | |
9380 | bool active = false; | |
9381 | enum pipe pipe, tracked_pipe; | |
9382 | ||
9383 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
9384 | encoder->base.base.id, | |
9385 | drm_get_encoder_name(&encoder->base)); | |
9386 | ||
9387 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
9388 | "encoder's stage crtc doesn't match current crtc\n"); | |
9389 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
9390 | "encoder's active_connectors set, but no crtc\n"); | |
9391 | ||
9392 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
9393 | base.head) { | |
9394 | if (connector->base.encoder != &encoder->base) | |
9395 | continue; | |
9396 | enabled = true; | |
9397 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
9398 | active = true; | |
9399 | } | |
9400 | WARN(!!encoder->base.crtc != enabled, | |
9401 | "encoder's enabled state mismatch " | |
9402 | "(expected %i, found %i)\n", | |
9403 | !!encoder->base.crtc, enabled); | |
9404 | WARN(active && !encoder->base.crtc, | |
9405 | "active encoder with no crtc\n"); | |
9406 | ||
9407 | WARN(encoder->connectors_active != active, | |
9408 | "encoder's computed active state doesn't match tracked active state " | |
9409 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
9410 | ||
9411 | active = encoder->get_hw_state(encoder, &pipe); | |
9412 | WARN(active != encoder->connectors_active, | |
9413 | "encoder's hw state doesn't match sw tracking " | |
9414 | "(expected %i, found %i)\n", | |
9415 | encoder->connectors_active, active); | |
9416 | ||
9417 | if (!encoder->base.crtc) | |
9418 | continue; | |
9419 | ||
9420 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
9421 | WARN(active && pipe != tracked_pipe, | |
9422 | "active encoder's pipe doesn't match" | |
9423 | "(expected %i, found %i)\n", | |
9424 | tracked_pipe, pipe); | |
9425 | ||
9426 | } | |
91d1b4bd DV |
9427 | } |
9428 | ||
9429 | static void | |
9430 | check_crtc_state(struct drm_device *dev) | |
9431 | { | |
9432 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9433 | struct intel_crtc *crtc; | |
9434 | struct intel_encoder *encoder; | |
9435 | struct intel_crtc_config pipe_config; | |
8af6cf88 DV |
9436 | |
9437 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9438 | base.head) { | |
9439 | bool enabled = false; | |
9440 | bool active = false; | |
9441 | ||
045ac3b5 JB |
9442 | memset(&pipe_config, 0, sizeof(pipe_config)); |
9443 | ||
8af6cf88 DV |
9444 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
9445 | crtc->base.base.id); | |
9446 | ||
9447 | WARN(crtc->active && !crtc->base.enabled, | |
9448 | "active crtc, but not enabled in sw tracking\n"); | |
9449 | ||
9450 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9451 | base.head) { | |
9452 | if (encoder->base.crtc != &crtc->base) | |
9453 | continue; | |
9454 | enabled = true; | |
9455 | if (encoder->connectors_active) | |
9456 | active = true; | |
9457 | } | |
6c49f241 | 9458 | |
8af6cf88 DV |
9459 | WARN(active != crtc->active, |
9460 | "crtc's computed active state doesn't match tracked active state " | |
9461 | "(expected %i, found %i)\n", active, crtc->active); | |
9462 | WARN(enabled != crtc->base.enabled, | |
9463 | "crtc's computed enabled state doesn't match tracked enabled state " | |
9464 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
9465 | ||
0e8ffe1b DV |
9466 | active = dev_priv->display.get_pipe_config(crtc, |
9467 | &pipe_config); | |
d62cf62a DV |
9468 | |
9469 | /* hw state is inconsistent with the pipe A quirk */ | |
9470 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
9471 | active = crtc->active; | |
9472 | ||
6c49f241 DV |
9473 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
9474 | base.head) { | |
3eaba51c | 9475 | enum pipe pipe; |
6c49f241 DV |
9476 | if (encoder->base.crtc != &crtc->base) |
9477 | continue; | |
1d37b689 | 9478 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
9479 | encoder->get_config(encoder, &pipe_config); |
9480 | } | |
9481 | ||
0e8ffe1b DV |
9482 | WARN(crtc->active != active, |
9483 | "crtc active state doesn't match with hw state " | |
9484 | "(expected %i, found %i)\n", crtc->active, active); | |
9485 | ||
c0b03411 DV |
9486 | if (active && |
9487 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
9488 | WARN(1, "pipe state doesn't match!\n"); | |
9489 | intel_dump_pipe_config(crtc, &pipe_config, | |
9490 | "[hw state]"); | |
9491 | intel_dump_pipe_config(crtc, &crtc->config, | |
9492 | "[sw state]"); | |
9493 | } | |
8af6cf88 DV |
9494 | } |
9495 | } | |
9496 | ||
91d1b4bd DV |
9497 | static void |
9498 | check_shared_dpll_state(struct drm_device *dev) | |
9499 | { | |
9500 | drm_i915_private_t *dev_priv = dev->dev_private; | |
9501 | struct intel_crtc *crtc; | |
9502 | struct intel_dpll_hw_state dpll_hw_state; | |
9503 | int i; | |
5358901f DV |
9504 | |
9505 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
9506 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
9507 | int enabled_crtcs = 0, active_crtcs = 0; | |
9508 | bool active; | |
9509 | ||
9510 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
9511 | ||
9512 | DRM_DEBUG_KMS("%s\n", pll->name); | |
9513 | ||
9514 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
9515 | ||
9516 | WARN(pll->active > pll->refcount, | |
9517 | "more active pll users than references: %i vs %i\n", | |
9518 | pll->active, pll->refcount); | |
9519 | WARN(pll->active && !pll->on, | |
9520 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
9521 | WARN(pll->on && !pll->active, |
9522 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
9523 | WARN(pll->on != active, |
9524 | "pll on state mismatch (expected %i, found %i)\n", | |
9525 | pll->on, active); | |
9526 | ||
9527 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9528 | base.head) { | |
9529 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) | |
9530 | enabled_crtcs++; | |
9531 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
9532 | active_crtcs++; | |
9533 | } | |
9534 | WARN(pll->active != active_crtcs, | |
9535 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
9536 | pll->active, active_crtcs); | |
9537 | WARN(pll->refcount != enabled_crtcs, | |
9538 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
9539 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
9540 | |
9541 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
9542 | sizeof(dpll_hw_state)), | |
9543 | "pll hw state mismatch\n"); | |
5358901f | 9544 | } |
8af6cf88 DV |
9545 | } |
9546 | ||
91d1b4bd DV |
9547 | void |
9548 | intel_modeset_check_state(struct drm_device *dev) | |
9549 | { | |
9550 | check_connector_state(dev); | |
9551 | check_encoder_state(dev); | |
9552 | check_crtc_state(dev); | |
9553 | check_shared_dpll_state(dev); | |
9554 | } | |
9555 | ||
18442d08 VS |
9556 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
9557 | int dotclock) | |
9558 | { | |
9559 | /* | |
9560 | * FDI already provided one idea for the dotclock. | |
9561 | * Yell if the encoder disagrees. | |
9562 | */ | |
241bfc38 | 9563 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 9564 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 9565 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
9566 | } |
9567 | ||
f30da187 DV |
9568 | static int __intel_set_mode(struct drm_crtc *crtc, |
9569 | struct drm_display_mode *mode, | |
9570 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
9571 | { |
9572 | struct drm_device *dev = crtc->dev; | |
dbf2b54e | 9573 | drm_i915_private_t *dev_priv = dev->dev_private; |
b8cecdf5 DV |
9574 | struct drm_display_mode *saved_mode, *saved_hwmode; |
9575 | struct intel_crtc_config *pipe_config = NULL; | |
25c5b266 DV |
9576 | struct intel_crtc *intel_crtc; |
9577 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 9578 | int ret = 0; |
a6778b3c | 9579 | |
a1e22653 | 9580 | saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
9581 | if (!saved_mode) |
9582 | return -ENOMEM; | |
3ac18232 | 9583 | saved_hwmode = saved_mode + 1; |
a6778b3c | 9584 | |
e2e1ed41 | 9585 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
9586 | &prepare_pipes, &disable_pipes); |
9587 | ||
3ac18232 TG |
9588 | *saved_hwmode = crtc->hwmode; |
9589 | *saved_mode = crtc->mode; | |
a6778b3c | 9590 | |
25c5b266 DV |
9591 | /* Hack: Because we don't (yet) support global modeset on multiple |
9592 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
9593 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
9594 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
9595 | * changing their mode at the same time. */ | |
25c5b266 | 9596 | if (modeset_pipes) { |
4e53c2e0 | 9597 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
9598 | if (IS_ERR(pipe_config)) { |
9599 | ret = PTR_ERR(pipe_config); | |
9600 | pipe_config = NULL; | |
9601 | ||
3ac18232 | 9602 | goto out; |
25c5b266 | 9603 | } |
c0b03411 DV |
9604 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
9605 | "[modeset]"); | |
25c5b266 | 9606 | } |
a6778b3c | 9607 | |
30a970c6 JB |
9608 | /* |
9609 | * See if the config requires any additional preparation, e.g. | |
9610 | * to adjust global state with pipes off. We need to do this | |
9611 | * here so we can get the modeset_pipe updated config for the new | |
9612 | * mode set on this crtc. For other crtcs we need to use the | |
9613 | * adjusted_mode bits in the crtc directly. | |
9614 | */ | |
c164f833 | 9615 | if (IS_VALLEYVIEW(dev)) { |
30a970c6 JB |
9616 | valleyview_modeset_global_pipes(dev, &prepare_pipes, |
9617 | modeset_pipes, pipe_config); | |
9618 | ||
c164f833 VS |
9619 | /* may have added more to prepare_pipes than we should */ |
9620 | prepare_pipes &= ~disable_pipes; | |
9621 | } | |
9622 | ||
460da916 DV |
9623 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
9624 | intel_crtc_disable(&intel_crtc->base); | |
9625 | ||
ea9d758d DV |
9626 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
9627 | if (intel_crtc->base.enabled) | |
9628 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
9629 | } | |
a6778b3c | 9630 | |
6c4c86f5 DV |
9631 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
9632 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 9633 | */ |
b8cecdf5 | 9634 | if (modeset_pipes) { |
25c5b266 | 9635 | crtc->mode = *mode; |
b8cecdf5 DV |
9636 | /* mode_set/enable/disable functions rely on a correct pipe |
9637 | * config. */ | |
9638 | to_intel_crtc(crtc)->config = *pipe_config; | |
9639 | } | |
7758a113 | 9640 | |
ea9d758d DV |
9641 | /* Only after disabling all output pipelines that will be changed can we |
9642 | * update the the output configuration. */ | |
9643 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 9644 | |
47fab737 DV |
9645 | if (dev_priv->display.modeset_global_resources) |
9646 | dev_priv->display.modeset_global_resources(dev); | |
9647 | ||
a6778b3c DV |
9648 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
9649 | * on the DPLL. | |
f6e5b160 | 9650 | */ |
25c5b266 | 9651 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
c0c36b94 | 9652 | ret = intel_crtc_mode_set(&intel_crtc->base, |
c0c36b94 CW |
9653 | x, y, fb); |
9654 | if (ret) | |
9655 | goto done; | |
a6778b3c DV |
9656 | } |
9657 | ||
9658 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
25c5b266 DV |
9659 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
9660 | dev_priv->display.crtc_enable(&intel_crtc->base); | |
a6778b3c | 9661 | |
25c5b266 DV |
9662 | if (modeset_pipes) { |
9663 | /* Store real post-adjustment hardware mode. */ | |
b8cecdf5 | 9664 | crtc->hwmode = pipe_config->adjusted_mode; |
a6778b3c | 9665 | |
25c5b266 DV |
9666 | /* Calculate and store various constants which |
9667 | * are later needed by vblank and swap-completion | |
9668 | * timestamping. They are derived from true hwmode. | |
9669 | */ | |
9670 | drm_calc_timestamping_constants(crtc); | |
9671 | } | |
a6778b3c DV |
9672 | |
9673 | /* FIXME: add subpixel order */ | |
9674 | done: | |
c0c36b94 | 9675 | if (ret && crtc->enabled) { |
3ac18232 TG |
9676 | crtc->hwmode = *saved_hwmode; |
9677 | crtc->mode = *saved_mode; | |
a6778b3c DV |
9678 | } |
9679 | ||
3ac18232 | 9680 | out: |
b8cecdf5 | 9681 | kfree(pipe_config); |
3ac18232 | 9682 | kfree(saved_mode); |
a6778b3c | 9683 | return ret; |
f6e5b160 CW |
9684 | } |
9685 | ||
e7457a9a DL |
9686 | static int intel_set_mode(struct drm_crtc *crtc, |
9687 | struct drm_display_mode *mode, | |
9688 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
9689 | { |
9690 | int ret; | |
9691 | ||
9692 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
9693 | ||
9694 | if (ret == 0) | |
9695 | intel_modeset_check_state(crtc->dev); | |
9696 | ||
9697 | return ret; | |
9698 | } | |
9699 | ||
c0c36b94 CW |
9700 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
9701 | { | |
9702 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); | |
9703 | } | |
9704 | ||
25c5b266 DV |
9705 | #undef for_each_intel_crtc_masked |
9706 | ||
d9e55608 DV |
9707 | static void intel_set_config_free(struct intel_set_config *config) |
9708 | { | |
9709 | if (!config) | |
9710 | return; | |
9711 | ||
1aa4b628 DV |
9712 | kfree(config->save_connector_encoders); |
9713 | kfree(config->save_encoder_crtcs); | |
d9e55608 DV |
9714 | kfree(config); |
9715 | } | |
9716 | ||
85f9eb71 DV |
9717 | static int intel_set_config_save_state(struct drm_device *dev, |
9718 | struct intel_set_config *config) | |
9719 | { | |
85f9eb71 DV |
9720 | struct drm_encoder *encoder; |
9721 | struct drm_connector *connector; | |
9722 | int count; | |
9723 | ||
1aa4b628 DV |
9724 | config->save_encoder_crtcs = |
9725 | kcalloc(dev->mode_config.num_encoder, | |
9726 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
9727 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
9728 | return -ENOMEM; |
9729 | ||
1aa4b628 DV |
9730 | config->save_connector_encoders = |
9731 | kcalloc(dev->mode_config.num_connector, | |
9732 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
9733 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
9734 | return -ENOMEM; |
9735 | ||
9736 | /* Copy data. Note that driver private data is not affected. | |
9737 | * Should anything bad happen only the expected state is | |
9738 | * restored, not the drivers personal bookkeeping. | |
9739 | */ | |
85f9eb71 DV |
9740 | count = 0; |
9741 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 9742 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
9743 | } |
9744 | ||
9745 | count = 0; | |
9746 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 9747 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
9748 | } |
9749 | ||
9750 | return 0; | |
9751 | } | |
9752 | ||
9753 | static void intel_set_config_restore_state(struct drm_device *dev, | |
9754 | struct intel_set_config *config) | |
9755 | { | |
9a935856 DV |
9756 | struct intel_encoder *encoder; |
9757 | struct intel_connector *connector; | |
85f9eb71 DV |
9758 | int count; |
9759 | ||
85f9eb71 | 9760 | count = 0; |
9a935856 DV |
9761 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9762 | encoder->new_crtc = | |
9763 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
9764 | } |
9765 | ||
9766 | count = 0; | |
9a935856 DV |
9767 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
9768 | connector->new_encoder = | |
9769 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
9770 | } |
9771 | } | |
9772 | ||
e3de42b6 | 9773 | static bool |
2e57f47d | 9774 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
9775 | { |
9776 | int i; | |
9777 | ||
2e57f47d CW |
9778 | if (set->num_connectors == 0) |
9779 | return false; | |
9780 | ||
9781 | if (WARN_ON(set->connectors == NULL)) | |
9782 | return false; | |
9783 | ||
9784 | for (i = 0; i < set->num_connectors; i++) | |
9785 | if (set->connectors[i]->encoder && | |
9786 | set->connectors[i]->encoder->crtc == set->crtc && | |
9787 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
9788 | return true; |
9789 | ||
9790 | return false; | |
9791 | } | |
9792 | ||
5e2b584e DV |
9793 | static void |
9794 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
9795 | struct intel_set_config *config) | |
9796 | { | |
9797 | ||
9798 | /* We should be able to check here if the fb has the same properties | |
9799 | * and then just flip_or_move it */ | |
2e57f47d CW |
9800 | if (is_crtc_connector_off(set)) { |
9801 | config->mode_changed = true; | |
e3de42b6 | 9802 | } else if (set->crtc->fb != set->fb) { |
5e2b584e DV |
9803 | /* If we have no fb then treat it as a full mode set */ |
9804 | if (set->crtc->fb == NULL) { | |
319d9827 JB |
9805 | struct intel_crtc *intel_crtc = |
9806 | to_intel_crtc(set->crtc); | |
9807 | ||
9808 | if (intel_crtc->active && i915_fastboot) { | |
9809 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); | |
9810 | config->fb_changed = true; | |
9811 | } else { | |
9812 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
9813 | config->mode_changed = true; | |
9814 | } | |
5e2b584e DV |
9815 | } else if (set->fb == NULL) { |
9816 | config->mode_changed = true; | |
72f4901e DV |
9817 | } else if (set->fb->pixel_format != |
9818 | set->crtc->fb->pixel_format) { | |
5e2b584e | 9819 | config->mode_changed = true; |
e3de42b6 | 9820 | } else { |
5e2b584e | 9821 | config->fb_changed = true; |
e3de42b6 | 9822 | } |
5e2b584e DV |
9823 | } |
9824 | ||
835c5873 | 9825 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
9826 | config->fb_changed = true; |
9827 | ||
9828 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
9829 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
9830 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
9831 | drm_mode_debug_printmodeline(set->mode); | |
9832 | config->mode_changed = true; | |
9833 | } | |
a1d95703 CW |
9834 | |
9835 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
9836 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
9837 | } |
9838 | ||
2e431051 | 9839 | static int |
9a935856 DV |
9840 | intel_modeset_stage_output_state(struct drm_device *dev, |
9841 | struct drm_mode_set *set, | |
9842 | struct intel_set_config *config) | |
50f56119 | 9843 | { |
85f9eb71 | 9844 | struct drm_crtc *new_crtc; |
9a935856 DV |
9845 | struct intel_connector *connector; |
9846 | struct intel_encoder *encoder; | |
f3f08572 | 9847 | int ro; |
50f56119 | 9848 | |
9abdda74 | 9849 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
9850 | * of connectors. For paranoia, double-check this. */ |
9851 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
9852 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
9853 | ||
9a935856 DV |
9854 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9855 | base.head) { | |
9856 | /* Otherwise traverse passed in connector list and get encoders | |
9857 | * for them. */ | |
50f56119 | 9858 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
9859 | if (set->connectors[ro] == &connector->base) { |
9860 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
9861 | break; |
9862 | } | |
9863 | } | |
9864 | ||
9a935856 DV |
9865 | /* If we disable the crtc, disable all its connectors. Also, if |
9866 | * the connector is on the changing crtc but not on the new | |
9867 | * connector list, disable it. */ | |
9868 | if ((!set->fb || ro == set->num_connectors) && | |
9869 | connector->base.encoder && | |
9870 | connector->base.encoder->crtc == set->crtc) { | |
9871 | connector->new_encoder = NULL; | |
9872 | ||
9873 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
9874 | connector->base.base.id, | |
9875 | drm_get_connector_name(&connector->base)); | |
9876 | } | |
9877 | ||
9878 | ||
9879 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 9880 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 9881 | config->mode_changed = true; |
50f56119 DV |
9882 | } |
9883 | } | |
9a935856 | 9884 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 9885 | |
9a935856 | 9886 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
9887 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9888 | base.head) { | |
9889 | if (!connector->new_encoder) | |
50f56119 DV |
9890 | continue; |
9891 | ||
9a935856 | 9892 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
9893 | |
9894 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 9895 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
9896 | new_crtc = set->crtc; |
9897 | } | |
9898 | ||
9899 | /* Make sure the new CRTC will work with the encoder */ | |
9a935856 DV |
9900 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
9901 | new_crtc)) { | |
5e2b584e | 9902 | return -EINVAL; |
50f56119 | 9903 | } |
9a935856 DV |
9904 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
9905 | ||
9906 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
9907 | connector->base.base.id, | |
9908 | drm_get_connector_name(&connector->base), | |
9909 | new_crtc->base.id); | |
9910 | } | |
9911 | ||
9912 | /* Check for any encoders that needs to be disabled. */ | |
9913 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9914 | base.head) { | |
9915 | list_for_each_entry(connector, | |
9916 | &dev->mode_config.connector_list, | |
9917 | base.head) { | |
9918 | if (connector->new_encoder == encoder) { | |
9919 | WARN_ON(!connector->new_encoder->new_crtc); | |
9920 | ||
9921 | goto next_encoder; | |
9922 | } | |
9923 | } | |
9924 | encoder->new_crtc = NULL; | |
9925 | next_encoder: | |
9926 | /* Only now check for crtc changes so we don't miss encoders | |
9927 | * that will be disabled. */ | |
9928 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 9929 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 9930 | config->mode_changed = true; |
50f56119 DV |
9931 | } |
9932 | } | |
9a935856 | 9933 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 9934 | |
2e431051 DV |
9935 | return 0; |
9936 | } | |
9937 | ||
9938 | static int intel_crtc_set_config(struct drm_mode_set *set) | |
9939 | { | |
9940 | struct drm_device *dev; | |
2e431051 DV |
9941 | struct drm_mode_set save_set; |
9942 | struct intel_set_config *config; | |
9943 | int ret; | |
2e431051 | 9944 | |
8d3e375e DV |
9945 | BUG_ON(!set); |
9946 | BUG_ON(!set->crtc); | |
9947 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 9948 | |
7e53f3a4 DV |
9949 | /* Enforce sane interface api - has been abused by the fb helper. */ |
9950 | BUG_ON(!set->mode && set->fb); | |
9951 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 9952 | |
2e431051 DV |
9953 | if (set->fb) { |
9954 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
9955 | set->crtc->base.id, set->fb->base.id, | |
9956 | (int)set->num_connectors, set->x, set->y); | |
9957 | } else { | |
9958 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
9959 | } |
9960 | ||
9961 | dev = set->crtc->dev; | |
9962 | ||
9963 | ret = -ENOMEM; | |
9964 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
9965 | if (!config) | |
9966 | goto out_config; | |
9967 | ||
9968 | ret = intel_set_config_save_state(dev, config); | |
9969 | if (ret) | |
9970 | goto out_config; | |
9971 | ||
9972 | save_set.crtc = set->crtc; | |
9973 | save_set.mode = &set->crtc->mode; | |
9974 | save_set.x = set->crtc->x; | |
9975 | save_set.y = set->crtc->y; | |
9976 | save_set.fb = set->crtc->fb; | |
9977 | ||
9978 | /* Compute whether we need a full modeset, only an fb base update or no | |
9979 | * change at all. In the future we might also check whether only the | |
9980 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
9981 | * such cases. */ | |
9982 | intel_set_config_compute_mode_changes(set, config); | |
9983 | ||
9a935856 | 9984 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
9985 | if (ret) |
9986 | goto fail; | |
9987 | ||
5e2b584e | 9988 | if (config->mode_changed) { |
c0c36b94 CW |
9989 | ret = intel_set_mode(set->crtc, set->mode, |
9990 | set->x, set->y, set->fb); | |
5e2b584e | 9991 | } else if (config->fb_changed) { |
4878cae2 VS |
9992 | intel_crtc_wait_for_pending_flips(set->crtc); |
9993 | ||
4f660f49 | 9994 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 9995 | set->x, set->y, set->fb); |
50f56119 DV |
9996 | } |
9997 | ||
2d05eae1 | 9998 | if (ret) { |
bf67dfeb DV |
9999 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
10000 | set->crtc->base.id, ret); | |
50f56119 | 10001 | fail: |
2d05eae1 | 10002 | intel_set_config_restore_state(dev, config); |
50f56119 | 10003 | |
2d05eae1 CW |
10004 | /* Try to restore the config */ |
10005 | if (config->mode_changed && | |
10006 | intel_set_mode(save_set.crtc, save_set.mode, | |
10007 | save_set.x, save_set.y, save_set.fb)) | |
10008 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
10009 | } | |
50f56119 | 10010 | |
d9e55608 DV |
10011 | out_config: |
10012 | intel_set_config_free(config); | |
50f56119 DV |
10013 | return ret; |
10014 | } | |
f6e5b160 CW |
10015 | |
10016 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 CW |
10017 | .cursor_set = intel_crtc_cursor_set, |
10018 | .cursor_move = intel_crtc_cursor_move, | |
10019 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 10020 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
10021 | .destroy = intel_crtc_destroy, |
10022 | .page_flip = intel_crtc_page_flip, | |
10023 | }; | |
10024 | ||
79f689aa PZ |
10025 | static void intel_cpu_pll_init(struct drm_device *dev) |
10026 | { | |
affa9354 | 10027 | if (HAS_DDI(dev)) |
79f689aa PZ |
10028 | intel_ddi_pll_init(dev); |
10029 | } | |
10030 | ||
5358901f DV |
10031 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
10032 | struct intel_shared_dpll *pll, | |
10033 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 10034 | { |
5358901f | 10035 | uint32_t val; |
ee7b9f93 | 10036 | |
5358901f | 10037 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
10038 | hw_state->dpll = val; |
10039 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
10040 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
10041 | |
10042 | return val & DPLL_VCO_ENABLE; | |
10043 | } | |
10044 | ||
15bdd4cf DV |
10045 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
10046 | struct intel_shared_dpll *pll) | |
10047 | { | |
10048 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
10049 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
10050 | } | |
10051 | ||
e7b903d2 DV |
10052 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
10053 | struct intel_shared_dpll *pll) | |
10054 | { | |
e7b903d2 DV |
10055 | /* PCH refclock must be enabled first */ |
10056 | assert_pch_refclk_enabled(dev_priv); | |
10057 | ||
15bdd4cf DV |
10058 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
10059 | ||
10060 | /* Wait for the clocks to stabilize. */ | |
10061 | POSTING_READ(PCH_DPLL(pll->id)); | |
10062 | udelay(150); | |
10063 | ||
10064 | /* The pixel multiplier can only be updated once the | |
10065 | * DPLL is enabled and the clocks are stable. | |
10066 | * | |
10067 | * So write it again. | |
10068 | */ | |
10069 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
10070 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10071 | udelay(200); |
10072 | } | |
10073 | ||
10074 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
10075 | struct intel_shared_dpll *pll) | |
10076 | { | |
10077 | struct drm_device *dev = dev_priv->dev; | |
10078 | struct intel_crtc *crtc; | |
e7b903d2 DV |
10079 | |
10080 | /* Make sure no transcoder isn't still depending on us. */ | |
10081 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
10082 | if (intel_crtc_to_shared_dpll(crtc) == pll) | |
10083 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
10084 | } |
10085 | ||
15bdd4cf DV |
10086 | I915_WRITE(PCH_DPLL(pll->id), 0); |
10087 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
10088 | udelay(200); |
10089 | } | |
10090 | ||
46edb027 DV |
10091 | static char *ibx_pch_dpll_names[] = { |
10092 | "PCH DPLL A", | |
10093 | "PCH DPLL B", | |
10094 | }; | |
10095 | ||
7c74ade1 | 10096 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 10097 | { |
e7b903d2 | 10098 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
10099 | int i; |
10100 | ||
7c74ade1 | 10101 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 10102 | |
e72f9fbf | 10103 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
10104 | dev_priv->shared_dplls[i].id = i; |
10105 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 10106 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
10107 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
10108 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
10109 | dev_priv->shared_dplls[i].get_hw_state = |
10110 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
10111 | } |
10112 | } | |
10113 | ||
7c74ade1 DV |
10114 | static void intel_shared_dpll_init(struct drm_device *dev) |
10115 | { | |
e7b903d2 | 10116 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 DV |
10117 | |
10118 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
10119 | ibx_pch_dpll_init(dev); | |
10120 | else | |
10121 | dev_priv->num_shared_dpll = 0; | |
10122 | ||
10123 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
10124 | DRM_DEBUG_KMS("%i shared PLLs initialized\n", | |
10125 | dev_priv->num_shared_dpll); | |
10126 | } | |
10127 | ||
b358d0a6 | 10128 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 10129 | { |
22fd0fab | 10130 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
10131 | struct intel_crtc *intel_crtc; |
10132 | int i; | |
10133 | ||
955382f3 | 10134 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
10135 | if (intel_crtc == NULL) |
10136 | return; | |
10137 | ||
10138 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
10139 | ||
10140 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
10141 | for (i = 0; i < 256; i++) { |
10142 | intel_crtc->lut_r[i] = i; | |
10143 | intel_crtc->lut_g[i] = i; | |
10144 | intel_crtc->lut_b[i] = i; | |
10145 | } | |
10146 | ||
1f1c2e24 VS |
10147 | /* |
10148 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
10149 | * is hooked to plane B. Hence we want plane A feeding pipe B. | |
10150 | */ | |
80824003 JB |
10151 | intel_crtc->pipe = pipe; |
10152 | intel_crtc->plane = pipe; | |
1f1c2e24 | 10153 | if (IS_MOBILE(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 10154 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 10155 | intel_crtc->plane = !pipe; |
80824003 JB |
10156 | } |
10157 | ||
22fd0fab JB |
10158 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
10159 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
10160 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
10161 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
10162 | ||
79e53945 | 10163 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
79e53945 JB |
10164 | } |
10165 | ||
752aa88a JB |
10166 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
10167 | { | |
10168 | struct drm_encoder *encoder = connector->base.encoder; | |
10169 | ||
10170 | WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex)); | |
10171 | ||
10172 | if (!encoder) | |
10173 | return INVALID_PIPE; | |
10174 | ||
10175 | return to_intel_crtc(encoder->crtc)->pipe; | |
10176 | } | |
10177 | ||
08d7b3d1 | 10178 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 10179 | struct drm_file *file) |
08d7b3d1 | 10180 | { |
08d7b3d1 | 10181 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
10182 | struct drm_mode_object *drmmode_obj; |
10183 | struct intel_crtc *crtc; | |
08d7b3d1 | 10184 | |
1cff8f6b DV |
10185 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
10186 | return -ENODEV; | |
08d7b3d1 | 10187 | |
c05422d5 DV |
10188 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
10189 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 10190 | |
c05422d5 | 10191 | if (!drmmode_obj) { |
08d7b3d1 | 10192 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 10193 | return -ENOENT; |
08d7b3d1 CW |
10194 | } |
10195 | ||
c05422d5 DV |
10196 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
10197 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 10198 | |
c05422d5 | 10199 | return 0; |
08d7b3d1 CW |
10200 | } |
10201 | ||
66a9278e | 10202 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 10203 | { |
66a9278e DV |
10204 | struct drm_device *dev = encoder->base.dev; |
10205 | struct intel_encoder *source_encoder; | |
79e53945 | 10206 | int index_mask = 0; |
79e53945 JB |
10207 | int entry = 0; |
10208 | ||
66a9278e DV |
10209 | list_for_each_entry(source_encoder, |
10210 | &dev->mode_config.encoder_list, base.head) { | |
10211 | ||
10212 | if (encoder == source_encoder) | |
79e53945 | 10213 | index_mask |= (1 << entry); |
66a9278e DV |
10214 | |
10215 | /* Intel hw has only one MUX where enocoders could be cloned. */ | |
10216 | if (encoder->cloneable && source_encoder->cloneable) | |
10217 | index_mask |= (1 << entry); | |
10218 | ||
79e53945 JB |
10219 | entry++; |
10220 | } | |
4ef69c7a | 10221 | |
79e53945 JB |
10222 | return index_mask; |
10223 | } | |
10224 | ||
4d302442 CW |
10225 | static bool has_edp_a(struct drm_device *dev) |
10226 | { | |
10227 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10228 | ||
10229 | if (!IS_MOBILE(dev)) | |
10230 | return false; | |
10231 | ||
10232 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
10233 | return false; | |
10234 | ||
10235 | if (IS_GEN5(dev) && | |
10236 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
10237 | return false; | |
10238 | ||
10239 | return true; | |
10240 | } | |
10241 | ||
79e53945 JB |
10242 | static void intel_setup_outputs(struct drm_device *dev) |
10243 | { | |
725e30ad | 10244 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 10245 | struct intel_encoder *encoder; |
cb0953d7 | 10246 | bool dpd_is_edp = false; |
79e53945 | 10247 | |
c9093354 | 10248 | intel_lvds_init(dev); |
79e53945 | 10249 | |
c40c0f5b | 10250 | if (!IS_ULT(dev)) |
79935fca | 10251 | intel_crt_init(dev); |
cb0953d7 | 10252 | |
affa9354 | 10253 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
10254 | int found; |
10255 | ||
10256 | /* Haswell uses DDI functions to detect digital outputs */ | |
10257 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
10258 | /* DDI A only supports eDP */ | |
10259 | if (found) | |
10260 | intel_ddi_init(dev, PORT_A); | |
10261 | ||
10262 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
10263 | * register */ | |
10264 | found = I915_READ(SFUSE_STRAP); | |
10265 | ||
10266 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
10267 | intel_ddi_init(dev, PORT_B); | |
10268 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
10269 | intel_ddi_init(dev, PORT_C); | |
10270 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
10271 | intel_ddi_init(dev, PORT_D); | |
10272 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 10273 | int found; |
270b3042 DV |
10274 | dpd_is_edp = intel_dpd_is_edp(dev); |
10275 | ||
10276 | if (has_edp_a(dev)) | |
10277 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 10278 | |
dc0fa718 | 10279 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 10280 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 10281 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 10282 | if (!found) |
e2debe91 | 10283 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 10284 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 10285 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
10286 | } |
10287 | ||
dc0fa718 | 10288 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 10289 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 10290 | |
dc0fa718 | 10291 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 10292 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 10293 | |
5eb08b69 | 10294 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 10295 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 10296 | |
270b3042 | 10297 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 10298 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 10299 | } else if (IS_VALLEYVIEW(dev)) { |
585a94b8 AB |
10300 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
10301 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, | |
10302 | PORT_B); | |
10303 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) | |
10304 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
10305 | } | |
10306 | ||
6f6005a5 JB |
10307 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
10308 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
10309 | PORT_C); | |
10310 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
10311 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, | |
10312 | PORT_C); | |
10313 | } | |
19c03924 | 10314 | |
3cfca973 | 10315 | intel_dsi_init(dev); |
103a196f | 10316 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 10317 | bool found = false; |
7d57382e | 10318 | |
e2debe91 | 10319 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 10320 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 10321 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
10322 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
10323 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 10324 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 10325 | } |
27185ae1 | 10326 | |
e7281eab | 10327 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 10328 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 10329 | } |
13520b05 KH |
10330 | |
10331 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 10332 | |
e2debe91 | 10333 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 10334 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 10335 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 10336 | } |
27185ae1 | 10337 | |
e2debe91 | 10338 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 10339 | |
b01f2c3a JB |
10340 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
10341 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 10342 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 10343 | } |
e7281eab | 10344 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 10345 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 10346 | } |
27185ae1 | 10347 | |
b01f2c3a | 10348 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 10349 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 10350 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 10351 | } else if (IS_GEN2(dev)) |
79e53945 JB |
10352 | intel_dvo_init(dev); |
10353 | ||
103a196f | 10354 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
10355 | intel_tv_init(dev); |
10356 | ||
4ef69c7a CW |
10357 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
10358 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
10359 | encoder->base.possible_clones = | |
66a9278e | 10360 | intel_encoder_clones(encoder); |
79e53945 | 10361 | } |
47356eb6 | 10362 | |
dde86e2d | 10363 | intel_init_pch_refclk(dev); |
270b3042 DV |
10364 | |
10365 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
10366 | } |
10367 | ||
ddfe1567 CW |
10368 | void intel_framebuffer_fini(struct intel_framebuffer *fb) |
10369 | { | |
10370 | drm_framebuffer_cleanup(&fb->base); | |
80075d49 | 10371 | WARN_ON(!fb->obj->framebuffer_references--); |
ddfe1567 CW |
10372 | drm_gem_object_unreference_unlocked(&fb->obj->base); |
10373 | } | |
10374 | ||
79e53945 JB |
10375 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
10376 | { | |
10377 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 10378 | |
ddfe1567 | 10379 | intel_framebuffer_fini(intel_fb); |
79e53945 JB |
10380 | kfree(intel_fb); |
10381 | } | |
10382 | ||
10383 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 10384 | struct drm_file *file, |
79e53945 JB |
10385 | unsigned int *handle) |
10386 | { | |
10387 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 10388 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 10389 | |
05394f39 | 10390 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
10391 | } |
10392 | ||
10393 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
10394 | .destroy = intel_user_framebuffer_destroy, | |
10395 | .create_handle = intel_user_framebuffer_create_handle, | |
10396 | }; | |
10397 | ||
38651674 DA |
10398 | int intel_framebuffer_init(struct drm_device *dev, |
10399 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 10400 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 10401 | struct drm_i915_gem_object *obj) |
79e53945 | 10402 | { |
53155c0a | 10403 | int aligned_height, tile_height; |
a35cdaa0 | 10404 | int pitch_limit; |
79e53945 JB |
10405 | int ret; |
10406 | ||
dd4916c5 DV |
10407 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
10408 | ||
c16ed4be CW |
10409 | if (obj->tiling_mode == I915_TILING_Y) { |
10410 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 10411 | return -EINVAL; |
c16ed4be | 10412 | } |
57cd6508 | 10413 | |
c16ed4be CW |
10414 | if (mode_cmd->pitches[0] & 63) { |
10415 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
10416 | mode_cmd->pitches[0]); | |
57cd6508 | 10417 | return -EINVAL; |
c16ed4be | 10418 | } |
57cd6508 | 10419 | |
a35cdaa0 CW |
10420 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
10421 | pitch_limit = 32*1024; | |
10422 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
10423 | if (obj->tiling_mode) | |
10424 | pitch_limit = 16*1024; | |
10425 | else | |
10426 | pitch_limit = 32*1024; | |
10427 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
10428 | if (obj->tiling_mode) | |
10429 | pitch_limit = 8*1024; | |
10430 | else | |
10431 | pitch_limit = 16*1024; | |
10432 | } else | |
10433 | /* XXX DSPC is limited to 4k tiled */ | |
10434 | pitch_limit = 8*1024; | |
10435 | ||
10436 | if (mode_cmd->pitches[0] > pitch_limit) { | |
10437 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
10438 | obj->tiling_mode ? "tiled" : "linear", | |
10439 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 10440 | return -EINVAL; |
c16ed4be | 10441 | } |
5d7bd705 VS |
10442 | |
10443 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
10444 | mode_cmd->pitches[0] != obj->stride) { |
10445 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
10446 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 10447 | return -EINVAL; |
c16ed4be | 10448 | } |
5d7bd705 | 10449 | |
57779d06 | 10450 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 10451 | switch (mode_cmd->pixel_format) { |
57779d06 | 10452 | case DRM_FORMAT_C8: |
04b3924d VS |
10453 | case DRM_FORMAT_RGB565: |
10454 | case DRM_FORMAT_XRGB8888: | |
10455 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
10456 | break; |
10457 | case DRM_FORMAT_XRGB1555: | |
10458 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 10459 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
10460 | DRM_DEBUG("unsupported pixel format: %s\n", |
10461 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10462 | return -EINVAL; |
c16ed4be | 10463 | } |
57779d06 VS |
10464 | break; |
10465 | case DRM_FORMAT_XBGR8888: | |
10466 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
10467 | case DRM_FORMAT_XRGB2101010: |
10468 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
10469 | case DRM_FORMAT_XBGR2101010: |
10470 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 10471 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
10472 | DRM_DEBUG("unsupported pixel format: %s\n", |
10473 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10474 | return -EINVAL; |
c16ed4be | 10475 | } |
b5626747 | 10476 | break; |
04b3924d VS |
10477 | case DRM_FORMAT_YUYV: |
10478 | case DRM_FORMAT_UYVY: | |
10479 | case DRM_FORMAT_YVYU: | |
10480 | case DRM_FORMAT_VYUY: | |
c16ed4be | 10481 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
10482 | DRM_DEBUG("unsupported pixel format: %s\n", |
10483 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 10484 | return -EINVAL; |
c16ed4be | 10485 | } |
57cd6508 CW |
10486 | break; |
10487 | default: | |
4ee62c76 VS |
10488 | DRM_DEBUG("unsupported pixel format: %s\n", |
10489 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
10490 | return -EINVAL; |
10491 | } | |
10492 | ||
90f9a336 VS |
10493 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
10494 | if (mode_cmd->offsets[0] != 0) | |
10495 | return -EINVAL; | |
10496 | ||
53155c0a DV |
10497 | tile_height = IS_GEN2(dev) ? 16 : 8; |
10498 | aligned_height = ALIGN(mode_cmd->height, | |
10499 | obj->tiling_mode ? tile_height : 1); | |
10500 | /* FIXME drm helper for size checks (especially planar formats)? */ | |
10501 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
10502 | return -EINVAL; | |
10503 | ||
c7d73f6a DV |
10504 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
10505 | intel_fb->obj = obj; | |
80075d49 | 10506 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 10507 | |
79e53945 JB |
10508 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
10509 | if (ret) { | |
10510 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
10511 | return ret; | |
10512 | } | |
10513 | ||
79e53945 JB |
10514 | return 0; |
10515 | } | |
10516 | ||
79e53945 JB |
10517 | static struct drm_framebuffer * |
10518 | intel_user_framebuffer_create(struct drm_device *dev, | |
10519 | struct drm_file *filp, | |
308e5bcb | 10520 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 10521 | { |
05394f39 | 10522 | struct drm_i915_gem_object *obj; |
79e53945 | 10523 | |
308e5bcb JB |
10524 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
10525 | mode_cmd->handles[0])); | |
c8725226 | 10526 | if (&obj->base == NULL) |
cce13ff7 | 10527 | return ERR_PTR(-ENOENT); |
79e53945 | 10528 | |
d2dff872 | 10529 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
10530 | } |
10531 | ||
4520f53a | 10532 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 10533 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
10534 | { |
10535 | } | |
10536 | #endif | |
10537 | ||
79e53945 | 10538 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 10539 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 10540 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
10541 | }; |
10542 | ||
e70236a8 JB |
10543 | /* Set up chip specific display functions */ |
10544 | static void intel_init_display(struct drm_device *dev) | |
10545 | { | |
10546 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10547 | ||
ee9300bb DV |
10548 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
10549 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
10550 | else if (IS_VALLEYVIEW(dev)) | |
10551 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
10552 | else if (IS_PINEVIEW(dev)) | |
10553 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
10554 | else | |
10555 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
10556 | ||
affa9354 | 10557 | if (HAS_DDI(dev)) { |
0e8ffe1b | 10558 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
09b4ddf9 | 10559 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
10560 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
10561 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 10562 | dev_priv->display.off = haswell_crtc_off; |
09b4ddf9 PZ |
10563 | dev_priv->display.update_plane = ironlake_update_plane; |
10564 | } else if (HAS_PCH_SPLIT(dev)) { | |
0e8ffe1b | 10565 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
f564048e | 10566 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
10567 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
10568 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 10569 | dev_priv->display.off = ironlake_crtc_off; |
17638cd6 | 10570 | dev_priv->display.update_plane = ironlake_update_plane; |
89b667f8 JB |
10571 | } else if (IS_VALLEYVIEW(dev)) { |
10572 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
10573 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; | |
10574 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
10575 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
10576 | dev_priv->display.off = i9xx_crtc_off; | |
10577 | dev_priv->display.update_plane = i9xx_update_plane; | |
f564048e | 10578 | } else { |
0e8ffe1b | 10579 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
f564048e | 10580 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
10581 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
10582 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 10583 | dev_priv->display.off = i9xx_crtc_off; |
17638cd6 | 10584 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 10585 | } |
e70236a8 | 10586 | |
e70236a8 | 10587 | /* Returns the core display clock speed */ |
25eb05fc JB |
10588 | if (IS_VALLEYVIEW(dev)) |
10589 | dev_priv->display.get_display_clock_speed = | |
10590 | valleyview_get_display_clock_speed; | |
10591 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
10592 | dev_priv->display.get_display_clock_speed = |
10593 | i945_get_display_clock_speed; | |
10594 | else if (IS_I915G(dev)) | |
10595 | dev_priv->display.get_display_clock_speed = | |
10596 | i915_get_display_clock_speed; | |
257a7ffc | 10597 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
10598 | dev_priv->display.get_display_clock_speed = |
10599 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
10600 | else if (IS_PINEVIEW(dev)) |
10601 | dev_priv->display.get_display_clock_speed = | |
10602 | pnv_get_display_clock_speed; | |
e70236a8 JB |
10603 | else if (IS_I915GM(dev)) |
10604 | dev_priv->display.get_display_clock_speed = | |
10605 | i915gm_get_display_clock_speed; | |
10606 | else if (IS_I865G(dev)) | |
10607 | dev_priv->display.get_display_clock_speed = | |
10608 | i865_get_display_clock_speed; | |
f0f8a9ce | 10609 | else if (IS_I85X(dev)) |
e70236a8 JB |
10610 | dev_priv->display.get_display_clock_speed = |
10611 | i855_get_display_clock_speed; | |
10612 | else /* 852, 830 */ | |
10613 | dev_priv->display.get_display_clock_speed = | |
10614 | i830_get_display_clock_speed; | |
10615 | ||
7f8a8569 | 10616 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 10617 | if (IS_GEN5(dev)) { |
674cf967 | 10618 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 10619 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 10620 | } else if (IS_GEN6(dev)) { |
674cf967 | 10621 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 10622 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
10623 | } else if (IS_IVYBRIDGE(dev)) { |
10624 | /* FIXME: detect B0+ stepping and use auto training */ | |
10625 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 10626 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
10627 | dev_priv->display.modeset_global_resources = |
10628 | ivb_modeset_global_resources; | |
4e0bbc31 | 10629 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
c82e4d26 | 10630 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
83358c85 | 10631 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
10632 | dev_priv->display.modeset_global_resources = |
10633 | haswell_modeset_global_resources; | |
a0e63c22 | 10634 | } |
6067aaea | 10635 | } else if (IS_G4X(dev)) { |
e0dac65e | 10636 | dev_priv->display.write_eld = g4x_write_eld; |
30a970c6 JB |
10637 | } else if (IS_VALLEYVIEW(dev)) { |
10638 | dev_priv->display.modeset_global_resources = | |
10639 | valleyview_modeset_global_resources; | |
9ca2fe73 | 10640 | dev_priv->display.write_eld = ironlake_write_eld; |
e70236a8 | 10641 | } |
8c9f3aaf JB |
10642 | |
10643 | /* Default just returns -ENODEV to indicate unsupported */ | |
10644 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
10645 | ||
10646 | switch (INTEL_INFO(dev)->gen) { | |
10647 | case 2: | |
10648 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
10649 | break; | |
10650 | ||
10651 | case 3: | |
10652 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
10653 | break; | |
10654 | ||
10655 | case 4: | |
10656 | case 5: | |
10657 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
10658 | break; | |
10659 | ||
10660 | case 6: | |
10661 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
10662 | break; | |
7c9017e5 | 10663 | case 7: |
4e0bbc31 | 10664 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
10665 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
10666 | break; | |
8c9f3aaf | 10667 | } |
7bd688cd JN |
10668 | |
10669 | intel_panel_init_backlight_funcs(dev); | |
e70236a8 JB |
10670 | } |
10671 | ||
b690e96c JB |
10672 | /* |
10673 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
10674 | * resume, or other times. This quirk makes sure that's the case for | |
10675 | * affected systems. | |
10676 | */ | |
0206e353 | 10677 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
10678 | { |
10679 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10680 | ||
10681 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 10682 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
10683 | } |
10684 | ||
435793df KP |
10685 | /* |
10686 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
10687 | */ | |
10688 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
10689 | { | |
10690 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10691 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 10692 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
10693 | } |
10694 | ||
4dca20ef | 10695 | /* |
5a15ab5b CE |
10696 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
10697 | * brightness value | |
4dca20ef CE |
10698 | */ |
10699 | static void quirk_invert_brightness(struct drm_device *dev) | |
10700 | { | |
10701 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10702 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 10703 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
10704 | } |
10705 | ||
b690e96c JB |
10706 | struct intel_quirk { |
10707 | int device; | |
10708 | int subsystem_vendor; | |
10709 | int subsystem_device; | |
10710 | void (*hook)(struct drm_device *dev); | |
10711 | }; | |
10712 | ||
5f85f176 EE |
10713 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
10714 | struct intel_dmi_quirk { | |
10715 | void (*hook)(struct drm_device *dev); | |
10716 | const struct dmi_system_id (*dmi_id_list)[]; | |
10717 | }; | |
10718 | ||
10719 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
10720 | { | |
10721 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
10722 | return 1; | |
10723 | } | |
10724 | ||
10725 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
10726 | { | |
10727 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
10728 | { | |
10729 | .callback = intel_dmi_reverse_brightness, | |
10730 | .ident = "NCR Corporation", | |
10731 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
10732 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
10733 | }, | |
10734 | }, | |
10735 | { } /* terminating entry */ | |
10736 | }, | |
10737 | .hook = quirk_invert_brightness, | |
10738 | }, | |
10739 | }; | |
10740 | ||
c43b5634 | 10741 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 10742 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 10743 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 10744 | |
b690e96c JB |
10745 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
10746 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
10747 | ||
b690e96c JB |
10748 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
10749 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
10750 | ||
a4945f95 | 10751 | /* 830 needs to leave pipe A & dpll A up */ |
dcdaed6e | 10752 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
435793df KP |
10753 | |
10754 | /* Lenovo U160 cannot use SSC on LVDS */ | |
10755 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
10756 | |
10757 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
10758 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 10759 | |
ee1452d7 JN |
10760 | /* |
10761 | * All GM45 Acer (and its brands eMachines and Packard Bell) laptops | |
10762 | * seem to use inverted backlight PWM. | |
10763 | */ | |
10764 | { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness }, | |
b690e96c JB |
10765 | }; |
10766 | ||
10767 | static void intel_init_quirks(struct drm_device *dev) | |
10768 | { | |
10769 | struct pci_dev *d = dev->pdev; | |
10770 | int i; | |
10771 | ||
10772 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
10773 | struct intel_quirk *q = &intel_quirks[i]; | |
10774 | ||
10775 | if (d->device == q->device && | |
10776 | (d->subsystem_vendor == q->subsystem_vendor || | |
10777 | q->subsystem_vendor == PCI_ANY_ID) && | |
10778 | (d->subsystem_device == q->subsystem_device || | |
10779 | q->subsystem_device == PCI_ANY_ID)) | |
10780 | q->hook(dev); | |
10781 | } | |
5f85f176 EE |
10782 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
10783 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
10784 | intel_dmi_quirks[i].hook(dev); | |
10785 | } | |
b690e96c JB |
10786 | } |
10787 | ||
9cce37f4 JB |
10788 | /* Disable the VGA plane that we never use */ |
10789 | static void i915_disable_vga(struct drm_device *dev) | |
10790 | { | |
10791 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10792 | u8 sr1; | |
766aa1c4 | 10793 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 JB |
10794 | |
10795 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
3fdcf431 | 10796 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
10797 | sr1 = inb(VGA_SR_DATA); |
10798 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
10799 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10800 | udelay(300); | |
10801 | ||
10802 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
10803 | POSTING_READ(vga_reg); | |
10804 | } | |
10805 | ||
f817586c DV |
10806 | void intel_modeset_init_hw(struct drm_device *dev) |
10807 | { | |
a8f78b58 ED |
10808 | intel_prepare_ddi(dev); |
10809 | ||
f817586c DV |
10810 | intel_init_clock_gating(dev); |
10811 | ||
40e9cf64 JB |
10812 | intel_init_dpio(dev); |
10813 | ||
79f5b2c7 | 10814 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 10815 | intel_enable_gt_powersave(dev); |
79f5b2c7 | 10816 | mutex_unlock(&dev->struct_mutex); |
f817586c DV |
10817 | } |
10818 | ||
7d708ee4 ID |
10819 | void intel_modeset_suspend_hw(struct drm_device *dev) |
10820 | { | |
10821 | intel_suspend_hw(dev); | |
10822 | } | |
10823 | ||
79e53945 JB |
10824 | void intel_modeset_init(struct drm_device *dev) |
10825 | { | |
652c393a | 10826 | struct drm_i915_private *dev_priv = dev->dev_private; |
7f1f3851 | 10827 | int i, j, ret; |
79e53945 JB |
10828 | |
10829 | drm_mode_config_init(dev); | |
10830 | ||
10831 | dev->mode_config.min_width = 0; | |
10832 | dev->mode_config.min_height = 0; | |
10833 | ||
019d96cb DA |
10834 | dev->mode_config.preferred_depth = 24; |
10835 | dev->mode_config.prefer_shadow = 1; | |
10836 | ||
e6ecefaa | 10837 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 10838 | |
b690e96c JB |
10839 | intel_init_quirks(dev); |
10840 | ||
1fa61106 ED |
10841 | intel_init_pm(dev); |
10842 | ||
e3c74757 BW |
10843 | if (INTEL_INFO(dev)->num_pipes == 0) |
10844 | return; | |
10845 | ||
e70236a8 JB |
10846 | intel_init_display(dev); |
10847 | ||
a6c45cf0 CW |
10848 | if (IS_GEN2(dev)) { |
10849 | dev->mode_config.max_width = 2048; | |
10850 | dev->mode_config.max_height = 2048; | |
10851 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
10852 | dev->mode_config.max_width = 4096; |
10853 | dev->mode_config.max_height = 4096; | |
79e53945 | 10854 | } else { |
a6c45cf0 CW |
10855 | dev->mode_config.max_width = 8192; |
10856 | dev->mode_config.max_height = 8192; | |
79e53945 | 10857 | } |
5d4545ae | 10858 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 10859 | |
28c97730 | 10860 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
10861 | INTEL_INFO(dev)->num_pipes, |
10862 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 10863 | |
08e2a7de | 10864 | for_each_pipe(i) { |
79e53945 | 10865 | intel_crtc_init(dev, i); |
7f1f3851 JB |
10866 | for (j = 0; j < dev_priv->num_plane; j++) { |
10867 | ret = intel_plane_init(dev, i, j); | |
10868 | if (ret) | |
06da8da2 VS |
10869 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
10870 | pipe_name(i), sprite_name(i, j), ret); | |
7f1f3851 | 10871 | } |
79e53945 JB |
10872 | } |
10873 | ||
79f689aa | 10874 | intel_cpu_pll_init(dev); |
e72f9fbf | 10875 | intel_shared_dpll_init(dev); |
ee7b9f93 | 10876 | |
9cce37f4 JB |
10877 | /* Just disable it once at startup */ |
10878 | i915_disable_vga(dev); | |
79e53945 | 10879 | intel_setup_outputs(dev); |
11be49eb CW |
10880 | |
10881 | /* Just in case the BIOS is doing something questionable. */ | |
10882 | intel_disable_fbc(dev); | |
2c7111db CW |
10883 | } |
10884 | ||
24929352 DV |
10885 | static void |
10886 | intel_connector_break_all_links(struct intel_connector *connector) | |
10887 | { | |
10888 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
10889 | connector->base.encoder = NULL; | |
10890 | connector->encoder->connectors_active = false; | |
10891 | connector->encoder->base.crtc = NULL; | |
10892 | } | |
10893 | ||
7fad798e DV |
10894 | static void intel_enable_pipe_a(struct drm_device *dev) |
10895 | { | |
10896 | struct intel_connector *connector; | |
10897 | struct drm_connector *crt = NULL; | |
10898 | struct intel_load_detect_pipe load_detect_temp; | |
10899 | ||
10900 | /* We can't just switch on the pipe A, we need to set things up with a | |
10901 | * proper mode and output configuration. As a gross hack, enable pipe A | |
10902 | * by enabling the load detect pipe once. */ | |
10903 | list_for_each_entry(connector, | |
10904 | &dev->mode_config.connector_list, | |
10905 | base.head) { | |
10906 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
10907 | crt = &connector->base; | |
10908 | break; | |
10909 | } | |
10910 | } | |
10911 | ||
10912 | if (!crt) | |
10913 | return; | |
10914 | ||
10915 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) | |
10916 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
10917 | ||
652c393a | 10918 | |
7fad798e DV |
10919 | } |
10920 | ||
fa555837 DV |
10921 | static bool |
10922 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
10923 | { | |
7eb552ae BW |
10924 | struct drm_device *dev = crtc->base.dev; |
10925 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
10926 | u32 reg, val; |
10927 | ||
7eb552ae | 10928 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
10929 | return true; |
10930 | ||
10931 | reg = DSPCNTR(!crtc->plane); | |
10932 | val = I915_READ(reg); | |
10933 | ||
10934 | if ((val & DISPLAY_PLANE_ENABLE) && | |
10935 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
10936 | return false; | |
10937 | ||
10938 | return true; | |
10939 | } | |
10940 | ||
24929352 DV |
10941 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
10942 | { | |
10943 | struct drm_device *dev = crtc->base.dev; | |
10944 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 10945 | u32 reg; |
24929352 | 10946 | |
24929352 | 10947 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 10948 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
10949 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
10950 | ||
10951 | /* We need to sanitize the plane -> pipe mapping first because this will | |
fa555837 DV |
10952 | * disable the crtc (and hence change the state) if it is wrong. Note |
10953 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
10954 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
10955 | struct intel_connector *connector; |
10956 | bool plane; | |
10957 | ||
24929352 DV |
10958 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
10959 | crtc->base.base.id); | |
10960 | ||
10961 | /* Pipe has the wrong plane attached and the plane is active. | |
10962 | * Temporarily change the plane mapping and disable everything | |
10963 | * ... */ | |
10964 | plane = crtc->plane; | |
10965 | crtc->plane = !plane; | |
10966 | dev_priv->display.crtc_disable(&crtc->base); | |
10967 | crtc->plane = plane; | |
10968 | ||
10969 | /* ... and break all links. */ | |
10970 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10971 | base.head) { | |
10972 | if (connector->encoder->base.crtc != &crtc->base) | |
10973 | continue; | |
10974 | ||
10975 | intel_connector_break_all_links(connector); | |
10976 | } | |
10977 | ||
10978 | WARN_ON(crtc->active); | |
10979 | crtc->base.enabled = false; | |
10980 | } | |
24929352 | 10981 | |
7fad798e DV |
10982 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
10983 | crtc->pipe == PIPE_A && !crtc->active) { | |
10984 | /* BIOS forgot to enable pipe A, this mostly happens after | |
10985 | * resume. Force-enable the pipe to fix this, the update_dpms | |
10986 | * call below we restore the pipe to the right state, but leave | |
10987 | * the required bits on. */ | |
10988 | intel_enable_pipe_a(dev); | |
10989 | } | |
10990 | ||
24929352 DV |
10991 | /* Adjust the state of the output pipe according to whether we |
10992 | * have active connectors/encoders. */ | |
10993 | intel_crtc_update_dpms(&crtc->base); | |
10994 | ||
10995 | if (crtc->active != crtc->base.enabled) { | |
10996 | struct intel_encoder *encoder; | |
10997 | ||
10998 | /* This can happen either due to bugs in the get_hw_state | |
10999 | * functions or because the pipe is force-enabled due to the | |
11000 | * pipe A quirk. */ | |
11001 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
11002 | crtc->base.base.id, | |
11003 | crtc->base.enabled ? "enabled" : "disabled", | |
11004 | crtc->active ? "enabled" : "disabled"); | |
11005 | ||
11006 | crtc->base.enabled = crtc->active; | |
11007 | ||
11008 | /* Because we only establish the connector -> encoder -> | |
11009 | * crtc links if something is active, this means the | |
11010 | * crtc is now deactivated. Break the links. connector | |
11011 | * -> encoder links are only establish when things are | |
11012 | * actually up, hence no need to break them. */ | |
11013 | WARN_ON(crtc->active); | |
11014 | ||
11015 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
11016 | WARN_ON(encoder->connectors_active); | |
11017 | encoder->base.crtc = NULL; | |
11018 | } | |
11019 | } | |
11020 | } | |
11021 | ||
11022 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
11023 | { | |
11024 | struct intel_connector *connector; | |
11025 | struct drm_device *dev = encoder->base.dev; | |
11026 | ||
11027 | /* We need to check both for a crtc link (meaning that the | |
11028 | * encoder is active and trying to read from a pipe) and the | |
11029 | * pipe itself being active. */ | |
11030 | bool has_active_crtc = encoder->base.crtc && | |
11031 | to_intel_crtc(encoder->base.crtc)->active; | |
11032 | ||
11033 | if (encoder->connectors_active && !has_active_crtc) { | |
11034 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
11035 | encoder->base.base.id, | |
11036 | drm_get_encoder_name(&encoder->base)); | |
11037 | ||
11038 | /* Connector is active, but has no active pipe. This is | |
11039 | * fallout from our resume register restoring. Disable | |
11040 | * the encoder manually again. */ | |
11041 | if (encoder->base.crtc) { | |
11042 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
11043 | encoder->base.base.id, | |
11044 | drm_get_encoder_name(&encoder->base)); | |
11045 | encoder->disable(encoder); | |
11046 | } | |
11047 | ||
11048 | /* Inconsistent output/port/pipe state happens presumably due to | |
11049 | * a bug in one of the get_hw_state functions. Or someplace else | |
11050 | * in our code, like the register restore mess on resume. Clamp | |
11051 | * things to off as a safer default. */ | |
11052 | list_for_each_entry(connector, | |
11053 | &dev->mode_config.connector_list, | |
11054 | base.head) { | |
11055 | if (connector->encoder != encoder) | |
11056 | continue; | |
11057 | ||
11058 | intel_connector_break_all_links(connector); | |
11059 | } | |
11060 | } | |
11061 | /* Enabled encoders without active connectors will be fixed in | |
11062 | * the crtc fixup. */ | |
11063 | } | |
11064 | ||
44cec740 | 11065 | void i915_redisable_vga(struct drm_device *dev) |
0fde901f KM |
11066 | { |
11067 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 11068 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 11069 | |
8dc8a27c PZ |
11070 | /* This function can be called both from intel_modeset_setup_hw_state or |
11071 | * at a very early point in our resume sequence, where the power well | |
11072 | * structures are not yet restored. Since this function is at a very | |
11073 | * paranoid "someone might have enabled VGA while we were not looking" | |
11074 | * level, just check if the power well is enabled instead of trying to | |
11075 | * follow the "don't touch the power well if we don't need it" policy | |
11076 | * the rest of the driver uses. */ | |
f9e711e9 | 11077 | if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && |
6aedd1f5 | 11078 | (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0) |
8dc8a27c PZ |
11079 | return; |
11080 | ||
e1553faa | 11081 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
0fde901f | 11082 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); |
209d5211 | 11083 | i915_disable_vga(dev); |
0fde901f KM |
11084 | } |
11085 | } | |
11086 | ||
30e984df | 11087 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
11088 | { |
11089 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11090 | enum pipe pipe; | |
24929352 DV |
11091 | struct intel_crtc *crtc; |
11092 | struct intel_encoder *encoder; | |
11093 | struct intel_connector *connector; | |
5358901f | 11094 | int i; |
24929352 | 11095 | |
0e8ffe1b DV |
11096 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
11097 | base.head) { | |
88adfff1 | 11098 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 11099 | |
0e8ffe1b DV |
11100 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
11101 | &crtc->config); | |
24929352 DV |
11102 | |
11103 | crtc->base.enabled = crtc->active; | |
4c445e0e | 11104 | crtc->primary_enabled = crtc->active; |
24929352 DV |
11105 | |
11106 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
11107 | crtc->base.base.id, | |
11108 | crtc->active ? "enabled" : "disabled"); | |
11109 | } | |
11110 | ||
5358901f | 11111 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
affa9354 | 11112 | if (HAS_DDI(dev)) |
6441ab5f PZ |
11113 | intel_ddi_setup_hw_pll_state(dev); |
11114 | ||
5358901f DV |
11115 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11116 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11117 | ||
11118 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
11119 | pll->active = 0; | |
11120 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
11121 | base.head) { | |
11122 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
11123 | pll->active++; | |
11124 | } | |
11125 | pll->refcount = pll->active; | |
11126 | ||
35c95375 DV |
11127 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
11128 | pll->name, pll->refcount, pll->on); | |
5358901f DV |
11129 | } |
11130 | ||
24929352 DV |
11131 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
11132 | base.head) { | |
11133 | pipe = 0; | |
11134 | ||
11135 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
11136 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
11137 | encoder->base.crtc = &crtc->base; | |
1d37b689 | 11138 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
11139 | } else { |
11140 | encoder->base.crtc = NULL; | |
11141 | } | |
11142 | ||
11143 | encoder->connectors_active = false; | |
6f2bcceb | 11144 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 DV |
11145 | encoder->base.base.id, |
11146 | drm_get_encoder_name(&encoder->base), | |
11147 | encoder->base.crtc ? "enabled" : "disabled", | |
6f2bcceb | 11148 | pipe_name(pipe)); |
24929352 DV |
11149 | } |
11150 | ||
11151 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
11152 | base.head) { | |
11153 | if (connector->get_hw_state(connector)) { | |
11154 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
11155 | connector->encoder->connectors_active = true; | |
11156 | connector->base.encoder = &connector->encoder->base; | |
11157 | } else { | |
11158 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
11159 | connector->base.encoder = NULL; | |
11160 | } | |
11161 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
11162 | connector->base.base.id, | |
11163 | drm_get_connector_name(&connector->base), | |
11164 | connector->base.encoder ? "enabled" : "disabled"); | |
11165 | } | |
30e984df DV |
11166 | } |
11167 | ||
11168 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
11169 | * and i915 state tracking structures. */ | |
11170 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
11171 | bool force_restore) | |
11172 | { | |
11173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11174 | enum pipe pipe; | |
30e984df DV |
11175 | struct intel_crtc *crtc; |
11176 | struct intel_encoder *encoder; | |
35c95375 | 11177 | int i; |
30e984df DV |
11178 | |
11179 | intel_modeset_readout_hw_state(dev); | |
24929352 | 11180 | |
babea61d JB |
11181 | /* |
11182 | * Now that we have the config, copy it to each CRTC struct | |
11183 | * Note that this could go away if we move to using crtc_config | |
11184 | * checking everywhere. | |
11185 | */ | |
11186 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
11187 | base.head) { | |
11188 | if (crtc->active && i915_fastboot) { | |
11189 | intel_crtc_mode_from_pipe_config(crtc, &crtc->config); | |
11190 | ||
11191 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", | |
11192 | crtc->base.base.id); | |
11193 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
11194 | } | |
11195 | } | |
11196 | ||
24929352 DV |
11197 | /* HW state is read out, now we need to sanitize this mess. */ |
11198 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
11199 | base.head) { | |
11200 | intel_sanitize_encoder(encoder); | |
11201 | } | |
11202 | ||
11203 | for_each_pipe(pipe) { | |
11204 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
11205 | intel_sanitize_crtc(crtc); | |
c0b03411 | 11206 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 11207 | } |
9a935856 | 11208 | |
35c95375 DV |
11209 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
11210 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
11211 | ||
11212 | if (!pll->on || pll->active) | |
11213 | continue; | |
11214 | ||
11215 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
11216 | ||
11217 | pll->disable(dev_priv, pll); | |
11218 | pll->on = false; | |
11219 | } | |
11220 | ||
243e6a44 VS |
11221 | if (IS_HASWELL(dev)) |
11222 | ilk_wm_get_hw_state(dev); | |
11223 | ||
45e2b5f6 | 11224 | if (force_restore) { |
7d0bc1ea VS |
11225 | i915_redisable_vga(dev); |
11226 | ||
f30da187 DV |
11227 | /* |
11228 | * We need to use raw interfaces for restoring state to avoid | |
11229 | * checking (bogus) intermediate states. | |
11230 | */ | |
45e2b5f6 | 11231 | for_each_pipe(pipe) { |
b5644d05 JB |
11232 | struct drm_crtc *crtc = |
11233 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
11234 | |
11235 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
11236 | crtc->fb); | |
45e2b5f6 DV |
11237 | } |
11238 | } else { | |
11239 | intel_modeset_update_staged_output_state(dev); | |
11240 | } | |
8af6cf88 DV |
11241 | |
11242 | intel_modeset_check_state(dev); | |
2e938892 DV |
11243 | |
11244 | drm_mode_config_reset(dev); | |
2c7111db CW |
11245 | } |
11246 | ||
11247 | void intel_modeset_gem_init(struct drm_device *dev) | |
11248 | { | |
1833b134 | 11249 | intel_modeset_init_hw(dev); |
02e792fb DV |
11250 | |
11251 | intel_setup_overlay(dev); | |
24929352 | 11252 | |
45e2b5f6 | 11253 | intel_modeset_setup_hw_state(dev, false); |
79e53945 JB |
11254 | } |
11255 | ||
11256 | void intel_modeset_cleanup(struct drm_device *dev) | |
11257 | { | |
652c393a JB |
11258 | struct drm_i915_private *dev_priv = dev->dev_private; |
11259 | struct drm_crtc *crtc; | |
d9255d57 | 11260 | struct drm_connector *connector; |
652c393a | 11261 | |
fd0c0642 DV |
11262 | /* |
11263 | * Interrupts and polling as the first thing to avoid creating havoc. | |
11264 | * Too much stuff here (turning of rps, connectors, ...) would | |
11265 | * experience fancy races otherwise. | |
11266 | */ | |
11267 | drm_irq_uninstall(dev); | |
11268 | cancel_work_sync(&dev_priv->hotplug_work); | |
11269 | /* | |
11270 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
11271 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
11272 | */ | |
f87ea761 | 11273 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 11274 | |
652c393a JB |
11275 | mutex_lock(&dev->struct_mutex); |
11276 | ||
723bfd70 JB |
11277 | intel_unregister_dsm_handler(); |
11278 | ||
652c393a JB |
11279 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
11280 | /* Skip inactive CRTCs */ | |
11281 | if (!crtc->fb) | |
11282 | continue; | |
11283 | ||
3dec0095 | 11284 | intel_increase_pllclock(crtc); |
652c393a JB |
11285 | } |
11286 | ||
973d04f9 | 11287 | intel_disable_fbc(dev); |
e70236a8 | 11288 | |
8090c6b9 | 11289 | intel_disable_gt_powersave(dev); |
0cdab21f | 11290 | |
930ebb46 DV |
11291 | ironlake_teardown_rc6(dev); |
11292 | ||
69341a5e KH |
11293 | mutex_unlock(&dev->struct_mutex); |
11294 | ||
1630fe75 CW |
11295 | /* flush any delayed tasks or pending work */ |
11296 | flush_scheduled_work(); | |
11297 | ||
db31af1d JN |
11298 | /* destroy the backlight and sysfs files before encoders/connectors */ |
11299 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
11300 | intel_panel_destroy_backlight(connector); | |
d9255d57 | 11301 | drm_sysfs_connector_remove(connector); |
db31af1d | 11302 | } |
d9255d57 | 11303 | |
79e53945 | 11304 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
11305 | |
11306 | intel_cleanup_overlay(dev); | |
79e53945 JB |
11307 | } |
11308 | ||
f1c79df3 ZW |
11309 | /* |
11310 | * Return which encoder is currently attached for connector. | |
11311 | */ | |
df0e9248 | 11312 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 11313 | { |
df0e9248 CW |
11314 | return &intel_attached_encoder(connector)->base; |
11315 | } | |
f1c79df3 | 11316 | |
df0e9248 CW |
11317 | void intel_connector_attach_encoder(struct intel_connector *connector, |
11318 | struct intel_encoder *encoder) | |
11319 | { | |
11320 | connector->encoder = encoder; | |
11321 | drm_mode_connector_attach_encoder(&connector->base, | |
11322 | &encoder->base); | |
79e53945 | 11323 | } |
28d52043 DA |
11324 | |
11325 | /* | |
11326 | * set vga decode state - true == enable VGA decode | |
11327 | */ | |
11328 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
11329 | { | |
11330 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11331 | u16 gmch_ctrl; | |
11332 | ||
11333 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
11334 | if (state) | |
11335 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
11336 | else | |
11337 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
11338 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
11339 | return 0; | |
11340 | } | |
c4a1d9e4 | 11341 | |
c4a1d9e4 | 11342 | struct intel_display_error_state { |
ff57f1b0 PZ |
11343 | |
11344 | u32 power_well_driver; | |
11345 | ||
63b66e5b CW |
11346 | int num_transcoders; |
11347 | ||
c4a1d9e4 CW |
11348 | struct intel_cursor_error_state { |
11349 | u32 control; | |
11350 | u32 position; | |
11351 | u32 base; | |
11352 | u32 size; | |
52331309 | 11353 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
11354 | |
11355 | struct intel_pipe_error_state { | |
ddf9c536 | 11356 | bool power_domain_on; |
c4a1d9e4 | 11357 | u32 source; |
52331309 | 11358 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
11359 | |
11360 | struct intel_plane_error_state { | |
11361 | u32 control; | |
11362 | u32 stride; | |
11363 | u32 size; | |
11364 | u32 pos; | |
11365 | u32 addr; | |
11366 | u32 surface; | |
11367 | u32 tile_offset; | |
52331309 | 11368 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
11369 | |
11370 | struct intel_transcoder_error_state { | |
ddf9c536 | 11371 | bool power_domain_on; |
63b66e5b CW |
11372 | enum transcoder cpu_transcoder; |
11373 | ||
11374 | u32 conf; | |
11375 | ||
11376 | u32 htotal; | |
11377 | u32 hblank; | |
11378 | u32 hsync; | |
11379 | u32 vtotal; | |
11380 | u32 vblank; | |
11381 | u32 vsync; | |
11382 | } transcoder[4]; | |
c4a1d9e4 CW |
11383 | }; |
11384 | ||
11385 | struct intel_display_error_state * | |
11386 | intel_display_capture_error_state(struct drm_device *dev) | |
11387 | { | |
0206e353 | 11388 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 | 11389 | struct intel_display_error_state *error; |
63b66e5b CW |
11390 | int transcoders[] = { |
11391 | TRANSCODER_A, | |
11392 | TRANSCODER_B, | |
11393 | TRANSCODER_C, | |
11394 | TRANSCODER_EDP, | |
11395 | }; | |
c4a1d9e4 CW |
11396 | int i; |
11397 | ||
63b66e5b CW |
11398 | if (INTEL_INFO(dev)->num_pipes == 0) |
11399 | return NULL; | |
11400 | ||
9d1cb914 | 11401 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
11402 | if (error == NULL) |
11403 | return NULL; | |
11404 | ||
190be112 | 11405 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
11406 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
11407 | ||
52331309 | 11408 | for_each_pipe(i) { |
ddf9c536 ID |
11409 | error->pipe[i].power_domain_on = |
11410 | intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i)); | |
11411 | if (!error->pipe[i].power_domain_on) | |
9d1cb914 PZ |
11412 | continue; |
11413 | ||
a18c4c3d PZ |
11414 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
11415 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
11416 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
11417 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
11418 | } else { | |
11419 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); | |
11420 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); | |
11421 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); | |
11422 | } | |
c4a1d9e4 CW |
11423 | |
11424 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
11425 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 11426 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 11427 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
11428 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
11429 | } | |
ca291363 PZ |
11430 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
11431 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
11432 | if (INTEL_INFO(dev)->gen >= 4) { |
11433 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
11434 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
11435 | } | |
11436 | ||
c4a1d9e4 | 11437 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
63b66e5b CW |
11438 | } |
11439 | ||
11440 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
11441 | if (HAS_DDI(dev_priv->dev)) | |
11442 | error->num_transcoders++; /* Account for eDP. */ | |
11443 | ||
11444 | for (i = 0; i < error->num_transcoders; i++) { | |
11445 | enum transcoder cpu_transcoder = transcoders[i]; | |
11446 | ||
ddf9c536 ID |
11447 | error->transcoder[i].power_domain_on = |
11448 | intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i)); | |
11449 | if (!error->transcoder[i].power_domain_on) | |
9d1cb914 PZ |
11450 | continue; |
11451 | ||
63b66e5b CW |
11452 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
11453 | ||
11454 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
11455 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
11456 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
11457 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
11458 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
11459 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
11460 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
11461 | } |
11462 | ||
11463 | return error; | |
11464 | } | |
11465 | ||
edc3d884 MK |
11466 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
11467 | ||
c4a1d9e4 | 11468 | void |
edc3d884 | 11469 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
11470 | struct drm_device *dev, |
11471 | struct intel_display_error_state *error) | |
11472 | { | |
11473 | int i; | |
11474 | ||
63b66e5b CW |
11475 | if (!error) |
11476 | return; | |
11477 | ||
edc3d884 | 11478 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 11479 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 11480 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 11481 | error->power_well_driver); |
52331309 | 11482 | for_each_pipe(i) { |
edc3d884 | 11483 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
11484 | err_printf(m, " Power: %s\n", |
11485 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 11486 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
edc3d884 MK |
11487 | |
11488 | err_printf(m, "Plane [%d]:\n", i); | |
11489 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
11490 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 11491 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
11492 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
11493 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 11494 | } |
4b71a570 | 11495 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 11496 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 11497 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
11498 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
11499 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
11500 | } |
11501 | ||
edc3d884 MK |
11502 | err_printf(m, "Cursor [%d]:\n", i); |
11503 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
11504 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
11505 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 11506 | } |
63b66e5b CW |
11507 | |
11508 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 11509 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 11510 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
11511 | err_printf(m, " Power: %s\n", |
11512 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
11513 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
11514 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
11515 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
11516 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
11517 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
11518 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
11519 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
11520 | } | |
c4a1d9e4 | 11521 | } |