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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
23b2f8bb | 28 | #include <linux/cpufreq.h> |
c1c7af60 JB |
29 | #include <linux/module.h> |
30 | #include <linux/input.h> | |
79e53945 | 31 | #include <linux/i2c.h> |
7662c8bd | 32 | #include <linux/kernel.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
9cce37f4 | 34 | #include <linux/vgaarb.h> |
e0dac65e | 35 | #include <drm/drm_edid.h> |
79e53945 JB |
36 | #include "drmP.h" |
37 | #include "intel_drv.h" | |
38 | #include "i915_drm.h" | |
39 | #include "i915_drv.h" | |
e5510fac | 40 | #include "i915_trace.h" |
ab2c0672 | 41 | #include "drm_dp_helper.h" |
79e53945 | 42 | #include "drm_crtc_helper.h" |
c0f372b3 | 43 | #include <linux/dma_remapping.h> |
79e53945 | 44 | |
32f9d658 ZW |
45 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
46 | ||
0206e353 | 47 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
7662c8bd | 48 | static void intel_update_watermarks(struct drm_device *dev); |
3dec0095 | 49 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 50 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 JB |
51 | |
52 | typedef struct { | |
0206e353 AJ |
53 | /* given values */ |
54 | int n; | |
55 | int m1, m2; | |
56 | int p1, p2; | |
57 | /* derived values */ | |
58 | int dot; | |
59 | int vco; | |
60 | int m; | |
61 | int p; | |
79e53945 JB |
62 | } intel_clock_t; |
63 | ||
64 | typedef struct { | |
0206e353 | 65 | int min, max; |
79e53945 JB |
66 | } intel_range_t; |
67 | ||
68 | typedef struct { | |
0206e353 AJ |
69 | int dot_limit; |
70 | int p2_slow, p2_fast; | |
79e53945 JB |
71 | } intel_p2_t; |
72 | ||
73 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
74 | typedef struct intel_limit intel_limit_t; |
75 | struct intel_limit { | |
0206e353 AJ |
76 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
77 | intel_p2_t p2; | |
78 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, | |
cec2f356 | 79 | int, int, intel_clock_t *, intel_clock_t *); |
d4906093 | 80 | }; |
79e53945 | 81 | |
2377b741 JB |
82 | /* FDI */ |
83 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
84 | ||
d4906093 ML |
85 | static bool |
86 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
87 | int target, int refclk, intel_clock_t *match_clock, |
88 | intel_clock_t *best_clock); | |
d4906093 ML |
89 | static bool |
90 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
91 | int target, int refclk, intel_clock_t *match_clock, |
92 | intel_clock_t *best_clock); | |
79e53945 | 93 | |
a4fc5ed6 KP |
94 | static bool |
95 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
cec2f356 SP |
96 | int target, int refclk, intel_clock_t *match_clock, |
97 | intel_clock_t *best_clock); | |
5eb08b69 | 98 | static bool |
f2b115e6 | 99 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
cec2f356 SP |
100 | int target, int refclk, intel_clock_t *match_clock, |
101 | intel_clock_t *best_clock); | |
a4fc5ed6 | 102 | |
021357ac CW |
103 | static inline u32 /* units of 100MHz */ |
104 | intel_fdi_link_freq(struct drm_device *dev) | |
105 | { | |
8b99e68c CW |
106 | if (IS_GEN5(dev)) { |
107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
108 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
109 | } else | |
110 | return 27; | |
021357ac CW |
111 | } |
112 | ||
e4b36699 | 113 | static const intel_limit_t intel_limits_i8xx_dvo = { |
0206e353 AJ |
114 | .dot = { .min = 25000, .max = 350000 }, |
115 | .vco = { .min = 930000, .max = 1400000 }, | |
116 | .n = { .min = 3, .max = 16 }, | |
117 | .m = { .min = 96, .max = 140 }, | |
118 | .m1 = { .min = 18, .max = 26 }, | |
119 | .m2 = { .min = 6, .max = 16 }, | |
120 | .p = { .min = 4, .max = 128 }, | |
121 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
122 | .p2 = { .dot_limit = 165000, |
123 | .p2_slow = 4, .p2_fast = 2 }, | |
d4906093 | 124 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
125 | }; |
126 | ||
127 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
0206e353 AJ |
128 | .dot = { .min = 25000, .max = 350000 }, |
129 | .vco = { .min = 930000, .max = 1400000 }, | |
130 | .n = { .min = 3, .max = 16 }, | |
131 | .m = { .min = 96, .max = 140 }, | |
132 | .m1 = { .min = 18, .max = 26 }, | |
133 | .m2 = { .min = 6, .max = 16 }, | |
134 | .p = { .min = 4, .max = 128 }, | |
135 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
136 | .p2 = { .dot_limit = 165000, |
137 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 138 | .find_pll = intel_find_best_PLL, |
e4b36699 | 139 | }; |
273e27ca | 140 | |
e4b36699 | 141 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
142 | .dot = { .min = 20000, .max = 400000 }, |
143 | .vco = { .min = 1400000, .max = 2800000 }, | |
144 | .n = { .min = 1, .max = 6 }, | |
145 | .m = { .min = 70, .max = 120 }, | |
146 | .m1 = { .min = 10, .max = 22 }, | |
147 | .m2 = { .min = 5, .max = 9 }, | |
148 | .p = { .min = 5, .max = 80 }, | |
149 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
150 | .p2 = { .dot_limit = 200000, |
151 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 152 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
153 | }; |
154 | ||
155 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
156 | .dot = { .min = 20000, .max = 400000 }, |
157 | .vco = { .min = 1400000, .max = 2800000 }, | |
158 | .n = { .min = 1, .max = 6 }, | |
159 | .m = { .min = 70, .max = 120 }, | |
160 | .m1 = { .min = 10, .max = 22 }, | |
161 | .m2 = { .min = 5, .max = 9 }, | |
162 | .p = { .min = 7, .max = 98 }, | |
163 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
164 | .p2 = { .dot_limit = 112000, |
165 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 166 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
167 | }; |
168 | ||
273e27ca | 169 | |
e4b36699 | 170 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
171 | .dot = { .min = 25000, .max = 270000 }, |
172 | .vco = { .min = 1750000, .max = 3500000}, | |
173 | .n = { .min = 1, .max = 4 }, | |
174 | .m = { .min = 104, .max = 138 }, | |
175 | .m1 = { .min = 17, .max = 23 }, | |
176 | .m2 = { .min = 5, .max = 11 }, | |
177 | .p = { .min = 10, .max = 30 }, | |
178 | .p1 = { .min = 1, .max = 3}, | |
179 | .p2 = { .dot_limit = 270000, | |
180 | .p2_slow = 10, | |
181 | .p2_fast = 10 | |
044c7c41 | 182 | }, |
d4906093 | 183 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
184 | }; |
185 | ||
186 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
187 | .dot = { .min = 22000, .max = 400000 }, |
188 | .vco = { .min = 1750000, .max = 3500000}, | |
189 | .n = { .min = 1, .max = 4 }, | |
190 | .m = { .min = 104, .max = 138 }, | |
191 | .m1 = { .min = 16, .max = 23 }, | |
192 | .m2 = { .min = 5, .max = 11 }, | |
193 | .p = { .min = 5, .max = 80 }, | |
194 | .p1 = { .min = 1, .max = 8}, | |
195 | .p2 = { .dot_limit = 165000, | |
196 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 197 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
198 | }; |
199 | ||
200 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
201 | .dot = { .min = 20000, .max = 115000 }, |
202 | .vco = { .min = 1750000, .max = 3500000 }, | |
203 | .n = { .min = 1, .max = 3 }, | |
204 | .m = { .min = 104, .max = 138 }, | |
205 | .m1 = { .min = 17, .max = 23 }, | |
206 | .m2 = { .min = 5, .max = 11 }, | |
207 | .p = { .min = 28, .max = 112 }, | |
208 | .p1 = { .min = 2, .max = 8 }, | |
209 | .p2 = { .dot_limit = 0, | |
210 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 211 | }, |
d4906093 | 212 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
213 | }; |
214 | ||
215 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
216 | .dot = { .min = 80000, .max = 224000 }, |
217 | .vco = { .min = 1750000, .max = 3500000 }, | |
218 | .n = { .min = 1, .max = 3 }, | |
219 | .m = { .min = 104, .max = 138 }, | |
220 | .m1 = { .min = 17, .max = 23 }, | |
221 | .m2 = { .min = 5, .max = 11 }, | |
222 | .p = { .min = 14, .max = 42 }, | |
223 | .p1 = { .min = 2, .max = 6 }, | |
224 | .p2 = { .dot_limit = 0, | |
225 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 226 | }, |
d4906093 | 227 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
228 | }; |
229 | ||
230 | static const intel_limit_t intel_limits_g4x_display_port = { | |
0206e353 AJ |
231 | .dot = { .min = 161670, .max = 227000 }, |
232 | .vco = { .min = 1750000, .max = 3500000}, | |
233 | .n = { .min = 1, .max = 2 }, | |
234 | .m = { .min = 97, .max = 108 }, | |
235 | .m1 = { .min = 0x10, .max = 0x12 }, | |
236 | .m2 = { .min = 0x05, .max = 0x06 }, | |
237 | .p = { .min = 10, .max = 20 }, | |
238 | .p1 = { .min = 1, .max = 2}, | |
239 | .p2 = { .dot_limit = 0, | |
273e27ca | 240 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 241 | .find_pll = intel_find_pll_g4x_dp, |
e4b36699 KP |
242 | }; |
243 | ||
f2b115e6 | 244 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
245 | .dot = { .min = 20000, .max = 400000}, |
246 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 247 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
248 | .n = { .min = 3, .max = 6 }, |
249 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 250 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
251 | .m1 = { .min = 0, .max = 0 }, |
252 | .m2 = { .min = 0, .max = 254 }, | |
253 | .p = { .min = 5, .max = 80 }, | |
254 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
255 | .p2 = { .dot_limit = 200000, |
256 | .p2_slow = 10, .p2_fast = 5 }, | |
6115707b | 257 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
258 | }; |
259 | ||
f2b115e6 | 260 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
261 | .dot = { .min = 20000, .max = 400000 }, |
262 | .vco = { .min = 1700000, .max = 3500000 }, | |
263 | .n = { .min = 3, .max = 6 }, | |
264 | .m = { .min = 2, .max = 256 }, | |
265 | .m1 = { .min = 0, .max = 0 }, | |
266 | .m2 = { .min = 0, .max = 254 }, | |
267 | .p = { .min = 7, .max = 112 }, | |
268 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
269 | .p2 = { .dot_limit = 112000, |
270 | .p2_slow = 14, .p2_fast = 14 }, | |
6115707b | 271 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
272 | }; |
273 | ||
273e27ca EA |
274 | /* Ironlake / Sandybridge |
275 | * | |
276 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
277 | * the range value for them is (actual_value - 2). | |
278 | */ | |
b91ad0ec | 279 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
280 | .dot = { .min = 25000, .max = 350000 }, |
281 | .vco = { .min = 1760000, .max = 3510000 }, | |
282 | .n = { .min = 1, .max = 5 }, | |
283 | .m = { .min = 79, .max = 127 }, | |
284 | .m1 = { .min = 12, .max = 22 }, | |
285 | .m2 = { .min = 5, .max = 9 }, | |
286 | .p = { .min = 5, .max = 80 }, | |
287 | .p1 = { .min = 1, .max = 8 }, | |
288 | .p2 = { .dot_limit = 225000, | |
289 | .p2_slow = 10, .p2_fast = 5 }, | |
4547668a | 290 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
291 | }; |
292 | ||
b91ad0ec | 293 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
294 | .dot = { .min = 25000, .max = 350000 }, |
295 | .vco = { .min = 1760000, .max = 3510000 }, | |
296 | .n = { .min = 1, .max = 3 }, | |
297 | .m = { .min = 79, .max = 118 }, | |
298 | .m1 = { .min = 12, .max = 22 }, | |
299 | .m2 = { .min = 5, .max = 9 }, | |
300 | .p = { .min = 28, .max = 112 }, | |
301 | .p1 = { .min = 2, .max = 8 }, | |
302 | .p2 = { .dot_limit = 225000, | |
303 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
304 | .find_pll = intel_g4x_find_best_PLL, |
305 | }; | |
306 | ||
307 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
308 | .dot = { .min = 25000, .max = 350000 }, |
309 | .vco = { .min = 1760000, .max = 3510000 }, | |
310 | .n = { .min = 1, .max = 3 }, | |
311 | .m = { .min = 79, .max = 127 }, | |
312 | .m1 = { .min = 12, .max = 22 }, | |
313 | .m2 = { .min = 5, .max = 9 }, | |
314 | .p = { .min = 14, .max = 56 }, | |
315 | .p1 = { .min = 2, .max = 8 }, | |
316 | .p2 = { .dot_limit = 225000, | |
317 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
318 | .find_pll = intel_g4x_find_best_PLL, |
319 | }; | |
320 | ||
273e27ca | 321 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 322 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
323 | .dot = { .min = 25000, .max = 350000 }, |
324 | .vco = { .min = 1760000, .max = 3510000 }, | |
325 | .n = { .min = 1, .max = 2 }, | |
326 | .m = { .min = 79, .max = 126 }, | |
327 | .m1 = { .min = 12, .max = 22 }, | |
328 | .m2 = { .min = 5, .max = 9 }, | |
329 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 330 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
331 | .p2 = { .dot_limit = 225000, |
332 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
333 | .find_pll = intel_g4x_find_best_PLL, |
334 | }; | |
335 | ||
336 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
337 | .dot = { .min = 25000, .max = 350000 }, |
338 | .vco = { .min = 1760000, .max = 3510000 }, | |
339 | .n = { .min = 1, .max = 3 }, | |
340 | .m = { .min = 79, .max = 126 }, | |
341 | .m1 = { .min = 12, .max = 22 }, | |
342 | .m2 = { .min = 5, .max = 9 }, | |
343 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 344 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
345 | .p2 = { .dot_limit = 225000, |
346 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
347 | .find_pll = intel_g4x_find_best_PLL, |
348 | }; | |
349 | ||
350 | static const intel_limit_t intel_limits_ironlake_display_port = { | |
0206e353 AJ |
351 | .dot = { .min = 25000, .max = 350000 }, |
352 | .vco = { .min = 1760000, .max = 3510000}, | |
353 | .n = { .min = 1, .max = 2 }, | |
354 | .m = { .min = 81, .max = 90 }, | |
355 | .m1 = { .min = 12, .max = 22 }, | |
356 | .m2 = { .min = 5, .max = 9 }, | |
357 | .p = { .min = 10, .max = 20 }, | |
358 | .p1 = { .min = 1, .max = 2}, | |
359 | .p2 = { .dot_limit = 0, | |
273e27ca | 360 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 361 | .find_pll = intel_find_pll_ironlake_dp, |
79e53945 JB |
362 | }; |
363 | ||
57f350b6 JB |
364 | u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) |
365 | { | |
366 | unsigned long flags; | |
367 | u32 val = 0; | |
368 | ||
369 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); | |
370 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { | |
371 | DRM_ERROR("DPIO idle wait timed out\n"); | |
372 | goto out_unlock; | |
373 | } | |
374 | ||
375 | I915_WRITE(DPIO_REG, reg); | |
376 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID | | |
377 | DPIO_BYTE); | |
378 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { | |
379 | DRM_ERROR("DPIO read wait timed out\n"); | |
380 | goto out_unlock; | |
381 | } | |
382 | val = I915_READ(DPIO_DATA); | |
383 | ||
384 | out_unlock: | |
385 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); | |
386 | return val; | |
387 | } | |
388 | ||
389 | static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, | |
390 | u32 val) | |
391 | { | |
392 | unsigned long flags; | |
393 | ||
394 | spin_lock_irqsave(&dev_priv->dpio_lock, flags); | |
395 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { | |
396 | DRM_ERROR("DPIO idle wait timed out\n"); | |
397 | goto out_unlock; | |
398 | } | |
399 | ||
400 | I915_WRITE(DPIO_DATA, val); | |
401 | I915_WRITE(DPIO_REG, reg); | |
402 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID | | |
403 | DPIO_BYTE); | |
404 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) | |
405 | DRM_ERROR("DPIO write wait timed out\n"); | |
406 | ||
407 | out_unlock: | |
408 | spin_unlock_irqrestore(&dev_priv->dpio_lock, flags); | |
409 | } | |
410 | ||
411 | static void vlv_init_dpio(struct drm_device *dev) | |
412 | { | |
413 | struct drm_i915_private *dev_priv = dev->dev_private; | |
414 | ||
415 | /* Reset the DPIO config */ | |
416 | I915_WRITE(DPIO_CTL, 0); | |
417 | POSTING_READ(DPIO_CTL); | |
418 | I915_WRITE(DPIO_CTL, 1); | |
419 | POSTING_READ(DPIO_CTL); | |
420 | } | |
421 | ||
618563e3 DV |
422 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
423 | { | |
424 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); | |
425 | return 1; | |
426 | } | |
427 | ||
428 | static const struct dmi_system_id intel_dual_link_lvds[] = { | |
429 | { | |
430 | .callback = intel_dual_link_lvds_callback, | |
431 | .ident = "Apple MacBook Pro (Core i5/i7 Series)", | |
432 | .matches = { | |
433 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
434 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), | |
435 | }, | |
436 | }, | |
437 | { } /* terminating entry */ | |
438 | }; | |
439 | ||
b0354385 TI |
440 | static bool is_dual_link_lvds(struct drm_i915_private *dev_priv, |
441 | unsigned int reg) | |
442 | { | |
443 | unsigned int val; | |
444 | ||
121d527a TI |
445 | /* use the module option value if specified */ |
446 | if (i915_lvds_channel_mode > 0) | |
447 | return i915_lvds_channel_mode == 2; | |
448 | ||
618563e3 DV |
449 | if (dmi_check_system(intel_dual_link_lvds)) |
450 | return true; | |
451 | ||
b0354385 TI |
452 | if (dev_priv->lvds_val) |
453 | val = dev_priv->lvds_val; | |
454 | else { | |
455 | /* BIOS should set the proper LVDS register value at boot, but | |
456 | * in reality, it doesn't set the value when the lid is closed; | |
457 | * we need to check "the value to be set" in VBT when LVDS | |
458 | * register is uninitialized. | |
459 | */ | |
460 | val = I915_READ(reg); | |
461 | if (!(val & ~LVDS_DETECTED)) | |
462 | val = dev_priv->bios_lvds_val; | |
463 | dev_priv->lvds_val = val; | |
464 | } | |
465 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; | |
466 | } | |
467 | ||
1b894b59 CW |
468 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
469 | int refclk) | |
2c07245f | 470 | { |
b91ad0ec ZW |
471 | struct drm_device *dev = crtc->dev; |
472 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2c07245f | 473 | const intel_limit_t *limit; |
b91ad0ec ZW |
474 | |
475 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
b0354385 | 476 | if (is_dual_link_lvds(dev_priv, PCH_LVDS)) { |
b91ad0ec | 477 | /* LVDS dual channel */ |
1b894b59 | 478 | if (refclk == 100000) |
b91ad0ec ZW |
479 | limit = &intel_limits_ironlake_dual_lvds_100m; |
480 | else | |
481 | limit = &intel_limits_ironlake_dual_lvds; | |
482 | } else { | |
1b894b59 | 483 | if (refclk == 100000) |
b91ad0ec ZW |
484 | limit = &intel_limits_ironlake_single_lvds_100m; |
485 | else | |
486 | limit = &intel_limits_ironlake_single_lvds; | |
487 | } | |
488 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
4547668a ZY |
489 | HAS_eDP) |
490 | limit = &intel_limits_ironlake_display_port; | |
2c07245f | 491 | else |
b91ad0ec | 492 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
493 | |
494 | return limit; | |
495 | } | |
496 | ||
044c7c41 ML |
497 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
498 | { | |
499 | struct drm_device *dev = crtc->dev; | |
500 | struct drm_i915_private *dev_priv = dev->dev_private; | |
501 | const intel_limit_t *limit; | |
502 | ||
503 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
b0354385 | 504 | if (is_dual_link_lvds(dev_priv, LVDS)) |
044c7c41 | 505 | /* LVDS with dual channel */ |
e4b36699 | 506 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
507 | else |
508 | /* LVDS with dual channel */ | |
e4b36699 | 509 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
510 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
511 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 512 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 513 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 514 | limit = &intel_limits_g4x_sdvo; |
0206e353 | 515 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 516 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 517 | } else /* The option is for other outputs */ |
e4b36699 | 518 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
519 | |
520 | return limit; | |
521 | } | |
522 | ||
1b894b59 | 523 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
524 | { |
525 | struct drm_device *dev = crtc->dev; | |
526 | const intel_limit_t *limit; | |
527 | ||
bad720ff | 528 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 529 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 530 | else if (IS_G4X(dev)) { |
044c7c41 | 531 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 532 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 533 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 534 | limit = &intel_limits_pineview_lvds; |
2177832f | 535 | else |
f2b115e6 | 536 | limit = &intel_limits_pineview_sdvo; |
a6c45cf0 CW |
537 | } else if (!IS_GEN2(dev)) { |
538 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
539 | limit = &intel_limits_i9xx_lvds; | |
540 | else | |
541 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
542 | } else { |
543 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 544 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 545 | else |
e4b36699 | 546 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
547 | } |
548 | return limit; | |
549 | } | |
550 | ||
f2b115e6 AJ |
551 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
552 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 553 | { |
2177832f SL |
554 | clock->m = clock->m2 + 2; |
555 | clock->p = clock->p1 * clock->p2; | |
556 | clock->vco = refclk * clock->m / clock->n; | |
557 | clock->dot = clock->vco / clock->p; | |
558 | } | |
559 | ||
560 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
561 | { | |
f2b115e6 AJ |
562 | if (IS_PINEVIEW(dev)) { |
563 | pineview_clock(refclk, clock); | |
2177832f SL |
564 | return; |
565 | } | |
79e53945 JB |
566 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
567 | clock->p = clock->p1 * clock->p2; | |
568 | clock->vco = refclk * clock->m / (clock->n + 2); | |
569 | clock->dot = clock->vco / clock->p; | |
570 | } | |
571 | ||
79e53945 JB |
572 | /** |
573 | * Returns whether any output on the specified pipe is of the specified type | |
574 | */ | |
4ef69c7a | 575 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 576 | { |
4ef69c7a CW |
577 | struct drm_device *dev = crtc->dev; |
578 | struct drm_mode_config *mode_config = &dev->mode_config; | |
579 | struct intel_encoder *encoder; | |
580 | ||
581 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
582 | if (encoder->base.crtc == crtc && encoder->type == type) | |
583 | return true; | |
584 | ||
585 | return false; | |
79e53945 JB |
586 | } |
587 | ||
7c04d1d9 | 588 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
589 | /** |
590 | * Returns whether the given set of divisors are valid for a given refclk with | |
591 | * the given connectors. | |
592 | */ | |
593 | ||
1b894b59 CW |
594 | static bool intel_PLL_is_valid(struct drm_device *dev, |
595 | const intel_limit_t *limit, | |
596 | const intel_clock_t *clock) | |
79e53945 | 597 | { |
79e53945 | 598 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 599 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 600 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
0206e353 | 601 | INTELPllInvalid("p out of range\n"); |
79e53945 | 602 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 603 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 604 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 605 | INTELPllInvalid("m1 out of range\n"); |
f2b115e6 | 606 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
0206e353 | 607 | INTELPllInvalid("m1 <= m2\n"); |
79e53945 | 608 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
0206e353 | 609 | INTELPllInvalid("m out of range\n"); |
79e53945 | 610 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
0206e353 | 611 | INTELPllInvalid("n out of range\n"); |
79e53945 | 612 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 613 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
614 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
615 | * connector, etc., rather than just a single range. | |
616 | */ | |
617 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 618 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
619 | |
620 | return true; | |
621 | } | |
622 | ||
d4906093 ML |
623 | static bool |
624 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
625 | int target, int refclk, intel_clock_t *match_clock, |
626 | intel_clock_t *best_clock) | |
d4906093 | 627 | |
79e53945 JB |
628 | { |
629 | struct drm_device *dev = crtc->dev; | |
630 | struct drm_i915_private *dev_priv = dev->dev_private; | |
631 | intel_clock_t clock; | |
79e53945 JB |
632 | int err = target; |
633 | ||
bc5e5718 | 634 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
832cc28d | 635 | (I915_READ(LVDS)) != 0) { |
79e53945 JB |
636 | /* |
637 | * For LVDS, if the panel is on, just rely on its current | |
638 | * settings for dual-channel. We haven't figured out how to | |
639 | * reliably set up different single/dual channel state, if we | |
640 | * even can. | |
641 | */ | |
b0354385 | 642 | if (is_dual_link_lvds(dev_priv, LVDS)) |
79e53945 JB |
643 | clock.p2 = limit->p2.p2_fast; |
644 | else | |
645 | clock.p2 = limit->p2.p2_slow; | |
646 | } else { | |
647 | if (target < limit->p2.dot_limit) | |
648 | clock.p2 = limit->p2.p2_slow; | |
649 | else | |
650 | clock.p2 = limit->p2.p2_fast; | |
651 | } | |
652 | ||
0206e353 | 653 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 654 | |
42158660 ZY |
655 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
656 | clock.m1++) { | |
657 | for (clock.m2 = limit->m2.min; | |
658 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
659 | /* m1 is always 0 in Pineview */ |
660 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
661 | break; |
662 | for (clock.n = limit->n.min; | |
663 | clock.n <= limit->n.max; clock.n++) { | |
664 | for (clock.p1 = limit->p1.min; | |
665 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
666 | int this_err; |
667 | ||
2177832f | 668 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
669 | if (!intel_PLL_is_valid(dev, limit, |
670 | &clock)) | |
79e53945 | 671 | continue; |
cec2f356 SP |
672 | if (match_clock && |
673 | clock.p != match_clock->p) | |
674 | continue; | |
79e53945 JB |
675 | |
676 | this_err = abs(clock.dot - target); | |
677 | if (this_err < err) { | |
678 | *best_clock = clock; | |
679 | err = this_err; | |
680 | } | |
681 | } | |
682 | } | |
683 | } | |
684 | } | |
685 | ||
686 | return (err != target); | |
687 | } | |
688 | ||
d4906093 ML |
689 | static bool |
690 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
691 | int target, int refclk, intel_clock_t *match_clock, |
692 | intel_clock_t *best_clock) | |
d4906093 ML |
693 | { |
694 | struct drm_device *dev = crtc->dev; | |
695 | struct drm_i915_private *dev_priv = dev->dev_private; | |
696 | intel_clock_t clock; | |
697 | int max_n; | |
698 | bool found; | |
6ba770dc AJ |
699 | /* approximately equals target * 0.00585 */ |
700 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
701 | found = false; |
702 | ||
703 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
704 | int lvds_reg; |
705 | ||
c619eed4 | 706 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
707 | lvds_reg = PCH_LVDS; |
708 | else | |
709 | lvds_reg = LVDS; | |
710 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == | |
d4906093 ML |
711 | LVDS_CLKB_POWER_UP) |
712 | clock.p2 = limit->p2.p2_fast; | |
713 | else | |
714 | clock.p2 = limit->p2.p2_slow; | |
715 | } else { | |
716 | if (target < limit->p2.dot_limit) | |
717 | clock.p2 = limit->p2.p2_slow; | |
718 | else | |
719 | clock.p2 = limit->p2.p2_fast; | |
720 | } | |
721 | ||
722 | memset(best_clock, 0, sizeof(*best_clock)); | |
723 | max_n = limit->n.max; | |
f77f13e2 | 724 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 725 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 726 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
727 | for (clock.m1 = limit->m1.max; |
728 | clock.m1 >= limit->m1.min; clock.m1--) { | |
729 | for (clock.m2 = limit->m2.max; | |
730 | clock.m2 >= limit->m2.min; clock.m2--) { | |
731 | for (clock.p1 = limit->p1.max; | |
732 | clock.p1 >= limit->p1.min; clock.p1--) { | |
733 | int this_err; | |
734 | ||
2177832f | 735 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
736 | if (!intel_PLL_is_valid(dev, limit, |
737 | &clock)) | |
d4906093 | 738 | continue; |
cec2f356 SP |
739 | if (match_clock && |
740 | clock.p != match_clock->p) | |
741 | continue; | |
1b894b59 CW |
742 | |
743 | this_err = abs(clock.dot - target); | |
d4906093 ML |
744 | if (this_err < err_most) { |
745 | *best_clock = clock; | |
746 | err_most = this_err; | |
747 | max_n = clock.n; | |
748 | found = true; | |
749 | } | |
750 | } | |
751 | } | |
752 | } | |
753 | } | |
2c07245f ZW |
754 | return found; |
755 | } | |
756 | ||
5eb08b69 | 757 | static bool |
f2b115e6 | 758 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
759 | int target, int refclk, intel_clock_t *match_clock, |
760 | intel_clock_t *best_clock) | |
5eb08b69 ZW |
761 | { |
762 | struct drm_device *dev = crtc->dev; | |
763 | intel_clock_t clock; | |
4547668a | 764 | |
5eb08b69 ZW |
765 | if (target < 200000) { |
766 | clock.n = 1; | |
767 | clock.p1 = 2; | |
768 | clock.p2 = 10; | |
769 | clock.m1 = 12; | |
770 | clock.m2 = 9; | |
771 | } else { | |
772 | clock.n = 2; | |
773 | clock.p1 = 1; | |
774 | clock.p2 = 10; | |
775 | clock.m1 = 14; | |
776 | clock.m2 = 8; | |
777 | } | |
778 | intel_clock(dev, refclk, &clock); | |
779 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
780 | return true; | |
781 | } | |
782 | ||
a4fc5ed6 KP |
783 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
784 | static bool | |
785 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
786 | int target, int refclk, intel_clock_t *match_clock, |
787 | intel_clock_t *best_clock) | |
a4fc5ed6 | 788 | { |
5eddb70b CW |
789 | intel_clock_t clock; |
790 | if (target < 200000) { | |
791 | clock.p1 = 2; | |
792 | clock.p2 = 10; | |
793 | clock.n = 2; | |
794 | clock.m1 = 23; | |
795 | clock.m2 = 8; | |
796 | } else { | |
797 | clock.p1 = 1; | |
798 | clock.p2 = 10; | |
799 | clock.n = 1; | |
800 | clock.m1 = 14; | |
801 | clock.m2 = 2; | |
802 | } | |
803 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); | |
804 | clock.p = (clock.p1 * clock.p2); | |
805 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
806 | clock.vco = 0; | |
807 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
808 | return true; | |
a4fc5ed6 KP |
809 | } |
810 | ||
9d0498a2 JB |
811 | /** |
812 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
813 | * @dev: drm device | |
814 | * @pipe: pipe to wait for | |
815 | * | |
816 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
817 | * mode setting code. | |
818 | */ | |
819 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 820 | { |
9d0498a2 | 821 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 822 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 823 | |
300387c0 CW |
824 | /* Clear existing vblank status. Note this will clear any other |
825 | * sticky status fields as well. | |
826 | * | |
827 | * This races with i915_driver_irq_handler() with the result | |
828 | * that either function could miss a vblank event. Here it is not | |
829 | * fatal, as we will either wait upon the next vblank interrupt or | |
830 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
831 | * called during modeset at which time the GPU should be idle and | |
832 | * should *not* be performing page flips and thus not waiting on | |
833 | * vblanks... | |
834 | * Currently, the result of us stealing a vblank from the irq | |
835 | * handler is that a single frame will be skipped during swapbuffers. | |
836 | */ | |
837 | I915_WRITE(pipestat_reg, | |
838 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
839 | ||
9d0498a2 | 840 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
841 | if (wait_for(I915_READ(pipestat_reg) & |
842 | PIPE_VBLANK_INTERRUPT_STATUS, | |
843 | 50)) | |
9d0498a2 JB |
844 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
845 | } | |
846 | ||
ab7ad7f6 KP |
847 | /* |
848 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
849 | * @dev: drm device |
850 | * @pipe: pipe to wait for | |
851 | * | |
852 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
853 | * spinning on the vblank interrupt status bit, since we won't actually | |
854 | * see an interrupt when the pipe is disabled. | |
855 | * | |
ab7ad7f6 KP |
856 | * On Gen4 and above: |
857 | * wait for the pipe register state bit to turn off | |
858 | * | |
859 | * Otherwise: | |
860 | * wait for the display line value to settle (it usually | |
861 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 862 | * |
9d0498a2 | 863 | */ |
58e10eb9 | 864 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
865 | { |
866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ab7ad7f6 KP |
867 | |
868 | if (INTEL_INFO(dev)->gen >= 4) { | |
58e10eb9 | 869 | int reg = PIPECONF(pipe); |
ab7ad7f6 KP |
870 | |
871 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
872 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
873 | 100)) | |
ab7ad7f6 KP |
874 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); |
875 | } else { | |
876 | u32 last_line; | |
58e10eb9 | 877 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
878 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
879 | ||
880 | /* Wait for the display line to settle */ | |
881 | do { | |
58e10eb9 | 882 | last_line = I915_READ(reg) & DSL_LINEMASK; |
ab7ad7f6 | 883 | mdelay(5); |
58e10eb9 | 884 | } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) && |
ab7ad7f6 KP |
885 | time_after(timeout, jiffies)); |
886 | if (time_after(jiffies, timeout)) | |
887 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); | |
888 | } | |
79e53945 JB |
889 | } |
890 | ||
b24e7179 JB |
891 | static const char *state_string(bool enabled) |
892 | { | |
893 | return enabled ? "on" : "off"; | |
894 | } | |
895 | ||
896 | /* Only for pre-ILK configs */ | |
897 | static void assert_pll(struct drm_i915_private *dev_priv, | |
898 | enum pipe pipe, bool state) | |
899 | { | |
900 | int reg; | |
901 | u32 val; | |
902 | bool cur_state; | |
903 | ||
904 | reg = DPLL(pipe); | |
905 | val = I915_READ(reg); | |
906 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
907 | WARN(cur_state != state, | |
908 | "PLL state assertion failure (expected %s, current %s)\n", | |
909 | state_string(state), state_string(cur_state)); | |
910 | } | |
911 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
912 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
913 | ||
040484af JB |
914 | /* For ILK+ */ |
915 | static void assert_pch_pll(struct drm_i915_private *dev_priv, | |
916 | enum pipe pipe, bool state) | |
917 | { | |
918 | int reg; | |
919 | u32 val; | |
920 | bool cur_state; | |
921 | ||
d3ccbe86 JB |
922 | if (HAS_PCH_CPT(dev_priv->dev)) { |
923 | u32 pch_dpll; | |
924 | ||
925 | pch_dpll = I915_READ(PCH_DPLL_SEL); | |
926 | ||
927 | /* Make sure the selected PLL is enabled to the transcoder */ | |
928 | WARN(!((pch_dpll >> (4 * pipe)) & 8), | |
929 | "transcoder %d PLL not enabled\n", pipe); | |
930 | ||
931 | /* Convert the transcoder pipe number to a pll pipe number */ | |
932 | pipe = (pch_dpll >> (4 * pipe)) & 1; | |
933 | } | |
934 | ||
040484af JB |
935 | reg = PCH_DPLL(pipe); |
936 | val = I915_READ(reg); | |
937 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
938 | WARN(cur_state != state, | |
939 | "PCH PLL state assertion failure (expected %s, current %s)\n", | |
940 | state_string(state), state_string(cur_state)); | |
941 | } | |
942 | #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true) | |
943 | #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false) | |
944 | ||
945 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
946 | enum pipe pipe, bool state) | |
947 | { | |
948 | int reg; | |
949 | u32 val; | |
950 | bool cur_state; | |
951 | ||
952 | reg = FDI_TX_CTL(pipe); | |
953 | val = I915_READ(reg); | |
954 | cur_state = !!(val & FDI_TX_ENABLE); | |
955 | WARN(cur_state != state, | |
956 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
957 | state_string(state), state_string(cur_state)); | |
958 | } | |
959 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
960 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
961 | ||
962 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
963 | enum pipe pipe, bool state) | |
964 | { | |
965 | int reg; | |
966 | u32 val; | |
967 | bool cur_state; | |
968 | ||
969 | reg = FDI_RX_CTL(pipe); | |
970 | val = I915_READ(reg); | |
971 | cur_state = !!(val & FDI_RX_ENABLE); | |
972 | WARN(cur_state != state, | |
973 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
974 | state_string(state), state_string(cur_state)); | |
975 | } | |
976 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
977 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
978 | ||
979 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
980 | enum pipe pipe) | |
981 | { | |
982 | int reg; | |
983 | u32 val; | |
984 | ||
985 | /* ILK FDI PLL is always enabled */ | |
986 | if (dev_priv->info->gen == 5) | |
987 | return; | |
988 | ||
989 | reg = FDI_TX_CTL(pipe); | |
990 | val = I915_READ(reg); | |
991 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
992 | } | |
993 | ||
994 | static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, | |
995 | enum pipe pipe) | |
996 | { | |
997 | int reg; | |
998 | u32 val; | |
999 | ||
1000 | reg = FDI_RX_CTL(pipe); | |
1001 | val = I915_READ(reg); | |
1002 | WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); | |
1003 | } | |
1004 | ||
ea0760cf JB |
1005 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1006 | enum pipe pipe) | |
1007 | { | |
1008 | int pp_reg, lvds_reg; | |
1009 | u32 val; | |
1010 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1011 | bool locked = true; |
ea0760cf JB |
1012 | |
1013 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1014 | pp_reg = PCH_PP_CONTROL; | |
1015 | lvds_reg = PCH_LVDS; | |
1016 | } else { | |
1017 | pp_reg = PP_CONTROL; | |
1018 | lvds_reg = LVDS; | |
1019 | } | |
1020 | ||
1021 | val = I915_READ(pp_reg); | |
1022 | if (!(val & PANEL_POWER_ON) || | |
1023 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1024 | locked = false; | |
1025 | ||
1026 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1027 | panel_pipe = PIPE_B; | |
1028 | ||
1029 | WARN(panel_pipe == pipe && locked, | |
1030 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1031 | pipe_name(pipe)); |
ea0760cf JB |
1032 | } |
1033 | ||
b840d907 JB |
1034 | void assert_pipe(struct drm_i915_private *dev_priv, |
1035 | enum pipe pipe, bool state) | |
b24e7179 JB |
1036 | { |
1037 | int reg; | |
1038 | u32 val; | |
63d7bbe9 | 1039 | bool cur_state; |
b24e7179 | 1040 | |
8e636784 DV |
1041 | /* if we need the pipe A quirk it must be always on */ |
1042 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1043 | state = true; | |
1044 | ||
b24e7179 JB |
1045 | reg = PIPECONF(pipe); |
1046 | val = I915_READ(reg); | |
63d7bbe9 JB |
1047 | cur_state = !!(val & PIPECONF_ENABLE); |
1048 | WARN(cur_state != state, | |
1049 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1050 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1051 | } |
1052 | ||
931872fc CW |
1053 | static void assert_plane(struct drm_i915_private *dev_priv, |
1054 | enum plane plane, bool state) | |
b24e7179 JB |
1055 | { |
1056 | int reg; | |
1057 | u32 val; | |
931872fc | 1058 | bool cur_state; |
b24e7179 JB |
1059 | |
1060 | reg = DSPCNTR(plane); | |
1061 | val = I915_READ(reg); | |
931872fc CW |
1062 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1063 | WARN(cur_state != state, | |
1064 | "plane %c assertion failure (expected %s, current %s)\n", | |
1065 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1066 | } |
1067 | ||
931872fc CW |
1068 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1069 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1070 | ||
b24e7179 JB |
1071 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1072 | enum pipe pipe) | |
1073 | { | |
1074 | int reg, i; | |
1075 | u32 val; | |
1076 | int cur_pipe; | |
1077 | ||
19ec1358 | 1078 | /* Planes are fixed to pipes on ILK+ */ |
28c05794 AJ |
1079 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
1080 | reg = DSPCNTR(pipe); | |
1081 | val = I915_READ(reg); | |
1082 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1083 | "plane %c assertion failure, should be disabled but not\n", | |
1084 | plane_name(pipe)); | |
19ec1358 | 1085 | return; |
28c05794 | 1086 | } |
19ec1358 | 1087 | |
b24e7179 JB |
1088 | /* Need to check both planes against the pipe */ |
1089 | for (i = 0; i < 2; i++) { | |
1090 | reg = DSPCNTR(i); | |
1091 | val = I915_READ(reg); | |
1092 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1093 | DISPPLANE_SEL_PIPE_SHIFT; | |
1094 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1095 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1096 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1097 | } |
1098 | } | |
1099 | ||
92f2584a JB |
1100 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1101 | { | |
1102 | u32 val; | |
1103 | bool enabled; | |
1104 | ||
1105 | val = I915_READ(PCH_DREF_CONTROL); | |
1106 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1107 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1108 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1109 | } | |
1110 | ||
1111 | static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, | |
1112 | enum pipe pipe) | |
1113 | { | |
1114 | int reg; | |
1115 | u32 val; | |
1116 | bool enabled; | |
1117 | ||
1118 | reg = TRANSCONF(pipe); | |
1119 | val = I915_READ(reg); | |
1120 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1121 | WARN(enabled, |
1122 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1123 | pipe_name(pipe)); | |
92f2584a JB |
1124 | } |
1125 | ||
4e634389 KP |
1126 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1127 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1128 | { |
1129 | if ((val & DP_PORT_EN) == 0) | |
1130 | return false; | |
1131 | ||
1132 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1133 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1134 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1135 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1136 | return false; | |
1137 | } else { | |
1138 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1139 | return false; | |
1140 | } | |
1141 | return true; | |
1142 | } | |
1143 | ||
1519b995 KP |
1144 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1145 | enum pipe pipe, u32 val) | |
1146 | { | |
1147 | if ((val & PORT_ENABLE) == 0) | |
1148 | return false; | |
1149 | ||
1150 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1151 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1152 | return false; | |
1153 | } else { | |
1154 | if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) | |
1155 | return false; | |
1156 | } | |
1157 | return true; | |
1158 | } | |
1159 | ||
1160 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1161 | enum pipe pipe, u32 val) | |
1162 | { | |
1163 | if ((val & LVDS_PORT_EN) == 0) | |
1164 | return false; | |
1165 | ||
1166 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1167 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1168 | return false; | |
1169 | } else { | |
1170 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1171 | return false; | |
1172 | } | |
1173 | return true; | |
1174 | } | |
1175 | ||
1176 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1177 | enum pipe pipe, u32 val) | |
1178 | { | |
1179 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1180 | return false; | |
1181 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1182 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1183 | return false; | |
1184 | } else { | |
1185 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1186 | return false; | |
1187 | } | |
1188 | return true; | |
1189 | } | |
1190 | ||
291906f1 | 1191 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1192 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1193 | { |
47a05eca | 1194 | u32 val = I915_READ(reg); |
4e634389 | 1195 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1196 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1197 | reg, pipe_name(pipe)); |
291906f1 JB |
1198 | } |
1199 | ||
1200 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1201 | enum pipe pipe, int reg) | |
1202 | { | |
47a05eca | 1203 | u32 val = I915_READ(reg); |
1519b995 | 1204 | WARN(hdmi_pipe_enabled(dev_priv, val, pipe), |
23c99e77 | 1205 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1206 | reg, pipe_name(pipe)); |
291906f1 JB |
1207 | } |
1208 | ||
1209 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1210 | enum pipe pipe) | |
1211 | { | |
1212 | int reg; | |
1213 | u32 val; | |
291906f1 | 1214 | |
f0575e92 KP |
1215 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1216 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1217 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1218 | |
1219 | reg = PCH_ADPA; | |
1220 | val = I915_READ(reg); | |
1519b995 | 1221 | WARN(adpa_pipe_enabled(dev_priv, val, pipe), |
291906f1 | 1222 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1223 | pipe_name(pipe)); |
291906f1 JB |
1224 | |
1225 | reg = PCH_LVDS; | |
1226 | val = I915_READ(reg); | |
1519b995 | 1227 | WARN(lvds_pipe_enabled(dev_priv, val, pipe), |
291906f1 | 1228 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1229 | pipe_name(pipe)); |
291906f1 JB |
1230 | |
1231 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); | |
1232 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); | |
1233 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); | |
1234 | } | |
1235 | ||
63d7bbe9 JB |
1236 | /** |
1237 | * intel_enable_pll - enable a PLL | |
1238 | * @dev_priv: i915 private structure | |
1239 | * @pipe: pipe PLL to enable | |
1240 | * | |
1241 | * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to | |
1242 | * make sure the PLL reg is writable first though, since the panel write | |
1243 | * protect mechanism may be enabled. | |
1244 | * | |
1245 | * Note! This is for pre-ILK only. | |
1246 | */ | |
1247 | static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1248 | { | |
1249 | int reg; | |
1250 | u32 val; | |
1251 | ||
1252 | /* No really, not for ILK+ */ | |
1253 | BUG_ON(dev_priv->info->gen >= 5); | |
1254 | ||
1255 | /* PLL is protected by panel, make sure we can write it */ | |
1256 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
1257 | assert_panel_unlocked(dev_priv, pipe); | |
1258 | ||
1259 | reg = DPLL(pipe); | |
1260 | val = I915_READ(reg); | |
1261 | val |= DPLL_VCO_ENABLE; | |
1262 | ||
1263 | /* We do this three times for luck */ | |
1264 | I915_WRITE(reg, val); | |
1265 | POSTING_READ(reg); | |
1266 | udelay(150); /* wait for warmup */ | |
1267 | I915_WRITE(reg, val); | |
1268 | POSTING_READ(reg); | |
1269 | udelay(150); /* wait for warmup */ | |
1270 | I915_WRITE(reg, val); | |
1271 | POSTING_READ(reg); | |
1272 | udelay(150); /* wait for warmup */ | |
1273 | } | |
1274 | ||
1275 | /** | |
1276 | * intel_disable_pll - disable a PLL | |
1277 | * @dev_priv: i915 private structure | |
1278 | * @pipe: pipe PLL to disable | |
1279 | * | |
1280 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1281 | * | |
1282 | * Note! This is for pre-ILK only. | |
1283 | */ | |
1284 | static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1285 | { | |
1286 | int reg; | |
1287 | u32 val; | |
1288 | ||
1289 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1290 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1291 | return; | |
1292 | ||
1293 | /* Make sure the pipe isn't still relying on us */ | |
1294 | assert_pipe_disabled(dev_priv, pipe); | |
1295 | ||
1296 | reg = DPLL(pipe); | |
1297 | val = I915_READ(reg); | |
1298 | val &= ~DPLL_VCO_ENABLE; | |
1299 | I915_WRITE(reg, val); | |
1300 | POSTING_READ(reg); | |
1301 | } | |
1302 | ||
92f2584a JB |
1303 | /** |
1304 | * intel_enable_pch_pll - enable PCH PLL | |
1305 | * @dev_priv: i915 private structure | |
1306 | * @pipe: pipe PLL to enable | |
1307 | * | |
1308 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1309 | * drives the transcoder clock. | |
1310 | */ | |
1311 | static void intel_enable_pch_pll(struct drm_i915_private *dev_priv, | |
1312 | enum pipe pipe) | |
1313 | { | |
1314 | int reg; | |
1315 | u32 val; | |
1316 | ||
4c609cb8 JB |
1317 | if (pipe > 1) |
1318 | return; | |
1319 | ||
92f2584a JB |
1320 | /* PCH only available on ILK+ */ |
1321 | BUG_ON(dev_priv->info->gen < 5); | |
1322 | ||
1323 | /* PCH refclock must be enabled first */ | |
1324 | assert_pch_refclk_enabled(dev_priv); | |
1325 | ||
1326 | reg = PCH_DPLL(pipe); | |
1327 | val = I915_READ(reg); | |
1328 | val |= DPLL_VCO_ENABLE; | |
1329 | I915_WRITE(reg, val); | |
1330 | POSTING_READ(reg); | |
1331 | udelay(200); | |
1332 | } | |
1333 | ||
1334 | static void intel_disable_pch_pll(struct drm_i915_private *dev_priv, | |
1335 | enum pipe pipe) | |
1336 | { | |
1337 | int reg; | |
7a419866 JB |
1338 | u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL, |
1339 | pll_sel = TRANSC_DPLL_ENABLE; | |
92f2584a | 1340 | |
4c609cb8 JB |
1341 | if (pipe > 1) |
1342 | return; | |
1343 | ||
92f2584a JB |
1344 | /* PCH only available on ILK+ */ |
1345 | BUG_ON(dev_priv->info->gen < 5); | |
1346 | ||
1347 | /* Make sure transcoder isn't still depending on us */ | |
1348 | assert_transcoder_disabled(dev_priv, pipe); | |
1349 | ||
7a419866 JB |
1350 | if (pipe == 0) |
1351 | pll_sel |= TRANSC_DPLLA_SEL; | |
1352 | else if (pipe == 1) | |
1353 | pll_sel |= TRANSC_DPLLB_SEL; | |
1354 | ||
1355 | ||
1356 | if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel) | |
1357 | return; | |
1358 | ||
92f2584a JB |
1359 | reg = PCH_DPLL(pipe); |
1360 | val = I915_READ(reg); | |
1361 | val &= ~DPLL_VCO_ENABLE; | |
1362 | I915_WRITE(reg, val); | |
1363 | POSTING_READ(reg); | |
1364 | udelay(200); | |
1365 | } | |
1366 | ||
040484af JB |
1367 | static void intel_enable_transcoder(struct drm_i915_private *dev_priv, |
1368 | enum pipe pipe) | |
1369 | { | |
1370 | int reg; | |
5f7f726d | 1371 | u32 val, pipeconf_val; |
7c26e5c6 | 1372 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
040484af JB |
1373 | |
1374 | /* PCH only available on ILK+ */ | |
1375 | BUG_ON(dev_priv->info->gen < 5); | |
1376 | ||
1377 | /* Make sure PCH DPLL is enabled */ | |
1378 | assert_pch_pll_enabled(dev_priv, pipe); | |
1379 | ||
1380 | /* FDI must be feeding us bits for PCH ports */ | |
1381 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1382 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1383 | ||
1384 | reg = TRANSCONF(pipe); | |
1385 | val = I915_READ(reg); | |
5f7f726d | 1386 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1387 | |
1388 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1389 | /* | |
1390 | * make the BPC in transcoder be consistent with | |
1391 | * that in pipeconf reg. | |
1392 | */ | |
1393 | val &= ~PIPE_BPC_MASK; | |
5f7f726d | 1394 | val |= pipeconf_val & PIPE_BPC_MASK; |
e9bcff5c | 1395 | } |
5f7f726d PZ |
1396 | |
1397 | val &= ~TRANS_INTERLACE_MASK; | |
1398 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1399 | if (HAS_PCH_IBX(dev_priv->dev) && |
1400 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1401 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1402 | else | |
1403 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1404 | else |
1405 | val |= TRANS_PROGRESSIVE; | |
1406 | ||
040484af JB |
1407 | I915_WRITE(reg, val | TRANS_ENABLE); |
1408 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
1409 | DRM_ERROR("failed to enable transcoder %d\n", pipe); | |
1410 | } | |
1411 | ||
1412 | static void intel_disable_transcoder(struct drm_i915_private *dev_priv, | |
1413 | enum pipe pipe) | |
1414 | { | |
1415 | int reg; | |
1416 | u32 val; | |
1417 | ||
1418 | /* FDI relies on the transcoder */ | |
1419 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1420 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1421 | ||
291906f1 JB |
1422 | /* Ports must be off as well */ |
1423 | assert_pch_ports_disabled(dev_priv, pipe); | |
1424 | ||
040484af JB |
1425 | reg = TRANSCONF(pipe); |
1426 | val = I915_READ(reg); | |
1427 | val &= ~TRANS_ENABLE; | |
1428 | I915_WRITE(reg, val); | |
1429 | /* wait for PCH transcoder off, transcoder state */ | |
1430 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4c9c18c2 | 1431 | DRM_ERROR("failed to disable transcoder %d\n", pipe); |
040484af JB |
1432 | } |
1433 | ||
b24e7179 | 1434 | /** |
309cfea8 | 1435 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1436 | * @dev_priv: i915 private structure |
1437 | * @pipe: pipe to enable | |
040484af | 1438 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1439 | * |
1440 | * Enable @pipe, making sure that various hardware specific requirements | |
1441 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1442 | * | |
1443 | * @pipe should be %PIPE_A or %PIPE_B. | |
1444 | * | |
1445 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1446 | * returning. | |
1447 | */ | |
040484af JB |
1448 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1449 | bool pch_port) | |
b24e7179 JB |
1450 | { |
1451 | int reg; | |
1452 | u32 val; | |
1453 | ||
1454 | /* | |
1455 | * A pipe without a PLL won't actually be able to drive bits from | |
1456 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1457 | * need the check. | |
1458 | */ | |
1459 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
1460 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1461 | else { |
1462 | if (pch_port) { | |
1463 | /* if driving the PCH, we need FDI enabled */ | |
1464 | assert_fdi_rx_pll_enabled(dev_priv, pipe); | |
1465 | assert_fdi_tx_pll_enabled(dev_priv, pipe); | |
1466 | } | |
1467 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1468 | } | |
b24e7179 JB |
1469 | |
1470 | reg = PIPECONF(pipe); | |
1471 | val = I915_READ(reg); | |
00d70b15 CW |
1472 | if (val & PIPECONF_ENABLE) |
1473 | return; | |
1474 | ||
1475 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1476 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1477 | } | |
1478 | ||
1479 | /** | |
309cfea8 | 1480 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1481 | * @dev_priv: i915 private structure |
1482 | * @pipe: pipe to disable | |
1483 | * | |
1484 | * Disable @pipe, making sure that various hardware specific requirements | |
1485 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1486 | * | |
1487 | * @pipe should be %PIPE_A or %PIPE_B. | |
1488 | * | |
1489 | * Will wait until the pipe has shut down before returning. | |
1490 | */ | |
1491 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1492 | enum pipe pipe) | |
1493 | { | |
1494 | int reg; | |
1495 | u32 val; | |
1496 | ||
1497 | /* | |
1498 | * Make sure planes won't keep trying to pump pixels to us, | |
1499 | * or we might hang the display. | |
1500 | */ | |
1501 | assert_planes_disabled(dev_priv, pipe); | |
1502 | ||
1503 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1504 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1505 | return; | |
1506 | ||
1507 | reg = PIPECONF(pipe); | |
1508 | val = I915_READ(reg); | |
00d70b15 CW |
1509 | if ((val & PIPECONF_ENABLE) == 0) |
1510 | return; | |
1511 | ||
1512 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1513 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1514 | } | |
1515 | ||
d74362c9 KP |
1516 | /* |
1517 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1518 | * trigger in order to latch. The display address reg provides this. | |
1519 | */ | |
1520 | static void intel_flush_display_plane(struct drm_i915_private *dev_priv, | |
1521 | enum plane plane) | |
1522 | { | |
1523 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); | |
1524 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); | |
1525 | } | |
1526 | ||
b24e7179 JB |
1527 | /** |
1528 | * intel_enable_plane - enable a display plane on a given pipe | |
1529 | * @dev_priv: i915 private structure | |
1530 | * @plane: plane to enable | |
1531 | * @pipe: pipe being fed | |
1532 | * | |
1533 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1534 | */ | |
1535 | static void intel_enable_plane(struct drm_i915_private *dev_priv, | |
1536 | enum plane plane, enum pipe pipe) | |
1537 | { | |
1538 | int reg; | |
1539 | u32 val; | |
1540 | ||
1541 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1542 | assert_pipe_enabled(dev_priv, pipe); | |
1543 | ||
1544 | reg = DSPCNTR(plane); | |
1545 | val = I915_READ(reg); | |
00d70b15 CW |
1546 | if (val & DISPLAY_PLANE_ENABLE) |
1547 | return; | |
1548 | ||
1549 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
d74362c9 | 1550 | intel_flush_display_plane(dev_priv, plane); |
b24e7179 JB |
1551 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1552 | } | |
1553 | ||
b24e7179 JB |
1554 | /** |
1555 | * intel_disable_plane - disable a display plane | |
1556 | * @dev_priv: i915 private structure | |
1557 | * @plane: plane to disable | |
1558 | * @pipe: pipe consuming the data | |
1559 | * | |
1560 | * Disable @plane; should be an independent operation. | |
1561 | */ | |
1562 | static void intel_disable_plane(struct drm_i915_private *dev_priv, | |
1563 | enum plane plane, enum pipe pipe) | |
1564 | { | |
1565 | int reg; | |
1566 | u32 val; | |
1567 | ||
1568 | reg = DSPCNTR(plane); | |
1569 | val = I915_READ(reg); | |
00d70b15 CW |
1570 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1571 | return; | |
1572 | ||
1573 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
b24e7179 JB |
1574 | intel_flush_display_plane(dev_priv, plane); |
1575 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1576 | } | |
1577 | ||
47a05eca | 1578 | static void disable_pch_dp(struct drm_i915_private *dev_priv, |
f0575e92 | 1579 | enum pipe pipe, int reg, u32 port_sel) |
47a05eca JB |
1580 | { |
1581 | u32 val = I915_READ(reg); | |
4e634389 | 1582 | if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) { |
f0575e92 | 1583 | DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe); |
47a05eca | 1584 | I915_WRITE(reg, val & ~DP_PORT_EN); |
f0575e92 | 1585 | } |
47a05eca JB |
1586 | } |
1587 | ||
1588 | static void disable_pch_hdmi(struct drm_i915_private *dev_priv, | |
1589 | enum pipe pipe, int reg) | |
1590 | { | |
1591 | u32 val = I915_READ(reg); | |
1519b995 | 1592 | if (hdmi_pipe_enabled(dev_priv, val, pipe)) { |
f0575e92 KP |
1593 | DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n", |
1594 | reg, pipe); | |
47a05eca | 1595 | I915_WRITE(reg, val & ~PORT_ENABLE); |
f0575e92 | 1596 | } |
47a05eca JB |
1597 | } |
1598 | ||
1599 | /* Disable any ports connected to this transcoder */ | |
1600 | static void intel_disable_pch_ports(struct drm_i915_private *dev_priv, | |
1601 | enum pipe pipe) | |
1602 | { | |
1603 | u32 reg, val; | |
1604 | ||
1605 | val = I915_READ(PCH_PP_CONTROL); | |
1606 | I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS); | |
1607 | ||
f0575e92 KP |
1608 | disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1609 | disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1610 | disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
47a05eca JB |
1611 | |
1612 | reg = PCH_ADPA; | |
1613 | val = I915_READ(reg); | |
1519b995 | 1614 | if (adpa_pipe_enabled(dev_priv, val, pipe)) |
47a05eca JB |
1615 | I915_WRITE(reg, val & ~ADPA_DAC_ENABLE); |
1616 | ||
1617 | reg = PCH_LVDS; | |
1618 | val = I915_READ(reg); | |
1519b995 KP |
1619 | if (lvds_pipe_enabled(dev_priv, val, pipe)) { |
1620 | DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val); | |
47a05eca JB |
1621 | I915_WRITE(reg, val & ~LVDS_PORT_EN); |
1622 | POSTING_READ(reg); | |
1623 | udelay(100); | |
1624 | } | |
1625 | ||
1626 | disable_pch_hdmi(dev_priv, pipe, HDMIB); | |
1627 | disable_pch_hdmi(dev_priv, pipe, HDMIC); | |
1628 | disable_pch_hdmi(dev_priv, pipe, HDMID); | |
1629 | } | |
1630 | ||
43a9539f CW |
1631 | static void i8xx_disable_fbc(struct drm_device *dev) |
1632 | { | |
1633 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1634 | u32 fbc_ctl; | |
1635 | ||
1636 | /* Disable compression */ | |
1637 | fbc_ctl = I915_READ(FBC_CONTROL); | |
1638 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
1639 | return; | |
1640 | ||
1641 | fbc_ctl &= ~FBC_CTL_EN; | |
1642 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
1643 | ||
1644 | /* Wait for compressing bit to clear */ | |
1645 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
1646 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
1647 | return; | |
1648 | } | |
1649 | ||
1650 | DRM_DEBUG_KMS("disabled FBC\n"); | |
1651 | } | |
1652 | ||
80824003 JB |
1653 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1654 | { | |
1655 | struct drm_device *dev = crtc->dev; | |
1656 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1657 | struct drm_framebuffer *fb = crtc->fb; | |
1658 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1659 | struct drm_i915_gem_object *obj = intel_fb->obj; |
80824003 | 1660 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
016b9b61 | 1661 | int cfb_pitch; |
80824003 JB |
1662 | int plane, i; |
1663 | u32 fbc_ctl, fbc_ctl2; | |
1664 | ||
016b9b61 | 1665 | cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
01f2c773 VS |
1666 | if (fb->pitches[0] < cfb_pitch) |
1667 | cfb_pitch = fb->pitches[0]; | |
80824003 JB |
1668 | |
1669 | /* FBC_CTL wants 64B units */ | |
016b9b61 CW |
1670 | cfb_pitch = (cfb_pitch / 64) - 1; |
1671 | plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; | |
80824003 JB |
1672 | |
1673 | /* Clear old tags */ | |
1674 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
1675 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
1676 | ||
1677 | /* Set it up... */ | |
de568510 CW |
1678 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; |
1679 | fbc_ctl2 |= plane; | |
80824003 JB |
1680 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
1681 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
1682 | ||
1683 | /* enable it... */ | |
1684 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; | |
ee25df2b | 1685 | if (IS_I945GM(dev)) |
49677901 | 1686 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
016b9b61 | 1687 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
80824003 | 1688 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; |
016b9b61 | 1689 | fbc_ctl |= obj->fence_reg; |
80824003 JB |
1690 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
1691 | ||
016b9b61 CW |
1692 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ", |
1693 | cfb_pitch, crtc->y, intel_crtc->plane); | |
80824003 JB |
1694 | } |
1695 | ||
ee5382ae | 1696 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
80824003 | 1697 | { |
80824003 JB |
1698 | struct drm_i915_private *dev_priv = dev->dev_private; |
1699 | ||
1700 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
1701 | } | |
1702 | ||
74dff282 JB |
1703 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1704 | { | |
1705 | struct drm_device *dev = crtc->dev; | |
1706 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1707 | struct drm_framebuffer *fb = crtc->fb; | |
1708 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1709 | struct drm_i915_gem_object *obj = intel_fb->obj; |
74dff282 | 1710 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1711 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
74dff282 JB |
1712 | unsigned long stall_watermark = 200; |
1713 | u32 dpfc_ctl; | |
1714 | ||
74dff282 | 1715 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; |
016b9b61 | 1716 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
de568510 | 1717 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); |
74dff282 | 1718 | |
74dff282 JB |
1719 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1720 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1721 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1722 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); | |
1723 | ||
1724 | /* enable it... */ | |
1725 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); | |
1726 | ||
28c97730 | 1727 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
74dff282 JB |
1728 | } |
1729 | ||
43a9539f | 1730 | static void g4x_disable_fbc(struct drm_device *dev) |
74dff282 JB |
1731 | { |
1732 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1733 | u32 dpfc_ctl; | |
1734 | ||
1735 | /* Disable compression */ | |
1736 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
bed4a673 CW |
1737 | if (dpfc_ctl & DPFC_CTL_EN) { |
1738 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1739 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
74dff282 | 1740 | |
bed4a673 CW |
1741 | DRM_DEBUG_KMS("disabled FBC\n"); |
1742 | } | |
74dff282 JB |
1743 | } |
1744 | ||
ee5382ae | 1745 | static bool g4x_fbc_enabled(struct drm_device *dev) |
74dff282 | 1746 | { |
74dff282 JB |
1747 | struct drm_i915_private *dev_priv = dev->dev_private; |
1748 | ||
1749 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
1750 | } | |
1751 | ||
4efe0708 JB |
1752 | static void sandybridge_blit_fbc_update(struct drm_device *dev) |
1753 | { | |
1754 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1755 | u32 blt_ecoskpd; | |
1756 | ||
1757 | /* Make sure blitter notifies FBC of writes */ | |
fcca7926 | 1758 | gen6_gt_force_wake_get(dev_priv); |
4efe0708 JB |
1759 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
1760 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << | |
1761 | GEN6_BLITTER_LOCK_SHIFT; | |
1762 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1763 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; | |
1764 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1765 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << | |
1766 | GEN6_BLITTER_LOCK_SHIFT); | |
1767 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1768 | POSTING_READ(GEN6_BLITTER_ECOSKPD); | |
fcca7926 | 1769 | gen6_gt_force_wake_put(dev_priv); |
4efe0708 JB |
1770 | } |
1771 | ||
b52eb4dc ZY |
1772 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1773 | { | |
1774 | struct drm_device *dev = crtc->dev; | |
1775 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1776 | struct drm_framebuffer *fb = crtc->fb; | |
1777 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1778 | struct drm_i915_gem_object *obj = intel_fb->obj; |
b52eb4dc | 1779 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1780 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
b52eb4dc ZY |
1781 | unsigned long stall_watermark = 200; |
1782 | u32 dpfc_ctl; | |
1783 | ||
bed4a673 | 1784 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
b52eb4dc ZY |
1785 | dpfc_ctl &= DPFC_RESERVED; |
1786 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); | |
9ce9d069 CW |
1787 | /* Set persistent mode for front-buffer rendering, ala X. */ |
1788 | dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; | |
016b9b61 | 1789 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); |
de568510 | 1790 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); |
b52eb4dc | 1791 | |
b52eb4dc ZY |
1792 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1793 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1794 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1795 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); | |
05394f39 | 1796 | I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); |
b52eb4dc | 1797 | /* enable it... */ |
bed4a673 | 1798 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
b52eb4dc | 1799 | |
9c04f015 YL |
1800 | if (IS_GEN6(dev)) { |
1801 | I915_WRITE(SNB_DPFC_CTL_SA, | |
016b9b61 | 1802 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
9c04f015 | 1803 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
4efe0708 | 1804 | sandybridge_blit_fbc_update(dev); |
9c04f015 YL |
1805 | } |
1806 | ||
b52eb4dc ZY |
1807 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
1808 | } | |
1809 | ||
43a9539f | 1810 | static void ironlake_disable_fbc(struct drm_device *dev) |
b52eb4dc ZY |
1811 | { |
1812 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1813 | u32 dpfc_ctl; | |
1814 | ||
1815 | /* Disable compression */ | |
1816 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
bed4a673 CW |
1817 | if (dpfc_ctl & DPFC_CTL_EN) { |
1818 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1819 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
b52eb4dc | 1820 | |
bed4a673 CW |
1821 | DRM_DEBUG_KMS("disabled FBC\n"); |
1822 | } | |
b52eb4dc ZY |
1823 | } |
1824 | ||
1825 | static bool ironlake_fbc_enabled(struct drm_device *dev) | |
1826 | { | |
1827 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1828 | ||
1829 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
1830 | } | |
1831 | ||
ee5382ae AJ |
1832 | bool intel_fbc_enabled(struct drm_device *dev) |
1833 | { | |
1834 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1835 | ||
1836 | if (!dev_priv->display.fbc_enabled) | |
1837 | return false; | |
1838 | ||
1839 | return dev_priv->display.fbc_enabled(dev); | |
1840 | } | |
1841 | ||
1630fe75 CW |
1842 | static void intel_fbc_work_fn(struct work_struct *__work) |
1843 | { | |
1844 | struct intel_fbc_work *work = | |
1845 | container_of(to_delayed_work(__work), | |
1846 | struct intel_fbc_work, work); | |
1847 | struct drm_device *dev = work->crtc->dev; | |
1848 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1849 | ||
1850 | mutex_lock(&dev->struct_mutex); | |
1851 | if (work == dev_priv->fbc_work) { | |
1852 | /* Double check that we haven't switched fb without cancelling | |
1853 | * the prior work. | |
1854 | */ | |
016b9b61 | 1855 | if (work->crtc->fb == work->fb) { |
1630fe75 CW |
1856 | dev_priv->display.enable_fbc(work->crtc, |
1857 | work->interval); | |
1858 | ||
016b9b61 CW |
1859 | dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane; |
1860 | dev_priv->cfb_fb = work->crtc->fb->base.id; | |
1861 | dev_priv->cfb_y = work->crtc->y; | |
1862 | } | |
1863 | ||
1630fe75 CW |
1864 | dev_priv->fbc_work = NULL; |
1865 | } | |
1866 | mutex_unlock(&dev->struct_mutex); | |
1867 | ||
1868 | kfree(work); | |
1869 | } | |
1870 | ||
1871 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) | |
1872 | { | |
1873 | if (dev_priv->fbc_work == NULL) | |
1874 | return; | |
1875 | ||
1876 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); | |
1877 | ||
1878 | /* Synchronisation is provided by struct_mutex and checking of | |
1879 | * dev_priv->fbc_work, so we can perform the cancellation | |
1880 | * entirely asynchronously. | |
1881 | */ | |
1882 | if (cancel_delayed_work(&dev_priv->fbc_work->work)) | |
1883 | /* tasklet was killed before being run, clean up */ | |
1884 | kfree(dev_priv->fbc_work); | |
1885 | ||
1886 | /* Mark the work as no longer wanted so that if it does | |
1887 | * wake-up (because the work was already running and waiting | |
1888 | * for our mutex), it will discover that is no longer | |
1889 | * necessary to run. | |
1890 | */ | |
1891 | dev_priv->fbc_work = NULL; | |
1892 | } | |
1893 | ||
43a9539f | 1894 | static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
ee5382ae | 1895 | { |
1630fe75 CW |
1896 | struct intel_fbc_work *work; |
1897 | struct drm_device *dev = crtc->dev; | |
1898 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee5382ae AJ |
1899 | |
1900 | if (!dev_priv->display.enable_fbc) | |
1901 | return; | |
1902 | ||
1630fe75 CW |
1903 | intel_cancel_fbc_work(dev_priv); |
1904 | ||
1905 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
1906 | if (work == NULL) { | |
1907 | dev_priv->display.enable_fbc(crtc, interval); | |
1908 | return; | |
1909 | } | |
1910 | ||
1911 | work->crtc = crtc; | |
1912 | work->fb = crtc->fb; | |
1913 | work->interval = interval; | |
1914 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); | |
1915 | ||
1916 | dev_priv->fbc_work = work; | |
1917 | ||
1918 | DRM_DEBUG_KMS("scheduling delayed FBC enable\n"); | |
1919 | ||
1920 | /* Delay the actual enabling to let pageflipping cease and the | |
016b9b61 CW |
1921 | * display to settle before starting the compression. Note that |
1922 | * this delay also serves a second purpose: it allows for a | |
1923 | * vblank to pass after disabling the FBC before we attempt | |
1924 | * to modify the control registers. | |
1630fe75 CW |
1925 | * |
1926 | * A more complicated solution would involve tracking vblanks | |
1927 | * following the termination of the page-flipping sequence | |
1928 | * and indeed performing the enable as a co-routine and not | |
1929 | * waiting synchronously upon the vblank. | |
1930 | */ | |
1931 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
ee5382ae AJ |
1932 | } |
1933 | ||
1934 | void intel_disable_fbc(struct drm_device *dev) | |
1935 | { | |
1936 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1937 | ||
1630fe75 CW |
1938 | intel_cancel_fbc_work(dev_priv); |
1939 | ||
ee5382ae AJ |
1940 | if (!dev_priv->display.disable_fbc) |
1941 | return; | |
1942 | ||
1943 | dev_priv->display.disable_fbc(dev); | |
016b9b61 | 1944 | dev_priv->cfb_plane = -1; |
ee5382ae AJ |
1945 | } |
1946 | ||
80824003 JB |
1947 | /** |
1948 | * intel_update_fbc - enable/disable FBC as needed | |
bed4a673 | 1949 | * @dev: the drm_device |
80824003 JB |
1950 | * |
1951 | * Set up the framebuffer compression hardware at mode set time. We | |
1952 | * enable it if possible: | |
1953 | * - plane A only (on pre-965) | |
1954 | * - no pixel mulitply/line duplication | |
1955 | * - no alpha buffer discard | |
1956 | * - no dual wide | |
1957 | * - framebuffer <= 2048 in width, 1536 in height | |
1958 | * | |
1959 | * We can't assume that any compression will take place (worst case), | |
1960 | * so the compressed buffer has to be the same size as the uncompressed | |
1961 | * one. It also must reside (along with the line length buffer) in | |
1962 | * stolen memory. | |
1963 | * | |
1964 | * We need to enable/disable FBC on a global basis. | |
1965 | */ | |
bed4a673 | 1966 | static void intel_update_fbc(struct drm_device *dev) |
80824003 | 1967 | { |
80824003 | 1968 | struct drm_i915_private *dev_priv = dev->dev_private; |
bed4a673 CW |
1969 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
1970 | struct intel_crtc *intel_crtc; | |
1971 | struct drm_framebuffer *fb; | |
80824003 | 1972 | struct intel_framebuffer *intel_fb; |
05394f39 | 1973 | struct drm_i915_gem_object *obj; |
cd0de039 | 1974 | int enable_fbc; |
9c928d16 JB |
1975 | |
1976 | DRM_DEBUG_KMS("\n"); | |
80824003 JB |
1977 | |
1978 | if (!i915_powersave) | |
1979 | return; | |
1980 | ||
ee5382ae | 1981 | if (!I915_HAS_FBC(dev)) |
e70236a8 JB |
1982 | return; |
1983 | ||
80824003 JB |
1984 | /* |
1985 | * If FBC is already on, we just have to verify that we can | |
1986 | * keep it that way... | |
1987 | * Need to disable if: | |
9c928d16 | 1988 | * - more than one pipe is active |
80824003 JB |
1989 | * - changing FBC params (stride, fence, mode) |
1990 | * - new fb is too large to fit in compressed buffer | |
1991 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
1992 | */ | |
9c928d16 | 1993 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
d210246a | 1994 | if (tmp_crtc->enabled && tmp_crtc->fb) { |
bed4a673 CW |
1995 | if (crtc) { |
1996 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
1997 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; | |
1998 | goto out_disable; | |
1999 | } | |
2000 | crtc = tmp_crtc; | |
2001 | } | |
9c928d16 | 2002 | } |
bed4a673 CW |
2003 | |
2004 | if (!crtc || crtc->fb == NULL) { | |
2005 | DRM_DEBUG_KMS("no output, disabling\n"); | |
2006 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; | |
9c928d16 JB |
2007 | goto out_disable; |
2008 | } | |
bed4a673 CW |
2009 | |
2010 | intel_crtc = to_intel_crtc(crtc); | |
2011 | fb = crtc->fb; | |
2012 | intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 2013 | obj = intel_fb->obj; |
bed4a673 | 2014 | |
cd0de039 KP |
2015 | enable_fbc = i915_enable_fbc; |
2016 | if (enable_fbc < 0) { | |
2017 | DRM_DEBUG_KMS("fbc set to per-chip default\n"); | |
2018 | enable_fbc = 1; | |
d56d8b28 | 2019 | if (INTEL_INFO(dev)->gen <= 6) |
cd0de039 KP |
2020 | enable_fbc = 0; |
2021 | } | |
2022 | if (!enable_fbc) { | |
2023 | DRM_DEBUG_KMS("fbc disabled per module param\n"); | |
c1a9f047 JB |
2024 | dev_priv->no_fbc_reason = FBC_MODULE_PARAM; |
2025 | goto out_disable; | |
2026 | } | |
05394f39 | 2027 | if (intel_fb->obj->base.size > dev_priv->cfb_size) { |
28c97730 | 2028 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
5eddb70b | 2029 | "compression\n"); |
b5e50c3f | 2030 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
80824003 JB |
2031 | goto out_disable; |
2032 | } | |
bed4a673 CW |
2033 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
2034 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { | |
28c97730 | 2035 | DRM_DEBUG_KMS("mode incompatible with compression, " |
5eddb70b | 2036 | "disabling\n"); |
b5e50c3f | 2037 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
80824003 JB |
2038 | goto out_disable; |
2039 | } | |
bed4a673 CW |
2040 | if ((crtc->mode.hdisplay > 2048) || |
2041 | (crtc->mode.vdisplay > 1536)) { | |
28c97730 | 2042 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
b5e50c3f | 2043 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
80824003 JB |
2044 | goto out_disable; |
2045 | } | |
bed4a673 | 2046 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { |
28c97730 | 2047 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
b5e50c3f | 2048 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
80824003 JB |
2049 | goto out_disable; |
2050 | } | |
de568510 CW |
2051 | |
2052 | /* The use of a CPU fence is mandatory in order to detect writes | |
2053 | * by the CPU to the scanout and trigger updates to the FBC. | |
2054 | */ | |
2055 | if (obj->tiling_mode != I915_TILING_X || | |
2056 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
2057 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); | |
b5e50c3f | 2058 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
80824003 JB |
2059 | goto out_disable; |
2060 | } | |
2061 | ||
c924b934 JW |
2062 | /* If the kernel debugger is active, always disable compression */ |
2063 | if (in_dbg_master()) | |
2064 | goto out_disable; | |
2065 | ||
016b9b61 CW |
2066 | /* If the scanout has not changed, don't modify the FBC settings. |
2067 | * Note that we make the fundamental assumption that the fb->obj | |
2068 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
2069 | * without first being decoupled from the scanout and FBC disabled. | |
2070 | */ | |
2071 | if (dev_priv->cfb_plane == intel_crtc->plane && | |
2072 | dev_priv->cfb_fb == fb->base.id && | |
2073 | dev_priv->cfb_y == crtc->y) | |
2074 | return; | |
2075 | ||
2076 | if (intel_fbc_enabled(dev)) { | |
2077 | /* We update FBC along two paths, after changing fb/crtc | |
2078 | * configuration (modeswitching) and after page-flipping | |
2079 | * finishes. For the latter, we know that not only did | |
2080 | * we disable the FBC at the start of the page-flip | |
2081 | * sequence, but also more than one vblank has passed. | |
2082 | * | |
2083 | * For the former case of modeswitching, it is possible | |
2084 | * to switch between two FBC valid configurations | |
2085 | * instantaneously so we do need to disable the FBC | |
2086 | * before we can modify its control registers. We also | |
2087 | * have to wait for the next vblank for that to take | |
2088 | * effect. However, since we delay enabling FBC we can | |
2089 | * assume that a vblank has passed since disabling and | |
2090 | * that we can safely alter the registers in the deferred | |
2091 | * callback. | |
2092 | * | |
2093 | * In the scenario that we go from a valid to invalid | |
2094 | * and then back to valid FBC configuration we have | |
2095 | * no strict enforcement that a vblank occurred since | |
2096 | * disabling the FBC. However, along all current pipe | |
2097 | * disabling paths we do need to wait for a vblank at | |
2098 | * some point. And we wait before enabling FBC anyway. | |
2099 | */ | |
2100 | DRM_DEBUG_KMS("disabling active FBC for update\n"); | |
2101 | intel_disable_fbc(dev); | |
2102 | } | |
2103 | ||
bed4a673 | 2104 | intel_enable_fbc(crtc, 500); |
80824003 JB |
2105 | return; |
2106 | ||
2107 | out_disable: | |
80824003 | 2108 | /* Multiple disables should be harmless */ |
a939406f CW |
2109 | if (intel_fbc_enabled(dev)) { |
2110 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
ee5382ae | 2111 | intel_disable_fbc(dev); |
a939406f | 2112 | } |
80824003 JB |
2113 | } |
2114 | ||
127bd2ac | 2115 | int |
48b956c5 | 2116 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 2117 | struct drm_i915_gem_object *obj, |
919926ae | 2118 | struct intel_ring_buffer *pipelined) |
6b95a207 | 2119 | { |
ce453d81 | 2120 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
2121 | u32 alignment; |
2122 | int ret; | |
2123 | ||
05394f39 | 2124 | switch (obj->tiling_mode) { |
6b95a207 | 2125 | case I915_TILING_NONE: |
534843da CW |
2126 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
2127 | alignment = 128 * 1024; | |
a6c45cf0 | 2128 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2129 | alignment = 4 * 1024; |
2130 | else | |
2131 | alignment = 64 * 1024; | |
6b95a207 KH |
2132 | break; |
2133 | case I915_TILING_X: | |
2134 | /* pin() will align the object as required by fence */ | |
2135 | alignment = 0; | |
2136 | break; | |
2137 | case I915_TILING_Y: | |
2138 | /* FIXME: Is this true? */ | |
2139 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
2140 | return -EINVAL; | |
2141 | default: | |
2142 | BUG(); | |
2143 | } | |
2144 | ||
ce453d81 | 2145 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 2146 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 2147 | if (ret) |
ce453d81 | 2148 | goto err_interruptible; |
6b95a207 KH |
2149 | |
2150 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2151 | * fence, whereas 965+ only requires a fence if using | |
2152 | * framebuffer compression. For simplicity, we always install | |
2153 | * a fence as the cost is not that onerous. | |
2154 | */ | |
05394f39 | 2155 | if (obj->tiling_mode != I915_TILING_NONE) { |
ce453d81 | 2156 | ret = i915_gem_object_get_fence(obj, pipelined); |
48b956c5 CW |
2157 | if (ret) |
2158 | goto err_unpin; | |
1690e1eb CW |
2159 | |
2160 | i915_gem_object_pin_fence(obj); | |
6b95a207 KH |
2161 | } |
2162 | ||
ce453d81 | 2163 | dev_priv->mm.interruptible = true; |
6b95a207 | 2164 | return 0; |
48b956c5 CW |
2165 | |
2166 | err_unpin: | |
2167 | i915_gem_object_unpin(obj); | |
ce453d81 CW |
2168 | err_interruptible: |
2169 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2170 | return ret; |
6b95a207 KH |
2171 | } |
2172 | ||
1690e1eb CW |
2173 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2174 | { | |
2175 | i915_gem_object_unpin_fence(obj); | |
2176 | i915_gem_object_unpin(obj); | |
2177 | } | |
2178 | ||
17638cd6 JB |
2179 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2180 | int x, int y) | |
81255565 JB |
2181 | { |
2182 | struct drm_device *dev = crtc->dev; | |
2183 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2184 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2185 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2186 | struct drm_i915_gem_object *obj; |
81255565 JB |
2187 | int plane = intel_crtc->plane; |
2188 | unsigned long Start, Offset; | |
81255565 | 2189 | u32 dspcntr; |
5eddb70b | 2190 | u32 reg; |
81255565 JB |
2191 | |
2192 | switch (plane) { | |
2193 | case 0: | |
2194 | case 1: | |
2195 | break; | |
2196 | default: | |
2197 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2198 | return -EINVAL; | |
2199 | } | |
2200 | ||
2201 | intel_fb = to_intel_framebuffer(fb); | |
2202 | obj = intel_fb->obj; | |
81255565 | 2203 | |
5eddb70b CW |
2204 | reg = DSPCNTR(plane); |
2205 | dspcntr = I915_READ(reg); | |
81255565 JB |
2206 | /* Mask out pixel format bits in case we change it */ |
2207 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
2208 | switch (fb->bits_per_pixel) { | |
2209 | case 8: | |
2210 | dspcntr |= DISPPLANE_8BPP; | |
2211 | break; | |
2212 | case 16: | |
2213 | if (fb->depth == 15) | |
2214 | dspcntr |= DISPPLANE_15_16BPP; | |
2215 | else | |
2216 | dspcntr |= DISPPLANE_16BPP; | |
2217 | break; | |
2218 | case 24: | |
2219 | case 32: | |
2220 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
2221 | break; | |
2222 | default: | |
17638cd6 | 2223 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); |
81255565 JB |
2224 | return -EINVAL; |
2225 | } | |
a6c45cf0 | 2226 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2227 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2228 | dspcntr |= DISPPLANE_TILED; |
2229 | else | |
2230 | dspcntr &= ~DISPPLANE_TILED; | |
2231 | } | |
2232 | ||
5eddb70b | 2233 | I915_WRITE(reg, dspcntr); |
81255565 | 2234 | |
05394f39 | 2235 | Start = obj->gtt_offset; |
01f2c773 | 2236 | Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2237 | |
4e6cfefc | 2238 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
01f2c773 VS |
2239 | Start, Offset, x, y, fb->pitches[0]); |
2240 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); | |
a6c45cf0 | 2241 | if (INTEL_INFO(dev)->gen >= 4) { |
5eddb70b CW |
2242 | I915_WRITE(DSPSURF(plane), Start); |
2243 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2244 | I915_WRITE(DSPADDR(plane), Offset); | |
2245 | } else | |
2246 | I915_WRITE(DSPADDR(plane), Start + Offset); | |
2247 | POSTING_READ(reg); | |
81255565 | 2248 | |
17638cd6 JB |
2249 | return 0; |
2250 | } | |
2251 | ||
2252 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2253 | struct drm_framebuffer *fb, int x, int y) | |
2254 | { | |
2255 | struct drm_device *dev = crtc->dev; | |
2256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2257 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2258 | struct intel_framebuffer *intel_fb; | |
2259 | struct drm_i915_gem_object *obj; | |
2260 | int plane = intel_crtc->plane; | |
2261 | unsigned long Start, Offset; | |
2262 | u32 dspcntr; | |
2263 | u32 reg; | |
2264 | ||
2265 | switch (plane) { | |
2266 | case 0: | |
2267 | case 1: | |
27f8227b | 2268 | case 2: |
17638cd6 JB |
2269 | break; |
2270 | default: | |
2271 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2272 | return -EINVAL; | |
2273 | } | |
2274 | ||
2275 | intel_fb = to_intel_framebuffer(fb); | |
2276 | obj = intel_fb->obj; | |
2277 | ||
2278 | reg = DSPCNTR(plane); | |
2279 | dspcntr = I915_READ(reg); | |
2280 | /* Mask out pixel format bits in case we change it */ | |
2281 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
2282 | switch (fb->bits_per_pixel) { | |
2283 | case 8: | |
2284 | dspcntr |= DISPPLANE_8BPP; | |
2285 | break; | |
2286 | case 16: | |
2287 | if (fb->depth != 16) | |
2288 | return -EINVAL; | |
2289 | ||
2290 | dspcntr |= DISPPLANE_16BPP; | |
2291 | break; | |
2292 | case 24: | |
2293 | case 32: | |
2294 | if (fb->depth == 24) | |
2295 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
2296 | else if (fb->depth == 30) | |
2297 | dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA; | |
2298 | else | |
2299 | return -EINVAL; | |
2300 | break; | |
2301 | default: | |
2302 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); | |
2303 | return -EINVAL; | |
2304 | } | |
2305 | ||
2306 | if (obj->tiling_mode != I915_TILING_NONE) | |
2307 | dspcntr |= DISPPLANE_TILED; | |
2308 | else | |
2309 | dspcntr &= ~DISPPLANE_TILED; | |
2310 | ||
2311 | /* must disable */ | |
2312 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2313 | ||
2314 | I915_WRITE(reg, dspcntr); | |
2315 | ||
2316 | Start = obj->gtt_offset; | |
01f2c773 | 2317 | Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
17638cd6 JB |
2318 | |
2319 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", | |
01f2c773 VS |
2320 | Start, Offset, x, y, fb->pitches[0]); |
2321 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); | |
17638cd6 JB |
2322 | I915_WRITE(DSPSURF(plane), Start); |
2323 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2324 | I915_WRITE(DSPADDR(plane), Offset); | |
2325 | POSTING_READ(reg); | |
2326 | ||
2327 | return 0; | |
2328 | } | |
2329 | ||
2330 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2331 | static int | |
2332 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2333 | int x, int y, enum mode_set_atomic state) | |
2334 | { | |
2335 | struct drm_device *dev = crtc->dev; | |
2336 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2337 | int ret; | |
2338 | ||
2339 | ret = dev_priv->display.update_plane(crtc, fb, x, y); | |
2340 | if (ret) | |
2341 | return ret; | |
2342 | ||
bed4a673 | 2343 | intel_update_fbc(dev); |
3dec0095 | 2344 | intel_increase_pllclock(crtc); |
81255565 JB |
2345 | |
2346 | return 0; | |
2347 | } | |
2348 | ||
5c3b82e2 | 2349 | static int |
3c4fdcfb KH |
2350 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
2351 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
2352 | { |
2353 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
2354 | struct drm_i915_master_private *master_priv; |
2355 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5c3b82e2 | 2356 | int ret; |
79e53945 JB |
2357 | |
2358 | /* no fb bound */ | |
2359 | if (!crtc->fb) { | |
a5071c2f | 2360 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2361 | return 0; |
2362 | } | |
2363 | ||
265db958 | 2364 | switch (intel_crtc->plane) { |
5c3b82e2 CW |
2365 | case 0: |
2366 | case 1: | |
2367 | break; | |
27f8227b JB |
2368 | case 2: |
2369 | if (IS_IVYBRIDGE(dev)) | |
2370 | break; | |
2371 | /* fall through otherwise */ | |
5c3b82e2 | 2372 | default: |
a5071c2f | 2373 | DRM_ERROR("no plane for crtc\n"); |
5c3b82e2 | 2374 | return -EINVAL; |
79e53945 JB |
2375 | } |
2376 | ||
5c3b82e2 | 2377 | mutex_lock(&dev->struct_mutex); |
265db958 CW |
2378 | ret = intel_pin_and_fence_fb_obj(dev, |
2379 | to_intel_framebuffer(crtc->fb)->obj, | |
919926ae | 2380 | NULL); |
5c3b82e2 CW |
2381 | if (ret != 0) { |
2382 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2383 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2384 | return ret; |
2385 | } | |
79e53945 | 2386 | |
265db958 | 2387 | if (old_fb) { |
e6c3a2a6 | 2388 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 2389 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
265db958 | 2390 | |
e6c3a2a6 | 2391 | wait_event(dev_priv->pending_flip_queue, |
01eec727 | 2392 | atomic_read(&dev_priv->mm.wedged) || |
05394f39 | 2393 | atomic_read(&obj->pending_flip) == 0); |
85345517 CW |
2394 | |
2395 | /* Big Hammer, we also need to ensure that any pending | |
2396 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2397 | * current scanout is retired before unpinning the old | |
2398 | * framebuffer. | |
01eec727 CW |
2399 | * |
2400 | * This should only fail upon a hung GPU, in which case we | |
2401 | * can safely continue. | |
85345517 | 2402 | */ |
a8198eea | 2403 | ret = i915_gem_object_finish_gpu(obj); |
01eec727 | 2404 | (void) ret; |
265db958 CW |
2405 | } |
2406 | ||
21c74a8e JW |
2407 | ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y, |
2408 | LEAVE_ATOMIC_MODE_SET); | |
4e6cfefc | 2409 | if (ret) { |
1690e1eb | 2410 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
5c3b82e2 | 2411 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2412 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2413 | return ret; |
79e53945 | 2414 | } |
3c4fdcfb | 2415 | |
b7f1de28 CW |
2416 | if (old_fb) { |
2417 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2418 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2419 | } |
652c393a | 2420 | |
5c3b82e2 | 2421 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
2422 | |
2423 | if (!dev->primary->master) | |
5c3b82e2 | 2424 | return 0; |
79e53945 JB |
2425 | |
2426 | master_priv = dev->primary->master->driver_priv; | |
2427 | if (!master_priv->sarea_priv) | |
5c3b82e2 | 2428 | return 0; |
79e53945 | 2429 | |
265db958 | 2430 | if (intel_crtc->pipe) { |
79e53945 JB |
2431 | master_priv->sarea_priv->pipeB_x = x; |
2432 | master_priv->sarea_priv->pipeB_y = y; | |
5c3b82e2 CW |
2433 | } else { |
2434 | master_priv->sarea_priv->pipeA_x = x; | |
2435 | master_priv->sarea_priv->pipeA_y = y; | |
79e53945 | 2436 | } |
5c3b82e2 CW |
2437 | |
2438 | return 0; | |
79e53945 JB |
2439 | } |
2440 | ||
5eddb70b | 2441 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
32f9d658 ZW |
2442 | { |
2443 | struct drm_device *dev = crtc->dev; | |
2444 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2445 | u32 dpa_ctl; | |
2446 | ||
28c97730 | 2447 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
32f9d658 ZW |
2448 | dpa_ctl = I915_READ(DP_A); |
2449 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
2450 | ||
2451 | if (clock < 200000) { | |
2452 | u32 temp; | |
2453 | dpa_ctl |= DP_PLL_FREQ_160MHZ; | |
2454 | /* workaround for 160Mhz: | |
2455 | 1) program 0x4600c bits 15:0 = 0x8124 | |
2456 | 2) program 0x46010 bit 0 = 1 | |
2457 | 3) program 0x46034 bit 24 = 1 | |
2458 | 4) program 0x64000 bit 14 = 1 | |
2459 | */ | |
2460 | temp = I915_READ(0x4600c); | |
2461 | temp &= 0xffff0000; | |
2462 | I915_WRITE(0x4600c, temp | 0x8124); | |
2463 | ||
2464 | temp = I915_READ(0x46010); | |
2465 | I915_WRITE(0x46010, temp | 1); | |
2466 | ||
2467 | temp = I915_READ(0x46034); | |
2468 | I915_WRITE(0x46034, temp | (1 << 24)); | |
2469 | } else { | |
2470 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
2471 | } | |
2472 | I915_WRITE(DP_A, dpa_ctl); | |
2473 | ||
5eddb70b | 2474 | POSTING_READ(DP_A); |
32f9d658 ZW |
2475 | udelay(500); |
2476 | } | |
2477 | ||
5e84e1a4 ZW |
2478 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2479 | { | |
2480 | struct drm_device *dev = crtc->dev; | |
2481 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2482 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2483 | int pipe = intel_crtc->pipe; | |
2484 | u32 reg, temp; | |
2485 | ||
2486 | /* enable normal train */ | |
2487 | reg = FDI_TX_CTL(pipe); | |
2488 | temp = I915_READ(reg); | |
61e499bf | 2489 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2490 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2491 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2492 | } else { |
2493 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2494 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2495 | } |
5e84e1a4 ZW |
2496 | I915_WRITE(reg, temp); |
2497 | ||
2498 | reg = FDI_RX_CTL(pipe); | |
2499 | temp = I915_READ(reg); | |
2500 | if (HAS_PCH_CPT(dev)) { | |
2501 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2502 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2503 | } else { | |
2504 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2505 | temp |= FDI_LINK_TRAIN_NONE; | |
2506 | } | |
2507 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2508 | ||
2509 | /* wait one idle pattern time */ | |
2510 | POSTING_READ(reg); | |
2511 | udelay(1000); | |
357555c0 JB |
2512 | |
2513 | /* IVB wants error correction enabled */ | |
2514 | if (IS_IVYBRIDGE(dev)) | |
2515 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2516 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2517 | } |
2518 | ||
291427f5 JB |
2519 | static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe) |
2520 | { | |
2521 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2522 | u32 flags = I915_READ(SOUTH_CHICKEN1); | |
2523 | ||
2524 | flags |= FDI_PHASE_SYNC_OVR(pipe); | |
2525 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ | |
2526 | flags |= FDI_PHASE_SYNC_EN(pipe); | |
2527 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ | |
2528 | POSTING_READ(SOUTH_CHICKEN1); | |
2529 | } | |
2530 | ||
8db9d77b ZW |
2531 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2532 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2533 | { | |
2534 | struct drm_device *dev = crtc->dev; | |
2535 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2536 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2537 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2538 | int plane = intel_crtc->plane; |
5eddb70b | 2539 | u32 reg, temp, tries; |
8db9d77b | 2540 | |
0fc932b8 JB |
2541 | /* FDI needs bits from pipe & plane first */ |
2542 | assert_pipe_enabled(dev_priv, pipe); | |
2543 | assert_plane_enabled(dev_priv, plane); | |
2544 | ||
e1a44743 AJ |
2545 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2546 | for train result */ | |
5eddb70b CW |
2547 | reg = FDI_RX_IMR(pipe); |
2548 | temp = I915_READ(reg); | |
e1a44743 AJ |
2549 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2550 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2551 | I915_WRITE(reg, temp); |
2552 | I915_READ(reg); | |
e1a44743 AJ |
2553 | udelay(150); |
2554 | ||
8db9d77b | 2555 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2556 | reg = FDI_TX_CTL(pipe); |
2557 | temp = I915_READ(reg); | |
77ffb597 AJ |
2558 | temp &= ~(7 << 19); |
2559 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2560 | temp &= ~FDI_LINK_TRAIN_NONE; |
2561 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2562 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2563 | |
5eddb70b CW |
2564 | reg = FDI_RX_CTL(pipe); |
2565 | temp = I915_READ(reg); | |
8db9d77b ZW |
2566 | temp &= ~FDI_LINK_TRAIN_NONE; |
2567 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2568 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2569 | ||
2570 | POSTING_READ(reg); | |
8db9d77b ZW |
2571 | udelay(150); |
2572 | ||
5b2adf89 | 2573 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
6f06ce18 JB |
2574 | if (HAS_PCH_IBX(dev)) { |
2575 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
2576 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2577 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
2578 | } | |
5b2adf89 | 2579 | |
5eddb70b | 2580 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2581 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2582 | temp = I915_READ(reg); |
8db9d77b ZW |
2583 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2584 | ||
2585 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2586 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2587 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2588 | break; |
2589 | } | |
8db9d77b | 2590 | } |
e1a44743 | 2591 | if (tries == 5) |
5eddb70b | 2592 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2593 | |
2594 | /* Train 2 */ | |
5eddb70b CW |
2595 | reg = FDI_TX_CTL(pipe); |
2596 | temp = I915_READ(reg); | |
8db9d77b ZW |
2597 | temp &= ~FDI_LINK_TRAIN_NONE; |
2598 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2599 | I915_WRITE(reg, temp); |
8db9d77b | 2600 | |
5eddb70b CW |
2601 | reg = FDI_RX_CTL(pipe); |
2602 | temp = I915_READ(reg); | |
8db9d77b ZW |
2603 | temp &= ~FDI_LINK_TRAIN_NONE; |
2604 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2605 | I915_WRITE(reg, temp); |
8db9d77b | 2606 | |
5eddb70b CW |
2607 | POSTING_READ(reg); |
2608 | udelay(150); | |
8db9d77b | 2609 | |
5eddb70b | 2610 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2611 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2612 | temp = I915_READ(reg); |
8db9d77b ZW |
2613 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2614 | ||
2615 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2616 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2617 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2618 | break; | |
2619 | } | |
8db9d77b | 2620 | } |
e1a44743 | 2621 | if (tries == 5) |
5eddb70b | 2622 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2623 | |
2624 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2625 | |
8db9d77b ZW |
2626 | } |
2627 | ||
0206e353 | 2628 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2629 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2630 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2631 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2632 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2633 | }; | |
2634 | ||
2635 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2636 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2637 | { | |
2638 | struct drm_device *dev = crtc->dev; | |
2639 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2640 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2641 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2642 | u32 reg, temp, i, retry; |
8db9d77b | 2643 | |
e1a44743 AJ |
2644 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2645 | for train result */ | |
5eddb70b CW |
2646 | reg = FDI_RX_IMR(pipe); |
2647 | temp = I915_READ(reg); | |
e1a44743 AJ |
2648 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2649 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2650 | I915_WRITE(reg, temp); |
2651 | ||
2652 | POSTING_READ(reg); | |
e1a44743 AJ |
2653 | udelay(150); |
2654 | ||
8db9d77b | 2655 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2656 | reg = FDI_TX_CTL(pipe); |
2657 | temp = I915_READ(reg); | |
77ffb597 AJ |
2658 | temp &= ~(7 << 19); |
2659 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2660 | temp &= ~FDI_LINK_TRAIN_NONE; |
2661 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2662 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2663 | /* SNB-B */ | |
2664 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2665 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2666 | |
5eddb70b CW |
2667 | reg = FDI_RX_CTL(pipe); |
2668 | temp = I915_READ(reg); | |
8db9d77b ZW |
2669 | if (HAS_PCH_CPT(dev)) { |
2670 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2671 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2672 | } else { | |
2673 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2674 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2675 | } | |
5eddb70b CW |
2676 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2677 | ||
2678 | POSTING_READ(reg); | |
8db9d77b ZW |
2679 | udelay(150); |
2680 | ||
291427f5 JB |
2681 | if (HAS_PCH_CPT(dev)) |
2682 | cpt_phase_pointer_enable(dev, pipe); | |
2683 | ||
0206e353 | 2684 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2685 | reg = FDI_TX_CTL(pipe); |
2686 | temp = I915_READ(reg); | |
8db9d77b ZW |
2687 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2688 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2689 | I915_WRITE(reg, temp); |
2690 | ||
2691 | POSTING_READ(reg); | |
8db9d77b ZW |
2692 | udelay(500); |
2693 | ||
fa37d39e SP |
2694 | for (retry = 0; retry < 5; retry++) { |
2695 | reg = FDI_RX_IIR(pipe); | |
2696 | temp = I915_READ(reg); | |
2697 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2698 | if (temp & FDI_RX_BIT_LOCK) { | |
2699 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2700 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2701 | break; | |
2702 | } | |
2703 | udelay(50); | |
8db9d77b | 2704 | } |
fa37d39e SP |
2705 | if (retry < 5) |
2706 | break; | |
8db9d77b ZW |
2707 | } |
2708 | if (i == 4) | |
5eddb70b | 2709 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2710 | |
2711 | /* Train 2 */ | |
5eddb70b CW |
2712 | reg = FDI_TX_CTL(pipe); |
2713 | temp = I915_READ(reg); | |
8db9d77b ZW |
2714 | temp &= ~FDI_LINK_TRAIN_NONE; |
2715 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2716 | if (IS_GEN6(dev)) { | |
2717 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2718 | /* SNB-B */ | |
2719 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2720 | } | |
5eddb70b | 2721 | I915_WRITE(reg, temp); |
8db9d77b | 2722 | |
5eddb70b CW |
2723 | reg = FDI_RX_CTL(pipe); |
2724 | temp = I915_READ(reg); | |
8db9d77b ZW |
2725 | if (HAS_PCH_CPT(dev)) { |
2726 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2727 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2728 | } else { | |
2729 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2730 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2731 | } | |
5eddb70b CW |
2732 | I915_WRITE(reg, temp); |
2733 | ||
2734 | POSTING_READ(reg); | |
8db9d77b ZW |
2735 | udelay(150); |
2736 | ||
0206e353 | 2737 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2738 | reg = FDI_TX_CTL(pipe); |
2739 | temp = I915_READ(reg); | |
8db9d77b ZW |
2740 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2741 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2742 | I915_WRITE(reg, temp); |
2743 | ||
2744 | POSTING_READ(reg); | |
8db9d77b ZW |
2745 | udelay(500); |
2746 | ||
fa37d39e SP |
2747 | for (retry = 0; retry < 5; retry++) { |
2748 | reg = FDI_RX_IIR(pipe); | |
2749 | temp = I915_READ(reg); | |
2750 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2751 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2752 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2753 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2754 | break; | |
2755 | } | |
2756 | udelay(50); | |
8db9d77b | 2757 | } |
fa37d39e SP |
2758 | if (retry < 5) |
2759 | break; | |
8db9d77b ZW |
2760 | } |
2761 | if (i == 4) | |
5eddb70b | 2762 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2763 | |
2764 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2765 | } | |
2766 | ||
357555c0 JB |
2767 | /* Manual link training for Ivy Bridge A0 parts */ |
2768 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2769 | { | |
2770 | struct drm_device *dev = crtc->dev; | |
2771 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2772 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2773 | int pipe = intel_crtc->pipe; | |
2774 | u32 reg, temp, i; | |
2775 | ||
2776 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2777 | for train result */ | |
2778 | reg = FDI_RX_IMR(pipe); | |
2779 | temp = I915_READ(reg); | |
2780 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2781 | temp &= ~FDI_RX_BIT_LOCK; | |
2782 | I915_WRITE(reg, temp); | |
2783 | ||
2784 | POSTING_READ(reg); | |
2785 | udelay(150); | |
2786 | ||
2787 | /* enable CPU FDI TX and PCH FDI RX */ | |
2788 | reg = FDI_TX_CTL(pipe); | |
2789 | temp = I915_READ(reg); | |
2790 | temp &= ~(7 << 19); | |
2791 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
2792 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2793 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
2794 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2795 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
c4f9c4c2 | 2796 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2797 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2798 | ||
2799 | reg = FDI_RX_CTL(pipe); | |
2800 | temp = I915_READ(reg); | |
2801 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2802 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2803 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
c4f9c4c2 | 2804 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2805 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2806 | ||
2807 | POSTING_READ(reg); | |
2808 | udelay(150); | |
2809 | ||
291427f5 JB |
2810 | if (HAS_PCH_CPT(dev)) |
2811 | cpt_phase_pointer_enable(dev, pipe); | |
2812 | ||
0206e353 | 2813 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2814 | reg = FDI_TX_CTL(pipe); |
2815 | temp = I915_READ(reg); | |
2816 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2817 | temp |= snb_b_fdi_train_param[i]; | |
2818 | I915_WRITE(reg, temp); | |
2819 | ||
2820 | POSTING_READ(reg); | |
2821 | udelay(500); | |
2822 | ||
2823 | reg = FDI_RX_IIR(pipe); | |
2824 | temp = I915_READ(reg); | |
2825 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2826 | ||
2827 | if (temp & FDI_RX_BIT_LOCK || | |
2828 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2829 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2830 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2831 | break; | |
2832 | } | |
2833 | } | |
2834 | if (i == 4) | |
2835 | DRM_ERROR("FDI train 1 fail!\n"); | |
2836 | ||
2837 | /* Train 2 */ | |
2838 | reg = FDI_TX_CTL(pipe); | |
2839 | temp = I915_READ(reg); | |
2840 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; | |
2841 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2842 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2843 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2844 | I915_WRITE(reg, temp); | |
2845 | ||
2846 | reg = FDI_RX_CTL(pipe); | |
2847 | temp = I915_READ(reg); | |
2848 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2849 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2850 | I915_WRITE(reg, temp); | |
2851 | ||
2852 | POSTING_READ(reg); | |
2853 | udelay(150); | |
2854 | ||
0206e353 | 2855 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2856 | reg = FDI_TX_CTL(pipe); |
2857 | temp = I915_READ(reg); | |
2858 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2859 | temp |= snb_b_fdi_train_param[i]; | |
2860 | I915_WRITE(reg, temp); | |
2861 | ||
2862 | POSTING_READ(reg); | |
2863 | udelay(500); | |
2864 | ||
2865 | reg = FDI_RX_IIR(pipe); | |
2866 | temp = I915_READ(reg); | |
2867 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2868 | ||
2869 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2870 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2871 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2872 | break; | |
2873 | } | |
2874 | } | |
2875 | if (i == 4) | |
2876 | DRM_ERROR("FDI train 2 fail!\n"); | |
2877 | ||
2878 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2879 | } | |
2880 | ||
2881 | static void ironlake_fdi_pll_enable(struct drm_crtc *crtc) | |
2c07245f ZW |
2882 | { |
2883 | struct drm_device *dev = crtc->dev; | |
2884 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2885 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2886 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2887 | u32 reg, temp; |
79e53945 | 2888 | |
c64e311e | 2889 | /* Write the TU size bits so error detection works */ |
5eddb70b CW |
2890 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
2891 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
c64e311e | 2892 | |
c98e9dcf | 2893 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2894 | reg = FDI_RX_CTL(pipe); |
2895 | temp = I915_READ(reg); | |
2896 | temp &= ~((0x7 << 19) | (0x7 << 16)); | |
c98e9dcf | 2897 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
5eddb70b CW |
2898 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
2899 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); | |
2900 | ||
2901 | POSTING_READ(reg); | |
c98e9dcf JB |
2902 | udelay(200); |
2903 | ||
2904 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2905 | temp = I915_READ(reg); |
2906 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2907 | ||
2908 | POSTING_READ(reg); | |
c98e9dcf JB |
2909 | udelay(200); |
2910 | ||
2911 | /* Enable CPU FDI TX PLL, always on for Ironlake */ | |
5eddb70b CW |
2912 | reg = FDI_TX_CTL(pipe); |
2913 | temp = I915_READ(reg); | |
c98e9dcf | 2914 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
5eddb70b CW |
2915 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
2916 | ||
2917 | POSTING_READ(reg); | |
c98e9dcf | 2918 | udelay(100); |
6be4a607 | 2919 | } |
0e23b99d JB |
2920 | } |
2921 | ||
291427f5 JB |
2922 | static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe) |
2923 | { | |
2924 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2925 | u32 flags = I915_READ(SOUTH_CHICKEN1); | |
2926 | ||
2927 | flags &= ~(FDI_PHASE_SYNC_EN(pipe)); | |
2928 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */ | |
2929 | flags &= ~(FDI_PHASE_SYNC_OVR(pipe)); | |
2930 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */ | |
2931 | POSTING_READ(SOUTH_CHICKEN1); | |
2932 | } | |
0fc932b8 JB |
2933 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2934 | { | |
2935 | struct drm_device *dev = crtc->dev; | |
2936 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2937 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2938 | int pipe = intel_crtc->pipe; | |
2939 | u32 reg, temp; | |
2940 | ||
2941 | /* disable CPU FDI tx and PCH FDI rx */ | |
2942 | reg = FDI_TX_CTL(pipe); | |
2943 | temp = I915_READ(reg); | |
2944 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2945 | POSTING_READ(reg); | |
2946 | ||
2947 | reg = FDI_RX_CTL(pipe); | |
2948 | temp = I915_READ(reg); | |
2949 | temp &= ~(0x7 << 16); | |
2950 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2951 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); | |
2952 | ||
2953 | POSTING_READ(reg); | |
2954 | udelay(100); | |
2955 | ||
2956 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2957 | if (HAS_PCH_IBX(dev)) { |
2958 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
0fc932b8 JB |
2959 | I915_WRITE(FDI_RX_CHICKEN(pipe), |
2960 | I915_READ(FDI_RX_CHICKEN(pipe) & | |
6f06ce18 | 2961 | ~FDI_RX_PHASE_SYNC_POINTER_EN)); |
291427f5 JB |
2962 | } else if (HAS_PCH_CPT(dev)) { |
2963 | cpt_phase_pointer_disable(dev, pipe); | |
6f06ce18 | 2964 | } |
0fc932b8 JB |
2965 | |
2966 | /* still set train pattern 1 */ | |
2967 | reg = FDI_TX_CTL(pipe); | |
2968 | temp = I915_READ(reg); | |
2969 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2970 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2971 | I915_WRITE(reg, temp); | |
2972 | ||
2973 | reg = FDI_RX_CTL(pipe); | |
2974 | temp = I915_READ(reg); | |
2975 | if (HAS_PCH_CPT(dev)) { | |
2976 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2977 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2978 | } else { | |
2979 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2980 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2981 | } | |
2982 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2983 | temp &= ~(0x07 << 16); | |
2984 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2985 | I915_WRITE(reg, temp); | |
2986 | ||
2987 | POSTING_READ(reg); | |
2988 | udelay(100); | |
2989 | } | |
2990 | ||
6b383a7f CW |
2991 | /* |
2992 | * When we disable a pipe, we need to clear any pending scanline wait events | |
2993 | * to avoid hanging the ring, which we assume we are waiting on. | |
2994 | */ | |
2995 | static void intel_clear_scanline_wait(struct drm_device *dev) | |
2996 | { | |
2997 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8168bd48 | 2998 | struct intel_ring_buffer *ring; |
6b383a7f CW |
2999 | u32 tmp; |
3000 | ||
3001 | if (IS_GEN2(dev)) | |
3002 | /* Can't break the hang on i8xx */ | |
3003 | return; | |
3004 | ||
1ec14ad3 | 3005 | ring = LP_RING(dev_priv); |
8168bd48 CW |
3006 | tmp = I915_READ_CTL(ring); |
3007 | if (tmp & RING_WAIT) | |
3008 | I915_WRITE_CTL(ring, tmp); | |
6b383a7f CW |
3009 | } |
3010 | ||
e6c3a2a6 CW |
3011 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
3012 | { | |
05394f39 | 3013 | struct drm_i915_gem_object *obj; |
e6c3a2a6 CW |
3014 | struct drm_i915_private *dev_priv; |
3015 | ||
3016 | if (crtc->fb == NULL) | |
3017 | return; | |
3018 | ||
05394f39 | 3019 | obj = to_intel_framebuffer(crtc->fb)->obj; |
e6c3a2a6 CW |
3020 | dev_priv = crtc->dev->dev_private; |
3021 | wait_event(dev_priv->pending_flip_queue, | |
05394f39 | 3022 | atomic_read(&obj->pending_flip) == 0); |
e6c3a2a6 CW |
3023 | } |
3024 | ||
040484af JB |
3025 | static bool intel_crtc_driving_pch(struct drm_crtc *crtc) |
3026 | { | |
3027 | struct drm_device *dev = crtc->dev; | |
3028 | struct drm_mode_config *mode_config = &dev->mode_config; | |
3029 | struct intel_encoder *encoder; | |
3030 | ||
3031 | /* | |
3032 | * If there's a non-PCH eDP on this crtc, it must be DP_A, and that | |
3033 | * must be driven by its own crtc; no sharing is possible. | |
3034 | */ | |
3035 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
3036 | if (encoder->base.crtc != crtc) | |
3037 | continue; | |
3038 | ||
3039 | switch (encoder->type) { | |
3040 | case INTEL_OUTPUT_EDP: | |
3041 | if (!intel_encoder_is_pch_edp(&encoder->base)) | |
3042 | return false; | |
3043 | continue; | |
3044 | } | |
3045 | } | |
3046 | ||
3047 | return true; | |
3048 | } | |
3049 | ||
f67a559d JB |
3050 | /* |
3051 | * Enable PCH resources required for PCH ports: | |
3052 | * - PCH PLLs | |
3053 | * - FDI training & RX/TX | |
3054 | * - update transcoder timings | |
3055 | * - DP transcoding bits | |
3056 | * - transcoder | |
3057 | */ | |
3058 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3059 | { |
3060 | struct drm_device *dev = crtc->dev; | |
3061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3062 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3063 | int pipe = intel_crtc->pipe; | |
4b645f14 | 3064 | u32 reg, temp, transc_sel; |
2c07245f | 3065 | |
c98e9dcf | 3066 | /* For PCH output, training FDI link */ |
674cf967 | 3067 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3068 | |
92f2584a | 3069 | intel_enable_pch_pll(dev_priv, pipe); |
8db9d77b | 3070 | |
c98e9dcf | 3071 | if (HAS_PCH_CPT(dev)) { |
4b645f14 JB |
3072 | transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL : |
3073 | TRANSC_DPLLB_SEL; | |
3074 | ||
c98e9dcf JB |
3075 | /* Be sure PCH DPLL SEL is set */ |
3076 | temp = I915_READ(PCH_DPLL_SEL); | |
d64311ab JB |
3077 | if (pipe == 0) { |
3078 | temp &= ~(TRANSA_DPLLB_SEL); | |
c98e9dcf | 3079 | temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); |
d64311ab JB |
3080 | } else if (pipe == 1) { |
3081 | temp &= ~(TRANSB_DPLLB_SEL); | |
c98e9dcf | 3082 | temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
d64311ab JB |
3083 | } else if (pipe == 2) { |
3084 | temp &= ~(TRANSC_DPLLB_SEL); | |
4b645f14 | 3085 | temp |= (TRANSC_DPLL_ENABLE | transc_sel); |
d64311ab | 3086 | } |
c98e9dcf | 3087 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3088 | } |
5eddb70b | 3089 | |
d9b6cb56 JB |
3090 | /* set transcoder timing, panel must allow it */ |
3091 | assert_panel_unlocked(dev_priv, pipe); | |
5eddb70b CW |
3092 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
3093 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); | |
3094 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); | |
8db9d77b | 3095 | |
5eddb70b CW |
3096 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
3097 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); | |
3098 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); | |
0529a0d9 | 3099 | I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); |
8db9d77b | 3100 | |
5e84e1a4 ZW |
3101 | intel_fdi_normal_train(crtc); |
3102 | ||
c98e9dcf JB |
3103 | /* For PCH DP, enable TRANS_DP_CTL */ |
3104 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3105 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3106 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
9325c9f0 | 3107 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; |
5eddb70b CW |
3108 | reg = TRANS_DP_CTL(pipe); |
3109 | temp = I915_READ(reg); | |
3110 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3111 | TRANS_DP_SYNC_MASK | |
3112 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3113 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3114 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3115 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3116 | |
3117 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3118 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3119 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3120 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3121 | |
3122 | switch (intel_trans_dp_port_sel(crtc)) { | |
3123 | case PCH_DP_B: | |
5eddb70b | 3124 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3125 | break; |
3126 | case PCH_DP_C: | |
5eddb70b | 3127 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3128 | break; |
3129 | case PCH_DP_D: | |
5eddb70b | 3130 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3131 | break; |
3132 | default: | |
3133 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); | |
5eddb70b | 3134 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 3135 | break; |
32f9d658 | 3136 | } |
2c07245f | 3137 | |
5eddb70b | 3138 | I915_WRITE(reg, temp); |
6be4a607 | 3139 | } |
b52eb4dc | 3140 | |
040484af | 3141 | intel_enable_transcoder(dev_priv, pipe); |
f67a559d JB |
3142 | } |
3143 | ||
d4270e57 JB |
3144 | void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) |
3145 | { | |
3146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3147 | int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe); | |
3148 | u32 temp; | |
3149 | ||
3150 | temp = I915_READ(dslreg); | |
3151 | udelay(500); | |
3152 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
3153 | /* Without this, mode sets may fail silently on FDI */ | |
3154 | I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS); | |
3155 | udelay(250); | |
3156 | I915_WRITE(tc2reg, 0); | |
3157 | if (wait_for(I915_READ(dslreg) != temp, 5)) | |
3158 | DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); | |
3159 | } | |
3160 | } | |
3161 | ||
f67a559d JB |
3162 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3163 | { | |
3164 | struct drm_device *dev = crtc->dev; | |
3165 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3166 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3167 | int pipe = intel_crtc->pipe; | |
3168 | int plane = intel_crtc->plane; | |
3169 | u32 temp; | |
3170 | bool is_pch_port; | |
3171 | ||
3172 | if (intel_crtc->active) | |
3173 | return; | |
3174 | ||
3175 | intel_crtc->active = true; | |
3176 | intel_update_watermarks(dev); | |
3177 | ||
3178 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
3179 | temp = I915_READ(PCH_LVDS); | |
3180 | if ((temp & LVDS_PORT_EN) == 0) | |
3181 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); | |
3182 | } | |
3183 | ||
3184 | is_pch_port = intel_crtc_driving_pch(crtc); | |
3185 | ||
3186 | if (is_pch_port) | |
357555c0 | 3187 | ironlake_fdi_pll_enable(crtc); |
f67a559d JB |
3188 | else |
3189 | ironlake_fdi_disable(crtc); | |
3190 | ||
3191 | /* Enable panel fitting for LVDS */ | |
3192 | if (dev_priv->pch_pf_size && | |
3193 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { | |
3194 | /* Force use of hard-coded filter coefficients | |
3195 | * as some pre-programmed values are broken, | |
3196 | * e.g. x201. | |
3197 | */ | |
9db4a9c7 JB |
3198 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
3199 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); | |
3200 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); | |
f67a559d JB |
3201 | } |
3202 | ||
9c54c0dd JB |
3203 | /* |
3204 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3205 | * clocks enabled | |
3206 | */ | |
3207 | intel_crtc_load_lut(crtc); | |
3208 | ||
f67a559d JB |
3209 | intel_enable_pipe(dev_priv, pipe, is_pch_port); |
3210 | intel_enable_plane(dev_priv, plane, pipe); | |
3211 | ||
3212 | if (is_pch_port) | |
3213 | ironlake_pch_enable(crtc); | |
c98e9dcf | 3214 | |
d1ebd816 | 3215 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3216 | intel_update_fbc(dev); |
d1ebd816 BW |
3217 | mutex_unlock(&dev->struct_mutex); |
3218 | ||
6b383a7f | 3219 | intel_crtc_update_cursor(crtc, true); |
6be4a607 JB |
3220 | } |
3221 | ||
3222 | static void ironlake_crtc_disable(struct drm_crtc *crtc) | |
3223 | { | |
3224 | struct drm_device *dev = crtc->dev; | |
3225 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3226 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3227 | int pipe = intel_crtc->pipe; | |
3228 | int plane = intel_crtc->plane; | |
5eddb70b | 3229 | u32 reg, temp; |
b52eb4dc | 3230 | |
f7abfe8b CW |
3231 | if (!intel_crtc->active) |
3232 | return; | |
3233 | ||
e6c3a2a6 | 3234 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3235 | drm_vblank_off(dev, pipe); |
6b383a7f | 3236 | intel_crtc_update_cursor(crtc, false); |
5eddb70b | 3237 | |
b24e7179 | 3238 | intel_disable_plane(dev_priv, plane, pipe); |
913d8d11 | 3239 | |
973d04f9 CW |
3240 | if (dev_priv->cfb_plane == plane) |
3241 | intel_disable_fbc(dev); | |
2c07245f | 3242 | |
b24e7179 | 3243 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3244 | |
6be4a607 | 3245 | /* Disable PF */ |
9db4a9c7 JB |
3246 | I915_WRITE(PF_CTL(pipe), 0); |
3247 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
2c07245f | 3248 | |
0fc932b8 | 3249 | ironlake_fdi_disable(crtc); |
2c07245f | 3250 | |
47a05eca JB |
3251 | /* This is a horrible layering violation; we should be doing this in |
3252 | * the connector/encoder ->prepare instead, but we don't always have | |
3253 | * enough information there about the config to know whether it will | |
3254 | * actually be necessary or just cause undesired flicker. | |
3255 | */ | |
3256 | intel_disable_pch_ports(dev_priv, pipe); | |
249c0e64 | 3257 | |
040484af | 3258 | intel_disable_transcoder(dev_priv, pipe); |
913d8d11 | 3259 | |
6be4a607 JB |
3260 | if (HAS_PCH_CPT(dev)) { |
3261 | /* disable TRANS_DP_CTL */ | |
5eddb70b CW |
3262 | reg = TRANS_DP_CTL(pipe); |
3263 | temp = I915_READ(reg); | |
3264 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
cb3543c6 | 3265 | temp |= TRANS_DP_PORT_SEL_NONE; |
5eddb70b | 3266 | I915_WRITE(reg, temp); |
6be4a607 JB |
3267 | |
3268 | /* disable DPLL_SEL */ | |
3269 | temp = I915_READ(PCH_DPLL_SEL); | |
9db4a9c7 JB |
3270 | switch (pipe) { |
3271 | case 0: | |
d64311ab | 3272 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
9db4a9c7 JB |
3273 | break; |
3274 | case 1: | |
6be4a607 | 3275 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
9db4a9c7 JB |
3276 | break; |
3277 | case 2: | |
4b645f14 | 3278 | /* C shares PLL A or B */ |
d64311ab | 3279 | temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); |
9db4a9c7 JB |
3280 | break; |
3281 | default: | |
3282 | BUG(); /* wtf */ | |
3283 | } | |
6be4a607 | 3284 | I915_WRITE(PCH_DPLL_SEL, temp); |
6be4a607 | 3285 | } |
e3421a18 | 3286 | |
6be4a607 | 3287 | /* disable PCH DPLL */ |
4b645f14 JB |
3288 | if (!intel_crtc->no_pll) |
3289 | intel_disable_pch_pll(dev_priv, pipe); | |
8db9d77b | 3290 | |
6be4a607 | 3291 | /* Switch from PCDclk to Rawclk */ |
5eddb70b CW |
3292 | reg = FDI_RX_CTL(pipe); |
3293 | temp = I915_READ(reg); | |
3294 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
8db9d77b | 3295 | |
6be4a607 | 3296 | /* Disable CPU FDI TX PLL */ |
5eddb70b CW |
3297 | reg = FDI_TX_CTL(pipe); |
3298 | temp = I915_READ(reg); | |
3299 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3300 | ||
3301 | POSTING_READ(reg); | |
6be4a607 | 3302 | udelay(100); |
8db9d77b | 3303 | |
5eddb70b CW |
3304 | reg = FDI_RX_CTL(pipe); |
3305 | temp = I915_READ(reg); | |
3306 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2c07245f | 3307 | |
6be4a607 | 3308 | /* Wait for the clocks to turn off. */ |
5eddb70b | 3309 | POSTING_READ(reg); |
6be4a607 | 3310 | udelay(100); |
6b383a7f | 3311 | |
f7abfe8b | 3312 | intel_crtc->active = false; |
6b383a7f | 3313 | intel_update_watermarks(dev); |
d1ebd816 BW |
3314 | |
3315 | mutex_lock(&dev->struct_mutex); | |
6b383a7f CW |
3316 | intel_update_fbc(dev); |
3317 | intel_clear_scanline_wait(dev); | |
d1ebd816 | 3318 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3319 | } |
1b3c7a47 | 3320 | |
6be4a607 JB |
3321 | static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) |
3322 | { | |
3323 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3324 | int pipe = intel_crtc->pipe; | |
3325 | int plane = intel_crtc->plane; | |
8db9d77b | 3326 | |
6be4a607 JB |
3327 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
3328 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
3329 | */ | |
3330 | switch (mode) { | |
3331 | case DRM_MODE_DPMS_ON: | |
3332 | case DRM_MODE_DPMS_STANDBY: | |
3333 | case DRM_MODE_DPMS_SUSPEND: | |
3334 | DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); | |
3335 | ironlake_crtc_enable(crtc); | |
3336 | break; | |
1b3c7a47 | 3337 | |
6be4a607 JB |
3338 | case DRM_MODE_DPMS_OFF: |
3339 | DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); | |
3340 | ironlake_crtc_disable(crtc); | |
2c07245f ZW |
3341 | break; |
3342 | } | |
3343 | } | |
3344 | ||
02e792fb DV |
3345 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3346 | { | |
02e792fb | 3347 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3348 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3349 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3350 | |
23f09ce3 | 3351 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3352 | dev_priv->mm.interruptible = false; |
3353 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3354 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3355 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3356 | } |
02e792fb | 3357 | |
5dcdbcb0 CW |
3358 | /* Let userspace switch the overlay on again. In most cases userspace |
3359 | * has to recompute where to put it anyway. | |
3360 | */ | |
02e792fb DV |
3361 | } |
3362 | ||
0b8765c6 | 3363 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
3364 | { |
3365 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
3366 | struct drm_i915_private *dev_priv = dev->dev_private; |
3367 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3368 | int pipe = intel_crtc->pipe; | |
80824003 | 3369 | int plane = intel_crtc->plane; |
79e53945 | 3370 | |
f7abfe8b CW |
3371 | if (intel_crtc->active) |
3372 | return; | |
3373 | ||
3374 | intel_crtc->active = true; | |
6b383a7f CW |
3375 | intel_update_watermarks(dev); |
3376 | ||
63d7bbe9 | 3377 | intel_enable_pll(dev_priv, pipe); |
040484af | 3378 | intel_enable_pipe(dev_priv, pipe, false); |
b24e7179 | 3379 | intel_enable_plane(dev_priv, plane, pipe); |
79e53945 | 3380 | |
0b8765c6 | 3381 | intel_crtc_load_lut(crtc); |
bed4a673 | 3382 | intel_update_fbc(dev); |
79e53945 | 3383 | |
0b8765c6 JB |
3384 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3385 | intel_crtc_dpms_overlay(intel_crtc, true); | |
6b383a7f | 3386 | intel_crtc_update_cursor(crtc, true); |
0b8765c6 | 3387 | } |
79e53945 | 3388 | |
0b8765c6 JB |
3389 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3390 | { | |
3391 | struct drm_device *dev = crtc->dev; | |
3392 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3393 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3394 | int pipe = intel_crtc->pipe; | |
3395 | int plane = intel_crtc->plane; | |
b690e96c | 3396 | |
f7abfe8b CW |
3397 | if (!intel_crtc->active) |
3398 | return; | |
3399 | ||
0b8765c6 | 3400 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
3401 | intel_crtc_wait_for_pending_flips(crtc); |
3402 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 3403 | intel_crtc_dpms_overlay(intel_crtc, false); |
6b383a7f | 3404 | intel_crtc_update_cursor(crtc, false); |
0b8765c6 | 3405 | |
973d04f9 CW |
3406 | if (dev_priv->cfb_plane == plane) |
3407 | intel_disable_fbc(dev); | |
79e53945 | 3408 | |
b24e7179 | 3409 | intel_disable_plane(dev_priv, plane, pipe); |
b24e7179 | 3410 | intel_disable_pipe(dev_priv, pipe); |
63d7bbe9 | 3411 | intel_disable_pll(dev_priv, pipe); |
0b8765c6 | 3412 | |
f7abfe8b | 3413 | intel_crtc->active = false; |
6b383a7f CW |
3414 | intel_update_fbc(dev); |
3415 | intel_update_watermarks(dev); | |
3416 | intel_clear_scanline_wait(dev); | |
0b8765c6 JB |
3417 | } |
3418 | ||
3419 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) | |
3420 | { | |
3421 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
3422 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
3423 | */ | |
3424 | switch (mode) { | |
3425 | case DRM_MODE_DPMS_ON: | |
3426 | case DRM_MODE_DPMS_STANDBY: | |
3427 | case DRM_MODE_DPMS_SUSPEND: | |
3428 | i9xx_crtc_enable(crtc); | |
3429 | break; | |
3430 | case DRM_MODE_DPMS_OFF: | |
3431 | i9xx_crtc_disable(crtc); | |
79e53945 JB |
3432 | break; |
3433 | } | |
2c07245f ZW |
3434 | } |
3435 | ||
3436 | /** | |
3437 | * Sets the power management mode of the pipe and plane. | |
2c07245f ZW |
3438 | */ |
3439 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
3440 | { | |
3441 | struct drm_device *dev = crtc->dev; | |
e70236a8 | 3442 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f ZW |
3443 | struct drm_i915_master_private *master_priv; |
3444 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3445 | int pipe = intel_crtc->pipe; | |
3446 | bool enabled; | |
3447 | ||
032d2a0d CW |
3448 | if (intel_crtc->dpms_mode == mode) |
3449 | return; | |
3450 | ||
65655d4a | 3451 | intel_crtc->dpms_mode = mode; |
debcaddc | 3452 | |
e70236a8 | 3453 | dev_priv->display.dpms(crtc, mode); |
79e53945 JB |
3454 | |
3455 | if (!dev->primary->master) | |
3456 | return; | |
3457 | ||
3458 | master_priv = dev->primary->master->driver_priv; | |
3459 | if (!master_priv->sarea_priv) | |
3460 | return; | |
3461 | ||
3462 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; | |
3463 | ||
3464 | switch (pipe) { | |
3465 | case 0: | |
3466 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
3467 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
3468 | break; | |
3469 | case 1: | |
3470 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
3471 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
3472 | break; | |
3473 | default: | |
9db4a9c7 | 3474 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
3475 | break; |
3476 | } | |
79e53945 JB |
3477 | } |
3478 | ||
cdd59983 CW |
3479 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3480 | { | |
3481 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
3482 | struct drm_device *dev = crtc->dev; | |
3483 | ||
3484 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
931872fc CW |
3485 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
3486 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); | |
cdd59983 CW |
3487 | |
3488 | if (crtc->fb) { | |
3489 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 3490 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 CW |
3491 | mutex_unlock(&dev->struct_mutex); |
3492 | } | |
3493 | } | |
3494 | ||
7e7d76c3 JB |
3495 | /* Prepare for a mode set. |
3496 | * | |
3497 | * Note we could be a lot smarter here. We need to figure out which outputs | |
3498 | * will be enabled, which disabled (in short, how the config will changes) | |
3499 | * and perform the minimum necessary steps to accomplish that, e.g. updating | |
3500 | * watermarks, FBC configuration, making sure PLLs are programmed correctly, | |
3501 | * panel fitting is in the proper state, etc. | |
3502 | */ | |
3503 | static void i9xx_crtc_prepare(struct drm_crtc *crtc) | |
79e53945 | 3504 | { |
7e7d76c3 | 3505 | i9xx_crtc_disable(crtc); |
79e53945 JB |
3506 | } |
3507 | ||
7e7d76c3 | 3508 | static void i9xx_crtc_commit(struct drm_crtc *crtc) |
79e53945 | 3509 | { |
7e7d76c3 | 3510 | i9xx_crtc_enable(crtc); |
7e7d76c3 JB |
3511 | } |
3512 | ||
3513 | static void ironlake_crtc_prepare(struct drm_crtc *crtc) | |
3514 | { | |
7e7d76c3 | 3515 | ironlake_crtc_disable(crtc); |
7e7d76c3 JB |
3516 | } |
3517 | ||
3518 | static void ironlake_crtc_commit(struct drm_crtc *crtc) | |
3519 | { | |
7e7d76c3 | 3520 | ironlake_crtc_enable(crtc); |
79e53945 JB |
3521 | } |
3522 | ||
0206e353 | 3523 | void intel_encoder_prepare(struct drm_encoder *encoder) |
79e53945 JB |
3524 | { |
3525 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
3526 | /* lvds has its own version of prepare see intel_lvds_prepare */ | |
3527 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | |
3528 | } | |
3529 | ||
0206e353 | 3530 | void intel_encoder_commit(struct drm_encoder *encoder) |
79e53945 JB |
3531 | { |
3532 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
d4270e57 JB |
3533 | struct drm_device *dev = encoder->dev; |
3534 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
3535 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
3536 | ||
79e53945 JB |
3537 | /* lvds has its own version of commit see intel_lvds_commit */ |
3538 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
d4270e57 JB |
3539 | |
3540 | if (HAS_PCH_CPT(dev)) | |
3541 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); | |
79e53945 JB |
3542 | } |
3543 | ||
ea5b213a CW |
3544 | void intel_encoder_destroy(struct drm_encoder *encoder) |
3545 | { | |
4ef69c7a | 3546 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 3547 | |
ea5b213a CW |
3548 | drm_encoder_cleanup(encoder); |
3549 | kfree(intel_encoder); | |
3550 | } | |
3551 | ||
79e53945 JB |
3552 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
3553 | struct drm_display_mode *mode, | |
3554 | struct drm_display_mode *adjusted_mode) | |
3555 | { | |
2c07245f | 3556 | struct drm_device *dev = crtc->dev; |
89749350 | 3557 | |
bad720ff | 3558 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 3559 | /* FDI link clock is fixed at 2.7G */ |
2377b741 JB |
3560 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
3561 | return false; | |
2c07245f | 3562 | } |
89749350 | 3563 | |
ca9bfa7e DV |
3564 | /* All interlaced capable intel hw wants timings in frames. */ |
3565 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
89749350 | 3566 | |
79e53945 JB |
3567 | return true; |
3568 | } | |
3569 | ||
25eb05fc JB |
3570 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
3571 | { | |
3572 | return 400000; /* FIXME */ | |
3573 | } | |
3574 | ||
e70236a8 JB |
3575 | static int i945_get_display_clock_speed(struct drm_device *dev) |
3576 | { | |
3577 | return 400000; | |
3578 | } | |
79e53945 | 3579 | |
e70236a8 | 3580 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 3581 | { |
e70236a8 JB |
3582 | return 333000; |
3583 | } | |
79e53945 | 3584 | |
e70236a8 JB |
3585 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
3586 | { | |
3587 | return 200000; | |
3588 | } | |
79e53945 | 3589 | |
e70236a8 JB |
3590 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
3591 | { | |
3592 | u16 gcfgc = 0; | |
79e53945 | 3593 | |
e70236a8 JB |
3594 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
3595 | ||
3596 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
3597 | return 133000; | |
3598 | else { | |
3599 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
3600 | case GC_DISPLAY_CLOCK_333_MHZ: | |
3601 | return 333000; | |
3602 | default: | |
3603 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
3604 | return 190000; | |
79e53945 | 3605 | } |
e70236a8 JB |
3606 | } |
3607 | } | |
3608 | ||
3609 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
3610 | { | |
3611 | return 266000; | |
3612 | } | |
3613 | ||
3614 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
3615 | { | |
3616 | u16 hpllcc = 0; | |
3617 | /* Assume that the hardware is in the high speed state. This | |
3618 | * should be the default. | |
3619 | */ | |
3620 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
3621 | case GC_CLOCK_133_200: | |
3622 | case GC_CLOCK_100_200: | |
3623 | return 200000; | |
3624 | case GC_CLOCK_166_250: | |
3625 | return 250000; | |
3626 | case GC_CLOCK_100_133: | |
79e53945 | 3627 | return 133000; |
e70236a8 | 3628 | } |
79e53945 | 3629 | |
e70236a8 JB |
3630 | /* Shouldn't happen */ |
3631 | return 0; | |
3632 | } | |
79e53945 | 3633 | |
e70236a8 JB |
3634 | static int i830_get_display_clock_speed(struct drm_device *dev) |
3635 | { | |
3636 | return 133000; | |
79e53945 JB |
3637 | } |
3638 | ||
2c07245f ZW |
3639 | struct fdi_m_n { |
3640 | u32 tu; | |
3641 | u32 gmch_m; | |
3642 | u32 gmch_n; | |
3643 | u32 link_m; | |
3644 | u32 link_n; | |
3645 | }; | |
3646 | ||
3647 | static void | |
3648 | fdi_reduce_ratio(u32 *num, u32 *den) | |
3649 | { | |
3650 | while (*num > 0xffffff || *den > 0xffffff) { | |
3651 | *num >>= 1; | |
3652 | *den >>= 1; | |
3653 | } | |
3654 | } | |
3655 | ||
2c07245f | 3656 | static void |
f2b115e6 AJ |
3657 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
3658 | int link_clock, struct fdi_m_n *m_n) | |
2c07245f | 3659 | { |
2c07245f ZW |
3660 | m_n->tu = 64; /* default size */ |
3661 | ||
22ed1113 CW |
3662 | /* BUG_ON(pixel_clock > INT_MAX / 36); */ |
3663 | m_n->gmch_m = bits_per_pixel * pixel_clock; | |
3664 | m_n->gmch_n = link_clock * nlanes * 8; | |
2c07245f ZW |
3665 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
3666 | ||
22ed1113 CW |
3667 | m_n->link_m = pixel_clock; |
3668 | m_n->link_n = link_clock; | |
2c07245f ZW |
3669 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
3670 | } | |
3671 | ||
3672 | ||
7662c8bd SL |
3673 | struct intel_watermark_params { |
3674 | unsigned long fifo_size; | |
3675 | unsigned long max_wm; | |
3676 | unsigned long default_wm; | |
3677 | unsigned long guard_size; | |
3678 | unsigned long cacheline_size; | |
3679 | }; | |
3680 | ||
f2b115e6 | 3681 | /* Pineview has different values for various configs */ |
d210246a | 3682 | static const struct intel_watermark_params pineview_display_wm = { |
f2b115e6 AJ |
3683 | PINEVIEW_DISPLAY_FIFO, |
3684 | PINEVIEW_MAX_WM, | |
3685 | PINEVIEW_DFT_WM, | |
3686 | PINEVIEW_GUARD_WM, | |
3687 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3688 | }; |
d210246a | 3689 | static const struct intel_watermark_params pineview_display_hplloff_wm = { |
f2b115e6 AJ |
3690 | PINEVIEW_DISPLAY_FIFO, |
3691 | PINEVIEW_MAX_WM, | |
3692 | PINEVIEW_DFT_HPLLOFF_WM, | |
3693 | PINEVIEW_GUARD_WM, | |
3694 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3695 | }; |
d210246a | 3696 | static const struct intel_watermark_params pineview_cursor_wm = { |
f2b115e6 AJ |
3697 | PINEVIEW_CURSOR_FIFO, |
3698 | PINEVIEW_CURSOR_MAX_WM, | |
3699 | PINEVIEW_CURSOR_DFT_WM, | |
3700 | PINEVIEW_CURSOR_GUARD_WM, | |
3701 | PINEVIEW_FIFO_LINE_SIZE, | |
7662c8bd | 3702 | }; |
d210246a | 3703 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { |
f2b115e6 AJ |
3704 | PINEVIEW_CURSOR_FIFO, |
3705 | PINEVIEW_CURSOR_MAX_WM, | |
3706 | PINEVIEW_CURSOR_DFT_WM, | |
3707 | PINEVIEW_CURSOR_GUARD_WM, | |
3708 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3709 | }; |
d210246a | 3710 | static const struct intel_watermark_params g4x_wm_info = { |
0e442c60 JB |
3711 | G4X_FIFO_SIZE, |
3712 | G4X_MAX_WM, | |
3713 | G4X_MAX_WM, | |
3714 | 2, | |
3715 | G4X_FIFO_LINE_SIZE, | |
3716 | }; | |
d210246a | 3717 | static const struct intel_watermark_params g4x_cursor_wm_info = { |
4fe5e611 ZY |
3718 | I965_CURSOR_FIFO, |
3719 | I965_CURSOR_MAX_WM, | |
3720 | I965_CURSOR_DFT_WM, | |
3721 | 2, | |
3722 | G4X_FIFO_LINE_SIZE, | |
3723 | }; | |
ceb04246 JB |
3724 | static const struct intel_watermark_params valleyview_wm_info = { |
3725 | VALLEYVIEW_FIFO_SIZE, | |
3726 | VALLEYVIEW_MAX_WM, | |
3727 | VALLEYVIEW_MAX_WM, | |
3728 | 2, | |
3729 | G4X_FIFO_LINE_SIZE, | |
3730 | }; | |
3731 | static const struct intel_watermark_params valleyview_cursor_wm_info = { | |
3732 | I965_CURSOR_FIFO, | |
3733 | VALLEYVIEW_CURSOR_MAX_WM, | |
3734 | I965_CURSOR_DFT_WM, | |
3735 | 2, | |
3736 | G4X_FIFO_LINE_SIZE, | |
3737 | }; | |
d210246a | 3738 | static const struct intel_watermark_params i965_cursor_wm_info = { |
4fe5e611 ZY |
3739 | I965_CURSOR_FIFO, |
3740 | I965_CURSOR_MAX_WM, | |
3741 | I965_CURSOR_DFT_WM, | |
3742 | 2, | |
3743 | I915_FIFO_LINE_SIZE, | |
3744 | }; | |
d210246a | 3745 | static const struct intel_watermark_params i945_wm_info = { |
dff33cfc | 3746 | I945_FIFO_SIZE, |
7662c8bd SL |
3747 | I915_MAX_WM, |
3748 | 1, | |
dff33cfc JB |
3749 | 2, |
3750 | I915_FIFO_LINE_SIZE | |
7662c8bd | 3751 | }; |
d210246a | 3752 | static const struct intel_watermark_params i915_wm_info = { |
dff33cfc | 3753 | I915_FIFO_SIZE, |
7662c8bd SL |
3754 | I915_MAX_WM, |
3755 | 1, | |
dff33cfc | 3756 | 2, |
7662c8bd SL |
3757 | I915_FIFO_LINE_SIZE |
3758 | }; | |
d210246a | 3759 | static const struct intel_watermark_params i855_wm_info = { |
7662c8bd SL |
3760 | I855GM_FIFO_SIZE, |
3761 | I915_MAX_WM, | |
3762 | 1, | |
dff33cfc | 3763 | 2, |
7662c8bd SL |
3764 | I830_FIFO_LINE_SIZE |
3765 | }; | |
d210246a | 3766 | static const struct intel_watermark_params i830_wm_info = { |
7662c8bd SL |
3767 | I830_FIFO_SIZE, |
3768 | I915_MAX_WM, | |
3769 | 1, | |
dff33cfc | 3770 | 2, |
7662c8bd SL |
3771 | I830_FIFO_LINE_SIZE |
3772 | }; | |
3773 | ||
d210246a | 3774 | static const struct intel_watermark_params ironlake_display_wm_info = { |
7f8a8569 ZW |
3775 | ILK_DISPLAY_FIFO, |
3776 | ILK_DISPLAY_MAXWM, | |
3777 | ILK_DISPLAY_DFTWM, | |
3778 | 2, | |
3779 | ILK_FIFO_LINE_SIZE | |
3780 | }; | |
d210246a | 3781 | static const struct intel_watermark_params ironlake_cursor_wm_info = { |
c936f44d ZY |
3782 | ILK_CURSOR_FIFO, |
3783 | ILK_CURSOR_MAXWM, | |
3784 | ILK_CURSOR_DFTWM, | |
3785 | 2, | |
3786 | ILK_FIFO_LINE_SIZE | |
3787 | }; | |
d210246a | 3788 | static const struct intel_watermark_params ironlake_display_srwm_info = { |
7f8a8569 ZW |
3789 | ILK_DISPLAY_SR_FIFO, |
3790 | ILK_DISPLAY_MAX_SRWM, | |
3791 | ILK_DISPLAY_DFT_SRWM, | |
3792 | 2, | |
3793 | ILK_FIFO_LINE_SIZE | |
3794 | }; | |
d210246a | 3795 | static const struct intel_watermark_params ironlake_cursor_srwm_info = { |
7f8a8569 ZW |
3796 | ILK_CURSOR_SR_FIFO, |
3797 | ILK_CURSOR_MAX_SRWM, | |
3798 | ILK_CURSOR_DFT_SRWM, | |
3799 | 2, | |
3800 | ILK_FIFO_LINE_SIZE | |
3801 | }; | |
3802 | ||
d210246a | 3803 | static const struct intel_watermark_params sandybridge_display_wm_info = { |
1398261a YL |
3804 | SNB_DISPLAY_FIFO, |
3805 | SNB_DISPLAY_MAXWM, | |
3806 | SNB_DISPLAY_DFTWM, | |
3807 | 2, | |
3808 | SNB_FIFO_LINE_SIZE | |
3809 | }; | |
d210246a | 3810 | static const struct intel_watermark_params sandybridge_cursor_wm_info = { |
1398261a YL |
3811 | SNB_CURSOR_FIFO, |
3812 | SNB_CURSOR_MAXWM, | |
3813 | SNB_CURSOR_DFTWM, | |
3814 | 2, | |
3815 | SNB_FIFO_LINE_SIZE | |
3816 | }; | |
d210246a | 3817 | static const struct intel_watermark_params sandybridge_display_srwm_info = { |
1398261a YL |
3818 | SNB_DISPLAY_SR_FIFO, |
3819 | SNB_DISPLAY_MAX_SRWM, | |
3820 | SNB_DISPLAY_DFT_SRWM, | |
3821 | 2, | |
3822 | SNB_FIFO_LINE_SIZE | |
3823 | }; | |
d210246a | 3824 | static const struct intel_watermark_params sandybridge_cursor_srwm_info = { |
1398261a YL |
3825 | SNB_CURSOR_SR_FIFO, |
3826 | SNB_CURSOR_MAX_SRWM, | |
3827 | SNB_CURSOR_DFT_SRWM, | |
3828 | 2, | |
3829 | SNB_FIFO_LINE_SIZE | |
3830 | }; | |
3831 | ||
3832 | ||
dff33cfc JB |
3833 | /** |
3834 | * intel_calculate_wm - calculate watermark level | |
3835 | * @clock_in_khz: pixel clock | |
3836 | * @wm: chip FIFO params | |
3837 | * @pixel_size: display pixel size | |
3838 | * @latency_ns: memory latency for the platform | |
3839 | * | |
3840 | * Calculate the watermark level (the level at which the display plane will | |
3841 | * start fetching from memory again). Each chip has a different display | |
3842 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
3843 | * in the correct intel_watermark_params structure. | |
3844 | * | |
3845 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
3846 | * on the pixel size. When it reaches the watermark level, it'll start | |
3847 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
3848 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
3849 | * will occur, and a display engine hang could result. | |
3850 | */ | |
7662c8bd | 3851 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
d210246a CW |
3852 | const struct intel_watermark_params *wm, |
3853 | int fifo_size, | |
7662c8bd SL |
3854 | int pixel_size, |
3855 | unsigned long latency_ns) | |
3856 | { | |
390c4dd4 | 3857 | long entries_required, wm_size; |
dff33cfc | 3858 | |
d660467c JB |
3859 | /* |
3860 | * Note: we need to make sure we don't overflow for various clock & | |
3861 | * latency values. | |
3862 | * clocks go from a few thousand to several hundred thousand. | |
3863 | * latency is usually a few thousand | |
3864 | */ | |
3865 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
3866 | 1000; | |
8de9b311 | 3867 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
7662c8bd | 3868 | |
bbb0aef5 | 3869 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); |
dff33cfc | 3870 | |
d210246a | 3871 | wm_size = fifo_size - (entries_required + wm->guard_size); |
dff33cfc | 3872 | |
bbb0aef5 | 3873 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); |
7662c8bd | 3874 | |
390c4dd4 JB |
3875 | /* Don't promote wm_size to unsigned... */ |
3876 | if (wm_size > (long)wm->max_wm) | |
7662c8bd | 3877 | wm_size = wm->max_wm; |
c3add4b6 | 3878 | if (wm_size <= 0) |
7662c8bd SL |
3879 | wm_size = wm->default_wm; |
3880 | return wm_size; | |
3881 | } | |
3882 | ||
3883 | struct cxsr_latency { | |
3884 | int is_desktop; | |
95534263 | 3885 | int is_ddr3; |
7662c8bd SL |
3886 | unsigned long fsb_freq; |
3887 | unsigned long mem_freq; | |
3888 | unsigned long display_sr; | |
3889 | unsigned long display_hpll_disable; | |
3890 | unsigned long cursor_sr; | |
3891 | unsigned long cursor_hpll_disable; | |
3892 | }; | |
3893 | ||
403c89ff | 3894 | static const struct cxsr_latency cxsr_latency_table[] = { |
95534263 LP |
3895 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
3896 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
3897 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
3898 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
3899 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
3900 | ||
3901 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
3902 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
3903 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
3904 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
3905 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
3906 | ||
3907 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
3908 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
3909 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
3910 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
3911 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
3912 | ||
3913 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
3914 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
3915 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
3916 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
3917 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
3918 | ||
3919 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
3920 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
3921 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
3922 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
3923 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
3924 | ||
3925 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
3926 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
3927 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
3928 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
3929 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
7662c8bd SL |
3930 | }; |
3931 | ||
403c89ff CW |
3932 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
3933 | int is_ddr3, | |
3934 | int fsb, | |
3935 | int mem) | |
7662c8bd | 3936 | { |
403c89ff | 3937 | const struct cxsr_latency *latency; |
7662c8bd | 3938 | int i; |
7662c8bd SL |
3939 | |
3940 | if (fsb == 0 || mem == 0) | |
3941 | return NULL; | |
3942 | ||
3943 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
3944 | latency = &cxsr_latency_table[i]; | |
3945 | if (is_desktop == latency->is_desktop && | |
95534263 | 3946 | is_ddr3 == latency->is_ddr3 && |
decbbcda JSR |
3947 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
3948 | return latency; | |
7662c8bd | 3949 | } |
decbbcda | 3950 | |
28c97730 | 3951 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
decbbcda JSR |
3952 | |
3953 | return NULL; | |
7662c8bd SL |
3954 | } |
3955 | ||
f2b115e6 | 3956 | static void pineview_disable_cxsr(struct drm_device *dev) |
7662c8bd SL |
3957 | { |
3958 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7662c8bd SL |
3959 | |
3960 | /* deactivate cxsr */ | |
3e33d94d | 3961 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
7662c8bd SL |
3962 | } |
3963 | ||
bcc24fb4 JB |
3964 | /* |
3965 | * Latency for FIFO fetches is dependent on several factors: | |
3966 | * - memory configuration (speed, channels) | |
3967 | * - chipset | |
3968 | * - current MCH state | |
3969 | * It can be fairly high in some situations, so here we assume a fairly | |
3970 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
3971 | * set this value too high, the FIFO will fetch frequently to stay full) | |
3972 | * and power consumption (set it too low to save power and we might see | |
3973 | * FIFO underruns and display "flicker"). | |
3974 | * | |
3975 | * A value of 5us seems to be a good balance; safe for very low end | |
3976 | * platforms but not overly aggressive on lower latency configs. | |
3977 | */ | |
69e302a9 | 3978 | static const int latency_ns = 5000; |
7662c8bd | 3979 | |
e70236a8 | 3980 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
dff33cfc JB |
3981 | { |
3982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3983 | uint32_t dsparb = I915_READ(DSPARB); | |
3984 | int size; | |
3985 | ||
8de9b311 CW |
3986 | size = dsparb & 0x7f; |
3987 | if (plane) | |
3988 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
dff33cfc | 3989 | |
28c97730 | 3990 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3991 | plane ? "B" : "A", size); |
dff33cfc JB |
3992 | |
3993 | return size; | |
3994 | } | |
7662c8bd | 3995 | |
e70236a8 JB |
3996 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
3997 | { | |
3998 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3999 | uint32_t dsparb = I915_READ(DSPARB); | |
4000 | int size; | |
4001 | ||
8de9b311 CW |
4002 | size = dsparb & 0x1ff; |
4003 | if (plane) | |
4004 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
e70236a8 | 4005 | size >>= 1; /* Convert to cachelines */ |
dff33cfc | 4006 | |
28c97730 | 4007 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 4008 | plane ? "B" : "A", size); |
dff33cfc JB |
4009 | |
4010 | return size; | |
4011 | } | |
7662c8bd | 4012 | |
e70236a8 JB |
4013 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
4014 | { | |
4015 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4016 | uint32_t dsparb = I915_READ(DSPARB); | |
4017 | int size; | |
4018 | ||
4019 | size = dsparb & 0x7f; | |
4020 | size >>= 2; /* Convert to cachelines */ | |
4021 | ||
28c97730 | 4022 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b CW |
4023 | plane ? "B" : "A", |
4024 | size); | |
e70236a8 JB |
4025 | |
4026 | return size; | |
4027 | } | |
4028 | ||
4029 | static int i830_get_fifo_size(struct drm_device *dev, int plane) | |
4030 | { | |
4031 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4032 | uint32_t dsparb = I915_READ(DSPARB); | |
4033 | int size; | |
4034 | ||
4035 | size = dsparb & 0x7f; | |
4036 | size >>= 1; /* Convert to cachelines */ | |
4037 | ||
28c97730 | 4038 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 4039 | plane ? "B" : "A", size); |
e70236a8 JB |
4040 | |
4041 | return size; | |
4042 | } | |
4043 | ||
d210246a CW |
4044 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) |
4045 | { | |
4046 | struct drm_crtc *crtc, *enabled = NULL; | |
4047 | ||
4048 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
4049 | if (crtc->enabled && crtc->fb) { | |
4050 | if (enabled) | |
4051 | return NULL; | |
4052 | enabled = crtc; | |
4053 | } | |
4054 | } | |
4055 | ||
4056 | return enabled; | |
4057 | } | |
4058 | ||
4059 | static void pineview_update_wm(struct drm_device *dev) | |
d4294342 ZY |
4060 | { |
4061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a | 4062 | struct drm_crtc *crtc; |
403c89ff | 4063 | const struct cxsr_latency *latency; |
d4294342 ZY |
4064 | u32 reg; |
4065 | unsigned long wm; | |
d4294342 | 4066 | |
403c89ff | 4067 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
95534263 | 4068 | dev_priv->fsb_freq, dev_priv->mem_freq); |
d4294342 ZY |
4069 | if (!latency) { |
4070 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
4071 | pineview_disable_cxsr(dev); | |
4072 | return; | |
4073 | } | |
4074 | ||
d210246a CW |
4075 | crtc = single_enabled_crtc(dev); |
4076 | if (crtc) { | |
4077 | int clock = crtc->mode.clock; | |
4078 | int pixel_size = crtc->fb->bits_per_pixel / 8; | |
d4294342 ZY |
4079 | |
4080 | /* Display SR */ | |
d210246a CW |
4081 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
4082 | pineview_display_wm.fifo_size, | |
d4294342 ZY |
4083 | pixel_size, latency->display_sr); |
4084 | reg = I915_READ(DSPFW1); | |
4085 | reg &= ~DSPFW_SR_MASK; | |
4086 | reg |= wm << DSPFW_SR_SHIFT; | |
4087 | I915_WRITE(DSPFW1, reg); | |
4088 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
4089 | ||
4090 | /* cursor SR */ | |
d210246a CW |
4091 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
4092 | pineview_display_wm.fifo_size, | |
d4294342 ZY |
4093 | pixel_size, latency->cursor_sr); |
4094 | reg = I915_READ(DSPFW3); | |
4095 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
4096 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
4097 | I915_WRITE(DSPFW3, reg); | |
4098 | ||
4099 | /* Display HPLL off SR */ | |
d210246a CW |
4100 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
4101 | pineview_display_hplloff_wm.fifo_size, | |
d4294342 ZY |
4102 | pixel_size, latency->display_hpll_disable); |
4103 | reg = I915_READ(DSPFW3); | |
4104 | reg &= ~DSPFW_HPLL_SR_MASK; | |
4105 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
4106 | I915_WRITE(DSPFW3, reg); | |
4107 | ||
4108 | /* cursor HPLL off SR */ | |
d210246a CW |
4109 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
4110 | pineview_display_hplloff_wm.fifo_size, | |
d4294342 ZY |
4111 | pixel_size, latency->cursor_hpll_disable); |
4112 | reg = I915_READ(DSPFW3); | |
4113 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
4114 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
4115 | I915_WRITE(DSPFW3, reg); | |
4116 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
4117 | ||
4118 | /* activate cxsr */ | |
3e33d94d CW |
4119 | I915_WRITE(DSPFW3, |
4120 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); | |
d4294342 ZY |
4121 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
4122 | } else { | |
4123 | pineview_disable_cxsr(dev); | |
4124 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); | |
4125 | } | |
4126 | } | |
4127 | ||
417ae147 CW |
4128 | static bool g4x_compute_wm0(struct drm_device *dev, |
4129 | int plane, | |
4130 | const struct intel_watermark_params *display, | |
4131 | int display_latency_ns, | |
4132 | const struct intel_watermark_params *cursor, | |
4133 | int cursor_latency_ns, | |
4134 | int *plane_wm, | |
4135 | int *cursor_wm) | |
4136 | { | |
4137 | struct drm_crtc *crtc; | |
4138 | int htotal, hdisplay, clock, pixel_size; | |
4139 | int line_time_us, line_count; | |
4140 | int entries, tlb_miss; | |
4141 | ||
4142 | crtc = intel_get_crtc_for_plane(dev, plane); | |
5c72d064 CW |
4143 | if (crtc->fb == NULL || !crtc->enabled) { |
4144 | *cursor_wm = cursor->guard_size; | |
4145 | *plane_wm = display->guard_size; | |
417ae147 | 4146 | return false; |
5c72d064 | 4147 | } |
417ae147 CW |
4148 | |
4149 | htotal = crtc->mode.htotal; | |
4150 | hdisplay = crtc->mode.hdisplay; | |
4151 | clock = crtc->mode.clock; | |
4152 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
4153 | ||
4154 | /* Use the small buffer method to calculate plane watermark */ | |
4155 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
4156 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; | |
4157 | if (tlb_miss > 0) | |
4158 | entries += tlb_miss; | |
4159 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
4160 | *plane_wm = entries + display->guard_size; | |
4161 | if (*plane_wm > (int)display->max_wm) | |
4162 | *plane_wm = display->max_wm; | |
4163 | ||
4164 | /* Use the large buffer method to calculate cursor watermark */ | |
4165 | line_time_us = ((htotal * 1000) / clock); | |
4166 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; | |
4167 | entries = line_count * 64 * pixel_size; | |
4168 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; | |
4169 | if (tlb_miss > 0) | |
4170 | entries += tlb_miss; | |
4171 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
4172 | *cursor_wm = entries + cursor->guard_size; | |
4173 | if (*cursor_wm > (int)cursor->max_wm) | |
4174 | *cursor_wm = (int)cursor->max_wm; | |
4175 | ||
4176 | return true; | |
4177 | } | |
4178 | ||
4179 | /* | |
4180 | * Check the wm result. | |
4181 | * | |
4182 | * If any calculated watermark values is larger than the maximum value that | |
4183 | * can be programmed into the associated watermark register, that watermark | |
4184 | * must be disabled. | |
4185 | */ | |
4186 | static bool g4x_check_srwm(struct drm_device *dev, | |
4187 | int display_wm, int cursor_wm, | |
4188 | const struct intel_watermark_params *display, | |
4189 | const struct intel_watermark_params *cursor) | |
652c393a | 4190 | { |
417ae147 CW |
4191 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", |
4192 | display_wm, cursor_wm); | |
652c393a | 4193 | |
417ae147 | 4194 | if (display_wm > display->max_wm) { |
bbb0aef5 | 4195 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", |
417ae147 CW |
4196 | display_wm, display->max_wm); |
4197 | return false; | |
4198 | } | |
0e442c60 | 4199 | |
417ae147 | 4200 | if (cursor_wm > cursor->max_wm) { |
bbb0aef5 | 4201 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", |
417ae147 CW |
4202 | cursor_wm, cursor->max_wm); |
4203 | return false; | |
4204 | } | |
0e442c60 | 4205 | |
417ae147 CW |
4206 | if (!(display_wm || cursor_wm)) { |
4207 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
4208 | return false; | |
4209 | } | |
0e442c60 | 4210 | |
417ae147 CW |
4211 | return true; |
4212 | } | |
0e442c60 | 4213 | |
417ae147 | 4214 | static bool g4x_compute_srwm(struct drm_device *dev, |
d210246a CW |
4215 | int plane, |
4216 | int latency_ns, | |
417ae147 CW |
4217 | const struct intel_watermark_params *display, |
4218 | const struct intel_watermark_params *cursor, | |
4219 | int *display_wm, int *cursor_wm) | |
4220 | { | |
d210246a CW |
4221 | struct drm_crtc *crtc; |
4222 | int hdisplay, htotal, pixel_size, clock; | |
417ae147 CW |
4223 | unsigned long line_time_us; |
4224 | int line_count, line_size; | |
4225 | int small, large; | |
4226 | int entries; | |
0e442c60 | 4227 | |
417ae147 CW |
4228 | if (!latency_ns) { |
4229 | *display_wm = *cursor_wm = 0; | |
4230 | return false; | |
4231 | } | |
0e442c60 | 4232 | |
d210246a CW |
4233 | crtc = intel_get_crtc_for_plane(dev, plane); |
4234 | hdisplay = crtc->mode.hdisplay; | |
4235 | htotal = crtc->mode.htotal; | |
4236 | clock = crtc->mode.clock; | |
4237 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
4238 | ||
417ae147 CW |
4239 | line_time_us = (htotal * 1000) / clock; |
4240 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
4241 | line_size = hdisplay * pixel_size; | |
0e442c60 | 4242 | |
417ae147 CW |
4243 | /* Use the minimum of the small and large buffer method for primary */ |
4244 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
4245 | large = line_count * line_size; | |
0e442c60 | 4246 | |
417ae147 CW |
4247 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
4248 | *display_wm = entries + display->guard_size; | |
4fe5e611 | 4249 | |
417ae147 CW |
4250 | /* calculate the self-refresh watermark for display cursor */ |
4251 | entries = line_count * pixel_size * 64; | |
4252 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
4253 | *cursor_wm = entries + cursor->guard_size; | |
4fe5e611 | 4254 | |
417ae147 CW |
4255 | return g4x_check_srwm(dev, |
4256 | *display_wm, *cursor_wm, | |
4257 | display, cursor); | |
4258 | } | |
4fe5e611 | 4259 | |
12a3c055 GB |
4260 | static bool vlv_compute_drain_latency(struct drm_device *dev, |
4261 | int plane, | |
4262 | int *plane_prec_mult, | |
4263 | int *plane_dl, | |
4264 | int *cursor_prec_mult, | |
4265 | int *cursor_dl) | |
4266 | { | |
4267 | struct drm_crtc *crtc; | |
4268 | int clock, pixel_size; | |
4269 | int entries; | |
4270 | ||
4271 | crtc = intel_get_crtc_for_plane(dev, plane); | |
4272 | if (crtc->fb == NULL || !crtc->enabled) | |
4273 | return false; | |
4274 | ||
4275 | clock = crtc->mode.clock; /* VESA DOT Clock */ | |
4276 | pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */ | |
4277 | ||
4278 | entries = (clock / 1000) * pixel_size; | |
4279 | *plane_prec_mult = (entries > 256) ? | |
4280 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; | |
4281 | *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * | |
4282 | pixel_size); | |
4283 | ||
4284 | entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ | |
4285 | *cursor_prec_mult = (entries > 256) ? | |
4286 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; | |
4287 | *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4); | |
4288 | ||
4289 | return true; | |
4290 | } | |
4291 | ||
4292 | /* | |
4293 | * Update drain latency registers of memory arbiter | |
4294 | * | |
4295 | * Valleyview SoC has a new memory arbiter and needs drain latency registers | |
4296 | * to be programmed. Each plane has a drain latency multiplier and a drain | |
4297 | * latency value. | |
4298 | */ | |
4299 | ||
4300 | static void vlv_update_drain_latency(struct drm_device *dev) | |
4301 | { | |
4302 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4303 | int planea_prec, planea_dl, planeb_prec, planeb_dl; | |
4304 | int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl; | |
4305 | int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is | |
4306 | either 16 or 32 */ | |
4307 | ||
4308 | /* For plane A, Cursor A */ | |
4309 | if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl, | |
4310 | &cursor_prec_mult, &cursora_dl)) { | |
4311 | cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? | |
4312 | DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16; | |
4313 | planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? | |
4314 | DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16; | |
4315 | ||
4316 | I915_WRITE(VLV_DDL1, cursora_prec | | |
4317 | (cursora_dl << DDL_CURSORA_SHIFT) | | |
4318 | planea_prec | planea_dl); | |
4319 | } | |
4320 | ||
4321 | /* For plane B, Cursor B */ | |
4322 | if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl, | |
4323 | &cursor_prec_mult, &cursorb_dl)) { | |
4324 | cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? | |
4325 | DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16; | |
4326 | planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? | |
4327 | DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16; | |
4328 | ||
4329 | I915_WRITE(VLV_DDL2, cursorb_prec | | |
4330 | (cursorb_dl << DDL_CURSORB_SHIFT) | | |
4331 | planeb_prec | planeb_dl); | |
4332 | } | |
4333 | } | |
4334 | ||
7ccb4a53 | 4335 | #define single_plane_enabled(mask) is_power_of_2(mask) |
d210246a | 4336 | |
ceb04246 JB |
4337 | static void valleyview_update_wm(struct drm_device *dev) |
4338 | { | |
4339 | static const int sr_latency_ns = 12000; | |
4340 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4341 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
4342 | int plane_sr, cursor_sr; | |
4343 | unsigned int enabled = 0; | |
4344 | ||
12a3c055 GB |
4345 | vlv_update_drain_latency(dev); |
4346 | ||
ceb04246 JB |
4347 | if (g4x_compute_wm0(dev, 0, |
4348 | &valleyview_wm_info, latency_ns, | |
4349 | &valleyview_cursor_wm_info, latency_ns, | |
4350 | &planea_wm, &cursora_wm)) | |
4351 | enabled |= 1; | |
4352 | ||
4353 | if (g4x_compute_wm0(dev, 1, | |
4354 | &valleyview_wm_info, latency_ns, | |
4355 | &valleyview_cursor_wm_info, latency_ns, | |
4356 | &planeb_wm, &cursorb_wm)) | |
4357 | enabled |= 2; | |
4358 | ||
4359 | plane_sr = cursor_sr = 0; | |
4360 | if (single_plane_enabled(enabled) && | |
4361 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
4362 | sr_latency_ns, | |
4363 | &valleyview_wm_info, | |
4364 | &valleyview_cursor_wm_info, | |
4365 | &plane_sr, &cursor_sr)) | |
4366 | I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN); | |
4367 | else | |
4368 | I915_WRITE(FW_BLC_SELF_VLV, | |
4369 | I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN); | |
4370 | ||
4371 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
4372 | planea_wm, cursora_wm, | |
4373 | planeb_wm, cursorb_wm, | |
4374 | plane_sr, cursor_sr); | |
4375 | ||
4376 | I915_WRITE(DSPFW1, | |
4377 | (plane_sr << DSPFW_SR_SHIFT) | | |
4378 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
4379 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
4380 | planea_wm); | |
4381 | I915_WRITE(DSPFW2, | |
4382 | (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | | |
4383 | (cursora_wm << DSPFW_CURSORA_SHIFT)); | |
4384 | I915_WRITE(DSPFW3, | |
4385 | (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT))); | |
4386 | } | |
4387 | ||
d210246a | 4388 | static void g4x_update_wm(struct drm_device *dev) |
417ae147 CW |
4389 | { |
4390 | static const int sr_latency_ns = 12000; | |
4391 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4392 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
d210246a CW |
4393 | int plane_sr, cursor_sr; |
4394 | unsigned int enabled = 0; | |
417ae147 CW |
4395 | |
4396 | if (g4x_compute_wm0(dev, 0, | |
4397 | &g4x_wm_info, latency_ns, | |
4398 | &g4x_cursor_wm_info, latency_ns, | |
4399 | &planea_wm, &cursora_wm)) | |
d210246a | 4400 | enabled |= 1; |
417ae147 CW |
4401 | |
4402 | if (g4x_compute_wm0(dev, 1, | |
4403 | &g4x_wm_info, latency_ns, | |
4404 | &g4x_cursor_wm_info, latency_ns, | |
4405 | &planeb_wm, &cursorb_wm)) | |
d210246a | 4406 | enabled |= 2; |
417ae147 CW |
4407 | |
4408 | plane_sr = cursor_sr = 0; | |
d210246a CW |
4409 | if (single_plane_enabled(enabled) && |
4410 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
4411 | sr_latency_ns, | |
417ae147 CW |
4412 | &g4x_wm_info, |
4413 | &g4x_cursor_wm_info, | |
4414 | &plane_sr, &cursor_sr)) | |
0e442c60 | 4415 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
417ae147 CW |
4416 | else |
4417 | I915_WRITE(FW_BLC_SELF, | |
4418 | I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); | |
0e442c60 | 4419 | |
308977ac CW |
4420 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
4421 | planea_wm, cursora_wm, | |
4422 | planeb_wm, cursorb_wm, | |
4423 | plane_sr, cursor_sr); | |
0e442c60 | 4424 | |
417ae147 CW |
4425 | I915_WRITE(DSPFW1, |
4426 | (plane_sr << DSPFW_SR_SHIFT) | | |
0e442c60 | 4427 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
417ae147 CW |
4428 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
4429 | planea_wm); | |
4430 | I915_WRITE(DSPFW2, | |
4431 | (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | | |
0e442c60 JB |
4432 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
4433 | /* HPLL off in SR has some issues on G4x... disable it */ | |
417ae147 CW |
4434 | I915_WRITE(DSPFW3, |
4435 | (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | | |
0e442c60 | 4436 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
652c393a JB |
4437 | } |
4438 | ||
d210246a | 4439 | static void i965_update_wm(struct drm_device *dev) |
7662c8bd SL |
4440 | { |
4441 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
4442 | struct drm_crtc *crtc; |
4443 | int srwm = 1; | |
4fe5e611 | 4444 | int cursor_sr = 16; |
1dc7546d JB |
4445 | |
4446 | /* Calc sr entries for one plane configs */ | |
d210246a CW |
4447 | crtc = single_enabled_crtc(dev); |
4448 | if (crtc) { | |
1dc7546d | 4449 | /* self-refresh has much higher latency */ |
69e302a9 | 4450 | static const int sr_latency_ns = 12000; |
d210246a CW |
4451 | int clock = crtc->mode.clock; |
4452 | int htotal = crtc->mode.htotal; | |
4453 | int hdisplay = crtc->mode.hdisplay; | |
4454 | int pixel_size = crtc->fb->bits_per_pixel / 8; | |
4455 | unsigned long line_time_us; | |
4456 | int entries; | |
1dc7546d | 4457 | |
d210246a | 4458 | line_time_us = ((htotal * 1000) / clock); |
1dc7546d JB |
4459 | |
4460 | /* Use ns/us then divide to preserve precision */ | |
d210246a CW |
4461 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
4462 | pixel_size * hdisplay; | |
4463 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); | |
d210246a | 4464 | srwm = I965_FIFO_SIZE - entries; |
1dc7546d JB |
4465 | if (srwm < 0) |
4466 | srwm = 1; | |
1b07e04e | 4467 | srwm &= 0x1ff; |
308977ac CW |
4468 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
4469 | entries, srwm); | |
4fe5e611 | 4470 | |
d210246a | 4471 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 4472 | pixel_size * 64; |
d210246a | 4473 | entries = DIV_ROUND_UP(entries, |
8de9b311 | 4474 | i965_cursor_wm_info.cacheline_size); |
4fe5e611 | 4475 | cursor_sr = i965_cursor_wm_info.fifo_size - |
d210246a | 4476 | (entries + i965_cursor_wm_info.guard_size); |
4fe5e611 ZY |
4477 | |
4478 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
4479 | cursor_sr = i965_cursor_wm_info.max_wm; | |
4480 | ||
4481 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
4482 | "cursor %d\n", srwm, cursor_sr); | |
4483 | ||
a6c45cf0 | 4484 | if (IS_CRESTLINE(dev)) |
adcdbc66 | 4485 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
33c5fd12 DJ |
4486 | } else { |
4487 | /* Turn off self refresh if both pipes are enabled */ | |
a6c45cf0 | 4488 | if (IS_CRESTLINE(dev)) |
adcdbc66 JB |
4489 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
4490 | & ~FW_BLC_SELF_EN); | |
1dc7546d | 4491 | } |
7662c8bd | 4492 | |
1dc7546d JB |
4493 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
4494 | srwm); | |
7662c8bd SL |
4495 | |
4496 | /* 965 has limitations... */ | |
417ae147 CW |
4497 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | |
4498 | (8 << 16) | (8 << 8) | (8 << 0)); | |
7662c8bd | 4499 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
4fe5e611 ZY |
4500 | /* update cursor SR watermark */ |
4501 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
7662c8bd SL |
4502 | } |
4503 | ||
d210246a | 4504 | static void i9xx_update_wm(struct drm_device *dev) |
7662c8bd SL |
4505 | { |
4506 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a | 4507 | const struct intel_watermark_params *wm_info; |
dff33cfc JB |
4508 | uint32_t fwater_lo; |
4509 | uint32_t fwater_hi; | |
d210246a CW |
4510 | int cwm, srwm = 1; |
4511 | int fifo_size; | |
dff33cfc | 4512 | int planea_wm, planeb_wm; |
d210246a | 4513 | struct drm_crtc *crtc, *enabled = NULL; |
7662c8bd | 4514 | |
72557b4f | 4515 | if (IS_I945GM(dev)) |
d210246a | 4516 | wm_info = &i945_wm_info; |
a6c45cf0 | 4517 | else if (!IS_GEN2(dev)) |
d210246a | 4518 | wm_info = &i915_wm_info; |
7662c8bd | 4519 | else |
d210246a CW |
4520 | wm_info = &i855_wm_info; |
4521 | ||
4522 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); | |
4523 | crtc = intel_get_crtc_for_plane(dev, 0); | |
4524 | if (crtc->enabled && crtc->fb) { | |
4525 | planea_wm = intel_calculate_wm(crtc->mode.clock, | |
4526 | wm_info, fifo_size, | |
4527 | crtc->fb->bits_per_pixel / 8, | |
4528 | latency_ns); | |
4529 | enabled = crtc; | |
4530 | } else | |
4531 | planea_wm = fifo_size - wm_info->guard_size; | |
4532 | ||
4533 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
4534 | crtc = intel_get_crtc_for_plane(dev, 1); | |
4535 | if (crtc->enabled && crtc->fb) { | |
4536 | planeb_wm = intel_calculate_wm(crtc->mode.clock, | |
4537 | wm_info, fifo_size, | |
4538 | crtc->fb->bits_per_pixel / 8, | |
4539 | latency_ns); | |
4540 | if (enabled == NULL) | |
4541 | enabled = crtc; | |
4542 | else | |
4543 | enabled = NULL; | |
4544 | } else | |
4545 | planeb_wm = fifo_size - wm_info->guard_size; | |
7662c8bd | 4546 | |
28c97730 | 4547 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
7662c8bd SL |
4548 | |
4549 | /* | |
4550 | * Overlay gets an aggressive default since video jitter is bad. | |
4551 | */ | |
4552 | cwm = 2; | |
4553 | ||
18b2190c AL |
4554 | /* Play safe and disable self-refresh before adjusting watermarks. */ |
4555 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
4556 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); | |
4557 | else if (IS_I915GM(dev)) | |
4558 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); | |
4559 | ||
dff33cfc | 4560 | /* Calc sr entries for one plane configs */ |
d210246a | 4561 | if (HAS_FW_BLC(dev) && enabled) { |
dff33cfc | 4562 | /* self-refresh has much higher latency */ |
69e302a9 | 4563 | static const int sr_latency_ns = 6000; |
d210246a CW |
4564 | int clock = enabled->mode.clock; |
4565 | int htotal = enabled->mode.htotal; | |
4566 | int hdisplay = enabled->mode.hdisplay; | |
4567 | int pixel_size = enabled->fb->bits_per_pixel / 8; | |
4568 | unsigned long line_time_us; | |
4569 | int entries; | |
dff33cfc | 4570 | |
d210246a | 4571 | line_time_us = (htotal * 1000) / clock; |
dff33cfc JB |
4572 | |
4573 | /* Use ns/us then divide to preserve precision */ | |
d210246a CW |
4574 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
4575 | pixel_size * hdisplay; | |
4576 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); | |
4577 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
4578 | srwm = wm_info->fifo_size - entries; | |
dff33cfc JB |
4579 | if (srwm < 0) |
4580 | srwm = 1; | |
ee980b80 LP |
4581 | |
4582 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
18b2190c AL |
4583 | I915_WRITE(FW_BLC_SELF, |
4584 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
4585 | else if (IS_I915GM(dev)) | |
ee980b80 | 4586 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
7662c8bd SL |
4587 | } |
4588 | ||
28c97730 | 4589 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
5eddb70b | 4590 | planea_wm, planeb_wm, cwm, srwm); |
7662c8bd | 4591 | |
dff33cfc JB |
4592 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
4593 | fwater_hi = (cwm & 0x1f); | |
4594 | ||
4595 | /* Set request length to 8 cachelines per fetch */ | |
4596 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
4597 | fwater_hi = fwater_hi | (1 << 8); | |
7662c8bd SL |
4598 | |
4599 | I915_WRITE(FW_BLC, fwater_lo); | |
4600 | I915_WRITE(FW_BLC2, fwater_hi); | |
18b2190c | 4601 | |
d210246a CW |
4602 | if (HAS_FW_BLC(dev)) { |
4603 | if (enabled) { | |
4604 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
4605 | I915_WRITE(FW_BLC_SELF, | |
4606 | FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); | |
4607 | else if (IS_I915GM(dev)) | |
4608 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); | |
4609 | DRM_DEBUG_KMS("memory self refresh enabled\n"); | |
4610 | } else | |
4611 | DRM_DEBUG_KMS("memory self refresh disabled\n"); | |
4612 | } | |
7662c8bd SL |
4613 | } |
4614 | ||
d210246a | 4615 | static void i830_update_wm(struct drm_device *dev) |
7662c8bd SL |
4616 | { |
4617 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
4618 | struct drm_crtc *crtc; |
4619 | uint32_t fwater_lo; | |
dff33cfc | 4620 | int planea_wm; |
7662c8bd | 4621 | |
d210246a CW |
4622 | crtc = single_enabled_crtc(dev); |
4623 | if (crtc == NULL) | |
4624 | return; | |
7662c8bd | 4625 | |
d210246a CW |
4626 | planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, |
4627 | dev_priv->display.get_fifo_size(dev, 0), | |
4628 | crtc->fb->bits_per_pixel / 8, | |
4629 | latency_ns); | |
4630 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; | |
f3601326 JB |
4631 | fwater_lo |= (3<<8) | planea_wm; |
4632 | ||
28c97730 | 4633 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
7662c8bd SL |
4634 | |
4635 | I915_WRITE(FW_BLC, fwater_lo); | |
4636 | } | |
4637 | ||
7f8a8569 | 4638 | #define ILK_LP0_PLANE_LATENCY 700 |
c936f44d | 4639 | #define ILK_LP0_CURSOR_LATENCY 1300 |
7f8a8569 | 4640 | |
1398261a YL |
4641 | /* |
4642 | * Check the wm result. | |
4643 | * | |
4644 | * If any calculated watermark values is larger than the maximum value that | |
4645 | * can be programmed into the associated watermark register, that watermark | |
4646 | * must be disabled. | |
1398261a | 4647 | */ |
b79d4990 JB |
4648 | static bool ironlake_check_srwm(struct drm_device *dev, int level, |
4649 | int fbc_wm, int display_wm, int cursor_wm, | |
4650 | const struct intel_watermark_params *display, | |
4651 | const struct intel_watermark_params *cursor) | |
1398261a YL |
4652 | { |
4653 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4654 | ||
4655 | DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," | |
4656 | " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); | |
4657 | ||
4658 | if (fbc_wm > SNB_FBC_MAX_SRWM) { | |
4659 | DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", | |
b79d4990 | 4660 | fbc_wm, SNB_FBC_MAX_SRWM, level); |
1398261a YL |
4661 | |
4662 | /* fbc has it's own way to disable FBC WM */ | |
4663 | I915_WRITE(DISP_ARB_CTL, | |
4664 | I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); | |
4665 | return false; | |
4666 | } | |
4667 | ||
b79d4990 | 4668 | if (display_wm > display->max_wm) { |
1398261a | 4669 | DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", |
b79d4990 | 4670 | display_wm, SNB_DISPLAY_MAX_SRWM, level); |
1398261a YL |
4671 | return false; |
4672 | } | |
4673 | ||
b79d4990 | 4674 | if (cursor_wm > cursor->max_wm) { |
1398261a | 4675 | DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", |
b79d4990 | 4676 | cursor_wm, SNB_CURSOR_MAX_SRWM, level); |
1398261a YL |
4677 | return false; |
4678 | } | |
4679 | ||
4680 | if (!(fbc_wm || display_wm || cursor_wm)) { | |
4681 | DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); | |
4682 | return false; | |
4683 | } | |
4684 | ||
4685 | return true; | |
4686 | } | |
4687 | ||
4688 | /* | |
4689 | * Compute watermark values of WM[1-3], | |
4690 | */ | |
d210246a CW |
4691 | static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, |
4692 | int latency_ns, | |
b79d4990 JB |
4693 | const struct intel_watermark_params *display, |
4694 | const struct intel_watermark_params *cursor, | |
4695 | int *fbc_wm, int *display_wm, int *cursor_wm) | |
1398261a | 4696 | { |
d210246a | 4697 | struct drm_crtc *crtc; |
1398261a | 4698 | unsigned long line_time_us; |
d210246a | 4699 | int hdisplay, htotal, pixel_size, clock; |
b79d4990 | 4700 | int line_count, line_size; |
1398261a YL |
4701 | int small, large; |
4702 | int entries; | |
1398261a YL |
4703 | |
4704 | if (!latency_ns) { | |
4705 | *fbc_wm = *display_wm = *cursor_wm = 0; | |
4706 | return false; | |
4707 | } | |
4708 | ||
d210246a CW |
4709 | crtc = intel_get_crtc_for_plane(dev, plane); |
4710 | hdisplay = crtc->mode.hdisplay; | |
4711 | htotal = crtc->mode.htotal; | |
4712 | clock = crtc->mode.clock; | |
4713 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
4714 | ||
1398261a YL |
4715 | line_time_us = (htotal * 1000) / clock; |
4716 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
4717 | line_size = hdisplay * pixel_size; | |
4718 | ||
4719 | /* Use the minimum of the small and large buffer method for primary */ | |
4720 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
4721 | large = line_count * line_size; | |
4722 | ||
b79d4990 JB |
4723 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
4724 | *display_wm = entries + display->guard_size; | |
1398261a YL |
4725 | |
4726 | /* | |
b79d4990 | 4727 | * Spec says: |
1398261a YL |
4728 | * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 |
4729 | */ | |
4730 | *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; | |
4731 | ||
4732 | /* calculate the self-refresh watermark for display cursor */ | |
4733 | entries = line_count * pixel_size * 64; | |
b79d4990 JB |
4734 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
4735 | *cursor_wm = entries + cursor->guard_size; | |
1398261a | 4736 | |
b79d4990 JB |
4737 | return ironlake_check_srwm(dev, level, |
4738 | *fbc_wm, *display_wm, *cursor_wm, | |
4739 | display, cursor); | |
4740 | } | |
4741 | ||
d210246a | 4742 | static void ironlake_update_wm(struct drm_device *dev) |
b79d4990 JB |
4743 | { |
4744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
4745 | int fbc_wm, plane_wm, cursor_wm; |
4746 | unsigned int enabled; | |
b79d4990 JB |
4747 | |
4748 | enabled = 0; | |
9f405100 CW |
4749 | if (g4x_compute_wm0(dev, 0, |
4750 | &ironlake_display_wm_info, | |
4751 | ILK_LP0_PLANE_LATENCY, | |
4752 | &ironlake_cursor_wm_info, | |
4753 | ILK_LP0_CURSOR_LATENCY, | |
4754 | &plane_wm, &cursor_wm)) { | |
b79d4990 JB |
4755 | I915_WRITE(WM0_PIPEA_ILK, |
4756 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
4757 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
4758 | " plane %d, " "cursor: %d\n", | |
4759 | plane_wm, cursor_wm); | |
d210246a | 4760 | enabled |= 1; |
b79d4990 JB |
4761 | } |
4762 | ||
9f405100 CW |
4763 | if (g4x_compute_wm0(dev, 1, |
4764 | &ironlake_display_wm_info, | |
4765 | ILK_LP0_PLANE_LATENCY, | |
4766 | &ironlake_cursor_wm_info, | |
4767 | ILK_LP0_CURSOR_LATENCY, | |
4768 | &plane_wm, &cursor_wm)) { | |
b79d4990 JB |
4769 | I915_WRITE(WM0_PIPEB_ILK, |
4770 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
4771 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
4772 | " plane %d, cursor: %d\n", | |
4773 | plane_wm, cursor_wm); | |
d210246a | 4774 | enabled |= 2; |
b79d4990 JB |
4775 | } |
4776 | ||
4777 | /* | |
4778 | * Calculate and update the self-refresh watermark only when one | |
4779 | * display plane is used. | |
4780 | */ | |
4781 | I915_WRITE(WM3_LP_ILK, 0); | |
4782 | I915_WRITE(WM2_LP_ILK, 0); | |
4783 | I915_WRITE(WM1_LP_ILK, 0); | |
4784 | ||
d210246a | 4785 | if (!single_plane_enabled(enabled)) |
b79d4990 | 4786 | return; |
d210246a | 4787 | enabled = ffs(enabled) - 1; |
b79d4990 JB |
4788 | |
4789 | /* WM1 */ | |
d210246a CW |
4790 | if (!ironlake_compute_srwm(dev, 1, enabled, |
4791 | ILK_READ_WM1_LATENCY() * 500, | |
b79d4990 JB |
4792 | &ironlake_display_srwm_info, |
4793 | &ironlake_cursor_srwm_info, | |
4794 | &fbc_wm, &plane_wm, &cursor_wm)) | |
4795 | return; | |
4796 | ||
4797 | I915_WRITE(WM1_LP_ILK, | |
4798 | WM1_LP_SR_EN | | |
4799 | (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4800 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4801 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4802 | cursor_wm); | |
4803 | ||
4804 | /* WM2 */ | |
d210246a CW |
4805 | if (!ironlake_compute_srwm(dev, 2, enabled, |
4806 | ILK_READ_WM2_LATENCY() * 500, | |
b79d4990 JB |
4807 | &ironlake_display_srwm_info, |
4808 | &ironlake_cursor_srwm_info, | |
4809 | &fbc_wm, &plane_wm, &cursor_wm)) | |
4810 | return; | |
4811 | ||
4812 | I915_WRITE(WM2_LP_ILK, | |
4813 | WM2_LP_EN | | |
4814 | (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4815 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4816 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4817 | cursor_wm); | |
4818 | ||
4819 | /* | |
4820 | * WM3 is unsupported on ILK, probably because we don't have latency | |
4821 | * data for that power state | |
4822 | */ | |
1398261a YL |
4823 | } |
4824 | ||
b840d907 | 4825 | void sandybridge_update_wm(struct drm_device *dev) |
1398261a YL |
4826 | { |
4827 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a0fa62d3 | 4828 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
47842649 | 4829 | u32 val; |
d210246a CW |
4830 | int fbc_wm, plane_wm, cursor_wm; |
4831 | unsigned int enabled; | |
1398261a YL |
4832 | |
4833 | enabled = 0; | |
9f405100 CW |
4834 | if (g4x_compute_wm0(dev, 0, |
4835 | &sandybridge_display_wm_info, latency, | |
4836 | &sandybridge_cursor_wm_info, latency, | |
4837 | &plane_wm, &cursor_wm)) { | |
47842649 JB |
4838 | val = I915_READ(WM0_PIPEA_ILK); |
4839 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
4840 | I915_WRITE(WM0_PIPEA_ILK, val | | |
4841 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | |
1398261a YL |
4842 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
4843 | " plane %d, " "cursor: %d\n", | |
4844 | plane_wm, cursor_wm); | |
d210246a | 4845 | enabled |= 1; |
1398261a YL |
4846 | } |
4847 | ||
9f405100 CW |
4848 | if (g4x_compute_wm0(dev, 1, |
4849 | &sandybridge_display_wm_info, latency, | |
4850 | &sandybridge_cursor_wm_info, latency, | |
4851 | &plane_wm, &cursor_wm)) { | |
47842649 JB |
4852 | val = I915_READ(WM0_PIPEB_ILK); |
4853 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
4854 | I915_WRITE(WM0_PIPEB_ILK, val | | |
4855 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | |
1398261a YL |
4856 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
4857 | " plane %d, cursor: %d\n", | |
4858 | plane_wm, cursor_wm); | |
d210246a | 4859 | enabled |= 2; |
1398261a YL |
4860 | } |
4861 | ||
d6c892df JB |
4862 | /* IVB has 3 pipes */ |
4863 | if (IS_IVYBRIDGE(dev) && | |
4864 | g4x_compute_wm0(dev, 2, | |
4865 | &sandybridge_display_wm_info, latency, | |
4866 | &sandybridge_cursor_wm_info, latency, | |
4867 | &plane_wm, &cursor_wm)) { | |
47842649 JB |
4868 | val = I915_READ(WM0_PIPEC_IVB); |
4869 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
4870 | I915_WRITE(WM0_PIPEC_IVB, val | | |
4871 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | |
d6c892df JB |
4872 | DRM_DEBUG_KMS("FIFO watermarks For pipe C -" |
4873 | " plane %d, cursor: %d\n", | |
4874 | plane_wm, cursor_wm); | |
4875 | enabled |= 3; | |
4876 | } | |
4877 | ||
1398261a YL |
4878 | /* |
4879 | * Calculate and update the self-refresh watermark only when one | |
4880 | * display plane is used. | |
4881 | * | |
4882 | * SNB support 3 levels of watermark. | |
4883 | * | |
4884 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, | |
4885 | * and disabled in the descending order | |
4886 | * | |
4887 | */ | |
4888 | I915_WRITE(WM3_LP_ILK, 0); | |
4889 | I915_WRITE(WM2_LP_ILK, 0); | |
4890 | I915_WRITE(WM1_LP_ILK, 0); | |
4891 | ||
b840d907 JB |
4892 | if (!single_plane_enabled(enabled) || |
4893 | dev_priv->sprite_scaling_enabled) | |
1398261a | 4894 | return; |
d210246a | 4895 | enabled = ffs(enabled) - 1; |
1398261a YL |
4896 | |
4897 | /* WM1 */ | |
d210246a CW |
4898 | if (!ironlake_compute_srwm(dev, 1, enabled, |
4899 | SNB_READ_WM1_LATENCY() * 500, | |
b79d4990 JB |
4900 | &sandybridge_display_srwm_info, |
4901 | &sandybridge_cursor_srwm_info, | |
4902 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4903 | return; |
4904 | ||
4905 | I915_WRITE(WM1_LP_ILK, | |
4906 | WM1_LP_SR_EN | | |
4907 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4908 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4909 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4910 | cursor_wm); | |
4911 | ||
4912 | /* WM2 */ | |
d210246a CW |
4913 | if (!ironlake_compute_srwm(dev, 2, enabled, |
4914 | SNB_READ_WM2_LATENCY() * 500, | |
b79d4990 JB |
4915 | &sandybridge_display_srwm_info, |
4916 | &sandybridge_cursor_srwm_info, | |
4917 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4918 | return; |
4919 | ||
4920 | I915_WRITE(WM2_LP_ILK, | |
4921 | WM2_LP_EN | | |
4922 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4923 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4924 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4925 | cursor_wm); | |
4926 | ||
4927 | /* WM3 */ | |
d210246a CW |
4928 | if (!ironlake_compute_srwm(dev, 3, enabled, |
4929 | SNB_READ_WM3_LATENCY() * 500, | |
b79d4990 JB |
4930 | &sandybridge_display_srwm_info, |
4931 | &sandybridge_cursor_srwm_info, | |
4932 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4933 | return; |
4934 | ||
4935 | I915_WRITE(WM3_LP_ILK, | |
4936 | WM3_LP_EN | | |
4937 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4938 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4939 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4940 | cursor_wm); | |
4941 | } | |
4942 | ||
b840d907 JB |
4943 | static bool |
4944 | sandybridge_compute_sprite_wm(struct drm_device *dev, int plane, | |
4945 | uint32_t sprite_width, int pixel_size, | |
4946 | const struct intel_watermark_params *display, | |
4947 | int display_latency_ns, int *sprite_wm) | |
4948 | { | |
4949 | struct drm_crtc *crtc; | |
4950 | int clock; | |
4951 | int entries, tlb_miss; | |
4952 | ||
4953 | crtc = intel_get_crtc_for_plane(dev, plane); | |
4954 | if (crtc->fb == NULL || !crtc->enabled) { | |
4955 | *sprite_wm = display->guard_size; | |
4956 | return false; | |
4957 | } | |
4958 | ||
4959 | clock = crtc->mode.clock; | |
4960 | ||
4961 | /* Use the small buffer method to calculate the sprite watermark */ | |
4962 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
4963 | tlb_miss = display->fifo_size*display->cacheline_size - | |
4964 | sprite_width * 8; | |
4965 | if (tlb_miss > 0) | |
4966 | entries += tlb_miss; | |
4967 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
4968 | *sprite_wm = entries + display->guard_size; | |
4969 | if (*sprite_wm > (int)display->max_wm) | |
4970 | *sprite_wm = display->max_wm; | |
4971 | ||
4972 | return true; | |
4973 | } | |
4974 | ||
4975 | static bool | |
4976 | sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, | |
4977 | uint32_t sprite_width, int pixel_size, | |
4978 | const struct intel_watermark_params *display, | |
4979 | int latency_ns, int *sprite_wm) | |
4980 | { | |
4981 | struct drm_crtc *crtc; | |
4982 | unsigned long line_time_us; | |
4983 | int clock; | |
4984 | int line_count, line_size; | |
4985 | int small, large; | |
4986 | int entries; | |
4987 | ||
4988 | if (!latency_ns) { | |
4989 | *sprite_wm = 0; | |
4990 | return false; | |
4991 | } | |
4992 | ||
4993 | crtc = intel_get_crtc_for_plane(dev, plane); | |
4994 | clock = crtc->mode.clock; | |
4e9bb47b HL |
4995 | if (!clock) { |
4996 | *sprite_wm = 0; | |
4997 | return false; | |
4998 | } | |
b840d907 JB |
4999 | |
5000 | line_time_us = (sprite_width * 1000) / clock; | |
4e9bb47b HL |
5001 | if (!line_time_us) { |
5002 | *sprite_wm = 0; | |
5003 | return false; | |
5004 | } | |
5005 | ||
b840d907 JB |
5006 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
5007 | line_size = sprite_width * pixel_size; | |
5008 | ||
5009 | /* Use the minimum of the small and large buffer method for primary */ | |
5010 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
5011 | large = line_count * line_size; | |
5012 | ||
5013 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
5014 | *sprite_wm = entries + display->guard_size; | |
5015 | ||
5016 | return *sprite_wm > 0x3ff ? false : true; | |
5017 | } | |
5018 | ||
5019 | static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, | |
5020 | uint32_t sprite_width, int pixel_size) | |
5021 | { | |
5022 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5023 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ | |
47842649 | 5024 | u32 val; |
b840d907 JB |
5025 | int sprite_wm, reg; |
5026 | int ret; | |
5027 | ||
5028 | switch (pipe) { | |
5029 | case 0: | |
5030 | reg = WM0_PIPEA_ILK; | |
5031 | break; | |
5032 | case 1: | |
5033 | reg = WM0_PIPEB_ILK; | |
5034 | break; | |
5035 | case 2: | |
5036 | reg = WM0_PIPEC_IVB; | |
5037 | break; | |
5038 | default: | |
5039 | return; /* bad pipe */ | |
5040 | } | |
5041 | ||
5042 | ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size, | |
5043 | &sandybridge_display_wm_info, | |
5044 | latency, &sprite_wm); | |
5045 | if (!ret) { | |
5046 | DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n", | |
5047 | pipe); | |
5048 | return; | |
5049 | } | |
5050 | ||
47842649 JB |
5051 | val = I915_READ(reg); |
5052 | val &= ~WM0_PIPE_SPRITE_MASK; | |
5053 | I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); | |
b840d907 JB |
5054 | DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm); |
5055 | ||
5056 | ||
5057 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, | |
5058 | pixel_size, | |
5059 | &sandybridge_display_srwm_info, | |
5060 | SNB_READ_WM1_LATENCY() * 500, | |
5061 | &sprite_wm); | |
5062 | if (!ret) { | |
5063 | DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n", | |
5064 | pipe); | |
5065 | return; | |
5066 | } | |
5067 | I915_WRITE(WM1S_LP_ILK, sprite_wm); | |
5068 | ||
5069 | /* Only IVB has two more LP watermarks for sprite */ | |
5070 | if (!IS_IVYBRIDGE(dev)) | |
5071 | return; | |
5072 | ||
5073 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, | |
5074 | pixel_size, | |
5075 | &sandybridge_display_srwm_info, | |
5076 | SNB_READ_WM2_LATENCY() * 500, | |
5077 | &sprite_wm); | |
5078 | if (!ret) { | |
5079 | DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n", | |
5080 | pipe); | |
5081 | return; | |
5082 | } | |
5083 | I915_WRITE(WM2S_LP_IVB, sprite_wm); | |
5084 | ||
5085 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, | |
5086 | pixel_size, | |
5087 | &sandybridge_display_srwm_info, | |
5088 | SNB_READ_WM3_LATENCY() * 500, | |
5089 | &sprite_wm); | |
5090 | if (!ret) { | |
5091 | DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n", | |
5092 | pipe); | |
5093 | return; | |
5094 | } | |
5095 | I915_WRITE(WM3S_LP_IVB, sprite_wm); | |
5096 | } | |
5097 | ||
7662c8bd SL |
5098 | /** |
5099 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
5100 | * | |
5101 | * Calculate watermark values for the various WM regs based on current mode | |
5102 | * and plane configuration. | |
5103 | * | |
5104 | * There are several cases to deal with here: | |
5105 | * - normal (i.e. non-self-refresh) | |
5106 | * - self-refresh (SR) mode | |
5107 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
5108 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
5109 | * lines), so need to account for TLB latency | |
5110 | * | |
5111 | * The normal calculation is: | |
5112 | * watermark = dotclock * bytes per pixel * latency | |
5113 | * where latency is platform & configuration dependent (we assume pessimal | |
5114 | * values here). | |
5115 | * | |
5116 | * The SR calculation is: | |
5117 | * watermark = (trunc(latency/line time)+1) * surface width * | |
5118 | * bytes per pixel | |
5119 | * where | |
5120 | * line time = htotal / dotclock | |
fa143215 | 5121 | * surface width = hdisplay for normal plane and 64 for cursor |
7662c8bd SL |
5122 | * and latency is assumed to be high, as above. |
5123 | * | |
5124 | * The final value programmed to the register should always be rounded up, | |
5125 | * and include an extra 2 entries to account for clock crossings. | |
5126 | * | |
5127 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
5128 | * to set the non-SR watermarks to 8. | |
5eddb70b | 5129 | */ |
7662c8bd SL |
5130 | static void intel_update_watermarks(struct drm_device *dev) |
5131 | { | |
e70236a8 | 5132 | struct drm_i915_private *dev_priv = dev->dev_private; |
7662c8bd | 5133 | |
d210246a CW |
5134 | if (dev_priv->display.update_wm) |
5135 | dev_priv->display.update_wm(dev); | |
7662c8bd SL |
5136 | } |
5137 | ||
b840d907 JB |
5138 | void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
5139 | uint32_t sprite_width, int pixel_size) | |
5140 | { | |
5141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5142 | ||
5143 | if (dev_priv->display.update_sprite_wm) | |
5144 | dev_priv->display.update_sprite_wm(dev, pipe, sprite_width, | |
5145 | pixel_size); | |
5146 | } | |
5147 | ||
a7615030 CW |
5148 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5149 | { | |
72bbe58c KP |
5150 | if (i915_panel_use_ssc >= 0) |
5151 | return i915_panel_use_ssc != 0; | |
5152 | return dev_priv->lvds_use_ssc | |
435793df | 5153 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
5154 | } |
5155 | ||
5a354204 JB |
5156 | /** |
5157 | * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send | |
5158 | * @crtc: CRTC structure | |
3b5c78a3 | 5159 | * @mode: requested mode |
5a354204 JB |
5160 | * |
5161 | * A pipe may be connected to one or more outputs. Based on the depth of the | |
5162 | * attached framebuffer, choose a good color depth to use on the pipe. | |
5163 | * | |
5164 | * If possible, match the pipe depth to the fb depth. In some cases, this | |
5165 | * isn't ideal, because the connected output supports a lesser or restricted | |
5166 | * set of depths. Resolve that here: | |
5167 | * LVDS typically supports only 6bpc, so clamp down in that case | |
5168 | * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc | |
5169 | * Displays may support a restricted set as well, check EDID and clamp as | |
5170 | * appropriate. | |
3b5c78a3 | 5171 | * DP may want to dither down to 6bpc to fit larger modes |
5a354204 JB |
5172 | * |
5173 | * RETURNS: | |
5174 | * Dithering requirement (i.e. false if display bpc and pipe bpc match, | |
5175 | * true if they don't match). | |
5176 | */ | |
5177 | static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, | |
3b5c78a3 AJ |
5178 | unsigned int *pipe_bpp, |
5179 | struct drm_display_mode *mode) | |
5a354204 JB |
5180 | { |
5181 | struct drm_device *dev = crtc->dev; | |
5182 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5183 | struct drm_encoder *encoder; | |
5184 | struct drm_connector *connector; | |
5185 | unsigned int display_bpc = UINT_MAX, bpc; | |
5186 | ||
5187 | /* Walk the encoders & connectors on this crtc, get min bpc */ | |
5188 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
5189 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5190 | ||
5191 | if (encoder->crtc != crtc) | |
5192 | continue; | |
5193 | ||
5194 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) { | |
5195 | unsigned int lvds_bpc; | |
5196 | ||
5197 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == | |
5198 | LVDS_A3_POWER_UP) | |
5199 | lvds_bpc = 8; | |
5200 | else | |
5201 | lvds_bpc = 6; | |
5202 | ||
5203 | if (lvds_bpc < display_bpc) { | |
82820490 | 5204 | DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); |
5a354204 JB |
5205 | display_bpc = lvds_bpc; |
5206 | } | |
5207 | continue; | |
5208 | } | |
5209 | ||
5210 | if (intel_encoder->type == INTEL_OUTPUT_EDP) { | |
5211 | /* Use VBT settings if we have an eDP panel */ | |
5212 | unsigned int edp_bpc = dev_priv->edp.bpp / 3; | |
5213 | ||
5214 | if (edp_bpc < display_bpc) { | |
82820490 | 5215 | DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); |
5a354204 JB |
5216 | display_bpc = edp_bpc; |
5217 | } | |
5218 | continue; | |
5219 | } | |
5220 | ||
5221 | /* Not one of the known troublemakers, check the EDID */ | |
5222 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
5223 | head) { | |
5224 | if (connector->encoder != encoder) | |
5225 | continue; | |
5226 | ||
62ac41a6 JB |
5227 | /* Don't use an invalid EDID bpc value */ |
5228 | if (connector->display_info.bpc && | |
5229 | connector->display_info.bpc < display_bpc) { | |
82820490 | 5230 | DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); |
5a354204 JB |
5231 | display_bpc = connector->display_info.bpc; |
5232 | } | |
5233 | } | |
5234 | ||
5235 | /* | |
5236 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
5237 | * through, clamp it down. (Note: >12bpc will be caught below.) | |
5238 | */ | |
5239 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { | |
5240 | if (display_bpc > 8 && display_bpc < 12) { | |
82820490 | 5241 | DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); |
5a354204 JB |
5242 | display_bpc = 12; |
5243 | } else { | |
82820490 | 5244 | DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); |
5a354204 JB |
5245 | display_bpc = 8; |
5246 | } | |
5247 | } | |
5248 | } | |
5249 | ||
3b5c78a3 AJ |
5250 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
5251 | DRM_DEBUG_KMS("Dithering DP to 6bpc\n"); | |
5252 | display_bpc = 6; | |
5253 | } | |
5254 | ||
5a354204 JB |
5255 | /* |
5256 | * We could just drive the pipe at the highest bpc all the time and | |
5257 | * enable dithering as needed, but that costs bandwidth. So choose | |
5258 | * the minimum value that expresses the full color range of the fb but | |
5259 | * also stays within the max display bpc discovered above. | |
5260 | */ | |
5261 | ||
5262 | switch (crtc->fb->depth) { | |
5263 | case 8: | |
5264 | bpc = 8; /* since we go through a colormap */ | |
5265 | break; | |
5266 | case 15: | |
5267 | case 16: | |
5268 | bpc = 6; /* min is 18bpp */ | |
5269 | break; | |
5270 | case 24: | |
578393cd | 5271 | bpc = 8; |
5a354204 JB |
5272 | break; |
5273 | case 30: | |
578393cd | 5274 | bpc = 10; |
5a354204 JB |
5275 | break; |
5276 | case 48: | |
578393cd | 5277 | bpc = 12; |
5a354204 JB |
5278 | break; |
5279 | default: | |
5280 | DRM_DEBUG("unsupported depth, assuming 24 bits\n"); | |
5281 | bpc = min((unsigned int)8, display_bpc); | |
5282 | break; | |
5283 | } | |
5284 | ||
578393cd KP |
5285 | display_bpc = min(display_bpc, bpc); |
5286 | ||
82820490 AJ |
5287 | DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n", |
5288 | bpc, display_bpc); | |
5a354204 | 5289 | |
578393cd | 5290 | *pipe_bpp = display_bpc * 3; |
5a354204 JB |
5291 | |
5292 | return display_bpc != bpc; | |
5293 | } | |
5294 | ||
c65d77d8 JB |
5295 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
5296 | { | |
5297 | struct drm_device *dev = crtc->dev; | |
5298 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5299 | int refclk; | |
5300 | ||
5301 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
5302 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
5303 | refclk = dev_priv->lvds_ssc_freq * 1000; | |
5304 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
5305 | refclk / 1000); | |
5306 | } else if (!IS_GEN2(dev)) { | |
5307 | refclk = 96000; | |
5308 | } else { | |
5309 | refclk = 48000; | |
5310 | } | |
5311 | ||
5312 | return refclk; | |
5313 | } | |
5314 | ||
5315 | static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, | |
5316 | intel_clock_t *clock) | |
5317 | { | |
5318 | /* SDVO TV has fixed PLL values depend on its clock range, | |
5319 | this mirrors vbios setting. */ | |
5320 | if (adjusted_mode->clock >= 100000 | |
5321 | && adjusted_mode->clock < 140500) { | |
5322 | clock->p1 = 2; | |
5323 | clock->p2 = 10; | |
5324 | clock->n = 3; | |
5325 | clock->m1 = 16; | |
5326 | clock->m2 = 8; | |
5327 | } else if (adjusted_mode->clock >= 140500 | |
5328 | && adjusted_mode->clock <= 200000) { | |
5329 | clock->p1 = 1; | |
5330 | clock->p2 = 10; | |
5331 | clock->n = 6; | |
5332 | clock->m1 = 12; | |
5333 | clock->m2 = 8; | |
5334 | } | |
5335 | } | |
5336 | ||
a7516a05 JB |
5337 | static void i9xx_update_pll_dividers(struct drm_crtc *crtc, |
5338 | intel_clock_t *clock, | |
5339 | intel_clock_t *reduced_clock) | |
5340 | { | |
5341 | struct drm_device *dev = crtc->dev; | |
5342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5343 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5344 | int pipe = intel_crtc->pipe; | |
5345 | u32 fp, fp2 = 0; | |
5346 | ||
5347 | if (IS_PINEVIEW(dev)) { | |
5348 | fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; | |
5349 | if (reduced_clock) | |
5350 | fp2 = (1 << reduced_clock->n) << 16 | | |
5351 | reduced_clock->m1 << 8 | reduced_clock->m2; | |
5352 | } else { | |
5353 | fp = clock->n << 16 | clock->m1 << 8 | clock->m2; | |
5354 | if (reduced_clock) | |
5355 | fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | | |
5356 | reduced_clock->m2; | |
5357 | } | |
5358 | ||
5359 | I915_WRITE(FP0(pipe), fp); | |
5360 | ||
5361 | intel_crtc->lowfreq_avail = false; | |
5362 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
5363 | reduced_clock && i915_powersave) { | |
5364 | I915_WRITE(FP1(pipe), fp2); | |
5365 | intel_crtc->lowfreq_avail = true; | |
5366 | } else { | |
5367 | I915_WRITE(FP1(pipe), fp); | |
5368 | } | |
5369 | } | |
5370 | ||
93e537a1 DV |
5371 | static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock, |
5372 | struct drm_display_mode *adjusted_mode) | |
5373 | { | |
5374 | struct drm_device *dev = crtc->dev; | |
5375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5376 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5377 | int pipe = intel_crtc->pipe; | |
5378 | u32 temp, lvds_sync = 0; | |
5379 | ||
5380 | temp = I915_READ(LVDS); | |
5381 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
5382 | if (pipe == 1) { | |
5383 | temp |= LVDS_PIPEB_SELECT; | |
5384 | } else { | |
5385 | temp &= ~LVDS_PIPEB_SELECT; | |
5386 | } | |
5387 | /* set the corresponsding LVDS_BORDER bit */ | |
5388 | temp |= dev_priv->lvds_border_bits; | |
5389 | /* Set the B0-B3 data pairs corresponding to whether we're going to | |
5390 | * set the DPLLs for dual-channel mode or not. | |
5391 | */ | |
5392 | if (clock->p2 == 7) | |
5393 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
5394 | else | |
5395 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
5396 | ||
5397 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
5398 | * appropriately here, but we need to look more thoroughly into how | |
5399 | * panels behave in the two modes. | |
5400 | */ | |
5401 | /* set the dithering flag on LVDS as needed */ | |
5402 | if (INTEL_INFO(dev)->gen >= 4) { | |
5403 | if (dev_priv->lvds_dither) | |
5404 | temp |= LVDS_ENABLE_DITHER; | |
5405 | else | |
5406 | temp &= ~LVDS_ENABLE_DITHER; | |
5407 | } | |
5408 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) | |
5409 | lvds_sync |= LVDS_HSYNC_POLARITY; | |
5410 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) | |
5411 | lvds_sync |= LVDS_VSYNC_POLARITY; | |
5412 | if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) | |
5413 | != lvds_sync) { | |
5414 | char flags[2] = "-+"; | |
5415 | DRM_INFO("Changing LVDS panel from " | |
5416 | "(%chsync, %cvsync) to (%chsync, %cvsync)\n", | |
5417 | flags[!(temp & LVDS_HSYNC_POLARITY)], | |
5418 | flags[!(temp & LVDS_VSYNC_POLARITY)], | |
5419 | flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], | |
5420 | flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); | |
5421 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
5422 | temp |= lvds_sync; | |
5423 | } | |
5424 | I915_WRITE(LVDS, temp); | |
5425 | } | |
5426 | ||
eb1cbe48 DV |
5427 | static void i9xx_update_pll(struct drm_crtc *crtc, |
5428 | struct drm_display_mode *mode, | |
5429 | struct drm_display_mode *adjusted_mode, | |
5430 | intel_clock_t *clock, intel_clock_t *reduced_clock, | |
5431 | int num_connectors) | |
5432 | { | |
5433 | struct drm_device *dev = crtc->dev; | |
5434 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5435 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5436 | int pipe = intel_crtc->pipe; | |
5437 | u32 dpll; | |
5438 | bool is_sdvo; | |
5439 | ||
5440 | is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) || | |
5441 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); | |
5442 | ||
5443 | dpll = DPLL_VGA_MODE_DIS; | |
5444 | ||
5445 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
5446 | dpll |= DPLLB_MODE_LVDS; | |
5447 | else | |
5448 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
5449 | if (is_sdvo) { | |
5450 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); | |
5451 | if (pixel_multiplier > 1) { | |
5452 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
5453 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
5454 | } | |
5455 | dpll |= DPLL_DVO_HIGH_SPEED; | |
5456 | } | |
5457 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
5458 | dpll |= DPLL_DVO_HIGH_SPEED; | |
5459 | ||
5460 | /* compute bitmask from p1 value */ | |
5461 | if (IS_PINEVIEW(dev)) | |
5462 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
5463 | else { | |
5464 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5465 | if (IS_G4X(dev) && reduced_clock) | |
5466 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5467 | } | |
5468 | switch (clock->p2) { | |
5469 | case 5: | |
5470 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5471 | break; | |
5472 | case 7: | |
5473 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5474 | break; | |
5475 | case 10: | |
5476 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5477 | break; | |
5478 | case 14: | |
5479 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5480 | break; | |
5481 | } | |
5482 | if (INTEL_INFO(dev)->gen >= 4) | |
5483 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
5484 | ||
5485 | if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
5486 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
5487 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
5488 | /* XXX: just matching BIOS for now */ | |
5489 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ | |
5490 | dpll |= 3; | |
5491 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
5492 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) | |
5493 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5494 | else | |
5495 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5496 | ||
5497 | dpll |= DPLL_VCO_ENABLE; | |
5498 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
5499 | POSTING_READ(DPLL(pipe)); | |
5500 | udelay(150); | |
5501 | ||
5502 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. | |
5503 | * This is an exception to the general rule that mode_set doesn't turn | |
5504 | * things on. | |
5505 | */ | |
5506 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
5507 | intel_update_lvds(crtc, clock, adjusted_mode); | |
5508 | ||
5509 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) | |
5510 | intel_dp_set_m_n(crtc, mode, adjusted_mode); | |
5511 | ||
5512 | I915_WRITE(DPLL(pipe), dpll); | |
5513 | ||
5514 | /* Wait for the clocks to stabilize. */ | |
5515 | POSTING_READ(DPLL(pipe)); | |
5516 | udelay(150); | |
5517 | ||
5518 | if (INTEL_INFO(dev)->gen >= 4) { | |
5519 | u32 temp = 0; | |
5520 | if (is_sdvo) { | |
5521 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); | |
5522 | if (temp > 1) | |
5523 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
5524 | else | |
5525 | temp = 0; | |
5526 | } | |
5527 | I915_WRITE(DPLL_MD(pipe), temp); | |
5528 | } else { | |
5529 | /* The pixel multiplier can only be updated once the | |
5530 | * DPLL is enabled and the clocks are stable. | |
5531 | * | |
5532 | * So write it again. | |
5533 | */ | |
5534 | I915_WRITE(DPLL(pipe), dpll); | |
5535 | } | |
5536 | } | |
5537 | ||
5538 | static void i8xx_update_pll(struct drm_crtc *crtc, | |
5539 | struct drm_display_mode *adjusted_mode, | |
5540 | intel_clock_t *clock, | |
5541 | int num_connectors) | |
5542 | { | |
5543 | struct drm_device *dev = crtc->dev; | |
5544 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5545 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5546 | int pipe = intel_crtc->pipe; | |
5547 | u32 dpll; | |
5548 | ||
5549 | dpll = DPLL_VGA_MODE_DIS; | |
5550 | ||
5551 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
5552 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5553 | } else { | |
5554 | if (clock->p1 == 2) | |
5555 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5556 | else | |
5557 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5558 | if (clock->p2 == 4) | |
5559 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5560 | } | |
5561 | ||
5562 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) | |
5563 | /* XXX: just matching BIOS for now */ | |
5564 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ | |
5565 | dpll |= 3; | |
5566 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
5567 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) | |
5568 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5569 | else | |
5570 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5571 | ||
5572 | dpll |= DPLL_VCO_ENABLE; | |
5573 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
5574 | POSTING_READ(DPLL(pipe)); | |
5575 | udelay(150); | |
5576 | ||
5577 | I915_WRITE(DPLL(pipe), dpll); | |
5578 | ||
5579 | /* Wait for the clocks to stabilize. */ | |
5580 | POSTING_READ(DPLL(pipe)); | |
5581 | udelay(150); | |
5582 | ||
5583 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. | |
5584 | * This is an exception to the general rule that mode_set doesn't turn | |
5585 | * things on. | |
5586 | */ | |
5587 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
5588 | intel_update_lvds(crtc, clock, adjusted_mode); | |
5589 | ||
5590 | /* The pixel multiplier can only be updated once the | |
5591 | * DPLL is enabled and the clocks are stable. | |
5592 | * | |
5593 | * So write it again. | |
5594 | */ | |
5595 | I915_WRITE(DPLL(pipe), dpll); | |
5596 | } | |
5597 | ||
f564048e EA |
5598 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
5599 | struct drm_display_mode *mode, | |
5600 | struct drm_display_mode *adjusted_mode, | |
5601 | int x, int y, | |
5602 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
5603 | { |
5604 | struct drm_device *dev = crtc->dev; | |
5605 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5606 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5607 | int pipe = intel_crtc->pipe; | |
80824003 | 5608 | int plane = intel_crtc->plane; |
c751ce4f | 5609 | int refclk, num_connectors = 0; |
652c393a | 5610 | intel_clock_t clock, reduced_clock; |
eb1cbe48 DV |
5611 | u32 dspcntr, pipeconf, vsyncshift; |
5612 | bool ok, has_reduced_clock = false, is_sdvo = false; | |
5613 | bool is_lvds = false, is_tv = false, is_dp = false; | |
79e53945 | 5614 | struct drm_mode_config *mode_config = &dev->mode_config; |
5eddb70b | 5615 | struct intel_encoder *encoder; |
d4906093 | 5616 | const intel_limit_t *limit; |
5c3b82e2 | 5617 | int ret; |
79e53945 | 5618 | |
5eddb70b CW |
5619 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
5620 | if (encoder->base.crtc != crtc) | |
79e53945 JB |
5621 | continue; |
5622 | ||
5eddb70b | 5623 | switch (encoder->type) { |
79e53945 JB |
5624 | case INTEL_OUTPUT_LVDS: |
5625 | is_lvds = true; | |
5626 | break; | |
5627 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5628 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5629 | is_sdvo = true; |
5eddb70b | 5630 | if (encoder->needs_tv_clock) |
e2f0ba97 | 5631 | is_tv = true; |
79e53945 | 5632 | break; |
79e53945 JB |
5633 | case INTEL_OUTPUT_TVOUT: |
5634 | is_tv = true; | |
5635 | break; | |
a4fc5ed6 KP |
5636 | case INTEL_OUTPUT_DISPLAYPORT: |
5637 | is_dp = true; | |
5638 | break; | |
79e53945 | 5639 | } |
43565a06 | 5640 | |
c751ce4f | 5641 | num_connectors++; |
79e53945 JB |
5642 | } |
5643 | ||
c65d77d8 | 5644 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 5645 | |
d4906093 ML |
5646 | /* |
5647 | * Returns a set of divisors for the desired target clock with the given | |
5648 | * refclk, or FALSE. The returned values represent the clock equation: | |
5649 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
5650 | */ | |
1b894b59 | 5651 | limit = intel_limit(crtc, refclk); |
cec2f356 SP |
5652 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
5653 | &clock); | |
79e53945 JB |
5654 | if (!ok) { |
5655 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 5656 | return -EINVAL; |
79e53945 JB |
5657 | } |
5658 | ||
cda4b7d3 | 5659 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 5660 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 5661 | |
ddc9003c | 5662 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
5663 | /* |
5664 | * Ensure we match the reduced clock's P to the target clock. | |
5665 | * If the clocks don't match, we can't switch the display clock | |
5666 | * by using the FP0/FP1. In such case we will disable the LVDS | |
5667 | * downclock feature. | |
5668 | */ | |
ddc9003c | 5669 | has_reduced_clock = limit->find_pll(limit, crtc, |
5eddb70b CW |
5670 | dev_priv->lvds_downclock, |
5671 | refclk, | |
cec2f356 | 5672 | &clock, |
5eddb70b | 5673 | &reduced_clock); |
7026d4ac ZW |
5674 | } |
5675 | ||
c65d77d8 JB |
5676 | if (is_sdvo && is_tv) |
5677 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); | |
7026d4ac | 5678 | |
a7516a05 JB |
5679 | i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ? |
5680 | &reduced_clock : NULL); | |
79e53945 | 5681 | |
eb1cbe48 DV |
5682 | if (IS_GEN2(dev)) |
5683 | i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors); | |
79e53945 | 5684 | else |
eb1cbe48 DV |
5685 | i9xx_update_pll(crtc, mode, adjusted_mode, &clock, |
5686 | has_reduced_clock ? &reduced_clock : NULL, | |
5687 | num_connectors); | |
79e53945 JB |
5688 | |
5689 | /* setup pipeconf */ | |
5eddb70b | 5690 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
5691 | |
5692 | /* Set up the display plane register */ | |
5693 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
5694 | ||
929c77fb EA |
5695 | if (pipe == 0) |
5696 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
5697 | else | |
5698 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
79e53945 | 5699 | |
a6c45cf0 | 5700 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
79e53945 JB |
5701 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
5702 | * core speed. | |
5703 | * | |
5704 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
5705 | * pipe == 0 check? | |
5706 | */ | |
e70236a8 JB |
5707 | if (mode->clock > |
5708 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
5eddb70b | 5709 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
79e53945 | 5710 | else |
5eddb70b | 5711 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
79e53945 JB |
5712 | } |
5713 | ||
3b5c78a3 AJ |
5714 | /* default to 8bpc */ |
5715 | pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN); | |
5716 | if (is_dp) { | |
5717 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { | |
5718 | pipeconf |= PIPECONF_BPP_6 | | |
5719 | PIPECONF_DITHER_EN | | |
5720 | PIPECONF_DITHER_TYPE_SP; | |
5721 | } | |
5722 | } | |
5723 | ||
28c97730 | 5724 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
5725 | drm_mode_debug_printmodeline(mode); |
5726 | ||
a7516a05 JB |
5727 | if (HAS_PIPE_CXSR(dev)) { |
5728 | if (intel_crtc->lowfreq_avail) { | |
28c97730 | 5729 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
652c393a | 5730 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
a7516a05 | 5731 | } else { |
28c97730 | 5732 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
652c393a JB |
5733 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
5734 | } | |
5735 | } | |
5736 | ||
617cf884 | 5737 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
dbb02575 DV |
5738 | if (!IS_GEN2(dev) && |
5739 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
734b4157 KH |
5740 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
5741 | /* the chip adds 2 halflines automatically */ | |
734b4157 | 5742 | adjusted_mode->crtc_vtotal -= 1; |
734b4157 | 5743 | adjusted_mode->crtc_vblank_end -= 1; |
0529a0d9 DV |
5744 | vsyncshift = adjusted_mode->crtc_hsync_start |
5745 | - adjusted_mode->crtc_htotal/2; | |
5746 | } else { | |
617cf884 | 5747 | pipeconf |= PIPECONF_PROGRESSIVE; |
0529a0d9 DV |
5748 | vsyncshift = 0; |
5749 | } | |
5750 | ||
5751 | if (!IS_GEN3(dev)) | |
5752 | I915_WRITE(VSYNCSHIFT(pipe), vsyncshift); | |
734b4157 | 5753 | |
5eddb70b CW |
5754 | I915_WRITE(HTOTAL(pipe), |
5755 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 5756 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
5757 | I915_WRITE(HBLANK(pipe), |
5758 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 5759 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
5760 | I915_WRITE(HSYNC(pipe), |
5761 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 5762 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
5763 | |
5764 | I915_WRITE(VTOTAL(pipe), | |
5765 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 5766 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
5767 | I915_WRITE(VBLANK(pipe), |
5768 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 5769 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
5770 | I915_WRITE(VSYNC(pipe), |
5771 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 5772 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b CW |
5773 | |
5774 | /* pipesrc and dspsize control the size that is scaled from, | |
5775 | * which should always be the user's requested size. | |
79e53945 | 5776 | */ |
929c77fb EA |
5777 | I915_WRITE(DSPSIZE(plane), |
5778 | ((mode->vdisplay - 1) << 16) | | |
5779 | (mode->hdisplay - 1)); | |
5780 | I915_WRITE(DSPPOS(plane), 0); | |
5eddb70b CW |
5781 | I915_WRITE(PIPESRC(pipe), |
5782 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 5783 | |
f564048e EA |
5784 | I915_WRITE(PIPECONF(pipe), pipeconf); |
5785 | POSTING_READ(PIPECONF(pipe)); | |
929c77fb | 5786 | intel_enable_pipe(dev_priv, pipe, false); |
f564048e EA |
5787 | |
5788 | intel_wait_for_vblank(dev, pipe); | |
5789 | ||
f564048e EA |
5790 | I915_WRITE(DSPCNTR(plane), dspcntr); |
5791 | POSTING_READ(DSPCNTR(plane)); | |
284d9529 | 5792 | intel_enable_plane(dev_priv, plane, pipe); |
f564048e EA |
5793 | |
5794 | ret = intel_pipe_set_base(crtc, x, y, old_fb); | |
5795 | ||
5796 | intel_update_watermarks(dev); | |
5797 | ||
f564048e EA |
5798 | return ret; |
5799 | } | |
5800 | ||
9fb526db KP |
5801 | /* |
5802 | * Initialize reference clocks when the driver loads | |
5803 | */ | |
5804 | void ironlake_init_pch_refclk(struct drm_device *dev) | |
13d83a67 JB |
5805 | { |
5806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5807 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 5808 | struct intel_encoder *encoder; |
13d83a67 JB |
5809 | u32 temp; |
5810 | bool has_lvds = false; | |
199e5d79 KP |
5811 | bool has_cpu_edp = false; |
5812 | bool has_pch_edp = false; | |
5813 | bool has_panel = false; | |
99eb6a01 KP |
5814 | bool has_ck505 = false; |
5815 | bool can_ssc = false; | |
13d83a67 JB |
5816 | |
5817 | /* We need to take the global config into account */ | |
199e5d79 KP |
5818 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5819 | base.head) { | |
5820 | switch (encoder->type) { | |
5821 | case INTEL_OUTPUT_LVDS: | |
5822 | has_panel = true; | |
5823 | has_lvds = true; | |
5824 | break; | |
5825 | case INTEL_OUTPUT_EDP: | |
5826 | has_panel = true; | |
5827 | if (intel_encoder_is_pch_edp(&encoder->base)) | |
5828 | has_pch_edp = true; | |
5829 | else | |
5830 | has_cpu_edp = true; | |
5831 | break; | |
13d83a67 JB |
5832 | } |
5833 | } | |
5834 | ||
99eb6a01 KP |
5835 | if (HAS_PCH_IBX(dev)) { |
5836 | has_ck505 = dev_priv->display_clock_mode; | |
5837 | can_ssc = has_ck505; | |
5838 | } else { | |
5839 | has_ck505 = false; | |
5840 | can_ssc = true; | |
5841 | } | |
5842 | ||
5843 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", | |
5844 | has_panel, has_lvds, has_pch_edp, has_cpu_edp, | |
5845 | has_ck505); | |
13d83a67 JB |
5846 | |
5847 | /* Ironlake: try to setup display ref clock before DPLL | |
5848 | * enabling. This is only under driver's control after | |
5849 | * PCH B stepping, previous chipset stepping should be | |
5850 | * ignoring this setting. | |
5851 | */ | |
5852 | temp = I915_READ(PCH_DREF_CONTROL); | |
5853 | /* Always enable nonspread source */ | |
5854 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
13d83a67 | 5855 | |
99eb6a01 KP |
5856 | if (has_ck505) |
5857 | temp |= DREF_NONSPREAD_CK505_ENABLE; | |
5858 | else | |
5859 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | |
13d83a67 | 5860 | |
199e5d79 KP |
5861 | if (has_panel) { |
5862 | temp &= ~DREF_SSC_SOURCE_MASK; | |
5863 | temp |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 5864 | |
199e5d79 | 5865 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 5866 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5867 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
13d83a67 | 5868 | temp |= DREF_SSC1_ENABLE; |
e77166b5 DV |
5869 | } else |
5870 | temp &= ~DREF_SSC1_ENABLE; | |
199e5d79 KP |
5871 | |
5872 | /* Get SSC going before enabling the outputs */ | |
5873 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5874 | POSTING_READ(PCH_DREF_CONTROL); | |
5875 | udelay(200); | |
5876 | ||
13d83a67 JB |
5877 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5878 | ||
5879 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 5880 | if (has_cpu_edp) { |
99eb6a01 | 5881 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5882 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
13d83a67 | 5883 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 5884 | } |
13d83a67 JB |
5885 | else |
5886 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
199e5d79 KP |
5887 | } else |
5888 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5889 | ||
5890 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5891 | POSTING_READ(PCH_DREF_CONTROL); | |
5892 | udelay(200); | |
5893 | } else { | |
5894 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
5895 | ||
5896 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
5897 | ||
5898 | /* Turn off CPU output */ | |
5899 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5900 | ||
5901 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5902 | POSTING_READ(PCH_DREF_CONTROL); | |
5903 | udelay(200); | |
5904 | ||
5905 | /* Turn off the SSC source */ | |
5906 | temp &= ~DREF_SSC_SOURCE_MASK; | |
5907 | temp |= DREF_SSC_SOURCE_DISABLE; | |
5908 | ||
5909 | /* Turn off SSC1 */ | |
5910 | temp &= ~ DREF_SSC1_ENABLE; | |
5911 | ||
13d83a67 JB |
5912 | I915_WRITE(PCH_DREF_CONTROL, temp); |
5913 | POSTING_READ(PCH_DREF_CONTROL); | |
5914 | udelay(200); | |
5915 | } | |
5916 | } | |
5917 | ||
d9d444cb JB |
5918 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5919 | { | |
5920 | struct drm_device *dev = crtc->dev; | |
5921 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5922 | struct intel_encoder *encoder; | |
5923 | struct drm_mode_config *mode_config = &dev->mode_config; | |
5924 | struct intel_encoder *edp_encoder = NULL; | |
5925 | int num_connectors = 0; | |
5926 | bool is_lvds = false; | |
5927 | ||
5928 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
5929 | if (encoder->base.crtc != crtc) | |
5930 | continue; | |
5931 | ||
5932 | switch (encoder->type) { | |
5933 | case INTEL_OUTPUT_LVDS: | |
5934 | is_lvds = true; | |
5935 | break; | |
5936 | case INTEL_OUTPUT_EDP: | |
5937 | edp_encoder = encoder; | |
5938 | break; | |
5939 | } | |
5940 | num_connectors++; | |
5941 | } | |
5942 | ||
5943 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
5944 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
5945 | dev_priv->lvds_ssc_freq); | |
5946 | return dev_priv->lvds_ssc_freq * 1000; | |
5947 | } | |
5948 | ||
5949 | return 120000; | |
5950 | } | |
5951 | ||
f564048e EA |
5952 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
5953 | struct drm_display_mode *mode, | |
5954 | struct drm_display_mode *adjusted_mode, | |
5955 | int x, int y, | |
5956 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
5957 | { |
5958 | struct drm_device *dev = crtc->dev; | |
5959 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5960 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5961 | int pipe = intel_crtc->pipe; | |
80824003 | 5962 | int plane = intel_crtc->plane; |
c751ce4f | 5963 | int refclk, num_connectors = 0; |
652c393a | 5964 | intel_clock_t clock, reduced_clock; |
5eddb70b | 5965 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; |
a07d6787 | 5966 | bool ok, has_reduced_clock = false, is_sdvo = false; |
a4fc5ed6 | 5967 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
8e647a27 | 5968 | struct intel_encoder *has_edp_encoder = NULL; |
79e53945 | 5969 | struct drm_mode_config *mode_config = &dev->mode_config; |
5eddb70b | 5970 | struct intel_encoder *encoder; |
d4906093 | 5971 | const intel_limit_t *limit; |
5c3b82e2 | 5972 | int ret; |
2c07245f | 5973 | struct fdi_m_n m_n = {0}; |
fae14981 | 5974 | u32 temp; |
aa9b500d | 5975 | u32 lvds_sync = 0; |
5a354204 JB |
5976 | int target_clock, pixel_multiplier, lane, link_bw, factor; |
5977 | unsigned int pipe_bpp; | |
5978 | bool dither; | |
79e53945 | 5979 | |
5eddb70b CW |
5980 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
5981 | if (encoder->base.crtc != crtc) | |
79e53945 JB |
5982 | continue; |
5983 | ||
5eddb70b | 5984 | switch (encoder->type) { |
79e53945 JB |
5985 | case INTEL_OUTPUT_LVDS: |
5986 | is_lvds = true; | |
5987 | break; | |
5988 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5989 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5990 | is_sdvo = true; |
5eddb70b | 5991 | if (encoder->needs_tv_clock) |
e2f0ba97 | 5992 | is_tv = true; |
79e53945 | 5993 | break; |
79e53945 JB |
5994 | case INTEL_OUTPUT_TVOUT: |
5995 | is_tv = true; | |
5996 | break; | |
5997 | case INTEL_OUTPUT_ANALOG: | |
5998 | is_crt = true; | |
5999 | break; | |
a4fc5ed6 KP |
6000 | case INTEL_OUTPUT_DISPLAYPORT: |
6001 | is_dp = true; | |
6002 | break; | |
32f9d658 | 6003 | case INTEL_OUTPUT_EDP: |
5eddb70b | 6004 | has_edp_encoder = encoder; |
32f9d658 | 6005 | break; |
79e53945 | 6006 | } |
43565a06 | 6007 | |
c751ce4f | 6008 | num_connectors++; |
79e53945 JB |
6009 | } |
6010 | ||
d9d444cb | 6011 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 6012 | |
d4906093 ML |
6013 | /* |
6014 | * Returns a set of divisors for the desired target clock with the given | |
6015 | * refclk, or FALSE. The returned values represent the clock equation: | |
6016 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
6017 | */ | |
1b894b59 | 6018 | limit = intel_limit(crtc, refclk); |
cec2f356 SP |
6019 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
6020 | &clock); | |
79e53945 JB |
6021 | if (!ok) { |
6022 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 6023 | return -EINVAL; |
79e53945 JB |
6024 | } |
6025 | ||
cda4b7d3 | 6026 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 6027 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 6028 | |
ddc9003c | 6029 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
6030 | /* |
6031 | * Ensure we match the reduced clock's P to the target clock. | |
6032 | * If the clocks don't match, we can't switch the display clock | |
6033 | * by using the FP0/FP1. In such case we will disable the LVDS | |
6034 | * downclock feature. | |
6035 | */ | |
ddc9003c | 6036 | has_reduced_clock = limit->find_pll(limit, crtc, |
5eddb70b CW |
6037 | dev_priv->lvds_downclock, |
6038 | refclk, | |
cec2f356 | 6039 | &clock, |
5eddb70b | 6040 | &reduced_clock); |
652c393a | 6041 | } |
7026d4ac ZW |
6042 | /* SDVO TV has fixed PLL values depend on its clock range, |
6043 | this mirrors vbios setting. */ | |
6044 | if (is_sdvo && is_tv) { | |
6045 | if (adjusted_mode->clock >= 100000 | |
5eddb70b | 6046 | && adjusted_mode->clock < 140500) { |
7026d4ac ZW |
6047 | clock.p1 = 2; |
6048 | clock.p2 = 10; | |
6049 | clock.n = 3; | |
6050 | clock.m1 = 16; | |
6051 | clock.m2 = 8; | |
6052 | } else if (adjusted_mode->clock >= 140500 | |
5eddb70b | 6053 | && adjusted_mode->clock <= 200000) { |
7026d4ac ZW |
6054 | clock.p1 = 1; |
6055 | clock.p2 = 10; | |
6056 | clock.n = 6; | |
6057 | clock.m1 = 12; | |
6058 | clock.m2 = 8; | |
6059 | } | |
6060 | } | |
6061 | ||
2c07245f | 6062 | /* FDI link */ |
8febb297 EA |
6063 | pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
6064 | lane = 0; | |
6065 | /* CPU eDP doesn't require FDI link, so just set DP M/N | |
6066 | according to current link config */ | |
6067 | if (has_edp_encoder && | |
6068 | !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
6069 | target_clock = mode->clock; | |
6070 | intel_edp_link_config(has_edp_encoder, | |
6071 | &lane, &link_bw); | |
6072 | } else { | |
6073 | /* [e]DP over FDI requires target mode clock | |
6074 | instead of link clock */ | |
6075 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) | |
5eb08b69 | 6076 | target_clock = mode->clock; |
8febb297 EA |
6077 | else |
6078 | target_clock = adjusted_mode->clock; | |
6079 | ||
6080 | /* FDI is a binary signal running at ~2.7GHz, encoding | |
6081 | * each output octet as 10 bits. The actual frequency | |
6082 | * is stored as a divider into a 100MHz clock, and the | |
6083 | * mode pixel clock is stored in units of 1KHz. | |
6084 | * Hence the bw of each lane in terms of the mode signal | |
6085 | * is: | |
6086 | */ | |
6087 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6088 | } | |
58a27471 | 6089 | |
8febb297 EA |
6090 | /* determine panel color depth */ |
6091 | temp = I915_READ(PIPECONF(pipe)); | |
6092 | temp &= ~PIPE_BPC_MASK; | |
3b5c78a3 | 6093 | dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode); |
5a354204 JB |
6094 | switch (pipe_bpp) { |
6095 | case 18: | |
6096 | temp |= PIPE_6BPC; | |
8febb297 | 6097 | break; |
5a354204 JB |
6098 | case 24: |
6099 | temp |= PIPE_8BPC; | |
8febb297 | 6100 | break; |
5a354204 JB |
6101 | case 30: |
6102 | temp |= PIPE_10BPC; | |
8febb297 | 6103 | break; |
5a354204 JB |
6104 | case 36: |
6105 | temp |= PIPE_12BPC; | |
8febb297 EA |
6106 | break; |
6107 | default: | |
62ac41a6 JB |
6108 | WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n", |
6109 | pipe_bpp); | |
5a354204 JB |
6110 | temp |= PIPE_8BPC; |
6111 | pipe_bpp = 24; | |
6112 | break; | |
8febb297 | 6113 | } |
77ffb597 | 6114 | |
5a354204 JB |
6115 | intel_crtc->bpp = pipe_bpp; |
6116 | I915_WRITE(PIPECONF(pipe), temp); | |
6117 | ||
8febb297 EA |
6118 | if (!lane) { |
6119 | /* | |
6120 | * Account for spread spectrum to avoid | |
6121 | * oversubscribing the link. Max center spread | |
6122 | * is 2.5%; use 5% for safety's sake. | |
6123 | */ | |
5a354204 | 6124 | u32 bps = target_clock * intel_crtc->bpp * 21 / 20; |
8febb297 | 6125 | lane = bps / (link_bw * 8) + 1; |
5eb08b69 | 6126 | } |
2c07245f | 6127 | |
8febb297 EA |
6128 | intel_crtc->fdi_lanes = lane; |
6129 | ||
6130 | if (pixel_multiplier > 1) | |
6131 | link_bw *= pixel_multiplier; | |
5a354204 JB |
6132 | ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, |
6133 | &m_n); | |
8febb297 | 6134 | |
a07d6787 EA |
6135 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
6136 | if (has_reduced_clock) | |
6137 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
6138 | reduced_clock.m2; | |
79e53945 | 6139 | |
c1858123 | 6140 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
6141 | factor = 21; |
6142 | if (is_lvds) { | |
6143 | if ((intel_panel_use_ssc(dev_priv) && | |
6144 | dev_priv->lvds_ssc_freq == 100) || | |
6145 | (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) | |
6146 | factor = 25; | |
6147 | } else if (is_sdvo && is_tv) | |
6148 | factor = 20; | |
c1858123 | 6149 | |
cb0e0931 | 6150 | if (clock.m < factor * clock.n) |
8febb297 | 6151 | fp |= FP_CB_TUNE; |
2c07245f | 6152 | |
5eddb70b | 6153 | dpll = 0; |
2c07245f | 6154 | |
a07d6787 EA |
6155 | if (is_lvds) |
6156 | dpll |= DPLLB_MODE_LVDS; | |
6157 | else | |
6158 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6159 | if (is_sdvo) { | |
6160 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); | |
6161 | if (pixel_multiplier > 1) { | |
6162 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
79e53945 | 6163 | } |
a07d6787 EA |
6164 | dpll |= DPLL_DVO_HIGH_SPEED; |
6165 | } | |
6166 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) | |
6167 | dpll |= DPLL_DVO_HIGH_SPEED; | |
79e53945 | 6168 | |
a07d6787 EA |
6169 | /* compute bitmask from p1 value */ |
6170 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6171 | /* also FPA1 */ | |
6172 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
6173 | ||
6174 | switch (clock.p2) { | |
6175 | case 5: | |
6176 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6177 | break; | |
6178 | case 7: | |
6179 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6180 | break; | |
6181 | case 10: | |
6182 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6183 | break; | |
6184 | case 14: | |
6185 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6186 | break; | |
79e53945 JB |
6187 | } |
6188 | ||
43565a06 KH |
6189 | if (is_sdvo && is_tv) |
6190 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
6191 | else if (is_tv) | |
79e53945 | 6192 | /* XXX: just matching BIOS for now */ |
43565a06 | 6193 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 6194 | dpll |= 3; |
a7615030 | 6195 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 6196 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
6197 | else |
6198 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6199 | ||
6200 | /* setup pipeconf */ | |
5eddb70b | 6201 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
6202 | |
6203 | /* Set up the display plane register */ | |
6204 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
6205 | ||
f7cb34d4 | 6206 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
79e53945 JB |
6207 | drm_mode_debug_printmodeline(mode); |
6208 | ||
5c5313c8 | 6209 | /* PCH eDP needs FDI, but CPU eDP does not */ |
4b645f14 JB |
6210 | if (!intel_crtc->no_pll) { |
6211 | if (!has_edp_encoder || | |
6212 | intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
6213 | I915_WRITE(PCH_FP0(pipe), fp); | |
6214 | I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
6215 | ||
6216 | POSTING_READ(PCH_DPLL(pipe)); | |
6217 | udelay(150); | |
6218 | } | |
6219 | } else { | |
6220 | if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) && | |
6221 | fp == I915_READ(PCH_FP0(0))) { | |
6222 | intel_crtc->use_pll_a = true; | |
6223 | DRM_DEBUG_KMS("using pipe a dpll\n"); | |
6224 | } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) && | |
6225 | fp == I915_READ(PCH_FP0(1))) { | |
6226 | intel_crtc->use_pll_a = false; | |
6227 | DRM_DEBUG_KMS("using pipe b dpll\n"); | |
6228 | } else { | |
6229 | DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n"); | |
6230 | return -EINVAL; | |
6231 | } | |
79e53945 JB |
6232 | } |
6233 | ||
6234 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. | |
6235 | * This is an exception to the general rule that mode_set doesn't turn | |
6236 | * things on. | |
6237 | */ | |
6238 | if (is_lvds) { | |
fae14981 | 6239 | temp = I915_READ(PCH_LVDS); |
5eddb70b | 6240 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
7885d205 JB |
6241 | if (HAS_PCH_CPT(dev)) { |
6242 | temp &= ~PORT_TRANS_SEL_MASK; | |
4b645f14 | 6243 | temp |= PORT_TRANS_SEL_CPT(pipe); |
7885d205 JB |
6244 | } else { |
6245 | if (pipe == 1) | |
6246 | temp |= LVDS_PIPEB_SELECT; | |
6247 | else | |
6248 | temp &= ~LVDS_PIPEB_SELECT; | |
6249 | } | |
4b645f14 | 6250 | |
a3e17eb8 | 6251 | /* set the corresponsding LVDS_BORDER bit */ |
5eddb70b | 6252 | temp |= dev_priv->lvds_border_bits; |
79e53945 JB |
6253 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
6254 | * set the DPLLs for dual-channel mode or not. | |
6255 | */ | |
6256 | if (clock.p2 == 7) | |
5eddb70b | 6257 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
79e53945 | 6258 | else |
5eddb70b | 6259 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
79e53945 JB |
6260 | |
6261 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
6262 | * appropriately here, but we need to look more thoroughly into how | |
6263 | * panels behave in the two modes. | |
6264 | */ | |
aa9b500d BF |
6265 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
6266 | lvds_sync |= LVDS_HSYNC_POLARITY; | |
6267 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) | |
6268 | lvds_sync |= LVDS_VSYNC_POLARITY; | |
6269 | if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) | |
6270 | != lvds_sync) { | |
6271 | char flags[2] = "-+"; | |
6272 | DRM_INFO("Changing LVDS panel from " | |
6273 | "(%chsync, %cvsync) to (%chsync, %cvsync)\n", | |
6274 | flags[!(temp & LVDS_HSYNC_POLARITY)], | |
6275 | flags[!(temp & LVDS_VSYNC_POLARITY)], | |
6276 | flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], | |
6277 | flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); | |
6278 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
6279 | temp |= lvds_sync; | |
6280 | } | |
fae14981 | 6281 | I915_WRITE(PCH_LVDS, temp); |
79e53945 | 6282 | } |
434ed097 | 6283 | |
8febb297 EA |
6284 | pipeconf &= ~PIPECONF_DITHER_EN; |
6285 | pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; | |
5a354204 | 6286 | if ((is_lvds && dev_priv->lvds_dither) || dither) { |
8febb297 | 6287 | pipeconf |= PIPECONF_DITHER_EN; |
f74974c7 | 6288 | pipeconf |= PIPECONF_DITHER_TYPE_SP; |
434ed097 | 6289 | } |
5c5313c8 | 6290 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
a4fc5ed6 | 6291 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
8febb297 | 6292 | } else { |
8db9d77b | 6293 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
9db4a9c7 JB |
6294 | I915_WRITE(TRANSDATA_M1(pipe), 0); |
6295 | I915_WRITE(TRANSDATA_N1(pipe), 0); | |
6296 | I915_WRITE(TRANSDPLINK_M1(pipe), 0); | |
6297 | I915_WRITE(TRANSDPLINK_N1(pipe), 0); | |
8db9d77b | 6298 | } |
79e53945 | 6299 | |
4b645f14 JB |
6300 | if (!intel_crtc->no_pll && |
6301 | (!has_edp_encoder || | |
6302 | intel_encoder_is_pch_edp(&has_edp_encoder->base))) { | |
fae14981 | 6303 | I915_WRITE(PCH_DPLL(pipe), dpll); |
5eddb70b | 6304 | |
32f9d658 | 6305 | /* Wait for the clocks to stabilize. */ |
fae14981 | 6306 | POSTING_READ(PCH_DPLL(pipe)); |
32f9d658 ZW |
6307 | udelay(150); |
6308 | ||
8febb297 EA |
6309 | /* The pixel multiplier can only be updated once the |
6310 | * DPLL is enabled and the clocks are stable. | |
6311 | * | |
6312 | * So write it again. | |
6313 | */ | |
fae14981 | 6314 | I915_WRITE(PCH_DPLL(pipe), dpll); |
79e53945 | 6315 | } |
79e53945 | 6316 | |
5eddb70b | 6317 | intel_crtc->lowfreq_avail = false; |
4b645f14 JB |
6318 | if (!intel_crtc->no_pll) { |
6319 | if (is_lvds && has_reduced_clock && i915_powersave) { | |
6320 | I915_WRITE(PCH_FP1(pipe), fp2); | |
6321 | intel_crtc->lowfreq_avail = true; | |
6322 | if (HAS_PIPE_CXSR(dev)) { | |
6323 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
6324 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
6325 | } | |
6326 | } else { | |
6327 | I915_WRITE(PCH_FP1(pipe), fp); | |
6328 | if (HAS_PIPE_CXSR(dev)) { | |
6329 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
6330 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; | |
6331 | } | |
652c393a JB |
6332 | } |
6333 | } | |
6334 | ||
617cf884 | 6335 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
734b4157 | 6336 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5def474e | 6337 | pipeconf |= PIPECONF_INTERLACED_ILK; |
734b4157 | 6338 | /* the chip adds 2 halflines automatically */ |
734b4157 | 6339 | adjusted_mode->crtc_vtotal -= 1; |
734b4157 | 6340 | adjusted_mode->crtc_vblank_end -= 1; |
0529a0d9 DV |
6341 | I915_WRITE(VSYNCSHIFT(pipe), |
6342 | adjusted_mode->crtc_hsync_start | |
6343 | - adjusted_mode->crtc_htotal/2); | |
6344 | } else { | |
617cf884 | 6345 | pipeconf |= PIPECONF_PROGRESSIVE; |
0529a0d9 DV |
6346 | I915_WRITE(VSYNCSHIFT(pipe), 0); |
6347 | } | |
734b4157 | 6348 | |
5eddb70b CW |
6349 | I915_WRITE(HTOTAL(pipe), |
6350 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 6351 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
6352 | I915_WRITE(HBLANK(pipe), |
6353 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 6354 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
6355 | I915_WRITE(HSYNC(pipe), |
6356 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 6357 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
6358 | |
6359 | I915_WRITE(VTOTAL(pipe), | |
6360 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 6361 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
6362 | I915_WRITE(VBLANK(pipe), |
6363 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 6364 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
6365 | I915_WRITE(VSYNC(pipe), |
6366 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 6367 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b | 6368 | |
8febb297 EA |
6369 | /* pipesrc controls the size that is scaled from, which should |
6370 | * always be the user's requested size. | |
79e53945 | 6371 | */ |
5eddb70b CW |
6372 | I915_WRITE(PIPESRC(pipe), |
6373 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 6374 | |
8febb297 EA |
6375 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
6376 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); | |
6377 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); | |
6378 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); | |
2c07245f | 6379 | |
8febb297 EA |
6380 | if (has_edp_encoder && |
6381 | !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
6382 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); | |
2c07245f ZW |
6383 | } |
6384 | ||
5eddb70b CW |
6385 | I915_WRITE(PIPECONF(pipe), pipeconf); |
6386 | POSTING_READ(PIPECONF(pipe)); | |
79e53945 | 6387 | |
9d0498a2 | 6388 | intel_wait_for_vblank(dev, pipe); |
79e53945 | 6389 | |
5eddb70b | 6390 | I915_WRITE(DSPCNTR(plane), dspcntr); |
b24e7179 | 6391 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 6392 | |
5c3b82e2 | 6393 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
7662c8bd SL |
6394 | |
6395 | intel_update_watermarks(dev); | |
6396 | ||
1f803ee5 | 6397 | return ret; |
79e53945 JB |
6398 | } |
6399 | ||
f564048e EA |
6400 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
6401 | struct drm_display_mode *mode, | |
6402 | struct drm_display_mode *adjusted_mode, | |
6403 | int x, int y, | |
6404 | struct drm_framebuffer *old_fb) | |
6405 | { | |
6406 | struct drm_device *dev = crtc->dev; | |
6407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b701d27 EA |
6408 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6409 | int pipe = intel_crtc->pipe; | |
f564048e EA |
6410 | int ret; |
6411 | ||
0b701d27 | 6412 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 6413 | |
f564048e EA |
6414 | ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, |
6415 | x, y, old_fb); | |
79e53945 | 6416 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 6417 | |
d8e70a25 JB |
6418 | if (ret) |
6419 | intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; | |
6420 | else | |
6421 | intel_crtc->dpms_mode = DRM_MODE_DPMS_ON; | |
120eced9 | 6422 | |
1f803ee5 | 6423 | return ret; |
79e53945 JB |
6424 | } |
6425 | ||
3a9627f4 WF |
6426 | static bool intel_eld_uptodate(struct drm_connector *connector, |
6427 | int reg_eldv, uint32_t bits_eldv, | |
6428 | int reg_elda, uint32_t bits_elda, | |
6429 | int reg_edid) | |
6430 | { | |
6431 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6432 | uint8_t *eld = connector->eld; | |
6433 | uint32_t i; | |
6434 | ||
6435 | i = I915_READ(reg_eldv); | |
6436 | i &= bits_eldv; | |
6437 | ||
6438 | if (!eld[0]) | |
6439 | return !i; | |
6440 | ||
6441 | if (!i) | |
6442 | return false; | |
6443 | ||
6444 | i = I915_READ(reg_elda); | |
6445 | i &= ~bits_elda; | |
6446 | I915_WRITE(reg_elda, i); | |
6447 | ||
6448 | for (i = 0; i < eld[2]; i++) | |
6449 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
6450 | return false; | |
6451 | ||
6452 | return true; | |
6453 | } | |
6454 | ||
e0dac65e WF |
6455 | static void g4x_write_eld(struct drm_connector *connector, |
6456 | struct drm_crtc *crtc) | |
6457 | { | |
6458 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6459 | uint8_t *eld = connector->eld; | |
6460 | uint32_t eldv; | |
6461 | uint32_t len; | |
6462 | uint32_t i; | |
6463 | ||
6464 | i = I915_READ(G4X_AUD_VID_DID); | |
6465 | ||
6466 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
6467 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
6468 | else | |
6469 | eldv = G4X_ELDV_DEVCTG; | |
6470 | ||
3a9627f4 WF |
6471 | if (intel_eld_uptodate(connector, |
6472 | G4X_AUD_CNTL_ST, eldv, | |
6473 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
6474 | G4X_HDMIW_HDMIEDID)) | |
6475 | return; | |
6476 | ||
e0dac65e WF |
6477 | i = I915_READ(G4X_AUD_CNTL_ST); |
6478 | i &= ~(eldv | G4X_ELD_ADDR); | |
6479 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
6480 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
6481 | ||
6482 | if (!eld[0]) | |
6483 | return; | |
6484 | ||
6485 | len = min_t(uint8_t, eld[2], len); | |
6486 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6487 | for (i = 0; i < len; i++) | |
6488 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
6489 | ||
6490 | i = I915_READ(G4X_AUD_CNTL_ST); | |
6491 | i |= eldv; | |
6492 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
6493 | } | |
6494 | ||
6495 | static void ironlake_write_eld(struct drm_connector *connector, | |
6496 | struct drm_crtc *crtc) | |
6497 | { | |
6498 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6499 | uint8_t *eld = connector->eld; | |
6500 | uint32_t eldv; | |
6501 | uint32_t i; | |
6502 | int len; | |
6503 | int hdmiw_hdmiedid; | |
b6daa025 | 6504 | int aud_config; |
e0dac65e WF |
6505 | int aud_cntl_st; |
6506 | int aud_cntrl_st2; | |
6507 | ||
b3f33cbf | 6508 | if (HAS_PCH_IBX(connector->dev)) { |
1202b4c6 | 6509 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A; |
b6daa025 | 6510 | aud_config = IBX_AUD_CONFIG_A; |
1202b4c6 WF |
6511 | aud_cntl_st = IBX_AUD_CNTL_ST_A; |
6512 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; | |
e0dac65e | 6513 | } else { |
1202b4c6 | 6514 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A; |
b6daa025 | 6515 | aud_config = CPT_AUD_CONFIG_A; |
1202b4c6 WF |
6516 | aud_cntl_st = CPT_AUD_CNTL_ST_A; |
6517 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; | |
e0dac65e WF |
6518 | } |
6519 | ||
6520 | i = to_intel_crtc(crtc)->pipe; | |
6521 | hdmiw_hdmiedid += i * 0x100; | |
6522 | aud_cntl_st += i * 0x100; | |
b6daa025 | 6523 | aud_config += i * 0x100; |
e0dac65e WF |
6524 | |
6525 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i)); | |
6526 | ||
6527 | i = I915_READ(aud_cntl_st); | |
6528 | i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */ | |
6529 | if (!i) { | |
6530 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
6531 | /* operate blindly on all ports */ | |
1202b4c6 WF |
6532 | eldv = IBX_ELD_VALIDB; |
6533 | eldv |= IBX_ELD_VALIDB << 4; | |
6534 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e WF |
6535 | } else { |
6536 | DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); | |
1202b4c6 | 6537 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
6538 | } |
6539 | ||
3a9627f4 WF |
6540 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
6541 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
6542 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 WF |
6543 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
6544 | } else | |
6545 | I915_WRITE(aud_config, 0); | |
e0dac65e | 6546 | |
3a9627f4 WF |
6547 | if (intel_eld_uptodate(connector, |
6548 | aud_cntrl_st2, eldv, | |
6549 | aud_cntl_st, IBX_ELD_ADDRESS, | |
6550 | hdmiw_hdmiedid)) | |
6551 | return; | |
6552 | ||
e0dac65e WF |
6553 | i = I915_READ(aud_cntrl_st2); |
6554 | i &= ~eldv; | |
6555 | I915_WRITE(aud_cntrl_st2, i); | |
6556 | ||
6557 | if (!eld[0]) | |
6558 | return; | |
6559 | ||
e0dac65e | 6560 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 6561 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
6562 | I915_WRITE(aud_cntl_st, i); |
6563 | ||
6564 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
6565 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6566 | for (i = 0; i < len; i++) | |
6567 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
6568 | ||
6569 | i = I915_READ(aud_cntrl_st2); | |
6570 | i |= eldv; | |
6571 | I915_WRITE(aud_cntrl_st2, i); | |
6572 | } | |
6573 | ||
6574 | void intel_write_eld(struct drm_encoder *encoder, | |
6575 | struct drm_display_mode *mode) | |
6576 | { | |
6577 | struct drm_crtc *crtc = encoder->crtc; | |
6578 | struct drm_connector *connector; | |
6579 | struct drm_device *dev = encoder->dev; | |
6580 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6581 | ||
6582 | connector = drm_select_eld(encoder, mode); | |
6583 | if (!connector) | |
6584 | return; | |
6585 | ||
6586 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
6587 | connector->base.id, | |
6588 | drm_get_connector_name(connector), | |
6589 | connector->encoder->base.id, | |
6590 | drm_get_encoder_name(connector->encoder)); | |
6591 | ||
6592 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
6593 | ||
6594 | if (dev_priv->display.write_eld) | |
6595 | dev_priv->display.write_eld(connector, crtc); | |
6596 | } | |
6597 | ||
79e53945 JB |
6598 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
6599 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
6600 | { | |
6601 | struct drm_device *dev = crtc->dev; | |
6602 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6603 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9db4a9c7 | 6604 | int palreg = PALETTE(intel_crtc->pipe); |
79e53945 JB |
6605 | int i; |
6606 | ||
6607 | /* The clocks have to be on to load the palette. */ | |
aed3f09d | 6608 | if (!crtc->enabled || !intel_crtc->active) |
79e53945 JB |
6609 | return; |
6610 | ||
f2b115e6 | 6611 | /* use legacy palette for Ironlake */ |
bad720ff | 6612 | if (HAS_PCH_SPLIT(dev)) |
9db4a9c7 | 6613 | palreg = LGC_PALETTE(intel_crtc->pipe); |
2c07245f | 6614 | |
79e53945 JB |
6615 | for (i = 0; i < 256; i++) { |
6616 | I915_WRITE(palreg + 4 * i, | |
6617 | (intel_crtc->lut_r[i] << 16) | | |
6618 | (intel_crtc->lut_g[i] << 8) | | |
6619 | intel_crtc->lut_b[i]); | |
6620 | } | |
6621 | } | |
6622 | ||
560b85bb CW |
6623 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
6624 | { | |
6625 | struct drm_device *dev = crtc->dev; | |
6626 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6627 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6628 | bool visible = base != 0; | |
6629 | u32 cntl; | |
6630 | ||
6631 | if (intel_crtc->cursor_visible == visible) | |
6632 | return; | |
6633 | ||
9db4a9c7 | 6634 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
6635 | if (visible) { |
6636 | /* On these chipsets we can only modify the base whilst | |
6637 | * the cursor is disabled. | |
6638 | */ | |
9db4a9c7 | 6639 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
6640 | |
6641 | cntl &= ~(CURSOR_FORMAT_MASK); | |
6642 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
6643 | cntl |= CURSOR_ENABLE | | |
6644 | CURSOR_GAMMA_ENABLE | | |
6645 | CURSOR_FORMAT_ARGB; | |
6646 | } else | |
6647 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 6648 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
6649 | |
6650 | intel_crtc->cursor_visible = visible; | |
6651 | } | |
6652 | ||
6653 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
6654 | { | |
6655 | struct drm_device *dev = crtc->dev; | |
6656 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6657 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6658 | int pipe = intel_crtc->pipe; | |
6659 | bool visible = base != 0; | |
6660 | ||
6661 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 6662 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
6663 | if (base) { |
6664 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
6665 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6666 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
6667 | } else { | |
6668 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6669 | cntl |= CURSOR_MODE_DISABLE; | |
6670 | } | |
9db4a9c7 | 6671 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
6672 | |
6673 | intel_crtc->cursor_visible = visible; | |
6674 | } | |
6675 | /* and commit changes on next vblank */ | |
9db4a9c7 | 6676 | I915_WRITE(CURBASE(pipe), base); |
560b85bb CW |
6677 | } |
6678 | ||
65a21cd6 JB |
6679 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
6680 | { | |
6681 | struct drm_device *dev = crtc->dev; | |
6682 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6683 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6684 | int pipe = intel_crtc->pipe; | |
6685 | bool visible = base != 0; | |
6686 | ||
6687 | if (intel_crtc->cursor_visible != visible) { | |
6688 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
6689 | if (base) { | |
6690 | cntl &= ~CURSOR_MODE; | |
6691 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6692 | } else { | |
6693 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6694 | cntl |= CURSOR_MODE_DISABLE; | |
6695 | } | |
6696 | I915_WRITE(CURCNTR_IVB(pipe), cntl); | |
6697 | ||
6698 | intel_crtc->cursor_visible = visible; | |
6699 | } | |
6700 | /* and commit changes on next vblank */ | |
6701 | I915_WRITE(CURBASE_IVB(pipe), base); | |
6702 | } | |
6703 | ||
cda4b7d3 | 6704 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
6705 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
6706 | bool on) | |
cda4b7d3 CW |
6707 | { |
6708 | struct drm_device *dev = crtc->dev; | |
6709 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6710 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6711 | int pipe = intel_crtc->pipe; | |
6712 | int x = intel_crtc->cursor_x; | |
6713 | int y = intel_crtc->cursor_y; | |
560b85bb | 6714 | u32 base, pos; |
cda4b7d3 CW |
6715 | bool visible; |
6716 | ||
6717 | pos = 0; | |
6718 | ||
6b383a7f | 6719 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
6720 | base = intel_crtc->cursor_addr; |
6721 | if (x > (int) crtc->fb->width) | |
6722 | base = 0; | |
6723 | ||
6724 | if (y > (int) crtc->fb->height) | |
6725 | base = 0; | |
6726 | } else | |
6727 | base = 0; | |
6728 | ||
6729 | if (x < 0) { | |
6730 | if (x + intel_crtc->cursor_width < 0) | |
6731 | base = 0; | |
6732 | ||
6733 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
6734 | x = -x; | |
6735 | } | |
6736 | pos |= x << CURSOR_X_SHIFT; | |
6737 | ||
6738 | if (y < 0) { | |
6739 | if (y + intel_crtc->cursor_height < 0) | |
6740 | base = 0; | |
6741 | ||
6742 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
6743 | y = -y; | |
6744 | } | |
6745 | pos |= y << CURSOR_Y_SHIFT; | |
6746 | ||
6747 | visible = base != 0; | |
560b85bb | 6748 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
6749 | return; |
6750 | ||
65a21cd6 JB |
6751 | if (IS_IVYBRIDGE(dev)) { |
6752 | I915_WRITE(CURPOS_IVB(pipe), pos); | |
6753 | ivb_update_cursor(crtc, base); | |
6754 | } else { | |
6755 | I915_WRITE(CURPOS(pipe), pos); | |
6756 | if (IS_845G(dev) || IS_I865G(dev)) | |
6757 | i845_update_cursor(crtc, base); | |
6758 | else | |
6759 | i9xx_update_cursor(crtc, base); | |
6760 | } | |
cda4b7d3 CW |
6761 | |
6762 | if (visible) | |
6763 | intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); | |
6764 | } | |
6765 | ||
79e53945 | 6766 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 6767 | struct drm_file *file, |
79e53945 JB |
6768 | uint32_t handle, |
6769 | uint32_t width, uint32_t height) | |
6770 | { | |
6771 | struct drm_device *dev = crtc->dev; | |
6772 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6773 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 6774 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 6775 | uint32_t addr; |
3f8bc370 | 6776 | int ret; |
79e53945 | 6777 | |
28c97730 | 6778 | DRM_DEBUG_KMS("\n"); |
79e53945 JB |
6779 | |
6780 | /* if we want to turn off the cursor ignore width and height */ | |
6781 | if (!handle) { | |
28c97730 | 6782 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 6783 | addr = 0; |
05394f39 | 6784 | obj = NULL; |
5004417d | 6785 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 6786 | goto finish; |
79e53945 JB |
6787 | } |
6788 | ||
6789 | /* Currently we only support 64x64 cursors */ | |
6790 | if (width != 64 || height != 64) { | |
6791 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
6792 | return -EINVAL; | |
6793 | } | |
6794 | ||
05394f39 | 6795 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 6796 | if (&obj->base == NULL) |
79e53945 JB |
6797 | return -ENOENT; |
6798 | ||
05394f39 | 6799 | if (obj->base.size < width * height * 4) { |
79e53945 | 6800 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
6801 | ret = -ENOMEM; |
6802 | goto fail; | |
79e53945 JB |
6803 | } |
6804 | ||
71acb5eb | 6805 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 6806 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 6807 | if (!dev_priv->info->cursor_needs_physical) { |
d9e86c0e CW |
6808 | if (obj->tiling_mode) { |
6809 | DRM_ERROR("cursor cannot be tiled\n"); | |
6810 | ret = -EINVAL; | |
6811 | goto fail_locked; | |
6812 | } | |
6813 | ||
2da3b9b9 | 6814 | ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); |
e7b526bb CW |
6815 | if (ret) { |
6816 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 6817 | goto fail_locked; |
e7b526bb CW |
6818 | } |
6819 | ||
d9e86c0e CW |
6820 | ret = i915_gem_object_put_fence(obj); |
6821 | if (ret) { | |
2da3b9b9 | 6822 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
6823 | goto fail_unpin; |
6824 | } | |
6825 | ||
05394f39 | 6826 | addr = obj->gtt_offset; |
71acb5eb | 6827 | } else { |
6eeefaf3 | 6828 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 6829 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
6830 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
6831 | align); | |
71acb5eb DA |
6832 | if (ret) { |
6833 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 6834 | goto fail_locked; |
71acb5eb | 6835 | } |
05394f39 | 6836 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
6837 | } |
6838 | ||
a6c45cf0 | 6839 | if (IS_GEN2(dev)) |
14b60391 JB |
6840 | I915_WRITE(CURSIZE, (height << 12) | width); |
6841 | ||
3f8bc370 | 6842 | finish: |
3f8bc370 | 6843 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 6844 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 6845 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
6846 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
6847 | } else | |
6848 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
05394f39 | 6849 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 6850 | } |
80824003 | 6851 | |
7f9872e0 | 6852 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
6853 | |
6854 | intel_crtc->cursor_addr = addr; | |
05394f39 | 6855 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
6856 | intel_crtc->cursor_width = width; |
6857 | intel_crtc->cursor_height = height; | |
6858 | ||
6b383a7f | 6859 | intel_crtc_update_cursor(crtc, true); |
3f8bc370 | 6860 | |
79e53945 | 6861 | return 0; |
e7b526bb | 6862 | fail_unpin: |
05394f39 | 6863 | i915_gem_object_unpin(obj); |
7f9872e0 | 6864 | fail_locked: |
34b8686e | 6865 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 6866 | fail: |
05394f39 | 6867 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 6868 | return ret; |
79e53945 JB |
6869 | } |
6870 | ||
6871 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
6872 | { | |
79e53945 | 6873 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6874 | |
cda4b7d3 CW |
6875 | intel_crtc->cursor_x = x; |
6876 | intel_crtc->cursor_y = y; | |
652c393a | 6877 | |
6b383a7f | 6878 | intel_crtc_update_cursor(crtc, true); |
79e53945 JB |
6879 | |
6880 | return 0; | |
6881 | } | |
6882 | ||
6883 | /** Sets the color ramps on behalf of RandR */ | |
6884 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
6885 | u16 blue, int regno) | |
6886 | { | |
6887 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6888 | ||
6889 | intel_crtc->lut_r[regno] = red >> 8; | |
6890 | intel_crtc->lut_g[regno] = green >> 8; | |
6891 | intel_crtc->lut_b[regno] = blue >> 8; | |
6892 | } | |
6893 | ||
b8c00ac5 DA |
6894 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
6895 | u16 *blue, int regno) | |
6896 | { | |
6897 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6898 | ||
6899 | *red = intel_crtc->lut_r[regno] << 8; | |
6900 | *green = intel_crtc->lut_g[regno] << 8; | |
6901 | *blue = intel_crtc->lut_b[regno] << 8; | |
6902 | } | |
6903 | ||
79e53945 | 6904 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 6905 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 6906 | { |
7203425a | 6907 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 6908 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6909 | |
7203425a | 6910 | for (i = start; i < end; i++) { |
79e53945 JB |
6911 | intel_crtc->lut_r[i] = red[i] >> 8; |
6912 | intel_crtc->lut_g[i] = green[i] >> 8; | |
6913 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
6914 | } | |
6915 | ||
6916 | intel_crtc_load_lut(crtc); | |
6917 | } | |
6918 | ||
6919 | /** | |
6920 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
6921 | * detection. | |
6922 | * | |
6923 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
c751ce4f | 6924 | * its requirements. The pipe will be connected to no other encoders. |
79e53945 | 6925 | * |
c751ce4f | 6926 | * Currently this code will only succeed if there is a pipe with no encoders |
79e53945 JB |
6927 | * configured for it. In the future, it could choose to temporarily disable |
6928 | * some outputs to free up a pipe for its use. | |
6929 | * | |
6930 | * \return crtc, or NULL if no pipes are available. | |
6931 | */ | |
6932 | ||
6933 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
6934 | static struct drm_display_mode load_detect_mode = { | |
6935 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
6936 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
6937 | }; | |
6938 | ||
d2dff872 CW |
6939 | static struct drm_framebuffer * |
6940 | intel_framebuffer_create(struct drm_device *dev, | |
308e5bcb | 6941 | struct drm_mode_fb_cmd2 *mode_cmd, |
d2dff872 CW |
6942 | struct drm_i915_gem_object *obj) |
6943 | { | |
6944 | struct intel_framebuffer *intel_fb; | |
6945 | int ret; | |
6946 | ||
6947 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
6948 | if (!intel_fb) { | |
6949 | drm_gem_object_unreference_unlocked(&obj->base); | |
6950 | return ERR_PTR(-ENOMEM); | |
6951 | } | |
6952 | ||
6953 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
6954 | if (ret) { | |
6955 | drm_gem_object_unreference_unlocked(&obj->base); | |
6956 | kfree(intel_fb); | |
6957 | return ERR_PTR(ret); | |
6958 | } | |
6959 | ||
6960 | return &intel_fb->base; | |
6961 | } | |
6962 | ||
6963 | static u32 | |
6964 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
6965 | { | |
6966 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
6967 | return ALIGN(pitch, 64); | |
6968 | } | |
6969 | ||
6970 | static u32 | |
6971 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
6972 | { | |
6973 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
6974 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
6975 | } | |
6976 | ||
6977 | static struct drm_framebuffer * | |
6978 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
6979 | struct drm_display_mode *mode, | |
6980 | int depth, int bpp) | |
6981 | { | |
6982 | struct drm_i915_gem_object *obj; | |
308e5bcb | 6983 | struct drm_mode_fb_cmd2 mode_cmd; |
d2dff872 CW |
6984 | |
6985 | obj = i915_gem_alloc_object(dev, | |
6986 | intel_framebuffer_size_for_mode(mode, bpp)); | |
6987 | if (obj == NULL) | |
6988 | return ERR_PTR(-ENOMEM); | |
6989 | ||
6990 | mode_cmd.width = mode->hdisplay; | |
6991 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
6992 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
6993 | bpp); | |
5ca0c34a | 6994 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
6995 | |
6996 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
6997 | } | |
6998 | ||
6999 | static struct drm_framebuffer * | |
7000 | mode_fits_in_fbdev(struct drm_device *dev, | |
7001 | struct drm_display_mode *mode) | |
7002 | { | |
7003 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7004 | struct drm_i915_gem_object *obj; | |
7005 | struct drm_framebuffer *fb; | |
7006 | ||
7007 | if (dev_priv->fbdev == NULL) | |
7008 | return NULL; | |
7009 | ||
7010 | obj = dev_priv->fbdev->ifb.obj; | |
7011 | if (obj == NULL) | |
7012 | return NULL; | |
7013 | ||
7014 | fb = &dev_priv->fbdev->ifb.base; | |
01f2c773 VS |
7015 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
7016 | fb->bits_per_pixel)) | |
d2dff872 CW |
7017 | return NULL; |
7018 | ||
01f2c773 | 7019 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
7020 | return NULL; |
7021 | ||
7022 | return fb; | |
7023 | } | |
7024 | ||
7173188d CW |
7025 | bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
7026 | struct drm_connector *connector, | |
7027 | struct drm_display_mode *mode, | |
8261b191 | 7028 | struct intel_load_detect_pipe *old) |
79e53945 JB |
7029 | { |
7030 | struct intel_crtc *intel_crtc; | |
7031 | struct drm_crtc *possible_crtc; | |
4ef69c7a | 7032 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
7033 | struct drm_crtc *crtc = NULL; |
7034 | struct drm_device *dev = encoder->dev; | |
d2dff872 | 7035 | struct drm_framebuffer *old_fb; |
79e53945 JB |
7036 | int i = -1; |
7037 | ||
d2dff872 CW |
7038 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7039 | connector->base.id, drm_get_connector_name(connector), | |
7040 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7041 | ||
79e53945 JB |
7042 | /* |
7043 | * Algorithm gets a little messy: | |
7a5e4805 | 7044 | * |
79e53945 JB |
7045 | * - if the connector already has an assigned crtc, use it (but make |
7046 | * sure it's on first) | |
7a5e4805 | 7047 | * |
79e53945 JB |
7048 | * - try to find the first unused crtc that can drive this connector, |
7049 | * and use that if we find one | |
79e53945 JB |
7050 | */ |
7051 | ||
7052 | /* See if we already have a CRTC for this connector */ | |
7053 | if (encoder->crtc) { | |
7054 | crtc = encoder->crtc; | |
8261b191 | 7055 | |
79e53945 | 7056 | intel_crtc = to_intel_crtc(crtc); |
8261b191 CW |
7057 | old->dpms_mode = intel_crtc->dpms_mode; |
7058 | old->load_detect_temp = false; | |
7059 | ||
7060 | /* Make sure the crtc and connector are running */ | |
79e53945 | 7061 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { |
6492711d CW |
7062 | struct drm_encoder_helper_funcs *encoder_funcs; |
7063 | struct drm_crtc_helper_funcs *crtc_funcs; | |
7064 | ||
79e53945 JB |
7065 | crtc_funcs = crtc->helper_private; |
7066 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
6492711d CW |
7067 | |
7068 | encoder_funcs = encoder->helper_private; | |
79e53945 JB |
7069 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
7070 | } | |
8261b191 | 7071 | |
7173188d | 7072 | return true; |
79e53945 JB |
7073 | } |
7074 | ||
7075 | /* Find an unused one (if possible) */ | |
7076 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
7077 | i++; | |
7078 | if (!(encoder->possible_crtcs & (1 << i))) | |
7079 | continue; | |
7080 | if (!possible_crtc->enabled) { | |
7081 | crtc = possible_crtc; | |
7082 | break; | |
7083 | } | |
79e53945 JB |
7084 | } |
7085 | ||
7086 | /* | |
7087 | * If we didn't find an unused CRTC, don't use any. | |
7088 | */ | |
7089 | if (!crtc) { | |
7173188d CW |
7090 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
7091 | return false; | |
79e53945 JB |
7092 | } |
7093 | ||
7094 | encoder->crtc = crtc; | |
c1c43977 | 7095 | connector->encoder = encoder; |
79e53945 JB |
7096 | |
7097 | intel_crtc = to_intel_crtc(crtc); | |
8261b191 CW |
7098 | old->dpms_mode = intel_crtc->dpms_mode; |
7099 | old->load_detect_temp = true; | |
d2dff872 | 7100 | old->release_fb = NULL; |
79e53945 | 7101 | |
6492711d CW |
7102 | if (!mode) |
7103 | mode = &load_detect_mode; | |
79e53945 | 7104 | |
d2dff872 CW |
7105 | old_fb = crtc->fb; |
7106 | ||
7107 | /* We need a framebuffer large enough to accommodate all accesses | |
7108 | * that the plane may generate whilst we perform load detection. | |
7109 | * We can not rely on the fbcon either being present (we get called | |
7110 | * during its initialisation to detect all boot displays, or it may | |
7111 | * not even exist) or that it is large enough to satisfy the | |
7112 | * requested mode. | |
7113 | */ | |
7114 | crtc->fb = mode_fits_in_fbdev(dev, mode); | |
7115 | if (crtc->fb == NULL) { | |
7116 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); | |
7117 | crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); | |
7118 | old->release_fb = crtc->fb; | |
7119 | } else | |
7120 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
7121 | if (IS_ERR(crtc->fb)) { | |
7122 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); | |
7123 | crtc->fb = old_fb; | |
7124 | return false; | |
79e53945 | 7125 | } |
79e53945 | 7126 | |
d2dff872 | 7127 | if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) { |
6492711d | 7128 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
7129 | if (old->release_fb) |
7130 | old->release_fb->funcs->destroy(old->release_fb); | |
7131 | crtc->fb = old_fb; | |
6492711d | 7132 | return false; |
79e53945 | 7133 | } |
7173188d | 7134 | |
79e53945 | 7135 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 7136 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
79e53945 | 7137 | |
7173188d | 7138 | return true; |
79e53945 JB |
7139 | } |
7140 | ||
c1c43977 | 7141 | void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
8261b191 CW |
7142 | struct drm_connector *connector, |
7143 | struct intel_load_detect_pipe *old) | |
79e53945 | 7144 | { |
4ef69c7a | 7145 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
7146 | struct drm_device *dev = encoder->dev; |
7147 | struct drm_crtc *crtc = encoder->crtc; | |
7148 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
7149 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
7150 | ||
d2dff872 CW |
7151 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7152 | connector->base.id, drm_get_connector_name(connector), | |
7153 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7154 | ||
8261b191 | 7155 | if (old->load_detect_temp) { |
c1c43977 | 7156 | connector->encoder = NULL; |
79e53945 | 7157 | drm_helper_disable_unused_functions(dev); |
d2dff872 CW |
7158 | |
7159 | if (old->release_fb) | |
7160 | old->release_fb->funcs->destroy(old->release_fb); | |
7161 | ||
0622a53c | 7162 | return; |
79e53945 JB |
7163 | } |
7164 | ||
c751ce4f | 7165 | /* Switch crtc and encoder back off if necessary */ |
0622a53c CW |
7166 | if (old->dpms_mode != DRM_MODE_DPMS_ON) { |
7167 | encoder_funcs->dpms(encoder, old->dpms_mode); | |
8261b191 | 7168 | crtc_funcs->dpms(crtc, old->dpms_mode); |
79e53945 JB |
7169 | } |
7170 | } | |
7171 | ||
7172 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
7173 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
7174 | { | |
7175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7176 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7177 | int pipe = intel_crtc->pipe; | |
548f245b | 7178 | u32 dpll = I915_READ(DPLL(pipe)); |
79e53945 JB |
7179 | u32 fp; |
7180 | intel_clock_t clock; | |
7181 | ||
7182 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
39adb7a5 | 7183 | fp = I915_READ(FP0(pipe)); |
79e53945 | 7184 | else |
39adb7a5 | 7185 | fp = I915_READ(FP1(pipe)); |
79e53945 JB |
7186 | |
7187 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
7188 | if (IS_PINEVIEW(dev)) { |
7189 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
7190 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
7191 | } else { |
7192 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
7193 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
7194 | } | |
7195 | ||
a6c45cf0 | 7196 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
7197 | if (IS_PINEVIEW(dev)) |
7198 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
7199 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
7200 | else |
7201 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
7202 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
7203 | ||
7204 | switch (dpll & DPLL_MODE_MASK) { | |
7205 | case DPLLB_MODE_DAC_SERIAL: | |
7206 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
7207 | 5 : 10; | |
7208 | break; | |
7209 | case DPLLB_MODE_LVDS: | |
7210 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
7211 | 7 : 14; | |
7212 | break; | |
7213 | default: | |
28c97730 | 7214 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
7215 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
7216 | return 0; | |
7217 | } | |
7218 | ||
7219 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 7220 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
7221 | } else { |
7222 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
7223 | ||
7224 | if (is_lvds) { | |
7225 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
7226 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
7227 | clock.p2 = 14; | |
7228 | ||
7229 | if ((dpll & PLL_REF_INPUT_MASK) == | |
7230 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
7231 | /* XXX: might not be 66MHz */ | |
2177832f | 7232 | intel_clock(dev, 66000, &clock); |
79e53945 | 7233 | } else |
2177832f | 7234 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
7235 | } else { |
7236 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
7237 | clock.p1 = 2; | |
7238 | else { | |
7239 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
7240 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
7241 | } | |
7242 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
7243 | clock.p2 = 4; | |
7244 | else | |
7245 | clock.p2 = 2; | |
7246 | ||
2177832f | 7247 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
7248 | } |
7249 | } | |
7250 | ||
7251 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
7252 | * i830PllIsValid() because it relies on the xf86_config connector | |
7253 | * configuration being accurate, which it isn't necessarily. | |
7254 | */ | |
7255 | ||
7256 | return clock.dot; | |
7257 | } | |
7258 | ||
7259 | /** Returns the currently programmed mode of the given pipe. */ | |
7260 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
7261 | struct drm_crtc *crtc) | |
7262 | { | |
548f245b | 7263 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
7264 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7265 | int pipe = intel_crtc->pipe; | |
7266 | struct drm_display_mode *mode; | |
548f245b JB |
7267 | int htot = I915_READ(HTOTAL(pipe)); |
7268 | int hsync = I915_READ(HSYNC(pipe)); | |
7269 | int vtot = I915_READ(VTOTAL(pipe)); | |
7270 | int vsync = I915_READ(VSYNC(pipe)); | |
79e53945 JB |
7271 | |
7272 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
7273 | if (!mode) | |
7274 | return NULL; | |
7275 | ||
7276 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
7277 | mode->hdisplay = (htot & 0xffff) + 1; | |
7278 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
7279 | mode->hsync_start = (hsync & 0xffff) + 1; | |
7280 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
7281 | mode->vdisplay = (vtot & 0xffff) + 1; | |
7282 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
7283 | mode->vsync_start = (vsync & 0xffff) + 1; | |
7284 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
7285 | ||
7286 | drm_mode_set_name(mode); | |
7287 | drm_mode_set_crtcinfo(mode, 0); | |
7288 | ||
7289 | return mode; | |
7290 | } | |
7291 | ||
652c393a JB |
7292 | #define GPU_IDLE_TIMEOUT 500 /* ms */ |
7293 | ||
7294 | /* When this timer fires, we've been idle for awhile */ | |
7295 | static void intel_gpu_idle_timer(unsigned long arg) | |
7296 | { | |
7297 | struct drm_device *dev = (struct drm_device *)arg; | |
7298 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7299 | ||
ff7ea4c0 CW |
7300 | if (!list_empty(&dev_priv->mm.active_list)) { |
7301 | /* Still processing requests, so just re-arm the timer. */ | |
7302 | mod_timer(&dev_priv->idle_timer, jiffies + | |
7303 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
7304 | return; | |
7305 | } | |
652c393a | 7306 | |
ff7ea4c0 | 7307 | dev_priv->busy = false; |
01dfba93 | 7308 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
7309 | } |
7310 | ||
652c393a JB |
7311 | #define CRTC_IDLE_TIMEOUT 1000 /* ms */ |
7312 | ||
7313 | static void intel_crtc_idle_timer(unsigned long arg) | |
7314 | { | |
7315 | struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; | |
7316 | struct drm_crtc *crtc = &intel_crtc->base; | |
7317 | drm_i915_private_t *dev_priv = crtc->dev->dev_private; | |
ff7ea4c0 | 7318 | struct intel_framebuffer *intel_fb; |
652c393a | 7319 | |
ff7ea4c0 CW |
7320 | intel_fb = to_intel_framebuffer(crtc->fb); |
7321 | if (intel_fb && intel_fb->obj->active) { | |
7322 | /* The framebuffer is still being accessed by the GPU. */ | |
7323 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
7324 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
7325 | return; | |
7326 | } | |
652c393a | 7327 | |
ff7ea4c0 | 7328 | intel_crtc->busy = false; |
01dfba93 | 7329 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
7330 | } |
7331 | ||
3dec0095 | 7332 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
7333 | { |
7334 | struct drm_device *dev = crtc->dev; | |
7335 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7336 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7337 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
7338 | int dpll_reg = DPLL(pipe); |
7339 | int dpll; | |
652c393a | 7340 | |
bad720ff | 7341 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
7342 | return; |
7343 | ||
7344 | if (!dev_priv->lvds_downclock_avail) | |
7345 | return; | |
7346 | ||
dbdc6479 | 7347 | dpll = I915_READ(dpll_reg); |
652c393a | 7348 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 7349 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 7350 | |
8ac5a6d5 | 7351 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
7352 | |
7353 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
7354 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 7355 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 7356 | |
652c393a JB |
7357 | dpll = I915_READ(dpll_reg); |
7358 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 7359 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a JB |
7360 | } |
7361 | ||
7362 | /* Schedule downclock */ | |
3dec0095 DV |
7363 | mod_timer(&intel_crtc->idle_timer, jiffies + |
7364 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
652c393a JB |
7365 | } |
7366 | ||
7367 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
7368 | { | |
7369 | struct drm_device *dev = crtc->dev; | |
7370 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7371 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7372 | int pipe = intel_crtc->pipe; | |
9db4a9c7 | 7373 | int dpll_reg = DPLL(pipe); |
652c393a JB |
7374 | int dpll = I915_READ(dpll_reg); |
7375 | ||
bad720ff | 7376 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
7377 | return; |
7378 | ||
7379 | if (!dev_priv->lvds_downclock_avail) | |
7380 | return; | |
7381 | ||
7382 | /* | |
7383 | * Since this is called by a timer, we should never get here in | |
7384 | * the manual case. | |
7385 | */ | |
7386 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
44d98a61 | 7387 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 7388 | |
8ac5a6d5 | 7389 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
7390 | |
7391 | dpll |= DISPLAY_RATE_SELECT_FPA1; | |
7392 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 7393 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
7394 | dpll = I915_READ(dpll_reg); |
7395 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 7396 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
7397 | } |
7398 | ||
7399 | } | |
7400 | ||
7401 | /** | |
7402 | * intel_idle_update - adjust clocks for idleness | |
7403 | * @work: work struct | |
7404 | * | |
7405 | * Either the GPU or display (or both) went idle. Check the busy status | |
7406 | * here and adjust the CRTC and GPU clocks as necessary. | |
7407 | */ | |
7408 | static void intel_idle_update(struct work_struct *work) | |
7409 | { | |
7410 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
7411 | idle_work); | |
7412 | struct drm_device *dev = dev_priv->dev; | |
7413 | struct drm_crtc *crtc; | |
7414 | struct intel_crtc *intel_crtc; | |
7415 | ||
7416 | if (!i915_powersave) | |
7417 | return; | |
7418 | ||
7419 | mutex_lock(&dev->struct_mutex); | |
7420 | ||
7648fa99 JB |
7421 | i915_update_gfx_val(dev_priv); |
7422 | ||
652c393a JB |
7423 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
7424 | /* Skip inactive CRTCs */ | |
7425 | if (!crtc->fb) | |
7426 | continue; | |
7427 | ||
7428 | intel_crtc = to_intel_crtc(crtc); | |
7429 | if (!intel_crtc->busy) | |
7430 | intel_decrease_pllclock(crtc); | |
7431 | } | |
7432 | ||
45ac22c8 | 7433 | |
652c393a JB |
7434 | mutex_unlock(&dev->struct_mutex); |
7435 | } | |
7436 | ||
7437 | /** | |
7438 | * intel_mark_busy - mark the GPU and possibly the display busy | |
7439 | * @dev: drm device | |
7440 | * @obj: object we're operating on | |
7441 | * | |
7442 | * Callers can use this function to indicate that the GPU is busy processing | |
7443 | * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout | |
7444 | * buffer), we'll also mark the display as busy, so we know to increase its | |
7445 | * clock frequency. | |
7446 | */ | |
05394f39 | 7447 | void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj) |
652c393a JB |
7448 | { |
7449 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7450 | struct drm_crtc *crtc = NULL; | |
7451 | struct intel_framebuffer *intel_fb; | |
7452 | struct intel_crtc *intel_crtc; | |
7453 | ||
5e17ee74 ZW |
7454 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
7455 | return; | |
7456 | ||
18b2190c | 7457 | if (!dev_priv->busy) |
28cf798f | 7458 | dev_priv->busy = true; |
18b2190c | 7459 | else |
28cf798f CW |
7460 | mod_timer(&dev_priv->idle_timer, jiffies + |
7461 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
652c393a JB |
7462 | |
7463 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
7464 | if (!crtc->fb) | |
7465 | continue; | |
7466 | ||
7467 | intel_crtc = to_intel_crtc(crtc); | |
7468 | intel_fb = to_intel_framebuffer(crtc->fb); | |
7469 | if (intel_fb->obj == obj) { | |
7470 | if (!intel_crtc->busy) { | |
7471 | /* Non-busy -> busy, upclock */ | |
3dec0095 | 7472 | intel_increase_pllclock(crtc); |
652c393a JB |
7473 | intel_crtc->busy = true; |
7474 | } else { | |
7475 | /* Busy -> busy, put off timer */ | |
7476 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
7477 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
7478 | } | |
7479 | } | |
7480 | } | |
7481 | } | |
7482 | ||
79e53945 JB |
7483 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
7484 | { | |
7485 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
7486 | struct drm_device *dev = crtc->dev; |
7487 | struct intel_unpin_work *work; | |
7488 | unsigned long flags; | |
7489 | ||
7490 | spin_lock_irqsave(&dev->event_lock, flags); | |
7491 | work = intel_crtc->unpin_work; | |
7492 | intel_crtc->unpin_work = NULL; | |
7493 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7494 | ||
7495 | if (work) { | |
7496 | cancel_work_sync(&work->work); | |
7497 | kfree(work); | |
7498 | } | |
79e53945 JB |
7499 | |
7500 | drm_crtc_cleanup(crtc); | |
67e77c5a | 7501 | |
79e53945 JB |
7502 | kfree(intel_crtc); |
7503 | } | |
7504 | ||
6b95a207 KH |
7505 | static void intel_unpin_work_fn(struct work_struct *__work) |
7506 | { | |
7507 | struct intel_unpin_work *work = | |
7508 | container_of(__work, struct intel_unpin_work, work); | |
7509 | ||
7510 | mutex_lock(&work->dev->struct_mutex); | |
1690e1eb | 7511 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
7512 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
7513 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 7514 | |
7782de3b | 7515 | intel_update_fbc(work->dev); |
6b95a207 KH |
7516 | mutex_unlock(&work->dev->struct_mutex); |
7517 | kfree(work); | |
7518 | } | |
7519 | ||
1afe3e9d | 7520 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 7521 | struct drm_crtc *crtc) |
6b95a207 KH |
7522 | { |
7523 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
7524 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7525 | struct intel_unpin_work *work; | |
05394f39 | 7526 | struct drm_i915_gem_object *obj; |
6b95a207 | 7527 | struct drm_pending_vblank_event *e; |
49b14a5c | 7528 | struct timeval tnow, tvbl; |
6b95a207 KH |
7529 | unsigned long flags; |
7530 | ||
7531 | /* Ignore early vblank irqs */ | |
7532 | if (intel_crtc == NULL) | |
7533 | return; | |
7534 | ||
49b14a5c MK |
7535 | do_gettimeofday(&tnow); |
7536 | ||
6b95a207 KH |
7537 | spin_lock_irqsave(&dev->event_lock, flags); |
7538 | work = intel_crtc->unpin_work; | |
7539 | if (work == NULL || !work->pending) { | |
7540 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7541 | return; | |
7542 | } | |
7543 | ||
7544 | intel_crtc->unpin_work = NULL; | |
6b95a207 KH |
7545 | |
7546 | if (work->event) { | |
7547 | e = work->event; | |
49b14a5c | 7548 | e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl); |
0af7e4df MK |
7549 | |
7550 | /* Called before vblank count and timestamps have | |
7551 | * been updated for the vblank interval of flip | |
7552 | * completion? Need to increment vblank count and | |
7553 | * add one videorefresh duration to returned timestamp | |
49b14a5c MK |
7554 | * to account for this. We assume this happened if we |
7555 | * get called over 0.9 frame durations after the last | |
7556 | * timestamped vblank. | |
7557 | * | |
7558 | * This calculation can not be used with vrefresh rates | |
7559 | * below 5Hz (10Hz to be on the safe side) without | |
7560 | * promoting to 64 integers. | |
0af7e4df | 7561 | */ |
49b14a5c MK |
7562 | if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) > |
7563 | 9 * crtc->framedur_ns) { | |
0af7e4df | 7564 | e->event.sequence++; |
49b14a5c MK |
7565 | tvbl = ns_to_timeval(timeval_to_ns(&tvbl) + |
7566 | crtc->framedur_ns); | |
0af7e4df MK |
7567 | } |
7568 | ||
49b14a5c MK |
7569 | e->event.tv_sec = tvbl.tv_sec; |
7570 | e->event.tv_usec = tvbl.tv_usec; | |
0af7e4df | 7571 | |
6b95a207 KH |
7572 | list_add_tail(&e->base.link, |
7573 | &e->base.file_priv->event_list); | |
7574 | wake_up_interruptible(&e->base.file_priv->event_wait); | |
7575 | } | |
7576 | ||
0af7e4df MK |
7577 | drm_vblank_put(dev, intel_crtc->pipe); |
7578 | ||
6b95a207 KH |
7579 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7580 | ||
05394f39 | 7581 | obj = work->old_fb_obj; |
d9e86c0e | 7582 | |
e59f2bac | 7583 | atomic_clear_mask(1 << intel_crtc->plane, |
05394f39 CW |
7584 | &obj->pending_flip.counter); |
7585 | if (atomic_read(&obj->pending_flip) == 0) | |
f787a5f5 | 7586 | wake_up(&dev_priv->pending_flip_queue); |
d9e86c0e | 7587 | |
6b95a207 | 7588 | schedule_work(&work->work); |
e5510fac JB |
7589 | |
7590 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
7591 | } |
7592 | ||
1afe3e9d JB |
7593 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
7594 | { | |
7595 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7596 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
7597 | ||
49b14a5c | 7598 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
7599 | } |
7600 | ||
7601 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
7602 | { | |
7603 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7604 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
7605 | ||
49b14a5c | 7606 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
7607 | } |
7608 | ||
6b95a207 KH |
7609 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
7610 | { | |
7611 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7612 | struct intel_crtc *intel_crtc = | |
7613 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
7614 | unsigned long flags; | |
7615 | ||
7616 | spin_lock_irqsave(&dev->event_lock, flags); | |
de3f440f | 7617 | if (intel_crtc->unpin_work) { |
4e5359cd SF |
7618 | if ((++intel_crtc->unpin_work->pending) > 1) |
7619 | DRM_ERROR("Prepared flip multiple times\n"); | |
de3f440f JB |
7620 | } else { |
7621 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); | |
7622 | } | |
6b95a207 KH |
7623 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7624 | } | |
7625 | ||
8c9f3aaf JB |
7626 | static int intel_gen2_queue_flip(struct drm_device *dev, |
7627 | struct drm_crtc *crtc, | |
7628 | struct drm_framebuffer *fb, | |
7629 | struct drm_i915_gem_object *obj) | |
7630 | { | |
7631 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7632 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7633 | unsigned long offset; | |
7634 | u32 flip_mask; | |
7635 | int ret; | |
7636 | ||
7637 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
7638 | if (ret) | |
7639 | goto out; | |
7640 | ||
7641 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ | |
01f2c773 | 7642 | offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; |
8c9f3aaf JB |
7643 | |
7644 | ret = BEGIN_LP_RING(6); | |
7645 | if (ret) | |
7646 | goto out; | |
7647 | ||
7648 | /* Can't queue multiple flips, so wait for the previous | |
7649 | * one to finish before executing the next. | |
7650 | */ | |
7651 | if (intel_crtc->plane) | |
7652 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
7653 | else | |
7654 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
7655 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
7656 | OUT_RING(MI_NOOP); | |
7657 | OUT_RING(MI_DISPLAY_FLIP | | |
7658 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
01f2c773 | 7659 | OUT_RING(fb->pitches[0]); |
8c9f3aaf | 7660 | OUT_RING(obj->gtt_offset + offset); |
c6a32fcb | 7661 | OUT_RING(0); /* aux display base address, unused */ |
8c9f3aaf JB |
7662 | ADVANCE_LP_RING(); |
7663 | out: | |
7664 | return ret; | |
7665 | } | |
7666 | ||
7667 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
7668 | struct drm_crtc *crtc, | |
7669 | struct drm_framebuffer *fb, | |
7670 | struct drm_i915_gem_object *obj) | |
7671 | { | |
7672 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7673 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7674 | unsigned long offset; | |
7675 | u32 flip_mask; | |
7676 | int ret; | |
7677 | ||
7678 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
7679 | if (ret) | |
7680 | goto out; | |
7681 | ||
7682 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ | |
01f2c773 | 7683 | offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; |
8c9f3aaf JB |
7684 | |
7685 | ret = BEGIN_LP_RING(6); | |
7686 | if (ret) | |
7687 | goto out; | |
7688 | ||
7689 | if (intel_crtc->plane) | |
7690 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
7691 | else | |
7692 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
7693 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
7694 | OUT_RING(MI_NOOP); | |
7695 | OUT_RING(MI_DISPLAY_FLIP_I915 | | |
7696 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
01f2c773 | 7697 | OUT_RING(fb->pitches[0]); |
8c9f3aaf JB |
7698 | OUT_RING(obj->gtt_offset + offset); |
7699 | OUT_RING(MI_NOOP); | |
7700 | ||
7701 | ADVANCE_LP_RING(); | |
7702 | out: | |
7703 | return ret; | |
7704 | } | |
7705 | ||
7706 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
7707 | struct drm_crtc *crtc, | |
7708 | struct drm_framebuffer *fb, | |
7709 | struct drm_i915_gem_object *obj) | |
7710 | { | |
7711 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7712 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7713 | uint32_t pf, pipesrc; | |
7714 | int ret; | |
7715 | ||
7716 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
7717 | if (ret) | |
7718 | goto out; | |
7719 | ||
7720 | ret = BEGIN_LP_RING(4); | |
7721 | if (ret) | |
7722 | goto out; | |
7723 | ||
7724 | /* i965+ uses the linear or tiled offsets from the | |
7725 | * Display Registers (which do not change across a page-flip) | |
7726 | * so we need only reprogram the base address. | |
7727 | */ | |
7728 | OUT_RING(MI_DISPLAY_FLIP | | |
7729 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
01f2c773 | 7730 | OUT_RING(fb->pitches[0]); |
8c9f3aaf JB |
7731 | OUT_RING(obj->gtt_offset | obj->tiling_mode); |
7732 | ||
7733 | /* XXX Enabling the panel-fitter across page-flip is so far | |
7734 | * untested on non-native modes, so ignore it for now. | |
7735 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
7736 | */ | |
7737 | pf = 0; | |
7738 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
7739 | OUT_RING(pf | pipesrc); | |
7740 | ADVANCE_LP_RING(); | |
7741 | out: | |
7742 | return ret; | |
7743 | } | |
7744 | ||
7745 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
7746 | struct drm_crtc *crtc, | |
7747 | struct drm_framebuffer *fb, | |
7748 | struct drm_i915_gem_object *obj) | |
7749 | { | |
7750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7751 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7752 | uint32_t pf, pipesrc; | |
7753 | int ret; | |
7754 | ||
7755 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
7756 | if (ret) | |
7757 | goto out; | |
7758 | ||
7759 | ret = BEGIN_LP_RING(4); | |
7760 | if (ret) | |
7761 | goto out; | |
7762 | ||
7763 | OUT_RING(MI_DISPLAY_FLIP | | |
7764 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
01f2c773 | 7765 | OUT_RING(fb->pitches[0] | obj->tiling_mode); |
8c9f3aaf JB |
7766 | OUT_RING(obj->gtt_offset); |
7767 | ||
7768 | pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
7769 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
7770 | OUT_RING(pf | pipesrc); | |
7771 | ADVANCE_LP_RING(); | |
7772 | out: | |
7773 | return ret; | |
7774 | } | |
7775 | ||
7c9017e5 JB |
7776 | /* |
7777 | * On gen7 we currently use the blit ring because (in early silicon at least) | |
7778 | * the render ring doesn't give us interrpts for page flip completion, which | |
7779 | * means clients will hang after the first flip is queued. Fortunately the | |
7780 | * blit ring generates interrupts properly, so use it instead. | |
7781 | */ | |
7782 | static int intel_gen7_queue_flip(struct drm_device *dev, | |
7783 | struct drm_crtc *crtc, | |
7784 | struct drm_framebuffer *fb, | |
7785 | struct drm_i915_gem_object *obj) | |
7786 | { | |
7787 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7788 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7789 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; | |
7790 | int ret; | |
7791 | ||
7792 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
7793 | if (ret) | |
7794 | goto out; | |
7795 | ||
7796 | ret = intel_ring_begin(ring, 4); | |
7797 | if (ret) | |
7798 | goto out; | |
7799 | ||
7800 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19)); | |
01f2c773 | 7801 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
7c9017e5 JB |
7802 | intel_ring_emit(ring, (obj->gtt_offset)); |
7803 | intel_ring_emit(ring, (MI_NOOP)); | |
7804 | intel_ring_advance(ring); | |
7805 | out: | |
7806 | return ret; | |
7807 | } | |
7808 | ||
8c9f3aaf JB |
7809 | static int intel_default_queue_flip(struct drm_device *dev, |
7810 | struct drm_crtc *crtc, | |
7811 | struct drm_framebuffer *fb, | |
7812 | struct drm_i915_gem_object *obj) | |
7813 | { | |
7814 | return -ENODEV; | |
7815 | } | |
7816 | ||
6b95a207 KH |
7817 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
7818 | struct drm_framebuffer *fb, | |
7819 | struct drm_pending_vblank_event *event) | |
7820 | { | |
7821 | struct drm_device *dev = crtc->dev; | |
7822 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7823 | struct intel_framebuffer *intel_fb; | |
05394f39 | 7824 | struct drm_i915_gem_object *obj; |
6b95a207 KH |
7825 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7826 | struct intel_unpin_work *work; | |
8c9f3aaf | 7827 | unsigned long flags; |
52e68630 | 7828 | int ret; |
6b95a207 KH |
7829 | |
7830 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
7831 | if (work == NULL) | |
7832 | return -ENOMEM; | |
7833 | ||
6b95a207 KH |
7834 | work->event = event; |
7835 | work->dev = crtc->dev; | |
7836 | intel_fb = to_intel_framebuffer(crtc->fb); | |
b1b87f6b | 7837 | work->old_fb_obj = intel_fb->obj; |
6b95a207 KH |
7838 | INIT_WORK(&work->work, intel_unpin_work_fn); |
7839 | ||
7317c75e JB |
7840 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
7841 | if (ret) | |
7842 | goto free_work; | |
7843 | ||
6b95a207 KH |
7844 | /* We borrow the event spin lock for protecting unpin_work */ |
7845 | spin_lock_irqsave(&dev->event_lock, flags); | |
7846 | if (intel_crtc->unpin_work) { | |
7847 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7848 | kfree(work); | |
7317c75e | 7849 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
7850 | |
7851 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
7852 | return -EBUSY; |
7853 | } | |
7854 | intel_crtc->unpin_work = work; | |
7855 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7856 | ||
7857 | intel_fb = to_intel_framebuffer(fb); | |
7858 | obj = intel_fb->obj; | |
7859 | ||
468f0b44 | 7860 | mutex_lock(&dev->struct_mutex); |
6b95a207 | 7861 | |
75dfca80 | 7862 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
7863 | drm_gem_object_reference(&work->old_fb_obj->base); |
7864 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
7865 | |
7866 | crtc->fb = fb; | |
96b099fd | 7867 | |
e1f99ce6 | 7868 | work->pending_flip_obj = obj; |
e1f99ce6 | 7869 | |
4e5359cd SF |
7870 | work->enable_stall_check = true; |
7871 | ||
e1f99ce6 CW |
7872 | /* Block clients from rendering to the new back buffer until |
7873 | * the flip occurs and the object is no longer visible. | |
7874 | */ | |
05394f39 | 7875 | atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
e1f99ce6 | 7876 | |
8c9f3aaf JB |
7877 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); |
7878 | if (ret) | |
7879 | goto cleanup_pending; | |
6b95a207 | 7880 | |
7782de3b | 7881 | intel_disable_fbc(dev); |
6b95a207 KH |
7882 | mutex_unlock(&dev->struct_mutex); |
7883 | ||
e5510fac JB |
7884 | trace_i915_flip_request(intel_crtc->plane, obj); |
7885 | ||
6b95a207 | 7886 | return 0; |
96b099fd | 7887 | |
8c9f3aaf JB |
7888 | cleanup_pending: |
7889 | atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); | |
05394f39 CW |
7890 | drm_gem_object_unreference(&work->old_fb_obj->base); |
7891 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
7892 | mutex_unlock(&dev->struct_mutex); |
7893 | ||
7894 | spin_lock_irqsave(&dev->event_lock, flags); | |
7895 | intel_crtc->unpin_work = NULL; | |
7896 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7897 | ||
7317c75e JB |
7898 | drm_vblank_put(dev, intel_crtc->pipe); |
7899 | free_work: | |
96b099fd CW |
7900 | kfree(work); |
7901 | ||
7902 | return ret; | |
6b95a207 KH |
7903 | } |
7904 | ||
47f1c6c9 CW |
7905 | static void intel_sanitize_modesetting(struct drm_device *dev, |
7906 | int pipe, int plane) | |
7907 | { | |
7908 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7909 | u32 reg, val; | |
7910 | ||
f47166d2 CW |
7911 | /* Clear any frame start delays used for debugging left by the BIOS */ |
7912 | for_each_pipe(pipe) { | |
7913 | reg = PIPECONF(pipe); | |
7914 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
7915 | } | |
7916 | ||
47f1c6c9 CW |
7917 | if (HAS_PCH_SPLIT(dev)) |
7918 | return; | |
7919 | ||
7920 | /* Who knows what state these registers were left in by the BIOS or | |
7921 | * grub? | |
7922 | * | |
7923 | * If we leave the registers in a conflicting state (e.g. with the | |
7924 | * display plane reading from the other pipe than the one we intend | |
7925 | * to use) then when we attempt to teardown the active mode, we will | |
7926 | * not disable the pipes and planes in the correct order -- leaving | |
7927 | * a plane reading from a disabled pipe and possibly leading to | |
7928 | * undefined behaviour. | |
7929 | */ | |
7930 | ||
7931 | reg = DSPCNTR(plane); | |
7932 | val = I915_READ(reg); | |
7933 | ||
7934 | if ((val & DISPLAY_PLANE_ENABLE) == 0) | |
7935 | return; | |
7936 | if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe) | |
7937 | return; | |
7938 | ||
7939 | /* This display plane is active and attached to the other CPU pipe. */ | |
7940 | pipe = !pipe; | |
7941 | ||
7942 | /* Disable the plane and wait for it to stop reading from the pipe. */ | |
b24e7179 JB |
7943 | intel_disable_plane(dev_priv, plane, pipe); |
7944 | intel_disable_pipe(dev_priv, pipe); | |
47f1c6c9 | 7945 | } |
79e53945 | 7946 | |
f6e5b160 CW |
7947 | static void intel_crtc_reset(struct drm_crtc *crtc) |
7948 | { | |
7949 | struct drm_device *dev = crtc->dev; | |
7950 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7951 | ||
7952 | /* Reset flags back to the 'unknown' status so that they | |
7953 | * will be correctly set on the initial modeset. | |
7954 | */ | |
7955 | intel_crtc->dpms_mode = -1; | |
7956 | ||
7957 | /* We need to fix up any BIOS configuration that conflicts with | |
7958 | * our expectations. | |
7959 | */ | |
7960 | intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane); | |
7961 | } | |
7962 | ||
7963 | static struct drm_crtc_helper_funcs intel_helper_funcs = { | |
7964 | .dpms = intel_crtc_dpms, | |
7965 | .mode_fixup = intel_crtc_mode_fixup, | |
7966 | .mode_set = intel_crtc_mode_set, | |
7967 | .mode_set_base = intel_pipe_set_base, | |
7968 | .mode_set_base_atomic = intel_pipe_set_base_atomic, | |
7969 | .load_lut = intel_crtc_load_lut, | |
7970 | .disable = intel_crtc_disable, | |
7971 | }; | |
7972 | ||
7973 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
7974 | .reset = intel_crtc_reset, | |
7975 | .cursor_set = intel_crtc_cursor_set, | |
7976 | .cursor_move = intel_crtc_cursor_move, | |
7977 | .gamma_set = intel_crtc_gamma_set, | |
7978 | .set_config = drm_crtc_helper_set_config, | |
7979 | .destroy = intel_crtc_destroy, | |
7980 | .page_flip = intel_crtc_page_flip, | |
7981 | }; | |
7982 | ||
b358d0a6 | 7983 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 7984 | { |
22fd0fab | 7985 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
7986 | struct intel_crtc *intel_crtc; |
7987 | int i; | |
7988 | ||
7989 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
7990 | if (intel_crtc == NULL) | |
7991 | return; | |
7992 | ||
7993 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
7994 | ||
7995 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
7996 | for (i = 0; i < 256; i++) { |
7997 | intel_crtc->lut_r[i] = i; | |
7998 | intel_crtc->lut_g[i] = i; | |
7999 | intel_crtc->lut_b[i] = i; | |
8000 | } | |
8001 | ||
80824003 JB |
8002 | /* Swap pipes & planes for FBC on pre-965 */ |
8003 | intel_crtc->pipe = pipe; | |
8004 | intel_crtc->plane = pipe; | |
e2e767ab | 8005 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 8006 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 8007 | intel_crtc->plane = !pipe; |
80824003 JB |
8008 | } |
8009 | ||
22fd0fab JB |
8010 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
8011 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
8012 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
8013 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
8014 | ||
5d1d0cc8 | 8015 | intel_crtc_reset(&intel_crtc->base); |
04dbff52 | 8016 | intel_crtc->active = true; /* force the pipe off on setup_init_config */ |
5a354204 | 8017 | intel_crtc->bpp = 24; /* default for pre-Ironlake */ |
7e7d76c3 JB |
8018 | |
8019 | if (HAS_PCH_SPLIT(dev)) { | |
4b645f14 JB |
8020 | if (pipe == 2 && IS_IVYBRIDGE(dev)) |
8021 | intel_crtc->no_pll = true; | |
7e7d76c3 JB |
8022 | intel_helper_funcs.prepare = ironlake_crtc_prepare; |
8023 | intel_helper_funcs.commit = ironlake_crtc_commit; | |
8024 | } else { | |
8025 | intel_helper_funcs.prepare = i9xx_crtc_prepare; | |
8026 | intel_helper_funcs.commit = i9xx_crtc_commit; | |
8027 | } | |
8028 | ||
79e53945 JB |
8029 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
8030 | ||
652c393a JB |
8031 | intel_crtc->busy = false; |
8032 | ||
8033 | setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, | |
8034 | (unsigned long)intel_crtc); | |
79e53945 JB |
8035 | } |
8036 | ||
08d7b3d1 | 8037 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 8038 | struct drm_file *file) |
08d7b3d1 CW |
8039 | { |
8040 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8041 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; | |
c05422d5 DV |
8042 | struct drm_mode_object *drmmode_obj; |
8043 | struct intel_crtc *crtc; | |
08d7b3d1 CW |
8044 | |
8045 | if (!dev_priv) { | |
8046 | DRM_ERROR("called with no initialization\n"); | |
8047 | return -EINVAL; | |
8048 | } | |
8049 | ||
c05422d5 DV |
8050 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
8051 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 8052 | |
c05422d5 | 8053 | if (!drmmode_obj) { |
08d7b3d1 CW |
8054 | DRM_ERROR("no such CRTC id\n"); |
8055 | return -EINVAL; | |
8056 | } | |
8057 | ||
c05422d5 DV |
8058 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
8059 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 8060 | |
c05422d5 | 8061 | return 0; |
08d7b3d1 CW |
8062 | } |
8063 | ||
c5e4df33 | 8064 | static int intel_encoder_clones(struct drm_device *dev, int type_mask) |
79e53945 | 8065 | { |
4ef69c7a | 8066 | struct intel_encoder *encoder; |
79e53945 | 8067 | int index_mask = 0; |
79e53945 JB |
8068 | int entry = 0; |
8069 | ||
4ef69c7a CW |
8070 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
8071 | if (type_mask & encoder->clone_mask) | |
79e53945 JB |
8072 | index_mask |= (1 << entry); |
8073 | entry++; | |
8074 | } | |
4ef69c7a | 8075 | |
79e53945 JB |
8076 | return index_mask; |
8077 | } | |
8078 | ||
4d302442 CW |
8079 | static bool has_edp_a(struct drm_device *dev) |
8080 | { | |
8081 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8082 | ||
8083 | if (!IS_MOBILE(dev)) | |
8084 | return false; | |
8085 | ||
8086 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
8087 | return false; | |
8088 | ||
8089 | if (IS_GEN5(dev) && | |
8090 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
8091 | return false; | |
8092 | ||
8093 | return true; | |
8094 | } | |
8095 | ||
79e53945 JB |
8096 | static void intel_setup_outputs(struct drm_device *dev) |
8097 | { | |
725e30ad | 8098 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 8099 | struct intel_encoder *encoder; |
cb0953d7 | 8100 | bool dpd_is_edp = false; |
f3cfcba6 | 8101 | bool has_lvds; |
79e53945 | 8102 | |
f3cfcba6 | 8103 | has_lvds = intel_lvds_init(dev); |
c5d1b51d CW |
8104 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { |
8105 | /* disable the panel fitter on everything but LVDS */ | |
8106 | I915_WRITE(PFIT_CONTROL, 0); | |
8107 | } | |
79e53945 | 8108 | |
bad720ff | 8109 | if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 8110 | dpd_is_edp = intel_dpd_is_edp(dev); |
30ad48b7 | 8111 | |
4d302442 | 8112 | if (has_edp_a(dev)) |
32f9d658 ZW |
8113 | intel_dp_init(dev, DP_A); |
8114 | ||
cb0953d7 AJ |
8115 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
8116 | intel_dp_init(dev, PCH_DP_D); | |
8117 | } | |
8118 | ||
8119 | intel_crt_init(dev); | |
8120 | ||
8121 | if (HAS_PCH_SPLIT(dev)) { | |
8122 | int found; | |
8123 | ||
30ad48b7 | 8124 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
461ed3ca | 8125 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 8126 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 ZW |
8127 | if (!found) |
8128 | intel_hdmi_init(dev, HDMIB); | |
5eb08b69 ZW |
8129 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
8130 | intel_dp_init(dev, PCH_DP_B); | |
30ad48b7 ZW |
8131 | } |
8132 | ||
8133 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
8134 | intel_hdmi_init(dev, HDMIC); | |
8135 | ||
8136 | if (I915_READ(HDMID) & PORT_DETECTED) | |
8137 | intel_hdmi_init(dev, HDMID); | |
8138 | ||
5eb08b69 ZW |
8139 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
8140 | intel_dp_init(dev, PCH_DP_C); | |
8141 | ||
cb0953d7 | 8142 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5eb08b69 ZW |
8143 | intel_dp_init(dev, PCH_DP_D); |
8144 | ||
103a196f | 8145 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 8146 | bool found = false; |
7d57382e | 8147 | |
725e30ad | 8148 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 8149 | DRM_DEBUG_KMS("probing SDVOB\n"); |
eef4eacb | 8150 | found = intel_sdvo_init(dev, SDVOB, true); |
b01f2c3a JB |
8151 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
8152 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
725e30ad | 8153 | intel_hdmi_init(dev, SDVOB); |
b01f2c3a | 8154 | } |
27185ae1 | 8155 | |
b01f2c3a JB |
8156 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
8157 | DRM_DEBUG_KMS("probing DP_B\n"); | |
a4fc5ed6 | 8158 | intel_dp_init(dev, DP_B); |
b01f2c3a | 8159 | } |
725e30ad | 8160 | } |
13520b05 KH |
8161 | |
8162 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 8163 | |
b01f2c3a JB |
8164 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
8165 | DRM_DEBUG_KMS("probing SDVOC\n"); | |
eef4eacb | 8166 | found = intel_sdvo_init(dev, SDVOC, false); |
b01f2c3a | 8167 | } |
27185ae1 ML |
8168 | |
8169 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { | |
8170 | ||
b01f2c3a JB |
8171 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
8172 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
725e30ad | 8173 | intel_hdmi_init(dev, SDVOC); |
b01f2c3a JB |
8174 | } |
8175 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
8176 | DRM_DEBUG_KMS("probing DP_C\n"); | |
a4fc5ed6 | 8177 | intel_dp_init(dev, DP_C); |
b01f2c3a | 8178 | } |
725e30ad | 8179 | } |
27185ae1 | 8180 | |
b01f2c3a JB |
8181 | if (SUPPORTS_INTEGRATED_DP(dev) && |
8182 | (I915_READ(DP_D) & DP_DETECTED)) { | |
8183 | DRM_DEBUG_KMS("probing DP_D\n"); | |
a4fc5ed6 | 8184 | intel_dp_init(dev, DP_D); |
b01f2c3a | 8185 | } |
bad720ff | 8186 | } else if (IS_GEN2(dev)) |
79e53945 JB |
8187 | intel_dvo_init(dev); |
8188 | ||
103a196f | 8189 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
8190 | intel_tv_init(dev); |
8191 | ||
4ef69c7a CW |
8192 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
8193 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
8194 | encoder->base.possible_clones = | |
8195 | intel_encoder_clones(dev, encoder->clone_mask); | |
79e53945 | 8196 | } |
47356eb6 | 8197 | |
2c7111db CW |
8198 | /* disable all the possible outputs/crtcs before entering KMS mode */ |
8199 | drm_helper_disable_unused_functions(dev); | |
9fb526db KP |
8200 | |
8201 | if (HAS_PCH_SPLIT(dev)) | |
8202 | ironlake_init_pch_refclk(dev); | |
79e53945 JB |
8203 | } |
8204 | ||
8205 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
8206 | { | |
8207 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
8208 | |
8209 | drm_framebuffer_cleanup(fb); | |
05394f39 | 8210 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
79e53945 JB |
8211 | |
8212 | kfree(intel_fb); | |
8213 | } | |
8214 | ||
8215 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 8216 | struct drm_file *file, |
79e53945 JB |
8217 | unsigned int *handle) |
8218 | { | |
8219 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 8220 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 8221 | |
05394f39 | 8222 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
8223 | } |
8224 | ||
8225 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
8226 | .destroy = intel_user_framebuffer_destroy, | |
8227 | .create_handle = intel_user_framebuffer_create_handle, | |
8228 | }; | |
8229 | ||
38651674 DA |
8230 | int intel_framebuffer_init(struct drm_device *dev, |
8231 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 8232 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 8233 | struct drm_i915_gem_object *obj) |
79e53945 | 8234 | { |
79e53945 JB |
8235 | int ret; |
8236 | ||
05394f39 | 8237 | if (obj->tiling_mode == I915_TILING_Y) |
57cd6508 CW |
8238 | return -EINVAL; |
8239 | ||
308e5bcb | 8240 | if (mode_cmd->pitches[0] & 63) |
57cd6508 CW |
8241 | return -EINVAL; |
8242 | ||
308e5bcb | 8243 | switch (mode_cmd->pixel_format) { |
04b3924d VS |
8244 | case DRM_FORMAT_RGB332: |
8245 | case DRM_FORMAT_RGB565: | |
8246 | case DRM_FORMAT_XRGB8888: | |
b250da79 | 8247 | case DRM_FORMAT_XBGR8888: |
04b3924d VS |
8248 | case DRM_FORMAT_ARGB8888: |
8249 | case DRM_FORMAT_XRGB2101010: | |
8250 | case DRM_FORMAT_ARGB2101010: | |
308e5bcb | 8251 | /* RGB formats are common across chipsets */ |
b5626747 | 8252 | break; |
04b3924d VS |
8253 | case DRM_FORMAT_YUYV: |
8254 | case DRM_FORMAT_UYVY: | |
8255 | case DRM_FORMAT_YVYU: | |
8256 | case DRM_FORMAT_VYUY: | |
57cd6508 CW |
8257 | break; |
8258 | default: | |
aca25848 ED |
8259 | DRM_DEBUG_KMS("unsupported pixel format %u\n", |
8260 | mode_cmd->pixel_format); | |
57cd6508 CW |
8261 | return -EINVAL; |
8262 | } | |
8263 | ||
79e53945 JB |
8264 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
8265 | if (ret) { | |
8266 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
8267 | return ret; | |
8268 | } | |
8269 | ||
8270 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
79e53945 | 8271 | intel_fb->obj = obj; |
79e53945 JB |
8272 | return 0; |
8273 | } | |
8274 | ||
79e53945 JB |
8275 | static struct drm_framebuffer * |
8276 | intel_user_framebuffer_create(struct drm_device *dev, | |
8277 | struct drm_file *filp, | |
308e5bcb | 8278 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 8279 | { |
05394f39 | 8280 | struct drm_i915_gem_object *obj; |
79e53945 | 8281 | |
308e5bcb JB |
8282 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
8283 | mode_cmd->handles[0])); | |
c8725226 | 8284 | if (&obj->base == NULL) |
cce13ff7 | 8285 | return ERR_PTR(-ENOENT); |
79e53945 | 8286 | |
d2dff872 | 8287 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
8288 | } |
8289 | ||
79e53945 | 8290 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 8291 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 8292 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
8293 | }; |
8294 | ||
05394f39 | 8295 | static struct drm_i915_gem_object * |
aa40d6bb | 8296 | intel_alloc_context_page(struct drm_device *dev) |
9ea8d059 | 8297 | { |
05394f39 | 8298 | struct drm_i915_gem_object *ctx; |
9ea8d059 CW |
8299 | int ret; |
8300 | ||
2c34b850 BW |
8301 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
8302 | ||
aa40d6bb ZN |
8303 | ctx = i915_gem_alloc_object(dev, 4096); |
8304 | if (!ctx) { | |
9ea8d059 CW |
8305 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
8306 | return NULL; | |
8307 | } | |
8308 | ||
75e9e915 | 8309 | ret = i915_gem_object_pin(ctx, 4096, true); |
9ea8d059 CW |
8310 | if (ret) { |
8311 | DRM_ERROR("failed to pin power context: %d\n", ret); | |
8312 | goto err_unref; | |
8313 | } | |
8314 | ||
aa40d6bb | 8315 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
9ea8d059 CW |
8316 | if (ret) { |
8317 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); | |
8318 | goto err_unpin; | |
8319 | } | |
9ea8d059 | 8320 | |
aa40d6bb | 8321 | return ctx; |
9ea8d059 CW |
8322 | |
8323 | err_unpin: | |
aa40d6bb | 8324 | i915_gem_object_unpin(ctx); |
9ea8d059 | 8325 | err_unref: |
05394f39 | 8326 | drm_gem_object_unreference(&ctx->base); |
9ea8d059 CW |
8327 | mutex_unlock(&dev->struct_mutex); |
8328 | return NULL; | |
8329 | } | |
8330 | ||
7648fa99 JB |
8331 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
8332 | { | |
8333 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8334 | u16 rgvswctl; | |
8335 | ||
8336 | rgvswctl = I915_READ16(MEMSWCTL); | |
8337 | if (rgvswctl & MEMCTL_CMD_STS) { | |
8338 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
8339 | return false; /* still busy with another command */ | |
8340 | } | |
8341 | ||
8342 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
8343 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
8344 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
8345 | POSTING_READ16(MEMSWCTL); | |
8346 | ||
8347 | rgvswctl |= MEMCTL_CMD_STS; | |
8348 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
8349 | ||
8350 | return true; | |
8351 | } | |
8352 | ||
f97108d1 JB |
8353 | void ironlake_enable_drps(struct drm_device *dev) |
8354 | { | |
8355 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 8356 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
f97108d1 | 8357 | u8 fmax, fmin, fstart, vstart; |
f97108d1 | 8358 | |
ea056c14 JB |
8359 | /* Enable temp reporting */ |
8360 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
8361 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
8362 | ||
f97108d1 JB |
8363 | /* 100ms RC evaluation intervals */ |
8364 | I915_WRITE(RCUPEI, 100000); | |
8365 | I915_WRITE(RCDNEI, 100000); | |
8366 | ||
8367 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
8368 | I915_WRITE(RCBMAXAVG, 90000); | |
8369 | I915_WRITE(RCBMINAVG, 80000); | |
8370 | ||
8371 | I915_WRITE(MEMIHYST, 1); | |
8372 | ||
8373 | /* Set up min, max, and cur for interrupt handling */ | |
8374 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
8375 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
8376 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
8377 | MEMMODE_FSTART_SHIFT; | |
7648fa99 | 8378 | |
f97108d1 JB |
8379 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
8380 | PXVFREQ_PX_SHIFT; | |
8381 | ||
80dbf4b7 | 8382 | dev_priv->fmax = fmax; /* IPS callback will increase this */ |
7648fa99 JB |
8383 | dev_priv->fstart = fstart; |
8384 | ||
80dbf4b7 | 8385 | dev_priv->max_delay = fstart; |
f97108d1 JB |
8386 | dev_priv->min_delay = fmin; |
8387 | dev_priv->cur_delay = fstart; | |
8388 | ||
80dbf4b7 JB |
8389 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
8390 | fmax, fmin, fstart); | |
7648fa99 | 8391 | |
f97108d1 JB |
8392 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
8393 | ||
8394 | /* | |
8395 | * Interrupts will be enabled in ironlake_irq_postinstall | |
8396 | */ | |
8397 | ||
8398 | I915_WRITE(VIDSTART, vstart); | |
8399 | POSTING_READ(VIDSTART); | |
8400 | ||
8401 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
8402 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
8403 | ||
481b6af3 | 8404 | if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
913d8d11 | 8405 | DRM_ERROR("stuck trying to change perf mode\n"); |
f97108d1 JB |
8406 | msleep(1); |
8407 | ||
7648fa99 | 8408 | ironlake_set_drps(dev, fstart); |
f97108d1 | 8409 | |
7648fa99 JB |
8410 | dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
8411 | I915_READ(0x112e0); | |
8412 | dev_priv->last_time1 = jiffies_to_msecs(jiffies); | |
8413 | dev_priv->last_count2 = I915_READ(0x112f4); | |
8414 | getrawmonotonic(&dev_priv->last_time2); | |
f97108d1 JB |
8415 | } |
8416 | ||
8417 | void ironlake_disable_drps(struct drm_device *dev) | |
8418 | { | |
8419 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 8420 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
f97108d1 JB |
8421 | |
8422 | /* Ack interrupts, disable EFC interrupt */ | |
8423 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
8424 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
8425 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
8426 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
8427 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
8428 | ||
8429 | /* Go back to the starting frequency */ | |
7648fa99 | 8430 | ironlake_set_drps(dev, dev_priv->fstart); |
f97108d1 JB |
8431 | msleep(1); |
8432 | rgvswctl |= MEMCTL_CMD_STS; | |
8433 | I915_WRITE(MEMSWCTL, rgvswctl); | |
8434 | msleep(1); | |
8435 | ||
8436 | } | |
8437 | ||
3b8d8d91 JB |
8438 | void gen6_set_rps(struct drm_device *dev, u8 val) |
8439 | { | |
8440 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8441 | u32 swreq; | |
8442 | ||
8443 | swreq = (val & 0x3ff) << 25; | |
8444 | I915_WRITE(GEN6_RPNSWREQ, swreq); | |
8445 | } | |
8446 | ||
8447 | void gen6_disable_rps(struct drm_device *dev) | |
8448 | { | |
8449 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8450 | ||
8451 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); | |
8452 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); | |
8453 | I915_WRITE(GEN6_PMIER, 0); | |
6fdd4d98 DV |
8454 | /* Complete PM interrupt masking here doesn't race with the rps work |
8455 | * item again unmasking PM interrupts because that is using a different | |
8456 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving | |
8457 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ | |
4912d041 BW |
8458 | |
8459 | spin_lock_irq(&dev_priv->rps_lock); | |
8460 | dev_priv->pm_iir = 0; | |
8461 | spin_unlock_irq(&dev_priv->rps_lock); | |
8462 | ||
3b8d8d91 JB |
8463 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
8464 | } | |
8465 | ||
7648fa99 JB |
8466 | static unsigned long intel_pxfreq(u32 vidfreq) |
8467 | { | |
8468 | unsigned long freq; | |
8469 | int div = (vidfreq & 0x3f0000) >> 16; | |
8470 | int post = (vidfreq & 0x3000) >> 12; | |
8471 | int pre = (vidfreq & 0x7); | |
8472 | ||
8473 | if (!pre) | |
8474 | return 0; | |
8475 | ||
8476 | freq = ((div * 133333) / ((1<<post) * pre)); | |
8477 | ||
8478 | return freq; | |
8479 | } | |
8480 | ||
8481 | void intel_init_emon(struct drm_device *dev) | |
8482 | { | |
8483 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8484 | u32 lcfuse; | |
8485 | u8 pxw[16]; | |
8486 | int i; | |
8487 | ||
8488 | /* Disable to program */ | |
8489 | I915_WRITE(ECR, 0); | |
8490 | POSTING_READ(ECR); | |
8491 | ||
8492 | /* Program energy weights for various events */ | |
8493 | I915_WRITE(SDEW, 0x15040d00); | |
8494 | I915_WRITE(CSIEW0, 0x007f0000); | |
8495 | I915_WRITE(CSIEW1, 0x1e220004); | |
8496 | I915_WRITE(CSIEW2, 0x04000004); | |
8497 | ||
8498 | for (i = 0; i < 5; i++) | |
8499 | I915_WRITE(PEW + (i * 4), 0); | |
8500 | for (i = 0; i < 3; i++) | |
8501 | I915_WRITE(DEW + (i * 4), 0); | |
8502 | ||
8503 | /* Program P-state weights to account for frequency power adjustment */ | |
8504 | for (i = 0; i < 16; i++) { | |
8505 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
8506 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
8507 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
8508 | PXVFREQ_PX_SHIFT; | |
8509 | unsigned long val; | |
8510 | ||
8511 | val = vid * vid; | |
8512 | val *= (freq / 1000); | |
8513 | val *= 255; | |
8514 | val /= (127*127*900); | |
8515 | if (val > 0xff) | |
8516 | DRM_ERROR("bad pxval: %ld\n", val); | |
8517 | pxw[i] = val; | |
8518 | } | |
8519 | /* Render standby states get 0 weight */ | |
8520 | pxw[14] = 0; | |
8521 | pxw[15] = 0; | |
8522 | ||
8523 | for (i = 0; i < 4; i++) { | |
8524 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
8525 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
8526 | I915_WRITE(PXW + (i * 4), val); | |
8527 | } | |
8528 | ||
8529 | /* Adjust magic regs to magic values (more experimental results) */ | |
8530 | I915_WRITE(OGW0, 0); | |
8531 | I915_WRITE(OGW1, 0); | |
8532 | I915_WRITE(EG0, 0x00007f00); | |
8533 | I915_WRITE(EG1, 0x0000000e); | |
8534 | I915_WRITE(EG2, 0x000e0000); | |
8535 | I915_WRITE(EG3, 0x68000300); | |
8536 | I915_WRITE(EG4, 0x42000000); | |
8537 | I915_WRITE(EG5, 0x00140031); | |
8538 | I915_WRITE(EG6, 0); | |
8539 | I915_WRITE(EG7, 0); | |
8540 | ||
8541 | for (i = 0; i < 8; i++) | |
8542 | I915_WRITE(PXWL + (i * 4), 0); | |
8543 | ||
8544 | /* Enable PMON + select events */ | |
8545 | I915_WRITE(ECR, 0x80000019); | |
8546 | ||
8547 | lcfuse = I915_READ(LCFUSE02); | |
8548 | ||
8549 | dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); | |
8550 | } | |
8551 | ||
83b7f9ac | 8552 | static int intel_enable_rc6(struct drm_device *dev) |
c0f372b3 KP |
8553 | { |
8554 | /* | |
8555 | * Respect the kernel parameter if it is set | |
8556 | */ | |
8557 | if (i915_enable_rc6 >= 0) | |
8558 | return i915_enable_rc6; | |
8559 | ||
8560 | /* | |
8561 | * Disable RC6 on Ironlake | |
8562 | */ | |
8563 | if (INTEL_INFO(dev)->gen == 5) | |
8564 | return 0; | |
8565 | ||
8566 | /* | |
371de6e4 | 8567 | * Disable rc6 on Sandybridge |
c0f372b3 KP |
8568 | */ |
8569 | if (INTEL_INFO(dev)->gen == 6) { | |
aa464191 ED |
8570 | DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n"); |
8571 | return INTEL_RC6_ENABLE; | |
c0f372b3 | 8572 | } |
aa464191 ED |
8573 | DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n"); |
8574 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); | |
c0f372b3 KP |
8575 | } |
8576 | ||
3b8d8d91 | 8577 | void gen6_enable_rps(struct drm_i915_private *dev_priv) |
8fd26859 | 8578 | { |
a6044e23 JB |
8579 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
8580 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
7df8721b | 8581 | u32 pcu_mbox, rc6_mask = 0; |
dd202c6d | 8582 | u32 gtfifodbg; |
a6044e23 | 8583 | int cur_freq, min_freq, max_freq; |
83b7f9ac | 8584 | int rc6_mode; |
8fd26859 CW |
8585 | int i; |
8586 | ||
8587 | /* Here begins a magic sequence of register writes to enable | |
8588 | * auto-downclocking. | |
8589 | * | |
8590 | * Perhaps there might be some value in exposing these to | |
8591 | * userspace... | |
8592 | */ | |
8593 | I915_WRITE(GEN6_RC_STATE, 0); | |
d1ebd816 | 8594 | mutex_lock(&dev_priv->dev->struct_mutex); |
dd202c6d BW |
8595 | |
8596 | /* Clear the DBG now so we don't confuse earlier errors */ | |
8597 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { | |
8598 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); | |
8599 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
8600 | } | |
8601 | ||
fcca7926 | 8602 | gen6_gt_force_wake_get(dev_priv); |
8fd26859 | 8603 | |
3b8d8d91 | 8604 | /* disable the counters and set deterministic thresholds */ |
8fd26859 CW |
8605 | I915_WRITE(GEN6_RC_CONTROL, 0); |
8606 | ||
8607 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
8608 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
8609 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
8610 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
8611 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
8612 | ||
8613 | for (i = 0; i < I915_NUM_RINGS; i++) | |
8614 | I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10); | |
8615 | ||
8616 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
8617 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
8618 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
8619 | I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); | |
8620 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ | |
8621 | ||
83b7f9ac ED |
8622 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
8623 | if (rc6_mode & INTEL_RC6_ENABLE) | |
8624 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; | |
8625 | ||
8626 | if (rc6_mode & INTEL_RC6p_ENABLE) | |
8627 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; | |
8628 | ||
8629 | if (rc6_mode & INTEL_RC6pp_ENABLE) | |
8630 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; | |
8631 | ||
8632 | DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", | |
8633 | (rc6_mode & INTEL_RC6_ENABLE) ? "on" : "off", | |
8634 | (rc6_mode & INTEL_RC6p_ENABLE) ? "on" : "off", | |
8635 | (rc6_mode & INTEL_RC6pp_ENABLE) ? "on" : "off"); | |
7df8721b | 8636 | |
8fd26859 | 8637 | I915_WRITE(GEN6_RC_CONTROL, |
7df8721b | 8638 | rc6_mask | |
9c3d2f7f | 8639 | GEN6_RC_CTL_EI_MODE(1) | |
8fd26859 CW |
8640 | GEN6_RC_CTL_HW_ENABLE); |
8641 | ||
3b8d8d91 | 8642 | I915_WRITE(GEN6_RPNSWREQ, |
8fd26859 CW |
8643 | GEN6_FREQUENCY(10) | |
8644 | GEN6_OFFSET(0) | | |
8645 | GEN6_AGGRESSIVE_TURBO); | |
8646 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
8647 | GEN6_FREQUENCY(12)); | |
8648 | ||
8649 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); | |
8650 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
8651 | 18 << 24 | | |
8652 | 6 << 16); | |
ccab5c82 JB |
8653 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000); |
8654 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000); | |
8fd26859 | 8655 | I915_WRITE(GEN6_RP_UP_EI, 100000); |
ccab5c82 | 8656 | I915_WRITE(GEN6_RP_DOWN_EI, 5000000); |
8fd26859 CW |
8657 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
8658 | I915_WRITE(GEN6_RP_CONTROL, | |
8659 | GEN6_RP_MEDIA_TURBO | | |
6ed55ee7 | 8660 | GEN6_RP_MEDIA_HW_MODE | |
8fd26859 CW |
8661 | GEN6_RP_MEDIA_IS_GFX | |
8662 | GEN6_RP_ENABLE | | |
ccab5c82 JB |
8663 | GEN6_RP_UP_BUSY_AVG | |
8664 | GEN6_RP_DOWN_IDLE_CONT); | |
8fd26859 CW |
8665 | |
8666 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
8667 | 500)) | |
8668 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); | |
8669 | ||
8670 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
8671 | I915_WRITE(GEN6_PCODE_MAILBOX, | |
8672 | GEN6_PCODE_READY | | |
8673 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); | |
8674 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
8675 | 500)) | |
8676 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); | |
8677 | ||
a6044e23 JB |
8678 | min_freq = (rp_state_cap & 0xff0000) >> 16; |
8679 | max_freq = rp_state_cap & 0xff; | |
8680 | cur_freq = (gt_perf_status & 0xff00) >> 8; | |
8681 | ||
8682 | /* Check for overclock support */ | |
8683 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
8684 | 500)) | |
8685 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); | |
8686 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS); | |
8687 | pcu_mbox = I915_READ(GEN6_PCODE_DATA); | |
8688 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
8689 | 500)) | |
8690 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); | |
8691 | if (pcu_mbox & (1<<31)) { /* OC supported */ | |
8692 | max_freq = pcu_mbox & 0xff; | |
e281fcaa | 8693 | DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50); |
a6044e23 JB |
8694 | } |
8695 | ||
8696 | /* In units of 100MHz */ | |
8697 | dev_priv->max_delay = max_freq; | |
8698 | dev_priv->min_delay = min_freq; | |
8699 | dev_priv->cur_delay = cur_freq; | |
8700 | ||
8fd26859 CW |
8701 | /* requires MSI enabled */ |
8702 | I915_WRITE(GEN6_PMIER, | |
8703 | GEN6_PM_MBOX_EVENT | | |
8704 | GEN6_PM_THERMAL_EVENT | | |
8705 | GEN6_PM_RP_DOWN_TIMEOUT | | |
8706 | GEN6_PM_RP_UP_THRESHOLD | | |
8707 | GEN6_PM_RP_DOWN_THRESHOLD | | |
8708 | GEN6_PM_RP_UP_EI_EXPIRED | | |
8709 | GEN6_PM_RP_DOWN_EI_EXPIRED); | |
4912d041 BW |
8710 | spin_lock_irq(&dev_priv->rps_lock); |
8711 | WARN_ON(dev_priv->pm_iir != 0); | |
3b8d8d91 | 8712 | I915_WRITE(GEN6_PMIMR, 0); |
4912d041 | 8713 | spin_unlock_irq(&dev_priv->rps_lock); |
3b8d8d91 JB |
8714 | /* enable all PM interrupts */ |
8715 | I915_WRITE(GEN6_PMINTRMSK, 0); | |
8fd26859 | 8716 | |
fcca7926 | 8717 | gen6_gt_force_wake_put(dev_priv); |
d1ebd816 | 8718 | mutex_unlock(&dev_priv->dev->struct_mutex); |
8fd26859 CW |
8719 | } |
8720 | ||
23b2f8bb JB |
8721 | void gen6_update_ring_freq(struct drm_i915_private *dev_priv) |
8722 | { | |
8723 | int min_freq = 15; | |
8724 | int gpu_freq, ia_freq, max_ia_freq; | |
8725 | int scaling_factor = 180; | |
8726 | ||
8727 | max_ia_freq = cpufreq_quick_get_max(0); | |
8728 | /* | |
8729 | * Default to measured freq if none found, PCU will ensure we don't go | |
8730 | * over | |
8731 | */ | |
8732 | if (!max_ia_freq) | |
8733 | max_ia_freq = tsc_khz; | |
8734 | ||
8735 | /* Convert from kHz to MHz */ | |
8736 | max_ia_freq /= 1000; | |
8737 | ||
8738 | mutex_lock(&dev_priv->dev->struct_mutex); | |
8739 | ||
8740 | /* | |
8741 | * For each potential GPU frequency, load a ring frequency we'd like | |
8742 | * to use for memory access. We do this by specifying the IA frequency | |
8743 | * the PCU should use as a reference to determine the ring frequency. | |
8744 | */ | |
8745 | for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay; | |
8746 | gpu_freq--) { | |
8747 | int diff = dev_priv->max_delay - gpu_freq; | |
8748 | ||
8749 | /* | |
8750 | * For GPU frequencies less than 750MHz, just use the lowest | |
8751 | * ring freq. | |
8752 | */ | |
8753 | if (gpu_freq < min_freq) | |
8754 | ia_freq = 800; | |
8755 | else | |
8756 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
8757 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
8758 | ||
8759 | I915_WRITE(GEN6_PCODE_DATA, | |
8760 | (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) | | |
8761 | gpu_freq); | |
8762 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | | |
8763 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); | |
8764 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & | |
8765 | GEN6_PCODE_READY) == 0, 10)) { | |
8766 | DRM_ERROR("pcode write of freq table timed out\n"); | |
8767 | continue; | |
8768 | } | |
8769 | } | |
8770 | ||
8771 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
8772 | } | |
8773 | ||
6067aaea JB |
8774 | static void ironlake_init_clock_gating(struct drm_device *dev) |
8775 | { | |
8776 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8777 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; | |
8778 | ||
8779 | /* Required for FBC */ | |
8780 | dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE | | |
8781 | DPFCRUNIT_CLOCK_GATE_DISABLE | | |
8782 | DPFDUNIT_CLOCK_GATE_DISABLE; | |
8783 | /* Required for CxSR */ | |
8784 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; | |
8785 | ||
8786 | I915_WRITE(PCH_3DCGDIS0, | |
8787 | MARIUNIT_CLOCK_GATE_DISABLE | | |
8788 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
8789 | I915_WRITE(PCH_3DCGDIS1, | |
8790 | VFMUNIT_CLOCK_GATE_DISABLE); | |
8791 | ||
8792 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | |
8793 | ||
6067aaea JB |
8794 | /* |
8795 | * According to the spec the following bits should be set in | |
8796 | * order to enable memory self-refresh | |
8797 | * The bit 22/21 of 0x42004 | |
8798 | * The bit 5 of 0x42020 | |
8799 | * The bit 15 of 0x45000 | |
8800 | */ | |
8801 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8802 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8803 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
8804 | I915_WRITE(ILK_DSPCLK_GATE, | |
8805 | (I915_READ(ILK_DSPCLK_GATE) | | |
8806 | ILK_DPARB_CLK_GATE)); | |
8807 | I915_WRITE(DISP_ARB_CTL, | |
8808 | (I915_READ(DISP_ARB_CTL) | | |
8809 | DISP_FBC_WM_DIS)); | |
8810 | I915_WRITE(WM3_LP_ILK, 0); | |
8811 | I915_WRITE(WM2_LP_ILK, 0); | |
8812 | I915_WRITE(WM1_LP_ILK, 0); | |
8813 | ||
8814 | /* | |
8815 | * Based on the document from hardware guys the following bits | |
8816 | * should be set unconditionally in order to enable FBC. | |
8817 | * The bit 22 of 0x42000 | |
8818 | * The bit 22 of 0x42004 | |
8819 | * The bit 7,8,9 of 0x42020. | |
8820 | */ | |
8821 | if (IS_IRONLAKE_M(dev)) { | |
8822 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
8823 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
8824 | ILK_FBCQ_DIS); | |
8825 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8826 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8827 | ILK_DPARB_GATE); | |
8828 | I915_WRITE(ILK_DSPCLK_GATE, | |
8829 | I915_READ(ILK_DSPCLK_GATE) | | |
8830 | ILK_DPFC_DIS1 | | |
8831 | ILK_DPFC_DIS2 | | |
8832 | ILK_CLK_FBC); | |
8833 | } | |
8834 | ||
8835 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8836 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8837 | ILK_ELPIN_409_SELECT); | |
8838 | I915_WRITE(_3D_CHICKEN2, | |
8839 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
8840 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
8fd26859 CW |
8841 | } |
8842 | ||
6067aaea | 8843 | static void gen6_init_clock_gating(struct drm_device *dev) |
652c393a JB |
8844 | { |
8845 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9db4a9c7 | 8846 | int pipe; |
6067aaea JB |
8847 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
8848 | ||
8849 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | |
652c393a | 8850 | |
6067aaea JB |
8851 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
8852 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8853 | ILK_ELPIN_409_SELECT); | |
8956c8bb | 8854 | |
6067aaea JB |
8855 | I915_WRITE(WM3_LP_ILK, 0); |
8856 | I915_WRITE(WM2_LP_ILK, 0); | |
8857 | I915_WRITE(WM1_LP_ILK, 0); | |
652c393a | 8858 | |
406478dc EA |
8859 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
8860 | * gating disable must be set. Failure to set it results in | |
8861 | * flickering pixels due to Z write ordering failures after | |
8862 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
8863 | * Sanctuary and Tropics, and apparently anything else with | |
8864 | * alpha test or pixel discard. | |
9ca1d10d EA |
8865 | * |
8866 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
8867 | * but we didn't debug actual testcases to find it out. | |
406478dc | 8868 | */ |
9ca1d10d EA |
8869 | I915_WRITE(GEN6_UCGCTL2, |
8870 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | | |
8871 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
406478dc | 8872 | |
652c393a | 8873 | /* |
6067aaea JB |
8874 | * According to the spec the following bits should be |
8875 | * set in order to enable memory self-refresh and fbc: | |
8876 | * The bit21 and bit22 of 0x42000 | |
8877 | * The bit21 and bit22 of 0x42004 | |
8878 | * The bit5 and bit7 of 0x42020 | |
8879 | * The bit14 of 0x70180 | |
8880 | * The bit14 of 0x71180 | |
652c393a | 8881 | */ |
6067aaea JB |
8882 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
8883 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
8884 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
8885 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8886 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8887 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
8888 | I915_WRITE(ILK_DSPCLK_GATE, | |
8889 | I915_READ(ILK_DSPCLK_GATE) | | |
8890 | ILK_DPARB_CLK_GATE | | |
8891 | ILK_DPFD_CLK_GATE); | |
8956c8bb | 8892 | |
d74362c9 | 8893 | for_each_pipe(pipe) { |
6067aaea JB |
8894 | I915_WRITE(DSPCNTR(pipe), |
8895 | I915_READ(DSPCNTR(pipe)) | | |
8896 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
d74362c9 KP |
8897 | intel_flush_display_plane(dev_priv, pipe); |
8898 | } | |
6067aaea | 8899 | } |
8956c8bb | 8900 | |
28963a3e JB |
8901 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
8902 | { | |
8903 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8904 | int pipe; | |
8905 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; | |
7f8a8569 | 8906 | |
28963a3e | 8907 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
382b0936 | 8908 | |
28963a3e JB |
8909 | I915_WRITE(WM3_LP_ILK, 0); |
8910 | I915_WRITE(WM2_LP_ILK, 0); | |
8911 | I915_WRITE(WM1_LP_ILK, 0); | |
de6e2eaf | 8912 | |
eae66b50 ED |
8913 | /* According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
8914 | * This implements the WaDisableRCZUnitClockGating workaround. | |
8915 | */ | |
8916 | I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); | |
8917 | ||
28963a3e | 8918 | I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); |
67e92af0 | 8919 | |
116ac8d2 EA |
8920 | I915_WRITE(IVB_CHICKEN3, |
8921 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
8922 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
8923 | ||
d71de14d KG |
8924 | /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ |
8925 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, | |
8926 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); | |
8927 | ||
e4e0c058 ED |
8928 | /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ |
8929 | I915_WRITE(GEN7_L3CNTLREG1, | |
8930 | GEN7_WA_FOR_GEN7_L3_CONTROL); | |
8931 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, | |
8932 | GEN7_WA_L3_CHICKEN_MODE); | |
8933 | ||
db099c8f ED |
8934 | /* This is required by WaCatErrorRejectionIssue */ |
8935 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, | |
8936 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
8937 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
8938 | ||
d74362c9 | 8939 | for_each_pipe(pipe) { |
28963a3e JB |
8940 | I915_WRITE(DSPCNTR(pipe), |
8941 | I915_READ(DSPCNTR(pipe)) | | |
8942 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
d74362c9 KP |
8943 | intel_flush_display_plane(dev_priv, pipe); |
8944 | } | |
28963a3e JB |
8945 | } |
8946 | ||
fb046853 JB |
8947 | static void valleyview_init_clock_gating(struct drm_device *dev) |
8948 | { | |
8949 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8950 | int pipe; | |
8951 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; | |
8952 | ||
8953 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | |
8954 | ||
8955 | I915_WRITE(WM3_LP_ILK, 0); | |
8956 | I915_WRITE(WM2_LP_ILK, 0); | |
8957 | I915_WRITE(WM1_LP_ILK, 0); | |
8958 | ||
8959 | /* According to the spec, bit 13 (RCZUNIT) must be set on IVB. | |
8960 | * This implements the WaDisableRCZUnitClockGating workaround. | |
8961 | */ | |
8962 | I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); | |
8963 | ||
8964 | I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); | |
8965 | ||
8966 | I915_WRITE(IVB_CHICKEN3, | |
8967 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
8968 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
8969 | ||
8970 | /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ | |
8971 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, | |
8972 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); | |
8973 | ||
8974 | /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ | |
8975 | I915_WRITE(GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); | |
8976 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); | |
8977 | ||
8978 | /* This is required by WaCatErrorRejectionIssue */ | |
8979 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, | |
8980 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
8981 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
8982 | ||
8983 | for_each_pipe(pipe) { | |
8984 | I915_WRITE(DSPCNTR(pipe), | |
8985 | I915_READ(DSPCNTR(pipe)) | | |
8986 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
8987 | intel_flush_display_plane(dev_priv, pipe); | |
8988 | } | |
8989 | ||
8990 | I915_WRITE(CACHE_MODE_1, I915_READ(CACHE_MODE_1) | | |
8991 | (PIXEL_SUBSPAN_COLLECT_OPT_DISABLE << 16) | | |
8992 | PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); | |
8993 | } | |
8994 | ||
6067aaea JB |
8995 | static void g4x_init_clock_gating(struct drm_device *dev) |
8996 | { | |
8997 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8998 | uint32_t dspclk_gate; | |
8fd26859 | 8999 | |
6067aaea JB |
9000 | I915_WRITE(RENCLK_GATE_D1, 0); |
9001 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
9002 | GS_UNIT_CLOCK_GATE_DISABLE | | |
9003 | CL_UNIT_CLOCK_GATE_DISABLE); | |
9004 | I915_WRITE(RAMCLK_GATE_D, 0); | |
9005 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
9006 | OVRUNIT_CLOCK_GATE_DISABLE | | |
9007 | OVCUNIT_CLOCK_GATE_DISABLE; | |
9008 | if (IS_GM45(dev)) | |
9009 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
9010 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
9011 | } | |
1398261a | 9012 | |
6067aaea JB |
9013 | static void crestline_init_clock_gating(struct drm_device *dev) |
9014 | { | |
9015 | struct drm_i915_private *dev_priv = dev->dev_private; | |
652c393a | 9016 | |
6067aaea JB |
9017 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
9018 | I915_WRITE(RENCLK_GATE_D2, 0); | |
9019 | I915_WRITE(DSPCLK_GATE_D, 0); | |
9020 | I915_WRITE(RAMCLK_GATE_D, 0); | |
9021 | I915_WRITE16(DEUC, 0); | |
9022 | } | |
652c393a | 9023 | |
6067aaea JB |
9024 | static void broadwater_init_clock_gating(struct drm_device *dev) |
9025 | { | |
9026 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9027 | ||
9028 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | | |
9029 | I965_RCC_CLOCK_GATE_DISABLE | | |
9030 | I965_RCPB_CLOCK_GATE_DISABLE | | |
9031 | I965_ISC_CLOCK_GATE_DISABLE | | |
9032 | I965_FBC_CLOCK_GATE_DISABLE); | |
9033 | I915_WRITE(RENCLK_GATE_D2, 0); | |
9034 | } | |
9035 | ||
9036 | static void gen3_init_clock_gating(struct drm_device *dev) | |
9037 | { | |
9038 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9039 | u32 dstate = I915_READ(D_STATE); | |
9040 | ||
9041 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
9042 | DSTATE_DOT_CLOCK_GATING; | |
9043 | I915_WRITE(D_STATE, dstate); | |
9044 | } | |
9045 | ||
9046 | static void i85x_init_clock_gating(struct drm_device *dev) | |
9047 | { | |
9048 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9049 | ||
9050 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); | |
9051 | } | |
9052 | ||
9053 | static void i830_init_clock_gating(struct drm_device *dev) | |
9054 | { | |
9055 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9056 | ||
9057 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
652c393a JB |
9058 | } |
9059 | ||
645c62a5 JB |
9060 | static void ibx_init_clock_gating(struct drm_device *dev) |
9061 | { | |
9062 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9063 | ||
9064 | /* | |
9065 | * On Ibex Peak and Cougar Point, we need to disable clock | |
9066 | * gating for the panel power sequencer or it will fail to | |
9067 | * start up when no ports are active. | |
9068 | */ | |
9069 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
9070 | } | |
9071 | ||
9072 | static void cpt_init_clock_gating(struct drm_device *dev) | |
9073 | { | |
9074 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3bcf603f | 9075 | int pipe; |
645c62a5 JB |
9076 | |
9077 | /* | |
9078 | * On Ibex Peak and Cougar Point, we need to disable clock | |
9079 | * gating for the panel power sequencer or it will fail to | |
9080 | * start up when no ports are active. | |
9081 | */ | |
9082 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
9083 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | | |
9084 | DPLS_EDP_PPS_FIX_DIS); | |
3bcf603f JB |
9085 | /* Without this, mode sets may fail silently on FDI */ |
9086 | for_each_pipe(pipe) | |
9087 | I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS); | |
652c393a JB |
9088 | } |
9089 | ||
ac668088 | 9090 | static void ironlake_teardown_rc6(struct drm_device *dev) |
0cdab21f CW |
9091 | { |
9092 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9093 | ||
9094 | if (dev_priv->renderctx) { | |
ac668088 CW |
9095 | i915_gem_object_unpin(dev_priv->renderctx); |
9096 | drm_gem_object_unreference(&dev_priv->renderctx->base); | |
0cdab21f CW |
9097 | dev_priv->renderctx = NULL; |
9098 | } | |
9099 | ||
9100 | if (dev_priv->pwrctx) { | |
ac668088 CW |
9101 | i915_gem_object_unpin(dev_priv->pwrctx); |
9102 | drm_gem_object_unreference(&dev_priv->pwrctx->base); | |
9103 | dev_priv->pwrctx = NULL; | |
9104 | } | |
9105 | } | |
9106 | ||
9107 | static void ironlake_disable_rc6(struct drm_device *dev) | |
9108 | { | |
9109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9110 | ||
9111 | if (I915_READ(PWRCTXA)) { | |
9112 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ | |
9113 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); | |
9114 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), | |
9115 | 50); | |
0cdab21f CW |
9116 | |
9117 | I915_WRITE(PWRCTXA, 0); | |
9118 | POSTING_READ(PWRCTXA); | |
9119 | ||
ac668088 CW |
9120 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
9121 | POSTING_READ(RSTDBYCTL); | |
0cdab21f | 9122 | } |
ac668088 | 9123 | |
99507307 | 9124 | ironlake_teardown_rc6(dev); |
0cdab21f CW |
9125 | } |
9126 | ||
ac668088 | 9127 | static int ironlake_setup_rc6(struct drm_device *dev) |
d5bb081b JB |
9128 | { |
9129 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9130 | ||
ac668088 CW |
9131 | if (dev_priv->renderctx == NULL) |
9132 | dev_priv->renderctx = intel_alloc_context_page(dev); | |
9133 | if (!dev_priv->renderctx) | |
9134 | return -ENOMEM; | |
9135 | ||
9136 | if (dev_priv->pwrctx == NULL) | |
9137 | dev_priv->pwrctx = intel_alloc_context_page(dev); | |
9138 | if (!dev_priv->pwrctx) { | |
9139 | ironlake_teardown_rc6(dev); | |
9140 | return -ENOMEM; | |
9141 | } | |
9142 | ||
9143 | return 0; | |
d5bb081b JB |
9144 | } |
9145 | ||
9146 | void ironlake_enable_rc6(struct drm_device *dev) | |
9147 | { | |
9148 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9149 | int ret; | |
9150 | ||
ac668088 CW |
9151 | /* rc6 disabled by default due to repeated reports of hanging during |
9152 | * boot and resume. | |
9153 | */ | |
c0f372b3 | 9154 | if (!intel_enable_rc6(dev)) |
ac668088 CW |
9155 | return; |
9156 | ||
2c34b850 | 9157 | mutex_lock(&dev->struct_mutex); |
ac668088 | 9158 | ret = ironlake_setup_rc6(dev); |
2c34b850 BW |
9159 | if (ret) { |
9160 | mutex_unlock(&dev->struct_mutex); | |
ac668088 | 9161 | return; |
2c34b850 | 9162 | } |
ac668088 | 9163 | |
d5bb081b JB |
9164 | /* |
9165 | * GPU can automatically power down the render unit if given a page | |
9166 | * to save state. | |
9167 | */ | |
9168 | ret = BEGIN_LP_RING(6); | |
9169 | if (ret) { | |
ac668088 | 9170 | ironlake_teardown_rc6(dev); |
2c34b850 | 9171 | mutex_unlock(&dev->struct_mutex); |
d5bb081b JB |
9172 | return; |
9173 | } | |
ac668088 | 9174 | |
d5bb081b JB |
9175 | OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
9176 | OUT_RING(MI_SET_CONTEXT); | |
9177 | OUT_RING(dev_priv->renderctx->gtt_offset | | |
9178 | MI_MM_SPACE_GTT | | |
9179 | MI_SAVE_EXT_STATE_EN | | |
9180 | MI_RESTORE_EXT_STATE_EN | | |
9181 | MI_RESTORE_INHIBIT); | |
9182 | OUT_RING(MI_SUSPEND_FLUSH); | |
9183 | OUT_RING(MI_NOOP); | |
9184 | OUT_RING(MI_FLUSH); | |
9185 | ADVANCE_LP_RING(); | |
9186 | ||
4a246cfc BW |
9187 | /* |
9188 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW | |
9189 | * does an implicit flush, combined with MI_FLUSH above, it should be | |
9190 | * safe to assume that renderctx is valid | |
9191 | */ | |
9192 | ret = intel_wait_ring_idle(LP_RING(dev_priv)); | |
9193 | if (ret) { | |
9194 | DRM_ERROR("failed to enable ironlake power power savings\n"); | |
9195 | ironlake_teardown_rc6(dev); | |
9196 | mutex_unlock(&dev->struct_mutex); | |
9197 | return; | |
9198 | } | |
9199 | ||
d5bb081b JB |
9200 | I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); |
9201 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | |
2c34b850 | 9202 | mutex_unlock(&dev->struct_mutex); |
d5bb081b JB |
9203 | } |
9204 | ||
645c62a5 JB |
9205 | void intel_init_clock_gating(struct drm_device *dev) |
9206 | { | |
9207 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9208 | ||
9209 | dev_priv->display.init_clock_gating(dev); | |
9210 | ||
9211 | if (dev_priv->display.init_pch_clock_gating) | |
9212 | dev_priv->display.init_pch_clock_gating(dev); | |
9213 | } | |
ac668088 | 9214 | |
e70236a8 JB |
9215 | /* Set up chip specific display functions */ |
9216 | static void intel_init_display(struct drm_device *dev) | |
9217 | { | |
9218 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9219 | ||
9220 | /* We always want a DPMS function */ | |
f564048e | 9221 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 9222 | dev_priv->display.dpms = ironlake_crtc_dpms; |
f564048e | 9223 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
17638cd6 | 9224 | dev_priv->display.update_plane = ironlake_update_plane; |
f564048e | 9225 | } else { |
e70236a8 | 9226 | dev_priv->display.dpms = i9xx_crtc_dpms; |
f564048e | 9227 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
17638cd6 | 9228 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 9229 | } |
e70236a8 | 9230 | |
ee5382ae | 9231 | if (I915_HAS_FBC(dev)) { |
9c04f015 | 9232 | if (HAS_PCH_SPLIT(dev)) { |
b52eb4dc ZY |
9233 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
9234 | dev_priv->display.enable_fbc = ironlake_enable_fbc; | |
9235 | dev_priv->display.disable_fbc = ironlake_disable_fbc; | |
9236 | } else if (IS_GM45(dev)) { | |
74dff282 JB |
9237 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
9238 | dev_priv->display.enable_fbc = g4x_enable_fbc; | |
9239 | dev_priv->display.disable_fbc = g4x_disable_fbc; | |
a6c45cf0 | 9240 | } else if (IS_CRESTLINE(dev)) { |
e70236a8 JB |
9241 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
9242 | dev_priv->display.enable_fbc = i8xx_enable_fbc; | |
9243 | dev_priv->display.disable_fbc = i8xx_disable_fbc; | |
9244 | } | |
74dff282 | 9245 | /* 855GM needs testing */ |
e70236a8 JB |
9246 | } |
9247 | ||
9248 | /* Returns the core display clock speed */ | |
25eb05fc JB |
9249 | if (IS_VALLEYVIEW(dev)) |
9250 | dev_priv->display.get_display_clock_speed = | |
9251 | valleyview_get_display_clock_speed; | |
9252 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
9253 | dev_priv->display.get_display_clock_speed = |
9254 | i945_get_display_clock_speed; | |
9255 | else if (IS_I915G(dev)) | |
9256 | dev_priv->display.get_display_clock_speed = | |
9257 | i915_get_display_clock_speed; | |
f2b115e6 | 9258 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
9259 | dev_priv->display.get_display_clock_speed = |
9260 | i9xx_misc_get_display_clock_speed; | |
9261 | else if (IS_I915GM(dev)) | |
9262 | dev_priv->display.get_display_clock_speed = | |
9263 | i915gm_get_display_clock_speed; | |
9264 | else if (IS_I865G(dev)) | |
9265 | dev_priv->display.get_display_clock_speed = | |
9266 | i865_get_display_clock_speed; | |
f0f8a9ce | 9267 | else if (IS_I85X(dev)) |
e70236a8 JB |
9268 | dev_priv->display.get_display_clock_speed = |
9269 | i855_get_display_clock_speed; | |
9270 | else /* 852, 830 */ | |
9271 | dev_priv->display.get_display_clock_speed = | |
9272 | i830_get_display_clock_speed; | |
9273 | ||
9274 | /* For FIFO watermark updates */ | |
7f8a8569 | 9275 | if (HAS_PCH_SPLIT(dev)) { |
8d715f00 KP |
9276 | dev_priv->display.force_wake_get = __gen6_gt_force_wake_get; |
9277 | dev_priv->display.force_wake_put = __gen6_gt_force_wake_put; | |
9278 | ||
9279 | /* IVB configs may use multi-threaded forcewake */ | |
9280 | if (IS_IVYBRIDGE(dev)) { | |
9281 | u32 ecobus; | |
9282 | ||
c7dffff7 KP |
9283 | /* A small trick here - if the bios hasn't configured MT forcewake, |
9284 | * and if the device is in RC6, then force_wake_mt_get will not wake | |
9285 | * the device and the ECOBUS read will return zero. Which will be | |
9286 | * (correctly) interpreted by the test below as MT forcewake being | |
9287 | * disabled. | |
9288 | */ | |
8d715f00 KP |
9289 | mutex_lock(&dev->struct_mutex); |
9290 | __gen6_gt_force_wake_mt_get(dev_priv); | |
c7dffff7 | 9291 | ecobus = I915_READ_NOTRACE(ECOBUS); |
8d715f00 KP |
9292 | __gen6_gt_force_wake_mt_put(dev_priv); |
9293 | mutex_unlock(&dev->struct_mutex); | |
9294 | ||
9295 | if (ecobus & FORCEWAKE_MT_ENABLE) { | |
9296 | DRM_DEBUG_KMS("Using MT version of forcewake\n"); | |
9297 | dev_priv->display.force_wake_get = | |
9298 | __gen6_gt_force_wake_mt_get; | |
9299 | dev_priv->display.force_wake_put = | |
9300 | __gen6_gt_force_wake_mt_put; | |
9301 | } | |
9302 | } | |
9303 | ||
645c62a5 JB |
9304 | if (HAS_PCH_IBX(dev)) |
9305 | dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating; | |
9306 | else if (HAS_PCH_CPT(dev)) | |
9307 | dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating; | |
9308 | ||
f00a3ddf | 9309 | if (IS_GEN5(dev)) { |
7f8a8569 ZW |
9310 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) |
9311 | dev_priv->display.update_wm = ironlake_update_wm; | |
9312 | else { | |
9313 | DRM_DEBUG_KMS("Failed to get proper latency. " | |
9314 | "Disable CxSR\n"); | |
9315 | dev_priv->display.update_wm = NULL; | |
1398261a | 9316 | } |
674cf967 | 9317 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
6067aaea | 9318 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
e0dac65e | 9319 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a YL |
9320 | } else if (IS_GEN6(dev)) { |
9321 | if (SNB_READ_WM0_LATENCY()) { | |
9322 | dev_priv->display.update_wm = sandybridge_update_wm; | |
b840d907 | 9323 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
1398261a YL |
9324 | } else { |
9325 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
9326 | "Disable CxSR\n"); | |
9327 | dev_priv->display.update_wm = NULL; | |
7f8a8569 | 9328 | } |
674cf967 | 9329 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
6067aaea | 9330 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
e0dac65e | 9331 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
9332 | } else if (IS_IVYBRIDGE(dev)) { |
9333 | /* FIXME: detect B0+ stepping and use auto training */ | |
9334 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
fe100d4d JB |
9335 | if (SNB_READ_WM0_LATENCY()) { |
9336 | dev_priv->display.update_wm = sandybridge_update_wm; | |
b840d907 | 9337 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
fe100d4d JB |
9338 | } else { |
9339 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
9340 | "Disable CxSR\n"); | |
9341 | dev_priv->display.update_wm = NULL; | |
9342 | } | |
28963a3e | 9343 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
e0dac65e | 9344 | dev_priv->display.write_eld = ironlake_write_eld; |
7f8a8569 ZW |
9345 | } else |
9346 | dev_priv->display.update_wm = NULL; | |
ceb04246 JB |
9347 | } else if (IS_VALLEYVIEW(dev)) { |
9348 | dev_priv->display.update_wm = valleyview_update_wm; | |
fb046853 JB |
9349 | dev_priv->display.init_clock_gating = |
9350 | valleyview_init_clock_gating; | |
575155a9 JB |
9351 | dev_priv->display.force_wake_get = vlv_force_wake_get; |
9352 | dev_priv->display.force_wake_put = vlv_force_wake_put; | |
7f8a8569 | 9353 | } else if (IS_PINEVIEW(dev)) { |
d4294342 | 9354 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
95534263 | 9355 | dev_priv->is_ddr3, |
d4294342 ZY |
9356 | dev_priv->fsb_freq, |
9357 | dev_priv->mem_freq)) { | |
9358 | DRM_INFO("failed to find known CxSR latency " | |
95534263 | 9359 | "(found ddr%s fsb freq %d, mem freq %d), " |
d4294342 | 9360 | "disabling CxSR\n", |
0206e353 | 9361 | (dev_priv->is_ddr3 == 1) ? "3" : "2", |
d4294342 ZY |
9362 | dev_priv->fsb_freq, dev_priv->mem_freq); |
9363 | /* Disable CxSR and never update its watermark again */ | |
9364 | pineview_disable_cxsr(dev); | |
9365 | dev_priv->display.update_wm = NULL; | |
9366 | } else | |
9367 | dev_priv->display.update_wm = pineview_update_wm; | |
95e0ee92 | 9368 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
6067aaea | 9369 | } else if (IS_G4X(dev)) { |
e0dac65e | 9370 | dev_priv->display.write_eld = g4x_write_eld; |
e70236a8 | 9371 | dev_priv->display.update_wm = g4x_update_wm; |
6067aaea JB |
9372 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; |
9373 | } else if (IS_GEN4(dev)) { | |
e70236a8 | 9374 | dev_priv->display.update_wm = i965_update_wm; |
6067aaea JB |
9375 | if (IS_CRESTLINE(dev)) |
9376 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; | |
9377 | else if (IS_BROADWATER(dev)) | |
9378 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; | |
9379 | } else if (IS_GEN3(dev)) { | |
e70236a8 JB |
9380 | dev_priv->display.update_wm = i9xx_update_wm; |
9381 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
6067aaea JB |
9382 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
9383 | } else if (IS_I865G(dev)) { | |
9384 | dev_priv->display.update_wm = i830_update_wm; | |
9385 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
9386 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
8f4695ed AJ |
9387 | } else if (IS_I85X(dev)) { |
9388 | dev_priv->display.update_wm = i9xx_update_wm; | |
9389 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; | |
6067aaea | 9390 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
e70236a8 | 9391 | } else { |
8f4695ed | 9392 | dev_priv->display.update_wm = i830_update_wm; |
6067aaea | 9393 | dev_priv->display.init_clock_gating = i830_init_clock_gating; |
8f4695ed | 9394 | if (IS_845G(dev)) |
e70236a8 JB |
9395 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
9396 | else | |
9397 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
e70236a8 | 9398 | } |
8c9f3aaf JB |
9399 | |
9400 | /* Default just returns -ENODEV to indicate unsupported */ | |
9401 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
9402 | ||
9403 | switch (INTEL_INFO(dev)->gen) { | |
9404 | case 2: | |
9405 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
9406 | break; | |
9407 | ||
9408 | case 3: | |
9409 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
9410 | break; | |
9411 | ||
9412 | case 4: | |
9413 | case 5: | |
9414 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
9415 | break; | |
9416 | ||
9417 | case 6: | |
9418 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
9419 | break; | |
7c9017e5 JB |
9420 | case 7: |
9421 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
9422 | break; | |
8c9f3aaf | 9423 | } |
e70236a8 JB |
9424 | } |
9425 | ||
b690e96c JB |
9426 | /* |
9427 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
9428 | * resume, or other times. This quirk makes sure that's the case for | |
9429 | * affected systems. | |
9430 | */ | |
0206e353 | 9431 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
9432 | { |
9433 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9434 | ||
9435 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 9436 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
9437 | } |
9438 | ||
435793df KP |
9439 | /* |
9440 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
9441 | */ | |
9442 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
9443 | { | |
9444 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9445 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 9446 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
9447 | } |
9448 | ||
4dca20ef | 9449 | /* |
5a15ab5b CE |
9450 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
9451 | * brightness value | |
4dca20ef CE |
9452 | */ |
9453 | static void quirk_invert_brightness(struct drm_device *dev) | |
9454 | { | |
9455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9456 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 9457 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
9458 | } |
9459 | ||
b690e96c JB |
9460 | struct intel_quirk { |
9461 | int device; | |
9462 | int subsystem_vendor; | |
9463 | int subsystem_device; | |
9464 | void (*hook)(struct drm_device *dev); | |
9465 | }; | |
9466 | ||
9467 | struct intel_quirk intel_quirks[] = { | |
b690e96c | 9468 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 9469 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c JB |
9470 | |
9471 | /* Thinkpad R31 needs pipe A force quirk */ | |
9472 | { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, | |
9473 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ | |
9474 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
9475 | ||
9476 | /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ | |
9477 | { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, | |
9478 | /* ThinkPad X40 needs pipe A force quirk */ | |
9479 | ||
9480 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ | |
9481 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
9482 | ||
9483 | /* 855 & before need to leave pipe A & dpll A up */ | |
9484 | { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
9485 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
435793df KP |
9486 | |
9487 | /* Lenovo U160 cannot use SSC on LVDS */ | |
9488 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
9489 | |
9490 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
9491 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b CE |
9492 | |
9493 | /* Acer Aspire 5734Z must invert backlight brightness */ | |
9494 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
b690e96c JB |
9495 | }; |
9496 | ||
9497 | static void intel_init_quirks(struct drm_device *dev) | |
9498 | { | |
9499 | struct pci_dev *d = dev->pdev; | |
9500 | int i; | |
9501 | ||
9502 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
9503 | struct intel_quirk *q = &intel_quirks[i]; | |
9504 | ||
9505 | if (d->device == q->device && | |
9506 | (d->subsystem_vendor == q->subsystem_vendor || | |
9507 | q->subsystem_vendor == PCI_ANY_ID) && | |
9508 | (d->subsystem_device == q->subsystem_device || | |
9509 | q->subsystem_device == PCI_ANY_ID)) | |
9510 | q->hook(dev); | |
9511 | } | |
9512 | } | |
9513 | ||
9cce37f4 JB |
9514 | /* Disable the VGA plane that we never use */ |
9515 | static void i915_disable_vga(struct drm_device *dev) | |
9516 | { | |
9517 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9518 | u8 sr1; | |
9519 | u32 vga_reg; | |
9520 | ||
9521 | if (HAS_PCH_SPLIT(dev)) | |
9522 | vga_reg = CPU_VGACNTRL; | |
9523 | else | |
9524 | vga_reg = VGACNTRL; | |
9525 | ||
9526 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
9527 | outb(1, VGA_SR_INDEX); | |
9528 | sr1 = inb(VGA_SR_DATA); | |
9529 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
9530 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
9531 | udelay(300); | |
9532 | ||
9533 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
9534 | POSTING_READ(vga_reg); | |
9535 | } | |
9536 | ||
79e53945 JB |
9537 | void intel_modeset_init(struct drm_device *dev) |
9538 | { | |
652c393a | 9539 | struct drm_i915_private *dev_priv = dev->dev_private; |
b840d907 | 9540 | int i, ret; |
79e53945 JB |
9541 | |
9542 | drm_mode_config_init(dev); | |
9543 | ||
9544 | dev->mode_config.min_width = 0; | |
9545 | dev->mode_config.min_height = 0; | |
9546 | ||
019d96cb DA |
9547 | dev->mode_config.preferred_depth = 24; |
9548 | dev->mode_config.prefer_shadow = 1; | |
9549 | ||
79e53945 JB |
9550 | dev->mode_config.funcs = (void *)&intel_mode_funcs; |
9551 | ||
b690e96c JB |
9552 | intel_init_quirks(dev); |
9553 | ||
e70236a8 JB |
9554 | intel_init_display(dev); |
9555 | ||
a6c45cf0 CW |
9556 | if (IS_GEN2(dev)) { |
9557 | dev->mode_config.max_width = 2048; | |
9558 | dev->mode_config.max_height = 2048; | |
9559 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
9560 | dev->mode_config.max_width = 4096; |
9561 | dev->mode_config.max_height = 4096; | |
79e53945 | 9562 | } else { |
a6c45cf0 CW |
9563 | dev->mode_config.max_width = 8192; |
9564 | dev->mode_config.max_height = 8192; | |
79e53945 | 9565 | } |
35c3047a | 9566 | dev->mode_config.fb_base = dev->agp->base; |
79e53945 | 9567 | |
28c97730 | 9568 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
a3524f1b | 9569 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
79e53945 | 9570 | |
a3524f1b | 9571 | for (i = 0; i < dev_priv->num_pipe; i++) { |
79e53945 | 9572 | intel_crtc_init(dev, i); |
00c2064b JB |
9573 | ret = intel_plane_init(dev, i); |
9574 | if (ret) | |
9575 | DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); | |
79e53945 JB |
9576 | } |
9577 | ||
9cce37f4 JB |
9578 | /* Just disable it once at startup */ |
9579 | i915_disable_vga(dev); | |
79e53945 | 9580 | intel_setup_outputs(dev); |
652c393a | 9581 | |
645c62a5 | 9582 | intel_init_clock_gating(dev); |
9cce37f4 | 9583 | |
7648fa99 | 9584 | if (IS_IRONLAKE_M(dev)) { |
f97108d1 | 9585 | ironlake_enable_drps(dev); |
7648fa99 JB |
9586 | intel_init_emon(dev); |
9587 | } | |
f97108d1 | 9588 | |
1c70c0ce | 9589 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
3b8d8d91 | 9590 | gen6_enable_rps(dev_priv); |
23b2f8bb JB |
9591 | gen6_update_ring_freq(dev_priv); |
9592 | } | |
3b8d8d91 | 9593 | |
652c393a JB |
9594 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
9595 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, | |
9596 | (unsigned long)dev); | |
2c7111db CW |
9597 | } |
9598 | ||
9599 | void intel_modeset_gem_init(struct drm_device *dev) | |
9600 | { | |
9601 | if (IS_IRONLAKE_M(dev)) | |
9602 | ironlake_enable_rc6(dev); | |
02e792fb DV |
9603 | |
9604 | intel_setup_overlay(dev); | |
79e53945 JB |
9605 | } |
9606 | ||
9607 | void intel_modeset_cleanup(struct drm_device *dev) | |
9608 | { | |
652c393a JB |
9609 | struct drm_i915_private *dev_priv = dev->dev_private; |
9610 | struct drm_crtc *crtc; | |
9611 | struct intel_crtc *intel_crtc; | |
9612 | ||
f87ea761 | 9613 | drm_kms_helper_poll_fini(dev); |
652c393a JB |
9614 | mutex_lock(&dev->struct_mutex); |
9615 | ||
723bfd70 JB |
9616 | intel_unregister_dsm_handler(); |
9617 | ||
9618 | ||
652c393a JB |
9619 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
9620 | /* Skip inactive CRTCs */ | |
9621 | if (!crtc->fb) | |
9622 | continue; | |
9623 | ||
9624 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 9625 | intel_increase_pllclock(crtc); |
652c393a JB |
9626 | } |
9627 | ||
973d04f9 | 9628 | intel_disable_fbc(dev); |
e70236a8 | 9629 | |
f97108d1 JB |
9630 | if (IS_IRONLAKE_M(dev)) |
9631 | ironlake_disable_drps(dev); | |
1c70c0ce | 9632 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
3b8d8d91 | 9633 | gen6_disable_rps(dev); |
f97108d1 | 9634 | |
d5bb081b JB |
9635 | if (IS_IRONLAKE_M(dev)) |
9636 | ironlake_disable_rc6(dev); | |
0cdab21f | 9637 | |
57f350b6 JB |
9638 | if (IS_VALLEYVIEW(dev)) |
9639 | vlv_init_dpio(dev); | |
9640 | ||
69341a5e KH |
9641 | mutex_unlock(&dev->struct_mutex); |
9642 | ||
6c0d9350 DV |
9643 | /* Disable the irq before mode object teardown, for the irq might |
9644 | * enqueue unpin/hotplug work. */ | |
9645 | drm_irq_uninstall(dev); | |
9646 | cancel_work_sync(&dev_priv->hotplug_work); | |
6fdd4d98 | 9647 | cancel_work_sync(&dev_priv->rps_work); |
6c0d9350 | 9648 | |
1630fe75 CW |
9649 | /* flush any delayed tasks or pending work */ |
9650 | flush_scheduled_work(); | |
9651 | ||
3dec0095 DV |
9652 | /* Shut off idle work before the crtcs get freed. */ |
9653 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
9654 | intel_crtc = to_intel_crtc(crtc); | |
9655 | del_timer_sync(&intel_crtc->idle_timer); | |
9656 | } | |
9657 | del_timer_sync(&dev_priv->idle_timer); | |
9658 | cancel_work_sync(&dev_priv->idle_work); | |
9659 | ||
79e53945 JB |
9660 | drm_mode_config_cleanup(dev); |
9661 | } | |
9662 | ||
f1c79df3 ZW |
9663 | /* |
9664 | * Return which encoder is currently attached for connector. | |
9665 | */ | |
df0e9248 | 9666 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 9667 | { |
df0e9248 CW |
9668 | return &intel_attached_encoder(connector)->base; |
9669 | } | |
f1c79df3 | 9670 | |
df0e9248 CW |
9671 | void intel_connector_attach_encoder(struct intel_connector *connector, |
9672 | struct intel_encoder *encoder) | |
9673 | { | |
9674 | connector->encoder = encoder; | |
9675 | drm_mode_connector_attach_encoder(&connector->base, | |
9676 | &encoder->base); | |
79e53945 | 9677 | } |
28d52043 DA |
9678 | |
9679 | /* | |
9680 | * set vga decode state - true == enable VGA decode | |
9681 | */ | |
9682 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
9683 | { | |
9684 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9685 | u16 gmch_ctrl; | |
9686 | ||
9687 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
9688 | if (state) | |
9689 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
9690 | else | |
9691 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
9692 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
9693 | return 0; | |
9694 | } | |
c4a1d9e4 CW |
9695 | |
9696 | #ifdef CONFIG_DEBUG_FS | |
9697 | #include <linux/seq_file.h> | |
9698 | ||
9699 | struct intel_display_error_state { | |
9700 | struct intel_cursor_error_state { | |
9701 | u32 control; | |
9702 | u32 position; | |
9703 | u32 base; | |
9704 | u32 size; | |
9705 | } cursor[2]; | |
9706 | ||
9707 | struct intel_pipe_error_state { | |
9708 | u32 conf; | |
9709 | u32 source; | |
9710 | ||
9711 | u32 htotal; | |
9712 | u32 hblank; | |
9713 | u32 hsync; | |
9714 | u32 vtotal; | |
9715 | u32 vblank; | |
9716 | u32 vsync; | |
9717 | } pipe[2]; | |
9718 | ||
9719 | struct intel_plane_error_state { | |
9720 | u32 control; | |
9721 | u32 stride; | |
9722 | u32 size; | |
9723 | u32 pos; | |
9724 | u32 addr; | |
9725 | u32 surface; | |
9726 | u32 tile_offset; | |
9727 | } plane[2]; | |
9728 | }; | |
9729 | ||
9730 | struct intel_display_error_state * | |
9731 | intel_display_capture_error_state(struct drm_device *dev) | |
9732 | { | |
0206e353 | 9733 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
9734 | struct intel_display_error_state *error; |
9735 | int i; | |
9736 | ||
9737 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
9738 | if (error == NULL) | |
9739 | return NULL; | |
9740 | ||
9741 | for (i = 0; i < 2; i++) { | |
9742 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
9743 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
9744 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
9745 | ||
9746 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
9747 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
9748 | error->plane[i].size = I915_READ(DSPSIZE(i)); | |
0206e353 | 9749 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
c4a1d9e4 CW |
9750 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
9751 | if (INTEL_INFO(dev)->gen >= 4) { | |
9752 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
9753 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
9754 | } | |
9755 | ||
9756 | error->pipe[i].conf = I915_READ(PIPECONF(i)); | |
9757 | error->pipe[i].source = I915_READ(PIPESRC(i)); | |
9758 | error->pipe[i].htotal = I915_READ(HTOTAL(i)); | |
9759 | error->pipe[i].hblank = I915_READ(HBLANK(i)); | |
9760 | error->pipe[i].hsync = I915_READ(HSYNC(i)); | |
9761 | error->pipe[i].vtotal = I915_READ(VTOTAL(i)); | |
9762 | error->pipe[i].vblank = I915_READ(VBLANK(i)); | |
9763 | error->pipe[i].vsync = I915_READ(VSYNC(i)); | |
9764 | } | |
9765 | ||
9766 | return error; | |
9767 | } | |
9768 | ||
9769 | void | |
9770 | intel_display_print_error_state(struct seq_file *m, | |
9771 | struct drm_device *dev, | |
9772 | struct intel_display_error_state *error) | |
9773 | { | |
9774 | int i; | |
9775 | ||
9776 | for (i = 0; i < 2; i++) { | |
9777 | seq_printf(m, "Pipe [%d]:\n", i); | |
9778 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); | |
9779 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); | |
9780 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); | |
9781 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); | |
9782 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); | |
9783 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); | |
9784 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); | |
9785 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); | |
9786 | ||
9787 | seq_printf(m, "Plane [%d]:\n", i); | |
9788 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
9789 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
9790 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); | |
9791 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); | |
9792 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); | |
9793 | if (INTEL_INFO(dev)->gen >= 4) { | |
9794 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); | |
9795 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
9796 | } | |
9797 | ||
9798 | seq_printf(m, "Cursor [%d]:\n", i); | |
9799 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
9800 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); | |
9801 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
9802 | } | |
9803 | } | |
9804 | #endif |