]> git.proxmox.com Git - mirror_ubuntu-jammy-kernel.git/blame - drivers/gpu/drm/i915/intel_display.c
projects / mirror_ubuntu-jammy-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: fix up pch pll handling in ->mode_set
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
d4906093 62};
79e53945 63
2377b741
JB		 64/* FDI */
65#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
d2acd215
DV		 67int
68intel_pch_rawclk(struct drm_device *dev)
69{
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75}
76
021357ac
CW		 77static inline u32 /* units of 100MHz */
78intel_fdi_link_freq(struct drm_device *dev)
79{
8b99e68c
CW		 80 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
021357ac
CW		 85}
86
e4b36699 87static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 98};
99
100static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
e4b36699 111};
273e27ca 112
e4b36699 113static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 137};
138
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
044c7c41 152 },
e4b36699
KP		 153};
154
155static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
044c7c41 179 },
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
044c7c41 193 },
e4b36699
KP		 194};
195
f2b115e6 196static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 199 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
273e27ca 202 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
f2b115e6 211static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 222};
223
273e27ca
EA		 224/* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
b91ad0ec 229static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
b91ad0ec 242static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 253};
254
255static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 266};
267
273e27ca 268/* LVDS 100mhz refclk limits. */
b91ad0ec 269static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
0206e353 277 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 280};
281
282static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
0206e353 290 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 293};
294
a0c4da24
JB		 295static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
75e53986 303 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 306};
307
308static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 319};
320
321static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 324 .n = { .min = 1, .max = 7 },
74a4dd2e 325 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
75e53986 329 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 332};
333
1b894b59
CW		 334static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
2c07245f 336{
b91ad0ec 337 struct drm_device *dev = crtc->dev;
2c07245f 338 const intel_limit_t *limit;
b91ad0ec
ZW		 339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 341 if (intel_is_dual_link_lvds(dev)) {
1b894b59 342 if (refclk == 100000)
b91ad0ec
ZW		 343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
c6bb3538 352 } else
b91ad0ec 353 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 354
355 return limit;
356}
357
044c7c41
ML		 358static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359{
360 struct drm_device *dev = crtc->dev;
044c7c41
ML		 361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 364 if (intel_is_dual_link_lvds(dev))
e4b36699 365 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 366 else
e4b36699 367 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 370 limit = &intel_limits_g4x_hdmi;
044c7c41 371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 372 limit = &intel_limits_g4x_sdvo;
044c7c41 373 } else /* The option is for other outputs */
e4b36699 374 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 375
376 return limit;
377}
378
1b894b59 379static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 380{
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
bad720ff 384 if (HAS_PCH_SPLIT(dev))
1b894b59 385 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 386 else if (IS_G4X(dev)) {
044c7c41 387 limit = intel_g4x_limit(crtc);
f2b115e6 388 } else if (IS_PINEVIEW(dev)) {
2177832f 389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 390 limit = &intel_limits_pineview_lvds;
2177832f 391 else
f2b115e6 392 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 407 limit = &intel_limits_i8xx_lvds;
79e53945 408 else
e4b36699 409 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 410 }
411 return limit;
412}
413
f2b115e6
AJ		 414/* m1 is reserved as 0 in Pineview, n is a ring counter */
415static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 416{
2177832f
SL		 417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421}
422
7429e9d4
DV		 423static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424{
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426}
427
ac58c3f0 428static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 429{
7429e9d4 430 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434}
435
79e53945
JB		 436/**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
4ef69c7a 439bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 440{
4ef69c7a 441 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 442 struct intel_encoder *encoder;
443
6c2b7c12
DV		 444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
4ef69c7a
CW		 446 return true;
447
448 return false;
79e53945
JB		 449}
450
7c04d1d9 451#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 452/**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
1b894b59
CW		 457static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
79e53945 460{
79e53945 461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 462 INTELPllInvalid("p1 out of range\n");
79e53945 463 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 464 INTELPllInvalid("p out of range\n");
79e53945 465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 466 INTELPllInvalid("m2 out of range\n");
79e53945 467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 468 INTELPllInvalid("m1 out of range\n");
f2b115e6 469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 470 INTELPllInvalid("m1 <= m2\n");
79e53945 471 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 472 INTELPllInvalid("m out of range\n");
79e53945 473 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 474 INTELPllInvalid("n out of range\n");
79e53945 475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 476 INTELPllInvalid("vco out of range\n");
79e53945
JB		 477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 481 INTELPllInvalid("dot out of range\n");
79e53945
JB		 482
483 return true;
484}
485
d4906093 486static bool
ee9300bb 487i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
ac58c3f0
DV		 490{
491 struct drm_device *dev = crtc->dev;
492 intel_clock_t clock;
493 int err = target;
494
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
496 /*
497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
500 */
501 if (intel_is_dual_link_lvds(dev))
502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
512 memset(best_clock, 0, sizeof(*best_clock));
513
514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 518 if (clock.m2 >= clock.m1)
ac58c3f0
DV		 519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
524 int this_err;
d4906093 525
ac58c3f0
DV		 526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545}
546
547static bool
ee9300bb
DV		 548pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
79e53945
JB		 551{
552 struct drm_device *dev = crtc->dev;
79e53945 553 intel_clock_t clock;
79e53945
JB		 554 int err = target;
555
a210b028 556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 557 /*
a210b028
DV		 558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
79e53945 561 */
1974cad0 562 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
0206e353 573 memset(best_clock, 0, sizeof(*best_clock));
79e53945 574
42158660
ZY		 575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 583 int this_err;
584
ac58c3f0 585 pineview_clock(refclk, &clock);
1b894b59
CW		 586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
79e53945 588 continue;
cec2f356
SP		 589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
79e53945
JB		 592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604}
605
d4906093 606static bool
ee9300bb
DV		 607g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
d4906093
ML		 610{
611 struct drm_device *dev = crtc->dev;
d4906093
ML		 612 intel_clock_t clock;
613 int max_n;
614 bool found;
6ba770dc
AJ		 615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 620 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
f77f13e2 633 /* based on hardware requirement, prefer smaller n to precision */
d4906093 634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 635 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
ac58c3f0 644 i9xx_clock(refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
d4906093 647 continue;
1b894b59
CW		 648
649 this_err = abs(clock.dot - target);
d4906093
ML		 650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
2c07245f
ZW		 660 return found;
661}
662
a0c4da24 663static bool
ee9300bb
DV		 664vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
a0c4da24
JB		 667{
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
af447bd3 674 flag = 0;
a0c4da24
JB		 675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730}
a4fc5ed6 731
a5c961d1
PZ		 732enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734{
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
3b117c8f 738 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 739}
740
a928d536
PZ		 741static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742{
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750}
751
9d0498a2
JB		 752/**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 761{
9d0498a2 762 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 763 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 764
a928d536
PZ		 765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
300387c0
CW		 770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
9d0498a2 786 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
9d0498a2
JB		 790 DRM_DEBUG_KMS("vblank wait timed out\n");
791}
792
ab7ad7f6
KP		 793/*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
ab7ad7f6
KP		 802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
58e10eb9 808 *
9d0498a2 809 */
58e10eb9 810void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 811{
812 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
ab7ad7f6
KP		 815
816 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 817 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 818
819 /* Wait for the Pipe State to go off */
58e10eb9
CW		 820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
284637d9 822 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 823 } else {
837ba00f 824 u32 last_line, line_mask;
58e10eb9 825 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
837ba00f
PZ		 828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
ab7ad7f6
KP		 833 /* Wait for the display line to settle */
834 do {
837ba00f 835 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 836 mdelay(5);
837ba00f 837 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
284637d9 840 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 841 }
79e53945
JB		 842}
843
b0ea7d37
DL		 844/*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853{
854 u32 bit;
855
c36346e3
DL		 856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
b0ea7d37
DL		 884 }
885
886 return I915_READ(SDEISR) & bit;
887}
888
b24e7179
JB		 889static const char *state_string(bool enabled)
890{
891 return enabled ? "on" : "off";
892}
893
894/* Only for pre-ILK configs */
895static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897{
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908}
909#define assert_pll_enabled(d, p) assert_pll(d, p, true)
910#define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
040484af
JB		 912/* For ILK+ */
913static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 914 struct intel_pch_pll *pll,
915 struct intel_crtc *crtc,
916 bool state)
040484af 917{
040484af
JB		 918 u32 val;
919 bool cur_state;
920
9d82aa17
ED		 921 if (HAS_PCH_LPT(dev_priv->dev)) {
922 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
923 return;
924 }
925
92b27b08
CW		 926 if (WARN (!pll,
927 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 928 return;
ee7b9f93 929
92b27b08
CW		 930 val = I915_READ(pll->pll_reg);
931 cur_state = !!(val & DPLL_VCO_ENABLE);
932 WARN(cur_state != state,
933 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
934 pll->pll_reg, state_string(state), state_string(cur_state), val);
935
936 /* Make sure the selected PLL is correctly attached to the transcoder */
937 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 938 u32 pch_dpll;
939
940 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 941 cur_state = pll->pll_reg == _PCH_DPLL_B;
942 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 943 "PLL[%d] not attached to this transcoder %c: %08x\n",
944 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 945 cur_state = !!(val >> (4*crtc->pipe + 3));
946 WARN(cur_state != state,
4bb6f1f3 947 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 948 pll->pll_reg == _PCH_DPLL_B,
949 state_string(state),
4bb6f1f3 950 pipe_name(crtc->pipe),
92b27b08
CW		 951 val);
952 }
d3ccbe86 953 }
040484af 954}
92b27b08
CW		 955#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
956#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 957
958static void assert_fdi_tx(struct drm_i915_private *dev_priv,
959 enum pipe pipe, bool state)
960{
961 int reg;
962 u32 val;
963 bool cur_state;
ad80a810
PZ		 964 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
965 pipe);
040484af 966
affa9354
PZ		 967 if (HAS_DDI(dev_priv->dev)) {
968 /* DDI does not have a specific FDI_TX register */
ad80a810 969 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 970 val = I915_READ(reg);
ad80a810 971 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 972 } else {
973 reg = FDI_TX_CTL(pipe);
974 val = I915_READ(reg);
975 cur_state = !!(val & FDI_TX_ENABLE);
976 }
040484af
JB		 977 WARN(cur_state != state,
978 "FDI TX state assertion failure (expected %s, current %s)\n",
979 state_string(state), state_string(cur_state));
980}
981#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
982#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
983
984static void assert_fdi_rx(struct drm_i915_private *dev_priv,
985 enum pipe pipe, bool state)
986{
987 int reg;
988 u32 val;
989 bool cur_state;
990
d63fa0dc
PZ		 991 reg = FDI_RX_CTL(pipe);
992 val = I915_READ(reg);
993 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 994 WARN(cur_state != state,
995 "FDI RX state assertion failure (expected %s, current %s)\n",
996 state_string(state), state_string(cur_state));
997}
998#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
999#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1000
1001static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe)
1003{
1004 int reg;
1005 u32 val;
1006
1007 /* ILK FDI PLL is always enabled */
1008 if (dev_priv->info->gen == 5)
1009 return;
1010
bf507ef7 1011 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1012 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1013 return;
1014
040484af
JB		 1015 reg = FDI_TX_CTL(pipe);
1016 val = I915_READ(reg);
1017 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1018}
1019
1020static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1021 enum pipe pipe)
1022{
1023 int reg;
1024 u32 val;
1025
1026 reg = FDI_RX_CTL(pipe);
1027 val = I915_READ(reg);
1028 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1029}
1030
ea0760cf
JB		 1031static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1032 enum pipe pipe)
1033{
1034 int pp_reg, lvds_reg;
1035 u32 val;
1036 enum pipe panel_pipe = PIPE_A;
0de3b485 1037 bool locked = true;
ea0760cf
JB		 1038
1039 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1040 pp_reg = PCH_PP_CONTROL;
1041 lvds_reg = PCH_LVDS;
1042 } else {
1043 pp_reg = PP_CONTROL;
1044 lvds_reg = LVDS;
1045 }
1046
1047 val = I915_READ(pp_reg);
1048 if (!(val & PANEL_POWER_ON) ||
1049 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1050 locked = false;
1051
1052 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1053 panel_pipe = PIPE_B;
1054
1055 WARN(panel_pipe == pipe && locked,
1056 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1057 pipe_name(pipe));
ea0760cf
JB		 1058}
1059
b840d907
JB		 1060void assert_pipe(struct drm_i915_private *dev_priv,
1061 enum pipe pipe, bool state)
b24e7179
JB		 1062{
1063 int reg;
1064 u32 val;
63d7bbe9 1065 bool cur_state;
702e7a56
PZ		 1066 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1067 pipe);
b24e7179 1068
8e636784
DV		 1069 /* if we need the pipe A quirk it must be always on */
1070 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1071 state = true;
1072
b97186f0
PZ		 1073 if (!intel_display_power_enabled(dev_priv->dev,
1074 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1075 cur_state = false;
1076 } else {
1077 reg = PIPECONF(cpu_transcoder);
1078 val = I915_READ(reg);
1079 cur_state = !!(val & PIPECONF_ENABLE);
1080 }
1081
63d7bbe9
JB		 1082 WARN(cur_state != state,
1083 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1084 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1085}
1086
931872fc
CW		 1087static void assert_plane(struct drm_i915_private *dev_priv,
1088 enum plane plane, bool state)
b24e7179
JB		 1089{
1090 int reg;
1091 u32 val;
931872fc 1092 bool cur_state;
b24e7179
JB		 1093
1094 reg = DSPCNTR(plane);
1095 val = I915_READ(reg);
931872fc
CW		 1096 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1097 WARN(cur_state != state,
1098 "plane %c assertion failure (expected %s, current %s)\n",
1099 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1100}
1101
931872fc
CW		 1102#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1103#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1104
b24e7179
JB		 1105static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1106 enum pipe pipe)
1107{
653e1026 1108 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1109 int reg, i;
1110 u32 val;
1111 int cur_pipe;
1112
653e1026
VS		 1113 /* Primary planes are fixed to pipes on gen4+ */
1114 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1115 reg = DSPCNTR(pipe);
1116 val = I915_READ(reg);
1117 WARN((val & DISPLAY_PLANE_ENABLE),
1118 "plane %c assertion failure, should be disabled but not\n",
1119 plane_name(pipe));
19ec1358 1120 return;
28c05794 1121 }
19ec1358 1122
b24e7179 1123 /* Need to check both planes against the pipe */
653e1026 1124 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
b24e7179
JB		 1125 reg = DSPCNTR(i);
1126 val = I915_READ(reg);
1127 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1128 DISPPLANE_SEL_PIPE_SHIFT;
1129 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1130 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1131 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1132 }
1133}
1134
19332d7a
JB		 1135static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1136 enum pipe pipe)
1137{
20674eef 1138 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1139 int reg, i;
1140 u32 val;
1141
20674eef
VS		 1142 if (IS_VALLEYVIEW(dev)) {
1143 for (i = 0; i < dev_priv->num_plane; i++) {
1144 reg = SPCNTR(pipe, i);
1145 val = I915_READ(reg);
1146 WARN((val & SP_ENABLE),
1147 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1148 sprite_name(pipe, i), pipe_name(pipe));
1149 }
1150 } else if (INTEL_INFO(dev)->gen >= 7) {
1151 reg = SPRCTL(pipe);
1152 val = I915_READ(reg);
1153 WARN((val & SPRITE_ENABLE),
1154 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1155 plane_name(pipe), pipe_name(pipe));
1156 } else if (INTEL_INFO(dev)->gen >= 5) {
1157 reg = DVSCNTR(pipe);
19332d7a 1158 val = I915_READ(reg);
20674eef 1159 WARN((val & DVS_ENABLE),
06da8da2 1160 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1161 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1162 }
1163}
1164
92f2584a
JB		 1165static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1166{
1167 u32 val;
1168 bool enabled;
1169
9d82aa17
ED		 1170 if (HAS_PCH_LPT(dev_priv->dev)) {
1171 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1172 return;
1173 }
1174
92f2584a
JB		 1175 val = I915_READ(PCH_DREF_CONTROL);
1176 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1177 DREF_SUPERSPREAD_SOURCE_MASK));
1178 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1179}
1180
ab9412ba
DV		 1181static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1182 enum pipe pipe)
92f2584a
JB		 1183{
1184 int reg;
1185 u32 val;
1186 bool enabled;
1187
ab9412ba 1188 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1189 val = I915_READ(reg);
1190 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1191 WARN(enabled,
1192 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1193 pipe_name(pipe));
92f2584a
JB		 1194}
1195
4e634389
KP		 1196static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1197 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1198{
1199 if ((val & DP_PORT_EN) == 0)
1200 return false;
1201
1202 if (HAS_PCH_CPT(dev_priv->dev)) {
1203 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1204 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1205 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1206 return false;
1207 } else {
1208 if ((val & DP_PIPE_MASK) != (pipe << 30))
1209 return false;
1210 }
1211 return true;
1212}
1213
1519b995
KP		 1214static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1215 enum pipe pipe, u32 val)
1216{
dc0fa718 1217 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1218 return false;
1219
1220 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1221 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1222 return false;
1223 } else {
dc0fa718 1224 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1225 return false;
1226 }
1227 return true;
1228}
1229
1230static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe, u32 val)
1232{
1233 if ((val & LVDS_PORT_EN) == 0)
1234 return false;
1235
1236 if (HAS_PCH_CPT(dev_priv->dev)) {
1237 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1238 return false;
1239 } else {
1240 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1241 return false;
1242 }
1243 return true;
1244}
1245
1246static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, u32 val)
1248{
1249 if ((val & ADPA_DAC_ENABLE) == 0)
1250 return false;
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1253 return false;
1254 } else {
1255 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1256 return false;
1257 }
1258 return true;
1259}
1260
291906f1 1261static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1262 enum pipe pipe, int reg, u32 port_sel)
291906f1 1263{
47a05eca 1264 u32 val = I915_READ(reg);
4e634389 1265 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1266 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1267 reg, pipe_name(pipe));
de9a35ab 1268
75c5da27
DV		 1269 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1270 && (val & DP_PIPEB_SELECT),
de9a35ab 1271 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1272}
1273
1274static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, int reg)
1276{
47a05eca 1277 u32 val = I915_READ(reg);
b70ad586 1278 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1279 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1280 reg, pipe_name(pipe));
de9a35ab 1281
dc0fa718 1282 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1283 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1284 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1285}
1286
1287static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1288 enum pipe pipe)
1289{
1290 int reg;
1291 u32 val;
291906f1 1292
f0575e92
KP		 1293 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1294 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1295 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1296
1297 reg = PCH_ADPA;
1298 val = I915_READ(reg);
b70ad586 1299 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1300 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1301 pipe_name(pipe));
291906f1
JB		 1302
1303 reg = PCH_LVDS;
1304 val = I915_READ(reg);
b70ad586 1305 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1306 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1307 pipe_name(pipe));
291906f1 1308
e2debe91
PZ		 1309 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1310 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1311 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1312}
1313
63d7bbe9
JB		 1314/**
1315 * intel_enable_pll - enable a PLL
1316 * @dev_priv: i915 private structure
1317 * @pipe: pipe PLL to enable
1318 *
1319 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1320 * make sure the PLL reg is writable first though, since the panel write
1321 * protect mechanism may be enabled.
1322 *
1323 * Note! This is for pre-ILK only.
7434a255
TR		 1324 *
1325 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1326 */
1327static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1328{
1329 int reg;
1330 u32 val;
1331
58c6eaa2
DV		 1332 assert_pipe_disabled(dev_priv, pipe);
1333
63d7bbe9 1334 /* No really, not for ILK+ */
a0c4da24 1335 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1336
1337 /* PLL is protected by panel, make sure we can write it */
1338 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1339 assert_panel_unlocked(dev_priv, pipe);
1340
1341 reg = DPLL(pipe);
1342 val = I915_READ(reg);
1343 val |= DPLL_VCO_ENABLE;
1344
1345 /* We do this three times for luck */
1346 I915_WRITE(reg, val);
1347 POSTING_READ(reg);
1348 udelay(150); /* wait for warmup */
1349 I915_WRITE(reg, val);
1350 POSTING_READ(reg);
1351 udelay(150); /* wait for warmup */
1352 I915_WRITE(reg, val);
1353 POSTING_READ(reg);
1354 udelay(150); /* wait for warmup */
1355}
1356
1357/**
1358 * intel_disable_pll - disable a PLL
1359 * @dev_priv: i915 private structure
1360 * @pipe: pipe PLL to disable
1361 *
1362 * Disable the PLL for @pipe, making sure the pipe is off first.
1363 *
1364 * Note! This is for pre-ILK only.
1365 */
1366static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1367{
1368 int reg;
1369 u32 val;
1370
1371 /* Don't disable pipe A or pipe A PLLs if needed */
1372 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1373 return;
1374
1375 /* Make sure the pipe isn't still relying on us */
1376 assert_pipe_disabled(dev_priv, pipe);
1377
1378 reg = DPLL(pipe);
1379 val = I915_READ(reg);
1380 val &= ~DPLL_VCO_ENABLE;
1381 I915_WRITE(reg, val);
1382 POSTING_READ(reg);
1383}
1384
89b667f8
JB		 1385void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1386{
1387 u32 port_mask;
1388
1389 if (!port)
1390 port_mask = DPLL_PORTB_READY_MASK;
1391 else
1392 port_mask = DPLL_PORTC_READY_MASK;
1393
1394 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1395 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1396 'B' + port, I915_READ(DPLL(0)));
1397}
1398
92f2584a 1399/**
b6b4e185 1400 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1401 * @dev_priv: i915 private structure
1402 * @pipe: pipe PLL to enable
1403 *
1404 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1405 * drives the transcoder clock.
1406 */
b6b4e185 1407static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1408{
ee7b9f93 1409 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1410 struct intel_pch_pll *pll;
92f2584a
JB		 1411 int reg;
1412 u32 val;
1413
48da64a8 1414 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1415 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1416 pll = intel_crtc->pch_pll;
1417 if (pll == NULL)
1418 return;
1419
1420 if (WARN_ON(pll->refcount == 0))
1421 return;
ee7b9f93
JB		 1422
1423 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1424 pll->pll_reg, pll->active, pll->on,
1425 intel_crtc->base.base.id);
92f2584a
JB		 1426
1427 /* PCH refclock must be enabled first */
1428 assert_pch_refclk_enabled(dev_priv);
1429
cdbd2316
DV		 1430 if (pll->active++) {
1431 WARN_ON(!pll->on);
92b27b08 1432 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1433 return;
1434 }
1435
1436 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1437
1438 reg = pll->pll_reg;
92f2584a
JB		 1439 val = I915_READ(reg);
1440 val |= DPLL_VCO_ENABLE;
1441 I915_WRITE(reg, val);
1442 POSTING_READ(reg);
1443 udelay(200);
ee7b9f93
JB		 1444
1445 pll->on = true;
92f2584a
JB		 1446}
1447
ee7b9f93 1448static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1449{
ee7b9f93
JB		 1450 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1451 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1452 int reg;
ee7b9f93 1453 u32 val;
4c609cb8 1454
92f2584a
JB		 1455 /* PCH only available on ILK+ */
1456 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1457 if (pll == NULL)
1458 return;
92f2584a 1459
48da64a8
CW		 1460 if (WARN_ON(pll->refcount == 0))
1461 return;
7a419866 1462
ee7b9f93
JB		 1463 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1464 pll->pll_reg, pll->active, pll->on,
1465 intel_crtc->base.base.id);
7a419866 1466
48da64a8 1467 if (WARN_ON(pll->active == 0)) {
92b27b08 1468 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1469 return;
1470 }
1471
cdbd2316
DV		 1472 assert_pch_pll_enabled(dev_priv, pll, NULL);
1473 if (--pll->active)
7a419866 1474 return;
ee7b9f93
JB		 1475
1476 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1477
1478 /* Make sure transcoder isn't still depending on us */
ab9412ba 1479 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1480
ee7b9f93 1481 reg = pll->pll_reg;
92f2584a
JB		 1482 val = I915_READ(reg);
1483 val &= ~DPLL_VCO_ENABLE;
1484 I915_WRITE(reg, val);
1485 POSTING_READ(reg);
1486 udelay(200);
ee7b9f93
JB		 1487
1488 pll->on = false;
92f2584a
JB		 1489}
1490
b8a4f404
PZ		 1491static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1492 enum pipe pipe)
040484af 1493{
23670b32 1494 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1495 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1496 uint32_t reg, val, pipeconf_val;
040484af
JB		 1497
1498 /* PCH only available on ILK+ */
1499 BUG_ON(dev_priv->info->gen < 5);
1500
1501 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1502 assert_pch_pll_enabled(dev_priv,
1503 to_intel_crtc(crtc)->pch_pll,
1504 to_intel_crtc(crtc));
040484af
JB		 1505
1506 /* FDI must be feeding us bits for PCH ports */
1507 assert_fdi_tx_enabled(dev_priv, pipe);
1508 assert_fdi_rx_enabled(dev_priv, pipe);
1509
23670b32
DV		 1510 if (HAS_PCH_CPT(dev)) {
1511 /* Workaround: Set the timing override bit before enabling the
1512 * pch transcoder. */
1513 reg = TRANS_CHICKEN2(pipe);
1514 val = I915_READ(reg);
1515 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1516 I915_WRITE(reg, val);
59c859d6 1517 }
23670b32 1518
ab9412ba 1519 reg = PCH_TRANSCONF(pipe);
040484af 1520 val = I915_READ(reg);
5f7f726d 1521 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1522
1523 if (HAS_PCH_IBX(dev_priv->dev)) {
1524 /*
1525 * make the BPC in transcoder be consistent with
1526 * that in pipeconf reg.
1527 */
dfd07d72
DV		 1528 val &= ~PIPECONF_BPC_MASK;
1529 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1530 }
5f7f726d
PZ		 1531
1532 val &= ~TRANS_INTERLACE_MASK;
1533 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1534 if (HAS_PCH_IBX(dev_priv->dev) &&
1535 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1536 val |= TRANS_LEGACY_INTERLACED_ILK;
1537 else
1538 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1539 else
1540 val |= TRANS_PROGRESSIVE;
1541
040484af
JB		 1542 I915_WRITE(reg, val | TRANS_ENABLE);
1543 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1544 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1545}
1546
8fb033d7 1547static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1548 enum transcoder cpu_transcoder)
040484af 1549{
8fb033d7 1550 u32 val, pipeconf_val;
8fb033d7
PZ		 1551
1552 /* PCH only available on ILK+ */
1553 BUG_ON(dev_priv->info->gen < 5);
1554
8fb033d7 1555 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1556 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1557 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1558
223a6fdf
PZ		 1559 /* Workaround: set timing override bit. */
1560 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1561 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1562 I915_WRITE(_TRANSA_CHICKEN2, val);
1563
25f3ef11 1564 val = TRANS_ENABLE;
937bb610 1565 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1566
9a76b1c6
PZ		 1567 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1568 PIPECONF_INTERLACED_ILK)
a35f2679 1569 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1570 else
1571 val |= TRANS_PROGRESSIVE;
1572
ab9412ba
DV		 1573 I915_WRITE(LPT_TRANSCONF, val);
1574 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1575 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1576}
1577
b8a4f404
PZ		 1578static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1579 enum pipe pipe)
040484af 1580{
23670b32
DV		 1581 struct drm_device *dev = dev_priv->dev;
1582 uint32_t reg, val;
040484af
JB		 1583
1584 /* FDI relies on the transcoder */
1585 assert_fdi_tx_disabled(dev_priv, pipe);
1586 assert_fdi_rx_disabled(dev_priv, pipe);
1587
291906f1
JB		 1588 /* Ports must be off as well */
1589 assert_pch_ports_disabled(dev_priv, pipe);
1590
ab9412ba 1591 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1592 val = I915_READ(reg);
1593 val &= ~TRANS_ENABLE;
1594 I915_WRITE(reg, val);
1595 /* wait for PCH transcoder off, transcoder state */
1596 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1597 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1598
1599 if (!HAS_PCH_IBX(dev)) {
1600 /* Workaround: Clear the timing override chicken bit again. */
1601 reg = TRANS_CHICKEN2(pipe);
1602 val = I915_READ(reg);
1603 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1604 I915_WRITE(reg, val);
1605 }
040484af
JB		 1606}
1607
ab4d966c 1608static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1609{
8fb033d7
PZ		 1610 u32 val;
1611
ab9412ba 1612 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1613 val &= ~TRANS_ENABLE;
ab9412ba 1614 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1615 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1616 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1617 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1618
1619 /* Workaround: clear timing override bit. */
1620 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1621 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1622 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1623}
1624
b24e7179 1625/**
309cfea8 1626 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1627 * @dev_priv: i915 private structure
1628 * @pipe: pipe to enable
040484af 1629 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1630 *
1631 * Enable @pipe, making sure that various hardware specific requirements
1632 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1633 *
1634 * @pipe should be %PIPE_A or %PIPE_B.
1635 *
1636 * Will wait until the pipe is actually running (i.e. first vblank) before
1637 * returning.
1638 */
040484af
JB		 1639static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1640 bool pch_port)
b24e7179 1641{
702e7a56
PZ		 1642 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1643 pipe);
1a240d4d 1644 enum pipe pch_transcoder;
b24e7179
JB		 1645 int reg;
1646 u32 val;
1647
58c6eaa2
DV		 1648 assert_planes_disabled(dev_priv, pipe);
1649 assert_sprites_disabled(dev_priv, pipe);
1650
681e5811 1651 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1652 pch_transcoder = TRANSCODER_A;
1653 else
1654 pch_transcoder = pipe;
1655
b24e7179
JB		 1656 /*
1657 * A pipe without a PLL won't actually be able to drive bits from
1658 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1659 * need the check.
1660 */
1661 if (!HAS_PCH_SPLIT(dev_priv->dev))
1662 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1663 else {
1664 if (pch_port) {
1665 /* if driving the PCH, we need FDI enabled */
cc391bbb 1666 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1667 assert_fdi_tx_pll_enabled(dev_priv,
1668 (enum pipe) cpu_transcoder);
040484af
JB		 1669 }
1670 /* FIXME: assert CPU port conditions for SNB+ */
1671 }
b24e7179 1672
702e7a56 1673 reg = PIPECONF(cpu_transcoder);
b24e7179 1674 val = I915_READ(reg);
00d70b15
CW		 1675 if (val & PIPECONF_ENABLE)
1676 return;
1677
1678 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1679 intel_wait_for_vblank(dev_priv->dev, pipe);
1680}
1681
1682/**
309cfea8 1683 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1684 * @dev_priv: i915 private structure
1685 * @pipe: pipe to disable
1686 *
1687 * Disable @pipe, making sure that various hardware specific requirements
1688 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1689 *
1690 * @pipe should be %PIPE_A or %PIPE_B.
1691 *
1692 * Will wait until the pipe has shut down before returning.
1693 */
1694static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1695 enum pipe pipe)
1696{
702e7a56
PZ		 1697 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1698 pipe);
b24e7179
JB		 1699 int reg;
1700 u32 val;
1701
1702 /*
1703 * Make sure planes won't keep trying to pump pixels to us,
1704 * or we might hang the display.
1705 */
1706 assert_planes_disabled(dev_priv, pipe);
19332d7a 1707 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1708
1709 /* Don't disable pipe A or pipe A PLLs if needed */
1710 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1711 return;
1712
702e7a56 1713 reg = PIPECONF(cpu_transcoder);
b24e7179 1714 val = I915_READ(reg);
00d70b15
CW		 1715 if ((val & PIPECONF_ENABLE) == 0)
1716 return;
1717
1718 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1719 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1720}
1721
d74362c9
KP		 1722/*
1723 * Plane regs are double buffered, going from enabled->disabled needs a
1724 * trigger in order to latch. The display address reg provides this.
1725 */
6f1d69b0 1726void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1727 enum plane plane)
1728{
14f86147
DL		 1729 if (dev_priv->info->gen >= 4)
1730 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1731 else
1732 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1733}
1734
b24e7179
JB		 1735/**
1736 * intel_enable_plane - enable a display plane on a given pipe
1737 * @dev_priv: i915 private structure
1738 * @plane: plane to enable
1739 * @pipe: pipe being fed
1740 *
1741 * Enable @plane on @pipe, making sure that @pipe is running first.
1742 */
1743static void intel_enable_plane(struct drm_i915_private *dev_priv,
1744 enum plane plane, enum pipe pipe)
1745{
1746 int reg;
1747 u32 val;
1748
1749 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1750 assert_pipe_enabled(dev_priv, pipe);
1751
1752 reg = DSPCNTR(plane);
1753 val = I915_READ(reg);
00d70b15
CW		 1754 if (val & DISPLAY_PLANE_ENABLE)
1755 return;
1756
1757 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1758 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1759 intel_wait_for_vblank(dev_priv->dev, pipe);
1760}
1761
b24e7179
JB		 1762/**
1763 * intel_disable_plane - disable a display plane
1764 * @dev_priv: i915 private structure
1765 * @plane: plane to disable
1766 * @pipe: pipe consuming the data
1767 *
1768 * Disable @plane; should be an independent operation.
1769 */
1770static void intel_disable_plane(struct drm_i915_private *dev_priv,
1771 enum plane plane, enum pipe pipe)
1772{
1773 int reg;
1774 u32 val;
1775
1776 reg = DSPCNTR(plane);
1777 val = I915_READ(reg);
00d70b15
CW		 1778 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1779 return;
1780
1781 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1782 intel_flush_display_plane(dev_priv, plane);
1783 intel_wait_for_vblank(dev_priv->dev, pipe);
1784}
1785
693db184
CW		 1786static bool need_vtd_wa(struct drm_device *dev)
1787{
1788#ifdef CONFIG_INTEL_IOMMU
1789 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1790 return true;
1791#endif
1792 return false;
1793}
1794
127bd2ac 1795int
48b956c5 1796intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1797 struct drm_i915_gem_object *obj,
919926ae 1798 struct intel_ring_buffer *pipelined)
6b95a207 1799{
ce453d81 1800 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1801 u32 alignment;
1802 int ret;
1803
05394f39 1804 switch (obj->tiling_mode) {
6b95a207 1805 case I915_TILING_NONE:
534843da
CW		 1806 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1807 alignment = 128 * 1024;
a6c45cf0 1808 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1809 alignment = 4 * 1024;
1810 else
1811 alignment = 64 * 1024;
6b95a207
KH		 1812 break;
1813 case I915_TILING_X:
1814 /* pin() will align the object as required by fence */
1815 alignment = 0;
1816 break;
1817 case I915_TILING_Y:
8bb6e959
DV		 1818 /* Despite that we check this in framebuffer_init userspace can
1819 * screw us over and change the tiling after the fact. Only
1820 * pinned buffers can't change their tiling. */
1821 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1822 return -EINVAL;
1823 default:
1824 BUG();
1825 }
1826
693db184
CW		 1827 /* Note that the w/a also requires 64 PTE of padding following the
1828 * bo. We currently fill all unused PTE with the shadow page and so
1829 * we should always have valid PTE following the scanout preventing
1830 * the VT-d warning.
1831 */
1832 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1833 alignment = 256 * 1024;
1834
ce453d81 1835 dev_priv->mm.interruptible = false;
2da3b9b9 1836 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1837 if (ret)
ce453d81 1838 goto err_interruptible;
6b95a207
KH		 1839
1840 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1841 * fence, whereas 965+ only requires a fence if using
1842 * framebuffer compression. For simplicity, we always install
1843 * a fence as the cost is not that onerous.
1844 */
06d98131 1845 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1846 if (ret)
1847 goto err_unpin;
1690e1eb 1848
9a5a53b3 1849 i915_gem_object_pin_fence(obj);
6b95a207 1850
ce453d81 1851 dev_priv->mm.interruptible = true;
6b95a207 1852 return 0;
48b956c5
CW		 1853
1854err_unpin:
1855 i915_gem_object_unpin(obj);
ce453d81
CW		 1856err_interruptible:
1857 dev_priv->mm.interruptible = true;
48b956c5 1858 return ret;
6b95a207
KH		 1859}
1860
1690e1eb
CW		 1861void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1862{
1863 i915_gem_object_unpin_fence(obj);
1864 i915_gem_object_unpin(obj);
1865}
1866
c2c75131
DV		 1867/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1868 * is assumed to be a power-of-two. */
bc752862
CW		 1869unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1870 unsigned int tiling_mode,
1871 unsigned int cpp,
1872 unsigned int pitch)
c2c75131 1873{
bc752862
CW		 1874 if (tiling_mode != I915_TILING_NONE) {
1875 unsigned int tile_rows, tiles;
c2c75131 1876
bc752862
CW		 1877 tile_rows = *y / 8;
1878 *y %= 8;
c2c75131 1879
bc752862
CW		 1880 tiles = *x / (512/cpp);
1881 *x %= 512/cpp;
1882
1883 return tile_rows * pitch * 8 + tiles * 4096;
1884 } else {
1885 unsigned int offset;
1886
1887 offset = *y * pitch + *x * cpp;
1888 *y = 0;
1889 *x = (offset & 4095) / cpp;
1890 return offset & -4096;
1891 }
c2c75131
DV		 1892}
1893
17638cd6
JB		 1894static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1895 int x, int y)
81255565
JB		 1896{
1897 struct drm_device *dev = crtc->dev;
1898 struct drm_i915_private *dev_priv = dev->dev_private;
1899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1900 struct intel_framebuffer *intel_fb;
05394f39 1901 struct drm_i915_gem_object *obj;
81255565 1902 int plane = intel_crtc->plane;
e506a0c6 1903 unsigned long linear_offset;
81255565 1904 u32 dspcntr;
5eddb70b 1905 u32 reg;
81255565
JB		 1906
1907 switch (plane) {
1908 case 0:
1909 case 1:
1910 break;
1911 default:
84f44ce7 1912 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1913 return -EINVAL;
1914 }
1915
1916 intel_fb = to_intel_framebuffer(fb);
1917 obj = intel_fb->obj;
81255565 1918
5eddb70b
CW		 1919 reg = DSPCNTR(plane);
1920 dspcntr = I915_READ(reg);
81255565
JB		 1921 /* Mask out pixel format bits in case we change it */
1922 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1923 switch (fb->pixel_format) {
1924 case DRM_FORMAT_C8:
81255565
JB		 1925 dspcntr |= DISPPLANE_8BPP;
1926 break;
57779d06
VS		 1927 case DRM_FORMAT_XRGB1555:
1928 case DRM_FORMAT_ARGB1555:
1929 dspcntr |= DISPPLANE_BGRX555;
81255565 1930 break;
57779d06
VS		 1931 case DRM_FORMAT_RGB565:
1932 dspcntr |= DISPPLANE_BGRX565;
1933 break;
1934 case DRM_FORMAT_XRGB8888:
1935 case DRM_FORMAT_ARGB8888:
1936 dspcntr |= DISPPLANE_BGRX888;
1937 break;
1938 case DRM_FORMAT_XBGR8888:
1939 case DRM_FORMAT_ABGR8888:
1940 dspcntr |= DISPPLANE_RGBX888;
1941 break;
1942 case DRM_FORMAT_XRGB2101010:
1943 case DRM_FORMAT_ARGB2101010:
1944 dspcntr |= DISPPLANE_BGRX101010;
1945 break;
1946 case DRM_FORMAT_XBGR2101010:
1947 case DRM_FORMAT_ABGR2101010:
1948 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1949 break;
1950 default:
baba133a 1951 BUG();
81255565 1952 }
57779d06 1953
a6c45cf0 1954 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1955 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1956 dspcntr |= DISPPLANE_TILED;
1957 else
1958 dspcntr &= ~DISPPLANE_TILED;
1959 }
1960
de1aa629
VS		 1961 if (IS_G4X(dev))
1962 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1963
5eddb70b 1964 I915_WRITE(reg, dspcntr);
81255565 1965
e506a0c6 1966 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1967
c2c75131
DV		 1968 if (INTEL_INFO(dev)->gen >= 4) {
1969 intel_crtc->dspaddr_offset =
bc752862
CW		 1970 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1971 fb->bits_per_pixel / 8,
1972 fb->pitches[0]);
c2c75131
DV		 1973 linear_offset -= intel_crtc->dspaddr_offset;
1974 } else {
e506a0c6 1975 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1976 }
e506a0c6
DV		 1977
1978 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1979 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1980 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1981 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1982 I915_MODIFY_DISPBASE(DSPSURF(plane),
1983 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1984 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1985 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1986 } else
e506a0c6 1987 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 1988 POSTING_READ(reg);
81255565 1989
17638cd6
JB		 1990 return 0;
1991}
1992
1993static int ironlake_update_plane(struct drm_crtc *crtc,
1994 struct drm_framebuffer *fb, int x, int y)
1995{
1996 struct drm_device *dev = crtc->dev;
1997 struct drm_i915_private *dev_priv = dev->dev_private;
1998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1999 struct intel_framebuffer *intel_fb;
2000 struct drm_i915_gem_object *obj;
2001 int plane = intel_crtc->plane;
e506a0c6 2002 unsigned long linear_offset;
17638cd6
JB		 2003 u32 dspcntr;
2004 u32 reg;
2005
2006 switch (plane) {
2007 case 0:
2008 case 1:
27f8227b 2009 case 2:
17638cd6
JB		 2010 break;
2011 default:
84f44ce7 2012 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2013 return -EINVAL;
2014 }
2015
2016 intel_fb = to_intel_framebuffer(fb);
2017 obj = intel_fb->obj;
2018
2019 reg = DSPCNTR(plane);
2020 dspcntr = I915_READ(reg);
2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2023 switch (fb->pixel_format) {
2024 case DRM_FORMAT_C8:
17638cd6
JB		 2025 dspcntr |= DISPPLANE_8BPP;
2026 break;
57779d06
VS		 2027 case DRM_FORMAT_RGB565:
2028 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2029 break;
57779d06
VS		 2030 case DRM_FORMAT_XRGB8888:
2031 case DRM_FORMAT_ARGB8888:
2032 dspcntr |= DISPPLANE_BGRX888;
2033 break;
2034 case DRM_FORMAT_XBGR8888:
2035 case DRM_FORMAT_ABGR8888:
2036 dspcntr |= DISPPLANE_RGBX888;
2037 break;
2038 case DRM_FORMAT_XRGB2101010:
2039 case DRM_FORMAT_ARGB2101010:
2040 dspcntr |= DISPPLANE_BGRX101010;
2041 break;
2042 case DRM_FORMAT_XBGR2101010:
2043 case DRM_FORMAT_ABGR2101010:
2044 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2045 break;
2046 default:
baba133a 2047 BUG();
17638cd6
JB		 2048 }
2049
2050 if (obj->tiling_mode != I915_TILING_NONE)
2051 dspcntr |= DISPPLANE_TILED;
2052 else
2053 dspcntr &= ~DISPPLANE_TILED;
2054
2055 /* must disable */
2056 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2057
2058 I915_WRITE(reg, dspcntr);
2059
e506a0c6 2060 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2061 intel_crtc->dspaddr_offset =
bc752862
CW		 2062 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2063 fb->bits_per_pixel / 8,
2064 fb->pitches[0]);
c2c75131 2065 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2066
e506a0c6
DV		 2067 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2068 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2069 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2070 I915_MODIFY_DISPBASE(DSPSURF(plane),
2071 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2072 if (IS_HASWELL(dev)) {
2073 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2074 } else {
2075 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2076 I915_WRITE(DSPLINOFF(plane), linear_offset);
2077 }
17638cd6
JB		 2078 POSTING_READ(reg);
2079
2080 return 0;
2081}
2082
2083/* Assume fb object is pinned & idle & fenced and just update base pointers */
2084static int
2085intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2086 int x, int y, enum mode_set_atomic state)
2087{
2088 struct drm_device *dev = crtc->dev;
2089 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2090
6b8e6ed0
CW		 2091 if (dev_priv->display.disable_fbc)
2092 dev_priv->display.disable_fbc(dev);
3dec0095 2093 intel_increase_pllclock(crtc);
81255565 2094
6b8e6ed0 2095 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2096}
2097
96a02917
VS		 2098void intel_display_handle_reset(struct drm_device *dev)
2099{
2100 struct drm_i915_private *dev_priv = dev->dev_private;
2101 struct drm_crtc *crtc;
2102
2103 /*
2104 * Flips in the rings have been nuked by the reset,
2105 * so complete all pending flips so that user space
2106 * will get its events and not get stuck.
2107 *
2108 * Also update the base address of all primary
2109 * planes to the the last fb to make sure we're
2110 * showing the correct fb after a reset.
2111 *
2112 * Need to make two loops over the crtcs so that we
2113 * don't try to grab a crtc mutex before the
2114 * pending_flip_queue really got woken up.
2115 */
2116
2117 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2119 enum plane plane = intel_crtc->plane;
2120
2121 intel_prepare_page_flip(dev, plane);
2122 intel_finish_page_flip_plane(dev, plane);
2123 }
2124
2125 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2127
2128 mutex_lock(&crtc->mutex);
2129 if (intel_crtc->active)
2130 dev_priv->display.update_plane(crtc, crtc->fb,
2131 crtc->x, crtc->y);
2132 mutex_unlock(&crtc->mutex);
2133 }
2134}
2135
14667a4b
CW		 2136static int
2137intel_finish_fb(struct drm_framebuffer *old_fb)
2138{
2139 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2140 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2141 bool was_interruptible = dev_priv->mm.interruptible;
2142 int ret;
2143
14667a4b
CW		 2144 /* Big Hammer, we also need to ensure that any pending
2145 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2146 * current scanout is retired before unpinning the old
2147 * framebuffer.
2148 *
2149 * This should only fail upon a hung GPU, in which case we
2150 * can safely continue.
2151 */
2152 dev_priv->mm.interruptible = false;
2153 ret = i915_gem_object_finish_gpu(obj);
2154 dev_priv->mm.interruptible = was_interruptible;
2155
2156 return ret;
2157}
2158
198598d0
VS		 2159static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2160{
2161 struct drm_device *dev = crtc->dev;
2162 struct drm_i915_master_private *master_priv;
2163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2164
2165 if (!dev->primary->master)
2166 return;
2167
2168 master_priv = dev->primary->master->driver_priv;
2169 if (!master_priv->sarea_priv)
2170 return;
2171
2172 switch (intel_crtc->pipe) {
2173 case 0:
2174 master_priv->sarea_priv->pipeA_x = x;
2175 master_priv->sarea_priv->pipeA_y = y;
2176 break;
2177 case 1:
2178 master_priv->sarea_priv->pipeB_x = x;
2179 master_priv->sarea_priv->pipeB_y = y;
2180 break;
2181 default:
2182 break;
2183 }
2184}
2185
5c3b82e2 2186static int
3c4fdcfb 2187intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2188 struct drm_framebuffer *fb)
79e53945
JB		 2189{
2190 struct drm_device *dev = crtc->dev;
6b8e6ed0 2191 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2193 struct drm_framebuffer *old_fb;
5c3b82e2 2194 int ret;
79e53945
JB		 2195
2196 /* no fb bound */
94352cf9 2197 if (!fb) {
a5071c2f 2198 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2199 return 0;
2200 }
2201
7eb552ae 2202 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2203 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2204 plane_name(intel_crtc->plane),
2205 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2206 return -EINVAL;
79e53945
JB		 2207 }
2208
5c3b82e2 2209 mutex_lock(&dev->struct_mutex);
265db958 2210 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2211 to_intel_framebuffer(fb)->obj,
919926ae 2212 NULL);
5c3b82e2
CW		 2213 if (ret != 0) {
2214 mutex_unlock(&dev->struct_mutex);
a5071c2f 2215 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2216 return ret;
2217 }
79e53945 2218
94352cf9 2219 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2220 if (ret) {
94352cf9 2221 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2222 mutex_unlock(&dev->struct_mutex);
a5071c2f 2223 DRM_ERROR("failed to update base address\n");
4e6cfefc 2224 return ret;
79e53945 2225 }
3c4fdcfb 2226
94352cf9
DV		 2227 old_fb = crtc->fb;
2228 crtc->fb = fb;
6c4c86f5
DV		 2229 crtc->x = x;
2230 crtc->y = y;
94352cf9 2231
b7f1de28 2232 if (old_fb) {
d7697eea
DV		 2233 if (intel_crtc->active && old_fb != fb)
2234 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2235 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2236 }
652c393a 2237
6b8e6ed0 2238 intel_update_fbc(dev);
5c3b82e2 2239 mutex_unlock(&dev->struct_mutex);
79e53945 2240
198598d0 2241 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2242
2243 return 0;
79e53945
JB		 2244}
2245
5e84e1a4
ZW		 2246static void intel_fdi_normal_train(struct drm_crtc *crtc)
2247{
2248 struct drm_device *dev = crtc->dev;
2249 struct drm_i915_private *dev_priv = dev->dev_private;
2250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2251 int pipe = intel_crtc->pipe;
2252 u32 reg, temp;
2253
2254 /* enable normal train */
2255 reg = FDI_TX_CTL(pipe);
2256 temp = I915_READ(reg);
61e499bf 2257 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2258 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2259 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2260 } else {
2261 temp &= ~FDI_LINK_TRAIN_NONE;
2262 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2263 }
5e84e1a4
ZW		 2264 I915_WRITE(reg, temp);
2265
2266 reg = FDI_RX_CTL(pipe);
2267 temp = I915_READ(reg);
2268 if (HAS_PCH_CPT(dev)) {
2269 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2270 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2271 } else {
2272 temp &= ~FDI_LINK_TRAIN_NONE;
2273 temp |= FDI_LINK_TRAIN_NONE;
2274 }
2275 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2276
2277 /* wait one idle pattern time */
2278 POSTING_READ(reg);
2279 udelay(1000);
357555c0
JB		 2280
2281 /* IVB wants error correction enabled */
2282 if (IS_IVYBRIDGE(dev))
2283 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2284 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2285}
2286
1e833f40
DV		 2287static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2288{
2289 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2290}
2291
01a415fd
DV		 2292static void ivb_modeset_global_resources(struct drm_device *dev)
2293{
2294 struct drm_i915_private *dev_priv = dev->dev_private;
2295 struct intel_crtc *pipe_B_crtc =
2296 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2297 struct intel_crtc *pipe_C_crtc =
2298 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2299 uint32_t temp;
2300
1e833f40
DV		 2301 /*
2302 * When everything is off disable fdi C so that we could enable fdi B
2303 * with all lanes. Note that we don't care about enabled pipes without
2304 * an enabled pch encoder.
2305 */
2306 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2307 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2308 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2309 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2310
2311 temp = I915_READ(SOUTH_CHICKEN1);
2312 temp &= ~FDI_BC_BIFURCATION_SELECT;
2313 DRM_DEBUG_KMS("disabling fdi C rx\n");
2314 I915_WRITE(SOUTH_CHICKEN1, temp);
2315 }
2316}
2317
8db9d77b
ZW		 2318/* The FDI link training functions for ILK/Ibexpeak. */
2319static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2320{
2321 struct drm_device *dev = crtc->dev;
2322 struct drm_i915_private *dev_priv = dev->dev_private;
2323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2324 int pipe = intel_crtc->pipe;
0fc932b8 2325 int plane = intel_crtc->plane;
5eddb70b 2326 u32 reg, temp, tries;
8db9d77b 2327
0fc932b8
JB		 2328 /* FDI needs bits from pipe & plane first */
2329 assert_pipe_enabled(dev_priv, pipe);
2330 assert_plane_enabled(dev_priv, plane);
2331
e1a44743
AJ		 2332 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2333 for train result */
5eddb70b
CW		 2334 reg = FDI_RX_IMR(pipe);
2335 temp = I915_READ(reg);
e1a44743
AJ		 2336 temp &= ~FDI_RX_SYMBOL_LOCK;
2337 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2338 I915_WRITE(reg, temp);
2339 I915_READ(reg);
e1a44743
AJ		 2340 udelay(150);
2341
8db9d77b 2342 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2343 reg = FDI_TX_CTL(pipe);
2344 temp = I915_READ(reg);
627eb5a3
DV		 2345 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2346 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2347 temp &= ~FDI_LINK_TRAIN_NONE;
2348 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2349 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2350
5eddb70b
CW		 2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
8db9d77b
ZW		 2353 temp &= ~FDI_LINK_TRAIN_NONE;
2354 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2355 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2356
2357 POSTING_READ(reg);
8db9d77b
ZW		 2358 udelay(150);
2359
5b2adf89 2360 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2361 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2362 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2363 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2364
5eddb70b 2365 reg = FDI_RX_IIR(pipe);
e1a44743 2366 for (tries = 0; tries < 5; tries++) {
5eddb70b 2367 temp = I915_READ(reg);
8db9d77b
ZW		 2368 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2369
2370 if ((temp & FDI_RX_BIT_LOCK)) {
2371 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2372 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2373 break;
2374 }
8db9d77b 2375 }
e1a44743 2376 if (tries == 5)
5eddb70b 2377 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2378
2379 /* Train 2 */
5eddb70b
CW		 2380 reg = FDI_TX_CTL(pipe);
2381 temp = I915_READ(reg);
8db9d77b
ZW		 2382 temp &= ~FDI_LINK_TRAIN_NONE;
2383 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2384 I915_WRITE(reg, temp);
8db9d77b 2385
5eddb70b
CW		 2386 reg = FDI_RX_CTL(pipe);
2387 temp = I915_READ(reg);
8db9d77b
ZW		 2388 temp &= ~FDI_LINK_TRAIN_NONE;
2389 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2390 I915_WRITE(reg, temp);
8db9d77b 2391
5eddb70b
CW		 2392 POSTING_READ(reg);
2393 udelay(150);
8db9d77b 2394
5eddb70b 2395 reg = FDI_RX_IIR(pipe);
e1a44743 2396 for (tries = 0; tries < 5; tries++) {
5eddb70b 2397 temp = I915_READ(reg);
8db9d77b
ZW		 2398 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2399
2400 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2401 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2402 DRM_DEBUG_KMS("FDI train 2 done.\n");
2403 break;
2404 }
8db9d77b 2405 }
e1a44743 2406 if (tries == 5)
5eddb70b 2407 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2408
2409 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2410
8db9d77b
ZW		 2411}
2412
0206e353 2413static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2414 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2415 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2416 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2417 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2418};
2419
2420/* The FDI link training functions for SNB/Cougarpoint. */
2421static void gen6_fdi_link_train(struct drm_crtc *crtc)
2422{
2423 struct drm_device *dev = crtc->dev;
2424 struct drm_i915_private *dev_priv = dev->dev_private;
2425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2426 int pipe = intel_crtc->pipe;
fa37d39e 2427 u32 reg, temp, i, retry;
8db9d77b 2428
e1a44743
AJ		 2429 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2430 for train result */
5eddb70b
CW		 2431 reg = FDI_RX_IMR(pipe);
2432 temp = I915_READ(reg);
e1a44743
AJ		 2433 temp &= ~FDI_RX_SYMBOL_LOCK;
2434 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2435 I915_WRITE(reg, temp);
2436
2437 POSTING_READ(reg);
e1a44743
AJ		 2438 udelay(150);
2439
8db9d77b 2440 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2441 reg = FDI_TX_CTL(pipe);
2442 temp = I915_READ(reg);
627eb5a3
DV		 2443 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2444 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2445 temp &= ~FDI_LINK_TRAIN_NONE;
2446 temp |= FDI_LINK_TRAIN_PATTERN_1;
2447 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2448 /* SNB-B */
2449 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2450 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2451
d74cf324
DV		 2452 I915_WRITE(FDI_RX_MISC(pipe),
2453 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2454
5eddb70b
CW		 2455 reg = FDI_RX_CTL(pipe);
2456 temp = I915_READ(reg);
8db9d77b
ZW		 2457 if (HAS_PCH_CPT(dev)) {
2458 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2459 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2460 } else {
2461 temp &= ~FDI_LINK_TRAIN_NONE;
2462 temp |= FDI_LINK_TRAIN_PATTERN_1;
2463 }
5eddb70b
CW		 2464 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2465
2466 POSTING_READ(reg);
8db9d77b
ZW		 2467 udelay(150);
2468
0206e353 2469 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2470 reg = FDI_TX_CTL(pipe);
2471 temp = I915_READ(reg);
8db9d77b
ZW		 2472 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2473 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2474 I915_WRITE(reg, temp);
2475
2476 POSTING_READ(reg);
8db9d77b
ZW		 2477 udelay(500);
2478
fa37d39e
SP		 2479 for (retry = 0; retry < 5; retry++) {
2480 reg = FDI_RX_IIR(pipe);
2481 temp = I915_READ(reg);
2482 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2483 if (temp & FDI_RX_BIT_LOCK) {
2484 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2485 DRM_DEBUG_KMS("FDI train 1 done.\n");
2486 break;
2487 }
2488 udelay(50);
8db9d77b 2489 }
fa37d39e
SP		 2490 if (retry < 5)
2491 break;
8db9d77b
ZW		 2492 }
2493 if (i == 4)
5eddb70b 2494 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2495
2496 /* Train 2 */
5eddb70b
CW		 2497 reg = FDI_TX_CTL(pipe);
2498 temp = I915_READ(reg);
8db9d77b
ZW		 2499 temp &= ~FDI_LINK_TRAIN_NONE;
2500 temp |= FDI_LINK_TRAIN_PATTERN_2;
2501 if (IS_GEN6(dev)) {
2502 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503 /* SNB-B */
2504 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2505 }
5eddb70b 2506 I915_WRITE(reg, temp);
8db9d77b 2507
5eddb70b
CW		 2508 reg = FDI_RX_CTL(pipe);
2509 temp = I915_READ(reg);
8db9d77b
ZW		 2510 if (HAS_PCH_CPT(dev)) {
2511 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2512 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2513 } else {
2514 temp &= ~FDI_LINK_TRAIN_NONE;
2515 temp |= FDI_LINK_TRAIN_PATTERN_2;
2516 }
5eddb70b
CW		 2517 I915_WRITE(reg, temp);
2518
2519 POSTING_READ(reg);
8db9d77b
ZW		 2520 udelay(150);
2521
0206e353 2522 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2523 reg = FDI_TX_CTL(pipe);
2524 temp = I915_READ(reg);
8db9d77b
ZW		 2525 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2526 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2527 I915_WRITE(reg, temp);
2528
2529 POSTING_READ(reg);
8db9d77b
ZW		 2530 udelay(500);
2531
fa37d39e
SP		 2532 for (retry = 0; retry < 5; retry++) {
2533 reg = FDI_RX_IIR(pipe);
2534 temp = I915_READ(reg);
2535 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2536 if (temp & FDI_RX_SYMBOL_LOCK) {
2537 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2538 DRM_DEBUG_KMS("FDI train 2 done.\n");
2539 break;
2540 }
2541 udelay(50);
8db9d77b 2542 }
fa37d39e
SP		 2543 if (retry < 5)
2544 break;
8db9d77b
ZW		 2545 }
2546 if (i == 4)
5eddb70b 2547 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2548
2549 DRM_DEBUG_KMS("FDI train done.\n");
2550}
2551
357555c0
JB		 2552/* Manual link training for Ivy Bridge A0 parts */
2553static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2554{
2555 struct drm_device *dev = crtc->dev;
2556 struct drm_i915_private *dev_priv = dev->dev_private;
2557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2558 int pipe = intel_crtc->pipe;
2559 u32 reg, temp, i;
2560
2561 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2562 for train result */
2563 reg = FDI_RX_IMR(pipe);
2564 temp = I915_READ(reg);
2565 temp &= ~FDI_RX_SYMBOL_LOCK;
2566 temp &= ~FDI_RX_BIT_LOCK;
2567 I915_WRITE(reg, temp);
2568
2569 POSTING_READ(reg);
2570 udelay(150);
2571
01a415fd
DV		 2572 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2573 I915_READ(FDI_RX_IIR(pipe)));
2574
357555c0
JB		 2575 /* enable CPU FDI TX and PCH FDI RX */
2576 reg = FDI_TX_CTL(pipe);
2577 temp = I915_READ(reg);
627eb5a3
DV		 2578 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2579 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2580 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2581 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2582 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2583 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2584 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2585 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2586
d74cf324
DV		 2587 I915_WRITE(FDI_RX_MISC(pipe),
2588 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2589
357555c0
JB		 2590 reg = FDI_RX_CTL(pipe);
2591 temp = I915_READ(reg);
2592 temp &= ~FDI_LINK_TRAIN_AUTO;
2593 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2594 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2595 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2596 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2597
2598 POSTING_READ(reg);
2599 udelay(150);
2600
0206e353 2601 for (i = 0; i < 4; i++) {
357555c0
JB		 2602 reg = FDI_TX_CTL(pipe);
2603 temp = I915_READ(reg);
2604 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2605 temp |= snb_b_fdi_train_param[i];
2606 I915_WRITE(reg, temp);
2607
2608 POSTING_READ(reg);
2609 udelay(500);
2610
2611 reg = FDI_RX_IIR(pipe);
2612 temp = I915_READ(reg);
2613 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2614
2615 if (temp & FDI_RX_BIT_LOCK ||
2616 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2617 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2618 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2619 break;
2620 }
2621 }
2622 if (i == 4)
2623 DRM_ERROR("FDI train 1 fail!\n");
2624
2625 /* Train 2 */
2626 reg = FDI_TX_CTL(pipe);
2627 temp = I915_READ(reg);
2628 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2629 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2630 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2631 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2632 I915_WRITE(reg, temp);
2633
2634 reg = FDI_RX_CTL(pipe);
2635 temp = I915_READ(reg);
2636 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2637 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2638 I915_WRITE(reg, temp);
2639
2640 POSTING_READ(reg);
2641 udelay(150);
2642
0206e353 2643 for (i = 0; i < 4; i++) {
357555c0
JB		 2644 reg = FDI_TX_CTL(pipe);
2645 temp = I915_READ(reg);
2646 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2647 temp |= snb_b_fdi_train_param[i];
2648 I915_WRITE(reg, temp);
2649
2650 POSTING_READ(reg);
2651 udelay(500);
2652
2653 reg = FDI_RX_IIR(pipe);
2654 temp = I915_READ(reg);
2655 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2656
2657 if (temp & FDI_RX_SYMBOL_LOCK) {
2658 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2659 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2660 break;
2661 }
2662 }
2663 if (i == 4)
2664 DRM_ERROR("FDI train 2 fail!\n");
2665
2666 DRM_DEBUG_KMS("FDI train done.\n");
2667}
2668
88cefb6c 2669static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2670{
88cefb6c 2671 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2672 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2673 int pipe = intel_crtc->pipe;
5eddb70b 2674 u32 reg, temp;
79e53945 2675
c64e311e 2676
c98e9dcf 2677 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2678 reg = FDI_RX_CTL(pipe);
2679 temp = I915_READ(reg);
627eb5a3
DV		 2680 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2681 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2682 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2683 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2684
2685 POSTING_READ(reg);
c98e9dcf
JB		 2686 udelay(200);
2687
2688 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2689 temp = I915_READ(reg);
2690 I915_WRITE(reg, temp | FDI_PCDCLK);
2691
2692 POSTING_READ(reg);
c98e9dcf
JB		 2693 udelay(200);
2694
20749730
PZ		 2695 /* Enable CPU FDI TX PLL, always on for Ironlake */
2696 reg = FDI_TX_CTL(pipe);
2697 temp = I915_READ(reg);
2698 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2699 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2700
20749730
PZ		 2701 POSTING_READ(reg);
2702 udelay(100);
6be4a607 2703 }
0e23b99d
JB		 2704}
2705
88cefb6c
DV		 2706static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2707{
2708 struct drm_device *dev = intel_crtc->base.dev;
2709 struct drm_i915_private *dev_priv = dev->dev_private;
2710 int pipe = intel_crtc->pipe;
2711 u32 reg, temp;
2712
2713 /* Switch from PCDclk to Rawclk */
2714 reg = FDI_RX_CTL(pipe);
2715 temp = I915_READ(reg);
2716 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2717
2718 /* Disable CPU FDI TX PLL */
2719 reg = FDI_TX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2722
2723 POSTING_READ(reg);
2724 udelay(100);
2725
2726 reg = FDI_RX_CTL(pipe);
2727 temp = I915_READ(reg);
2728 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2729
2730 /* Wait for the clocks to turn off. */
2731 POSTING_READ(reg);
2732 udelay(100);
2733}
2734
0fc932b8
JB		 2735static void ironlake_fdi_disable(struct drm_crtc *crtc)
2736{
2737 struct drm_device *dev = crtc->dev;
2738 struct drm_i915_private *dev_priv = dev->dev_private;
2739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2740 int pipe = intel_crtc->pipe;
2741 u32 reg, temp;
2742
2743 /* disable CPU FDI tx and PCH FDI rx */
2744 reg = FDI_TX_CTL(pipe);
2745 temp = I915_READ(reg);
2746 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2747 POSTING_READ(reg);
2748
2749 reg = FDI_RX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 temp &= ~(0x7 << 16);
dfd07d72 2752 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2753 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2754
2755 POSTING_READ(reg);
2756 udelay(100);
2757
2758 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2759 if (HAS_PCH_IBX(dev)) {
2760 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2761 }
0fc932b8
JB		 2762
2763 /* still set train pattern 1 */
2764 reg = FDI_TX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 temp &= ~FDI_LINK_TRAIN_NONE;
2767 temp |= FDI_LINK_TRAIN_PATTERN_1;
2768 I915_WRITE(reg, temp);
2769
2770 reg = FDI_RX_CTL(pipe);
2771 temp = I915_READ(reg);
2772 if (HAS_PCH_CPT(dev)) {
2773 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2774 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2775 } else {
2776 temp &= ~FDI_LINK_TRAIN_NONE;
2777 temp |= FDI_LINK_TRAIN_PATTERN_1;
2778 }
2779 /* BPC in FDI rx is consistent with that in PIPECONF */
2780 temp &= ~(0x07 << 16);
dfd07d72 2781 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2782 I915_WRITE(reg, temp);
2783
2784 POSTING_READ(reg);
2785 udelay(100);
2786}
2787
5bb61643
CW		 2788static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2789{
2790 struct drm_device *dev = crtc->dev;
2791 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2793 unsigned long flags;
2794 bool pending;
2795
10d83730
VS		 2796 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2797 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2798 return false;
2799
2800 spin_lock_irqsave(&dev->event_lock, flags);
2801 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2802 spin_unlock_irqrestore(&dev->event_lock, flags);
2803
2804 return pending;
2805}
2806
e6c3a2a6
CW		 2807static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2808{
0f91128d 2809 struct drm_device *dev = crtc->dev;
5bb61643 2810 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2811
2812 if (crtc->fb == NULL)
2813 return;
2814
2c10d571
DV		 2815 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2816
5bb61643
CW		 2817 wait_event(dev_priv->pending_flip_queue,
2818 !intel_crtc_has_pending_flip(crtc));
2819
0f91128d
CW		 2820 mutex_lock(&dev->struct_mutex);
2821 intel_finish_fb(crtc->fb);
2822 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2823}
2824
e615efe4
ED		 2825/* Program iCLKIP clock to the desired frequency */
2826static void lpt_program_iclkip(struct drm_crtc *crtc)
2827{
2828 struct drm_device *dev = crtc->dev;
2829 struct drm_i915_private *dev_priv = dev->dev_private;
2830 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2831 u32 temp;
2832
09153000
DV		 2833 mutex_lock(&dev_priv->dpio_lock);
2834
e615efe4
ED		 2835 /* It is necessary to ungate the pixclk gate prior to programming
2836 * the divisors, and gate it back when it is done.
2837 */
2838 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2839
2840 /* Disable SSCCTL */
2841 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2842 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2843 SBI_SSCCTL_DISABLE,
2844 SBI_ICLK);
e615efe4
ED		 2845
2846 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2847 if (crtc->mode.clock == 20000) {
2848 auxdiv = 1;
2849 divsel = 0x41;
2850 phaseinc = 0x20;
2851 } else {
2852 /* The iCLK virtual clock root frequency is in MHz,
2853 * but the crtc->mode.clock in in KHz. To get the divisors,
2854 * it is necessary to divide one by another, so we
2855 * convert the virtual clock precision to KHz here for higher
2856 * precision.
2857 */
2858 u32 iclk_virtual_root_freq = 172800 * 1000;
2859 u32 iclk_pi_range = 64;
2860 u32 desired_divisor, msb_divisor_value, pi_value;
2861
2862 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2863 msb_divisor_value = desired_divisor / iclk_pi_range;
2864 pi_value = desired_divisor % iclk_pi_range;
2865
2866 auxdiv = 0;
2867 divsel = msb_divisor_value - 2;
2868 phaseinc = pi_value;
2869 }
2870
2871 /* This should not happen with any sane values */
2872 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2873 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2874 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2875 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2876
2877 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2878 crtc->mode.clock,
2879 auxdiv,
2880 divsel,
2881 phasedir,
2882 phaseinc);
2883
2884 /* Program SSCDIVINTPHASE6 */
988d6ee8 2885 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2886 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2887 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2888 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2889 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2890 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2891 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2892 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2893
2894 /* Program SSCAUXDIV */
988d6ee8 2895 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2896 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2897 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2898 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2899
2900 /* Enable modulator and associated divider */
988d6ee8 2901 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2902 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2903 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2904
2905 /* Wait for initialization time */
2906 udelay(24);
2907
2908 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2909
2910 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2911}
2912
275f01b2
DV		 2913static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2914 enum pipe pch_transcoder)
2915{
2916 struct drm_device *dev = crtc->base.dev;
2917 struct drm_i915_private *dev_priv = dev->dev_private;
2918 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2919
2920 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2921 I915_READ(HTOTAL(cpu_transcoder)));
2922 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2923 I915_READ(HBLANK(cpu_transcoder)));
2924 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2925 I915_READ(HSYNC(cpu_transcoder)));
2926
2927 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2928 I915_READ(VTOTAL(cpu_transcoder)));
2929 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2930 I915_READ(VBLANK(cpu_transcoder)));
2931 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2932 I915_READ(VSYNC(cpu_transcoder)));
2933 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2934 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2935}
2936
f67a559d
JB		 2937/*
2938 * Enable PCH resources required for PCH ports:
2939 * - PCH PLLs
2940 * - FDI training & RX/TX
2941 * - update transcoder timings
2942 * - DP transcoding bits
2943 * - transcoder
2944 */
2945static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2946{
2947 struct drm_device *dev = crtc->dev;
2948 struct drm_i915_private *dev_priv = dev->dev_private;
2949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2950 int pipe = intel_crtc->pipe;
ee7b9f93 2951 u32 reg, temp;
2c07245f 2952
ab9412ba 2953 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2954
cd986abb
DV		 2955 /* Write the TU size bits before fdi link training, so that error
2956 * detection works. */
2957 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2958 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2959
c98e9dcf 2960 /* For PCH output, training FDI link */
674cf967 2961 dev_priv->display.fdi_link_train(crtc);
2c07245f 2962
572deb37
DV		 2963 /* XXX: pch pll's can be enabled any time before we enable the PCH
2964 * transcoder, and we actually should do this to not upset any PCH
2965 * transcoder that already use the clock when we share it.
2966 *
2967 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
2968 * unconditionally resets the pll - we need that to have the right LVDS
2969 * enable sequence. */
b6b4e185 2970 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 2971
303b81e0 2972 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2973 u32 sel;
4b645f14 2974
c98e9dcf 2975 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2976 switch (pipe) {
2977 default:
2978 case 0:
2979 temp |= TRANSA_DPLL_ENABLE;
2980 sel = TRANSA_DPLLB_SEL;
2981 break;
2982 case 1:
2983 temp |= TRANSB_DPLL_ENABLE;
2984 sel = TRANSB_DPLLB_SEL;
2985 break;
2986 case 2:
2987 temp |= TRANSC_DPLL_ENABLE;
2988 sel = TRANSC_DPLLB_SEL;
2989 break;
d64311ab 2990 }
ee7b9f93
JB		 2991 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2992 temp |= sel;
2993 else
2994 temp &= ~sel;
c98e9dcf 2995 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2996 }
5eddb70b 2997
d9b6cb56
JB		 2998 /* set transcoder timing, panel must allow it */
2999 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3000 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3001
303b81e0 3002 intel_fdi_normal_train(crtc);
5e84e1a4 3003
c98e9dcf
JB		 3004 /* For PCH DP, enable TRANS_DP_CTL */
3005 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3006 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3007 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3008 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3009 reg = TRANS_DP_CTL(pipe);
3010 temp = I915_READ(reg);
3011 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3012 TRANS_DP_SYNC_MASK |
3013 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3014 temp |= (TRANS_DP_OUTPUT_ENABLE |
3015 TRANS_DP_ENH_FRAMING);
9325c9f0 3016 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3017
3018 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3019 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3020 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3021 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3022
3023 switch (intel_trans_dp_port_sel(crtc)) {
3024 case PCH_DP_B:
5eddb70b 3025 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3026 break;
3027 case PCH_DP_C:
5eddb70b 3028 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3029 break;
3030 case PCH_DP_D:
5eddb70b 3031 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3032 break;
3033 default:
e95d41e1 3034 BUG();
32f9d658 3035 }
2c07245f 3036
5eddb70b 3037 I915_WRITE(reg, temp);
6be4a607 3038 }
b52eb4dc 3039
b8a4f404 3040 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3041}
3042
1507e5bd
PZ		 3043static void lpt_pch_enable(struct drm_crtc *crtc)
3044{
3045 struct drm_device *dev = crtc->dev;
3046 struct drm_i915_private *dev_priv = dev->dev_private;
3047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3048 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3049
ab9412ba 3050 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3051
8c52b5e8 3052 lpt_program_iclkip(crtc);
1507e5bd 3053
0540e488 3054 /* Set transcoder timing. */
275f01b2 3055 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3056
937bb610 3057 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3058}
3059
ee7b9f93
JB		 3060static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3061{
3062 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3063
3064 if (pll == NULL)
3065 return;
3066
3067 if (pll->refcount == 0) {
3068 WARN(1, "bad PCH PLL refcount\n");
3069 return;
3070 }
3071
3072 --pll->refcount;
3073 intel_crtc->pch_pll = NULL;
3074}
3075
3076static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3077{
3078 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3079 struct intel_pch_pll *pll;
3080 int i;
3081
3082 pll = intel_crtc->pch_pll;
3083 if (pll) {
cdbd2316 3084 DRM_DEBUG_KMS("CRTC:%d dropping existing PCH PLL %x\n",
ee7b9f93 3085 intel_crtc->base.base.id, pll->pll_reg);
cdbd2316 3086 intel_put_pch_pll(intel_crtc);
ee7b9f93
JB		 3087 }
3088
98b6bd99
DV		 3089 if (HAS_PCH_IBX(dev_priv->dev)) {
3090 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3091 i = intel_crtc->pipe;
3092 pll = &dev_priv->pch_plls[i];
3093
3094 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3095 intel_crtc->base.base.id, pll->pll_reg);
3096
3097 goto found;
3098 }
3099
ee7b9f93
JB		 3100 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3101 pll = &dev_priv->pch_plls[i];
3102
3103 /* Only want to check enabled timings first */
3104 if (pll->refcount == 0)
3105 continue;
3106
3107 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3108 fp == I915_READ(pll->fp0_reg)) {
3109 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3110 intel_crtc->base.base.id,
3111 pll->pll_reg, pll->refcount, pll->active);
3112
3113 goto found;
3114 }
3115 }
3116
3117 /* Ok no matching timings, maybe there's a free one? */
3118 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3119 pll = &dev_priv->pch_plls[i];
3120 if (pll->refcount == 0) {
3121 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3122 intel_crtc->base.base.id, pll->pll_reg);
3123 goto found;
3124 }
3125 }
3126
3127 return NULL;
3128
3129found:
3130 intel_crtc->pch_pll = pll;
84f44ce7 3131 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
cdbd2316
DV		 3132 if (pll->active == 0) {
3133 DRM_DEBUG_DRIVER("setting up pll %d\n", i);
3134 WARN_ON(pll->on);
3135 assert_pch_pll_disabled(dev_priv, pll, NULL);
ee7b9f93 3136
cdbd2316
DV		 3137 /* Wait for the clocks to stabilize before rewriting the regs */
3138 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3139 POSTING_READ(pll->pll_reg);
3140 udelay(150);
3141
3142 I915_WRITE(pll->fp0_reg, fp);
3143 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3144 }
3145 pll->refcount++;
e04c7350 3146
ee7b9f93
JB		 3147 return pll;
3148}
3149
a1520318 3150static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3151{
3152 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3153 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3154 u32 temp;
3155
3156 temp = I915_READ(dslreg);
3157 udelay(500);
3158 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3159 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3160 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3161 }
3162}
3163
b074cec8
JB		 3164static void ironlake_pfit_enable(struct intel_crtc *crtc)
3165{
3166 struct drm_device *dev = crtc->base.dev;
3167 struct drm_i915_private *dev_priv = dev->dev_private;
3168 int pipe = crtc->pipe;
3169
0ef37f3f 3170 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3171 /* Force use of hard-coded filter coefficients
3172 * as some pre-programmed values are broken,
3173 * e.g. x201.
3174 */
3175 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3176 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3177 PF_PIPE_SEL_IVB(pipe));
3178 else
3179 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3180 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3181 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3182 }
3183}
3184
bb53d4ae
VS		 3185static void intel_enable_planes(struct drm_crtc *crtc)
3186{
3187 struct drm_device *dev = crtc->dev;
3188 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3189 struct intel_plane *intel_plane;
3190
3191 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3192 if (intel_plane->pipe == pipe)
3193 intel_plane_restore(&intel_plane->base);
3194}
3195
3196static void intel_disable_planes(struct drm_crtc *crtc)
3197{
3198 struct drm_device *dev = crtc->dev;
3199 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3200 struct intel_plane *intel_plane;
3201
3202 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3203 if (intel_plane->pipe == pipe)
3204 intel_plane_disable(&intel_plane->base);
3205}
3206
f67a559d
JB		 3207static void ironlake_crtc_enable(struct drm_crtc *crtc)
3208{
3209 struct drm_device *dev = crtc->dev;
3210 struct drm_i915_private *dev_priv = dev->dev_private;
3211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3212 struct intel_encoder *encoder;
f67a559d
JB		 3213 int pipe = intel_crtc->pipe;
3214 int plane = intel_crtc->plane;
3215 u32 temp;
f67a559d 3216
08a48469
DV		 3217 WARN_ON(!crtc->enabled);
3218
f67a559d
JB		 3219 if (intel_crtc->active)
3220 return;
3221
3222 intel_crtc->active = true;
8664281b
PZ		 3223
3224 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3225 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3226
f67a559d
JB		 3227 intel_update_watermarks(dev);
3228
3229 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3230 temp = I915_READ(PCH_LVDS);
3231 if ((temp & LVDS_PORT_EN) == 0)
3232 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3233 }
3234
f67a559d 3235
5bfe2ac0 3236 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3237 /* Note: FDI PLL enabling _must_ be done before we enable the
3238 * cpu pipes, hence this is separate from all the other fdi/pch
3239 * enabling. */
88cefb6c 3240 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3241 } else {
3242 assert_fdi_tx_disabled(dev_priv, pipe);
3243 assert_fdi_rx_disabled(dev_priv, pipe);
3244 }
f67a559d 3245
bf49ec8c
DV		 3246 for_each_encoder_on_crtc(dev, crtc, encoder)
3247 if (encoder->pre_enable)
3248 encoder->pre_enable(encoder);
f67a559d
JB		 3249
3250 /* Enable panel fitting for LVDS */
b074cec8 3251 ironlake_pfit_enable(intel_crtc);
f67a559d 3252
9c54c0dd
JB		 3253 /*
3254 * On ILK+ LUT must be loaded before the pipe is running but with
3255 * clocks enabled
3256 */
3257 intel_crtc_load_lut(crtc);
3258
5bfe2ac0
DV		 3259 intel_enable_pipe(dev_priv, pipe,
3260 intel_crtc->config.has_pch_encoder);
f67a559d 3261 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3262 intel_enable_planes(crtc);
5c38d48c 3263 intel_crtc_update_cursor(crtc, true);
f67a559d 3264
5bfe2ac0 3265 if (intel_crtc->config.has_pch_encoder)
f67a559d 3266 ironlake_pch_enable(crtc);
c98e9dcf 3267
d1ebd816 3268 mutex_lock(&dev->struct_mutex);
bed4a673 3269 intel_update_fbc(dev);
d1ebd816
BW		 3270 mutex_unlock(&dev->struct_mutex);
3271
fa5c73b1
DV		 3272 for_each_encoder_on_crtc(dev, crtc, encoder)
3273 encoder->enable(encoder);
61b77ddd
DV		 3274
3275 if (HAS_PCH_CPT(dev))
a1520318 3276 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3277
3278 /*
3279 * There seems to be a race in PCH platform hw (at least on some
3280 * outputs) where an enabled pipe still completes any pageflip right
3281 * away (as if the pipe is off) instead of waiting for vblank. As soon
3282 * as the first vblank happend, everything works as expected. Hence just
3283 * wait for one vblank before returning to avoid strange things
3284 * happening.
3285 */
3286 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3287}
3288
42db64ef
PZ		 3289/* IPS only exists on ULT machines and is tied to pipe A. */
3290static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3291{
3292 return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3293}
3294
3295static void hsw_enable_ips(struct intel_crtc *crtc)
3296{
3297 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3298
3299 if (!crtc->config.ips_enabled)
3300 return;
3301
3302 /* We can only enable IPS after we enable a plane and wait for a vblank.
3303 * We guarantee that the plane is enabled by calling intel_enable_ips
3304 * only after intel_enable_plane. And intel_enable_plane already waits
3305 * for a vblank, so all we need to do here is to enable the IPS bit. */
3306 assert_plane_enabled(dev_priv, crtc->plane);
3307 I915_WRITE(IPS_CTL, IPS_ENABLE);
3308}
3309
3310static void hsw_disable_ips(struct intel_crtc *crtc)
3311{
3312 struct drm_device *dev = crtc->base.dev;
3313 struct drm_i915_private *dev_priv = dev->dev_private;
3314
3315 if (!crtc->config.ips_enabled)
3316 return;
3317
3318 assert_plane_enabled(dev_priv, crtc->plane);
3319 I915_WRITE(IPS_CTL, 0);
3320
3321 /* We need to wait for a vblank before we can disable the plane. */
3322 intel_wait_for_vblank(dev, crtc->pipe);
3323}
3324
4f771f10
PZ		 3325static void haswell_crtc_enable(struct drm_crtc *crtc)
3326{
3327 struct drm_device *dev = crtc->dev;
3328 struct drm_i915_private *dev_priv = dev->dev_private;
3329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3330 struct intel_encoder *encoder;
3331 int pipe = intel_crtc->pipe;
3332 int plane = intel_crtc->plane;
4f771f10
PZ		 3333
3334 WARN_ON(!crtc->enabled);
3335
3336 if (intel_crtc->active)
3337 return;
3338
3339 intel_crtc->active = true;
8664281b
PZ		 3340
3341 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3342 if (intel_crtc->config.has_pch_encoder)
3343 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3344
4f771f10
PZ		 3345 intel_update_watermarks(dev);
3346
5bfe2ac0 3347 if (intel_crtc->config.has_pch_encoder)
04945641 3348 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3349
3350 for_each_encoder_on_crtc(dev, crtc, encoder)
3351 if (encoder->pre_enable)
3352 encoder->pre_enable(encoder);
3353
1f544388 3354 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3355
1f544388 3356 /* Enable panel fitting for eDP */
b074cec8 3357 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3358
3359 /*
3360 * On ILK+ LUT must be loaded before the pipe is running but with
3361 * clocks enabled
3362 */
3363 intel_crtc_load_lut(crtc);
3364
1f544388 3365 intel_ddi_set_pipe_settings(crtc);
8228c251 3366 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3367
5bfe2ac0
DV		 3368 intel_enable_pipe(dev_priv, pipe,
3369 intel_crtc->config.has_pch_encoder);
4f771f10 3370 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3371 intel_enable_planes(crtc);
5c38d48c 3372 intel_crtc_update_cursor(crtc, true);
4f771f10 3373
42db64ef
PZ		 3374 hsw_enable_ips(intel_crtc);
3375
5bfe2ac0 3376 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3377 lpt_pch_enable(crtc);
4f771f10
PZ		 3378
3379 mutex_lock(&dev->struct_mutex);
3380 intel_update_fbc(dev);
3381 mutex_unlock(&dev->struct_mutex);
3382
4f771f10
PZ		 3383 for_each_encoder_on_crtc(dev, crtc, encoder)
3384 encoder->enable(encoder);
3385
4f771f10
PZ		 3386 /*
3387 * There seems to be a race in PCH platform hw (at least on some
3388 * outputs) where an enabled pipe still completes any pageflip right
3389 * away (as if the pipe is off) instead of waiting for vblank. As soon
3390 * as the first vblank happend, everything works as expected. Hence just
3391 * wait for one vblank before returning to avoid strange things
3392 * happening.
3393 */
3394 intel_wait_for_vblank(dev, intel_crtc->pipe);
3395}
3396
3f8dce3a
DV		 3397static void ironlake_pfit_disable(struct intel_crtc *crtc)
3398{
3399 struct drm_device *dev = crtc->base.dev;
3400 struct drm_i915_private *dev_priv = dev->dev_private;
3401 int pipe = crtc->pipe;
3402
3403 /* To avoid upsetting the power well on haswell only disable the pfit if
3404 * it's in use. The hw state code will make sure we get this right. */
3405 if (crtc->config.pch_pfit.size) {
3406 I915_WRITE(PF_CTL(pipe), 0);
3407 I915_WRITE(PF_WIN_POS(pipe), 0);
3408 I915_WRITE(PF_WIN_SZ(pipe), 0);
3409 }
3410}
3411
6be4a607
JB		 3412static void ironlake_crtc_disable(struct drm_crtc *crtc)
3413{
3414 struct drm_device *dev = crtc->dev;
3415 struct drm_i915_private *dev_priv = dev->dev_private;
3416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3417 struct intel_encoder *encoder;
6be4a607
JB		 3418 int pipe = intel_crtc->pipe;
3419 int plane = intel_crtc->plane;
5eddb70b 3420 u32 reg, temp;
b52eb4dc 3421
ef9c3aee 3422
f7abfe8b
CW		 3423 if (!intel_crtc->active)
3424 return;
3425
ea9d758d
DV		 3426 for_each_encoder_on_crtc(dev, crtc, encoder)
3427 encoder->disable(encoder);
3428
e6c3a2a6 3429 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3430 drm_vblank_off(dev, pipe);
913d8d11 3431
973d04f9
CW		 3432 if (dev_priv->cfb_plane == plane)
3433 intel_disable_fbc(dev);
2c07245f 3434
0d5b8c61 3435 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3436 intel_disable_planes(crtc);
0d5b8c61
VS		 3437 intel_disable_plane(dev_priv, plane, pipe);
3438
8664281b 3439 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3440 intel_disable_pipe(dev_priv, pipe);
32f9d658 3441
3f8dce3a 3442 ironlake_pfit_disable(intel_crtc);
2c07245f 3443
bf49ec8c
DV		 3444 for_each_encoder_on_crtc(dev, crtc, encoder)
3445 if (encoder->post_disable)
3446 encoder->post_disable(encoder);
2c07245f 3447
0fc932b8 3448 ironlake_fdi_disable(crtc);
249c0e64 3449
b8a4f404 3450 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3451 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3452
6be4a607
JB		 3453 if (HAS_PCH_CPT(dev)) {
3454 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3455 reg = TRANS_DP_CTL(pipe);
3456 temp = I915_READ(reg);
3457 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3458 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3459 I915_WRITE(reg, temp);
6be4a607
JB		 3460
3461 /* disable DPLL_SEL */
3462 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3463 switch (pipe) {
3464 case 0:
d64311ab 3465 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3466 break;
3467 case 1:
6be4a607 3468 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3469 break;
3470 case 2:
4b645f14 3471 /* C shares PLL A or B */
d64311ab 3472 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3473 break;
3474 default:
3475 BUG(); /* wtf */
3476 }
6be4a607 3477 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3478 }
e3421a18 3479
6be4a607 3480 /* disable PCH DPLL */
ee7b9f93 3481 intel_disable_pch_pll(intel_crtc);
8db9d77b 3482
88cefb6c 3483 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3484
f7abfe8b 3485 intel_crtc->active = false;
6b383a7f 3486 intel_update_watermarks(dev);
d1ebd816
BW		 3487
3488 mutex_lock(&dev->struct_mutex);
6b383a7f 3489 intel_update_fbc(dev);
d1ebd816 3490 mutex_unlock(&dev->struct_mutex);
6be4a607 3491}
1b3c7a47 3492
4f771f10 3493static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3494{
4f771f10
PZ		 3495 struct drm_device *dev = crtc->dev;
3496 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3498 struct intel_encoder *encoder;
3499 int pipe = intel_crtc->pipe;
3500 int plane = intel_crtc->plane;
3b117c8f 3501 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3502
4f771f10
PZ		 3503 if (!intel_crtc->active)
3504 return;
3505
3506 for_each_encoder_on_crtc(dev, crtc, encoder)
3507 encoder->disable(encoder);
3508
3509 intel_crtc_wait_for_pending_flips(crtc);
3510 drm_vblank_off(dev, pipe);
4f771f10 3511
891348b2 3512 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3513 if (dev_priv->cfb_plane == plane)
3514 intel_disable_fbc(dev);
3515
42db64ef
PZ		 3516 hsw_disable_ips(intel_crtc);
3517
0d5b8c61 3518 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3519 intel_disable_planes(crtc);
891348b2
RV		 3520 intel_disable_plane(dev_priv, plane, pipe);
3521
8664281b
PZ		 3522 if (intel_crtc->config.has_pch_encoder)
3523 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3524 intel_disable_pipe(dev_priv, pipe);
3525
ad80a810 3526 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3527
3f8dce3a 3528 ironlake_pfit_disable(intel_crtc);
4f771f10 3529
1f544388 3530 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3531
3532 for_each_encoder_on_crtc(dev, crtc, encoder)
3533 if (encoder->post_disable)
3534 encoder->post_disable(encoder);
3535
88adfff1 3536 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3537 lpt_disable_pch_transcoder(dev_priv);
8664281b 3538 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3539 intel_ddi_fdi_disable(crtc);
83616634 3540 }
4f771f10
PZ		 3541
3542 intel_crtc->active = false;
3543 intel_update_watermarks(dev);
3544
3545 mutex_lock(&dev->struct_mutex);
3546 intel_update_fbc(dev);
3547 mutex_unlock(&dev->struct_mutex);
3548}
3549
ee7b9f93
JB		 3550static void ironlake_crtc_off(struct drm_crtc *crtc)
3551{
3552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3553 intel_put_pch_pll(intel_crtc);
3554}
3555
6441ab5f
PZ		 3556static void haswell_crtc_off(struct drm_crtc *crtc)
3557{
3558 intel_ddi_put_crtc_pll(crtc);
3559}
3560
02e792fb
DV		 3561static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3562{
02e792fb 3563 if (!enable && intel_crtc->overlay) {
23f09ce3 3564 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3565 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3566
23f09ce3 3567 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3568 dev_priv->mm.interruptible = false;
3569 (void) intel_overlay_switch_off(intel_crtc->overlay);
3570 dev_priv->mm.interruptible = true;
23f09ce3 3571 mutex_unlock(&dev->struct_mutex);
02e792fb 3572 }
02e792fb 3573
5dcdbcb0
CW		 3574 /* Let userspace switch the overlay on again. In most cases userspace
3575 * has to recompute where to put it anyway.
3576 */
02e792fb
DV		 3577}
3578
61bc95c1
EE		 3579/**
3580 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3581 * cursor plane briefly if not already running after enabling the display
3582 * plane.
3583 * This workaround avoids occasional blank screens when self refresh is
3584 * enabled.
3585 */
3586static void
3587g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3588{
3589 u32 cntl = I915_READ(CURCNTR(pipe));
3590
3591 if ((cntl & CURSOR_MODE) == 0) {
3592 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3593
3594 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3595 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3596 intel_wait_for_vblank(dev_priv->dev, pipe);
3597 I915_WRITE(CURCNTR(pipe), cntl);
3598 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3599 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3600 }
3601}
3602
2dd24552
JB		 3603static void i9xx_pfit_enable(struct intel_crtc *crtc)
3604{
3605 struct drm_device *dev = crtc->base.dev;
3606 struct drm_i915_private *dev_priv = dev->dev_private;
3607 struct intel_crtc_config *pipe_config = &crtc->config;
3608
328d8e82 3609 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3610 return;
3611
2dd24552 3612 /*
c0b03411
DV		 3613 * The panel fitter should only be adjusted whilst the pipe is disabled,
3614 * according to register description and PRM.
2dd24552 3615 */
c0b03411
DV		 3616 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3617 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3618
b074cec8
JB		 3619 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3620 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3621
3622 /* Border color in case we don't scale up to the full screen. Black by
3623 * default, change to something else for debugging. */
3624 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3625}
3626
89b667f8
JB		 3627static void valleyview_crtc_enable(struct drm_crtc *crtc)
3628{
3629 struct drm_device *dev = crtc->dev;
3630 struct drm_i915_private *dev_priv = dev->dev_private;
3631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3632 struct intel_encoder *encoder;
3633 int pipe = intel_crtc->pipe;
3634 int plane = intel_crtc->plane;
3635
3636 WARN_ON(!crtc->enabled);
3637
3638 if (intel_crtc->active)
3639 return;
3640
3641 intel_crtc->active = true;
3642 intel_update_watermarks(dev);
3643
3644 mutex_lock(&dev_priv->dpio_lock);
3645
3646 for_each_encoder_on_crtc(dev, crtc, encoder)
3647 if (encoder->pre_pll_enable)
3648 encoder->pre_pll_enable(encoder);
3649
3650 intel_enable_pll(dev_priv, pipe);
3651
3652 for_each_encoder_on_crtc(dev, crtc, encoder)
3653 if (encoder->pre_enable)
3654 encoder->pre_enable(encoder);
3655
3656 /* VLV wants encoder enabling _before_ the pipe is up. */
3657 for_each_encoder_on_crtc(dev, crtc, encoder)
3658 encoder->enable(encoder);
3659
2dd24552
JB		 3660 /* Enable panel fitting for eDP */
3661 i9xx_pfit_enable(intel_crtc);
3662
63cbb074
VS		 3663 intel_crtc_load_lut(crtc);
3664
89b667f8
JB		 3665 intel_enable_pipe(dev_priv, pipe, false);
3666 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3667 intel_enable_planes(crtc);
5c38d48c 3668 intel_crtc_update_cursor(crtc, true);
89b667f8 3669
f440eb13
VS		 3670 intel_update_fbc(dev);
3671
89b667f8
JB		 3672 mutex_unlock(&dev_priv->dpio_lock);
3673}
3674
0b8765c6 3675static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3676{
3677 struct drm_device *dev = crtc->dev;
79e53945
JB		 3678 struct drm_i915_private *dev_priv = dev->dev_private;
3679 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3680 struct intel_encoder *encoder;
79e53945 3681 int pipe = intel_crtc->pipe;
80824003 3682 int plane = intel_crtc->plane;
79e53945 3683
08a48469
DV		 3684 WARN_ON(!crtc->enabled);
3685
f7abfe8b
CW		 3686 if (intel_crtc->active)
3687 return;
3688
3689 intel_crtc->active = true;
6b383a7f
CW		 3690 intel_update_watermarks(dev);
3691
63d7bbe9 3692 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3693
3694 for_each_encoder_on_crtc(dev, crtc, encoder)
3695 if (encoder->pre_enable)
3696 encoder->pre_enable(encoder);
3697
2dd24552
JB		 3698 /* Enable panel fitting for LVDS */
3699 i9xx_pfit_enable(intel_crtc);
3700
63cbb074
VS		 3701 intel_crtc_load_lut(crtc);
3702
040484af 3703 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3704 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3705 intel_enable_planes(crtc);
22e407d7 3706 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3707 if (IS_G4X(dev))
3708 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3709 intel_crtc_update_cursor(crtc, true);
79e53945 3710
0b8765c6
JB		 3711 /* Give the overlay scaler a chance to enable if it's on this pipe */
3712 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3713
f440eb13
VS		 3714 intel_update_fbc(dev);
3715
fa5c73b1
DV		 3716 for_each_encoder_on_crtc(dev, crtc, encoder)
3717 encoder->enable(encoder);
0b8765c6 3718}
79e53945 3719
87476d63
DV		 3720static void i9xx_pfit_disable(struct intel_crtc *crtc)
3721{
3722 struct drm_device *dev = crtc->base.dev;
3723 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3724
328d8e82
DV		 3725 if (!crtc->config.gmch_pfit.control)
3726 return;
87476d63 3727
328d8e82 3728 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3729
328d8e82
DV		 3730 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3731 I915_READ(PFIT_CONTROL));
3732 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3733}
3734
0b8765c6
JB		 3735static void i9xx_crtc_disable(struct drm_crtc *crtc)
3736{
3737 struct drm_device *dev = crtc->dev;
3738 struct drm_i915_private *dev_priv = dev->dev_private;
3739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3740 struct intel_encoder *encoder;
0b8765c6
JB		 3741 int pipe = intel_crtc->pipe;
3742 int plane = intel_crtc->plane;
ef9c3aee 3743
f7abfe8b
CW		 3744 if (!intel_crtc->active)
3745 return;
3746
ea9d758d
DV		 3747 for_each_encoder_on_crtc(dev, crtc, encoder)
3748 encoder->disable(encoder);
3749
0b8765c6 3750 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3751 intel_crtc_wait_for_pending_flips(crtc);
3752 drm_vblank_off(dev, pipe);
0b8765c6 3753
973d04f9
CW		 3754 if (dev_priv->cfb_plane == plane)
3755 intel_disable_fbc(dev);
79e53945 3756
0d5b8c61
VS		 3757 intel_crtc_dpms_overlay(intel_crtc, false);
3758 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3759 intel_disable_planes(crtc);
b24e7179 3760 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3761
b24e7179 3762 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3763
87476d63 3764 i9xx_pfit_disable(intel_crtc);
24a1f16d 3765
89b667f8
JB		 3766 for_each_encoder_on_crtc(dev, crtc, encoder)
3767 if (encoder->post_disable)
3768 encoder->post_disable(encoder);
3769
63d7bbe9 3770 intel_disable_pll(dev_priv, pipe);
0b8765c6 3771
f7abfe8b 3772 intel_crtc->active = false;
6b383a7f
CW		 3773 intel_update_fbc(dev);
3774 intel_update_watermarks(dev);
0b8765c6
JB		 3775}
3776
ee7b9f93
JB		 3777static void i9xx_crtc_off(struct drm_crtc *crtc)
3778{
3779}
3780
976f8a20
DV		 3781static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3782 bool enabled)
2c07245f
ZW		 3783{
3784 struct drm_device *dev = crtc->dev;
3785 struct drm_i915_master_private *master_priv;
3786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3787 int pipe = intel_crtc->pipe;
79e53945
JB		 3788
3789 if (!dev->primary->master)
3790 return;
3791
3792 master_priv = dev->primary->master->driver_priv;
3793 if (!master_priv->sarea_priv)
3794 return;
3795
79e53945
JB		 3796 switch (pipe) {
3797 case 0:
3798 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3799 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3800 break;
3801 case 1:
3802 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3803 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3804 break;
3805 default:
9db4a9c7 3806 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3807 break;
3808 }
79e53945
JB		 3809}
3810
976f8a20
DV		 3811/**
3812 * Sets the power management mode of the pipe and plane.
3813 */
3814void intel_crtc_update_dpms(struct drm_crtc *crtc)
3815{
3816 struct drm_device *dev = crtc->dev;
3817 struct drm_i915_private *dev_priv = dev->dev_private;
3818 struct intel_encoder *intel_encoder;
3819 bool enable = false;
3820
3821 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3822 enable |= intel_encoder->connectors_active;
3823
3824 if (enable)
3825 dev_priv->display.crtc_enable(crtc);
3826 else
3827 dev_priv->display.crtc_disable(crtc);
3828
3829 intel_crtc_update_sarea(crtc, enable);
3830}
3831
cdd59983
CW		 3832static void intel_crtc_disable(struct drm_crtc *crtc)
3833{
cdd59983 3834 struct drm_device *dev = crtc->dev;
976f8a20 3835 struct drm_connector *connector;
ee7b9f93 3836 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3838
976f8a20
DV		 3839 /* crtc should still be enabled when we disable it. */
3840 WARN_ON(!crtc->enabled);
3841
3842 dev_priv->display.crtc_disable(crtc);
c77bf565 3843 intel_crtc->eld_vld = false;
976f8a20 3844 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3845 dev_priv->display.off(crtc);
3846
931872fc
CW		 3847 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3848 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3849
3850 if (crtc->fb) {
3851 mutex_lock(&dev->struct_mutex);
1690e1eb 3852 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3853 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3854 crtc->fb = NULL;
3855 }
3856
3857 /* Update computed state. */
3858 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3859 if (!connector->encoder || !connector->encoder->crtc)
3860 continue;
3861
3862 if (connector->encoder->crtc != crtc)
3863 continue;
3864
3865 connector->dpms = DRM_MODE_DPMS_OFF;
3866 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3867 }
3868}
3869
a261b246 3870void intel_modeset_disable(struct drm_device *dev)
79e53945 3871{
a261b246
DV		 3872 struct drm_crtc *crtc;
3873
3874 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3875 if (crtc->enabled)
3876 intel_crtc_disable(crtc);
3877 }
79e53945
JB		 3878}
3879
ea5b213a 3880void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3881{
4ef69c7a 3882 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3883
ea5b213a
CW		 3884 drm_encoder_cleanup(encoder);
3885 kfree(intel_encoder);
7e7d76c3
JB		 3886}
3887
5ab432ef
DV		 3888/* Simple dpms helper for encodres with just one connector, no cloning and only
3889 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3890 * state of the entire output pipe. */
3891void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3892{
5ab432ef
DV		 3893 if (mode == DRM_MODE_DPMS_ON) {
3894 encoder->connectors_active = true;
3895
b2cabb0e 3896 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3897 } else {
3898 encoder->connectors_active = false;
3899
b2cabb0e 3900 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3901 }
79e53945
JB		 3902}
3903
0a91ca29
DV		 3904/* Cross check the actual hw state with our own modeset state tracking (and it's
3905 * internal consistency). */
b980514c 3906static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3907{
0a91ca29
DV		 3908 if (connector->get_hw_state(connector)) {
3909 struct intel_encoder *encoder = connector->encoder;
3910 struct drm_crtc *crtc;
3911 bool encoder_enabled;
3912 enum pipe pipe;
3913
3914 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3915 connector->base.base.id,
3916 drm_get_connector_name(&connector->base));
3917
3918 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3919 "wrong connector dpms state\n");
3920 WARN(connector->base.encoder != &encoder->base,
3921 "active connector not linked to encoder\n");
3922 WARN(!encoder->connectors_active,
3923 "encoder->connectors_active not set\n");
3924
3925 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3926 WARN(!encoder_enabled, "encoder not enabled\n");
3927 if (WARN_ON(!encoder->base.crtc))
3928 return;
3929
3930 crtc = encoder->base.crtc;
3931
3932 WARN(!crtc->enabled, "crtc not enabled\n");
3933 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3934 WARN(pipe != to_intel_crtc(crtc)->pipe,
3935 "encoder active on the wrong pipe\n");
3936 }
79e53945
JB		 3937}
3938
5ab432ef
DV		 3939/* Even simpler default implementation, if there's really no special case to
3940 * consider. */
3941void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3942{
5ab432ef 3943 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3944
5ab432ef
DV		 3945 /* All the simple cases only support two dpms states. */
3946 if (mode != DRM_MODE_DPMS_ON)
3947 mode = DRM_MODE_DPMS_OFF;
d4270e57 3948
5ab432ef
DV		 3949 if (mode == connector->dpms)
3950 return;
3951
3952 connector->dpms = mode;
3953
3954 /* Only need to change hw state when actually enabled */
3955 if (encoder->base.crtc)
3956 intel_encoder_dpms(encoder, mode);
3957 else
8af6cf88 3958 WARN_ON(encoder->connectors_active != false);
0a91ca29 3959
b980514c 3960 intel_modeset_check_state(connector->dev);
79e53945
JB		 3961}
3962
f0947c37
DV		 3963/* Simple connector->get_hw_state implementation for encoders that support only
3964 * one connector and no cloning and hence the encoder state determines the state
3965 * of the connector. */
3966bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3967{
24929352 3968 enum pipe pipe = 0;
f0947c37 3969 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3970
f0947c37 3971 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3972}
3973
1857e1da
DV		 3974static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3975 struct intel_crtc_config *pipe_config)
3976{
3977 struct drm_i915_private *dev_priv = dev->dev_private;
3978 struct intel_crtc *pipe_B_crtc =
3979 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3980
3981 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3982 pipe_name(pipe), pipe_config->fdi_lanes);
3983 if (pipe_config->fdi_lanes > 4) {
3984 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3985 pipe_name(pipe), pipe_config->fdi_lanes);
3986 return false;
3987 }
3988
3989 if (IS_HASWELL(dev)) {
3990 if (pipe_config->fdi_lanes > 2) {
3991 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3992 pipe_config->fdi_lanes);
3993 return false;
3994 } else {
3995 return true;
3996 }
3997 }
3998
3999 if (INTEL_INFO(dev)->num_pipes == 2)
4000 return true;
4001
4002 /* Ivybridge 3 pipe is really complicated */
4003 switch (pipe) {
4004 case PIPE_A:
4005 return true;
4006 case PIPE_B:
4007 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4008 pipe_config->fdi_lanes > 2) {
4009 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4010 pipe_name(pipe), pipe_config->fdi_lanes);
4011 return false;
4012 }
4013 return true;
4014 case PIPE_C:
1e833f40 4015 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4016 pipe_B_crtc->config.fdi_lanes <= 2) {
4017 if (pipe_config->fdi_lanes > 2) {
4018 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4019 pipe_name(pipe), pipe_config->fdi_lanes);
4020 return false;
4021 }
4022 } else {
4023 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4024 return false;
4025 }
4026 return true;
4027 default:
4028 BUG();
4029 }
4030}
4031
e29c22c0
DV		 4032#define RETRY 1
4033static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4034 struct intel_crtc_config *pipe_config)
877d48d5 4035{
1857e1da 4036 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4037 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4038 int lane, link_bw, fdi_dotclock;
e29c22c0 4039 bool setup_ok, needs_recompute = false;
877d48d5 4040
e29c22c0 4041retry:
877d48d5
DV		 4042 /* FDI is a binary signal running at ~2.7GHz, encoding
4043 * each output octet as 10 bits. The actual frequency
4044 * is stored as a divider into a 100MHz clock, and the
4045 * mode pixel clock is stored in units of 1KHz.
4046 * Hence the bw of each lane in terms of the mode signal
4047 * is:
4048 */
4049 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4050
ff9a6750 4051 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4052 fdi_dotclock /= pipe_config->pixel_multiplier;
2bd89a07
DV		 4053
4054 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4055 pipe_config->pipe_bpp);
4056
4057 pipe_config->fdi_lanes = lane;
4058
2bd89a07 4059 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4060 link_bw, &pipe_config->fdi_m_n);
1857e1da 4061
e29c22c0
DV		 4062 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4063 intel_crtc->pipe, pipe_config);
4064 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4065 pipe_config->pipe_bpp -= 2*3;
4066 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4067 pipe_config->pipe_bpp);
4068 needs_recompute = true;
4069 pipe_config->bw_constrained = true;
4070
4071 goto retry;
4072 }
4073
4074 if (needs_recompute)
4075 return RETRY;
4076
4077 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4078}
4079
42db64ef
PZ		 4080static void hsw_compute_ips_config(struct intel_crtc *crtc,
4081 struct intel_crtc_config *pipe_config)
4082{
3c4ca58c
PZ		 4083 pipe_config->ips_enabled = i915_enable_ips &&
4084 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4085 pipe_config->pipe_bpp == 24;
4086}
4087
e29c22c0
DV		 4088static int intel_crtc_compute_config(struct drm_crtc *crtc,
4089 struct intel_crtc_config *pipe_config)
79e53945 4090{
2c07245f 4091 struct drm_device *dev = crtc->dev;
b8cecdf5 4092 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
42db64ef 4093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
89749350 4094
bad720ff 4095 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4096 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4097 if (pipe_config->requested_mode.clock * 3
4098 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4099 return -EINVAL;
2c07245f 4100 }
89749350 4101
f9bef081
DV		 4102 /* All interlaced capable intel hw wants timings in frames. Note though
4103 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4104 * timings, so we need to be careful not to clobber these.*/
7ae89233 4105 if (!pipe_config->timings_set)
f9bef081 4106 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4107
8693a824
DL		 4108 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4109 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4110 */
4111 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4112 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4113 return -EINVAL;
44f46b42 4114
bd080ee5 4115 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4116 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4117 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4118 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4119 * for lvds. */
4120 pipe_config->pipe_bpp = 8*3;
4121 }
4122
42db64ef
PZ		 4123 if (IS_HASWELL(dev))
4124 hsw_compute_ips_config(intel_crtc, pipe_config);
4125
877d48d5 4126 if (pipe_config->has_pch_encoder)
42db64ef 4127 return ironlake_fdi_compute_config(intel_crtc, pipe_config);
877d48d5 4128
e29c22c0 4129 return 0;
79e53945
JB		 4130}
4131
25eb05fc
JB		 4132static int valleyview_get_display_clock_speed(struct drm_device *dev)
4133{
4134 return 400000; /* FIXME */
4135}
4136
e70236a8
JB		 4137static int i945_get_display_clock_speed(struct drm_device *dev)
4138{
4139 return 400000;
4140}
79e53945 4141
e70236a8 4142static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4143{
e70236a8
JB		 4144 return 333000;
4145}
79e53945 4146
e70236a8
JB		 4147static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4148{
4149 return 200000;
4150}
79e53945 4151
e70236a8
JB		 4152static int i915gm_get_display_clock_speed(struct drm_device *dev)
4153{
4154 u16 gcfgc = 0;
79e53945 4155
e70236a8
JB		 4156 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4157
4158 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4159 return 133000;
4160 else {
4161 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4162 case GC_DISPLAY_CLOCK_333_MHZ:
4163 return 333000;
4164 default:
4165 case GC_DISPLAY_CLOCK_190_200_MHZ:
4166 return 190000;
79e53945 4167 }
e70236a8
JB		 4168 }
4169}
4170
4171static int i865_get_display_clock_speed(struct drm_device *dev)
4172{
4173 return 266000;
4174}
4175
4176static int i855_get_display_clock_speed(struct drm_device *dev)
4177{
4178 u16 hpllcc = 0;
4179 /* Assume that the hardware is in the high speed state. This
4180 * should be the default.
4181 */
4182 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4183 case GC_CLOCK_133_200:
4184 case GC_CLOCK_100_200:
4185 return 200000;
4186 case GC_CLOCK_166_250:
4187 return 250000;
4188 case GC_CLOCK_100_133:
79e53945 4189 return 133000;
e70236a8 4190 }
79e53945 4191
e70236a8
JB		 4192 /* Shouldn't happen */
4193 return 0;
4194}
79e53945 4195
e70236a8
JB		 4196static int i830_get_display_clock_speed(struct drm_device *dev)
4197{
4198 return 133000;
79e53945
JB		 4199}
4200
2c07245f 4201static void
a65851af 4202intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4203{
a65851af
VS		 4204 while (*num > DATA_LINK_M_N_MASK ||
4205 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4206 *num >>= 1;
4207 *den >>= 1;
4208 }
4209}
4210
a65851af
VS		 4211static void compute_m_n(unsigned int m, unsigned int n,
4212 uint32_t *ret_m, uint32_t *ret_n)
4213{
4214 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4215 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4216 intel_reduce_m_n_ratio(ret_m, ret_n);
4217}
4218
e69d0bc1
DV		 4219void
4220intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4221 int pixel_clock, int link_clock,
4222 struct intel_link_m_n *m_n)
2c07245f 4223{
e69d0bc1 4224 m_n->tu = 64;
a65851af
VS		 4225
4226 compute_m_n(bits_per_pixel * pixel_clock,
4227 link_clock * nlanes * 8,
4228 &m_n->gmch_m, &m_n->gmch_n);
4229
4230 compute_m_n(pixel_clock, link_clock,
4231 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4232}
4233
a7615030
CW		 4234static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4235{
72bbe58c
KP		 4236 if (i915_panel_use_ssc >= 0)
4237 return i915_panel_use_ssc != 0;
41aa3448 4238 return dev_priv->vbt.lvds_use_ssc
435793df 4239 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4240}
4241
a0c4da24
JB		 4242static int vlv_get_refclk(struct drm_crtc *crtc)
4243{
4244 struct drm_device *dev = crtc->dev;
4245 struct drm_i915_private *dev_priv = dev->dev_private;
4246 int refclk = 27000; /* for DP & HDMI */
4247
4248 return 100000; /* only one validated so far */
4249
4250 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4251 refclk = 96000;
4252 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4253 if (intel_panel_use_ssc(dev_priv))
4254 refclk = 100000;
4255 else
4256 refclk = 96000;
4257 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4258 refclk = 100000;
4259 }
4260
4261 return refclk;
4262}
4263
c65d77d8
JB		 4264static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4265{
4266 struct drm_device *dev = crtc->dev;
4267 struct drm_i915_private *dev_priv = dev->dev_private;
4268 int refclk;
4269
a0c4da24
JB		 4270 if (IS_VALLEYVIEW(dev)) {
4271 refclk = vlv_get_refclk(crtc);
4272 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4273 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4274 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4275 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4276 refclk / 1000);
4277 } else if (!IS_GEN2(dev)) {
4278 refclk = 96000;
4279 } else {
4280 refclk = 48000;
4281 }
4282
4283 return refclk;
4284}
4285
7429e9d4
DV		 4286static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4287{
4288 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4289}
4290
4291static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4292{
4293 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4294}
4295
f47709a9 4296static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4297 intel_clock_t *reduced_clock)
4298{
f47709a9 4299 struct drm_device *dev = crtc->base.dev;
a7516a05 4300 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4301 int pipe = crtc->pipe;
a7516a05
JB		 4302 u32 fp, fp2 = 0;
4303
4304 if (IS_PINEVIEW(dev)) {
7429e9d4 4305 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4306 if (reduced_clock)
7429e9d4 4307 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4308 } else {
7429e9d4 4309 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4310 if (reduced_clock)
7429e9d4 4311 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4312 }
4313
4314 I915_WRITE(FP0(pipe), fp);
4315
f47709a9
DV		 4316 crtc->lowfreq_avail = false;
4317 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4318 reduced_clock && i915_powersave) {
4319 I915_WRITE(FP1(pipe), fp2);
f47709a9 4320 crtc->lowfreq_avail = true;
a7516a05
JB		 4321 } else {
4322 I915_WRITE(FP1(pipe), fp);
4323 }
4324}
4325
89b667f8
JB		 4326static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4327{
4328 u32 reg_val;
4329
4330 /*
4331 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4332 * and set it to a reasonable value instead.
4333 */
ae99258f 4334 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4335 reg_val &= 0xffffff00;
4336 reg_val |= 0x00000030;
ae99258f 4337 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4338
ae99258f 4339 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4340 reg_val &= 0x8cffffff;
4341 reg_val = 0x8c000000;
ae99258f 4342 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4343
ae99258f 4344 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4345 reg_val &= 0xffffff00;
ae99258f 4346 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4347
ae99258f 4348 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4349 reg_val &= 0x00ffffff;
4350 reg_val |= 0xb0000000;
ae99258f 4351 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4352}
4353
b551842d
DV		 4354static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4355 struct intel_link_m_n *m_n)
4356{
4357 struct drm_device *dev = crtc->base.dev;
4358 struct drm_i915_private *dev_priv = dev->dev_private;
4359 int pipe = crtc->pipe;
4360
e3b95f1e
DV		 4361 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4362 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4363 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4364 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4365}
4366
4367static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4368 struct intel_link_m_n *m_n)
4369{
4370 struct drm_device *dev = crtc->base.dev;
4371 struct drm_i915_private *dev_priv = dev->dev_private;
4372 int pipe = crtc->pipe;
4373 enum transcoder transcoder = crtc->config.cpu_transcoder;
4374
4375 if (INTEL_INFO(dev)->gen >= 5) {
4376 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4377 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4378 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4379 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4380 } else {
e3b95f1e
DV		 4381 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4382 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4383 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4384 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4385 }
4386}
4387
03afc4a2
DV		 4388static void intel_dp_set_m_n(struct intel_crtc *crtc)
4389{
4390 if (crtc->config.has_pch_encoder)
4391 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4392 else
4393 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4394}
4395
f47709a9 4396static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4397{
f47709a9 4398 struct drm_device *dev = crtc->base.dev;
a0c4da24 4399 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8 4400 struct intel_encoder *encoder;
f47709a9 4401 int pipe = crtc->pipe;
89b667f8 4402 u32 dpll, mdiv;
a0c4da24 4403 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4404 bool is_hdmi;
198a037f 4405 u32 coreclk, reg_val, dpll_md;
a0c4da24 4406
09153000
DV		 4407 mutex_lock(&dev_priv->dpio_lock);
4408
89b667f8 4409 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4410
f47709a9
DV		 4411 bestn = crtc->config.dpll.n;
4412 bestm1 = crtc->config.dpll.m1;
4413 bestm2 = crtc->config.dpll.m2;
4414 bestp1 = crtc->config.dpll.p1;
4415 bestp2 = crtc->config.dpll.p2;
a0c4da24 4416
89b667f8
JB		 4417 /* See eDP HDMI DPIO driver vbios notes doc */
4418
4419 /* PLL B needs special handling */
4420 if (pipe)
4421 vlv_pllb_recal_opamp(dev_priv);
4422
4423 /* Set up Tx target for periodic Rcomp update */
ae99258f 4424 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4425
4426 /* Disable target IRef on PLL */
ae99258f 4427 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4428 reg_val &= 0x00ffffff;
ae99258f 4429 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4430
4431 /* Disable fast lock */
ae99258f 4432 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4433
4434 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4435 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4436 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4437 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4438 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4439
4440 /*
4441 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4442 * but we don't support that).
4443 * Note: don't use the DAC post divider as it seems unstable.
4444 */
4445 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4446 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4447
89b667f8 4448 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4449 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4450
89b667f8 4451 /* Set HBR and RBR LPF coefficients */
ff9a6750 4452 if (crtc->config.port_clock == 162000 ||
89b667f8 4453 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
ae99258f 4454 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4455 0x005f0021);
4456 else
ae99258f 4457 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4458 0x00d0000f);
4459
4460 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4461 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4462 /* Use SSC source */
4463 if (!pipe)
ae99258f 4464 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4465 0x0df40000);
4466 else
ae99258f 4467 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4468 0x0df70000);
4469 } else { /* HDMI or VGA */
4470 /* Use bend source */
4471 if (!pipe)
ae99258f 4472 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4473 0x0df70000);
4474 else
ae99258f 4475 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4476 0x0df40000);
4477 }
a0c4da24 4478
ae99258f 4479 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4480 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4481 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4482 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4483 coreclk |= 0x01000000;
ae99258f 4484 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4485
ae99258f 4486 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4487
89b667f8
JB		 4488 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4489 if (encoder->pre_pll_enable)
4490 encoder->pre_pll_enable(encoder);
2a8f64ca 4491
89b667f8
JB		 4492 /* Enable DPIO clock input */
4493 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4494 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4495 if (pipe)
4496 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4497
89b667f8 4498 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4499 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4500 POSTING_READ(DPLL(pipe));
4501 udelay(150);
a0c4da24 4502
89b667f8
JB		 4503 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4504 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4505
ef1b460d
DV		 4506 dpll_md = (crtc->config.pixel_multiplier - 1)
4507 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f
DV		 4508 I915_WRITE(DPLL_MD(pipe), dpll_md);
4509 POSTING_READ(DPLL_MD(pipe));
f47709a9 4510
89b667f8
JB		 4511 if (crtc->config.has_dp_encoder)
4512 intel_dp_set_m_n(crtc);
09153000
DV		 4513
4514 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4515}
4516
f47709a9
DV		 4517static void i9xx_update_pll(struct intel_crtc *crtc,
4518 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4519 int num_connectors)
4520{
f47709a9 4521 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4522 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4523 struct intel_encoder *encoder;
f47709a9 4524 int pipe = crtc->pipe;
eb1cbe48
DV		 4525 u32 dpll;
4526 bool is_sdvo;
f47709a9 4527 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4528
f47709a9 4529 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4530
f47709a9
DV		 4531 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4532 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4533
4534 dpll = DPLL_VGA_MODE_DIS;
4535
f47709a9 4536 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4537 dpll |= DPLLB_MODE_LVDS;
4538 else
4539 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4540
ef1b460d 4541 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4542 dpll |= (crtc->config.pixel_multiplier - 1)
4543 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4544 }
198a037f
DV		 4545
4546 if (is_sdvo)
4547 dpll |= DPLL_DVO_HIGH_SPEED;
4548
f47709a9 4549 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4550 dpll |= DPLL_DVO_HIGH_SPEED;
4551
4552 /* compute bitmask from p1 value */
4553 if (IS_PINEVIEW(dev))
4554 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4555 else {
4556 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4557 if (IS_G4X(dev) && reduced_clock)
4558 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4559 }
4560 switch (clock->p2) {
4561 case 5:
4562 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4563 break;
4564 case 7:
4565 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4566 break;
4567 case 10:
4568 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4569 break;
4570 case 14:
4571 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4572 break;
4573 }
4574 if (INTEL_INFO(dev)->gen >= 4)
4575 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4576
09ede541 4577 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4578 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4579 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4580 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4581 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4582 else
4583 dpll |= PLL_REF_INPUT_DREFCLK;
4584
4585 dpll |= DPLL_VCO_ENABLE;
4586 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4587 POSTING_READ(DPLL(pipe));
4588 udelay(150);
4589
f47709a9 4590 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4591 if (encoder->pre_pll_enable)
4592 encoder->pre_pll_enable(encoder);
eb1cbe48 4593
f47709a9
DV		 4594 if (crtc->config.has_dp_encoder)
4595 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4596
4597 I915_WRITE(DPLL(pipe), dpll);
4598
4599 /* Wait for the clocks to stabilize. */
4600 POSTING_READ(DPLL(pipe));
4601 udelay(150);
4602
4603 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4604 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4605 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f 4606 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4607 } else {
4608 /* The pixel multiplier can only be updated once the
4609 * DPLL is enabled and the clocks are stable.
4610 *
4611 * So write it again.
4612 */
4613 I915_WRITE(DPLL(pipe), dpll);
4614 }
4615}
4616
f47709a9 4617static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4618 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4619 int num_connectors)
4620{
f47709a9 4621 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4622 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4623 struct intel_encoder *encoder;
f47709a9 4624 int pipe = crtc->pipe;
eb1cbe48 4625 u32 dpll;
f47709a9 4626 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4627
f47709a9 4628 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4629
eb1cbe48
DV		 4630 dpll = DPLL_VGA_MODE_DIS;
4631
f47709a9 4632 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4633 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4634 } else {
4635 if (clock->p1 == 2)
4636 dpll |= PLL_P1_DIVIDE_BY_TWO;
4637 else
4638 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4639 if (clock->p2 == 4)
4640 dpll |= PLL_P2_DIVIDE_BY_4;
4641 }
4642
f47709a9 4643 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4644 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4645 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4646 else
4647 dpll |= PLL_REF_INPUT_DREFCLK;
4648
4649 dpll |= DPLL_VCO_ENABLE;
4650 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4651 POSTING_READ(DPLL(pipe));
4652 udelay(150);
4653
f47709a9 4654 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4655 if (encoder->pre_pll_enable)
4656 encoder->pre_pll_enable(encoder);
eb1cbe48 4657
5b5896e4
DV		 4658 I915_WRITE(DPLL(pipe), dpll);
4659
4660 /* Wait for the clocks to stabilize. */
4661 POSTING_READ(DPLL(pipe));
4662 udelay(150);
4663
eb1cbe48
DV		 4664 /* The pixel multiplier can only be updated once the
4665 * DPLL is enabled and the clocks are stable.
4666 *
4667 * So write it again.
4668 */
4669 I915_WRITE(DPLL(pipe), dpll);
4670}
4671
8a654f3b 4672static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4673{
4674 struct drm_device *dev = intel_crtc->base.dev;
4675 struct drm_i915_private *dev_priv = dev->dev_private;
4676 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4677 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4678 struct drm_display_mode *adjusted_mode =
4679 &intel_crtc->config.adjusted_mode;
4680 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4681 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4682
4683 /* We need to be careful not to changed the adjusted mode, for otherwise
4684 * the hw state checker will get angry at the mismatch. */
4685 crtc_vtotal = adjusted_mode->crtc_vtotal;
4686 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4687
4688 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4689 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4690 crtc_vtotal -= 1;
4691 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4692 vsyncshift = adjusted_mode->crtc_hsync_start
4693 - adjusted_mode->crtc_htotal / 2;
4694 } else {
4695 vsyncshift = 0;
4696 }
4697
4698 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4699 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4700
fe2b8f9d 4701 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4702 (adjusted_mode->crtc_hdisplay - 1) |
4703 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4704 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4705 (adjusted_mode->crtc_hblank_start - 1) |
4706 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4707 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4708 (adjusted_mode->crtc_hsync_start - 1) |
4709 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4710
fe2b8f9d 4711 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4712 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4713 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4714 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4715 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4716 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4717 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4718 (adjusted_mode->crtc_vsync_start - 1) |
4719 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4720
b5e508d4
PZ		 4721 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4722 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4723 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4724 * bits. */
4725 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4726 (pipe == PIPE_B || pipe == PIPE_C))
4727 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4728
b0e77b9c
PZ		 4729 /* pipesrc controls the size that is scaled from, which should
4730 * always be the user's requested size.
4731 */
4732 I915_WRITE(PIPESRC(pipe),
4733 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4734}
4735
1bd1bd80
DV		 4736static void intel_get_pipe_timings(struct intel_crtc *crtc,
4737 struct intel_crtc_config *pipe_config)
4738{
4739 struct drm_device *dev = crtc->base.dev;
4740 struct drm_i915_private *dev_priv = dev->dev_private;
4741 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4742 uint32_t tmp;
4743
4744 tmp = I915_READ(HTOTAL(cpu_transcoder));
4745 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4746 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4747 tmp = I915_READ(HBLANK(cpu_transcoder));
4748 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4749 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4750 tmp = I915_READ(HSYNC(cpu_transcoder));
4751 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4752 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4753
4754 tmp = I915_READ(VTOTAL(cpu_transcoder));
4755 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4756 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4757 tmp = I915_READ(VBLANK(cpu_transcoder));
4758 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4759 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4760 tmp = I915_READ(VSYNC(cpu_transcoder));
4761 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4762 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4763
4764 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4765 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4766 pipe_config->adjusted_mode.crtc_vtotal += 1;
4767 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4768 }
4769
4770 tmp = I915_READ(PIPESRC(crtc->pipe));
4771 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4772 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4773}
4774
84b046f3
DV		 4775static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4776{
4777 struct drm_device *dev = intel_crtc->base.dev;
4778 struct drm_i915_private *dev_priv = dev->dev_private;
4779 uint32_t pipeconf;
4780
4781 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4782
4783 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4784 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4785 * core speed.
4786 *
4787 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4788 * pipe == 0 check?
4789 */
4790 if (intel_crtc->config.requested_mode.clock >
4791 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4792 pipeconf |= PIPECONF_DOUBLE_WIDE;
4793 else
4794 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4795 }
4796
ff9ce46e
DV		 4797 /* only g4x and later have fancy bpc/dither controls */
4798 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4799 pipeconf &= ~(PIPECONF_BPC_MASK |
4800 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4801
4802 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4803 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4804 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4805 PIPECONF_DITHER_TYPE_SP;
84b046f3 4806
ff9ce46e
DV		 4807 switch (intel_crtc->config.pipe_bpp) {
4808 case 18:
4809 pipeconf |= PIPECONF_6BPC;
4810 break;
4811 case 24:
4812 pipeconf |= PIPECONF_8BPC;
4813 break;
4814 case 30:
4815 pipeconf |= PIPECONF_10BPC;
4816 break;
4817 default:
4818 /* Case prevented by intel_choose_pipe_bpp_dither. */
4819 BUG();
84b046f3
DV		 4820 }
4821 }
4822
4823 if (HAS_PIPE_CXSR(dev)) {
4824 if (intel_crtc->lowfreq_avail) {
4825 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4826 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4827 } else {
4828 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4829 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4830 }
4831 }
4832
4833 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4834 if (!IS_GEN2(dev) &&
4835 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4836 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4837 else
4838 pipeconf |= PIPECONF_PROGRESSIVE;
4839
9c8e09b7
VS		 4840 if (IS_VALLEYVIEW(dev)) {
4841 if (intel_crtc->config.limited_color_range)
4842 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4843 else
4844 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4845 }
4846
84b046f3
DV		 4847 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4848 POSTING_READ(PIPECONF(intel_crtc->pipe));
4849}
4850
f564048e 4851static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4852 int x, int y,
94352cf9 4853 struct drm_framebuffer *fb)
79e53945
JB		 4854{
4855 struct drm_device *dev = crtc->dev;
4856 struct drm_i915_private *dev_priv = dev->dev_private;
4857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4858 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4859 int pipe = intel_crtc->pipe;
80824003 4860 int plane = intel_crtc->plane;
c751ce4f 4861 int refclk, num_connectors = 0;
652c393a 4862 intel_clock_t clock, reduced_clock;
84b046f3 4863 u32 dspcntr;
a16af721
DV		 4864 bool ok, has_reduced_clock = false;
4865 bool is_lvds = false;
5eddb70b 4866 struct intel_encoder *encoder;
d4906093 4867 const intel_limit_t *limit;
5c3b82e2 4868 int ret;
79e53945 4869
6c2b7c12 4870 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4871 switch (encoder->type) {
79e53945
JB		 4872 case INTEL_OUTPUT_LVDS:
4873 is_lvds = true;
4874 break;
79e53945 4875 }
43565a06 4876
c751ce4f 4877 num_connectors++;
79e53945
JB		 4878 }
4879
c65d77d8 4880 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4881
d4906093
ML		 4882 /*
4883 * Returns a set of divisors for the desired target clock with the given
4884 * refclk, or FALSE. The returned values represent the clock equation:
4885 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4886 */
1b894b59 4887 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4888 ok = dev_priv->display.find_dpll(limit, crtc,
4889 intel_crtc->config.port_clock,
ee9300bb
DV		 4890 refclk, NULL, &clock);
4891 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4892 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4893 return -EINVAL;
79e53945
JB		 4894 }
4895
cda4b7d3 4896 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4897 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4898
ddc9003c 4899 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4900 /*
4901 * Ensure we match the reduced clock's P to the target clock.
4902 * If the clocks don't match, we can't switch the display clock
4903 * by using the FP0/FP1. In such case we will disable the LVDS
4904 * downclock feature.
4905 */
ee9300bb
DV		 4906 has_reduced_clock =
4907 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4908 dev_priv->lvds_downclock,
ee9300bb 4909 refclk, &clock,
5eddb70b 4910 &reduced_clock);
7026d4ac 4911 }
f47709a9
DV		 4912 /* Compat-code for transition, will disappear. */
4913 if (!intel_crtc->config.clock_set) {
4914 intel_crtc->config.dpll.n = clock.n;
4915 intel_crtc->config.dpll.m1 = clock.m1;
4916 intel_crtc->config.dpll.m2 = clock.m2;
4917 intel_crtc->config.dpll.p1 = clock.p1;
4918 intel_crtc->config.dpll.p2 = clock.p2;
4919 }
7026d4ac 4920
eb1cbe48 4921 if (IS_GEN2(dev))
8a654f3b 4922 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4923 has_reduced_clock ? &reduced_clock : NULL,
4924 num_connectors);
a0c4da24 4925 else if (IS_VALLEYVIEW(dev))
f47709a9 4926 vlv_update_pll(intel_crtc);
79e53945 4927 else
f47709a9 4928 i9xx_update_pll(intel_crtc,
eb1cbe48 4929 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4930 num_connectors);
79e53945 4931
79e53945
JB		 4932 /* Set up the display plane register */
4933 dspcntr = DISPPLANE_GAMMA_ENABLE;
4934
da6ecc5d
JB		 4935 if (!IS_VALLEYVIEW(dev)) {
4936 if (pipe == 0)
4937 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4938 else
4939 dspcntr |= DISPPLANE_SEL_PIPE_B;
4940 }
79e53945 4941
8a654f3b 4942 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4943
4944 /* pipesrc and dspsize control the size that is scaled from,
4945 * which should always be the user's requested size.
79e53945 4946 */
929c77fb
EA		 4947 I915_WRITE(DSPSIZE(plane),
4948 ((mode->vdisplay - 1) << 16) |
4949 (mode->hdisplay - 1));
4950 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4951
84b046f3
DV		 4952 i9xx_set_pipeconf(intel_crtc);
4953
f564048e
EA		 4954 I915_WRITE(DSPCNTR(plane), dspcntr);
4955 POSTING_READ(DSPCNTR(plane));
4956
94352cf9 4957 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4958
4959 intel_update_watermarks(dev);
4960
f564048e
EA		 4961 return ret;
4962}
4963
2fa2fe9a
DV		 4964static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4965 struct intel_crtc_config *pipe_config)
4966{
4967 struct drm_device *dev = crtc->base.dev;
4968 struct drm_i915_private *dev_priv = dev->dev_private;
4969 uint32_t tmp;
4970
4971 tmp = I915_READ(PFIT_CONTROL);
4972
4973 if (INTEL_INFO(dev)->gen < 4) {
4974 if (crtc->pipe != PIPE_B)
4975 return;
4976
4977 /* gen2/3 store dither state in pfit control, needs to match */
4978 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4979 } else {
4980 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4981 return;
4982 }
4983
4984 if (!(tmp & PFIT_ENABLE))
4985 return;
4986
4987 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4988 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4989 if (INTEL_INFO(dev)->gen < 5)
4990 pipe_config->gmch_pfit.lvds_border_bits =
4991 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4992}
4993
0e8ffe1b
DV		 4994static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4995 struct intel_crtc_config *pipe_config)
4996{
4997 struct drm_device *dev = crtc->base.dev;
4998 struct drm_i915_private *dev_priv = dev->dev_private;
4999 uint32_t tmp;
5000
eccb140b
DV		 5001 pipe_config->cpu_transcoder = crtc->pipe;
5002
0e8ffe1b
DV		 5003 tmp = I915_READ(PIPECONF(crtc->pipe));
5004 if (!(tmp & PIPECONF_ENABLE))
5005 return false;
5006
1bd1bd80
DV		 5007 intel_get_pipe_timings(crtc, pipe_config);
5008
2fa2fe9a
DV		 5009 i9xx_get_pfit_config(crtc, pipe_config);
5010
6c49f241
DV		 5011 if (INTEL_INFO(dev)->gen >= 4) {
5012 tmp = I915_READ(DPLL_MD(crtc->pipe));
5013 pipe_config->pixel_multiplier =
5014 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5015 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5016 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5017 tmp = I915_READ(DPLL(crtc->pipe));
5018 pipe_config->pixel_multiplier =
5019 ((tmp & SDVO_MULTIPLIER_MASK)
5020 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5021 } else {
5022 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5023 * port and will be fixed up in the encoder->get_config
5024 * function. */
5025 pipe_config->pixel_multiplier = 1;
5026 }
5027
0e8ffe1b
DV		 5028 return true;
5029}
5030
dde86e2d 5031static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5032{
5033 struct drm_i915_private *dev_priv = dev->dev_private;
5034 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5035 struct intel_encoder *encoder;
74cfd7ac 5036 u32 val, final;
13d83a67 5037 bool has_lvds = false;
199e5d79 5038 bool has_cpu_edp = false;
199e5d79 5039 bool has_panel = false;
99eb6a01
KP		 5040 bool has_ck505 = false;
5041 bool can_ssc = false;
13d83a67
JB		 5042
5043 /* We need to take the global config into account */
199e5d79
KP		 5044 list_for_each_entry(encoder, &mode_config->encoder_list,
5045 base.head) {
5046 switch (encoder->type) {
5047 case INTEL_OUTPUT_LVDS:
5048 has_panel = true;
5049 has_lvds = true;
5050 break;
5051 case INTEL_OUTPUT_EDP:
5052 has_panel = true;
2de6905f 5053 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5054 has_cpu_edp = true;
5055 break;
13d83a67
JB		 5056 }
5057 }
5058
99eb6a01 5059 if (HAS_PCH_IBX(dev)) {
41aa3448 5060 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5061 can_ssc = has_ck505;
5062 } else {
5063 has_ck505 = false;
5064 can_ssc = true;
5065 }
5066
2de6905f
ID		 5067 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5068 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5069
5070 /* Ironlake: try to setup display ref clock before DPLL
5071 * enabling. This is only under driver's control after
5072 * PCH B stepping, previous chipset stepping should be
5073 * ignoring this setting.
5074 */
74cfd7ac
CW		 5075 val = I915_READ(PCH_DREF_CONTROL);
5076
5077 /* As we must carefully and slowly disable/enable each source in turn,
5078 * compute the final state we want first and check if we need to
5079 * make any changes at all.
5080 */
5081 final = val;
5082 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5083 if (has_ck505)
5084 final |= DREF_NONSPREAD_CK505_ENABLE;
5085 else
5086 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5087
5088 final &= ~DREF_SSC_SOURCE_MASK;
5089 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5090 final &= ~DREF_SSC1_ENABLE;
5091
5092 if (has_panel) {
5093 final |= DREF_SSC_SOURCE_ENABLE;
5094
5095 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5096 final |= DREF_SSC1_ENABLE;
5097
5098 if (has_cpu_edp) {
5099 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5100 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5101 else
5102 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5103 } else
5104 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5105 } else {
5106 final |= DREF_SSC_SOURCE_DISABLE;
5107 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5108 }
5109
5110 if (final == val)
5111 return;
5112
13d83a67 5113 /* Always enable nonspread source */
74cfd7ac 5114 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5115
99eb6a01 5116 if (has_ck505)
74cfd7ac 5117 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5118 else
74cfd7ac 5119 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5120
199e5d79 5121 if (has_panel) {
74cfd7ac
CW		 5122 val &= ~DREF_SSC_SOURCE_MASK;
5123 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5124
199e5d79 5125 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5126 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5127 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5128 val |= DREF_SSC1_ENABLE;
e77166b5 5129 } else
74cfd7ac 5130 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5131
5132 /* Get SSC going before enabling the outputs */
74cfd7ac 5133 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5134 POSTING_READ(PCH_DREF_CONTROL);
5135 udelay(200);
5136
74cfd7ac 5137 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5138
5139 /* Enable CPU source on CPU attached eDP */
199e5d79 5140 if (has_cpu_edp) {
99eb6a01 5141 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5142 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5143 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5144 }
13d83a67 5145 else
74cfd7ac 5146 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5147 } else
74cfd7ac 5148 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5149
74cfd7ac 5150 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5151 POSTING_READ(PCH_DREF_CONTROL);
5152 udelay(200);
5153 } else {
5154 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5155
74cfd7ac 5156 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5157
5158 /* Turn off CPU output */
74cfd7ac 5159 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5160
74cfd7ac 5161 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5162 POSTING_READ(PCH_DREF_CONTROL);
5163 udelay(200);
5164
5165 /* Turn off the SSC source */
74cfd7ac
CW		 5166 val &= ~DREF_SSC_SOURCE_MASK;
5167 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5168
5169 /* Turn off SSC1 */
74cfd7ac 5170 val &= ~DREF_SSC1_ENABLE;
199e5d79 5171
74cfd7ac 5172 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5173 POSTING_READ(PCH_DREF_CONTROL);
5174 udelay(200);
5175 }
74cfd7ac
CW		 5176
5177 BUG_ON(val != final);
13d83a67
JB		 5178}
5179
dde86e2d
PZ		 5180/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5181static void lpt_init_pch_refclk(struct drm_device *dev)
5182{
5183 struct drm_i915_private *dev_priv = dev->dev_private;
5184 struct drm_mode_config *mode_config = &dev->mode_config;
5185 struct intel_encoder *encoder;
5186 bool has_vga = false;
5187 bool is_sdv = false;
5188 u32 tmp;
5189
5190 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5191 switch (encoder->type) {
5192 case INTEL_OUTPUT_ANALOG:
5193 has_vga = true;
5194 break;
5195 }
5196 }
5197
5198 if (!has_vga)
5199 return;
5200
c00db246
DV		 5201 mutex_lock(&dev_priv->dpio_lock);
5202
dde86e2d
PZ		 5203 /* XXX: Rip out SDV support once Haswell ships for real. */
5204 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5205 is_sdv = true;
5206
5207 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5208 tmp &= ~SBI_SSCCTL_DISABLE;
5209 tmp |= SBI_SSCCTL_PATHALT;
5210 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5211
5212 udelay(24);
5213
5214 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5215 tmp &= ~SBI_SSCCTL_PATHALT;
5216 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5217
5218 if (!is_sdv) {
5219 tmp = I915_READ(SOUTH_CHICKEN2);
5220 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5221 I915_WRITE(SOUTH_CHICKEN2, tmp);
5222
5223 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5224 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5225 DRM_ERROR("FDI mPHY reset assert timeout\n");
5226
5227 tmp = I915_READ(SOUTH_CHICKEN2);
5228 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5229 I915_WRITE(SOUTH_CHICKEN2, tmp);
5230
5231 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5232 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5233 100))
5234 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5235 }
5236
5237 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5238 tmp &= ~(0xFF << 24);
5239 tmp |= (0x12 << 24);
5240 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5241
dde86e2d
PZ		 5242 if (is_sdv) {
5243 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5244 tmp |= 0x7FFF;
5245 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5246 }
5247
5248 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5249 tmp |= (1 << 11);
5250 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5251
5252 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5253 tmp |= (1 << 11);
5254 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5255
5256 if (is_sdv) {
5257 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5258 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5259 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5260
5261 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5262 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5263 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5264
5265 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5266 tmp |= (0x3F << 8);
5267 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5268
5269 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5270 tmp |= (0x3F << 8);
5271 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5272 }
5273
5274 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5275 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5276 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5277
5278 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5279 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5280 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5281
5282 if (!is_sdv) {
5283 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5284 tmp &= ~(7 << 13);
5285 tmp |= (5 << 13);
5286 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5287
5288 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5289 tmp &= ~(7 << 13);
5290 tmp |= (5 << 13);
5291 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5292 }
5293
5294 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5295 tmp &= ~0xFF;
5296 tmp |= 0x1C;
5297 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5298
5299 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5300 tmp &= ~0xFF;
5301 tmp |= 0x1C;
5302 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5303
5304 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5305 tmp &= ~(0xFF << 16);
5306 tmp |= (0x1C << 16);
5307 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5308
5309 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5310 tmp &= ~(0xFF << 16);
5311 tmp |= (0x1C << 16);
5312 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5313
5314 if (!is_sdv) {
5315 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5316 tmp |= (1 << 27);
5317 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5318
5319 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5320 tmp |= (1 << 27);
5321 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5322
5323 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5324 tmp &= ~(0xF << 28);
5325 tmp |= (4 << 28);
5326 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5327
5328 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5329 tmp &= ~(0xF << 28);
5330 tmp |= (4 << 28);
5331 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5332 }
5333
5334 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5335 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5336 tmp |= SBI_DBUFF0_ENABLE;
5337 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5338
5339 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5340}
5341
5342/*
5343 * Initialize reference clocks when the driver loads
5344 */
5345void intel_init_pch_refclk(struct drm_device *dev)
5346{
5347 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5348 ironlake_init_pch_refclk(dev);
5349 else if (HAS_PCH_LPT(dev))
5350 lpt_init_pch_refclk(dev);
5351}
5352
d9d444cb
JB		 5353static int ironlake_get_refclk(struct drm_crtc *crtc)
5354{
5355 struct drm_device *dev = crtc->dev;
5356 struct drm_i915_private *dev_priv = dev->dev_private;
5357 struct intel_encoder *encoder;
d9d444cb
JB		 5358 int num_connectors = 0;
5359 bool is_lvds = false;
5360
6c2b7c12 5361 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5362 switch (encoder->type) {
5363 case INTEL_OUTPUT_LVDS:
5364 is_lvds = true;
5365 break;
d9d444cb
JB		 5366 }
5367 num_connectors++;
5368 }
5369
5370 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5371 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5372 dev_priv->vbt.lvds_ssc_freq);
5373 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5374 }
5375
5376 return 120000;
5377}
5378
6ff93609 5379static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5380{
c8203565 5381 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5383 int pipe = intel_crtc->pipe;
c8203565
PZ		 5384 uint32_t val;
5385
5386 val = I915_READ(PIPECONF(pipe));
5387
dfd07d72 5388 val &= ~PIPECONF_BPC_MASK;
965e0c48 5389 switch (intel_crtc->config.pipe_bpp) {
c8203565 5390 case 18:
dfd07d72 5391 val |= PIPECONF_6BPC;
c8203565
PZ		 5392 break;
5393 case 24:
dfd07d72 5394 val |= PIPECONF_8BPC;
c8203565
PZ		 5395 break;
5396 case 30:
dfd07d72 5397 val |= PIPECONF_10BPC;
c8203565
PZ		 5398 break;
5399 case 36:
dfd07d72 5400 val |= PIPECONF_12BPC;
c8203565
PZ		 5401 break;
5402 default:
cc769b62
PZ		 5403 /* Case prevented by intel_choose_pipe_bpp_dither. */
5404 BUG();
c8203565
PZ		 5405 }
5406
5407 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5408 if (intel_crtc->config.dither)
c8203565
PZ		 5409 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5410
5411 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5412 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5413 val |= PIPECONF_INTERLACED_ILK;
5414 else
5415 val |= PIPECONF_PROGRESSIVE;
5416
50f3b016 5417 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5418 val |= PIPECONF_COLOR_RANGE_SELECT;
5419 else
5420 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5421
c8203565
PZ		 5422 I915_WRITE(PIPECONF(pipe), val);
5423 POSTING_READ(PIPECONF(pipe));
5424}
5425
86d3efce
VS		 5426/*
5427 * Set up the pipe CSC unit.
5428 *
5429 * Currently only full range RGB to limited range RGB conversion
5430 * is supported, but eventually this should handle various
5431 * RGB<->YCbCr scenarios as well.
5432 */
50f3b016 5433static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5434{
5435 struct drm_device *dev = crtc->dev;
5436 struct drm_i915_private *dev_priv = dev->dev_private;
5437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5438 int pipe = intel_crtc->pipe;
5439 uint16_t coeff = 0x7800; /* 1.0 */
5440
5441 /*
5442 * TODO: Check what kind of values actually come out of the pipe
5443 * with these coeff/postoff values and adjust to get the best
5444 * accuracy. Perhaps we even need to take the bpc value into
5445 * consideration.
5446 */
5447
50f3b016 5448 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5449 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5450
5451 /*
5452 * GY/GU and RY/RU should be the other way around according
5453 * to BSpec, but reality doesn't agree. Just set them up in
5454 * a way that results in the correct picture.
5455 */
5456 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5457 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5458
5459 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5460 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5461
5462 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5463 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5464
5465 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5466 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5467 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5468
5469 if (INTEL_INFO(dev)->gen > 6) {
5470 uint16_t postoff = 0;
5471
50f3b016 5472 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5473 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5474
5475 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5476 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5477 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5478
5479 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5480 } else {
5481 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5482
50f3b016 5483 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5484 mode |= CSC_BLACK_SCREEN_OFFSET;
5485
5486 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5487 }
5488}
5489
6ff93609 5490static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5491{
5492 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5494 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5495 uint32_t val;
5496
702e7a56 5497 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5498
5499 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5500 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5501 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5502
5503 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5504 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5505 val |= PIPECONF_INTERLACED_ILK;
5506 else
5507 val |= PIPECONF_PROGRESSIVE;
5508
702e7a56
PZ		 5509 I915_WRITE(PIPECONF(cpu_transcoder), val);
5510 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5511}
5512
6591c6e4 5513static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5514 intel_clock_t *clock,
5515 bool *has_reduced_clock,
5516 intel_clock_t *reduced_clock)
5517{
5518 struct drm_device *dev = crtc->dev;
5519 struct drm_i915_private *dev_priv = dev->dev_private;
5520 struct intel_encoder *intel_encoder;
5521 int refclk;
d4906093 5522 const intel_limit_t *limit;
a16af721 5523 bool ret, is_lvds = false;
79e53945 5524
6591c6e4
PZ		 5525 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5526 switch (intel_encoder->type) {
79e53945
JB		 5527 case INTEL_OUTPUT_LVDS:
5528 is_lvds = true;
5529 break;
79e53945
JB		 5530 }
5531 }
5532
d9d444cb 5533 refclk = ironlake_get_refclk(crtc);
79e53945 5534
d4906093
ML		 5535 /*
5536 * Returns a set of divisors for the desired target clock with the given
5537 * refclk, or FALSE. The returned values represent the clock equation:
5538 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5539 */
1b894b59 5540 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5541 ret = dev_priv->display.find_dpll(limit, crtc,
5542 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5543 refclk, NULL, clock);
6591c6e4
PZ		 5544 if (!ret)
5545 return false;
cda4b7d3 5546
ddc9003c 5547 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5548 /*
5549 * Ensure we match the reduced clock's P to the target clock.
5550 * If the clocks don't match, we can't switch the display clock
5551 * by using the FP0/FP1. In such case we will disable the LVDS
5552 * downclock feature.
5553 */
ee9300bb
DV		 5554 *has_reduced_clock =
5555 dev_priv->display.find_dpll(limit, crtc,
5556 dev_priv->lvds_downclock,
5557 refclk, clock,
5558 reduced_clock);
652c393a 5559 }
61e9653f 5560
6591c6e4
PZ		 5561 return true;
5562}
5563
01a415fd
DV		 5564static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5565{
5566 struct drm_i915_private *dev_priv = dev->dev_private;
5567 uint32_t temp;
5568
5569 temp = I915_READ(SOUTH_CHICKEN1);
5570 if (temp & FDI_BC_BIFURCATION_SELECT)
5571 return;
5572
5573 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5574 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5575
5576 temp |= FDI_BC_BIFURCATION_SELECT;
5577 DRM_DEBUG_KMS("enabling fdi C rx\n");
5578 I915_WRITE(SOUTH_CHICKEN1, temp);
5579 POSTING_READ(SOUTH_CHICKEN1);
5580}
5581
ebfd86fd
DV		 5582static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5583{
5584 struct drm_device *dev = intel_crtc->base.dev;
5585 struct drm_i915_private *dev_priv = dev->dev_private;
5586
5587 switch (intel_crtc->pipe) {
5588 case PIPE_A:
5589 break;
5590 case PIPE_B:
5591 if (intel_crtc->config.fdi_lanes > 2)
5592 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5593 else
5594 cpt_enable_fdi_bc_bifurcation(dev);
5595
5596 break;
5597 case PIPE_C:
01a415fd
DV		 5598 cpt_enable_fdi_bc_bifurcation(dev);
5599
ebfd86fd 5600 break;
01a415fd
DV		 5601 default:
5602 BUG();
5603 }
5604}
5605
d4b1931c
PZ		 5606int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5607{
5608 /*
5609 * Account for spread spectrum to avoid
5610 * oversubscribing the link. Max center spread
5611 * is 2.5%; use 5% for safety's sake.
5612 */
5613 u32 bps = target_clock * bpp * 21 / 20;
5614 return bps / (link_bw * 8) + 1;
5615}
5616
7429e9d4
DV		 5617static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5618{
5619 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5620}
5621
de13a2e3 5622static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5623 u32 *fp,
9a7c7890 5624 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5625{
de13a2e3 5626 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5627 struct drm_device *dev = crtc->dev;
5628 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5629 struct intel_encoder *intel_encoder;
5630 uint32_t dpll;
6cc5f341 5631 int factor, num_connectors = 0;
09ede541 5632 bool is_lvds = false, is_sdvo = false;
79e53945 5633
de13a2e3
PZ		 5634 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5635 switch (intel_encoder->type) {
79e53945
JB		 5636 case INTEL_OUTPUT_LVDS:
5637 is_lvds = true;
5638 break;
5639 case INTEL_OUTPUT_SDVO:
7d57382e 5640 case INTEL_OUTPUT_HDMI:
79e53945
JB		 5641 is_sdvo = true;
5642 break;
79e53945 5643 }
43565a06 5644
c751ce4f 5645 num_connectors++;
79e53945 5646 }
79e53945 5647
c1858123 5648 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5649 factor = 21;
5650 if (is_lvds) {
5651 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5652 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5653 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5654 factor = 25;
09ede541 5655 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5656 factor = 20;
c1858123 5657
7429e9d4 5658 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5659 *fp |= FP_CB_TUNE;
2c07245f 5660
9a7c7890
DV		 5661 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5662 *fp2 |= FP_CB_TUNE;
5663
5eddb70b 5664 dpll = 0;
2c07245f 5665
a07d6787
EA		 5666 if (is_lvds)
5667 dpll |= DPLLB_MODE_LVDS;
5668 else
5669 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5670
ef1b460d
DV		 5671 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5672 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5673
5674 if (is_sdvo)
5675 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5676 if (intel_crtc->config.has_dp_encoder)
a07d6787 5677 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5678
a07d6787 5679 /* compute bitmask from p1 value */
7429e9d4 5680 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5681 /* also FPA1 */
7429e9d4 5682 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5683
7429e9d4 5684 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5685 case 5:
5686 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5687 break;
5688 case 7:
5689 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5690 break;
5691 case 10:
5692 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5693 break;
5694 case 14:
5695 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5696 break;
79e53945
JB		 5697 }
5698
b4c09f3b 5699 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5700 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5701 else
5702 dpll |= PLL_REF_INPUT_DREFCLK;
5703
de13a2e3
PZ		 5704 return dpll;
5705}
5706
5707static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5708 int x, int y,
5709 struct drm_framebuffer *fb)
5710{
5711 struct drm_device *dev = crtc->dev;
5712 struct drm_i915_private *dev_priv = dev->dev_private;
5713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5714 int pipe = intel_crtc->pipe;
5715 int plane = intel_crtc->plane;
5716 int num_connectors = 0;
5717 intel_clock_t clock, reduced_clock;
cbbab5bd 5718 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5719 bool ok, has_reduced_clock = false;
8b47047b 5720 bool is_lvds = false;
de13a2e3 5721 struct intel_encoder *encoder;
de13a2e3 5722 int ret;
de13a2e3
PZ		 5723
5724 for_each_encoder_on_crtc(dev, crtc, encoder) {
5725 switch (encoder->type) {
5726 case INTEL_OUTPUT_LVDS:
5727 is_lvds = true;
5728 break;
de13a2e3
PZ		 5729 }
5730
5731 num_connectors++;
a07d6787 5732 }
79e53945 5733
5dc5298b
PZ		 5734 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5735 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5736
ff9a6750 5737 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5738 &has_reduced_clock, &reduced_clock);
ee9300bb 5739 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5740 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5741 return -EINVAL;
79e53945 5742 }
f47709a9
DV		 5743 /* Compat-code for transition, will disappear. */
5744 if (!intel_crtc->config.clock_set) {
5745 intel_crtc->config.dpll.n = clock.n;
5746 intel_crtc->config.dpll.m1 = clock.m1;
5747 intel_crtc->config.dpll.m2 = clock.m2;
5748 intel_crtc->config.dpll.p1 = clock.p1;
5749 intel_crtc->config.dpll.p2 = clock.p2;
5750 }
79e53945 5751
de13a2e3
PZ		 5752 /* Ensure that the cursor is valid for the new mode before changing... */
5753 intel_crtc_update_cursor(crtc, true);
5754
5dc5298b 5755 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5756 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5757 struct intel_pch_pll *pll;
4b645f14 5758
7429e9d4 5759 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5760 if (has_reduced_clock)
7429e9d4 5761 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5762
7429e9d4 5763 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5764 &fp, &reduced_clock,
5765 has_reduced_clock ? &fp2 : NULL);
5766
ee7b9f93
JB		 5767 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5768 if (pll == NULL) {
84f44ce7
VS		 5769 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5770 pipe_name(pipe));
4b645f14
JB		 5771 return -EINVAL;
5772 }
ee7b9f93
JB		 5773 } else
5774 intel_put_pch_pll(intel_crtc);
79e53945 5775
03afc4a2
DV		 5776 if (intel_crtc->config.has_dp_encoder)
5777 intel_dp_set_m_n(intel_crtc);
79e53945 5778
dafd226c
DV		 5779 for_each_encoder_on_crtc(dev, crtc, encoder)
5780 if (encoder->pre_pll_enable)
5781 encoder->pre_pll_enable(encoder);
79e53945 5782
ee7b9f93
JB		 5783 if (intel_crtc->pch_pll) {
5784 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5785
32f9d658 5786 /* Wait for the clocks to stabilize. */
ee7b9f93 5787 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5788 udelay(150);
5789
8febb297
EA		 5790 /* The pixel multiplier can only be updated once the
5791 * DPLL is enabled and the clocks are stable.
5792 *
5793 * So write it again.
5794 */
ee7b9f93 5795 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5796 }
79e53945 5797
5eddb70b 5798 intel_crtc->lowfreq_avail = false;
ee7b9f93 5799 if (intel_crtc->pch_pll) {
4b645f14 5800 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5801 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5802 intel_crtc->lowfreq_avail = true;
4b645f14 5803 } else {
ee7b9f93 5804 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5805 }
5806 }
5807
8a654f3b 5808 intel_set_pipe_timings(intel_crtc);
5eddb70b 5809
ca3a0ff8 5810 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5811 intel_cpu_transcoder_set_m_n(intel_crtc,
5812 &intel_crtc->config.fdi_m_n);
5813 }
2c07245f 5814
ebfd86fd
DV		 5815 if (IS_IVYBRIDGE(dev))
5816 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5817
6ff93609 5818 ironlake_set_pipeconf(crtc);
79e53945 5819
a1f9e77e
PZ		 5820 /* Set up the display plane register */
5821 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5822 POSTING_READ(DSPCNTR(plane));
79e53945 5823
94352cf9 5824 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5825
5826 intel_update_watermarks(dev);
5827
1857e1da 5828 return ret;
79e53945
JB		 5829}
5830
72419203
DV		 5831static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5832 struct intel_crtc_config *pipe_config)
5833{
5834 struct drm_device *dev = crtc->base.dev;
5835 struct drm_i915_private *dev_priv = dev->dev_private;
5836 enum transcoder transcoder = pipe_config->cpu_transcoder;
5837
5838 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5839 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5840 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5841 & ~TU_SIZE_MASK;
5842 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5843 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5844 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5845}
5846
2fa2fe9a
DV		 5847static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5848 struct intel_crtc_config *pipe_config)
5849{
5850 struct drm_device *dev = crtc->base.dev;
5851 struct drm_i915_private *dev_priv = dev->dev_private;
5852 uint32_t tmp;
5853
5854 tmp = I915_READ(PF_CTL(crtc->pipe));
5855
5856 if (tmp & PF_ENABLE) {
5857 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5858 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5859
5860 /* We currently do not free assignements of panel fitters on
5861 * ivb/hsw (since we don't use the higher upscaling modes which
5862 * differentiates them) so just WARN about this case for now. */
5863 if (IS_GEN7(dev)) {
5864 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5865 PF_PIPE_SEL_IVB(crtc->pipe));
5866 }
2fa2fe9a
DV		 5867 }
5868}
5869
0e8ffe1b
DV		 5870static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5871 struct intel_crtc_config *pipe_config)
5872{
5873 struct drm_device *dev = crtc->base.dev;
5874 struct drm_i915_private *dev_priv = dev->dev_private;
5875 uint32_t tmp;
5876
eccb140b
DV		 5877 pipe_config->cpu_transcoder = crtc->pipe;
5878
0e8ffe1b
DV		 5879 tmp = I915_READ(PIPECONF(crtc->pipe));
5880 if (!(tmp & PIPECONF_ENABLE))
5881 return false;
5882
ab9412ba 5883 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5884 pipe_config->has_pch_encoder = true;
5885
627eb5a3
DV		 5886 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5887 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5888 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5889
5890 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241
DV		 5891
5892 /* XXX: Can't properly read out the pch dpll pixel multiplier
5893 * since we don't have state tracking for pch clocks yet. */
5894 pipe_config->pixel_multiplier = 1;
5895 } else {
5896 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5897 }
5898
1bd1bd80
DV		 5899 intel_get_pipe_timings(crtc, pipe_config);
5900
2fa2fe9a
DV		 5901 ironlake_get_pfit_config(crtc, pipe_config);
5902
0e8ffe1b
DV		 5903 return true;
5904}
5905
d6dd9eb1
DV		 5906static void haswell_modeset_global_resources(struct drm_device *dev)
5907{
d6dd9eb1
DV		 5908 bool enable = false;
5909 struct intel_crtc *crtc;
d6dd9eb1
DV		 5910
5911 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5912 if (!crtc->base.enabled)
5913 continue;
d6dd9eb1 5914
e7a639c4
DV		 5915 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5916 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5917 enable = true;
5918 }
5919
d6dd9eb1
DV		 5920 intel_set_power_well(dev, enable);
5921}
5922
09b4ddf9 5923static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5924 int x, int y,
5925 struct drm_framebuffer *fb)
5926{
5927 struct drm_device *dev = crtc->dev;
5928 struct drm_i915_private *dev_priv = dev->dev_private;
5929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5930 int plane = intel_crtc->plane;
09b4ddf9 5931 int ret;
09b4ddf9 5932
ff9a6750 5933 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5934 return -EINVAL;
5935
09b4ddf9
PZ		 5936 /* Ensure that the cursor is valid for the new mode before changing... */
5937 intel_crtc_update_cursor(crtc, true);
5938
03afc4a2
DV		 5939 if (intel_crtc->config.has_dp_encoder)
5940 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5941
5942 intel_crtc->lowfreq_avail = false;
09b4ddf9 5943
8a654f3b 5944 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5945
ca3a0ff8 5946 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5947 intel_cpu_transcoder_set_m_n(intel_crtc,
5948 &intel_crtc->config.fdi_m_n);
5949 }
09b4ddf9 5950
6ff93609 5951 haswell_set_pipeconf(crtc);
09b4ddf9 5952
50f3b016 5953 intel_set_pipe_csc(crtc);
86d3efce 5954
09b4ddf9 5955 /* Set up the display plane register */
86d3efce 5956 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5957 POSTING_READ(DSPCNTR(plane));
5958
5959 ret = intel_pipe_set_base(crtc, x, y, fb);
5960
5961 intel_update_watermarks(dev);
5962
1f803ee5 5963 return ret;
79e53945
JB		 5964}
5965
0e8ffe1b
DV		 5966static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5967 struct intel_crtc_config *pipe_config)
5968{
5969 struct drm_device *dev = crtc->base.dev;
5970 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5971 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5972 uint32_t tmp;
5973
eccb140b
DV		 5974 pipe_config->cpu_transcoder = crtc->pipe;
5975 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5976 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5977 enum pipe trans_edp_pipe;
5978 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5979 default:
5980 WARN(1, "unknown pipe linked to edp transcoder\n");
5981 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5982 case TRANS_DDI_EDP_INPUT_A_ON:
5983 trans_edp_pipe = PIPE_A;
5984 break;
5985 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5986 trans_edp_pipe = PIPE_B;
5987 break;
5988 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5989 trans_edp_pipe = PIPE_C;
5990 break;
5991 }
5992
5993 if (trans_edp_pipe == crtc->pipe)
5994 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5995 }
5996
b97186f0 5997 if (!intel_display_power_enabled(dev,
eccb140b 5998 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 5999 return false;
6000
eccb140b 6001 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6002 if (!(tmp & PIPECONF_ENABLE))
6003 return false;
6004
88adfff1 6005 /*
f196e6be 6006 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6007 * DDI E. So just check whether this pipe is wired to DDI E and whether
6008 * the PCH transcoder is on.
6009 */
eccb140b 6010 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6011 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6012 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6013 pipe_config->has_pch_encoder = true;
6014
627eb5a3
DV		 6015 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6016 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6017 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6018
6019 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6020 }
6021
1bd1bd80
DV		 6022 intel_get_pipe_timings(crtc, pipe_config);
6023
2fa2fe9a
DV		 6024 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6025 if (intel_display_power_enabled(dev, pfit_domain))
6026 ironlake_get_pfit_config(crtc, pipe_config);
6027
42db64ef
PZ		 6028 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6029 (I915_READ(IPS_CTL) & IPS_ENABLE);
6030
6c49f241
DV		 6031 pipe_config->pixel_multiplier = 1;
6032
0e8ffe1b
DV		 6033 return true;
6034}
6035
f564048e 6036static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6037 int x, int y,
94352cf9 6038 struct drm_framebuffer *fb)
f564048e
EA		 6039{
6040 struct drm_device *dev = crtc->dev;
6041 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6042 struct drm_encoder_helper_funcs *encoder_funcs;
6043 struct intel_encoder *encoder;
0b701d27 6044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6045 struct drm_display_mode *adjusted_mode =
6046 &intel_crtc->config.adjusted_mode;
6047 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6048 int pipe = intel_crtc->pipe;
f564048e
EA		 6049 int ret;
6050
0b701d27 6051 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6052
b8cecdf5
DV		 6053 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6054
79e53945 6055 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6056
9256aa19
DV		 6057 if (ret != 0)
6058 return ret;
6059
6060 for_each_encoder_on_crtc(dev, crtc, encoder) {
6061 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6062 encoder->base.base.id,
6063 drm_get_encoder_name(&encoder->base),
6064 mode->base.id, mode->name);
6cc5f341
DV		 6065 if (encoder->mode_set) {
6066 encoder->mode_set(encoder);
6067 } else {
6068 encoder_funcs = encoder->base.helper_private;
6069 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6070 }
9256aa19
DV		 6071 }
6072
6073 return 0;
79e53945
JB		 6074}
6075
3a9627f4
WF		 6076static bool intel_eld_uptodate(struct drm_connector *connector,
6077 int reg_eldv, uint32_t bits_eldv,
6078 int reg_elda, uint32_t bits_elda,
6079 int reg_edid)
6080{
6081 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6082 uint8_t *eld = connector->eld;
6083 uint32_t i;
6084
6085 i = I915_READ(reg_eldv);
6086 i &= bits_eldv;
6087
6088 if (!eld[0])
6089 return !i;
6090
6091 if (!i)
6092 return false;
6093
6094 i = I915_READ(reg_elda);
6095 i &= ~bits_elda;
6096 I915_WRITE(reg_elda, i);
6097
6098 for (i = 0; i < eld[2]; i++)
6099 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6100 return false;
6101
6102 return true;
6103}
6104
e0dac65e
WF		 6105static void g4x_write_eld(struct drm_connector *connector,
6106 struct drm_crtc *crtc)
6107{
6108 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6109 uint8_t *eld = connector->eld;
6110 uint32_t eldv;
6111 uint32_t len;
6112 uint32_t i;
6113
6114 i = I915_READ(G4X_AUD_VID_DID);
6115
6116 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6117 eldv = G4X_ELDV_DEVCL_DEVBLC;
6118 else
6119 eldv = G4X_ELDV_DEVCTG;
6120
3a9627f4
WF		 6121 if (intel_eld_uptodate(connector,
6122 G4X_AUD_CNTL_ST, eldv,
6123 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6124 G4X_HDMIW_HDMIEDID))
6125 return;
6126
e0dac65e
WF		 6127 i = I915_READ(G4X_AUD_CNTL_ST);
6128 i &= ~(eldv | G4X_ELD_ADDR);
6129 len = (i >> 9) & 0x1f; /* ELD buffer size */
6130 I915_WRITE(G4X_AUD_CNTL_ST, i);
6131
6132 if (!eld[0])
6133 return;
6134
6135 len = min_t(uint8_t, eld[2], len);
6136 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6137 for (i = 0; i < len; i++)
6138 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6139
6140 i = I915_READ(G4X_AUD_CNTL_ST);
6141 i |= eldv;
6142 I915_WRITE(G4X_AUD_CNTL_ST, i);
6143}
6144
83358c85
WX		 6145static void haswell_write_eld(struct drm_connector *connector,
6146 struct drm_crtc *crtc)
6147{
6148 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6149 uint8_t *eld = connector->eld;
6150 struct drm_device *dev = crtc->dev;
7b9f35a6 6151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6152 uint32_t eldv;
6153 uint32_t i;
6154 int len;
6155 int pipe = to_intel_crtc(crtc)->pipe;
6156 int tmp;
6157
6158 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6159 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6160 int aud_config = HSW_AUD_CFG(pipe);
6161 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6162
6163
6164 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6165
6166 /* Audio output enable */
6167 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6168 tmp = I915_READ(aud_cntrl_st2);
6169 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6170 I915_WRITE(aud_cntrl_st2, tmp);
6171
6172 /* Wait for 1 vertical blank */
6173 intel_wait_for_vblank(dev, pipe);
6174
6175 /* Set ELD valid state */
6176 tmp = I915_READ(aud_cntrl_st2);
6177 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6178 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6179 I915_WRITE(aud_cntrl_st2, tmp);
6180 tmp = I915_READ(aud_cntrl_st2);
6181 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6182
6183 /* Enable HDMI mode */
6184 tmp = I915_READ(aud_config);
6185 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6186 /* clear N_programing_enable and N_value_index */
6187 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6188 I915_WRITE(aud_config, tmp);
6189
6190 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6191
6192 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6193 intel_crtc->eld_vld = true;
83358c85
WX		 6194
6195 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6196 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6197 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6198 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6199 } else
6200 I915_WRITE(aud_config, 0);
6201
6202 if (intel_eld_uptodate(connector,
6203 aud_cntrl_st2, eldv,
6204 aud_cntl_st, IBX_ELD_ADDRESS,
6205 hdmiw_hdmiedid))
6206 return;
6207
6208 i = I915_READ(aud_cntrl_st2);
6209 i &= ~eldv;
6210 I915_WRITE(aud_cntrl_st2, i);
6211
6212 if (!eld[0])
6213 return;
6214
6215 i = I915_READ(aud_cntl_st);
6216 i &= ~IBX_ELD_ADDRESS;
6217 I915_WRITE(aud_cntl_st, i);
6218 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6219 DRM_DEBUG_DRIVER("port num:%d\n", i);
6220
6221 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6222 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6223 for (i = 0; i < len; i++)
6224 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6225
6226 i = I915_READ(aud_cntrl_st2);
6227 i |= eldv;
6228 I915_WRITE(aud_cntrl_st2, i);
6229
6230}
6231
e0dac65e
WF		 6232static void ironlake_write_eld(struct drm_connector *connector,
6233 struct drm_crtc *crtc)
6234{
6235 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6236 uint8_t *eld = connector->eld;
6237 uint32_t eldv;
6238 uint32_t i;
6239 int len;
6240 int hdmiw_hdmiedid;
b6daa025 6241 int aud_config;
e0dac65e
WF		 6242 int aud_cntl_st;
6243 int aud_cntrl_st2;
9b138a83 6244 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6245
b3f33cbf 6246 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6247 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6248 aud_config = IBX_AUD_CFG(pipe);
6249 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6250 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6251 } else {
9b138a83
WX		 6252 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6253 aud_config = CPT_AUD_CFG(pipe);
6254 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6255 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6256 }
6257
9b138a83 6258 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6259
6260 i = I915_READ(aud_cntl_st);
9b138a83 6261 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6262 if (!i) {
6263 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6264 /* operate blindly on all ports */
1202b4c6
WF		 6265 eldv = IBX_ELD_VALIDB;
6266 eldv |= IBX_ELD_VALIDB << 4;
6267 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6268 } else {
2582a850 6269 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6270 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6271 }
6272
3a9627f4
WF		 6273 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6274 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6275 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6276 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6277 } else
6278 I915_WRITE(aud_config, 0);
e0dac65e 6279
3a9627f4
WF		 6280 if (intel_eld_uptodate(connector,
6281 aud_cntrl_st2, eldv,
6282 aud_cntl_st, IBX_ELD_ADDRESS,
6283 hdmiw_hdmiedid))
6284 return;
6285
e0dac65e
WF		 6286 i = I915_READ(aud_cntrl_st2);
6287 i &= ~eldv;
6288 I915_WRITE(aud_cntrl_st2, i);
6289
6290 if (!eld[0])
6291 return;
6292
e0dac65e 6293 i = I915_READ(aud_cntl_st);
1202b4c6 6294 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6295 I915_WRITE(aud_cntl_st, i);
6296
6297 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6298 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6299 for (i = 0; i < len; i++)
6300 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6301
6302 i = I915_READ(aud_cntrl_st2);
6303 i |= eldv;
6304 I915_WRITE(aud_cntrl_st2, i);
6305}
6306
6307void intel_write_eld(struct drm_encoder *encoder,
6308 struct drm_display_mode *mode)
6309{
6310 struct drm_crtc *crtc = encoder->crtc;
6311 struct drm_connector *connector;
6312 struct drm_device *dev = encoder->dev;
6313 struct drm_i915_private *dev_priv = dev->dev_private;
6314
6315 connector = drm_select_eld(encoder, mode);
6316 if (!connector)
6317 return;
6318
6319 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6320 connector->base.id,
6321 drm_get_connector_name(connector),
6322 connector->encoder->base.id,
6323 drm_get_encoder_name(connector->encoder));
6324
6325 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6326
6327 if (dev_priv->display.write_eld)
6328 dev_priv->display.write_eld(connector, crtc);
6329}
6330
79e53945
JB		 6331/** Loads the palette/gamma unit for the CRTC with the prepared values */
6332void intel_crtc_load_lut(struct drm_crtc *crtc)
6333{
6334 struct drm_device *dev = crtc->dev;
6335 struct drm_i915_private *dev_priv = dev->dev_private;
6336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6337 enum pipe pipe = intel_crtc->pipe;
6338 int palreg = PALETTE(pipe);
79e53945 6339 int i;
42db64ef 6340 bool reenable_ips = false;
79e53945
JB		 6341
6342 /* The clocks have to be on to load the palette. */
aed3f09d 6343 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6344 return;
6345
14420bd0
VS		 6346 if (!HAS_PCH_SPLIT(dev_priv->dev))
6347 assert_pll_enabled(dev_priv, pipe);
6348
f2b115e6 6349 /* use legacy palette for Ironlake */
bad720ff 6350 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6351 palreg = LGC_PALETTE(pipe);
6352
6353 /* Workaround : Do not read or write the pipe palette/gamma data while
6354 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6355 */
6356 if (intel_crtc->config.ips_enabled &&
6357 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6358 GAMMA_MODE_MODE_SPLIT)) {
6359 hsw_disable_ips(intel_crtc);
6360 reenable_ips = true;
6361 }
2c07245f 6362
79e53945
JB		 6363 for (i = 0; i < 256; i++) {
6364 I915_WRITE(palreg + 4 * i,
6365 (intel_crtc->lut_r[i] << 16) |
6366 (intel_crtc->lut_g[i] << 8) |
6367 intel_crtc->lut_b[i]);
6368 }
42db64ef
PZ		 6369
6370 if (reenable_ips)
6371 hsw_enable_ips(intel_crtc);
79e53945
JB		 6372}
6373
560b85bb
CW		 6374static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6375{
6376 struct drm_device *dev = crtc->dev;
6377 struct drm_i915_private *dev_priv = dev->dev_private;
6378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6379 bool visible = base != 0;
6380 u32 cntl;
6381
6382 if (intel_crtc->cursor_visible == visible)
6383 return;
6384
9db4a9c7 6385 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6386 if (visible) {
6387 /* On these chipsets we can only modify the base whilst
6388 * the cursor is disabled.
6389 */
9db4a9c7 6390 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6391
6392 cntl &= ~(CURSOR_FORMAT_MASK);
6393 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6394 cntl |= CURSOR_ENABLE |
6395 CURSOR_GAMMA_ENABLE |
6396 CURSOR_FORMAT_ARGB;
6397 } else
6398 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6399 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6400
6401 intel_crtc->cursor_visible = visible;
6402}
6403
6404static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6405{
6406 struct drm_device *dev = crtc->dev;
6407 struct drm_i915_private *dev_priv = dev->dev_private;
6408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6409 int pipe = intel_crtc->pipe;
6410 bool visible = base != 0;
6411
6412 if (intel_crtc->cursor_visible != visible) {
548f245b 6413 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6414 if (base) {
6415 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6416 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6417 cntl |= pipe << 28; /* Connect to correct pipe */
6418 } else {
6419 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6420 cntl |= CURSOR_MODE_DISABLE;
6421 }
9db4a9c7 6422 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6423
6424 intel_crtc->cursor_visible = visible;
6425 }
6426 /* and commit changes on next vblank */
9db4a9c7 6427 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6428}
6429
65a21cd6
JB		 6430static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6431{
6432 struct drm_device *dev = crtc->dev;
6433 struct drm_i915_private *dev_priv = dev->dev_private;
6434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6435 int pipe = intel_crtc->pipe;
6436 bool visible = base != 0;
6437
6438 if (intel_crtc->cursor_visible != visible) {
6439 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6440 if (base) {
6441 cntl &= ~CURSOR_MODE;
6442 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6443 } else {
6444 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6445 cntl |= CURSOR_MODE_DISABLE;
6446 }
86d3efce
VS		 6447 if (IS_HASWELL(dev))
6448 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6449 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6450
6451 intel_crtc->cursor_visible = visible;
6452 }
6453 /* and commit changes on next vblank */
6454 I915_WRITE(CURBASE_IVB(pipe), base);
6455}
6456
cda4b7d3 6457/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6458static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6459 bool on)
cda4b7d3
CW		 6460{
6461 struct drm_device *dev = crtc->dev;
6462 struct drm_i915_private *dev_priv = dev->dev_private;
6463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6464 int pipe = intel_crtc->pipe;
6465 int x = intel_crtc->cursor_x;
6466 int y = intel_crtc->cursor_y;
560b85bb 6467 u32 base, pos;
cda4b7d3
CW		 6468 bool visible;
6469
6470 pos = 0;
6471
6b383a7f 6472 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6473 base = intel_crtc->cursor_addr;
6474 if (x > (int) crtc->fb->width)
6475 base = 0;
6476
6477 if (y > (int) crtc->fb->height)
6478 base = 0;
6479 } else
6480 base = 0;
6481
6482 if (x < 0) {
6483 if (x + intel_crtc->cursor_width < 0)
6484 base = 0;
6485
6486 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6487 x = -x;
6488 }
6489 pos |= x << CURSOR_X_SHIFT;
6490
6491 if (y < 0) {
6492 if (y + intel_crtc->cursor_height < 0)
6493 base = 0;
6494
6495 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6496 y = -y;
6497 }
6498 pos |= y << CURSOR_Y_SHIFT;
6499
6500 visible = base != 0;
560b85bb 6501 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6502 return;
6503
0cd83aa9 6504 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6505 I915_WRITE(CURPOS_IVB(pipe), pos);
6506 ivb_update_cursor(crtc, base);
6507 } else {
6508 I915_WRITE(CURPOS(pipe), pos);
6509 if (IS_845G(dev) || IS_I865G(dev))
6510 i845_update_cursor(crtc, base);
6511 else
6512 i9xx_update_cursor(crtc, base);
6513 }
cda4b7d3
CW		 6514}
6515
79e53945 6516static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6517 struct drm_file *file,
79e53945
JB		 6518 uint32_t handle,
6519 uint32_t width, uint32_t height)
6520{
6521 struct drm_device *dev = crtc->dev;
6522 struct drm_i915_private *dev_priv = dev->dev_private;
6523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6524 struct drm_i915_gem_object *obj;
cda4b7d3 6525 uint32_t addr;
3f8bc370 6526 int ret;
79e53945 6527
79e53945
JB		 6528 /* if we want to turn off the cursor ignore width and height */
6529 if (!handle) {
28c97730 6530 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6531 addr = 0;
05394f39 6532 obj = NULL;
5004417d 6533 mutex_lock(&dev->struct_mutex);
3f8bc370 6534 goto finish;
79e53945
JB		 6535 }
6536
6537 /* Currently we only support 64x64 cursors */
6538 if (width != 64 || height != 64) {
6539 DRM_ERROR("we currently only support 64x64 cursors\n");
6540 return -EINVAL;
6541 }
6542
05394f39 6543 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6544 if (&obj->base == NULL)
79e53945
JB		 6545 return -ENOENT;
6546
05394f39 6547 if (obj->base.size < width * height * 4) {
79e53945 6548 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6549 ret = -ENOMEM;
6550 goto fail;
79e53945
JB		 6551 }
6552
71acb5eb 6553 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6554 mutex_lock(&dev->struct_mutex);
b295d1b6 6555 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6556 unsigned alignment;
6557
d9e86c0e
CW		 6558 if (obj->tiling_mode) {
6559 DRM_ERROR("cursor cannot be tiled\n");
6560 ret = -EINVAL;
6561 goto fail_locked;
6562 }
6563
693db184
CW		 6564 /* Note that the w/a also requires 2 PTE of padding following
6565 * the bo. We currently fill all unused PTE with the shadow
6566 * page and so we should always have valid PTE following the
6567 * cursor preventing the VT-d warning.
6568 */
6569 alignment = 0;
6570 if (need_vtd_wa(dev))
6571 alignment = 64*1024;
6572
6573 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6574 if (ret) {
6575 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6576 goto fail_locked;
e7b526bb
CW		 6577 }
6578
d9e86c0e
CW		 6579 ret = i915_gem_object_put_fence(obj);
6580 if (ret) {
2da3b9b9 6581 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6582 goto fail_unpin;
6583 }
6584
05394f39 6585 addr = obj->gtt_offset;
71acb5eb 6586 } else {
6eeefaf3 6587 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6588 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6589 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6590 align);
71acb5eb
DA		 6591 if (ret) {
6592 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6593 goto fail_locked;
71acb5eb 6594 }
05394f39 6595 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6596 }
6597
a6c45cf0 6598 if (IS_GEN2(dev))
14b60391
JB		 6599 I915_WRITE(CURSIZE, (height << 12) | width);
6600
3f8bc370 6601 finish:
3f8bc370 6602 if (intel_crtc->cursor_bo) {
b295d1b6 6603 if (dev_priv->info->cursor_needs_physical) {
05394f39 6604 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6605 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6606 } else
6607 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6608 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6609 }
80824003 6610
7f9872e0 6611 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6612
6613 intel_crtc->cursor_addr = addr;
05394f39 6614 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6615 intel_crtc->cursor_width = width;
6616 intel_crtc->cursor_height = height;
6617
40ccc72b 6618 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6619
79e53945 6620 return 0;
e7b526bb 6621fail_unpin:
05394f39 6622 i915_gem_object_unpin(obj);
7f9872e0 6623fail_locked:
34b8686e 6624 mutex_unlock(&dev->struct_mutex);
bc9025bd 6625fail:
05394f39 6626 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6627 return ret;
79e53945
JB		 6628}
6629
6630static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6631{
79e53945 6632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6633
cda4b7d3
CW		 6634 intel_crtc->cursor_x = x;
6635 intel_crtc->cursor_y = y;
652c393a 6636
40ccc72b 6637 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6638
6639 return 0;
6640}
6641
6642/** Sets the color ramps on behalf of RandR */
6643void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6644 u16 blue, int regno)
6645{
6646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6647
6648 intel_crtc->lut_r[regno] = red >> 8;
6649 intel_crtc->lut_g[regno] = green >> 8;
6650 intel_crtc->lut_b[regno] = blue >> 8;
6651}
6652
b8c00ac5
DA		 6653void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6654 u16 *blue, int regno)
6655{
6656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6657
6658 *red = intel_crtc->lut_r[regno] << 8;
6659 *green = intel_crtc->lut_g[regno] << 8;
6660 *blue = intel_crtc->lut_b[regno] << 8;
6661}
6662
79e53945 6663static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6664 u16 *blue, uint32_t start, uint32_t size)
79e53945 6665{
7203425a 6666 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6667 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6668
7203425a 6669 for (i = start; i < end; i++) {
79e53945
JB		 6670 intel_crtc->lut_r[i] = red[i] >> 8;
6671 intel_crtc->lut_g[i] = green[i] >> 8;
6672 intel_crtc->lut_b[i] = blue[i] >> 8;
6673 }
6674
6675 intel_crtc_load_lut(crtc);
6676}
6677
79e53945
JB		 6678/* VESA 640x480x72Hz mode to set on the pipe */
6679static struct drm_display_mode load_detect_mode = {
6680 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6681 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6682};
6683
d2dff872
CW		 6684static struct drm_framebuffer *
6685intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6686 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6687 struct drm_i915_gem_object *obj)
6688{
6689 struct intel_framebuffer *intel_fb;
6690 int ret;
6691
6692 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6693 if (!intel_fb) {
6694 drm_gem_object_unreference_unlocked(&obj->base);
6695 return ERR_PTR(-ENOMEM);
6696 }
6697
6698 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6699 if (ret) {
6700 drm_gem_object_unreference_unlocked(&obj->base);
6701 kfree(intel_fb);
6702 return ERR_PTR(ret);
6703 }
6704
6705 return &intel_fb->base;
6706}
6707
6708static u32
6709intel_framebuffer_pitch_for_width(int width, int bpp)
6710{
6711 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6712 return ALIGN(pitch, 64);
6713}
6714
6715static u32
6716intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6717{
6718 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6719 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6720}
6721
6722static struct drm_framebuffer *
6723intel_framebuffer_create_for_mode(struct drm_device *dev,
6724 struct drm_display_mode *mode,
6725 int depth, int bpp)
6726{
6727 struct drm_i915_gem_object *obj;
0fed39bd 6728 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6729
6730 obj = i915_gem_alloc_object(dev,
6731 intel_framebuffer_size_for_mode(mode, bpp));
6732 if (obj == NULL)
6733 return ERR_PTR(-ENOMEM);
6734
6735 mode_cmd.width = mode->hdisplay;
6736 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6737 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6738 bpp);
5ca0c34a 6739 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6740
6741 return intel_framebuffer_create(dev, &mode_cmd, obj);
6742}
6743
6744static struct drm_framebuffer *
6745mode_fits_in_fbdev(struct drm_device *dev,
6746 struct drm_display_mode *mode)
6747{
6748 struct drm_i915_private *dev_priv = dev->dev_private;
6749 struct drm_i915_gem_object *obj;
6750 struct drm_framebuffer *fb;
6751
6752 if (dev_priv->fbdev == NULL)
6753 return NULL;
6754
6755 obj = dev_priv->fbdev->ifb.obj;
6756 if (obj == NULL)
6757 return NULL;
6758
6759 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6760 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6761 fb->bits_per_pixel))
d2dff872
CW		 6762 return NULL;
6763
01f2c773 6764 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6765 return NULL;
6766
6767 return fb;
6768}
6769
d2434ab7 6770bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6771 struct drm_display_mode *mode,
8261b191 6772 struct intel_load_detect_pipe *old)
79e53945
JB		 6773{
6774 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6775 struct intel_encoder *intel_encoder =
6776 intel_attached_encoder(connector);
79e53945 6777 struct drm_crtc *possible_crtc;
4ef69c7a 6778 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6779 struct drm_crtc *crtc = NULL;
6780 struct drm_device *dev = encoder->dev;
94352cf9 6781 struct drm_framebuffer *fb;
79e53945
JB		 6782 int i = -1;
6783
d2dff872
CW		 6784 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6785 connector->base.id, drm_get_connector_name(connector),
6786 encoder->base.id, drm_get_encoder_name(encoder));
6787
79e53945
JB		 6788 /*
6789 * Algorithm gets a little messy:
7a5e4805 6790 *
79e53945
JB		 6791 * - if the connector already has an assigned crtc, use it (but make
6792 * sure it's on first)
7a5e4805 6793 *
79e53945
JB		 6794 * - try to find the first unused crtc that can drive this connector,
6795 * and use that if we find one
79e53945
JB		 6796 */
6797
6798 /* See if we already have a CRTC for this connector */
6799 if (encoder->crtc) {
6800 crtc = encoder->crtc;
8261b191 6801
7b24056b
DV		 6802 mutex_lock(&crtc->mutex);
6803
24218aac 6804 old->dpms_mode = connector->dpms;
8261b191
CW		 6805 old->load_detect_temp = false;
6806
6807 /* Make sure the crtc and connector are running */
24218aac
DV		 6808 if (connector->dpms != DRM_MODE_DPMS_ON)
6809 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6810
7173188d 6811 return true;
79e53945
JB		 6812 }
6813
6814 /* Find an unused one (if possible) */
6815 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6816 i++;
6817 if (!(encoder->possible_crtcs & (1 << i)))
6818 continue;
6819 if (!possible_crtc->enabled) {
6820 crtc = possible_crtc;
6821 break;
6822 }
79e53945
JB		 6823 }
6824
6825 /*
6826 * If we didn't find an unused CRTC, don't use any.
6827 */
6828 if (!crtc) {
7173188d
CW		 6829 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6830 return false;
79e53945
JB		 6831 }
6832
7b24056b 6833 mutex_lock(&crtc->mutex);
fc303101
DV		 6834 intel_encoder->new_crtc = to_intel_crtc(crtc);
6835 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6836
6837 intel_crtc = to_intel_crtc(crtc);
24218aac 6838 old->dpms_mode = connector->dpms;
8261b191 6839 old->load_detect_temp = true;
d2dff872 6840 old->release_fb = NULL;
79e53945 6841
6492711d
CW		 6842 if (!mode)
6843 mode = &load_detect_mode;
79e53945 6844
d2dff872
CW		 6845 /* We need a framebuffer large enough to accommodate all accesses
6846 * that the plane may generate whilst we perform load detection.
6847 * We can not rely on the fbcon either being present (we get called
6848 * during its initialisation to detect all boot displays, or it may
6849 * not even exist) or that it is large enough to satisfy the
6850 * requested mode.
6851 */
94352cf9
DV		 6852 fb = mode_fits_in_fbdev(dev, mode);
6853 if (fb == NULL) {
d2dff872 6854 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6855 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6856 old->release_fb = fb;
d2dff872
CW		 6857 } else
6858 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6859 if (IS_ERR(fb)) {
d2dff872 6860 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6861 mutex_unlock(&crtc->mutex);
0e8b3d3e 6862 return false;
79e53945 6863 }
79e53945 6864
c0c36b94 6865 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6866 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6867 if (old->release_fb)
6868 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6869 mutex_unlock(&crtc->mutex);
0e8b3d3e 6870 return false;
79e53945 6871 }
7173188d 6872
79e53945 6873 /* let the connector get through one full cycle before testing */
9d0498a2 6874 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6875 return true;
79e53945
JB		 6876}
6877
d2434ab7 6878void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6879 struct intel_load_detect_pipe *old)
79e53945 6880{
d2434ab7
DV		 6881 struct intel_encoder *intel_encoder =
6882 intel_attached_encoder(connector);
4ef69c7a 6883 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6884 struct drm_crtc *crtc = encoder->crtc;
79e53945 6885
d2dff872
CW		 6886 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6887 connector->base.id, drm_get_connector_name(connector),
6888 encoder->base.id, drm_get_encoder_name(encoder));
6889
8261b191 6890 if (old->load_detect_temp) {
fc303101
DV		 6891 to_intel_connector(connector)->new_encoder = NULL;
6892 intel_encoder->new_crtc = NULL;
6893 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6894
36206361
DV		 6895 if (old->release_fb) {
6896 drm_framebuffer_unregister_private(old->release_fb);
6897 drm_framebuffer_unreference(old->release_fb);
6898 }
d2dff872 6899
67c96400 6900 mutex_unlock(&crtc->mutex);
0622a53c 6901 return;
79e53945
JB		 6902 }
6903
c751ce4f 6904 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6905 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6906 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6907
6908 mutex_unlock(&crtc->mutex);
79e53945
JB		 6909}
6910
6911/* Returns the clock of the currently programmed mode of the given pipe. */
6912static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6913{
6914 struct drm_i915_private *dev_priv = dev->dev_private;
6915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6916 int pipe = intel_crtc->pipe;
548f245b 6917 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6918 u32 fp;
6919 intel_clock_t clock;
6920
6921 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6922 fp = I915_READ(FP0(pipe));
79e53945 6923 else
39adb7a5 6924 fp = I915_READ(FP1(pipe));
79e53945
JB		 6925
6926 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6927 if (IS_PINEVIEW(dev)) {
6928 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6929 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6930 } else {
6931 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6932 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6933 }
6934
a6c45cf0 6935 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6936 if (IS_PINEVIEW(dev))
6937 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6938 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6939 else
6940 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6941 DPLL_FPA01_P1_POST_DIV_SHIFT);
6942
6943 switch (dpll & DPLL_MODE_MASK) {
6944 case DPLLB_MODE_DAC_SERIAL:
6945 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6946 5 : 10;
6947 break;
6948 case DPLLB_MODE_LVDS:
6949 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6950 7 : 14;
6951 break;
6952 default:
28c97730 6953 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6954 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6955 return 0;
6956 }
6957
ac58c3f0
DV		 6958 if (IS_PINEVIEW(dev))
6959 pineview_clock(96000, &clock);
6960 else
6961 i9xx_clock(96000, &clock);
79e53945
JB		 6962 } else {
6963 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6964
6965 if (is_lvds) {
6966 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6967 DPLL_FPA01_P1_POST_DIV_SHIFT);
6968 clock.p2 = 14;
6969
6970 if ((dpll & PLL_REF_INPUT_MASK) ==
6971 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6972 /* XXX: might not be 66MHz */
ac58c3f0 6973 i9xx_clock(66000, &clock);
79e53945 6974 } else
ac58c3f0 6975 i9xx_clock(48000, &clock);
79e53945
JB		 6976 } else {
6977 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6978 clock.p1 = 2;
6979 else {
6980 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6981 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6982 }
6983 if (dpll & PLL_P2_DIVIDE_BY_4)
6984 clock.p2 = 4;
6985 else
6986 clock.p2 = 2;
6987
ac58c3f0 6988 i9xx_clock(48000, &clock);
79e53945
JB		 6989 }
6990 }
6991
6992 /* XXX: It would be nice to validate the clocks, but we can't reuse
6993 * i830PllIsValid() because it relies on the xf86_config connector
6994 * configuration being accurate, which it isn't necessarily.
6995 */
6996
6997 return clock.dot;
6998}
6999
7000/** Returns the currently programmed mode of the given pipe. */
7001struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7002 struct drm_crtc *crtc)
7003{
548f245b 7004 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7006 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7007 struct drm_display_mode *mode;
fe2b8f9d
PZ		 7008 int htot = I915_READ(HTOTAL(cpu_transcoder));
7009 int hsync = I915_READ(HSYNC(cpu_transcoder));
7010 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7011 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7012
7013 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7014 if (!mode)
7015 return NULL;
7016
7017 mode->clock = intel_crtc_clock_get(dev, crtc);
7018 mode->hdisplay = (htot & 0xffff) + 1;
7019 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7020 mode->hsync_start = (hsync & 0xffff) + 1;
7021 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7022 mode->vdisplay = (vtot & 0xffff) + 1;
7023 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7024 mode->vsync_start = (vsync & 0xffff) + 1;
7025 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7026
7027 drm_mode_set_name(mode);
79e53945
JB		 7028
7029 return mode;
7030}
7031
3dec0095 7032static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7033{
7034 struct drm_device *dev = crtc->dev;
7035 drm_i915_private_t *dev_priv = dev->dev_private;
7036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7037 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7038 int dpll_reg = DPLL(pipe);
7039 int dpll;
652c393a 7040
bad720ff 7041 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7042 return;
7043
7044 if (!dev_priv->lvds_downclock_avail)
7045 return;
7046
dbdc6479 7047 dpll = I915_READ(dpll_reg);
652c393a 7048 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7049 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7050
8ac5a6d5 7051 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7052
7053 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7054 I915_WRITE(dpll_reg, dpll);
9d0498a2 7055 intel_wait_for_vblank(dev, pipe);
dbdc6479 7056
652c393a
JB		 7057 dpll = I915_READ(dpll_reg);
7058 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7059 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7060 }
652c393a
JB		 7061}
7062
7063static void intel_decrease_pllclock(struct drm_crtc *crtc)
7064{
7065 struct drm_device *dev = crtc->dev;
7066 drm_i915_private_t *dev_priv = dev->dev_private;
7067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7068
bad720ff 7069 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7070 return;
7071
7072 if (!dev_priv->lvds_downclock_avail)
7073 return;
7074
7075 /*
7076 * Since this is called by a timer, we should never get here in
7077 * the manual case.
7078 */
7079 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7080 int pipe = intel_crtc->pipe;
7081 int dpll_reg = DPLL(pipe);
7082 int dpll;
f6e5b160 7083
44d98a61 7084 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7085
8ac5a6d5 7086 assert_panel_unlocked(dev_priv, pipe);
652c393a 7087
dc257cf1 7088 dpll = I915_READ(dpll_reg);
652c393a
JB		 7089 dpll |= DISPLAY_RATE_SELECT_FPA1;
7090 I915_WRITE(dpll_reg, dpll);
9d0498a2 7091 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7092 dpll = I915_READ(dpll_reg);
7093 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7094 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7095 }
7096
7097}
7098
f047e395
CW		 7099void intel_mark_busy(struct drm_device *dev)
7100{
f047e395
CW		 7101 i915_update_gfx_val(dev->dev_private);
7102}
7103
7104void intel_mark_idle(struct drm_device *dev)
652c393a 7105{
652c393a 7106 struct drm_crtc *crtc;
652c393a
JB		 7107
7108 if (!i915_powersave)
7109 return;
7110
652c393a 7111 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7112 if (!crtc->fb)
7113 continue;
7114
725a5b54 7115 intel_decrease_pllclock(crtc);
652c393a 7116 }
652c393a
JB		 7117}
7118
c65355bb
CW		 7119void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7120 struct intel_ring_buffer *ring)
652c393a 7121{
f047e395
CW		 7122 struct drm_device *dev = obj->base.dev;
7123 struct drm_crtc *crtc;
652c393a 7124
f047e395 7125 if (!i915_powersave)
acb87dfb
CW		 7126 return;
7127
652c393a
JB		 7128 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7129 if (!crtc->fb)
7130 continue;
7131
c65355bb
CW		 7132 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7133 continue;
7134
7135 intel_increase_pllclock(crtc);
7136 if (ring && intel_fbc_enabled(dev))
7137 ring->fbc_dirty = true;
652c393a
JB		 7138 }
7139}
7140
79e53945
JB		 7141static void intel_crtc_destroy(struct drm_crtc *crtc)
7142{
7143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7144 struct drm_device *dev = crtc->dev;
7145 struct intel_unpin_work *work;
7146 unsigned long flags;
7147
7148 spin_lock_irqsave(&dev->event_lock, flags);
7149 work = intel_crtc->unpin_work;
7150 intel_crtc->unpin_work = NULL;
7151 spin_unlock_irqrestore(&dev->event_lock, flags);
7152
7153 if (work) {
7154 cancel_work_sync(&work->work);
7155 kfree(work);
7156 }
79e53945 7157
40ccc72b
MK		 7158 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7159
79e53945 7160 drm_crtc_cleanup(crtc);
67e77c5a 7161
79e53945
JB		 7162 kfree(intel_crtc);
7163}
7164
6b95a207
KH		 7165static void intel_unpin_work_fn(struct work_struct *__work)
7166{
7167 struct intel_unpin_work *work =
7168 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7169 struct drm_device *dev = work->crtc->dev;
6b95a207 7170
b4a98e57 7171 mutex_lock(&dev->struct_mutex);
1690e1eb 7172 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7173 drm_gem_object_unreference(&work->pending_flip_obj->base);
7174 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7175
b4a98e57
CW		 7176 intel_update_fbc(dev);
7177 mutex_unlock(&dev->struct_mutex);
7178
7179 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7180 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7181
6b95a207
KH		 7182 kfree(work);
7183}
7184
1afe3e9d 7185static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7186 struct drm_crtc *crtc)
6b95a207
KH		 7187{
7188 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7190 struct intel_unpin_work *work;
6b95a207
KH		 7191 unsigned long flags;
7192
7193 /* Ignore early vblank irqs */
7194 if (intel_crtc == NULL)
7195 return;
7196
7197 spin_lock_irqsave(&dev->event_lock, flags);
7198 work = intel_crtc->unpin_work;
e7d841ca
CW		 7199
7200 /* Ensure we don't miss a work->pending update ... */
7201 smp_rmb();
7202
7203 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7204 spin_unlock_irqrestore(&dev->event_lock, flags);
7205 return;
7206 }
7207
e7d841ca
CW		 7208 /* and that the unpin work is consistent wrt ->pending. */
7209 smp_rmb();
7210
6b95a207 7211 intel_crtc->unpin_work = NULL;
6b95a207 7212
45a066eb
RC		 7213 if (work->event)
7214 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7215
0af7e4df
MK		 7216 drm_vblank_put(dev, intel_crtc->pipe);
7217
6b95a207
KH		 7218 spin_unlock_irqrestore(&dev->event_lock, flags);
7219
2c10d571 7220 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7221
7222 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7223
7224 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7225}
7226
1afe3e9d
JB		 7227void intel_finish_page_flip(struct drm_device *dev, int pipe)
7228{
7229 drm_i915_private_t *dev_priv = dev->dev_private;
7230 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7231
49b14a5c 7232 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7233}
7234
7235void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7236{
7237 drm_i915_private_t *dev_priv = dev->dev_private;
7238 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7239
49b14a5c 7240 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7241}
7242
6b95a207
KH		 7243void intel_prepare_page_flip(struct drm_device *dev, int plane)
7244{
7245 drm_i915_private_t *dev_priv = dev->dev_private;
7246 struct intel_crtc *intel_crtc =
7247 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7248 unsigned long flags;
7249
e7d841ca
CW		 7250 /* NB: An MMIO update of the plane base pointer will also
7251 * generate a page-flip completion irq, i.e. every modeset
7252 * is also accompanied by a spurious intel_prepare_page_flip().
7253 */
6b95a207 7254 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7255 if (intel_crtc->unpin_work)
7256 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7257 spin_unlock_irqrestore(&dev->event_lock, flags);
7258}
7259
e7d841ca
CW		 7260inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7261{
7262 /* Ensure that the work item is consistent when activating it ... */
7263 smp_wmb();
7264 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7265 /* and that it is marked active as soon as the irq could fire. */
7266 smp_wmb();
7267}
7268
8c9f3aaf
JB		 7269static int intel_gen2_queue_flip(struct drm_device *dev,
7270 struct drm_crtc *crtc,
7271 struct drm_framebuffer *fb,
7272 struct drm_i915_gem_object *obj)
7273{
7274 struct drm_i915_private *dev_priv = dev->dev_private;
7275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7276 u32 flip_mask;
6d90c952 7277 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7278 int ret;
7279
6d90c952 7280 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7281 if (ret)
83d4092b 7282 goto err;
8c9f3aaf 7283
6d90c952 7284 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7285 if (ret)
83d4092b 7286 goto err_unpin;
8c9f3aaf
JB		 7287
7288 /* Can't queue multiple flips, so wait for the previous
7289 * one to finish before executing the next.
7290 */
7291 if (intel_crtc->plane)
7292 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7293 else
7294 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7295 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7296 intel_ring_emit(ring, MI_NOOP);
7297 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7298 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7299 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7300 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7301 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7302
7303 intel_mark_page_flip_active(intel_crtc);
6d90c952 7304 intel_ring_advance(ring);
83d4092b
CW		 7305 return 0;
7306
7307err_unpin:
7308 intel_unpin_fb_obj(obj);
7309err:
8c9f3aaf
JB		 7310 return ret;
7311}
7312
7313static int intel_gen3_queue_flip(struct drm_device *dev,
7314 struct drm_crtc *crtc,
7315 struct drm_framebuffer *fb,
7316 struct drm_i915_gem_object *obj)
7317{
7318 struct drm_i915_private *dev_priv = dev->dev_private;
7319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7320 u32 flip_mask;
6d90c952 7321 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7322 int ret;
7323
6d90c952 7324 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7325 if (ret)
83d4092b 7326 goto err;
8c9f3aaf 7327
6d90c952 7328 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7329 if (ret)
83d4092b 7330 goto err_unpin;
8c9f3aaf
JB		 7331
7332 if (intel_crtc->plane)
7333 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7334 else
7335 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7336 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7337 intel_ring_emit(ring, MI_NOOP);
7338 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7339 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7340 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7341 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7342 intel_ring_emit(ring, MI_NOOP);
7343
e7d841ca 7344 intel_mark_page_flip_active(intel_crtc);
6d90c952 7345 intel_ring_advance(ring);
83d4092b
CW		 7346 return 0;
7347
7348err_unpin:
7349 intel_unpin_fb_obj(obj);
7350err:
8c9f3aaf
JB		 7351 return ret;
7352}
7353
7354static int intel_gen4_queue_flip(struct drm_device *dev,
7355 struct drm_crtc *crtc,
7356 struct drm_framebuffer *fb,
7357 struct drm_i915_gem_object *obj)
7358{
7359 struct drm_i915_private *dev_priv = dev->dev_private;
7360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7361 uint32_t pf, pipesrc;
6d90c952 7362 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7363 int ret;
7364
6d90c952 7365 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7366 if (ret)
83d4092b 7367 goto err;
8c9f3aaf 7368
6d90c952 7369 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7370 if (ret)
83d4092b 7371 goto err_unpin;
8c9f3aaf
JB		 7372
7373 /* i965+ uses the linear or tiled offsets from the
7374 * Display Registers (which do not change across a page-flip)
7375 * so we need only reprogram the base address.
7376 */
6d90c952
DV		 7377 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7378 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7379 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7380 intel_ring_emit(ring,
7381 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7382 obj->tiling_mode);
8c9f3aaf
JB		 7383
7384 /* XXX Enabling the panel-fitter across page-flip is so far
7385 * untested on non-native modes, so ignore it for now.
7386 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7387 */
7388 pf = 0;
7389 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7390 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7391
7392 intel_mark_page_flip_active(intel_crtc);
6d90c952 7393 intel_ring_advance(ring);
83d4092b
CW		 7394 return 0;
7395
7396err_unpin:
7397 intel_unpin_fb_obj(obj);
7398err:
8c9f3aaf
JB		 7399 return ret;
7400}
7401
7402static int intel_gen6_queue_flip(struct drm_device *dev,
7403 struct drm_crtc *crtc,
7404 struct drm_framebuffer *fb,
7405 struct drm_i915_gem_object *obj)
7406{
7407 struct drm_i915_private *dev_priv = dev->dev_private;
7408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7409 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7410 uint32_t pf, pipesrc;
7411 int ret;
7412
6d90c952 7413 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7414 if (ret)
83d4092b 7415 goto err;
8c9f3aaf 7416
6d90c952 7417 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7418 if (ret)
83d4092b 7419 goto err_unpin;
8c9f3aaf 7420
6d90c952
DV		 7421 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7422 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7423 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7424 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7425
dc257cf1
DV		 7426 /* Contrary to the suggestions in the documentation,
7427 * "Enable Panel Fitter" does not seem to be required when page
7428 * flipping with a non-native mode, and worse causes a normal
7429 * modeset to fail.
7430 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7431 */
7432 pf = 0;
8c9f3aaf 7433 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7434 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7435
7436 intel_mark_page_flip_active(intel_crtc);
6d90c952 7437 intel_ring_advance(ring);
83d4092b
CW		 7438 return 0;
7439
7440err_unpin:
7441 intel_unpin_fb_obj(obj);
7442err:
8c9f3aaf
JB		 7443 return ret;
7444}
7445
7c9017e5
JB		 7446/*
7447 * On gen7 we currently use the blit ring because (in early silicon at least)
7448 * the render ring doesn't give us interrpts for page flip completion, which
7449 * means clients will hang after the first flip is queued. Fortunately the
7450 * blit ring generates interrupts properly, so use it instead.
7451 */
7452static int intel_gen7_queue_flip(struct drm_device *dev,
7453 struct drm_crtc *crtc,
7454 struct drm_framebuffer *fb,
7455 struct drm_i915_gem_object *obj)
7456{
7457 struct drm_i915_private *dev_priv = dev->dev_private;
7458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7459 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7460 uint32_t plane_bit = 0;
7c9017e5
JB		 7461 int ret;
7462
7463 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7464 if (ret)
83d4092b 7465 goto err;
7c9017e5 7466
cb05d8de
DV		 7467 switch(intel_crtc->plane) {
7468 case PLANE_A:
7469 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7470 break;
7471 case PLANE_B:
7472 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7473 break;
7474 case PLANE_C:
7475 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7476 break;
7477 default:
7478 WARN_ONCE(1, "unknown plane in flip command\n");
7479 ret = -ENODEV;
ab3951eb 7480 goto err_unpin;
cb05d8de
DV		 7481 }
7482
7c9017e5
JB		 7483 ret = intel_ring_begin(ring, 4);
7484 if (ret)
83d4092b 7485 goto err_unpin;
7c9017e5 7486
cb05d8de 7487 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7488 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7489 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7490 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7491
7492 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7493 intel_ring_advance(ring);
83d4092b
CW		 7494 return 0;
7495
7496err_unpin:
7497 intel_unpin_fb_obj(obj);
7498err:
7c9017e5
JB		 7499 return ret;
7500}
7501
8c9f3aaf
JB		 7502static int intel_default_queue_flip(struct drm_device *dev,
7503 struct drm_crtc *crtc,
7504 struct drm_framebuffer *fb,
7505 struct drm_i915_gem_object *obj)
7506{
7507 return -ENODEV;
7508}
7509
6b95a207
KH		 7510static int intel_crtc_page_flip(struct drm_crtc *crtc,
7511 struct drm_framebuffer *fb,
7512 struct drm_pending_vblank_event *event)
7513{
7514 struct drm_device *dev = crtc->dev;
7515 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7516 struct drm_framebuffer *old_fb = crtc->fb;
7517 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7519 struct intel_unpin_work *work;
8c9f3aaf 7520 unsigned long flags;
52e68630 7521 int ret;
6b95a207 7522
e6a595d2
VS		 7523 /* Can't change pixel format via MI display flips. */
7524 if (fb->pixel_format != crtc->fb->pixel_format)
7525 return -EINVAL;
7526
7527 /*
7528 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7529 * Note that pitch changes could also affect these register.
7530 */
7531 if (INTEL_INFO(dev)->gen > 3 &&
7532 (fb->offsets[0] != crtc->fb->offsets[0] ||
7533 fb->pitches[0] != crtc->fb->pitches[0]))
7534 return -EINVAL;
7535
6b95a207
KH		 7536 work = kzalloc(sizeof *work, GFP_KERNEL);
7537 if (work == NULL)
7538 return -ENOMEM;
7539
6b95a207 7540 work->event = event;
b4a98e57 7541 work->crtc = crtc;
4a35f83b 7542 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7543 INIT_WORK(&work->work, intel_unpin_work_fn);
7544
7317c75e
JB		 7545 ret = drm_vblank_get(dev, intel_crtc->pipe);
7546 if (ret)
7547 goto free_work;
7548
6b95a207
KH		 7549 /* We borrow the event spin lock for protecting unpin_work */
7550 spin_lock_irqsave(&dev->event_lock, flags);
7551 if (intel_crtc->unpin_work) {
7552 spin_unlock_irqrestore(&dev->event_lock, flags);
7553 kfree(work);
7317c75e 7554 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7555
7556 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7557 return -EBUSY;
7558 }
7559 intel_crtc->unpin_work = work;
7560 spin_unlock_irqrestore(&dev->event_lock, flags);
7561
b4a98e57
CW		 7562 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7563 flush_workqueue(dev_priv->wq);
7564
79158103
CW		 7565 ret = i915_mutex_lock_interruptible(dev);
7566 if (ret)
7567 goto cleanup;
6b95a207 7568
75dfca80 7569 /* Reference the objects for the scheduled work. */
05394f39
CW		 7570 drm_gem_object_reference(&work->old_fb_obj->base);
7571 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7572
7573 crtc->fb = fb;
96b099fd 7574
e1f99ce6 7575 work->pending_flip_obj = obj;
e1f99ce6 7576
4e5359cd
SF		 7577 work->enable_stall_check = true;
7578
b4a98e57 7579 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7580 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7581
8c9f3aaf
JB		 7582 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7583 if (ret)
7584 goto cleanup_pending;
6b95a207 7585
7782de3b 7586 intel_disable_fbc(dev);
c65355bb 7587 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 7588 mutex_unlock(&dev->struct_mutex);
7589
e5510fac
JB		 7590 trace_i915_flip_request(intel_crtc->plane, obj);
7591
6b95a207 7592 return 0;
96b099fd 7593
8c9f3aaf 7594cleanup_pending:
b4a98e57 7595 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7596 crtc->fb = old_fb;
05394f39
CW		 7597 drm_gem_object_unreference(&work->old_fb_obj->base);
7598 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7599 mutex_unlock(&dev->struct_mutex);
7600
79158103 7601cleanup:
96b099fd
CW		 7602 spin_lock_irqsave(&dev->event_lock, flags);
7603 intel_crtc->unpin_work = NULL;
7604 spin_unlock_irqrestore(&dev->event_lock, flags);
7605
7317c75e
JB		 7606 drm_vblank_put(dev, intel_crtc->pipe);
7607free_work:
96b099fd
CW		 7608 kfree(work);
7609
7610 return ret;
6b95a207
KH		 7611}
7612
f6e5b160 7613static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7614 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7615 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7616};
7617
50f56119
DV		 7618static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7619 struct drm_crtc *crtc)
7620{
7621 struct drm_device *dev;
7622 struct drm_crtc *tmp;
7623 int crtc_mask = 1;
47f1c6c9 7624
50f56119 7625 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7626
50f56119 7627 dev = crtc->dev;
47f1c6c9 7628
50f56119
DV		 7629 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7630 if (tmp == crtc)
7631 break;
7632 crtc_mask <<= 1;
7633 }
47f1c6c9 7634
50f56119
DV		 7635 if (encoder->possible_crtcs & crtc_mask)
7636 return true;
7637 return false;
47f1c6c9 7638}
79e53945 7639
9a935856
DV		 7640/**
7641 * intel_modeset_update_staged_output_state
7642 *
7643 * Updates the staged output configuration state, e.g. after we've read out the
7644 * current hw state.
7645 */
7646static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7647{
9a935856
DV		 7648 struct intel_encoder *encoder;
7649 struct intel_connector *connector;
f6e5b160 7650
9a935856
DV		 7651 list_for_each_entry(connector, &dev->mode_config.connector_list,
7652 base.head) {
7653 connector->new_encoder =
7654 to_intel_encoder(connector->base.encoder);
7655 }
f6e5b160 7656
9a935856
DV		 7657 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7658 base.head) {
7659 encoder->new_crtc =
7660 to_intel_crtc(encoder->base.crtc);
7661 }
f6e5b160
CW		 7662}
7663
9a935856
DV		 7664/**
7665 * intel_modeset_commit_output_state
7666 *
7667 * This function copies the stage display pipe configuration to the real one.
7668 */
7669static void intel_modeset_commit_output_state(struct drm_device *dev)
7670{
7671 struct intel_encoder *encoder;
7672 struct intel_connector *connector;
f6e5b160 7673
9a935856
DV		 7674 list_for_each_entry(connector, &dev->mode_config.connector_list,
7675 base.head) {
7676 connector->base.encoder = &connector->new_encoder->base;
7677 }
f6e5b160 7678
9a935856
DV		 7679 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7680 base.head) {
7681 encoder->base.crtc = &encoder->new_crtc->base;
7682 }
7683}
7684
050f7aeb
DV		 7685static void
7686connected_sink_compute_bpp(struct intel_connector * connector,
7687 struct intel_crtc_config *pipe_config)
7688{
7689 int bpp = pipe_config->pipe_bpp;
7690
7691 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7692 connector->base.base.id,
7693 drm_get_connector_name(&connector->base));
7694
7695 /* Don't use an invalid EDID bpc value */
7696 if (connector->base.display_info.bpc &&
7697 connector->base.display_info.bpc * 3 < bpp) {
7698 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7699 bpp, connector->base.display_info.bpc*3);
7700 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7701 }
7702
7703 /* Clamp bpp to 8 on screens without EDID 1.4 */
7704 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7705 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7706 bpp);
7707 pipe_config->pipe_bpp = 24;
7708 }
7709}
7710
4e53c2e0 7711static int
050f7aeb
DV		 7712compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7713 struct drm_framebuffer *fb,
7714 struct intel_crtc_config *pipe_config)
4e53c2e0 7715{
050f7aeb
DV		 7716 struct drm_device *dev = crtc->base.dev;
7717 struct intel_connector *connector;
4e53c2e0
DV		 7718 int bpp;
7719
d42264b1
DV		 7720 switch (fb->pixel_format) {
7721 case DRM_FORMAT_C8:
4e53c2e0
DV		 7722 bpp = 8*3; /* since we go through a colormap */
7723 break;
d42264b1
DV		 7724 case DRM_FORMAT_XRGB1555:
7725 case DRM_FORMAT_ARGB1555:
7726 /* checked in intel_framebuffer_init already */
7727 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7728 return -EINVAL;
7729 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7730 bpp = 6*3; /* min is 18bpp */
7731 break;
d42264b1
DV		 7732 case DRM_FORMAT_XBGR8888:
7733 case DRM_FORMAT_ABGR8888:
7734 /* checked in intel_framebuffer_init already */
7735 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7736 return -EINVAL;
7737 case DRM_FORMAT_XRGB8888:
7738 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7739 bpp = 8*3;
7740 break;
d42264b1
DV		 7741 case DRM_FORMAT_XRGB2101010:
7742 case DRM_FORMAT_ARGB2101010:
7743 case DRM_FORMAT_XBGR2101010:
7744 case DRM_FORMAT_ABGR2101010:
7745 /* checked in intel_framebuffer_init already */
7746 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7747 return -EINVAL;
4e53c2e0
DV		 7748 bpp = 10*3;
7749 break;
baba133a 7750 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7751 default:
7752 DRM_DEBUG_KMS("unsupported depth\n");
7753 return -EINVAL;
7754 }
7755
4e53c2e0
DV		 7756 pipe_config->pipe_bpp = bpp;
7757
7758 /* Clamp display bpp to EDID value */
7759 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7760 base.head) {
1b829e05
DV		 7761 if (!connector->new_encoder ||
7762 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7763 continue;
7764
050f7aeb 7765 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7766 }
7767
7768 return bpp;
7769}
7770
c0b03411
DV		 7771static void intel_dump_pipe_config(struct intel_crtc *crtc,
7772 struct intel_crtc_config *pipe_config,
7773 const char *context)
7774{
7775 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7776 context, pipe_name(crtc->pipe));
7777
7778 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7779 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7780 pipe_config->pipe_bpp, pipe_config->dither);
7781 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7782 pipe_config->has_pch_encoder,
7783 pipe_config->fdi_lanes,
7784 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7785 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7786 pipe_config->fdi_m_n.tu);
7787 DRM_DEBUG_KMS("requested mode:\n");
7788 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7789 DRM_DEBUG_KMS("adjusted mode:\n");
7790 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7791 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7792 pipe_config->gmch_pfit.control,
7793 pipe_config->gmch_pfit.pgm_ratios,
7794 pipe_config->gmch_pfit.lvds_border_bits);
7795 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7796 pipe_config->pch_pfit.pos,
7797 pipe_config->pch_pfit.size);
42db64ef 7798 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7799}
7800
accfc0c5
DV		 7801static bool check_encoder_cloning(struct drm_crtc *crtc)
7802{
7803 int num_encoders = 0;
7804 bool uncloneable_encoders = false;
7805 struct intel_encoder *encoder;
7806
7807 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7808 base.head) {
7809 if (&encoder->new_crtc->base != crtc)
7810 continue;
7811
7812 num_encoders++;
7813 if (!encoder->cloneable)
7814 uncloneable_encoders = true;
7815 }
7816
7817 return !(num_encoders > 1 && uncloneable_encoders);
7818}
7819
b8cecdf5
DV		 7820static struct intel_crtc_config *
7821intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7822 struct drm_framebuffer *fb,
b8cecdf5 7823 struct drm_display_mode *mode)
ee7b9f93 7824{
7758a113 7825 struct drm_device *dev = crtc->dev;
7758a113
DV		 7826 struct drm_encoder_helper_funcs *encoder_funcs;
7827 struct intel_encoder *encoder;
b8cecdf5 7828 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7829 int plane_bpp, ret = -EINVAL;
7830 bool retry = true;
ee7b9f93 7831
accfc0c5
DV		 7832 if (!check_encoder_cloning(crtc)) {
7833 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7834 return ERR_PTR(-EINVAL);
7835 }
7836
b8cecdf5
DV		 7837 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7838 if (!pipe_config)
7758a113
DV		 7839 return ERR_PTR(-ENOMEM);
7840
b8cecdf5
DV		 7841 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7842 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7843 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
b8cecdf5 7844
050f7aeb
DV		 7845 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7846 * plane pixel format and any sink constraints into account. Returns the
7847 * source plane bpp so that dithering can be selected on mismatches
7848 * after encoders and crtc also have had their say. */
7849 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7850 fb, pipe_config);
4e53c2e0
DV		 7851 if (plane_bpp < 0)
7852 goto fail;
7853
e29c22c0 7854encoder_retry:
ef1b460d 7855 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 7856 pipe_config->port_clock = 0;
ef1b460d 7857 pipe_config->pixel_multiplier = 1;
ff9a6750 7858
7758a113
DV		 7859 /* Pass our mode to the connectors and the CRTC to give them a chance to
7860 * adjust it according to limitations or connector properties, and also
7861 * a chance to reject the mode entirely.
47f1c6c9 7862 */
7758a113
DV		 7863 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7864 base.head) {
47f1c6c9 7865
7758a113
DV		 7866 if (&encoder->new_crtc->base != crtc)
7867 continue;
7ae89233
DV		 7868
7869 if (encoder->compute_config) {
7870 if (!(encoder->compute_config(encoder, pipe_config))) {
7871 DRM_DEBUG_KMS("Encoder config failure\n");
7872 goto fail;
7873 }
7874
7875 continue;
7876 }
7877
7758a113 7878 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7879 if (!(encoder_funcs->mode_fixup(&encoder->base,
7880 &pipe_config->requested_mode,
7881 &pipe_config->adjusted_mode))) {
7758a113
DV		 7882 DRM_DEBUG_KMS("Encoder fixup failed\n");
7883 goto fail;
7884 }
ee7b9f93 7885 }
47f1c6c9 7886
ff9a6750
DV		 7887 /* Set default port clock if not overwritten by the encoder. Needs to be
7888 * done afterwards in case the encoder adjusts the mode. */
7889 if (!pipe_config->port_clock)
7890 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7891
e29c22c0
DV		 7892 ret = intel_crtc_compute_config(crtc, pipe_config);
7893 if (ret < 0) {
7758a113
DV		 7894 DRM_DEBUG_KMS("CRTC fixup failed\n");
7895 goto fail;
ee7b9f93 7896 }
e29c22c0
DV		 7897
7898 if (ret == RETRY) {
7899 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7900 ret = -EINVAL;
7901 goto fail;
7902 }
7903
7904 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7905 retry = false;
7906 goto encoder_retry;
7907 }
7908
4e53c2e0
DV		 7909 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7910 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7911 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7912
b8cecdf5 7913 return pipe_config;
7758a113 7914fail:
b8cecdf5 7915 kfree(pipe_config);
e29c22c0 7916 return ERR_PTR(ret);
ee7b9f93 7917}
47f1c6c9 7918
e2e1ed41
DV		 7919/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7920 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7921static void
7922intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7923 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7924{
7925 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7926 struct drm_device *dev = crtc->dev;
7927 struct intel_encoder *encoder;
7928 struct intel_connector *connector;
7929 struct drm_crtc *tmp_crtc;
79e53945 7930
e2e1ed41 7931 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7932
e2e1ed41
DV		 7933 /* Check which crtcs have changed outputs connected to them, these need
7934 * to be part of the prepare_pipes mask. We don't (yet) support global
7935 * modeset across multiple crtcs, so modeset_pipes will only have one
7936 * bit set at most. */
7937 list_for_each_entry(connector, &dev->mode_config.connector_list,
7938 base.head) {
7939 if (connector->base.encoder == &connector->new_encoder->base)
7940 continue;
79e53945 7941
e2e1ed41
DV		 7942 if (connector->base.encoder) {
7943 tmp_crtc = connector->base.encoder->crtc;
7944
7945 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7946 }
7947
7948 if (connector->new_encoder)
7949 *prepare_pipes |=
7950 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7951 }
7952
e2e1ed41
DV		 7953 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7954 base.head) {
7955 if (encoder->base.crtc == &encoder->new_crtc->base)
7956 continue;
7957
7958 if (encoder->base.crtc) {
7959 tmp_crtc = encoder->base.crtc;
7960
7961 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7962 }
7963
7964 if (encoder->new_crtc)
7965 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7966 }
7967
e2e1ed41
DV		 7968 /* Check for any pipes that will be fully disabled ... */
7969 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7970 base.head) {
7971 bool used = false;
22fd0fab 7972
e2e1ed41
DV		 7973 /* Don't try to disable disabled crtcs. */
7974 if (!intel_crtc->base.enabled)
7975 continue;
7e7d76c3 7976
e2e1ed41
DV		 7977 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7978 base.head) {
7979 if (encoder->new_crtc == intel_crtc)
7980 used = true;
7981 }
7982
7983 if (!used)
7984 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7985 }
7986
e2e1ed41
DV		 7987
7988 /* set_mode is also used to update properties on life display pipes. */
7989 intel_crtc = to_intel_crtc(crtc);
7990 if (crtc->enabled)
7991 *prepare_pipes |= 1 << intel_crtc->pipe;
7992
b6c5164d
DV		 7993 /*
7994 * For simplicity do a full modeset on any pipe where the output routing
7995 * changed. We could be more clever, but that would require us to be
7996 * more careful with calling the relevant encoder->mode_set functions.
7997 */
e2e1ed41
DV		 7998 if (*prepare_pipes)
7999 *modeset_pipes = *prepare_pipes;
8000
8001 /* ... and mask these out. */
8002 *modeset_pipes &= ~(*disable_pipes);
8003 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8004
8005 /*
8006 * HACK: We don't (yet) fully support global modesets. intel_set_config
8007 * obies this rule, but the modeset restore mode of
8008 * intel_modeset_setup_hw_state does not.
8009 */
8010 *modeset_pipes &= 1 << intel_crtc->pipe;
8011 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8012
8013 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8014 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8015}
79e53945 8016
ea9d758d 8017static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8018{
ea9d758d 8019 struct drm_encoder *encoder;
f6e5b160 8020 struct drm_device *dev = crtc->dev;
f6e5b160 8021
ea9d758d
DV		 8022 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8023 if (encoder->crtc == crtc)
8024 return true;
8025
8026 return false;
8027}
8028
8029static void
8030intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8031{
8032 struct intel_encoder *intel_encoder;
8033 struct intel_crtc *intel_crtc;
8034 struct drm_connector *connector;
8035
8036 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8037 base.head) {
8038 if (!intel_encoder->base.crtc)
8039 continue;
8040
8041 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8042
8043 if (prepare_pipes & (1 << intel_crtc->pipe))
8044 intel_encoder->connectors_active = false;
8045 }
8046
8047 intel_modeset_commit_output_state(dev);
8048
8049 /* Update computed state. */
8050 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8051 base.head) {
8052 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8053 }
8054
8055 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8056 if (!connector->encoder || !connector->encoder->crtc)
8057 continue;
8058
8059 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8060
8061 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8062 struct drm_property *dpms_property =
8063 dev->mode_config.dpms_property;
8064
ea9d758d 8065 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8066 drm_object_property_set_value(&connector->base,
68d34720
DV		 8067 dpms_property,
8068 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8069
8070 intel_encoder = to_intel_encoder(connector->encoder);
8071 intel_encoder->connectors_active = true;
8072 }
8073 }
8074
8075}
8076
25c5b266
DV		 8077#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8078 list_for_each_entry((intel_crtc), \
8079 &(dev)->mode_config.crtc_list, \
8080 base.head) \
0973f18f 8081 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8082
0e8ffe1b 8083static bool
2fa2fe9a
DV		 8084intel_pipe_config_compare(struct drm_device *dev,
8085 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8086 struct intel_crtc_config *pipe_config)
8087{
08a24034
DV		 8088#define PIPE_CONF_CHECK_I(name) \
8089 if (current_config->name != pipe_config->name) { \
8090 DRM_ERROR("mismatch in " #name " " \
8091 "(expected %i, found %i)\n", \
8092 current_config->name, \
8093 pipe_config->name); \
8094 return false; \
88adfff1
DV		 8095 }
8096
1bd1bd80
DV		 8097#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8098 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8099 DRM_ERROR("mismatch in " #name " " \
8100 "(expected %i, found %i)\n", \
8101 current_config->name & (mask), \
8102 pipe_config->name & (mask)); \
8103 return false; \
8104 }
8105
bb760063
DV		 8106#define PIPE_CONF_QUIRK(quirk) \
8107 ((current_config->quirks | pipe_config->quirks) & (quirk))
8108
eccb140b
DV		 8109 PIPE_CONF_CHECK_I(cpu_transcoder);
8110
08a24034
DV		 8111 PIPE_CONF_CHECK_I(has_pch_encoder);
8112 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8113 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8114 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8115 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8116 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8117 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8118
1bd1bd80
DV		 8119 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8120 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8121 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8122 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8123 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8124 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8125
8126 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8127 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8128 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8129 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8130 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8131 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8132
6c49f241
DV		 8133 if (!HAS_PCH_SPLIT(dev))
8134 PIPE_CONF_CHECK_I(pixel_multiplier);
8135
1bd1bd80
DV		 8136 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8137 DRM_MODE_FLAG_INTERLACE);
8138
bb760063
DV		 8139 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8140 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8141 DRM_MODE_FLAG_PHSYNC);
8142 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8143 DRM_MODE_FLAG_NHSYNC);
8144 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8145 DRM_MODE_FLAG_PVSYNC);
8146 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8147 DRM_MODE_FLAG_NVSYNC);
8148 }
045ac3b5 8149
1bd1bd80
DV		 8150 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8151 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8152
2fa2fe9a
DV		 8153 PIPE_CONF_CHECK_I(gmch_pfit.control);
8154 /* pfit ratios are autocomputed by the hw on gen4+ */
8155 if (INTEL_INFO(dev)->gen < 4)
8156 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8157 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8158 PIPE_CONF_CHECK_I(pch_pfit.pos);
8159 PIPE_CONF_CHECK_I(pch_pfit.size);
8160
42db64ef
PZ		 8161 PIPE_CONF_CHECK_I(ips_enabled);
8162
08a24034 8163#undef PIPE_CONF_CHECK_I
1bd1bd80 8164#undef PIPE_CONF_CHECK_FLAGS
bb760063 8165#undef PIPE_CONF_QUIRK
627eb5a3 8166
0e8ffe1b
DV		 8167 return true;
8168}
8169
b980514c 8170void
8af6cf88
DV		 8171intel_modeset_check_state(struct drm_device *dev)
8172{
0e8ffe1b 8173 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 8174 struct intel_crtc *crtc;
8175 struct intel_encoder *encoder;
8176 struct intel_connector *connector;
0e8ffe1b 8177 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8178
8179 list_for_each_entry(connector, &dev->mode_config.connector_list,
8180 base.head) {
8181 /* This also checks the encoder/connector hw state with the
8182 * ->get_hw_state callbacks. */
8183 intel_connector_check_state(connector);
8184
8185 WARN(&connector->new_encoder->base != connector->base.encoder,
8186 "connector's staged encoder doesn't match current encoder\n");
8187 }
8188
8189 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8190 base.head) {
8191 bool enabled = false;
8192 bool active = false;
8193 enum pipe pipe, tracked_pipe;
8194
8195 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8196 encoder->base.base.id,
8197 drm_get_encoder_name(&encoder->base));
8198
8199 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8200 "encoder's stage crtc doesn't match current crtc\n");
8201 WARN(encoder->connectors_active && !encoder->base.crtc,
8202 "encoder's active_connectors set, but no crtc\n");
8203
8204 list_for_each_entry(connector, &dev->mode_config.connector_list,
8205 base.head) {
8206 if (connector->base.encoder != &encoder->base)
8207 continue;
8208 enabled = true;
8209 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8210 active = true;
8211 }
8212 WARN(!!encoder->base.crtc != enabled,
8213 "encoder's enabled state mismatch "
8214 "(expected %i, found %i)\n",
8215 !!encoder->base.crtc, enabled);
8216 WARN(active && !encoder->base.crtc,
8217 "active encoder with no crtc\n");
8218
8219 WARN(encoder->connectors_active != active,
8220 "encoder's computed active state doesn't match tracked active state "
8221 "(expected %i, found %i)\n", active, encoder->connectors_active);
8222
8223 active = encoder->get_hw_state(encoder, &pipe);
8224 WARN(active != encoder->connectors_active,
8225 "encoder's hw state doesn't match sw tracking "
8226 "(expected %i, found %i)\n",
8227 encoder->connectors_active, active);
8228
8229 if (!encoder->base.crtc)
8230 continue;
8231
8232 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8233 WARN(active && pipe != tracked_pipe,
8234 "active encoder's pipe doesn't match"
8235 "(expected %i, found %i)\n",
8236 tracked_pipe, pipe);
8237
8238 }
8239
8240 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8241 base.head) {
8242 bool enabled = false;
8243 bool active = false;
8244
045ac3b5
JB		 8245 memset(&pipe_config, 0, sizeof(pipe_config));
8246
8af6cf88
DV		 8247 DRM_DEBUG_KMS("[CRTC:%d]\n",
8248 crtc->base.base.id);
8249
8250 WARN(crtc->active && !crtc->base.enabled,
8251 "active crtc, but not enabled in sw tracking\n");
8252
8253 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8254 base.head) {
8255 if (encoder->base.crtc != &crtc->base)
8256 continue;
8257 enabled = true;
8258 if (encoder->connectors_active)
8259 active = true;
8260 }
6c49f241 8261
8af6cf88
DV		 8262 WARN(active != crtc->active,
8263 "crtc's computed active state doesn't match tracked active state "
8264 "(expected %i, found %i)\n", active, crtc->active);
8265 WARN(enabled != crtc->base.enabled,
8266 "crtc's computed enabled state doesn't match tracked enabled state "
8267 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8268
0e8ffe1b
DV		 8269 active = dev_priv->display.get_pipe_config(crtc,
8270 &pipe_config);
6c49f241
DV		 8271 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8272 base.head) {
8273 if (encoder->base.crtc != &crtc->base)
8274 continue;
8275 if (encoder->get_config)
8276 encoder->get_config(encoder, &pipe_config);
8277 }
8278
0e8ffe1b
DV		 8279 WARN(crtc->active != active,
8280 "crtc active state doesn't match with hw state "
8281 "(expected %i, found %i)\n", crtc->active, active);
8282
c0b03411
DV		 8283 if (active &&
8284 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8285 WARN(1, "pipe state doesn't match!\n");
8286 intel_dump_pipe_config(crtc, &pipe_config,
8287 "[hw state]");
8288 intel_dump_pipe_config(crtc, &crtc->config,
8289 "[sw state]");
8290 }
8af6cf88
DV		 8291 }
8292}
8293
f30da187
DV		 8294static int __intel_set_mode(struct drm_crtc *crtc,
8295 struct drm_display_mode *mode,
8296 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8297{
8298 struct drm_device *dev = crtc->dev;
dbf2b54e 8299 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8300 struct drm_display_mode *saved_mode, *saved_hwmode;
8301 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8302 struct intel_crtc *intel_crtc;
8303 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8304 int ret = 0;
a6778b3c 8305
3ac18232 8306 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8307 if (!saved_mode)
8308 return -ENOMEM;
3ac18232 8309 saved_hwmode = saved_mode + 1;
a6778b3c 8310
e2e1ed41 8311 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8312 &prepare_pipes, &disable_pipes);
8313
3ac18232
TG		 8314 *saved_hwmode = crtc->hwmode;
8315 *saved_mode = crtc->mode;
a6778b3c 8316
25c5b266
DV		 8317 /* Hack: Because we don't (yet) support global modeset on multiple
8318 * crtcs, we don't keep track of the new mode for more than one crtc.
8319 * Hence simply check whether any bit is set in modeset_pipes in all the
8320 * pieces of code that are not yet converted to deal with mutliple crtcs
8321 * changing their mode at the same time. */
25c5b266 8322 if (modeset_pipes) {
4e53c2e0 8323 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8324 if (IS_ERR(pipe_config)) {
8325 ret = PTR_ERR(pipe_config);
8326 pipe_config = NULL;
8327
3ac18232 8328 goto out;
25c5b266 8329 }
c0b03411
DV		 8330 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8331 "[modeset]");
25c5b266 8332 }
a6778b3c 8333
460da916
DV		 8334 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8335 intel_crtc_disable(&intel_crtc->base);
8336
ea9d758d
DV		 8337 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8338 if (intel_crtc->base.enabled)
8339 dev_priv->display.crtc_disable(&intel_crtc->base);
8340 }
a6778b3c 8341
6c4c86f5
DV		 8342 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8343 * to set it here already despite that we pass it down the callchain.
f6e5b160 8344 */
b8cecdf5 8345 if (modeset_pipes) {
25c5b266 8346 crtc->mode = *mode;
b8cecdf5
DV		 8347 /* mode_set/enable/disable functions rely on a correct pipe
8348 * config. */
8349 to_intel_crtc(crtc)->config = *pipe_config;
8350 }
7758a113 8351
ea9d758d
DV		 8352 /* Only after disabling all output pipelines that will be changed can we
8353 * update the the output configuration. */
8354 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8355
47fab737
DV		 8356 if (dev_priv->display.modeset_global_resources)
8357 dev_priv->display.modeset_global_resources(dev);
8358
a6778b3c
DV		 8359 /* Set up the DPLL and any encoders state that needs to adjust or depend
8360 * on the DPLL.
f6e5b160 8361 */
25c5b266 8362 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8363 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8364 x, y, fb);
8365 if (ret)
8366 goto done;
a6778b3c
DV		 8367 }
8368
8369 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8370 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8371 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8372
25c5b266
DV		 8373 if (modeset_pipes) {
8374 /* Store real post-adjustment hardware mode. */
b8cecdf5 8375 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8376
25c5b266
DV		 8377 /* Calculate and store various constants which
8378 * are later needed by vblank and swap-completion
8379 * timestamping. They are derived from true hwmode.
8380 */
8381 drm_calc_timestamping_constants(crtc);
8382 }
a6778b3c
DV		 8383
8384 /* FIXME: add subpixel order */
8385done:
c0c36b94 8386 if (ret && crtc->enabled) {
3ac18232
TG		 8387 crtc->hwmode = *saved_hwmode;
8388 crtc->mode = *saved_mode;
a6778b3c
DV		 8389 }
8390
3ac18232 8391out:
b8cecdf5 8392 kfree(pipe_config);
3ac18232 8393 kfree(saved_mode);
a6778b3c 8394 return ret;
f6e5b160
CW		 8395}
8396
f30da187
DV		 8397int intel_set_mode(struct drm_crtc *crtc,
8398 struct drm_display_mode *mode,
8399 int x, int y, struct drm_framebuffer *fb)
8400{
8401 int ret;
8402
8403 ret = __intel_set_mode(crtc, mode, x, y, fb);
8404
8405 if (ret == 0)
8406 intel_modeset_check_state(crtc->dev);
8407
8408 return ret;
8409}
8410
c0c36b94
CW		 8411void intel_crtc_restore_mode(struct drm_crtc *crtc)
8412{
8413 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8414}
8415
25c5b266
DV		 8416#undef for_each_intel_crtc_masked
8417
d9e55608
DV		 8418static void intel_set_config_free(struct intel_set_config *config)
8419{
8420 if (!config)
8421 return;
8422
1aa4b628
DV		 8423 kfree(config->save_connector_encoders);
8424 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8425 kfree(config);
8426}
8427
85f9eb71
DV		 8428static int intel_set_config_save_state(struct drm_device *dev,
8429 struct intel_set_config *config)
8430{
85f9eb71
DV		 8431 struct drm_encoder *encoder;
8432 struct drm_connector *connector;
8433 int count;
8434
1aa4b628
DV		 8435 config->save_encoder_crtcs =
8436 kcalloc(dev->mode_config.num_encoder,
8437 sizeof(struct drm_crtc *), GFP_KERNEL);
8438 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8439 return -ENOMEM;
8440
1aa4b628
DV		 8441 config->save_connector_encoders =
8442 kcalloc(dev->mode_config.num_connector,
8443 sizeof(struct drm_encoder *), GFP_KERNEL);
8444 if (!config->save_connector_encoders)
85f9eb71
DV		 8445 return -ENOMEM;
8446
8447 /* Copy data. Note that driver private data is not affected.
8448 * Should anything bad happen only the expected state is
8449 * restored, not the drivers personal bookkeeping.
8450 */
85f9eb71
DV		 8451 count = 0;
8452 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8453 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8454 }
8455
8456 count = 0;
8457 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8458 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8459 }
8460
8461 return 0;
8462}
8463
8464static void intel_set_config_restore_state(struct drm_device *dev,
8465 struct intel_set_config *config)
8466{
9a935856
DV		 8467 struct intel_encoder *encoder;
8468 struct intel_connector *connector;
85f9eb71
DV		 8469 int count;
8470
85f9eb71 8471 count = 0;
9a935856
DV		 8472 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8473 encoder->new_crtc =
8474 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8475 }
8476
8477 count = 0;
9a935856
DV		 8478 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8479 connector->new_encoder =
8480 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8481 }
8482}
8483
5e2b584e
DV		 8484static void
8485intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8486 struct intel_set_config *config)
8487{
8488
8489 /* We should be able to check here if the fb has the same properties
8490 * and then just flip_or_move it */
8491 if (set->crtc->fb != set->fb) {
8492 /* If we have no fb then treat it as a full mode set */
8493 if (set->crtc->fb == NULL) {
8494 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8495 config->mode_changed = true;
8496 } else if (set->fb == NULL) {
8497 config->mode_changed = true;
72f4901e
DV		 8498 } else if (set->fb->pixel_format !=
8499 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8500 config->mode_changed = true;
8501 } else
8502 config->fb_changed = true;
8503 }
8504
835c5873 8505 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8506 config->fb_changed = true;
8507
8508 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8509 DRM_DEBUG_KMS("modes are different, full mode set\n");
8510 drm_mode_debug_printmodeline(&set->crtc->mode);
8511 drm_mode_debug_printmodeline(set->mode);
8512 config->mode_changed = true;
8513 }
8514}
8515
2e431051 8516static int
9a935856
DV		 8517intel_modeset_stage_output_state(struct drm_device *dev,
8518 struct drm_mode_set *set,
8519 struct intel_set_config *config)
50f56119 8520{
85f9eb71 8521 struct drm_crtc *new_crtc;
9a935856
DV		 8522 struct intel_connector *connector;
8523 struct intel_encoder *encoder;
2e431051 8524 int count, ro;
50f56119 8525
9abdda74 8526 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8527 * of connectors. For paranoia, double-check this. */
8528 WARN_ON(!set->fb && (set->num_connectors != 0));
8529 WARN_ON(set->fb && (set->num_connectors == 0));
8530
50f56119 8531 count = 0;
9a935856
DV		 8532 list_for_each_entry(connector, &dev->mode_config.connector_list,
8533 base.head) {
8534 /* Otherwise traverse passed in connector list and get encoders
8535 * for them. */
50f56119 8536 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8537 if (set->connectors[ro] == &connector->base) {
8538 connector->new_encoder = connector->encoder;
50f56119
DV		 8539 break;
8540 }
8541 }
8542
9a935856
DV		 8543 /* If we disable the crtc, disable all its connectors. Also, if
8544 * the connector is on the changing crtc but not on the new
8545 * connector list, disable it. */
8546 if ((!set->fb || ro == set->num_connectors) &&
8547 connector->base.encoder &&
8548 connector->base.encoder->crtc == set->crtc) {
8549 connector->new_encoder = NULL;
8550
8551 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8552 connector->base.base.id,
8553 drm_get_connector_name(&connector->base));
8554 }
8555
8556
8557 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8558 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8559 config->mode_changed = true;
50f56119
DV		 8560 }
8561 }
9a935856 8562 /* connector->new_encoder is now updated for all connectors. */
50f56119 8563
9a935856 8564 /* Update crtc of enabled connectors. */
50f56119 8565 count = 0;
9a935856
DV		 8566 list_for_each_entry(connector, &dev->mode_config.connector_list,
8567 base.head) {
8568 if (!connector->new_encoder)
50f56119
DV		 8569 continue;
8570
9a935856 8571 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8572
8573 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8574 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8575 new_crtc = set->crtc;
8576 }
8577
8578 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8579 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8580 new_crtc)) {
5e2b584e 8581 return -EINVAL;
50f56119 8582 }
9a935856
DV		 8583 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8584
8585 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8586 connector->base.base.id,
8587 drm_get_connector_name(&connector->base),
8588 new_crtc->base.id);
8589 }
8590
8591 /* Check for any encoders that needs to be disabled. */
8592 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8593 base.head) {
8594 list_for_each_entry(connector,
8595 &dev->mode_config.connector_list,
8596 base.head) {
8597 if (connector->new_encoder == encoder) {
8598 WARN_ON(!connector->new_encoder->new_crtc);
8599
8600 goto next_encoder;
8601 }
8602 }
8603 encoder->new_crtc = NULL;
8604next_encoder:
8605 /* Only now check for crtc changes so we don't miss encoders
8606 * that will be disabled. */
8607 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8608 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8609 config->mode_changed = true;
50f56119
DV		 8610 }
8611 }
9a935856 8612 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8613
2e431051
DV		 8614 return 0;
8615}
8616
8617static int intel_crtc_set_config(struct drm_mode_set *set)
8618{
8619 struct drm_device *dev;
2e431051
DV		 8620 struct drm_mode_set save_set;
8621 struct intel_set_config *config;
8622 int ret;
2e431051 8623
8d3e375e
DV		 8624 BUG_ON(!set);
8625 BUG_ON(!set->crtc);
8626 BUG_ON(!set->crtc->helper_private);
2e431051 8627
7e53f3a4
DV		 8628 /* Enforce sane interface api - has been abused by the fb helper. */
8629 BUG_ON(!set->mode && set->fb);
8630 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8631
2e431051
DV		 8632 if (set->fb) {
8633 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8634 set->crtc->base.id, set->fb->base.id,
8635 (int)set->num_connectors, set->x, set->y);
8636 } else {
8637 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8638 }
8639
8640 dev = set->crtc->dev;
8641
8642 ret = -ENOMEM;
8643 config = kzalloc(sizeof(*config), GFP_KERNEL);
8644 if (!config)
8645 goto out_config;
8646
8647 ret = intel_set_config_save_state(dev, config);
8648 if (ret)
8649 goto out_config;
8650
8651 save_set.crtc = set->crtc;
8652 save_set.mode = &set->crtc->mode;
8653 save_set.x = set->crtc->x;
8654 save_set.y = set->crtc->y;
8655 save_set.fb = set->crtc->fb;
8656
8657 /* Compute whether we need a full modeset, only an fb base update or no
8658 * change at all. In the future we might also check whether only the
8659 * mode changed, e.g. for LVDS where we only change the panel fitter in
8660 * such cases. */
8661 intel_set_config_compute_mode_changes(set, config);
8662
9a935856 8663 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8664 if (ret)
8665 goto fail;
8666
5e2b584e 8667 if (config->mode_changed) {
c0c36b94
CW		 8668 ret = intel_set_mode(set->crtc, set->mode,
8669 set->x, set->y, set->fb);
8670 if (ret) {
8671 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8672 set->crtc->base.id, ret);
87f1faa6
DV		 8673 goto fail;
8674 }
5e2b584e 8675 } else if (config->fb_changed) {
4878cae2
VS		 8676 intel_crtc_wait_for_pending_flips(set->crtc);
8677
4f660f49 8678 ret = intel_pipe_set_base(set->crtc,
94352cf9 8679 set->x, set->y, set->fb);
50f56119
DV		 8680 }
8681
d9e55608
DV		 8682 intel_set_config_free(config);
8683
50f56119
DV		 8684 return 0;
8685
8686fail:
85f9eb71 8687 intel_set_config_restore_state(dev, config);
50f56119
DV		 8688
8689 /* Try to restore the config */
5e2b584e 8690 if (config->mode_changed &&
c0c36b94
CW		 8691 intel_set_mode(save_set.crtc, save_set.mode,
8692 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8693 DRM_ERROR("failed to restore config after modeset failure\n");
8694
d9e55608
DV		 8695out_config:
8696 intel_set_config_free(config);
50f56119
DV		 8697 return ret;
8698}
f6e5b160
CW		 8699
8700static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8701 .cursor_set = intel_crtc_cursor_set,
8702 .cursor_move = intel_crtc_cursor_move,
8703 .gamma_set = intel_crtc_gamma_set,
50f56119 8704 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8705 .destroy = intel_crtc_destroy,
8706 .page_flip = intel_crtc_page_flip,
8707};
8708
79f689aa
PZ		 8709static void intel_cpu_pll_init(struct drm_device *dev)
8710{
affa9354 8711 if (HAS_DDI(dev))
79f689aa
PZ		 8712 intel_ddi_pll_init(dev);
8713}
8714
ee7b9f93
JB		 8715static void intel_pch_pll_init(struct drm_device *dev)
8716{
8717 drm_i915_private_t *dev_priv = dev->dev_private;
8718 int i;
8719
8720 if (dev_priv->num_pch_pll == 0) {
8721 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8722 return;
8723 }
8724
8725 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8726 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8727 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8728 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8729 }
8730}
8731
b358d0a6 8732static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8733{
22fd0fab 8734 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8735 struct intel_crtc *intel_crtc;
8736 int i;
8737
8738 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8739 if (intel_crtc == NULL)
8740 return;
8741
8742 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8743
8744 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8745 for (i = 0; i < 256; i++) {
8746 intel_crtc->lut_r[i] = i;
8747 intel_crtc->lut_g[i] = i;
8748 intel_crtc->lut_b[i] = i;
8749 }
8750
80824003
JB		 8751 /* Swap pipes & planes for FBC on pre-965 */
8752 intel_crtc->pipe = pipe;
8753 intel_crtc->plane = pipe;
e2e767ab 8754 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8755 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8756 intel_crtc->plane = !pipe;
80824003
JB		 8757 }
8758
22fd0fab
JB		 8759 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8760 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8761 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8762 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8763
79e53945 8764 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8765}
8766
08d7b3d1 8767int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8768 struct drm_file *file)
08d7b3d1 8769{
08d7b3d1 8770 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8771 struct drm_mode_object *drmmode_obj;
8772 struct intel_crtc *crtc;
08d7b3d1 8773
1cff8f6b
DV		 8774 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8775 return -ENODEV;
08d7b3d1 8776
c05422d5
DV		 8777 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8778 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8779
c05422d5 8780 if (!drmmode_obj) {
08d7b3d1
CW		 8781 DRM_ERROR("no such CRTC id\n");
8782 return -EINVAL;
8783 }
8784
c05422d5
DV		 8785 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8786 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8787
c05422d5 8788 return 0;
08d7b3d1
CW		 8789}
8790
66a9278e 8791static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8792{
66a9278e
DV		 8793 struct drm_device *dev = encoder->base.dev;
8794 struct intel_encoder *source_encoder;
79e53945 8795 int index_mask = 0;
79e53945
JB		 8796 int entry = 0;
8797
66a9278e
DV		 8798 list_for_each_entry(source_encoder,
8799 &dev->mode_config.encoder_list, base.head) {
8800
8801 if (encoder == source_encoder)
79e53945 8802 index_mask |= (1 << entry);
66a9278e
DV		 8803
8804 /* Intel hw has only one MUX where enocoders could be cloned. */
8805 if (encoder->cloneable && source_encoder->cloneable)
8806 index_mask |= (1 << entry);
8807
79e53945
JB		 8808 entry++;
8809 }
4ef69c7a 8810
79e53945
JB		 8811 return index_mask;
8812}
8813
4d302442
CW		 8814static bool has_edp_a(struct drm_device *dev)
8815{
8816 struct drm_i915_private *dev_priv = dev->dev_private;
8817
8818 if (!IS_MOBILE(dev))
8819 return false;
8820
8821 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8822 return false;
8823
8824 if (IS_GEN5(dev) &&
8825 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8826 return false;
8827
8828 return true;
8829}
8830
79e53945
JB		 8831static void intel_setup_outputs(struct drm_device *dev)
8832{
725e30ad 8833 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8834 struct intel_encoder *encoder;
cb0953d7 8835 bool dpd_is_edp = false;
f3cfcba6 8836 bool has_lvds;
79e53945 8837
f3cfcba6 8838 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8839 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8840 /* disable the panel fitter on everything but LVDS */
8841 I915_WRITE(PFIT_CONTROL, 0);
8842 }
79e53945 8843
c40c0f5b 8844 if (!IS_ULT(dev))
79935fca 8845 intel_crt_init(dev);
cb0953d7 8846
affa9354 8847 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8848 int found;
8849
8850 /* Haswell uses DDI functions to detect digital outputs */
8851 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8852 /* DDI A only supports eDP */
8853 if (found)
8854 intel_ddi_init(dev, PORT_A);
8855
8856 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8857 * register */
8858 found = I915_READ(SFUSE_STRAP);
8859
8860 if (found & SFUSE_STRAP_DDIB_DETECTED)
8861 intel_ddi_init(dev, PORT_B);
8862 if (found & SFUSE_STRAP_DDIC_DETECTED)
8863 intel_ddi_init(dev, PORT_C);
8864 if (found & SFUSE_STRAP_DDID_DETECTED)
8865 intel_ddi_init(dev, PORT_D);
8866 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8867 int found;
270b3042
DV		 8868 dpd_is_edp = intel_dpd_is_edp(dev);
8869
8870 if (has_edp_a(dev))
8871 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8872
dc0fa718 8873 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8874 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8875 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8876 if (!found)
e2debe91 8877 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8878 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8879 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8880 }
8881
dc0fa718 8882 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8883 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8884
dc0fa718 8885 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8886 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8887
5eb08b69 8888 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8889 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8890
270b3042 8891 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8892 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8893 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8894 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8895 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8896 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8897
dc0fa718 8898 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8899 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8900 PORT_B);
67cfc203
VS		 8901 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8902 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8903 }
103a196f 8904 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8905 bool found = false;
7d57382e 8906
e2debe91 8907 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8908 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8909 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8910 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8911 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8912 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8913 }
27185ae1 8914
e7281eab 8915 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8916 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 8917 }
13520b05
KH		 8918
8919 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8920
e2debe91 8921 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8922 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8923 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8924 }
27185ae1 8925
e2debe91 8926 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8927
b01f2c3a
JB		 8928 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8929 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8930 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 8931 }
e7281eab 8932 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8933 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 8934 }
27185ae1 8935
b01f2c3a 8936 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 8937 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 8938 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 8939 } else if (IS_GEN2(dev))
79e53945
JB		 8940 intel_dvo_init(dev);
8941
103a196f 8942 if (SUPPORTS_TV(dev))
79e53945
JB		 8943 intel_tv_init(dev);
8944
4ef69c7a
CW		 8945 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8946 encoder->base.possible_crtcs = encoder->crtc_mask;
8947 encoder->base.possible_clones =
66a9278e 8948 intel_encoder_clones(encoder);
79e53945 8949 }
47356eb6 8950
dde86e2d 8951 intel_init_pch_refclk(dev);
270b3042
DV		 8952
8953 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8954}
8955
8956static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8957{
8958 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8959
8960 drm_framebuffer_cleanup(fb);
05394f39 8961 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8962
8963 kfree(intel_fb);
8964}
8965
8966static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8967 struct drm_file *file,
79e53945
JB		 8968 unsigned int *handle)
8969{
8970 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8971 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8972
05394f39 8973 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8974}
8975
8976static const struct drm_framebuffer_funcs intel_fb_funcs = {
8977 .destroy = intel_user_framebuffer_destroy,
8978 .create_handle = intel_user_framebuffer_create_handle,
8979};
8980
38651674
DA		 8981int intel_framebuffer_init(struct drm_device *dev,
8982 struct intel_framebuffer *intel_fb,
308e5bcb 8983 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8984 struct drm_i915_gem_object *obj)
79e53945 8985{
79e53945
JB		 8986 int ret;
8987
c16ed4be
CW		 8988 if (obj->tiling_mode == I915_TILING_Y) {
8989 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8990 return -EINVAL;
c16ed4be 8991 }
57cd6508 8992
c16ed4be
CW		 8993 if (mode_cmd->pitches[0] & 63) {
8994 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8995 mode_cmd->pitches[0]);
57cd6508 8996 return -EINVAL;
c16ed4be 8997 }
57cd6508 8998
5d7bd705 8999 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 9000 if (mode_cmd->pitches[0] > 32768) {
9001 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
9002 mode_cmd->pitches[0]);
5d7bd705 9003 return -EINVAL;
c16ed4be 9004 }
5d7bd705
VS		 9005
9006 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9007 mode_cmd->pitches[0] != obj->stride) {
9008 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9009 mode_cmd->pitches[0], obj->stride);
5d7bd705 9010 return -EINVAL;
c16ed4be 9011 }
5d7bd705 9012
57779d06 9013 /* Reject formats not supported by any plane early. */
308e5bcb 9014 switch (mode_cmd->pixel_format) {
57779d06 9015 case DRM_FORMAT_C8:
04b3924d
VS		 9016 case DRM_FORMAT_RGB565:
9017 case DRM_FORMAT_XRGB8888:
9018 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9019 break;
9020 case DRM_FORMAT_XRGB1555:
9021 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 9022 if (INTEL_INFO(dev)->gen > 3) {
9023 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9024 return -EINVAL;
c16ed4be 9025 }
57779d06
VS		 9026 break;
9027 case DRM_FORMAT_XBGR8888:
9028 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9029 case DRM_FORMAT_XRGB2101010:
9030 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9031 case DRM_FORMAT_XBGR2101010:
9032 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 9033 if (INTEL_INFO(dev)->gen < 4) {
9034 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9035 return -EINVAL;
c16ed4be 9036 }
b5626747 9037 break;
04b3924d
VS		 9038 case DRM_FORMAT_YUYV:
9039 case DRM_FORMAT_UYVY:
9040 case DRM_FORMAT_YVYU:
9041 case DRM_FORMAT_VYUY:
c16ed4be
CW		 9042 if (INTEL_INFO(dev)->gen < 5) {
9043 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9044 return -EINVAL;
c16ed4be 9045 }
57cd6508
CW		 9046 break;
9047 default:
c16ed4be 9048 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 9049 return -EINVAL;
9050 }
9051
90f9a336
VS		 9052 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9053 if (mode_cmd->offsets[0] != 0)
9054 return -EINVAL;
9055
c7d73f6a
DV		 9056 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9057 intel_fb->obj = obj;
9058
79e53945
JB		 9059 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9060 if (ret) {
9061 DRM_ERROR("framebuffer init failed %d\n", ret);
9062 return ret;
9063 }
9064
79e53945
JB		 9065 return 0;
9066}
9067
79e53945
JB		 9068static struct drm_framebuffer *
9069intel_user_framebuffer_create(struct drm_device *dev,
9070 struct drm_file *filp,
308e5bcb 9071 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9072{
05394f39 9073 struct drm_i915_gem_object *obj;
79e53945 9074
308e5bcb
JB		 9075 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9076 mode_cmd->handles[0]));
c8725226 9077 if (&obj->base == NULL)
cce13ff7 9078 return ERR_PTR(-ENOENT);
79e53945 9079
d2dff872 9080 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9081}
9082
79e53945 9083static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9084 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9085 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9086};
9087
e70236a8
JB		 9088/* Set up chip specific display functions */
9089static void intel_init_display(struct drm_device *dev)
9090{
9091 struct drm_i915_private *dev_priv = dev->dev_private;
9092
ee9300bb
DV		 9093 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9094 dev_priv->display.find_dpll = g4x_find_best_dpll;
9095 else if (IS_VALLEYVIEW(dev))
9096 dev_priv->display.find_dpll = vlv_find_best_dpll;
9097 else if (IS_PINEVIEW(dev))
9098 dev_priv->display.find_dpll = pnv_find_best_dpll;
9099 else
9100 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9101
affa9354 9102 if (HAS_DDI(dev)) {
0e8ffe1b 9103 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9104 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9105 dev_priv->display.crtc_enable = haswell_crtc_enable;
9106 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9107 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9108 dev_priv->display.update_plane = ironlake_update_plane;
9109 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9110 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9111 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9112 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9113 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9114 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9115 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9116 } else if (IS_VALLEYVIEW(dev)) {
9117 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9118 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9119 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9120 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9121 dev_priv->display.off = i9xx_crtc_off;
9122 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9123 } else {
0e8ffe1b 9124 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9125 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9126 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9127 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9128 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9129 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9130 }
e70236a8 9131
e70236a8 9132 /* Returns the core display clock speed */
25eb05fc
JB		 9133 if (IS_VALLEYVIEW(dev))
9134 dev_priv->display.get_display_clock_speed =
9135 valleyview_get_display_clock_speed;
9136 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9137 dev_priv->display.get_display_clock_speed =
9138 i945_get_display_clock_speed;
9139 else if (IS_I915G(dev))
9140 dev_priv->display.get_display_clock_speed =
9141 i915_get_display_clock_speed;
f2b115e6 9142 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9143 dev_priv->display.get_display_clock_speed =
9144 i9xx_misc_get_display_clock_speed;
9145 else if (IS_I915GM(dev))
9146 dev_priv->display.get_display_clock_speed =
9147 i915gm_get_display_clock_speed;
9148 else if (IS_I865G(dev))
9149 dev_priv->display.get_display_clock_speed =
9150 i865_get_display_clock_speed;
f0f8a9ce 9151 else if (IS_I85X(dev))
e70236a8
JB		 9152 dev_priv->display.get_display_clock_speed =
9153 i855_get_display_clock_speed;
9154 else /* 852, 830 */
9155 dev_priv->display.get_display_clock_speed =
9156 i830_get_display_clock_speed;
9157
7f8a8569 9158 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9159 if (IS_GEN5(dev)) {
674cf967 9160 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9161 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9162 } else if (IS_GEN6(dev)) {
674cf967 9163 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9164 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9165 } else if (IS_IVYBRIDGE(dev)) {
9166 /* FIXME: detect B0+ stepping and use auto training */
9167 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9168 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9169 dev_priv->display.modeset_global_resources =
9170 ivb_modeset_global_resources;
c82e4d26
ED		 9171 } else if (IS_HASWELL(dev)) {
9172 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9173 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9174 dev_priv->display.modeset_global_resources =
9175 haswell_modeset_global_resources;
a0e63c22 9176 }
6067aaea 9177 } else if (IS_G4X(dev)) {
e0dac65e 9178 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9179 }
8c9f3aaf
JB		 9180
9181 /* Default just returns -ENODEV to indicate unsupported */
9182 dev_priv->display.queue_flip = intel_default_queue_flip;
9183
9184 switch (INTEL_INFO(dev)->gen) {
9185 case 2:
9186 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9187 break;
9188
9189 case 3:
9190 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9191 break;
9192
9193 case 4:
9194 case 5:
9195 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9196 break;
9197
9198 case 6:
9199 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9200 break;
7c9017e5
JB		 9201 case 7:
9202 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9203 break;
8c9f3aaf 9204 }
e70236a8
JB		 9205}
9206
b690e96c
JB		 9207/*
9208 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9209 * resume, or other times. This quirk makes sure that's the case for
9210 * affected systems.
9211 */
0206e353 9212static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9213{
9214 struct drm_i915_private *dev_priv = dev->dev_private;
9215
9216 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9217 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9218}
9219
435793df
KP		 9220/*
9221 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9222 */
9223static void quirk_ssc_force_disable(struct drm_device *dev)
9224{
9225 struct drm_i915_private *dev_priv = dev->dev_private;
9226 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9227 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9228}
9229
4dca20ef 9230/*
5a15ab5b
CE		 9231 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9232 * brightness value
4dca20ef
CE		 9233 */
9234static void quirk_invert_brightness(struct drm_device *dev)
9235{
9236 struct drm_i915_private *dev_priv = dev->dev_private;
9237 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9238 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9239}
9240
b690e96c
JB		 9241struct intel_quirk {
9242 int device;
9243 int subsystem_vendor;
9244 int subsystem_device;
9245 void (*hook)(struct drm_device *dev);
9246};
9247
5f85f176
EE		 9248/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9249struct intel_dmi_quirk {
9250 void (*hook)(struct drm_device *dev);
9251 const struct dmi_system_id (*dmi_id_list)[];
9252};
9253
9254static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9255{
9256 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9257 return 1;
9258}
9259
9260static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9261 {
9262 .dmi_id_list = &(const struct dmi_system_id[]) {
9263 {
9264 .callback = intel_dmi_reverse_brightness,
9265 .ident = "NCR Corporation",
9266 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9267 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9268 },
9269 },
9270 { } /* terminating entry */
9271 },
9272 .hook = quirk_invert_brightness,
9273 },
9274};
9275
c43b5634 9276static struct intel_quirk intel_quirks[] = {
b690e96c 9277 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9278 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9279
b690e96c
JB		 9280 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9281 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9282
b690e96c
JB		 9283 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9284 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9285
ccd0d36e 9286 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9287 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9288 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9289
9290 /* Lenovo U160 cannot use SSC on LVDS */
9291 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9292
9293 /* Sony Vaio Y cannot use SSC on LVDS */
9294 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9295
9296 /* Acer Aspire 5734Z must invert backlight brightness */
9297 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9298
9299 /* Acer/eMachines G725 */
9300 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9301
9302 /* Acer/eMachines e725 */
9303 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9304
9305 /* Acer/Packard Bell NCL20 */
9306 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9307
9308 /* Acer Aspire 4736Z */
9309 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9310};
9311
9312static void intel_init_quirks(struct drm_device *dev)
9313{
9314 struct pci_dev *d = dev->pdev;
9315 int i;
9316
9317 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9318 struct intel_quirk *q = &intel_quirks[i];
9319
9320 if (d->device == q->device &&
9321 (d->subsystem_vendor == q->subsystem_vendor ||
9322 q->subsystem_vendor == PCI_ANY_ID) &&
9323 (d->subsystem_device == q->subsystem_device ||
9324 q->subsystem_device == PCI_ANY_ID))
9325 q->hook(dev);
9326 }
5f85f176
EE		 9327 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9328 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9329 intel_dmi_quirks[i].hook(dev);
9330 }
b690e96c
JB		 9331}
9332
9cce37f4
JB		 9333/* Disable the VGA plane that we never use */
9334static void i915_disable_vga(struct drm_device *dev)
9335{
9336 struct drm_i915_private *dev_priv = dev->dev_private;
9337 u8 sr1;
766aa1c4 9338 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9339
9340 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9341 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9342 sr1 = inb(VGA_SR_DATA);
9343 outb(sr1 | 1<<5, VGA_SR_DATA);
9344 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9345 udelay(300);
9346
9347 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9348 POSTING_READ(vga_reg);
9349}
9350
f817586c
DV		 9351void intel_modeset_init_hw(struct drm_device *dev)
9352{
fa42e23c 9353 intel_init_power_well(dev);
0232e927 9354
a8f78b58
ED		 9355 intel_prepare_ddi(dev);
9356
f817586c
DV		 9357 intel_init_clock_gating(dev);
9358
79f5b2c7 9359 mutex_lock(&dev->struct_mutex);
8090c6b9 9360 intel_enable_gt_powersave(dev);
79f5b2c7 9361 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9362}
9363
7d708ee4
ID		 9364void intel_modeset_suspend_hw(struct drm_device *dev)
9365{
9366 intel_suspend_hw(dev);
9367}
9368
79e53945
JB		 9369void intel_modeset_init(struct drm_device *dev)
9370{
652c393a 9371 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9372 int i, j, ret;
79e53945
JB		 9373
9374 drm_mode_config_init(dev);
9375
9376 dev->mode_config.min_width = 0;
9377 dev->mode_config.min_height = 0;
9378
019d96cb
DA		 9379 dev->mode_config.preferred_depth = 24;
9380 dev->mode_config.prefer_shadow = 1;
9381
e6ecefaa 9382 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9383
b690e96c
JB		 9384 intel_init_quirks(dev);
9385
1fa61106
ED		 9386 intel_init_pm(dev);
9387
e3c74757
BW		 9388 if (INTEL_INFO(dev)->num_pipes == 0)
9389 return;
9390
e70236a8
JB		 9391 intel_init_display(dev);
9392
a6c45cf0
CW		 9393 if (IS_GEN2(dev)) {
9394 dev->mode_config.max_width = 2048;
9395 dev->mode_config.max_height = 2048;
9396 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9397 dev->mode_config.max_width = 4096;
9398 dev->mode_config.max_height = 4096;
79e53945 9399 } else {
a6c45cf0
CW		 9400 dev->mode_config.max_width = 8192;
9401 dev->mode_config.max_height = 8192;
79e53945 9402 }
5d4545ae 9403 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9404
28c97730 9405 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9406 INTEL_INFO(dev)->num_pipes,
9407 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9408
7eb552ae 9409 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9410 intel_crtc_init(dev, i);
7f1f3851
JB		 9411 for (j = 0; j < dev_priv->num_plane; j++) {
9412 ret = intel_plane_init(dev, i, j);
9413 if (ret)
06da8da2
VS		 9414 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9415 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9416 }
79e53945
JB		 9417 }
9418
79f689aa 9419 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9420 intel_pch_pll_init(dev);
9421
9cce37f4
JB		 9422 /* Just disable it once at startup */
9423 i915_disable_vga(dev);
79e53945 9424 intel_setup_outputs(dev);
11be49eb
CW		 9425
9426 /* Just in case the BIOS is doing something questionable. */
9427 intel_disable_fbc(dev);
2c7111db
CW		 9428}
9429
24929352
DV		 9430static void
9431intel_connector_break_all_links(struct intel_connector *connector)
9432{
9433 connector->base.dpms = DRM_MODE_DPMS_OFF;
9434 connector->base.encoder = NULL;
9435 connector->encoder->connectors_active = false;
9436 connector->encoder->base.crtc = NULL;
9437}
9438
7fad798e
DV		 9439static void intel_enable_pipe_a(struct drm_device *dev)
9440{
9441 struct intel_connector *connector;
9442 struct drm_connector *crt = NULL;
9443 struct intel_load_detect_pipe load_detect_temp;
9444
9445 /* We can't just switch on the pipe A, we need to set things up with a
9446 * proper mode and output configuration. As a gross hack, enable pipe A
9447 * by enabling the load detect pipe once. */
9448 list_for_each_entry(connector,
9449 &dev->mode_config.connector_list,
9450 base.head) {
9451 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9452 crt = &connector->base;
9453 break;
9454 }
9455 }
9456
9457 if (!crt)
9458 return;
9459
9460 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9461 intel_release_load_detect_pipe(crt, &load_detect_temp);
9462
652c393a 9463
7fad798e
DV		 9464}
9465
fa555837
DV		 9466static bool
9467intel_check_plane_mapping(struct intel_crtc *crtc)
9468{
7eb552ae
BW		 9469 struct drm_device *dev = crtc->base.dev;
9470 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9471 u32 reg, val;
9472
7eb552ae 9473 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9474 return true;
9475
9476 reg = DSPCNTR(!crtc->plane);
9477 val = I915_READ(reg);
9478
9479 if ((val & DISPLAY_PLANE_ENABLE) &&
9480 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9481 return false;
9482
9483 return true;
9484}
9485
24929352
DV		 9486static void intel_sanitize_crtc(struct intel_crtc *crtc)
9487{
9488 struct drm_device *dev = crtc->base.dev;
9489 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9490 u32 reg;
24929352 9491
24929352 9492 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9493 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9494 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9495
9496 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9497 * disable the crtc (and hence change the state) if it is wrong. Note
9498 * that gen4+ has a fixed plane -> pipe mapping. */
9499 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9500 struct intel_connector *connector;
9501 bool plane;
9502
24929352
DV		 9503 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9504 crtc->base.base.id);
9505
9506 /* Pipe has the wrong plane attached and the plane is active.
9507 * Temporarily change the plane mapping and disable everything
9508 * ... */
9509 plane = crtc->plane;
9510 crtc->plane = !plane;
9511 dev_priv->display.crtc_disable(&crtc->base);
9512 crtc->plane = plane;
9513
9514 /* ... and break all links. */
9515 list_for_each_entry(connector, &dev->mode_config.connector_list,
9516 base.head) {
9517 if (connector->encoder->base.crtc != &crtc->base)
9518 continue;
9519
9520 intel_connector_break_all_links(connector);
9521 }
9522
9523 WARN_ON(crtc->active);
9524 crtc->base.enabled = false;
9525 }
24929352 9526
7fad798e
DV		 9527 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9528 crtc->pipe == PIPE_A && !crtc->active) {
9529 /* BIOS forgot to enable pipe A, this mostly happens after
9530 * resume. Force-enable the pipe to fix this, the update_dpms
9531 * call below we restore the pipe to the right state, but leave
9532 * the required bits on. */
9533 intel_enable_pipe_a(dev);
9534 }
9535
24929352
DV		 9536 /* Adjust the state of the output pipe according to whether we
9537 * have active connectors/encoders. */
9538 intel_crtc_update_dpms(&crtc->base);
9539
9540 if (crtc->active != crtc->base.enabled) {
9541 struct intel_encoder *encoder;
9542
9543 /* This can happen either due to bugs in the get_hw_state
9544 * functions or because the pipe is force-enabled due to the
9545 * pipe A quirk. */
9546 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9547 crtc->base.base.id,
9548 crtc->base.enabled ? "enabled" : "disabled",
9549 crtc->active ? "enabled" : "disabled");
9550
9551 crtc->base.enabled = crtc->active;
9552
9553 /* Because we only establish the connector -> encoder ->
9554 * crtc links if something is active, this means the
9555 * crtc is now deactivated. Break the links. connector
9556 * -> encoder links are only establish when things are
9557 * actually up, hence no need to break them. */
9558 WARN_ON(crtc->active);
9559
9560 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9561 WARN_ON(encoder->connectors_active);
9562 encoder->base.crtc = NULL;
9563 }
9564 }
9565}
9566
9567static void intel_sanitize_encoder(struct intel_encoder *encoder)
9568{
9569 struct intel_connector *connector;
9570 struct drm_device *dev = encoder->base.dev;
9571
9572 /* We need to check both for a crtc link (meaning that the
9573 * encoder is active and trying to read from a pipe) and the
9574 * pipe itself being active. */
9575 bool has_active_crtc = encoder->base.crtc &&
9576 to_intel_crtc(encoder->base.crtc)->active;
9577
9578 if (encoder->connectors_active && !has_active_crtc) {
9579 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9580 encoder->base.base.id,
9581 drm_get_encoder_name(&encoder->base));
9582
9583 /* Connector is active, but has no active pipe. This is
9584 * fallout from our resume register restoring. Disable
9585 * the encoder manually again. */
9586 if (encoder->base.crtc) {
9587 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9588 encoder->base.base.id,
9589 drm_get_encoder_name(&encoder->base));
9590 encoder->disable(encoder);
9591 }
9592
9593 /* Inconsistent output/port/pipe state happens presumably due to
9594 * a bug in one of the get_hw_state functions. Or someplace else
9595 * in our code, like the register restore mess on resume. Clamp
9596 * things to off as a safer default. */
9597 list_for_each_entry(connector,
9598 &dev->mode_config.connector_list,
9599 base.head) {
9600 if (connector->encoder != encoder)
9601 continue;
9602
9603 intel_connector_break_all_links(connector);
9604 }
9605 }
9606 /* Enabled encoders without active connectors will be fixed in
9607 * the crtc fixup. */
9608}
9609
44cec740 9610void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9611{
9612 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9613 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9614
9615 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9616 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9617 i915_disable_vga(dev);
0fde901f
KM		 9618 }
9619}
9620
24929352
DV		 9621/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9622 * and i915 state tracking structures. */
45e2b5f6
DV		 9623void intel_modeset_setup_hw_state(struct drm_device *dev,
9624 bool force_restore)
24929352
DV		 9625{
9626 struct drm_i915_private *dev_priv = dev->dev_private;
9627 enum pipe pipe;
b5644d05 9628 struct drm_plane *plane;
24929352
DV		 9629 struct intel_crtc *crtc;
9630 struct intel_encoder *encoder;
9631 struct intel_connector *connector;
9632
0e8ffe1b
DV		 9633 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9634 base.head) {
88adfff1 9635 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9636
0e8ffe1b
DV		 9637 crtc->active = dev_priv->display.get_pipe_config(crtc,
9638 &crtc->config);
24929352
DV		 9639
9640 crtc->base.enabled = crtc->active;
9641
9642 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9643 crtc->base.base.id,
9644 crtc->active ? "enabled" : "disabled");
9645 }
9646
affa9354 9647 if (HAS_DDI(dev))
6441ab5f
PZ		 9648 intel_ddi_setup_hw_pll_state(dev);
9649
24929352
DV		 9650 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9651 base.head) {
9652 pipe = 0;
9653
9654 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9655 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9656 encoder->base.crtc = &crtc->base;
9657 if (encoder->get_config)
9658 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9659 } else {
9660 encoder->base.crtc = NULL;
9661 }
9662
9663 encoder->connectors_active = false;
9664 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9665 encoder->base.base.id,
9666 drm_get_encoder_name(&encoder->base),
9667 encoder->base.crtc ? "enabled" : "disabled",
9668 pipe);
9669 }
9670
9671 list_for_each_entry(connector, &dev->mode_config.connector_list,
9672 base.head) {
9673 if (connector->get_hw_state(connector)) {
9674 connector->base.dpms = DRM_MODE_DPMS_ON;
9675 connector->encoder->connectors_active = true;
9676 connector->base.encoder = &connector->encoder->base;
9677 } else {
9678 connector->base.dpms = DRM_MODE_DPMS_OFF;
9679 connector->base.encoder = NULL;
9680 }
9681 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9682 connector->base.base.id,
9683 drm_get_connector_name(&connector->base),
9684 connector->base.encoder ? "enabled" : "disabled");
9685 }
9686
9687 /* HW state is read out, now we need to sanitize this mess. */
9688 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9689 base.head) {
9690 intel_sanitize_encoder(encoder);
9691 }
9692
9693 for_each_pipe(pipe) {
9694 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9695 intel_sanitize_crtc(crtc);
c0b03411 9696 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 9697 }
9a935856 9698
45e2b5f6 9699 if (force_restore) {
f30da187
DV		 9700 /*
9701 * We need to use raw interfaces for restoring state to avoid
9702 * checking (bogus) intermediate states.
9703 */
45e2b5f6 9704 for_each_pipe(pipe) {
b5644d05
JB		 9705 struct drm_crtc *crtc =
9706 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9707
9708 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9709 crtc->fb);
45e2b5f6 9710 }
b5644d05
JB		 9711 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9712 intel_plane_restore(plane);
0fde901f
KM		 9713
9714 i915_redisable_vga(dev);
45e2b5f6
DV		 9715 } else {
9716 intel_modeset_update_staged_output_state(dev);
9717 }
8af6cf88
DV		 9718
9719 intel_modeset_check_state(dev);
2e938892
DV		 9720
9721 drm_mode_config_reset(dev);
2c7111db
CW		 9722}
9723
9724void intel_modeset_gem_init(struct drm_device *dev)
9725{
1833b134 9726 intel_modeset_init_hw(dev);
02e792fb
DV		 9727
9728 intel_setup_overlay(dev);
24929352 9729
45e2b5f6 9730 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9731}
9732
9733void intel_modeset_cleanup(struct drm_device *dev)
9734{
652c393a
JB		 9735 struct drm_i915_private *dev_priv = dev->dev_private;
9736 struct drm_crtc *crtc;
9737 struct intel_crtc *intel_crtc;
9738
fd0c0642
DV		 9739 /*
9740 * Interrupts and polling as the first thing to avoid creating havoc.
9741 * Too much stuff here (turning of rps, connectors, ...) would
9742 * experience fancy races otherwise.
9743 */
9744 drm_irq_uninstall(dev);
9745 cancel_work_sync(&dev_priv->hotplug_work);
9746 /*
9747 * Due to the hpd irq storm handling the hotplug work can re-arm the
9748 * poll handlers. Hence disable polling after hpd handling is shut down.
9749 */
f87ea761 9750 drm_kms_helper_poll_fini(dev);
fd0c0642 9751
652c393a
JB		 9752 mutex_lock(&dev->struct_mutex);
9753
723bfd70
JB		 9754 intel_unregister_dsm_handler();
9755
652c393a
JB		 9756 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9757 /* Skip inactive CRTCs */
9758 if (!crtc->fb)
9759 continue;
9760
9761 intel_crtc = to_intel_crtc(crtc);
3dec0095 9762 intel_increase_pllclock(crtc);
652c393a
JB		 9763 }
9764
973d04f9 9765 intel_disable_fbc(dev);
e70236a8 9766
8090c6b9 9767 intel_disable_gt_powersave(dev);
0cdab21f 9768
930ebb46
DV		 9769 ironlake_teardown_rc6(dev);
9770
69341a5e
KH		 9771 mutex_unlock(&dev->struct_mutex);
9772
1630fe75
CW		 9773 /* flush any delayed tasks or pending work */
9774 flush_scheduled_work();
9775
dc652f90
JN		 9776 /* destroy backlight, if any, before the connectors */
9777 intel_panel_destroy_backlight(dev);
9778
79e53945 9779 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9780
9781 intel_cleanup_overlay(dev);
79e53945
JB		 9782}
9783
f1c79df3
ZW		 9784/*
9785 * Return which encoder is currently attached for connector.
9786 */
df0e9248 9787struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9788{
df0e9248
CW		 9789 return &intel_attached_encoder(connector)->base;
9790}
f1c79df3 9791
df0e9248
CW		 9792void intel_connector_attach_encoder(struct intel_connector *connector,
9793 struct intel_encoder *encoder)
9794{
9795 connector->encoder = encoder;
9796 drm_mode_connector_attach_encoder(&connector->base,
9797 &encoder->base);
79e53945 9798}
28d52043
DA		 9799
9800/*
9801 * set vga decode state - true == enable VGA decode
9802 */
9803int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9804{
9805 struct drm_i915_private *dev_priv = dev->dev_private;
9806 u16 gmch_ctrl;
9807
9808 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9809 if (state)
9810 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9811 else
9812 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9813 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9814 return 0;
9815}
c4a1d9e4
CW		 9816
9817#ifdef CONFIG_DEBUG_FS
9818#include <linux/seq_file.h>
9819
9820struct intel_display_error_state {
ff57f1b0
PZ		 9821
9822 u32 power_well_driver;
9823
c4a1d9e4
CW		 9824 struct intel_cursor_error_state {
9825 u32 control;
9826 u32 position;
9827 u32 base;
9828 u32 size;
52331309 9829 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9830
9831 struct intel_pipe_error_state {
ff57f1b0 9832 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9833 u32 conf;
9834 u32 source;
9835
9836 u32 htotal;
9837 u32 hblank;
9838 u32 hsync;
9839 u32 vtotal;
9840 u32 vblank;
9841 u32 vsync;
52331309 9842 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9843
9844 struct intel_plane_error_state {
9845 u32 control;
9846 u32 stride;
9847 u32 size;
9848 u32 pos;
9849 u32 addr;
9850 u32 surface;
9851 u32 tile_offset;
52331309 9852 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9853};
9854
9855struct intel_display_error_state *
9856intel_display_capture_error_state(struct drm_device *dev)
9857{
0206e353 9858 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9859 struct intel_display_error_state *error;
702e7a56 9860 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9861 int i;
9862
9863 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9864 if (error == NULL)
9865 return NULL;
9866
ff57f1b0
PZ		 9867 if (HAS_POWER_WELL(dev))
9868 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9869
52331309 9870 for_each_pipe(i) {
702e7a56 9871 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 9872 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 9873
a18c4c3d
PZ		 9874 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9875 error->cursor[i].control = I915_READ(CURCNTR(i));
9876 error->cursor[i].position = I915_READ(CURPOS(i));
9877 error->cursor[i].base = I915_READ(CURBASE(i));
9878 } else {
9879 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9880 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9881 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9882 }
c4a1d9e4
CW		 9883
9884 error->plane[i].control = I915_READ(DSPCNTR(i));
9885 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9886 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9887 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9888 error->plane[i].pos = I915_READ(DSPPOS(i));
9889 }
ca291363
PZ		 9890 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9891 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9892 if (INTEL_INFO(dev)->gen >= 4) {
9893 error->plane[i].surface = I915_READ(DSPSURF(i));
9894 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9895 }
9896
702e7a56 9897 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9898 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9899 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9900 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9901 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9902 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9903 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9904 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9905 }
9906
12d217c7
PZ		 9907 /* In the code above we read the registers without checking if the power
9908 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9909 * prevent the next I915_WRITE from detecting it and printing an error
9910 * message. */
9911 if (HAS_POWER_WELL(dev))
9912 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9913
c4a1d9e4
CW		 9914 return error;
9915}
9916
edc3d884
MK		 9917#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9918
c4a1d9e4 9919void
edc3d884 9920intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 9921 struct drm_device *dev,
9922 struct intel_display_error_state *error)
9923{
9924 int i;
9925
edc3d884 9926 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 9927 if (HAS_POWER_WELL(dev))
edc3d884 9928 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 9929 error->power_well_driver);
52331309 9930 for_each_pipe(i) {
edc3d884
MK		 9931 err_printf(m, "Pipe [%d]:\n", i);
9932 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 9933 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 9934 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9935 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
9936 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9937 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9938 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9939 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9940 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9941 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9942
9943 err_printf(m, "Plane [%d]:\n", i);
9944 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
9945 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9946 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 9947 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
9948 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 9949 }
4b71a570 9950 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 9951 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 9952 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 9953 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
9954 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 9955 }
9956
edc3d884
MK		 9957 err_printf(m, "Cursor [%d]:\n", i);
9958 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9959 err_printf(m, " POS: %08x\n", error->cursor[i].position);
9960 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 9961 }
9962}
9963#endif
Ubuntu Jammy Linux kernel mirror