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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
0206e353 | 44 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
3dec0095 | 45 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 46 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 47 | |
f1f644dc JB |
48 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
49 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
50 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
51 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 52 | |
e7457a9a DL |
53 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
54 | int x, int y, struct drm_framebuffer *old_fb); | |
55 | ||
56 | ||
79e53945 | 57 | typedef struct { |
0206e353 | 58 | int min, max; |
79e53945 JB |
59 | } intel_range_t; |
60 | ||
61 | typedef struct { | |
0206e353 AJ |
62 | int dot_limit; |
63 | int p2_slow, p2_fast; | |
79e53945 JB |
64 | } intel_p2_t; |
65 | ||
d4906093 ML |
66 | typedef struct intel_limit intel_limit_t; |
67 | struct intel_limit { | |
0206e353 AJ |
68 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
69 | intel_p2_t p2; | |
d4906093 | 70 | }; |
79e53945 | 71 | |
d2acd215 DV |
72 | int |
73 | intel_pch_rawclk(struct drm_device *dev) | |
74 | { | |
75 | struct drm_i915_private *dev_priv = dev->dev_private; | |
76 | ||
77 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
78 | ||
79 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
80 | } | |
81 | ||
021357ac CW |
82 | static inline u32 /* units of 100MHz */ |
83 | intel_fdi_link_freq(struct drm_device *dev) | |
84 | { | |
8b99e68c CW |
85 | if (IS_GEN5(dev)) { |
86 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
88 | } else | |
89 | return 27; | |
021357ac CW |
90 | } |
91 | ||
5d536e28 | 92 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 AJ |
93 | .dot = { .min = 25000, .max = 350000 }, |
94 | .vco = { .min = 930000, .max = 1400000 }, | |
95 | .n = { .min = 3, .max = 16 }, | |
96 | .m = { .min = 96, .max = 140 }, | |
97 | .m1 = { .min = 18, .max = 26 }, | |
98 | .m2 = { .min = 6, .max = 16 }, | |
99 | .p = { .min = 4, .max = 128 }, | |
100 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
101 | .p2 = { .dot_limit = 165000, |
102 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
103 | }; |
104 | ||
5d536e28 DV |
105 | static const intel_limit_t intel_limits_i8xx_dvo = { |
106 | .dot = { .min = 25000, .max = 350000 }, | |
107 | .vco = { .min = 930000, .max = 1400000 }, | |
108 | .n = { .min = 3, .max = 16 }, | |
109 | .m = { .min = 96, .max = 140 }, | |
110 | .m1 = { .min = 18, .max = 26 }, | |
111 | .m2 = { .min = 6, .max = 16 }, | |
112 | .p = { .min = 4, .max = 128 }, | |
113 | .p1 = { .min = 2, .max = 33 }, | |
114 | .p2 = { .dot_limit = 165000, | |
115 | .p2_slow = 4, .p2_fast = 4 }, | |
116 | }; | |
117 | ||
e4b36699 | 118 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 AJ |
119 | .dot = { .min = 25000, .max = 350000 }, |
120 | .vco = { .min = 930000, .max = 1400000 }, | |
121 | .n = { .min = 3, .max = 16 }, | |
122 | .m = { .min = 96, .max = 140 }, | |
123 | .m1 = { .min = 18, .max = 26 }, | |
124 | .m2 = { .min = 6, .max = 16 }, | |
125 | .p = { .min = 4, .max = 128 }, | |
126 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
127 | .p2 = { .dot_limit = 165000, |
128 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 129 | }; |
273e27ca | 130 | |
e4b36699 | 131 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
132 | .dot = { .min = 20000, .max = 400000 }, |
133 | .vco = { .min = 1400000, .max = 2800000 }, | |
134 | .n = { .min = 1, .max = 6 }, | |
135 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
136 | .m1 = { .min = 8, .max = 18 }, |
137 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
138 | .p = { .min = 5, .max = 80 }, |
139 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
140 | .p2 = { .dot_limit = 200000, |
141 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
142 | }; |
143 | ||
144 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
145 | .dot = { .min = 20000, .max = 400000 }, |
146 | .vco = { .min = 1400000, .max = 2800000 }, | |
147 | .n = { .min = 1, .max = 6 }, | |
148 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
149 | .m1 = { .min = 8, .max = 18 }, |
150 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
151 | .p = { .min = 7, .max = 98 }, |
152 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
153 | .p2 = { .dot_limit = 112000, |
154 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
155 | }; |
156 | ||
273e27ca | 157 | |
e4b36699 | 158 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
159 | .dot = { .min = 25000, .max = 270000 }, |
160 | .vco = { .min = 1750000, .max = 3500000}, | |
161 | .n = { .min = 1, .max = 4 }, | |
162 | .m = { .min = 104, .max = 138 }, | |
163 | .m1 = { .min = 17, .max = 23 }, | |
164 | .m2 = { .min = 5, .max = 11 }, | |
165 | .p = { .min = 10, .max = 30 }, | |
166 | .p1 = { .min = 1, .max = 3}, | |
167 | .p2 = { .dot_limit = 270000, | |
168 | .p2_slow = 10, | |
169 | .p2_fast = 10 | |
044c7c41 | 170 | }, |
e4b36699 KP |
171 | }; |
172 | ||
173 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
174 | .dot = { .min = 22000, .max = 400000 }, |
175 | .vco = { .min = 1750000, .max = 3500000}, | |
176 | .n = { .min = 1, .max = 4 }, | |
177 | .m = { .min = 104, .max = 138 }, | |
178 | .m1 = { .min = 16, .max = 23 }, | |
179 | .m2 = { .min = 5, .max = 11 }, | |
180 | .p = { .min = 5, .max = 80 }, | |
181 | .p1 = { .min = 1, .max = 8}, | |
182 | .p2 = { .dot_limit = 165000, | |
183 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
184 | }; |
185 | ||
186 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
187 | .dot = { .min = 20000, .max = 115000 }, |
188 | .vco = { .min = 1750000, .max = 3500000 }, | |
189 | .n = { .min = 1, .max = 3 }, | |
190 | .m = { .min = 104, .max = 138 }, | |
191 | .m1 = { .min = 17, .max = 23 }, | |
192 | .m2 = { .min = 5, .max = 11 }, | |
193 | .p = { .min = 28, .max = 112 }, | |
194 | .p1 = { .min = 2, .max = 8 }, | |
195 | .p2 = { .dot_limit = 0, | |
196 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 197 | }, |
e4b36699 KP |
198 | }; |
199 | ||
200 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
201 | .dot = { .min = 80000, .max = 224000 }, |
202 | .vco = { .min = 1750000, .max = 3500000 }, | |
203 | .n = { .min = 1, .max = 3 }, | |
204 | .m = { .min = 104, .max = 138 }, | |
205 | .m1 = { .min = 17, .max = 23 }, | |
206 | .m2 = { .min = 5, .max = 11 }, | |
207 | .p = { .min = 14, .max = 42 }, | |
208 | .p1 = { .min = 2, .max = 6 }, | |
209 | .p2 = { .dot_limit = 0, | |
210 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 211 | }, |
e4b36699 KP |
212 | }; |
213 | ||
f2b115e6 | 214 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
215 | .dot = { .min = 20000, .max = 400000}, |
216 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 217 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
218 | .n = { .min = 3, .max = 6 }, |
219 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 220 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
221 | .m1 = { .min = 0, .max = 0 }, |
222 | .m2 = { .min = 0, .max = 254 }, | |
223 | .p = { .min = 5, .max = 80 }, | |
224 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
225 | .p2 = { .dot_limit = 200000, |
226 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
227 | }; |
228 | ||
f2b115e6 | 229 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
230 | .dot = { .min = 20000, .max = 400000 }, |
231 | .vco = { .min = 1700000, .max = 3500000 }, | |
232 | .n = { .min = 3, .max = 6 }, | |
233 | .m = { .min = 2, .max = 256 }, | |
234 | .m1 = { .min = 0, .max = 0 }, | |
235 | .m2 = { .min = 0, .max = 254 }, | |
236 | .p = { .min = 7, .max = 112 }, | |
237 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
238 | .p2 = { .dot_limit = 112000, |
239 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
240 | }; |
241 | ||
273e27ca EA |
242 | /* Ironlake / Sandybridge |
243 | * | |
244 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
245 | * the range value for them is (actual_value - 2). | |
246 | */ | |
b91ad0ec | 247 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
248 | .dot = { .min = 25000, .max = 350000 }, |
249 | .vco = { .min = 1760000, .max = 3510000 }, | |
250 | .n = { .min = 1, .max = 5 }, | |
251 | .m = { .min = 79, .max = 127 }, | |
252 | .m1 = { .min = 12, .max = 22 }, | |
253 | .m2 = { .min = 5, .max = 9 }, | |
254 | .p = { .min = 5, .max = 80 }, | |
255 | .p1 = { .min = 1, .max = 8 }, | |
256 | .p2 = { .dot_limit = 225000, | |
257 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
258 | }; |
259 | ||
b91ad0ec | 260 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
261 | .dot = { .min = 25000, .max = 350000 }, |
262 | .vco = { .min = 1760000, .max = 3510000 }, | |
263 | .n = { .min = 1, .max = 3 }, | |
264 | .m = { .min = 79, .max = 118 }, | |
265 | .m1 = { .min = 12, .max = 22 }, | |
266 | .m2 = { .min = 5, .max = 9 }, | |
267 | .p = { .min = 28, .max = 112 }, | |
268 | .p1 = { .min = 2, .max = 8 }, | |
269 | .p2 = { .dot_limit = 225000, | |
270 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
271 | }; |
272 | ||
273 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
274 | .dot = { .min = 25000, .max = 350000 }, |
275 | .vco = { .min = 1760000, .max = 3510000 }, | |
276 | .n = { .min = 1, .max = 3 }, | |
277 | .m = { .min = 79, .max = 127 }, | |
278 | .m1 = { .min = 12, .max = 22 }, | |
279 | .m2 = { .min = 5, .max = 9 }, | |
280 | .p = { .min = 14, .max = 56 }, | |
281 | .p1 = { .min = 2, .max = 8 }, | |
282 | .p2 = { .dot_limit = 225000, | |
283 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
284 | }; |
285 | ||
273e27ca | 286 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 287 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
288 | .dot = { .min = 25000, .max = 350000 }, |
289 | .vco = { .min = 1760000, .max = 3510000 }, | |
290 | .n = { .min = 1, .max = 2 }, | |
291 | .m = { .min = 79, .max = 126 }, | |
292 | .m1 = { .min = 12, .max = 22 }, | |
293 | .m2 = { .min = 5, .max = 9 }, | |
294 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 295 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
296 | .p2 = { .dot_limit = 225000, |
297 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
298 | }; |
299 | ||
300 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
301 | .dot = { .min = 25000, .max = 350000 }, |
302 | .vco = { .min = 1760000, .max = 3510000 }, | |
303 | .n = { .min = 1, .max = 3 }, | |
304 | .m = { .min = 79, .max = 126 }, | |
305 | .m1 = { .min = 12, .max = 22 }, | |
306 | .m2 = { .min = 5, .max = 9 }, | |
307 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 308 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
309 | .p2 = { .dot_limit = 225000, |
310 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
311 | }; |
312 | ||
a0c4da24 JB |
313 | static const intel_limit_t intel_limits_vlv_dac = { |
314 | .dot = { .min = 25000, .max = 270000 }, | |
315 | .vco = { .min = 4000000, .max = 6000000 }, | |
316 | .n = { .min = 1, .max = 7 }, | |
317 | .m = { .min = 22, .max = 450 }, /* guess */ | |
318 | .m1 = { .min = 2, .max = 3 }, | |
319 | .m2 = { .min = 11, .max = 156 }, | |
320 | .p = { .min = 10, .max = 30 }, | |
75e53986 | 321 | .p1 = { .min = 1, .max = 3 }, |
a0c4da24 JB |
322 | .p2 = { .dot_limit = 270000, |
323 | .p2_slow = 2, .p2_fast = 20 }, | |
a0c4da24 JB |
324 | }; |
325 | ||
326 | static const intel_limit_t intel_limits_vlv_hdmi = { | |
75e53986 DV |
327 | .dot = { .min = 25000, .max = 270000 }, |
328 | .vco = { .min = 4000000, .max = 6000000 }, | |
a0c4da24 JB |
329 | .n = { .min = 1, .max = 7 }, |
330 | .m = { .min = 60, .max = 300 }, /* guess */ | |
331 | .m1 = { .min = 2, .max = 3 }, | |
332 | .m2 = { .min = 11, .max = 156 }, | |
333 | .p = { .min = 10, .max = 30 }, | |
334 | .p1 = { .min = 2, .max = 3 }, | |
335 | .p2 = { .dot_limit = 270000, | |
336 | .p2_slow = 2, .p2_fast = 20 }, | |
a0c4da24 JB |
337 | }; |
338 | ||
1b894b59 CW |
339 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
340 | int refclk) | |
2c07245f | 341 | { |
b91ad0ec | 342 | struct drm_device *dev = crtc->dev; |
2c07245f | 343 | const intel_limit_t *limit; |
b91ad0ec ZW |
344 | |
345 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 346 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 347 | if (refclk == 100000) |
b91ad0ec ZW |
348 | limit = &intel_limits_ironlake_dual_lvds_100m; |
349 | else | |
350 | limit = &intel_limits_ironlake_dual_lvds; | |
351 | } else { | |
1b894b59 | 352 | if (refclk == 100000) |
b91ad0ec ZW |
353 | limit = &intel_limits_ironlake_single_lvds_100m; |
354 | else | |
355 | limit = &intel_limits_ironlake_single_lvds; | |
356 | } | |
c6bb3538 | 357 | } else |
b91ad0ec | 358 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
359 | |
360 | return limit; | |
361 | } | |
362 | ||
044c7c41 ML |
363 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
364 | { | |
365 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
366 | const intel_limit_t *limit; |
367 | ||
368 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 369 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 370 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 371 | else |
e4b36699 | 372 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
373 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
374 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 375 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 376 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 377 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 378 | } else /* The option is for other outputs */ |
e4b36699 | 379 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
380 | |
381 | return limit; | |
382 | } | |
383 | ||
1b894b59 | 384 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
385 | { |
386 | struct drm_device *dev = crtc->dev; | |
387 | const intel_limit_t *limit; | |
388 | ||
bad720ff | 389 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 390 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 391 | else if (IS_G4X(dev)) { |
044c7c41 | 392 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 393 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 394 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 395 | limit = &intel_limits_pineview_lvds; |
2177832f | 396 | else |
f2b115e6 | 397 | limit = &intel_limits_pineview_sdvo; |
a0c4da24 JB |
398 | } else if (IS_VALLEYVIEW(dev)) { |
399 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) | |
400 | limit = &intel_limits_vlv_dac; | |
a0c4da24 | 401 | else |
65ce4bf5 | 402 | limit = &intel_limits_vlv_hdmi; |
a6c45cf0 CW |
403 | } else if (!IS_GEN2(dev)) { |
404 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
405 | limit = &intel_limits_i9xx_lvds; | |
406 | else | |
407 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
408 | } else { |
409 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 410 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 411 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 412 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
413 | else |
414 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
415 | } |
416 | return limit; | |
417 | } | |
418 | ||
f2b115e6 AJ |
419 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
420 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 421 | { |
2177832f SL |
422 | clock->m = clock->m2 + 2; |
423 | clock->p = clock->p1 * clock->p2; | |
424 | clock->vco = refclk * clock->m / clock->n; | |
425 | clock->dot = clock->vco / clock->p; | |
426 | } | |
427 | ||
7429e9d4 DV |
428 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
429 | { | |
430 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
431 | } | |
432 | ||
ac58c3f0 | 433 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 434 | { |
7429e9d4 | 435 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 JB |
436 | clock->p = clock->p1 * clock->p2; |
437 | clock->vco = refclk * clock->m / (clock->n + 2); | |
438 | clock->dot = clock->vco / clock->p; | |
439 | } | |
440 | ||
79e53945 JB |
441 | /** |
442 | * Returns whether any output on the specified pipe is of the specified type | |
443 | */ | |
4ef69c7a | 444 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 445 | { |
4ef69c7a | 446 | struct drm_device *dev = crtc->dev; |
4ef69c7a CW |
447 | struct intel_encoder *encoder; |
448 | ||
6c2b7c12 DV |
449 | for_each_encoder_on_crtc(dev, crtc, encoder) |
450 | if (encoder->type == type) | |
4ef69c7a CW |
451 | return true; |
452 | ||
453 | return false; | |
79e53945 JB |
454 | } |
455 | ||
7c04d1d9 | 456 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
457 | /** |
458 | * Returns whether the given set of divisors are valid for a given refclk with | |
459 | * the given connectors. | |
460 | */ | |
461 | ||
1b894b59 CW |
462 | static bool intel_PLL_is_valid(struct drm_device *dev, |
463 | const intel_limit_t *limit, | |
464 | const intel_clock_t *clock) | |
79e53945 | 465 | { |
79e53945 | 466 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 467 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 468 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
0206e353 | 469 | INTELPllInvalid("p out of range\n"); |
79e53945 | 470 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 471 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 472 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 473 | INTELPllInvalid("m1 out of range\n"); |
f2b115e6 | 474 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
0206e353 | 475 | INTELPllInvalid("m1 <= m2\n"); |
79e53945 | 476 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
0206e353 | 477 | INTELPllInvalid("m out of range\n"); |
79e53945 | 478 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
0206e353 | 479 | INTELPllInvalid("n out of range\n"); |
79e53945 | 480 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 481 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
482 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
483 | * connector, etc., rather than just a single range. | |
484 | */ | |
485 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 486 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
487 | |
488 | return true; | |
489 | } | |
490 | ||
d4906093 | 491 | static bool |
ee9300bb | 492 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
493 | int target, int refclk, intel_clock_t *match_clock, |
494 | intel_clock_t *best_clock) | |
79e53945 JB |
495 | { |
496 | struct drm_device *dev = crtc->dev; | |
79e53945 | 497 | intel_clock_t clock; |
79e53945 JB |
498 | int err = target; |
499 | ||
a210b028 | 500 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 501 | /* |
a210b028 DV |
502 | * For LVDS just rely on its current settings for dual-channel. |
503 | * We haven't figured out how to reliably set up different | |
504 | * single/dual channel state, if we even can. | |
79e53945 | 505 | */ |
1974cad0 | 506 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
507 | clock.p2 = limit->p2.p2_fast; |
508 | else | |
509 | clock.p2 = limit->p2.p2_slow; | |
510 | } else { | |
511 | if (target < limit->p2.dot_limit) | |
512 | clock.p2 = limit->p2.p2_slow; | |
513 | else | |
514 | clock.p2 = limit->p2.p2_fast; | |
515 | } | |
516 | ||
0206e353 | 517 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 518 | |
42158660 ZY |
519 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
520 | clock.m1++) { | |
521 | for (clock.m2 = limit->m2.min; | |
522 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 523 | if (clock.m2 >= clock.m1) |
42158660 ZY |
524 | break; |
525 | for (clock.n = limit->n.min; | |
526 | clock.n <= limit->n.max; clock.n++) { | |
527 | for (clock.p1 = limit->p1.min; | |
528 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
529 | int this_err; |
530 | ||
ac58c3f0 DV |
531 | i9xx_clock(refclk, &clock); |
532 | if (!intel_PLL_is_valid(dev, limit, | |
533 | &clock)) | |
534 | continue; | |
535 | if (match_clock && | |
536 | clock.p != match_clock->p) | |
537 | continue; | |
538 | ||
539 | this_err = abs(clock.dot - target); | |
540 | if (this_err < err) { | |
541 | *best_clock = clock; | |
542 | err = this_err; | |
543 | } | |
544 | } | |
545 | } | |
546 | } | |
547 | } | |
548 | ||
549 | return (err != target); | |
550 | } | |
551 | ||
552 | static bool | |
ee9300bb DV |
553 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
554 | int target, int refclk, intel_clock_t *match_clock, | |
555 | intel_clock_t *best_clock) | |
79e53945 JB |
556 | { |
557 | struct drm_device *dev = crtc->dev; | |
79e53945 | 558 | intel_clock_t clock; |
79e53945 JB |
559 | int err = target; |
560 | ||
a210b028 | 561 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 562 | /* |
a210b028 DV |
563 | * For LVDS just rely on its current settings for dual-channel. |
564 | * We haven't figured out how to reliably set up different | |
565 | * single/dual channel state, if we even can. | |
79e53945 | 566 | */ |
1974cad0 | 567 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
568 | clock.p2 = limit->p2.p2_fast; |
569 | else | |
570 | clock.p2 = limit->p2.p2_slow; | |
571 | } else { | |
572 | if (target < limit->p2.dot_limit) | |
573 | clock.p2 = limit->p2.p2_slow; | |
574 | else | |
575 | clock.p2 = limit->p2.p2_fast; | |
576 | } | |
577 | ||
0206e353 | 578 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 579 | |
42158660 ZY |
580 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
581 | clock.m1++) { | |
582 | for (clock.m2 = limit->m2.min; | |
583 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
584 | for (clock.n = limit->n.min; |
585 | clock.n <= limit->n.max; clock.n++) { | |
586 | for (clock.p1 = limit->p1.min; | |
587 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
588 | int this_err; |
589 | ||
ac58c3f0 | 590 | pineview_clock(refclk, &clock); |
1b894b59 CW |
591 | if (!intel_PLL_is_valid(dev, limit, |
592 | &clock)) | |
79e53945 | 593 | continue; |
cec2f356 SP |
594 | if (match_clock && |
595 | clock.p != match_clock->p) | |
596 | continue; | |
79e53945 JB |
597 | |
598 | this_err = abs(clock.dot - target); | |
599 | if (this_err < err) { | |
600 | *best_clock = clock; | |
601 | err = this_err; | |
602 | } | |
603 | } | |
604 | } | |
605 | } | |
606 | } | |
607 | ||
608 | return (err != target); | |
609 | } | |
610 | ||
d4906093 | 611 | static bool |
ee9300bb DV |
612 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
613 | int target, int refclk, intel_clock_t *match_clock, | |
614 | intel_clock_t *best_clock) | |
d4906093 ML |
615 | { |
616 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
617 | intel_clock_t clock; |
618 | int max_n; | |
619 | bool found; | |
6ba770dc AJ |
620 | /* approximately equals target * 0.00585 */ |
621 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
622 | found = false; |
623 | ||
624 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 625 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
626 | clock.p2 = limit->p2.p2_fast; |
627 | else | |
628 | clock.p2 = limit->p2.p2_slow; | |
629 | } else { | |
630 | if (target < limit->p2.dot_limit) | |
631 | clock.p2 = limit->p2.p2_slow; | |
632 | else | |
633 | clock.p2 = limit->p2.p2_fast; | |
634 | } | |
635 | ||
636 | memset(best_clock, 0, sizeof(*best_clock)); | |
637 | max_n = limit->n.max; | |
f77f13e2 | 638 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 639 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 640 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
641 | for (clock.m1 = limit->m1.max; |
642 | clock.m1 >= limit->m1.min; clock.m1--) { | |
643 | for (clock.m2 = limit->m2.max; | |
644 | clock.m2 >= limit->m2.min; clock.m2--) { | |
645 | for (clock.p1 = limit->p1.max; | |
646 | clock.p1 >= limit->p1.min; clock.p1--) { | |
647 | int this_err; | |
648 | ||
ac58c3f0 | 649 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
650 | if (!intel_PLL_is_valid(dev, limit, |
651 | &clock)) | |
d4906093 | 652 | continue; |
1b894b59 CW |
653 | |
654 | this_err = abs(clock.dot - target); | |
d4906093 ML |
655 | if (this_err < err_most) { |
656 | *best_clock = clock; | |
657 | err_most = this_err; | |
658 | max_n = clock.n; | |
659 | found = true; | |
660 | } | |
661 | } | |
662 | } | |
663 | } | |
664 | } | |
2c07245f ZW |
665 | return found; |
666 | } | |
667 | ||
a0c4da24 | 668 | static bool |
ee9300bb DV |
669 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
670 | int target, int refclk, intel_clock_t *match_clock, | |
671 | intel_clock_t *best_clock) | |
a0c4da24 JB |
672 | { |
673 | u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; | |
674 | u32 m, n, fastclk; | |
f3f08572 | 675 | u32 updrate, minupdate, p; |
a0c4da24 JB |
676 | unsigned long bestppm, ppm, absppm; |
677 | int dotclk, flag; | |
678 | ||
af447bd3 | 679 | flag = 0; |
a0c4da24 JB |
680 | dotclk = target * 1000; |
681 | bestppm = 1000000; | |
682 | ppm = absppm = 0; | |
683 | fastclk = dotclk / (2*100); | |
684 | updrate = 0; | |
685 | minupdate = 19200; | |
a0c4da24 JB |
686 | n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; |
687 | bestm1 = bestm2 = bestp1 = bestp2 = 0; | |
688 | ||
689 | /* based on hardware requirement, prefer smaller n to precision */ | |
690 | for (n = limit->n.min; n <= ((refclk) / minupdate); n++) { | |
691 | updrate = refclk / n; | |
692 | for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) { | |
693 | for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) { | |
694 | if (p2 > 10) | |
695 | p2 = p2 - 1; | |
696 | p = p1 * p2; | |
697 | /* based on hardware requirement, prefer bigger m1,m2 values */ | |
698 | for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) { | |
699 | m2 = (((2*(fastclk * p * n / m1 )) + | |
700 | refclk) / (2*refclk)); | |
701 | m = m1 * m2; | |
702 | vco = updrate * m; | |
703 | if (vco >= limit->vco.min && vco < limit->vco.max) { | |
704 | ppm = 1000000 * ((vco / p) - fastclk) / fastclk; | |
705 | absppm = (ppm > 0) ? ppm : (-ppm); | |
706 | if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) { | |
707 | bestppm = 0; | |
708 | flag = 1; | |
709 | } | |
710 | if (absppm < bestppm - 10) { | |
711 | bestppm = absppm; | |
712 | flag = 1; | |
713 | } | |
714 | if (flag) { | |
715 | bestn = n; | |
716 | bestm1 = m1; | |
717 | bestm2 = m2; | |
718 | bestp1 = p1; | |
719 | bestp2 = p2; | |
720 | flag = 0; | |
721 | } | |
722 | } | |
723 | } | |
724 | } | |
725 | } | |
726 | } | |
727 | best_clock->n = bestn; | |
728 | best_clock->m1 = bestm1; | |
729 | best_clock->m2 = bestm2; | |
730 | best_clock->p1 = bestp1; | |
731 | best_clock->p2 = bestp2; | |
732 | ||
733 | return true; | |
734 | } | |
a4fc5ed6 | 735 | |
20ddf665 VS |
736 | bool intel_crtc_active(struct drm_crtc *crtc) |
737 | { | |
738 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
739 | ||
740 | /* Be paranoid as we can arrive here with only partial | |
741 | * state retrieved from the hardware during setup. | |
742 | * | |
743 | * We can ditch the adjusted_mode.clock check as soon | |
744 | * as Haswell has gained clock readout/fastboot support. | |
745 | * | |
746 | * We can ditch the crtc->fb check as soon as we can | |
747 | * properly reconstruct framebuffers. | |
748 | */ | |
749 | return intel_crtc->active && crtc->fb && | |
750 | intel_crtc->config.adjusted_mode.clock; | |
751 | } | |
752 | ||
a5c961d1 PZ |
753 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
754 | enum pipe pipe) | |
755 | { | |
756 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
757 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
758 | ||
3b117c8f | 759 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
760 | } |
761 | ||
a928d536 PZ |
762 | static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) |
763 | { | |
764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
765 | u32 frame, frame_reg = PIPEFRAME(pipe); | |
766 | ||
767 | frame = I915_READ(frame_reg); | |
768 | ||
769 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
770 | DRM_DEBUG_KMS("vblank wait timed out\n"); | |
771 | } | |
772 | ||
9d0498a2 JB |
773 | /** |
774 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
775 | * @dev: drm device | |
776 | * @pipe: pipe to wait for | |
777 | * | |
778 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
779 | * mode setting code. | |
780 | */ | |
781 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 782 | { |
9d0498a2 | 783 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 784 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 785 | |
a928d536 PZ |
786 | if (INTEL_INFO(dev)->gen >= 5) { |
787 | ironlake_wait_for_vblank(dev, pipe); | |
788 | return; | |
789 | } | |
790 | ||
300387c0 CW |
791 | /* Clear existing vblank status. Note this will clear any other |
792 | * sticky status fields as well. | |
793 | * | |
794 | * This races with i915_driver_irq_handler() with the result | |
795 | * that either function could miss a vblank event. Here it is not | |
796 | * fatal, as we will either wait upon the next vblank interrupt or | |
797 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
798 | * called during modeset at which time the GPU should be idle and | |
799 | * should *not* be performing page flips and thus not waiting on | |
800 | * vblanks... | |
801 | * Currently, the result of us stealing a vblank from the irq | |
802 | * handler is that a single frame will be skipped during swapbuffers. | |
803 | */ | |
804 | I915_WRITE(pipestat_reg, | |
805 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
806 | ||
9d0498a2 | 807 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
808 | if (wait_for(I915_READ(pipestat_reg) & |
809 | PIPE_VBLANK_INTERRUPT_STATUS, | |
810 | 50)) | |
9d0498a2 JB |
811 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
812 | } | |
813 | ||
ab7ad7f6 KP |
814 | /* |
815 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
816 | * @dev: drm device |
817 | * @pipe: pipe to wait for | |
818 | * | |
819 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
820 | * spinning on the vblank interrupt status bit, since we won't actually | |
821 | * see an interrupt when the pipe is disabled. | |
822 | * | |
ab7ad7f6 KP |
823 | * On Gen4 and above: |
824 | * wait for the pipe register state bit to turn off | |
825 | * | |
826 | * Otherwise: | |
827 | * wait for the display line value to settle (it usually | |
828 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 829 | * |
9d0498a2 | 830 | */ |
58e10eb9 | 831 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
832 | { |
833 | struct drm_i915_private *dev_priv = dev->dev_private; | |
702e7a56 PZ |
834 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
835 | pipe); | |
ab7ad7f6 KP |
836 | |
837 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 838 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
839 | |
840 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
841 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
842 | 100)) | |
284637d9 | 843 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 844 | } else { |
837ba00f | 845 | u32 last_line, line_mask; |
58e10eb9 | 846 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
847 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
848 | ||
837ba00f PZ |
849 | if (IS_GEN2(dev)) |
850 | line_mask = DSL_LINEMASK_GEN2; | |
851 | else | |
852 | line_mask = DSL_LINEMASK_GEN3; | |
853 | ||
ab7ad7f6 KP |
854 | /* Wait for the display line to settle */ |
855 | do { | |
837ba00f | 856 | last_line = I915_READ(reg) & line_mask; |
ab7ad7f6 | 857 | mdelay(5); |
837ba00f | 858 | } while (((I915_READ(reg) & line_mask) != last_line) && |
ab7ad7f6 KP |
859 | time_after(timeout, jiffies)); |
860 | if (time_after(jiffies, timeout)) | |
284637d9 | 861 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 862 | } |
79e53945 JB |
863 | } |
864 | ||
b0ea7d37 DL |
865 | /* |
866 | * ibx_digital_port_connected - is the specified port connected? | |
867 | * @dev_priv: i915 private structure | |
868 | * @port: the port to test | |
869 | * | |
870 | * Returns true if @port is connected, false otherwise. | |
871 | */ | |
872 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
873 | struct intel_digital_port *port) | |
874 | { | |
875 | u32 bit; | |
876 | ||
c36346e3 DL |
877 | if (HAS_PCH_IBX(dev_priv->dev)) { |
878 | switch(port->port) { | |
879 | case PORT_B: | |
880 | bit = SDE_PORTB_HOTPLUG; | |
881 | break; | |
882 | case PORT_C: | |
883 | bit = SDE_PORTC_HOTPLUG; | |
884 | break; | |
885 | case PORT_D: | |
886 | bit = SDE_PORTD_HOTPLUG; | |
887 | break; | |
888 | default: | |
889 | return true; | |
890 | } | |
891 | } else { | |
892 | switch(port->port) { | |
893 | case PORT_B: | |
894 | bit = SDE_PORTB_HOTPLUG_CPT; | |
895 | break; | |
896 | case PORT_C: | |
897 | bit = SDE_PORTC_HOTPLUG_CPT; | |
898 | break; | |
899 | case PORT_D: | |
900 | bit = SDE_PORTD_HOTPLUG_CPT; | |
901 | break; | |
902 | default: | |
903 | return true; | |
904 | } | |
b0ea7d37 DL |
905 | } |
906 | ||
907 | return I915_READ(SDEISR) & bit; | |
908 | } | |
909 | ||
b24e7179 JB |
910 | static const char *state_string(bool enabled) |
911 | { | |
912 | return enabled ? "on" : "off"; | |
913 | } | |
914 | ||
915 | /* Only for pre-ILK configs */ | |
55607e8a DV |
916 | void assert_pll(struct drm_i915_private *dev_priv, |
917 | enum pipe pipe, bool state) | |
b24e7179 JB |
918 | { |
919 | int reg; | |
920 | u32 val; | |
921 | bool cur_state; | |
922 | ||
923 | reg = DPLL(pipe); | |
924 | val = I915_READ(reg); | |
925 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
926 | WARN(cur_state != state, | |
927 | "PLL state assertion failure (expected %s, current %s)\n", | |
928 | state_string(state), state_string(cur_state)); | |
929 | } | |
b24e7179 | 930 | |
23538ef1 JN |
931 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
932 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
933 | { | |
934 | u32 val; | |
935 | bool cur_state; | |
936 | ||
937 | mutex_lock(&dev_priv->dpio_lock); | |
938 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
939 | mutex_unlock(&dev_priv->dpio_lock); | |
940 | ||
941 | cur_state = val & DSI_PLL_VCO_EN; | |
942 | WARN(cur_state != state, | |
943 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
944 | state_string(state), state_string(cur_state)); | |
945 | } | |
946 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
947 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
948 | ||
55607e8a | 949 | struct intel_shared_dpll * |
e2b78267 DV |
950 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
951 | { | |
952 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
953 | ||
a43f6e0f | 954 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
955 | return NULL; |
956 | ||
a43f6e0f | 957 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
958 | } |
959 | ||
040484af | 960 | /* For ILK+ */ |
55607e8a DV |
961 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
962 | struct intel_shared_dpll *pll, | |
963 | bool state) | |
040484af | 964 | { |
040484af | 965 | bool cur_state; |
5358901f | 966 | struct intel_dpll_hw_state hw_state; |
040484af | 967 | |
9d82aa17 ED |
968 | if (HAS_PCH_LPT(dev_priv->dev)) { |
969 | DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); | |
970 | return; | |
971 | } | |
972 | ||
92b27b08 | 973 | if (WARN (!pll, |
46edb027 | 974 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 975 | return; |
ee7b9f93 | 976 | |
5358901f | 977 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 978 | WARN(cur_state != state, |
5358901f DV |
979 | "%s assertion failure (expected %s, current %s)\n", |
980 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 981 | } |
040484af JB |
982 | |
983 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
984 | enum pipe pipe, bool state) | |
985 | { | |
986 | int reg; | |
987 | u32 val; | |
988 | bool cur_state; | |
ad80a810 PZ |
989 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
990 | pipe); | |
040484af | 991 | |
affa9354 PZ |
992 | if (HAS_DDI(dev_priv->dev)) { |
993 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 994 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 995 | val = I915_READ(reg); |
ad80a810 | 996 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
997 | } else { |
998 | reg = FDI_TX_CTL(pipe); | |
999 | val = I915_READ(reg); | |
1000 | cur_state = !!(val & FDI_TX_ENABLE); | |
1001 | } | |
040484af JB |
1002 | WARN(cur_state != state, |
1003 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1004 | state_string(state), state_string(cur_state)); | |
1005 | } | |
1006 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1007 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1008 | ||
1009 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1010 | enum pipe pipe, bool state) | |
1011 | { | |
1012 | int reg; | |
1013 | u32 val; | |
1014 | bool cur_state; | |
1015 | ||
d63fa0dc PZ |
1016 | reg = FDI_RX_CTL(pipe); |
1017 | val = I915_READ(reg); | |
1018 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1019 | WARN(cur_state != state, |
1020 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1021 | state_string(state), state_string(cur_state)); | |
1022 | } | |
1023 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1024 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1025 | ||
1026 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1027 | enum pipe pipe) | |
1028 | { | |
1029 | int reg; | |
1030 | u32 val; | |
1031 | ||
1032 | /* ILK FDI PLL is always enabled */ | |
1033 | if (dev_priv->info->gen == 5) | |
1034 | return; | |
1035 | ||
bf507ef7 | 1036 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1037 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1038 | return; |
1039 | ||
040484af JB |
1040 | reg = FDI_TX_CTL(pipe); |
1041 | val = I915_READ(reg); | |
1042 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1043 | } | |
1044 | ||
55607e8a DV |
1045 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1046 | enum pipe pipe, bool state) | |
040484af JB |
1047 | { |
1048 | int reg; | |
1049 | u32 val; | |
55607e8a | 1050 | bool cur_state; |
040484af JB |
1051 | |
1052 | reg = FDI_RX_CTL(pipe); | |
1053 | val = I915_READ(reg); | |
55607e8a DV |
1054 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1055 | WARN(cur_state != state, | |
1056 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1057 | state_string(state), state_string(cur_state)); | |
040484af JB |
1058 | } |
1059 | ||
ea0760cf JB |
1060 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1061 | enum pipe pipe) | |
1062 | { | |
1063 | int pp_reg, lvds_reg; | |
1064 | u32 val; | |
1065 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1066 | bool locked = true; |
ea0760cf JB |
1067 | |
1068 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
1069 | pp_reg = PCH_PP_CONTROL; | |
1070 | lvds_reg = PCH_LVDS; | |
1071 | } else { | |
1072 | pp_reg = PP_CONTROL; | |
1073 | lvds_reg = LVDS; | |
1074 | } | |
1075 | ||
1076 | val = I915_READ(pp_reg); | |
1077 | if (!(val & PANEL_POWER_ON) || | |
1078 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
1079 | locked = false; | |
1080 | ||
1081 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
1082 | panel_pipe = PIPE_B; | |
1083 | ||
1084 | WARN(panel_pipe == pipe && locked, | |
1085 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1086 | pipe_name(pipe)); |
ea0760cf JB |
1087 | } |
1088 | ||
93ce0ba6 JN |
1089 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1090 | enum pipe pipe, bool state) | |
1091 | { | |
1092 | struct drm_device *dev = dev_priv->dev; | |
1093 | bool cur_state; | |
1094 | ||
1095 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
1096 | cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE; | |
1097 | else if (IS_845G(dev) || IS_I865G(dev)) | |
1098 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; | |
1099 | else | |
1100 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; | |
1101 | ||
1102 | WARN(cur_state != state, | |
1103 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1104 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1105 | } | |
1106 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1107 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1108 | ||
b840d907 JB |
1109 | void assert_pipe(struct drm_i915_private *dev_priv, |
1110 | enum pipe pipe, bool state) | |
b24e7179 JB |
1111 | { |
1112 | int reg; | |
1113 | u32 val; | |
63d7bbe9 | 1114 | bool cur_state; |
702e7a56 PZ |
1115 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1116 | pipe); | |
b24e7179 | 1117 | |
8e636784 DV |
1118 | /* if we need the pipe A quirk it must be always on */ |
1119 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
1120 | state = true; | |
1121 | ||
b97186f0 PZ |
1122 | if (!intel_display_power_enabled(dev_priv->dev, |
1123 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { | |
69310161 PZ |
1124 | cur_state = false; |
1125 | } else { | |
1126 | reg = PIPECONF(cpu_transcoder); | |
1127 | val = I915_READ(reg); | |
1128 | cur_state = !!(val & PIPECONF_ENABLE); | |
1129 | } | |
1130 | ||
63d7bbe9 JB |
1131 | WARN(cur_state != state, |
1132 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1133 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1134 | } |
1135 | ||
931872fc CW |
1136 | static void assert_plane(struct drm_i915_private *dev_priv, |
1137 | enum plane plane, bool state) | |
b24e7179 JB |
1138 | { |
1139 | int reg; | |
1140 | u32 val; | |
931872fc | 1141 | bool cur_state; |
b24e7179 JB |
1142 | |
1143 | reg = DSPCNTR(plane); | |
1144 | val = I915_READ(reg); | |
931872fc CW |
1145 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1146 | WARN(cur_state != state, | |
1147 | "plane %c assertion failure (expected %s, current %s)\n", | |
1148 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1149 | } |
1150 | ||
931872fc CW |
1151 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1152 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1153 | ||
b24e7179 JB |
1154 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1155 | enum pipe pipe) | |
1156 | { | |
653e1026 | 1157 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1158 | int reg, i; |
1159 | u32 val; | |
1160 | int cur_pipe; | |
1161 | ||
653e1026 VS |
1162 | /* Primary planes are fixed to pipes on gen4+ */ |
1163 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1164 | reg = DSPCNTR(pipe); |
1165 | val = I915_READ(reg); | |
1166 | WARN((val & DISPLAY_PLANE_ENABLE), | |
1167 | "plane %c assertion failure, should be disabled but not\n", | |
1168 | plane_name(pipe)); | |
19ec1358 | 1169 | return; |
28c05794 | 1170 | } |
19ec1358 | 1171 | |
b24e7179 | 1172 | /* Need to check both planes against the pipe */ |
08e2a7de | 1173 | for_each_pipe(i) { |
b24e7179 JB |
1174 | reg = DSPCNTR(i); |
1175 | val = I915_READ(reg); | |
1176 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1177 | DISPPLANE_SEL_PIPE_SHIFT; | |
1178 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1179 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1180 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1181 | } |
1182 | } | |
1183 | ||
19332d7a JB |
1184 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1185 | enum pipe pipe) | |
1186 | { | |
20674eef | 1187 | struct drm_device *dev = dev_priv->dev; |
19332d7a JB |
1188 | int reg, i; |
1189 | u32 val; | |
1190 | ||
20674eef VS |
1191 | if (IS_VALLEYVIEW(dev)) { |
1192 | for (i = 0; i < dev_priv->num_plane; i++) { | |
1193 | reg = SPCNTR(pipe, i); | |
1194 | val = I915_READ(reg); | |
1195 | WARN((val & SP_ENABLE), | |
1196 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", | |
1197 | sprite_name(pipe, i), pipe_name(pipe)); | |
1198 | } | |
1199 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1200 | reg = SPRCTL(pipe); | |
19332d7a | 1201 | val = I915_READ(reg); |
20674eef | 1202 | WARN((val & SPRITE_ENABLE), |
06da8da2 | 1203 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1204 | plane_name(pipe), pipe_name(pipe)); |
1205 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1206 | reg = DVSCNTR(pipe); | |
19332d7a | 1207 | val = I915_READ(reg); |
20674eef | 1208 | WARN((val & DVS_ENABLE), |
06da8da2 | 1209 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1210 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1211 | } |
1212 | } | |
1213 | ||
92f2584a JB |
1214 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
1215 | { | |
1216 | u32 val; | |
1217 | bool enabled; | |
1218 | ||
9d82aa17 ED |
1219 | if (HAS_PCH_LPT(dev_priv->dev)) { |
1220 | DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); | |
1221 | return; | |
1222 | } | |
1223 | ||
92f2584a JB |
1224 | val = I915_READ(PCH_DREF_CONTROL); |
1225 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1226 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1227 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1228 | } | |
1229 | ||
ab9412ba DV |
1230 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1231 | enum pipe pipe) | |
92f2584a JB |
1232 | { |
1233 | int reg; | |
1234 | u32 val; | |
1235 | bool enabled; | |
1236 | ||
ab9412ba | 1237 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1238 | val = I915_READ(reg); |
1239 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1240 | WARN(enabled, |
1241 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1242 | pipe_name(pipe)); | |
92f2584a JB |
1243 | } |
1244 | ||
4e634389 KP |
1245 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1246 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1247 | { |
1248 | if ((val & DP_PORT_EN) == 0) | |
1249 | return false; | |
1250 | ||
1251 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1252 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1253 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1254 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1255 | return false; | |
1256 | } else { | |
1257 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1258 | return false; | |
1259 | } | |
1260 | return true; | |
1261 | } | |
1262 | ||
1519b995 KP |
1263 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1264 | enum pipe pipe, u32 val) | |
1265 | { | |
dc0fa718 | 1266 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1267 | return false; |
1268 | ||
1269 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1270 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 KP |
1271 | return false; |
1272 | } else { | |
dc0fa718 | 1273 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1274 | return false; |
1275 | } | |
1276 | return true; | |
1277 | } | |
1278 | ||
1279 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1280 | enum pipe pipe, u32 val) | |
1281 | { | |
1282 | if ((val & LVDS_PORT_EN) == 0) | |
1283 | return false; | |
1284 | ||
1285 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1286 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1287 | return false; | |
1288 | } else { | |
1289 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1290 | return false; | |
1291 | } | |
1292 | return true; | |
1293 | } | |
1294 | ||
1295 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1296 | enum pipe pipe, u32 val) | |
1297 | { | |
1298 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1299 | return false; | |
1300 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1301 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1302 | return false; | |
1303 | } else { | |
1304 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1305 | return false; | |
1306 | } | |
1307 | return true; | |
1308 | } | |
1309 | ||
291906f1 | 1310 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1311 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1312 | { |
47a05eca | 1313 | u32 val = I915_READ(reg); |
4e634389 | 1314 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1315 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1316 | reg, pipe_name(pipe)); |
de9a35ab | 1317 | |
75c5da27 DV |
1318 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1319 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1320 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1321 | } |
1322 | ||
1323 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1324 | enum pipe pipe, int reg) | |
1325 | { | |
47a05eca | 1326 | u32 val = I915_READ(reg); |
b70ad586 | 1327 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1328 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1329 | reg, pipe_name(pipe)); |
de9a35ab | 1330 | |
dc0fa718 | 1331 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1332 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1333 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1334 | } |
1335 | ||
1336 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1337 | enum pipe pipe) | |
1338 | { | |
1339 | int reg; | |
1340 | u32 val; | |
291906f1 | 1341 | |
f0575e92 KP |
1342 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1343 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1344 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1345 | |
1346 | reg = PCH_ADPA; | |
1347 | val = I915_READ(reg); | |
b70ad586 | 1348 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1349 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1350 | pipe_name(pipe)); |
291906f1 JB |
1351 | |
1352 | reg = PCH_LVDS; | |
1353 | val = I915_READ(reg); | |
b70ad586 | 1354 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1355 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1356 | pipe_name(pipe)); |
291906f1 | 1357 | |
e2debe91 PZ |
1358 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1359 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1360 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1361 | } |
1362 | ||
426115cf | 1363 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1364 | { |
426115cf DV |
1365 | struct drm_device *dev = crtc->base.dev; |
1366 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1367 | int reg = DPLL(crtc->pipe); | |
1368 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1369 | |
426115cf | 1370 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1371 | |
1372 | /* No really, not for ILK+ */ | |
1373 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1374 | ||
1375 | /* PLL is protected by panel, make sure we can write it */ | |
1376 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
426115cf | 1377 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1378 | |
426115cf DV |
1379 | I915_WRITE(reg, dpll); |
1380 | POSTING_READ(reg); | |
1381 | udelay(150); | |
1382 | ||
1383 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1384 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1385 | ||
1386 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1387 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1388 | |
1389 | /* We do this three times for luck */ | |
426115cf | 1390 | I915_WRITE(reg, dpll); |
87442f73 DV |
1391 | POSTING_READ(reg); |
1392 | udelay(150); /* wait for warmup */ | |
426115cf | 1393 | I915_WRITE(reg, dpll); |
87442f73 DV |
1394 | POSTING_READ(reg); |
1395 | udelay(150); /* wait for warmup */ | |
426115cf | 1396 | I915_WRITE(reg, dpll); |
87442f73 DV |
1397 | POSTING_READ(reg); |
1398 | udelay(150); /* wait for warmup */ | |
1399 | } | |
1400 | ||
66e3d5c0 | 1401 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1402 | { |
66e3d5c0 DV |
1403 | struct drm_device *dev = crtc->base.dev; |
1404 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1405 | int reg = DPLL(crtc->pipe); | |
1406 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1407 | |
66e3d5c0 | 1408 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1409 | |
63d7bbe9 | 1410 | /* No really, not for ILK+ */ |
87442f73 | 1411 | BUG_ON(dev_priv->info->gen >= 5); |
63d7bbe9 JB |
1412 | |
1413 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1414 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1415 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1416 | |
66e3d5c0 DV |
1417 | I915_WRITE(reg, dpll); |
1418 | ||
1419 | /* Wait for the clocks to stabilize. */ | |
1420 | POSTING_READ(reg); | |
1421 | udelay(150); | |
1422 | ||
1423 | if (INTEL_INFO(dev)->gen >= 4) { | |
1424 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1425 | crtc->config.dpll_hw_state.dpll_md); | |
1426 | } else { | |
1427 | /* The pixel multiplier can only be updated once the | |
1428 | * DPLL is enabled and the clocks are stable. | |
1429 | * | |
1430 | * So write it again. | |
1431 | */ | |
1432 | I915_WRITE(reg, dpll); | |
1433 | } | |
63d7bbe9 JB |
1434 | |
1435 | /* We do this three times for luck */ | |
66e3d5c0 | 1436 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1437 | POSTING_READ(reg); |
1438 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1439 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1440 | POSTING_READ(reg); |
1441 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1442 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1443 | POSTING_READ(reg); |
1444 | udelay(150); /* wait for warmup */ | |
1445 | } | |
1446 | ||
1447 | /** | |
50b44a44 | 1448 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1449 | * @dev_priv: i915 private structure |
1450 | * @pipe: pipe PLL to disable | |
1451 | * | |
1452 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1453 | * | |
1454 | * Note! This is for pre-ILK only. | |
1455 | */ | |
50b44a44 | 1456 | static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
63d7bbe9 | 1457 | { |
63d7bbe9 JB |
1458 | /* Don't disable pipe A or pipe A PLLs if needed */ |
1459 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1460 | return; | |
1461 | ||
1462 | /* Make sure the pipe isn't still relying on us */ | |
1463 | assert_pipe_disabled(dev_priv, pipe); | |
1464 | ||
50b44a44 DV |
1465 | I915_WRITE(DPLL(pipe), 0); |
1466 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1467 | } |
1468 | ||
89b667f8 JB |
1469 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port) |
1470 | { | |
1471 | u32 port_mask; | |
1472 | ||
1473 | if (!port) | |
1474 | port_mask = DPLL_PORTB_READY_MASK; | |
1475 | else | |
1476 | port_mask = DPLL_PORTC_READY_MASK; | |
1477 | ||
1478 | if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) | |
1479 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", | |
1480 | 'B' + port, I915_READ(DPLL(0))); | |
1481 | } | |
1482 | ||
92f2584a | 1483 | /** |
e72f9fbf | 1484 | * ironlake_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1485 | * @dev_priv: i915 private structure |
1486 | * @pipe: pipe PLL to enable | |
1487 | * | |
1488 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1489 | * drives the transcoder clock. | |
1490 | */ | |
e2b78267 | 1491 | static void ironlake_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1492 | { |
e2b78267 DV |
1493 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1494 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
92f2584a | 1495 | |
48da64a8 | 1496 | /* PCH PLLs only available on ILK, SNB and IVB */ |
92f2584a | 1497 | BUG_ON(dev_priv->info->gen < 5); |
87a875bb | 1498 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1499 | return; |
1500 | ||
1501 | if (WARN_ON(pll->refcount == 0)) | |
1502 | return; | |
ee7b9f93 | 1503 | |
46edb027 DV |
1504 | DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n", |
1505 | pll->name, pll->active, pll->on, | |
e2b78267 | 1506 | crtc->base.base.id); |
92f2584a | 1507 | |
cdbd2316 DV |
1508 | if (pll->active++) { |
1509 | WARN_ON(!pll->on); | |
e9d6944e | 1510 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1511 | return; |
1512 | } | |
f4a091c7 | 1513 | WARN_ON(pll->on); |
ee7b9f93 | 1514 | |
46edb027 | 1515 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1516 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1517 | pll->on = true; |
92f2584a JB |
1518 | } |
1519 | ||
e2b78267 | 1520 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1521 | { |
e2b78267 DV |
1522 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
1523 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
4c609cb8 | 1524 | |
92f2584a JB |
1525 | /* PCH only available on ILK+ */ |
1526 | BUG_ON(dev_priv->info->gen < 5); | |
87a875bb | 1527 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1528 | return; |
92f2584a | 1529 | |
48da64a8 CW |
1530 | if (WARN_ON(pll->refcount == 0)) |
1531 | return; | |
7a419866 | 1532 | |
46edb027 DV |
1533 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1534 | pll->name, pll->active, pll->on, | |
e2b78267 | 1535 | crtc->base.base.id); |
7a419866 | 1536 | |
48da64a8 | 1537 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1538 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1539 | return; |
1540 | } | |
1541 | ||
e9d6944e | 1542 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1543 | WARN_ON(!pll->on); |
cdbd2316 | 1544 | if (--pll->active) |
7a419866 | 1545 | return; |
ee7b9f93 | 1546 | |
46edb027 | 1547 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1548 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1549 | pll->on = false; |
92f2584a JB |
1550 | } |
1551 | ||
b8a4f404 PZ |
1552 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1553 | enum pipe pipe) | |
040484af | 1554 | { |
23670b32 | 1555 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1556 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1557 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1558 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1559 | |
1560 | /* PCH only available on ILK+ */ | |
1561 | BUG_ON(dev_priv->info->gen < 5); | |
1562 | ||
1563 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1564 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1565 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1566 | |
1567 | /* FDI must be feeding us bits for PCH ports */ | |
1568 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1569 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1570 | ||
23670b32 DV |
1571 | if (HAS_PCH_CPT(dev)) { |
1572 | /* Workaround: Set the timing override bit before enabling the | |
1573 | * pch transcoder. */ | |
1574 | reg = TRANS_CHICKEN2(pipe); | |
1575 | val = I915_READ(reg); | |
1576 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1577 | I915_WRITE(reg, val); | |
59c859d6 | 1578 | } |
23670b32 | 1579 | |
ab9412ba | 1580 | reg = PCH_TRANSCONF(pipe); |
040484af | 1581 | val = I915_READ(reg); |
5f7f726d | 1582 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1583 | |
1584 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1585 | /* | |
1586 | * make the BPC in transcoder be consistent with | |
1587 | * that in pipeconf reg. | |
1588 | */ | |
dfd07d72 DV |
1589 | val &= ~PIPECONF_BPC_MASK; |
1590 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1591 | } |
5f7f726d PZ |
1592 | |
1593 | val &= ~TRANS_INTERLACE_MASK; | |
1594 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1595 | if (HAS_PCH_IBX(dev_priv->dev) && |
1596 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1597 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1598 | else | |
1599 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1600 | else |
1601 | val |= TRANS_PROGRESSIVE; | |
1602 | ||
040484af JB |
1603 | I915_WRITE(reg, val | TRANS_ENABLE); |
1604 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1605 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1606 | } |
1607 | ||
8fb033d7 | 1608 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1609 | enum transcoder cpu_transcoder) |
040484af | 1610 | { |
8fb033d7 | 1611 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1612 | |
1613 | /* PCH only available on ILK+ */ | |
1614 | BUG_ON(dev_priv->info->gen < 5); | |
1615 | ||
8fb033d7 | 1616 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1617 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1618 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1619 | |
223a6fdf PZ |
1620 | /* Workaround: set timing override bit. */ |
1621 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1622 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1623 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1624 | ||
25f3ef11 | 1625 | val = TRANS_ENABLE; |
937bb610 | 1626 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1627 | |
9a76b1c6 PZ |
1628 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1629 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1630 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1631 | else |
1632 | val |= TRANS_PROGRESSIVE; | |
1633 | ||
ab9412ba DV |
1634 | I915_WRITE(LPT_TRANSCONF, val); |
1635 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1636 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1637 | } |
1638 | ||
b8a4f404 PZ |
1639 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1640 | enum pipe pipe) | |
040484af | 1641 | { |
23670b32 DV |
1642 | struct drm_device *dev = dev_priv->dev; |
1643 | uint32_t reg, val; | |
040484af JB |
1644 | |
1645 | /* FDI relies on the transcoder */ | |
1646 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1647 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1648 | ||
291906f1 JB |
1649 | /* Ports must be off as well */ |
1650 | assert_pch_ports_disabled(dev_priv, pipe); | |
1651 | ||
ab9412ba | 1652 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1653 | val = I915_READ(reg); |
1654 | val &= ~TRANS_ENABLE; | |
1655 | I915_WRITE(reg, val); | |
1656 | /* wait for PCH transcoder off, transcoder state */ | |
1657 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1658 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1659 | |
1660 | if (!HAS_PCH_IBX(dev)) { | |
1661 | /* Workaround: Clear the timing override chicken bit again. */ | |
1662 | reg = TRANS_CHICKEN2(pipe); | |
1663 | val = I915_READ(reg); | |
1664 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1665 | I915_WRITE(reg, val); | |
1666 | } | |
040484af JB |
1667 | } |
1668 | ||
ab4d966c | 1669 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1670 | { |
8fb033d7 PZ |
1671 | u32 val; |
1672 | ||
ab9412ba | 1673 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1674 | val &= ~TRANS_ENABLE; |
ab9412ba | 1675 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1676 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1677 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1678 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1679 | |
1680 | /* Workaround: clear timing override bit. */ | |
1681 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1682 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1683 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1684 | } |
1685 | ||
b24e7179 | 1686 | /** |
309cfea8 | 1687 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1688 | * @dev_priv: i915 private structure |
1689 | * @pipe: pipe to enable | |
040484af | 1690 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1691 | * |
1692 | * Enable @pipe, making sure that various hardware specific requirements | |
1693 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1694 | * | |
1695 | * @pipe should be %PIPE_A or %PIPE_B. | |
1696 | * | |
1697 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1698 | * returning. | |
1699 | */ | |
040484af | 1700 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
23538ef1 | 1701 | bool pch_port, bool dsi) |
b24e7179 | 1702 | { |
702e7a56 PZ |
1703 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1704 | pipe); | |
1a240d4d | 1705 | enum pipe pch_transcoder; |
b24e7179 JB |
1706 | int reg; |
1707 | u32 val; | |
1708 | ||
58c6eaa2 | 1709 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1710 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1711 | assert_sprites_disabled(dev_priv, pipe); |
1712 | ||
681e5811 | 1713 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
1714 | pch_transcoder = TRANSCODER_A; |
1715 | else | |
1716 | pch_transcoder = pipe; | |
1717 | ||
b24e7179 JB |
1718 | /* |
1719 | * A pipe without a PLL won't actually be able to drive bits from | |
1720 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1721 | * need the check. | |
1722 | */ | |
1723 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
23538ef1 JN |
1724 | if (dsi) |
1725 | assert_dsi_pll_enabled(dev_priv); | |
1726 | else | |
1727 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1728 | else { |
1729 | if (pch_port) { | |
1730 | /* if driving the PCH, we need FDI enabled */ | |
cc391bbb | 1731 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1732 | assert_fdi_tx_pll_enabled(dev_priv, |
1733 | (enum pipe) cpu_transcoder); | |
040484af JB |
1734 | } |
1735 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1736 | } | |
b24e7179 | 1737 | |
702e7a56 | 1738 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1739 | val = I915_READ(reg); |
00d70b15 CW |
1740 | if (val & PIPECONF_ENABLE) |
1741 | return; | |
1742 | ||
1743 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1744 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1745 | } | |
1746 | ||
1747 | /** | |
309cfea8 | 1748 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1749 | * @dev_priv: i915 private structure |
1750 | * @pipe: pipe to disable | |
1751 | * | |
1752 | * Disable @pipe, making sure that various hardware specific requirements | |
1753 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1754 | * | |
1755 | * @pipe should be %PIPE_A or %PIPE_B. | |
1756 | * | |
1757 | * Will wait until the pipe has shut down before returning. | |
1758 | */ | |
1759 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1760 | enum pipe pipe) | |
1761 | { | |
702e7a56 PZ |
1762 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1763 | pipe); | |
b24e7179 JB |
1764 | int reg; |
1765 | u32 val; | |
1766 | ||
1767 | /* | |
1768 | * Make sure planes won't keep trying to pump pixels to us, | |
1769 | * or we might hang the display. | |
1770 | */ | |
1771 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1772 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1773 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 JB |
1774 | |
1775 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1776 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1777 | return; | |
1778 | ||
702e7a56 | 1779 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1780 | val = I915_READ(reg); |
00d70b15 CW |
1781 | if ((val & PIPECONF_ENABLE) == 0) |
1782 | return; | |
1783 | ||
1784 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1785 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1786 | } | |
1787 | ||
d74362c9 KP |
1788 | /* |
1789 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1790 | * trigger in order to latch. The display address reg provides this. | |
1791 | */ | |
6f1d69b0 | 1792 | void intel_flush_display_plane(struct drm_i915_private *dev_priv, |
d74362c9 KP |
1793 | enum plane plane) |
1794 | { | |
14f86147 DL |
1795 | if (dev_priv->info->gen >= 4) |
1796 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); | |
1797 | else | |
1798 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); | |
d74362c9 KP |
1799 | } |
1800 | ||
b24e7179 JB |
1801 | /** |
1802 | * intel_enable_plane - enable a display plane on a given pipe | |
1803 | * @dev_priv: i915 private structure | |
1804 | * @plane: plane to enable | |
1805 | * @pipe: pipe being fed | |
1806 | * | |
1807 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1808 | */ | |
1809 | static void intel_enable_plane(struct drm_i915_private *dev_priv, | |
1810 | enum plane plane, enum pipe pipe) | |
1811 | { | |
1812 | int reg; | |
1813 | u32 val; | |
1814 | ||
1815 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1816 | assert_pipe_enabled(dev_priv, pipe); | |
1817 | ||
1818 | reg = DSPCNTR(plane); | |
1819 | val = I915_READ(reg); | |
00d70b15 CW |
1820 | if (val & DISPLAY_PLANE_ENABLE) |
1821 | return; | |
1822 | ||
1823 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
d74362c9 | 1824 | intel_flush_display_plane(dev_priv, plane); |
b24e7179 JB |
1825 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1826 | } | |
1827 | ||
b24e7179 JB |
1828 | /** |
1829 | * intel_disable_plane - disable a display plane | |
1830 | * @dev_priv: i915 private structure | |
1831 | * @plane: plane to disable | |
1832 | * @pipe: pipe consuming the data | |
1833 | * | |
1834 | * Disable @plane; should be an independent operation. | |
1835 | */ | |
1836 | static void intel_disable_plane(struct drm_i915_private *dev_priv, | |
1837 | enum plane plane, enum pipe pipe) | |
1838 | { | |
1839 | int reg; | |
1840 | u32 val; | |
1841 | ||
1842 | reg = DSPCNTR(plane); | |
1843 | val = I915_READ(reg); | |
00d70b15 CW |
1844 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1845 | return; | |
1846 | ||
1847 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
b24e7179 JB |
1848 | intel_flush_display_plane(dev_priv, plane); |
1849 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1850 | } | |
1851 | ||
693db184 CW |
1852 | static bool need_vtd_wa(struct drm_device *dev) |
1853 | { | |
1854 | #ifdef CONFIG_INTEL_IOMMU | |
1855 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
1856 | return true; | |
1857 | #endif | |
1858 | return false; | |
1859 | } | |
1860 | ||
127bd2ac | 1861 | int |
48b956c5 | 1862 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 1863 | struct drm_i915_gem_object *obj, |
919926ae | 1864 | struct intel_ring_buffer *pipelined) |
6b95a207 | 1865 | { |
ce453d81 | 1866 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
1867 | u32 alignment; |
1868 | int ret; | |
1869 | ||
05394f39 | 1870 | switch (obj->tiling_mode) { |
6b95a207 | 1871 | case I915_TILING_NONE: |
534843da CW |
1872 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
1873 | alignment = 128 * 1024; | |
a6c45cf0 | 1874 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
1875 | alignment = 4 * 1024; |
1876 | else | |
1877 | alignment = 64 * 1024; | |
6b95a207 KH |
1878 | break; |
1879 | case I915_TILING_X: | |
1880 | /* pin() will align the object as required by fence */ | |
1881 | alignment = 0; | |
1882 | break; | |
1883 | case I915_TILING_Y: | |
8bb6e959 DV |
1884 | /* Despite that we check this in framebuffer_init userspace can |
1885 | * screw us over and change the tiling after the fact. Only | |
1886 | * pinned buffers can't change their tiling. */ | |
1887 | DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n"); | |
6b95a207 KH |
1888 | return -EINVAL; |
1889 | default: | |
1890 | BUG(); | |
1891 | } | |
1892 | ||
693db184 CW |
1893 | /* Note that the w/a also requires 64 PTE of padding following the |
1894 | * bo. We currently fill all unused PTE with the shadow page and so | |
1895 | * we should always have valid PTE following the scanout preventing | |
1896 | * the VT-d warning. | |
1897 | */ | |
1898 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
1899 | alignment = 256 * 1024; | |
1900 | ||
ce453d81 | 1901 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 1902 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 1903 | if (ret) |
ce453d81 | 1904 | goto err_interruptible; |
6b95a207 KH |
1905 | |
1906 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
1907 | * fence, whereas 965+ only requires a fence if using | |
1908 | * framebuffer compression. For simplicity, we always install | |
1909 | * a fence as the cost is not that onerous. | |
1910 | */ | |
06d98131 | 1911 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
1912 | if (ret) |
1913 | goto err_unpin; | |
1690e1eb | 1914 | |
9a5a53b3 | 1915 | i915_gem_object_pin_fence(obj); |
6b95a207 | 1916 | |
ce453d81 | 1917 | dev_priv->mm.interruptible = true; |
6b95a207 | 1918 | return 0; |
48b956c5 CW |
1919 | |
1920 | err_unpin: | |
cc98b413 | 1921 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
1922 | err_interruptible: |
1923 | dev_priv->mm.interruptible = true; | |
48b956c5 | 1924 | return ret; |
6b95a207 KH |
1925 | } |
1926 | ||
1690e1eb CW |
1927 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
1928 | { | |
1929 | i915_gem_object_unpin_fence(obj); | |
cc98b413 | 1930 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
1931 | } |
1932 | ||
c2c75131 DV |
1933 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
1934 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
1935 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
1936 | unsigned int tiling_mode, | |
1937 | unsigned int cpp, | |
1938 | unsigned int pitch) | |
c2c75131 | 1939 | { |
bc752862 CW |
1940 | if (tiling_mode != I915_TILING_NONE) { |
1941 | unsigned int tile_rows, tiles; | |
c2c75131 | 1942 | |
bc752862 CW |
1943 | tile_rows = *y / 8; |
1944 | *y %= 8; | |
c2c75131 | 1945 | |
bc752862 CW |
1946 | tiles = *x / (512/cpp); |
1947 | *x %= 512/cpp; | |
1948 | ||
1949 | return tile_rows * pitch * 8 + tiles * 4096; | |
1950 | } else { | |
1951 | unsigned int offset; | |
1952 | ||
1953 | offset = *y * pitch + *x * cpp; | |
1954 | *y = 0; | |
1955 | *x = (offset & 4095) / cpp; | |
1956 | return offset & -4096; | |
1957 | } | |
c2c75131 DV |
1958 | } |
1959 | ||
17638cd6 JB |
1960 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
1961 | int x, int y) | |
81255565 JB |
1962 | { |
1963 | struct drm_device *dev = crtc->dev; | |
1964 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1965 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1966 | struct intel_framebuffer *intel_fb; | |
05394f39 | 1967 | struct drm_i915_gem_object *obj; |
81255565 | 1968 | int plane = intel_crtc->plane; |
e506a0c6 | 1969 | unsigned long linear_offset; |
81255565 | 1970 | u32 dspcntr; |
5eddb70b | 1971 | u32 reg; |
81255565 JB |
1972 | |
1973 | switch (plane) { | |
1974 | case 0: | |
1975 | case 1: | |
1976 | break; | |
1977 | default: | |
84f44ce7 | 1978 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
81255565 JB |
1979 | return -EINVAL; |
1980 | } | |
1981 | ||
1982 | intel_fb = to_intel_framebuffer(fb); | |
1983 | obj = intel_fb->obj; | |
81255565 | 1984 | |
5eddb70b CW |
1985 | reg = DSPCNTR(plane); |
1986 | dspcntr = I915_READ(reg); | |
81255565 JB |
1987 | /* Mask out pixel format bits in case we change it */ |
1988 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
1989 | switch (fb->pixel_format) { |
1990 | case DRM_FORMAT_C8: | |
81255565 JB |
1991 | dspcntr |= DISPPLANE_8BPP; |
1992 | break; | |
57779d06 VS |
1993 | case DRM_FORMAT_XRGB1555: |
1994 | case DRM_FORMAT_ARGB1555: | |
1995 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 1996 | break; |
57779d06 VS |
1997 | case DRM_FORMAT_RGB565: |
1998 | dspcntr |= DISPPLANE_BGRX565; | |
1999 | break; | |
2000 | case DRM_FORMAT_XRGB8888: | |
2001 | case DRM_FORMAT_ARGB8888: | |
2002 | dspcntr |= DISPPLANE_BGRX888; | |
2003 | break; | |
2004 | case DRM_FORMAT_XBGR8888: | |
2005 | case DRM_FORMAT_ABGR8888: | |
2006 | dspcntr |= DISPPLANE_RGBX888; | |
2007 | break; | |
2008 | case DRM_FORMAT_XRGB2101010: | |
2009 | case DRM_FORMAT_ARGB2101010: | |
2010 | dspcntr |= DISPPLANE_BGRX101010; | |
2011 | break; | |
2012 | case DRM_FORMAT_XBGR2101010: | |
2013 | case DRM_FORMAT_ABGR2101010: | |
2014 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2015 | break; |
2016 | default: | |
baba133a | 2017 | BUG(); |
81255565 | 2018 | } |
57779d06 | 2019 | |
a6c45cf0 | 2020 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2021 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2022 | dspcntr |= DISPPLANE_TILED; |
2023 | else | |
2024 | dspcntr &= ~DISPPLANE_TILED; | |
2025 | } | |
2026 | ||
de1aa629 VS |
2027 | if (IS_G4X(dev)) |
2028 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2029 | ||
5eddb70b | 2030 | I915_WRITE(reg, dspcntr); |
81255565 | 2031 | |
e506a0c6 | 2032 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2033 | |
c2c75131 DV |
2034 | if (INTEL_INFO(dev)->gen >= 4) { |
2035 | intel_crtc->dspaddr_offset = | |
bc752862 CW |
2036 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2037 | fb->bits_per_pixel / 8, | |
2038 | fb->pitches[0]); | |
c2c75131 DV |
2039 | linear_offset -= intel_crtc->dspaddr_offset; |
2040 | } else { | |
e506a0c6 | 2041 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2042 | } |
e506a0c6 | 2043 | |
f343c5f6 BW |
2044 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2045 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2046 | fb->pitches[0]); | |
01f2c773 | 2047 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2048 | if (INTEL_INFO(dev)->gen >= 4) { |
c2c75131 | 2049 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
f343c5f6 | 2050 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
5eddb70b | 2051 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2052 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2053 | } else |
f343c5f6 | 2054 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2055 | POSTING_READ(reg); |
81255565 | 2056 | |
17638cd6 JB |
2057 | return 0; |
2058 | } | |
2059 | ||
2060 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2061 | struct drm_framebuffer *fb, int x, int y) | |
2062 | { | |
2063 | struct drm_device *dev = crtc->dev; | |
2064 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2065 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2066 | struct intel_framebuffer *intel_fb; | |
2067 | struct drm_i915_gem_object *obj; | |
2068 | int plane = intel_crtc->plane; | |
e506a0c6 | 2069 | unsigned long linear_offset; |
17638cd6 JB |
2070 | u32 dspcntr; |
2071 | u32 reg; | |
2072 | ||
2073 | switch (plane) { | |
2074 | case 0: | |
2075 | case 1: | |
27f8227b | 2076 | case 2: |
17638cd6 JB |
2077 | break; |
2078 | default: | |
84f44ce7 | 2079 | DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane)); |
17638cd6 JB |
2080 | return -EINVAL; |
2081 | } | |
2082 | ||
2083 | intel_fb = to_intel_framebuffer(fb); | |
2084 | obj = intel_fb->obj; | |
2085 | ||
2086 | reg = DSPCNTR(plane); | |
2087 | dspcntr = I915_READ(reg); | |
2088 | /* Mask out pixel format bits in case we change it */ | |
2089 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
57779d06 VS |
2090 | switch (fb->pixel_format) { |
2091 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2092 | dspcntr |= DISPPLANE_8BPP; |
2093 | break; | |
57779d06 VS |
2094 | case DRM_FORMAT_RGB565: |
2095 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2096 | break; |
57779d06 VS |
2097 | case DRM_FORMAT_XRGB8888: |
2098 | case DRM_FORMAT_ARGB8888: | |
2099 | dspcntr |= DISPPLANE_BGRX888; | |
2100 | break; | |
2101 | case DRM_FORMAT_XBGR8888: | |
2102 | case DRM_FORMAT_ABGR8888: | |
2103 | dspcntr |= DISPPLANE_RGBX888; | |
2104 | break; | |
2105 | case DRM_FORMAT_XRGB2101010: | |
2106 | case DRM_FORMAT_ARGB2101010: | |
2107 | dspcntr |= DISPPLANE_BGRX101010; | |
2108 | break; | |
2109 | case DRM_FORMAT_XBGR2101010: | |
2110 | case DRM_FORMAT_ABGR2101010: | |
2111 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2112 | break; |
2113 | default: | |
baba133a | 2114 | BUG(); |
17638cd6 JB |
2115 | } |
2116 | ||
2117 | if (obj->tiling_mode != I915_TILING_NONE) | |
2118 | dspcntr |= DISPPLANE_TILED; | |
2119 | else | |
2120 | dspcntr &= ~DISPPLANE_TILED; | |
2121 | ||
1f5d76db PZ |
2122 | if (IS_HASWELL(dev)) |
2123 | dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE; | |
2124 | else | |
2125 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
17638cd6 JB |
2126 | |
2127 | I915_WRITE(reg, dspcntr); | |
2128 | ||
e506a0c6 | 2129 | linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
c2c75131 | 2130 | intel_crtc->dspaddr_offset = |
bc752862 CW |
2131 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
2132 | fb->bits_per_pixel / 8, | |
2133 | fb->pitches[0]); | |
c2c75131 | 2134 | linear_offset -= intel_crtc->dspaddr_offset; |
17638cd6 | 2135 | |
f343c5f6 BW |
2136 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2137 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2138 | fb->pitches[0]); | |
01f2c773 | 2139 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
c2c75131 | 2140 | I915_MODIFY_DISPBASE(DSPSURF(plane), |
f343c5f6 | 2141 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
bc1c91eb DL |
2142 | if (IS_HASWELL(dev)) { |
2143 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); | |
2144 | } else { | |
2145 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2146 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2147 | } | |
17638cd6 JB |
2148 | POSTING_READ(reg); |
2149 | ||
2150 | return 0; | |
2151 | } | |
2152 | ||
2153 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2154 | static int | |
2155 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2156 | int x, int y, enum mode_set_atomic state) | |
2157 | { | |
2158 | struct drm_device *dev = crtc->dev; | |
2159 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2160 | |
6b8e6ed0 CW |
2161 | if (dev_priv->display.disable_fbc) |
2162 | dev_priv->display.disable_fbc(dev); | |
3dec0095 | 2163 | intel_increase_pllclock(crtc); |
81255565 | 2164 | |
6b8e6ed0 | 2165 | return dev_priv->display.update_plane(crtc, fb, x, y); |
81255565 JB |
2166 | } |
2167 | ||
96a02917 VS |
2168 | void intel_display_handle_reset(struct drm_device *dev) |
2169 | { | |
2170 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2171 | struct drm_crtc *crtc; | |
2172 | ||
2173 | /* | |
2174 | * Flips in the rings have been nuked by the reset, | |
2175 | * so complete all pending flips so that user space | |
2176 | * will get its events and not get stuck. | |
2177 | * | |
2178 | * Also update the base address of all primary | |
2179 | * planes to the the last fb to make sure we're | |
2180 | * showing the correct fb after a reset. | |
2181 | * | |
2182 | * Need to make two loops over the crtcs so that we | |
2183 | * don't try to grab a crtc mutex before the | |
2184 | * pending_flip_queue really got woken up. | |
2185 | */ | |
2186 | ||
2187 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2188 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2189 | enum plane plane = intel_crtc->plane; | |
2190 | ||
2191 | intel_prepare_page_flip(dev, plane); | |
2192 | intel_finish_page_flip_plane(dev, plane); | |
2193 | } | |
2194 | ||
2195 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2196 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2197 | ||
2198 | mutex_lock(&crtc->mutex); | |
2199 | if (intel_crtc->active) | |
2200 | dev_priv->display.update_plane(crtc, crtc->fb, | |
2201 | crtc->x, crtc->y); | |
2202 | mutex_unlock(&crtc->mutex); | |
2203 | } | |
2204 | } | |
2205 | ||
14667a4b CW |
2206 | static int |
2207 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2208 | { | |
2209 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; | |
2210 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2211 | bool was_interruptible = dev_priv->mm.interruptible; | |
2212 | int ret; | |
2213 | ||
14667a4b CW |
2214 | /* Big Hammer, we also need to ensure that any pending |
2215 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2216 | * current scanout is retired before unpinning the old | |
2217 | * framebuffer. | |
2218 | * | |
2219 | * This should only fail upon a hung GPU, in which case we | |
2220 | * can safely continue. | |
2221 | */ | |
2222 | dev_priv->mm.interruptible = false; | |
2223 | ret = i915_gem_object_finish_gpu(obj); | |
2224 | dev_priv->mm.interruptible = was_interruptible; | |
2225 | ||
2226 | return ret; | |
2227 | } | |
2228 | ||
198598d0 VS |
2229 | static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) |
2230 | { | |
2231 | struct drm_device *dev = crtc->dev; | |
2232 | struct drm_i915_master_private *master_priv; | |
2233 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2234 | ||
2235 | if (!dev->primary->master) | |
2236 | return; | |
2237 | ||
2238 | master_priv = dev->primary->master->driver_priv; | |
2239 | if (!master_priv->sarea_priv) | |
2240 | return; | |
2241 | ||
2242 | switch (intel_crtc->pipe) { | |
2243 | case 0: | |
2244 | master_priv->sarea_priv->pipeA_x = x; | |
2245 | master_priv->sarea_priv->pipeA_y = y; | |
2246 | break; | |
2247 | case 1: | |
2248 | master_priv->sarea_priv->pipeB_x = x; | |
2249 | master_priv->sarea_priv->pipeB_y = y; | |
2250 | break; | |
2251 | default: | |
2252 | break; | |
2253 | } | |
2254 | } | |
2255 | ||
5c3b82e2 | 2256 | static int |
3c4fdcfb | 2257 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2258 | struct drm_framebuffer *fb) |
79e53945 JB |
2259 | { |
2260 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2261 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2262 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
94352cf9 | 2263 | struct drm_framebuffer *old_fb; |
5c3b82e2 | 2264 | int ret; |
79e53945 JB |
2265 | |
2266 | /* no fb bound */ | |
94352cf9 | 2267 | if (!fb) { |
a5071c2f | 2268 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2269 | return 0; |
2270 | } | |
2271 | ||
7eb552ae | 2272 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2273 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2274 | plane_name(intel_crtc->plane), | |
2275 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2276 | return -EINVAL; |
79e53945 JB |
2277 | } |
2278 | ||
5c3b82e2 | 2279 | mutex_lock(&dev->struct_mutex); |
265db958 | 2280 | ret = intel_pin_and_fence_fb_obj(dev, |
94352cf9 | 2281 | to_intel_framebuffer(fb)->obj, |
919926ae | 2282 | NULL); |
5c3b82e2 CW |
2283 | if (ret != 0) { |
2284 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2285 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2286 | return ret; |
2287 | } | |
79e53945 | 2288 | |
4d6a3e63 JB |
2289 | /* Update pipe size and adjust fitter if needed */ |
2290 | if (i915_fastboot) { | |
2291 | I915_WRITE(PIPESRC(intel_crtc->pipe), | |
2292 | ((crtc->mode.hdisplay - 1) << 16) | | |
2293 | (crtc->mode.vdisplay - 1)); | |
fd4daa9c | 2294 | if (!intel_crtc->config.pch_pfit.enabled && |
4d6a3e63 JB |
2295 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2296 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
2297 | I915_WRITE(PF_CTL(intel_crtc->pipe), 0); | |
2298 | I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0); | |
2299 | I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0); | |
2300 | } | |
2301 | } | |
2302 | ||
94352cf9 | 2303 | ret = dev_priv->display.update_plane(crtc, fb, x, y); |
4e6cfefc | 2304 | if (ret) { |
94352cf9 | 2305 | intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); |
5c3b82e2 | 2306 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2307 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2308 | return ret; |
79e53945 | 2309 | } |
3c4fdcfb | 2310 | |
94352cf9 DV |
2311 | old_fb = crtc->fb; |
2312 | crtc->fb = fb; | |
6c4c86f5 DV |
2313 | crtc->x = x; |
2314 | crtc->y = y; | |
94352cf9 | 2315 | |
b7f1de28 | 2316 | if (old_fb) { |
d7697eea DV |
2317 | if (intel_crtc->active && old_fb != fb) |
2318 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2319 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2320 | } |
652c393a | 2321 | |
6b8e6ed0 | 2322 | intel_update_fbc(dev); |
4906557e | 2323 | intel_edp_psr_update(dev); |
5c3b82e2 | 2324 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2325 | |
198598d0 | 2326 | intel_crtc_update_sarea_pos(crtc, x, y); |
5c3b82e2 CW |
2327 | |
2328 | return 0; | |
79e53945 JB |
2329 | } |
2330 | ||
5e84e1a4 ZW |
2331 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2332 | { | |
2333 | struct drm_device *dev = crtc->dev; | |
2334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2335 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2336 | int pipe = intel_crtc->pipe; | |
2337 | u32 reg, temp; | |
2338 | ||
2339 | /* enable normal train */ | |
2340 | reg = FDI_TX_CTL(pipe); | |
2341 | temp = I915_READ(reg); | |
61e499bf | 2342 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2343 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2344 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2345 | } else { |
2346 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2347 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2348 | } |
5e84e1a4 ZW |
2349 | I915_WRITE(reg, temp); |
2350 | ||
2351 | reg = FDI_RX_CTL(pipe); | |
2352 | temp = I915_READ(reg); | |
2353 | if (HAS_PCH_CPT(dev)) { | |
2354 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2355 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2356 | } else { | |
2357 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2358 | temp |= FDI_LINK_TRAIN_NONE; | |
2359 | } | |
2360 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2361 | ||
2362 | /* wait one idle pattern time */ | |
2363 | POSTING_READ(reg); | |
2364 | udelay(1000); | |
357555c0 JB |
2365 | |
2366 | /* IVB wants error correction enabled */ | |
2367 | if (IS_IVYBRIDGE(dev)) | |
2368 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2369 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2370 | } |
2371 | ||
1e833f40 DV |
2372 | static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc) |
2373 | { | |
2374 | return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder; | |
2375 | } | |
2376 | ||
01a415fd DV |
2377 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2378 | { | |
2379 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2380 | struct intel_crtc *pipe_B_crtc = | |
2381 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2382 | struct intel_crtc *pipe_C_crtc = | |
2383 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2384 | uint32_t temp; | |
2385 | ||
1e833f40 DV |
2386 | /* |
2387 | * When everything is off disable fdi C so that we could enable fdi B | |
2388 | * with all lanes. Note that we don't care about enabled pipes without | |
2389 | * an enabled pch encoder. | |
2390 | */ | |
2391 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2392 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2393 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2394 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2395 | ||
2396 | temp = I915_READ(SOUTH_CHICKEN1); | |
2397 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2398 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2399 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2400 | } | |
2401 | } | |
2402 | ||
8db9d77b ZW |
2403 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2404 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2405 | { | |
2406 | struct drm_device *dev = crtc->dev; | |
2407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2408 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2409 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2410 | int plane = intel_crtc->plane; |
5eddb70b | 2411 | u32 reg, temp, tries; |
8db9d77b | 2412 | |
0fc932b8 JB |
2413 | /* FDI needs bits from pipe & plane first */ |
2414 | assert_pipe_enabled(dev_priv, pipe); | |
2415 | assert_plane_enabled(dev_priv, plane); | |
2416 | ||
e1a44743 AJ |
2417 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2418 | for train result */ | |
5eddb70b CW |
2419 | reg = FDI_RX_IMR(pipe); |
2420 | temp = I915_READ(reg); | |
e1a44743 AJ |
2421 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2422 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2423 | I915_WRITE(reg, temp); |
2424 | I915_READ(reg); | |
e1a44743 AJ |
2425 | udelay(150); |
2426 | ||
8db9d77b | 2427 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2428 | reg = FDI_TX_CTL(pipe); |
2429 | temp = I915_READ(reg); | |
627eb5a3 DV |
2430 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2431 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2432 | temp &= ~FDI_LINK_TRAIN_NONE; |
2433 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2434 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2435 | |
5eddb70b CW |
2436 | reg = FDI_RX_CTL(pipe); |
2437 | temp = I915_READ(reg); | |
8db9d77b ZW |
2438 | temp &= ~FDI_LINK_TRAIN_NONE; |
2439 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2440 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2441 | ||
2442 | POSTING_READ(reg); | |
8db9d77b ZW |
2443 | udelay(150); |
2444 | ||
5b2adf89 | 2445 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
2446 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
2447 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2448 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 2449 | |
5eddb70b | 2450 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2451 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2452 | temp = I915_READ(reg); |
8db9d77b ZW |
2453 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2454 | ||
2455 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2456 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2457 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2458 | break; |
2459 | } | |
8db9d77b | 2460 | } |
e1a44743 | 2461 | if (tries == 5) |
5eddb70b | 2462 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2463 | |
2464 | /* Train 2 */ | |
5eddb70b CW |
2465 | reg = FDI_TX_CTL(pipe); |
2466 | temp = I915_READ(reg); | |
8db9d77b ZW |
2467 | temp &= ~FDI_LINK_TRAIN_NONE; |
2468 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2469 | I915_WRITE(reg, temp); |
8db9d77b | 2470 | |
5eddb70b CW |
2471 | reg = FDI_RX_CTL(pipe); |
2472 | temp = I915_READ(reg); | |
8db9d77b ZW |
2473 | temp &= ~FDI_LINK_TRAIN_NONE; |
2474 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2475 | I915_WRITE(reg, temp); |
8db9d77b | 2476 | |
5eddb70b CW |
2477 | POSTING_READ(reg); |
2478 | udelay(150); | |
8db9d77b | 2479 | |
5eddb70b | 2480 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2481 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2482 | temp = I915_READ(reg); |
8db9d77b ZW |
2483 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2484 | ||
2485 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2486 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2487 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2488 | break; | |
2489 | } | |
8db9d77b | 2490 | } |
e1a44743 | 2491 | if (tries == 5) |
5eddb70b | 2492 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2493 | |
2494 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2495 | |
8db9d77b ZW |
2496 | } |
2497 | ||
0206e353 | 2498 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2499 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2500 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2501 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2502 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2503 | }; | |
2504 | ||
2505 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2506 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2507 | { | |
2508 | struct drm_device *dev = crtc->dev; | |
2509 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2510 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2511 | int pipe = intel_crtc->pipe; | |
fa37d39e | 2512 | u32 reg, temp, i, retry; |
8db9d77b | 2513 | |
e1a44743 AJ |
2514 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2515 | for train result */ | |
5eddb70b CW |
2516 | reg = FDI_RX_IMR(pipe); |
2517 | temp = I915_READ(reg); | |
e1a44743 AJ |
2518 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2519 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2520 | I915_WRITE(reg, temp); |
2521 | ||
2522 | POSTING_READ(reg); | |
e1a44743 AJ |
2523 | udelay(150); |
2524 | ||
8db9d77b | 2525 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2526 | reg = FDI_TX_CTL(pipe); |
2527 | temp = I915_READ(reg); | |
627eb5a3 DV |
2528 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2529 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2530 | temp &= ~FDI_LINK_TRAIN_NONE; |
2531 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2532 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2533 | /* SNB-B */ | |
2534 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2535 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2536 | |
d74cf324 DV |
2537 | I915_WRITE(FDI_RX_MISC(pipe), |
2538 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
2539 | ||
5eddb70b CW |
2540 | reg = FDI_RX_CTL(pipe); |
2541 | temp = I915_READ(reg); | |
8db9d77b ZW |
2542 | if (HAS_PCH_CPT(dev)) { |
2543 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2544 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2545 | } else { | |
2546 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2547 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2548 | } | |
5eddb70b CW |
2549 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2550 | ||
2551 | POSTING_READ(reg); | |
8db9d77b ZW |
2552 | udelay(150); |
2553 | ||
0206e353 | 2554 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2555 | reg = FDI_TX_CTL(pipe); |
2556 | temp = I915_READ(reg); | |
8db9d77b ZW |
2557 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2558 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2559 | I915_WRITE(reg, temp); |
2560 | ||
2561 | POSTING_READ(reg); | |
8db9d77b ZW |
2562 | udelay(500); |
2563 | ||
fa37d39e SP |
2564 | for (retry = 0; retry < 5; retry++) { |
2565 | reg = FDI_RX_IIR(pipe); | |
2566 | temp = I915_READ(reg); | |
2567 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2568 | if (temp & FDI_RX_BIT_LOCK) { | |
2569 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2570 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2571 | break; | |
2572 | } | |
2573 | udelay(50); | |
8db9d77b | 2574 | } |
fa37d39e SP |
2575 | if (retry < 5) |
2576 | break; | |
8db9d77b ZW |
2577 | } |
2578 | if (i == 4) | |
5eddb70b | 2579 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2580 | |
2581 | /* Train 2 */ | |
5eddb70b CW |
2582 | reg = FDI_TX_CTL(pipe); |
2583 | temp = I915_READ(reg); | |
8db9d77b ZW |
2584 | temp &= ~FDI_LINK_TRAIN_NONE; |
2585 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2586 | if (IS_GEN6(dev)) { | |
2587 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2588 | /* SNB-B */ | |
2589 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2590 | } | |
5eddb70b | 2591 | I915_WRITE(reg, temp); |
8db9d77b | 2592 | |
5eddb70b CW |
2593 | reg = FDI_RX_CTL(pipe); |
2594 | temp = I915_READ(reg); | |
8db9d77b ZW |
2595 | if (HAS_PCH_CPT(dev)) { |
2596 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2597 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2598 | } else { | |
2599 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2600 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2601 | } | |
5eddb70b CW |
2602 | I915_WRITE(reg, temp); |
2603 | ||
2604 | POSTING_READ(reg); | |
8db9d77b ZW |
2605 | udelay(150); |
2606 | ||
0206e353 | 2607 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2608 | reg = FDI_TX_CTL(pipe); |
2609 | temp = I915_READ(reg); | |
8db9d77b ZW |
2610 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2611 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2612 | I915_WRITE(reg, temp); |
2613 | ||
2614 | POSTING_READ(reg); | |
8db9d77b ZW |
2615 | udelay(500); |
2616 | ||
fa37d39e SP |
2617 | for (retry = 0; retry < 5; retry++) { |
2618 | reg = FDI_RX_IIR(pipe); | |
2619 | temp = I915_READ(reg); | |
2620 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2621 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2622 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2623 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2624 | break; | |
2625 | } | |
2626 | udelay(50); | |
8db9d77b | 2627 | } |
fa37d39e SP |
2628 | if (retry < 5) |
2629 | break; | |
8db9d77b ZW |
2630 | } |
2631 | if (i == 4) | |
5eddb70b | 2632 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2633 | |
2634 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2635 | } | |
2636 | ||
357555c0 JB |
2637 | /* Manual link training for Ivy Bridge A0 parts */ |
2638 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2639 | { | |
2640 | struct drm_device *dev = crtc->dev; | |
2641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2642 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2643 | int pipe = intel_crtc->pipe; | |
139ccd3f | 2644 | u32 reg, temp, i, j; |
357555c0 JB |
2645 | |
2646 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2647 | for train result */ | |
2648 | reg = FDI_RX_IMR(pipe); | |
2649 | temp = I915_READ(reg); | |
2650 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2651 | temp &= ~FDI_RX_BIT_LOCK; | |
2652 | I915_WRITE(reg, temp); | |
2653 | ||
2654 | POSTING_READ(reg); | |
2655 | udelay(150); | |
2656 | ||
01a415fd DV |
2657 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
2658 | I915_READ(FDI_RX_IIR(pipe))); | |
2659 | ||
139ccd3f JB |
2660 | /* Try each vswing and preemphasis setting twice before moving on */ |
2661 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
2662 | /* disable first in case we need to retry */ | |
2663 | reg = FDI_TX_CTL(pipe); | |
2664 | temp = I915_READ(reg); | |
2665 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2666 | temp &= ~FDI_TX_ENABLE; | |
2667 | I915_WRITE(reg, temp); | |
357555c0 | 2668 | |
139ccd3f JB |
2669 | reg = FDI_RX_CTL(pipe); |
2670 | temp = I915_READ(reg); | |
2671 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2672 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2673 | temp &= ~FDI_RX_ENABLE; | |
2674 | I915_WRITE(reg, temp); | |
357555c0 | 2675 | |
139ccd3f | 2676 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
2677 | reg = FDI_TX_CTL(pipe); |
2678 | temp = I915_READ(reg); | |
139ccd3f JB |
2679 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2680 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
2681 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 2682 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
2683 | temp |= snb_b_fdi_train_param[j/2]; |
2684 | temp |= FDI_COMPOSITE_SYNC; | |
2685 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 2686 | |
139ccd3f JB |
2687 | I915_WRITE(FDI_RX_MISC(pipe), |
2688 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 2689 | |
139ccd3f | 2690 | reg = FDI_RX_CTL(pipe); |
357555c0 | 2691 | temp = I915_READ(reg); |
139ccd3f JB |
2692 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
2693 | temp |= FDI_COMPOSITE_SYNC; | |
2694 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 2695 | |
139ccd3f JB |
2696 | POSTING_READ(reg); |
2697 | udelay(1); /* should be 0.5us */ | |
357555c0 | 2698 | |
139ccd3f JB |
2699 | for (i = 0; i < 4; i++) { |
2700 | reg = FDI_RX_IIR(pipe); | |
2701 | temp = I915_READ(reg); | |
2702 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2703 | |
139ccd3f JB |
2704 | if (temp & FDI_RX_BIT_LOCK || |
2705 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2706 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2707 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
2708 | i); | |
2709 | break; | |
2710 | } | |
2711 | udelay(1); /* should be 0.5us */ | |
2712 | } | |
2713 | if (i == 4) { | |
2714 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
2715 | continue; | |
2716 | } | |
357555c0 | 2717 | |
139ccd3f | 2718 | /* Train 2 */ |
357555c0 JB |
2719 | reg = FDI_TX_CTL(pipe); |
2720 | temp = I915_READ(reg); | |
139ccd3f JB |
2721 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2722 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2723 | I915_WRITE(reg, temp); | |
2724 | ||
2725 | reg = FDI_RX_CTL(pipe); | |
2726 | temp = I915_READ(reg); | |
2727 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2728 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
2729 | I915_WRITE(reg, temp); |
2730 | ||
2731 | POSTING_READ(reg); | |
139ccd3f | 2732 | udelay(2); /* should be 1.5us */ |
357555c0 | 2733 | |
139ccd3f JB |
2734 | for (i = 0; i < 4; i++) { |
2735 | reg = FDI_RX_IIR(pipe); | |
2736 | temp = I915_READ(reg); | |
2737 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 2738 | |
139ccd3f JB |
2739 | if (temp & FDI_RX_SYMBOL_LOCK || |
2740 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
2741 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2742 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
2743 | i); | |
2744 | goto train_done; | |
2745 | } | |
2746 | udelay(2); /* should be 1.5us */ | |
357555c0 | 2747 | } |
139ccd3f JB |
2748 | if (i == 4) |
2749 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 2750 | } |
357555c0 | 2751 | |
139ccd3f | 2752 | train_done: |
357555c0 JB |
2753 | DRM_DEBUG_KMS("FDI train done.\n"); |
2754 | } | |
2755 | ||
88cefb6c | 2756 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 2757 | { |
88cefb6c | 2758 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 2759 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 2760 | int pipe = intel_crtc->pipe; |
5eddb70b | 2761 | u32 reg, temp; |
79e53945 | 2762 | |
c64e311e | 2763 | |
c98e9dcf | 2764 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2765 | reg = FDI_RX_CTL(pipe); |
2766 | temp = I915_READ(reg); | |
627eb5a3 DV |
2767 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
2768 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 2769 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
2770 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
2771 | ||
2772 | POSTING_READ(reg); | |
c98e9dcf JB |
2773 | udelay(200); |
2774 | ||
2775 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2776 | temp = I915_READ(reg); |
2777 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2778 | ||
2779 | POSTING_READ(reg); | |
c98e9dcf JB |
2780 | udelay(200); |
2781 | ||
20749730 PZ |
2782 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
2783 | reg = FDI_TX_CTL(pipe); | |
2784 | temp = I915_READ(reg); | |
2785 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
2786 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 2787 | |
20749730 PZ |
2788 | POSTING_READ(reg); |
2789 | udelay(100); | |
6be4a607 | 2790 | } |
0e23b99d JB |
2791 | } |
2792 | ||
88cefb6c DV |
2793 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
2794 | { | |
2795 | struct drm_device *dev = intel_crtc->base.dev; | |
2796 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2797 | int pipe = intel_crtc->pipe; | |
2798 | u32 reg, temp; | |
2799 | ||
2800 | /* Switch from PCDclk to Rawclk */ | |
2801 | reg = FDI_RX_CTL(pipe); | |
2802 | temp = I915_READ(reg); | |
2803 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
2804 | ||
2805 | /* Disable CPU FDI TX PLL */ | |
2806 | reg = FDI_TX_CTL(pipe); | |
2807 | temp = I915_READ(reg); | |
2808 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
2809 | ||
2810 | POSTING_READ(reg); | |
2811 | udelay(100); | |
2812 | ||
2813 | reg = FDI_RX_CTL(pipe); | |
2814 | temp = I915_READ(reg); | |
2815 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2816 | ||
2817 | /* Wait for the clocks to turn off. */ | |
2818 | POSTING_READ(reg); | |
2819 | udelay(100); | |
2820 | } | |
2821 | ||
0fc932b8 JB |
2822 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2823 | { | |
2824 | struct drm_device *dev = crtc->dev; | |
2825 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2826 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2827 | int pipe = intel_crtc->pipe; | |
2828 | u32 reg, temp; | |
2829 | ||
2830 | /* disable CPU FDI tx and PCH FDI rx */ | |
2831 | reg = FDI_TX_CTL(pipe); | |
2832 | temp = I915_READ(reg); | |
2833 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2834 | POSTING_READ(reg); | |
2835 | ||
2836 | reg = FDI_RX_CTL(pipe); | |
2837 | temp = I915_READ(reg); | |
2838 | temp &= ~(0x7 << 16); | |
dfd07d72 | 2839 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2840 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
2841 | ||
2842 | POSTING_READ(reg); | |
2843 | udelay(100); | |
2844 | ||
2845 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2846 | if (HAS_PCH_IBX(dev)) { |
2847 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
6f06ce18 | 2848 | } |
0fc932b8 JB |
2849 | |
2850 | /* still set train pattern 1 */ | |
2851 | reg = FDI_TX_CTL(pipe); | |
2852 | temp = I915_READ(reg); | |
2853 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2854 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2855 | I915_WRITE(reg, temp); | |
2856 | ||
2857 | reg = FDI_RX_CTL(pipe); | |
2858 | temp = I915_READ(reg); | |
2859 | if (HAS_PCH_CPT(dev)) { | |
2860 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2861 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2862 | } else { | |
2863 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2864 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2865 | } | |
2866 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2867 | temp &= ~(0x07 << 16); | |
dfd07d72 | 2868 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
2869 | I915_WRITE(reg, temp); |
2870 | ||
2871 | POSTING_READ(reg); | |
2872 | udelay(100); | |
2873 | } | |
2874 | ||
5bb61643 CW |
2875 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2876 | { | |
2877 | struct drm_device *dev = crtc->dev; | |
2878 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10d83730 | 2879 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5bb61643 CW |
2880 | unsigned long flags; |
2881 | bool pending; | |
2882 | ||
10d83730 VS |
2883 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
2884 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
5bb61643 CW |
2885 | return false; |
2886 | ||
2887 | spin_lock_irqsave(&dev->event_lock, flags); | |
2888 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2889 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2890 | ||
2891 | return pending; | |
2892 | } | |
2893 | ||
e6c3a2a6 CW |
2894 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2895 | { | |
0f91128d | 2896 | struct drm_device *dev = crtc->dev; |
5bb61643 | 2897 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 CW |
2898 | |
2899 | if (crtc->fb == NULL) | |
2900 | return; | |
2901 | ||
2c10d571 DV |
2902 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
2903 | ||
5bb61643 CW |
2904 | wait_event(dev_priv->pending_flip_queue, |
2905 | !intel_crtc_has_pending_flip(crtc)); | |
2906 | ||
0f91128d CW |
2907 | mutex_lock(&dev->struct_mutex); |
2908 | intel_finish_fb(crtc->fb); | |
2909 | mutex_unlock(&dev->struct_mutex); | |
e6c3a2a6 CW |
2910 | } |
2911 | ||
e615efe4 ED |
2912 | /* Program iCLKIP clock to the desired frequency */ |
2913 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
2914 | { | |
2915 | struct drm_device *dev = crtc->dev; | |
2916 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12d7ceed | 2917 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.clock; |
e615efe4 ED |
2918 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
2919 | u32 temp; | |
2920 | ||
09153000 DV |
2921 | mutex_lock(&dev_priv->dpio_lock); |
2922 | ||
e615efe4 ED |
2923 | /* It is necessary to ungate the pixclk gate prior to programming |
2924 | * the divisors, and gate it back when it is done. | |
2925 | */ | |
2926 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
2927 | ||
2928 | /* Disable SSCCTL */ | |
2929 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
2930 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
2931 | SBI_SSCCTL_DISABLE, | |
2932 | SBI_ICLK); | |
e615efe4 ED |
2933 | |
2934 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 2935 | if (clock == 20000) { |
e615efe4 ED |
2936 | auxdiv = 1; |
2937 | divsel = 0x41; | |
2938 | phaseinc = 0x20; | |
2939 | } else { | |
2940 | /* The iCLK virtual clock root frequency is in MHz, | |
12d7ceed | 2941 | * but the adjusted_mode->clock in in KHz. To get the divisors, |
e615efe4 ED |
2942 | * it is necessary to divide one by another, so we |
2943 | * convert the virtual clock precision to KHz here for higher | |
2944 | * precision. | |
2945 | */ | |
2946 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
2947 | u32 iclk_pi_range = 64; | |
2948 | u32 desired_divisor, msb_divisor_value, pi_value; | |
2949 | ||
12d7ceed | 2950 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
2951 | msb_divisor_value = desired_divisor / iclk_pi_range; |
2952 | pi_value = desired_divisor % iclk_pi_range; | |
2953 | ||
2954 | auxdiv = 0; | |
2955 | divsel = msb_divisor_value - 2; | |
2956 | phaseinc = pi_value; | |
2957 | } | |
2958 | ||
2959 | /* This should not happen with any sane values */ | |
2960 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
2961 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
2962 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
2963 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
2964 | ||
2965 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 2966 | clock, |
e615efe4 ED |
2967 | auxdiv, |
2968 | divsel, | |
2969 | phasedir, | |
2970 | phaseinc); | |
2971 | ||
2972 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 2973 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
2974 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
2975 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
2976 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
2977 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
2978 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
2979 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 2980 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
2981 | |
2982 | /* Program SSCAUXDIV */ | |
988d6ee8 | 2983 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
2984 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
2985 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 2986 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
2987 | |
2988 | /* Enable modulator and associated divider */ | |
988d6ee8 | 2989 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 2990 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 2991 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
2992 | |
2993 | /* Wait for initialization time */ | |
2994 | udelay(24); | |
2995 | ||
2996 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
2997 | |
2998 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
2999 | } |
3000 | ||
275f01b2 DV |
3001 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3002 | enum pipe pch_transcoder) | |
3003 | { | |
3004 | struct drm_device *dev = crtc->base.dev; | |
3005 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3006 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3007 | ||
3008 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3009 | I915_READ(HTOTAL(cpu_transcoder))); | |
3010 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3011 | I915_READ(HBLANK(cpu_transcoder))); | |
3012 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3013 | I915_READ(HSYNC(cpu_transcoder))); | |
3014 | ||
3015 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3016 | I915_READ(VTOTAL(cpu_transcoder))); | |
3017 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3018 | I915_READ(VBLANK(cpu_transcoder))); | |
3019 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3020 | I915_READ(VSYNC(cpu_transcoder))); | |
3021 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3022 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3023 | } | |
3024 | ||
f67a559d JB |
3025 | /* |
3026 | * Enable PCH resources required for PCH ports: | |
3027 | * - PCH PLLs | |
3028 | * - FDI training & RX/TX | |
3029 | * - update transcoder timings | |
3030 | * - DP transcoding bits | |
3031 | * - transcoder | |
3032 | */ | |
3033 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3034 | { |
3035 | struct drm_device *dev = crtc->dev; | |
3036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3037 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3038 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3039 | u32 reg, temp; |
2c07245f | 3040 | |
ab9412ba | 3041 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3042 | |
cd986abb DV |
3043 | /* Write the TU size bits before fdi link training, so that error |
3044 | * detection works. */ | |
3045 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3046 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3047 | ||
c98e9dcf | 3048 | /* For PCH output, training FDI link */ |
674cf967 | 3049 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3050 | |
3ad8a208 DV |
3051 | /* We need to program the right clock selection before writing the pixel |
3052 | * mutliplier into the DPLL. */ | |
303b81e0 | 3053 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3054 | u32 sel; |
4b645f14 | 3055 | |
c98e9dcf | 3056 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3057 | temp |= TRANS_DPLL_ENABLE(pipe); |
3058 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3059 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3060 | temp |= sel; |
3061 | else | |
3062 | temp &= ~sel; | |
c98e9dcf | 3063 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3064 | } |
5eddb70b | 3065 | |
3ad8a208 DV |
3066 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3067 | * transcoder, and we actually should do this to not upset any PCH | |
3068 | * transcoder that already use the clock when we share it. | |
3069 | * | |
3070 | * Note that enable_shared_dpll tries to do the right thing, but | |
3071 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3072 | * the right LVDS enable sequence. */ | |
3073 | ironlake_enable_shared_dpll(intel_crtc); | |
3074 | ||
d9b6cb56 JB |
3075 | /* set transcoder timing, panel must allow it */ |
3076 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3077 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3078 | |
303b81e0 | 3079 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3080 | |
c98e9dcf JB |
3081 | /* For PCH DP, enable TRANS_DP_CTL */ |
3082 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3083 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3084 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3085 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3086 | reg = TRANS_DP_CTL(pipe); |
3087 | temp = I915_READ(reg); | |
3088 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3089 | TRANS_DP_SYNC_MASK | |
3090 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3091 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3092 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3093 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3094 | |
3095 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3096 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3097 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3098 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3099 | |
3100 | switch (intel_trans_dp_port_sel(crtc)) { | |
3101 | case PCH_DP_B: | |
5eddb70b | 3102 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3103 | break; |
3104 | case PCH_DP_C: | |
5eddb70b | 3105 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3106 | break; |
3107 | case PCH_DP_D: | |
5eddb70b | 3108 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3109 | break; |
3110 | default: | |
e95d41e1 | 3111 | BUG(); |
32f9d658 | 3112 | } |
2c07245f | 3113 | |
5eddb70b | 3114 | I915_WRITE(reg, temp); |
6be4a607 | 3115 | } |
b52eb4dc | 3116 | |
b8a4f404 | 3117 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3118 | } |
3119 | ||
1507e5bd PZ |
3120 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3121 | { | |
3122 | struct drm_device *dev = crtc->dev; | |
3123 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3124 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3125 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3126 | |
ab9412ba | 3127 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3128 | |
8c52b5e8 | 3129 | lpt_program_iclkip(crtc); |
1507e5bd | 3130 | |
0540e488 | 3131 | /* Set transcoder timing. */ |
275f01b2 | 3132 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3133 | |
937bb610 | 3134 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3135 | } |
3136 | ||
e2b78267 | 3137 | static void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3138 | { |
e2b78267 | 3139 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3140 | |
3141 | if (pll == NULL) | |
3142 | return; | |
3143 | ||
3144 | if (pll->refcount == 0) { | |
46edb027 | 3145 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3146 | return; |
3147 | } | |
3148 | ||
f4a091c7 DV |
3149 | if (--pll->refcount == 0) { |
3150 | WARN_ON(pll->on); | |
3151 | WARN_ON(pll->active); | |
3152 | } | |
3153 | ||
a43f6e0f | 3154 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3155 | } |
3156 | ||
b89a1d39 | 3157 | static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3158 | { |
e2b78267 DV |
3159 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3160 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3161 | enum intel_dpll_id i; | |
ee7b9f93 | 3162 | |
ee7b9f93 | 3163 | if (pll) { |
46edb027 DV |
3164 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3165 | crtc->base.base.id, pll->name); | |
e2b78267 | 3166 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3167 | } |
3168 | ||
98b6bd99 DV |
3169 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3170 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3171 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3172 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3173 | |
46edb027 DV |
3174 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3175 | crtc->base.base.id, pll->name); | |
98b6bd99 DV |
3176 | |
3177 | goto found; | |
3178 | } | |
3179 | ||
e72f9fbf DV |
3180 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3181 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3182 | |
3183 | /* Only want to check enabled timings first */ | |
3184 | if (pll->refcount == 0) | |
3185 | continue; | |
3186 | ||
b89a1d39 DV |
3187 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3188 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3189 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3190 | crtc->base.base.id, |
46edb027 | 3191 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3192 | |
3193 | goto found; | |
3194 | } | |
3195 | } | |
3196 | ||
3197 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3198 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3199 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3200 | if (pll->refcount == 0) { |
46edb027 DV |
3201 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3202 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3203 | goto found; |
3204 | } | |
3205 | } | |
3206 | ||
3207 | return NULL; | |
3208 | ||
3209 | found: | |
a43f6e0f | 3210 | crtc->config.shared_dpll = i; |
46edb027 DV |
3211 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3212 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3213 | |
cdbd2316 | 3214 | if (pll->active == 0) { |
66e985c0 DV |
3215 | memcpy(&pll->hw_state, &crtc->config.dpll_hw_state, |
3216 | sizeof(pll->hw_state)); | |
3217 | ||
46edb027 | 3218 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); |
cdbd2316 | 3219 | WARN_ON(pll->on); |
e9d6944e | 3220 | assert_shared_dpll_disabled(dev_priv, pll); |
ee7b9f93 | 3221 | |
15bdd4cf | 3222 | pll->mode_set(dev_priv, pll); |
cdbd2316 DV |
3223 | } |
3224 | pll->refcount++; | |
e04c7350 | 3225 | |
ee7b9f93 JB |
3226 | return pll; |
3227 | } | |
3228 | ||
a1520318 | 3229 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3230 | { |
3231 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3232 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3233 | u32 temp; |
3234 | ||
3235 | temp = I915_READ(dslreg); | |
3236 | udelay(500); | |
3237 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3238 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3239 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3240 | } |
3241 | } | |
3242 | ||
b074cec8 JB |
3243 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3244 | { | |
3245 | struct drm_device *dev = crtc->base.dev; | |
3246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3247 | int pipe = crtc->pipe; | |
3248 | ||
fd4daa9c | 3249 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3250 | /* Force use of hard-coded filter coefficients |
3251 | * as some pre-programmed values are broken, | |
3252 | * e.g. x201. | |
3253 | */ | |
3254 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3255 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3256 | PF_PIPE_SEL_IVB(pipe)); | |
3257 | else | |
3258 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3259 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3260 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3261 | } |
3262 | } | |
3263 | ||
bb53d4ae VS |
3264 | static void intel_enable_planes(struct drm_crtc *crtc) |
3265 | { | |
3266 | struct drm_device *dev = crtc->dev; | |
3267 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3268 | struct intel_plane *intel_plane; | |
3269 | ||
3270 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3271 | if (intel_plane->pipe == pipe) | |
3272 | intel_plane_restore(&intel_plane->base); | |
3273 | } | |
3274 | ||
3275 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3276 | { | |
3277 | struct drm_device *dev = crtc->dev; | |
3278 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
3279 | struct intel_plane *intel_plane; | |
3280 | ||
3281 | list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head) | |
3282 | if (intel_plane->pipe == pipe) | |
3283 | intel_plane_disable(&intel_plane->base); | |
3284 | } | |
3285 | ||
f67a559d JB |
3286 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3287 | { | |
3288 | struct drm_device *dev = crtc->dev; | |
3289 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3290 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3291 | struct intel_encoder *encoder; |
f67a559d JB |
3292 | int pipe = intel_crtc->pipe; |
3293 | int plane = intel_crtc->plane; | |
f67a559d | 3294 | |
08a48469 DV |
3295 | WARN_ON(!crtc->enabled); |
3296 | ||
f67a559d JB |
3297 | if (intel_crtc->active) |
3298 | return; | |
3299 | ||
3300 | intel_crtc->active = true; | |
8664281b PZ |
3301 | |
3302 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3303 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
3304 | ||
f6736a1a | 3305 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
3306 | if (encoder->pre_enable) |
3307 | encoder->pre_enable(encoder); | |
f67a559d | 3308 | |
5bfe2ac0 | 3309 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
3310 | /* Note: FDI PLL enabling _must_ be done before we enable the |
3311 | * cpu pipes, hence this is separate from all the other fdi/pch | |
3312 | * enabling. */ | |
88cefb6c | 3313 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
3314 | } else { |
3315 | assert_fdi_tx_disabled(dev_priv, pipe); | |
3316 | assert_fdi_rx_disabled(dev_priv, pipe); | |
3317 | } | |
f67a559d | 3318 | |
b074cec8 | 3319 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 3320 | |
9c54c0dd JB |
3321 | /* |
3322 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3323 | * clocks enabled | |
3324 | */ | |
3325 | intel_crtc_load_lut(crtc); | |
3326 | ||
f37fcc2a | 3327 | intel_update_watermarks(crtc); |
5bfe2ac0 | 3328 | intel_enable_pipe(dev_priv, pipe, |
23538ef1 | 3329 | intel_crtc->config.has_pch_encoder, false); |
f67a559d | 3330 | intel_enable_plane(dev_priv, plane, pipe); |
bb53d4ae | 3331 | intel_enable_planes(crtc); |
5c38d48c | 3332 | intel_crtc_update_cursor(crtc, true); |
f67a559d | 3333 | |
5bfe2ac0 | 3334 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 3335 | ironlake_pch_enable(crtc); |
c98e9dcf | 3336 | |
d1ebd816 | 3337 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3338 | intel_update_fbc(dev); |
d1ebd816 BW |
3339 | mutex_unlock(&dev->struct_mutex); |
3340 | ||
fa5c73b1 DV |
3341 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3342 | encoder->enable(encoder); | |
61b77ddd DV |
3343 | |
3344 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 3345 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 DV |
3346 | |
3347 | /* | |
3348 | * There seems to be a race in PCH platform hw (at least on some | |
3349 | * outputs) where an enabled pipe still completes any pageflip right | |
3350 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3351 | * as the first vblank happend, everything works as expected. Hence just | |
3352 | * wait for one vblank before returning to avoid strange things | |
3353 | * happening. | |
3354 | */ | |
3355 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
6be4a607 JB |
3356 | } |
3357 | ||
42db64ef PZ |
3358 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
3359 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
3360 | { | |
f5adf94e | 3361 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
3362 | } |
3363 | ||
3364 | static void hsw_enable_ips(struct intel_crtc *crtc) | |
3365 | { | |
3366 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
3367 | ||
3368 | if (!crtc->config.ips_enabled) | |
3369 | return; | |
3370 | ||
3371 | /* We can only enable IPS after we enable a plane and wait for a vblank. | |
3372 | * We guarantee that the plane is enabled by calling intel_enable_ips | |
3373 | * only after intel_enable_plane. And intel_enable_plane already waits | |
3374 | * for a vblank, so all we need to do here is to enable the IPS bit. */ | |
3375 | assert_plane_enabled(dev_priv, crtc->plane); | |
3376 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3377 | } | |
3378 | ||
3379 | static void hsw_disable_ips(struct intel_crtc *crtc) | |
3380 | { | |
3381 | struct drm_device *dev = crtc->base.dev; | |
3382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3383 | ||
3384 | if (!crtc->config.ips_enabled) | |
3385 | return; | |
3386 | ||
3387 | assert_plane_enabled(dev_priv, crtc->plane); | |
3388 | I915_WRITE(IPS_CTL, 0); | |
81c12f6e | 3389 | POSTING_READ(IPS_CTL); |
42db64ef PZ |
3390 | |
3391 | /* We need to wait for a vblank before we can disable the plane. */ | |
3392 | intel_wait_for_vblank(dev, crtc->pipe); | |
3393 | } | |
3394 | ||
4f771f10 PZ |
3395 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
3396 | { | |
3397 | struct drm_device *dev = crtc->dev; | |
3398 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3399 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3400 | struct intel_encoder *encoder; | |
3401 | int pipe = intel_crtc->pipe; | |
3402 | int plane = intel_crtc->plane; | |
4f771f10 PZ |
3403 | |
3404 | WARN_ON(!crtc->enabled); | |
3405 | ||
3406 | if (intel_crtc->active) | |
3407 | return; | |
3408 | ||
3409 | intel_crtc->active = true; | |
8664281b PZ |
3410 | |
3411 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
3412 | if (intel_crtc->config.has_pch_encoder) | |
3413 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
3414 | ||
5bfe2ac0 | 3415 | if (intel_crtc->config.has_pch_encoder) |
04945641 | 3416 | dev_priv->display.fdi_link_train(crtc); |
4f771f10 PZ |
3417 | |
3418 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3419 | if (encoder->pre_enable) | |
3420 | encoder->pre_enable(encoder); | |
3421 | ||
1f544388 | 3422 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 3423 | |
b074cec8 | 3424 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
3425 | |
3426 | /* | |
3427 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3428 | * clocks enabled | |
3429 | */ | |
3430 | intel_crtc_load_lut(crtc); | |
3431 | ||
1f544388 | 3432 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 3433 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 3434 | |
f37fcc2a | 3435 | intel_update_watermarks(crtc); |
5bfe2ac0 | 3436 | intel_enable_pipe(dev_priv, pipe, |
23538ef1 | 3437 | intel_crtc->config.has_pch_encoder, false); |
4f771f10 | 3438 | intel_enable_plane(dev_priv, plane, pipe); |
bb53d4ae | 3439 | intel_enable_planes(crtc); |
5c38d48c | 3440 | intel_crtc_update_cursor(crtc, true); |
4f771f10 | 3441 | |
42db64ef PZ |
3442 | hsw_enable_ips(intel_crtc); |
3443 | ||
5bfe2ac0 | 3444 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 3445 | lpt_pch_enable(crtc); |
4f771f10 PZ |
3446 | |
3447 | mutex_lock(&dev->struct_mutex); | |
3448 | intel_update_fbc(dev); | |
3449 | mutex_unlock(&dev->struct_mutex); | |
3450 | ||
8807e55b | 3451 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 3452 | encoder->enable(encoder); |
8807e55b JN |
3453 | intel_opregion_notify_encoder(encoder, true); |
3454 | } | |
4f771f10 | 3455 | |
4f771f10 PZ |
3456 | /* |
3457 | * There seems to be a race in PCH platform hw (at least on some | |
3458 | * outputs) where an enabled pipe still completes any pageflip right | |
3459 | * away (as if the pipe is off) instead of waiting for vblank. As soon | |
3460 | * as the first vblank happend, everything works as expected. Hence just | |
3461 | * wait for one vblank before returning to avoid strange things | |
3462 | * happening. | |
3463 | */ | |
3464 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
3465 | } | |
3466 | ||
3f8dce3a DV |
3467 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
3468 | { | |
3469 | struct drm_device *dev = crtc->base.dev; | |
3470 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3471 | int pipe = crtc->pipe; | |
3472 | ||
3473 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
3474 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 3475 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
3476 | I915_WRITE(PF_CTL(pipe), 0); |
3477 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
3478 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
3479 | } | |
3480 | } | |
3481 | ||
6be4a607 JB |
3482 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
3483 | { | |
3484 | struct drm_device *dev = crtc->dev; | |
3485 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3486 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3487 | struct intel_encoder *encoder; |
6be4a607 JB |
3488 | int pipe = intel_crtc->pipe; |
3489 | int plane = intel_crtc->plane; | |
5eddb70b | 3490 | u32 reg, temp; |
b52eb4dc | 3491 | |
ef9c3aee | 3492 | |
f7abfe8b CW |
3493 | if (!intel_crtc->active) |
3494 | return; | |
3495 | ||
ea9d758d DV |
3496 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3497 | encoder->disable(encoder); | |
3498 | ||
e6c3a2a6 | 3499 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3500 | drm_vblank_off(dev, pipe); |
913d8d11 | 3501 | |
5c3fe8b0 | 3502 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 3503 | intel_disable_fbc(dev); |
2c07245f | 3504 | |
0d5b8c61 | 3505 | intel_crtc_update_cursor(crtc, false); |
bb53d4ae | 3506 | intel_disable_planes(crtc); |
0d5b8c61 VS |
3507 | intel_disable_plane(dev_priv, plane, pipe); |
3508 | ||
d925c59a DV |
3509 | if (intel_crtc->config.has_pch_encoder) |
3510 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
3511 | ||
b24e7179 | 3512 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3513 | |
3f8dce3a | 3514 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 3515 | |
bf49ec8c DV |
3516 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3517 | if (encoder->post_disable) | |
3518 | encoder->post_disable(encoder); | |
2c07245f | 3519 | |
d925c59a DV |
3520 | if (intel_crtc->config.has_pch_encoder) { |
3521 | ironlake_fdi_disable(crtc); | |
913d8d11 | 3522 | |
d925c59a DV |
3523 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
3524 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 3525 | |
d925c59a DV |
3526 | if (HAS_PCH_CPT(dev)) { |
3527 | /* disable TRANS_DP_CTL */ | |
3528 | reg = TRANS_DP_CTL(pipe); | |
3529 | temp = I915_READ(reg); | |
3530 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
3531 | TRANS_DP_PORT_SEL_MASK); | |
3532 | temp |= TRANS_DP_PORT_SEL_NONE; | |
3533 | I915_WRITE(reg, temp); | |
3534 | ||
3535 | /* disable DPLL_SEL */ | |
3536 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 3537 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 3538 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 3539 | } |
e3421a18 | 3540 | |
d925c59a | 3541 | /* disable PCH DPLL */ |
e72f9fbf | 3542 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 3543 | |
d925c59a DV |
3544 | ironlake_fdi_pll_disable(intel_crtc); |
3545 | } | |
6b383a7f | 3546 | |
f7abfe8b | 3547 | intel_crtc->active = false; |
46ba614c | 3548 | intel_update_watermarks(crtc); |
d1ebd816 BW |
3549 | |
3550 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 3551 | intel_update_fbc(dev); |
d1ebd816 | 3552 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3553 | } |
1b3c7a47 | 3554 | |
4f771f10 | 3555 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 3556 | { |
4f771f10 PZ |
3557 | struct drm_device *dev = crtc->dev; |
3558 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 3559 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 PZ |
3560 | struct intel_encoder *encoder; |
3561 | int pipe = intel_crtc->pipe; | |
3562 | int plane = intel_crtc->plane; | |
3b117c8f | 3563 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 3564 | |
4f771f10 PZ |
3565 | if (!intel_crtc->active) |
3566 | return; | |
3567 | ||
8807e55b JN |
3568 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
3569 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 3570 | encoder->disable(encoder); |
8807e55b | 3571 | } |
4f771f10 PZ |
3572 | |
3573 | intel_crtc_wait_for_pending_flips(crtc); | |
3574 | drm_vblank_off(dev, pipe); | |
4f771f10 | 3575 | |
891348b2 | 3576 | /* FBC must be disabled before disabling the plane on HSW. */ |
5c3fe8b0 | 3577 | if (dev_priv->fbc.plane == plane) |
4f771f10 PZ |
3578 | intel_disable_fbc(dev); |
3579 | ||
42db64ef PZ |
3580 | hsw_disable_ips(intel_crtc); |
3581 | ||
0d5b8c61 | 3582 | intel_crtc_update_cursor(crtc, false); |
bb53d4ae | 3583 | intel_disable_planes(crtc); |
891348b2 RV |
3584 | intel_disable_plane(dev_priv, plane, pipe); |
3585 | ||
8664281b PZ |
3586 | if (intel_crtc->config.has_pch_encoder) |
3587 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
4f771f10 PZ |
3588 | intel_disable_pipe(dev_priv, pipe); |
3589 | ||
ad80a810 | 3590 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 3591 | |
3f8dce3a | 3592 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 3593 | |
1f544388 | 3594 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 PZ |
3595 | |
3596 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3597 | if (encoder->post_disable) | |
3598 | encoder->post_disable(encoder); | |
3599 | ||
88adfff1 | 3600 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 3601 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 3602 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 3603 | intel_ddi_fdi_disable(crtc); |
83616634 | 3604 | } |
4f771f10 PZ |
3605 | |
3606 | intel_crtc->active = false; | |
46ba614c | 3607 | intel_update_watermarks(crtc); |
4f771f10 PZ |
3608 | |
3609 | mutex_lock(&dev->struct_mutex); | |
3610 | intel_update_fbc(dev); | |
3611 | mutex_unlock(&dev->struct_mutex); | |
3612 | } | |
3613 | ||
ee7b9f93 JB |
3614 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
3615 | { | |
3616 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 3617 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
3618 | } |
3619 | ||
6441ab5f PZ |
3620 | static void haswell_crtc_off(struct drm_crtc *crtc) |
3621 | { | |
3622 | intel_ddi_put_crtc_pll(crtc); | |
3623 | } | |
3624 | ||
02e792fb DV |
3625 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3626 | { | |
02e792fb | 3627 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3628 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3629 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3630 | |
23f09ce3 | 3631 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3632 | dev_priv->mm.interruptible = false; |
3633 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3634 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3635 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3636 | } |
02e792fb | 3637 | |
5dcdbcb0 CW |
3638 | /* Let userspace switch the overlay on again. In most cases userspace |
3639 | * has to recompute where to put it anyway. | |
3640 | */ | |
02e792fb DV |
3641 | } |
3642 | ||
61bc95c1 EE |
3643 | /** |
3644 | * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware | |
3645 | * cursor plane briefly if not already running after enabling the display | |
3646 | * plane. | |
3647 | * This workaround avoids occasional blank screens when self refresh is | |
3648 | * enabled. | |
3649 | */ | |
3650 | static void | |
3651 | g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe) | |
3652 | { | |
3653 | u32 cntl = I915_READ(CURCNTR(pipe)); | |
3654 | ||
3655 | if ((cntl & CURSOR_MODE) == 0) { | |
3656 | u32 fw_bcl_self = I915_READ(FW_BLC_SELF); | |
3657 | ||
3658 | I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); | |
3659 | I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); | |
3660 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
3661 | I915_WRITE(CURCNTR(pipe), cntl); | |
3662 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3663 | I915_WRITE(FW_BLC_SELF, fw_bcl_self); | |
3664 | } | |
3665 | } | |
3666 | ||
2dd24552 JB |
3667 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
3668 | { | |
3669 | struct drm_device *dev = crtc->base.dev; | |
3670 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3671 | struct intel_crtc_config *pipe_config = &crtc->config; | |
3672 | ||
328d8e82 | 3673 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
3674 | return; |
3675 | ||
2dd24552 | 3676 | /* |
c0b03411 DV |
3677 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
3678 | * according to register description and PRM. | |
2dd24552 | 3679 | */ |
c0b03411 DV |
3680 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
3681 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 3682 | |
b074cec8 JB |
3683 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
3684 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
3685 | |
3686 | /* Border color in case we don't scale up to the full screen. Black by | |
3687 | * default, change to something else for debugging. */ | |
3688 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
3689 | } |
3690 | ||
89b667f8 JB |
3691 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
3692 | { | |
3693 | struct drm_device *dev = crtc->dev; | |
3694 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3695 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3696 | struct intel_encoder *encoder; | |
3697 | int pipe = intel_crtc->pipe; | |
3698 | int plane = intel_crtc->plane; | |
23538ef1 | 3699 | bool is_dsi; |
89b667f8 JB |
3700 | |
3701 | WARN_ON(!crtc->enabled); | |
3702 | ||
3703 | if (intel_crtc->active) | |
3704 | return; | |
3705 | ||
3706 | intel_crtc->active = true; | |
89b667f8 | 3707 | |
89b667f8 JB |
3708 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3709 | if (encoder->pre_pll_enable) | |
3710 | encoder->pre_pll_enable(encoder); | |
3711 | ||
23538ef1 JN |
3712 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
3713 | ||
e9fd1c02 JN |
3714 | if (!is_dsi) |
3715 | vlv_enable_pll(intel_crtc); | |
89b667f8 JB |
3716 | |
3717 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3718 | if (encoder->pre_enable) | |
3719 | encoder->pre_enable(encoder); | |
3720 | ||
2dd24552 JB |
3721 | i9xx_pfit_enable(intel_crtc); |
3722 | ||
63cbb074 VS |
3723 | intel_crtc_load_lut(crtc); |
3724 | ||
f37fcc2a | 3725 | intel_update_watermarks(crtc); |
23538ef1 | 3726 | intel_enable_pipe(dev_priv, pipe, false, is_dsi); |
89b667f8 | 3727 | intel_enable_plane(dev_priv, plane, pipe); |
bb53d4ae | 3728 | intel_enable_planes(crtc); |
5c38d48c | 3729 | intel_crtc_update_cursor(crtc, true); |
89b667f8 | 3730 | |
89b667f8 | 3731 | intel_update_fbc(dev); |
5004945f JN |
3732 | |
3733 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
3734 | encoder->enable(encoder); | |
89b667f8 JB |
3735 | } |
3736 | ||
0b8765c6 | 3737 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
3738 | { |
3739 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
3740 | struct drm_i915_private *dev_priv = dev->dev_private; |
3741 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3742 | struct intel_encoder *encoder; |
79e53945 | 3743 | int pipe = intel_crtc->pipe; |
80824003 | 3744 | int plane = intel_crtc->plane; |
79e53945 | 3745 | |
08a48469 DV |
3746 | WARN_ON(!crtc->enabled); |
3747 | ||
f7abfe8b CW |
3748 | if (intel_crtc->active) |
3749 | return; | |
3750 | ||
3751 | intel_crtc->active = true; | |
6b383a7f | 3752 | |
9d6d9f19 MK |
3753 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3754 | if (encoder->pre_enable) | |
3755 | encoder->pre_enable(encoder); | |
3756 | ||
f6736a1a DV |
3757 | i9xx_enable_pll(intel_crtc); |
3758 | ||
2dd24552 JB |
3759 | i9xx_pfit_enable(intel_crtc); |
3760 | ||
63cbb074 VS |
3761 | intel_crtc_load_lut(crtc); |
3762 | ||
f37fcc2a | 3763 | intel_update_watermarks(crtc); |
23538ef1 | 3764 | intel_enable_pipe(dev_priv, pipe, false, false); |
b24e7179 | 3765 | intel_enable_plane(dev_priv, plane, pipe); |
bb53d4ae | 3766 | intel_enable_planes(crtc); |
22e407d7 | 3767 | /* The fixup needs to happen before cursor is enabled */ |
61bc95c1 EE |
3768 | if (IS_G4X(dev)) |
3769 | g4x_fixup_plane(dev_priv, pipe); | |
22e407d7 | 3770 | intel_crtc_update_cursor(crtc, true); |
79e53945 | 3771 | |
0b8765c6 JB |
3772 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3773 | intel_crtc_dpms_overlay(intel_crtc, true); | |
ef9c3aee | 3774 | |
f440eb13 | 3775 | intel_update_fbc(dev); |
ef9c3aee | 3776 | |
fa5c73b1 DV |
3777 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3778 | encoder->enable(encoder); | |
0b8765c6 | 3779 | } |
79e53945 | 3780 | |
87476d63 DV |
3781 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
3782 | { | |
3783 | struct drm_device *dev = crtc->base.dev; | |
3784 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 3785 | |
328d8e82 DV |
3786 | if (!crtc->config.gmch_pfit.control) |
3787 | return; | |
87476d63 | 3788 | |
328d8e82 | 3789 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 3790 | |
328d8e82 DV |
3791 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
3792 | I915_READ(PFIT_CONTROL)); | |
3793 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
3794 | } |
3795 | ||
0b8765c6 JB |
3796 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3797 | { | |
3798 | struct drm_device *dev = crtc->dev; | |
3799 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3800 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 3801 | struct intel_encoder *encoder; |
0b8765c6 JB |
3802 | int pipe = intel_crtc->pipe; |
3803 | int plane = intel_crtc->plane; | |
ef9c3aee | 3804 | |
f7abfe8b CW |
3805 | if (!intel_crtc->active) |
3806 | return; | |
3807 | ||
ea9d758d DV |
3808 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3809 | encoder->disable(encoder); | |
3810 | ||
0b8765c6 | 3811 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
3812 | intel_crtc_wait_for_pending_flips(crtc); |
3813 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 3814 | |
5c3fe8b0 | 3815 | if (dev_priv->fbc.plane == plane) |
973d04f9 | 3816 | intel_disable_fbc(dev); |
79e53945 | 3817 | |
0d5b8c61 VS |
3818 | intel_crtc_dpms_overlay(intel_crtc, false); |
3819 | intel_crtc_update_cursor(crtc, false); | |
bb53d4ae | 3820 | intel_disable_planes(crtc); |
b24e7179 | 3821 | intel_disable_plane(dev_priv, plane, pipe); |
0d5b8c61 | 3822 | |
b24e7179 | 3823 | intel_disable_pipe(dev_priv, pipe); |
24a1f16d | 3824 | |
87476d63 | 3825 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 3826 | |
89b667f8 JB |
3827 | for_each_encoder_on_crtc(dev, crtc, encoder) |
3828 | if (encoder->post_disable) | |
3829 | encoder->post_disable(encoder); | |
3830 | ||
e9fd1c02 JN |
3831 | if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
3832 | i9xx_disable_pll(dev_priv, pipe); | |
0b8765c6 | 3833 | |
f7abfe8b | 3834 | intel_crtc->active = false; |
46ba614c | 3835 | intel_update_watermarks(crtc); |
f37fcc2a | 3836 | |
6b383a7f | 3837 | intel_update_fbc(dev); |
0b8765c6 JB |
3838 | } |
3839 | ||
ee7b9f93 JB |
3840 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
3841 | { | |
3842 | } | |
3843 | ||
976f8a20 DV |
3844 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
3845 | bool enabled) | |
2c07245f ZW |
3846 | { |
3847 | struct drm_device *dev = crtc->dev; | |
3848 | struct drm_i915_master_private *master_priv; | |
3849 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3850 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
3851 | |
3852 | if (!dev->primary->master) | |
3853 | return; | |
3854 | ||
3855 | master_priv = dev->primary->master->driver_priv; | |
3856 | if (!master_priv->sarea_priv) | |
3857 | return; | |
3858 | ||
79e53945 JB |
3859 | switch (pipe) { |
3860 | case 0: | |
3861 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
3862 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
3863 | break; | |
3864 | case 1: | |
3865 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
3866 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
3867 | break; | |
3868 | default: | |
9db4a9c7 | 3869 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
3870 | break; |
3871 | } | |
79e53945 JB |
3872 | } |
3873 | ||
976f8a20 DV |
3874 | /** |
3875 | * Sets the power management mode of the pipe and plane. | |
3876 | */ | |
3877 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
3878 | { | |
3879 | struct drm_device *dev = crtc->dev; | |
3880 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3881 | struct intel_encoder *intel_encoder; | |
3882 | bool enable = false; | |
3883 | ||
3884 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
3885 | enable |= intel_encoder->connectors_active; | |
3886 | ||
3887 | if (enable) | |
3888 | dev_priv->display.crtc_enable(crtc); | |
3889 | else | |
3890 | dev_priv->display.crtc_disable(crtc); | |
3891 | ||
3892 | intel_crtc_update_sarea(crtc, enable); | |
3893 | } | |
3894 | ||
cdd59983 CW |
3895 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3896 | { | |
cdd59983 | 3897 | struct drm_device *dev = crtc->dev; |
976f8a20 | 3898 | struct drm_connector *connector; |
ee7b9f93 | 3899 | struct drm_i915_private *dev_priv = dev->dev_private; |
7b9f35a6 | 3900 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cdd59983 | 3901 | |
976f8a20 DV |
3902 | /* crtc should still be enabled when we disable it. */ |
3903 | WARN_ON(!crtc->enabled); | |
3904 | ||
3905 | dev_priv->display.crtc_disable(crtc); | |
c77bf565 | 3906 | intel_crtc->eld_vld = false; |
976f8a20 | 3907 | intel_crtc_update_sarea(crtc, false); |
ee7b9f93 JB |
3908 | dev_priv->display.off(crtc); |
3909 | ||
931872fc | 3910 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
93ce0ba6 | 3911 | assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
931872fc | 3912 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); |
cdd59983 CW |
3913 | |
3914 | if (crtc->fb) { | |
3915 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 3916 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 | 3917 | mutex_unlock(&dev->struct_mutex); |
976f8a20 DV |
3918 | crtc->fb = NULL; |
3919 | } | |
3920 | ||
3921 | /* Update computed state. */ | |
3922 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
3923 | if (!connector->encoder || !connector->encoder->crtc) | |
3924 | continue; | |
3925 | ||
3926 | if (connector->encoder->crtc != crtc) | |
3927 | continue; | |
3928 | ||
3929 | connector->dpms = DRM_MODE_DPMS_OFF; | |
3930 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
3931 | } |
3932 | } | |
3933 | ||
ea5b213a | 3934 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 3935 | { |
4ef69c7a | 3936 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 3937 | |
ea5b213a CW |
3938 | drm_encoder_cleanup(encoder); |
3939 | kfree(intel_encoder); | |
7e7d76c3 JB |
3940 | } |
3941 | ||
9237329d | 3942 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
3943 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
3944 | * state of the entire output pipe. */ | |
9237329d | 3945 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 3946 | { |
5ab432ef DV |
3947 | if (mode == DRM_MODE_DPMS_ON) { |
3948 | encoder->connectors_active = true; | |
3949 | ||
b2cabb0e | 3950 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
3951 | } else { |
3952 | encoder->connectors_active = false; | |
3953 | ||
b2cabb0e | 3954 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 3955 | } |
79e53945 JB |
3956 | } |
3957 | ||
0a91ca29 DV |
3958 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
3959 | * internal consistency). */ | |
b980514c | 3960 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 3961 | { |
0a91ca29 DV |
3962 | if (connector->get_hw_state(connector)) { |
3963 | struct intel_encoder *encoder = connector->encoder; | |
3964 | struct drm_crtc *crtc; | |
3965 | bool encoder_enabled; | |
3966 | enum pipe pipe; | |
3967 | ||
3968 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
3969 | connector->base.base.id, | |
3970 | drm_get_connector_name(&connector->base)); | |
3971 | ||
3972 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, | |
3973 | "wrong connector dpms state\n"); | |
3974 | WARN(connector->base.encoder != &encoder->base, | |
3975 | "active connector not linked to encoder\n"); | |
3976 | WARN(!encoder->connectors_active, | |
3977 | "encoder->connectors_active not set\n"); | |
3978 | ||
3979 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
3980 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
3981 | if (WARN_ON(!encoder->base.crtc)) | |
3982 | return; | |
3983 | ||
3984 | crtc = encoder->base.crtc; | |
3985 | ||
3986 | WARN(!crtc->enabled, "crtc not enabled\n"); | |
3987 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
3988 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
3989 | "encoder active on the wrong pipe\n"); | |
3990 | } | |
79e53945 JB |
3991 | } |
3992 | ||
5ab432ef DV |
3993 | /* Even simpler default implementation, if there's really no special case to |
3994 | * consider. */ | |
3995 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 3996 | { |
5ab432ef | 3997 | struct intel_encoder *encoder = intel_attached_encoder(connector); |
d4270e57 | 3998 | |
5ab432ef DV |
3999 | /* All the simple cases only support two dpms states. */ |
4000 | if (mode != DRM_MODE_DPMS_ON) | |
4001 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 4002 | |
5ab432ef DV |
4003 | if (mode == connector->dpms) |
4004 | return; | |
4005 | ||
4006 | connector->dpms = mode; | |
4007 | ||
4008 | /* Only need to change hw state when actually enabled */ | |
4009 | if (encoder->base.crtc) | |
4010 | intel_encoder_dpms(encoder, mode); | |
4011 | else | |
8af6cf88 | 4012 | WARN_ON(encoder->connectors_active != false); |
0a91ca29 | 4013 | |
b980514c | 4014 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
4015 | } |
4016 | ||
f0947c37 DV |
4017 | /* Simple connector->get_hw_state implementation for encoders that support only |
4018 | * one connector and no cloning and hence the encoder state determines the state | |
4019 | * of the connector. */ | |
4020 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 4021 | { |
24929352 | 4022 | enum pipe pipe = 0; |
f0947c37 | 4023 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 4024 | |
f0947c37 | 4025 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
4026 | } |
4027 | ||
1857e1da DV |
4028 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
4029 | struct intel_crtc_config *pipe_config) | |
4030 | { | |
4031 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4032 | struct intel_crtc *pipe_B_crtc = | |
4033 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
4034 | ||
4035 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
4036 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4037 | if (pipe_config->fdi_lanes > 4) { | |
4038 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
4039 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4040 | return false; | |
4041 | } | |
4042 | ||
4043 | if (IS_HASWELL(dev)) { | |
4044 | if (pipe_config->fdi_lanes > 2) { | |
4045 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
4046 | pipe_config->fdi_lanes); | |
4047 | return false; | |
4048 | } else { | |
4049 | return true; | |
4050 | } | |
4051 | } | |
4052 | ||
4053 | if (INTEL_INFO(dev)->num_pipes == 2) | |
4054 | return true; | |
4055 | ||
4056 | /* Ivybridge 3 pipe is really complicated */ | |
4057 | switch (pipe) { | |
4058 | case PIPE_A: | |
4059 | return true; | |
4060 | case PIPE_B: | |
4061 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
4062 | pipe_config->fdi_lanes > 2) { | |
4063 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4064 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4065 | return false; | |
4066 | } | |
4067 | return true; | |
4068 | case PIPE_C: | |
1e833f40 | 4069 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
4070 | pipe_B_crtc->config.fdi_lanes <= 2) { |
4071 | if (pipe_config->fdi_lanes > 2) { | |
4072 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
4073 | pipe_name(pipe), pipe_config->fdi_lanes); | |
4074 | return false; | |
4075 | } | |
4076 | } else { | |
4077 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
4078 | return false; | |
4079 | } | |
4080 | return true; | |
4081 | default: | |
4082 | BUG(); | |
4083 | } | |
4084 | } | |
4085 | ||
e29c22c0 DV |
4086 | #define RETRY 1 |
4087 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
4088 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 4089 | { |
1857e1da | 4090 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 4091 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 4092 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 4093 | bool setup_ok, needs_recompute = false; |
877d48d5 | 4094 | |
e29c22c0 | 4095 | retry: |
877d48d5 DV |
4096 | /* FDI is a binary signal running at ~2.7GHz, encoding |
4097 | * each output octet as 10 bits. The actual frequency | |
4098 | * is stored as a divider into a 100MHz clock, and the | |
4099 | * mode pixel clock is stored in units of 1KHz. | |
4100 | * Hence the bw of each lane in terms of the mode signal | |
4101 | * is: | |
4102 | */ | |
4103 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
4104 | ||
ff9a6750 | 4105 | fdi_dotclock = adjusted_mode->clock; |
877d48d5 | 4106 | |
2bd89a07 | 4107 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
4108 | pipe_config->pipe_bpp); |
4109 | ||
4110 | pipe_config->fdi_lanes = lane; | |
4111 | ||
2bd89a07 | 4112 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 4113 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 4114 | |
e29c22c0 DV |
4115 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
4116 | intel_crtc->pipe, pipe_config); | |
4117 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
4118 | pipe_config->pipe_bpp -= 2*3; | |
4119 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
4120 | pipe_config->pipe_bpp); | |
4121 | needs_recompute = true; | |
4122 | pipe_config->bw_constrained = true; | |
4123 | ||
4124 | goto retry; | |
4125 | } | |
4126 | ||
4127 | if (needs_recompute) | |
4128 | return RETRY; | |
4129 | ||
4130 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
4131 | } |
4132 | ||
42db64ef PZ |
4133 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
4134 | struct intel_crtc_config *pipe_config) | |
4135 | { | |
3c4ca58c PZ |
4136 | pipe_config->ips_enabled = i915_enable_ips && |
4137 | hsw_crtc_supports_ips(crtc) && | |
b6dfdc9b | 4138 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
4139 | } |
4140 | ||
a43f6e0f | 4141 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 4142 | struct intel_crtc_config *pipe_config) |
79e53945 | 4143 | { |
a43f6e0f | 4144 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 4145 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 4146 | |
ad3a4479 | 4147 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
4148 | if (INTEL_INFO(dev)->gen < 4) { |
4149 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4150 | int clock_limit = | |
4151 | dev_priv->display.get_display_clock_speed(dev); | |
4152 | ||
4153 | /* | |
4154 | * Enable pixel doubling when the dot clock | |
4155 | * is > 90% of the (display) core speed. | |
4156 | * | |
b397c96b VS |
4157 | * GDG double wide on either pipe, |
4158 | * otherwise pipe A only. | |
cf532bb2 | 4159 | */ |
b397c96b | 4160 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
ad3a4479 VS |
4161 | adjusted_mode->clock > clock_limit * 9 / 10) { |
4162 | clock_limit *= 2; | |
cf532bb2 | 4163 | pipe_config->double_wide = true; |
ad3a4479 VS |
4164 | } |
4165 | ||
4166 | if (adjusted_mode->clock > clock_limit * 9 / 10) | |
e29c22c0 | 4167 | return -EINVAL; |
2c07245f | 4168 | } |
89749350 | 4169 | |
1d1d0e27 VS |
4170 | /* |
4171 | * Pipe horizontal size must be even in: | |
4172 | * - DVO ganged mode | |
4173 | * - LVDS dual channel mode | |
4174 | * - Double wide pipe | |
4175 | */ | |
4176 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
4177 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
4178 | pipe_config->pipe_src_w &= ~1; | |
4179 | ||
8693a824 DL |
4180 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
4181 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
4182 | */ |
4183 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
4184 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 4185 | return -EINVAL; |
44f46b42 | 4186 | |
bd080ee5 | 4187 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 4188 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 4189 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
4190 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
4191 | * for lvds. */ | |
4192 | pipe_config->pipe_bpp = 8*3; | |
4193 | } | |
4194 | ||
f5adf94e | 4195 | if (HAS_IPS(dev)) |
a43f6e0f DV |
4196 | hsw_compute_ips_config(crtc, pipe_config); |
4197 | ||
4198 | /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old | |
4199 | * clock survives for now. */ | |
4200 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
4201 | pipe_config->shared_dpll = crtc->config.shared_dpll; | |
42db64ef | 4202 | |
877d48d5 | 4203 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 4204 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 4205 | |
e29c22c0 | 4206 | return 0; |
79e53945 JB |
4207 | } |
4208 | ||
25eb05fc JB |
4209 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
4210 | { | |
4211 | return 400000; /* FIXME */ | |
4212 | } | |
4213 | ||
e70236a8 JB |
4214 | static int i945_get_display_clock_speed(struct drm_device *dev) |
4215 | { | |
4216 | return 400000; | |
4217 | } | |
79e53945 | 4218 | |
e70236a8 | 4219 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 4220 | { |
e70236a8 JB |
4221 | return 333000; |
4222 | } | |
79e53945 | 4223 | |
e70236a8 JB |
4224 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
4225 | { | |
4226 | return 200000; | |
4227 | } | |
79e53945 | 4228 | |
257a7ffc DV |
4229 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
4230 | { | |
4231 | u16 gcfgc = 0; | |
4232 | ||
4233 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
4234 | ||
4235 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4236 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
4237 | return 267000; | |
4238 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
4239 | return 333000; | |
4240 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
4241 | return 444000; | |
4242 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
4243 | return 200000; | |
4244 | default: | |
4245 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
4246 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
4247 | return 133000; | |
4248 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
4249 | return 167000; | |
4250 | } | |
4251 | } | |
4252 | ||
e70236a8 JB |
4253 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
4254 | { | |
4255 | u16 gcfgc = 0; | |
79e53945 | 4256 | |
e70236a8 JB |
4257 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
4258 | ||
4259 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
4260 | return 133000; | |
4261 | else { | |
4262 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
4263 | case GC_DISPLAY_CLOCK_333_MHZ: | |
4264 | return 333000; | |
4265 | default: | |
4266 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
4267 | return 190000; | |
79e53945 | 4268 | } |
e70236a8 JB |
4269 | } |
4270 | } | |
4271 | ||
4272 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
4273 | { | |
4274 | return 266000; | |
4275 | } | |
4276 | ||
4277 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
4278 | { | |
4279 | u16 hpllcc = 0; | |
4280 | /* Assume that the hardware is in the high speed state. This | |
4281 | * should be the default. | |
4282 | */ | |
4283 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
4284 | case GC_CLOCK_133_200: | |
4285 | case GC_CLOCK_100_200: | |
4286 | return 200000; | |
4287 | case GC_CLOCK_166_250: | |
4288 | return 250000; | |
4289 | case GC_CLOCK_100_133: | |
79e53945 | 4290 | return 133000; |
e70236a8 | 4291 | } |
79e53945 | 4292 | |
e70236a8 JB |
4293 | /* Shouldn't happen */ |
4294 | return 0; | |
4295 | } | |
79e53945 | 4296 | |
e70236a8 JB |
4297 | static int i830_get_display_clock_speed(struct drm_device *dev) |
4298 | { | |
4299 | return 133000; | |
79e53945 JB |
4300 | } |
4301 | ||
2c07245f | 4302 | static void |
a65851af | 4303 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 4304 | { |
a65851af VS |
4305 | while (*num > DATA_LINK_M_N_MASK || |
4306 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
4307 | *num >>= 1; |
4308 | *den >>= 1; | |
4309 | } | |
4310 | } | |
4311 | ||
a65851af VS |
4312 | static void compute_m_n(unsigned int m, unsigned int n, |
4313 | uint32_t *ret_m, uint32_t *ret_n) | |
4314 | { | |
4315 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
4316 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
4317 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
4318 | } | |
4319 | ||
e69d0bc1 DV |
4320 | void |
4321 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
4322 | int pixel_clock, int link_clock, | |
4323 | struct intel_link_m_n *m_n) | |
2c07245f | 4324 | { |
e69d0bc1 | 4325 | m_n->tu = 64; |
a65851af VS |
4326 | |
4327 | compute_m_n(bits_per_pixel * pixel_clock, | |
4328 | link_clock * nlanes * 8, | |
4329 | &m_n->gmch_m, &m_n->gmch_n); | |
4330 | ||
4331 | compute_m_n(pixel_clock, link_clock, | |
4332 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
4333 | } |
4334 | ||
a7615030 CW |
4335 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4336 | { | |
72bbe58c KP |
4337 | if (i915_panel_use_ssc >= 0) |
4338 | return i915_panel_use_ssc != 0; | |
41aa3448 | 4339 | return dev_priv->vbt.lvds_use_ssc |
435793df | 4340 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
4341 | } |
4342 | ||
c65d77d8 JB |
4343 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
4344 | { | |
4345 | struct drm_device *dev = crtc->dev; | |
4346 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4347 | int refclk; | |
4348 | ||
a0c4da24 | 4349 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 4350 | refclk = 100000; |
a0c4da24 | 4351 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 4352 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
41aa3448 | 4353 | refclk = dev_priv->vbt.lvds_ssc_freq * 1000; |
c65d77d8 JB |
4354 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", |
4355 | refclk / 1000); | |
4356 | } else if (!IS_GEN2(dev)) { | |
4357 | refclk = 96000; | |
4358 | } else { | |
4359 | refclk = 48000; | |
4360 | } | |
4361 | ||
4362 | return refclk; | |
4363 | } | |
4364 | ||
7429e9d4 | 4365 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 4366 | { |
7df00d7a | 4367 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 4368 | } |
f47709a9 | 4369 | |
7429e9d4 DV |
4370 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
4371 | { | |
4372 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
4373 | } |
4374 | ||
f47709a9 | 4375 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
4376 | intel_clock_t *reduced_clock) |
4377 | { | |
f47709a9 | 4378 | struct drm_device *dev = crtc->base.dev; |
a7516a05 | 4379 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4380 | int pipe = crtc->pipe; |
a7516a05 JB |
4381 | u32 fp, fp2 = 0; |
4382 | ||
4383 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 4384 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4385 | if (reduced_clock) |
7429e9d4 | 4386 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 4387 | } else { |
7429e9d4 | 4388 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 4389 | if (reduced_clock) |
7429e9d4 | 4390 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
4391 | } |
4392 | ||
4393 | I915_WRITE(FP0(pipe), fp); | |
8bcc2795 | 4394 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 4395 | |
f47709a9 DV |
4396 | crtc->lowfreq_avail = false; |
4397 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
a7516a05 JB |
4398 | reduced_clock && i915_powersave) { |
4399 | I915_WRITE(FP1(pipe), fp2); | |
8bcc2795 | 4400 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 4401 | crtc->lowfreq_avail = true; |
a7516a05 JB |
4402 | } else { |
4403 | I915_WRITE(FP1(pipe), fp); | |
8bcc2795 | 4404 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
4405 | } |
4406 | } | |
4407 | ||
5e69f97f CML |
4408 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
4409 | pipe) | |
89b667f8 JB |
4410 | { |
4411 | u32 reg_val; | |
4412 | ||
4413 | /* | |
4414 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
4415 | * and set it to a reasonable value instead. | |
4416 | */ | |
5e69f97f | 4417 | reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1)); |
89b667f8 JB |
4418 | reg_val &= 0xffffff00; |
4419 | reg_val |= 0x00000030; | |
5e69f97f | 4420 | vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val); |
89b667f8 | 4421 | |
5e69f97f | 4422 | reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION); |
89b667f8 JB |
4423 | reg_val &= 0x8cffffff; |
4424 | reg_val = 0x8c000000; | |
5e69f97f | 4425 | vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val); |
89b667f8 | 4426 | |
5e69f97f | 4427 | reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1)); |
89b667f8 | 4428 | reg_val &= 0xffffff00; |
5e69f97f | 4429 | vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val); |
89b667f8 | 4430 | |
5e69f97f | 4431 | reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION); |
89b667f8 JB |
4432 | reg_val &= 0x00ffffff; |
4433 | reg_val |= 0xb0000000; | |
5e69f97f | 4434 | vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val); |
89b667f8 JB |
4435 | } |
4436 | ||
b551842d DV |
4437 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
4438 | struct intel_link_m_n *m_n) | |
4439 | { | |
4440 | struct drm_device *dev = crtc->base.dev; | |
4441 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4442 | int pipe = crtc->pipe; | |
4443 | ||
e3b95f1e DV |
4444 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4445 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
4446 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
4447 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
4448 | } |
4449 | ||
4450 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
4451 | struct intel_link_m_n *m_n) | |
4452 | { | |
4453 | struct drm_device *dev = crtc->base.dev; | |
4454 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4455 | int pipe = crtc->pipe; | |
4456 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
4457 | ||
4458 | if (INTEL_INFO(dev)->gen >= 5) { | |
4459 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
4460 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
4461 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
4462 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
4463 | } else { | |
e3b95f1e DV |
4464 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
4465 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
4466 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
4467 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
4468 | } |
4469 | } | |
4470 | ||
03afc4a2 DV |
4471 | static void intel_dp_set_m_n(struct intel_crtc *crtc) |
4472 | { | |
4473 | if (crtc->config.has_pch_encoder) | |
4474 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4475 | else | |
4476 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
4477 | } | |
4478 | ||
f47709a9 | 4479 | static void vlv_update_pll(struct intel_crtc *crtc) |
a0c4da24 | 4480 | { |
f47709a9 | 4481 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 4482 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 4483 | int pipe = crtc->pipe; |
89b667f8 | 4484 | u32 dpll, mdiv; |
a0c4da24 | 4485 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
198a037f | 4486 | u32 coreclk, reg_val, dpll_md; |
a0c4da24 | 4487 | |
09153000 DV |
4488 | mutex_lock(&dev_priv->dpio_lock); |
4489 | ||
f47709a9 DV |
4490 | bestn = crtc->config.dpll.n; |
4491 | bestm1 = crtc->config.dpll.m1; | |
4492 | bestm2 = crtc->config.dpll.m2; | |
4493 | bestp1 = crtc->config.dpll.p1; | |
4494 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 4495 | |
89b667f8 JB |
4496 | /* See eDP HDMI DPIO driver vbios notes doc */ |
4497 | ||
4498 | /* PLL B needs special handling */ | |
4499 | if (pipe) | |
5e69f97f | 4500 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
4501 | |
4502 | /* Set up Tx target for periodic Rcomp update */ | |
5e69f97f | 4503 | vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f); |
89b667f8 JB |
4504 | |
4505 | /* Disable target IRef on PLL */ | |
5e69f97f | 4506 | reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe)); |
89b667f8 | 4507 | reg_val &= 0x00ffffff; |
5e69f97f | 4508 | vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val); |
89b667f8 JB |
4509 | |
4510 | /* Disable fast lock */ | |
5e69f97f | 4511 | vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610); |
89b667f8 JB |
4512 | |
4513 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
4514 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
4515 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
4516 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 4517 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
4518 | |
4519 | /* | |
4520 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
4521 | * but we don't support that). | |
4522 | * Note: don't use the DAC post divider as it seems unstable. | |
4523 | */ | |
4524 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
5e69f97f | 4525 | vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv); |
a0c4da24 | 4526 | |
a0c4da24 | 4527 | mdiv |= DPIO_ENABLE_CALIBRATION; |
5e69f97f | 4528 | vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv); |
a0c4da24 | 4529 | |
89b667f8 | 4530 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 4531 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 4532 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 4533 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
5e69f97f | 4534 | vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe), |
885b0120 | 4535 | 0x009f0003); |
89b667f8 | 4536 | else |
5e69f97f | 4537 | vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe), |
89b667f8 JB |
4538 | 0x00d0000f); |
4539 | ||
4540 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
4541 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
4542 | /* Use SSC source */ | |
4543 | if (!pipe) | |
5e69f97f | 4544 | vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe), |
89b667f8 JB |
4545 | 0x0df40000); |
4546 | else | |
5e69f97f | 4547 | vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe), |
89b667f8 JB |
4548 | 0x0df70000); |
4549 | } else { /* HDMI or VGA */ | |
4550 | /* Use bend source */ | |
4551 | if (!pipe) | |
5e69f97f | 4552 | vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe), |
89b667f8 JB |
4553 | 0x0df70000); |
4554 | else | |
5e69f97f | 4555 | vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe), |
89b667f8 JB |
4556 | 0x0df40000); |
4557 | } | |
a0c4da24 | 4558 | |
5e69f97f | 4559 | coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe)); |
89b667f8 JB |
4560 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
4561 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
4562 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
4563 | coreclk |= 0x01000000; | |
5e69f97f | 4564 | vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk); |
a0c4da24 | 4565 | |
5e69f97f | 4566 | vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000); |
a0c4da24 | 4567 | |
89b667f8 JB |
4568 | /* Enable DPIO clock input */ |
4569 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
4570 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
4571 | if (pipe) | |
4572 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
a0c4da24 JB |
4573 | |
4574 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
4575 | crtc->config.dpll_hw_state.dpll = dpll; |
4576 | ||
ef1b460d DV |
4577 | dpll_md = (crtc->config.pixel_multiplier - 1) |
4578 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 DV |
4579 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
4580 | ||
89b667f8 JB |
4581 | if (crtc->config.has_dp_encoder) |
4582 | intel_dp_set_m_n(crtc); | |
09153000 DV |
4583 | |
4584 | mutex_unlock(&dev_priv->dpio_lock); | |
a0c4da24 JB |
4585 | } |
4586 | ||
f47709a9 DV |
4587 | static void i9xx_update_pll(struct intel_crtc *crtc, |
4588 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
4589 | int num_connectors) |
4590 | { | |
f47709a9 | 4591 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 4592 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
4593 | u32 dpll; |
4594 | bool is_sdvo; | |
f47709a9 | 4595 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 4596 | |
f47709a9 | 4597 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 4598 | |
f47709a9 DV |
4599 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
4600 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
4601 | |
4602 | dpll = DPLL_VGA_MODE_DIS; | |
4603 | ||
f47709a9 | 4604 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
4605 | dpll |= DPLLB_MODE_LVDS; |
4606 | else | |
4607 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 4608 | |
ef1b460d | 4609 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
4610 | dpll |= (crtc->config.pixel_multiplier - 1) |
4611 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 4612 | } |
198a037f DV |
4613 | |
4614 | if (is_sdvo) | |
4a33e48d | 4615 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 4616 | |
f47709a9 | 4617 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 4618 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
4619 | |
4620 | /* compute bitmask from p1 value */ | |
4621 | if (IS_PINEVIEW(dev)) | |
4622 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
4623 | else { | |
4624 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4625 | if (IS_G4X(dev) && reduced_clock) | |
4626 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
4627 | } | |
4628 | switch (clock->p2) { | |
4629 | case 5: | |
4630 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
4631 | break; | |
4632 | case 7: | |
4633 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
4634 | break; | |
4635 | case 10: | |
4636 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
4637 | break; | |
4638 | case 14: | |
4639 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
4640 | break; | |
4641 | } | |
4642 | if (INTEL_INFO(dev)->gen >= 4) | |
4643 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
4644 | ||
09ede541 | 4645 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 4646 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 4647 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
4648 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4649 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4650 | else | |
4651 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4652 | ||
4653 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
4654 | crtc->config.dpll_hw_state.dpll = dpll; |
4655 | ||
eb1cbe48 | 4656 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
4657 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
4658 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 4659 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 | 4660 | } |
66e3d5c0 DV |
4661 | |
4662 | if (crtc->config.has_dp_encoder) | |
4663 | intel_dp_set_m_n(crtc); | |
eb1cbe48 DV |
4664 | } |
4665 | ||
f47709a9 | 4666 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 4667 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
4668 | int num_connectors) |
4669 | { | |
f47709a9 | 4670 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 4671 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 4672 | u32 dpll; |
f47709a9 | 4673 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 4674 | |
f47709a9 | 4675 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 4676 | |
eb1cbe48 DV |
4677 | dpll = DPLL_VGA_MODE_DIS; |
4678 | ||
f47709a9 | 4679 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
4680 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
4681 | } else { | |
4682 | if (clock->p1 == 2) | |
4683 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
4684 | else | |
4685 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
4686 | if (clock->p2 == 4) | |
4687 | dpll |= PLL_P2_DIVIDE_BY_4; | |
4688 | } | |
4689 | ||
4a33e48d DV |
4690 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
4691 | dpll |= DPLL_DVO_2X_MODE; | |
4692 | ||
f47709a9 | 4693 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
4694 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
4695 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
4696 | else | |
4697 | dpll |= PLL_REF_INPUT_DREFCLK; | |
4698 | ||
4699 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 4700 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
4701 | } |
4702 | ||
8a654f3b | 4703 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
4704 | { |
4705 | struct drm_device *dev = intel_crtc->base.dev; | |
4706 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4707 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 4708 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
4709 | struct drm_display_mode *adjusted_mode = |
4710 | &intel_crtc->config.adjusted_mode; | |
4d8a62ea DV |
4711 | uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; |
4712 | ||
4713 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
4714 | * the hw state checker will get angry at the mismatch. */ | |
4715 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
4716 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c PZ |
4717 | |
4718 | if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
4719 | /* the chip adds 2 halflines automatically */ | |
4d8a62ea DV |
4720 | crtc_vtotal -= 1; |
4721 | crtc_vblank_end -= 1; | |
b0e77b9c PZ |
4722 | vsyncshift = adjusted_mode->crtc_hsync_start |
4723 | - adjusted_mode->crtc_htotal / 2; | |
4724 | } else { | |
4725 | vsyncshift = 0; | |
4726 | } | |
4727 | ||
4728 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 4729 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 4730 | |
fe2b8f9d | 4731 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
4732 | (adjusted_mode->crtc_hdisplay - 1) | |
4733 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 4734 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
4735 | (adjusted_mode->crtc_hblank_start - 1) | |
4736 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 4737 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
4738 | (adjusted_mode->crtc_hsync_start - 1) | |
4739 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
4740 | ||
fe2b8f9d | 4741 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 4742 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 4743 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 4744 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 4745 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 4746 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 4747 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
4748 | (adjusted_mode->crtc_vsync_start - 1) | |
4749 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
4750 | ||
b5e508d4 PZ |
4751 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
4752 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
4753 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
4754 | * bits. */ | |
4755 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
4756 | (pipe == PIPE_B || pipe == PIPE_C)) | |
4757 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
4758 | ||
b0e77b9c PZ |
4759 | /* pipesrc controls the size that is scaled from, which should |
4760 | * always be the user's requested size. | |
4761 | */ | |
4762 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
4763 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
4764 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
4765 | } |
4766 | ||
1bd1bd80 DV |
4767 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
4768 | struct intel_crtc_config *pipe_config) | |
4769 | { | |
4770 | struct drm_device *dev = crtc->base.dev; | |
4771 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4772 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
4773 | uint32_t tmp; | |
4774 | ||
4775 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
4776 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
4777 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
4778 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
4779 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
4780 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
4781 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
4782 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
4783 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
4784 | ||
4785 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
4786 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
4787 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
4788 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
4789 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
4790 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
4791 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
4792 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
4793 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
4794 | ||
4795 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
4796 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
4797 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
4798 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
4799 | } | |
4800 | ||
4801 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
4802 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
4803 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
4804 | ||
4805 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
4806 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
4807 | } |
4808 | ||
babea61d JB |
4809 | static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc, |
4810 | struct intel_crtc_config *pipe_config) | |
4811 | { | |
4812 | struct drm_crtc *crtc = &intel_crtc->base; | |
4813 | ||
4814 | crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; | |
4815 | crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal; | |
4816 | crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
4817 | crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
4818 | ||
4819 | crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; | |
4820 | crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
4821 | crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
4822 | crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
4823 | ||
4824 | crtc->mode.flags = pipe_config->adjusted_mode.flags; | |
4825 | ||
4826 | crtc->mode.clock = pipe_config->adjusted_mode.clock; | |
4827 | crtc->mode.flags |= pipe_config->adjusted_mode.flags; | |
4828 | } | |
4829 | ||
84b046f3 DV |
4830 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
4831 | { | |
4832 | struct drm_device *dev = intel_crtc->base.dev; | |
4833 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4834 | uint32_t pipeconf; | |
4835 | ||
9f11a9e4 | 4836 | pipeconf = 0; |
84b046f3 | 4837 | |
67c72a12 DV |
4838 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
4839 | I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE) | |
4840 | pipeconf |= PIPECONF_ENABLE; | |
4841 | ||
cf532bb2 VS |
4842 | if (intel_crtc->config.double_wide) |
4843 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 4844 | |
ff9ce46e DV |
4845 | /* only g4x and later have fancy bpc/dither controls */ |
4846 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
4847 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
4848 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
4849 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 4850 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 4851 | |
ff9ce46e DV |
4852 | switch (intel_crtc->config.pipe_bpp) { |
4853 | case 18: | |
4854 | pipeconf |= PIPECONF_6BPC; | |
4855 | break; | |
4856 | case 24: | |
4857 | pipeconf |= PIPECONF_8BPC; | |
4858 | break; | |
4859 | case 30: | |
4860 | pipeconf |= PIPECONF_10BPC; | |
4861 | break; | |
4862 | default: | |
4863 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
4864 | BUG(); | |
84b046f3 DV |
4865 | } |
4866 | } | |
4867 | ||
4868 | if (HAS_PIPE_CXSR(dev)) { | |
4869 | if (intel_crtc->lowfreq_avail) { | |
4870 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
4871 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
4872 | } else { | |
4873 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
4874 | } |
4875 | } | |
4876 | ||
84b046f3 DV |
4877 | if (!IS_GEN2(dev) && |
4878 | intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) | |
4879 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
4880 | else | |
4881 | pipeconf |= PIPECONF_PROGRESSIVE; | |
4882 | ||
9f11a9e4 DV |
4883 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
4884 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 4885 | |
84b046f3 DV |
4886 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
4887 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
4888 | } | |
4889 | ||
f564048e | 4890 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 4891 | int x, int y, |
94352cf9 | 4892 | struct drm_framebuffer *fb) |
79e53945 JB |
4893 | { |
4894 | struct drm_device *dev = crtc->dev; | |
4895 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4896 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4897 | int pipe = intel_crtc->pipe; | |
80824003 | 4898 | int plane = intel_crtc->plane; |
c751ce4f | 4899 | int refclk, num_connectors = 0; |
652c393a | 4900 | intel_clock_t clock, reduced_clock; |
84b046f3 | 4901 | u32 dspcntr; |
a16af721 | 4902 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 4903 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 4904 | struct intel_encoder *encoder; |
d4906093 | 4905 | const intel_limit_t *limit; |
5c3b82e2 | 4906 | int ret; |
79e53945 | 4907 | |
6c2b7c12 | 4908 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 4909 | switch (encoder->type) { |
79e53945 JB |
4910 | case INTEL_OUTPUT_LVDS: |
4911 | is_lvds = true; | |
4912 | break; | |
e9fd1c02 JN |
4913 | case INTEL_OUTPUT_DSI: |
4914 | is_dsi = true; | |
4915 | break; | |
79e53945 | 4916 | } |
43565a06 | 4917 | |
c751ce4f | 4918 | num_connectors++; |
79e53945 JB |
4919 | } |
4920 | ||
c65d77d8 | 4921 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 4922 | |
65ce4bf5 | 4923 | if (!is_dsi && !intel_crtc->config.clock_set) { |
e9fd1c02 JN |
4924 | /* |
4925 | * Returns a set of divisors for the desired target clock with | |
4926 | * the given refclk, or FALSE. The returned values represent | |
4927 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
4928 | * 2) / p1 / p2. | |
4929 | */ | |
4930 | limit = intel_limit(crtc, refclk); | |
4931 | ok = dev_priv->display.find_dpll(limit, crtc, | |
4932 | intel_crtc->config.port_clock, | |
4933 | refclk, NULL, &clock); | |
4934 | if (!ok && !intel_crtc->config.clock_set) { | |
4935 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
4936 | return -EINVAL; | |
4937 | } | |
79e53945 JB |
4938 | } |
4939 | ||
ddc9003c | 4940 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
4941 | /* |
4942 | * Ensure we match the reduced clock's P to the target clock. | |
4943 | * If the clocks don't match, we can't switch the display clock | |
4944 | * by using the FP0/FP1. In such case we will disable the LVDS | |
4945 | * downclock feature. | |
4946 | */ | |
65ce4bf5 | 4947 | limit = intel_limit(crtc, refclk); |
ee9300bb DV |
4948 | has_reduced_clock = |
4949 | dev_priv->display.find_dpll(limit, crtc, | |
5eddb70b | 4950 | dev_priv->lvds_downclock, |
ee9300bb | 4951 | refclk, &clock, |
5eddb70b | 4952 | &reduced_clock); |
7026d4ac | 4953 | } |
f47709a9 DV |
4954 | /* Compat-code for transition, will disappear. */ |
4955 | if (!intel_crtc->config.clock_set) { | |
4956 | intel_crtc->config.dpll.n = clock.n; | |
4957 | intel_crtc->config.dpll.m1 = clock.m1; | |
4958 | intel_crtc->config.dpll.m2 = clock.m2; | |
4959 | intel_crtc->config.dpll.p1 = clock.p1; | |
4960 | intel_crtc->config.dpll.p2 = clock.p2; | |
4961 | } | |
7026d4ac | 4962 | |
e9fd1c02 | 4963 | if (IS_GEN2(dev)) { |
8a654f3b | 4964 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
4965 | has_reduced_clock ? &reduced_clock : NULL, |
4966 | num_connectors); | |
e9fd1c02 JN |
4967 | } else if (IS_VALLEYVIEW(dev)) { |
4968 | if (!is_dsi) | |
4969 | vlv_update_pll(intel_crtc); | |
4970 | } else { | |
f47709a9 | 4971 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 4972 | has_reduced_clock ? &reduced_clock : NULL, |
89b667f8 | 4973 | num_connectors); |
e9fd1c02 | 4974 | } |
79e53945 | 4975 | |
79e53945 JB |
4976 | /* Set up the display plane register */ |
4977 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
4978 | ||
da6ecc5d JB |
4979 | if (!IS_VALLEYVIEW(dev)) { |
4980 | if (pipe == 0) | |
4981 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
4982 | else | |
4983 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
4984 | } | |
79e53945 | 4985 | |
8a654f3b | 4986 | intel_set_pipe_timings(intel_crtc); |
5eddb70b CW |
4987 | |
4988 | /* pipesrc and dspsize control the size that is scaled from, | |
4989 | * which should always be the user's requested size. | |
79e53945 | 4990 | */ |
929c77fb | 4991 | I915_WRITE(DSPSIZE(plane), |
37327abd VS |
4992 | ((intel_crtc->config.pipe_src_h - 1) << 16) | |
4993 | (intel_crtc->config.pipe_src_w - 1)); | |
929c77fb | 4994 | I915_WRITE(DSPPOS(plane), 0); |
2c07245f | 4995 | |
84b046f3 DV |
4996 | i9xx_set_pipeconf(intel_crtc); |
4997 | ||
f564048e EA |
4998 | I915_WRITE(DSPCNTR(plane), dspcntr); |
4999 | POSTING_READ(DSPCNTR(plane)); | |
5000 | ||
94352cf9 | 5001 | ret = intel_pipe_set_base(crtc, x, y, fb); |
f564048e | 5002 | |
f564048e EA |
5003 | return ret; |
5004 | } | |
5005 | ||
2fa2fe9a DV |
5006 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5007 | struct intel_crtc_config *pipe_config) | |
5008 | { | |
5009 | struct drm_device *dev = crtc->base.dev; | |
5010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5011 | uint32_t tmp; | |
5012 | ||
5013 | tmp = I915_READ(PFIT_CONTROL); | |
06922821 DV |
5014 | if (!(tmp & PFIT_ENABLE)) |
5015 | return; | |
2fa2fe9a | 5016 | |
06922821 | 5017 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
5018 | if (INTEL_INFO(dev)->gen < 4) { |
5019 | if (crtc->pipe != PIPE_B) | |
5020 | return; | |
2fa2fe9a DV |
5021 | } else { |
5022 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
5023 | return; | |
5024 | } | |
5025 | ||
06922821 | 5026 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
5027 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
5028 | if (INTEL_INFO(dev)->gen < 5) | |
5029 | pipe_config->gmch_pfit.lvds_border_bits = | |
5030 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
5031 | } | |
5032 | ||
0e8ffe1b DV |
5033 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5034 | struct intel_crtc_config *pipe_config) | |
5035 | { | |
5036 | struct drm_device *dev = crtc->base.dev; | |
5037 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5038 | uint32_t tmp; | |
5039 | ||
e143a21c | 5040 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 5041 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 5042 | |
0e8ffe1b DV |
5043 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
5044 | if (!(tmp & PIPECONF_ENABLE)) | |
5045 | return false; | |
5046 | ||
42571aef VS |
5047 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
5048 | switch (tmp & PIPECONF_BPC_MASK) { | |
5049 | case PIPECONF_6BPC: | |
5050 | pipe_config->pipe_bpp = 18; | |
5051 | break; | |
5052 | case PIPECONF_8BPC: | |
5053 | pipe_config->pipe_bpp = 24; | |
5054 | break; | |
5055 | case PIPECONF_10BPC: | |
5056 | pipe_config->pipe_bpp = 30; | |
5057 | break; | |
5058 | default: | |
5059 | break; | |
5060 | } | |
5061 | } | |
5062 | ||
282740f7 VS |
5063 | if (INTEL_INFO(dev)->gen < 4) |
5064 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
5065 | ||
1bd1bd80 DV |
5066 | intel_get_pipe_timings(crtc, pipe_config); |
5067 | ||
2fa2fe9a DV |
5068 | i9xx_get_pfit_config(crtc, pipe_config); |
5069 | ||
6c49f241 DV |
5070 | if (INTEL_INFO(dev)->gen >= 4) { |
5071 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
5072 | pipe_config->pixel_multiplier = | |
5073 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
5074 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 5075 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
5076 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
5077 | tmp = I915_READ(DPLL(crtc->pipe)); | |
5078 | pipe_config->pixel_multiplier = | |
5079 | ((tmp & SDVO_MULTIPLIER_MASK) | |
5080 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
5081 | } else { | |
5082 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
5083 | * port and will be fixed up in the encoder->get_config | |
5084 | * function. */ | |
5085 | pipe_config->pixel_multiplier = 1; | |
5086 | } | |
8bcc2795 DV |
5087 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
5088 | if (!IS_VALLEYVIEW(dev)) { | |
5089 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); | |
5090 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
5091 | } else { |
5092 | /* Mask out read-only status bits. */ | |
5093 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
5094 | DPLL_PORTC_READY_MASK | | |
5095 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 5096 | } |
6c49f241 | 5097 | |
18442d08 VS |
5098 | i9xx_crtc_clock_get(crtc, pipe_config); |
5099 | ||
0e8ffe1b DV |
5100 | return true; |
5101 | } | |
5102 | ||
dde86e2d | 5103 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
5104 | { |
5105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5106 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 5107 | struct intel_encoder *encoder; |
74cfd7ac | 5108 | u32 val, final; |
13d83a67 | 5109 | bool has_lvds = false; |
199e5d79 | 5110 | bool has_cpu_edp = false; |
199e5d79 | 5111 | bool has_panel = false; |
99eb6a01 KP |
5112 | bool has_ck505 = false; |
5113 | bool can_ssc = false; | |
13d83a67 JB |
5114 | |
5115 | /* We need to take the global config into account */ | |
199e5d79 KP |
5116 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5117 | base.head) { | |
5118 | switch (encoder->type) { | |
5119 | case INTEL_OUTPUT_LVDS: | |
5120 | has_panel = true; | |
5121 | has_lvds = true; | |
5122 | break; | |
5123 | case INTEL_OUTPUT_EDP: | |
5124 | has_panel = true; | |
2de6905f | 5125 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
5126 | has_cpu_edp = true; |
5127 | break; | |
13d83a67 JB |
5128 | } |
5129 | } | |
5130 | ||
99eb6a01 | 5131 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 5132 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
5133 | can_ssc = has_ck505; |
5134 | } else { | |
5135 | has_ck505 = false; | |
5136 | can_ssc = true; | |
5137 | } | |
5138 | ||
2de6905f ID |
5139 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
5140 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
5141 | |
5142 | /* Ironlake: try to setup display ref clock before DPLL | |
5143 | * enabling. This is only under driver's control after | |
5144 | * PCH B stepping, previous chipset stepping should be | |
5145 | * ignoring this setting. | |
5146 | */ | |
74cfd7ac CW |
5147 | val = I915_READ(PCH_DREF_CONTROL); |
5148 | ||
5149 | /* As we must carefully and slowly disable/enable each source in turn, | |
5150 | * compute the final state we want first and check if we need to | |
5151 | * make any changes at all. | |
5152 | */ | |
5153 | final = val; | |
5154 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
5155 | if (has_ck505) | |
5156 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
5157 | else | |
5158 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
5159 | ||
5160 | final &= ~DREF_SSC_SOURCE_MASK; | |
5161 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
5162 | final &= ~DREF_SSC1_ENABLE; | |
5163 | ||
5164 | if (has_panel) { | |
5165 | final |= DREF_SSC_SOURCE_ENABLE; | |
5166 | ||
5167 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5168 | final |= DREF_SSC1_ENABLE; | |
5169 | ||
5170 | if (has_cpu_edp) { | |
5171 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
5172 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
5173 | else | |
5174 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
5175 | } else | |
5176 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5177 | } else { | |
5178 | final |= DREF_SSC_SOURCE_DISABLE; | |
5179 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5180 | } | |
5181 | ||
5182 | if (final == val) | |
5183 | return; | |
5184 | ||
13d83a67 | 5185 | /* Always enable nonspread source */ |
74cfd7ac | 5186 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 5187 | |
99eb6a01 | 5188 | if (has_ck505) |
74cfd7ac | 5189 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 5190 | else |
74cfd7ac | 5191 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 5192 | |
199e5d79 | 5193 | if (has_panel) { |
74cfd7ac CW |
5194 | val &= ~DREF_SSC_SOURCE_MASK; |
5195 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 5196 | |
199e5d79 | 5197 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 5198 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5199 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 5200 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 5201 | } else |
74cfd7ac | 5202 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
5203 | |
5204 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 5205 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5206 | POSTING_READ(PCH_DREF_CONTROL); |
5207 | udelay(200); | |
5208 | ||
74cfd7ac | 5209 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
5210 | |
5211 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 5212 | if (has_cpu_edp) { |
99eb6a01 | 5213 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5214 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 5215 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 5216 | } |
13d83a67 | 5217 | else |
74cfd7ac | 5218 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 5219 | } else |
74cfd7ac | 5220 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5221 | |
74cfd7ac | 5222 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5223 | POSTING_READ(PCH_DREF_CONTROL); |
5224 | udelay(200); | |
5225 | } else { | |
5226 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
5227 | ||
74cfd7ac | 5228 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
5229 | |
5230 | /* Turn off CPU output */ | |
74cfd7ac | 5231 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 5232 | |
74cfd7ac | 5233 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
5234 | POSTING_READ(PCH_DREF_CONTROL); |
5235 | udelay(200); | |
5236 | ||
5237 | /* Turn off the SSC source */ | |
74cfd7ac CW |
5238 | val &= ~DREF_SSC_SOURCE_MASK; |
5239 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
5240 | |
5241 | /* Turn off SSC1 */ | |
74cfd7ac | 5242 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 5243 | |
74cfd7ac | 5244 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
5245 | POSTING_READ(PCH_DREF_CONTROL); |
5246 | udelay(200); | |
5247 | } | |
74cfd7ac CW |
5248 | |
5249 | BUG_ON(val != final); | |
13d83a67 JB |
5250 | } |
5251 | ||
f31f2d55 | 5252 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 5253 | { |
f31f2d55 | 5254 | uint32_t tmp; |
dde86e2d | 5255 | |
0ff066a9 PZ |
5256 | tmp = I915_READ(SOUTH_CHICKEN2); |
5257 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
5258 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5259 | |
0ff066a9 PZ |
5260 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
5261 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
5262 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 5263 | |
0ff066a9 PZ |
5264 | tmp = I915_READ(SOUTH_CHICKEN2); |
5265 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
5266 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 5267 | |
0ff066a9 PZ |
5268 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
5269 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
5270 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
5271 | } |
5272 | ||
5273 | /* WaMPhyProgramming:hsw */ | |
5274 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
5275 | { | |
5276 | uint32_t tmp; | |
dde86e2d PZ |
5277 | |
5278 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
5279 | tmp &= ~(0xFF << 24); | |
5280 | tmp |= (0x12 << 24); | |
5281 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
5282 | ||
dde86e2d PZ |
5283 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
5284 | tmp |= (1 << 11); | |
5285 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
5286 | ||
5287 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
5288 | tmp |= (1 << 11); | |
5289 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
5290 | ||
dde86e2d PZ |
5291 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
5292 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5293 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
5294 | ||
5295 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
5296 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
5297 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
5298 | ||
0ff066a9 PZ |
5299 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
5300 | tmp &= ~(7 << 13); | |
5301 | tmp |= (5 << 13); | |
5302 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 5303 | |
0ff066a9 PZ |
5304 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
5305 | tmp &= ~(7 << 13); | |
5306 | tmp |= (5 << 13); | |
5307 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
5308 | |
5309 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
5310 | tmp &= ~0xFF; | |
5311 | tmp |= 0x1C; | |
5312 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
5313 | ||
5314 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
5315 | tmp &= ~0xFF; | |
5316 | tmp |= 0x1C; | |
5317 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
5318 | ||
5319 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
5320 | tmp &= ~(0xFF << 16); | |
5321 | tmp |= (0x1C << 16); | |
5322 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
5323 | ||
5324 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
5325 | tmp &= ~(0xFF << 16); | |
5326 | tmp |= (0x1C << 16); | |
5327 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
5328 | ||
0ff066a9 PZ |
5329 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
5330 | tmp |= (1 << 27); | |
5331 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 5332 | |
0ff066a9 PZ |
5333 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
5334 | tmp |= (1 << 27); | |
5335 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 5336 | |
0ff066a9 PZ |
5337 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
5338 | tmp &= ~(0xF << 28); | |
5339 | tmp |= (4 << 28); | |
5340 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 5341 | |
0ff066a9 PZ |
5342 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
5343 | tmp &= ~(0xF << 28); | |
5344 | tmp |= (4 << 28); | |
5345 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
5346 | } |
5347 | ||
2fa86a1f PZ |
5348 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
5349 | * Programming" based on the parameters passed: | |
5350 | * - Sequence to enable CLKOUT_DP | |
5351 | * - Sequence to enable CLKOUT_DP without spread | |
5352 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
5353 | */ | |
5354 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
5355 | bool with_fdi) | |
f31f2d55 PZ |
5356 | { |
5357 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
5358 | uint32_t reg, tmp; |
5359 | ||
5360 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
5361 | with_spread = true; | |
5362 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
5363 | with_fdi, "LP PCH doesn't have FDI\n")) | |
5364 | with_fdi = false; | |
f31f2d55 PZ |
5365 | |
5366 | mutex_lock(&dev_priv->dpio_lock); | |
5367 | ||
5368 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5369 | tmp &= ~SBI_SSCCTL_DISABLE; | |
5370 | tmp |= SBI_SSCCTL_PATHALT; | |
5371 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5372 | ||
5373 | udelay(24); | |
5374 | ||
2fa86a1f PZ |
5375 | if (with_spread) { |
5376 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5377 | tmp &= ~SBI_SSCCTL_PATHALT; | |
5378 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 5379 | |
2fa86a1f PZ |
5380 | if (with_fdi) { |
5381 | lpt_reset_fdi_mphy(dev_priv); | |
5382 | lpt_program_fdi_mphy(dev_priv); | |
5383 | } | |
5384 | } | |
dde86e2d | 5385 | |
2fa86a1f PZ |
5386 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
5387 | SBI_GEN0 : SBI_DBUFF0; | |
5388 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
5389 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
5390 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
5391 | |
5392 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
5393 | } |
5394 | ||
47701c3b PZ |
5395 | /* Sequence to disable CLKOUT_DP */ |
5396 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
5397 | { | |
5398 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5399 | uint32_t reg, tmp; | |
5400 | ||
5401 | mutex_lock(&dev_priv->dpio_lock); | |
5402 | ||
5403 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
5404 | SBI_GEN0 : SBI_DBUFF0; | |
5405 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
5406 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
5407 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
5408 | ||
5409 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
5410 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
5411 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
5412 | tmp |= SBI_SSCCTL_PATHALT; | |
5413 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5414 | udelay(32); | |
5415 | } | |
5416 | tmp |= SBI_SSCCTL_DISABLE; | |
5417 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
5418 | } | |
5419 | ||
5420 | mutex_unlock(&dev_priv->dpio_lock); | |
5421 | } | |
5422 | ||
bf8fa3d3 PZ |
5423 | static void lpt_init_pch_refclk(struct drm_device *dev) |
5424 | { | |
5425 | struct drm_mode_config *mode_config = &dev->mode_config; | |
5426 | struct intel_encoder *encoder; | |
5427 | bool has_vga = false; | |
5428 | ||
5429 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
5430 | switch (encoder->type) { | |
5431 | case INTEL_OUTPUT_ANALOG: | |
5432 | has_vga = true; | |
5433 | break; | |
5434 | } | |
5435 | } | |
5436 | ||
47701c3b PZ |
5437 | if (has_vga) |
5438 | lpt_enable_clkout_dp(dev, true, true); | |
5439 | else | |
5440 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
5441 | } |
5442 | ||
dde86e2d PZ |
5443 | /* |
5444 | * Initialize reference clocks when the driver loads | |
5445 | */ | |
5446 | void intel_init_pch_refclk(struct drm_device *dev) | |
5447 | { | |
5448 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
5449 | ironlake_init_pch_refclk(dev); | |
5450 | else if (HAS_PCH_LPT(dev)) | |
5451 | lpt_init_pch_refclk(dev); | |
5452 | } | |
5453 | ||
d9d444cb JB |
5454 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5455 | { | |
5456 | struct drm_device *dev = crtc->dev; | |
5457 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5458 | struct intel_encoder *encoder; | |
d9d444cb JB |
5459 | int num_connectors = 0; |
5460 | bool is_lvds = false; | |
5461 | ||
6c2b7c12 | 5462 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
5463 | switch (encoder->type) { |
5464 | case INTEL_OUTPUT_LVDS: | |
5465 | is_lvds = true; | |
5466 | break; | |
d9d444cb JB |
5467 | } |
5468 | num_connectors++; | |
5469 | } | |
5470 | ||
5471 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
5472 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
41aa3448 RV |
5473 | dev_priv->vbt.lvds_ssc_freq); |
5474 | return dev_priv->vbt.lvds_ssc_freq * 1000; | |
d9d444cb JB |
5475 | } |
5476 | ||
5477 | return 120000; | |
5478 | } | |
5479 | ||
6ff93609 | 5480 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 5481 | { |
c8203565 | 5482 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
5483 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5484 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
5485 | uint32_t val; |
5486 | ||
78114071 | 5487 | val = 0; |
c8203565 | 5488 | |
965e0c48 | 5489 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 5490 | case 18: |
dfd07d72 | 5491 | val |= PIPECONF_6BPC; |
c8203565 PZ |
5492 | break; |
5493 | case 24: | |
dfd07d72 | 5494 | val |= PIPECONF_8BPC; |
c8203565 PZ |
5495 | break; |
5496 | case 30: | |
dfd07d72 | 5497 | val |= PIPECONF_10BPC; |
c8203565 PZ |
5498 | break; |
5499 | case 36: | |
dfd07d72 | 5500 | val |= PIPECONF_12BPC; |
c8203565 PZ |
5501 | break; |
5502 | default: | |
cc769b62 PZ |
5503 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
5504 | BUG(); | |
c8203565 PZ |
5505 | } |
5506 | ||
d8b32247 | 5507 | if (intel_crtc->config.dither) |
c8203565 PZ |
5508 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5509 | ||
6ff93609 | 5510 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
5511 | val |= PIPECONF_INTERLACED_ILK; |
5512 | else | |
5513 | val |= PIPECONF_PROGRESSIVE; | |
5514 | ||
50f3b016 | 5515 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 5516 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 5517 | |
c8203565 PZ |
5518 | I915_WRITE(PIPECONF(pipe), val); |
5519 | POSTING_READ(PIPECONF(pipe)); | |
5520 | } | |
5521 | ||
86d3efce VS |
5522 | /* |
5523 | * Set up the pipe CSC unit. | |
5524 | * | |
5525 | * Currently only full range RGB to limited range RGB conversion | |
5526 | * is supported, but eventually this should handle various | |
5527 | * RGB<->YCbCr scenarios as well. | |
5528 | */ | |
50f3b016 | 5529 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
5530 | { |
5531 | struct drm_device *dev = crtc->dev; | |
5532 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5533 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5534 | int pipe = intel_crtc->pipe; | |
5535 | uint16_t coeff = 0x7800; /* 1.0 */ | |
5536 | ||
5537 | /* | |
5538 | * TODO: Check what kind of values actually come out of the pipe | |
5539 | * with these coeff/postoff values and adjust to get the best | |
5540 | * accuracy. Perhaps we even need to take the bpc value into | |
5541 | * consideration. | |
5542 | */ | |
5543 | ||
50f3b016 | 5544 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
5545 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
5546 | ||
5547 | /* | |
5548 | * GY/GU and RY/RU should be the other way around according | |
5549 | * to BSpec, but reality doesn't agree. Just set them up in | |
5550 | * a way that results in the correct picture. | |
5551 | */ | |
5552 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
5553 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
5554 | ||
5555 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
5556 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
5557 | ||
5558 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
5559 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
5560 | ||
5561 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
5562 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
5563 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
5564 | ||
5565 | if (INTEL_INFO(dev)->gen > 6) { | |
5566 | uint16_t postoff = 0; | |
5567 | ||
50f3b016 | 5568 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
5569 | postoff = (16 * (1 << 13) / 255) & 0x1fff; |
5570 | ||
5571 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
5572 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
5573 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
5574 | ||
5575 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
5576 | } else { | |
5577 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
5578 | ||
50f3b016 | 5579 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
5580 | mode |= CSC_BLACK_SCREEN_OFFSET; |
5581 | ||
5582 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
5583 | } | |
5584 | } | |
5585 | ||
6ff93609 | 5586 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 PZ |
5587 | { |
5588 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
5589 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 5590 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
5591 | uint32_t val; |
5592 | ||
3eff4faa | 5593 | val = 0; |
ee2b0b38 | 5594 | |
d8b32247 | 5595 | if (intel_crtc->config.dither) |
ee2b0b38 PZ |
5596 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
5597 | ||
6ff93609 | 5598 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
5599 | val |= PIPECONF_INTERLACED_ILK; |
5600 | else | |
5601 | val |= PIPECONF_PROGRESSIVE; | |
5602 | ||
702e7a56 PZ |
5603 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
5604 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
5605 | |
5606 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
5607 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
ee2b0b38 PZ |
5608 | } |
5609 | ||
6591c6e4 | 5610 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
5611 | intel_clock_t *clock, |
5612 | bool *has_reduced_clock, | |
5613 | intel_clock_t *reduced_clock) | |
5614 | { | |
5615 | struct drm_device *dev = crtc->dev; | |
5616 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5617 | struct intel_encoder *intel_encoder; | |
5618 | int refclk; | |
d4906093 | 5619 | const intel_limit_t *limit; |
a16af721 | 5620 | bool ret, is_lvds = false; |
79e53945 | 5621 | |
6591c6e4 PZ |
5622 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5623 | switch (intel_encoder->type) { | |
79e53945 JB |
5624 | case INTEL_OUTPUT_LVDS: |
5625 | is_lvds = true; | |
5626 | break; | |
79e53945 JB |
5627 | } |
5628 | } | |
5629 | ||
d9d444cb | 5630 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 5631 | |
d4906093 ML |
5632 | /* |
5633 | * Returns a set of divisors for the desired target clock with the given | |
5634 | * refclk, or FALSE. The returned values represent the clock equation: | |
5635 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
5636 | */ | |
1b894b59 | 5637 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
5638 | ret = dev_priv->display.find_dpll(limit, crtc, |
5639 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 5640 | refclk, NULL, clock); |
6591c6e4 PZ |
5641 | if (!ret) |
5642 | return false; | |
cda4b7d3 | 5643 | |
ddc9003c | 5644 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
5645 | /* |
5646 | * Ensure we match the reduced clock's P to the target clock. | |
5647 | * If the clocks don't match, we can't switch the display clock | |
5648 | * by using the FP0/FP1. In such case we will disable the LVDS | |
5649 | * downclock feature. | |
5650 | */ | |
ee9300bb DV |
5651 | *has_reduced_clock = |
5652 | dev_priv->display.find_dpll(limit, crtc, | |
5653 | dev_priv->lvds_downclock, | |
5654 | refclk, clock, | |
5655 | reduced_clock); | |
652c393a | 5656 | } |
61e9653f | 5657 | |
6591c6e4 PZ |
5658 | return true; |
5659 | } | |
5660 | ||
01a415fd DV |
5661 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
5662 | { | |
5663 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5664 | uint32_t temp; | |
5665 | ||
5666 | temp = I915_READ(SOUTH_CHICKEN1); | |
5667 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
5668 | return; | |
5669 | ||
5670 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
5671 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
5672 | ||
5673 | temp |= FDI_BC_BIFURCATION_SELECT; | |
5674 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
5675 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
5676 | POSTING_READ(SOUTH_CHICKEN1); | |
5677 | } | |
5678 | ||
ebfd86fd | 5679 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) |
01a415fd DV |
5680 | { |
5681 | struct drm_device *dev = intel_crtc->base.dev; | |
5682 | struct drm_i915_private *dev_priv = dev->dev_private; | |
01a415fd DV |
5683 | |
5684 | switch (intel_crtc->pipe) { | |
5685 | case PIPE_A: | |
ebfd86fd | 5686 | break; |
01a415fd | 5687 | case PIPE_B: |
ebfd86fd | 5688 | if (intel_crtc->config.fdi_lanes > 2) |
01a415fd DV |
5689 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); |
5690 | else | |
5691 | cpt_enable_fdi_bc_bifurcation(dev); | |
5692 | ||
ebfd86fd | 5693 | break; |
01a415fd | 5694 | case PIPE_C: |
01a415fd DV |
5695 | cpt_enable_fdi_bc_bifurcation(dev); |
5696 | ||
ebfd86fd | 5697 | break; |
01a415fd DV |
5698 | default: |
5699 | BUG(); | |
5700 | } | |
5701 | } | |
5702 | ||
d4b1931c PZ |
5703 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
5704 | { | |
5705 | /* | |
5706 | * Account for spread spectrum to avoid | |
5707 | * oversubscribing the link. Max center spread | |
5708 | * is 2.5%; use 5% for safety's sake. | |
5709 | */ | |
5710 | u32 bps = target_clock * bpp * 21 / 20; | |
5711 | return bps / (link_bw * 8) + 1; | |
5712 | } | |
5713 | ||
7429e9d4 | 5714 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 5715 | { |
7429e9d4 | 5716 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
5717 | } |
5718 | ||
de13a2e3 | 5719 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 5720 | u32 *fp, |
9a7c7890 | 5721 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 5722 | { |
de13a2e3 | 5723 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
5724 | struct drm_device *dev = crtc->dev; |
5725 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
5726 | struct intel_encoder *intel_encoder; |
5727 | uint32_t dpll; | |
6cc5f341 | 5728 | int factor, num_connectors = 0; |
09ede541 | 5729 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 5730 | |
de13a2e3 PZ |
5731 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
5732 | switch (intel_encoder->type) { | |
79e53945 JB |
5733 | case INTEL_OUTPUT_LVDS: |
5734 | is_lvds = true; | |
5735 | break; | |
5736 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5737 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5738 | is_sdvo = true; |
79e53945 | 5739 | break; |
79e53945 | 5740 | } |
43565a06 | 5741 | |
c751ce4f | 5742 | num_connectors++; |
79e53945 | 5743 | } |
79e53945 | 5744 | |
c1858123 | 5745 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
5746 | factor = 21; |
5747 | if (is_lvds) { | |
5748 | if ((intel_panel_use_ssc(dev_priv) && | |
41aa3448 | 5749 | dev_priv->vbt.lvds_ssc_freq == 100) || |
f0b44056 | 5750 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 5751 | factor = 25; |
09ede541 | 5752 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 5753 | factor = 20; |
c1858123 | 5754 | |
7429e9d4 | 5755 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 5756 | *fp |= FP_CB_TUNE; |
2c07245f | 5757 | |
9a7c7890 DV |
5758 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
5759 | *fp2 |= FP_CB_TUNE; | |
5760 | ||
5eddb70b | 5761 | dpll = 0; |
2c07245f | 5762 | |
a07d6787 EA |
5763 | if (is_lvds) |
5764 | dpll |= DPLLB_MODE_LVDS; | |
5765 | else | |
5766 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 5767 | |
ef1b460d DV |
5768 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
5769 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
5770 | |
5771 | if (is_sdvo) | |
4a33e48d | 5772 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 5773 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 5774 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 5775 | |
a07d6787 | 5776 | /* compute bitmask from p1 value */ |
7429e9d4 | 5777 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 5778 | /* also FPA1 */ |
7429e9d4 | 5779 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 5780 | |
7429e9d4 | 5781 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
5782 | case 5: |
5783 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5784 | break; | |
5785 | case 7: | |
5786 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5787 | break; | |
5788 | case 10: | |
5789 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5790 | break; | |
5791 | case 14: | |
5792 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5793 | break; | |
79e53945 JB |
5794 | } |
5795 | ||
b4c09f3b | 5796 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 5797 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
5798 | else |
5799 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5800 | ||
959e16d6 | 5801 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
5802 | } |
5803 | ||
5804 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
5805 | int x, int y, |
5806 | struct drm_framebuffer *fb) | |
5807 | { | |
5808 | struct drm_device *dev = crtc->dev; | |
5809 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5810 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5811 | int pipe = intel_crtc->pipe; | |
5812 | int plane = intel_crtc->plane; | |
5813 | int num_connectors = 0; | |
5814 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 5815 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 5816 | bool ok, has_reduced_clock = false; |
8b47047b | 5817 | bool is_lvds = false; |
de13a2e3 | 5818 | struct intel_encoder *encoder; |
e2b78267 | 5819 | struct intel_shared_dpll *pll; |
de13a2e3 | 5820 | int ret; |
de13a2e3 PZ |
5821 | |
5822 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
5823 | switch (encoder->type) { | |
5824 | case INTEL_OUTPUT_LVDS: | |
5825 | is_lvds = true; | |
5826 | break; | |
de13a2e3 PZ |
5827 | } |
5828 | ||
5829 | num_connectors++; | |
a07d6787 | 5830 | } |
79e53945 | 5831 | |
5dc5298b PZ |
5832 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
5833 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 5834 | |
ff9a6750 | 5835 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 5836 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 5837 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
5838 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
5839 | return -EINVAL; | |
79e53945 | 5840 | } |
f47709a9 DV |
5841 | /* Compat-code for transition, will disappear. */ |
5842 | if (!intel_crtc->config.clock_set) { | |
5843 | intel_crtc->config.dpll.n = clock.n; | |
5844 | intel_crtc->config.dpll.m1 = clock.m1; | |
5845 | intel_crtc->config.dpll.m2 = clock.m2; | |
5846 | intel_crtc->config.dpll.p1 = clock.p1; | |
5847 | intel_crtc->config.dpll.p2 = clock.p2; | |
5848 | } | |
79e53945 | 5849 | |
5dc5298b | 5850 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 5851 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 5852 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 5853 | if (has_reduced_clock) |
7429e9d4 | 5854 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 5855 | |
7429e9d4 | 5856 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
5857 | &fp, &reduced_clock, |
5858 | has_reduced_clock ? &fp2 : NULL); | |
5859 | ||
959e16d6 | 5860 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
5861 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
5862 | if (has_reduced_clock) | |
5863 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
5864 | else | |
5865 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
5866 | ||
b89a1d39 | 5867 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 5868 | if (pll == NULL) { |
84f44ce7 VS |
5869 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
5870 | pipe_name(pipe)); | |
4b645f14 JB |
5871 | return -EINVAL; |
5872 | } | |
ee7b9f93 | 5873 | } else |
e72f9fbf | 5874 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 5875 | |
03afc4a2 DV |
5876 | if (intel_crtc->config.has_dp_encoder) |
5877 | intel_dp_set_m_n(intel_crtc); | |
79e53945 | 5878 | |
bcd644e0 DV |
5879 | if (is_lvds && has_reduced_clock && i915_powersave) |
5880 | intel_crtc->lowfreq_avail = true; | |
5881 | else | |
5882 | intel_crtc->lowfreq_avail = false; | |
e2b78267 DV |
5883 | |
5884 | if (intel_crtc->config.has_pch_encoder) { | |
5885 | pll = intel_crtc_to_shared_dpll(intel_crtc); | |
5886 | ||
652c393a JB |
5887 | } |
5888 | ||
8a654f3b | 5889 | intel_set_pipe_timings(intel_crtc); |
5eddb70b | 5890 | |
ca3a0ff8 | 5891 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
5892 | intel_cpu_transcoder_set_m_n(intel_crtc, |
5893 | &intel_crtc->config.fdi_m_n); | |
5894 | } | |
2c07245f | 5895 | |
ebfd86fd DV |
5896 | if (IS_IVYBRIDGE(dev)) |
5897 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
79e53945 | 5898 | |
6ff93609 | 5899 | ironlake_set_pipeconf(crtc); |
79e53945 | 5900 | |
a1f9e77e PZ |
5901 | /* Set up the display plane register */ |
5902 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); | |
b24e7179 | 5903 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 5904 | |
94352cf9 | 5905 | ret = intel_pipe_set_base(crtc, x, y, fb); |
7662c8bd | 5906 | |
1857e1da | 5907 | return ret; |
79e53945 JB |
5908 | } |
5909 | ||
eb14cb74 VS |
5910 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
5911 | struct intel_link_m_n *m_n) | |
5912 | { | |
5913 | struct drm_device *dev = crtc->base.dev; | |
5914 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5915 | enum pipe pipe = crtc->pipe; | |
5916 | ||
5917 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
5918 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
5919 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
5920 | & ~TU_SIZE_MASK; | |
5921 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
5922 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
5923 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
5924 | } | |
5925 | ||
5926 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
5927 | enum transcoder transcoder, | |
5928 | struct intel_link_m_n *m_n) | |
72419203 DV |
5929 | { |
5930 | struct drm_device *dev = crtc->base.dev; | |
5931 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 5932 | enum pipe pipe = crtc->pipe; |
72419203 | 5933 | |
eb14cb74 VS |
5934 | if (INTEL_INFO(dev)->gen >= 5) { |
5935 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
5936 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
5937 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
5938 | & ~TU_SIZE_MASK; | |
5939 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
5940 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
5941 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
5942 | } else { | |
5943 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
5944 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
5945 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
5946 | & ~TU_SIZE_MASK; | |
5947 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
5948 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
5949 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
5950 | } | |
5951 | } | |
5952 | ||
5953 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5954 | struct intel_crtc_config *pipe_config) | |
5955 | { | |
5956 | if (crtc->config.has_pch_encoder) | |
5957 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
5958 | else | |
5959 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
5960 | &pipe_config->dp_m_n); | |
5961 | } | |
72419203 | 5962 | |
eb14cb74 VS |
5963 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5964 | struct intel_crtc_config *pipe_config) | |
5965 | { | |
5966 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
5967 | &pipe_config->fdi_m_n); | |
72419203 DV |
5968 | } |
5969 | ||
2fa2fe9a DV |
5970 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5971 | struct intel_crtc_config *pipe_config) | |
5972 | { | |
5973 | struct drm_device *dev = crtc->base.dev; | |
5974 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5975 | uint32_t tmp; | |
5976 | ||
5977 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
5978 | ||
5979 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 5980 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
5981 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
5982 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
5983 | |
5984 | /* We currently do not free assignements of panel fitters on | |
5985 | * ivb/hsw (since we don't use the higher upscaling modes which | |
5986 | * differentiates them) so just WARN about this case for now. */ | |
5987 | if (IS_GEN7(dev)) { | |
5988 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
5989 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
5990 | } | |
2fa2fe9a | 5991 | } |
79e53945 JB |
5992 | } |
5993 | ||
0e8ffe1b DV |
5994 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5995 | struct intel_crtc_config *pipe_config) | |
5996 | { | |
5997 | struct drm_device *dev = crtc->base.dev; | |
5998 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5999 | uint32_t tmp; | |
6000 | ||
e143a21c | 6001 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6002 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6003 | |
0e8ffe1b DV |
6004 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6005 | if (!(tmp & PIPECONF_ENABLE)) | |
6006 | return false; | |
6007 | ||
42571aef VS |
6008 | switch (tmp & PIPECONF_BPC_MASK) { |
6009 | case PIPECONF_6BPC: | |
6010 | pipe_config->pipe_bpp = 18; | |
6011 | break; | |
6012 | case PIPECONF_8BPC: | |
6013 | pipe_config->pipe_bpp = 24; | |
6014 | break; | |
6015 | case PIPECONF_10BPC: | |
6016 | pipe_config->pipe_bpp = 30; | |
6017 | break; | |
6018 | case PIPECONF_12BPC: | |
6019 | pipe_config->pipe_bpp = 36; | |
6020 | break; | |
6021 | default: | |
6022 | break; | |
6023 | } | |
6024 | ||
ab9412ba | 6025 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
6026 | struct intel_shared_dpll *pll; |
6027 | ||
88adfff1 DV |
6028 | pipe_config->has_pch_encoder = true; |
6029 | ||
627eb5a3 DV |
6030 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
6031 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
6032 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
6033 | |
6034 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 6035 | |
c0d43d62 | 6036 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
6037 | pipe_config->shared_dpll = |
6038 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
6039 | } else { |
6040 | tmp = I915_READ(PCH_DPLL_SEL); | |
6041 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
6042 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
6043 | else | |
6044 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
6045 | } | |
66e985c0 DV |
6046 | |
6047 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
6048 | ||
6049 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
6050 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
6051 | |
6052 | tmp = pipe_config->dpll_hw_state.dpll; | |
6053 | pipe_config->pixel_multiplier = | |
6054 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
6055 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
6056 | |
6057 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
6058 | } else { |
6059 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
6060 | } |
6061 | ||
1bd1bd80 DV |
6062 | intel_get_pipe_timings(crtc, pipe_config); |
6063 | ||
2fa2fe9a DV |
6064 | ironlake_get_pfit_config(crtc, pipe_config); |
6065 | ||
0e8ffe1b DV |
6066 | return true; |
6067 | } | |
6068 | ||
be256dc7 PZ |
6069 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
6070 | { | |
6071 | struct drm_device *dev = dev_priv->dev; | |
6072 | struct intel_ddi_plls *plls = &dev_priv->ddi_plls; | |
6073 | struct intel_crtc *crtc; | |
6074 | unsigned long irqflags; | |
bd633a7c | 6075 | uint32_t val; |
be256dc7 PZ |
6076 | |
6077 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
6078 | WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n", | |
6079 | pipe_name(crtc->pipe)); | |
6080 | ||
6081 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
6082 | WARN(plls->spll_refcount, "SPLL enabled\n"); | |
6083 | WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n"); | |
6084 | WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n"); | |
6085 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
6086 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
6087 | "CPU PWM1 enabled\n"); | |
6088 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
6089 | "CPU PWM2 enabled\n"); | |
6090 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, | |
6091 | "PCH PWM1 enabled\n"); | |
6092 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
6093 | "Utility pin enabled\n"); | |
6094 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
6095 | ||
6096 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
6097 | val = I915_READ(DEIMR); | |
6098 | WARN((val & ~DE_PCH_EVENT_IVB) != val, | |
6099 | "Unexpected DEIMR bits enabled: 0x%x\n", val); | |
6100 | val = I915_READ(SDEIMR); | |
bd633a7c | 6101 | WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff, |
be256dc7 PZ |
6102 | "Unexpected SDEIMR bits enabled: 0x%x\n", val); |
6103 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
6104 | } | |
6105 | ||
6106 | /* | |
6107 | * This function implements pieces of two sequences from BSpec: | |
6108 | * - Sequence for display software to disable LCPLL | |
6109 | * - Sequence for display software to allow package C8+ | |
6110 | * The steps implemented here are just the steps that actually touch the LCPLL | |
6111 | * register. Callers should take care of disabling all the display engine | |
6112 | * functions, doing the mode unset, fixing interrupts, etc. | |
6113 | */ | |
6114 | void hsw_disable_lcpll(struct drm_i915_private *dev_priv, | |
6115 | bool switch_to_fclk, bool allow_power_down) | |
6116 | { | |
6117 | uint32_t val; | |
6118 | ||
6119 | assert_can_disable_lcpll(dev_priv); | |
6120 | ||
6121 | val = I915_READ(LCPLL_CTL); | |
6122 | ||
6123 | if (switch_to_fclk) { | |
6124 | val |= LCPLL_CD_SOURCE_FCLK; | |
6125 | I915_WRITE(LCPLL_CTL, val); | |
6126 | ||
6127 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
6128 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
6129 | DRM_ERROR("Switching to FCLK failed\n"); | |
6130 | ||
6131 | val = I915_READ(LCPLL_CTL); | |
6132 | } | |
6133 | ||
6134 | val |= LCPLL_PLL_DISABLE; | |
6135 | I915_WRITE(LCPLL_CTL, val); | |
6136 | POSTING_READ(LCPLL_CTL); | |
6137 | ||
6138 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
6139 | DRM_ERROR("LCPLL still locked\n"); | |
6140 | ||
6141 | val = I915_READ(D_COMP); | |
6142 | val |= D_COMP_COMP_DISABLE; | |
515b2392 PZ |
6143 | mutex_lock(&dev_priv->rps.hw_lock); |
6144 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | |
6145 | DRM_ERROR("Failed to disable D_COMP\n"); | |
6146 | mutex_unlock(&dev_priv->rps.hw_lock); | |
be256dc7 PZ |
6147 | POSTING_READ(D_COMP); |
6148 | ndelay(100); | |
6149 | ||
6150 | if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1)) | |
6151 | DRM_ERROR("D_COMP RCOMP still in progress\n"); | |
6152 | ||
6153 | if (allow_power_down) { | |
6154 | val = I915_READ(LCPLL_CTL); | |
6155 | val |= LCPLL_POWER_DOWN_ALLOW; | |
6156 | I915_WRITE(LCPLL_CTL, val); | |
6157 | POSTING_READ(LCPLL_CTL); | |
6158 | } | |
6159 | } | |
6160 | ||
6161 | /* | |
6162 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
6163 | * source. | |
6164 | */ | |
6165 | void hsw_restore_lcpll(struct drm_i915_private *dev_priv) | |
6166 | { | |
6167 | uint32_t val; | |
6168 | ||
6169 | val = I915_READ(LCPLL_CTL); | |
6170 | ||
6171 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
6172 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
6173 | return; | |
6174 | ||
215733fa PZ |
6175 | /* Make sure we're not on PC8 state before disabling PC8, otherwise |
6176 | * we'll hang the machine! */ | |
6177 | dev_priv->uncore.funcs.force_wake_get(dev_priv); | |
6178 | ||
be256dc7 PZ |
6179 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
6180 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
6181 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 6182 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
6183 | } |
6184 | ||
6185 | val = I915_READ(D_COMP); | |
6186 | val |= D_COMP_COMP_FORCE; | |
6187 | val &= ~D_COMP_COMP_DISABLE; | |
515b2392 PZ |
6188 | mutex_lock(&dev_priv->rps.hw_lock); |
6189 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val)) | |
6190 | DRM_ERROR("Failed to enable D_COMP\n"); | |
6191 | mutex_unlock(&dev_priv->rps.hw_lock); | |
35d8f2eb | 6192 | POSTING_READ(D_COMP); |
be256dc7 PZ |
6193 | |
6194 | val = I915_READ(LCPLL_CTL); | |
6195 | val &= ~LCPLL_PLL_DISABLE; | |
6196 | I915_WRITE(LCPLL_CTL, val); | |
6197 | ||
6198 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
6199 | DRM_ERROR("LCPLL not locked yet\n"); | |
6200 | ||
6201 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
6202 | val = I915_READ(LCPLL_CTL); | |
6203 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
6204 | I915_WRITE(LCPLL_CTL, val); | |
6205 | ||
6206 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
6207 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
6208 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
6209 | } | |
215733fa PZ |
6210 | |
6211 | dev_priv->uncore.funcs.force_wake_put(dev_priv); | |
be256dc7 PZ |
6212 | } |
6213 | ||
c67a470b PZ |
6214 | void hsw_enable_pc8_work(struct work_struct *__work) |
6215 | { | |
6216 | struct drm_i915_private *dev_priv = | |
6217 | container_of(to_delayed_work(__work), struct drm_i915_private, | |
6218 | pc8.enable_work); | |
6219 | struct drm_device *dev = dev_priv->dev; | |
6220 | uint32_t val; | |
6221 | ||
6222 | if (dev_priv->pc8.enabled) | |
6223 | return; | |
6224 | ||
6225 | DRM_DEBUG_KMS("Enabling package C8+\n"); | |
6226 | ||
6227 | dev_priv->pc8.enabled = true; | |
6228 | ||
6229 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6230 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6231 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
6232 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6233 | } | |
6234 | ||
6235 | lpt_disable_clkout_dp(dev); | |
6236 | hsw_pc8_disable_interrupts(dev); | |
6237 | hsw_disable_lcpll(dev_priv, true, true); | |
6238 | } | |
6239 | ||
6240 | static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6241 | { | |
6242 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6243 | WARN(dev_priv->pc8.disable_count < 1, | |
6244 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6245 | ||
6246 | dev_priv->pc8.disable_count--; | |
6247 | if (dev_priv->pc8.disable_count != 0) | |
6248 | return; | |
6249 | ||
6250 | schedule_delayed_work(&dev_priv->pc8.enable_work, | |
90058745 | 6251 | msecs_to_jiffies(i915_pc8_timeout)); |
c67a470b PZ |
6252 | } |
6253 | ||
6254 | static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
6255 | { | |
6256 | struct drm_device *dev = dev_priv->dev; | |
6257 | uint32_t val; | |
6258 | ||
6259 | WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock)); | |
6260 | WARN(dev_priv->pc8.disable_count < 0, | |
6261 | "pc8.disable_count: %d\n", dev_priv->pc8.disable_count); | |
6262 | ||
6263 | dev_priv->pc8.disable_count++; | |
6264 | if (dev_priv->pc8.disable_count != 1) | |
6265 | return; | |
6266 | ||
6267 | cancel_delayed_work_sync(&dev_priv->pc8.enable_work); | |
6268 | if (!dev_priv->pc8.enabled) | |
6269 | return; | |
6270 | ||
6271 | DRM_DEBUG_KMS("Disabling package C8+\n"); | |
6272 | ||
6273 | hsw_restore_lcpll(dev_priv); | |
6274 | hsw_pc8_restore_interrupts(dev); | |
6275 | lpt_init_pch_refclk(dev); | |
6276 | ||
6277 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6278 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6279 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
6280 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6281 | } | |
6282 | ||
6283 | intel_prepare_ddi(dev); | |
6284 | i915_gem_init_swizzling(dev); | |
6285 | mutex_lock(&dev_priv->rps.hw_lock); | |
6286 | gen6_update_ring_freq(dev); | |
6287 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6288 | dev_priv->pc8.enabled = false; | |
6289 | } | |
6290 | ||
6291 | void hsw_enable_package_c8(struct drm_i915_private *dev_priv) | |
6292 | { | |
6293 | mutex_lock(&dev_priv->pc8.lock); | |
6294 | __hsw_enable_package_c8(dev_priv); | |
6295 | mutex_unlock(&dev_priv->pc8.lock); | |
6296 | } | |
6297 | ||
6298 | void hsw_disable_package_c8(struct drm_i915_private *dev_priv) | |
6299 | { | |
6300 | mutex_lock(&dev_priv->pc8.lock); | |
6301 | __hsw_disable_package_c8(dev_priv); | |
6302 | mutex_unlock(&dev_priv->pc8.lock); | |
6303 | } | |
6304 | ||
6305 | static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv) | |
6306 | { | |
6307 | struct drm_device *dev = dev_priv->dev; | |
6308 | struct intel_crtc *crtc; | |
6309 | uint32_t val; | |
6310 | ||
6311 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) | |
6312 | if (crtc->base.enabled) | |
6313 | return false; | |
6314 | ||
6315 | /* This case is still possible since we have the i915.disable_power_well | |
6316 | * parameter and also the KVMr or something else might be requesting the | |
6317 | * power well. */ | |
6318 | val = I915_READ(HSW_PWR_WELL_DRIVER); | |
6319 | if (val != 0) { | |
6320 | DRM_DEBUG_KMS("Not enabling PC8: power well on\n"); | |
6321 | return false; | |
6322 | } | |
6323 | ||
6324 | return true; | |
6325 | } | |
6326 | ||
6327 | /* Since we're called from modeset_global_resources there's no way to | |
6328 | * symmetrically increase and decrease the refcount, so we use | |
6329 | * dev_priv->pc8.requirements_met to track whether we already have the refcount | |
6330 | * or not. | |
6331 | */ | |
6332 | static void hsw_update_package_c8(struct drm_device *dev) | |
6333 | { | |
6334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6335 | bool allow; | |
6336 | ||
6337 | if (!i915_enable_pc8) | |
6338 | return; | |
6339 | ||
6340 | mutex_lock(&dev_priv->pc8.lock); | |
6341 | ||
6342 | allow = hsw_can_enable_package_c8(dev_priv); | |
6343 | ||
6344 | if (allow == dev_priv->pc8.requirements_met) | |
6345 | goto done; | |
6346 | ||
6347 | dev_priv->pc8.requirements_met = allow; | |
6348 | ||
6349 | if (allow) | |
6350 | __hsw_enable_package_c8(dev_priv); | |
6351 | else | |
6352 | __hsw_disable_package_c8(dev_priv); | |
6353 | ||
6354 | done: | |
6355 | mutex_unlock(&dev_priv->pc8.lock); | |
6356 | } | |
6357 | ||
6358 | static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv) | |
6359 | { | |
6360 | if (!dev_priv->pc8.gpu_idle) { | |
6361 | dev_priv->pc8.gpu_idle = true; | |
6362 | hsw_enable_package_c8(dev_priv); | |
6363 | } | |
6364 | } | |
6365 | ||
6366 | static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv) | |
6367 | { | |
6368 | if (dev_priv->pc8.gpu_idle) { | |
6369 | dev_priv->pc8.gpu_idle = false; | |
6370 | hsw_disable_package_c8(dev_priv); | |
6371 | } | |
be256dc7 PZ |
6372 | } |
6373 | ||
d6dd9eb1 DV |
6374 | static void haswell_modeset_global_resources(struct drm_device *dev) |
6375 | { | |
d6dd9eb1 DV |
6376 | bool enable = false; |
6377 | struct intel_crtc *crtc; | |
d6dd9eb1 DV |
6378 | |
6379 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
e7a639c4 DV |
6380 | if (!crtc->base.enabled) |
6381 | continue; | |
d6dd9eb1 | 6382 | |
fd4daa9c | 6383 | if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled || |
e7a639c4 | 6384 | crtc->config.cpu_transcoder != TRANSCODER_EDP) |
d6dd9eb1 DV |
6385 | enable = true; |
6386 | } | |
6387 | ||
d6dd9eb1 | 6388 | intel_set_power_well(dev, enable); |
c67a470b PZ |
6389 | |
6390 | hsw_update_package_c8(dev); | |
d6dd9eb1 DV |
6391 | } |
6392 | ||
09b4ddf9 | 6393 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
6394 | int x, int y, |
6395 | struct drm_framebuffer *fb) | |
6396 | { | |
6397 | struct drm_device *dev = crtc->dev; | |
6398 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6399 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
09b4ddf9 | 6400 | int plane = intel_crtc->plane; |
09b4ddf9 | 6401 | int ret; |
09b4ddf9 | 6402 | |
ff9a6750 | 6403 | if (!intel_ddi_pll_mode_set(crtc)) |
6441ab5f PZ |
6404 | return -EINVAL; |
6405 | ||
03afc4a2 DV |
6406 | if (intel_crtc->config.has_dp_encoder) |
6407 | intel_dp_set_m_n(intel_crtc); | |
09b4ddf9 PZ |
6408 | |
6409 | intel_crtc->lowfreq_avail = false; | |
09b4ddf9 | 6410 | |
8a654f3b | 6411 | intel_set_pipe_timings(intel_crtc); |
09b4ddf9 | 6412 | |
ca3a0ff8 | 6413 | if (intel_crtc->config.has_pch_encoder) { |
ca3a0ff8 DV |
6414 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6415 | &intel_crtc->config.fdi_m_n); | |
6416 | } | |
09b4ddf9 | 6417 | |
6ff93609 | 6418 | haswell_set_pipeconf(crtc); |
09b4ddf9 | 6419 | |
50f3b016 | 6420 | intel_set_pipe_csc(crtc); |
86d3efce | 6421 | |
09b4ddf9 | 6422 | /* Set up the display plane register */ |
86d3efce | 6423 | I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); |
09b4ddf9 PZ |
6424 | POSTING_READ(DSPCNTR(plane)); |
6425 | ||
6426 | ret = intel_pipe_set_base(crtc, x, y, fb); | |
6427 | ||
1f803ee5 | 6428 | return ret; |
79e53945 JB |
6429 | } |
6430 | ||
0e8ffe1b DV |
6431 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
6432 | struct intel_crtc_config *pipe_config) | |
6433 | { | |
6434 | struct drm_device *dev = crtc->base.dev; | |
6435 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 6436 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
6437 | uint32_t tmp; |
6438 | ||
e143a21c | 6439 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
6440 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
6441 | ||
eccb140b DV |
6442 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
6443 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
6444 | enum pipe trans_edp_pipe; | |
6445 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
6446 | default: | |
6447 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
6448 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
6449 | case TRANS_DDI_EDP_INPUT_A_ON: | |
6450 | trans_edp_pipe = PIPE_A; | |
6451 | break; | |
6452 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
6453 | trans_edp_pipe = PIPE_B; | |
6454 | break; | |
6455 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
6456 | trans_edp_pipe = PIPE_C; | |
6457 | break; | |
6458 | } | |
6459 | ||
6460 | if (trans_edp_pipe == crtc->pipe) | |
6461 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
6462 | } | |
6463 | ||
b97186f0 | 6464 | if (!intel_display_power_enabled(dev, |
eccb140b | 6465 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
6466 | return false; |
6467 | ||
eccb140b | 6468 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
6469 | if (!(tmp & PIPECONF_ENABLE)) |
6470 | return false; | |
6471 | ||
88adfff1 | 6472 | /* |
f196e6be | 6473 | * Haswell has only FDI/PCH transcoder A. It is which is connected to |
88adfff1 DV |
6474 | * DDI E. So just check whether this pipe is wired to DDI E and whether |
6475 | * the PCH transcoder is on. | |
6476 | */ | |
eccb140b | 6477 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); |
88adfff1 | 6478 | if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) && |
ab9412ba | 6479 | I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
88adfff1 DV |
6480 | pipe_config->has_pch_encoder = true; |
6481 | ||
627eb5a3 DV |
6482 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); |
6483 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
6484 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
6485 | |
6486 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
627eb5a3 DV |
6487 | } |
6488 | ||
1bd1bd80 DV |
6489 | intel_get_pipe_timings(crtc, pipe_config); |
6490 | ||
2fa2fe9a DV |
6491 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
6492 | if (intel_display_power_enabled(dev, pfit_domain)) | |
6493 | ironlake_get_pfit_config(crtc, pipe_config); | |
88adfff1 | 6494 | |
42db64ef PZ |
6495 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
6496 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
6497 | ||
6c49f241 DV |
6498 | pipe_config->pixel_multiplier = 1; |
6499 | ||
0e8ffe1b DV |
6500 | return true; |
6501 | } | |
6502 | ||
f564048e | 6503 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 6504 | int x, int y, |
94352cf9 | 6505 | struct drm_framebuffer *fb) |
f564048e EA |
6506 | { |
6507 | struct drm_device *dev = crtc->dev; | |
6508 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9256aa19 | 6509 | struct intel_encoder *encoder; |
0b701d27 | 6510 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b8cecdf5 | 6511 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; |
0b701d27 | 6512 | int pipe = intel_crtc->pipe; |
f564048e EA |
6513 | int ret; |
6514 | ||
0b701d27 | 6515 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 6516 | |
b8cecdf5 DV |
6517 | ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb); |
6518 | ||
79e53945 | 6519 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 6520 | |
9256aa19 DV |
6521 | if (ret != 0) |
6522 | return ret; | |
6523 | ||
6524 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
6525 | DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", | |
6526 | encoder->base.base.id, | |
6527 | drm_get_encoder_name(&encoder->base), | |
6528 | mode->base.id, mode->name); | |
36f2d1f1 | 6529 | encoder->mode_set(encoder); |
9256aa19 DV |
6530 | } |
6531 | ||
6532 | return 0; | |
79e53945 JB |
6533 | } |
6534 | ||
3a9627f4 WF |
6535 | static bool intel_eld_uptodate(struct drm_connector *connector, |
6536 | int reg_eldv, uint32_t bits_eldv, | |
6537 | int reg_elda, uint32_t bits_elda, | |
6538 | int reg_edid) | |
6539 | { | |
6540 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6541 | uint8_t *eld = connector->eld; | |
6542 | uint32_t i; | |
6543 | ||
6544 | i = I915_READ(reg_eldv); | |
6545 | i &= bits_eldv; | |
6546 | ||
6547 | if (!eld[0]) | |
6548 | return !i; | |
6549 | ||
6550 | if (!i) | |
6551 | return false; | |
6552 | ||
6553 | i = I915_READ(reg_elda); | |
6554 | i &= ~bits_elda; | |
6555 | I915_WRITE(reg_elda, i); | |
6556 | ||
6557 | for (i = 0; i < eld[2]; i++) | |
6558 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
6559 | return false; | |
6560 | ||
6561 | return true; | |
6562 | } | |
6563 | ||
e0dac65e WF |
6564 | static void g4x_write_eld(struct drm_connector *connector, |
6565 | struct drm_crtc *crtc) | |
6566 | { | |
6567 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6568 | uint8_t *eld = connector->eld; | |
6569 | uint32_t eldv; | |
6570 | uint32_t len; | |
6571 | uint32_t i; | |
6572 | ||
6573 | i = I915_READ(G4X_AUD_VID_DID); | |
6574 | ||
6575 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
6576 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
6577 | else | |
6578 | eldv = G4X_ELDV_DEVCTG; | |
6579 | ||
3a9627f4 WF |
6580 | if (intel_eld_uptodate(connector, |
6581 | G4X_AUD_CNTL_ST, eldv, | |
6582 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
6583 | G4X_HDMIW_HDMIEDID)) | |
6584 | return; | |
6585 | ||
e0dac65e WF |
6586 | i = I915_READ(G4X_AUD_CNTL_ST); |
6587 | i &= ~(eldv | G4X_ELD_ADDR); | |
6588 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
6589 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
6590 | ||
6591 | if (!eld[0]) | |
6592 | return; | |
6593 | ||
6594 | len = min_t(uint8_t, eld[2], len); | |
6595 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6596 | for (i = 0; i < len; i++) | |
6597 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
6598 | ||
6599 | i = I915_READ(G4X_AUD_CNTL_ST); | |
6600 | i |= eldv; | |
6601 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
6602 | } | |
6603 | ||
83358c85 WX |
6604 | static void haswell_write_eld(struct drm_connector *connector, |
6605 | struct drm_crtc *crtc) | |
6606 | { | |
6607 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6608 | uint8_t *eld = connector->eld; | |
6609 | struct drm_device *dev = crtc->dev; | |
7b9f35a6 | 6610 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83358c85 WX |
6611 | uint32_t eldv; |
6612 | uint32_t i; | |
6613 | int len; | |
6614 | int pipe = to_intel_crtc(crtc)->pipe; | |
6615 | int tmp; | |
6616 | ||
6617 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
6618 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
6619 | int aud_config = HSW_AUD_CFG(pipe); | |
6620 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
6621 | ||
6622 | ||
6623 | DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); | |
6624 | ||
6625 | /* Audio output enable */ | |
6626 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
6627 | tmp = I915_READ(aud_cntrl_st2); | |
6628 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
6629 | I915_WRITE(aud_cntrl_st2, tmp); | |
6630 | ||
6631 | /* Wait for 1 vertical blank */ | |
6632 | intel_wait_for_vblank(dev, pipe); | |
6633 | ||
6634 | /* Set ELD valid state */ | |
6635 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 6636 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
6637 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
6638 | I915_WRITE(aud_cntrl_st2, tmp); | |
6639 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 6640 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
6641 | |
6642 | /* Enable HDMI mode */ | |
6643 | tmp = I915_READ(aud_config); | |
7e7cb34f | 6644 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
6645 | /* clear N_programing_enable and N_value_index */ |
6646 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
6647 | I915_WRITE(aud_config, tmp); | |
6648 | ||
6649 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
6650 | ||
6651 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
7b9f35a6 | 6652 | intel_crtc->eld_vld = true; |
83358c85 WX |
6653 | |
6654 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
6655 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
6656 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
6657 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
6658 | } else | |
6659 | I915_WRITE(aud_config, 0); | |
6660 | ||
6661 | if (intel_eld_uptodate(connector, | |
6662 | aud_cntrl_st2, eldv, | |
6663 | aud_cntl_st, IBX_ELD_ADDRESS, | |
6664 | hdmiw_hdmiedid)) | |
6665 | return; | |
6666 | ||
6667 | i = I915_READ(aud_cntrl_st2); | |
6668 | i &= ~eldv; | |
6669 | I915_WRITE(aud_cntrl_st2, i); | |
6670 | ||
6671 | if (!eld[0]) | |
6672 | return; | |
6673 | ||
6674 | i = I915_READ(aud_cntl_st); | |
6675 | i &= ~IBX_ELD_ADDRESS; | |
6676 | I915_WRITE(aud_cntl_st, i); | |
6677 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
6678 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
6679 | ||
6680 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
6681 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6682 | for (i = 0; i < len; i++) | |
6683 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
6684 | ||
6685 | i = I915_READ(aud_cntrl_st2); | |
6686 | i |= eldv; | |
6687 | I915_WRITE(aud_cntrl_st2, i); | |
6688 | ||
6689 | } | |
6690 | ||
e0dac65e WF |
6691 | static void ironlake_write_eld(struct drm_connector *connector, |
6692 | struct drm_crtc *crtc) | |
6693 | { | |
6694 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6695 | uint8_t *eld = connector->eld; | |
6696 | uint32_t eldv; | |
6697 | uint32_t i; | |
6698 | int len; | |
6699 | int hdmiw_hdmiedid; | |
b6daa025 | 6700 | int aud_config; |
e0dac65e WF |
6701 | int aud_cntl_st; |
6702 | int aud_cntrl_st2; | |
9b138a83 | 6703 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 6704 | |
b3f33cbf | 6705 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
6706 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
6707 | aud_config = IBX_AUD_CFG(pipe); | |
6708 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 6709 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
e0dac65e | 6710 | } else { |
9b138a83 WX |
6711 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
6712 | aud_config = CPT_AUD_CFG(pipe); | |
6713 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 6714 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
6715 | } |
6716 | ||
9b138a83 | 6717 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e WF |
6718 | |
6719 | i = I915_READ(aud_cntl_st); | |
9b138a83 | 6720 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ |
e0dac65e WF |
6721 | if (!i) { |
6722 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
6723 | /* operate blindly on all ports */ | |
1202b4c6 WF |
6724 | eldv = IBX_ELD_VALIDB; |
6725 | eldv |= IBX_ELD_VALIDB << 4; | |
6726 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 6727 | } else { |
2582a850 | 6728 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 6729 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
6730 | } |
6731 | ||
3a9627f4 WF |
6732 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
6733 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
6734 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 WF |
6735 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
6736 | } else | |
6737 | I915_WRITE(aud_config, 0); | |
e0dac65e | 6738 | |
3a9627f4 WF |
6739 | if (intel_eld_uptodate(connector, |
6740 | aud_cntrl_st2, eldv, | |
6741 | aud_cntl_st, IBX_ELD_ADDRESS, | |
6742 | hdmiw_hdmiedid)) | |
6743 | return; | |
6744 | ||
e0dac65e WF |
6745 | i = I915_READ(aud_cntrl_st2); |
6746 | i &= ~eldv; | |
6747 | I915_WRITE(aud_cntrl_st2, i); | |
6748 | ||
6749 | if (!eld[0]) | |
6750 | return; | |
6751 | ||
e0dac65e | 6752 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 6753 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
6754 | I915_WRITE(aud_cntl_st, i); |
6755 | ||
6756 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
6757 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6758 | for (i = 0; i < len; i++) | |
6759 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
6760 | ||
6761 | i = I915_READ(aud_cntrl_st2); | |
6762 | i |= eldv; | |
6763 | I915_WRITE(aud_cntrl_st2, i); | |
6764 | } | |
6765 | ||
6766 | void intel_write_eld(struct drm_encoder *encoder, | |
6767 | struct drm_display_mode *mode) | |
6768 | { | |
6769 | struct drm_crtc *crtc = encoder->crtc; | |
6770 | struct drm_connector *connector; | |
6771 | struct drm_device *dev = encoder->dev; | |
6772 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6773 | ||
6774 | connector = drm_select_eld(encoder, mode); | |
6775 | if (!connector) | |
6776 | return; | |
6777 | ||
6778 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
6779 | connector->base.id, | |
6780 | drm_get_connector_name(connector), | |
6781 | connector->encoder->base.id, | |
6782 | drm_get_encoder_name(connector->encoder)); | |
6783 | ||
6784 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
6785 | ||
6786 | if (dev_priv->display.write_eld) | |
6787 | dev_priv->display.write_eld(connector, crtc); | |
6788 | } | |
6789 | ||
79e53945 JB |
6790 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
6791 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
6792 | { | |
6793 | struct drm_device *dev = crtc->dev; | |
6794 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6795 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
42db64ef PZ |
6796 | enum pipe pipe = intel_crtc->pipe; |
6797 | int palreg = PALETTE(pipe); | |
79e53945 | 6798 | int i; |
42db64ef | 6799 | bool reenable_ips = false; |
79e53945 JB |
6800 | |
6801 | /* The clocks have to be on to load the palette. */ | |
aed3f09d | 6802 | if (!crtc->enabled || !intel_crtc->active) |
79e53945 JB |
6803 | return; |
6804 | ||
23538ef1 JN |
6805 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { |
6806 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
6807 | assert_dsi_pll_enabled(dev_priv); | |
6808 | else | |
6809 | assert_pll_enabled(dev_priv, pipe); | |
6810 | } | |
14420bd0 | 6811 | |
f2b115e6 | 6812 | /* use legacy palette for Ironlake */ |
bad720ff | 6813 | if (HAS_PCH_SPLIT(dev)) |
42db64ef PZ |
6814 | palreg = LGC_PALETTE(pipe); |
6815 | ||
6816 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
6817 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
6818 | */ | |
6819 | if (intel_crtc->config.ips_enabled && | |
6820 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == | |
6821 | GAMMA_MODE_MODE_SPLIT)) { | |
6822 | hsw_disable_ips(intel_crtc); | |
6823 | reenable_ips = true; | |
6824 | } | |
2c07245f | 6825 | |
79e53945 JB |
6826 | for (i = 0; i < 256; i++) { |
6827 | I915_WRITE(palreg + 4 * i, | |
6828 | (intel_crtc->lut_r[i] << 16) | | |
6829 | (intel_crtc->lut_g[i] << 8) | | |
6830 | intel_crtc->lut_b[i]); | |
6831 | } | |
42db64ef PZ |
6832 | |
6833 | if (reenable_ips) | |
6834 | hsw_enable_ips(intel_crtc); | |
79e53945 JB |
6835 | } |
6836 | ||
560b85bb CW |
6837 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
6838 | { | |
6839 | struct drm_device *dev = crtc->dev; | |
6840 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6841 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6842 | bool visible = base != 0; | |
6843 | u32 cntl; | |
6844 | ||
6845 | if (intel_crtc->cursor_visible == visible) | |
6846 | return; | |
6847 | ||
9db4a9c7 | 6848 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
6849 | if (visible) { |
6850 | /* On these chipsets we can only modify the base whilst | |
6851 | * the cursor is disabled. | |
6852 | */ | |
9db4a9c7 | 6853 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
6854 | |
6855 | cntl &= ~(CURSOR_FORMAT_MASK); | |
6856 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
6857 | cntl |= CURSOR_ENABLE | | |
6858 | CURSOR_GAMMA_ENABLE | | |
6859 | CURSOR_FORMAT_ARGB; | |
6860 | } else | |
6861 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 6862 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
6863 | |
6864 | intel_crtc->cursor_visible = visible; | |
6865 | } | |
6866 | ||
6867 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
6868 | { | |
6869 | struct drm_device *dev = crtc->dev; | |
6870 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6871 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6872 | int pipe = intel_crtc->pipe; | |
6873 | bool visible = base != 0; | |
6874 | ||
6875 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 6876 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
6877 | if (base) { |
6878 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
6879 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6880 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
6881 | } else { | |
6882 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6883 | cntl |= CURSOR_MODE_DISABLE; | |
6884 | } | |
9db4a9c7 | 6885 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
6886 | |
6887 | intel_crtc->cursor_visible = visible; | |
6888 | } | |
6889 | /* and commit changes on next vblank */ | |
9db4a9c7 | 6890 | I915_WRITE(CURBASE(pipe), base); |
560b85bb CW |
6891 | } |
6892 | ||
65a21cd6 JB |
6893 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
6894 | { | |
6895 | struct drm_device *dev = crtc->dev; | |
6896 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6897 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6898 | int pipe = intel_crtc->pipe; | |
6899 | bool visible = base != 0; | |
6900 | ||
6901 | if (intel_crtc->cursor_visible != visible) { | |
6902 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
6903 | if (base) { | |
6904 | cntl &= ~CURSOR_MODE; | |
6905 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6906 | } else { | |
6907 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6908 | cntl |= CURSOR_MODE_DISABLE; | |
6909 | } | |
1f5d76db | 6910 | if (IS_HASWELL(dev)) { |
86d3efce | 6911 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
1f5d76db PZ |
6912 | cntl &= ~CURSOR_TRICKLE_FEED_DISABLE; |
6913 | } | |
65a21cd6 JB |
6914 | I915_WRITE(CURCNTR_IVB(pipe), cntl); |
6915 | ||
6916 | intel_crtc->cursor_visible = visible; | |
6917 | } | |
6918 | /* and commit changes on next vblank */ | |
6919 | I915_WRITE(CURBASE_IVB(pipe), base); | |
6920 | } | |
6921 | ||
cda4b7d3 | 6922 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
6923 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
6924 | bool on) | |
cda4b7d3 CW |
6925 | { |
6926 | struct drm_device *dev = crtc->dev; | |
6927 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6928 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6929 | int pipe = intel_crtc->pipe; | |
6930 | int x = intel_crtc->cursor_x; | |
6931 | int y = intel_crtc->cursor_y; | |
d6e4db15 | 6932 | u32 base = 0, pos = 0; |
cda4b7d3 CW |
6933 | bool visible; |
6934 | ||
d6e4db15 | 6935 | if (on) |
cda4b7d3 | 6936 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 6937 | |
d6e4db15 VS |
6938 | if (x >= intel_crtc->config.pipe_src_w) |
6939 | base = 0; | |
6940 | ||
6941 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
6942 | base = 0; |
6943 | ||
6944 | if (x < 0) { | |
efc9064e | 6945 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
6946 | base = 0; |
6947 | ||
6948 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
6949 | x = -x; | |
6950 | } | |
6951 | pos |= x << CURSOR_X_SHIFT; | |
6952 | ||
6953 | if (y < 0) { | |
efc9064e | 6954 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
6955 | base = 0; |
6956 | ||
6957 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
6958 | y = -y; | |
6959 | } | |
6960 | pos |= y << CURSOR_Y_SHIFT; | |
6961 | ||
6962 | visible = base != 0; | |
560b85bb | 6963 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
6964 | return; |
6965 | ||
0cd83aa9 | 6966 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
65a21cd6 JB |
6967 | I915_WRITE(CURPOS_IVB(pipe), pos); |
6968 | ivb_update_cursor(crtc, base); | |
6969 | } else { | |
6970 | I915_WRITE(CURPOS(pipe), pos); | |
6971 | if (IS_845G(dev) || IS_I865G(dev)) | |
6972 | i845_update_cursor(crtc, base); | |
6973 | else | |
6974 | i9xx_update_cursor(crtc, base); | |
6975 | } | |
cda4b7d3 CW |
6976 | } |
6977 | ||
79e53945 | 6978 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 6979 | struct drm_file *file, |
79e53945 JB |
6980 | uint32_t handle, |
6981 | uint32_t width, uint32_t height) | |
6982 | { | |
6983 | struct drm_device *dev = crtc->dev; | |
6984 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6985 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 6986 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 6987 | uint32_t addr; |
3f8bc370 | 6988 | int ret; |
79e53945 | 6989 | |
79e53945 JB |
6990 | /* if we want to turn off the cursor ignore width and height */ |
6991 | if (!handle) { | |
28c97730 | 6992 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 6993 | addr = 0; |
05394f39 | 6994 | obj = NULL; |
5004417d | 6995 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 6996 | goto finish; |
79e53945 JB |
6997 | } |
6998 | ||
6999 | /* Currently we only support 64x64 cursors */ | |
7000 | if (width != 64 || height != 64) { | |
7001 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
7002 | return -EINVAL; | |
7003 | } | |
7004 | ||
05394f39 | 7005 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 7006 | if (&obj->base == NULL) |
79e53945 JB |
7007 | return -ENOENT; |
7008 | ||
05394f39 | 7009 | if (obj->base.size < width * height * 4) { |
79e53945 | 7010 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
7011 | ret = -ENOMEM; |
7012 | goto fail; | |
79e53945 JB |
7013 | } |
7014 | ||
71acb5eb | 7015 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 7016 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 7017 | if (!dev_priv->info->cursor_needs_physical) { |
693db184 CW |
7018 | unsigned alignment; |
7019 | ||
d9e86c0e CW |
7020 | if (obj->tiling_mode) { |
7021 | DRM_ERROR("cursor cannot be tiled\n"); | |
7022 | ret = -EINVAL; | |
7023 | goto fail_locked; | |
7024 | } | |
7025 | ||
693db184 CW |
7026 | /* Note that the w/a also requires 2 PTE of padding following |
7027 | * the bo. We currently fill all unused PTE with the shadow | |
7028 | * page and so we should always have valid PTE following the | |
7029 | * cursor preventing the VT-d warning. | |
7030 | */ | |
7031 | alignment = 0; | |
7032 | if (need_vtd_wa(dev)) | |
7033 | alignment = 64*1024; | |
7034 | ||
7035 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb CW |
7036 | if (ret) { |
7037 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 7038 | goto fail_locked; |
e7b526bb CW |
7039 | } |
7040 | ||
d9e86c0e CW |
7041 | ret = i915_gem_object_put_fence(obj); |
7042 | if (ret) { | |
2da3b9b9 | 7043 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
7044 | goto fail_unpin; |
7045 | } | |
7046 | ||
f343c5f6 | 7047 | addr = i915_gem_obj_ggtt_offset(obj); |
71acb5eb | 7048 | } else { |
6eeefaf3 | 7049 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 7050 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
7051 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
7052 | align); | |
71acb5eb DA |
7053 | if (ret) { |
7054 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 7055 | goto fail_locked; |
71acb5eb | 7056 | } |
05394f39 | 7057 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
7058 | } |
7059 | ||
a6c45cf0 | 7060 | if (IS_GEN2(dev)) |
14b60391 JB |
7061 | I915_WRITE(CURSIZE, (height << 12) | width); |
7062 | ||
3f8bc370 | 7063 | finish: |
3f8bc370 | 7064 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 7065 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 7066 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
7067 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
7068 | } else | |
cc98b413 | 7069 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
05394f39 | 7070 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 7071 | } |
80824003 | 7072 | |
7f9872e0 | 7073 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
7074 | |
7075 | intel_crtc->cursor_addr = addr; | |
05394f39 | 7076 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
7077 | intel_crtc->cursor_width = width; |
7078 | intel_crtc->cursor_height = height; | |
7079 | ||
f2f5f771 VS |
7080 | if (intel_crtc->active) |
7081 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
3f8bc370 | 7082 | |
79e53945 | 7083 | return 0; |
e7b526bb | 7084 | fail_unpin: |
cc98b413 | 7085 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 7086 | fail_locked: |
34b8686e | 7087 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 7088 | fail: |
05394f39 | 7089 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 7090 | return ret; |
79e53945 JB |
7091 | } |
7092 | ||
7093 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
7094 | { | |
79e53945 | 7095 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7096 | |
cda4b7d3 CW |
7097 | intel_crtc->cursor_x = x; |
7098 | intel_crtc->cursor_y = y; | |
652c393a | 7099 | |
f2f5f771 VS |
7100 | if (intel_crtc->active) |
7101 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); | |
79e53945 JB |
7102 | |
7103 | return 0; | |
7104 | } | |
7105 | ||
7106 | /** Sets the color ramps on behalf of RandR */ | |
7107 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
7108 | u16 blue, int regno) | |
7109 | { | |
7110 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7111 | ||
7112 | intel_crtc->lut_r[regno] = red >> 8; | |
7113 | intel_crtc->lut_g[regno] = green >> 8; | |
7114 | intel_crtc->lut_b[regno] = blue >> 8; | |
7115 | } | |
7116 | ||
b8c00ac5 DA |
7117 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
7118 | u16 *blue, int regno) | |
7119 | { | |
7120 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7121 | ||
7122 | *red = intel_crtc->lut_r[regno] << 8; | |
7123 | *green = intel_crtc->lut_g[regno] << 8; | |
7124 | *blue = intel_crtc->lut_b[regno] << 8; | |
7125 | } | |
7126 | ||
79e53945 | 7127 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 7128 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 7129 | { |
7203425a | 7130 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 7131 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 7132 | |
7203425a | 7133 | for (i = start; i < end; i++) { |
79e53945 JB |
7134 | intel_crtc->lut_r[i] = red[i] >> 8; |
7135 | intel_crtc->lut_g[i] = green[i] >> 8; | |
7136 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
7137 | } | |
7138 | ||
7139 | intel_crtc_load_lut(crtc); | |
7140 | } | |
7141 | ||
79e53945 JB |
7142 | /* VESA 640x480x72Hz mode to set on the pipe */ |
7143 | static struct drm_display_mode load_detect_mode = { | |
7144 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
7145 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
7146 | }; | |
7147 | ||
d2dff872 CW |
7148 | static struct drm_framebuffer * |
7149 | intel_framebuffer_create(struct drm_device *dev, | |
308e5bcb | 7150 | struct drm_mode_fb_cmd2 *mode_cmd, |
d2dff872 CW |
7151 | struct drm_i915_gem_object *obj) |
7152 | { | |
7153 | struct intel_framebuffer *intel_fb; | |
7154 | int ret; | |
7155 | ||
7156 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
7157 | if (!intel_fb) { | |
7158 | drm_gem_object_unreference_unlocked(&obj->base); | |
7159 | return ERR_PTR(-ENOMEM); | |
7160 | } | |
7161 | ||
7162 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
7163 | if (ret) { | |
7164 | drm_gem_object_unreference_unlocked(&obj->base); | |
7165 | kfree(intel_fb); | |
7166 | return ERR_PTR(ret); | |
7167 | } | |
7168 | ||
7169 | return &intel_fb->base; | |
7170 | } | |
7171 | ||
7172 | static u32 | |
7173 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
7174 | { | |
7175 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
7176 | return ALIGN(pitch, 64); | |
7177 | } | |
7178 | ||
7179 | static u32 | |
7180 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
7181 | { | |
7182 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
7183 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
7184 | } | |
7185 | ||
7186 | static struct drm_framebuffer * | |
7187 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
7188 | struct drm_display_mode *mode, | |
7189 | int depth, int bpp) | |
7190 | { | |
7191 | struct drm_i915_gem_object *obj; | |
0fed39bd | 7192 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
7193 | |
7194 | obj = i915_gem_alloc_object(dev, | |
7195 | intel_framebuffer_size_for_mode(mode, bpp)); | |
7196 | if (obj == NULL) | |
7197 | return ERR_PTR(-ENOMEM); | |
7198 | ||
7199 | mode_cmd.width = mode->hdisplay; | |
7200 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
7201 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
7202 | bpp); | |
5ca0c34a | 7203 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
7204 | |
7205 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
7206 | } | |
7207 | ||
7208 | static struct drm_framebuffer * | |
7209 | mode_fits_in_fbdev(struct drm_device *dev, | |
7210 | struct drm_display_mode *mode) | |
7211 | { | |
7212 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7213 | struct drm_i915_gem_object *obj; | |
7214 | struct drm_framebuffer *fb; | |
7215 | ||
7216 | if (dev_priv->fbdev == NULL) | |
7217 | return NULL; | |
7218 | ||
7219 | obj = dev_priv->fbdev->ifb.obj; | |
7220 | if (obj == NULL) | |
7221 | return NULL; | |
7222 | ||
7223 | fb = &dev_priv->fbdev->ifb.base; | |
01f2c773 VS |
7224 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
7225 | fb->bits_per_pixel)) | |
d2dff872 CW |
7226 | return NULL; |
7227 | ||
01f2c773 | 7228 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
7229 | return NULL; |
7230 | ||
7231 | return fb; | |
7232 | } | |
7233 | ||
d2434ab7 | 7234 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 7235 | struct drm_display_mode *mode, |
8261b191 | 7236 | struct intel_load_detect_pipe *old) |
79e53945 JB |
7237 | { |
7238 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
7239 | struct intel_encoder *intel_encoder = |
7240 | intel_attached_encoder(connector); | |
79e53945 | 7241 | struct drm_crtc *possible_crtc; |
4ef69c7a | 7242 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
7243 | struct drm_crtc *crtc = NULL; |
7244 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 7245 | struct drm_framebuffer *fb; |
79e53945 JB |
7246 | int i = -1; |
7247 | ||
d2dff872 CW |
7248 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7249 | connector->base.id, drm_get_connector_name(connector), | |
7250 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7251 | ||
79e53945 JB |
7252 | /* |
7253 | * Algorithm gets a little messy: | |
7a5e4805 | 7254 | * |
79e53945 JB |
7255 | * - if the connector already has an assigned crtc, use it (but make |
7256 | * sure it's on first) | |
7a5e4805 | 7257 | * |
79e53945 JB |
7258 | * - try to find the first unused crtc that can drive this connector, |
7259 | * and use that if we find one | |
79e53945 JB |
7260 | */ |
7261 | ||
7262 | /* See if we already have a CRTC for this connector */ | |
7263 | if (encoder->crtc) { | |
7264 | crtc = encoder->crtc; | |
8261b191 | 7265 | |
7b24056b DV |
7266 | mutex_lock(&crtc->mutex); |
7267 | ||
24218aac | 7268 | old->dpms_mode = connector->dpms; |
8261b191 CW |
7269 | old->load_detect_temp = false; |
7270 | ||
7271 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
7272 | if (connector->dpms != DRM_MODE_DPMS_ON) |
7273 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 7274 | |
7173188d | 7275 | return true; |
79e53945 JB |
7276 | } |
7277 | ||
7278 | /* Find an unused one (if possible) */ | |
7279 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
7280 | i++; | |
7281 | if (!(encoder->possible_crtcs & (1 << i))) | |
7282 | continue; | |
7283 | if (!possible_crtc->enabled) { | |
7284 | crtc = possible_crtc; | |
7285 | break; | |
7286 | } | |
79e53945 JB |
7287 | } |
7288 | ||
7289 | /* | |
7290 | * If we didn't find an unused CRTC, don't use any. | |
7291 | */ | |
7292 | if (!crtc) { | |
7173188d CW |
7293 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
7294 | return false; | |
79e53945 JB |
7295 | } |
7296 | ||
7b24056b | 7297 | mutex_lock(&crtc->mutex); |
fc303101 DV |
7298 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
7299 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
7300 | |
7301 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 7302 | old->dpms_mode = connector->dpms; |
8261b191 | 7303 | old->load_detect_temp = true; |
d2dff872 | 7304 | old->release_fb = NULL; |
79e53945 | 7305 | |
6492711d CW |
7306 | if (!mode) |
7307 | mode = &load_detect_mode; | |
79e53945 | 7308 | |
d2dff872 CW |
7309 | /* We need a framebuffer large enough to accommodate all accesses |
7310 | * that the plane may generate whilst we perform load detection. | |
7311 | * We can not rely on the fbcon either being present (we get called | |
7312 | * during its initialisation to detect all boot displays, or it may | |
7313 | * not even exist) or that it is large enough to satisfy the | |
7314 | * requested mode. | |
7315 | */ | |
94352cf9 DV |
7316 | fb = mode_fits_in_fbdev(dev, mode); |
7317 | if (fb == NULL) { | |
d2dff872 | 7318 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
7319 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
7320 | old->release_fb = fb; | |
d2dff872 CW |
7321 | } else |
7322 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 7323 | if (IS_ERR(fb)) { |
d2dff872 | 7324 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
7b24056b | 7325 | mutex_unlock(&crtc->mutex); |
0e8b3d3e | 7326 | return false; |
79e53945 | 7327 | } |
79e53945 | 7328 | |
c0c36b94 | 7329 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 7330 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
7331 | if (old->release_fb) |
7332 | old->release_fb->funcs->destroy(old->release_fb); | |
7b24056b | 7333 | mutex_unlock(&crtc->mutex); |
0e8b3d3e | 7334 | return false; |
79e53945 | 7335 | } |
7173188d | 7336 | |
79e53945 | 7337 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 7338 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 7339 | return true; |
79e53945 JB |
7340 | } |
7341 | ||
d2434ab7 | 7342 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
8261b191 | 7343 | struct intel_load_detect_pipe *old) |
79e53945 | 7344 | { |
d2434ab7 DV |
7345 | struct intel_encoder *intel_encoder = |
7346 | intel_attached_encoder(connector); | |
4ef69c7a | 7347 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 7348 | struct drm_crtc *crtc = encoder->crtc; |
79e53945 | 7349 | |
d2dff872 CW |
7350 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
7351 | connector->base.id, drm_get_connector_name(connector), | |
7352 | encoder->base.id, drm_get_encoder_name(encoder)); | |
7353 | ||
8261b191 | 7354 | if (old->load_detect_temp) { |
fc303101 DV |
7355 | to_intel_connector(connector)->new_encoder = NULL; |
7356 | intel_encoder->new_crtc = NULL; | |
7357 | intel_set_mode(crtc, NULL, 0, 0, NULL); | |
d2dff872 | 7358 | |
36206361 DV |
7359 | if (old->release_fb) { |
7360 | drm_framebuffer_unregister_private(old->release_fb); | |
7361 | drm_framebuffer_unreference(old->release_fb); | |
7362 | } | |
d2dff872 | 7363 | |
67c96400 | 7364 | mutex_unlock(&crtc->mutex); |
0622a53c | 7365 | return; |
79e53945 JB |
7366 | } |
7367 | ||
c751ce4f | 7368 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
7369 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
7370 | connector->funcs->dpms(connector, old->dpms_mode); | |
7b24056b DV |
7371 | |
7372 | mutex_unlock(&crtc->mutex); | |
79e53945 JB |
7373 | } |
7374 | ||
da4a1efa VS |
7375 | static int i9xx_pll_refclk(struct drm_device *dev, |
7376 | const struct intel_crtc_config *pipe_config) | |
7377 | { | |
7378 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7379 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
7380 | ||
7381 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
7382 | return dev_priv->vbt.lvds_ssc_freq * 1000; | |
7383 | else if (HAS_PCH_SPLIT(dev)) | |
7384 | return 120000; | |
7385 | else if (!IS_GEN2(dev)) | |
7386 | return 96000; | |
7387 | else | |
7388 | return 48000; | |
7389 | } | |
7390 | ||
79e53945 | 7391 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
7392 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
7393 | struct intel_crtc_config *pipe_config) | |
79e53945 | 7394 | { |
f1f644dc | 7395 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7396 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 7397 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 7398 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
7399 | u32 fp; |
7400 | intel_clock_t clock; | |
da4a1efa | 7401 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
7402 | |
7403 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 7404 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 7405 | else |
293623f7 | 7406 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
7407 | |
7408 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
7409 | if (IS_PINEVIEW(dev)) { |
7410 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
7411 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
7412 | } else { |
7413 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
7414 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
7415 | } | |
7416 | ||
a6c45cf0 | 7417 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
7418 | if (IS_PINEVIEW(dev)) |
7419 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
7420 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
7421 | else |
7422 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
7423 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
7424 | ||
7425 | switch (dpll & DPLL_MODE_MASK) { | |
7426 | case DPLLB_MODE_DAC_SERIAL: | |
7427 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
7428 | 5 : 10; | |
7429 | break; | |
7430 | case DPLLB_MODE_LVDS: | |
7431 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
7432 | 7 : 14; | |
7433 | break; | |
7434 | default: | |
28c97730 | 7435 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 7436 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 7437 | return; |
79e53945 JB |
7438 | } |
7439 | ||
ac58c3f0 | 7440 | if (IS_PINEVIEW(dev)) |
da4a1efa | 7441 | pineview_clock(refclk, &clock); |
ac58c3f0 | 7442 | else |
da4a1efa | 7443 | i9xx_clock(refclk, &clock); |
79e53945 JB |
7444 | } else { |
7445 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
7446 | ||
7447 | if (is_lvds) { | |
7448 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
7449 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
7450 | clock.p2 = 14; | |
79e53945 JB |
7451 | } else { |
7452 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
7453 | clock.p1 = 2; | |
7454 | else { | |
7455 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
7456 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
7457 | } | |
7458 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
7459 | clock.p2 = 4; | |
7460 | else | |
7461 | clock.p2 = 2; | |
79e53945 | 7462 | } |
da4a1efa VS |
7463 | |
7464 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
7465 | } |
7466 | ||
18442d08 VS |
7467 | /* |
7468 | * This value includes pixel_multiplier. We will use | |
7469 | * port_clock to compute adjusted_mode.clock in the | |
7470 | * encoder's get_config() function. | |
7471 | */ | |
7472 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
7473 | } |
7474 | ||
6878da05 VS |
7475 | int intel_dotclock_calculate(int link_freq, |
7476 | const struct intel_link_m_n *m_n) | |
f1f644dc | 7477 | { |
f1f644dc JB |
7478 | /* |
7479 | * The calculation for the data clock is: | |
1041a02f | 7480 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 7481 | * But we want to avoid losing precison if possible, so: |
1041a02f | 7482 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
7483 | * |
7484 | * and the link clock is simpler: | |
1041a02f | 7485 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
7486 | */ |
7487 | ||
6878da05 VS |
7488 | if (!m_n->link_n) |
7489 | return 0; | |
f1f644dc | 7490 | |
6878da05 VS |
7491 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
7492 | } | |
f1f644dc | 7493 | |
18442d08 VS |
7494 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
7495 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
7496 | { |
7497 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 7498 | |
18442d08 VS |
7499 | /* read out port_clock from the DPLL */ |
7500 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 7501 | |
f1f644dc | 7502 | /* |
18442d08 VS |
7503 | * This value does not include pixel_multiplier. |
7504 | * We will check that port_clock and adjusted_mode.clock | |
7505 | * agree once we know their relationship in the encoder's | |
7506 | * get_config() function. | |
79e53945 | 7507 | */ |
18442d08 VS |
7508 | pipe_config->adjusted_mode.clock = |
7509 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, | |
7510 | &pipe_config->fdi_m_n); | |
79e53945 JB |
7511 | } |
7512 | ||
7513 | /** Returns the currently programmed mode of the given pipe. */ | |
7514 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
7515 | struct drm_crtc *crtc) | |
7516 | { | |
548f245b | 7517 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 7518 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 7519 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 7520 | struct drm_display_mode *mode; |
f1f644dc | 7521 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
7522 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
7523 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
7524 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
7525 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 7526 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
7527 | |
7528 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
7529 | if (!mode) | |
7530 | return NULL; | |
7531 | ||
f1f644dc JB |
7532 | /* |
7533 | * Construct a pipe_config sufficient for getting the clock info | |
7534 | * back out of crtc_clock_get. | |
7535 | * | |
7536 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
7537 | * to use a real value here instead. | |
7538 | */ | |
293623f7 | 7539 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 7540 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
7541 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
7542 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
7543 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
7544 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
7545 | ||
7546 | mode->clock = pipe_config.adjusted_mode.clock; | |
79e53945 JB |
7547 | mode->hdisplay = (htot & 0xffff) + 1; |
7548 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
7549 | mode->hsync_start = (hsync & 0xffff) + 1; | |
7550 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
7551 | mode->vdisplay = (vtot & 0xffff) + 1; | |
7552 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
7553 | mode->vsync_start = (vsync & 0xffff) + 1; | |
7554 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
7555 | ||
7556 | drm_mode_set_name(mode); | |
79e53945 JB |
7557 | |
7558 | return mode; | |
7559 | } | |
7560 | ||
3dec0095 | 7561 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
7562 | { |
7563 | struct drm_device *dev = crtc->dev; | |
7564 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7565 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7566 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
7567 | int dpll_reg = DPLL(pipe); |
7568 | int dpll; | |
652c393a | 7569 | |
bad720ff | 7570 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
7571 | return; |
7572 | ||
7573 | if (!dev_priv->lvds_downclock_avail) | |
7574 | return; | |
7575 | ||
dbdc6479 | 7576 | dpll = I915_READ(dpll_reg); |
652c393a | 7577 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 7578 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 7579 | |
8ac5a6d5 | 7580 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
7581 | |
7582 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
7583 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 7584 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 7585 | |
652c393a JB |
7586 | dpll = I915_READ(dpll_reg); |
7587 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 7588 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 7589 | } |
652c393a JB |
7590 | } |
7591 | ||
7592 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
7593 | { | |
7594 | struct drm_device *dev = crtc->dev; | |
7595 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7596 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
652c393a | 7597 | |
bad720ff | 7598 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
7599 | return; |
7600 | ||
7601 | if (!dev_priv->lvds_downclock_avail) | |
7602 | return; | |
7603 | ||
7604 | /* | |
7605 | * Since this is called by a timer, we should never get here in | |
7606 | * the manual case. | |
7607 | */ | |
7608 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
7609 | int pipe = intel_crtc->pipe; |
7610 | int dpll_reg = DPLL(pipe); | |
7611 | int dpll; | |
f6e5b160 | 7612 | |
44d98a61 | 7613 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 7614 | |
8ac5a6d5 | 7615 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 7616 | |
dc257cf1 | 7617 | dpll = I915_READ(dpll_reg); |
652c393a JB |
7618 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
7619 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 7620 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
7621 | dpll = I915_READ(dpll_reg); |
7622 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 7623 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
7624 | } |
7625 | ||
7626 | } | |
7627 | ||
f047e395 CW |
7628 | void intel_mark_busy(struct drm_device *dev) |
7629 | { | |
c67a470b PZ |
7630 | struct drm_i915_private *dev_priv = dev->dev_private; |
7631 | ||
7632 | hsw_package_c8_gpu_busy(dev_priv); | |
7633 | i915_update_gfx_val(dev_priv); | |
f047e395 CW |
7634 | } |
7635 | ||
7636 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 7637 | { |
c67a470b | 7638 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 7639 | struct drm_crtc *crtc; |
652c393a | 7640 | |
c67a470b PZ |
7641 | hsw_package_c8_gpu_idle(dev_priv); |
7642 | ||
652c393a JB |
7643 | if (!i915_powersave) |
7644 | return; | |
7645 | ||
652c393a | 7646 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
652c393a JB |
7647 | if (!crtc->fb) |
7648 | continue; | |
7649 | ||
725a5b54 | 7650 | intel_decrease_pllclock(crtc); |
652c393a | 7651 | } |
652c393a JB |
7652 | } |
7653 | ||
c65355bb CW |
7654 | void intel_mark_fb_busy(struct drm_i915_gem_object *obj, |
7655 | struct intel_ring_buffer *ring) | |
652c393a | 7656 | { |
f047e395 CW |
7657 | struct drm_device *dev = obj->base.dev; |
7658 | struct drm_crtc *crtc; | |
652c393a | 7659 | |
f047e395 | 7660 | if (!i915_powersave) |
acb87dfb CW |
7661 | return; |
7662 | ||
652c393a JB |
7663 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
7664 | if (!crtc->fb) | |
7665 | continue; | |
7666 | ||
c65355bb CW |
7667 | if (to_intel_framebuffer(crtc->fb)->obj != obj) |
7668 | continue; | |
7669 | ||
7670 | intel_increase_pllclock(crtc); | |
7671 | if (ring && intel_fbc_enabled(dev)) | |
7672 | ring->fbc_dirty = true; | |
652c393a JB |
7673 | } |
7674 | } | |
7675 | ||
79e53945 JB |
7676 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
7677 | { | |
7678 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
7679 | struct drm_device *dev = crtc->dev; |
7680 | struct intel_unpin_work *work; | |
7681 | unsigned long flags; | |
7682 | ||
7683 | spin_lock_irqsave(&dev->event_lock, flags); | |
7684 | work = intel_crtc->unpin_work; | |
7685 | intel_crtc->unpin_work = NULL; | |
7686 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7687 | ||
7688 | if (work) { | |
7689 | cancel_work_sync(&work->work); | |
7690 | kfree(work); | |
7691 | } | |
79e53945 | 7692 | |
40ccc72b MK |
7693 | intel_crtc_cursor_set(crtc, NULL, 0, 0, 0); |
7694 | ||
79e53945 | 7695 | drm_crtc_cleanup(crtc); |
67e77c5a | 7696 | |
79e53945 JB |
7697 | kfree(intel_crtc); |
7698 | } | |
7699 | ||
6b95a207 KH |
7700 | static void intel_unpin_work_fn(struct work_struct *__work) |
7701 | { | |
7702 | struct intel_unpin_work *work = | |
7703 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 7704 | struct drm_device *dev = work->crtc->dev; |
6b95a207 | 7705 | |
b4a98e57 | 7706 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 7707 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
7708 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
7709 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 7710 | |
b4a98e57 CW |
7711 | intel_update_fbc(dev); |
7712 | mutex_unlock(&dev->struct_mutex); | |
7713 | ||
7714 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); | |
7715 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
7716 | ||
6b95a207 KH |
7717 | kfree(work); |
7718 | } | |
7719 | ||
1afe3e9d | 7720 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 7721 | struct drm_crtc *crtc) |
6b95a207 KH |
7722 | { |
7723 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
7724 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7725 | struct intel_unpin_work *work; | |
6b95a207 KH |
7726 | unsigned long flags; |
7727 | ||
7728 | /* Ignore early vblank irqs */ | |
7729 | if (intel_crtc == NULL) | |
7730 | return; | |
7731 | ||
7732 | spin_lock_irqsave(&dev->event_lock, flags); | |
7733 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
7734 | |
7735 | /* Ensure we don't miss a work->pending update ... */ | |
7736 | smp_rmb(); | |
7737 | ||
7738 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
7739 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7740 | return; | |
7741 | } | |
7742 | ||
e7d841ca CW |
7743 | /* and that the unpin work is consistent wrt ->pending. */ |
7744 | smp_rmb(); | |
7745 | ||
6b95a207 | 7746 | intel_crtc->unpin_work = NULL; |
6b95a207 | 7747 | |
45a066eb RC |
7748 | if (work->event) |
7749 | drm_send_vblank_event(dev, intel_crtc->pipe, work->event); | |
6b95a207 | 7750 | |
0af7e4df MK |
7751 | drm_vblank_put(dev, intel_crtc->pipe); |
7752 | ||
6b95a207 KH |
7753 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7754 | ||
2c10d571 | 7755 | wake_up_all(&dev_priv->pending_flip_queue); |
b4a98e57 CW |
7756 | |
7757 | queue_work(dev_priv->wq, &work->work); | |
e5510fac JB |
7758 | |
7759 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
7760 | } |
7761 | ||
1afe3e9d JB |
7762 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
7763 | { | |
7764 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7765 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
7766 | ||
49b14a5c | 7767 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
7768 | } |
7769 | ||
7770 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
7771 | { | |
7772 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7773 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
7774 | ||
49b14a5c | 7775 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
7776 | } |
7777 | ||
6b95a207 KH |
7778 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
7779 | { | |
7780 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7781 | struct intel_crtc *intel_crtc = | |
7782 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
7783 | unsigned long flags; | |
7784 | ||
e7d841ca CW |
7785 | /* NB: An MMIO update of the plane base pointer will also |
7786 | * generate a page-flip completion irq, i.e. every modeset | |
7787 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
7788 | */ | |
6b95a207 | 7789 | spin_lock_irqsave(&dev->event_lock, flags); |
e7d841ca CW |
7790 | if (intel_crtc->unpin_work) |
7791 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); | |
6b95a207 KH |
7792 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7793 | } | |
7794 | ||
e7d841ca CW |
7795 | inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
7796 | { | |
7797 | /* Ensure that the work item is consistent when activating it ... */ | |
7798 | smp_wmb(); | |
7799 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
7800 | /* and that it is marked active as soon as the irq could fire. */ | |
7801 | smp_wmb(); | |
7802 | } | |
7803 | ||
8c9f3aaf JB |
7804 | static int intel_gen2_queue_flip(struct drm_device *dev, |
7805 | struct drm_crtc *crtc, | |
7806 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
7807 | struct drm_i915_gem_object *obj, |
7808 | uint32_t flags) | |
8c9f3aaf JB |
7809 | { |
7810 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7811 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 7812 | u32 flip_mask; |
6d90c952 | 7813 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7814 | int ret; |
7815 | ||
6d90c952 | 7816 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7817 | if (ret) |
83d4092b | 7818 | goto err; |
8c9f3aaf | 7819 | |
6d90c952 | 7820 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 7821 | if (ret) |
83d4092b | 7822 | goto err_unpin; |
8c9f3aaf JB |
7823 | |
7824 | /* Can't queue multiple flips, so wait for the previous | |
7825 | * one to finish before executing the next. | |
7826 | */ | |
7827 | if (intel_crtc->plane) | |
7828 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
7829 | else | |
7830 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
7831 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
7832 | intel_ring_emit(ring, MI_NOOP); | |
7833 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
7834 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7835 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 7836 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 | 7837 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
7838 | |
7839 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 7840 | __intel_ring_advance(ring); |
83d4092b CW |
7841 | return 0; |
7842 | ||
7843 | err_unpin: | |
7844 | intel_unpin_fb_obj(obj); | |
7845 | err: | |
8c9f3aaf JB |
7846 | return ret; |
7847 | } | |
7848 | ||
7849 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
7850 | struct drm_crtc *crtc, | |
7851 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
7852 | struct drm_i915_gem_object *obj, |
7853 | uint32_t flags) | |
8c9f3aaf JB |
7854 | { |
7855 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7856 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8c9f3aaf | 7857 | u32 flip_mask; |
6d90c952 | 7858 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7859 | int ret; |
7860 | ||
6d90c952 | 7861 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7862 | if (ret) |
83d4092b | 7863 | goto err; |
8c9f3aaf | 7864 | |
6d90c952 | 7865 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 7866 | if (ret) |
83d4092b | 7867 | goto err_unpin; |
8c9f3aaf JB |
7868 | |
7869 | if (intel_crtc->plane) | |
7870 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
7871 | else | |
7872 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
7873 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
7874 | intel_ring_emit(ring, MI_NOOP); | |
7875 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
7876 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7877 | intel_ring_emit(ring, fb->pitches[0]); | |
f343c5f6 | 7878 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
6d90c952 DV |
7879 | intel_ring_emit(ring, MI_NOOP); |
7880 | ||
e7d841ca | 7881 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 7882 | __intel_ring_advance(ring); |
83d4092b CW |
7883 | return 0; |
7884 | ||
7885 | err_unpin: | |
7886 | intel_unpin_fb_obj(obj); | |
7887 | err: | |
8c9f3aaf JB |
7888 | return ret; |
7889 | } | |
7890 | ||
7891 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
7892 | struct drm_crtc *crtc, | |
7893 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
7894 | struct drm_i915_gem_object *obj, |
7895 | uint32_t flags) | |
8c9f3aaf JB |
7896 | { |
7897 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7898 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7899 | uint32_t pf, pipesrc; | |
6d90c952 | 7900 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7901 | int ret; |
7902 | ||
6d90c952 | 7903 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7904 | if (ret) |
83d4092b | 7905 | goto err; |
8c9f3aaf | 7906 | |
6d90c952 | 7907 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 7908 | if (ret) |
83d4092b | 7909 | goto err_unpin; |
8c9f3aaf JB |
7910 | |
7911 | /* i965+ uses the linear or tiled offsets from the | |
7912 | * Display Registers (which do not change across a page-flip) | |
7913 | * so we need only reprogram the base address. | |
7914 | */ | |
6d90c952 DV |
7915 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7916 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7917 | intel_ring_emit(ring, fb->pitches[0]); | |
c2c75131 | 7918 | intel_ring_emit(ring, |
f343c5f6 | 7919 | (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) | |
c2c75131 | 7920 | obj->tiling_mode); |
8c9f3aaf JB |
7921 | |
7922 | /* XXX Enabling the panel-fitter across page-flip is so far | |
7923 | * untested on non-native modes, so ignore it for now. | |
7924 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
7925 | */ | |
7926 | pf = 0; | |
7927 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 7928 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
7929 | |
7930 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 7931 | __intel_ring_advance(ring); |
83d4092b CW |
7932 | return 0; |
7933 | ||
7934 | err_unpin: | |
7935 | intel_unpin_fb_obj(obj); | |
7936 | err: | |
8c9f3aaf JB |
7937 | return ret; |
7938 | } | |
7939 | ||
7940 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
7941 | struct drm_crtc *crtc, | |
7942 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
7943 | struct drm_i915_gem_object *obj, |
7944 | uint32_t flags) | |
8c9f3aaf JB |
7945 | { |
7946 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7947 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6d90c952 | 7948 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
8c9f3aaf JB |
7949 | uint32_t pf, pipesrc; |
7950 | int ret; | |
7951 | ||
6d90c952 | 7952 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); |
8c9f3aaf | 7953 | if (ret) |
83d4092b | 7954 | goto err; |
8c9f3aaf | 7955 | |
6d90c952 | 7956 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 7957 | if (ret) |
83d4092b | 7958 | goto err_unpin; |
8c9f3aaf | 7959 | |
6d90c952 DV |
7960 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
7961 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
7962 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
f343c5f6 | 7963 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
8c9f3aaf | 7964 | |
dc257cf1 DV |
7965 | /* Contrary to the suggestions in the documentation, |
7966 | * "Enable Panel Fitter" does not seem to be required when page | |
7967 | * flipping with a non-native mode, and worse causes a normal | |
7968 | * modeset to fail. | |
7969 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
7970 | */ | |
7971 | pf = 0; | |
8c9f3aaf | 7972 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 7973 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
7974 | |
7975 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 7976 | __intel_ring_advance(ring); |
83d4092b CW |
7977 | return 0; |
7978 | ||
7979 | err_unpin: | |
7980 | intel_unpin_fb_obj(obj); | |
7981 | err: | |
8c9f3aaf JB |
7982 | return ret; |
7983 | } | |
7984 | ||
7c9017e5 JB |
7985 | static int intel_gen7_queue_flip(struct drm_device *dev, |
7986 | struct drm_crtc *crtc, | |
7987 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
7988 | struct drm_i915_gem_object *obj, |
7989 | uint32_t flags) | |
7c9017e5 JB |
7990 | { |
7991 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7992 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ffe74d75 | 7993 | struct intel_ring_buffer *ring; |
cb05d8de | 7994 | uint32_t plane_bit = 0; |
ffe74d75 CW |
7995 | int len, ret; |
7996 | ||
7997 | ring = obj->ring; | |
1c5fd085 | 7998 | if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS) |
ffe74d75 | 7999 | ring = &dev_priv->ring[BCS]; |
7c9017e5 JB |
8000 | |
8001 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
8002 | if (ret) | |
83d4092b | 8003 | goto err; |
7c9017e5 | 8004 | |
cb05d8de DV |
8005 | switch(intel_crtc->plane) { |
8006 | case PLANE_A: | |
8007 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
8008 | break; | |
8009 | case PLANE_B: | |
8010 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
8011 | break; | |
8012 | case PLANE_C: | |
8013 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
8014 | break; | |
8015 | default: | |
8016 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
8017 | ret = -ENODEV; | |
ab3951eb | 8018 | goto err_unpin; |
cb05d8de DV |
8019 | } |
8020 | ||
ffe74d75 CW |
8021 | len = 4; |
8022 | if (ring->id == RCS) | |
8023 | len += 6; | |
8024 | ||
8025 | ret = intel_ring_begin(ring, len); | |
7c9017e5 | 8026 | if (ret) |
83d4092b | 8027 | goto err_unpin; |
7c9017e5 | 8028 | |
ffe74d75 CW |
8029 | /* Unmask the flip-done completion message. Note that the bspec says that |
8030 | * we should do this for both the BCS and RCS, and that we must not unmask | |
8031 | * more than one flip event at any time (or ensure that one flip message | |
8032 | * can be sent by waiting for flip-done prior to queueing new flips). | |
8033 | * Experimentation says that BCS works despite DERRMR masking all | |
8034 | * flip-done completion events and that unmasking all planes at once | |
8035 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
8036 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
8037 | */ | |
8038 | if (ring->id == RCS) { | |
8039 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
8040 | intel_ring_emit(ring, DERRMR); | |
8041 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
8042 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
8043 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
8044 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1)); | |
8045 | intel_ring_emit(ring, DERRMR); | |
8046 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
8047 | } | |
8048 | ||
cb05d8de | 8049 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 8050 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
f343c5f6 | 8051 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); |
7c9017e5 | 8052 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
8053 | |
8054 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 8055 | __intel_ring_advance(ring); |
83d4092b CW |
8056 | return 0; |
8057 | ||
8058 | err_unpin: | |
8059 | intel_unpin_fb_obj(obj); | |
8060 | err: | |
7c9017e5 JB |
8061 | return ret; |
8062 | } | |
8063 | ||
8c9f3aaf JB |
8064 | static int intel_default_queue_flip(struct drm_device *dev, |
8065 | struct drm_crtc *crtc, | |
8066 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8067 | struct drm_i915_gem_object *obj, |
8068 | uint32_t flags) | |
8c9f3aaf JB |
8069 | { |
8070 | return -ENODEV; | |
8071 | } | |
8072 | ||
6b95a207 KH |
8073 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
8074 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
8075 | struct drm_pending_vblank_event *event, |
8076 | uint32_t page_flip_flags) | |
6b95a207 KH |
8077 | { |
8078 | struct drm_device *dev = crtc->dev; | |
8079 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4a35f83b VS |
8080 | struct drm_framebuffer *old_fb = crtc->fb; |
8081 | struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; | |
6b95a207 KH |
8082 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8083 | struct intel_unpin_work *work; | |
8c9f3aaf | 8084 | unsigned long flags; |
52e68630 | 8085 | int ret; |
6b95a207 | 8086 | |
e6a595d2 VS |
8087 | /* Can't change pixel format via MI display flips. */ |
8088 | if (fb->pixel_format != crtc->fb->pixel_format) | |
8089 | return -EINVAL; | |
8090 | ||
8091 | /* | |
8092 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
8093 | * Note that pitch changes could also affect these register. | |
8094 | */ | |
8095 | if (INTEL_INFO(dev)->gen > 3 && | |
8096 | (fb->offsets[0] != crtc->fb->offsets[0] || | |
8097 | fb->pitches[0] != crtc->fb->pitches[0])) | |
8098 | return -EINVAL; | |
8099 | ||
b14c5679 | 8100 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
8101 | if (work == NULL) |
8102 | return -ENOMEM; | |
8103 | ||
6b95a207 | 8104 | work->event = event; |
b4a98e57 | 8105 | work->crtc = crtc; |
4a35f83b | 8106 | work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; |
6b95a207 KH |
8107 | INIT_WORK(&work->work, intel_unpin_work_fn); |
8108 | ||
7317c75e JB |
8109 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
8110 | if (ret) | |
8111 | goto free_work; | |
8112 | ||
6b95a207 KH |
8113 | /* We borrow the event spin lock for protecting unpin_work */ |
8114 | spin_lock_irqsave(&dev->event_lock, flags); | |
8115 | if (intel_crtc->unpin_work) { | |
8116 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8117 | kfree(work); | |
7317c75e | 8118 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
8119 | |
8120 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
8121 | return -EBUSY; |
8122 | } | |
8123 | intel_crtc->unpin_work = work; | |
8124 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8125 | ||
b4a98e57 CW |
8126 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
8127 | flush_workqueue(dev_priv->wq); | |
8128 | ||
79158103 CW |
8129 | ret = i915_mutex_lock_interruptible(dev); |
8130 | if (ret) | |
8131 | goto cleanup; | |
6b95a207 | 8132 | |
75dfca80 | 8133 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
8134 | drm_gem_object_reference(&work->old_fb_obj->base); |
8135 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
8136 | |
8137 | crtc->fb = fb; | |
96b099fd | 8138 | |
e1f99ce6 | 8139 | work->pending_flip_obj = obj; |
e1f99ce6 | 8140 | |
4e5359cd SF |
8141 | work->enable_stall_check = true; |
8142 | ||
b4a98e57 | 8143 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 8144 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 8145 | |
ed8d1975 | 8146 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags); |
8c9f3aaf JB |
8147 | if (ret) |
8148 | goto cleanup_pending; | |
6b95a207 | 8149 | |
7782de3b | 8150 | intel_disable_fbc(dev); |
c65355bb | 8151 | intel_mark_fb_busy(obj, NULL); |
6b95a207 KH |
8152 | mutex_unlock(&dev->struct_mutex); |
8153 | ||
e5510fac JB |
8154 | trace_i915_flip_request(intel_crtc->plane, obj); |
8155 | ||
6b95a207 | 8156 | return 0; |
96b099fd | 8157 | |
8c9f3aaf | 8158 | cleanup_pending: |
b4a98e57 | 8159 | atomic_dec(&intel_crtc->unpin_work_count); |
4a35f83b | 8160 | crtc->fb = old_fb; |
05394f39 CW |
8161 | drm_gem_object_unreference(&work->old_fb_obj->base); |
8162 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
8163 | mutex_unlock(&dev->struct_mutex); |
8164 | ||
79158103 | 8165 | cleanup: |
96b099fd CW |
8166 | spin_lock_irqsave(&dev->event_lock, flags); |
8167 | intel_crtc->unpin_work = NULL; | |
8168 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
8169 | ||
7317c75e JB |
8170 | drm_vblank_put(dev, intel_crtc->pipe); |
8171 | free_work: | |
96b099fd CW |
8172 | kfree(work); |
8173 | ||
8174 | return ret; | |
6b95a207 KH |
8175 | } |
8176 | ||
f6e5b160 | 8177 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
8178 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
8179 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
8180 | }; |
8181 | ||
50f56119 DV |
8182 | static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, |
8183 | struct drm_crtc *crtc) | |
8184 | { | |
8185 | struct drm_device *dev; | |
8186 | struct drm_crtc *tmp; | |
8187 | int crtc_mask = 1; | |
47f1c6c9 | 8188 | |
50f56119 | 8189 | WARN(!crtc, "checking null crtc?\n"); |
47f1c6c9 | 8190 | |
50f56119 | 8191 | dev = crtc->dev; |
47f1c6c9 | 8192 | |
50f56119 DV |
8193 | list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { |
8194 | if (tmp == crtc) | |
8195 | break; | |
8196 | crtc_mask <<= 1; | |
8197 | } | |
47f1c6c9 | 8198 | |
50f56119 DV |
8199 | if (encoder->possible_crtcs & crtc_mask) |
8200 | return true; | |
8201 | return false; | |
47f1c6c9 | 8202 | } |
79e53945 | 8203 | |
9a935856 DV |
8204 | /** |
8205 | * intel_modeset_update_staged_output_state | |
8206 | * | |
8207 | * Updates the staged output configuration state, e.g. after we've read out the | |
8208 | * current hw state. | |
8209 | */ | |
8210 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 8211 | { |
9a935856 DV |
8212 | struct intel_encoder *encoder; |
8213 | struct intel_connector *connector; | |
f6e5b160 | 8214 | |
9a935856 DV |
8215 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8216 | base.head) { | |
8217 | connector->new_encoder = | |
8218 | to_intel_encoder(connector->base.encoder); | |
8219 | } | |
f6e5b160 | 8220 | |
9a935856 DV |
8221 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8222 | base.head) { | |
8223 | encoder->new_crtc = | |
8224 | to_intel_crtc(encoder->base.crtc); | |
8225 | } | |
f6e5b160 CW |
8226 | } |
8227 | ||
9a935856 DV |
8228 | /** |
8229 | * intel_modeset_commit_output_state | |
8230 | * | |
8231 | * This function copies the stage display pipe configuration to the real one. | |
8232 | */ | |
8233 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
8234 | { | |
8235 | struct intel_encoder *encoder; | |
8236 | struct intel_connector *connector; | |
f6e5b160 | 8237 | |
9a935856 DV |
8238 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
8239 | base.head) { | |
8240 | connector->base.encoder = &connector->new_encoder->base; | |
8241 | } | |
f6e5b160 | 8242 | |
9a935856 DV |
8243 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8244 | base.head) { | |
8245 | encoder->base.crtc = &encoder->new_crtc->base; | |
8246 | } | |
8247 | } | |
8248 | ||
050f7aeb DV |
8249 | static void |
8250 | connected_sink_compute_bpp(struct intel_connector * connector, | |
8251 | struct intel_crtc_config *pipe_config) | |
8252 | { | |
8253 | int bpp = pipe_config->pipe_bpp; | |
8254 | ||
8255 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
8256 | connector->base.base.id, | |
8257 | drm_get_connector_name(&connector->base)); | |
8258 | ||
8259 | /* Don't use an invalid EDID bpc value */ | |
8260 | if (connector->base.display_info.bpc && | |
8261 | connector->base.display_info.bpc * 3 < bpp) { | |
8262 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
8263 | bpp, connector->base.display_info.bpc*3); | |
8264 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
8265 | } | |
8266 | ||
8267 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
8268 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
8269 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
8270 | bpp); | |
8271 | pipe_config->pipe_bpp = 24; | |
8272 | } | |
8273 | } | |
8274 | ||
4e53c2e0 | 8275 | static int |
050f7aeb DV |
8276 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
8277 | struct drm_framebuffer *fb, | |
8278 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 8279 | { |
050f7aeb DV |
8280 | struct drm_device *dev = crtc->base.dev; |
8281 | struct intel_connector *connector; | |
4e53c2e0 DV |
8282 | int bpp; |
8283 | ||
d42264b1 DV |
8284 | switch (fb->pixel_format) { |
8285 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
8286 | bpp = 8*3; /* since we go through a colormap */ |
8287 | break; | |
d42264b1 DV |
8288 | case DRM_FORMAT_XRGB1555: |
8289 | case DRM_FORMAT_ARGB1555: | |
8290 | /* checked in intel_framebuffer_init already */ | |
8291 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
8292 | return -EINVAL; | |
8293 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
8294 | bpp = 6*3; /* min is 18bpp */ |
8295 | break; | |
d42264b1 DV |
8296 | case DRM_FORMAT_XBGR8888: |
8297 | case DRM_FORMAT_ABGR8888: | |
8298 | /* checked in intel_framebuffer_init already */ | |
8299 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
8300 | return -EINVAL; | |
8301 | case DRM_FORMAT_XRGB8888: | |
8302 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
8303 | bpp = 8*3; |
8304 | break; | |
d42264b1 DV |
8305 | case DRM_FORMAT_XRGB2101010: |
8306 | case DRM_FORMAT_ARGB2101010: | |
8307 | case DRM_FORMAT_XBGR2101010: | |
8308 | case DRM_FORMAT_ABGR2101010: | |
8309 | /* checked in intel_framebuffer_init already */ | |
8310 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 8311 | return -EINVAL; |
4e53c2e0 DV |
8312 | bpp = 10*3; |
8313 | break; | |
baba133a | 8314 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
8315 | default: |
8316 | DRM_DEBUG_KMS("unsupported depth\n"); | |
8317 | return -EINVAL; | |
8318 | } | |
8319 | ||
4e53c2e0 DV |
8320 | pipe_config->pipe_bpp = bpp; |
8321 | ||
8322 | /* Clamp display bpp to EDID value */ | |
8323 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 8324 | base.head) { |
1b829e05 DV |
8325 | if (!connector->new_encoder || |
8326 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
8327 | continue; |
8328 | ||
050f7aeb | 8329 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
8330 | } |
8331 | ||
8332 | return bpp; | |
8333 | } | |
8334 | ||
644db711 DV |
8335 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
8336 | { | |
8337 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
8338 | "type: 0x%x flags: 0x%x\n", | |
8339 | mode->clock, | |
8340 | mode->crtc_hdisplay, mode->crtc_hsync_start, | |
8341 | mode->crtc_hsync_end, mode->crtc_htotal, | |
8342 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
8343 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
8344 | } | |
8345 | ||
c0b03411 DV |
8346 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
8347 | struct intel_crtc_config *pipe_config, | |
8348 | const char *context) | |
8349 | { | |
8350 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
8351 | context, pipe_name(crtc->pipe)); | |
8352 | ||
8353 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
8354 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
8355 | pipe_config->pipe_bpp, pipe_config->dither); | |
8356 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
8357 | pipe_config->has_pch_encoder, | |
8358 | pipe_config->fdi_lanes, | |
8359 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
8360 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
8361 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
8362 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
8363 | pipe_config->has_dp_encoder, | |
8364 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
8365 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
8366 | pipe_config->dp_m_n.tu); | |
c0b03411 DV |
8367 | DRM_DEBUG_KMS("requested mode:\n"); |
8368 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
8369 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
8370 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 8371 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 8372 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
8373 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
8374 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
8375 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
8376 | pipe_config->gmch_pfit.control, | |
8377 | pipe_config->gmch_pfit.pgm_ratios, | |
8378 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 8379 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 8380 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
8381 | pipe_config->pch_pfit.size, |
8382 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 8383 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 8384 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
8385 | } |
8386 | ||
accfc0c5 DV |
8387 | static bool check_encoder_cloning(struct drm_crtc *crtc) |
8388 | { | |
8389 | int num_encoders = 0; | |
8390 | bool uncloneable_encoders = false; | |
8391 | struct intel_encoder *encoder; | |
8392 | ||
8393 | list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, | |
8394 | base.head) { | |
8395 | if (&encoder->new_crtc->base != crtc) | |
8396 | continue; | |
8397 | ||
8398 | num_encoders++; | |
8399 | if (!encoder->cloneable) | |
8400 | uncloneable_encoders = true; | |
8401 | } | |
8402 | ||
8403 | return !(num_encoders > 1 && uncloneable_encoders); | |
8404 | } | |
8405 | ||
b8cecdf5 DV |
8406 | static struct intel_crtc_config * |
8407 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 8408 | struct drm_framebuffer *fb, |
b8cecdf5 | 8409 | struct drm_display_mode *mode) |
ee7b9f93 | 8410 | { |
7758a113 | 8411 | struct drm_device *dev = crtc->dev; |
7758a113 | 8412 | struct intel_encoder *encoder; |
b8cecdf5 | 8413 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
8414 | int plane_bpp, ret = -EINVAL; |
8415 | bool retry = true; | |
ee7b9f93 | 8416 | |
accfc0c5 DV |
8417 | if (!check_encoder_cloning(crtc)) { |
8418 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
8419 | return ERR_PTR(-EINVAL); | |
8420 | } | |
8421 | ||
b8cecdf5 DV |
8422 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
8423 | if (!pipe_config) | |
7758a113 DV |
8424 | return ERR_PTR(-ENOMEM); |
8425 | ||
b8cecdf5 DV |
8426 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
8427 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd VS |
8428 | |
8429 | pipe_config->pipe_src_w = mode->hdisplay; | |
8430 | pipe_config->pipe_src_h = mode->vdisplay; | |
8431 | ||
e143a21c DV |
8432 | pipe_config->cpu_transcoder = |
8433 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 8434 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 8435 | |
2960bc9c ID |
8436 | /* |
8437 | * Sanitize sync polarity flags based on requested ones. If neither | |
8438 | * positive or negative polarity is requested, treat this as meaning | |
8439 | * negative polarity. | |
8440 | */ | |
8441 | if (!(pipe_config->adjusted_mode.flags & | |
8442 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
8443 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
8444 | ||
8445 | if (!(pipe_config->adjusted_mode.flags & | |
8446 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
8447 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
8448 | ||
050f7aeb DV |
8449 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
8450 | * plane pixel format and any sink constraints into account. Returns the | |
8451 | * source plane bpp so that dithering can be selected on mismatches | |
8452 | * after encoders and crtc also have had their say. */ | |
8453 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
8454 | fb, pipe_config); | |
4e53c2e0 DV |
8455 | if (plane_bpp < 0) |
8456 | goto fail; | |
8457 | ||
e29c22c0 | 8458 | encoder_retry: |
ef1b460d | 8459 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 8460 | pipe_config->port_clock = 0; |
ef1b460d | 8461 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 8462 | |
135c81b8 DV |
8463 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
8464 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0); | |
8465 | ||
7758a113 DV |
8466 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
8467 | * adjust it according to limitations or connector properties, and also | |
8468 | * a chance to reject the mode entirely. | |
47f1c6c9 | 8469 | */ |
7758a113 DV |
8470 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8471 | base.head) { | |
47f1c6c9 | 8472 | |
7758a113 DV |
8473 | if (&encoder->new_crtc->base != crtc) |
8474 | continue; | |
7ae89233 | 8475 | |
efea6e8e DV |
8476 | if (!(encoder->compute_config(encoder, pipe_config))) { |
8477 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
8478 | goto fail; |
8479 | } | |
ee7b9f93 | 8480 | } |
47f1c6c9 | 8481 | |
ff9a6750 DV |
8482 | /* Set default port clock if not overwritten by the encoder. Needs to be |
8483 | * done afterwards in case the encoder adjusts the mode. */ | |
8484 | if (!pipe_config->port_clock) | |
3c52f4eb VS |
8485 | pipe_config->port_clock = pipe_config->adjusted_mode.clock * |
8486 | pipe_config->pixel_multiplier; | |
ff9a6750 | 8487 | |
a43f6e0f | 8488 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 8489 | if (ret < 0) { |
7758a113 DV |
8490 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
8491 | goto fail; | |
ee7b9f93 | 8492 | } |
e29c22c0 DV |
8493 | |
8494 | if (ret == RETRY) { | |
8495 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
8496 | ret = -EINVAL; | |
8497 | goto fail; | |
8498 | } | |
8499 | ||
8500 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
8501 | retry = false; | |
8502 | goto encoder_retry; | |
8503 | } | |
8504 | ||
4e53c2e0 DV |
8505 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
8506 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
8507 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
8508 | ||
b8cecdf5 | 8509 | return pipe_config; |
7758a113 | 8510 | fail: |
b8cecdf5 | 8511 | kfree(pipe_config); |
e29c22c0 | 8512 | return ERR_PTR(ret); |
ee7b9f93 | 8513 | } |
47f1c6c9 | 8514 | |
e2e1ed41 DV |
8515 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
8516 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
8517 | static void | |
8518 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
8519 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
8520 | { |
8521 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
8522 | struct drm_device *dev = crtc->dev; |
8523 | struct intel_encoder *encoder; | |
8524 | struct intel_connector *connector; | |
8525 | struct drm_crtc *tmp_crtc; | |
79e53945 | 8526 | |
e2e1ed41 | 8527 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 8528 | |
e2e1ed41 DV |
8529 | /* Check which crtcs have changed outputs connected to them, these need |
8530 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
8531 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
8532 | * bit set at most. */ | |
8533 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
8534 | base.head) { | |
8535 | if (connector->base.encoder == &connector->new_encoder->base) | |
8536 | continue; | |
79e53945 | 8537 | |
e2e1ed41 DV |
8538 | if (connector->base.encoder) { |
8539 | tmp_crtc = connector->base.encoder->crtc; | |
8540 | ||
8541 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
8542 | } | |
8543 | ||
8544 | if (connector->new_encoder) | |
8545 | *prepare_pipes |= | |
8546 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
8547 | } |
8548 | ||
e2e1ed41 DV |
8549 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8550 | base.head) { | |
8551 | if (encoder->base.crtc == &encoder->new_crtc->base) | |
8552 | continue; | |
8553 | ||
8554 | if (encoder->base.crtc) { | |
8555 | tmp_crtc = encoder->base.crtc; | |
8556 | ||
8557 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
8558 | } | |
8559 | ||
8560 | if (encoder->new_crtc) | |
8561 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
8562 | } |
8563 | ||
e2e1ed41 DV |
8564 | /* Check for any pipes that will be fully disabled ... */ |
8565 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
8566 | base.head) { | |
8567 | bool used = false; | |
22fd0fab | 8568 | |
e2e1ed41 DV |
8569 | /* Don't try to disable disabled crtcs. */ |
8570 | if (!intel_crtc->base.enabled) | |
8571 | continue; | |
7e7d76c3 | 8572 | |
e2e1ed41 DV |
8573 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8574 | base.head) { | |
8575 | if (encoder->new_crtc == intel_crtc) | |
8576 | used = true; | |
8577 | } | |
8578 | ||
8579 | if (!used) | |
8580 | *disable_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
8581 | } |
8582 | ||
e2e1ed41 DV |
8583 | |
8584 | /* set_mode is also used to update properties on life display pipes. */ | |
8585 | intel_crtc = to_intel_crtc(crtc); | |
8586 | if (crtc->enabled) | |
8587 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
8588 | ||
b6c5164d DV |
8589 | /* |
8590 | * For simplicity do a full modeset on any pipe where the output routing | |
8591 | * changed. We could be more clever, but that would require us to be | |
8592 | * more careful with calling the relevant encoder->mode_set functions. | |
8593 | */ | |
e2e1ed41 DV |
8594 | if (*prepare_pipes) |
8595 | *modeset_pipes = *prepare_pipes; | |
8596 | ||
8597 | /* ... and mask these out. */ | |
8598 | *modeset_pipes &= ~(*disable_pipes); | |
8599 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
8600 | |
8601 | /* | |
8602 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
8603 | * obies this rule, but the modeset restore mode of | |
8604 | * intel_modeset_setup_hw_state does not. | |
8605 | */ | |
8606 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
8607 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
8608 | |
8609 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
8610 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 8611 | } |
79e53945 | 8612 | |
ea9d758d | 8613 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 8614 | { |
ea9d758d | 8615 | struct drm_encoder *encoder; |
f6e5b160 | 8616 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 8617 | |
ea9d758d DV |
8618 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
8619 | if (encoder->crtc == crtc) | |
8620 | return true; | |
8621 | ||
8622 | return false; | |
8623 | } | |
8624 | ||
8625 | static void | |
8626 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
8627 | { | |
8628 | struct intel_encoder *intel_encoder; | |
8629 | struct intel_crtc *intel_crtc; | |
8630 | struct drm_connector *connector; | |
8631 | ||
8632 | list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, | |
8633 | base.head) { | |
8634 | if (!intel_encoder->base.crtc) | |
8635 | continue; | |
8636 | ||
8637 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
8638 | ||
8639 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
8640 | intel_encoder->connectors_active = false; | |
8641 | } | |
8642 | ||
8643 | intel_modeset_commit_output_state(dev); | |
8644 | ||
8645 | /* Update computed state. */ | |
8646 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
8647 | base.head) { | |
8648 | intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); | |
8649 | } | |
8650 | ||
8651 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
8652 | if (!connector->encoder || !connector->encoder->crtc) | |
8653 | continue; | |
8654 | ||
8655 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
8656 | ||
8657 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
8658 | struct drm_property *dpms_property = |
8659 | dev->mode_config.dpms_property; | |
8660 | ||
ea9d758d | 8661 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 8662 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
8663 | dpms_property, |
8664 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
8665 | |
8666 | intel_encoder = to_intel_encoder(connector->encoder); | |
8667 | intel_encoder->connectors_active = true; | |
8668 | } | |
8669 | } | |
8670 | ||
8671 | } | |
8672 | ||
3bd26263 | 8673 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 8674 | { |
3bd26263 | 8675 | int diff; |
f1f644dc JB |
8676 | |
8677 | if (clock1 == clock2) | |
8678 | return true; | |
8679 | ||
8680 | if (!clock1 || !clock2) | |
8681 | return false; | |
8682 | ||
8683 | diff = abs(clock1 - clock2); | |
8684 | ||
8685 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
8686 | return true; | |
8687 | ||
8688 | return false; | |
8689 | } | |
8690 | ||
25c5b266 DV |
8691 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
8692 | list_for_each_entry((intel_crtc), \ | |
8693 | &(dev)->mode_config.crtc_list, \ | |
8694 | base.head) \ | |
0973f18f | 8695 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 8696 | |
0e8ffe1b | 8697 | static bool |
2fa2fe9a DV |
8698 | intel_pipe_config_compare(struct drm_device *dev, |
8699 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
8700 | struct intel_crtc_config *pipe_config) |
8701 | { | |
66e985c0 DV |
8702 | #define PIPE_CONF_CHECK_X(name) \ |
8703 | if (current_config->name != pipe_config->name) { \ | |
8704 | DRM_ERROR("mismatch in " #name " " \ | |
8705 | "(expected 0x%08x, found 0x%08x)\n", \ | |
8706 | current_config->name, \ | |
8707 | pipe_config->name); \ | |
8708 | return false; \ | |
8709 | } | |
8710 | ||
08a24034 DV |
8711 | #define PIPE_CONF_CHECK_I(name) \ |
8712 | if (current_config->name != pipe_config->name) { \ | |
8713 | DRM_ERROR("mismatch in " #name " " \ | |
8714 | "(expected %i, found %i)\n", \ | |
8715 | current_config->name, \ | |
8716 | pipe_config->name); \ | |
8717 | return false; \ | |
88adfff1 DV |
8718 | } |
8719 | ||
1bd1bd80 DV |
8720 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
8721 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 8722 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
8723 | "(expected %i, found %i)\n", \ |
8724 | current_config->name & (mask), \ | |
8725 | pipe_config->name & (mask)); \ | |
8726 | return false; \ | |
8727 | } | |
8728 | ||
5e550656 VS |
8729 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
8730 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
8731 | DRM_ERROR("mismatch in " #name " " \ | |
8732 | "(expected %i, found %i)\n", \ | |
8733 | current_config->name, \ | |
8734 | pipe_config->name); \ | |
8735 | return false; \ | |
8736 | } | |
8737 | ||
bb760063 DV |
8738 | #define PIPE_CONF_QUIRK(quirk) \ |
8739 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
8740 | ||
eccb140b DV |
8741 | PIPE_CONF_CHECK_I(cpu_transcoder); |
8742 | ||
08a24034 DV |
8743 | PIPE_CONF_CHECK_I(has_pch_encoder); |
8744 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
8745 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
8746 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
8747 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
8748 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
8749 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 8750 | |
eb14cb74 VS |
8751 | PIPE_CONF_CHECK_I(has_dp_encoder); |
8752 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
8753 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
8754 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
8755 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
8756 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
8757 | ||
1bd1bd80 DV |
8758 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
8759 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
8760 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
8761 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
8762 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
8763 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
8764 | ||
8765 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
8766 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
8767 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
8768 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
8769 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
8770 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
8771 | ||
c93f54cf | 8772 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6c49f241 | 8773 | |
1bd1bd80 DV |
8774 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
8775 | DRM_MODE_FLAG_INTERLACE); | |
8776 | ||
bb760063 DV |
8777 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
8778 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
8779 | DRM_MODE_FLAG_PHSYNC); | |
8780 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
8781 | DRM_MODE_FLAG_NHSYNC); | |
8782 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
8783 | DRM_MODE_FLAG_PVSYNC); | |
8784 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
8785 | DRM_MODE_FLAG_NVSYNC); | |
8786 | } | |
045ac3b5 | 8787 | |
37327abd VS |
8788 | PIPE_CONF_CHECK_I(pipe_src_w); |
8789 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 8790 | |
2fa2fe9a DV |
8791 | PIPE_CONF_CHECK_I(gmch_pfit.control); |
8792 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
8793 | if (INTEL_INFO(dev)->gen < 4) | |
8794 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
8795 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
fd4daa9c CW |
8796 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
8797 | if (current_config->pch_pfit.enabled) { | |
8798 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
8799 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
8800 | } | |
2fa2fe9a | 8801 | |
42db64ef PZ |
8802 | PIPE_CONF_CHECK_I(ips_enabled); |
8803 | ||
282740f7 VS |
8804 | PIPE_CONF_CHECK_I(double_wide); |
8805 | ||
c0d43d62 | 8806 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 8807 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 8808 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
8809 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
8810 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
c0d43d62 | 8811 | |
42571aef VS |
8812 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
8813 | PIPE_CONF_CHECK_I(pipe_bpp); | |
8814 | ||
d71b8d4a | 8815 | if (!IS_HASWELL(dev)) { |
5e550656 | 8816 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.clock); |
d71b8d4a VS |
8817 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
8818 | } | |
5e550656 | 8819 | |
66e985c0 | 8820 | #undef PIPE_CONF_CHECK_X |
08a24034 | 8821 | #undef PIPE_CONF_CHECK_I |
1bd1bd80 | 8822 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 8823 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 8824 | #undef PIPE_CONF_QUIRK |
88adfff1 | 8825 | |
0e8ffe1b DV |
8826 | return true; |
8827 | } | |
8828 | ||
91d1b4bd DV |
8829 | static void |
8830 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 8831 | { |
8af6cf88 DV |
8832 | struct intel_connector *connector; |
8833 | ||
8834 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
8835 | base.head) { | |
8836 | /* This also checks the encoder/connector hw state with the | |
8837 | * ->get_hw_state callbacks. */ | |
8838 | intel_connector_check_state(connector); | |
8839 | ||
8840 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
8841 | "connector's staged encoder doesn't match current encoder\n"); | |
8842 | } | |
91d1b4bd DV |
8843 | } |
8844 | ||
8845 | static void | |
8846 | check_encoder_state(struct drm_device *dev) | |
8847 | { | |
8848 | struct intel_encoder *encoder; | |
8849 | struct intel_connector *connector; | |
8af6cf88 DV |
8850 | |
8851 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
8852 | base.head) { | |
8853 | bool enabled = false; | |
8854 | bool active = false; | |
8855 | enum pipe pipe, tracked_pipe; | |
8856 | ||
8857 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
8858 | encoder->base.base.id, | |
8859 | drm_get_encoder_name(&encoder->base)); | |
8860 | ||
8861 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
8862 | "encoder's stage crtc doesn't match current crtc\n"); | |
8863 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
8864 | "encoder's active_connectors set, but no crtc\n"); | |
8865 | ||
8866 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
8867 | base.head) { | |
8868 | if (connector->base.encoder != &encoder->base) | |
8869 | continue; | |
8870 | enabled = true; | |
8871 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
8872 | active = true; | |
8873 | } | |
8874 | WARN(!!encoder->base.crtc != enabled, | |
8875 | "encoder's enabled state mismatch " | |
8876 | "(expected %i, found %i)\n", | |
8877 | !!encoder->base.crtc, enabled); | |
8878 | WARN(active && !encoder->base.crtc, | |
8879 | "active encoder with no crtc\n"); | |
8880 | ||
8881 | WARN(encoder->connectors_active != active, | |
8882 | "encoder's computed active state doesn't match tracked active state " | |
8883 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
8884 | ||
8885 | active = encoder->get_hw_state(encoder, &pipe); | |
8886 | WARN(active != encoder->connectors_active, | |
8887 | "encoder's hw state doesn't match sw tracking " | |
8888 | "(expected %i, found %i)\n", | |
8889 | encoder->connectors_active, active); | |
8890 | ||
8891 | if (!encoder->base.crtc) | |
8892 | continue; | |
8893 | ||
8894 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
8895 | WARN(active && pipe != tracked_pipe, | |
8896 | "active encoder's pipe doesn't match" | |
8897 | "(expected %i, found %i)\n", | |
8898 | tracked_pipe, pipe); | |
8899 | ||
8900 | } | |
91d1b4bd DV |
8901 | } |
8902 | ||
8903 | static void | |
8904 | check_crtc_state(struct drm_device *dev) | |
8905 | { | |
8906 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8907 | struct intel_crtc *crtc; | |
8908 | struct intel_encoder *encoder; | |
8909 | struct intel_crtc_config pipe_config; | |
8af6cf88 DV |
8910 | |
8911 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
8912 | base.head) { | |
8913 | bool enabled = false; | |
8914 | bool active = false; | |
8915 | ||
045ac3b5 JB |
8916 | memset(&pipe_config, 0, sizeof(pipe_config)); |
8917 | ||
8af6cf88 DV |
8918 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
8919 | crtc->base.base.id); | |
8920 | ||
8921 | WARN(crtc->active && !crtc->base.enabled, | |
8922 | "active crtc, but not enabled in sw tracking\n"); | |
8923 | ||
8924 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
8925 | base.head) { | |
8926 | if (encoder->base.crtc != &crtc->base) | |
8927 | continue; | |
8928 | enabled = true; | |
8929 | if (encoder->connectors_active) | |
8930 | active = true; | |
8931 | } | |
6c49f241 | 8932 | |
8af6cf88 DV |
8933 | WARN(active != crtc->active, |
8934 | "crtc's computed active state doesn't match tracked active state " | |
8935 | "(expected %i, found %i)\n", active, crtc->active); | |
8936 | WARN(enabled != crtc->base.enabled, | |
8937 | "crtc's computed enabled state doesn't match tracked enabled state " | |
8938 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
8939 | ||
0e8ffe1b DV |
8940 | active = dev_priv->display.get_pipe_config(crtc, |
8941 | &pipe_config); | |
d62cf62a DV |
8942 | |
8943 | /* hw state is inconsistent with the pipe A quirk */ | |
8944 | if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
8945 | active = crtc->active; | |
8946 | ||
6c49f241 DV |
8947 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
8948 | base.head) { | |
3eaba51c | 8949 | enum pipe pipe; |
6c49f241 DV |
8950 | if (encoder->base.crtc != &crtc->base) |
8951 | continue; | |
3eaba51c VS |
8952 | if (encoder->get_config && |
8953 | encoder->get_hw_state(encoder, &pipe)) | |
6c49f241 DV |
8954 | encoder->get_config(encoder, &pipe_config); |
8955 | } | |
8956 | ||
0e8ffe1b DV |
8957 | WARN(crtc->active != active, |
8958 | "crtc active state doesn't match with hw state " | |
8959 | "(expected %i, found %i)\n", crtc->active, active); | |
8960 | ||
c0b03411 DV |
8961 | if (active && |
8962 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
8963 | WARN(1, "pipe state doesn't match!\n"); | |
8964 | intel_dump_pipe_config(crtc, &pipe_config, | |
8965 | "[hw state]"); | |
8966 | intel_dump_pipe_config(crtc, &crtc->config, | |
8967 | "[sw state]"); | |
8968 | } | |
8af6cf88 DV |
8969 | } |
8970 | } | |
8971 | ||
91d1b4bd DV |
8972 | static void |
8973 | check_shared_dpll_state(struct drm_device *dev) | |
8974 | { | |
8975 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8976 | struct intel_crtc *crtc; | |
8977 | struct intel_dpll_hw_state dpll_hw_state; | |
8978 | int i; | |
5358901f DV |
8979 | |
8980 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
8981 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
8982 | int enabled_crtcs = 0, active_crtcs = 0; | |
8983 | bool active; | |
8984 | ||
8985 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
8986 | ||
8987 | DRM_DEBUG_KMS("%s\n", pll->name); | |
8988 | ||
8989 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
8990 | ||
8991 | WARN(pll->active > pll->refcount, | |
8992 | "more active pll users than references: %i vs %i\n", | |
8993 | pll->active, pll->refcount); | |
8994 | WARN(pll->active && !pll->on, | |
8995 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
8996 | WARN(pll->on && !pll->active, |
8997 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
8998 | WARN(pll->on != active, |
8999 | "pll on state mismatch (expected %i, found %i)\n", | |
9000 | pll->on, active); | |
9001 | ||
9002 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
9003 | base.head) { | |
9004 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) | |
9005 | enabled_crtcs++; | |
9006 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
9007 | active_crtcs++; | |
9008 | } | |
9009 | WARN(pll->active != active_crtcs, | |
9010 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
9011 | pll->active, active_crtcs); | |
9012 | WARN(pll->refcount != enabled_crtcs, | |
9013 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
9014 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
9015 | |
9016 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
9017 | sizeof(dpll_hw_state)), | |
9018 | "pll hw state mismatch\n"); | |
5358901f | 9019 | } |
8af6cf88 DV |
9020 | } |
9021 | ||
91d1b4bd DV |
9022 | void |
9023 | intel_modeset_check_state(struct drm_device *dev) | |
9024 | { | |
9025 | check_connector_state(dev); | |
9026 | check_encoder_state(dev); | |
9027 | check_crtc_state(dev); | |
9028 | check_shared_dpll_state(dev); | |
9029 | } | |
9030 | ||
18442d08 VS |
9031 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
9032 | int dotclock) | |
9033 | { | |
9034 | /* | |
9035 | * FDI already provided one idea for the dotclock. | |
9036 | * Yell if the encoder disagrees. | |
9037 | */ | |
9038 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.clock, dotclock), | |
9039 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
9040 | pipe_config->adjusted_mode.clock, dotclock); | |
9041 | } | |
9042 | ||
f30da187 DV |
9043 | static int __intel_set_mode(struct drm_crtc *crtc, |
9044 | struct drm_display_mode *mode, | |
9045 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
9046 | { |
9047 | struct drm_device *dev = crtc->dev; | |
dbf2b54e | 9048 | drm_i915_private_t *dev_priv = dev->dev_private; |
b8cecdf5 DV |
9049 | struct drm_display_mode *saved_mode, *saved_hwmode; |
9050 | struct intel_crtc_config *pipe_config = NULL; | |
25c5b266 DV |
9051 | struct intel_crtc *intel_crtc; |
9052 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 9053 | int ret = 0; |
a6778b3c | 9054 | |
a1e22653 | 9055 | saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
9056 | if (!saved_mode) |
9057 | return -ENOMEM; | |
3ac18232 | 9058 | saved_hwmode = saved_mode + 1; |
a6778b3c | 9059 | |
e2e1ed41 | 9060 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
9061 | &prepare_pipes, &disable_pipes); |
9062 | ||
3ac18232 TG |
9063 | *saved_hwmode = crtc->hwmode; |
9064 | *saved_mode = crtc->mode; | |
a6778b3c | 9065 | |
25c5b266 DV |
9066 | /* Hack: Because we don't (yet) support global modeset on multiple |
9067 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
9068 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
9069 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
9070 | * changing their mode at the same time. */ | |
25c5b266 | 9071 | if (modeset_pipes) { |
4e53c2e0 | 9072 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
9073 | if (IS_ERR(pipe_config)) { |
9074 | ret = PTR_ERR(pipe_config); | |
9075 | pipe_config = NULL; | |
9076 | ||
3ac18232 | 9077 | goto out; |
25c5b266 | 9078 | } |
c0b03411 DV |
9079 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
9080 | "[modeset]"); | |
25c5b266 | 9081 | } |
a6778b3c | 9082 | |
460da916 DV |
9083 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
9084 | intel_crtc_disable(&intel_crtc->base); | |
9085 | ||
ea9d758d DV |
9086 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
9087 | if (intel_crtc->base.enabled) | |
9088 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
9089 | } | |
a6778b3c | 9090 | |
6c4c86f5 DV |
9091 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
9092 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 9093 | */ |
b8cecdf5 | 9094 | if (modeset_pipes) { |
25c5b266 | 9095 | crtc->mode = *mode; |
b8cecdf5 DV |
9096 | /* mode_set/enable/disable functions rely on a correct pipe |
9097 | * config. */ | |
9098 | to_intel_crtc(crtc)->config = *pipe_config; | |
9099 | } | |
7758a113 | 9100 | |
ea9d758d DV |
9101 | /* Only after disabling all output pipelines that will be changed can we |
9102 | * update the the output configuration. */ | |
9103 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 9104 | |
47fab737 DV |
9105 | if (dev_priv->display.modeset_global_resources) |
9106 | dev_priv->display.modeset_global_resources(dev); | |
9107 | ||
a6778b3c DV |
9108 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
9109 | * on the DPLL. | |
f6e5b160 | 9110 | */ |
25c5b266 | 9111 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
c0c36b94 | 9112 | ret = intel_crtc_mode_set(&intel_crtc->base, |
c0c36b94 CW |
9113 | x, y, fb); |
9114 | if (ret) | |
9115 | goto done; | |
a6778b3c DV |
9116 | } |
9117 | ||
9118 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
25c5b266 DV |
9119 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) |
9120 | dev_priv->display.crtc_enable(&intel_crtc->base); | |
a6778b3c | 9121 | |
25c5b266 DV |
9122 | if (modeset_pipes) { |
9123 | /* Store real post-adjustment hardware mode. */ | |
b8cecdf5 | 9124 | crtc->hwmode = pipe_config->adjusted_mode; |
a6778b3c | 9125 | |
25c5b266 DV |
9126 | /* Calculate and store various constants which |
9127 | * are later needed by vblank and swap-completion | |
9128 | * timestamping. They are derived from true hwmode. | |
9129 | */ | |
9130 | drm_calc_timestamping_constants(crtc); | |
9131 | } | |
a6778b3c DV |
9132 | |
9133 | /* FIXME: add subpixel order */ | |
9134 | done: | |
c0c36b94 | 9135 | if (ret && crtc->enabled) { |
3ac18232 TG |
9136 | crtc->hwmode = *saved_hwmode; |
9137 | crtc->mode = *saved_mode; | |
a6778b3c DV |
9138 | } |
9139 | ||
3ac18232 | 9140 | out: |
b8cecdf5 | 9141 | kfree(pipe_config); |
3ac18232 | 9142 | kfree(saved_mode); |
a6778b3c | 9143 | return ret; |
f6e5b160 CW |
9144 | } |
9145 | ||
e7457a9a DL |
9146 | static int intel_set_mode(struct drm_crtc *crtc, |
9147 | struct drm_display_mode *mode, | |
9148 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
9149 | { |
9150 | int ret; | |
9151 | ||
9152 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
9153 | ||
9154 | if (ret == 0) | |
9155 | intel_modeset_check_state(crtc->dev); | |
9156 | ||
9157 | return ret; | |
9158 | } | |
9159 | ||
c0c36b94 CW |
9160 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
9161 | { | |
9162 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); | |
9163 | } | |
9164 | ||
25c5b266 DV |
9165 | #undef for_each_intel_crtc_masked |
9166 | ||
d9e55608 DV |
9167 | static void intel_set_config_free(struct intel_set_config *config) |
9168 | { | |
9169 | if (!config) | |
9170 | return; | |
9171 | ||
1aa4b628 DV |
9172 | kfree(config->save_connector_encoders); |
9173 | kfree(config->save_encoder_crtcs); | |
d9e55608 DV |
9174 | kfree(config); |
9175 | } | |
9176 | ||
85f9eb71 DV |
9177 | static int intel_set_config_save_state(struct drm_device *dev, |
9178 | struct intel_set_config *config) | |
9179 | { | |
85f9eb71 DV |
9180 | struct drm_encoder *encoder; |
9181 | struct drm_connector *connector; | |
9182 | int count; | |
9183 | ||
1aa4b628 DV |
9184 | config->save_encoder_crtcs = |
9185 | kcalloc(dev->mode_config.num_encoder, | |
9186 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
9187 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
9188 | return -ENOMEM; |
9189 | ||
1aa4b628 DV |
9190 | config->save_connector_encoders = |
9191 | kcalloc(dev->mode_config.num_connector, | |
9192 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
9193 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
9194 | return -ENOMEM; |
9195 | ||
9196 | /* Copy data. Note that driver private data is not affected. | |
9197 | * Should anything bad happen only the expected state is | |
9198 | * restored, not the drivers personal bookkeeping. | |
9199 | */ | |
85f9eb71 DV |
9200 | count = 0; |
9201 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 9202 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
9203 | } |
9204 | ||
9205 | count = 0; | |
9206 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 9207 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
9208 | } |
9209 | ||
9210 | return 0; | |
9211 | } | |
9212 | ||
9213 | static void intel_set_config_restore_state(struct drm_device *dev, | |
9214 | struct intel_set_config *config) | |
9215 | { | |
9a935856 DV |
9216 | struct intel_encoder *encoder; |
9217 | struct intel_connector *connector; | |
85f9eb71 DV |
9218 | int count; |
9219 | ||
85f9eb71 | 9220 | count = 0; |
9a935856 DV |
9221 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9222 | encoder->new_crtc = | |
9223 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
9224 | } |
9225 | ||
9226 | count = 0; | |
9a935856 DV |
9227 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
9228 | connector->new_encoder = | |
9229 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
9230 | } |
9231 | } | |
9232 | ||
e3de42b6 | 9233 | static bool |
2e57f47d | 9234 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
9235 | { |
9236 | int i; | |
9237 | ||
2e57f47d CW |
9238 | if (set->num_connectors == 0) |
9239 | return false; | |
9240 | ||
9241 | if (WARN_ON(set->connectors == NULL)) | |
9242 | return false; | |
9243 | ||
9244 | for (i = 0; i < set->num_connectors; i++) | |
9245 | if (set->connectors[i]->encoder && | |
9246 | set->connectors[i]->encoder->crtc == set->crtc && | |
9247 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
9248 | return true; |
9249 | ||
9250 | return false; | |
9251 | } | |
9252 | ||
5e2b584e DV |
9253 | static void |
9254 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
9255 | struct intel_set_config *config) | |
9256 | { | |
9257 | ||
9258 | /* We should be able to check here if the fb has the same properties | |
9259 | * and then just flip_or_move it */ | |
2e57f47d CW |
9260 | if (is_crtc_connector_off(set)) { |
9261 | config->mode_changed = true; | |
e3de42b6 | 9262 | } else if (set->crtc->fb != set->fb) { |
5e2b584e DV |
9263 | /* If we have no fb then treat it as a full mode set */ |
9264 | if (set->crtc->fb == NULL) { | |
319d9827 JB |
9265 | struct intel_crtc *intel_crtc = |
9266 | to_intel_crtc(set->crtc); | |
9267 | ||
9268 | if (intel_crtc->active && i915_fastboot) { | |
9269 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); | |
9270 | config->fb_changed = true; | |
9271 | } else { | |
9272 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
9273 | config->mode_changed = true; | |
9274 | } | |
5e2b584e DV |
9275 | } else if (set->fb == NULL) { |
9276 | config->mode_changed = true; | |
72f4901e DV |
9277 | } else if (set->fb->pixel_format != |
9278 | set->crtc->fb->pixel_format) { | |
5e2b584e | 9279 | config->mode_changed = true; |
e3de42b6 | 9280 | } else { |
5e2b584e | 9281 | config->fb_changed = true; |
e3de42b6 | 9282 | } |
5e2b584e DV |
9283 | } |
9284 | ||
835c5873 | 9285 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
9286 | config->fb_changed = true; |
9287 | ||
9288 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
9289 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
9290 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
9291 | drm_mode_debug_printmodeline(set->mode); | |
9292 | config->mode_changed = true; | |
9293 | } | |
a1d95703 CW |
9294 | |
9295 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
9296 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
9297 | } |
9298 | ||
2e431051 | 9299 | static int |
9a935856 DV |
9300 | intel_modeset_stage_output_state(struct drm_device *dev, |
9301 | struct drm_mode_set *set, | |
9302 | struct intel_set_config *config) | |
50f56119 | 9303 | { |
85f9eb71 | 9304 | struct drm_crtc *new_crtc; |
9a935856 DV |
9305 | struct intel_connector *connector; |
9306 | struct intel_encoder *encoder; | |
f3f08572 | 9307 | int ro; |
50f56119 | 9308 | |
9abdda74 | 9309 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
9310 | * of connectors. For paranoia, double-check this. */ |
9311 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
9312 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
9313 | ||
9a935856 DV |
9314 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9315 | base.head) { | |
9316 | /* Otherwise traverse passed in connector list and get encoders | |
9317 | * for them. */ | |
50f56119 | 9318 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 DV |
9319 | if (set->connectors[ro] == &connector->base) { |
9320 | connector->new_encoder = connector->encoder; | |
50f56119 DV |
9321 | break; |
9322 | } | |
9323 | } | |
9324 | ||
9a935856 DV |
9325 | /* If we disable the crtc, disable all its connectors. Also, if |
9326 | * the connector is on the changing crtc but not on the new | |
9327 | * connector list, disable it. */ | |
9328 | if ((!set->fb || ro == set->num_connectors) && | |
9329 | connector->base.encoder && | |
9330 | connector->base.encoder->crtc == set->crtc) { | |
9331 | connector->new_encoder = NULL; | |
9332 | ||
9333 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
9334 | connector->base.base.id, | |
9335 | drm_get_connector_name(&connector->base)); | |
9336 | } | |
9337 | ||
9338 | ||
9339 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 9340 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 9341 | config->mode_changed = true; |
50f56119 DV |
9342 | } |
9343 | } | |
9a935856 | 9344 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 9345 | |
9a935856 | 9346 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
9347 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9348 | base.head) { | |
9349 | if (!connector->new_encoder) | |
50f56119 DV |
9350 | continue; |
9351 | ||
9a935856 | 9352 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
9353 | |
9354 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 9355 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
9356 | new_crtc = set->crtc; |
9357 | } | |
9358 | ||
9359 | /* Make sure the new CRTC will work with the encoder */ | |
9a935856 DV |
9360 | if (!intel_encoder_crtc_ok(&connector->new_encoder->base, |
9361 | new_crtc)) { | |
5e2b584e | 9362 | return -EINVAL; |
50f56119 | 9363 | } |
9a935856 DV |
9364 | connector->encoder->new_crtc = to_intel_crtc(new_crtc); |
9365 | ||
9366 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
9367 | connector->base.base.id, | |
9368 | drm_get_connector_name(&connector->base), | |
9369 | new_crtc->base.id); | |
9370 | } | |
9371 | ||
9372 | /* Check for any encoders that needs to be disabled. */ | |
9373 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
9374 | base.head) { | |
9375 | list_for_each_entry(connector, | |
9376 | &dev->mode_config.connector_list, | |
9377 | base.head) { | |
9378 | if (connector->new_encoder == encoder) { | |
9379 | WARN_ON(!connector->new_encoder->new_crtc); | |
9380 | ||
9381 | goto next_encoder; | |
9382 | } | |
9383 | } | |
9384 | encoder->new_crtc = NULL; | |
9385 | next_encoder: | |
9386 | /* Only now check for crtc changes so we don't miss encoders | |
9387 | * that will be disabled. */ | |
9388 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 9389 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 9390 | config->mode_changed = true; |
50f56119 DV |
9391 | } |
9392 | } | |
9a935856 | 9393 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
50f56119 | 9394 | |
2e431051 DV |
9395 | return 0; |
9396 | } | |
9397 | ||
9398 | static int intel_crtc_set_config(struct drm_mode_set *set) | |
9399 | { | |
9400 | struct drm_device *dev; | |
2e431051 DV |
9401 | struct drm_mode_set save_set; |
9402 | struct intel_set_config *config; | |
9403 | int ret; | |
2e431051 | 9404 | |
8d3e375e DV |
9405 | BUG_ON(!set); |
9406 | BUG_ON(!set->crtc); | |
9407 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 9408 | |
7e53f3a4 DV |
9409 | /* Enforce sane interface api - has been abused by the fb helper. */ |
9410 | BUG_ON(!set->mode && set->fb); | |
9411 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 9412 | |
2e431051 DV |
9413 | if (set->fb) { |
9414 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
9415 | set->crtc->base.id, set->fb->base.id, | |
9416 | (int)set->num_connectors, set->x, set->y); | |
9417 | } else { | |
9418 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
9419 | } |
9420 | ||
9421 | dev = set->crtc->dev; | |
9422 | ||
9423 | ret = -ENOMEM; | |
9424 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
9425 | if (!config) | |
9426 | goto out_config; | |
9427 | ||
9428 | ret = intel_set_config_save_state(dev, config); | |
9429 | if (ret) | |
9430 | goto out_config; | |
9431 | ||
9432 | save_set.crtc = set->crtc; | |
9433 | save_set.mode = &set->crtc->mode; | |
9434 | save_set.x = set->crtc->x; | |
9435 | save_set.y = set->crtc->y; | |
9436 | save_set.fb = set->crtc->fb; | |
9437 | ||
9438 | /* Compute whether we need a full modeset, only an fb base update or no | |
9439 | * change at all. In the future we might also check whether only the | |
9440 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
9441 | * such cases. */ | |
9442 | intel_set_config_compute_mode_changes(set, config); | |
9443 | ||
9a935856 | 9444 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
9445 | if (ret) |
9446 | goto fail; | |
9447 | ||
5e2b584e | 9448 | if (config->mode_changed) { |
c0c36b94 CW |
9449 | ret = intel_set_mode(set->crtc, set->mode, |
9450 | set->x, set->y, set->fb); | |
5e2b584e | 9451 | } else if (config->fb_changed) { |
4878cae2 VS |
9452 | intel_crtc_wait_for_pending_flips(set->crtc); |
9453 | ||
4f660f49 | 9454 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 9455 | set->x, set->y, set->fb); |
50f56119 DV |
9456 | } |
9457 | ||
2d05eae1 | 9458 | if (ret) { |
bf67dfeb DV |
9459 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
9460 | set->crtc->base.id, ret); | |
50f56119 | 9461 | fail: |
2d05eae1 | 9462 | intel_set_config_restore_state(dev, config); |
50f56119 | 9463 | |
2d05eae1 CW |
9464 | /* Try to restore the config */ |
9465 | if (config->mode_changed && | |
9466 | intel_set_mode(save_set.crtc, save_set.mode, | |
9467 | save_set.x, save_set.y, save_set.fb)) | |
9468 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
9469 | } | |
50f56119 | 9470 | |
d9e55608 DV |
9471 | out_config: |
9472 | intel_set_config_free(config); | |
50f56119 DV |
9473 | return ret; |
9474 | } | |
f6e5b160 CW |
9475 | |
9476 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 CW |
9477 | .cursor_set = intel_crtc_cursor_set, |
9478 | .cursor_move = intel_crtc_cursor_move, | |
9479 | .gamma_set = intel_crtc_gamma_set, | |
50f56119 | 9480 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
9481 | .destroy = intel_crtc_destroy, |
9482 | .page_flip = intel_crtc_page_flip, | |
9483 | }; | |
9484 | ||
79f689aa PZ |
9485 | static void intel_cpu_pll_init(struct drm_device *dev) |
9486 | { | |
affa9354 | 9487 | if (HAS_DDI(dev)) |
79f689aa PZ |
9488 | intel_ddi_pll_init(dev); |
9489 | } | |
9490 | ||
5358901f DV |
9491 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
9492 | struct intel_shared_dpll *pll, | |
9493 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 9494 | { |
5358901f | 9495 | uint32_t val; |
ee7b9f93 | 9496 | |
5358901f | 9497 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
9498 | hw_state->dpll = val; |
9499 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
9500 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
9501 | |
9502 | return val & DPLL_VCO_ENABLE; | |
9503 | } | |
9504 | ||
15bdd4cf DV |
9505 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
9506 | struct intel_shared_dpll *pll) | |
9507 | { | |
9508 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
9509 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
9510 | } | |
9511 | ||
e7b903d2 DV |
9512 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
9513 | struct intel_shared_dpll *pll) | |
9514 | { | |
e7b903d2 DV |
9515 | /* PCH refclock must be enabled first */ |
9516 | assert_pch_refclk_enabled(dev_priv); | |
9517 | ||
15bdd4cf DV |
9518 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
9519 | ||
9520 | /* Wait for the clocks to stabilize. */ | |
9521 | POSTING_READ(PCH_DPLL(pll->id)); | |
9522 | udelay(150); | |
9523 | ||
9524 | /* The pixel multiplier can only be updated once the | |
9525 | * DPLL is enabled and the clocks are stable. | |
9526 | * | |
9527 | * So write it again. | |
9528 | */ | |
9529 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
9530 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
9531 | udelay(200); |
9532 | } | |
9533 | ||
9534 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
9535 | struct intel_shared_dpll *pll) | |
9536 | { | |
9537 | struct drm_device *dev = dev_priv->dev; | |
9538 | struct intel_crtc *crtc; | |
e7b903d2 DV |
9539 | |
9540 | /* Make sure no transcoder isn't still depending on us. */ | |
9541 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
9542 | if (intel_crtc_to_shared_dpll(crtc) == pll) | |
9543 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
9544 | } |
9545 | ||
15bdd4cf DV |
9546 | I915_WRITE(PCH_DPLL(pll->id), 0); |
9547 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
9548 | udelay(200); |
9549 | } | |
9550 | ||
46edb027 DV |
9551 | static char *ibx_pch_dpll_names[] = { |
9552 | "PCH DPLL A", | |
9553 | "PCH DPLL B", | |
9554 | }; | |
9555 | ||
7c74ade1 | 9556 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 9557 | { |
e7b903d2 | 9558 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
9559 | int i; |
9560 | ||
7c74ade1 | 9561 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 9562 | |
e72f9fbf | 9563 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
9564 | dev_priv->shared_dplls[i].id = i; |
9565 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 9566 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
9567 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
9568 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
9569 | dev_priv->shared_dplls[i].get_hw_state = |
9570 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
9571 | } |
9572 | } | |
9573 | ||
7c74ade1 DV |
9574 | static void intel_shared_dpll_init(struct drm_device *dev) |
9575 | { | |
e7b903d2 | 9576 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 DV |
9577 | |
9578 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
9579 | ibx_pch_dpll_init(dev); | |
9580 | else | |
9581 | dev_priv->num_shared_dpll = 0; | |
9582 | ||
9583 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
9584 | DRM_DEBUG_KMS("%i shared PLLs initialized\n", | |
9585 | dev_priv->num_shared_dpll); | |
9586 | } | |
9587 | ||
b358d0a6 | 9588 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 9589 | { |
22fd0fab | 9590 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
9591 | struct intel_crtc *intel_crtc; |
9592 | int i; | |
9593 | ||
955382f3 | 9594 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
9595 | if (intel_crtc == NULL) |
9596 | return; | |
9597 | ||
9598 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
9599 | ||
9600 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
9601 | for (i = 0; i < 256; i++) { |
9602 | intel_crtc->lut_r[i] = i; | |
9603 | intel_crtc->lut_g[i] = i; | |
9604 | intel_crtc->lut_b[i] = i; | |
9605 | } | |
9606 | ||
80824003 JB |
9607 | /* Swap pipes & planes for FBC on pre-965 */ |
9608 | intel_crtc->pipe = pipe; | |
9609 | intel_crtc->plane = pipe; | |
e2e767ab | 9610 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 9611 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 9612 | intel_crtc->plane = !pipe; |
80824003 JB |
9613 | } |
9614 | ||
22fd0fab JB |
9615 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
9616 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
9617 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
9618 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
9619 | ||
79e53945 | 9620 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
79e53945 JB |
9621 | } |
9622 | ||
08d7b3d1 | 9623 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 9624 | struct drm_file *file) |
08d7b3d1 | 9625 | { |
08d7b3d1 | 9626 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
c05422d5 DV |
9627 | struct drm_mode_object *drmmode_obj; |
9628 | struct intel_crtc *crtc; | |
08d7b3d1 | 9629 | |
1cff8f6b DV |
9630 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
9631 | return -ENODEV; | |
08d7b3d1 | 9632 | |
c05422d5 DV |
9633 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
9634 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 9635 | |
c05422d5 | 9636 | if (!drmmode_obj) { |
08d7b3d1 CW |
9637 | DRM_ERROR("no such CRTC id\n"); |
9638 | return -EINVAL; | |
9639 | } | |
9640 | ||
c05422d5 DV |
9641 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
9642 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 9643 | |
c05422d5 | 9644 | return 0; |
08d7b3d1 CW |
9645 | } |
9646 | ||
66a9278e | 9647 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 9648 | { |
66a9278e DV |
9649 | struct drm_device *dev = encoder->base.dev; |
9650 | struct intel_encoder *source_encoder; | |
79e53945 | 9651 | int index_mask = 0; |
79e53945 JB |
9652 | int entry = 0; |
9653 | ||
66a9278e DV |
9654 | list_for_each_entry(source_encoder, |
9655 | &dev->mode_config.encoder_list, base.head) { | |
9656 | ||
9657 | if (encoder == source_encoder) | |
79e53945 | 9658 | index_mask |= (1 << entry); |
66a9278e DV |
9659 | |
9660 | /* Intel hw has only one MUX where enocoders could be cloned. */ | |
9661 | if (encoder->cloneable && source_encoder->cloneable) | |
9662 | index_mask |= (1 << entry); | |
9663 | ||
79e53945 JB |
9664 | entry++; |
9665 | } | |
4ef69c7a | 9666 | |
79e53945 JB |
9667 | return index_mask; |
9668 | } | |
9669 | ||
4d302442 CW |
9670 | static bool has_edp_a(struct drm_device *dev) |
9671 | { | |
9672 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9673 | ||
9674 | if (!IS_MOBILE(dev)) | |
9675 | return false; | |
9676 | ||
9677 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
9678 | return false; | |
9679 | ||
9680 | if (IS_GEN5(dev) && | |
9681 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
9682 | return false; | |
9683 | ||
9684 | return true; | |
9685 | } | |
9686 | ||
79e53945 JB |
9687 | static void intel_setup_outputs(struct drm_device *dev) |
9688 | { | |
725e30ad | 9689 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 9690 | struct intel_encoder *encoder; |
cb0953d7 | 9691 | bool dpd_is_edp = false; |
79e53945 | 9692 | |
c9093354 | 9693 | intel_lvds_init(dev); |
79e53945 | 9694 | |
c40c0f5b | 9695 | if (!IS_ULT(dev)) |
79935fca | 9696 | intel_crt_init(dev); |
cb0953d7 | 9697 | |
affa9354 | 9698 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
9699 | int found; |
9700 | ||
9701 | /* Haswell uses DDI functions to detect digital outputs */ | |
9702 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
9703 | /* DDI A only supports eDP */ | |
9704 | if (found) | |
9705 | intel_ddi_init(dev, PORT_A); | |
9706 | ||
9707 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
9708 | * register */ | |
9709 | found = I915_READ(SFUSE_STRAP); | |
9710 | ||
9711 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
9712 | intel_ddi_init(dev, PORT_B); | |
9713 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
9714 | intel_ddi_init(dev, PORT_C); | |
9715 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
9716 | intel_ddi_init(dev, PORT_D); | |
9717 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 9718 | int found; |
270b3042 DV |
9719 | dpd_is_edp = intel_dpd_is_edp(dev); |
9720 | ||
9721 | if (has_edp_a(dev)) | |
9722 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 9723 | |
dc0fa718 | 9724 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 9725 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 9726 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 9727 | if (!found) |
e2debe91 | 9728 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 9729 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 9730 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
9731 | } |
9732 | ||
dc0fa718 | 9733 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 9734 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 9735 | |
dc0fa718 | 9736 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 9737 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 9738 | |
5eb08b69 | 9739 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 9740 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 9741 | |
270b3042 | 9742 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 9743 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 9744 | } else if (IS_VALLEYVIEW(dev)) { |
19c03924 | 9745 | /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */ |
6f6005a5 JB |
9746 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
9747 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
9748 | PORT_C); | |
9749 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
9750 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, | |
9751 | PORT_C); | |
9752 | } | |
19c03924 | 9753 | |
dc0fa718 | 9754 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
e2debe91 PZ |
9755 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
9756 | PORT_B); | |
67cfc203 VS |
9757 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) |
9758 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
4a87d65d | 9759 | } |
3cfca973 JN |
9760 | |
9761 | intel_dsi_init(dev); | |
103a196f | 9762 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 9763 | bool found = false; |
7d57382e | 9764 | |
e2debe91 | 9765 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 9766 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 9767 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
9768 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
9769 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 9770 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 9771 | } |
27185ae1 | 9772 | |
e7281eab | 9773 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 9774 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 9775 | } |
13520b05 KH |
9776 | |
9777 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 9778 | |
e2debe91 | 9779 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 9780 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 9781 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 9782 | } |
27185ae1 | 9783 | |
e2debe91 | 9784 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 9785 | |
b01f2c3a JB |
9786 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
9787 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 9788 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 9789 | } |
e7281eab | 9790 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 9791 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 9792 | } |
27185ae1 | 9793 | |
b01f2c3a | 9794 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 9795 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 9796 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 9797 | } else if (IS_GEN2(dev)) |
79e53945 JB |
9798 | intel_dvo_init(dev); |
9799 | ||
103a196f | 9800 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
9801 | intel_tv_init(dev); |
9802 | ||
4ef69c7a CW |
9803 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
9804 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
9805 | encoder->base.possible_clones = | |
66a9278e | 9806 | intel_encoder_clones(encoder); |
79e53945 | 9807 | } |
47356eb6 | 9808 | |
dde86e2d | 9809 | intel_init_pch_refclk(dev); |
270b3042 DV |
9810 | |
9811 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
9812 | } |
9813 | ||
ddfe1567 CW |
9814 | void intel_framebuffer_fini(struct intel_framebuffer *fb) |
9815 | { | |
9816 | drm_framebuffer_cleanup(&fb->base); | |
9817 | drm_gem_object_unreference_unlocked(&fb->obj->base); | |
9818 | } | |
9819 | ||
79e53945 JB |
9820 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) |
9821 | { | |
9822 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 9823 | |
ddfe1567 | 9824 | intel_framebuffer_fini(intel_fb); |
79e53945 JB |
9825 | kfree(intel_fb); |
9826 | } | |
9827 | ||
9828 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 9829 | struct drm_file *file, |
79e53945 JB |
9830 | unsigned int *handle) |
9831 | { | |
9832 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 9833 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 9834 | |
05394f39 | 9835 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
9836 | } |
9837 | ||
9838 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
9839 | .destroy = intel_user_framebuffer_destroy, | |
9840 | .create_handle = intel_user_framebuffer_create_handle, | |
9841 | }; | |
9842 | ||
38651674 DA |
9843 | int intel_framebuffer_init(struct drm_device *dev, |
9844 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 9845 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 9846 | struct drm_i915_gem_object *obj) |
79e53945 | 9847 | { |
a35cdaa0 | 9848 | int pitch_limit; |
79e53945 JB |
9849 | int ret; |
9850 | ||
c16ed4be CW |
9851 | if (obj->tiling_mode == I915_TILING_Y) { |
9852 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 9853 | return -EINVAL; |
c16ed4be | 9854 | } |
57cd6508 | 9855 | |
c16ed4be CW |
9856 | if (mode_cmd->pitches[0] & 63) { |
9857 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
9858 | mode_cmd->pitches[0]); | |
57cd6508 | 9859 | return -EINVAL; |
c16ed4be | 9860 | } |
57cd6508 | 9861 | |
a35cdaa0 CW |
9862 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
9863 | pitch_limit = 32*1024; | |
9864 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
9865 | if (obj->tiling_mode) | |
9866 | pitch_limit = 16*1024; | |
9867 | else | |
9868 | pitch_limit = 32*1024; | |
9869 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
9870 | if (obj->tiling_mode) | |
9871 | pitch_limit = 8*1024; | |
9872 | else | |
9873 | pitch_limit = 16*1024; | |
9874 | } else | |
9875 | /* XXX DSPC is limited to 4k tiled */ | |
9876 | pitch_limit = 8*1024; | |
9877 | ||
9878 | if (mode_cmd->pitches[0] > pitch_limit) { | |
9879 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
9880 | obj->tiling_mode ? "tiled" : "linear", | |
9881 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 9882 | return -EINVAL; |
c16ed4be | 9883 | } |
5d7bd705 VS |
9884 | |
9885 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
9886 | mode_cmd->pitches[0] != obj->stride) { |
9887 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
9888 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 9889 | return -EINVAL; |
c16ed4be | 9890 | } |
5d7bd705 | 9891 | |
57779d06 | 9892 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 9893 | switch (mode_cmd->pixel_format) { |
57779d06 | 9894 | case DRM_FORMAT_C8: |
04b3924d VS |
9895 | case DRM_FORMAT_RGB565: |
9896 | case DRM_FORMAT_XRGB8888: | |
9897 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
9898 | break; |
9899 | case DRM_FORMAT_XRGB1555: | |
9900 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 9901 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
9902 | DRM_DEBUG("unsupported pixel format: %s\n", |
9903 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 9904 | return -EINVAL; |
c16ed4be | 9905 | } |
57779d06 VS |
9906 | break; |
9907 | case DRM_FORMAT_XBGR8888: | |
9908 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
9909 | case DRM_FORMAT_XRGB2101010: |
9910 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
9911 | case DRM_FORMAT_XBGR2101010: |
9912 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 9913 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
9914 | DRM_DEBUG("unsupported pixel format: %s\n", |
9915 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 9916 | return -EINVAL; |
c16ed4be | 9917 | } |
b5626747 | 9918 | break; |
04b3924d VS |
9919 | case DRM_FORMAT_YUYV: |
9920 | case DRM_FORMAT_UYVY: | |
9921 | case DRM_FORMAT_YVYU: | |
9922 | case DRM_FORMAT_VYUY: | |
c16ed4be | 9923 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
9924 | DRM_DEBUG("unsupported pixel format: %s\n", |
9925 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 9926 | return -EINVAL; |
c16ed4be | 9927 | } |
57cd6508 CW |
9928 | break; |
9929 | default: | |
4ee62c76 VS |
9930 | DRM_DEBUG("unsupported pixel format: %s\n", |
9931 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
9932 | return -EINVAL; |
9933 | } | |
9934 | ||
90f9a336 VS |
9935 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
9936 | if (mode_cmd->offsets[0] != 0) | |
9937 | return -EINVAL; | |
9938 | ||
c7d73f6a DV |
9939 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
9940 | intel_fb->obj = obj; | |
9941 | ||
79e53945 JB |
9942 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
9943 | if (ret) { | |
9944 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
9945 | return ret; | |
9946 | } | |
9947 | ||
79e53945 JB |
9948 | return 0; |
9949 | } | |
9950 | ||
79e53945 JB |
9951 | static struct drm_framebuffer * |
9952 | intel_user_framebuffer_create(struct drm_device *dev, | |
9953 | struct drm_file *filp, | |
308e5bcb | 9954 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 9955 | { |
05394f39 | 9956 | struct drm_i915_gem_object *obj; |
79e53945 | 9957 | |
308e5bcb JB |
9958 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
9959 | mode_cmd->handles[0])); | |
c8725226 | 9960 | if (&obj->base == NULL) |
cce13ff7 | 9961 | return ERR_PTR(-ENOENT); |
79e53945 | 9962 | |
d2dff872 | 9963 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
9964 | } |
9965 | ||
79e53945 | 9966 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 9967 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 9968 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
9969 | }; |
9970 | ||
e70236a8 JB |
9971 | /* Set up chip specific display functions */ |
9972 | static void intel_init_display(struct drm_device *dev) | |
9973 | { | |
9974 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9975 | ||
ee9300bb DV |
9976 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
9977 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
9978 | else if (IS_VALLEYVIEW(dev)) | |
9979 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
9980 | else if (IS_PINEVIEW(dev)) | |
9981 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
9982 | else | |
9983 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
9984 | ||
affa9354 | 9985 | if (HAS_DDI(dev)) { |
0e8ffe1b | 9986 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
09b4ddf9 | 9987 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
9988 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
9989 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
6441ab5f | 9990 | dev_priv->display.off = haswell_crtc_off; |
09b4ddf9 PZ |
9991 | dev_priv->display.update_plane = ironlake_update_plane; |
9992 | } else if (HAS_PCH_SPLIT(dev)) { | |
0e8ffe1b | 9993 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
f564048e | 9994 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
9995 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
9996 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 9997 | dev_priv->display.off = ironlake_crtc_off; |
17638cd6 | 9998 | dev_priv->display.update_plane = ironlake_update_plane; |
89b667f8 JB |
9999 | } else if (IS_VALLEYVIEW(dev)) { |
10000 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
10001 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; | |
10002 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
10003 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
10004 | dev_priv->display.off = i9xx_crtc_off; | |
10005 | dev_priv->display.update_plane = i9xx_update_plane; | |
f564048e | 10006 | } else { |
0e8ffe1b | 10007 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
f564048e | 10008 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
10009 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
10010 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 10011 | dev_priv->display.off = i9xx_crtc_off; |
17638cd6 | 10012 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 10013 | } |
e70236a8 | 10014 | |
e70236a8 | 10015 | /* Returns the core display clock speed */ |
25eb05fc JB |
10016 | if (IS_VALLEYVIEW(dev)) |
10017 | dev_priv->display.get_display_clock_speed = | |
10018 | valleyview_get_display_clock_speed; | |
10019 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
10020 | dev_priv->display.get_display_clock_speed = |
10021 | i945_get_display_clock_speed; | |
10022 | else if (IS_I915G(dev)) | |
10023 | dev_priv->display.get_display_clock_speed = | |
10024 | i915_get_display_clock_speed; | |
257a7ffc | 10025 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
10026 | dev_priv->display.get_display_clock_speed = |
10027 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
10028 | else if (IS_PINEVIEW(dev)) |
10029 | dev_priv->display.get_display_clock_speed = | |
10030 | pnv_get_display_clock_speed; | |
e70236a8 JB |
10031 | else if (IS_I915GM(dev)) |
10032 | dev_priv->display.get_display_clock_speed = | |
10033 | i915gm_get_display_clock_speed; | |
10034 | else if (IS_I865G(dev)) | |
10035 | dev_priv->display.get_display_clock_speed = | |
10036 | i865_get_display_clock_speed; | |
f0f8a9ce | 10037 | else if (IS_I85X(dev)) |
e70236a8 JB |
10038 | dev_priv->display.get_display_clock_speed = |
10039 | i855_get_display_clock_speed; | |
10040 | else /* 852, 830 */ | |
10041 | dev_priv->display.get_display_clock_speed = | |
10042 | i830_get_display_clock_speed; | |
10043 | ||
7f8a8569 | 10044 | if (HAS_PCH_SPLIT(dev)) { |
f00a3ddf | 10045 | if (IS_GEN5(dev)) { |
674cf967 | 10046 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
e0dac65e | 10047 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a | 10048 | } else if (IS_GEN6(dev)) { |
674cf967 | 10049 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
e0dac65e | 10050 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
10051 | } else if (IS_IVYBRIDGE(dev)) { |
10052 | /* FIXME: detect B0+ stepping and use auto training */ | |
10053 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
e0dac65e | 10054 | dev_priv->display.write_eld = ironlake_write_eld; |
01a415fd DV |
10055 | dev_priv->display.modeset_global_resources = |
10056 | ivb_modeset_global_resources; | |
c82e4d26 ED |
10057 | } else if (IS_HASWELL(dev)) { |
10058 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; | |
83358c85 | 10059 | dev_priv->display.write_eld = haswell_write_eld; |
d6dd9eb1 DV |
10060 | dev_priv->display.modeset_global_resources = |
10061 | haswell_modeset_global_resources; | |
a0e63c22 | 10062 | } |
6067aaea | 10063 | } else if (IS_G4X(dev)) { |
e0dac65e | 10064 | dev_priv->display.write_eld = g4x_write_eld; |
e70236a8 | 10065 | } |
8c9f3aaf JB |
10066 | |
10067 | /* Default just returns -ENODEV to indicate unsupported */ | |
10068 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
10069 | ||
10070 | switch (INTEL_INFO(dev)->gen) { | |
10071 | case 2: | |
10072 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
10073 | break; | |
10074 | ||
10075 | case 3: | |
10076 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
10077 | break; | |
10078 | ||
10079 | case 4: | |
10080 | case 5: | |
10081 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
10082 | break; | |
10083 | ||
10084 | case 6: | |
10085 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
10086 | break; | |
7c9017e5 JB |
10087 | case 7: |
10088 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
10089 | break; | |
8c9f3aaf | 10090 | } |
e70236a8 JB |
10091 | } |
10092 | ||
b690e96c JB |
10093 | /* |
10094 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
10095 | * resume, or other times. This quirk makes sure that's the case for | |
10096 | * affected systems. | |
10097 | */ | |
0206e353 | 10098 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
10099 | { |
10100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10101 | ||
10102 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 10103 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
10104 | } |
10105 | ||
435793df KP |
10106 | /* |
10107 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
10108 | */ | |
10109 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
10110 | { | |
10111 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10112 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 10113 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
10114 | } |
10115 | ||
4dca20ef | 10116 | /* |
5a15ab5b CE |
10117 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
10118 | * brightness value | |
4dca20ef CE |
10119 | */ |
10120 | static void quirk_invert_brightness(struct drm_device *dev) | |
10121 | { | |
10122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10123 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 10124 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
10125 | } |
10126 | ||
e85843be KM |
10127 | /* |
10128 | * Some machines (Dell XPS13) suffer broken backlight controls if | |
10129 | * BLM_PCH_PWM_ENABLE is set. | |
10130 | */ | |
10131 | static void quirk_no_pcm_pwm_enable(struct drm_device *dev) | |
10132 | { | |
10133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10134 | dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE; | |
10135 | DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n"); | |
10136 | } | |
10137 | ||
b690e96c JB |
10138 | struct intel_quirk { |
10139 | int device; | |
10140 | int subsystem_vendor; | |
10141 | int subsystem_device; | |
10142 | void (*hook)(struct drm_device *dev); | |
10143 | }; | |
10144 | ||
5f85f176 EE |
10145 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
10146 | struct intel_dmi_quirk { | |
10147 | void (*hook)(struct drm_device *dev); | |
10148 | const struct dmi_system_id (*dmi_id_list)[]; | |
10149 | }; | |
10150 | ||
10151 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
10152 | { | |
10153 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
10154 | return 1; | |
10155 | } | |
10156 | ||
10157 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
10158 | { | |
10159 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
10160 | { | |
10161 | .callback = intel_dmi_reverse_brightness, | |
10162 | .ident = "NCR Corporation", | |
10163 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
10164 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
10165 | }, | |
10166 | }, | |
10167 | { } /* terminating entry */ | |
10168 | }, | |
10169 | .hook = quirk_invert_brightness, | |
10170 | }, | |
10171 | }; | |
10172 | ||
c43b5634 | 10173 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 10174 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 10175 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 10176 | |
b690e96c JB |
10177 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
10178 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
10179 | ||
b690e96c JB |
10180 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
10181 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
10182 | ||
ccd0d36e | 10183 | /* 830/845 need to leave pipe A & dpll A up */ |
b690e96c | 10184 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
dcdaed6e | 10185 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, |
435793df KP |
10186 | |
10187 | /* Lenovo U160 cannot use SSC on LVDS */ | |
10188 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
10189 | |
10190 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
10191 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 10192 | |
ee1452d7 JN |
10193 | /* |
10194 | * All GM45 Acer (and its brands eMachines and Packard Bell) laptops | |
10195 | * seem to use inverted backlight PWM. | |
10196 | */ | |
10197 | { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness }, | |
e85843be KM |
10198 | |
10199 | /* Dell XPS13 HD Sandy Bridge */ | |
10200 | { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable }, | |
10201 | /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */ | |
10202 | { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable }, | |
b690e96c JB |
10203 | }; |
10204 | ||
10205 | static void intel_init_quirks(struct drm_device *dev) | |
10206 | { | |
10207 | struct pci_dev *d = dev->pdev; | |
10208 | int i; | |
10209 | ||
10210 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
10211 | struct intel_quirk *q = &intel_quirks[i]; | |
10212 | ||
10213 | if (d->device == q->device && | |
10214 | (d->subsystem_vendor == q->subsystem_vendor || | |
10215 | q->subsystem_vendor == PCI_ANY_ID) && | |
10216 | (d->subsystem_device == q->subsystem_device || | |
10217 | q->subsystem_device == PCI_ANY_ID)) | |
10218 | q->hook(dev); | |
10219 | } | |
5f85f176 EE |
10220 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
10221 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
10222 | intel_dmi_quirks[i].hook(dev); | |
10223 | } | |
b690e96c JB |
10224 | } |
10225 | ||
9cce37f4 JB |
10226 | /* Disable the VGA plane that we never use */ |
10227 | static void i915_disable_vga(struct drm_device *dev) | |
10228 | { | |
10229 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10230 | u8 sr1; | |
766aa1c4 | 10231 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 JB |
10232 | |
10233 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
3fdcf431 | 10234 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
10235 | sr1 = inb(VGA_SR_DATA); |
10236 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
10237 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10238 | udelay(300); | |
10239 | ||
10240 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
10241 | POSTING_READ(vga_reg); | |
10242 | } | |
10243 | ||
6e1b4fda | 10244 | static void i915_enable_vga_mem(struct drm_device *dev) |
81b5c7bc AW |
10245 | { |
10246 | /* Enable VGA memory on Intel HD */ | |
10247 | if (HAS_PCH_SPLIT(dev)) { | |
10248 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10249 | outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE); | |
10250 | vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO | | |
10251 | VGA_RSRC_LEGACY_MEM | | |
10252 | VGA_RSRC_NORMAL_IO | | |
10253 | VGA_RSRC_NORMAL_MEM); | |
10254 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10255 | } | |
10256 | } | |
10257 | ||
6e1b4fda VS |
10258 | void i915_disable_vga_mem(struct drm_device *dev) |
10259 | { | |
10260 | /* Disable VGA memory on Intel HD */ | |
10261 | if (HAS_PCH_SPLIT(dev)) { | |
10262 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10263 | outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE); | |
10264 | vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO | | |
10265 | VGA_RSRC_NORMAL_IO | | |
10266 | VGA_RSRC_NORMAL_MEM); | |
10267 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
10268 | } | |
10269 | } | |
10270 | ||
f817586c DV |
10271 | void intel_modeset_init_hw(struct drm_device *dev) |
10272 | { | |
a8f78b58 ED |
10273 | intel_prepare_ddi(dev); |
10274 | ||
f817586c DV |
10275 | intel_init_clock_gating(dev); |
10276 | ||
79f5b2c7 | 10277 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 10278 | intel_enable_gt_powersave(dev); |
79f5b2c7 | 10279 | mutex_unlock(&dev->struct_mutex); |
f817586c DV |
10280 | } |
10281 | ||
7d708ee4 ID |
10282 | void intel_modeset_suspend_hw(struct drm_device *dev) |
10283 | { | |
10284 | intel_suspend_hw(dev); | |
10285 | } | |
10286 | ||
79e53945 JB |
10287 | void intel_modeset_init(struct drm_device *dev) |
10288 | { | |
652c393a | 10289 | struct drm_i915_private *dev_priv = dev->dev_private; |
7f1f3851 | 10290 | int i, j, ret; |
79e53945 JB |
10291 | |
10292 | drm_mode_config_init(dev); | |
10293 | ||
10294 | dev->mode_config.min_width = 0; | |
10295 | dev->mode_config.min_height = 0; | |
10296 | ||
019d96cb DA |
10297 | dev->mode_config.preferred_depth = 24; |
10298 | dev->mode_config.prefer_shadow = 1; | |
10299 | ||
e6ecefaa | 10300 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 10301 | |
b690e96c JB |
10302 | intel_init_quirks(dev); |
10303 | ||
1fa61106 ED |
10304 | intel_init_pm(dev); |
10305 | ||
e3c74757 BW |
10306 | if (INTEL_INFO(dev)->num_pipes == 0) |
10307 | return; | |
10308 | ||
e70236a8 JB |
10309 | intel_init_display(dev); |
10310 | ||
a6c45cf0 CW |
10311 | if (IS_GEN2(dev)) { |
10312 | dev->mode_config.max_width = 2048; | |
10313 | dev->mode_config.max_height = 2048; | |
10314 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
10315 | dev->mode_config.max_width = 4096; |
10316 | dev->mode_config.max_height = 4096; | |
79e53945 | 10317 | } else { |
a6c45cf0 CW |
10318 | dev->mode_config.max_width = 8192; |
10319 | dev->mode_config.max_height = 8192; | |
79e53945 | 10320 | } |
5d4545ae | 10321 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 10322 | |
28c97730 | 10323 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
10324 | INTEL_INFO(dev)->num_pipes, |
10325 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 10326 | |
08e2a7de | 10327 | for_each_pipe(i) { |
79e53945 | 10328 | intel_crtc_init(dev, i); |
7f1f3851 JB |
10329 | for (j = 0; j < dev_priv->num_plane; j++) { |
10330 | ret = intel_plane_init(dev, i, j); | |
10331 | if (ret) | |
06da8da2 VS |
10332 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
10333 | pipe_name(i), sprite_name(i, j), ret); | |
7f1f3851 | 10334 | } |
79e53945 JB |
10335 | } |
10336 | ||
79f689aa | 10337 | intel_cpu_pll_init(dev); |
e72f9fbf | 10338 | intel_shared_dpll_init(dev); |
ee7b9f93 | 10339 | |
9cce37f4 JB |
10340 | /* Just disable it once at startup */ |
10341 | i915_disable_vga(dev); | |
79e53945 | 10342 | intel_setup_outputs(dev); |
11be49eb CW |
10343 | |
10344 | /* Just in case the BIOS is doing something questionable. */ | |
10345 | intel_disable_fbc(dev); | |
2c7111db CW |
10346 | } |
10347 | ||
24929352 DV |
10348 | static void |
10349 | intel_connector_break_all_links(struct intel_connector *connector) | |
10350 | { | |
10351 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
10352 | connector->base.encoder = NULL; | |
10353 | connector->encoder->connectors_active = false; | |
10354 | connector->encoder->base.crtc = NULL; | |
10355 | } | |
10356 | ||
7fad798e DV |
10357 | static void intel_enable_pipe_a(struct drm_device *dev) |
10358 | { | |
10359 | struct intel_connector *connector; | |
10360 | struct drm_connector *crt = NULL; | |
10361 | struct intel_load_detect_pipe load_detect_temp; | |
10362 | ||
10363 | /* We can't just switch on the pipe A, we need to set things up with a | |
10364 | * proper mode and output configuration. As a gross hack, enable pipe A | |
10365 | * by enabling the load detect pipe once. */ | |
10366 | list_for_each_entry(connector, | |
10367 | &dev->mode_config.connector_list, | |
10368 | base.head) { | |
10369 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
10370 | crt = &connector->base; | |
10371 | break; | |
10372 | } | |
10373 | } | |
10374 | ||
10375 | if (!crt) | |
10376 | return; | |
10377 | ||
10378 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) | |
10379 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
10380 | ||
652c393a | 10381 | |
7fad798e DV |
10382 | } |
10383 | ||
fa555837 DV |
10384 | static bool |
10385 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
10386 | { | |
7eb552ae BW |
10387 | struct drm_device *dev = crtc->base.dev; |
10388 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
10389 | u32 reg, val; |
10390 | ||
7eb552ae | 10391 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
10392 | return true; |
10393 | ||
10394 | reg = DSPCNTR(!crtc->plane); | |
10395 | val = I915_READ(reg); | |
10396 | ||
10397 | if ((val & DISPLAY_PLANE_ENABLE) && | |
10398 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
10399 | return false; | |
10400 | ||
10401 | return true; | |
10402 | } | |
10403 | ||
24929352 DV |
10404 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
10405 | { | |
10406 | struct drm_device *dev = crtc->base.dev; | |
10407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 10408 | u32 reg; |
24929352 | 10409 | |
24929352 | 10410 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 10411 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
10412 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
10413 | ||
10414 | /* We need to sanitize the plane -> pipe mapping first because this will | |
fa555837 DV |
10415 | * disable the crtc (and hence change the state) if it is wrong. Note |
10416 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
10417 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
10418 | struct intel_connector *connector; |
10419 | bool plane; | |
10420 | ||
24929352 DV |
10421 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
10422 | crtc->base.base.id); | |
10423 | ||
10424 | /* Pipe has the wrong plane attached and the plane is active. | |
10425 | * Temporarily change the plane mapping and disable everything | |
10426 | * ... */ | |
10427 | plane = crtc->plane; | |
10428 | crtc->plane = !plane; | |
10429 | dev_priv->display.crtc_disable(&crtc->base); | |
10430 | crtc->plane = plane; | |
10431 | ||
10432 | /* ... and break all links. */ | |
10433 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10434 | base.head) { | |
10435 | if (connector->encoder->base.crtc != &crtc->base) | |
10436 | continue; | |
10437 | ||
10438 | intel_connector_break_all_links(connector); | |
10439 | } | |
10440 | ||
10441 | WARN_ON(crtc->active); | |
10442 | crtc->base.enabled = false; | |
10443 | } | |
24929352 | 10444 | |
7fad798e DV |
10445 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
10446 | crtc->pipe == PIPE_A && !crtc->active) { | |
10447 | /* BIOS forgot to enable pipe A, this mostly happens after | |
10448 | * resume. Force-enable the pipe to fix this, the update_dpms | |
10449 | * call below we restore the pipe to the right state, but leave | |
10450 | * the required bits on. */ | |
10451 | intel_enable_pipe_a(dev); | |
10452 | } | |
10453 | ||
24929352 DV |
10454 | /* Adjust the state of the output pipe according to whether we |
10455 | * have active connectors/encoders. */ | |
10456 | intel_crtc_update_dpms(&crtc->base); | |
10457 | ||
10458 | if (crtc->active != crtc->base.enabled) { | |
10459 | struct intel_encoder *encoder; | |
10460 | ||
10461 | /* This can happen either due to bugs in the get_hw_state | |
10462 | * functions or because the pipe is force-enabled due to the | |
10463 | * pipe A quirk. */ | |
10464 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
10465 | crtc->base.base.id, | |
10466 | crtc->base.enabled ? "enabled" : "disabled", | |
10467 | crtc->active ? "enabled" : "disabled"); | |
10468 | ||
10469 | crtc->base.enabled = crtc->active; | |
10470 | ||
10471 | /* Because we only establish the connector -> encoder -> | |
10472 | * crtc links if something is active, this means the | |
10473 | * crtc is now deactivated. Break the links. connector | |
10474 | * -> encoder links are only establish when things are | |
10475 | * actually up, hence no need to break them. */ | |
10476 | WARN_ON(crtc->active); | |
10477 | ||
10478 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
10479 | WARN_ON(encoder->connectors_active); | |
10480 | encoder->base.crtc = NULL; | |
10481 | } | |
10482 | } | |
10483 | } | |
10484 | ||
10485 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
10486 | { | |
10487 | struct intel_connector *connector; | |
10488 | struct drm_device *dev = encoder->base.dev; | |
10489 | ||
10490 | /* We need to check both for a crtc link (meaning that the | |
10491 | * encoder is active and trying to read from a pipe) and the | |
10492 | * pipe itself being active. */ | |
10493 | bool has_active_crtc = encoder->base.crtc && | |
10494 | to_intel_crtc(encoder->base.crtc)->active; | |
10495 | ||
10496 | if (encoder->connectors_active && !has_active_crtc) { | |
10497 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
10498 | encoder->base.base.id, | |
10499 | drm_get_encoder_name(&encoder->base)); | |
10500 | ||
10501 | /* Connector is active, but has no active pipe. This is | |
10502 | * fallout from our resume register restoring. Disable | |
10503 | * the encoder manually again. */ | |
10504 | if (encoder->base.crtc) { | |
10505 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
10506 | encoder->base.base.id, | |
10507 | drm_get_encoder_name(&encoder->base)); | |
10508 | encoder->disable(encoder); | |
10509 | } | |
10510 | ||
10511 | /* Inconsistent output/port/pipe state happens presumably due to | |
10512 | * a bug in one of the get_hw_state functions. Or someplace else | |
10513 | * in our code, like the register restore mess on resume. Clamp | |
10514 | * things to off as a safer default. */ | |
10515 | list_for_each_entry(connector, | |
10516 | &dev->mode_config.connector_list, | |
10517 | base.head) { | |
10518 | if (connector->encoder != encoder) | |
10519 | continue; | |
10520 | ||
10521 | intel_connector_break_all_links(connector); | |
10522 | } | |
10523 | } | |
10524 | /* Enabled encoders without active connectors will be fixed in | |
10525 | * the crtc fixup. */ | |
10526 | } | |
10527 | ||
44cec740 | 10528 | void i915_redisable_vga(struct drm_device *dev) |
0fde901f KM |
10529 | { |
10530 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 10531 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 10532 | |
8dc8a27c PZ |
10533 | /* This function can be called both from intel_modeset_setup_hw_state or |
10534 | * at a very early point in our resume sequence, where the power well | |
10535 | * structures are not yet restored. Since this function is at a very | |
10536 | * paranoid "someone might have enabled VGA while we were not looking" | |
10537 | * level, just check if the power well is enabled instead of trying to | |
10538 | * follow the "don't touch the power well if we don't need it" policy | |
10539 | * the rest of the driver uses. */ | |
10540 | if (HAS_POWER_WELL(dev) && | |
6aedd1f5 | 10541 | (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0) |
8dc8a27c PZ |
10542 | return; |
10543 | ||
0fde901f KM |
10544 | if (I915_READ(vga_reg) != VGA_DISP_DISABLE) { |
10545 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
209d5211 | 10546 | i915_disable_vga(dev); |
6e1b4fda | 10547 | i915_disable_vga_mem(dev); |
0fde901f KM |
10548 | } |
10549 | } | |
10550 | ||
30e984df | 10551 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
10552 | { |
10553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10554 | enum pipe pipe; | |
24929352 DV |
10555 | struct intel_crtc *crtc; |
10556 | struct intel_encoder *encoder; | |
10557 | struct intel_connector *connector; | |
5358901f | 10558 | int i; |
24929352 | 10559 | |
0e8ffe1b DV |
10560 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, |
10561 | base.head) { | |
88adfff1 | 10562 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 10563 | |
0e8ffe1b DV |
10564 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
10565 | &crtc->config); | |
24929352 DV |
10566 | |
10567 | crtc->base.enabled = crtc->active; | |
10568 | ||
10569 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
10570 | crtc->base.base.id, | |
10571 | crtc->active ? "enabled" : "disabled"); | |
10572 | } | |
10573 | ||
5358901f | 10574 | /* FIXME: Smash this into the new shared dpll infrastructure. */ |
affa9354 | 10575 | if (HAS_DDI(dev)) |
6441ab5f PZ |
10576 | intel_ddi_setup_hw_pll_state(dev); |
10577 | ||
5358901f DV |
10578 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
10579 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10580 | ||
10581 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
10582 | pll->active = 0; | |
10583 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
10584 | base.head) { | |
10585 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
10586 | pll->active++; | |
10587 | } | |
10588 | pll->refcount = pll->active; | |
10589 | ||
35c95375 DV |
10590 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
10591 | pll->name, pll->refcount, pll->on); | |
5358901f DV |
10592 | } |
10593 | ||
24929352 DV |
10594 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, |
10595 | base.head) { | |
10596 | pipe = 0; | |
10597 | ||
10598 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
10599 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
10600 | encoder->base.crtc = &crtc->base; | |
510d5f2f | 10601 | if (encoder->get_config) |
045ac3b5 | 10602 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
10603 | } else { |
10604 | encoder->base.crtc = NULL; | |
10605 | } | |
10606 | ||
10607 | encoder->connectors_active = false; | |
10608 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", | |
10609 | encoder->base.base.id, | |
10610 | drm_get_encoder_name(&encoder->base), | |
10611 | encoder->base.crtc ? "enabled" : "disabled", | |
10612 | pipe); | |
10613 | } | |
10614 | ||
10615 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10616 | base.head) { | |
10617 | if (connector->get_hw_state(connector)) { | |
10618 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
10619 | connector->encoder->connectors_active = true; | |
10620 | connector->base.encoder = &connector->encoder->base; | |
10621 | } else { | |
10622 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
10623 | connector->base.encoder = NULL; | |
10624 | } | |
10625 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
10626 | connector->base.base.id, | |
10627 | drm_get_connector_name(&connector->base), | |
10628 | connector->base.encoder ? "enabled" : "disabled"); | |
10629 | } | |
30e984df DV |
10630 | } |
10631 | ||
10632 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
10633 | * and i915 state tracking structures. */ | |
10634 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
10635 | bool force_restore) | |
10636 | { | |
10637 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10638 | enum pipe pipe; | |
10639 | struct drm_plane *plane; | |
10640 | struct intel_crtc *crtc; | |
10641 | struct intel_encoder *encoder; | |
35c95375 | 10642 | int i; |
30e984df DV |
10643 | |
10644 | intel_modeset_readout_hw_state(dev); | |
24929352 | 10645 | |
babea61d JB |
10646 | /* |
10647 | * Now that we have the config, copy it to each CRTC struct | |
10648 | * Note that this could go away if we move to using crtc_config | |
10649 | * checking everywhere. | |
10650 | */ | |
10651 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, | |
10652 | base.head) { | |
10653 | if (crtc->active && i915_fastboot) { | |
10654 | intel_crtc_mode_from_pipe_config(crtc, &crtc->config); | |
10655 | ||
10656 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", | |
10657 | crtc->base.base.id); | |
10658 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
10659 | } | |
10660 | } | |
10661 | ||
24929352 DV |
10662 | /* HW state is read out, now we need to sanitize this mess. */ |
10663 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
10664 | base.head) { | |
10665 | intel_sanitize_encoder(encoder); | |
10666 | } | |
10667 | ||
10668 | for_each_pipe(pipe) { | |
10669 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
10670 | intel_sanitize_crtc(crtc); | |
c0b03411 | 10671 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 10672 | } |
9a935856 | 10673 | |
35c95375 DV |
10674 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
10675 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10676 | ||
10677 | if (!pll->on || pll->active) | |
10678 | continue; | |
10679 | ||
10680 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
10681 | ||
10682 | pll->disable(dev_priv, pll); | |
10683 | pll->on = false; | |
10684 | } | |
10685 | ||
45e2b5f6 | 10686 | if (force_restore) { |
f30da187 DV |
10687 | /* |
10688 | * We need to use raw interfaces for restoring state to avoid | |
10689 | * checking (bogus) intermediate states. | |
10690 | */ | |
45e2b5f6 | 10691 | for_each_pipe(pipe) { |
b5644d05 JB |
10692 | struct drm_crtc *crtc = |
10693 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
10694 | |
10695 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
10696 | crtc->fb); | |
45e2b5f6 | 10697 | } |
b5644d05 JB |
10698 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) |
10699 | intel_plane_restore(plane); | |
0fde901f KM |
10700 | |
10701 | i915_redisable_vga(dev); | |
45e2b5f6 DV |
10702 | } else { |
10703 | intel_modeset_update_staged_output_state(dev); | |
10704 | } | |
8af6cf88 DV |
10705 | |
10706 | intel_modeset_check_state(dev); | |
2e938892 DV |
10707 | |
10708 | drm_mode_config_reset(dev); | |
2c7111db CW |
10709 | } |
10710 | ||
10711 | void intel_modeset_gem_init(struct drm_device *dev) | |
10712 | { | |
1833b134 | 10713 | intel_modeset_init_hw(dev); |
02e792fb DV |
10714 | |
10715 | intel_setup_overlay(dev); | |
24929352 | 10716 | |
45e2b5f6 | 10717 | intel_modeset_setup_hw_state(dev, false); |
79e53945 JB |
10718 | } |
10719 | ||
10720 | void intel_modeset_cleanup(struct drm_device *dev) | |
10721 | { | |
652c393a JB |
10722 | struct drm_i915_private *dev_priv = dev->dev_private; |
10723 | struct drm_crtc *crtc; | |
652c393a | 10724 | |
fd0c0642 DV |
10725 | /* |
10726 | * Interrupts and polling as the first thing to avoid creating havoc. | |
10727 | * Too much stuff here (turning of rps, connectors, ...) would | |
10728 | * experience fancy races otherwise. | |
10729 | */ | |
10730 | drm_irq_uninstall(dev); | |
10731 | cancel_work_sync(&dev_priv->hotplug_work); | |
10732 | /* | |
10733 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
10734 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
10735 | */ | |
f87ea761 | 10736 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 10737 | |
652c393a JB |
10738 | mutex_lock(&dev->struct_mutex); |
10739 | ||
723bfd70 JB |
10740 | intel_unregister_dsm_handler(); |
10741 | ||
652c393a JB |
10742 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
10743 | /* Skip inactive CRTCs */ | |
10744 | if (!crtc->fb) | |
10745 | continue; | |
10746 | ||
3dec0095 | 10747 | intel_increase_pllclock(crtc); |
652c393a JB |
10748 | } |
10749 | ||
973d04f9 | 10750 | intel_disable_fbc(dev); |
e70236a8 | 10751 | |
6e1b4fda | 10752 | i915_enable_vga_mem(dev); |
81b5c7bc | 10753 | |
8090c6b9 | 10754 | intel_disable_gt_powersave(dev); |
0cdab21f | 10755 | |
930ebb46 DV |
10756 | ironlake_teardown_rc6(dev); |
10757 | ||
69341a5e KH |
10758 | mutex_unlock(&dev->struct_mutex); |
10759 | ||
1630fe75 CW |
10760 | /* flush any delayed tasks or pending work */ |
10761 | flush_scheduled_work(); | |
10762 | ||
dc652f90 JN |
10763 | /* destroy backlight, if any, before the connectors */ |
10764 | intel_panel_destroy_backlight(dev); | |
10765 | ||
79e53945 | 10766 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
10767 | |
10768 | intel_cleanup_overlay(dev); | |
79e53945 JB |
10769 | } |
10770 | ||
f1c79df3 ZW |
10771 | /* |
10772 | * Return which encoder is currently attached for connector. | |
10773 | */ | |
df0e9248 | 10774 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 10775 | { |
df0e9248 CW |
10776 | return &intel_attached_encoder(connector)->base; |
10777 | } | |
f1c79df3 | 10778 | |
df0e9248 CW |
10779 | void intel_connector_attach_encoder(struct intel_connector *connector, |
10780 | struct intel_encoder *encoder) | |
10781 | { | |
10782 | connector->encoder = encoder; | |
10783 | drm_mode_connector_attach_encoder(&connector->base, | |
10784 | &encoder->base); | |
79e53945 | 10785 | } |
28d52043 DA |
10786 | |
10787 | /* | |
10788 | * set vga decode state - true == enable VGA decode | |
10789 | */ | |
10790 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
10791 | { | |
10792 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10793 | u16 gmch_ctrl; | |
10794 | ||
10795 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
10796 | if (state) | |
10797 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
10798 | else | |
10799 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
10800 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
10801 | return 0; | |
10802 | } | |
c4a1d9e4 | 10803 | |
c4a1d9e4 | 10804 | struct intel_display_error_state { |
ff57f1b0 PZ |
10805 | |
10806 | u32 power_well_driver; | |
10807 | ||
63b66e5b CW |
10808 | int num_transcoders; |
10809 | ||
c4a1d9e4 CW |
10810 | struct intel_cursor_error_state { |
10811 | u32 control; | |
10812 | u32 position; | |
10813 | u32 base; | |
10814 | u32 size; | |
52331309 | 10815 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
10816 | |
10817 | struct intel_pipe_error_state { | |
c4a1d9e4 | 10818 | u32 source; |
52331309 | 10819 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
10820 | |
10821 | struct intel_plane_error_state { | |
10822 | u32 control; | |
10823 | u32 stride; | |
10824 | u32 size; | |
10825 | u32 pos; | |
10826 | u32 addr; | |
10827 | u32 surface; | |
10828 | u32 tile_offset; | |
52331309 | 10829 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
10830 | |
10831 | struct intel_transcoder_error_state { | |
10832 | enum transcoder cpu_transcoder; | |
10833 | ||
10834 | u32 conf; | |
10835 | ||
10836 | u32 htotal; | |
10837 | u32 hblank; | |
10838 | u32 hsync; | |
10839 | u32 vtotal; | |
10840 | u32 vblank; | |
10841 | u32 vsync; | |
10842 | } transcoder[4]; | |
c4a1d9e4 CW |
10843 | }; |
10844 | ||
10845 | struct intel_display_error_state * | |
10846 | intel_display_capture_error_state(struct drm_device *dev) | |
10847 | { | |
0206e353 | 10848 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 | 10849 | struct intel_display_error_state *error; |
63b66e5b CW |
10850 | int transcoders[] = { |
10851 | TRANSCODER_A, | |
10852 | TRANSCODER_B, | |
10853 | TRANSCODER_C, | |
10854 | TRANSCODER_EDP, | |
10855 | }; | |
c4a1d9e4 CW |
10856 | int i; |
10857 | ||
63b66e5b CW |
10858 | if (INTEL_INFO(dev)->num_pipes == 0) |
10859 | return NULL; | |
10860 | ||
c4a1d9e4 CW |
10861 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
10862 | if (error == NULL) | |
10863 | return NULL; | |
10864 | ||
ff57f1b0 PZ |
10865 | if (HAS_POWER_WELL(dev)) |
10866 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); | |
10867 | ||
52331309 | 10868 | for_each_pipe(i) { |
a18c4c3d PZ |
10869 | if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { |
10870 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
10871 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
10872 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
10873 | } else { | |
10874 | error->cursor[i].control = I915_READ(CURCNTR_IVB(i)); | |
10875 | error->cursor[i].position = I915_READ(CURPOS_IVB(i)); | |
10876 | error->cursor[i].base = I915_READ(CURBASE_IVB(i)); | |
10877 | } | |
c4a1d9e4 CW |
10878 | |
10879 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
10880 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 10881 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 10882 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
10883 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
10884 | } | |
ca291363 PZ |
10885 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
10886 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
10887 | if (INTEL_INFO(dev)->gen >= 4) { |
10888 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
10889 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
10890 | } | |
10891 | ||
c4a1d9e4 | 10892 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
63b66e5b CW |
10893 | } |
10894 | ||
10895 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
10896 | if (HAS_DDI(dev_priv->dev)) | |
10897 | error->num_transcoders++; /* Account for eDP. */ | |
10898 | ||
10899 | for (i = 0; i < error->num_transcoders; i++) { | |
10900 | enum transcoder cpu_transcoder = transcoders[i]; | |
10901 | ||
10902 | error->transcoder[i].cpu_transcoder = cpu_transcoder; | |
10903 | ||
10904 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
10905 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
10906 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
10907 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10908 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
10909 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
10910 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
10911 | } |
10912 | ||
12d217c7 PZ |
10913 | /* In the code above we read the registers without checking if the power |
10914 | * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to | |
10915 | * prevent the next I915_WRITE from detecting it and printing an error | |
10916 | * message. */ | |
907b28c5 | 10917 | intel_uncore_clear_errors(dev); |
12d217c7 | 10918 | |
c4a1d9e4 CW |
10919 | return error; |
10920 | } | |
10921 | ||
edc3d884 MK |
10922 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
10923 | ||
c4a1d9e4 | 10924 | void |
edc3d884 | 10925 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
10926 | struct drm_device *dev, |
10927 | struct intel_display_error_state *error) | |
10928 | { | |
10929 | int i; | |
10930 | ||
63b66e5b CW |
10931 | if (!error) |
10932 | return; | |
10933 | ||
edc3d884 | 10934 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
ff57f1b0 | 10935 | if (HAS_POWER_WELL(dev)) |
edc3d884 | 10936 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 10937 | error->power_well_driver); |
52331309 | 10938 | for_each_pipe(i) { |
edc3d884 | 10939 | err_printf(m, "Pipe [%d]:\n", i); |
edc3d884 | 10940 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
edc3d884 MK |
10941 | |
10942 | err_printf(m, "Plane [%d]:\n", i); | |
10943 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
10944 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 10945 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
10946 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
10947 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 10948 | } |
4b71a570 | 10949 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 10950 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 10951 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
10952 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
10953 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
10954 | } |
10955 | ||
edc3d884 MK |
10956 | err_printf(m, "Cursor [%d]:\n", i); |
10957 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
10958 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
10959 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 10960 | } |
63b66e5b CW |
10961 | |
10962 | for (i = 0; i < error->num_transcoders; i++) { | |
10963 | err_printf(m, " CPU transcoder: %c\n", | |
10964 | transcoder_name(error->transcoder[i].cpu_transcoder)); | |
10965 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); | |
10966 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
10967 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
10968 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
10969 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
10970 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
10971 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
10972 | } | |
c4a1d9e4 | 10973 | } |