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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
42 | #include <drm/drm_plane_helper.h> |
43 | #include <drm/drm_rect.h> | |
c0f372b3 | 44 | #include <linux/dma_remapping.h> |
79e53945 | 45 | |
465c120c MR |
46 | /* Primary plane formats supported by all gen */ |
47 | #define COMMON_PRIMARY_FORMATS \ | |
48 | DRM_FORMAT_C8, \ | |
49 | DRM_FORMAT_RGB565, \ | |
50 | DRM_FORMAT_XRGB8888, \ | |
51 | DRM_FORMAT_ARGB8888 | |
52 | ||
53 | /* Primary plane formats for gen <= 3 */ | |
54 | static const uint32_t intel_primary_formats_gen2[] = { | |
55 | COMMON_PRIMARY_FORMATS, | |
56 | DRM_FORMAT_XRGB1555, | |
57 | DRM_FORMAT_ARGB1555, | |
58 | }; | |
59 | ||
60 | /* Primary plane formats for gen >= 4 */ | |
61 | static const uint32_t intel_primary_formats_gen4[] = { | |
62 | COMMON_PRIMARY_FORMATS, \ | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_ABGR8888, | |
65 | DRM_FORMAT_XRGB2101010, | |
66 | DRM_FORMAT_ARGB2101010, | |
67 | DRM_FORMAT_XBGR2101010, | |
68 | DRM_FORMAT_ABGR2101010, | |
69 | }; | |
70 | ||
3d7d6510 MR |
71 | /* Cursor formats */ |
72 | static const uint32_t intel_cursor_formats[] = { | |
73 | DRM_FORMAT_ARGB8888, | |
74 | }; | |
75 | ||
6b383a7f | 76 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 77 | |
f1f644dc JB |
78 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
79 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
80 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
81 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 82 | |
e7457a9a DL |
83 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
84 | int x, int y, struct drm_framebuffer *old_fb); | |
eb1bfe80 JB |
85 | static int intel_framebuffer_init(struct drm_device *dev, |
86 | struct intel_framebuffer *ifb, | |
87 | struct drm_mode_fb_cmd2 *mode_cmd, | |
88 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
89 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
90 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 91 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
92 | struct intel_link_m_n *m_n, |
93 | struct intel_link_m_n *m2_n2); | |
29407aab | 94 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
95 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
96 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f VS |
97 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
98 | const struct intel_crtc_config *pipe_config); | |
99 | static void chv_prepare_pll(struct intel_crtc *crtc, | |
100 | const struct intel_crtc_config *pipe_config); | |
e7457a9a | 101 | |
0e32b39c DA |
102 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
103 | { | |
104 | if (!connector->mst_port) | |
105 | return connector->encoder; | |
106 | else | |
107 | return &connector->mst_port->mst_encoders[pipe]->base; | |
108 | } | |
109 | ||
79e53945 | 110 | typedef struct { |
0206e353 | 111 | int min, max; |
79e53945 JB |
112 | } intel_range_t; |
113 | ||
114 | typedef struct { | |
0206e353 AJ |
115 | int dot_limit; |
116 | int p2_slow, p2_fast; | |
79e53945 JB |
117 | } intel_p2_t; |
118 | ||
d4906093 ML |
119 | typedef struct intel_limit intel_limit_t; |
120 | struct intel_limit { | |
0206e353 AJ |
121 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
122 | intel_p2_t p2; | |
d4906093 | 123 | }; |
79e53945 | 124 | |
d2acd215 DV |
125 | int |
126 | intel_pch_rawclk(struct drm_device *dev) | |
127 | { | |
128 | struct drm_i915_private *dev_priv = dev->dev_private; | |
129 | ||
130 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
131 | ||
132 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
133 | } | |
134 | ||
021357ac CW |
135 | static inline u32 /* units of 100MHz */ |
136 | intel_fdi_link_freq(struct drm_device *dev) | |
137 | { | |
8b99e68c CW |
138 | if (IS_GEN5(dev)) { |
139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
140 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
141 | } else | |
142 | return 27; | |
021357ac CW |
143 | } |
144 | ||
5d536e28 | 145 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 146 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 147 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 148 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
149 | .m = { .min = 96, .max = 140 }, |
150 | .m1 = { .min = 18, .max = 26 }, | |
151 | .m2 = { .min = 6, .max = 16 }, | |
152 | .p = { .min = 4, .max = 128 }, | |
153 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
154 | .p2 = { .dot_limit = 165000, |
155 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
156 | }; |
157 | ||
5d536e28 DV |
158 | static const intel_limit_t intel_limits_i8xx_dvo = { |
159 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 160 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 161 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
162 | .m = { .min = 96, .max = 140 }, |
163 | .m1 = { .min = 18, .max = 26 }, | |
164 | .m2 = { .min = 6, .max = 16 }, | |
165 | .p = { .min = 4, .max = 128 }, | |
166 | .p1 = { .min = 2, .max = 33 }, | |
167 | .p2 = { .dot_limit = 165000, | |
168 | .p2_slow = 4, .p2_fast = 4 }, | |
169 | }; | |
170 | ||
e4b36699 | 171 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 172 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 173 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 174 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
175 | .m = { .min = 96, .max = 140 }, |
176 | .m1 = { .min = 18, .max = 26 }, | |
177 | .m2 = { .min = 6, .max = 16 }, | |
178 | .p = { .min = 4, .max = 128 }, | |
179 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
180 | .p2 = { .dot_limit = 165000, |
181 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 182 | }; |
273e27ca | 183 | |
e4b36699 | 184 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
185 | .dot = { .min = 20000, .max = 400000 }, |
186 | .vco = { .min = 1400000, .max = 2800000 }, | |
187 | .n = { .min = 1, .max = 6 }, | |
188 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
189 | .m1 = { .min = 8, .max = 18 }, |
190 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
191 | .p = { .min = 5, .max = 80 }, |
192 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
193 | .p2 = { .dot_limit = 200000, |
194 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
195 | }; |
196 | ||
197 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
198 | .dot = { .min = 20000, .max = 400000 }, |
199 | .vco = { .min = 1400000, .max = 2800000 }, | |
200 | .n = { .min = 1, .max = 6 }, | |
201 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
202 | .m1 = { .min = 8, .max = 18 }, |
203 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
204 | .p = { .min = 7, .max = 98 }, |
205 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
206 | .p2 = { .dot_limit = 112000, |
207 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
208 | }; |
209 | ||
273e27ca | 210 | |
e4b36699 | 211 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
212 | .dot = { .min = 25000, .max = 270000 }, |
213 | .vco = { .min = 1750000, .max = 3500000}, | |
214 | .n = { .min = 1, .max = 4 }, | |
215 | .m = { .min = 104, .max = 138 }, | |
216 | .m1 = { .min = 17, .max = 23 }, | |
217 | .m2 = { .min = 5, .max = 11 }, | |
218 | .p = { .min = 10, .max = 30 }, | |
219 | .p1 = { .min = 1, .max = 3}, | |
220 | .p2 = { .dot_limit = 270000, | |
221 | .p2_slow = 10, | |
222 | .p2_fast = 10 | |
044c7c41 | 223 | }, |
e4b36699 KP |
224 | }; |
225 | ||
226 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
227 | .dot = { .min = 22000, .max = 400000 }, |
228 | .vco = { .min = 1750000, .max = 3500000}, | |
229 | .n = { .min = 1, .max = 4 }, | |
230 | .m = { .min = 104, .max = 138 }, | |
231 | .m1 = { .min = 16, .max = 23 }, | |
232 | .m2 = { .min = 5, .max = 11 }, | |
233 | .p = { .min = 5, .max = 80 }, | |
234 | .p1 = { .min = 1, .max = 8}, | |
235 | .p2 = { .dot_limit = 165000, | |
236 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
237 | }; |
238 | ||
239 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
240 | .dot = { .min = 20000, .max = 115000 }, |
241 | .vco = { .min = 1750000, .max = 3500000 }, | |
242 | .n = { .min = 1, .max = 3 }, | |
243 | .m = { .min = 104, .max = 138 }, | |
244 | .m1 = { .min = 17, .max = 23 }, | |
245 | .m2 = { .min = 5, .max = 11 }, | |
246 | .p = { .min = 28, .max = 112 }, | |
247 | .p1 = { .min = 2, .max = 8 }, | |
248 | .p2 = { .dot_limit = 0, | |
249 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 250 | }, |
e4b36699 KP |
251 | }; |
252 | ||
253 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
254 | .dot = { .min = 80000, .max = 224000 }, |
255 | .vco = { .min = 1750000, .max = 3500000 }, | |
256 | .n = { .min = 1, .max = 3 }, | |
257 | .m = { .min = 104, .max = 138 }, | |
258 | .m1 = { .min = 17, .max = 23 }, | |
259 | .m2 = { .min = 5, .max = 11 }, | |
260 | .p = { .min = 14, .max = 42 }, | |
261 | .p1 = { .min = 2, .max = 6 }, | |
262 | .p2 = { .dot_limit = 0, | |
263 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 264 | }, |
e4b36699 KP |
265 | }; |
266 | ||
f2b115e6 | 267 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
268 | .dot = { .min = 20000, .max = 400000}, |
269 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 270 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
271 | .n = { .min = 3, .max = 6 }, |
272 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 273 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
274 | .m1 = { .min = 0, .max = 0 }, |
275 | .m2 = { .min = 0, .max = 254 }, | |
276 | .p = { .min = 5, .max = 80 }, | |
277 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
278 | .p2 = { .dot_limit = 200000, |
279 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
280 | }; |
281 | ||
f2b115e6 | 282 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
283 | .dot = { .min = 20000, .max = 400000 }, |
284 | .vco = { .min = 1700000, .max = 3500000 }, | |
285 | .n = { .min = 3, .max = 6 }, | |
286 | .m = { .min = 2, .max = 256 }, | |
287 | .m1 = { .min = 0, .max = 0 }, | |
288 | .m2 = { .min = 0, .max = 254 }, | |
289 | .p = { .min = 7, .max = 112 }, | |
290 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
291 | .p2 = { .dot_limit = 112000, |
292 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
293 | }; |
294 | ||
273e27ca EA |
295 | /* Ironlake / Sandybridge |
296 | * | |
297 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
298 | * the range value for them is (actual_value - 2). | |
299 | */ | |
b91ad0ec | 300 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
301 | .dot = { .min = 25000, .max = 350000 }, |
302 | .vco = { .min = 1760000, .max = 3510000 }, | |
303 | .n = { .min = 1, .max = 5 }, | |
304 | .m = { .min = 79, .max = 127 }, | |
305 | .m1 = { .min = 12, .max = 22 }, | |
306 | .m2 = { .min = 5, .max = 9 }, | |
307 | .p = { .min = 5, .max = 80 }, | |
308 | .p1 = { .min = 1, .max = 8 }, | |
309 | .p2 = { .dot_limit = 225000, | |
310 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
311 | }; |
312 | ||
b91ad0ec | 313 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
314 | .dot = { .min = 25000, .max = 350000 }, |
315 | .vco = { .min = 1760000, .max = 3510000 }, | |
316 | .n = { .min = 1, .max = 3 }, | |
317 | .m = { .min = 79, .max = 118 }, | |
318 | .m1 = { .min = 12, .max = 22 }, | |
319 | .m2 = { .min = 5, .max = 9 }, | |
320 | .p = { .min = 28, .max = 112 }, | |
321 | .p1 = { .min = 2, .max = 8 }, | |
322 | .p2 = { .dot_limit = 225000, | |
323 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
324 | }; |
325 | ||
326 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
327 | .dot = { .min = 25000, .max = 350000 }, |
328 | .vco = { .min = 1760000, .max = 3510000 }, | |
329 | .n = { .min = 1, .max = 3 }, | |
330 | .m = { .min = 79, .max = 127 }, | |
331 | .m1 = { .min = 12, .max = 22 }, | |
332 | .m2 = { .min = 5, .max = 9 }, | |
333 | .p = { .min = 14, .max = 56 }, | |
334 | .p1 = { .min = 2, .max = 8 }, | |
335 | .p2 = { .dot_limit = 225000, | |
336 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
337 | }; |
338 | ||
273e27ca | 339 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 340 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
341 | .dot = { .min = 25000, .max = 350000 }, |
342 | .vco = { .min = 1760000, .max = 3510000 }, | |
343 | .n = { .min = 1, .max = 2 }, | |
344 | .m = { .min = 79, .max = 126 }, | |
345 | .m1 = { .min = 12, .max = 22 }, | |
346 | .m2 = { .min = 5, .max = 9 }, | |
347 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 348 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
349 | .p2 = { .dot_limit = 225000, |
350 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
351 | }; |
352 | ||
353 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
354 | .dot = { .min = 25000, .max = 350000 }, |
355 | .vco = { .min = 1760000, .max = 3510000 }, | |
356 | .n = { .min = 1, .max = 3 }, | |
357 | .m = { .min = 79, .max = 126 }, | |
358 | .m1 = { .min = 12, .max = 22 }, | |
359 | .m2 = { .min = 5, .max = 9 }, | |
360 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 361 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
362 | .p2 = { .dot_limit = 225000, |
363 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
364 | }; |
365 | ||
dc730512 | 366 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
367 | /* |
368 | * These are the data rate limits (measured in fast clocks) | |
369 | * since those are the strictest limits we have. The fast | |
370 | * clock and actual rate limits are more relaxed, so checking | |
371 | * them would make no difference. | |
372 | */ | |
373 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 374 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 375 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
376 | .m1 = { .min = 2, .max = 3 }, |
377 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 378 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 379 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
380 | }; |
381 | ||
ef9348c8 CML |
382 | static const intel_limit_t intel_limits_chv = { |
383 | /* | |
384 | * These are the data rate limits (measured in fast clocks) | |
385 | * since those are the strictest limits we have. The fast | |
386 | * clock and actual rate limits are more relaxed, so checking | |
387 | * them would make no difference. | |
388 | */ | |
389 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
390 | .vco = { .min = 4860000, .max = 6700000 }, | |
391 | .n = { .min = 1, .max = 1 }, | |
392 | .m1 = { .min = 2, .max = 2 }, | |
393 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
394 | .p1 = { .min = 2, .max = 4 }, | |
395 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
396 | }; | |
397 | ||
6b4bf1c4 VS |
398 | static void vlv_clock(int refclk, intel_clock_t *clock) |
399 | { | |
400 | clock->m = clock->m1 * clock->m2; | |
401 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
402 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
403 | return; | |
fb03ac01 VS |
404 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
405 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
406 | } |
407 | ||
e0638cdf PZ |
408 | /** |
409 | * Returns whether any output on the specified pipe is of the specified type | |
410 | */ | |
4093561b | 411 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 412 | { |
409ee761 | 413 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
414 | struct intel_encoder *encoder; |
415 | ||
409ee761 | 416 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
417 | if (encoder->type == type) |
418 | return true; | |
419 | ||
420 | return false; | |
421 | } | |
422 | ||
d0737e1d ACO |
423 | /** |
424 | * Returns whether any output on the specified pipe will have the specified | |
425 | * type after a staged modeset is complete, i.e., the same as | |
426 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
427 | * encoder->crtc. | |
428 | */ | |
429 | static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type) | |
430 | { | |
431 | struct drm_device *dev = crtc->base.dev; | |
432 | struct intel_encoder *encoder; | |
433 | ||
434 | for_each_intel_encoder(dev, encoder) | |
435 | if (encoder->new_crtc == crtc && encoder->type == type) | |
436 | return true; | |
437 | ||
438 | return false; | |
439 | } | |
440 | ||
409ee761 | 441 | static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc, |
1b894b59 | 442 | int refclk) |
2c07245f | 443 | { |
409ee761 | 444 | struct drm_device *dev = crtc->base.dev; |
2c07245f | 445 | const intel_limit_t *limit; |
b91ad0ec | 446 | |
d0737e1d | 447 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 448 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 449 | if (refclk == 100000) |
b91ad0ec ZW |
450 | limit = &intel_limits_ironlake_dual_lvds_100m; |
451 | else | |
452 | limit = &intel_limits_ironlake_dual_lvds; | |
453 | } else { | |
1b894b59 | 454 | if (refclk == 100000) |
b91ad0ec ZW |
455 | limit = &intel_limits_ironlake_single_lvds_100m; |
456 | else | |
457 | limit = &intel_limits_ironlake_single_lvds; | |
458 | } | |
c6bb3538 | 459 | } else |
b91ad0ec | 460 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
461 | |
462 | return limit; | |
463 | } | |
464 | ||
409ee761 | 465 | static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc) |
044c7c41 | 466 | { |
409ee761 | 467 | struct drm_device *dev = crtc->base.dev; |
044c7c41 ML |
468 | const intel_limit_t *limit; |
469 | ||
d0737e1d | 470 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 471 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 472 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 473 | else |
e4b36699 | 474 | limit = &intel_limits_g4x_single_channel_lvds; |
d0737e1d ACO |
475 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) || |
476 | intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 477 | limit = &intel_limits_g4x_hdmi; |
d0737e1d | 478 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 479 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 480 | } else /* The option is for other outputs */ |
e4b36699 | 481 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
482 | |
483 | return limit; | |
484 | } | |
485 | ||
409ee761 | 486 | static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk) |
79e53945 | 487 | { |
409ee761 | 488 | struct drm_device *dev = crtc->base.dev; |
79e53945 JB |
489 | const intel_limit_t *limit; |
490 | ||
bad720ff | 491 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 492 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 493 | else if (IS_G4X(dev)) { |
044c7c41 | 494 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 495 | } else if (IS_PINEVIEW(dev)) { |
d0737e1d | 496 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 497 | limit = &intel_limits_pineview_lvds; |
2177832f | 498 | else |
f2b115e6 | 499 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
500 | } else if (IS_CHERRYVIEW(dev)) { |
501 | limit = &intel_limits_chv; | |
a0c4da24 | 502 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 503 | limit = &intel_limits_vlv; |
a6c45cf0 | 504 | } else if (!IS_GEN2(dev)) { |
d0737e1d | 505 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
506 | limit = &intel_limits_i9xx_lvds; |
507 | else | |
508 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 509 | } else { |
d0737e1d | 510 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
e4b36699 | 511 | limit = &intel_limits_i8xx_lvds; |
d0737e1d | 512 | else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 513 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
514 | else |
515 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
516 | } |
517 | return limit; | |
518 | } | |
519 | ||
f2b115e6 AJ |
520 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
521 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 522 | { |
2177832f SL |
523 | clock->m = clock->m2 + 2; |
524 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
525 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
526 | return; | |
fb03ac01 VS |
527 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
528 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
529 | } |
530 | ||
7429e9d4 DV |
531 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
532 | { | |
533 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
534 | } | |
535 | ||
ac58c3f0 | 536 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 537 | { |
7429e9d4 | 538 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 539 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
540 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
541 | return; | |
fb03ac01 VS |
542 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
543 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
544 | } |
545 | ||
ef9348c8 CML |
546 | static void chv_clock(int refclk, intel_clock_t *clock) |
547 | { | |
548 | clock->m = clock->m1 * clock->m2; | |
549 | clock->p = clock->p1 * clock->p2; | |
550 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
551 | return; | |
552 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
553 | clock->n << 22); | |
554 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
555 | } | |
556 | ||
7c04d1d9 | 557 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
558 | /** |
559 | * Returns whether the given set of divisors are valid for a given refclk with | |
560 | * the given connectors. | |
561 | */ | |
562 | ||
1b894b59 CW |
563 | static bool intel_PLL_is_valid(struct drm_device *dev, |
564 | const intel_limit_t *limit, | |
565 | const intel_clock_t *clock) | |
79e53945 | 566 | { |
f01b7962 VS |
567 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
568 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 569 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 570 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 571 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 572 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 573 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 574 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
575 | |
576 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
577 | if (clock->m1 <= clock->m2) | |
578 | INTELPllInvalid("m1 <= m2\n"); | |
579 | ||
580 | if (!IS_VALLEYVIEW(dev)) { | |
581 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
582 | INTELPllInvalid("p out of range\n"); | |
583 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
584 | INTELPllInvalid("m out of range\n"); | |
585 | } | |
586 | ||
79e53945 | 587 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 588 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
589 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
590 | * connector, etc., rather than just a single range. | |
591 | */ | |
592 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 593 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
594 | |
595 | return true; | |
596 | } | |
597 | ||
d4906093 | 598 | static bool |
a919ff14 | 599 | i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
cec2f356 SP |
600 | int target, int refclk, intel_clock_t *match_clock, |
601 | intel_clock_t *best_clock) | |
79e53945 | 602 | { |
a919ff14 | 603 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 604 | intel_clock_t clock; |
79e53945 JB |
605 | int err = target; |
606 | ||
d0737e1d | 607 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 608 | /* |
a210b028 DV |
609 | * For LVDS just rely on its current settings for dual-channel. |
610 | * We haven't figured out how to reliably set up different | |
611 | * single/dual channel state, if we even can. | |
79e53945 | 612 | */ |
1974cad0 | 613 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
614 | clock.p2 = limit->p2.p2_fast; |
615 | else | |
616 | clock.p2 = limit->p2.p2_slow; | |
617 | } else { | |
618 | if (target < limit->p2.dot_limit) | |
619 | clock.p2 = limit->p2.p2_slow; | |
620 | else | |
621 | clock.p2 = limit->p2.p2_fast; | |
622 | } | |
623 | ||
0206e353 | 624 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 625 | |
42158660 ZY |
626 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
627 | clock.m1++) { | |
628 | for (clock.m2 = limit->m2.min; | |
629 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 630 | if (clock.m2 >= clock.m1) |
42158660 ZY |
631 | break; |
632 | for (clock.n = limit->n.min; | |
633 | clock.n <= limit->n.max; clock.n++) { | |
634 | for (clock.p1 = limit->p1.min; | |
635 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
636 | int this_err; |
637 | ||
ac58c3f0 DV |
638 | i9xx_clock(refclk, &clock); |
639 | if (!intel_PLL_is_valid(dev, limit, | |
640 | &clock)) | |
641 | continue; | |
642 | if (match_clock && | |
643 | clock.p != match_clock->p) | |
644 | continue; | |
645 | ||
646 | this_err = abs(clock.dot - target); | |
647 | if (this_err < err) { | |
648 | *best_clock = clock; | |
649 | err = this_err; | |
650 | } | |
651 | } | |
652 | } | |
653 | } | |
654 | } | |
655 | ||
656 | return (err != target); | |
657 | } | |
658 | ||
659 | static bool | |
a919ff14 | 660 | pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
661 | int target, int refclk, intel_clock_t *match_clock, |
662 | intel_clock_t *best_clock) | |
79e53945 | 663 | { |
a919ff14 | 664 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 665 | intel_clock_t clock; |
79e53945 JB |
666 | int err = target; |
667 | ||
d0737e1d | 668 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 669 | /* |
a210b028 DV |
670 | * For LVDS just rely on its current settings for dual-channel. |
671 | * We haven't figured out how to reliably set up different | |
672 | * single/dual channel state, if we even can. | |
79e53945 | 673 | */ |
1974cad0 | 674 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
675 | clock.p2 = limit->p2.p2_fast; |
676 | else | |
677 | clock.p2 = limit->p2.p2_slow; | |
678 | } else { | |
679 | if (target < limit->p2.dot_limit) | |
680 | clock.p2 = limit->p2.p2_slow; | |
681 | else | |
682 | clock.p2 = limit->p2.p2_fast; | |
683 | } | |
684 | ||
0206e353 | 685 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 686 | |
42158660 ZY |
687 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
688 | clock.m1++) { | |
689 | for (clock.m2 = limit->m2.min; | |
690 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
691 | for (clock.n = limit->n.min; |
692 | clock.n <= limit->n.max; clock.n++) { | |
693 | for (clock.p1 = limit->p1.min; | |
694 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
695 | int this_err; |
696 | ||
ac58c3f0 | 697 | pineview_clock(refclk, &clock); |
1b894b59 CW |
698 | if (!intel_PLL_is_valid(dev, limit, |
699 | &clock)) | |
79e53945 | 700 | continue; |
cec2f356 SP |
701 | if (match_clock && |
702 | clock.p != match_clock->p) | |
703 | continue; | |
79e53945 JB |
704 | |
705 | this_err = abs(clock.dot - target); | |
706 | if (this_err < err) { | |
707 | *best_clock = clock; | |
708 | err = this_err; | |
709 | } | |
710 | } | |
711 | } | |
712 | } | |
713 | } | |
714 | ||
715 | return (err != target); | |
716 | } | |
717 | ||
d4906093 | 718 | static bool |
a919ff14 | 719 | g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
720 | int target, int refclk, intel_clock_t *match_clock, |
721 | intel_clock_t *best_clock) | |
d4906093 | 722 | { |
a919ff14 | 723 | struct drm_device *dev = crtc->base.dev; |
d4906093 ML |
724 | intel_clock_t clock; |
725 | int max_n; | |
726 | bool found; | |
6ba770dc AJ |
727 | /* approximately equals target * 0.00585 */ |
728 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
729 | found = false; |
730 | ||
d0737e1d | 731 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 732 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
733 | clock.p2 = limit->p2.p2_fast; |
734 | else | |
735 | clock.p2 = limit->p2.p2_slow; | |
736 | } else { | |
737 | if (target < limit->p2.dot_limit) | |
738 | clock.p2 = limit->p2.p2_slow; | |
739 | else | |
740 | clock.p2 = limit->p2.p2_fast; | |
741 | } | |
742 | ||
743 | memset(best_clock, 0, sizeof(*best_clock)); | |
744 | max_n = limit->n.max; | |
f77f13e2 | 745 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 746 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 747 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
748 | for (clock.m1 = limit->m1.max; |
749 | clock.m1 >= limit->m1.min; clock.m1--) { | |
750 | for (clock.m2 = limit->m2.max; | |
751 | clock.m2 >= limit->m2.min; clock.m2--) { | |
752 | for (clock.p1 = limit->p1.max; | |
753 | clock.p1 >= limit->p1.min; clock.p1--) { | |
754 | int this_err; | |
755 | ||
ac58c3f0 | 756 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
757 | if (!intel_PLL_is_valid(dev, limit, |
758 | &clock)) | |
d4906093 | 759 | continue; |
1b894b59 CW |
760 | |
761 | this_err = abs(clock.dot - target); | |
d4906093 ML |
762 | if (this_err < err_most) { |
763 | *best_clock = clock; | |
764 | err_most = this_err; | |
765 | max_n = clock.n; | |
766 | found = true; | |
767 | } | |
768 | } | |
769 | } | |
770 | } | |
771 | } | |
2c07245f ZW |
772 | return found; |
773 | } | |
774 | ||
a0c4da24 | 775 | static bool |
a919ff14 | 776 | vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ee9300bb DV |
777 | int target, int refclk, intel_clock_t *match_clock, |
778 | intel_clock_t *best_clock) | |
a0c4da24 | 779 | { |
a919ff14 | 780 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 781 | intel_clock_t clock; |
69e4f900 | 782 | unsigned int bestppm = 1000000; |
27e639bf VS |
783 | /* min update 19.2 MHz */ |
784 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 785 | bool found = false; |
a0c4da24 | 786 | |
6b4bf1c4 VS |
787 | target *= 5; /* fast clock */ |
788 | ||
789 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
790 | |
791 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 792 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 793 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 794 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 795 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 796 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 797 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 798 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
799 | unsigned int ppm, diff; |
800 | ||
6b4bf1c4 VS |
801 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
802 | refclk * clock.m1); | |
803 | ||
804 | vlv_clock(refclk, &clock); | |
43b0ac53 | 805 | |
f01b7962 VS |
806 | if (!intel_PLL_is_valid(dev, limit, |
807 | &clock)) | |
43b0ac53 VS |
808 | continue; |
809 | ||
6b4bf1c4 VS |
810 | diff = abs(clock.dot - target); |
811 | ppm = div_u64(1000000ULL * diff, target); | |
812 | ||
813 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 814 | bestppm = 0; |
6b4bf1c4 | 815 | *best_clock = clock; |
49e497ef | 816 | found = true; |
43b0ac53 | 817 | } |
6b4bf1c4 | 818 | |
c686122c | 819 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 820 | bestppm = ppm; |
6b4bf1c4 | 821 | *best_clock = clock; |
49e497ef | 822 | found = true; |
a0c4da24 JB |
823 | } |
824 | } | |
825 | } | |
826 | } | |
827 | } | |
a0c4da24 | 828 | |
49e497ef | 829 | return found; |
a0c4da24 | 830 | } |
a4fc5ed6 | 831 | |
ef9348c8 | 832 | static bool |
a919ff14 | 833 | chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc, |
ef9348c8 CML |
834 | int target, int refclk, intel_clock_t *match_clock, |
835 | intel_clock_t *best_clock) | |
836 | { | |
a919ff14 | 837 | struct drm_device *dev = crtc->base.dev; |
ef9348c8 CML |
838 | intel_clock_t clock; |
839 | uint64_t m2; | |
840 | int found = false; | |
841 | ||
842 | memset(best_clock, 0, sizeof(*best_clock)); | |
843 | ||
844 | /* | |
845 | * Based on hardware doc, the n always set to 1, and m1 always | |
846 | * set to 2. If requires to support 200Mhz refclk, we need to | |
847 | * revisit this because n may not 1 anymore. | |
848 | */ | |
849 | clock.n = 1, clock.m1 = 2; | |
850 | target *= 5; /* fast clock */ | |
851 | ||
852 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
853 | for (clock.p2 = limit->p2.p2_fast; | |
854 | clock.p2 >= limit->p2.p2_slow; | |
855 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
856 | ||
857 | clock.p = clock.p1 * clock.p2; | |
858 | ||
859 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
860 | clock.n) << 22, refclk * clock.m1); | |
861 | ||
862 | if (m2 > INT_MAX/clock.m1) | |
863 | continue; | |
864 | ||
865 | clock.m2 = m2; | |
866 | ||
867 | chv_clock(refclk, &clock); | |
868 | ||
869 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
870 | continue; | |
871 | ||
872 | /* based on hardware requirement, prefer bigger p | |
873 | */ | |
874 | if (clock.p > best_clock->p) { | |
875 | *best_clock = clock; | |
876 | found = true; | |
877 | } | |
878 | } | |
879 | } | |
880 | ||
881 | return found; | |
882 | } | |
883 | ||
20ddf665 VS |
884 | bool intel_crtc_active(struct drm_crtc *crtc) |
885 | { | |
886 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
887 | ||
888 | /* Be paranoid as we can arrive here with only partial | |
889 | * state retrieved from the hardware during setup. | |
890 | * | |
241bfc38 | 891 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
892 | * as Haswell has gained clock readout/fastboot support. |
893 | * | |
66e514c1 | 894 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 VS |
895 | * properly reconstruct framebuffers. |
896 | */ | |
f4510a27 | 897 | return intel_crtc->active && crtc->primary->fb && |
241bfc38 | 898 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
899 | } |
900 | ||
a5c961d1 PZ |
901 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
902 | enum pipe pipe) | |
903 | { | |
904 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
905 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
906 | ||
3b117c8f | 907 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
908 | } |
909 | ||
fbf49ea2 VS |
910 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
911 | { | |
912 | struct drm_i915_private *dev_priv = dev->dev_private; | |
913 | u32 reg = PIPEDSL(pipe); | |
914 | u32 line1, line2; | |
915 | u32 line_mask; | |
916 | ||
917 | if (IS_GEN2(dev)) | |
918 | line_mask = DSL_LINEMASK_GEN2; | |
919 | else | |
920 | line_mask = DSL_LINEMASK_GEN3; | |
921 | ||
922 | line1 = I915_READ(reg) & line_mask; | |
923 | mdelay(5); | |
924 | line2 = I915_READ(reg) & line_mask; | |
925 | ||
926 | return line1 == line2; | |
927 | } | |
928 | ||
ab7ad7f6 KP |
929 | /* |
930 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 931 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
932 | * |
933 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
934 | * spinning on the vblank interrupt status bit, since we won't actually | |
935 | * see an interrupt when the pipe is disabled. | |
936 | * | |
ab7ad7f6 KP |
937 | * On Gen4 and above: |
938 | * wait for the pipe register state bit to turn off | |
939 | * | |
940 | * Otherwise: | |
941 | * wait for the display line value to settle (it usually | |
942 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 943 | * |
9d0498a2 | 944 | */ |
575f7ab7 | 945 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 946 | { |
575f7ab7 | 947 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 948 | struct drm_i915_private *dev_priv = dev->dev_private; |
575f7ab7 VS |
949 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; |
950 | enum pipe pipe = crtc->pipe; | |
ab7ad7f6 KP |
951 | |
952 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 953 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
954 | |
955 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
956 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
957 | 100)) | |
284637d9 | 958 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 959 | } else { |
ab7ad7f6 | 960 | /* Wait for the display line to settle */ |
fbf49ea2 | 961 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 962 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 963 | } |
79e53945 JB |
964 | } |
965 | ||
b0ea7d37 DL |
966 | /* |
967 | * ibx_digital_port_connected - is the specified port connected? | |
968 | * @dev_priv: i915 private structure | |
969 | * @port: the port to test | |
970 | * | |
971 | * Returns true if @port is connected, false otherwise. | |
972 | */ | |
973 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
974 | struct intel_digital_port *port) | |
975 | { | |
976 | u32 bit; | |
977 | ||
c36346e3 | 978 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 979 | switch (port->port) { |
c36346e3 DL |
980 | case PORT_B: |
981 | bit = SDE_PORTB_HOTPLUG; | |
982 | break; | |
983 | case PORT_C: | |
984 | bit = SDE_PORTC_HOTPLUG; | |
985 | break; | |
986 | case PORT_D: | |
987 | bit = SDE_PORTD_HOTPLUG; | |
988 | break; | |
989 | default: | |
990 | return true; | |
991 | } | |
992 | } else { | |
eba905b2 | 993 | switch (port->port) { |
c36346e3 DL |
994 | case PORT_B: |
995 | bit = SDE_PORTB_HOTPLUG_CPT; | |
996 | break; | |
997 | case PORT_C: | |
998 | bit = SDE_PORTC_HOTPLUG_CPT; | |
999 | break; | |
1000 | case PORT_D: | |
1001 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1002 | break; | |
1003 | default: | |
1004 | return true; | |
1005 | } | |
b0ea7d37 DL |
1006 | } |
1007 | ||
1008 | return I915_READ(SDEISR) & bit; | |
1009 | } | |
1010 | ||
b24e7179 JB |
1011 | static const char *state_string(bool enabled) |
1012 | { | |
1013 | return enabled ? "on" : "off"; | |
1014 | } | |
1015 | ||
1016 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1017 | void assert_pll(struct drm_i915_private *dev_priv, |
1018 | enum pipe pipe, bool state) | |
b24e7179 JB |
1019 | { |
1020 | int reg; | |
1021 | u32 val; | |
1022 | bool cur_state; | |
1023 | ||
1024 | reg = DPLL(pipe); | |
1025 | val = I915_READ(reg); | |
1026 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1027 | WARN(cur_state != state, | |
1028 | "PLL state assertion failure (expected %s, current %s)\n", | |
1029 | state_string(state), state_string(cur_state)); | |
1030 | } | |
b24e7179 | 1031 | |
23538ef1 JN |
1032 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1033 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1034 | { | |
1035 | u32 val; | |
1036 | bool cur_state; | |
1037 | ||
1038 | mutex_lock(&dev_priv->dpio_lock); | |
1039 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1040 | mutex_unlock(&dev_priv->dpio_lock); | |
1041 | ||
1042 | cur_state = val & DSI_PLL_VCO_EN; | |
1043 | WARN(cur_state != state, | |
1044 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
1045 | state_string(state), state_string(cur_state)); | |
1046 | } | |
1047 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1048 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1049 | ||
55607e8a | 1050 | struct intel_shared_dpll * |
e2b78267 DV |
1051 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1052 | { | |
1053 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1054 | ||
a43f6e0f | 1055 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
1056 | return NULL; |
1057 | ||
a43f6e0f | 1058 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
1059 | } |
1060 | ||
040484af | 1061 | /* For ILK+ */ |
55607e8a DV |
1062 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1063 | struct intel_shared_dpll *pll, | |
1064 | bool state) | |
040484af | 1065 | { |
040484af | 1066 | bool cur_state; |
5358901f | 1067 | struct intel_dpll_hw_state hw_state; |
040484af | 1068 | |
92b27b08 | 1069 | if (WARN (!pll, |
46edb027 | 1070 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1071 | return; |
ee7b9f93 | 1072 | |
5358901f | 1073 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 1074 | WARN(cur_state != state, |
5358901f DV |
1075 | "%s assertion failure (expected %s, current %s)\n", |
1076 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1077 | } |
040484af JB |
1078 | |
1079 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1080 | enum pipe pipe, bool state) | |
1081 | { | |
1082 | int reg; | |
1083 | u32 val; | |
1084 | bool cur_state; | |
ad80a810 PZ |
1085 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1086 | pipe); | |
040484af | 1087 | |
affa9354 PZ |
1088 | if (HAS_DDI(dev_priv->dev)) { |
1089 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1090 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1091 | val = I915_READ(reg); |
ad80a810 | 1092 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1093 | } else { |
1094 | reg = FDI_TX_CTL(pipe); | |
1095 | val = I915_READ(reg); | |
1096 | cur_state = !!(val & FDI_TX_ENABLE); | |
1097 | } | |
040484af JB |
1098 | WARN(cur_state != state, |
1099 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1100 | state_string(state), state_string(cur_state)); | |
1101 | } | |
1102 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1103 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1104 | ||
1105 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1106 | enum pipe pipe, bool state) | |
1107 | { | |
1108 | int reg; | |
1109 | u32 val; | |
1110 | bool cur_state; | |
1111 | ||
d63fa0dc PZ |
1112 | reg = FDI_RX_CTL(pipe); |
1113 | val = I915_READ(reg); | |
1114 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1115 | WARN(cur_state != state, |
1116 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1117 | state_string(state), state_string(cur_state)); | |
1118 | } | |
1119 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1120 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1121 | ||
1122 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1123 | enum pipe pipe) | |
1124 | { | |
1125 | int reg; | |
1126 | u32 val; | |
1127 | ||
1128 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1129 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1130 | return; |
1131 | ||
bf507ef7 | 1132 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1133 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1134 | return; |
1135 | ||
040484af JB |
1136 | reg = FDI_TX_CTL(pipe); |
1137 | val = I915_READ(reg); | |
1138 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1139 | } | |
1140 | ||
55607e8a DV |
1141 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1142 | enum pipe pipe, bool state) | |
040484af JB |
1143 | { |
1144 | int reg; | |
1145 | u32 val; | |
55607e8a | 1146 | bool cur_state; |
040484af JB |
1147 | |
1148 | reg = FDI_RX_CTL(pipe); | |
1149 | val = I915_READ(reg); | |
55607e8a DV |
1150 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1151 | WARN(cur_state != state, | |
1152 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1153 | state_string(state), state_string(cur_state)); | |
040484af JB |
1154 | } |
1155 | ||
b680c37a DV |
1156 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1157 | enum pipe pipe) | |
ea0760cf | 1158 | { |
bedd4dba JN |
1159 | struct drm_device *dev = dev_priv->dev; |
1160 | int pp_reg; | |
ea0760cf JB |
1161 | u32 val; |
1162 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1163 | bool locked = true; |
ea0760cf | 1164 | |
bedd4dba JN |
1165 | if (WARN_ON(HAS_DDI(dev))) |
1166 | return; | |
1167 | ||
1168 | if (HAS_PCH_SPLIT(dev)) { | |
1169 | u32 port_sel; | |
1170 | ||
ea0760cf | 1171 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1172 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1173 | ||
1174 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1175 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1176 | panel_pipe = PIPE_B; | |
1177 | /* XXX: else fix for eDP */ | |
1178 | } else if (IS_VALLEYVIEW(dev)) { | |
1179 | /* presumably write lock depends on pipe, not port select */ | |
1180 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1181 | panel_pipe = pipe; | |
ea0760cf JB |
1182 | } else { |
1183 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1184 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1185 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1186 | } |
1187 | ||
1188 | val = I915_READ(pp_reg); | |
1189 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1190 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1191 | locked = false; |
1192 | ||
ea0760cf JB |
1193 | WARN(panel_pipe == pipe && locked, |
1194 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1195 | pipe_name(pipe)); |
ea0760cf JB |
1196 | } |
1197 | ||
93ce0ba6 JN |
1198 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1199 | enum pipe pipe, bool state) | |
1200 | { | |
1201 | struct drm_device *dev = dev_priv->dev; | |
1202 | bool cur_state; | |
1203 | ||
d9d82081 | 1204 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1205 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1206 | else |
5efb3e28 | 1207 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 JN |
1208 | |
1209 | WARN(cur_state != state, | |
1210 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1211 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1212 | } | |
1213 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1214 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1215 | ||
b840d907 JB |
1216 | void assert_pipe(struct drm_i915_private *dev_priv, |
1217 | enum pipe pipe, bool state) | |
b24e7179 JB |
1218 | { |
1219 | int reg; | |
1220 | u32 val; | |
63d7bbe9 | 1221 | bool cur_state; |
702e7a56 PZ |
1222 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1223 | pipe); | |
b24e7179 | 1224 | |
b6b5d049 VS |
1225 | /* if we need the pipe quirk it must be always on */ |
1226 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1227 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1228 | state = true; |
1229 | ||
f458ebbc | 1230 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1231 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1232 | cur_state = false; |
1233 | } else { | |
1234 | reg = PIPECONF(cpu_transcoder); | |
1235 | val = I915_READ(reg); | |
1236 | cur_state = !!(val & PIPECONF_ENABLE); | |
1237 | } | |
1238 | ||
63d7bbe9 JB |
1239 | WARN(cur_state != state, |
1240 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1241 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1242 | } |
1243 | ||
931872fc CW |
1244 | static void assert_plane(struct drm_i915_private *dev_priv, |
1245 | enum plane plane, bool state) | |
b24e7179 JB |
1246 | { |
1247 | int reg; | |
1248 | u32 val; | |
931872fc | 1249 | bool cur_state; |
b24e7179 JB |
1250 | |
1251 | reg = DSPCNTR(plane); | |
1252 | val = I915_READ(reg); | |
931872fc CW |
1253 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1254 | WARN(cur_state != state, | |
1255 | "plane %c assertion failure (expected %s, current %s)\n", | |
1256 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1257 | } |
1258 | ||
931872fc CW |
1259 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1260 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1261 | ||
b24e7179 JB |
1262 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1263 | enum pipe pipe) | |
1264 | { | |
653e1026 | 1265 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1266 | int reg, i; |
1267 | u32 val; | |
1268 | int cur_pipe; | |
1269 | ||
653e1026 VS |
1270 | /* Primary planes are fixed to pipes on gen4+ */ |
1271 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1272 | reg = DSPCNTR(pipe); |
1273 | val = I915_READ(reg); | |
83f26f16 | 1274 | WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1275 | "plane %c assertion failure, should be disabled but not\n", |
1276 | plane_name(pipe)); | |
19ec1358 | 1277 | return; |
28c05794 | 1278 | } |
19ec1358 | 1279 | |
b24e7179 | 1280 | /* Need to check both planes against the pipe */ |
055e393f | 1281 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1282 | reg = DSPCNTR(i); |
1283 | val = I915_READ(reg); | |
1284 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1285 | DISPPLANE_SEL_PIPE_SHIFT; | |
1286 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1287 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1288 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1289 | } |
1290 | } | |
1291 | ||
19332d7a JB |
1292 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1293 | enum pipe pipe) | |
1294 | { | |
20674eef | 1295 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1296 | int reg, sprite; |
19332d7a JB |
1297 | u32 val; |
1298 | ||
7feb8b88 DL |
1299 | if (INTEL_INFO(dev)->gen >= 9) { |
1300 | for_each_sprite(pipe, sprite) { | |
1301 | val = I915_READ(PLANE_CTL(pipe, sprite)); | |
1302 | WARN(val & PLANE_CTL_ENABLE, | |
1303 | "plane %d assertion failure, should be off on pipe %c but is still active\n", | |
1304 | sprite, pipe_name(pipe)); | |
1305 | } | |
1306 | } else if (IS_VALLEYVIEW(dev)) { | |
1fe47785 DL |
1307 | for_each_sprite(pipe, sprite) { |
1308 | reg = SPCNTR(pipe, sprite); | |
20674eef | 1309 | val = I915_READ(reg); |
83f26f16 | 1310 | WARN(val & SP_ENABLE, |
20674eef | 1311 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1312 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1313 | } |
1314 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1315 | reg = SPRCTL(pipe); | |
19332d7a | 1316 | val = I915_READ(reg); |
83f26f16 | 1317 | WARN(val & SPRITE_ENABLE, |
06da8da2 | 1318 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1319 | plane_name(pipe), pipe_name(pipe)); |
1320 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1321 | reg = DVSCNTR(pipe); | |
19332d7a | 1322 | val = I915_READ(reg); |
83f26f16 | 1323 | WARN(val & DVS_ENABLE, |
06da8da2 | 1324 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1325 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1326 | } |
1327 | } | |
1328 | ||
08c71e5e VS |
1329 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1330 | { | |
1331 | if (WARN_ON(drm_crtc_vblank_get(crtc) == 0)) | |
1332 | drm_crtc_vblank_put(crtc); | |
1333 | } | |
1334 | ||
89eff4be | 1335 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1336 | { |
1337 | u32 val; | |
1338 | bool enabled; | |
1339 | ||
89eff4be | 1340 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1341 | |
92f2584a JB |
1342 | val = I915_READ(PCH_DREF_CONTROL); |
1343 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1344 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1345 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1346 | } | |
1347 | ||
ab9412ba DV |
1348 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1349 | enum pipe pipe) | |
92f2584a JB |
1350 | { |
1351 | int reg; | |
1352 | u32 val; | |
1353 | bool enabled; | |
1354 | ||
ab9412ba | 1355 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1356 | val = I915_READ(reg); |
1357 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1358 | WARN(enabled, |
1359 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1360 | pipe_name(pipe)); | |
92f2584a JB |
1361 | } |
1362 | ||
4e634389 KP |
1363 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1364 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1365 | { |
1366 | if ((val & DP_PORT_EN) == 0) | |
1367 | return false; | |
1368 | ||
1369 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1370 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1371 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1372 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1373 | return false; | |
44f37d1f CML |
1374 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1375 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1376 | return false; | |
f0575e92 KP |
1377 | } else { |
1378 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1379 | return false; | |
1380 | } | |
1381 | return true; | |
1382 | } | |
1383 | ||
1519b995 KP |
1384 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1385 | enum pipe pipe, u32 val) | |
1386 | { | |
dc0fa718 | 1387 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1388 | return false; |
1389 | ||
1390 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1391 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1392 | return false; |
44f37d1f CML |
1393 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1394 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1395 | return false; | |
1519b995 | 1396 | } else { |
dc0fa718 | 1397 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1398 | return false; |
1399 | } | |
1400 | return true; | |
1401 | } | |
1402 | ||
1403 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1404 | enum pipe pipe, u32 val) | |
1405 | { | |
1406 | if ((val & LVDS_PORT_EN) == 0) | |
1407 | return false; | |
1408 | ||
1409 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1410 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1411 | return false; | |
1412 | } else { | |
1413 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1414 | return false; | |
1415 | } | |
1416 | return true; | |
1417 | } | |
1418 | ||
1419 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1420 | enum pipe pipe, u32 val) | |
1421 | { | |
1422 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1423 | return false; | |
1424 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1425 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1426 | return false; | |
1427 | } else { | |
1428 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1429 | return false; | |
1430 | } | |
1431 | return true; | |
1432 | } | |
1433 | ||
291906f1 | 1434 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1435 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1436 | { |
47a05eca | 1437 | u32 val = I915_READ(reg); |
4e634389 | 1438 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1439 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1440 | reg, pipe_name(pipe)); |
de9a35ab | 1441 | |
75c5da27 DV |
1442 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1443 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1444 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1445 | } |
1446 | ||
1447 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1448 | enum pipe pipe, int reg) | |
1449 | { | |
47a05eca | 1450 | u32 val = I915_READ(reg); |
b70ad586 | 1451 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1452 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1453 | reg, pipe_name(pipe)); |
de9a35ab | 1454 | |
dc0fa718 | 1455 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1456 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1457 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1458 | } |
1459 | ||
1460 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1461 | enum pipe pipe) | |
1462 | { | |
1463 | int reg; | |
1464 | u32 val; | |
291906f1 | 1465 | |
f0575e92 KP |
1466 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1467 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1468 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1469 | |
1470 | reg = PCH_ADPA; | |
1471 | val = I915_READ(reg); | |
b70ad586 | 1472 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1473 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1474 | pipe_name(pipe)); |
291906f1 JB |
1475 | |
1476 | reg = PCH_LVDS; | |
1477 | val = I915_READ(reg); | |
b70ad586 | 1478 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1479 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1480 | pipe_name(pipe)); |
291906f1 | 1481 | |
e2debe91 PZ |
1482 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1483 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1484 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1485 | } |
1486 | ||
40e9cf64 JB |
1487 | static void intel_init_dpio(struct drm_device *dev) |
1488 | { | |
1489 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1490 | ||
1491 | if (!IS_VALLEYVIEW(dev)) | |
1492 | return; | |
1493 | ||
a09caddd CML |
1494 | /* |
1495 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1496 | * CHV x1 PHY (DP/HDMI D) | |
1497 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1498 | */ | |
1499 | if (IS_CHERRYVIEW(dev)) { | |
1500 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1501 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1502 | } else { | |
1503 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1504 | } | |
5382f5f3 JB |
1505 | } |
1506 | ||
d288f65f VS |
1507 | static void vlv_enable_pll(struct intel_crtc *crtc, |
1508 | const struct intel_crtc_config *pipe_config) | |
87442f73 | 1509 | { |
426115cf DV |
1510 | struct drm_device *dev = crtc->base.dev; |
1511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1512 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1513 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1514 | |
426115cf | 1515 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1516 | |
1517 | /* No really, not for ILK+ */ | |
1518 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1519 | ||
1520 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1521 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1522 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1523 | |
426115cf DV |
1524 | I915_WRITE(reg, dpll); |
1525 | POSTING_READ(reg); | |
1526 | udelay(150); | |
1527 | ||
1528 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1529 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1530 | ||
d288f65f | 1531 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1532 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1533 | |
1534 | /* We do this three times for luck */ | |
426115cf | 1535 | I915_WRITE(reg, dpll); |
87442f73 DV |
1536 | POSTING_READ(reg); |
1537 | udelay(150); /* wait for warmup */ | |
426115cf | 1538 | I915_WRITE(reg, dpll); |
87442f73 DV |
1539 | POSTING_READ(reg); |
1540 | udelay(150); /* wait for warmup */ | |
426115cf | 1541 | I915_WRITE(reg, dpll); |
87442f73 DV |
1542 | POSTING_READ(reg); |
1543 | udelay(150); /* wait for warmup */ | |
1544 | } | |
1545 | ||
d288f65f VS |
1546 | static void chv_enable_pll(struct intel_crtc *crtc, |
1547 | const struct intel_crtc_config *pipe_config) | |
9d556c99 CML |
1548 | { |
1549 | struct drm_device *dev = crtc->base.dev; | |
1550 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1551 | int pipe = crtc->pipe; | |
1552 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1553 | u32 tmp; |
1554 | ||
1555 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1556 | ||
1557 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1558 | ||
1559 | mutex_lock(&dev_priv->dpio_lock); | |
1560 | ||
1561 | /* Enable back the 10bit clock to display controller */ | |
1562 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1563 | tmp |= DPIO_DCLKP_EN; | |
1564 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1565 | ||
1566 | /* | |
1567 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1568 | */ | |
1569 | udelay(1); | |
1570 | ||
1571 | /* Enable PLL */ | |
d288f65f | 1572 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1573 | |
1574 | /* Check PLL is locked */ | |
a11b0703 | 1575 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1576 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1577 | ||
a11b0703 | 1578 | /* not sure when this should be written */ |
d288f65f | 1579 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 VS |
1580 | POSTING_READ(DPLL_MD(pipe)); |
1581 | ||
9d556c99 CML |
1582 | mutex_unlock(&dev_priv->dpio_lock); |
1583 | } | |
1584 | ||
1c4e0274 VS |
1585 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1586 | { | |
1587 | struct intel_crtc *crtc; | |
1588 | int count = 0; | |
1589 | ||
1590 | for_each_intel_crtc(dev, crtc) | |
1591 | count += crtc->active && | |
409ee761 | 1592 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1593 | |
1594 | return count; | |
1595 | } | |
1596 | ||
66e3d5c0 | 1597 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1598 | { |
66e3d5c0 DV |
1599 | struct drm_device *dev = crtc->base.dev; |
1600 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1601 | int reg = DPLL(crtc->pipe); | |
1602 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1603 | |
66e3d5c0 | 1604 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1605 | |
63d7bbe9 | 1606 | /* No really, not for ILK+ */ |
3d13ef2e | 1607 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1608 | |
1609 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1610 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1611 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1612 | |
1c4e0274 VS |
1613 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1614 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1615 | /* | |
1616 | * It appears to be important that we don't enable this | |
1617 | * for the current pipe before otherwise configuring the | |
1618 | * PLL. No idea how this should be handled if multiple | |
1619 | * DVO outputs are enabled simultaneosly. | |
1620 | */ | |
1621 | dpll |= DPLL_DVO_2X_MODE; | |
1622 | I915_WRITE(DPLL(!crtc->pipe), | |
1623 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1624 | } | |
66e3d5c0 DV |
1625 | |
1626 | /* Wait for the clocks to stabilize. */ | |
1627 | POSTING_READ(reg); | |
1628 | udelay(150); | |
1629 | ||
1630 | if (INTEL_INFO(dev)->gen >= 4) { | |
1631 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1632 | crtc->config.dpll_hw_state.dpll_md); | |
1633 | } else { | |
1634 | /* The pixel multiplier can only be updated once the | |
1635 | * DPLL is enabled and the clocks are stable. | |
1636 | * | |
1637 | * So write it again. | |
1638 | */ | |
1639 | I915_WRITE(reg, dpll); | |
1640 | } | |
63d7bbe9 JB |
1641 | |
1642 | /* We do this three times for luck */ | |
66e3d5c0 | 1643 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1644 | POSTING_READ(reg); |
1645 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1646 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1647 | POSTING_READ(reg); |
1648 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1649 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1650 | POSTING_READ(reg); |
1651 | udelay(150); /* wait for warmup */ | |
1652 | } | |
1653 | ||
1654 | /** | |
50b44a44 | 1655 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1656 | * @dev_priv: i915 private structure |
1657 | * @pipe: pipe PLL to disable | |
1658 | * | |
1659 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1660 | * | |
1661 | * Note! This is for pre-ILK only. | |
1662 | */ | |
1c4e0274 | 1663 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1664 | { |
1c4e0274 VS |
1665 | struct drm_device *dev = crtc->base.dev; |
1666 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1667 | enum pipe pipe = crtc->pipe; | |
1668 | ||
1669 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1670 | if (IS_I830(dev) && | |
409ee761 | 1671 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
1c4e0274 VS |
1672 | intel_num_dvo_pipes(dev) == 1) { |
1673 | I915_WRITE(DPLL(PIPE_B), | |
1674 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1675 | I915_WRITE(DPLL(PIPE_A), | |
1676 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1677 | } | |
1678 | ||
b6b5d049 VS |
1679 | /* Don't disable pipe or pipe PLLs if needed */ |
1680 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1681 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1682 | return; |
1683 | ||
1684 | /* Make sure the pipe isn't still relying on us */ | |
1685 | assert_pipe_disabled(dev_priv, pipe); | |
1686 | ||
50b44a44 DV |
1687 | I915_WRITE(DPLL(pipe), 0); |
1688 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1689 | } |
1690 | ||
f6071166 JB |
1691 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1692 | { | |
1693 | u32 val = 0; | |
1694 | ||
1695 | /* Make sure the pipe isn't still relying on us */ | |
1696 | assert_pipe_disabled(dev_priv, pipe); | |
1697 | ||
e5cbfbfb ID |
1698 | /* |
1699 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1700 | * The latter is needed for VGA hotplug / manual detection. | |
1701 | */ | |
f6071166 | 1702 | if (pipe == PIPE_B) |
e5cbfbfb | 1703 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1704 | I915_WRITE(DPLL(pipe), val); |
1705 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1706 | |
1707 | } | |
1708 | ||
1709 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1710 | { | |
d752048d | 1711 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1712 | u32 val; |
1713 | ||
a11b0703 VS |
1714 | /* Make sure the pipe isn't still relying on us */ |
1715 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1716 | |
a11b0703 | 1717 | /* Set PLL en = 0 */ |
d17ec4ce | 1718 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1719 | if (pipe != PIPE_A) |
1720 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1721 | I915_WRITE(DPLL(pipe), val); | |
1722 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1723 | |
1724 | mutex_lock(&dev_priv->dpio_lock); | |
1725 | ||
1726 | /* Disable 10bit clock to display controller */ | |
1727 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1728 | val &= ~DPIO_DCLKP_EN; | |
1729 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1730 | ||
61407f6d VS |
1731 | /* disable left/right clock distribution */ |
1732 | if (pipe != PIPE_B) { | |
1733 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1734 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1735 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1736 | } else { | |
1737 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1738 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1739 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1740 | } | |
1741 | ||
d752048d | 1742 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1743 | } |
1744 | ||
e4607fcf CML |
1745 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1746 | struct intel_digital_port *dport) | |
89b667f8 JB |
1747 | { |
1748 | u32 port_mask; | |
00fc31b7 | 1749 | int dpll_reg; |
89b667f8 | 1750 | |
e4607fcf CML |
1751 | switch (dport->port) { |
1752 | case PORT_B: | |
89b667f8 | 1753 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1754 | dpll_reg = DPLL(0); |
e4607fcf CML |
1755 | break; |
1756 | case PORT_C: | |
89b667f8 | 1757 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1758 | dpll_reg = DPLL(0); |
1759 | break; | |
1760 | case PORT_D: | |
1761 | port_mask = DPLL_PORTD_READY_MASK; | |
1762 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1763 | break; |
1764 | default: | |
1765 | BUG(); | |
1766 | } | |
89b667f8 | 1767 | |
00fc31b7 | 1768 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1769 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1770 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1771 | } |
1772 | ||
b14b1055 DV |
1773 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1774 | { | |
1775 | struct drm_device *dev = crtc->base.dev; | |
1776 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1777 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1778 | ||
be19f0ff CW |
1779 | if (WARN_ON(pll == NULL)) |
1780 | return; | |
1781 | ||
3e369b76 | 1782 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1783 | if (pll->active == 0) { |
1784 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1785 | WARN_ON(pll->on); | |
1786 | assert_shared_dpll_disabled(dev_priv, pll); | |
1787 | ||
1788 | pll->mode_set(dev_priv, pll); | |
1789 | } | |
1790 | } | |
1791 | ||
92f2584a | 1792 | /** |
85b3894f | 1793 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1794 | * @dev_priv: i915 private structure |
1795 | * @pipe: pipe PLL to enable | |
1796 | * | |
1797 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1798 | * drives the transcoder clock. | |
1799 | */ | |
85b3894f | 1800 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1801 | { |
3d13ef2e DL |
1802 | struct drm_device *dev = crtc->base.dev; |
1803 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1804 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1805 | |
87a875bb | 1806 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1807 | return; |
1808 | ||
3e369b76 | 1809 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1810 | return; |
ee7b9f93 | 1811 | |
74dd6928 | 1812 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1813 | pll->name, pll->active, pll->on, |
e2b78267 | 1814 | crtc->base.base.id); |
92f2584a | 1815 | |
cdbd2316 DV |
1816 | if (pll->active++) { |
1817 | WARN_ON(!pll->on); | |
e9d6944e | 1818 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1819 | return; |
1820 | } | |
f4a091c7 | 1821 | WARN_ON(pll->on); |
ee7b9f93 | 1822 | |
bd2bb1b9 PZ |
1823 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1824 | ||
46edb027 | 1825 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1826 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1827 | pll->on = true; |
92f2584a JB |
1828 | } |
1829 | ||
f6daaec2 | 1830 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1831 | { |
3d13ef2e DL |
1832 | struct drm_device *dev = crtc->base.dev; |
1833 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1834 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1835 | |
92f2584a | 1836 | /* PCH only available on ILK+ */ |
3d13ef2e | 1837 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1838 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1839 | return; |
92f2584a | 1840 | |
3e369b76 | 1841 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1842 | return; |
7a419866 | 1843 | |
46edb027 DV |
1844 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1845 | pll->name, pll->active, pll->on, | |
e2b78267 | 1846 | crtc->base.base.id); |
7a419866 | 1847 | |
48da64a8 | 1848 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1849 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1850 | return; |
1851 | } | |
1852 | ||
e9d6944e | 1853 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1854 | WARN_ON(!pll->on); |
cdbd2316 | 1855 | if (--pll->active) |
7a419866 | 1856 | return; |
ee7b9f93 | 1857 | |
46edb027 | 1858 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1859 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1860 | pll->on = false; |
bd2bb1b9 PZ |
1861 | |
1862 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1863 | } |
1864 | ||
b8a4f404 PZ |
1865 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1866 | enum pipe pipe) | |
040484af | 1867 | { |
23670b32 | 1868 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1869 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1870 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1871 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1872 | |
1873 | /* PCH only available on ILK+ */ | |
55522f37 | 1874 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1875 | |
1876 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1877 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1878 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1879 | |
1880 | /* FDI must be feeding us bits for PCH ports */ | |
1881 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1882 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1883 | ||
23670b32 DV |
1884 | if (HAS_PCH_CPT(dev)) { |
1885 | /* Workaround: Set the timing override bit before enabling the | |
1886 | * pch transcoder. */ | |
1887 | reg = TRANS_CHICKEN2(pipe); | |
1888 | val = I915_READ(reg); | |
1889 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1890 | I915_WRITE(reg, val); | |
59c859d6 | 1891 | } |
23670b32 | 1892 | |
ab9412ba | 1893 | reg = PCH_TRANSCONF(pipe); |
040484af | 1894 | val = I915_READ(reg); |
5f7f726d | 1895 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1896 | |
1897 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1898 | /* | |
1899 | * make the BPC in transcoder be consistent with | |
1900 | * that in pipeconf reg. | |
1901 | */ | |
dfd07d72 DV |
1902 | val &= ~PIPECONF_BPC_MASK; |
1903 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1904 | } |
5f7f726d PZ |
1905 | |
1906 | val &= ~TRANS_INTERLACE_MASK; | |
1907 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 1908 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 1909 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1910 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1911 | else | |
1912 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1913 | else |
1914 | val |= TRANS_PROGRESSIVE; | |
1915 | ||
040484af JB |
1916 | I915_WRITE(reg, val | TRANS_ENABLE); |
1917 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1918 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1919 | } |
1920 | ||
8fb033d7 | 1921 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1922 | enum transcoder cpu_transcoder) |
040484af | 1923 | { |
8fb033d7 | 1924 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1925 | |
1926 | /* PCH only available on ILK+ */ | |
55522f37 | 1927 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 1928 | |
8fb033d7 | 1929 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1930 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1931 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1932 | |
223a6fdf PZ |
1933 | /* Workaround: set timing override bit. */ |
1934 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1935 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1936 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1937 | ||
25f3ef11 | 1938 | val = TRANS_ENABLE; |
937bb610 | 1939 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1940 | |
9a76b1c6 PZ |
1941 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1942 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1943 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1944 | else |
1945 | val |= TRANS_PROGRESSIVE; | |
1946 | ||
ab9412ba DV |
1947 | I915_WRITE(LPT_TRANSCONF, val); |
1948 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1949 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1950 | } |
1951 | ||
b8a4f404 PZ |
1952 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1953 | enum pipe pipe) | |
040484af | 1954 | { |
23670b32 DV |
1955 | struct drm_device *dev = dev_priv->dev; |
1956 | uint32_t reg, val; | |
040484af JB |
1957 | |
1958 | /* FDI relies on the transcoder */ | |
1959 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1960 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1961 | ||
291906f1 JB |
1962 | /* Ports must be off as well */ |
1963 | assert_pch_ports_disabled(dev_priv, pipe); | |
1964 | ||
ab9412ba | 1965 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1966 | val = I915_READ(reg); |
1967 | val &= ~TRANS_ENABLE; | |
1968 | I915_WRITE(reg, val); | |
1969 | /* wait for PCH transcoder off, transcoder state */ | |
1970 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1971 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
1972 | |
1973 | if (!HAS_PCH_IBX(dev)) { | |
1974 | /* Workaround: Clear the timing override chicken bit again. */ | |
1975 | reg = TRANS_CHICKEN2(pipe); | |
1976 | val = I915_READ(reg); | |
1977 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1978 | I915_WRITE(reg, val); | |
1979 | } | |
040484af JB |
1980 | } |
1981 | ||
ab4d966c | 1982 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1983 | { |
8fb033d7 PZ |
1984 | u32 val; |
1985 | ||
ab9412ba | 1986 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1987 | val &= ~TRANS_ENABLE; |
ab9412ba | 1988 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1989 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1990 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1991 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1992 | |
1993 | /* Workaround: clear timing override bit. */ | |
1994 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1995 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 1996 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
1997 | } |
1998 | ||
b24e7179 | 1999 | /** |
309cfea8 | 2000 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2001 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2002 | * |
0372264a | 2003 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2004 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2005 | */ |
e1fdc473 | 2006 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2007 | { |
0372264a PZ |
2008 | struct drm_device *dev = crtc->base.dev; |
2009 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2010 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2011 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2012 | pipe); | |
1a240d4d | 2013 | enum pipe pch_transcoder; |
b24e7179 JB |
2014 | int reg; |
2015 | u32 val; | |
2016 | ||
58c6eaa2 | 2017 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2018 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2019 | assert_sprites_disabled(dev_priv, pipe); |
2020 | ||
681e5811 | 2021 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2022 | pch_transcoder = TRANSCODER_A; |
2023 | else | |
2024 | pch_transcoder = pipe; | |
2025 | ||
b24e7179 JB |
2026 | /* |
2027 | * A pipe without a PLL won't actually be able to drive bits from | |
2028 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2029 | * need the check. | |
2030 | */ | |
2031 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
409ee761 | 2032 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2033 | assert_dsi_pll_enabled(dev_priv); |
2034 | else | |
2035 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2036 | else { |
30421c4f | 2037 | if (crtc->config.has_pch_encoder) { |
040484af | 2038 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2039 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2040 | assert_fdi_tx_pll_enabled(dev_priv, |
2041 | (enum pipe) cpu_transcoder); | |
040484af JB |
2042 | } |
2043 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2044 | } | |
b24e7179 | 2045 | |
702e7a56 | 2046 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2047 | val = I915_READ(reg); |
7ad25d48 | 2048 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2049 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2050 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2051 | return; |
7ad25d48 | 2052 | } |
00d70b15 CW |
2053 | |
2054 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2055 | POSTING_READ(reg); |
b24e7179 JB |
2056 | } |
2057 | ||
2058 | /** | |
309cfea8 | 2059 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2060 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2061 | * |
575f7ab7 VS |
2062 | * Disable the pipe of @crtc, making sure that various hardware |
2063 | * specific requirements are met, if applicable, e.g. plane | |
2064 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2065 | * |
2066 | * Will wait until the pipe has shut down before returning. | |
2067 | */ | |
575f7ab7 | 2068 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2069 | { |
575f7ab7 VS |
2070 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
2071 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
2072 | enum pipe pipe = crtc->pipe; | |
b24e7179 JB |
2073 | int reg; |
2074 | u32 val; | |
2075 | ||
2076 | /* | |
2077 | * Make sure planes won't keep trying to pump pixels to us, | |
2078 | * or we might hang the display. | |
2079 | */ | |
2080 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2081 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2082 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2083 | |
702e7a56 | 2084 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2085 | val = I915_READ(reg); |
00d70b15 CW |
2086 | if ((val & PIPECONF_ENABLE) == 0) |
2087 | return; | |
2088 | ||
67adc644 VS |
2089 | /* |
2090 | * Double wide has implications for planes | |
2091 | * so best keep it disabled when not needed. | |
2092 | */ | |
2093 | if (crtc->config.double_wide) | |
2094 | val &= ~PIPECONF_DOUBLE_WIDE; | |
2095 | ||
2096 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2097 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2098 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2099 | val &= ~PIPECONF_ENABLE; |
2100 | ||
2101 | I915_WRITE(reg, val); | |
2102 | if ((val & PIPECONF_ENABLE) == 0) | |
2103 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2104 | } |
2105 | ||
d74362c9 KP |
2106 | /* |
2107 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2108 | * trigger in order to latch. The display address reg provides this. | |
2109 | */ | |
1dba99f4 VS |
2110 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2111 | enum plane plane) | |
d74362c9 | 2112 | { |
3d13ef2e DL |
2113 | struct drm_device *dev = dev_priv->dev; |
2114 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2115 | |
2116 | I915_WRITE(reg, I915_READ(reg)); | |
2117 | POSTING_READ(reg); | |
d74362c9 KP |
2118 | } |
2119 | ||
b24e7179 | 2120 | /** |
262ca2b0 | 2121 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2122 | * @plane: plane to be enabled |
2123 | * @crtc: crtc for the plane | |
b24e7179 | 2124 | * |
fdd508a6 | 2125 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2126 | */ |
fdd508a6 VS |
2127 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2128 | struct drm_crtc *crtc) | |
b24e7179 | 2129 | { |
fdd508a6 VS |
2130 | struct drm_device *dev = plane->dev; |
2131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2132 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2133 | |
2134 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2135 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b24e7179 | 2136 | |
98ec7739 VS |
2137 | if (intel_crtc->primary_enabled) |
2138 | return; | |
0037f71c | 2139 | |
4c445e0e | 2140 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2141 | |
fdd508a6 VS |
2142 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2143 | crtc->x, crtc->y); | |
33c3b0d1 VS |
2144 | |
2145 | /* | |
2146 | * BDW signals flip done immediately if the plane | |
2147 | * is disabled, even if the plane enable is already | |
2148 | * armed to occur at the next vblank :( | |
2149 | */ | |
2150 | if (IS_BROADWELL(dev)) | |
2151 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
b24e7179 JB |
2152 | } |
2153 | ||
b24e7179 | 2154 | /** |
262ca2b0 | 2155 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
fdd508a6 VS |
2156 | * @plane: plane to be disabled |
2157 | * @crtc: crtc for the plane | |
b24e7179 | 2158 | * |
fdd508a6 | 2159 | * Disable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2160 | */ |
fdd508a6 VS |
2161 | static void intel_disable_primary_hw_plane(struct drm_plane *plane, |
2162 | struct drm_crtc *crtc) | |
b24e7179 | 2163 | { |
fdd508a6 VS |
2164 | struct drm_device *dev = plane->dev; |
2165 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2166 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2167 | ||
2168 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); | |
b24e7179 | 2169 | |
98ec7739 VS |
2170 | if (!intel_crtc->primary_enabled) |
2171 | return; | |
0037f71c | 2172 | |
4c445e0e | 2173 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2174 | |
fdd508a6 VS |
2175 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2176 | crtc->x, crtc->y); | |
b24e7179 JB |
2177 | } |
2178 | ||
693db184 CW |
2179 | static bool need_vtd_wa(struct drm_device *dev) |
2180 | { | |
2181 | #ifdef CONFIG_INTEL_IOMMU | |
2182 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2183 | return true; | |
2184 | #endif | |
2185 | return false; | |
2186 | } | |
2187 | ||
a57ce0b2 JB |
2188 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
2189 | { | |
2190 | int tile_height; | |
2191 | ||
2192 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; | |
2193 | return ALIGN(height, tile_height); | |
2194 | } | |
2195 | ||
127bd2ac | 2196 | int |
850c4cdc TU |
2197 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2198 | struct drm_framebuffer *fb, | |
a4872ba6 | 2199 | struct intel_engine_cs *pipelined) |
6b95a207 | 2200 | { |
850c4cdc | 2201 | struct drm_device *dev = fb->dev; |
ce453d81 | 2202 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2203 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 KH |
2204 | u32 alignment; |
2205 | int ret; | |
2206 | ||
ebcdd39e MR |
2207 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2208 | ||
05394f39 | 2209 | switch (obj->tiling_mode) { |
6b95a207 | 2210 | case I915_TILING_NONE: |
1fada4cc DL |
2211 | if (INTEL_INFO(dev)->gen >= 9) |
2212 | alignment = 256 * 1024; | |
2213 | else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
534843da | 2214 | alignment = 128 * 1024; |
a6c45cf0 | 2215 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2216 | alignment = 4 * 1024; |
2217 | else | |
2218 | alignment = 64 * 1024; | |
6b95a207 KH |
2219 | break; |
2220 | case I915_TILING_X: | |
1fada4cc DL |
2221 | if (INTEL_INFO(dev)->gen >= 9) |
2222 | alignment = 256 * 1024; | |
2223 | else { | |
2224 | /* pin() will align the object as required by fence */ | |
2225 | alignment = 0; | |
2226 | } | |
6b95a207 KH |
2227 | break; |
2228 | case I915_TILING_Y: | |
80075d49 | 2229 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
2230 | return -EINVAL; |
2231 | default: | |
2232 | BUG(); | |
2233 | } | |
2234 | ||
693db184 CW |
2235 | /* Note that the w/a also requires 64 PTE of padding following the |
2236 | * bo. We currently fill all unused PTE with the shadow page and so | |
2237 | * we should always have valid PTE following the scanout preventing | |
2238 | * the VT-d warning. | |
2239 | */ | |
2240 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2241 | alignment = 256 * 1024; | |
2242 | ||
d6dd6843 PZ |
2243 | /* |
2244 | * Global gtt pte registers are special registers which actually forward | |
2245 | * writes to a chunk of system memory. Which means that there is no risk | |
2246 | * that the register values disappear as soon as we call | |
2247 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2248 | * pin/unpin/fence and not more. | |
2249 | */ | |
2250 | intel_runtime_pm_get(dev_priv); | |
2251 | ||
ce453d81 | 2252 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 2253 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 2254 | if (ret) |
ce453d81 | 2255 | goto err_interruptible; |
6b95a207 KH |
2256 | |
2257 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2258 | * fence, whereas 965+ only requires a fence if using | |
2259 | * framebuffer compression. For simplicity, we always install | |
2260 | * a fence as the cost is not that onerous. | |
2261 | */ | |
06d98131 | 2262 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2263 | if (ret) |
2264 | goto err_unpin; | |
1690e1eb | 2265 | |
9a5a53b3 | 2266 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2267 | |
ce453d81 | 2268 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2269 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2270 | return 0; |
48b956c5 CW |
2271 | |
2272 | err_unpin: | |
cc98b413 | 2273 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
2274 | err_interruptible: |
2275 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2276 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2277 | return ret; |
6b95a207 KH |
2278 | } |
2279 | ||
1690e1eb CW |
2280 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2281 | { | |
ebcdd39e MR |
2282 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2283 | ||
1690e1eb | 2284 | i915_gem_object_unpin_fence(obj); |
cc98b413 | 2285 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
2286 | } |
2287 | ||
c2c75131 DV |
2288 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2289 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2290 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2291 | unsigned int tiling_mode, | |
2292 | unsigned int cpp, | |
2293 | unsigned int pitch) | |
c2c75131 | 2294 | { |
bc752862 CW |
2295 | if (tiling_mode != I915_TILING_NONE) { |
2296 | unsigned int tile_rows, tiles; | |
c2c75131 | 2297 | |
bc752862 CW |
2298 | tile_rows = *y / 8; |
2299 | *y %= 8; | |
c2c75131 | 2300 | |
bc752862 CW |
2301 | tiles = *x / (512/cpp); |
2302 | *x %= 512/cpp; | |
2303 | ||
2304 | return tile_rows * pitch * 8 + tiles * 4096; | |
2305 | } else { | |
2306 | unsigned int offset; | |
2307 | ||
2308 | offset = *y * pitch + *x * cpp; | |
2309 | *y = 0; | |
2310 | *x = (offset & 4095) / cpp; | |
2311 | return offset & -4096; | |
2312 | } | |
c2c75131 DV |
2313 | } |
2314 | ||
46f297fb JB |
2315 | int intel_format_to_fourcc(int format) |
2316 | { | |
2317 | switch (format) { | |
2318 | case DISPPLANE_8BPP: | |
2319 | return DRM_FORMAT_C8; | |
2320 | case DISPPLANE_BGRX555: | |
2321 | return DRM_FORMAT_XRGB1555; | |
2322 | case DISPPLANE_BGRX565: | |
2323 | return DRM_FORMAT_RGB565; | |
2324 | default: | |
2325 | case DISPPLANE_BGRX888: | |
2326 | return DRM_FORMAT_XRGB8888; | |
2327 | case DISPPLANE_RGBX888: | |
2328 | return DRM_FORMAT_XBGR8888; | |
2329 | case DISPPLANE_BGRX101010: | |
2330 | return DRM_FORMAT_XRGB2101010; | |
2331 | case DISPPLANE_RGBX101010: | |
2332 | return DRM_FORMAT_XBGR2101010; | |
2333 | } | |
2334 | } | |
2335 | ||
484b41dd | 2336 | static bool intel_alloc_plane_obj(struct intel_crtc *crtc, |
46f297fb JB |
2337 | struct intel_plane_config *plane_config) |
2338 | { | |
2339 | struct drm_device *dev = crtc->base.dev; | |
2340 | struct drm_i915_gem_object *obj = NULL; | |
2341 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2342 | u32 base = plane_config->base; | |
2343 | ||
ff2652ea CW |
2344 | if (plane_config->size == 0) |
2345 | return false; | |
2346 | ||
46f297fb JB |
2347 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
2348 | plane_config->size); | |
2349 | if (!obj) | |
484b41dd | 2350 | return false; |
46f297fb JB |
2351 | |
2352 | if (plane_config->tiled) { | |
2353 | obj->tiling_mode = I915_TILING_X; | |
66e514c1 | 2354 | obj->stride = crtc->base.primary->fb->pitches[0]; |
46f297fb JB |
2355 | } |
2356 | ||
66e514c1 DA |
2357 | mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format; |
2358 | mode_cmd.width = crtc->base.primary->fb->width; | |
2359 | mode_cmd.height = crtc->base.primary->fb->height; | |
2360 | mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0]; | |
46f297fb JB |
2361 | |
2362 | mutex_lock(&dev->struct_mutex); | |
2363 | ||
66e514c1 | 2364 | if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb), |
484b41dd | 2365 | &mode_cmd, obj)) { |
46f297fb JB |
2366 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2367 | goto out_unref_obj; | |
2368 | } | |
2369 | ||
a071fa00 | 2370 | obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe); |
46f297fb | 2371 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2372 | |
2373 | DRM_DEBUG_KMS("plane fb obj %p\n", obj); | |
2374 | return true; | |
46f297fb JB |
2375 | |
2376 | out_unref_obj: | |
2377 | drm_gem_object_unreference(&obj->base); | |
2378 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2379 | return false; |
2380 | } | |
2381 | ||
2382 | static void intel_find_plane_obj(struct intel_crtc *intel_crtc, | |
2383 | struct intel_plane_config *plane_config) | |
2384 | { | |
2385 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2386 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2387 | struct drm_crtc *c; |
2388 | struct intel_crtc *i; | |
2ff8fde1 | 2389 | struct drm_i915_gem_object *obj; |
484b41dd | 2390 | |
66e514c1 | 2391 | if (!intel_crtc->base.primary->fb) |
484b41dd JB |
2392 | return; |
2393 | ||
2394 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) | |
2395 | return; | |
2396 | ||
66e514c1 DA |
2397 | kfree(intel_crtc->base.primary->fb); |
2398 | intel_crtc->base.primary->fb = NULL; | |
484b41dd JB |
2399 | |
2400 | /* | |
2401 | * Failed to alloc the obj, check to see if we should share | |
2402 | * an fb with another CRTC instead | |
2403 | */ | |
70e1e0ec | 2404 | for_each_crtc(dev, c) { |
484b41dd JB |
2405 | i = to_intel_crtc(c); |
2406 | ||
2407 | if (c == &intel_crtc->base) | |
2408 | continue; | |
2409 | ||
2ff8fde1 MR |
2410 | if (!i->active) |
2411 | continue; | |
2412 | ||
2413 | obj = intel_fb_obj(c->primary->fb); | |
2414 | if (obj == NULL) | |
484b41dd JB |
2415 | continue; |
2416 | ||
2ff8fde1 | 2417 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
d9ceb816 JB |
2418 | if (obj->tiling_mode != I915_TILING_NONE) |
2419 | dev_priv->preserve_bios_swizzle = true; | |
2420 | ||
66e514c1 DA |
2421 | drm_framebuffer_reference(c->primary->fb); |
2422 | intel_crtc->base.primary->fb = c->primary->fb; | |
2ff8fde1 | 2423 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); |
484b41dd JB |
2424 | break; |
2425 | } | |
2426 | } | |
46f297fb JB |
2427 | } |
2428 | ||
29b9bde6 DV |
2429 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2430 | struct drm_framebuffer *fb, | |
2431 | int x, int y) | |
81255565 JB |
2432 | { |
2433 | struct drm_device *dev = crtc->dev; | |
2434 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2435 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2436 | struct drm_i915_gem_object *obj; |
81255565 | 2437 | int plane = intel_crtc->plane; |
e506a0c6 | 2438 | unsigned long linear_offset; |
81255565 | 2439 | u32 dspcntr; |
f45651ba | 2440 | u32 reg = DSPCNTR(plane); |
48404c1e | 2441 | int pixel_size; |
f45651ba | 2442 | |
fdd508a6 VS |
2443 | if (!intel_crtc->primary_enabled) { |
2444 | I915_WRITE(reg, 0); | |
2445 | if (INTEL_INFO(dev)->gen >= 4) | |
2446 | I915_WRITE(DSPSURF(plane), 0); | |
2447 | else | |
2448 | I915_WRITE(DSPADDR(plane), 0); | |
2449 | POSTING_READ(reg); | |
2450 | return; | |
2451 | } | |
2452 | ||
c9ba6fad VS |
2453 | obj = intel_fb_obj(fb); |
2454 | if (WARN_ON(obj == NULL)) | |
2455 | return; | |
2456 | ||
2457 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2458 | ||
f45651ba VS |
2459 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2460 | ||
fdd508a6 | 2461 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2462 | |
2463 | if (INTEL_INFO(dev)->gen < 4) { | |
2464 | if (intel_crtc->pipe == PIPE_B) | |
2465 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2466 | ||
2467 | /* pipesrc and dspsize control the size that is scaled from, | |
2468 | * which should always be the user's requested size. | |
2469 | */ | |
2470 | I915_WRITE(DSPSIZE(plane), | |
2471 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
2472 | (intel_crtc->config.pipe_src_w - 1)); | |
2473 | I915_WRITE(DSPPOS(plane), 0); | |
c14b0485 VS |
2474 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2475 | I915_WRITE(PRIMSIZE(plane), | |
2476 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
2477 | (intel_crtc->config.pipe_src_w - 1)); | |
2478 | I915_WRITE(PRIMPOS(plane), 0); | |
2479 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2480 | } |
81255565 | 2481 | |
57779d06 VS |
2482 | switch (fb->pixel_format) { |
2483 | case DRM_FORMAT_C8: | |
81255565 JB |
2484 | dspcntr |= DISPPLANE_8BPP; |
2485 | break; | |
57779d06 VS |
2486 | case DRM_FORMAT_XRGB1555: |
2487 | case DRM_FORMAT_ARGB1555: | |
2488 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2489 | break; |
57779d06 VS |
2490 | case DRM_FORMAT_RGB565: |
2491 | dspcntr |= DISPPLANE_BGRX565; | |
2492 | break; | |
2493 | case DRM_FORMAT_XRGB8888: | |
2494 | case DRM_FORMAT_ARGB8888: | |
2495 | dspcntr |= DISPPLANE_BGRX888; | |
2496 | break; | |
2497 | case DRM_FORMAT_XBGR8888: | |
2498 | case DRM_FORMAT_ABGR8888: | |
2499 | dspcntr |= DISPPLANE_RGBX888; | |
2500 | break; | |
2501 | case DRM_FORMAT_XRGB2101010: | |
2502 | case DRM_FORMAT_ARGB2101010: | |
2503 | dspcntr |= DISPPLANE_BGRX101010; | |
2504 | break; | |
2505 | case DRM_FORMAT_XBGR2101010: | |
2506 | case DRM_FORMAT_ABGR2101010: | |
2507 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2508 | break; |
2509 | default: | |
baba133a | 2510 | BUG(); |
81255565 | 2511 | } |
57779d06 | 2512 | |
f45651ba VS |
2513 | if (INTEL_INFO(dev)->gen >= 4 && |
2514 | obj->tiling_mode != I915_TILING_NONE) | |
2515 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2516 | |
de1aa629 VS |
2517 | if (IS_G4X(dev)) |
2518 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2519 | ||
b9897127 | 2520 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2521 | |
c2c75131 DV |
2522 | if (INTEL_INFO(dev)->gen >= 4) { |
2523 | intel_crtc->dspaddr_offset = | |
bc752862 | 2524 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2525 | pixel_size, |
bc752862 | 2526 | fb->pitches[0]); |
c2c75131 DV |
2527 | linear_offset -= intel_crtc->dspaddr_offset; |
2528 | } else { | |
e506a0c6 | 2529 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2530 | } |
e506a0c6 | 2531 | |
48404c1e SJ |
2532 | if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) { |
2533 | dspcntr |= DISPPLANE_ROTATE_180; | |
2534 | ||
2535 | x += (intel_crtc->config.pipe_src_w - 1); | |
2536 | y += (intel_crtc->config.pipe_src_h - 1); | |
2537 | ||
2538 | /* Finding the last pixel of the last line of the display | |
2539 | data and adding to linear_offset*/ | |
2540 | linear_offset += | |
2541 | (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + | |
2542 | (intel_crtc->config.pipe_src_w - 1) * pixel_size; | |
2543 | } | |
2544 | ||
2545 | I915_WRITE(reg, dspcntr); | |
2546 | ||
f343c5f6 BW |
2547 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2548 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2549 | fb->pitches[0]); | |
01f2c773 | 2550 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2551 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2552 | I915_WRITE(DSPSURF(plane), |
2553 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2554 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2555 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2556 | } else |
f343c5f6 | 2557 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2558 | POSTING_READ(reg); |
17638cd6 JB |
2559 | } |
2560 | ||
29b9bde6 DV |
2561 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2562 | struct drm_framebuffer *fb, | |
2563 | int x, int y) | |
17638cd6 JB |
2564 | { |
2565 | struct drm_device *dev = crtc->dev; | |
2566 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2567 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2568 | struct drm_i915_gem_object *obj; |
17638cd6 | 2569 | int plane = intel_crtc->plane; |
e506a0c6 | 2570 | unsigned long linear_offset; |
17638cd6 | 2571 | u32 dspcntr; |
f45651ba | 2572 | u32 reg = DSPCNTR(plane); |
48404c1e | 2573 | int pixel_size; |
f45651ba | 2574 | |
fdd508a6 VS |
2575 | if (!intel_crtc->primary_enabled) { |
2576 | I915_WRITE(reg, 0); | |
2577 | I915_WRITE(DSPSURF(plane), 0); | |
2578 | POSTING_READ(reg); | |
2579 | return; | |
2580 | } | |
2581 | ||
c9ba6fad VS |
2582 | obj = intel_fb_obj(fb); |
2583 | if (WARN_ON(obj == NULL)) | |
2584 | return; | |
2585 | ||
2586 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2587 | ||
f45651ba VS |
2588 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2589 | ||
fdd508a6 | 2590 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2591 | |
2592 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2593 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2594 | |
57779d06 VS |
2595 | switch (fb->pixel_format) { |
2596 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2597 | dspcntr |= DISPPLANE_8BPP; |
2598 | break; | |
57779d06 VS |
2599 | case DRM_FORMAT_RGB565: |
2600 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2601 | break; |
57779d06 VS |
2602 | case DRM_FORMAT_XRGB8888: |
2603 | case DRM_FORMAT_ARGB8888: | |
2604 | dspcntr |= DISPPLANE_BGRX888; | |
2605 | break; | |
2606 | case DRM_FORMAT_XBGR8888: | |
2607 | case DRM_FORMAT_ABGR8888: | |
2608 | dspcntr |= DISPPLANE_RGBX888; | |
2609 | break; | |
2610 | case DRM_FORMAT_XRGB2101010: | |
2611 | case DRM_FORMAT_ARGB2101010: | |
2612 | dspcntr |= DISPPLANE_BGRX101010; | |
2613 | break; | |
2614 | case DRM_FORMAT_XBGR2101010: | |
2615 | case DRM_FORMAT_ABGR2101010: | |
2616 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2617 | break; |
2618 | default: | |
baba133a | 2619 | BUG(); |
17638cd6 JB |
2620 | } |
2621 | ||
2622 | if (obj->tiling_mode != I915_TILING_NONE) | |
2623 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2624 | |
f45651ba | 2625 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2626 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2627 | |
b9897127 | 2628 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2629 | intel_crtc->dspaddr_offset = |
bc752862 | 2630 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2631 | pixel_size, |
bc752862 | 2632 | fb->pitches[0]); |
c2c75131 | 2633 | linear_offset -= intel_crtc->dspaddr_offset; |
48404c1e SJ |
2634 | if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) { |
2635 | dspcntr |= DISPPLANE_ROTATE_180; | |
2636 | ||
2637 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
2638 | x += (intel_crtc->config.pipe_src_w - 1); | |
2639 | y += (intel_crtc->config.pipe_src_h - 1); | |
2640 | ||
2641 | /* Finding the last pixel of the last line of the display | |
2642 | data and adding to linear_offset*/ | |
2643 | linear_offset += | |
2644 | (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + | |
2645 | (intel_crtc->config.pipe_src_w - 1) * pixel_size; | |
2646 | } | |
2647 | } | |
2648 | ||
2649 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2650 | |
f343c5f6 BW |
2651 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2652 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2653 | fb->pitches[0]); | |
01f2c773 | 2654 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2655 | I915_WRITE(DSPSURF(plane), |
2656 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2657 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2658 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2659 | } else { | |
2660 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2661 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2662 | } | |
17638cd6 | 2663 | POSTING_READ(reg); |
17638cd6 JB |
2664 | } |
2665 | ||
70d21f0e DL |
2666 | static void skylake_update_primary_plane(struct drm_crtc *crtc, |
2667 | struct drm_framebuffer *fb, | |
2668 | int x, int y) | |
2669 | { | |
2670 | struct drm_device *dev = crtc->dev; | |
2671 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2672 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2673 | struct intel_framebuffer *intel_fb; | |
2674 | struct drm_i915_gem_object *obj; | |
2675 | int pipe = intel_crtc->pipe; | |
2676 | u32 plane_ctl, stride; | |
2677 | ||
2678 | if (!intel_crtc->primary_enabled) { | |
2679 | I915_WRITE(PLANE_CTL(pipe, 0), 0); | |
2680 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
2681 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
2682 | return; | |
2683 | } | |
2684 | ||
2685 | plane_ctl = PLANE_CTL_ENABLE | | |
2686 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
2687 | PLANE_CTL_PIPE_CSC_ENABLE; | |
2688 | ||
2689 | switch (fb->pixel_format) { | |
2690 | case DRM_FORMAT_RGB565: | |
2691 | plane_ctl |= PLANE_CTL_FORMAT_RGB_565; | |
2692 | break; | |
2693 | case DRM_FORMAT_XRGB8888: | |
2694 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2695 | break; | |
2696 | case DRM_FORMAT_XBGR8888: | |
2697 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2698 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; | |
2699 | break; | |
2700 | case DRM_FORMAT_XRGB2101010: | |
2701 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
2702 | break; | |
2703 | case DRM_FORMAT_XBGR2101010: | |
2704 | plane_ctl |= PLANE_CTL_ORDER_RGBX; | |
2705 | plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; | |
2706 | break; | |
2707 | default: | |
2708 | BUG(); | |
2709 | } | |
2710 | ||
2711 | intel_fb = to_intel_framebuffer(fb); | |
2712 | obj = intel_fb->obj; | |
2713 | ||
2714 | /* | |
2715 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
2716 | * linear buffers or in number of tiles for tiled buffers. | |
2717 | */ | |
2718 | switch (obj->tiling_mode) { | |
2719 | case I915_TILING_NONE: | |
2720 | stride = fb->pitches[0] >> 6; | |
2721 | break; | |
2722 | case I915_TILING_X: | |
2723 | plane_ctl |= PLANE_CTL_TILED_X; | |
2724 | stride = fb->pitches[0] >> 9; | |
2725 | break; | |
2726 | default: | |
2727 | BUG(); | |
2728 | } | |
2729 | ||
2730 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
1447dde0 SJ |
2731 | if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) |
2732 | plane_ctl |= PLANE_CTL_ROTATE_180; | |
70d21f0e DL |
2733 | |
2734 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); | |
2735 | ||
2736 | DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n", | |
2737 | i915_gem_obj_ggtt_offset(obj), | |
2738 | x, y, fb->width, fb->height, | |
2739 | fb->pitches[0]); | |
2740 | ||
2741 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
2742 | I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x); | |
2743 | I915_WRITE(PLANE_SIZE(pipe, 0), | |
2744 | (intel_crtc->config.pipe_src_h - 1) << 16 | | |
2745 | (intel_crtc->config.pipe_src_w - 1)); | |
2746 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
2747 | I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj)); | |
2748 | ||
2749 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
2750 | } | |
2751 | ||
17638cd6 JB |
2752 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
2753 | static int | |
2754 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2755 | int x, int y, enum mode_set_atomic state) | |
2756 | { | |
2757 | struct drm_device *dev = crtc->dev; | |
2758 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2759 | |
6b8e6ed0 CW |
2760 | if (dev_priv->display.disable_fbc) |
2761 | dev_priv->display.disable_fbc(dev); | |
81255565 | 2762 | |
29b9bde6 DV |
2763 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2764 | ||
2765 | return 0; | |
81255565 JB |
2766 | } |
2767 | ||
7514747d | 2768 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 2769 | { |
96a02917 VS |
2770 | struct drm_crtc *crtc; |
2771 | ||
70e1e0ec | 2772 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2773 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2774 | enum plane plane = intel_crtc->plane; | |
2775 | ||
2776 | intel_prepare_page_flip(dev, plane); | |
2777 | intel_finish_page_flip_plane(dev, plane); | |
2778 | } | |
7514747d VS |
2779 | } |
2780 | ||
2781 | static void intel_update_primary_planes(struct drm_device *dev) | |
2782 | { | |
2783 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2784 | struct drm_crtc *crtc; | |
96a02917 | 2785 | |
70e1e0ec | 2786 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2787 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2788 | ||
51fd371b | 2789 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
2790 | /* |
2791 | * FIXME: Once we have proper support for primary planes (and | |
2792 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 2793 | * a NULL crtc->primary->fb. |
947fdaad | 2794 | */ |
f4510a27 | 2795 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 2796 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 2797 | crtc->primary->fb, |
262ca2b0 MR |
2798 | crtc->x, |
2799 | crtc->y); | |
51fd371b | 2800 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
2801 | } |
2802 | } | |
2803 | ||
7514747d VS |
2804 | void intel_prepare_reset(struct drm_device *dev) |
2805 | { | |
f98ce92f VS |
2806 | struct drm_i915_private *dev_priv = to_i915(dev); |
2807 | struct intel_crtc *crtc; | |
2808 | ||
7514747d VS |
2809 | /* no reset support for gen2 */ |
2810 | if (IS_GEN2(dev)) | |
2811 | return; | |
2812 | ||
2813 | /* reset doesn't touch the display */ | |
2814 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
2815 | return; | |
2816 | ||
2817 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
2818 | |
2819 | /* | |
2820 | * Disabling the crtcs gracefully seems nicer. Also the | |
2821 | * g33 docs say we should at least disable all the planes. | |
2822 | */ | |
2823 | for_each_intel_crtc(dev, crtc) { | |
2824 | if (crtc->active) | |
2825 | dev_priv->display.crtc_disable(&crtc->base); | |
2826 | } | |
7514747d VS |
2827 | } |
2828 | ||
2829 | void intel_finish_reset(struct drm_device *dev) | |
2830 | { | |
2831 | struct drm_i915_private *dev_priv = to_i915(dev); | |
2832 | ||
2833 | /* | |
2834 | * Flips in the rings will be nuked by the reset, | |
2835 | * so complete all pending flips so that user space | |
2836 | * will get its events and not get stuck. | |
2837 | */ | |
2838 | intel_complete_page_flips(dev); | |
2839 | ||
2840 | /* no reset support for gen2 */ | |
2841 | if (IS_GEN2(dev)) | |
2842 | return; | |
2843 | ||
2844 | /* reset doesn't touch the display */ | |
2845 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
2846 | /* | |
2847 | * Flips in the rings have been nuked by the reset, | |
2848 | * so update the base address of all primary | |
2849 | * planes to the the last fb to make sure we're | |
2850 | * showing the correct fb after a reset. | |
2851 | */ | |
2852 | intel_update_primary_planes(dev); | |
2853 | return; | |
2854 | } | |
2855 | ||
2856 | /* | |
2857 | * The display has been reset as well, | |
2858 | * so need a full re-initialization. | |
2859 | */ | |
2860 | intel_runtime_pm_disable_interrupts(dev_priv); | |
2861 | intel_runtime_pm_enable_interrupts(dev_priv); | |
2862 | ||
2863 | intel_modeset_init_hw(dev); | |
2864 | ||
2865 | spin_lock_irq(&dev_priv->irq_lock); | |
2866 | if (dev_priv->display.hpd_irq_setup) | |
2867 | dev_priv->display.hpd_irq_setup(dev); | |
2868 | spin_unlock_irq(&dev_priv->irq_lock); | |
2869 | ||
2870 | intel_modeset_setup_hw_state(dev, true); | |
2871 | ||
2872 | intel_hpd_init(dev_priv); | |
2873 | ||
2874 | drm_modeset_unlock_all(dev); | |
2875 | } | |
2876 | ||
14667a4b CW |
2877 | static int |
2878 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2879 | { | |
2ff8fde1 | 2880 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
14667a4b CW |
2881 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2882 | bool was_interruptible = dev_priv->mm.interruptible; | |
2883 | int ret; | |
2884 | ||
14667a4b CW |
2885 | /* Big Hammer, we also need to ensure that any pending |
2886 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2887 | * current scanout is retired before unpinning the old | |
2888 | * framebuffer. | |
2889 | * | |
2890 | * This should only fail upon a hung GPU, in which case we | |
2891 | * can safely continue. | |
2892 | */ | |
2893 | dev_priv->mm.interruptible = false; | |
2894 | ret = i915_gem_object_finish_gpu(obj); | |
2895 | dev_priv->mm.interruptible = was_interruptible; | |
2896 | ||
2897 | return ret; | |
2898 | } | |
2899 | ||
7d5e3799 CW |
2900 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2901 | { | |
2902 | struct drm_device *dev = crtc->dev; | |
2903 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2904 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
2905 | bool pending; |
2906 | ||
2907 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
2908 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
2909 | return false; | |
2910 | ||
5e2d7afc | 2911 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 2912 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 2913 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
2914 | |
2915 | return pending; | |
2916 | } | |
2917 | ||
e30e8f75 GP |
2918 | static void intel_update_pipe_size(struct intel_crtc *crtc) |
2919 | { | |
2920 | struct drm_device *dev = crtc->base.dev; | |
2921 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2922 | const struct drm_display_mode *adjusted_mode; | |
2923 | ||
2924 | if (!i915.fastboot) | |
2925 | return; | |
2926 | ||
2927 | /* | |
2928 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2929 | * that in compute_mode_changes we check the native mode (not the pfit | |
2930 | * mode) to see if we can flip rather than do a full mode set. In the | |
2931 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2932 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2933 | * sized surface. | |
2934 | * | |
2935 | * To fix this properly, we need to hoist the checks up into | |
2936 | * compute_mode_changes (or above), check the actual pfit state and | |
2937 | * whether the platform allows pfit disable with pipe active, and only | |
2938 | * then update the pipesrc and pfit state, even on the flip path. | |
2939 | */ | |
2940 | ||
2941 | adjusted_mode = &crtc->config.adjusted_mode; | |
2942 | ||
2943 | I915_WRITE(PIPESRC(crtc->pipe), | |
2944 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | | |
2945 | (adjusted_mode->crtc_vdisplay - 1)); | |
2946 | if (!crtc->config.pch_pfit.enabled && | |
409ee761 ACO |
2947 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
2948 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
e30e8f75 GP |
2949 | I915_WRITE(PF_CTL(crtc->pipe), 0); |
2950 | I915_WRITE(PF_WIN_POS(crtc->pipe), 0); | |
2951 | I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); | |
2952 | } | |
2953 | crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; | |
2954 | crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; | |
2955 | } | |
2956 | ||
5e84e1a4 ZW |
2957 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2958 | { | |
2959 | struct drm_device *dev = crtc->dev; | |
2960 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2961 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2962 | int pipe = intel_crtc->pipe; | |
2963 | u32 reg, temp; | |
2964 | ||
2965 | /* enable normal train */ | |
2966 | reg = FDI_TX_CTL(pipe); | |
2967 | temp = I915_READ(reg); | |
61e499bf | 2968 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2969 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2970 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2971 | } else { |
2972 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2973 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2974 | } |
5e84e1a4 ZW |
2975 | I915_WRITE(reg, temp); |
2976 | ||
2977 | reg = FDI_RX_CTL(pipe); | |
2978 | temp = I915_READ(reg); | |
2979 | if (HAS_PCH_CPT(dev)) { | |
2980 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2981 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2982 | } else { | |
2983 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2984 | temp |= FDI_LINK_TRAIN_NONE; | |
2985 | } | |
2986 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2987 | ||
2988 | /* wait one idle pattern time */ | |
2989 | POSTING_READ(reg); | |
2990 | udelay(1000); | |
357555c0 JB |
2991 | |
2992 | /* IVB wants error correction enabled */ | |
2993 | if (IS_IVYBRIDGE(dev)) | |
2994 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2995 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2996 | } |
2997 | ||
1fbc0d78 | 2998 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 2999 | { |
1fbc0d78 DV |
3000 | return crtc->base.enabled && crtc->active && |
3001 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
3002 | } |
3003 | ||
01a415fd DV |
3004 | static void ivb_modeset_global_resources(struct drm_device *dev) |
3005 | { | |
3006 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3007 | struct intel_crtc *pipe_B_crtc = | |
3008 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
3009 | struct intel_crtc *pipe_C_crtc = | |
3010 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
3011 | uint32_t temp; | |
3012 | ||
1e833f40 DV |
3013 | /* |
3014 | * When everything is off disable fdi C so that we could enable fdi B | |
3015 | * with all lanes. Note that we don't care about enabled pipes without | |
3016 | * an enabled pch encoder. | |
3017 | */ | |
3018 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
3019 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
3020 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
3021 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3022 | ||
3023 | temp = I915_READ(SOUTH_CHICKEN1); | |
3024 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
3025 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
3026 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3027 | } | |
3028 | } | |
3029 | ||
8db9d77b ZW |
3030 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3031 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3032 | { | |
3033 | struct drm_device *dev = crtc->dev; | |
3034 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3035 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3036 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3037 | u32 reg, temp, tries; |
8db9d77b | 3038 | |
1c8562f6 | 3039 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3040 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3041 | |
e1a44743 AJ |
3042 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3043 | for train result */ | |
5eddb70b CW |
3044 | reg = FDI_RX_IMR(pipe); |
3045 | temp = I915_READ(reg); | |
e1a44743 AJ |
3046 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3047 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3048 | I915_WRITE(reg, temp); |
3049 | I915_READ(reg); | |
e1a44743 AJ |
3050 | udelay(150); |
3051 | ||
8db9d77b | 3052 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3053 | reg = FDI_TX_CTL(pipe); |
3054 | temp = I915_READ(reg); | |
627eb5a3 DV |
3055 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3056 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
3057 | temp &= ~FDI_LINK_TRAIN_NONE; |
3058 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3059 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3060 | |
5eddb70b CW |
3061 | reg = FDI_RX_CTL(pipe); |
3062 | temp = I915_READ(reg); | |
8db9d77b ZW |
3063 | temp &= ~FDI_LINK_TRAIN_NONE; |
3064 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3065 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3066 | ||
3067 | POSTING_READ(reg); | |
8db9d77b ZW |
3068 | udelay(150); |
3069 | ||
5b2adf89 | 3070 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3071 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3072 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3073 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3074 | |
5eddb70b | 3075 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3076 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3077 | temp = I915_READ(reg); |
8db9d77b ZW |
3078 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3079 | ||
3080 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3081 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3082 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3083 | break; |
3084 | } | |
8db9d77b | 3085 | } |
e1a44743 | 3086 | if (tries == 5) |
5eddb70b | 3087 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3088 | |
3089 | /* Train 2 */ | |
5eddb70b CW |
3090 | reg = FDI_TX_CTL(pipe); |
3091 | temp = I915_READ(reg); | |
8db9d77b ZW |
3092 | temp &= ~FDI_LINK_TRAIN_NONE; |
3093 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3094 | I915_WRITE(reg, temp); |
8db9d77b | 3095 | |
5eddb70b CW |
3096 | reg = FDI_RX_CTL(pipe); |
3097 | temp = I915_READ(reg); | |
8db9d77b ZW |
3098 | temp &= ~FDI_LINK_TRAIN_NONE; |
3099 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3100 | I915_WRITE(reg, temp); |
8db9d77b | 3101 | |
5eddb70b CW |
3102 | POSTING_READ(reg); |
3103 | udelay(150); | |
8db9d77b | 3104 | |
5eddb70b | 3105 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3106 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3107 | temp = I915_READ(reg); |
8db9d77b ZW |
3108 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3109 | ||
3110 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3111 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3112 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3113 | break; | |
3114 | } | |
8db9d77b | 3115 | } |
e1a44743 | 3116 | if (tries == 5) |
5eddb70b | 3117 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3118 | |
3119 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3120 | |
8db9d77b ZW |
3121 | } |
3122 | ||
0206e353 | 3123 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3124 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3125 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3126 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3127 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3128 | }; | |
3129 | ||
3130 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3131 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3132 | { | |
3133 | struct drm_device *dev = crtc->dev; | |
3134 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3135 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3136 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3137 | u32 reg, temp, i, retry; |
8db9d77b | 3138 | |
e1a44743 AJ |
3139 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3140 | for train result */ | |
5eddb70b CW |
3141 | reg = FDI_RX_IMR(pipe); |
3142 | temp = I915_READ(reg); | |
e1a44743 AJ |
3143 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3144 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3145 | I915_WRITE(reg, temp); |
3146 | ||
3147 | POSTING_READ(reg); | |
e1a44743 AJ |
3148 | udelay(150); |
3149 | ||
8db9d77b | 3150 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3151 | reg = FDI_TX_CTL(pipe); |
3152 | temp = I915_READ(reg); | |
627eb5a3 DV |
3153 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3154 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
3155 | temp &= ~FDI_LINK_TRAIN_NONE; |
3156 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3157 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3158 | /* SNB-B */ | |
3159 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3160 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3161 | |
d74cf324 DV |
3162 | I915_WRITE(FDI_RX_MISC(pipe), |
3163 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3164 | ||
5eddb70b CW |
3165 | reg = FDI_RX_CTL(pipe); |
3166 | temp = I915_READ(reg); | |
8db9d77b ZW |
3167 | if (HAS_PCH_CPT(dev)) { |
3168 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3169 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3170 | } else { | |
3171 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3172 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3173 | } | |
5eddb70b CW |
3174 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3175 | ||
3176 | POSTING_READ(reg); | |
8db9d77b ZW |
3177 | udelay(150); |
3178 | ||
0206e353 | 3179 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3180 | reg = FDI_TX_CTL(pipe); |
3181 | temp = I915_READ(reg); | |
8db9d77b ZW |
3182 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3183 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3184 | I915_WRITE(reg, temp); |
3185 | ||
3186 | POSTING_READ(reg); | |
8db9d77b ZW |
3187 | udelay(500); |
3188 | ||
fa37d39e SP |
3189 | for (retry = 0; retry < 5; retry++) { |
3190 | reg = FDI_RX_IIR(pipe); | |
3191 | temp = I915_READ(reg); | |
3192 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3193 | if (temp & FDI_RX_BIT_LOCK) { | |
3194 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3195 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3196 | break; | |
3197 | } | |
3198 | udelay(50); | |
8db9d77b | 3199 | } |
fa37d39e SP |
3200 | if (retry < 5) |
3201 | break; | |
8db9d77b ZW |
3202 | } |
3203 | if (i == 4) | |
5eddb70b | 3204 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3205 | |
3206 | /* Train 2 */ | |
5eddb70b CW |
3207 | reg = FDI_TX_CTL(pipe); |
3208 | temp = I915_READ(reg); | |
8db9d77b ZW |
3209 | temp &= ~FDI_LINK_TRAIN_NONE; |
3210 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3211 | if (IS_GEN6(dev)) { | |
3212 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3213 | /* SNB-B */ | |
3214 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3215 | } | |
5eddb70b | 3216 | I915_WRITE(reg, temp); |
8db9d77b | 3217 | |
5eddb70b CW |
3218 | reg = FDI_RX_CTL(pipe); |
3219 | temp = I915_READ(reg); | |
8db9d77b ZW |
3220 | if (HAS_PCH_CPT(dev)) { |
3221 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3222 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3223 | } else { | |
3224 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3225 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3226 | } | |
5eddb70b CW |
3227 | I915_WRITE(reg, temp); |
3228 | ||
3229 | POSTING_READ(reg); | |
8db9d77b ZW |
3230 | udelay(150); |
3231 | ||
0206e353 | 3232 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3233 | reg = FDI_TX_CTL(pipe); |
3234 | temp = I915_READ(reg); | |
8db9d77b ZW |
3235 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3236 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3237 | I915_WRITE(reg, temp); |
3238 | ||
3239 | POSTING_READ(reg); | |
8db9d77b ZW |
3240 | udelay(500); |
3241 | ||
fa37d39e SP |
3242 | for (retry = 0; retry < 5; retry++) { |
3243 | reg = FDI_RX_IIR(pipe); | |
3244 | temp = I915_READ(reg); | |
3245 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3246 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3247 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3248 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3249 | break; | |
3250 | } | |
3251 | udelay(50); | |
8db9d77b | 3252 | } |
fa37d39e SP |
3253 | if (retry < 5) |
3254 | break; | |
8db9d77b ZW |
3255 | } |
3256 | if (i == 4) | |
5eddb70b | 3257 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3258 | |
3259 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3260 | } | |
3261 | ||
357555c0 JB |
3262 | /* Manual link training for Ivy Bridge A0 parts */ |
3263 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3264 | { | |
3265 | struct drm_device *dev = crtc->dev; | |
3266 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3267 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3268 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3269 | u32 reg, temp, i, j; |
357555c0 JB |
3270 | |
3271 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3272 | for train result */ | |
3273 | reg = FDI_RX_IMR(pipe); | |
3274 | temp = I915_READ(reg); | |
3275 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3276 | temp &= ~FDI_RX_BIT_LOCK; | |
3277 | I915_WRITE(reg, temp); | |
3278 | ||
3279 | POSTING_READ(reg); | |
3280 | udelay(150); | |
3281 | ||
01a415fd DV |
3282 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3283 | I915_READ(FDI_RX_IIR(pipe))); | |
3284 | ||
139ccd3f JB |
3285 | /* Try each vswing and preemphasis setting twice before moving on */ |
3286 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3287 | /* disable first in case we need to retry */ | |
3288 | reg = FDI_TX_CTL(pipe); | |
3289 | temp = I915_READ(reg); | |
3290 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3291 | temp &= ~FDI_TX_ENABLE; | |
3292 | I915_WRITE(reg, temp); | |
357555c0 | 3293 | |
139ccd3f JB |
3294 | reg = FDI_RX_CTL(pipe); |
3295 | temp = I915_READ(reg); | |
3296 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3297 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3298 | temp &= ~FDI_RX_ENABLE; | |
3299 | I915_WRITE(reg, temp); | |
357555c0 | 3300 | |
139ccd3f | 3301 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3302 | reg = FDI_TX_CTL(pipe); |
3303 | temp = I915_READ(reg); | |
139ccd3f JB |
3304 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3305 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
3306 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 3307 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3308 | temp |= snb_b_fdi_train_param[j/2]; |
3309 | temp |= FDI_COMPOSITE_SYNC; | |
3310 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3311 | |
139ccd3f JB |
3312 | I915_WRITE(FDI_RX_MISC(pipe), |
3313 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3314 | |
139ccd3f | 3315 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3316 | temp = I915_READ(reg); |
139ccd3f JB |
3317 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3318 | temp |= FDI_COMPOSITE_SYNC; | |
3319 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3320 | |
139ccd3f JB |
3321 | POSTING_READ(reg); |
3322 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3323 | |
139ccd3f JB |
3324 | for (i = 0; i < 4; i++) { |
3325 | reg = FDI_RX_IIR(pipe); | |
3326 | temp = I915_READ(reg); | |
3327 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3328 | |
139ccd3f JB |
3329 | if (temp & FDI_RX_BIT_LOCK || |
3330 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3331 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3332 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3333 | i); | |
3334 | break; | |
3335 | } | |
3336 | udelay(1); /* should be 0.5us */ | |
3337 | } | |
3338 | if (i == 4) { | |
3339 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3340 | continue; | |
3341 | } | |
357555c0 | 3342 | |
139ccd3f | 3343 | /* Train 2 */ |
357555c0 JB |
3344 | reg = FDI_TX_CTL(pipe); |
3345 | temp = I915_READ(reg); | |
139ccd3f JB |
3346 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3347 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3348 | I915_WRITE(reg, temp); | |
3349 | ||
3350 | reg = FDI_RX_CTL(pipe); | |
3351 | temp = I915_READ(reg); | |
3352 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3353 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3354 | I915_WRITE(reg, temp); |
3355 | ||
3356 | POSTING_READ(reg); | |
139ccd3f | 3357 | udelay(2); /* should be 1.5us */ |
357555c0 | 3358 | |
139ccd3f JB |
3359 | for (i = 0; i < 4; i++) { |
3360 | reg = FDI_RX_IIR(pipe); | |
3361 | temp = I915_READ(reg); | |
3362 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3363 | |
139ccd3f JB |
3364 | if (temp & FDI_RX_SYMBOL_LOCK || |
3365 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3366 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3367 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3368 | i); | |
3369 | goto train_done; | |
3370 | } | |
3371 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3372 | } |
139ccd3f JB |
3373 | if (i == 4) |
3374 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3375 | } |
357555c0 | 3376 | |
139ccd3f | 3377 | train_done: |
357555c0 JB |
3378 | DRM_DEBUG_KMS("FDI train done.\n"); |
3379 | } | |
3380 | ||
88cefb6c | 3381 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3382 | { |
88cefb6c | 3383 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3384 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3385 | int pipe = intel_crtc->pipe; |
5eddb70b | 3386 | u32 reg, temp; |
79e53945 | 3387 | |
c64e311e | 3388 | |
c98e9dcf | 3389 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3390 | reg = FDI_RX_CTL(pipe); |
3391 | temp = I915_READ(reg); | |
627eb5a3 DV |
3392 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
3393 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 3394 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3395 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3396 | ||
3397 | POSTING_READ(reg); | |
c98e9dcf JB |
3398 | udelay(200); |
3399 | ||
3400 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3401 | temp = I915_READ(reg); |
3402 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3403 | ||
3404 | POSTING_READ(reg); | |
c98e9dcf JB |
3405 | udelay(200); |
3406 | ||
20749730 PZ |
3407 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3408 | reg = FDI_TX_CTL(pipe); | |
3409 | temp = I915_READ(reg); | |
3410 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3411 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3412 | |
20749730 PZ |
3413 | POSTING_READ(reg); |
3414 | udelay(100); | |
6be4a607 | 3415 | } |
0e23b99d JB |
3416 | } |
3417 | ||
88cefb6c DV |
3418 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3419 | { | |
3420 | struct drm_device *dev = intel_crtc->base.dev; | |
3421 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3422 | int pipe = intel_crtc->pipe; | |
3423 | u32 reg, temp; | |
3424 | ||
3425 | /* Switch from PCDclk to Rawclk */ | |
3426 | reg = FDI_RX_CTL(pipe); | |
3427 | temp = I915_READ(reg); | |
3428 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3429 | ||
3430 | /* Disable CPU FDI TX PLL */ | |
3431 | reg = FDI_TX_CTL(pipe); | |
3432 | temp = I915_READ(reg); | |
3433 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3434 | ||
3435 | POSTING_READ(reg); | |
3436 | udelay(100); | |
3437 | ||
3438 | reg = FDI_RX_CTL(pipe); | |
3439 | temp = I915_READ(reg); | |
3440 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3441 | ||
3442 | /* Wait for the clocks to turn off. */ | |
3443 | POSTING_READ(reg); | |
3444 | udelay(100); | |
3445 | } | |
3446 | ||
0fc932b8 JB |
3447 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3448 | { | |
3449 | struct drm_device *dev = crtc->dev; | |
3450 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3451 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3452 | int pipe = intel_crtc->pipe; | |
3453 | u32 reg, temp; | |
3454 | ||
3455 | /* disable CPU FDI tx and PCH FDI rx */ | |
3456 | reg = FDI_TX_CTL(pipe); | |
3457 | temp = I915_READ(reg); | |
3458 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3459 | POSTING_READ(reg); | |
3460 | ||
3461 | reg = FDI_RX_CTL(pipe); | |
3462 | temp = I915_READ(reg); | |
3463 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3464 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3465 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3466 | ||
3467 | POSTING_READ(reg); | |
3468 | udelay(100); | |
3469 | ||
3470 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3471 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3472 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3473 | |
3474 | /* still set train pattern 1 */ | |
3475 | reg = FDI_TX_CTL(pipe); | |
3476 | temp = I915_READ(reg); | |
3477 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3478 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3479 | I915_WRITE(reg, temp); | |
3480 | ||
3481 | reg = FDI_RX_CTL(pipe); | |
3482 | temp = I915_READ(reg); | |
3483 | if (HAS_PCH_CPT(dev)) { | |
3484 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3485 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3486 | } else { | |
3487 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3488 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3489 | } | |
3490 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3491 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3492 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3493 | I915_WRITE(reg, temp); |
3494 | ||
3495 | POSTING_READ(reg); | |
3496 | udelay(100); | |
3497 | } | |
3498 | ||
5dce5b93 CW |
3499 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3500 | { | |
3501 | struct intel_crtc *crtc; | |
3502 | ||
3503 | /* Note that we don't need to be called with mode_config.lock here | |
3504 | * as our list of CRTC objects is static for the lifetime of the | |
3505 | * device and so cannot disappear as we iterate. Similarly, we can | |
3506 | * happily treat the predicates as racy, atomic checks as userspace | |
3507 | * cannot claim and pin a new fb without at least acquring the | |
3508 | * struct_mutex and so serialising with us. | |
3509 | */ | |
d3fcc808 | 3510 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3511 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3512 | continue; | |
3513 | ||
3514 | if (crtc->unpin_work) | |
3515 | intel_wait_for_vblank(dev, crtc->pipe); | |
3516 | ||
3517 | return true; | |
3518 | } | |
3519 | ||
3520 | return false; | |
3521 | } | |
3522 | ||
d6bbafa1 CW |
3523 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3524 | { | |
3525 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3526 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3527 | ||
3528 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3529 | smp_rmb(); | |
3530 | intel_crtc->unpin_work = NULL; | |
3531 | ||
3532 | if (work->event) | |
3533 | drm_send_vblank_event(intel_crtc->base.dev, | |
3534 | intel_crtc->pipe, | |
3535 | work->event); | |
3536 | ||
3537 | drm_crtc_vblank_put(&intel_crtc->base); | |
3538 | ||
3539 | wake_up_all(&dev_priv->pending_flip_queue); | |
3540 | queue_work(dev_priv->wq, &work->work); | |
3541 | ||
3542 | trace_i915_flip_complete(intel_crtc->plane, | |
3543 | work->pending_flip_obj); | |
3544 | } | |
3545 | ||
46a55d30 | 3546 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3547 | { |
0f91128d | 3548 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3549 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3550 | |
2c10d571 | 3551 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3552 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3553 | !intel_crtc_has_pending_flip(crtc), | |
3554 | 60*HZ) == 0)) { | |
3555 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3556 | |
5e2d7afc | 3557 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3558 | if (intel_crtc->unpin_work) { |
3559 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3560 | page_flip_completed(intel_crtc); | |
3561 | } | |
5e2d7afc | 3562 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3563 | } |
5bb61643 | 3564 | |
975d568a CW |
3565 | if (crtc->primary->fb) { |
3566 | mutex_lock(&dev->struct_mutex); | |
3567 | intel_finish_fb(crtc->primary->fb); | |
3568 | mutex_unlock(&dev->struct_mutex); | |
3569 | } | |
e6c3a2a6 CW |
3570 | } |
3571 | ||
e615efe4 ED |
3572 | /* Program iCLKIP clock to the desired frequency */ |
3573 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3574 | { | |
3575 | struct drm_device *dev = crtc->dev; | |
3576 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 3577 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
3578 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3579 | u32 temp; | |
3580 | ||
09153000 DV |
3581 | mutex_lock(&dev_priv->dpio_lock); |
3582 | ||
e615efe4 ED |
3583 | /* It is necessary to ungate the pixclk gate prior to programming |
3584 | * the divisors, and gate it back when it is done. | |
3585 | */ | |
3586 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3587 | ||
3588 | /* Disable SSCCTL */ | |
3589 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3590 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3591 | SBI_SSCCTL_DISABLE, | |
3592 | SBI_ICLK); | |
e615efe4 ED |
3593 | |
3594 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3595 | if (clock == 20000) { |
e615efe4 ED |
3596 | auxdiv = 1; |
3597 | divsel = 0x41; | |
3598 | phaseinc = 0x20; | |
3599 | } else { | |
3600 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3601 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3602 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3603 | * convert the virtual clock precision to KHz here for higher |
3604 | * precision. | |
3605 | */ | |
3606 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3607 | u32 iclk_pi_range = 64; | |
3608 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3609 | ||
12d7ceed | 3610 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3611 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3612 | pi_value = desired_divisor % iclk_pi_range; | |
3613 | ||
3614 | auxdiv = 0; | |
3615 | divsel = msb_divisor_value - 2; | |
3616 | phaseinc = pi_value; | |
3617 | } | |
3618 | ||
3619 | /* This should not happen with any sane values */ | |
3620 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3621 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3622 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3623 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3624 | ||
3625 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3626 | clock, |
e615efe4 ED |
3627 | auxdiv, |
3628 | divsel, | |
3629 | phasedir, | |
3630 | phaseinc); | |
3631 | ||
3632 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3633 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3634 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3635 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3636 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3637 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3638 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3639 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3640 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3641 | |
3642 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3643 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3644 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3645 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3646 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3647 | |
3648 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3649 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3650 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3651 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3652 | |
3653 | /* Wait for initialization time */ | |
3654 | udelay(24); | |
3655 | ||
3656 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3657 | |
3658 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3659 | } |
3660 | ||
275f01b2 DV |
3661 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3662 | enum pipe pch_transcoder) | |
3663 | { | |
3664 | struct drm_device *dev = crtc->base.dev; | |
3665 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3666 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3667 | ||
3668 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3669 | I915_READ(HTOTAL(cpu_transcoder))); | |
3670 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3671 | I915_READ(HBLANK(cpu_transcoder))); | |
3672 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3673 | I915_READ(HSYNC(cpu_transcoder))); | |
3674 | ||
3675 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3676 | I915_READ(VTOTAL(cpu_transcoder))); | |
3677 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3678 | I915_READ(VBLANK(cpu_transcoder))); | |
3679 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3680 | I915_READ(VSYNC(cpu_transcoder))); | |
3681 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3682 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3683 | } | |
3684 | ||
1fbc0d78 DV |
3685 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3686 | { | |
3687 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3688 | uint32_t temp; | |
3689 | ||
3690 | temp = I915_READ(SOUTH_CHICKEN1); | |
3691 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3692 | return; | |
3693 | ||
3694 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3695 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3696 | ||
3697 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3698 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3699 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3700 | POSTING_READ(SOUTH_CHICKEN1); | |
3701 | } | |
3702 | ||
3703 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3704 | { | |
3705 | struct drm_device *dev = intel_crtc->base.dev; | |
3706 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3707 | ||
3708 | switch (intel_crtc->pipe) { | |
3709 | case PIPE_A: | |
3710 | break; | |
3711 | case PIPE_B: | |
3712 | if (intel_crtc->config.fdi_lanes > 2) | |
3713 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3714 | else | |
3715 | cpt_enable_fdi_bc_bifurcation(dev); | |
3716 | ||
3717 | break; | |
3718 | case PIPE_C: | |
3719 | cpt_enable_fdi_bc_bifurcation(dev); | |
3720 | ||
3721 | break; | |
3722 | default: | |
3723 | BUG(); | |
3724 | } | |
3725 | } | |
3726 | ||
f67a559d JB |
3727 | /* |
3728 | * Enable PCH resources required for PCH ports: | |
3729 | * - PCH PLLs | |
3730 | * - FDI training & RX/TX | |
3731 | * - update transcoder timings | |
3732 | * - DP transcoding bits | |
3733 | * - transcoder | |
3734 | */ | |
3735 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3736 | { |
3737 | struct drm_device *dev = crtc->dev; | |
3738 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3739 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3740 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3741 | u32 reg, temp; |
2c07245f | 3742 | |
ab9412ba | 3743 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3744 | |
1fbc0d78 DV |
3745 | if (IS_IVYBRIDGE(dev)) |
3746 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3747 | ||
cd986abb DV |
3748 | /* Write the TU size bits before fdi link training, so that error |
3749 | * detection works. */ | |
3750 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3751 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3752 | ||
c98e9dcf | 3753 | /* For PCH output, training FDI link */ |
674cf967 | 3754 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3755 | |
3ad8a208 DV |
3756 | /* We need to program the right clock selection before writing the pixel |
3757 | * mutliplier into the DPLL. */ | |
303b81e0 | 3758 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3759 | u32 sel; |
4b645f14 | 3760 | |
c98e9dcf | 3761 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3762 | temp |= TRANS_DPLL_ENABLE(pipe); |
3763 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3764 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3765 | temp |= sel; |
3766 | else | |
3767 | temp &= ~sel; | |
c98e9dcf | 3768 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3769 | } |
5eddb70b | 3770 | |
3ad8a208 DV |
3771 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3772 | * transcoder, and we actually should do this to not upset any PCH | |
3773 | * transcoder that already use the clock when we share it. | |
3774 | * | |
3775 | * Note that enable_shared_dpll tries to do the right thing, but | |
3776 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3777 | * the right LVDS enable sequence. */ | |
85b3894f | 3778 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 3779 | |
d9b6cb56 JB |
3780 | /* set transcoder timing, panel must allow it */ |
3781 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3782 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3783 | |
303b81e0 | 3784 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3785 | |
c98e9dcf | 3786 | /* For PCH DP, enable TRANS_DP_CTL */ |
0a88818d | 3787 | if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) { |
dfd07d72 | 3788 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3789 | reg = TRANS_DP_CTL(pipe); |
3790 | temp = I915_READ(reg); | |
3791 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3792 | TRANS_DP_SYNC_MASK | |
3793 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3794 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3795 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3796 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3797 | |
3798 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3799 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3800 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3801 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3802 | |
3803 | switch (intel_trans_dp_port_sel(crtc)) { | |
3804 | case PCH_DP_B: | |
5eddb70b | 3805 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3806 | break; |
3807 | case PCH_DP_C: | |
5eddb70b | 3808 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3809 | break; |
3810 | case PCH_DP_D: | |
5eddb70b | 3811 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3812 | break; |
3813 | default: | |
e95d41e1 | 3814 | BUG(); |
32f9d658 | 3815 | } |
2c07245f | 3816 | |
5eddb70b | 3817 | I915_WRITE(reg, temp); |
6be4a607 | 3818 | } |
b52eb4dc | 3819 | |
b8a4f404 | 3820 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3821 | } |
3822 | ||
1507e5bd PZ |
3823 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3824 | { | |
3825 | struct drm_device *dev = crtc->dev; | |
3826 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3827 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3828 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3829 | |
ab9412ba | 3830 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3831 | |
8c52b5e8 | 3832 | lpt_program_iclkip(crtc); |
1507e5bd | 3833 | |
0540e488 | 3834 | /* Set transcoder timing. */ |
275f01b2 | 3835 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3836 | |
937bb610 | 3837 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3838 | } |
3839 | ||
716c2e55 | 3840 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3841 | { |
e2b78267 | 3842 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3843 | |
3844 | if (pll == NULL) | |
3845 | return; | |
3846 | ||
3e369b76 | 3847 | if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { |
1e6f2ddc | 3848 | WARN(1, "bad %s crtc mask\n", pll->name); |
ee7b9f93 JB |
3849 | return; |
3850 | } | |
3851 | ||
3e369b76 ACO |
3852 | pll->config.crtc_mask &= ~(1 << crtc->pipe); |
3853 | if (pll->config.crtc_mask == 0) { | |
f4a091c7 DV |
3854 | WARN_ON(pll->on); |
3855 | WARN_ON(pll->active); | |
3856 | } | |
3857 | ||
a43f6e0f | 3858 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3859 | } |
3860 | ||
716c2e55 | 3861 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3862 | { |
e2b78267 | 3863 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 3864 | struct intel_shared_dpll *pll; |
e2b78267 | 3865 | enum intel_dpll_id i; |
ee7b9f93 | 3866 | |
98b6bd99 DV |
3867 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3868 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3869 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3870 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3871 | |
46edb027 DV |
3872 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3873 | crtc->base.base.id, pll->name); | |
98b6bd99 | 3874 | |
8bd31e67 | 3875 | WARN_ON(pll->new_config->crtc_mask); |
f2a69f44 | 3876 | |
98b6bd99 DV |
3877 | goto found; |
3878 | } | |
3879 | ||
e72f9fbf DV |
3880 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3881 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3882 | |
3883 | /* Only want to check enabled timings first */ | |
8bd31e67 | 3884 | if (pll->new_config->crtc_mask == 0) |
ee7b9f93 JB |
3885 | continue; |
3886 | ||
8bd31e67 ACO |
3887 | if (memcmp(&crtc->new_config->dpll_hw_state, |
3888 | &pll->new_config->hw_state, | |
3889 | sizeof(pll->new_config->hw_state)) == 0) { | |
3890 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", | |
1e6f2ddc | 3891 | crtc->base.base.id, pll->name, |
8bd31e67 ACO |
3892 | pll->new_config->crtc_mask, |
3893 | pll->active); | |
ee7b9f93 JB |
3894 | goto found; |
3895 | } | |
3896 | } | |
3897 | ||
3898 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3899 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3900 | pll = &dev_priv->shared_dplls[i]; | |
8bd31e67 | 3901 | if (pll->new_config->crtc_mask == 0) { |
46edb027 DV |
3902 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3903 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3904 | goto found; |
3905 | } | |
3906 | } | |
3907 | ||
3908 | return NULL; | |
3909 | ||
3910 | found: | |
8bd31e67 ACO |
3911 | if (pll->new_config->crtc_mask == 0) |
3912 | pll->new_config->hw_state = crtc->new_config->dpll_hw_state; | |
f2a69f44 | 3913 | |
8bd31e67 | 3914 | crtc->new_config->shared_dpll = i; |
46edb027 DV |
3915 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3916 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3917 | |
8bd31e67 | 3918 | pll->new_config->crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 3919 | |
ee7b9f93 JB |
3920 | return pll; |
3921 | } | |
3922 | ||
8bd31e67 ACO |
3923 | /** |
3924 | * intel_shared_dpll_start_config - start a new PLL staged config | |
3925 | * @dev_priv: DRM device | |
3926 | * @clear_pipes: mask of pipes that will have their PLLs freed | |
3927 | * | |
3928 | * Starts a new PLL staged config, copying the current config but | |
3929 | * releasing the references of pipes specified in clear_pipes. | |
3930 | */ | |
3931 | static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv, | |
3932 | unsigned clear_pipes) | |
3933 | { | |
3934 | struct intel_shared_dpll *pll; | |
3935 | enum intel_dpll_id i; | |
3936 | ||
3937 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3938 | pll = &dev_priv->shared_dplls[i]; | |
3939 | ||
3940 | pll->new_config = kmemdup(&pll->config, sizeof pll->config, | |
3941 | GFP_KERNEL); | |
3942 | if (!pll->new_config) | |
3943 | goto cleanup; | |
3944 | ||
3945 | pll->new_config->crtc_mask &= ~clear_pipes; | |
3946 | } | |
3947 | ||
3948 | return 0; | |
3949 | ||
3950 | cleanup: | |
3951 | while (--i >= 0) { | |
3952 | pll = &dev_priv->shared_dplls[i]; | |
f354d733 | 3953 | kfree(pll->new_config); |
8bd31e67 ACO |
3954 | pll->new_config = NULL; |
3955 | } | |
3956 | ||
3957 | return -ENOMEM; | |
3958 | } | |
3959 | ||
3960 | static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv) | |
3961 | { | |
3962 | struct intel_shared_dpll *pll; | |
3963 | enum intel_dpll_id i; | |
3964 | ||
3965 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3966 | pll = &dev_priv->shared_dplls[i]; | |
3967 | ||
3968 | WARN_ON(pll->new_config == &pll->config); | |
3969 | ||
3970 | pll->config = *pll->new_config; | |
3971 | kfree(pll->new_config); | |
3972 | pll->new_config = NULL; | |
3973 | } | |
3974 | } | |
3975 | ||
3976 | static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv) | |
3977 | { | |
3978 | struct intel_shared_dpll *pll; | |
3979 | enum intel_dpll_id i; | |
3980 | ||
3981 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
3982 | pll = &dev_priv->shared_dplls[i]; | |
3983 | ||
3984 | WARN_ON(pll->new_config == &pll->config); | |
3985 | ||
3986 | kfree(pll->new_config); | |
3987 | pll->new_config = NULL; | |
3988 | } | |
3989 | } | |
3990 | ||
a1520318 | 3991 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3992 | { |
3993 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3994 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3995 | u32 temp; |
3996 | ||
3997 | temp = I915_READ(dslreg); | |
3998 | udelay(500); | |
3999 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4000 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4001 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4002 | } |
4003 | } | |
4004 | ||
bd2e244f JB |
4005 | static void skylake_pfit_enable(struct intel_crtc *crtc) |
4006 | { | |
4007 | struct drm_device *dev = crtc->base.dev; | |
4008 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4009 | int pipe = crtc->pipe; | |
4010 | ||
4011 | if (crtc->config.pch_pfit.enabled) { | |
4012 | I915_WRITE(PS_CTL(pipe), PS_ENABLE); | |
4013 | I915_WRITE(PS_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
4014 | I915_WRITE(PS_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
4015 | } | |
4016 | } | |
4017 | ||
b074cec8 JB |
4018 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4019 | { | |
4020 | struct drm_device *dev = crtc->base.dev; | |
4021 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4022 | int pipe = crtc->pipe; | |
4023 | ||
fd4daa9c | 4024 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
4025 | /* Force use of hard-coded filter coefficients |
4026 | * as some pre-programmed values are broken, | |
4027 | * e.g. x201. | |
4028 | */ | |
4029 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4030 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4031 | PF_PIPE_SEL_IVB(pipe)); | |
4032 | else | |
4033 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
4034 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
4035 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
4036 | } |
4037 | } | |
4038 | ||
bb53d4ae VS |
4039 | static void intel_enable_planes(struct drm_crtc *crtc) |
4040 | { | |
4041 | struct drm_device *dev = crtc->dev; | |
4042 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4043 | struct drm_plane *plane; |
bb53d4ae VS |
4044 | struct intel_plane *intel_plane; |
4045 | ||
af2b653b MR |
4046 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4047 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
4048 | if (intel_plane->pipe == pipe) |
4049 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 4050 | } |
bb53d4ae VS |
4051 | } |
4052 | ||
4053 | static void intel_disable_planes(struct drm_crtc *crtc) | |
4054 | { | |
4055 | struct drm_device *dev = crtc->dev; | |
4056 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4057 | struct drm_plane *plane; |
bb53d4ae VS |
4058 | struct intel_plane *intel_plane; |
4059 | ||
af2b653b MR |
4060 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4061 | intel_plane = to_intel_plane(plane); | |
bb53d4ae | 4062 | if (intel_plane->pipe == pipe) |
cf4c7c12 | 4063 | plane->funcs->disable_plane(plane); |
af2b653b | 4064 | } |
bb53d4ae VS |
4065 | } |
4066 | ||
20bc8673 | 4067 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4068 | { |
cea165c3 VS |
4069 | struct drm_device *dev = crtc->base.dev; |
4070 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 PZ |
4071 | |
4072 | if (!crtc->config.ips_enabled) | |
4073 | return; | |
4074 | ||
cea165c3 VS |
4075 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4076 | intel_wait_for_vblank(dev, crtc->pipe); | |
4077 | ||
d77e4531 | 4078 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4079 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4080 | mutex_lock(&dev_priv->rps.hw_lock); |
4081 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4082 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4083 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4084 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4085 | * mailbox." Moreover, the mailbox may return a bogus state, |
4086 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4087 | */ |
4088 | } else { | |
4089 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4090 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4091 | * is essentially intel_wait_for_vblank. If we don't have this | |
4092 | * and don't wait for vblanks until the end of crtc_enable, then | |
4093 | * the HW state readout code will complain that the expected | |
4094 | * IPS_CTL value is not the one we read. */ | |
4095 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4096 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4097 | } | |
d77e4531 PZ |
4098 | } |
4099 | ||
20bc8673 | 4100 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4101 | { |
4102 | struct drm_device *dev = crtc->base.dev; | |
4103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4104 | ||
4105 | if (!crtc->config.ips_enabled) | |
4106 | return; | |
4107 | ||
4108 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4109 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4110 | mutex_lock(&dev_priv->rps.hw_lock); |
4111 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4112 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4113 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4114 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4115 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4116 | } else { |
2a114cc1 | 4117 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4118 | POSTING_READ(IPS_CTL); |
4119 | } | |
d77e4531 PZ |
4120 | |
4121 | /* We need to wait for a vblank before we can disable the plane. */ | |
4122 | intel_wait_for_vblank(dev, crtc->pipe); | |
4123 | } | |
4124 | ||
4125 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4126 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4127 | { | |
4128 | struct drm_device *dev = crtc->dev; | |
4129 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4130 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4131 | enum pipe pipe = intel_crtc->pipe; | |
4132 | int palreg = PALETTE(pipe); | |
4133 | int i; | |
4134 | bool reenable_ips = false; | |
4135 | ||
4136 | /* The clocks have to be on to load the palette. */ | |
4137 | if (!crtc->enabled || !intel_crtc->active) | |
4138 | return; | |
4139 | ||
4140 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
409ee761 | 4141 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4142 | assert_dsi_pll_enabled(dev_priv); |
4143 | else | |
4144 | assert_pll_enabled(dev_priv, pipe); | |
4145 | } | |
4146 | ||
4147 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4148 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4149 | palreg = LGC_PALETTE(pipe); |
4150 | ||
4151 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4152 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4153 | */ | |
41e6fc4c | 4154 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
d77e4531 PZ |
4155 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4156 | GAMMA_MODE_MODE_SPLIT)) { | |
4157 | hsw_disable_ips(intel_crtc); | |
4158 | reenable_ips = true; | |
4159 | } | |
4160 | ||
4161 | for (i = 0; i < 256; i++) { | |
4162 | I915_WRITE(palreg + 4 * i, | |
4163 | (intel_crtc->lut_r[i] << 16) | | |
4164 | (intel_crtc->lut_g[i] << 8) | | |
4165 | intel_crtc->lut_b[i]); | |
4166 | } | |
4167 | ||
4168 | if (reenable_ips) | |
4169 | hsw_enable_ips(intel_crtc); | |
4170 | } | |
4171 | ||
d3eedb1a VS |
4172 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
4173 | { | |
4174 | if (!enable && intel_crtc->overlay) { | |
4175 | struct drm_device *dev = intel_crtc->base.dev; | |
4176 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4177 | ||
4178 | mutex_lock(&dev->struct_mutex); | |
4179 | dev_priv->mm.interruptible = false; | |
4180 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4181 | dev_priv->mm.interruptible = true; | |
4182 | mutex_unlock(&dev->struct_mutex); | |
4183 | } | |
4184 | ||
4185 | /* Let userspace switch the overlay on again. In most cases userspace | |
4186 | * has to recompute where to put it anyway. | |
4187 | */ | |
4188 | } | |
4189 | ||
d3eedb1a | 4190 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4191 | { |
4192 | struct drm_device *dev = crtc->dev; | |
a5c4d7bc VS |
4193 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4194 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4195 | |
fdd508a6 | 4196 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
a5c4d7bc VS |
4197 | intel_enable_planes(crtc); |
4198 | intel_crtc_update_cursor(crtc, true); | |
d3eedb1a | 4199 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
4200 | |
4201 | hsw_enable_ips(intel_crtc); | |
4202 | ||
4203 | mutex_lock(&dev->struct_mutex); | |
4204 | intel_update_fbc(dev); | |
4205 | mutex_unlock(&dev->struct_mutex); | |
f99d7069 DV |
4206 | |
4207 | /* | |
4208 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4209 | * to compute the mask of flip planes precisely. For the time being | |
4210 | * consider this a flip from a NULL plane. | |
4211 | */ | |
4212 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4213 | } |
4214 | ||
d3eedb1a | 4215 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4216 | { |
4217 | struct drm_device *dev = crtc->dev; | |
4218 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4219 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4220 | int pipe = intel_crtc->pipe; | |
4221 | int plane = intel_crtc->plane; | |
4222 | ||
4223 | intel_crtc_wait_for_pending_flips(crtc); | |
a5c4d7bc VS |
4224 | |
4225 | if (dev_priv->fbc.plane == plane) | |
4226 | intel_disable_fbc(dev); | |
4227 | ||
4228 | hsw_disable_ips(intel_crtc); | |
4229 | ||
d3eedb1a | 4230 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc VS |
4231 | intel_crtc_update_cursor(crtc, false); |
4232 | intel_disable_planes(crtc); | |
fdd508a6 | 4233 | intel_disable_primary_hw_plane(crtc->primary, crtc); |
f98551ae | 4234 | |
f99d7069 DV |
4235 | /* |
4236 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4237 | * to compute the mask of flip planes precisely. For the time being | |
4238 | * consider this a flip to a NULL plane. | |
4239 | */ | |
4240 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4241 | } |
4242 | ||
f67a559d JB |
4243 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4244 | { | |
4245 | struct drm_device *dev = crtc->dev; | |
4246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4247 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4248 | struct intel_encoder *encoder; |
f67a559d | 4249 | int pipe = intel_crtc->pipe; |
f67a559d | 4250 | |
08a48469 DV |
4251 | WARN_ON(!crtc->enabled); |
4252 | ||
f67a559d JB |
4253 | if (intel_crtc->active) |
4254 | return; | |
4255 | ||
b14b1055 DV |
4256 | if (intel_crtc->config.has_pch_encoder) |
4257 | intel_prepare_shared_dpll(intel_crtc); | |
4258 | ||
29407aab DV |
4259 | if (intel_crtc->config.has_dp_encoder) |
4260 | intel_dp_set_m_n(intel_crtc); | |
4261 | ||
4262 | intel_set_pipe_timings(intel_crtc); | |
4263 | ||
4264 | if (intel_crtc->config.has_pch_encoder) { | |
4265 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
f769cd24 | 4266 | &intel_crtc->config.fdi_m_n, NULL); |
29407aab DV |
4267 | } |
4268 | ||
4269 | ironlake_set_pipeconf(crtc); | |
4270 | ||
f67a559d | 4271 | intel_crtc->active = true; |
8664281b | 4272 | |
a72e4c9f DV |
4273 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4274 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4275 | |
f6736a1a | 4276 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4277 | if (encoder->pre_enable) |
4278 | encoder->pre_enable(encoder); | |
f67a559d | 4279 | |
5bfe2ac0 | 4280 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
4281 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4282 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4283 | * enabling. */ | |
88cefb6c | 4284 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4285 | } else { |
4286 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4287 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4288 | } | |
f67a559d | 4289 | |
b074cec8 | 4290 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4291 | |
9c54c0dd JB |
4292 | /* |
4293 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4294 | * clocks enabled | |
4295 | */ | |
4296 | intel_crtc_load_lut(crtc); | |
4297 | ||
f37fcc2a | 4298 | intel_update_watermarks(crtc); |
e1fdc473 | 4299 | intel_enable_pipe(intel_crtc); |
f67a559d | 4300 | |
5bfe2ac0 | 4301 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 4302 | ironlake_pch_enable(crtc); |
c98e9dcf | 4303 | |
fa5c73b1 DV |
4304 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4305 | encoder->enable(encoder); | |
61b77ddd DV |
4306 | |
4307 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4308 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4309 | |
4b3a9526 VS |
4310 | assert_vblank_disabled(crtc); |
4311 | drm_crtc_vblank_on(crtc); | |
4312 | ||
d3eedb1a | 4313 | intel_crtc_enable_planes(crtc); |
6be4a607 JB |
4314 | } |
4315 | ||
42db64ef PZ |
4316 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4317 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4318 | { | |
f5adf94e | 4319 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4320 | } |
4321 | ||
e4916946 PZ |
4322 | /* |
4323 | * This implements the workaround described in the "notes" section of the mode | |
4324 | * set sequence documentation. When going from no pipes or single pipe to | |
4325 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4326 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4327 | */ | |
4328 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4329 | { | |
4330 | struct drm_device *dev = crtc->base.dev; | |
4331 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4332 | ||
4333 | /* We want to get the other_active_crtc only if there's only 1 other | |
4334 | * active crtc. */ | |
d3fcc808 | 4335 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4336 | if (!crtc_it->active || crtc_it == crtc) |
4337 | continue; | |
4338 | ||
4339 | if (other_active_crtc) | |
4340 | return; | |
4341 | ||
4342 | other_active_crtc = crtc_it; | |
4343 | } | |
4344 | if (!other_active_crtc) | |
4345 | return; | |
4346 | ||
4347 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4348 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4349 | } | |
4350 | ||
4f771f10 PZ |
4351 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4352 | { | |
4353 | struct drm_device *dev = crtc->dev; | |
4354 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4355 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4356 | struct intel_encoder *encoder; | |
4357 | int pipe = intel_crtc->pipe; | |
4f771f10 PZ |
4358 | |
4359 | WARN_ON(!crtc->enabled); | |
4360 | ||
4361 | if (intel_crtc->active) | |
4362 | return; | |
4363 | ||
df8ad70c DV |
4364 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4365 | intel_enable_shared_dpll(intel_crtc); | |
4366 | ||
229fca97 DV |
4367 | if (intel_crtc->config.has_dp_encoder) |
4368 | intel_dp_set_m_n(intel_crtc); | |
4369 | ||
4370 | intel_set_pipe_timings(intel_crtc); | |
4371 | ||
ebb69c95 CT |
4372 | if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) { |
4373 | I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder), | |
4374 | intel_crtc->config.pixel_multiplier - 1); | |
4375 | } | |
4376 | ||
229fca97 DV |
4377 | if (intel_crtc->config.has_pch_encoder) { |
4378 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
f769cd24 | 4379 | &intel_crtc->config.fdi_m_n, NULL); |
229fca97 DV |
4380 | } |
4381 | ||
4382 | haswell_set_pipeconf(crtc); | |
4383 | ||
4384 | intel_set_pipe_csc(crtc); | |
4385 | ||
4f771f10 | 4386 | intel_crtc->active = true; |
8664281b | 4387 | |
a72e4c9f | 4388 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
4389 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4390 | if (encoder->pre_enable) | |
4391 | encoder->pre_enable(encoder); | |
4392 | ||
4fe9467d | 4393 | if (intel_crtc->config.has_pch_encoder) { |
a72e4c9f DV |
4394 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4395 | true); | |
4fe9467d ID |
4396 | dev_priv->display.fdi_link_train(crtc); |
4397 | } | |
4398 | ||
1f544388 | 4399 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4400 | |
bd2e244f JB |
4401 | if (IS_SKYLAKE(dev)) |
4402 | skylake_pfit_enable(intel_crtc); | |
4403 | else | |
4404 | ironlake_pfit_enable(intel_crtc); | |
4f771f10 PZ |
4405 | |
4406 | /* | |
4407 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4408 | * clocks enabled | |
4409 | */ | |
4410 | intel_crtc_load_lut(crtc); | |
4411 | ||
1f544388 | 4412 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4413 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4414 | |
f37fcc2a | 4415 | intel_update_watermarks(crtc); |
e1fdc473 | 4416 | intel_enable_pipe(intel_crtc); |
42db64ef | 4417 | |
5bfe2ac0 | 4418 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 4419 | lpt_pch_enable(crtc); |
4f771f10 | 4420 | |
0e32b39c DA |
4421 | if (intel_crtc->config.dp_encoder_is_mst) |
4422 | intel_ddi_set_vc_payload_alloc(crtc, true); | |
4423 | ||
8807e55b | 4424 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4425 | encoder->enable(encoder); |
8807e55b JN |
4426 | intel_opregion_notify_encoder(encoder, true); |
4427 | } | |
4f771f10 | 4428 | |
4b3a9526 VS |
4429 | assert_vblank_disabled(crtc); |
4430 | drm_crtc_vblank_on(crtc); | |
4431 | ||
e4916946 PZ |
4432 | /* If we change the relative order between pipe/planes enabling, we need |
4433 | * to change the workaround. */ | |
4434 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4435 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4436 | } |
4437 | ||
bd2e244f JB |
4438 | static void skylake_pfit_disable(struct intel_crtc *crtc) |
4439 | { | |
4440 | struct drm_device *dev = crtc->base.dev; | |
4441 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4442 | int pipe = crtc->pipe; | |
4443 | ||
4444 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4445 | * it's in use. The hw state code will make sure we get this right. */ | |
4446 | if (crtc->config.pch_pfit.enabled) { | |
4447 | I915_WRITE(PS_CTL(pipe), 0); | |
4448 | I915_WRITE(PS_WIN_POS(pipe), 0); | |
4449 | I915_WRITE(PS_WIN_SZ(pipe), 0); | |
4450 | } | |
4451 | } | |
4452 | ||
3f8dce3a DV |
4453 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4454 | { | |
4455 | struct drm_device *dev = crtc->base.dev; | |
4456 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4457 | int pipe = crtc->pipe; | |
4458 | ||
4459 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4460 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 4461 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
4462 | I915_WRITE(PF_CTL(pipe), 0); |
4463 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4464 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4465 | } | |
4466 | } | |
4467 | ||
6be4a607 JB |
4468 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4469 | { | |
4470 | struct drm_device *dev = crtc->dev; | |
4471 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4472 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4473 | struct intel_encoder *encoder; |
6be4a607 | 4474 | int pipe = intel_crtc->pipe; |
5eddb70b | 4475 | u32 reg, temp; |
b52eb4dc | 4476 | |
f7abfe8b CW |
4477 | if (!intel_crtc->active) |
4478 | return; | |
4479 | ||
d3eedb1a | 4480 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4481 | |
4b3a9526 VS |
4482 | drm_crtc_vblank_off(crtc); |
4483 | assert_vblank_disabled(crtc); | |
4484 | ||
ea9d758d DV |
4485 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4486 | encoder->disable(encoder); | |
4487 | ||
d925c59a | 4488 | if (intel_crtc->config.has_pch_encoder) |
a72e4c9f | 4489 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 4490 | |
575f7ab7 | 4491 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4492 | |
3f8dce3a | 4493 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4494 | |
bf49ec8c DV |
4495 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4496 | if (encoder->post_disable) | |
4497 | encoder->post_disable(encoder); | |
2c07245f | 4498 | |
d925c59a DV |
4499 | if (intel_crtc->config.has_pch_encoder) { |
4500 | ironlake_fdi_disable(crtc); | |
913d8d11 | 4501 | |
d925c59a | 4502 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
a72e4c9f | 4503 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 4504 | |
d925c59a DV |
4505 | if (HAS_PCH_CPT(dev)) { |
4506 | /* disable TRANS_DP_CTL */ | |
4507 | reg = TRANS_DP_CTL(pipe); | |
4508 | temp = I915_READ(reg); | |
4509 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4510 | TRANS_DP_PORT_SEL_MASK); | |
4511 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4512 | I915_WRITE(reg, temp); | |
4513 | ||
4514 | /* disable DPLL_SEL */ | |
4515 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4516 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4517 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4518 | } |
e3421a18 | 4519 | |
d925c59a | 4520 | /* disable PCH DPLL */ |
e72f9fbf | 4521 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4522 | |
d925c59a DV |
4523 | ironlake_fdi_pll_disable(intel_crtc); |
4524 | } | |
6b383a7f | 4525 | |
f7abfe8b | 4526 | intel_crtc->active = false; |
46ba614c | 4527 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4528 | |
4529 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 4530 | intel_update_fbc(dev); |
d1ebd816 | 4531 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4532 | } |
1b3c7a47 | 4533 | |
4f771f10 | 4534 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4535 | { |
4f771f10 PZ |
4536 | struct drm_device *dev = crtc->dev; |
4537 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4538 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 4539 | struct intel_encoder *encoder; |
3b117c8f | 4540 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 4541 | |
4f771f10 PZ |
4542 | if (!intel_crtc->active) |
4543 | return; | |
4544 | ||
d3eedb1a | 4545 | intel_crtc_disable_planes(crtc); |
dda9a66a | 4546 | |
4b3a9526 VS |
4547 | drm_crtc_vblank_off(crtc); |
4548 | assert_vblank_disabled(crtc); | |
4549 | ||
8807e55b JN |
4550 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4551 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4552 | encoder->disable(encoder); |
8807e55b | 4553 | } |
4f771f10 | 4554 | |
8664281b | 4555 | if (intel_crtc->config.has_pch_encoder) |
a72e4c9f DV |
4556 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4557 | false); | |
575f7ab7 | 4558 | intel_disable_pipe(intel_crtc); |
4f771f10 | 4559 | |
a4bf214f VS |
4560 | if (intel_crtc->config.dp_encoder_is_mst) |
4561 | intel_ddi_set_vc_payload_alloc(crtc, false); | |
4562 | ||
ad80a810 | 4563 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4564 | |
bd2e244f JB |
4565 | if (IS_SKYLAKE(dev)) |
4566 | skylake_pfit_disable(intel_crtc); | |
4567 | else | |
4568 | ironlake_pfit_disable(intel_crtc); | |
4f771f10 | 4569 | |
1f544388 | 4570 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 4571 | |
88adfff1 | 4572 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 4573 | lpt_disable_pch_transcoder(dev_priv); |
a72e4c9f DV |
4574 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4575 | true); | |
1ad960f2 | 4576 | intel_ddi_fdi_disable(crtc); |
83616634 | 4577 | } |
4f771f10 | 4578 | |
97b040aa ID |
4579 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4580 | if (encoder->post_disable) | |
4581 | encoder->post_disable(encoder); | |
4582 | ||
4f771f10 | 4583 | intel_crtc->active = false; |
46ba614c | 4584 | intel_update_watermarks(crtc); |
4f771f10 PZ |
4585 | |
4586 | mutex_lock(&dev->struct_mutex); | |
4587 | intel_update_fbc(dev); | |
4588 | mutex_unlock(&dev->struct_mutex); | |
df8ad70c DV |
4589 | |
4590 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
4591 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
4592 | } |
4593 | ||
ee7b9f93 JB |
4594 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4595 | { | |
4596 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 4597 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
4598 | } |
4599 | ||
6441ab5f | 4600 | |
2dd24552 JB |
4601 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4602 | { | |
4603 | struct drm_device *dev = crtc->base.dev; | |
4604 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4605 | struct intel_crtc_config *pipe_config = &crtc->config; | |
4606 | ||
328d8e82 | 4607 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
4608 | return; |
4609 | ||
2dd24552 | 4610 | /* |
c0b03411 DV |
4611 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4612 | * according to register description and PRM. | |
2dd24552 | 4613 | */ |
c0b03411 DV |
4614 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4615 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4616 | |
b074cec8 JB |
4617 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4618 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4619 | |
4620 | /* Border color in case we don't scale up to the full screen. Black by | |
4621 | * default, change to something else for debugging. */ | |
4622 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4623 | } |
4624 | ||
d05410f9 DA |
4625 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
4626 | { | |
4627 | switch (port) { | |
4628 | case PORT_A: | |
4629 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4630 | case PORT_B: | |
4631 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4632 | case PORT_C: | |
4633 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4634 | case PORT_D: | |
4635 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4636 | default: | |
4637 | WARN_ON_ONCE(1); | |
4638 | return POWER_DOMAIN_PORT_OTHER; | |
4639 | } | |
4640 | } | |
4641 | ||
77d22dca ID |
4642 | #define for_each_power_domain(domain, mask) \ |
4643 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4644 | if ((1 << (domain)) & (mask)) | |
4645 | ||
319be8ae ID |
4646 | enum intel_display_power_domain |
4647 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4648 | { | |
4649 | struct drm_device *dev = intel_encoder->base.dev; | |
4650 | struct intel_digital_port *intel_dig_port; | |
4651 | ||
4652 | switch (intel_encoder->type) { | |
4653 | case INTEL_OUTPUT_UNKNOWN: | |
4654 | /* Only DDI platforms should ever use this output type */ | |
4655 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4656 | case INTEL_OUTPUT_DISPLAYPORT: | |
4657 | case INTEL_OUTPUT_HDMI: | |
4658 | case INTEL_OUTPUT_EDP: | |
4659 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 4660 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
4661 | case INTEL_OUTPUT_DP_MST: |
4662 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
4663 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
4664 | case INTEL_OUTPUT_ANALOG: |
4665 | return POWER_DOMAIN_PORT_CRT; | |
4666 | case INTEL_OUTPUT_DSI: | |
4667 | return POWER_DOMAIN_PORT_DSI; | |
4668 | default: | |
4669 | return POWER_DOMAIN_PORT_OTHER; | |
4670 | } | |
4671 | } | |
4672 | ||
4673 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4674 | { |
319be8ae ID |
4675 | struct drm_device *dev = crtc->dev; |
4676 | struct intel_encoder *intel_encoder; | |
4677 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4678 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
4679 | unsigned long mask; |
4680 | enum transcoder transcoder; | |
4681 | ||
4682 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4683 | ||
4684 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4685 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
fabf6e51 DV |
4686 | if (intel_crtc->config.pch_pfit.enabled || |
4687 | intel_crtc->config.pch_pfit.force_thru) | |
77d22dca ID |
4688 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
4689 | ||
319be8ae ID |
4690 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4691 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4692 | ||
77d22dca ID |
4693 | return mask; |
4694 | } | |
4695 | ||
77d22dca ID |
4696 | static void modeset_update_crtc_power_domains(struct drm_device *dev) |
4697 | { | |
4698 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4699 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4700 | struct intel_crtc *crtc; | |
4701 | ||
4702 | /* | |
4703 | * First get all needed power domains, then put all unneeded, to avoid | |
4704 | * any unnecessary toggling of the power wells. | |
4705 | */ | |
d3fcc808 | 4706 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4707 | enum intel_display_power_domain domain; |
4708 | ||
4709 | if (!crtc->base.enabled) | |
4710 | continue; | |
4711 | ||
319be8ae | 4712 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
4713 | |
4714 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
4715 | intel_display_power_get(dev_priv, domain); | |
4716 | } | |
4717 | ||
50f6e502 VS |
4718 | if (dev_priv->display.modeset_global_resources) |
4719 | dev_priv->display.modeset_global_resources(dev); | |
4720 | ||
d3fcc808 | 4721 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4722 | enum intel_display_power_domain domain; |
4723 | ||
4724 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
4725 | intel_display_power_put(dev_priv, domain); | |
4726 | ||
4727 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
4728 | } | |
4729 | ||
4730 | intel_display_set_init_power(dev_priv, false); | |
4731 | } | |
4732 | ||
dfcab17e | 4733 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 4734 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 4735 | { |
586f49dc | 4736 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 4737 | |
586f49dc JB |
4738 | /* Obtain SKU information */ |
4739 | mutex_lock(&dev_priv->dpio_lock); | |
4740 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
4741 | CCK_FUSE_HPLL_FREQ_MASK; | |
4742 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 4743 | |
dfcab17e | 4744 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
4745 | } |
4746 | ||
f8bf63fd VS |
4747 | static void vlv_update_cdclk(struct drm_device *dev) |
4748 | { | |
4749 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4750 | ||
4751 | dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
43dc52c3 | 4752 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
f8bf63fd VS |
4753 | dev_priv->vlv_cdclk_freq); |
4754 | ||
4755 | /* | |
4756 | * Program the gmbus_freq based on the cdclk frequency. | |
4757 | * BSpec erroneously claims we should aim for 4MHz, but | |
4758 | * in fact 1MHz is the correct frequency. | |
4759 | */ | |
6be1e3d3 | 4760 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000)); |
f8bf63fd VS |
4761 | } |
4762 | ||
30a970c6 JB |
4763 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
4764 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
4765 | { | |
4766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4767 | u32 val, cmd; | |
4768 | ||
d197b7d3 | 4769 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); |
d60c4473 | 4770 | |
dfcab17e | 4771 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 4772 | cmd = 2; |
dfcab17e | 4773 | else if (cdclk == 266667) |
30a970c6 JB |
4774 | cmd = 1; |
4775 | else | |
4776 | cmd = 0; | |
4777 | ||
4778 | mutex_lock(&dev_priv->rps.hw_lock); | |
4779 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4780 | val &= ~DSPFREQGUAR_MASK; | |
4781 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4782 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4783 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4784 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4785 | 50)) { | |
4786 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4787 | } | |
4788 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4789 | ||
dfcab17e | 4790 | if (cdclk == 400000) { |
6bcda4f0 | 4791 | u32 divider; |
30a970c6 | 4792 | |
6bcda4f0 | 4793 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 JB |
4794 | |
4795 | mutex_lock(&dev_priv->dpio_lock); | |
4796 | /* adjust cdclk divider */ | |
4797 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 4798 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
4799 | val |= divider; |
4800 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
4801 | |
4802 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
4803 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
4804 | 50)) | |
4805 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
4806 | mutex_unlock(&dev_priv->dpio_lock); |
4807 | } | |
4808 | ||
4809 | mutex_lock(&dev_priv->dpio_lock); | |
4810 | /* adjust self-refresh exit latency value */ | |
4811 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4812 | val &= ~0x7f; | |
4813 | ||
4814 | /* | |
4815 | * For high bandwidth configs, we set a higher latency in the bunit | |
4816 | * so that the core display fetch happens in time to avoid underruns. | |
4817 | */ | |
dfcab17e | 4818 | if (cdclk == 400000) |
30a970c6 JB |
4819 | val |= 4500 / 250; /* 4.5 usec */ |
4820 | else | |
4821 | val |= 3000 / 250; /* 3.0 usec */ | |
4822 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4823 | mutex_unlock(&dev_priv->dpio_lock); | |
4824 | ||
f8bf63fd | 4825 | vlv_update_cdclk(dev); |
30a970c6 JB |
4826 | } |
4827 | ||
383c5a6a VS |
4828 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
4829 | { | |
4830 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4831 | u32 val, cmd; | |
4832 | ||
4833 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); | |
4834 | ||
4835 | switch (cdclk) { | |
4836 | case 400000: | |
4837 | cmd = 3; | |
4838 | break; | |
4839 | case 333333: | |
4840 | case 320000: | |
4841 | cmd = 2; | |
4842 | break; | |
4843 | case 266667: | |
4844 | cmd = 1; | |
4845 | break; | |
4846 | case 200000: | |
4847 | cmd = 0; | |
4848 | break; | |
4849 | default: | |
4850 | WARN_ON(1); | |
4851 | return; | |
4852 | } | |
4853 | ||
4854 | mutex_lock(&dev_priv->rps.hw_lock); | |
4855 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4856 | val &= ~DSPFREQGUAR_MASK_CHV; | |
4857 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
4858 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4859 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4860 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
4861 | 50)) { | |
4862 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4863 | } | |
4864 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4865 | ||
4866 | vlv_update_cdclk(dev); | |
4867 | } | |
4868 | ||
30a970c6 JB |
4869 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
4870 | int max_pixclk) | |
4871 | { | |
6bcda4f0 | 4872 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
29dc7ef3 | 4873 | |
d49a340d VS |
4874 | /* FIXME: Punit isn't quite ready yet */ |
4875 | if (IS_CHERRYVIEW(dev_priv->dev)) | |
4876 | return 400000; | |
4877 | ||
30a970c6 JB |
4878 | /* |
4879 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4880 | * 200MHz | |
4881 | * 267MHz | |
29dc7ef3 | 4882 | * 320/333MHz (depends on HPLL freq) |
30a970c6 JB |
4883 | * 400MHz |
4884 | * So we check to see whether we're above 90% of the lower bin and | |
4885 | * adjust if needed. | |
e37c67a1 VS |
4886 | * |
4887 | * We seem to get an unstable or solid color picture at 200MHz. | |
4888 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
4889 | * are off. | |
30a970c6 | 4890 | */ |
29dc7ef3 | 4891 | if (max_pixclk > freq_320*9/10) |
dfcab17e VS |
4892 | return 400000; |
4893 | else if (max_pixclk > 266667*9/10) | |
29dc7ef3 | 4894 | return freq_320; |
e37c67a1 | 4895 | else if (max_pixclk > 0) |
dfcab17e | 4896 | return 266667; |
e37c67a1 VS |
4897 | else |
4898 | return 200000; | |
30a970c6 JB |
4899 | } |
4900 | ||
2f2d7aa1 VS |
4901 | /* compute the max pixel clock for new configuration */ |
4902 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
4903 | { |
4904 | struct drm_device *dev = dev_priv->dev; | |
4905 | struct intel_crtc *intel_crtc; | |
4906 | int max_pixclk = 0; | |
4907 | ||
d3fcc808 | 4908 | for_each_intel_crtc(dev, intel_crtc) { |
2f2d7aa1 | 4909 | if (intel_crtc->new_enabled) |
30a970c6 | 4910 | max_pixclk = max(max_pixclk, |
2f2d7aa1 | 4911 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
30a970c6 JB |
4912 | } |
4913 | ||
4914 | return max_pixclk; | |
4915 | } | |
4916 | ||
4917 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 4918 | unsigned *prepare_pipes) |
30a970c6 JB |
4919 | { |
4920 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4921 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 4922 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 | 4923 | |
d60c4473 ID |
4924 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
4925 | dev_priv->vlv_cdclk_freq) | |
30a970c6 JB |
4926 | return; |
4927 | ||
2f2d7aa1 | 4928 | /* disable/enable all currently active pipes while we change cdclk */ |
d3fcc808 | 4929 | for_each_intel_crtc(dev, intel_crtc) |
30a970c6 JB |
4930 | if (intel_crtc->base.enabled) |
4931 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4932 | } | |
4933 | ||
4934 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4935 | { | |
4936 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 4937 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4938 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
4939 | ||
383c5a6a | 4940 | if (req_cdclk != dev_priv->vlv_cdclk_freq) { |
738c05c0 ID |
4941 | /* |
4942 | * FIXME: We can end up here with all power domains off, yet | |
4943 | * with a CDCLK frequency other than the minimum. To account | |
4944 | * for this take the PIPE-A power domain, which covers the HW | |
4945 | * blocks needed for the following programming. This can be | |
4946 | * removed once it's guaranteed that we get here either with | |
4947 | * the minimum CDCLK set, or the required power domains | |
4948 | * enabled. | |
4949 | */ | |
4950 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
4951 | ||
383c5a6a VS |
4952 | if (IS_CHERRYVIEW(dev)) |
4953 | cherryview_set_cdclk(dev, req_cdclk); | |
4954 | else | |
4955 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 ID |
4956 | |
4957 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); | |
383c5a6a | 4958 | } |
30a970c6 JB |
4959 | } |
4960 | ||
89b667f8 JB |
4961 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4962 | { | |
4963 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 4964 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
4965 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4966 | struct intel_encoder *encoder; | |
4967 | int pipe = intel_crtc->pipe; | |
23538ef1 | 4968 | bool is_dsi; |
89b667f8 JB |
4969 | |
4970 | WARN_ON(!crtc->enabled); | |
4971 | ||
4972 | if (intel_crtc->active) | |
4973 | return; | |
4974 | ||
409ee761 | 4975 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 4976 | |
1ae0d137 VS |
4977 | if (!is_dsi) { |
4978 | if (IS_CHERRYVIEW(dev)) | |
d288f65f | 4979 | chv_prepare_pll(intel_crtc, &intel_crtc->config); |
1ae0d137 | 4980 | else |
d288f65f | 4981 | vlv_prepare_pll(intel_crtc, &intel_crtc->config); |
1ae0d137 | 4982 | } |
5b18e57c DV |
4983 | |
4984 | if (intel_crtc->config.has_dp_encoder) | |
4985 | intel_dp_set_m_n(intel_crtc); | |
4986 | ||
4987 | intel_set_pipe_timings(intel_crtc); | |
4988 | ||
c14b0485 VS |
4989 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
4990 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4991 | ||
4992 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
4993 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
4994 | } | |
4995 | ||
5b18e57c DV |
4996 | i9xx_set_pipeconf(intel_crtc); |
4997 | ||
89b667f8 | 4998 | intel_crtc->active = true; |
89b667f8 | 4999 | |
a72e4c9f | 5000 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5001 | |
89b667f8 JB |
5002 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5003 | if (encoder->pre_pll_enable) | |
5004 | encoder->pre_pll_enable(encoder); | |
5005 | ||
9d556c99 CML |
5006 | if (!is_dsi) { |
5007 | if (IS_CHERRYVIEW(dev)) | |
d288f65f | 5008 | chv_enable_pll(intel_crtc, &intel_crtc->config); |
9d556c99 | 5009 | else |
d288f65f | 5010 | vlv_enable_pll(intel_crtc, &intel_crtc->config); |
9d556c99 | 5011 | } |
89b667f8 JB |
5012 | |
5013 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
5014 | if (encoder->pre_enable) | |
5015 | encoder->pre_enable(encoder); | |
5016 | ||
2dd24552 JB |
5017 | i9xx_pfit_enable(intel_crtc); |
5018 | ||
63cbb074 VS |
5019 | intel_crtc_load_lut(crtc); |
5020 | ||
f37fcc2a | 5021 | intel_update_watermarks(crtc); |
e1fdc473 | 5022 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5023 | |
5004945f JN |
5024 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5025 | encoder->enable(encoder); | |
9ab0460b | 5026 | |
4b3a9526 VS |
5027 | assert_vblank_disabled(crtc); |
5028 | drm_crtc_vblank_on(crtc); | |
5029 | ||
9ab0460b | 5030 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5031 | |
56b80e1f | 5032 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5033 | i9xx_check_fifo_underruns(dev_priv); |
89b667f8 JB |
5034 | } |
5035 | ||
f13c2ef3 DV |
5036 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
5037 | { | |
5038 | struct drm_device *dev = crtc->base.dev; | |
5039 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5040 | ||
5041 | I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); | |
5042 | I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); | |
5043 | } | |
5044 | ||
0b8765c6 | 5045 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
5046 | { |
5047 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5048 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 5049 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 5050 | struct intel_encoder *encoder; |
79e53945 | 5051 | int pipe = intel_crtc->pipe; |
79e53945 | 5052 | |
08a48469 DV |
5053 | WARN_ON(!crtc->enabled); |
5054 | ||
f7abfe8b CW |
5055 | if (intel_crtc->active) |
5056 | return; | |
5057 | ||
f13c2ef3 DV |
5058 | i9xx_set_pll_dividers(intel_crtc); |
5059 | ||
5b18e57c DV |
5060 | if (intel_crtc->config.has_dp_encoder) |
5061 | intel_dp_set_m_n(intel_crtc); | |
5062 | ||
5063 | intel_set_pipe_timings(intel_crtc); | |
5064 | ||
5b18e57c DV |
5065 | i9xx_set_pipeconf(intel_crtc); |
5066 | ||
f7abfe8b | 5067 | intel_crtc->active = true; |
6b383a7f | 5068 | |
4a3436e8 | 5069 | if (!IS_GEN2(dev)) |
a72e4c9f | 5070 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5071 | |
9d6d9f19 MK |
5072 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5073 | if (encoder->pre_enable) | |
5074 | encoder->pre_enable(encoder); | |
5075 | ||
f6736a1a DV |
5076 | i9xx_enable_pll(intel_crtc); |
5077 | ||
2dd24552 JB |
5078 | i9xx_pfit_enable(intel_crtc); |
5079 | ||
63cbb074 VS |
5080 | intel_crtc_load_lut(crtc); |
5081 | ||
f37fcc2a | 5082 | intel_update_watermarks(crtc); |
e1fdc473 | 5083 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5084 | |
fa5c73b1 DV |
5085 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5086 | encoder->enable(encoder); | |
9ab0460b | 5087 | |
4b3a9526 VS |
5088 | assert_vblank_disabled(crtc); |
5089 | drm_crtc_vblank_on(crtc); | |
5090 | ||
9ab0460b | 5091 | intel_crtc_enable_planes(crtc); |
d40d9187 | 5092 | |
4a3436e8 VS |
5093 | /* |
5094 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5095 | * So don't enable underrun reporting before at least some planes | |
5096 | * are enabled. | |
5097 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5098 | * but leave the pipe running. | |
5099 | */ | |
5100 | if (IS_GEN2(dev)) | |
a72e4c9f | 5101 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5102 | |
56b80e1f | 5103 | /* Underruns don't raise interrupts, so check manually. */ |
a72e4c9f | 5104 | i9xx_check_fifo_underruns(dev_priv); |
0b8765c6 | 5105 | } |
79e53945 | 5106 | |
87476d63 DV |
5107 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5108 | { | |
5109 | struct drm_device *dev = crtc->base.dev; | |
5110 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 5111 | |
328d8e82 DV |
5112 | if (!crtc->config.gmch_pfit.control) |
5113 | return; | |
87476d63 | 5114 | |
328d8e82 | 5115 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 5116 | |
328d8e82 DV |
5117 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
5118 | I915_READ(PFIT_CONTROL)); | |
5119 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
5120 | } |
5121 | ||
0b8765c6 JB |
5122 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
5123 | { | |
5124 | struct drm_device *dev = crtc->dev; | |
5125 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5126 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5127 | struct intel_encoder *encoder; |
0b8765c6 | 5128 | int pipe = intel_crtc->pipe; |
ef9c3aee | 5129 | |
f7abfe8b CW |
5130 | if (!intel_crtc->active) |
5131 | return; | |
5132 | ||
4a3436e8 VS |
5133 | /* |
5134 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5135 | * So diasble underrun reporting before all the planes get disabled. | |
5136 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5137 | * but leave the pipe running. | |
5138 | */ | |
5139 | if (IS_GEN2(dev)) | |
a72e4c9f | 5140 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5141 | |
564ed191 ID |
5142 | /* |
5143 | * Vblank time updates from the shadow to live plane control register | |
5144 | * are blocked if the memory self-refresh mode is active at that | |
5145 | * moment. So to make sure the plane gets truly disabled, disable | |
5146 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5147 | * will be checked/applied by the HW only at the next frame start | |
5148 | * event which is after the vblank start event, so we need to have a | |
5149 | * wait-for-vblank between disabling the plane and the pipe. | |
5150 | */ | |
5151 | intel_set_memory_cxsr(dev_priv, false); | |
9ab0460b VS |
5152 | intel_crtc_disable_planes(crtc); |
5153 | ||
6304cd91 VS |
5154 | /* |
5155 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
5156 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
5157 | * We also need to wait on all gmch platforms because of the |
5158 | * self-refresh mode constraint explained above. | |
6304cd91 | 5159 | */ |
564ed191 | 5160 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 5161 | |
4b3a9526 VS |
5162 | drm_crtc_vblank_off(crtc); |
5163 | assert_vblank_disabled(crtc); | |
5164 | ||
5165 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
5166 | encoder->disable(encoder); | |
5167 | ||
575f7ab7 | 5168 | intel_disable_pipe(intel_crtc); |
24a1f16d | 5169 | |
87476d63 | 5170 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 5171 | |
89b667f8 JB |
5172 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5173 | if (encoder->post_disable) | |
5174 | encoder->post_disable(encoder); | |
5175 | ||
409ee761 | 5176 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
5177 | if (IS_CHERRYVIEW(dev)) |
5178 | chv_disable_pll(dev_priv, pipe); | |
5179 | else if (IS_VALLEYVIEW(dev)) | |
5180 | vlv_disable_pll(dev_priv, pipe); | |
5181 | else | |
1c4e0274 | 5182 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 5183 | } |
0b8765c6 | 5184 | |
4a3436e8 | 5185 | if (!IS_GEN2(dev)) |
a72e4c9f | 5186 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 5187 | |
f7abfe8b | 5188 | intel_crtc->active = false; |
46ba614c | 5189 | intel_update_watermarks(crtc); |
f37fcc2a | 5190 | |
efa9624e | 5191 | mutex_lock(&dev->struct_mutex); |
6b383a7f | 5192 | intel_update_fbc(dev); |
efa9624e | 5193 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
5194 | } |
5195 | ||
ee7b9f93 JB |
5196 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
5197 | { | |
5198 | } | |
5199 | ||
b04c5bd6 BF |
5200 | /* Master function to enable/disable CRTC and corresponding power wells */ |
5201 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
5202 | { |
5203 | struct drm_device *dev = crtc->dev; | |
5204 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 5205 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
5206 | enum intel_display_power_domain domain; |
5207 | unsigned long domains; | |
976f8a20 | 5208 | |
0e572fe7 DV |
5209 | if (enable) { |
5210 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
5211 | domains = get_crtc_power_domains(crtc); |
5212 | for_each_power_domain(domain, domains) | |
5213 | intel_display_power_get(dev_priv, domain); | |
5214 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
5215 | |
5216 | dev_priv->display.crtc_enable(crtc); | |
5217 | } | |
5218 | } else { | |
5219 | if (intel_crtc->active) { | |
5220 | dev_priv->display.crtc_disable(crtc); | |
5221 | ||
e1e9fb84 DV |
5222 | domains = intel_crtc->enabled_power_domains; |
5223 | for_each_power_domain(domain, domains) | |
5224 | intel_display_power_put(dev_priv, domain); | |
5225 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
5226 | } |
5227 | } | |
b04c5bd6 BF |
5228 | } |
5229 | ||
5230 | /** | |
5231 | * Sets the power management mode of the pipe and plane. | |
5232 | */ | |
5233 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
5234 | { | |
5235 | struct drm_device *dev = crtc->dev; | |
5236 | struct intel_encoder *intel_encoder; | |
5237 | bool enable = false; | |
5238 | ||
5239 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
5240 | enable |= intel_encoder->connectors_active; | |
5241 | ||
5242 | intel_crtc_control(crtc, enable); | |
976f8a20 DV |
5243 | } |
5244 | ||
cdd59983 CW |
5245 | static void intel_crtc_disable(struct drm_crtc *crtc) |
5246 | { | |
cdd59983 | 5247 | struct drm_device *dev = crtc->dev; |
976f8a20 | 5248 | struct drm_connector *connector; |
ee7b9f93 | 5249 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 5250 | |
976f8a20 DV |
5251 | /* crtc should still be enabled when we disable it. */ |
5252 | WARN_ON(!crtc->enabled); | |
5253 | ||
5254 | dev_priv->display.crtc_disable(crtc); | |
ee7b9f93 JB |
5255 | dev_priv->display.off(crtc); |
5256 | ||
455a6808 | 5257 | crtc->primary->funcs->disable_plane(crtc->primary); |
976f8a20 DV |
5258 | |
5259 | /* Update computed state. */ | |
5260 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
5261 | if (!connector->encoder || !connector->encoder->crtc) | |
5262 | continue; | |
5263 | ||
5264 | if (connector->encoder->crtc != crtc) | |
5265 | continue; | |
5266 | ||
5267 | connector->dpms = DRM_MODE_DPMS_OFF; | |
5268 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
5269 | } |
5270 | } | |
5271 | ||
ea5b213a | 5272 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5273 | { |
4ef69c7a | 5274 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5275 | |
ea5b213a CW |
5276 | drm_encoder_cleanup(encoder); |
5277 | kfree(intel_encoder); | |
7e7d76c3 JB |
5278 | } |
5279 | ||
9237329d | 5280 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
5281 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
5282 | * state of the entire output pipe. */ | |
9237329d | 5283 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 5284 | { |
5ab432ef DV |
5285 | if (mode == DRM_MODE_DPMS_ON) { |
5286 | encoder->connectors_active = true; | |
5287 | ||
b2cabb0e | 5288 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
5289 | } else { |
5290 | encoder->connectors_active = false; | |
5291 | ||
b2cabb0e | 5292 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 5293 | } |
79e53945 JB |
5294 | } |
5295 | ||
0a91ca29 DV |
5296 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5297 | * internal consistency). */ | |
b980514c | 5298 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 5299 | { |
0a91ca29 DV |
5300 | if (connector->get_hw_state(connector)) { |
5301 | struct intel_encoder *encoder = connector->encoder; | |
5302 | struct drm_crtc *crtc; | |
5303 | bool encoder_enabled; | |
5304 | enum pipe pipe; | |
5305 | ||
5306 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5307 | connector->base.base.id, | |
c23cc417 | 5308 | connector->base.name); |
0a91ca29 | 5309 | |
0e32b39c DA |
5310 | /* there is no real hw state for MST connectors */ |
5311 | if (connector->mst_port) | |
5312 | return; | |
5313 | ||
0a91ca29 DV |
5314 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
5315 | "wrong connector dpms state\n"); | |
5316 | WARN(connector->base.encoder != &encoder->base, | |
5317 | "active connector not linked to encoder\n"); | |
0a91ca29 | 5318 | |
36cd7444 DA |
5319 | if (encoder) { |
5320 | WARN(!encoder->connectors_active, | |
5321 | "encoder->connectors_active not set\n"); | |
5322 | ||
5323 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
5324 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
5325 | if (WARN_ON(!encoder->base.crtc)) | |
5326 | return; | |
0a91ca29 | 5327 | |
36cd7444 | 5328 | crtc = encoder->base.crtc; |
0a91ca29 | 5329 | |
36cd7444 DA |
5330 | WARN(!crtc->enabled, "crtc not enabled\n"); |
5331 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
5332 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
5333 | "encoder active on the wrong pipe\n"); | |
5334 | } | |
0a91ca29 | 5335 | } |
79e53945 JB |
5336 | } |
5337 | ||
5ab432ef DV |
5338 | /* Even simpler default implementation, if there's really no special case to |
5339 | * consider. */ | |
5340 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 5341 | { |
5ab432ef DV |
5342 | /* All the simple cases only support two dpms states. */ |
5343 | if (mode != DRM_MODE_DPMS_ON) | |
5344 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 5345 | |
5ab432ef DV |
5346 | if (mode == connector->dpms) |
5347 | return; | |
5348 | ||
5349 | connector->dpms = mode; | |
5350 | ||
5351 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
5352 | if (connector->encoder) |
5353 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 5354 | |
b980514c | 5355 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
5356 | } |
5357 | ||
f0947c37 DV |
5358 | /* Simple connector->get_hw_state implementation for encoders that support only |
5359 | * one connector and no cloning and hence the encoder state determines the state | |
5360 | * of the connector. */ | |
5361 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5362 | { |
24929352 | 5363 | enum pipe pipe = 0; |
f0947c37 | 5364 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 5365 | |
f0947c37 | 5366 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
5367 | } |
5368 | ||
1857e1da DV |
5369 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5370 | struct intel_crtc_config *pipe_config) | |
5371 | { | |
5372 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5373 | struct intel_crtc *pipe_B_crtc = | |
5374 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
5375 | ||
5376 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
5377 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5378 | if (pipe_config->fdi_lanes > 4) { | |
5379 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
5380 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5381 | return false; | |
5382 | } | |
5383 | ||
bafb6553 | 5384 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
5385 | if (pipe_config->fdi_lanes > 2) { |
5386 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
5387 | pipe_config->fdi_lanes); | |
5388 | return false; | |
5389 | } else { | |
5390 | return true; | |
5391 | } | |
5392 | } | |
5393 | ||
5394 | if (INTEL_INFO(dev)->num_pipes == 2) | |
5395 | return true; | |
5396 | ||
5397 | /* Ivybridge 3 pipe is really complicated */ | |
5398 | switch (pipe) { | |
5399 | case PIPE_A: | |
5400 | return true; | |
5401 | case PIPE_B: | |
5402 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
5403 | pipe_config->fdi_lanes > 2) { | |
5404 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5405 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5406 | return false; | |
5407 | } | |
5408 | return true; | |
5409 | case PIPE_C: | |
1e833f40 | 5410 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
5411 | pipe_B_crtc->config.fdi_lanes <= 2) { |
5412 | if (pipe_config->fdi_lanes > 2) { | |
5413 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5414 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5415 | return false; | |
5416 | } | |
5417 | } else { | |
5418 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
5419 | return false; | |
5420 | } | |
5421 | return true; | |
5422 | default: | |
5423 | BUG(); | |
5424 | } | |
5425 | } | |
5426 | ||
e29c22c0 DV |
5427 | #define RETRY 1 |
5428 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5429 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 5430 | { |
1857e1da | 5431 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 5432 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 5433 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 5434 | bool setup_ok, needs_recompute = false; |
877d48d5 | 5435 | |
e29c22c0 | 5436 | retry: |
877d48d5 DV |
5437 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5438 | * each output octet as 10 bits. The actual frequency | |
5439 | * is stored as a divider into a 100MHz clock, and the | |
5440 | * mode pixel clock is stored in units of 1KHz. | |
5441 | * Hence the bw of each lane in terms of the mode signal | |
5442 | * is: | |
5443 | */ | |
5444 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5445 | ||
241bfc38 | 5446 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 5447 | |
2bd89a07 | 5448 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
5449 | pipe_config->pipe_bpp); |
5450 | ||
5451 | pipe_config->fdi_lanes = lane; | |
5452 | ||
2bd89a07 | 5453 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 5454 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 5455 | |
e29c22c0 DV |
5456 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
5457 | intel_crtc->pipe, pipe_config); | |
5458 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
5459 | pipe_config->pipe_bpp -= 2*3; | |
5460 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
5461 | pipe_config->pipe_bpp); | |
5462 | needs_recompute = true; | |
5463 | pipe_config->bw_constrained = true; | |
5464 | ||
5465 | goto retry; | |
5466 | } | |
5467 | ||
5468 | if (needs_recompute) | |
5469 | return RETRY; | |
5470 | ||
5471 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
5472 | } |
5473 | ||
42db64ef PZ |
5474 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5475 | struct intel_crtc_config *pipe_config) | |
5476 | { | |
d330a953 | 5477 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 5478 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 5479 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
5480 | } |
5481 | ||
a43f6e0f | 5482 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 5483 | struct intel_crtc_config *pipe_config) |
79e53945 | 5484 | { |
a43f6e0f | 5485 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 5486 | struct drm_i915_private *dev_priv = dev->dev_private; |
b8cecdf5 | 5487 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 5488 | |
ad3a4479 | 5489 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 5490 | if (INTEL_INFO(dev)->gen < 4) { |
cf532bb2 VS |
5491 | int clock_limit = |
5492 | dev_priv->display.get_display_clock_speed(dev); | |
5493 | ||
5494 | /* | |
5495 | * Enable pixel doubling when the dot clock | |
5496 | * is > 90% of the (display) core speed. | |
5497 | * | |
b397c96b VS |
5498 | * GDG double wide on either pipe, |
5499 | * otherwise pipe A only. | |
cf532bb2 | 5500 | */ |
b397c96b | 5501 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 5502 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 5503 | clock_limit *= 2; |
cf532bb2 | 5504 | pipe_config->double_wide = true; |
ad3a4479 VS |
5505 | } |
5506 | ||
241bfc38 | 5507 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 5508 | return -EINVAL; |
2c07245f | 5509 | } |
89749350 | 5510 | |
1d1d0e27 VS |
5511 | /* |
5512 | * Pipe horizontal size must be even in: | |
5513 | * - DVO ganged mode | |
5514 | * - LVDS dual channel mode | |
5515 | * - Double wide pipe | |
5516 | */ | |
409ee761 | 5517 | if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
5518 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
5519 | pipe_config->pipe_src_w &= ~1; | |
5520 | ||
8693a824 DL |
5521 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
5522 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
5523 | */ |
5524 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
5525 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 5526 | return -EINVAL; |
44f46b42 | 5527 | |
bd080ee5 | 5528 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 5529 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 5530 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
5531 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
5532 | * for lvds. */ | |
5533 | pipe_config->pipe_bpp = 8*3; | |
5534 | } | |
5535 | ||
f5adf94e | 5536 | if (HAS_IPS(dev)) |
a43f6e0f DV |
5537 | hsw_compute_ips_config(crtc, pipe_config); |
5538 | ||
877d48d5 | 5539 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 5540 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 5541 | |
e29c22c0 | 5542 | return 0; |
79e53945 JB |
5543 | } |
5544 | ||
25eb05fc JB |
5545 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
5546 | { | |
d197b7d3 | 5547 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
5548 | u32 val; |
5549 | int divider; | |
5550 | ||
d49a340d VS |
5551 | /* FIXME: Punit isn't quite ready yet */ |
5552 | if (IS_CHERRYVIEW(dev)) | |
5553 | return 400000; | |
5554 | ||
6bcda4f0 VS |
5555 | if (dev_priv->hpll_freq == 0) |
5556 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
5557 | ||
d197b7d3 VS |
5558 | mutex_lock(&dev_priv->dpio_lock); |
5559 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
5560 | mutex_unlock(&dev_priv->dpio_lock); | |
5561 | ||
5562 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
5563 | ||
7d007f40 VS |
5564 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
5565 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5566 | "cdclk change in progress\n"); | |
5567 | ||
6bcda4f0 | 5568 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
5569 | } |
5570 | ||
e70236a8 JB |
5571 | static int i945_get_display_clock_speed(struct drm_device *dev) |
5572 | { | |
5573 | return 400000; | |
5574 | } | |
79e53945 | 5575 | |
e70236a8 | 5576 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 5577 | { |
e70236a8 JB |
5578 | return 333000; |
5579 | } | |
79e53945 | 5580 | |
e70236a8 JB |
5581 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
5582 | { | |
5583 | return 200000; | |
5584 | } | |
79e53945 | 5585 | |
257a7ffc DV |
5586 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
5587 | { | |
5588 | u16 gcfgc = 0; | |
5589 | ||
5590 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
5591 | ||
5592 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5593 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
5594 | return 267000; | |
5595 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
5596 | return 333000; | |
5597 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
5598 | return 444000; | |
5599 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
5600 | return 200000; | |
5601 | default: | |
5602 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
5603 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
5604 | return 133000; | |
5605 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
5606 | return 167000; | |
5607 | } | |
5608 | } | |
5609 | ||
e70236a8 JB |
5610 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
5611 | { | |
5612 | u16 gcfgc = 0; | |
79e53945 | 5613 | |
e70236a8 JB |
5614 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
5615 | ||
5616 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
5617 | return 133000; | |
5618 | else { | |
5619 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5620 | case GC_DISPLAY_CLOCK_333_MHZ: | |
5621 | return 333000; | |
5622 | default: | |
5623 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
5624 | return 190000; | |
79e53945 | 5625 | } |
e70236a8 JB |
5626 | } |
5627 | } | |
5628 | ||
5629 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
5630 | { | |
5631 | return 266000; | |
5632 | } | |
5633 | ||
5634 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
5635 | { | |
5636 | u16 hpllcc = 0; | |
5637 | /* Assume that the hardware is in the high speed state. This | |
5638 | * should be the default. | |
5639 | */ | |
5640 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
5641 | case GC_CLOCK_133_200: | |
5642 | case GC_CLOCK_100_200: | |
5643 | return 200000; | |
5644 | case GC_CLOCK_166_250: | |
5645 | return 250000; | |
5646 | case GC_CLOCK_100_133: | |
79e53945 | 5647 | return 133000; |
e70236a8 | 5648 | } |
79e53945 | 5649 | |
e70236a8 JB |
5650 | /* Shouldn't happen */ |
5651 | return 0; | |
5652 | } | |
79e53945 | 5653 | |
e70236a8 JB |
5654 | static int i830_get_display_clock_speed(struct drm_device *dev) |
5655 | { | |
5656 | return 133000; | |
79e53945 JB |
5657 | } |
5658 | ||
2c07245f | 5659 | static void |
a65851af | 5660 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 5661 | { |
a65851af VS |
5662 | while (*num > DATA_LINK_M_N_MASK || |
5663 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
5664 | *num >>= 1; |
5665 | *den >>= 1; | |
5666 | } | |
5667 | } | |
5668 | ||
a65851af VS |
5669 | static void compute_m_n(unsigned int m, unsigned int n, |
5670 | uint32_t *ret_m, uint32_t *ret_n) | |
5671 | { | |
5672 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
5673 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
5674 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
5675 | } | |
5676 | ||
e69d0bc1 DV |
5677 | void |
5678 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
5679 | int pixel_clock, int link_clock, | |
5680 | struct intel_link_m_n *m_n) | |
2c07245f | 5681 | { |
e69d0bc1 | 5682 | m_n->tu = 64; |
a65851af VS |
5683 | |
5684 | compute_m_n(bits_per_pixel * pixel_clock, | |
5685 | link_clock * nlanes * 8, | |
5686 | &m_n->gmch_m, &m_n->gmch_n); | |
5687 | ||
5688 | compute_m_n(pixel_clock, link_clock, | |
5689 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
5690 | } |
5691 | ||
a7615030 CW |
5692 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5693 | { | |
d330a953 JN |
5694 | if (i915.panel_use_ssc >= 0) |
5695 | return i915.panel_use_ssc != 0; | |
41aa3448 | 5696 | return dev_priv->vbt.lvds_use_ssc |
435793df | 5697 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
5698 | } |
5699 | ||
409ee761 | 5700 | static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors) |
c65d77d8 | 5701 | { |
409ee761 | 5702 | struct drm_device *dev = crtc->base.dev; |
c65d77d8 JB |
5703 | struct drm_i915_private *dev_priv = dev->dev_private; |
5704 | int refclk; | |
5705 | ||
a0c4da24 | 5706 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 5707 | refclk = 100000; |
d0737e1d | 5708 | } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 5709 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
5710 | refclk = dev_priv->vbt.lvds_ssc_freq; |
5711 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
5712 | } else if (!IS_GEN2(dev)) { |
5713 | refclk = 96000; | |
5714 | } else { | |
5715 | refclk = 48000; | |
5716 | } | |
5717 | ||
5718 | return refclk; | |
5719 | } | |
5720 | ||
7429e9d4 | 5721 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 5722 | { |
7df00d7a | 5723 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 5724 | } |
f47709a9 | 5725 | |
7429e9d4 DV |
5726 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
5727 | { | |
5728 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
5729 | } |
5730 | ||
f47709a9 | 5731 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
5732 | intel_clock_t *reduced_clock) |
5733 | { | |
f47709a9 | 5734 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
5735 | u32 fp, fp2 = 0; |
5736 | ||
5737 | if (IS_PINEVIEW(dev)) { | |
e1f234bd | 5738 | fp = pnv_dpll_compute_fp(&crtc->new_config->dpll); |
a7516a05 | 5739 | if (reduced_clock) |
7429e9d4 | 5740 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 5741 | } else { |
e1f234bd | 5742 | fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll); |
a7516a05 | 5743 | if (reduced_clock) |
7429e9d4 | 5744 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
5745 | } |
5746 | ||
e1f234bd | 5747 | crtc->new_config->dpll_hw_state.fp0 = fp; |
a7516a05 | 5748 | |
f47709a9 | 5749 | crtc->lowfreq_avail = false; |
e1f234bd | 5750 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
d330a953 | 5751 | reduced_clock && i915.powersave) { |
e1f234bd | 5752 | crtc->new_config->dpll_hw_state.fp1 = fp2; |
f47709a9 | 5753 | crtc->lowfreq_avail = true; |
a7516a05 | 5754 | } else { |
e1f234bd | 5755 | crtc->new_config->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
5756 | } |
5757 | } | |
5758 | ||
5e69f97f CML |
5759 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
5760 | pipe) | |
89b667f8 JB |
5761 | { |
5762 | u32 reg_val; | |
5763 | ||
5764 | /* | |
5765 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
5766 | * and set it to a reasonable value instead. | |
5767 | */ | |
ab3c759a | 5768 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
5769 | reg_val &= 0xffffff00; |
5770 | reg_val |= 0x00000030; | |
ab3c759a | 5771 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5772 | |
ab3c759a | 5773 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5774 | reg_val &= 0x8cffffff; |
5775 | reg_val = 0x8c000000; | |
ab3c759a | 5776 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 5777 | |
ab3c759a | 5778 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 5779 | reg_val &= 0xffffff00; |
ab3c759a | 5780 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5781 | |
ab3c759a | 5782 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5783 | reg_val &= 0x00ffffff; |
5784 | reg_val |= 0xb0000000; | |
ab3c759a | 5785 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
5786 | } |
5787 | ||
b551842d DV |
5788 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
5789 | struct intel_link_m_n *m_n) | |
5790 | { | |
5791 | struct drm_device *dev = crtc->base.dev; | |
5792 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5793 | int pipe = crtc->pipe; | |
5794 | ||
e3b95f1e DV |
5795 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5796 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
5797 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
5798 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
5799 | } |
5800 | ||
5801 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
5802 | struct intel_link_m_n *m_n, |
5803 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
5804 | { |
5805 | struct drm_device *dev = crtc->base.dev; | |
5806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5807 | int pipe = crtc->pipe; | |
5808 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
5809 | ||
5810 | if (INTEL_INFO(dev)->gen >= 5) { | |
5811 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
5812 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
5813 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
5814 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
5815 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
5816 | * for gen < 8) and if DRRS is supported (to make sure the | |
5817 | * registers are not unnecessarily accessed). | |
5818 | */ | |
5819 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
5820 | crtc->config.has_drrs) { | |
5821 | I915_WRITE(PIPE_DATA_M2(transcoder), | |
5822 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
5823 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
5824 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
5825 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
5826 | } | |
b551842d | 5827 | } else { |
e3b95f1e DV |
5828 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5829 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
5830 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
5831 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
5832 | } |
5833 | } | |
5834 | ||
f769cd24 | 5835 | void intel_dp_set_m_n(struct intel_crtc *crtc) |
03afc4a2 DV |
5836 | { |
5837 | if (crtc->config.has_pch_encoder) | |
5838 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5839 | else | |
f769cd24 VK |
5840 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n, |
5841 | &crtc->config.dp_m2_n2); | |
03afc4a2 DV |
5842 | } |
5843 | ||
d288f65f VS |
5844 | static void vlv_update_pll(struct intel_crtc *crtc, |
5845 | struct intel_crtc_config *pipe_config) | |
bdd4b6a6 DV |
5846 | { |
5847 | u32 dpll, dpll_md; | |
5848 | ||
5849 | /* | |
5850 | * Enable DPIO clock input. We should never disable the reference | |
5851 | * clock for pipe B, since VGA hotplug / manual detection depends | |
5852 | * on it. | |
5853 | */ | |
5854 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
5855 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
5856 | /* We should never disable this, set it here for state tracking */ | |
5857 | if (crtc->pipe == PIPE_B) | |
5858 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5859 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 5860 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 5861 | |
d288f65f | 5862 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 5863 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 5864 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
5865 | } |
5866 | ||
d288f65f VS |
5867 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5868 | const struct intel_crtc_config *pipe_config) | |
a0c4da24 | 5869 | { |
f47709a9 | 5870 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 5871 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 5872 | int pipe = crtc->pipe; |
bdd4b6a6 | 5873 | u32 mdiv; |
a0c4da24 | 5874 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 5875 | u32 coreclk, reg_val; |
a0c4da24 | 5876 | |
09153000 DV |
5877 | mutex_lock(&dev_priv->dpio_lock); |
5878 | ||
d288f65f VS |
5879 | bestn = pipe_config->dpll.n; |
5880 | bestm1 = pipe_config->dpll.m1; | |
5881 | bestm2 = pipe_config->dpll.m2; | |
5882 | bestp1 = pipe_config->dpll.p1; | |
5883 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 5884 | |
89b667f8 JB |
5885 | /* See eDP HDMI DPIO driver vbios notes doc */ |
5886 | ||
5887 | /* PLL B needs special handling */ | |
bdd4b6a6 | 5888 | if (pipe == PIPE_B) |
5e69f97f | 5889 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
5890 | |
5891 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 5892 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
5893 | |
5894 | /* Disable target IRef on PLL */ | |
ab3c759a | 5895 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 5896 | reg_val &= 0x00ffffff; |
ab3c759a | 5897 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
5898 | |
5899 | /* Disable fast lock */ | |
ab3c759a | 5900 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
5901 | |
5902 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
5903 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
5904 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
5905 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 5906 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
5907 | |
5908 | /* | |
5909 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
5910 | * but we don't support that). | |
5911 | * Note: don't use the DAC post divider as it seems unstable. | |
5912 | */ | |
5913 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 5914 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5915 | |
a0c4da24 | 5916 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 5917 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5918 | |
89b667f8 | 5919 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 5920 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
5921 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
5922 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 5923 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 5924 | 0x009f0003); |
89b667f8 | 5925 | else |
ab3c759a | 5926 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
5927 | 0x00d0000f); |
5928 | ||
0a88818d | 5929 | if (crtc->config.has_dp_encoder) { |
89b667f8 | 5930 | /* Use SSC source */ |
bdd4b6a6 | 5931 | if (pipe == PIPE_A) |
ab3c759a | 5932 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5933 | 0x0df40000); |
5934 | else | |
ab3c759a | 5935 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5936 | 0x0df70000); |
5937 | } else { /* HDMI or VGA */ | |
5938 | /* Use bend source */ | |
bdd4b6a6 | 5939 | if (pipe == PIPE_A) |
ab3c759a | 5940 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5941 | 0x0df70000); |
5942 | else | |
ab3c759a | 5943 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5944 | 0x0df40000); |
5945 | } | |
a0c4da24 | 5946 | |
ab3c759a | 5947 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 5948 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
5949 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
5950 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 5951 | coreclk |= 0x01000000; |
ab3c759a | 5952 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 5953 | |
ab3c759a | 5954 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 5955 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
5956 | } |
5957 | ||
d288f65f VS |
5958 | static void chv_update_pll(struct intel_crtc *crtc, |
5959 | struct intel_crtc_config *pipe_config) | |
1ae0d137 | 5960 | { |
d288f65f | 5961 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
1ae0d137 VS |
5962 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
5963 | DPLL_VCO_ENABLE; | |
5964 | if (crtc->pipe != PIPE_A) | |
d288f65f | 5965 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 5966 | |
d288f65f VS |
5967 | pipe_config->dpll_hw_state.dpll_md = |
5968 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
5969 | } |
5970 | ||
d288f65f VS |
5971 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5972 | const struct intel_crtc_config *pipe_config) | |
9d556c99 CML |
5973 | { |
5974 | struct drm_device *dev = crtc->base.dev; | |
5975 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5976 | int pipe = crtc->pipe; | |
5977 | int dpll_reg = DPLL(crtc->pipe); | |
5978 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
580d3811 | 5979 | u32 loopfilter, intcoeff; |
9d556c99 CML |
5980 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
5981 | int refclk; | |
5982 | ||
d288f65f VS |
5983 | bestn = pipe_config->dpll.n; |
5984 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
5985 | bestm1 = pipe_config->dpll.m1; | |
5986 | bestm2 = pipe_config->dpll.m2 >> 22; | |
5987 | bestp1 = pipe_config->dpll.p1; | |
5988 | bestp2 = pipe_config->dpll.p2; | |
9d556c99 CML |
5989 | |
5990 | /* | |
5991 | * Enable Refclk and SSC | |
5992 | */ | |
a11b0703 | 5993 | I915_WRITE(dpll_reg, |
d288f65f | 5994 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 VS |
5995 | |
5996 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 5997 | |
9d556c99 CML |
5998 | /* p1 and p2 divider */ |
5999 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6000 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6001 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6002 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6003 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6004 | ||
6005 | /* Feedback post-divider - m2 */ | |
6006 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6007 | ||
6008 | /* Feedback refclk divider - n and m1 */ | |
6009 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6010 | DPIO_CHV_M1_DIV_BY_2 | | |
6011 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6012 | ||
6013 | /* M2 fraction division */ | |
6014 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
6015 | ||
6016 | /* M2 fraction division enable */ | |
6017 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), | |
6018 | DPIO_CHV_FRAC_DIV_EN | | |
6019 | (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT)); | |
6020 | ||
6021 | /* Loop filter */ | |
409ee761 | 6022 | refclk = i9xx_get_refclk(crtc, 0); |
9d556c99 CML |
6023 | loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | |
6024 | 2 << DPIO_CHV_GAIN_CTRL_SHIFT; | |
6025 | if (refclk == 100000) | |
6026 | intcoeff = 11; | |
6027 | else if (refclk == 38400) | |
6028 | intcoeff = 10; | |
6029 | else | |
6030 | intcoeff = 9; | |
6031 | loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT; | |
6032 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); | |
6033 | ||
6034 | /* AFC Recal */ | |
6035 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6036 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6037 | DPIO_AFC_RECAL); | |
6038 | ||
6039 | mutex_unlock(&dev_priv->dpio_lock); | |
6040 | } | |
6041 | ||
d288f65f VS |
6042 | /** |
6043 | * vlv_force_pll_on - forcibly enable just the PLL | |
6044 | * @dev_priv: i915 private structure | |
6045 | * @pipe: pipe PLL to enable | |
6046 | * @dpll: PLL configuration | |
6047 | * | |
6048 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6049 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6050 | * be enabled. | |
6051 | */ | |
6052 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
6053 | const struct dpll *dpll) | |
6054 | { | |
6055 | struct intel_crtc *crtc = | |
6056 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
6057 | struct intel_crtc_config pipe_config = { | |
6058 | .pixel_multiplier = 1, | |
6059 | .dpll = *dpll, | |
6060 | }; | |
6061 | ||
6062 | if (IS_CHERRYVIEW(dev)) { | |
6063 | chv_update_pll(crtc, &pipe_config); | |
6064 | chv_prepare_pll(crtc, &pipe_config); | |
6065 | chv_enable_pll(crtc, &pipe_config); | |
6066 | } else { | |
6067 | vlv_update_pll(crtc, &pipe_config); | |
6068 | vlv_prepare_pll(crtc, &pipe_config); | |
6069 | vlv_enable_pll(crtc, &pipe_config); | |
6070 | } | |
6071 | } | |
6072 | ||
6073 | /** | |
6074 | * vlv_force_pll_off - forcibly disable just the PLL | |
6075 | * @dev_priv: i915 private structure | |
6076 | * @pipe: pipe PLL to disable | |
6077 | * | |
6078 | * Disable the PLL for @pipe. To be used in cases where we need | |
6079 | * the PLL enabled even when @pipe is not going to be enabled. | |
6080 | */ | |
6081 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
6082 | { | |
6083 | if (IS_CHERRYVIEW(dev)) | |
6084 | chv_disable_pll(to_i915(dev), pipe); | |
6085 | else | |
6086 | vlv_disable_pll(to_i915(dev), pipe); | |
6087 | } | |
6088 | ||
f47709a9 DV |
6089 | static void i9xx_update_pll(struct intel_crtc *crtc, |
6090 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
6091 | int num_connectors) |
6092 | { | |
f47709a9 | 6093 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 6094 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
6095 | u32 dpll; |
6096 | bool is_sdvo; | |
d0737e1d | 6097 | struct dpll *clock = &crtc->new_config->dpll; |
eb1cbe48 | 6098 | |
f47709a9 | 6099 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 6100 | |
d0737e1d ACO |
6101 | is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) || |
6102 | intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
6103 | |
6104 | dpll = DPLL_VGA_MODE_DIS; | |
6105 | ||
d0737e1d | 6106 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
6107 | dpll |= DPLLB_MODE_LVDS; |
6108 | else | |
6109 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 6110 | |
ef1b460d | 6111 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
d0737e1d | 6112 | dpll |= (crtc->new_config->pixel_multiplier - 1) |
198a037f | 6113 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 6114 | } |
198a037f DV |
6115 | |
6116 | if (is_sdvo) | |
4a33e48d | 6117 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 6118 | |
0a88818d | 6119 | if (crtc->new_config->has_dp_encoder) |
4a33e48d | 6120 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
6121 | |
6122 | /* compute bitmask from p1 value */ | |
6123 | if (IS_PINEVIEW(dev)) | |
6124 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
6125 | else { | |
6126 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6127 | if (IS_G4X(dev) && reduced_clock) | |
6128 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
6129 | } | |
6130 | switch (clock->p2) { | |
6131 | case 5: | |
6132 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6133 | break; | |
6134 | case 7: | |
6135 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6136 | break; | |
6137 | case 10: | |
6138 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6139 | break; | |
6140 | case 14: | |
6141 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6142 | break; | |
6143 | } | |
6144 | if (INTEL_INFO(dev)->gen >= 4) | |
6145 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
6146 | ||
d0737e1d | 6147 | if (crtc->new_config->sdvo_tv_clock) |
eb1cbe48 | 6148 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
d0737e1d | 6149 | else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
6150 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6151 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
6152 | else | |
6153 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6154 | ||
6155 | dpll |= DPLL_VCO_ENABLE; | |
d0737e1d | 6156 | crtc->new_config->dpll_hw_state.dpll = dpll; |
8bcc2795 | 6157 | |
eb1cbe48 | 6158 | if (INTEL_INFO(dev)->gen >= 4) { |
d0737e1d | 6159 | u32 dpll_md = (crtc->new_config->pixel_multiplier - 1) |
ef1b460d | 6160 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d0737e1d | 6161 | crtc->new_config->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
6162 | } |
6163 | } | |
6164 | ||
f47709a9 | 6165 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 6166 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
6167 | int num_connectors) |
6168 | { | |
f47709a9 | 6169 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 6170 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 6171 | u32 dpll; |
d0737e1d | 6172 | struct dpll *clock = &crtc->new_config->dpll; |
eb1cbe48 | 6173 | |
f47709a9 | 6174 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 6175 | |
eb1cbe48 DV |
6176 | dpll = DPLL_VGA_MODE_DIS; |
6177 | ||
d0737e1d | 6178 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
6179 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6180 | } else { | |
6181 | if (clock->p1 == 2) | |
6182 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
6183 | else | |
6184 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6185 | if (clock->p2 == 4) | |
6186 | dpll |= PLL_P2_DIVIDE_BY_4; | |
6187 | } | |
6188 | ||
d0737e1d | 6189 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
6190 | dpll |= DPLL_DVO_2X_MODE; |
6191 | ||
d0737e1d | 6192 | if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
6193 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6194 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
6195 | else | |
6196 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6197 | ||
6198 | dpll |= DPLL_VCO_ENABLE; | |
d0737e1d | 6199 | crtc->new_config->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
6200 | } |
6201 | ||
8a654f3b | 6202 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
6203 | { |
6204 | struct drm_device *dev = intel_crtc->base.dev; | |
6205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6206 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 6207 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
6208 | struct drm_display_mode *adjusted_mode = |
6209 | &intel_crtc->config.adjusted_mode; | |
1caea6e9 VS |
6210 | uint32_t crtc_vtotal, crtc_vblank_end; |
6211 | int vsyncshift = 0; | |
4d8a62ea DV |
6212 | |
6213 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
6214 | * the hw state checker will get angry at the mismatch. */ | |
6215 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
6216 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 6217 | |
609aeaca | 6218 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 6219 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
6220 | crtc_vtotal -= 1; |
6221 | crtc_vblank_end -= 1; | |
609aeaca | 6222 | |
409ee761 | 6223 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
6224 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
6225 | else | |
6226 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
6227 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
6228 | if (vsyncshift < 0) |
6229 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
6230 | } |
6231 | ||
6232 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 6233 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 6234 | |
fe2b8f9d | 6235 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
6236 | (adjusted_mode->crtc_hdisplay - 1) | |
6237 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 6238 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
6239 | (adjusted_mode->crtc_hblank_start - 1) | |
6240 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 6241 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
6242 | (adjusted_mode->crtc_hsync_start - 1) | |
6243 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
6244 | ||
fe2b8f9d | 6245 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 6246 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 6247 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 6248 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 6249 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 6250 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 6251 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
6252 | (adjusted_mode->crtc_vsync_start - 1) | |
6253 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
6254 | ||
b5e508d4 PZ |
6255 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
6256 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
6257 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
6258 | * bits. */ | |
6259 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
6260 | (pipe == PIPE_B || pipe == PIPE_C)) | |
6261 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
6262 | ||
b0e77b9c PZ |
6263 | /* pipesrc controls the size that is scaled from, which should |
6264 | * always be the user's requested size. | |
6265 | */ | |
6266 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
6267 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
6268 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
6269 | } |
6270 | ||
1bd1bd80 DV |
6271 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
6272 | struct intel_crtc_config *pipe_config) | |
6273 | { | |
6274 | struct drm_device *dev = crtc->base.dev; | |
6275 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6276 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
6277 | uint32_t tmp; | |
6278 | ||
6279 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
6280 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
6281 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
6282 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
6283 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
6284 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
6285 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
6286 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
6287 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
6288 | ||
6289 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
6290 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
6291 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
6292 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
6293 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
6294 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
6295 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
6296 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
6297 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
6298 | ||
6299 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
6300 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
6301 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
6302 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
6303 | } | |
6304 | ||
6305 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
6306 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
6307 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
6308 | ||
6309 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
6310 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
6311 | } |
6312 | ||
f6a83288 DV |
6313 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
6314 | struct intel_crtc_config *pipe_config) | |
babea61d | 6315 | { |
f6a83288 DV |
6316 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
6317 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; | |
6318 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
6319 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
babea61d | 6320 | |
f6a83288 DV |
6321 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
6322 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
6323 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
6324 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
babea61d | 6325 | |
f6a83288 | 6326 | mode->flags = pipe_config->adjusted_mode.flags; |
babea61d | 6327 | |
f6a83288 DV |
6328 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
6329 | mode->flags |= pipe_config->adjusted_mode.flags; | |
babea61d JB |
6330 | } |
6331 | ||
84b046f3 DV |
6332 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
6333 | { | |
6334 | struct drm_device *dev = intel_crtc->base.dev; | |
6335 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6336 | uint32_t pipeconf; | |
6337 | ||
9f11a9e4 | 6338 | pipeconf = 0; |
84b046f3 | 6339 | |
b6b5d049 VS |
6340 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
6341 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
6342 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 6343 | |
cf532bb2 VS |
6344 | if (intel_crtc->config.double_wide) |
6345 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 6346 | |
ff9ce46e DV |
6347 | /* only g4x and later have fancy bpc/dither controls */ |
6348 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
6349 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6350 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
6351 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 6352 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 6353 | |
ff9ce46e DV |
6354 | switch (intel_crtc->config.pipe_bpp) { |
6355 | case 18: | |
6356 | pipeconf |= PIPECONF_6BPC; | |
6357 | break; | |
6358 | case 24: | |
6359 | pipeconf |= PIPECONF_8BPC; | |
6360 | break; | |
6361 | case 30: | |
6362 | pipeconf |= PIPECONF_10BPC; | |
6363 | break; | |
6364 | default: | |
6365 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
6366 | BUG(); | |
84b046f3 DV |
6367 | } |
6368 | } | |
6369 | ||
6370 | if (HAS_PIPE_CXSR(dev)) { | |
6371 | if (intel_crtc->lowfreq_avail) { | |
6372 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
6373 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
6374 | } else { | |
6375 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
6376 | } |
6377 | } | |
6378 | ||
efc2cfff VS |
6379 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6380 | if (INTEL_INFO(dev)->gen < 4 || | |
409ee761 | 6381 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
6382 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
6383 | else | |
6384 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
6385 | } else | |
84b046f3 DV |
6386 | pipeconf |= PIPECONF_PROGRESSIVE; |
6387 | ||
9f11a9e4 DV |
6388 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
6389 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 6390 | |
84b046f3 DV |
6391 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
6392 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
6393 | } | |
6394 | ||
d6dfee7a | 6395 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc) |
79e53945 | 6396 | { |
c7653199 | 6397 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 6398 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 6399 | int refclk, num_connectors = 0; |
652c393a | 6400 | intel_clock_t clock, reduced_clock; |
a16af721 | 6401 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 6402 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 6403 | struct intel_encoder *encoder; |
d4906093 | 6404 | const intel_limit_t *limit; |
79e53945 | 6405 | |
d0737e1d ACO |
6406 | for_each_intel_encoder(dev, encoder) { |
6407 | if (encoder->new_crtc != crtc) | |
6408 | continue; | |
6409 | ||
5eddb70b | 6410 | switch (encoder->type) { |
79e53945 JB |
6411 | case INTEL_OUTPUT_LVDS: |
6412 | is_lvds = true; | |
6413 | break; | |
e9fd1c02 JN |
6414 | case INTEL_OUTPUT_DSI: |
6415 | is_dsi = true; | |
6416 | break; | |
6847d71b PZ |
6417 | default: |
6418 | break; | |
79e53945 | 6419 | } |
43565a06 | 6420 | |
c751ce4f | 6421 | num_connectors++; |
79e53945 JB |
6422 | } |
6423 | ||
f2335330 | 6424 | if (is_dsi) |
5b18e57c | 6425 | return 0; |
f2335330 | 6426 | |
d0737e1d | 6427 | if (!crtc->new_config->clock_set) { |
409ee761 | 6428 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 6429 | |
e9fd1c02 JN |
6430 | /* |
6431 | * Returns a set of divisors for the desired target clock with | |
6432 | * the given refclk, or FALSE. The returned values represent | |
6433 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
6434 | * 2) / p1 / p2. | |
6435 | */ | |
409ee761 | 6436 | limit = intel_limit(crtc, refclk); |
c7653199 | 6437 | ok = dev_priv->display.find_dpll(limit, crtc, |
d0737e1d | 6438 | crtc->new_config->port_clock, |
e9fd1c02 | 6439 | refclk, NULL, &clock); |
f2335330 | 6440 | if (!ok) { |
e9fd1c02 JN |
6441 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6442 | return -EINVAL; | |
6443 | } | |
79e53945 | 6444 | |
f2335330 JN |
6445 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
6446 | /* | |
6447 | * Ensure we match the reduced clock's P to the target | |
6448 | * clock. If the clocks don't match, we can't switch | |
6449 | * the display clock by using the FP0/FP1. In such case | |
6450 | * we will disable the LVDS downclock feature. | |
6451 | */ | |
6452 | has_reduced_clock = | |
c7653199 | 6453 | dev_priv->display.find_dpll(limit, crtc, |
f2335330 JN |
6454 | dev_priv->lvds_downclock, |
6455 | refclk, &clock, | |
6456 | &reduced_clock); | |
6457 | } | |
6458 | /* Compat-code for transition, will disappear. */ | |
d0737e1d ACO |
6459 | crtc->new_config->dpll.n = clock.n; |
6460 | crtc->new_config->dpll.m1 = clock.m1; | |
6461 | crtc->new_config->dpll.m2 = clock.m2; | |
6462 | crtc->new_config->dpll.p1 = clock.p1; | |
6463 | crtc->new_config->dpll.p2 = clock.p2; | |
f47709a9 | 6464 | } |
7026d4ac | 6465 | |
e9fd1c02 | 6466 | if (IS_GEN2(dev)) { |
c7653199 | 6467 | i8xx_update_pll(crtc, |
2a8f64ca VP |
6468 | has_reduced_clock ? &reduced_clock : NULL, |
6469 | num_connectors); | |
9d556c99 | 6470 | } else if (IS_CHERRYVIEW(dev)) { |
d0737e1d | 6471 | chv_update_pll(crtc, crtc->new_config); |
e9fd1c02 | 6472 | } else if (IS_VALLEYVIEW(dev)) { |
d0737e1d | 6473 | vlv_update_pll(crtc, crtc->new_config); |
e9fd1c02 | 6474 | } else { |
c7653199 | 6475 | i9xx_update_pll(crtc, |
eb1cbe48 | 6476 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 6477 | num_connectors); |
e9fd1c02 | 6478 | } |
79e53945 | 6479 | |
c8f7a0db | 6480 | return 0; |
f564048e EA |
6481 | } |
6482 | ||
2fa2fe9a DV |
6483 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
6484 | struct intel_crtc_config *pipe_config) | |
6485 | { | |
6486 | struct drm_device *dev = crtc->base.dev; | |
6487 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6488 | uint32_t tmp; | |
6489 | ||
dc9e7dec VS |
6490 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
6491 | return; | |
6492 | ||
2fa2fe9a | 6493 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
6494 | if (!(tmp & PFIT_ENABLE)) |
6495 | return; | |
2fa2fe9a | 6496 | |
06922821 | 6497 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
6498 | if (INTEL_INFO(dev)->gen < 4) { |
6499 | if (crtc->pipe != PIPE_B) | |
6500 | return; | |
2fa2fe9a DV |
6501 | } else { |
6502 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
6503 | return; | |
6504 | } | |
6505 | ||
06922821 | 6506 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
6507 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
6508 | if (INTEL_INFO(dev)->gen < 5) | |
6509 | pipe_config->gmch_pfit.lvds_border_bits = | |
6510 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
6511 | } | |
6512 | ||
acbec814 JB |
6513 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
6514 | struct intel_crtc_config *pipe_config) | |
6515 | { | |
6516 | struct drm_device *dev = crtc->base.dev; | |
6517 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6518 | int pipe = pipe_config->cpu_transcoder; | |
6519 | intel_clock_t clock; | |
6520 | u32 mdiv; | |
662c6ecb | 6521 | int refclk = 100000; |
acbec814 | 6522 | |
f573de5a SK |
6523 | /* In case of MIPI DPLL will not even be used */ |
6524 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
6525 | return; | |
6526 | ||
acbec814 | 6527 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 6528 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
6529 | mutex_unlock(&dev_priv->dpio_lock); |
6530 | ||
6531 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
6532 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
6533 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
6534 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
6535 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
6536 | ||
f646628b | 6537 | vlv_clock(refclk, &clock); |
acbec814 | 6538 | |
f646628b VS |
6539 | /* clock.dot is the fast clock */ |
6540 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
6541 | } |
6542 | ||
1ad292b5 JB |
6543 | static void i9xx_get_plane_config(struct intel_crtc *crtc, |
6544 | struct intel_plane_config *plane_config) | |
6545 | { | |
6546 | struct drm_device *dev = crtc->base.dev; | |
6547 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6548 | u32 val, base, offset; | |
6549 | int pipe = crtc->pipe, plane = crtc->plane; | |
6550 | int fourcc, pixel_format; | |
6551 | int aligned_height; | |
6552 | ||
66e514c1 DA |
6553 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
6554 | if (!crtc->base.primary->fb) { | |
1ad292b5 JB |
6555 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
6556 | return; | |
6557 | } | |
6558 | ||
6559 | val = I915_READ(DSPCNTR(plane)); | |
6560 | ||
6561 | if (INTEL_INFO(dev)->gen >= 4) | |
6562 | if (val & DISPPLANE_TILED) | |
6563 | plane_config->tiled = true; | |
6564 | ||
6565 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
6566 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
6567 | crtc->base.primary->fb->pixel_format = fourcc; |
6568 | crtc->base.primary->fb->bits_per_pixel = | |
1ad292b5 JB |
6569 | drm_format_plane_cpp(fourcc, 0) * 8; |
6570 | ||
6571 | if (INTEL_INFO(dev)->gen >= 4) { | |
6572 | if (plane_config->tiled) | |
6573 | offset = I915_READ(DSPTILEOFF(plane)); | |
6574 | else | |
6575 | offset = I915_READ(DSPLINOFF(plane)); | |
6576 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
6577 | } else { | |
6578 | base = I915_READ(DSPADDR(plane)); | |
6579 | } | |
6580 | plane_config->base = base; | |
6581 | ||
6582 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
6583 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
6584 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
6585 | |
6586 | val = I915_READ(DSPSTRIDE(pipe)); | |
026b96e2 | 6587 | crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 6588 | |
66e514c1 | 6589 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
1ad292b5 JB |
6590 | plane_config->tiled); |
6591 | ||
1267a26b FF |
6592 | plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
6593 | aligned_height); | |
1ad292b5 JB |
6594 | |
6595 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
6596 | pipe, plane, crtc->base.primary->fb->width, |
6597 | crtc->base.primary->fb->height, | |
6598 | crtc->base.primary->fb->bits_per_pixel, base, | |
6599 | crtc->base.primary->fb->pitches[0], | |
1ad292b5 JB |
6600 | plane_config->size); |
6601 | ||
6602 | } | |
6603 | ||
70b23a98 VS |
6604 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
6605 | struct intel_crtc_config *pipe_config) | |
6606 | { | |
6607 | struct drm_device *dev = crtc->base.dev; | |
6608 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6609 | int pipe = pipe_config->cpu_transcoder; | |
6610 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
6611 | intel_clock_t clock; | |
6612 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
6613 | int refclk = 100000; | |
6614 | ||
6615 | mutex_lock(&dev_priv->dpio_lock); | |
6616 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
6617 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
6618 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
6619 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
6620 | mutex_unlock(&dev_priv->dpio_lock); | |
6621 | ||
6622 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
6623 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
6624 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
6625 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
6626 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
6627 | ||
6628 | chv_clock(refclk, &clock); | |
6629 | ||
6630 | /* clock.dot is the fast clock */ | |
6631 | pipe_config->port_clock = clock.dot / 5; | |
6632 | } | |
6633 | ||
0e8ffe1b DV |
6634 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
6635 | struct intel_crtc_config *pipe_config) | |
6636 | { | |
6637 | struct drm_device *dev = crtc->base.dev; | |
6638 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6639 | uint32_t tmp; | |
6640 | ||
f458ebbc DV |
6641 | if (!intel_display_power_is_enabled(dev_priv, |
6642 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
6643 | return false; |
6644 | ||
e143a21c | 6645 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6646 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6647 | |
0e8ffe1b DV |
6648 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6649 | if (!(tmp & PIPECONF_ENABLE)) | |
6650 | return false; | |
6651 | ||
42571aef VS |
6652 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
6653 | switch (tmp & PIPECONF_BPC_MASK) { | |
6654 | case PIPECONF_6BPC: | |
6655 | pipe_config->pipe_bpp = 18; | |
6656 | break; | |
6657 | case PIPECONF_8BPC: | |
6658 | pipe_config->pipe_bpp = 24; | |
6659 | break; | |
6660 | case PIPECONF_10BPC: | |
6661 | pipe_config->pipe_bpp = 30; | |
6662 | break; | |
6663 | default: | |
6664 | break; | |
6665 | } | |
6666 | } | |
6667 | ||
b5a9fa09 DV |
6668 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
6669 | pipe_config->limited_color_range = true; | |
6670 | ||
282740f7 VS |
6671 | if (INTEL_INFO(dev)->gen < 4) |
6672 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
6673 | ||
1bd1bd80 DV |
6674 | intel_get_pipe_timings(crtc, pipe_config); |
6675 | ||
2fa2fe9a DV |
6676 | i9xx_get_pfit_config(crtc, pipe_config); |
6677 | ||
6c49f241 DV |
6678 | if (INTEL_INFO(dev)->gen >= 4) { |
6679 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6680 | pipe_config->pixel_multiplier = | |
6681 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
6682 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 6683 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
6684 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
6685 | tmp = I915_READ(DPLL(crtc->pipe)); | |
6686 | pipe_config->pixel_multiplier = | |
6687 | ((tmp & SDVO_MULTIPLIER_MASK) | |
6688 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
6689 | } else { | |
6690 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
6691 | * port and will be fixed up in the encoder->get_config | |
6692 | * function. */ | |
6693 | pipe_config->pixel_multiplier = 1; | |
6694 | } | |
8bcc2795 DV |
6695 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
6696 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
6697 | /* |
6698 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
6699 | * on 830. Filter it out here so that we don't | |
6700 | * report errors due to that. | |
6701 | */ | |
6702 | if (IS_I830(dev)) | |
6703 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
6704 | ||
8bcc2795 DV |
6705 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
6706 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
6707 | } else { |
6708 | /* Mask out read-only status bits. */ | |
6709 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
6710 | DPLL_PORTC_READY_MASK | | |
6711 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 6712 | } |
6c49f241 | 6713 | |
70b23a98 VS |
6714 | if (IS_CHERRYVIEW(dev)) |
6715 | chv_crtc_clock_get(crtc, pipe_config); | |
6716 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
6717 | vlv_crtc_clock_get(crtc, pipe_config); |
6718 | else | |
6719 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 6720 | |
0e8ffe1b DV |
6721 | return true; |
6722 | } | |
6723 | ||
dde86e2d | 6724 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
6725 | { |
6726 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 6727 | struct intel_encoder *encoder; |
74cfd7ac | 6728 | u32 val, final; |
13d83a67 | 6729 | bool has_lvds = false; |
199e5d79 | 6730 | bool has_cpu_edp = false; |
199e5d79 | 6731 | bool has_panel = false; |
99eb6a01 KP |
6732 | bool has_ck505 = false; |
6733 | bool can_ssc = false; | |
13d83a67 JB |
6734 | |
6735 | /* We need to take the global config into account */ | |
b2784e15 | 6736 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
6737 | switch (encoder->type) { |
6738 | case INTEL_OUTPUT_LVDS: | |
6739 | has_panel = true; | |
6740 | has_lvds = true; | |
6741 | break; | |
6742 | case INTEL_OUTPUT_EDP: | |
6743 | has_panel = true; | |
2de6905f | 6744 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
6745 | has_cpu_edp = true; |
6746 | break; | |
6847d71b PZ |
6747 | default: |
6748 | break; | |
13d83a67 JB |
6749 | } |
6750 | } | |
6751 | ||
99eb6a01 | 6752 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 6753 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
6754 | can_ssc = has_ck505; |
6755 | } else { | |
6756 | has_ck505 = false; | |
6757 | can_ssc = true; | |
6758 | } | |
6759 | ||
2de6905f ID |
6760 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
6761 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
6762 | |
6763 | /* Ironlake: try to setup display ref clock before DPLL | |
6764 | * enabling. This is only under driver's control after | |
6765 | * PCH B stepping, previous chipset stepping should be | |
6766 | * ignoring this setting. | |
6767 | */ | |
74cfd7ac CW |
6768 | val = I915_READ(PCH_DREF_CONTROL); |
6769 | ||
6770 | /* As we must carefully and slowly disable/enable each source in turn, | |
6771 | * compute the final state we want first and check if we need to | |
6772 | * make any changes at all. | |
6773 | */ | |
6774 | final = val; | |
6775 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
6776 | if (has_ck505) | |
6777 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
6778 | else | |
6779 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
6780 | ||
6781 | final &= ~DREF_SSC_SOURCE_MASK; | |
6782 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
6783 | final &= ~DREF_SSC1_ENABLE; | |
6784 | ||
6785 | if (has_panel) { | |
6786 | final |= DREF_SSC_SOURCE_ENABLE; | |
6787 | ||
6788 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6789 | final |= DREF_SSC1_ENABLE; | |
6790 | ||
6791 | if (has_cpu_edp) { | |
6792 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6793 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
6794 | else | |
6795 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
6796 | } else | |
6797 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6798 | } else { | |
6799 | final |= DREF_SSC_SOURCE_DISABLE; | |
6800 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6801 | } | |
6802 | ||
6803 | if (final == val) | |
6804 | return; | |
6805 | ||
13d83a67 | 6806 | /* Always enable nonspread source */ |
74cfd7ac | 6807 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 6808 | |
99eb6a01 | 6809 | if (has_ck505) |
74cfd7ac | 6810 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 6811 | else |
74cfd7ac | 6812 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 6813 | |
199e5d79 | 6814 | if (has_panel) { |
74cfd7ac CW |
6815 | val &= ~DREF_SSC_SOURCE_MASK; |
6816 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 6817 | |
199e5d79 | 6818 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 6819 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6820 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 6821 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 6822 | } else |
74cfd7ac | 6823 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
6824 | |
6825 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 6826 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6827 | POSTING_READ(PCH_DREF_CONTROL); |
6828 | udelay(200); | |
6829 | ||
74cfd7ac | 6830 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
6831 | |
6832 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 6833 | if (has_cpu_edp) { |
99eb6a01 | 6834 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6835 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 6836 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 6837 | } else |
74cfd7ac | 6838 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 6839 | } else |
74cfd7ac | 6840 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6841 | |
74cfd7ac | 6842 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6843 | POSTING_READ(PCH_DREF_CONTROL); |
6844 | udelay(200); | |
6845 | } else { | |
6846 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
6847 | ||
74cfd7ac | 6848 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
6849 | |
6850 | /* Turn off CPU output */ | |
74cfd7ac | 6851 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6852 | |
74cfd7ac | 6853 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6854 | POSTING_READ(PCH_DREF_CONTROL); |
6855 | udelay(200); | |
6856 | ||
6857 | /* Turn off the SSC source */ | |
74cfd7ac CW |
6858 | val &= ~DREF_SSC_SOURCE_MASK; |
6859 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
6860 | |
6861 | /* Turn off SSC1 */ | |
74cfd7ac | 6862 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 6863 | |
74cfd7ac | 6864 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
6865 | POSTING_READ(PCH_DREF_CONTROL); |
6866 | udelay(200); | |
6867 | } | |
74cfd7ac CW |
6868 | |
6869 | BUG_ON(val != final); | |
13d83a67 JB |
6870 | } |
6871 | ||
f31f2d55 | 6872 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 6873 | { |
f31f2d55 | 6874 | uint32_t tmp; |
dde86e2d | 6875 | |
0ff066a9 PZ |
6876 | tmp = I915_READ(SOUTH_CHICKEN2); |
6877 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
6878 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6879 | |
0ff066a9 PZ |
6880 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
6881 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
6882 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 6883 | |
0ff066a9 PZ |
6884 | tmp = I915_READ(SOUTH_CHICKEN2); |
6885 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
6886 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6887 | |
0ff066a9 PZ |
6888 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
6889 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
6890 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
6891 | } |
6892 | ||
6893 | /* WaMPhyProgramming:hsw */ | |
6894 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
6895 | { | |
6896 | uint32_t tmp; | |
dde86e2d PZ |
6897 | |
6898 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
6899 | tmp &= ~(0xFF << 24); | |
6900 | tmp |= (0x12 << 24); | |
6901 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
6902 | ||
dde86e2d PZ |
6903 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
6904 | tmp |= (1 << 11); | |
6905 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
6906 | ||
6907 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
6908 | tmp |= (1 << 11); | |
6909 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
6910 | ||
dde86e2d PZ |
6911 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
6912 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6913 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
6914 | ||
6915 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
6916 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6917 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
6918 | ||
0ff066a9 PZ |
6919 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
6920 | tmp &= ~(7 << 13); | |
6921 | tmp |= (5 << 13); | |
6922 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 6923 | |
0ff066a9 PZ |
6924 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
6925 | tmp &= ~(7 << 13); | |
6926 | tmp |= (5 << 13); | |
6927 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
6928 | |
6929 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
6930 | tmp &= ~0xFF; | |
6931 | tmp |= 0x1C; | |
6932 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
6933 | ||
6934 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
6935 | tmp &= ~0xFF; | |
6936 | tmp |= 0x1C; | |
6937 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
6938 | ||
6939 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
6940 | tmp &= ~(0xFF << 16); | |
6941 | tmp |= (0x1C << 16); | |
6942 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
6943 | ||
6944 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
6945 | tmp &= ~(0xFF << 16); | |
6946 | tmp |= (0x1C << 16); | |
6947 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
6948 | ||
0ff066a9 PZ |
6949 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
6950 | tmp |= (1 << 27); | |
6951 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 6952 | |
0ff066a9 PZ |
6953 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
6954 | tmp |= (1 << 27); | |
6955 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 6956 | |
0ff066a9 PZ |
6957 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
6958 | tmp &= ~(0xF << 28); | |
6959 | tmp |= (4 << 28); | |
6960 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 6961 | |
0ff066a9 PZ |
6962 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
6963 | tmp &= ~(0xF << 28); | |
6964 | tmp |= (4 << 28); | |
6965 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
6966 | } |
6967 | ||
2fa86a1f PZ |
6968 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
6969 | * Programming" based on the parameters passed: | |
6970 | * - Sequence to enable CLKOUT_DP | |
6971 | * - Sequence to enable CLKOUT_DP without spread | |
6972 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
6973 | */ | |
6974 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
6975 | bool with_fdi) | |
f31f2d55 PZ |
6976 | { |
6977 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
6978 | uint32_t reg, tmp; |
6979 | ||
6980 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
6981 | with_spread = true; | |
6982 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
6983 | with_fdi, "LP PCH doesn't have FDI\n")) | |
6984 | with_fdi = false; | |
f31f2d55 PZ |
6985 | |
6986 | mutex_lock(&dev_priv->dpio_lock); | |
6987 | ||
6988 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6989 | tmp &= ~SBI_SSCCTL_DISABLE; | |
6990 | tmp |= SBI_SSCCTL_PATHALT; | |
6991 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6992 | ||
6993 | udelay(24); | |
6994 | ||
2fa86a1f PZ |
6995 | if (with_spread) { |
6996 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6997 | tmp &= ~SBI_SSCCTL_PATHALT; | |
6998 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 6999 | |
2fa86a1f PZ |
7000 | if (with_fdi) { |
7001 | lpt_reset_fdi_mphy(dev_priv); | |
7002 | lpt_program_fdi_mphy(dev_priv); | |
7003 | } | |
7004 | } | |
dde86e2d | 7005 | |
2fa86a1f PZ |
7006 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
7007 | SBI_GEN0 : SBI_DBUFF0; | |
7008 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7009 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7010 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
7011 | |
7012 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
7013 | } |
7014 | ||
47701c3b PZ |
7015 | /* Sequence to disable CLKOUT_DP */ |
7016 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
7017 | { | |
7018 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7019 | uint32_t reg, tmp; | |
7020 | ||
7021 | mutex_lock(&dev_priv->dpio_lock); | |
7022 | ||
7023 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
7024 | SBI_GEN0 : SBI_DBUFF0; | |
7025 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
7026 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7027 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
7028 | ||
7029 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7030 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
7031 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
7032 | tmp |= SBI_SSCCTL_PATHALT; | |
7033 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7034 | udelay(32); | |
7035 | } | |
7036 | tmp |= SBI_SSCCTL_DISABLE; | |
7037 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7038 | } | |
7039 | ||
7040 | mutex_unlock(&dev_priv->dpio_lock); | |
7041 | } | |
7042 | ||
bf8fa3d3 PZ |
7043 | static void lpt_init_pch_refclk(struct drm_device *dev) |
7044 | { | |
bf8fa3d3 PZ |
7045 | struct intel_encoder *encoder; |
7046 | bool has_vga = false; | |
7047 | ||
b2784e15 | 7048 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
7049 | switch (encoder->type) { |
7050 | case INTEL_OUTPUT_ANALOG: | |
7051 | has_vga = true; | |
7052 | break; | |
6847d71b PZ |
7053 | default: |
7054 | break; | |
bf8fa3d3 PZ |
7055 | } |
7056 | } | |
7057 | ||
47701c3b PZ |
7058 | if (has_vga) |
7059 | lpt_enable_clkout_dp(dev, true, true); | |
7060 | else | |
7061 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
7062 | } |
7063 | ||
dde86e2d PZ |
7064 | /* |
7065 | * Initialize reference clocks when the driver loads | |
7066 | */ | |
7067 | void intel_init_pch_refclk(struct drm_device *dev) | |
7068 | { | |
7069 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7070 | ironlake_init_pch_refclk(dev); | |
7071 | else if (HAS_PCH_LPT(dev)) | |
7072 | lpt_init_pch_refclk(dev); | |
7073 | } | |
7074 | ||
d9d444cb JB |
7075 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
7076 | { | |
7077 | struct drm_device *dev = crtc->dev; | |
7078 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7079 | struct intel_encoder *encoder; | |
d9d444cb JB |
7080 | int num_connectors = 0; |
7081 | bool is_lvds = false; | |
7082 | ||
d0737e1d ACO |
7083 | for_each_intel_encoder(dev, encoder) { |
7084 | if (encoder->new_crtc != to_intel_crtc(crtc)) | |
7085 | continue; | |
7086 | ||
d9d444cb JB |
7087 | switch (encoder->type) { |
7088 | case INTEL_OUTPUT_LVDS: | |
7089 | is_lvds = true; | |
7090 | break; | |
6847d71b PZ |
7091 | default: |
7092 | break; | |
d9d444cb JB |
7093 | } |
7094 | num_connectors++; | |
7095 | } | |
7096 | ||
7097 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 7098 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 7099 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 7100 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
7101 | } |
7102 | ||
7103 | return 120000; | |
7104 | } | |
7105 | ||
6ff93609 | 7106 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 7107 | { |
c8203565 | 7108 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
7109 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7110 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
7111 | uint32_t val; |
7112 | ||
78114071 | 7113 | val = 0; |
c8203565 | 7114 | |
965e0c48 | 7115 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 7116 | case 18: |
dfd07d72 | 7117 | val |= PIPECONF_6BPC; |
c8203565 PZ |
7118 | break; |
7119 | case 24: | |
dfd07d72 | 7120 | val |= PIPECONF_8BPC; |
c8203565 PZ |
7121 | break; |
7122 | case 30: | |
dfd07d72 | 7123 | val |= PIPECONF_10BPC; |
c8203565 PZ |
7124 | break; |
7125 | case 36: | |
dfd07d72 | 7126 | val |= PIPECONF_12BPC; |
c8203565 PZ |
7127 | break; |
7128 | default: | |
cc769b62 PZ |
7129 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
7130 | BUG(); | |
c8203565 PZ |
7131 | } |
7132 | ||
d8b32247 | 7133 | if (intel_crtc->config.dither) |
c8203565 PZ |
7134 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7135 | ||
6ff93609 | 7136 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
7137 | val |= PIPECONF_INTERLACED_ILK; |
7138 | else | |
7139 | val |= PIPECONF_PROGRESSIVE; | |
7140 | ||
50f3b016 | 7141 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 7142 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 7143 | |
c8203565 PZ |
7144 | I915_WRITE(PIPECONF(pipe), val); |
7145 | POSTING_READ(PIPECONF(pipe)); | |
7146 | } | |
7147 | ||
86d3efce VS |
7148 | /* |
7149 | * Set up the pipe CSC unit. | |
7150 | * | |
7151 | * Currently only full range RGB to limited range RGB conversion | |
7152 | * is supported, but eventually this should handle various | |
7153 | * RGB<->YCbCr scenarios as well. | |
7154 | */ | |
50f3b016 | 7155 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
7156 | { |
7157 | struct drm_device *dev = crtc->dev; | |
7158 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7159 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7160 | int pipe = intel_crtc->pipe; | |
7161 | uint16_t coeff = 0x7800; /* 1.0 */ | |
7162 | ||
7163 | /* | |
7164 | * TODO: Check what kind of values actually come out of the pipe | |
7165 | * with these coeff/postoff values and adjust to get the best | |
7166 | * accuracy. Perhaps we even need to take the bpc value into | |
7167 | * consideration. | |
7168 | */ | |
7169 | ||
50f3b016 | 7170 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
7171 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
7172 | ||
7173 | /* | |
7174 | * GY/GU and RY/RU should be the other way around according | |
7175 | * to BSpec, but reality doesn't agree. Just set them up in | |
7176 | * a way that results in the correct picture. | |
7177 | */ | |
7178 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
7179 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
7180 | ||
7181 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
7182 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
7183 | ||
7184 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
7185 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
7186 | ||
7187 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
7188 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
7189 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
7190 | ||
7191 | if (INTEL_INFO(dev)->gen > 6) { | |
7192 | uint16_t postoff = 0; | |
7193 | ||
50f3b016 | 7194 | if (intel_crtc->config.limited_color_range) |
32cf0cb0 | 7195 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
7196 | |
7197 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
7198 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
7199 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
7200 | ||
7201 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
7202 | } else { | |
7203 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
7204 | ||
50f3b016 | 7205 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
7206 | mode |= CSC_BLACK_SCREEN_OFFSET; |
7207 | ||
7208 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
7209 | } | |
7210 | } | |
7211 | ||
6ff93609 | 7212 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 7213 | { |
756f85cf PZ |
7214 | struct drm_device *dev = crtc->dev; |
7215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 7216 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 7217 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 7218 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
7219 | uint32_t val; |
7220 | ||
3eff4faa | 7221 | val = 0; |
ee2b0b38 | 7222 | |
756f85cf | 7223 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
7224 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7225 | ||
6ff93609 | 7226 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
7227 | val |= PIPECONF_INTERLACED_ILK; |
7228 | else | |
7229 | val |= PIPECONF_PROGRESSIVE; | |
7230 | ||
702e7a56 PZ |
7231 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
7232 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
7233 | |
7234 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
7235 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 7236 | |
3cdf122c | 7237 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
7238 | val = 0; |
7239 | ||
7240 | switch (intel_crtc->config.pipe_bpp) { | |
7241 | case 18: | |
7242 | val |= PIPEMISC_DITHER_6_BPC; | |
7243 | break; | |
7244 | case 24: | |
7245 | val |= PIPEMISC_DITHER_8_BPC; | |
7246 | break; | |
7247 | case 30: | |
7248 | val |= PIPEMISC_DITHER_10_BPC; | |
7249 | break; | |
7250 | case 36: | |
7251 | val |= PIPEMISC_DITHER_12_BPC; | |
7252 | break; | |
7253 | default: | |
7254 | /* Case prevented by pipe_config_set_bpp. */ | |
7255 | BUG(); | |
7256 | } | |
7257 | ||
7258 | if (intel_crtc->config.dither) | |
7259 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
7260 | ||
7261 | I915_WRITE(PIPEMISC(pipe), val); | |
7262 | } | |
ee2b0b38 PZ |
7263 | } |
7264 | ||
6591c6e4 | 7265 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
7266 | intel_clock_t *clock, |
7267 | bool *has_reduced_clock, | |
7268 | intel_clock_t *reduced_clock) | |
7269 | { | |
7270 | struct drm_device *dev = crtc->dev; | |
7271 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a919ff14 | 7272 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6591c6e4 | 7273 | int refclk; |
d4906093 | 7274 | const intel_limit_t *limit; |
a16af721 | 7275 | bool ret, is_lvds = false; |
79e53945 | 7276 | |
d0737e1d | 7277 | is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 7278 | |
d9d444cb | 7279 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 7280 | |
d4906093 ML |
7281 | /* |
7282 | * Returns a set of divisors for the desired target clock with the given | |
7283 | * refclk, or FALSE. The returned values represent the clock equation: | |
7284 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
7285 | */ | |
409ee761 | 7286 | limit = intel_limit(intel_crtc, refclk); |
a919ff14 | 7287 | ret = dev_priv->display.find_dpll(limit, intel_crtc, |
d0737e1d | 7288 | intel_crtc->new_config->port_clock, |
ee9300bb | 7289 | refclk, NULL, clock); |
6591c6e4 PZ |
7290 | if (!ret) |
7291 | return false; | |
cda4b7d3 | 7292 | |
ddc9003c | 7293 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
7294 | /* |
7295 | * Ensure we match the reduced clock's P to the target clock. | |
7296 | * If the clocks don't match, we can't switch the display clock | |
7297 | * by using the FP0/FP1. In such case we will disable the LVDS | |
7298 | * downclock feature. | |
7299 | */ | |
ee9300bb | 7300 | *has_reduced_clock = |
a919ff14 | 7301 | dev_priv->display.find_dpll(limit, intel_crtc, |
ee9300bb DV |
7302 | dev_priv->lvds_downclock, |
7303 | refclk, clock, | |
7304 | reduced_clock); | |
652c393a | 7305 | } |
61e9653f | 7306 | |
6591c6e4 PZ |
7307 | return true; |
7308 | } | |
7309 | ||
d4b1931c PZ |
7310 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
7311 | { | |
7312 | /* | |
7313 | * Account for spread spectrum to avoid | |
7314 | * oversubscribing the link. Max center spread | |
7315 | * is 2.5%; use 5% for safety's sake. | |
7316 | */ | |
7317 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 7318 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
7319 | } |
7320 | ||
7429e9d4 | 7321 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 7322 | { |
7429e9d4 | 7323 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
7324 | } |
7325 | ||
de13a2e3 | 7326 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 7327 | u32 *fp, |
9a7c7890 | 7328 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 7329 | { |
de13a2e3 | 7330 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
7331 | struct drm_device *dev = crtc->dev; |
7332 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
7333 | struct intel_encoder *intel_encoder; |
7334 | uint32_t dpll; | |
6cc5f341 | 7335 | int factor, num_connectors = 0; |
09ede541 | 7336 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 7337 | |
d0737e1d ACO |
7338 | for_each_intel_encoder(dev, intel_encoder) { |
7339 | if (intel_encoder->new_crtc != to_intel_crtc(crtc)) | |
7340 | continue; | |
7341 | ||
de13a2e3 | 7342 | switch (intel_encoder->type) { |
79e53945 JB |
7343 | case INTEL_OUTPUT_LVDS: |
7344 | is_lvds = true; | |
7345 | break; | |
7346 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 7347 | case INTEL_OUTPUT_HDMI: |
79e53945 | 7348 | is_sdvo = true; |
79e53945 | 7349 | break; |
6847d71b PZ |
7350 | default: |
7351 | break; | |
79e53945 | 7352 | } |
43565a06 | 7353 | |
c751ce4f | 7354 | num_connectors++; |
79e53945 | 7355 | } |
79e53945 | 7356 | |
c1858123 | 7357 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
7358 | factor = 21; |
7359 | if (is_lvds) { | |
7360 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 7361 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 7362 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 7363 | factor = 25; |
d0737e1d | 7364 | } else if (intel_crtc->new_config->sdvo_tv_clock) |
8febb297 | 7365 | factor = 20; |
c1858123 | 7366 | |
d0737e1d | 7367 | if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor)) |
7d0ac5b7 | 7368 | *fp |= FP_CB_TUNE; |
2c07245f | 7369 | |
9a7c7890 DV |
7370 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
7371 | *fp2 |= FP_CB_TUNE; | |
7372 | ||
5eddb70b | 7373 | dpll = 0; |
2c07245f | 7374 | |
a07d6787 EA |
7375 | if (is_lvds) |
7376 | dpll |= DPLLB_MODE_LVDS; | |
7377 | else | |
7378 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 7379 | |
d0737e1d | 7380 | dpll |= (intel_crtc->new_config->pixel_multiplier - 1) |
ef1b460d | 7381 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
7382 | |
7383 | if (is_sdvo) | |
4a33e48d | 7384 | dpll |= DPLL_SDVO_HIGH_SPEED; |
d0737e1d | 7385 | if (intel_crtc->new_config->has_dp_encoder) |
4a33e48d | 7386 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 7387 | |
a07d6787 | 7388 | /* compute bitmask from p1 value */ |
d0737e1d | 7389 | dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 7390 | /* also FPA1 */ |
d0737e1d | 7391 | dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 7392 | |
d0737e1d | 7393 | switch (intel_crtc->new_config->dpll.p2) { |
a07d6787 EA |
7394 | case 5: |
7395 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7396 | break; | |
7397 | case 7: | |
7398 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7399 | break; | |
7400 | case 10: | |
7401 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7402 | break; | |
7403 | case 14: | |
7404 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7405 | break; | |
79e53945 JB |
7406 | } |
7407 | ||
b4c09f3b | 7408 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 7409 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
7410 | else |
7411 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7412 | ||
959e16d6 | 7413 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
7414 | } |
7415 | ||
3fb37703 | 7416 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc) |
de13a2e3 | 7417 | { |
c7653199 | 7418 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 7419 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 7420 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 7421 | bool ok, has_reduced_clock = false; |
8b47047b | 7422 | bool is_lvds = false; |
e2b78267 | 7423 | struct intel_shared_dpll *pll; |
de13a2e3 | 7424 | |
409ee761 | 7425 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 7426 | |
5dc5298b PZ |
7427 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
7428 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 7429 | |
c7653199 | 7430 | ok = ironlake_compute_clocks(&crtc->base, &clock, |
de13a2e3 | 7431 | &has_reduced_clock, &reduced_clock); |
d0737e1d | 7432 | if (!ok && !crtc->new_config->clock_set) { |
de13a2e3 PZ |
7433 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7434 | return -EINVAL; | |
79e53945 | 7435 | } |
f47709a9 | 7436 | /* Compat-code for transition, will disappear. */ |
d0737e1d ACO |
7437 | if (!crtc->new_config->clock_set) { |
7438 | crtc->new_config->dpll.n = clock.n; | |
7439 | crtc->new_config->dpll.m1 = clock.m1; | |
7440 | crtc->new_config->dpll.m2 = clock.m2; | |
7441 | crtc->new_config->dpll.p1 = clock.p1; | |
7442 | crtc->new_config->dpll.p2 = clock.p2; | |
f47709a9 | 7443 | } |
79e53945 | 7444 | |
5dc5298b | 7445 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
d0737e1d ACO |
7446 | if (crtc->new_config->has_pch_encoder) { |
7447 | fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll); | |
cbbab5bd | 7448 | if (has_reduced_clock) |
7429e9d4 | 7449 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 7450 | |
c7653199 | 7451 | dpll = ironlake_compute_dpll(crtc, |
cbbab5bd DV |
7452 | &fp, &reduced_clock, |
7453 | has_reduced_clock ? &fp2 : NULL); | |
7454 | ||
d0737e1d ACO |
7455 | crtc->new_config->dpll_hw_state.dpll = dpll; |
7456 | crtc->new_config->dpll_hw_state.fp0 = fp; | |
66e985c0 | 7457 | if (has_reduced_clock) |
d0737e1d | 7458 | crtc->new_config->dpll_hw_state.fp1 = fp2; |
66e985c0 | 7459 | else |
d0737e1d | 7460 | crtc->new_config->dpll_hw_state.fp1 = fp; |
66e985c0 | 7461 | |
c7653199 | 7462 | pll = intel_get_shared_dpll(crtc); |
ee7b9f93 | 7463 | if (pll == NULL) { |
84f44ce7 | 7464 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 7465 | pipe_name(crtc->pipe)); |
4b645f14 JB |
7466 | return -EINVAL; |
7467 | } | |
3fb37703 | 7468 | } |
79e53945 | 7469 | |
d330a953 | 7470 | if (is_lvds && has_reduced_clock && i915.powersave) |
c7653199 | 7471 | crtc->lowfreq_avail = true; |
bcd644e0 | 7472 | else |
c7653199 | 7473 | crtc->lowfreq_avail = false; |
e2b78267 | 7474 | |
c8f7a0db | 7475 | return 0; |
79e53945 JB |
7476 | } |
7477 | ||
eb14cb74 VS |
7478 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
7479 | struct intel_link_m_n *m_n) | |
7480 | { | |
7481 | struct drm_device *dev = crtc->base.dev; | |
7482 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7483 | enum pipe pipe = crtc->pipe; | |
7484 | ||
7485 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
7486 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
7487 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7488 | & ~TU_SIZE_MASK; | |
7489 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
7490 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7491 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7492 | } | |
7493 | ||
7494 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
7495 | enum transcoder transcoder, | |
b95af8be VK |
7496 | struct intel_link_m_n *m_n, |
7497 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
7498 | { |
7499 | struct drm_device *dev = crtc->base.dev; | |
7500 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 7501 | enum pipe pipe = crtc->pipe; |
72419203 | 7502 | |
eb14cb74 VS |
7503 | if (INTEL_INFO(dev)->gen >= 5) { |
7504 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
7505 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
7506 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
7507 | & ~TU_SIZE_MASK; | |
7508 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
7509 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
7510 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
7511 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
7512 | * gen < 8) and if DRRS is supported (to make sure the | |
7513 | * registers are not unnecessarily read). | |
7514 | */ | |
7515 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
7516 | crtc->config.has_drrs) { | |
7517 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); | |
7518 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
7519 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
7520 | & ~TU_SIZE_MASK; | |
7521 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
7522 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
7523 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7524 | } | |
eb14cb74 VS |
7525 | } else { |
7526 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
7527 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
7528 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7529 | & ~TU_SIZE_MASK; | |
7530 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
7531 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7532 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7533 | } | |
7534 | } | |
7535 | ||
7536 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
7537 | struct intel_crtc_config *pipe_config) | |
7538 | { | |
7539 | if (crtc->config.has_pch_encoder) | |
7540 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
7541 | else | |
7542 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
7543 | &pipe_config->dp_m_n, |
7544 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 7545 | } |
72419203 | 7546 | |
eb14cb74 VS |
7547 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
7548 | struct intel_crtc_config *pipe_config) | |
7549 | { | |
7550 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 7551 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
7552 | } |
7553 | ||
bd2e244f JB |
7554 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
7555 | struct intel_crtc_config *pipe_config) | |
7556 | { | |
7557 | struct drm_device *dev = crtc->base.dev; | |
7558 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7559 | uint32_t tmp; | |
7560 | ||
7561 | tmp = I915_READ(PS_CTL(crtc->pipe)); | |
7562 | ||
7563 | if (tmp & PS_ENABLE) { | |
7564 | pipe_config->pch_pfit.enabled = true; | |
7565 | pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe)); | |
7566 | pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe)); | |
7567 | } | |
7568 | } | |
7569 | ||
2fa2fe9a DV |
7570 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
7571 | struct intel_crtc_config *pipe_config) | |
7572 | { | |
7573 | struct drm_device *dev = crtc->base.dev; | |
7574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7575 | uint32_t tmp; | |
7576 | ||
7577 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
7578 | ||
7579 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 7580 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
7581 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
7582 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
7583 | |
7584 | /* We currently do not free assignements of panel fitters on | |
7585 | * ivb/hsw (since we don't use the higher upscaling modes which | |
7586 | * differentiates them) so just WARN about this case for now. */ | |
7587 | if (IS_GEN7(dev)) { | |
7588 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
7589 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
7590 | } | |
2fa2fe9a | 7591 | } |
79e53945 JB |
7592 | } |
7593 | ||
4c6baa59 JB |
7594 | static void ironlake_get_plane_config(struct intel_crtc *crtc, |
7595 | struct intel_plane_config *plane_config) | |
7596 | { | |
7597 | struct drm_device *dev = crtc->base.dev; | |
7598 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7599 | u32 val, base, offset; | |
7600 | int pipe = crtc->pipe, plane = crtc->plane; | |
7601 | int fourcc, pixel_format; | |
7602 | int aligned_height; | |
7603 | ||
66e514c1 DA |
7604 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
7605 | if (!crtc->base.primary->fb) { | |
4c6baa59 JB |
7606 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7607 | return; | |
7608 | } | |
7609 | ||
7610 | val = I915_READ(DSPCNTR(plane)); | |
7611 | ||
7612 | if (INTEL_INFO(dev)->gen >= 4) | |
7613 | if (val & DISPPLANE_TILED) | |
7614 | plane_config->tiled = true; | |
7615 | ||
7616 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
7617 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
7618 | crtc->base.primary->fb->pixel_format = fourcc; |
7619 | crtc->base.primary->fb->bits_per_pixel = | |
4c6baa59 JB |
7620 | drm_format_plane_cpp(fourcc, 0) * 8; |
7621 | ||
7622 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7623 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
7624 | offset = I915_READ(DSPOFFSET(plane)); | |
7625 | } else { | |
7626 | if (plane_config->tiled) | |
7627 | offset = I915_READ(DSPTILEOFF(plane)); | |
7628 | else | |
7629 | offset = I915_READ(DSPLINOFF(plane)); | |
7630 | } | |
7631 | plane_config->base = base; | |
7632 | ||
7633 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
7634 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
7635 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
7636 | |
7637 | val = I915_READ(DSPSTRIDE(pipe)); | |
026b96e2 | 7638 | crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 7639 | |
66e514c1 | 7640 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
4c6baa59 JB |
7641 | plane_config->tiled); |
7642 | ||
1267a26b FF |
7643 | plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
7644 | aligned_height); | |
4c6baa59 JB |
7645 | |
7646 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
7647 | pipe, plane, crtc->base.primary->fb->width, |
7648 | crtc->base.primary->fb->height, | |
7649 | crtc->base.primary->fb->bits_per_pixel, base, | |
7650 | crtc->base.primary->fb->pitches[0], | |
4c6baa59 JB |
7651 | plane_config->size); |
7652 | } | |
7653 | ||
0e8ffe1b DV |
7654 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
7655 | struct intel_crtc_config *pipe_config) | |
7656 | { | |
7657 | struct drm_device *dev = crtc->base.dev; | |
7658 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7659 | uint32_t tmp; | |
7660 | ||
f458ebbc DV |
7661 | if (!intel_display_power_is_enabled(dev_priv, |
7662 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
7663 | return false; |
7664 | ||
e143a21c | 7665 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7666 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7667 | |
0e8ffe1b DV |
7668 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7669 | if (!(tmp & PIPECONF_ENABLE)) | |
7670 | return false; | |
7671 | ||
42571aef VS |
7672 | switch (tmp & PIPECONF_BPC_MASK) { |
7673 | case PIPECONF_6BPC: | |
7674 | pipe_config->pipe_bpp = 18; | |
7675 | break; | |
7676 | case PIPECONF_8BPC: | |
7677 | pipe_config->pipe_bpp = 24; | |
7678 | break; | |
7679 | case PIPECONF_10BPC: | |
7680 | pipe_config->pipe_bpp = 30; | |
7681 | break; | |
7682 | case PIPECONF_12BPC: | |
7683 | pipe_config->pipe_bpp = 36; | |
7684 | break; | |
7685 | default: | |
7686 | break; | |
7687 | } | |
7688 | ||
b5a9fa09 DV |
7689 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
7690 | pipe_config->limited_color_range = true; | |
7691 | ||
ab9412ba | 7692 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
7693 | struct intel_shared_dpll *pll; |
7694 | ||
88adfff1 DV |
7695 | pipe_config->has_pch_encoder = true; |
7696 | ||
627eb5a3 DV |
7697 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
7698 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7699 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7700 | |
7701 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 7702 | |
c0d43d62 | 7703 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
7704 | pipe_config->shared_dpll = |
7705 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
7706 | } else { |
7707 | tmp = I915_READ(PCH_DPLL_SEL); | |
7708 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
7709 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
7710 | else | |
7711 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
7712 | } | |
66e985c0 DV |
7713 | |
7714 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
7715 | ||
7716 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
7717 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
7718 | |
7719 | tmp = pipe_config->dpll_hw_state.dpll; | |
7720 | pipe_config->pixel_multiplier = | |
7721 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
7722 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
7723 | |
7724 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
7725 | } else { |
7726 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
7727 | } |
7728 | ||
1bd1bd80 DV |
7729 | intel_get_pipe_timings(crtc, pipe_config); |
7730 | ||
2fa2fe9a DV |
7731 | ironlake_get_pfit_config(crtc, pipe_config); |
7732 | ||
0e8ffe1b DV |
7733 | return true; |
7734 | } | |
7735 | ||
be256dc7 PZ |
7736 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
7737 | { | |
7738 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 7739 | struct intel_crtc *crtc; |
be256dc7 | 7740 | |
d3fcc808 | 7741 | for_each_intel_crtc(dev, crtc) |
798183c5 | 7742 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
7743 | pipe_name(crtc->pipe)); |
7744 | ||
7745 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
8cc3e169 DV |
7746 | WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); |
7747 | WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
7748 | WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
be256dc7 PZ |
7749 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
7750 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
7751 | "CPU PWM1 enabled\n"); | |
c5107b87 PZ |
7752 | if (IS_HASWELL(dev)) |
7753 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
7754 | "CPU PWM2 enabled\n"); | |
be256dc7 PZ |
7755 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
7756 | "PCH PWM1 enabled\n"); | |
7757 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
7758 | "Utility pin enabled\n"); | |
7759 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
7760 | ||
9926ada1 PZ |
7761 | /* |
7762 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
7763 | * interrupts remain enabled. We used to check for that, but since it's | |
7764 | * gen-specific and since we only disable LCPLL after we fully disable | |
7765 | * the interrupts, the check below should be enough. | |
7766 | */ | |
9df7575f | 7767 | WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
7768 | } |
7769 | ||
9ccd5aeb PZ |
7770 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
7771 | { | |
7772 | struct drm_device *dev = dev_priv->dev; | |
7773 | ||
7774 | if (IS_HASWELL(dev)) | |
7775 | return I915_READ(D_COMP_HSW); | |
7776 | else | |
7777 | return I915_READ(D_COMP_BDW); | |
7778 | } | |
7779 | ||
3c4c9b81 PZ |
7780 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
7781 | { | |
7782 | struct drm_device *dev = dev_priv->dev; | |
7783 | ||
7784 | if (IS_HASWELL(dev)) { | |
7785 | mutex_lock(&dev_priv->rps.hw_lock); | |
7786 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
7787 | val)) | |
f475dadf | 7788 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
7789 | mutex_unlock(&dev_priv->rps.hw_lock); |
7790 | } else { | |
9ccd5aeb PZ |
7791 | I915_WRITE(D_COMP_BDW, val); |
7792 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 7793 | } |
be256dc7 PZ |
7794 | } |
7795 | ||
7796 | /* | |
7797 | * This function implements pieces of two sequences from BSpec: | |
7798 | * - Sequence for display software to disable LCPLL | |
7799 | * - Sequence for display software to allow package C8+ | |
7800 | * The steps implemented here are just the steps that actually touch the LCPLL | |
7801 | * register. Callers should take care of disabling all the display engine | |
7802 | * functions, doing the mode unset, fixing interrupts, etc. | |
7803 | */ | |
6ff58d53 PZ |
7804 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
7805 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
7806 | { |
7807 | uint32_t val; | |
7808 | ||
7809 | assert_can_disable_lcpll(dev_priv); | |
7810 | ||
7811 | val = I915_READ(LCPLL_CTL); | |
7812 | ||
7813 | if (switch_to_fclk) { | |
7814 | val |= LCPLL_CD_SOURCE_FCLK; | |
7815 | I915_WRITE(LCPLL_CTL, val); | |
7816 | ||
7817 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
7818 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
7819 | DRM_ERROR("Switching to FCLK failed\n"); | |
7820 | ||
7821 | val = I915_READ(LCPLL_CTL); | |
7822 | } | |
7823 | ||
7824 | val |= LCPLL_PLL_DISABLE; | |
7825 | I915_WRITE(LCPLL_CTL, val); | |
7826 | POSTING_READ(LCPLL_CTL); | |
7827 | ||
7828 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
7829 | DRM_ERROR("LCPLL still locked\n"); | |
7830 | ||
9ccd5aeb | 7831 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 7832 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 7833 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7834 | ndelay(100); |
7835 | ||
9ccd5aeb PZ |
7836 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
7837 | 1)) | |
be256dc7 PZ |
7838 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
7839 | ||
7840 | if (allow_power_down) { | |
7841 | val = I915_READ(LCPLL_CTL); | |
7842 | val |= LCPLL_POWER_DOWN_ALLOW; | |
7843 | I915_WRITE(LCPLL_CTL, val); | |
7844 | POSTING_READ(LCPLL_CTL); | |
7845 | } | |
7846 | } | |
7847 | ||
7848 | /* | |
7849 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
7850 | * source. | |
7851 | */ | |
6ff58d53 | 7852 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
7853 | { |
7854 | uint32_t val; | |
7855 | ||
7856 | val = I915_READ(LCPLL_CTL); | |
7857 | ||
7858 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
7859 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
7860 | return; | |
7861 | ||
a8a8bd54 PZ |
7862 | /* |
7863 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
7864 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
7865 | * | |
7866 | * The other problem is that hsw_restore_lcpll() is called as part of | |
7867 | * the runtime PM resume sequence, so we can't just call | |
7868 | * gen6_gt_force_wake_get() because that function calls | |
7869 | * intel_runtime_pm_get(), and we can't change the runtime PM refcount | |
7870 | * while we are on the resume sequence. So to solve this problem we have | |
7871 | * to call special forcewake code that doesn't touch runtime PM and | |
7872 | * doesn't enable the forcewake delayed work. | |
7873 | */ | |
d2e40e27 | 7874 | spin_lock_irq(&dev_priv->uncore.lock); |
a8a8bd54 PZ |
7875 | if (dev_priv->uncore.forcewake_count++ == 0) |
7876 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); | |
d2e40e27 | 7877 | spin_unlock_irq(&dev_priv->uncore.lock); |
215733fa | 7878 | |
be256dc7 PZ |
7879 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
7880 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
7881 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 7882 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
7883 | } |
7884 | ||
9ccd5aeb | 7885 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
7886 | val |= D_COMP_COMP_FORCE; |
7887 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7888 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7889 | |
7890 | val = I915_READ(LCPLL_CTL); | |
7891 | val &= ~LCPLL_PLL_DISABLE; | |
7892 | I915_WRITE(LCPLL_CTL, val); | |
7893 | ||
7894 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
7895 | DRM_ERROR("LCPLL not locked yet\n"); | |
7896 | ||
7897 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
7898 | val = I915_READ(LCPLL_CTL); | |
7899 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
7900 | I915_WRITE(LCPLL_CTL, val); | |
7901 | ||
7902 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
7903 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
7904 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
7905 | } | |
215733fa | 7906 | |
a8a8bd54 | 7907 | /* See the big comment above. */ |
d2e40e27 | 7908 | spin_lock_irq(&dev_priv->uncore.lock); |
a8a8bd54 PZ |
7909 | if (--dev_priv->uncore.forcewake_count == 0) |
7910 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); | |
d2e40e27 | 7911 | spin_unlock_irq(&dev_priv->uncore.lock); |
be256dc7 PZ |
7912 | } |
7913 | ||
765dab67 PZ |
7914 | /* |
7915 | * Package states C8 and deeper are really deep PC states that can only be | |
7916 | * reached when all the devices on the system allow it, so even if the graphics | |
7917 | * device allows PC8+, it doesn't mean the system will actually get to these | |
7918 | * states. Our driver only allows PC8+ when going into runtime PM. | |
7919 | * | |
7920 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
7921 | * well is disabled and most interrupts are disabled, and these are also | |
7922 | * requirements for runtime PM. When these conditions are met, we manually do | |
7923 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
7924 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
7925 | * hang the machine. | |
7926 | * | |
7927 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
7928 | * the state of some registers, so when we come back from PC8+ we need to | |
7929 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
7930 | * need to take care of the registers kept by RC6. Notice that this happens even | |
7931 | * if we don't put the device in PCI D3 state (which is what currently happens | |
7932 | * because of the runtime PM support). | |
7933 | * | |
7934 | * For more, read "Display Sequences for Package C8" on the hardware | |
7935 | * documentation. | |
7936 | */ | |
a14cb6fc | 7937 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 7938 | { |
c67a470b PZ |
7939 | struct drm_device *dev = dev_priv->dev; |
7940 | uint32_t val; | |
7941 | ||
c67a470b PZ |
7942 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
7943 | ||
c67a470b PZ |
7944 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
7945 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7946 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
7947 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7948 | } | |
7949 | ||
7950 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
7951 | hsw_disable_lcpll(dev_priv, true, true); |
7952 | } | |
7953 | ||
a14cb6fc | 7954 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
7955 | { |
7956 | struct drm_device *dev = dev_priv->dev; | |
7957 | uint32_t val; | |
7958 | ||
c67a470b PZ |
7959 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
7960 | ||
7961 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
7962 | lpt_init_pch_refclk(dev); |
7963 | ||
7964 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
7965 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7966 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
7967 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7968 | } | |
7969 | ||
7970 | intel_prepare_ddi(dev); | |
c67a470b PZ |
7971 | } |
7972 | ||
797d0259 | 7973 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc) |
09b4ddf9 | 7974 | { |
c7653199 | 7975 | if (!intel_ddi_pll_select(crtc)) |
6441ab5f | 7976 | return -EINVAL; |
716c2e55 | 7977 | |
c7653199 | 7978 | crtc->lowfreq_avail = false; |
644cef34 | 7979 | |
c8f7a0db | 7980 | return 0; |
79e53945 JB |
7981 | } |
7982 | ||
96b7dfb7 S |
7983 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
7984 | enum port port, | |
7985 | struct intel_crtc_config *pipe_config) | |
7986 | { | |
3148ade7 | 7987 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
7988 | |
7989 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
7990 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
7991 | ||
7992 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
7993 | case SKL_DPLL0: |
7994 | /* | |
7995 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
7996 | * of the shared DPLL framework and thus needs to be read out | |
7997 | * separately | |
7998 | */ | |
7999 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
8000 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
8001 | break; | |
96b7dfb7 S |
8002 | case SKL_DPLL1: |
8003 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
8004 | break; | |
8005 | case SKL_DPLL2: | |
8006 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
8007 | break; | |
8008 | case SKL_DPLL3: | |
8009 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
8010 | break; | |
96b7dfb7 S |
8011 | } |
8012 | } | |
8013 | ||
7d2c8175 DL |
8014 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
8015 | enum port port, | |
8016 | struct intel_crtc_config *pipe_config) | |
8017 | { | |
8018 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
8019 | ||
8020 | switch (pipe_config->ddi_pll_sel) { | |
8021 | case PORT_CLK_SEL_WRPLL1: | |
8022 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
8023 | break; | |
8024 | case PORT_CLK_SEL_WRPLL2: | |
8025 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
8026 | break; | |
8027 | } | |
8028 | } | |
8029 | ||
26804afd DV |
8030 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
8031 | struct intel_crtc_config *pipe_config) | |
8032 | { | |
8033 | struct drm_device *dev = crtc->base.dev; | |
8034 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 8035 | struct intel_shared_dpll *pll; |
26804afd DV |
8036 | enum port port; |
8037 | uint32_t tmp; | |
8038 | ||
8039 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
8040 | ||
8041 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
8042 | ||
96b7dfb7 S |
8043 | if (IS_SKYLAKE(dev)) |
8044 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
8045 | else | |
8046 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 8047 | |
d452c5b6 DV |
8048 | if (pipe_config->shared_dpll >= 0) { |
8049 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
8050 | ||
8051 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
8052 | &pipe_config->dpll_hw_state)); | |
8053 | } | |
8054 | ||
26804afd DV |
8055 | /* |
8056 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
8057 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
8058 | * the PCH transcoder is on. | |
8059 | */ | |
ca370455 DL |
8060 | if (INTEL_INFO(dev)->gen < 9 && |
8061 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
8062 | pipe_config->has_pch_encoder = true; |
8063 | ||
8064 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
8065 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8066 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
8067 | ||
8068 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
8069 | } | |
8070 | } | |
8071 | ||
0e8ffe1b DV |
8072 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
8073 | struct intel_crtc_config *pipe_config) | |
8074 | { | |
8075 | struct drm_device *dev = crtc->base.dev; | |
8076 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 8077 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
8078 | uint32_t tmp; |
8079 | ||
f458ebbc | 8080 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
8081 | POWER_DOMAIN_PIPE(crtc->pipe))) |
8082 | return false; | |
8083 | ||
e143a21c | 8084 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
8085 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
8086 | ||
eccb140b DV |
8087 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
8088 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
8089 | enum pipe trans_edp_pipe; | |
8090 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
8091 | default: | |
8092 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
8093 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
8094 | case TRANS_DDI_EDP_INPUT_A_ON: | |
8095 | trans_edp_pipe = PIPE_A; | |
8096 | break; | |
8097 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
8098 | trans_edp_pipe = PIPE_B; | |
8099 | break; | |
8100 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
8101 | trans_edp_pipe = PIPE_C; | |
8102 | break; | |
8103 | } | |
8104 | ||
8105 | if (trans_edp_pipe == crtc->pipe) | |
8106 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
8107 | } | |
8108 | ||
f458ebbc | 8109 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 8110 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
8111 | return false; |
8112 | ||
eccb140b | 8113 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
8114 | if (!(tmp & PIPECONF_ENABLE)) |
8115 | return false; | |
8116 | ||
26804afd | 8117 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 8118 | |
1bd1bd80 DV |
8119 | intel_get_pipe_timings(crtc, pipe_config); |
8120 | ||
2fa2fe9a | 8121 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
bd2e244f JB |
8122 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
8123 | if (IS_SKYLAKE(dev)) | |
8124 | skylake_get_pfit_config(crtc, pipe_config); | |
8125 | else | |
8126 | ironlake_get_pfit_config(crtc, pipe_config); | |
8127 | } | |
88adfff1 | 8128 | |
e59150dc JB |
8129 | if (IS_HASWELL(dev)) |
8130 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
8131 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 8132 | |
ebb69c95 CT |
8133 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
8134 | pipe_config->pixel_multiplier = | |
8135 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
8136 | } else { | |
8137 | pipe_config->pixel_multiplier = 1; | |
8138 | } | |
6c49f241 | 8139 | |
0e8ffe1b DV |
8140 | return true; |
8141 | } | |
8142 | ||
560b85bb CW |
8143 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
8144 | { | |
8145 | struct drm_device *dev = crtc->dev; | |
8146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8147 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 8148 | uint32_t cntl = 0, size = 0; |
560b85bb | 8149 | |
dc41c154 VS |
8150 | if (base) { |
8151 | unsigned int width = intel_crtc->cursor_width; | |
8152 | unsigned int height = intel_crtc->cursor_height; | |
8153 | unsigned int stride = roundup_pow_of_two(width) * 4; | |
8154 | ||
8155 | switch (stride) { | |
8156 | default: | |
8157 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
8158 | width, stride); | |
8159 | stride = 256; | |
8160 | /* fallthrough */ | |
8161 | case 256: | |
8162 | case 512: | |
8163 | case 1024: | |
8164 | case 2048: | |
8165 | break; | |
4b0e333e CW |
8166 | } |
8167 | ||
dc41c154 VS |
8168 | cntl |= CURSOR_ENABLE | |
8169 | CURSOR_GAMMA_ENABLE | | |
8170 | CURSOR_FORMAT_ARGB | | |
8171 | CURSOR_STRIDE(stride); | |
8172 | ||
8173 | size = (height << 12) | width; | |
4b0e333e | 8174 | } |
560b85bb | 8175 | |
dc41c154 VS |
8176 | if (intel_crtc->cursor_cntl != 0 && |
8177 | (intel_crtc->cursor_base != base || | |
8178 | intel_crtc->cursor_size != size || | |
8179 | intel_crtc->cursor_cntl != cntl)) { | |
8180 | /* On these chipsets we can only modify the base/size/stride | |
8181 | * whilst the cursor is disabled. | |
8182 | */ | |
8183 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 8184 | POSTING_READ(_CURACNTR); |
dc41c154 | 8185 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 8186 | } |
560b85bb | 8187 | |
99d1f387 | 8188 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 8189 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
8190 | intel_crtc->cursor_base = base; |
8191 | } | |
4726e0b0 | 8192 | |
dc41c154 VS |
8193 | if (intel_crtc->cursor_size != size) { |
8194 | I915_WRITE(CURSIZE, size); | |
8195 | intel_crtc->cursor_size = size; | |
4b0e333e | 8196 | } |
560b85bb | 8197 | |
4b0e333e | 8198 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
8199 | I915_WRITE(_CURACNTR, cntl); |
8200 | POSTING_READ(_CURACNTR); | |
4b0e333e | 8201 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 8202 | } |
560b85bb CW |
8203 | } |
8204 | ||
560b85bb | 8205 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
8206 | { |
8207 | struct drm_device *dev = crtc->dev; | |
8208 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8209 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8210 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
8211 | uint32_t cntl; |
8212 | ||
8213 | cntl = 0; | |
8214 | if (base) { | |
8215 | cntl = MCURSOR_GAMMA_ENABLE; | |
8216 | switch (intel_crtc->cursor_width) { | |
4726e0b0 SK |
8217 | case 64: |
8218 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
8219 | break; | |
8220 | case 128: | |
8221 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
8222 | break; | |
8223 | case 256: | |
8224 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
8225 | break; | |
8226 | default: | |
8227 | WARN_ON(1); | |
8228 | return; | |
65a21cd6 | 8229 | } |
4b0e333e | 8230 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
8231 | |
8232 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
8233 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 8234 | } |
65a21cd6 | 8235 | |
4398ad45 VS |
8236 | if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) |
8237 | cntl |= CURSOR_ROTATE_180; | |
8238 | ||
4b0e333e CW |
8239 | if (intel_crtc->cursor_cntl != cntl) { |
8240 | I915_WRITE(CURCNTR(pipe), cntl); | |
8241 | POSTING_READ(CURCNTR(pipe)); | |
8242 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 8243 | } |
4b0e333e | 8244 | |
65a21cd6 | 8245 | /* and commit changes on next vblank */ |
5efb3e28 VS |
8246 | I915_WRITE(CURBASE(pipe), base); |
8247 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
8248 | |
8249 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
8250 | } |
8251 | ||
cda4b7d3 | 8252 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
8253 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
8254 | bool on) | |
cda4b7d3 CW |
8255 | { |
8256 | struct drm_device *dev = crtc->dev; | |
8257 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8258 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8259 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
8260 | int x = crtc->cursor_x; |
8261 | int y = crtc->cursor_y; | |
d6e4db15 | 8262 | u32 base = 0, pos = 0; |
cda4b7d3 | 8263 | |
d6e4db15 | 8264 | if (on) |
cda4b7d3 | 8265 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 8266 | |
d6e4db15 VS |
8267 | if (x >= intel_crtc->config.pipe_src_w) |
8268 | base = 0; | |
8269 | ||
8270 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
8271 | base = 0; |
8272 | ||
8273 | if (x < 0) { | |
efc9064e | 8274 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
8275 | base = 0; |
8276 | ||
8277 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
8278 | x = -x; | |
8279 | } | |
8280 | pos |= x << CURSOR_X_SHIFT; | |
8281 | ||
8282 | if (y < 0) { | |
efc9064e | 8283 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
8284 | base = 0; |
8285 | ||
8286 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
8287 | y = -y; | |
8288 | } | |
8289 | pos |= y << CURSOR_Y_SHIFT; | |
8290 | ||
4b0e333e | 8291 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
8292 | return; |
8293 | ||
5efb3e28 VS |
8294 | I915_WRITE(CURPOS(pipe), pos); |
8295 | ||
4398ad45 VS |
8296 | /* ILK+ do this automagically */ |
8297 | if (HAS_GMCH_DISPLAY(dev) && | |
8298 | to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) { | |
8299 | base += (intel_crtc->cursor_height * | |
8300 | intel_crtc->cursor_width - 1) * 4; | |
8301 | } | |
8302 | ||
8ac54669 | 8303 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
8304 | i845_update_cursor(crtc, base); |
8305 | else | |
8306 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
8307 | } |
8308 | ||
dc41c154 VS |
8309 | static bool cursor_size_ok(struct drm_device *dev, |
8310 | uint32_t width, uint32_t height) | |
8311 | { | |
8312 | if (width == 0 || height == 0) | |
8313 | return false; | |
8314 | ||
8315 | /* | |
8316 | * 845g/865g are special in that they are only limited by | |
8317 | * the width of their cursors, the height is arbitrary up to | |
8318 | * the precision of the register. Everything else requires | |
8319 | * square cursors, limited to a few power-of-two sizes. | |
8320 | */ | |
8321 | if (IS_845G(dev) || IS_I865G(dev)) { | |
8322 | if ((width & 63) != 0) | |
8323 | return false; | |
8324 | ||
8325 | if (width > (IS_845G(dev) ? 64 : 512)) | |
8326 | return false; | |
8327 | ||
8328 | if (height > 1023) | |
8329 | return false; | |
8330 | } else { | |
8331 | switch (width | height) { | |
8332 | case 256: | |
8333 | case 128: | |
8334 | if (IS_GEN2(dev)) | |
8335 | return false; | |
8336 | case 64: | |
8337 | break; | |
8338 | default: | |
8339 | return false; | |
8340 | } | |
8341 | } | |
8342 | ||
8343 | return true; | |
8344 | } | |
8345 | ||
79e53945 | 8346 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 8347 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 8348 | { |
7203425a | 8349 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 8350 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8351 | |
7203425a | 8352 | for (i = start; i < end; i++) { |
79e53945 JB |
8353 | intel_crtc->lut_r[i] = red[i] >> 8; |
8354 | intel_crtc->lut_g[i] = green[i] >> 8; | |
8355 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
8356 | } | |
8357 | ||
8358 | intel_crtc_load_lut(crtc); | |
8359 | } | |
8360 | ||
79e53945 JB |
8361 | /* VESA 640x480x72Hz mode to set on the pipe */ |
8362 | static struct drm_display_mode load_detect_mode = { | |
8363 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
8364 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
8365 | }; | |
8366 | ||
a8bb6818 DV |
8367 | struct drm_framebuffer * |
8368 | __intel_framebuffer_create(struct drm_device *dev, | |
8369 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8370 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
8371 | { |
8372 | struct intel_framebuffer *intel_fb; | |
8373 | int ret; | |
8374 | ||
8375 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
8376 | if (!intel_fb) { | |
6ccb81f2 | 8377 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
8378 | return ERR_PTR(-ENOMEM); |
8379 | } | |
8380 | ||
8381 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
8382 | if (ret) |
8383 | goto err; | |
d2dff872 CW |
8384 | |
8385 | return &intel_fb->base; | |
dd4916c5 | 8386 | err: |
6ccb81f2 | 8387 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
8388 | kfree(intel_fb); |
8389 | ||
8390 | return ERR_PTR(ret); | |
d2dff872 CW |
8391 | } |
8392 | ||
b5ea642a | 8393 | static struct drm_framebuffer * |
a8bb6818 DV |
8394 | intel_framebuffer_create(struct drm_device *dev, |
8395 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8396 | struct drm_i915_gem_object *obj) | |
8397 | { | |
8398 | struct drm_framebuffer *fb; | |
8399 | int ret; | |
8400 | ||
8401 | ret = i915_mutex_lock_interruptible(dev); | |
8402 | if (ret) | |
8403 | return ERR_PTR(ret); | |
8404 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
8405 | mutex_unlock(&dev->struct_mutex); | |
8406 | ||
8407 | return fb; | |
8408 | } | |
8409 | ||
d2dff872 CW |
8410 | static u32 |
8411 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
8412 | { | |
8413 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
8414 | return ALIGN(pitch, 64); | |
8415 | } | |
8416 | ||
8417 | static u32 | |
8418 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
8419 | { | |
8420 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 8421 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
8422 | } |
8423 | ||
8424 | static struct drm_framebuffer * | |
8425 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
8426 | struct drm_display_mode *mode, | |
8427 | int depth, int bpp) | |
8428 | { | |
8429 | struct drm_i915_gem_object *obj; | |
0fed39bd | 8430 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
8431 | |
8432 | obj = i915_gem_alloc_object(dev, | |
8433 | intel_framebuffer_size_for_mode(mode, bpp)); | |
8434 | if (obj == NULL) | |
8435 | return ERR_PTR(-ENOMEM); | |
8436 | ||
8437 | mode_cmd.width = mode->hdisplay; | |
8438 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
8439 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
8440 | bpp); | |
5ca0c34a | 8441 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
8442 | |
8443 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
8444 | } | |
8445 | ||
8446 | static struct drm_framebuffer * | |
8447 | mode_fits_in_fbdev(struct drm_device *dev, | |
8448 | struct drm_display_mode *mode) | |
8449 | { | |
4520f53a | 8450 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
8451 | struct drm_i915_private *dev_priv = dev->dev_private; |
8452 | struct drm_i915_gem_object *obj; | |
8453 | struct drm_framebuffer *fb; | |
8454 | ||
4c0e5528 | 8455 | if (!dev_priv->fbdev) |
d2dff872 CW |
8456 | return NULL; |
8457 | ||
4c0e5528 | 8458 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
8459 | return NULL; |
8460 | ||
4c0e5528 DV |
8461 | obj = dev_priv->fbdev->fb->obj; |
8462 | BUG_ON(!obj); | |
8463 | ||
8bcd4553 | 8464 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
8465 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8466 | fb->bits_per_pixel)) | |
d2dff872 CW |
8467 | return NULL; |
8468 | ||
01f2c773 | 8469 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
8470 | return NULL; |
8471 | ||
8472 | return fb; | |
4520f53a DV |
8473 | #else |
8474 | return NULL; | |
8475 | #endif | |
d2dff872 CW |
8476 | } |
8477 | ||
d2434ab7 | 8478 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 8479 | struct drm_display_mode *mode, |
51fd371b RC |
8480 | struct intel_load_detect_pipe *old, |
8481 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
8482 | { |
8483 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
8484 | struct intel_encoder *intel_encoder = |
8485 | intel_attached_encoder(connector); | |
79e53945 | 8486 | struct drm_crtc *possible_crtc; |
4ef69c7a | 8487 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
8488 | struct drm_crtc *crtc = NULL; |
8489 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 8490 | struct drm_framebuffer *fb; |
51fd371b RC |
8491 | struct drm_mode_config *config = &dev->mode_config; |
8492 | int ret, i = -1; | |
79e53945 | 8493 | |
d2dff872 | 8494 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8495 | connector->base.id, connector->name, |
8e329a03 | 8496 | encoder->base.id, encoder->name); |
d2dff872 | 8497 | |
51fd371b RC |
8498 | retry: |
8499 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
8500 | if (ret) | |
8501 | goto fail_unlock; | |
6e9f798d | 8502 | |
79e53945 JB |
8503 | /* |
8504 | * Algorithm gets a little messy: | |
7a5e4805 | 8505 | * |
79e53945 JB |
8506 | * - if the connector already has an assigned crtc, use it (but make |
8507 | * sure it's on first) | |
7a5e4805 | 8508 | * |
79e53945 JB |
8509 | * - try to find the first unused crtc that can drive this connector, |
8510 | * and use that if we find one | |
79e53945 JB |
8511 | */ |
8512 | ||
8513 | /* See if we already have a CRTC for this connector */ | |
8514 | if (encoder->crtc) { | |
8515 | crtc = encoder->crtc; | |
8261b191 | 8516 | |
51fd371b | 8517 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de DV |
8518 | if (ret) |
8519 | goto fail_unlock; | |
8520 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
51fd371b RC |
8521 | if (ret) |
8522 | goto fail_unlock; | |
7b24056b | 8523 | |
24218aac | 8524 | old->dpms_mode = connector->dpms; |
8261b191 CW |
8525 | old->load_detect_temp = false; |
8526 | ||
8527 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
8528 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8529 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 8530 | |
7173188d | 8531 | return true; |
79e53945 JB |
8532 | } |
8533 | ||
8534 | /* Find an unused one (if possible) */ | |
70e1e0ec | 8535 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
8536 | i++; |
8537 | if (!(encoder->possible_crtcs & (1 << i))) | |
8538 | continue; | |
a459249c VS |
8539 | if (possible_crtc->enabled) |
8540 | continue; | |
8541 | /* This can occur when applying the pipe A quirk on resume. */ | |
8542 | if (to_intel_crtc(possible_crtc)->new_enabled) | |
8543 | continue; | |
8544 | ||
8545 | crtc = possible_crtc; | |
8546 | break; | |
79e53945 JB |
8547 | } |
8548 | ||
8549 | /* | |
8550 | * If we didn't find an unused CRTC, don't use any. | |
8551 | */ | |
8552 | if (!crtc) { | |
7173188d | 8553 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 8554 | goto fail_unlock; |
79e53945 JB |
8555 | } |
8556 | ||
51fd371b RC |
8557 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8558 | if (ret) | |
4d02e2de DV |
8559 | goto fail_unlock; |
8560 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
8561 | if (ret) | |
51fd371b | 8562 | goto fail_unlock; |
fc303101 DV |
8563 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8564 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
8565 | |
8566 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 VS |
8567 | intel_crtc->new_enabled = true; |
8568 | intel_crtc->new_config = &intel_crtc->config; | |
24218aac | 8569 | old->dpms_mode = connector->dpms; |
8261b191 | 8570 | old->load_detect_temp = true; |
d2dff872 | 8571 | old->release_fb = NULL; |
79e53945 | 8572 | |
6492711d CW |
8573 | if (!mode) |
8574 | mode = &load_detect_mode; | |
79e53945 | 8575 | |
d2dff872 CW |
8576 | /* We need a framebuffer large enough to accommodate all accesses |
8577 | * that the plane may generate whilst we perform load detection. | |
8578 | * We can not rely on the fbcon either being present (we get called | |
8579 | * during its initialisation to detect all boot displays, or it may | |
8580 | * not even exist) or that it is large enough to satisfy the | |
8581 | * requested mode. | |
8582 | */ | |
94352cf9 DV |
8583 | fb = mode_fits_in_fbdev(dev, mode); |
8584 | if (fb == NULL) { | |
d2dff872 | 8585 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
8586 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
8587 | old->release_fb = fb; | |
d2dff872 CW |
8588 | } else |
8589 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 8590 | if (IS_ERR(fb)) { |
d2dff872 | 8591 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 8592 | goto fail; |
79e53945 | 8593 | } |
79e53945 | 8594 | |
c0c36b94 | 8595 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 8596 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
8597 | if (old->release_fb) |
8598 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 8599 | goto fail; |
79e53945 | 8600 | } |
7173188d | 8601 | |
79e53945 | 8602 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 8603 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 8604 | return true; |
412b61d8 VS |
8605 | |
8606 | fail: | |
8607 | intel_crtc->new_enabled = crtc->enabled; | |
8608 | if (intel_crtc->new_enabled) | |
8609 | intel_crtc->new_config = &intel_crtc->config; | |
8610 | else | |
8611 | intel_crtc->new_config = NULL; | |
51fd371b RC |
8612 | fail_unlock: |
8613 | if (ret == -EDEADLK) { | |
8614 | drm_modeset_backoff(ctx); | |
8615 | goto retry; | |
8616 | } | |
8617 | ||
412b61d8 | 8618 | return false; |
79e53945 JB |
8619 | } |
8620 | ||
d2434ab7 | 8621 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
208bf9fd | 8622 | struct intel_load_detect_pipe *old) |
79e53945 | 8623 | { |
d2434ab7 DV |
8624 | struct intel_encoder *intel_encoder = |
8625 | intel_attached_encoder(connector); | |
4ef69c7a | 8626 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 8627 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 8628 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8629 | |
d2dff872 | 8630 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8631 | connector->base.id, connector->name, |
8e329a03 | 8632 | encoder->base.id, encoder->name); |
d2dff872 | 8633 | |
8261b191 | 8634 | if (old->load_detect_temp) { |
fc303101 DV |
8635 | to_intel_connector(connector)->new_encoder = NULL; |
8636 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
8637 | intel_crtc->new_enabled = false; |
8638 | intel_crtc->new_config = NULL; | |
fc303101 | 8639 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 8640 | |
36206361 DV |
8641 | if (old->release_fb) { |
8642 | drm_framebuffer_unregister_private(old->release_fb); | |
8643 | drm_framebuffer_unreference(old->release_fb); | |
8644 | } | |
d2dff872 | 8645 | |
0622a53c | 8646 | return; |
79e53945 JB |
8647 | } |
8648 | ||
c751ce4f | 8649 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
8650 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
8651 | connector->funcs->dpms(connector, old->dpms_mode); | |
79e53945 JB |
8652 | } |
8653 | ||
da4a1efa VS |
8654 | static int i9xx_pll_refclk(struct drm_device *dev, |
8655 | const struct intel_crtc_config *pipe_config) | |
8656 | { | |
8657 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8658 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
8659 | ||
8660 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 8661 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
8662 | else if (HAS_PCH_SPLIT(dev)) |
8663 | return 120000; | |
8664 | else if (!IS_GEN2(dev)) | |
8665 | return 96000; | |
8666 | else | |
8667 | return 48000; | |
8668 | } | |
8669 | ||
79e53945 | 8670 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
8671 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
8672 | struct intel_crtc_config *pipe_config) | |
79e53945 | 8673 | { |
f1f644dc | 8674 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 8675 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 8676 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 8677 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
8678 | u32 fp; |
8679 | intel_clock_t clock; | |
da4a1efa | 8680 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
8681 | |
8682 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 8683 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 8684 | else |
293623f7 | 8685 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
8686 | |
8687 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
8688 | if (IS_PINEVIEW(dev)) { |
8689 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
8690 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
8691 | } else { |
8692 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
8693 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
8694 | } | |
8695 | ||
a6c45cf0 | 8696 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
8697 | if (IS_PINEVIEW(dev)) |
8698 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
8699 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
8700 | else |
8701 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
8702 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8703 | ||
8704 | switch (dpll & DPLL_MODE_MASK) { | |
8705 | case DPLLB_MODE_DAC_SERIAL: | |
8706 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
8707 | 5 : 10; | |
8708 | break; | |
8709 | case DPLLB_MODE_LVDS: | |
8710 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
8711 | 7 : 14; | |
8712 | break; | |
8713 | default: | |
28c97730 | 8714 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 8715 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 8716 | return; |
79e53945 JB |
8717 | } |
8718 | ||
ac58c3f0 | 8719 | if (IS_PINEVIEW(dev)) |
da4a1efa | 8720 | pineview_clock(refclk, &clock); |
ac58c3f0 | 8721 | else |
da4a1efa | 8722 | i9xx_clock(refclk, &clock); |
79e53945 | 8723 | } else { |
0fb58223 | 8724 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 8725 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
8726 | |
8727 | if (is_lvds) { | |
8728 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
8729 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
8730 | |
8731 | if (lvds & LVDS_CLKB_POWER_UP) | |
8732 | clock.p2 = 7; | |
8733 | else | |
8734 | clock.p2 = 14; | |
79e53945 JB |
8735 | } else { |
8736 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
8737 | clock.p1 = 2; | |
8738 | else { | |
8739 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
8740 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
8741 | } | |
8742 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
8743 | clock.p2 = 4; | |
8744 | else | |
8745 | clock.p2 = 2; | |
79e53945 | 8746 | } |
da4a1efa VS |
8747 | |
8748 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
8749 | } |
8750 | ||
18442d08 VS |
8751 | /* |
8752 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 8753 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
8754 | * encoder's get_config() function. |
8755 | */ | |
8756 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
8757 | } |
8758 | ||
6878da05 VS |
8759 | int intel_dotclock_calculate(int link_freq, |
8760 | const struct intel_link_m_n *m_n) | |
f1f644dc | 8761 | { |
f1f644dc JB |
8762 | /* |
8763 | * The calculation for the data clock is: | |
1041a02f | 8764 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 8765 | * But we want to avoid losing precison if possible, so: |
1041a02f | 8766 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
8767 | * |
8768 | * and the link clock is simpler: | |
1041a02f | 8769 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
8770 | */ |
8771 | ||
6878da05 VS |
8772 | if (!m_n->link_n) |
8773 | return 0; | |
f1f644dc | 8774 | |
6878da05 VS |
8775 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8776 | } | |
f1f644dc | 8777 | |
18442d08 VS |
8778 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8779 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
8780 | { |
8781 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 8782 | |
18442d08 VS |
8783 | /* read out port_clock from the DPLL */ |
8784 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 8785 | |
f1f644dc | 8786 | /* |
18442d08 | 8787 | * This value does not include pixel_multiplier. |
241bfc38 | 8788 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
8789 | * agree once we know their relationship in the encoder's |
8790 | * get_config() function. | |
79e53945 | 8791 | */ |
241bfc38 | 8792 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
8793 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8794 | &pipe_config->fdi_m_n); | |
79e53945 JB |
8795 | } |
8796 | ||
8797 | /** Returns the currently programmed mode of the given pipe. */ | |
8798 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
8799 | struct drm_crtc *crtc) | |
8800 | { | |
548f245b | 8801 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 8802 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 8803 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 8804 | struct drm_display_mode *mode; |
f1f644dc | 8805 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
8806 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8807 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8808 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
8809 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 8810 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
8811 | |
8812 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
8813 | if (!mode) | |
8814 | return NULL; | |
8815 | ||
f1f644dc JB |
8816 | /* |
8817 | * Construct a pipe_config sufficient for getting the clock info | |
8818 | * back out of crtc_clock_get. | |
8819 | * | |
8820 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
8821 | * to use a real value here instead. | |
8822 | */ | |
293623f7 | 8823 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 8824 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
8825 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
8826 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
8827 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
8828 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
8829 | ||
773ae034 | 8830 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
8831 | mode->hdisplay = (htot & 0xffff) + 1; |
8832 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
8833 | mode->hsync_start = (hsync & 0xffff) + 1; | |
8834 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
8835 | mode->vdisplay = (vtot & 0xffff) + 1; | |
8836 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
8837 | mode->vsync_start = (vsync & 0xffff) + 1; | |
8838 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
8839 | ||
8840 | drm_mode_set_name(mode); | |
79e53945 JB |
8841 | |
8842 | return mode; | |
8843 | } | |
8844 | ||
652c393a JB |
8845 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
8846 | { | |
8847 | struct drm_device *dev = crtc->dev; | |
fbee40df | 8848 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8849 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 8850 | |
baff296c | 8851 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
8852 | return; |
8853 | ||
8854 | if (!dev_priv->lvds_downclock_avail) | |
8855 | return; | |
8856 | ||
8857 | /* | |
8858 | * Since this is called by a timer, we should never get here in | |
8859 | * the manual case. | |
8860 | */ | |
8861 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
8862 | int pipe = intel_crtc->pipe; |
8863 | int dpll_reg = DPLL(pipe); | |
8864 | int dpll; | |
f6e5b160 | 8865 | |
44d98a61 | 8866 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 8867 | |
8ac5a6d5 | 8868 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 8869 | |
dc257cf1 | 8870 | dpll = I915_READ(dpll_reg); |
652c393a JB |
8871 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
8872 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 8873 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
8874 | dpll = I915_READ(dpll_reg); |
8875 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 8876 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
8877 | } |
8878 | ||
8879 | } | |
8880 | ||
f047e395 CW |
8881 | void intel_mark_busy(struct drm_device *dev) |
8882 | { | |
c67a470b PZ |
8883 | struct drm_i915_private *dev_priv = dev->dev_private; |
8884 | ||
f62a0076 CW |
8885 | if (dev_priv->mm.busy) |
8886 | return; | |
8887 | ||
43694d69 | 8888 | intel_runtime_pm_get(dev_priv); |
c67a470b | 8889 | i915_update_gfx_val(dev_priv); |
f62a0076 | 8890 | dev_priv->mm.busy = true; |
f047e395 CW |
8891 | } |
8892 | ||
8893 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 8894 | { |
c67a470b | 8895 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 8896 | struct drm_crtc *crtc; |
652c393a | 8897 | |
f62a0076 CW |
8898 | if (!dev_priv->mm.busy) |
8899 | return; | |
8900 | ||
8901 | dev_priv->mm.busy = false; | |
8902 | ||
d330a953 | 8903 | if (!i915.powersave) |
bb4cdd53 | 8904 | goto out; |
652c393a | 8905 | |
70e1e0ec | 8906 | for_each_crtc(dev, crtc) { |
f4510a27 | 8907 | if (!crtc->primary->fb) |
652c393a JB |
8908 | continue; |
8909 | ||
725a5b54 | 8910 | intel_decrease_pllclock(crtc); |
652c393a | 8911 | } |
b29c19b6 | 8912 | |
3d13ef2e | 8913 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 8914 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 PZ |
8915 | |
8916 | out: | |
43694d69 | 8917 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
8918 | } |
8919 | ||
79e53945 JB |
8920 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
8921 | { | |
8922 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
8923 | struct drm_device *dev = crtc->dev; |
8924 | struct intel_unpin_work *work; | |
67e77c5a | 8925 | |
5e2d7afc | 8926 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
8927 | work = intel_crtc->unpin_work; |
8928 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 8929 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
8930 | |
8931 | if (work) { | |
8932 | cancel_work_sync(&work->work); | |
8933 | kfree(work); | |
8934 | } | |
79e53945 JB |
8935 | |
8936 | drm_crtc_cleanup(crtc); | |
67e77c5a | 8937 | |
79e53945 JB |
8938 | kfree(intel_crtc); |
8939 | } | |
8940 | ||
6b95a207 KH |
8941 | static void intel_unpin_work_fn(struct work_struct *__work) |
8942 | { | |
8943 | struct intel_unpin_work *work = | |
8944 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 8945 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 8946 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 8947 | |
b4a98e57 | 8948 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 8949 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
8950 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
8951 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 8952 | |
b4a98e57 | 8953 | intel_update_fbc(dev); |
f06cc1b9 JH |
8954 | |
8955 | if (work->flip_queued_req) | |
8956 | i915_gem_request_unreference(work->flip_queued_req); | |
8957 | work->flip_queued_req = NULL; | |
b4a98e57 CW |
8958 | mutex_unlock(&dev->struct_mutex); |
8959 | ||
f99d7069 DV |
8960 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
8961 | ||
b4a98e57 CW |
8962 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
8963 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
8964 | ||
6b95a207 KH |
8965 | kfree(work); |
8966 | } | |
8967 | ||
1afe3e9d | 8968 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 8969 | struct drm_crtc *crtc) |
6b95a207 | 8970 | { |
6b95a207 KH |
8971 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8972 | struct intel_unpin_work *work; | |
6b95a207 KH |
8973 | unsigned long flags; |
8974 | ||
8975 | /* Ignore early vblank irqs */ | |
8976 | if (intel_crtc == NULL) | |
8977 | return; | |
8978 | ||
f326038a DV |
8979 | /* |
8980 | * This is called both by irq handlers and the reset code (to complete | |
8981 | * lost pageflips) so needs the full irqsave spinlocks. | |
8982 | */ | |
6b95a207 KH |
8983 | spin_lock_irqsave(&dev->event_lock, flags); |
8984 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
8985 | |
8986 | /* Ensure we don't miss a work->pending update ... */ | |
8987 | smp_rmb(); | |
8988 | ||
8989 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
8990 | spin_unlock_irqrestore(&dev->event_lock, flags); |
8991 | return; | |
8992 | } | |
8993 | ||
d6bbafa1 | 8994 | page_flip_completed(intel_crtc); |
0af7e4df | 8995 | |
6b95a207 | 8996 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
8997 | } |
8998 | ||
1afe3e9d JB |
8999 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
9000 | { | |
fbee40df | 9001 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9002 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
9003 | ||
49b14a5c | 9004 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9005 | } |
9006 | ||
9007 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
9008 | { | |
fbee40df | 9009 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9010 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
9011 | ||
49b14a5c | 9012 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9013 | } |
9014 | ||
75f7f3ec VS |
9015 | /* Is 'a' after or equal to 'b'? */ |
9016 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
9017 | { | |
9018 | return !((a - b) & 0x80000000); | |
9019 | } | |
9020 | ||
9021 | static bool page_flip_finished(struct intel_crtc *crtc) | |
9022 | { | |
9023 | struct drm_device *dev = crtc->base.dev; | |
9024 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9025 | ||
bdfa7542 VS |
9026 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
9027 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
9028 | return true; | |
9029 | ||
75f7f3ec VS |
9030 | /* |
9031 | * The relevant registers doen't exist on pre-ctg. | |
9032 | * As the flip done interrupt doesn't trigger for mmio | |
9033 | * flips on gmch platforms, a flip count check isn't | |
9034 | * really needed there. But since ctg has the registers, | |
9035 | * include it in the check anyway. | |
9036 | */ | |
9037 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
9038 | return true; | |
9039 | ||
9040 | /* | |
9041 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
9042 | * used the same base address. In that case the mmio flip might | |
9043 | * have completed, but the CS hasn't even executed the flip yet. | |
9044 | * | |
9045 | * A flip count check isn't enough as the CS might have updated | |
9046 | * the base address just after start of vblank, but before we | |
9047 | * managed to process the interrupt. This means we'd complete the | |
9048 | * CS flip too soon. | |
9049 | * | |
9050 | * Combining both checks should get us a good enough result. It may | |
9051 | * still happen that the CS flip has been executed, but has not | |
9052 | * yet actually completed. But in case the base address is the same | |
9053 | * anyway, we don't really care. | |
9054 | */ | |
9055 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
9056 | crtc->unpin_work->gtt_offset && | |
9057 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
9058 | crtc->unpin_work->flip_count); | |
9059 | } | |
9060 | ||
6b95a207 KH |
9061 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
9062 | { | |
fbee40df | 9063 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9064 | struct intel_crtc *intel_crtc = |
9065 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
9066 | unsigned long flags; | |
9067 | ||
f326038a DV |
9068 | |
9069 | /* | |
9070 | * This is called both by irq handlers and the reset code (to complete | |
9071 | * lost pageflips) so needs the full irqsave spinlocks. | |
9072 | * | |
9073 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
9074 | * generate a page-flip completion irq, i.e. every modeset |
9075 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
9076 | */ | |
6b95a207 | 9077 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 9078 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 9079 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
9080 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9081 | } | |
9082 | ||
eba905b2 | 9083 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
9084 | { |
9085 | /* Ensure that the work item is consistent when activating it ... */ | |
9086 | smp_wmb(); | |
9087 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
9088 | /* and that it is marked active as soon as the irq could fire. */ | |
9089 | smp_wmb(); | |
9090 | } | |
9091 | ||
8c9f3aaf JB |
9092 | static int intel_gen2_queue_flip(struct drm_device *dev, |
9093 | struct drm_crtc *crtc, | |
9094 | struct drm_framebuffer *fb, | |
ed8d1975 | 9095 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9096 | struct intel_engine_cs *ring, |
ed8d1975 | 9097 | uint32_t flags) |
8c9f3aaf | 9098 | { |
8c9f3aaf | 9099 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9100 | u32 flip_mask; |
9101 | int ret; | |
9102 | ||
6d90c952 | 9103 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9104 | if (ret) |
4fa62c89 | 9105 | return ret; |
8c9f3aaf JB |
9106 | |
9107 | /* Can't queue multiple flips, so wait for the previous | |
9108 | * one to finish before executing the next. | |
9109 | */ | |
9110 | if (intel_crtc->plane) | |
9111 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9112 | else | |
9113 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9114 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9115 | intel_ring_emit(ring, MI_NOOP); | |
9116 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
9117 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9118 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9119 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 9120 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
9121 | |
9122 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9123 | __intel_ring_advance(ring); |
83d4092b | 9124 | return 0; |
8c9f3aaf JB |
9125 | } |
9126 | ||
9127 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
9128 | struct drm_crtc *crtc, | |
9129 | struct drm_framebuffer *fb, | |
ed8d1975 | 9130 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9131 | struct intel_engine_cs *ring, |
ed8d1975 | 9132 | uint32_t flags) |
8c9f3aaf | 9133 | { |
8c9f3aaf | 9134 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9135 | u32 flip_mask; |
9136 | int ret; | |
9137 | ||
6d90c952 | 9138 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9139 | if (ret) |
4fa62c89 | 9140 | return ret; |
8c9f3aaf JB |
9141 | |
9142 | if (intel_crtc->plane) | |
9143 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9144 | else | |
9145 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9146 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9147 | intel_ring_emit(ring, MI_NOOP); | |
9148 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
9149 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9150 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9151 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
9152 | intel_ring_emit(ring, MI_NOOP); |
9153 | ||
e7d841ca | 9154 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 9155 | __intel_ring_advance(ring); |
83d4092b | 9156 | return 0; |
8c9f3aaf JB |
9157 | } |
9158 | ||
9159 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
9160 | struct drm_crtc *crtc, | |
9161 | struct drm_framebuffer *fb, | |
ed8d1975 | 9162 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9163 | struct intel_engine_cs *ring, |
ed8d1975 | 9164 | uint32_t flags) |
8c9f3aaf JB |
9165 | { |
9166 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9167 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9168 | uint32_t pf, pipesrc; | |
9169 | int ret; | |
9170 | ||
6d90c952 | 9171 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9172 | if (ret) |
4fa62c89 | 9173 | return ret; |
8c9f3aaf JB |
9174 | |
9175 | /* i965+ uses the linear or tiled offsets from the | |
9176 | * Display Registers (which do not change across a page-flip) | |
9177 | * so we need only reprogram the base address. | |
9178 | */ | |
6d90c952 DV |
9179 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9180 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9181 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9182 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 9183 | obj->tiling_mode); |
8c9f3aaf JB |
9184 | |
9185 | /* XXX Enabling the panel-fitter across page-flip is so far | |
9186 | * untested on non-native modes, so ignore it for now. | |
9187 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
9188 | */ | |
9189 | pf = 0; | |
9190 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 9191 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9192 | |
9193 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9194 | __intel_ring_advance(ring); |
83d4092b | 9195 | return 0; |
8c9f3aaf JB |
9196 | } |
9197 | ||
9198 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
9199 | struct drm_crtc *crtc, | |
9200 | struct drm_framebuffer *fb, | |
ed8d1975 | 9201 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9202 | struct intel_engine_cs *ring, |
ed8d1975 | 9203 | uint32_t flags) |
8c9f3aaf JB |
9204 | { |
9205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9206 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9207 | uint32_t pf, pipesrc; | |
9208 | int ret; | |
9209 | ||
6d90c952 | 9210 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9211 | if (ret) |
4fa62c89 | 9212 | return ret; |
8c9f3aaf | 9213 | |
6d90c952 DV |
9214 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9215 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9216 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 9217 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 9218 | |
dc257cf1 DV |
9219 | /* Contrary to the suggestions in the documentation, |
9220 | * "Enable Panel Fitter" does not seem to be required when page | |
9221 | * flipping with a non-native mode, and worse causes a normal | |
9222 | * modeset to fail. | |
9223 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
9224 | */ | |
9225 | pf = 0; | |
8c9f3aaf | 9226 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 9227 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9228 | |
9229 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9230 | __intel_ring_advance(ring); |
83d4092b | 9231 | return 0; |
8c9f3aaf JB |
9232 | } |
9233 | ||
7c9017e5 JB |
9234 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9235 | struct drm_crtc *crtc, | |
9236 | struct drm_framebuffer *fb, | |
ed8d1975 | 9237 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9238 | struct intel_engine_cs *ring, |
ed8d1975 | 9239 | uint32_t flags) |
7c9017e5 | 9240 | { |
7c9017e5 | 9241 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 9242 | uint32_t plane_bit = 0; |
ffe74d75 CW |
9243 | int len, ret; |
9244 | ||
eba905b2 | 9245 | switch (intel_crtc->plane) { |
cb05d8de DV |
9246 | case PLANE_A: |
9247 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
9248 | break; | |
9249 | case PLANE_B: | |
9250 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
9251 | break; | |
9252 | case PLANE_C: | |
9253 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
9254 | break; | |
9255 | default: | |
9256 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 9257 | return -ENODEV; |
cb05d8de DV |
9258 | } |
9259 | ||
ffe74d75 | 9260 | len = 4; |
f476828a | 9261 | if (ring->id == RCS) { |
ffe74d75 | 9262 | len += 6; |
f476828a DL |
9263 | /* |
9264 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
9265 | * 48bits addresses, and we need a NOOP for the batch size to | |
9266 | * stay even. | |
9267 | */ | |
9268 | if (IS_GEN8(dev)) | |
9269 | len += 2; | |
9270 | } | |
ffe74d75 | 9271 | |
f66fab8e VS |
9272 | /* |
9273 | * BSpec MI_DISPLAY_FLIP for IVB: | |
9274 | * "The full packet must be contained within the same cache line." | |
9275 | * | |
9276 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
9277 | * cacheline, if we ever start emitting more commands before | |
9278 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
9279 | * then do the cacheline alignment, and finally emit the | |
9280 | * MI_DISPLAY_FLIP. | |
9281 | */ | |
9282 | ret = intel_ring_cacheline_align(ring); | |
9283 | if (ret) | |
4fa62c89 | 9284 | return ret; |
f66fab8e | 9285 | |
ffe74d75 | 9286 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 9287 | if (ret) |
4fa62c89 | 9288 | return ret; |
7c9017e5 | 9289 | |
ffe74d75 CW |
9290 | /* Unmask the flip-done completion message. Note that the bspec says that |
9291 | * we should do this for both the BCS and RCS, and that we must not unmask | |
9292 | * more than one flip event at any time (or ensure that one flip message | |
9293 | * can be sent by waiting for flip-done prior to queueing new flips). | |
9294 | * Experimentation says that BCS works despite DERRMR masking all | |
9295 | * flip-done completion events and that unmasking all planes at once | |
9296 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
9297 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
9298 | */ | |
9299 | if (ring->id == RCS) { | |
9300 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9301 | intel_ring_emit(ring, DERRMR); | |
9302 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9303 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9304 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
9305 | if (IS_GEN8(dev)) |
9306 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9307 | MI_SRM_LRM_GLOBAL_GTT); | |
9308 | else | |
9309 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
9310 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
9311 | intel_ring_emit(ring, DERRMR); |
9312 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
9313 | if (IS_GEN8(dev)) { |
9314 | intel_ring_emit(ring, 0); | |
9315 | intel_ring_emit(ring, MI_NOOP); | |
9316 | } | |
ffe74d75 CW |
9317 | } |
9318 | ||
cb05d8de | 9319 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 9320 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 9321 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 9322 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
9323 | |
9324 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9325 | __intel_ring_advance(ring); |
83d4092b | 9326 | return 0; |
7c9017e5 JB |
9327 | } |
9328 | ||
84c33a64 SG |
9329 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
9330 | struct drm_i915_gem_object *obj) | |
9331 | { | |
9332 | /* | |
9333 | * This is not being used for older platforms, because | |
9334 | * non-availability of flip done interrupt forces us to use | |
9335 | * CS flips. Older platforms derive flip done using some clever | |
9336 | * tricks involving the flip_pending status bits and vblank irqs. | |
9337 | * So using MMIO flips there would disrupt this mechanism. | |
9338 | */ | |
9339 | ||
8e09bf83 CW |
9340 | if (ring == NULL) |
9341 | return true; | |
9342 | ||
84c33a64 SG |
9343 | if (INTEL_INFO(ring->dev)->gen < 5) |
9344 | return false; | |
9345 | ||
9346 | if (i915.use_mmio_flip < 0) | |
9347 | return false; | |
9348 | else if (i915.use_mmio_flip > 0) | |
9349 | return true; | |
14bf993e OM |
9350 | else if (i915.enable_execlists) |
9351 | return true; | |
84c33a64 | 9352 | else |
41c52415 | 9353 | return ring != i915_gem_request_get_ring(obj->last_read_req); |
84c33a64 SG |
9354 | } |
9355 | ||
ff944564 DL |
9356 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
9357 | { | |
9358 | struct drm_device *dev = intel_crtc->base.dev; | |
9359 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9360 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
9361 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
9362 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
9363 | const enum pipe pipe = intel_crtc->pipe; | |
9364 | u32 ctl, stride; | |
9365 | ||
9366 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
9367 | ctl &= ~PLANE_CTL_TILED_MASK; | |
9368 | if (obj->tiling_mode == I915_TILING_X) | |
9369 | ctl |= PLANE_CTL_TILED_X; | |
9370 | ||
9371 | /* | |
9372 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
9373 | * linear buffers or in number of tiles for tiled buffers. | |
9374 | */ | |
9375 | stride = fb->pitches[0] >> 6; | |
9376 | if (obj->tiling_mode == I915_TILING_X) | |
9377 | stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */ | |
9378 | ||
9379 | /* | |
9380 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
9381 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
9382 | */ | |
9383 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
9384 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
9385 | ||
9386 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
9387 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
9388 | } | |
9389 | ||
9390 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
9391 | { |
9392 | struct drm_device *dev = intel_crtc->base.dev; | |
9393 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9394 | struct intel_framebuffer *intel_fb = | |
9395 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
9396 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
9397 | u32 dspcntr; | |
9398 | u32 reg; | |
9399 | ||
84c33a64 SG |
9400 | reg = DSPCNTR(intel_crtc->plane); |
9401 | dspcntr = I915_READ(reg); | |
9402 | ||
c5d97472 DL |
9403 | if (obj->tiling_mode != I915_TILING_NONE) |
9404 | dspcntr |= DISPPLANE_TILED; | |
9405 | else | |
9406 | dspcntr &= ~DISPPLANE_TILED; | |
9407 | ||
84c33a64 SG |
9408 | I915_WRITE(reg, dspcntr); |
9409 | ||
9410 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
9411 | intel_crtc->unpin_work->gtt_offset); | |
9412 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 9413 | |
ff944564 DL |
9414 | } |
9415 | ||
9416 | /* | |
9417 | * XXX: This is the temporary way to update the plane registers until we get | |
9418 | * around to using the usual plane update functions for MMIO flips | |
9419 | */ | |
9420 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
9421 | { | |
9422 | struct drm_device *dev = intel_crtc->base.dev; | |
9423 | bool atomic_update; | |
9424 | u32 start_vbl_count; | |
9425 | ||
9426 | intel_mark_page_flip_active(intel_crtc); | |
9427 | ||
9428 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
9429 | ||
9430 | if (INTEL_INFO(dev)->gen >= 9) | |
9431 | skl_do_mmio_flip(intel_crtc); | |
9432 | else | |
9433 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
9434 | ilk_do_mmio_flip(intel_crtc); | |
9435 | ||
9362c7c5 ACO |
9436 | if (atomic_update) |
9437 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
84c33a64 SG |
9438 | } |
9439 | ||
9362c7c5 | 9440 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 9441 | { |
cc8c4cc2 | 9442 | struct intel_crtc *crtc = |
9362c7c5 | 9443 | container_of(work, struct intel_crtc, mmio_flip.work); |
cc8c4cc2 | 9444 | struct intel_mmio_flip *mmio_flip; |
84c33a64 | 9445 | |
cc8c4cc2 JH |
9446 | mmio_flip = &crtc->mmio_flip; |
9447 | if (mmio_flip->req) | |
9c654818 JH |
9448 | WARN_ON(__i915_wait_request(mmio_flip->req, |
9449 | crtc->reset_counter, | |
9450 | false, NULL, NULL) != 0); | |
84c33a64 | 9451 | |
cc8c4cc2 JH |
9452 | intel_do_mmio_flip(crtc); |
9453 | if (mmio_flip->req) { | |
9454 | mutex_lock(&crtc->base.dev->struct_mutex); | |
9455 | i915_gem_request_unreference(mmio_flip->req); | |
9456 | mutex_unlock(&crtc->base.dev->struct_mutex); | |
9457 | } | |
9458 | mmio_flip->req = NULL; | |
84c33a64 SG |
9459 | } |
9460 | ||
9461 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
9462 | struct drm_crtc *crtc, | |
9463 | struct drm_framebuffer *fb, | |
9464 | struct drm_i915_gem_object *obj, | |
9465 | struct intel_engine_cs *ring, | |
9466 | uint32_t flags) | |
9467 | { | |
84c33a64 | 9468 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
84c33a64 | 9469 | |
cc8c4cc2 JH |
9470 | i915_gem_request_assign(&intel_crtc->mmio_flip.req, |
9471 | obj->last_write_req); | |
536f5b5e ACO |
9472 | |
9473 | schedule_work(&intel_crtc->mmio_flip.work); | |
84c33a64 | 9474 | |
84c33a64 SG |
9475 | return 0; |
9476 | } | |
9477 | ||
830c81db DL |
9478 | static int intel_gen9_queue_flip(struct drm_device *dev, |
9479 | struct drm_crtc *crtc, | |
9480 | struct drm_framebuffer *fb, | |
9481 | struct drm_i915_gem_object *obj, | |
9482 | struct intel_engine_cs *ring, | |
9483 | uint32_t flags) | |
9484 | { | |
9485 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9486 | uint32_t plane = 0, stride; | |
9487 | int ret; | |
9488 | ||
9489 | switch(intel_crtc->pipe) { | |
9490 | case PIPE_A: | |
9491 | plane = MI_DISPLAY_FLIP_SKL_PLANE_1_A; | |
9492 | break; | |
9493 | case PIPE_B: | |
9494 | plane = MI_DISPLAY_FLIP_SKL_PLANE_1_B; | |
9495 | break; | |
9496 | case PIPE_C: | |
9497 | plane = MI_DISPLAY_FLIP_SKL_PLANE_1_C; | |
9498 | break; | |
9499 | default: | |
9500 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
9501 | return -ENODEV; | |
9502 | } | |
9503 | ||
9504 | switch (obj->tiling_mode) { | |
9505 | case I915_TILING_NONE: | |
9506 | stride = fb->pitches[0] >> 6; | |
9507 | break; | |
9508 | case I915_TILING_X: | |
9509 | stride = fb->pitches[0] >> 9; | |
9510 | break; | |
9511 | default: | |
9512 | WARN_ONCE(1, "unknown tiling in flip command\n"); | |
9513 | return -ENODEV; | |
9514 | } | |
9515 | ||
9516 | ret = intel_ring_begin(ring, 10); | |
9517 | if (ret) | |
9518 | return ret; | |
9519 | ||
9520 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9521 | intel_ring_emit(ring, DERRMR); | |
9522 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9523 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9524 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
9525 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9526 | MI_SRM_LRM_GLOBAL_GTT); | |
9527 | intel_ring_emit(ring, DERRMR); | |
9528 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
9529 | intel_ring_emit(ring, 0); | |
9530 | ||
9531 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane); | |
9532 | intel_ring_emit(ring, stride << 6 | obj->tiling_mode); | |
9533 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); | |
9534 | ||
9535 | intel_mark_page_flip_active(intel_crtc); | |
9536 | __intel_ring_advance(ring); | |
9537 | ||
9538 | return 0; | |
9539 | } | |
9540 | ||
8c9f3aaf JB |
9541 | static int intel_default_queue_flip(struct drm_device *dev, |
9542 | struct drm_crtc *crtc, | |
9543 | struct drm_framebuffer *fb, | |
ed8d1975 | 9544 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9545 | struct intel_engine_cs *ring, |
ed8d1975 | 9546 | uint32_t flags) |
8c9f3aaf JB |
9547 | { |
9548 | return -ENODEV; | |
9549 | } | |
9550 | ||
d6bbafa1 CW |
9551 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
9552 | struct drm_crtc *crtc) | |
9553 | { | |
9554 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9555 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9556 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
9557 | u32 addr; | |
9558 | ||
9559 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
9560 | return true; | |
9561 | ||
9562 | if (!work->enable_stall_check) | |
9563 | return false; | |
9564 | ||
9565 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
9566 | if (work->flip_queued_req && |
9567 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
9568 | return false; | |
d6bbafa1 CW |
9569 | |
9570 | work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe); | |
9571 | } | |
9572 | ||
9573 | if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3) | |
9574 | return false; | |
9575 | ||
9576 | /* Potential stall - if we see that the flip has happened, | |
9577 | * assume a missed interrupt. */ | |
9578 | if (INTEL_INFO(dev)->gen >= 4) | |
9579 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
9580 | else | |
9581 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
9582 | ||
9583 | /* There is a potential issue here with a false positive after a flip | |
9584 | * to the same address. We could address this by checking for a | |
9585 | * non-incrementing frame counter. | |
9586 | */ | |
9587 | return addr == work->gtt_offset; | |
9588 | } | |
9589 | ||
9590 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
9591 | { | |
9592 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9593 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
9594 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
f326038a DV |
9595 | |
9596 | WARN_ON(!in_irq()); | |
d6bbafa1 CW |
9597 | |
9598 | if (crtc == NULL) | |
9599 | return; | |
9600 | ||
f326038a | 9601 | spin_lock(&dev->event_lock); |
d6bbafa1 CW |
9602 | if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) { |
9603 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", | |
9604 | intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe)); | |
9605 | page_flip_completed(intel_crtc); | |
9606 | } | |
f326038a | 9607 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
9608 | } |
9609 | ||
6b95a207 KH |
9610 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
9611 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
9612 | struct drm_pending_vblank_event *event, |
9613 | uint32_t page_flip_flags) | |
6b95a207 KH |
9614 | { |
9615 | struct drm_device *dev = crtc->dev; | |
9616 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 9617 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 9618 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 9619 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 GP |
9620 | struct drm_plane *primary = crtc->primary; |
9621 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
a071fa00 | 9622 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 9623 | struct intel_unpin_work *work; |
a4872ba6 | 9624 | struct intel_engine_cs *ring; |
52e68630 | 9625 | int ret; |
6b95a207 | 9626 | |
2ff8fde1 MR |
9627 | /* |
9628 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
9629 | * check to be safe. In the future we may enable pageflipping from | |
9630 | * a disabled primary plane. | |
9631 | */ | |
9632 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
9633 | return -EBUSY; | |
9634 | ||
e6a595d2 | 9635 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 9636 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
9637 | return -EINVAL; |
9638 | ||
9639 | /* | |
9640 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
9641 | * Note that pitch changes could also affect these register. | |
9642 | */ | |
9643 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
9644 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
9645 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
9646 | return -EINVAL; |
9647 | ||
f900db47 CW |
9648 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
9649 | goto out_hang; | |
9650 | ||
b14c5679 | 9651 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
9652 | if (work == NULL) |
9653 | return -ENOMEM; | |
9654 | ||
6b95a207 | 9655 | work->event = event; |
b4a98e57 | 9656 | work->crtc = crtc; |
2ff8fde1 | 9657 | work->old_fb_obj = intel_fb_obj(old_fb); |
6b95a207 KH |
9658 | INIT_WORK(&work->work, intel_unpin_work_fn); |
9659 | ||
87b6b101 | 9660 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
9661 | if (ret) |
9662 | goto free_work; | |
9663 | ||
6b95a207 | 9664 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 9665 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 9666 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
9667 | /* Before declaring the flip queue wedged, check if |
9668 | * the hardware completed the operation behind our backs. | |
9669 | */ | |
9670 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
9671 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
9672 | page_flip_completed(intel_crtc); | |
9673 | } else { | |
9674 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 9675 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 9676 | |
d6bbafa1 CW |
9677 | drm_crtc_vblank_put(crtc); |
9678 | kfree(work); | |
9679 | return -EBUSY; | |
9680 | } | |
6b95a207 KH |
9681 | } |
9682 | intel_crtc->unpin_work = work; | |
5e2d7afc | 9683 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 9684 | |
b4a98e57 CW |
9685 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
9686 | flush_workqueue(dev_priv->wq); | |
9687 | ||
79158103 CW |
9688 | ret = i915_mutex_lock_interruptible(dev); |
9689 | if (ret) | |
9690 | goto cleanup; | |
6b95a207 | 9691 | |
75dfca80 | 9692 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
9693 | drm_gem_object_reference(&work->old_fb_obj->base); |
9694 | drm_gem_object_reference(&obj->base); | |
6b95a207 | 9695 | |
f4510a27 | 9696 | crtc->primary->fb = fb; |
96b099fd | 9697 | |
e1f99ce6 | 9698 | work->pending_flip_obj = obj; |
e1f99ce6 | 9699 | |
b4a98e57 | 9700 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 9701 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 9702 | |
75f7f3ec | 9703 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 9704 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 9705 | |
4fa62c89 VS |
9706 | if (IS_VALLEYVIEW(dev)) { |
9707 | ring = &dev_priv->ring[BCS]; | |
8e09bf83 CW |
9708 | if (obj->tiling_mode != work->old_fb_obj->tiling_mode) |
9709 | /* vlv: DISPLAY_FLIP fails to change tiling */ | |
9710 | ring = NULL; | |
2a92d5bc CW |
9711 | } else if (IS_IVYBRIDGE(dev)) { |
9712 | ring = &dev_priv->ring[BCS]; | |
4fa62c89 | 9713 | } else if (INTEL_INFO(dev)->gen >= 7) { |
41c52415 | 9714 | ring = i915_gem_request_get_ring(obj->last_read_req); |
4fa62c89 VS |
9715 | if (ring == NULL || ring->id != RCS) |
9716 | ring = &dev_priv->ring[BCS]; | |
9717 | } else { | |
9718 | ring = &dev_priv->ring[RCS]; | |
9719 | } | |
9720 | ||
850c4cdc | 9721 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring); |
8c9f3aaf JB |
9722 | if (ret) |
9723 | goto cleanup_pending; | |
6b95a207 | 9724 | |
4fa62c89 VS |
9725 | work->gtt_offset = |
9726 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset; | |
9727 | ||
d6bbafa1 | 9728 | if (use_mmio_flip(ring, obj)) { |
84c33a64 SG |
9729 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
9730 | page_flip_flags); | |
d6bbafa1 CW |
9731 | if (ret) |
9732 | goto cleanup_unpin; | |
9733 | ||
f06cc1b9 JH |
9734 | i915_gem_request_assign(&work->flip_queued_req, |
9735 | obj->last_write_req); | |
d6bbafa1 | 9736 | } else { |
84c33a64 | 9737 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
d6bbafa1 CW |
9738 | page_flip_flags); |
9739 | if (ret) | |
9740 | goto cleanup_unpin; | |
9741 | ||
f06cc1b9 JH |
9742 | i915_gem_request_assign(&work->flip_queued_req, |
9743 | intel_ring_get_request(ring)); | |
d6bbafa1 CW |
9744 | } |
9745 | ||
9746 | work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe); | |
9747 | work->enable_stall_check = true; | |
4fa62c89 | 9748 | |
a071fa00 DV |
9749 | i915_gem_track_fb(work->old_fb_obj, obj, |
9750 | INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
9751 | ||
7782de3b | 9752 | intel_disable_fbc(dev); |
f99d7069 | 9753 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
9754 | mutex_unlock(&dev->struct_mutex); |
9755 | ||
e5510fac JB |
9756 | trace_i915_flip_request(intel_crtc->plane, obj); |
9757 | ||
6b95a207 | 9758 | return 0; |
96b099fd | 9759 | |
4fa62c89 VS |
9760 | cleanup_unpin: |
9761 | intel_unpin_fb_obj(obj); | |
8c9f3aaf | 9762 | cleanup_pending: |
b4a98e57 | 9763 | atomic_dec(&intel_crtc->unpin_work_count); |
f4510a27 | 9764 | crtc->primary->fb = old_fb; |
05394f39 CW |
9765 | drm_gem_object_unreference(&work->old_fb_obj->base); |
9766 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
9767 | mutex_unlock(&dev->struct_mutex); |
9768 | ||
79158103 | 9769 | cleanup: |
5e2d7afc | 9770 | spin_lock_irq(&dev->event_lock); |
96b099fd | 9771 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 9772 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 9773 | |
87b6b101 | 9774 | drm_crtc_vblank_put(crtc); |
7317c75e | 9775 | free_work: |
96b099fd CW |
9776 | kfree(work); |
9777 | ||
f900db47 CW |
9778 | if (ret == -EIO) { |
9779 | out_hang: | |
455a6808 GP |
9780 | ret = primary->funcs->update_plane(primary, crtc, fb, |
9781 | intel_plane->crtc_x, | |
9782 | intel_plane->crtc_y, | |
9783 | intel_plane->crtc_h, | |
9784 | intel_plane->crtc_w, | |
9785 | intel_plane->src_x, | |
9786 | intel_plane->src_y, | |
9787 | intel_plane->src_h, | |
9788 | intel_plane->src_w); | |
f0d3dad3 | 9789 | if (ret == 0 && event) { |
5e2d7afc | 9790 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 9791 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 9792 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 9793 | } |
f900db47 | 9794 | } |
96b099fd | 9795 | return ret; |
6b95a207 KH |
9796 | } |
9797 | ||
f6e5b160 | 9798 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
9799 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
9800 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
9801 | }; |
9802 | ||
9a935856 DV |
9803 | /** |
9804 | * intel_modeset_update_staged_output_state | |
9805 | * | |
9806 | * Updates the staged output configuration state, e.g. after we've read out the | |
9807 | * current hw state. | |
9808 | */ | |
9809 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 9810 | { |
7668851f | 9811 | struct intel_crtc *crtc; |
9a935856 DV |
9812 | struct intel_encoder *encoder; |
9813 | struct intel_connector *connector; | |
f6e5b160 | 9814 | |
9a935856 DV |
9815 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9816 | base.head) { | |
9817 | connector->new_encoder = | |
9818 | to_intel_encoder(connector->base.encoder); | |
9819 | } | |
f6e5b160 | 9820 | |
b2784e15 | 9821 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
9822 | encoder->new_crtc = |
9823 | to_intel_crtc(encoder->base.crtc); | |
9824 | } | |
7668851f | 9825 | |
d3fcc808 | 9826 | for_each_intel_crtc(dev, crtc) { |
7668851f | 9827 | crtc->new_enabled = crtc->base.enabled; |
7bd0a8e7 VS |
9828 | |
9829 | if (crtc->new_enabled) | |
9830 | crtc->new_config = &crtc->config; | |
9831 | else | |
9832 | crtc->new_config = NULL; | |
7668851f | 9833 | } |
f6e5b160 CW |
9834 | } |
9835 | ||
9a935856 DV |
9836 | /** |
9837 | * intel_modeset_commit_output_state | |
9838 | * | |
9839 | * This function copies the stage display pipe configuration to the real one. | |
9840 | */ | |
9841 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
9842 | { | |
7668851f | 9843 | struct intel_crtc *crtc; |
9a935856 DV |
9844 | struct intel_encoder *encoder; |
9845 | struct intel_connector *connector; | |
f6e5b160 | 9846 | |
9a935856 DV |
9847 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
9848 | base.head) { | |
9849 | connector->base.encoder = &connector->new_encoder->base; | |
9850 | } | |
f6e5b160 | 9851 | |
b2784e15 | 9852 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
9853 | encoder->base.crtc = &encoder->new_crtc->base; |
9854 | } | |
7668851f | 9855 | |
d3fcc808 | 9856 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
9857 | crtc->base.enabled = crtc->new_enabled; |
9858 | } | |
9a935856 DV |
9859 | } |
9860 | ||
050f7aeb | 9861 | static void |
eba905b2 | 9862 | connected_sink_compute_bpp(struct intel_connector *connector, |
050f7aeb DV |
9863 | struct intel_crtc_config *pipe_config) |
9864 | { | |
9865 | int bpp = pipe_config->pipe_bpp; | |
9866 | ||
9867 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
9868 | connector->base.base.id, | |
c23cc417 | 9869 | connector->base.name); |
050f7aeb DV |
9870 | |
9871 | /* Don't use an invalid EDID bpc value */ | |
9872 | if (connector->base.display_info.bpc && | |
9873 | connector->base.display_info.bpc * 3 < bpp) { | |
9874 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
9875 | bpp, connector->base.display_info.bpc*3); | |
9876 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
9877 | } | |
9878 | ||
9879 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
9880 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
9881 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
9882 | bpp); | |
9883 | pipe_config->pipe_bpp = 24; | |
9884 | } | |
9885 | } | |
9886 | ||
4e53c2e0 | 9887 | static int |
050f7aeb DV |
9888 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
9889 | struct drm_framebuffer *fb, | |
9890 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 9891 | { |
050f7aeb DV |
9892 | struct drm_device *dev = crtc->base.dev; |
9893 | struct intel_connector *connector; | |
4e53c2e0 DV |
9894 | int bpp; |
9895 | ||
d42264b1 DV |
9896 | switch (fb->pixel_format) { |
9897 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
9898 | bpp = 8*3; /* since we go through a colormap */ |
9899 | break; | |
d42264b1 DV |
9900 | case DRM_FORMAT_XRGB1555: |
9901 | case DRM_FORMAT_ARGB1555: | |
9902 | /* checked in intel_framebuffer_init already */ | |
9903 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
9904 | return -EINVAL; | |
9905 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
9906 | bpp = 6*3; /* min is 18bpp */ |
9907 | break; | |
d42264b1 DV |
9908 | case DRM_FORMAT_XBGR8888: |
9909 | case DRM_FORMAT_ABGR8888: | |
9910 | /* checked in intel_framebuffer_init already */ | |
9911 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
9912 | return -EINVAL; | |
9913 | case DRM_FORMAT_XRGB8888: | |
9914 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
9915 | bpp = 8*3; |
9916 | break; | |
d42264b1 DV |
9917 | case DRM_FORMAT_XRGB2101010: |
9918 | case DRM_FORMAT_ARGB2101010: | |
9919 | case DRM_FORMAT_XBGR2101010: | |
9920 | case DRM_FORMAT_ABGR2101010: | |
9921 | /* checked in intel_framebuffer_init already */ | |
9922 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 9923 | return -EINVAL; |
4e53c2e0 DV |
9924 | bpp = 10*3; |
9925 | break; | |
baba133a | 9926 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
9927 | default: |
9928 | DRM_DEBUG_KMS("unsupported depth\n"); | |
9929 | return -EINVAL; | |
9930 | } | |
9931 | ||
4e53c2e0 DV |
9932 | pipe_config->pipe_bpp = bpp; |
9933 | ||
9934 | /* Clamp display bpp to EDID value */ | |
9935 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 9936 | base.head) { |
1b829e05 DV |
9937 | if (!connector->new_encoder || |
9938 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
9939 | continue; |
9940 | ||
050f7aeb | 9941 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
9942 | } |
9943 | ||
9944 | return bpp; | |
9945 | } | |
9946 | ||
644db711 DV |
9947 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
9948 | { | |
9949 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
9950 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 9951 | mode->crtc_clock, |
644db711 DV |
9952 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
9953 | mode->crtc_hsync_end, mode->crtc_htotal, | |
9954 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
9955 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
9956 | } | |
9957 | ||
c0b03411 DV |
9958 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
9959 | struct intel_crtc_config *pipe_config, | |
9960 | const char *context) | |
9961 | { | |
9962 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
9963 | context, pipe_name(crtc->pipe)); | |
9964 | ||
9965 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
9966 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
9967 | pipe_config->pipe_bpp, pipe_config->dither); | |
9968 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
9969 | pipe_config->has_pch_encoder, | |
9970 | pipe_config->fdi_lanes, | |
9971 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
9972 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
9973 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
9974 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
9975 | pipe_config->has_dp_encoder, | |
9976 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
9977 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
9978 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
9979 | |
9980 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
9981 | pipe_config->has_dp_encoder, | |
9982 | pipe_config->dp_m2_n2.gmch_m, | |
9983 | pipe_config->dp_m2_n2.gmch_n, | |
9984 | pipe_config->dp_m2_n2.link_m, | |
9985 | pipe_config->dp_m2_n2.link_n, | |
9986 | pipe_config->dp_m2_n2.tu); | |
9987 | ||
55072d19 DV |
9988 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
9989 | pipe_config->has_audio, | |
9990 | pipe_config->has_infoframe); | |
9991 | ||
c0b03411 DV |
9992 | DRM_DEBUG_KMS("requested mode:\n"); |
9993 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
9994 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
9995 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 9996 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 9997 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
9998 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
9999 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
10000 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
10001 | pipe_config->gmch_pfit.control, | |
10002 | pipe_config->gmch_pfit.pgm_ratios, | |
10003 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 10004 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 10005 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
10006 | pipe_config->pch_pfit.size, |
10007 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 10008 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 10009 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
10010 | } |
10011 | ||
bc079e8b VS |
10012 | static bool encoders_cloneable(const struct intel_encoder *a, |
10013 | const struct intel_encoder *b) | |
accfc0c5 | 10014 | { |
bc079e8b VS |
10015 | /* masks could be asymmetric, so check both ways */ |
10016 | return a == b || (a->cloneable & (1 << b->type) && | |
10017 | b->cloneable & (1 << a->type)); | |
10018 | } | |
10019 | ||
10020 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, | |
10021 | struct intel_encoder *encoder) | |
10022 | { | |
10023 | struct drm_device *dev = crtc->base.dev; | |
10024 | struct intel_encoder *source_encoder; | |
10025 | ||
b2784e15 | 10026 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b VS |
10027 | if (source_encoder->new_crtc != crtc) |
10028 | continue; | |
10029 | ||
10030 | if (!encoders_cloneable(encoder, source_encoder)) | |
10031 | return false; | |
10032 | } | |
10033 | ||
10034 | return true; | |
10035 | } | |
10036 | ||
10037 | static bool check_encoder_cloning(struct intel_crtc *crtc) | |
10038 | { | |
10039 | struct drm_device *dev = crtc->base.dev; | |
accfc0c5 DV |
10040 | struct intel_encoder *encoder; |
10041 | ||
b2784e15 | 10042 | for_each_intel_encoder(dev, encoder) { |
bc079e8b | 10043 | if (encoder->new_crtc != crtc) |
accfc0c5 DV |
10044 | continue; |
10045 | ||
bc079e8b VS |
10046 | if (!check_single_encoder_cloning(crtc, encoder)) |
10047 | return false; | |
accfc0c5 DV |
10048 | } |
10049 | ||
bc079e8b | 10050 | return true; |
accfc0c5 DV |
10051 | } |
10052 | ||
00f0b378 VS |
10053 | static bool check_digital_port_conflicts(struct drm_device *dev) |
10054 | { | |
10055 | struct intel_connector *connector; | |
10056 | unsigned int used_ports = 0; | |
10057 | ||
10058 | /* | |
10059 | * Walk the connector list instead of the encoder | |
10060 | * list to detect the problem on ddi platforms | |
10061 | * where there's just one encoder per digital port. | |
10062 | */ | |
10063 | list_for_each_entry(connector, | |
10064 | &dev->mode_config.connector_list, base.head) { | |
10065 | struct intel_encoder *encoder = connector->new_encoder; | |
10066 | ||
10067 | if (!encoder) | |
10068 | continue; | |
10069 | ||
10070 | WARN_ON(!encoder->new_crtc); | |
10071 | ||
10072 | switch (encoder->type) { | |
10073 | unsigned int port_mask; | |
10074 | case INTEL_OUTPUT_UNKNOWN: | |
10075 | if (WARN_ON(!HAS_DDI(dev))) | |
10076 | break; | |
10077 | case INTEL_OUTPUT_DISPLAYPORT: | |
10078 | case INTEL_OUTPUT_HDMI: | |
10079 | case INTEL_OUTPUT_EDP: | |
10080 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
10081 | ||
10082 | /* the same port mustn't appear more than once */ | |
10083 | if (used_ports & port_mask) | |
10084 | return false; | |
10085 | ||
10086 | used_ports |= port_mask; | |
10087 | default: | |
10088 | break; | |
10089 | } | |
10090 | } | |
10091 | ||
10092 | return true; | |
10093 | } | |
10094 | ||
b8cecdf5 DV |
10095 | static struct intel_crtc_config * |
10096 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 10097 | struct drm_framebuffer *fb, |
b8cecdf5 | 10098 | struct drm_display_mode *mode) |
ee7b9f93 | 10099 | { |
7758a113 | 10100 | struct drm_device *dev = crtc->dev; |
7758a113 | 10101 | struct intel_encoder *encoder; |
b8cecdf5 | 10102 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
10103 | int plane_bpp, ret = -EINVAL; |
10104 | bool retry = true; | |
ee7b9f93 | 10105 | |
bc079e8b | 10106 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
accfc0c5 DV |
10107 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
10108 | return ERR_PTR(-EINVAL); | |
10109 | } | |
10110 | ||
00f0b378 VS |
10111 | if (!check_digital_port_conflicts(dev)) { |
10112 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
10113 | return ERR_PTR(-EINVAL); | |
10114 | } | |
10115 | ||
b8cecdf5 DV |
10116 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10117 | if (!pipe_config) | |
7758a113 DV |
10118 | return ERR_PTR(-ENOMEM); |
10119 | ||
b8cecdf5 DV |
10120 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
10121 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 10122 | |
e143a21c DV |
10123 | pipe_config->cpu_transcoder = |
10124 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 10125 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 10126 | |
2960bc9c ID |
10127 | /* |
10128 | * Sanitize sync polarity flags based on requested ones. If neither | |
10129 | * positive or negative polarity is requested, treat this as meaning | |
10130 | * negative polarity. | |
10131 | */ | |
10132 | if (!(pipe_config->adjusted_mode.flags & | |
10133 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
10134 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
10135 | ||
10136 | if (!(pipe_config->adjusted_mode.flags & | |
10137 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
10138 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
10139 | ||
050f7aeb DV |
10140 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
10141 | * plane pixel format and any sink constraints into account. Returns the | |
10142 | * source plane bpp so that dithering can be selected on mismatches | |
10143 | * after encoders and crtc also have had their say. */ | |
10144 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
10145 | fb, pipe_config); | |
4e53c2e0 DV |
10146 | if (plane_bpp < 0) |
10147 | goto fail; | |
10148 | ||
e41a56be VS |
10149 | /* |
10150 | * Determine the real pipe dimensions. Note that stereo modes can | |
10151 | * increase the actual pipe size due to the frame doubling and | |
10152 | * insertion of additional space for blanks between the frame. This | |
10153 | * is stored in the crtc timings. We use the requested mode to do this | |
10154 | * computation to clearly distinguish it from the adjusted mode, which | |
10155 | * can be changed by the connectors in the below retry loop. | |
10156 | */ | |
ecb7e16b GP |
10157 | drm_crtc_get_hv_timing(&pipe_config->requested_mode, |
10158 | &pipe_config->pipe_src_w, | |
10159 | &pipe_config->pipe_src_h); | |
e41a56be | 10160 | |
e29c22c0 | 10161 | encoder_retry: |
ef1b460d | 10162 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10163 | pipe_config->port_clock = 0; |
ef1b460d | 10164 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10165 | |
135c81b8 | 10166 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 10167 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 10168 | |
7758a113 DV |
10169 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10170 | * adjust it according to limitations or connector properties, and also | |
10171 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10172 | */ |
b2784e15 | 10173 | for_each_intel_encoder(dev, encoder) { |
47f1c6c9 | 10174 | |
7758a113 DV |
10175 | if (&encoder->new_crtc->base != crtc) |
10176 | continue; | |
7ae89233 | 10177 | |
efea6e8e DV |
10178 | if (!(encoder->compute_config(encoder, pipe_config))) { |
10179 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
10180 | goto fail; |
10181 | } | |
ee7b9f93 | 10182 | } |
47f1c6c9 | 10183 | |
ff9a6750 DV |
10184 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10185 | * done afterwards in case the encoder adjusts the mode. */ | |
10186 | if (!pipe_config->port_clock) | |
241bfc38 DL |
10187 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
10188 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 10189 | |
a43f6e0f | 10190 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10191 | if (ret < 0) { |
7758a113 DV |
10192 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10193 | goto fail; | |
ee7b9f93 | 10194 | } |
e29c22c0 DV |
10195 | |
10196 | if (ret == RETRY) { | |
10197 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10198 | ret = -EINVAL; | |
10199 | goto fail; | |
10200 | } | |
10201 | ||
10202 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10203 | retry = false; | |
10204 | goto encoder_retry; | |
10205 | } | |
10206 | ||
4e53c2e0 DV |
10207 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
10208 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
10209 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
10210 | ||
b8cecdf5 | 10211 | return pipe_config; |
7758a113 | 10212 | fail: |
b8cecdf5 | 10213 | kfree(pipe_config); |
e29c22c0 | 10214 | return ERR_PTR(ret); |
ee7b9f93 | 10215 | } |
47f1c6c9 | 10216 | |
e2e1ed41 DV |
10217 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
10218 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
10219 | static void | |
10220 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
10221 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
10222 | { |
10223 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
10224 | struct drm_device *dev = crtc->dev; |
10225 | struct intel_encoder *encoder; | |
10226 | struct intel_connector *connector; | |
10227 | struct drm_crtc *tmp_crtc; | |
79e53945 | 10228 | |
e2e1ed41 | 10229 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 10230 | |
e2e1ed41 DV |
10231 | /* Check which crtcs have changed outputs connected to them, these need |
10232 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
10233 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
10234 | * bit set at most. */ | |
10235 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10236 | base.head) { | |
10237 | if (connector->base.encoder == &connector->new_encoder->base) | |
10238 | continue; | |
79e53945 | 10239 | |
e2e1ed41 DV |
10240 | if (connector->base.encoder) { |
10241 | tmp_crtc = connector->base.encoder->crtc; | |
10242 | ||
10243 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10244 | } | |
10245 | ||
10246 | if (connector->new_encoder) | |
10247 | *prepare_pipes |= | |
10248 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
10249 | } |
10250 | ||
b2784e15 | 10251 | for_each_intel_encoder(dev, encoder) { |
e2e1ed41 DV |
10252 | if (encoder->base.crtc == &encoder->new_crtc->base) |
10253 | continue; | |
10254 | ||
10255 | if (encoder->base.crtc) { | |
10256 | tmp_crtc = encoder->base.crtc; | |
10257 | ||
10258 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10259 | } | |
10260 | ||
10261 | if (encoder->new_crtc) | |
10262 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
10263 | } |
10264 | ||
7668851f | 10265 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 10266 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 10267 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
e2e1ed41 | 10268 | continue; |
7e7d76c3 | 10269 | |
7668851f | 10270 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 10271 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
10272 | else |
10273 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
10274 | } |
10275 | ||
e2e1ed41 DV |
10276 | |
10277 | /* set_mode is also used to update properties on life display pipes. */ | |
10278 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 10279 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
10280 | *prepare_pipes |= 1 << intel_crtc->pipe; |
10281 | ||
b6c5164d DV |
10282 | /* |
10283 | * For simplicity do a full modeset on any pipe where the output routing | |
10284 | * changed. We could be more clever, but that would require us to be | |
10285 | * more careful with calling the relevant encoder->mode_set functions. | |
10286 | */ | |
e2e1ed41 DV |
10287 | if (*prepare_pipes) |
10288 | *modeset_pipes = *prepare_pipes; | |
10289 | ||
10290 | /* ... and mask these out. */ | |
10291 | *modeset_pipes &= ~(*disable_pipes); | |
10292 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
10293 | |
10294 | /* | |
10295 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
10296 | * obies this rule, but the modeset restore mode of | |
10297 | * intel_modeset_setup_hw_state does not. | |
10298 | */ | |
10299 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
10300 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
10301 | |
10302 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
10303 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 10304 | } |
79e53945 | 10305 | |
ea9d758d | 10306 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 10307 | { |
ea9d758d | 10308 | struct drm_encoder *encoder; |
f6e5b160 | 10309 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 10310 | |
ea9d758d DV |
10311 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
10312 | if (encoder->crtc == crtc) | |
10313 | return true; | |
10314 | ||
10315 | return false; | |
10316 | } | |
10317 | ||
10318 | static void | |
10319 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
10320 | { | |
ba41c0de | 10321 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea9d758d DV |
10322 | struct intel_encoder *intel_encoder; |
10323 | struct intel_crtc *intel_crtc; | |
10324 | struct drm_connector *connector; | |
10325 | ||
ba41c0de DV |
10326 | intel_shared_dpll_commit(dev_priv); |
10327 | ||
b2784e15 | 10328 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
10329 | if (!intel_encoder->base.crtc) |
10330 | continue; | |
10331 | ||
10332 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
10333 | ||
10334 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
10335 | intel_encoder->connectors_active = false; | |
10336 | } | |
10337 | ||
10338 | intel_modeset_commit_output_state(dev); | |
10339 | ||
7668851f | 10340 | /* Double check state. */ |
d3fcc808 | 10341 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 10342 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 VS |
10343 | WARN_ON(intel_crtc->new_config && |
10344 | intel_crtc->new_config != &intel_crtc->config); | |
10345 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); | |
ea9d758d DV |
10346 | } |
10347 | ||
10348 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
10349 | if (!connector->encoder || !connector->encoder->crtc) | |
10350 | continue; | |
10351 | ||
10352 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
10353 | ||
10354 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
10355 | struct drm_property *dpms_property = |
10356 | dev->mode_config.dpms_property; | |
10357 | ||
ea9d758d | 10358 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 10359 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
10360 | dpms_property, |
10361 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
10362 | |
10363 | intel_encoder = to_intel_encoder(connector->encoder); | |
10364 | intel_encoder->connectors_active = true; | |
10365 | } | |
10366 | } | |
10367 | ||
10368 | } | |
10369 | ||
3bd26263 | 10370 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 10371 | { |
3bd26263 | 10372 | int diff; |
f1f644dc JB |
10373 | |
10374 | if (clock1 == clock2) | |
10375 | return true; | |
10376 | ||
10377 | if (!clock1 || !clock2) | |
10378 | return false; | |
10379 | ||
10380 | diff = abs(clock1 - clock2); | |
10381 | ||
10382 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
10383 | return true; | |
10384 | ||
10385 | return false; | |
10386 | } | |
10387 | ||
25c5b266 DV |
10388 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
10389 | list_for_each_entry((intel_crtc), \ | |
10390 | &(dev)->mode_config.crtc_list, \ | |
10391 | base.head) \ | |
0973f18f | 10392 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 10393 | |
0e8ffe1b | 10394 | static bool |
2fa2fe9a DV |
10395 | intel_pipe_config_compare(struct drm_device *dev, |
10396 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
10397 | struct intel_crtc_config *pipe_config) |
10398 | { | |
66e985c0 DV |
10399 | #define PIPE_CONF_CHECK_X(name) \ |
10400 | if (current_config->name != pipe_config->name) { \ | |
10401 | DRM_ERROR("mismatch in " #name " " \ | |
10402 | "(expected 0x%08x, found 0x%08x)\n", \ | |
10403 | current_config->name, \ | |
10404 | pipe_config->name); \ | |
10405 | return false; \ | |
10406 | } | |
10407 | ||
08a24034 DV |
10408 | #define PIPE_CONF_CHECK_I(name) \ |
10409 | if (current_config->name != pipe_config->name) { \ | |
10410 | DRM_ERROR("mismatch in " #name " " \ | |
10411 | "(expected %i, found %i)\n", \ | |
10412 | current_config->name, \ | |
10413 | pipe_config->name); \ | |
10414 | return false; \ | |
88adfff1 DV |
10415 | } |
10416 | ||
b95af8be VK |
10417 | /* This is required for BDW+ where there is only one set of registers for |
10418 | * switching between high and low RR. | |
10419 | * This macro can be used whenever a comparison has to be made between one | |
10420 | * hw state and multiple sw state variables. | |
10421 | */ | |
10422 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
10423 | if ((current_config->name != pipe_config->name) && \ | |
10424 | (current_config->alt_name != pipe_config->name)) { \ | |
10425 | DRM_ERROR("mismatch in " #name " " \ | |
10426 | "(expected %i or %i, found %i)\n", \ | |
10427 | current_config->name, \ | |
10428 | current_config->alt_name, \ | |
10429 | pipe_config->name); \ | |
10430 | return false; \ | |
10431 | } | |
10432 | ||
1bd1bd80 DV |
10433 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
10434 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 10435 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
10436 | "(expected %i, found %i)\n", \ |
10437 | current_config->name & (mask), \ | |
10438 | pipe_config->name & (mask)); \ | |
10439 | return false; \ | |
10440 | } | |
10441 | ||
5e550656 VS |
10442 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
10443 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
10444 | DRM_ERROR("mismatch in " #name " " \ | |
10445 | "(expected %i, found %i)\n", \ | |
10446 | current_config->name, \ | |
10447 | pipe_config->name); \ | |
10448 | return false; \ | |
10449 | } | |
10450 | ||
bb760063 DV |
10451 | #define PIPE_CONF_QUIRK(quirk) \ |
10452 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
10453 | ||
eccb140b DV |
10454 | PIPE_CONF_CHECK_I(cpu_transcoder); |
10455 | ||
08a24034 DV |
10456 | PIPE_CONF_CHECK_I(has_pch_encoder); |
10457 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
10458 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
10459 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
10460 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
10461 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
10462 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 10463 | |
eb14cb74 | 10464 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
10465 | |
10466 | if (INTEL_INFO(dev)->gen < 8) { | |
10467 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
10468 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
10469 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
10470 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
10471 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
10472 | ||
10473 | if (current_config->has_drrs) { | |
10474 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
10475 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
10476 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
10477 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
10478 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
10479 | } | |
10480 | } else { | |
10481 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
10482 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
10483 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
10484 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
10485 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
10486 | } | |
eb14cb74 | 10487 | |
1bd1bd80 DV |
10488 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
10489 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
10490 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
10491 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
10492 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
10493 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
10494 | ||
10495 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
10496 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
10497 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
10498 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
10499 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
10500 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
10501 | ||
c93f54cf | 10502 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 10503 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
10504 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
10505 | IS_VALLEYVIEW(dev)) | |
10506 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 10507 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 10508 | |
9ed109a7 DV |
10509 | PIPE_CONF_CHECK_I(has_audio); |
10510 | ||
1bd1bd80 DV |
10511 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
10512 | DRM_MODE_FLAG_INTERLACE); | |
10513 | ||
bb760063 DV |
10514 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
10515 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10516 | DRM_MODE_FLAG_PHSYNC); | |
10517 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10518 | DRM_MODE_FLAG_NHSYNC); | |
10519 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10520 | DRM_MODE_FLAG_PVSYNC); | |
10521 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10522 | DRM_MODE_FLAG_NVSYNC); | |
10523 | } | |
045ac3b5 | 10524 | |
37327abd VS |
10525 | PIPE_CONF_CHECK_I(pipe_src_w); |
10526 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 10527 | |
9953599b DV |
10528 | /* |
10529 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
10530 | * screen. Since we don't yet re-compute the pipe config when moving | |
10531 | * just the lvds port away to another pipe the sw tracking won't match. | |
10532 | * | |
10533 | * Proper atomic modesets with recomputed global state will fix this. | |
10534 | * Until then just don't check gmch state for inherited modes. | |
10535 | */ | |
10536 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
10537 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
10538 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
10539 | if (INTEL_INFO(dev)->gen < 4) | |
10540 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
10541 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
10542 | } | |
10543 | ||
fd4daa9c CW |
10544 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
10545 | if (current_config->pch_pfit.enabled) { | |
10546 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
10547 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
10548 | } | |
2fa2fe9a | 10549 | |
e59150dc JB |
10550 | /* BDW+ don't expose a synchronous way to read the state */ |
10551 | if (IS_HASWELL(dev)) | |
10552 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 10553 | |
282740f7 VS |
10554 | PIPE_CONF_CHECK_I(double_wide); |
10555 | ||
26804afd DV |
10556 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
10557 | ||
c0d43d62 | 10558 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 10559 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 10560 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
10561 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
10562 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 10563 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
10564 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
10565 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
10566 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 10567 | |
42571aef VS |
10568 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
10569 | PIPE_CONF_CHECK_I(pipe_bpp); | |
10570 | ||
a9a7e98a JB |
10571 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
10572 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | |
5e550656 | 10573 | |
66e985c0 | 10574 | #undef PIPE_CONF_CHECK_X |
08a24034 | 10575 | #undef PIPE_CONF_CHECK_I |
b95af8be | 10576 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 10577 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 10578 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 10579 | #undef PIPE_CONF_QUIRK |
88adfff1 | 10580 | |
0e8ffe1b DV |
10581 | return true; |
10582 | } | |
10583 | ||
08db6652 DL |
10584 | static void check_wm_state(struct drm_device *dev) |
10585 | { | |
10586 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10587 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
10588 | struct intel_crtc *intel_crtc; | |
10589 | int plane; | |
10590 | ||
10591 | if (INTEL_INFO(dev)->gen < 9) | |
10592 | return; | |
10593 | ||
10594 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
10595 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
10596 | ||
10597 | for_each_intel_crtc(dev, intel_crtc) { | |
10598 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
10599 | const enum pipe pipe = intel_crtc->pipe; | |
10600 | ||
10601 | if (!intel_crtc->active) | |
10602 | continue; | |
10603 | ||
10604 | /* planes */ | |
10605 | for_each_plane(pipe, plane) { | |
10606 | hw_entry = &hw_ddb.plane[pipe][plane]; | |
10607 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
10608 | ||
10609 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
10610 | continue; | |
10611 | ||
10612 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
10613 | "(expected (%u,%u), found (%u,%u))\n", | |
10614 | pipe_name(pipe), plane + 1, | |
10615 | sw_entry->start, sw_entry->end, | |
10616 | hw_entry->start, hw_entry->end); | |
10617 | } | |
10618 | ||
10619 | /* cursor */ | |
10620 | hw_entry = &hw_ddb.cursor[pipe]; | |
10621 | sw_entry = &sw_ddb->cursor[pipe]; | |
10622 | ||
10623 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
10624 | continue; | |
10625 | ||
10626 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
10627 | "(expected (%u,%u), found (%u,%u))\n", | |
10628 | pipe_name(pipe), | |
10629 | sw_entry->start, sw_entry->end, | |
10630 | hw_entry->start, hw_entry->end); | |
10631 | } | |
10632 | } | |
10633 | ||
91d1b4bd DV |
10634 | static void |
10635 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 10636 | { |
8af6cf88 DV |
10637 | struct intel_connector *connector; |
10638 | ||
10639 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10640 | base.head) { | |
10641 | /* This also checks the encoder/connector hw state with the | |
10642 | * ->get_hw_state callbacks. */ | |
10643 | intel_connector_check_state(connector); | |
10644 | ||
10645 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
10646 | "connector's staged encoder doesn't match current encoder\n"); | |
10647 | } | |
91d1b4bd DV |
10648 | } |
10649 | ||
10650 | static void | |
10651 | check_encoder_state(struct drm_device *dev) | |
10652 | { | |
10653 | struct intel_encoder *encoder; | |
10654 | struct intel_connector *connector; | |
8af6cf88 | 10655 | |
b2784e15 | 10656 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
10657 | bool enabled = false; |
10658 | bool active = false; | |
10659 | enum pipe pipe, tracked_pipe; | |
10660 | ||
10661 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
10662 | encoder->base.base.id, | |
8e329a03 | 10663 | encoder->base.name); |
8af6cf88 DV |
10664 | |
10665 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
10666 | "encoder's stage crtc doesn't match current crtc\n"); | |
10667 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
10668 | "encoder's active_connectors set, but no crtc\n"); | |
10669 | ||
10670 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10671 | base.head) { | |
10672 | if (connector->base.encoder != &encoder->base) | |
10673 | continue; | |
10674 | enabled = true; | |
10675 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
10676 | active = true; | |
10677 | } | |
0e32b39c DA |
10678 | /* |
10679 | * for MST connectors if we unplug the connector is gone | |
10680 | * away but the encoder is still connected to a crtc | |
10681 | * until a modeset happens in response to the hotplug. | |
10682 | */ | |
10683 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
10684 | continue; | |
10685 | ||
8af6cf88 DV |
10686 | WARN(!!encoder->base.crtc != enabled, |
10687 | "encoder's enabled state mismatch " | |
10688 | "(expected %i, found %i)\n", | |
10689 | !!encoder->base.crtc, enabled); | |
10690 | WARN(active && !encoder->base.crtc, | |
10691 | "active encoder with no crtc\n"); | |
10692 | ||
10693 | WARN(encoder->connectors_active != active, | |
10694 | "encoder's computed active state doesn't match tracked active state " | |
10695 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
10696 | ||
10697 | active = encoder->get_hw_state(encoder, &pipe); | |
10698 | WARN(active != encoder->connectors_active, | |
10699 | "encoder's hw state doesn't match sw tracking " | |
10700 | "(expected %i, found %i)\n", | |
10701 | encoder->connectors_active, active); | |
10702 | ||
10703 | if (!encoder->base.crtc) | |
10704 | continue; | |
10705 | ||
10706 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
10707 | WARN(active && pipe != tracked_pipe, | |
10708 | "active encoder's pipe doesn't match" | |
10709 | "(expected %i, found %i)\n", | |
10710 | tracked_pipe, pipe); | |
10711 | ||
10712 | } | |
91d1b4bd DV |
10713 | } |
10714 | ||
10715 | static void | |
10716 | check_crtc_state(struct drm_device *dev) | |
10717 | { | |
fbee40df | 10718 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10719 | struct intel_crtc *crtc; |
10720 | struct intel_encoder *encoder; | |
10721 | struct intel_crtc_config pipe_config; | |
8af6cf88 | 10722 | |
d3fcc808 | 10723 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
10724 | bool enabled = false; |
10725 | bool active = false; | |
10726 | ||
045ac3b5 JB |
10727 | memset(&pipe_config, 0, sizeof(pipe_config)); |
10728 | ||
8af6cf88 DV |
10729 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
10730 | crtc->base.base.id); | |
10731 | ||
10732 | WARN(crtc->active && !crtc->base.enabled, | |
10733 | "active crtc, but not enabled in sw tracking\n"); | |
10734 | ||
b2784e15 | 10735 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
10736 | if (encoder->base.crtc != &crtc->base) |
10737 | continue; | |
10738 | enabled = true; | |
10739 | if (encoder->connectors_active) | |
10740 | active = true; | |
10741 | } | |
6c49f241 | 10742 | |
8af6cf88 DV |
10743 | WARN(active != crtc->active, |
10744 | "crtc's computed active state doesn't match tracked active state " | |
10745 | "(expected %i, found %i)\n", active, crtc->active); | |
10746 | WARN(enabled != crtc->base.enabled, | |
10747 | "crtc's computed enabled state doesn't match tracked enabled state " | |
10748 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
10749 | ||
0e8ffe1b DV |
10750 | active = dev_priv->display.get_pipe_config(crtc, |
10751 | &pipe_config); | |
d62cf62a | 10752 | |
b6b5d049 VS |
10753 | /* hw state is inconsistent with the pipe quirk */ |
10754 | if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
10755 | (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
d62cf62a DV |
10756 | active = crtc->active; |
10757 | ||
b2784e15 | 10758 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 10759 | enum pipe pipe; |
6c49f241 DV |
10760 | if (encoder->base.crtc != &crtc->base) |
10761 | continue; | |
1d37b689 | 10762 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
10763 | encoder->get_config(encoder, &pipe_config); |
10764 | } | |
10765 | ||
0e8ffe1b DV |
10766 | WARN(crtc->active != active, |
10767 | "crtc active state doesn't match with hw state " | |
10768 | "(expected %i, found %i)\n", crtc->active, active); | |
10769 | ||
c0b03411 DV |
10770 | if (active && |
10771 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
10772 | WARN(1, "pipe state doesn't match!\n"); | |
10773 | intel_dump_pipe_config(crtc, &pipe_config, | |
10774 | "[hw state]"); | |
10775 | intel_dump_pipe_config(crtc, &crtc->config, | |
10776 | "[sw state]"); | |
10777 | } | |
8af6cf88 DV |
10778 | } |
10779 | } | |
10780 | ||
91d1b4bd DV |
10781 | static void |
10782 | check_shared_dpll_state(struct drm_device *dev) | |
10783 | { | |
fbee40df | 10784 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10785 | struct intel_crtc *crtc; |
10786 | struct intel_dpll_hw_state dpll_hw_state; | |
10787 | int i; | |
5358901f DV |
10788 | |
10789 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
10790 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10791 | int enabled_crtcs = 0, active_crtcs = 0; | |
10792 | bool active; | |
10793 | ||
10794 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
10795 | ||
10796 | DRM_DEBUG_KMS("%s\n", pll->name); | |
10797 | ||
10798 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
10799 | ||
3e369b76 | 10800 | WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 10801 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 10802 | pll->active, hweight32(pll->config.crtc_mask)); |
5358901f DV |
10803 | WARN(pll->active && !pll->on, |
10804 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
10805 | WARN(pll->on && !pll->active, |
10806 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
10807 | WARN(pll->on != active, |
10808 | "pll on state mismatch (expected %i, found %i)\n", | |
10809 | pll->on, active); | |
10810 | ||
d3fcc808 | 10811 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
10812 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
10813 | enabled_crtcs++; | |
10814 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
10815 | active_crtcs++; | |
10816 | } | |
10817 | WARN(pll->active != active_crtcs, | |
10818 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
10819 | pll->active, active_crtcs); | |
3e369b76 | 10820 | WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 10821 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 10822 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 10823 | |
3e369b76 | 10824 | WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
10825 | sizeof(dpll_hw_state)), |
10826 | "pll hw state mismatch\n"); | |
5358901f | 10827 | } |
8af6cf88 DV |
10828 | } |
10829 | ||
91d1b4bd DV |
10830 | void |
10831 | intel_modeset_check_state(struct drm_device *dev) | |
10832 | { | |
08db6652 | 10833 | check_wm_state(dev); |
91d1b4bd DV |
10834 | check_connector_state(dev); |
10835 | check_encoder_state(dev); | |
10836 | check_crtc_state(dev); | |
10837 | check_shared_dpll_state(dev); | |
10838 | } | |
10839 | ||
18442d08 VS |
10840 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
10841 | int dotclock) | |
10842 | { | |
10843 | /* | |
10844 | * FDI already provided one idea for the dotclock. | |
10845 | * Yell if the encoder disagrees. | |
10846 | */ | |
241bfc38 | 10847 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 10848 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 10849 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
10850 | } |
10851 | ||
80715b2f VS |
10852 | static void update_scanline_offset(struct intel_crtc *crtc) |
10853 | { | |
10854 | struct drm_device *dev = crtc->base.dev; | |
10855 | ||
10856 | /* | |
10857 | * The scanline counter increments at the leading edge of hsync. | |
10858 | * | |
10859 | * On most platforms it starts counting from vtotal-1 on the | |
10860 | * first active line. That means the scanline counter value is | |
10861 | * always one less than what we would expect. Ie. just after | |
10862 | * start of vblank, which also occurs at start of hsync (on the | |
10863 | * last active line), the scanline counter will read vblank_start-1. | |
10864 | * | |
10865 | * On gen2 the scanline counter starts counting from 1 instead | |
10866 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
10867 | * to keep the value positive), instead of adding one. | |
10868 | * | |
10869 | * On HSW+ the behaviour of the scanline counter depends on the output | |
10870 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
10871 | * there's an extra 1 line difference. So we need to add two instead of | |
10872 | * one to the value. | |
10873 | */ | |
10874 | if (IS_GEN2(dev)) { | |
10875 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
10876 | int vtotal; | |
10877 | ||
10878 | vtotal = mode->crtc_vtotal; | |
10879 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
10880 | vtotal /= 2; | |
10881 | ||
10882 | crtc->scanline_offset = vtotal - 1; | |
10883 | } else if (HAS_DDI(dev) && | |
409ee761 | 10884 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
10885 | crtc->scanline_offset = 2; |
10886 | } else | |
10887 | crtc->scanline_offset = 1; | |
10888 | } | |
10889 | ||
7f27126e JB |
10890 | static struct intel_crtc_config * |
10891 | intel_modeset_compute_config(struct drm_crtc *crtc, | |
10892 | struct drm_display_mode *mode, | |
10893 | struct drm_framebuffer *fb, | |
10894 | unsigned *modeset_pipes, | |
10895 | unsigned *prepare_pipes, | |
10896 | unsigned *disable_pipes) | |
10897 | { | |
10898 | struct intel_crtc_config *pipe_config = NULL; | |
10899 | ||
10900 | intel_modeset_affected_pipes(crtc, modeset_pipes, | |
10901 | prepare_pipes, disable_pipes); | |
10902 | ||
10903 | if ((*modeset_pipes) == 0) | |
10904 | goto out; | |
10905 | ||
10906 | /* | |
10907 | * Note this needs changes when we start tracking multiple modes | |
10908 | * and crtcs. At that point we'll need to compute the whole config | |
10909 | * (i.e. one pipe_config for each crtc) rather than just the one | |
10910 | * for this crtc. | |
10911 | */ | |
10912 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); | |
10913 | if (IS_ERR(pipe_config)) { | |
10914 | goto out; | |
10915 | } | |
10916 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, | |
10917 | "[modeset]"); | |
7f27126e JB |
10918 | |
10919 | out: | |
10920 | return pipe_config; | |
10921 | } | |
10922 | ||
f30da187 DV |
10923 | static int __intel_set_mode(struct drm_crtc *crtc, |
10924 | struct drm_display_mode *mode, | |
7f27126e JB |
10925 | int x, int y, struct drm_framebuffer *fb, |
10926 | struct intel_crtc_config *pipe_config, | |
10927 | unsigned modeset_pipes, | |
10928 | unsigned prepare_pipes, | |
10929 | unsigned disable_pipes) | |
a6778b3c DV |
10930 | { |
10931 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10932 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 10933 | struct drm_display_mode *saved_mode; |
25c5b266 | 10934 | struct intel_crtc *intel_crtc; |
c0c36b94 | 10935 | int ret = 0; |
a6778b3c | 10936 | |
4b4b9238 | 10937 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
10938 | if (!saved_mode) |
10939 | return -ENOMEM; | |
a6778b3c | 10940 | |
3ac18232 | 10941 | *saved_mode = crtc->mode; |
a6778b3c | 10942 | |
b9950a13 VS |
10943 | if (modeset_pipes) |
10944 | to_intel_crtc(crtc)->new_config = pipe_config; | |
10945 | ||
30a970c6 JB |
10946 | /* |
10947 | * See if the config requires any additional preparation, e.g. | |
10948 | * to adjust global state with pipes off. We need to do this | |
10949 | * here so we can get the modeset_pipe updated config for the new | |
10950 | * mode set on this crtc. For other crtcs we need to use the | |
10951 | * adjusted_mode bits in the crtc directly. | |
10952 | */ | |
c164f833 | 10953 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 10954 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 10955 | |
c164f833 VS |
10956 | /* may have added more to prepare_pipes than we should */ |
10957 | prepare_pipes &= ~disable_pipes; | |
10958 | } | |
10959 | ||
8bd31e67 ACO |
10960 | if (dev_priv->display.crtc_compute_clock) { |
10961 | unsigned clear_pipes = modeset_pipes | disable_pipes; | |
10962 | ||
10963 | ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); | |
10964 | if (ret) | |
10965 | goto done; | |
10966 | ||
10967 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { | |
10968 | ret = dev_priv->display.crtc_compute_clock(intel_crtc); | |
10969 | if (ret) { | |
10970 | intel_shared_dpll_abort_config(dev_priv); | |
10971 | goto done; | |
10972 | } | |
10973 | } | |
10974 | } | |
10975 | ||
460da916 DV |
10976 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
10977 | intel_crtc_disable(&intel_crtc->base); | |
10978 | ||
ea9d758d DV |
10979 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
10980 | if (intel_crtc->base.enabled) | |
10981 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
10982 | } | |
a6778b3c | 10983 | |
6c4c86f5 DV |
10984 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
10985 | * to set it here already despite that we pass it down the callchain. | |
7f27126e JB |
10986 | * |
10987 | * Note we'll need to fix this up when we start tracking multiple | |
10988 | * pipes; here we assume a single modeset_pipe and only track the | |
10989 | * single crtc and mode. | |
f6e5b160 | 10990 | */ |
b8cecdf5 | 10991 | if (modeset_pipes) { |
25c5b266 | 10992 | crtc->mode = *mode; |
b8cecdf5 DV |
10993 | /* mode_set/enable/disable functions rely on a correct pipe |
10994 | * config. */ | |
10995 | to_intel_crtc(crtc)->config = *pipe_config; | |
50741abc | 10996 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
c326c0a9 VS |
10997 | |
10998 | /* | |
10999 | * Calculate and store various constants which | |
11000 | * are later needed by vblank and swap-completion | |
11001 | * timestamping. They are derived from true hwmode. | |
11002 | */ | |
11003 | drm_calc_timestamping_constants(crtc, | |
11004 | &pipe_config->adjusted_mode); | |
b8cecdf5 | 11005 | } |
7758a113 | 11006 | |
ea9d758d DV |
11007 | /* Only after disabling all output pipelines that will be changed can we |
11008 | * update the the output configuration. */ | |
11009 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 11010 | |
50f6e502 | 11011 | modeset_update_crtc_power_domains(dev); |
47fab737 | 11012 | |
a6778b3c DV |
11013 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
11014 | * on the DPLL. | |
f6e5b160 | 11015 | */ |
25c5b266 | 11016 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
455a6808 GP |
11017 | struct drm_plane *primary = intel_crtc->base.primary; |
11018 | int vdisplay, hdisplay; | |
4c10794f | 11019 | |
455a6808 GP |
11020 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); |
11021 | ret = primary->funcs->update_plane(primary, &intel_crtc->base, | |
11022 | fb, 0, 0, | |
11023 | hdisplay, vdisplay, | |
11024 | x << 16, y << 16, | |
11025 | hdisplay << 16, vdisplay << 16); | |
a6778b3c DV |
11026 | } |
11027 | ||
11028 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
11029 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
11030 | update_scanline_offset(intel_crtc); | |
11031 | ||
25c5b266 | 11032 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 11033 | } |
a6778b3c | 11034 | |
a6778b3c DV |
11035 | /* FIXME: add subpixel order */ |
11036 | done: | |
4b4b9238 | 11037 | if (ret && crtc->enabled) |
3ac18232 | 11038 | crtc->mode = *saved_mode; |
a6778b3c | 11039 | |
b8cecdf5 | 11040 | kfree(pipe_config); |
3ac18232 | 11041 | kfree(saved_mode); |
a6778b3c | 11042 | return ret; |
f6e5b160 CW |
11043 | } |
11044 | ||
7f27126e JB |
11045 | static int intel_set_mode_pipes(struct drm_crtc *crtc, |
11046 | struct drm_display_mode *mode, | |
11047 | int x, int y, struct drm_framebuffer *fb, | |
11048 | struct intel_crtc_config *pipe_config, | |
11049 | unsigned modeset_pipes, | |
11050 | unsigned prepare_pipes, | |
11051 | unsigned disable_pipes) | |
f30da187 DV |
11052 | { |
11053 | int ret; | |
11054 | ||
7f27126e JB |
11055 | ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes, |
11056 | prepare_pipes, disable_pipes); | |
f30da187 DV |
11057 | |
11058 | if (ret == 0) | |
11059 | intel_modeset_check_state(crtc->dev); | |
11060 | ||
11061 | return ret; | |
11062 | } | |
11063 | ||
7f27126e JB |
11064 | static int intel_set_mode(struct drm_crtc *crtc, |
11065 | struct drm_display_mode *mode, | |
11066 | int x, int y, struct drm_framebuffer *fb) | |
11067 | { | |
11068 | struct intel_crtc_config *pipe_config; | |
11069 | unsigned modeset_pipes, prepare_pipes, disable_pipes; | |
11070 | ||
11071 | pipe_config = intel_modeset_compute_config(crtc, mode, fb, | |
11072 | &modeset_pipes, | |
11073 | &prepare_pipes, | |
11074 | &disable_pipes); | |
11075 | ||
11076 | if (IS_ERR(pipe_config)) | |
11077 | return PTR_ERR(pipe_config); | |
11078 | ||
11079 | return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config, | |
11080 | modeset_pipes, prepare_pipes, | |
11081 | disable_pipes); | |
11082 | } | |
11083 | ||
c0c36b94 CW |
11084 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
11085 | { | |
f4510a27 | 11086 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
c0c36b94 CW |
11087 | } |
11088 | ||
25c5b266 DV |
11089 | #undef for_each_intel_crtc_masked |
11090 | ||
d9e55608 DV |
11091 | static void intel_set_config_free(struct intel_set_config *config) |
11092 | { | |
11093 | if (!config) | |
11094 | return; | |
11095 | ||
1aa4b628 DV |
11096 | kfree(config->save_connector_encoders); |
11097 | kfree(config->save_encoder_crtcs); | |
7668851f | 11098 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
11099 | kfree(config); |
11100 | } | |
11101 | ||
85f9eb71 DV |
11102 | static int intel_set_config_save_state(struct drm_device *dev, |
11103 | struct intel_set_config *config) | |
11104 | { | |
7668851f | 11105 | struct drm_crtc *crtc; |
85f9eb71 DV |
11106 | struct drm_encoder *encoder; |
11107 | struct drm_connector *connector; | |
11108 | int count; | |
11109 | ||
7668851f VS |
11110 | config->save_crtc_enabled = |
11111 | kcalloc(dev->mode_config.num_crtc, | |
11112 | sizeof(bool), GFP_KERNEL); | |
11113 | if (!config->save_crtc_enabled) | |
11114 | return -ENOMEM; | |
11115 | ||
1aa4b628 DV |
11116 | config->save_encoder_crtcs = |
11117 | kcalloc(dev->mode_config.num_encoder, | |
11118 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
11119 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
11120 | return -ENOMEM; |
11121 | ||
1aa4b628 DV |
11122 | config->save_connector_encoders = |
11123 | kcalloc(dev->mode_config.num_connector, | |
11124 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
11125 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
11126 | return -ENOMEM; |
11127 | ||
11128 | /* Copy data. Note that driver private data is not affected. | |
11129 | * Should anything bad happen only the expected state is | |
11130 | * restored, not the drivers personal bookkeeping. | |
11131 | */ | |
7668851f | 11132 | count = 0; |
70e1e0ec | 11133 | for_each_crtc(dev, crtc) { |
7668851f VS |
11134 | config->save_crtc_enabled[count++] = crtc->enabled; |
11135 | } | |
11136 | ||
85f9eb71 DV |
11137 | count = 0; |
11138 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 11139 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
11140 | } |
11141 | ||
11142 | count = 0; | |
11143 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 11144 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
11145 | } |
11146 | ||
11147 | return 0; | |
11148 | } | |
11149 | ||
11150 | static void intel_set_config_restore_state(struct drm_device *dev, | |
11151 | struct intel_set_config *config) | |
11152 | { | |
7668851f | 11153 | struct intel_crtc *crtc; |
9a935856 DV |
11154 | struct intel_encoder *encoder; |
11155 | struct intel_connector *connector; | |
85f9eb71 DV |
11156 | int count; |
11157 | ||
7668851f | 11158 | count = 0; |
d3fcc808 | 11159 | for_each_intel_crtc(dev, crtc) { |
7668851f | 11160 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
7bd0a8e7 VS |
11161 | |
11162 | if (crtc->new_enabled) | |
11163 | crtc->new_config = &crtc->config; | |
11164 | else | |
11165 | crtc->new_config = NULL; | |
7668851f VS |
11166 | } |
11167 | ||
85f9eb71 | 11168 | count = 0; |
b2784e15 | 11169 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
11170 | encoder->new_crtc = |
11171 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
11172 | } |
11173 | ||
11174 | count = 0; | |
9a935856 DV |
11175 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
11176 | connector->new_encoder = | |
11177 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
11178 | } |
11179 | } | |
11180 | ||
e3de42b6 | 11181 | static bool |
2e57f47d | 11182 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
11183 | { |
11184 | int i; | |
11185 | ||
2e57f47d CW |
11186 | if (set->num_connectors == 0) |
11187 | return false; | |
11188 | ||
11189 | if (WARN_ON(set->connectors == NULL)) | |
11190 | return false; | |
11191 | ||
11192 | for (i = 0; i < set->num_connectors; i++) | |
11193 | if (set->connectors[i]->encoder && | |
11194 | set->connectors[i]->encoder->crtc == set->crtc && | |
11195 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
11196 | return true; |
11197 | ||
11198 | return false; | |
11199 | } | |
11200 | ||
5e2b584e DV |
11201 | static void |
11202 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
11203 | struct intel_set_config *config) | |
11204 | { | |
11205 | ||
11206 | /* We should be able to check here if the fb has the same properties | |
11207 | * and then just flip_or_move it */ | |
2e57f47d CW |
11208 | if (is_crtc_connector_off(set)) { |
11209 | config->mode_changed = true; | |
f4510a27 | 11210 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
11211 | /* |
11212 | * If we have no fb, we can only flip as long as the crtc is | |
11213 | * active, otherwise we need a full mode set. The crtc may | |
11214 | * be active if we've only disabled the primary plane, or | |
11215 | * in fastboot situations. | |
11216 | */ | |
f4510a27 | 11217 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
11218 | struct intel_crtc *intel_crtc = |
11219 | to_intel_crtc(set->crtc); | |
11220 | ||
3b150f08 | 11221 | if (intel_crtc->active) { |
319d9827 JB |
11222 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
11223 | config->fb_changed = true; | |
11224 | } else { | |
11225 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
11226 | config->mode_changed = true; | |
11227 | } | |
5e2b584e DV |
11228 | } else if (set->fb == NULL) { |
11229 | config->mode_changed = true; | |
72f4901e | 11230 | } else if (set->fb->pixel_format != |
f4510a27 | 11231 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 11232 | config->mode_changed = true; |
e3de42b6 | 11233 | } else { |
5e2b584e | 11234 | config->fb_changed = true; |
e3de42b6 | 11235 | } |
5e2b584e DV |
11236 | } |
11237 | ||
835c5873 | 11238 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
11239 | config->fb_changed = true; |
11240 | ||
11241 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
11242 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
11243 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
11244 | drm_mode_debug_printmodeline(set->mode); | |
11245 | config->mode_changed = true; | |
11246 | } | |
a1d95703 CW |
11247 | |
11248 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
11249 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
11250 | } |
11251 | ||
2e431051 | 11252 | static int |
9a935856 DV |
11253 | intel_modeset_stage_output_state(struct drm_device *dev, |
11254 | struct drm_mode_set *set, | |
11255 | struct intel_set_config *config) | |
50f56119 | 11256 | { |
9a935856 DV |
11257 | struct intel_connector *connector; |
11258 | struct intel_encoder *encoder; | |
7668851f | 11259 | struct intel_crtc *crtc; |
f3f08572 | 11260 | int ro; |
50f56119 | 11261 | |
9abdda74 | 11262 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
11263 | * of connectors. For paranoia, double-check this. */ |
11264 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
11265 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
11266 | ||
9a935856 DV |
11267 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11268 | base.head) { | |
11269 | /* Otherwise traverse passed in connector list and get encoders | |
11270 | * for them. */ | |
50f56119 | 11271 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 | 11272 | if (set->connectors[ro] == &connector->base) { |
0e32b39c | 11273 | connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
50f56119 DV |
11274 | break; |
11275 | } | |
11276 | } | |
11277 | ||
9a935856 DV |
11278 | /* If we disable the crtc, disable all its connectors. Also, if |
11279 | * the connector is on the changing crtc but not on the new | |
11280 | * connector list, disable it. */ | |
11281 | if ((!set->fb || ro == set->num_connectors) && | |
11282 | connector->base.encoder && | |
11283 | connector->base.encoder->crtc == set->crtc) { | |
11284 | connector->new_encoder = NULL; | |
11285 | ||
11286 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
11287 | connector->base.base.id, | |
c23cc417 | 11288 | connector->base.name); |
9a935856 DV |
11289 | } |
11290 | ||
11291 | ||
11292 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 11293 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 11294 | config->mode_changed = true; |
50f56119 DV |
11295 | } |
11296 | } | |
9a935856 | 11297 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 11298 | |
9a935856 | 11299 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
11300 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11301 | base.head) { | |
7668851f VS |
11302 | struct drm_crtc *new_crtc; |
11303 | ||
9a935856 | 11304 | if (!connector->new_encoder) |
50f56119 DV |
11305 | continue; |
11306 | ||
9a935856 | 11307 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
11308 | |
11309 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 11310 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
11311 | new_crtc = set->crtc; |
11312 | } | |
11313 | ||
11314 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
11315 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
11316 | new_crtc)) { | |
5e2b584e | 11317 | return -EINVAL; |
50f56119 | 11318 | } |
0e32b39c | 11319 | connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
9a935856 DV |
11320 | |
11321 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
11322 | connector->base.base.id, | |
c23cc417 | 11323 | connector->base.name, |
9a935856 DV |
11324 | new_crtc->base.id); |
11325 | } | |
11326 | ||
11327 | /* Check for any encoders that needs to be disabled. */ | |
b2784e15 | 11328 | for_each_intel_encoder(dev, encoder) { |
5a65f358 | 11329 | int num_connectors = 0; |
9a935856 DV |
11330 | list_for_each_entry(connector, |
11331 | &dev->mode_config.connector_list, | |
11332 | base.head) { | |
11333 | if (connector->new_encoder == encoder) { | |
11334 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 11335 | num_connectors++; |
9a935856 DV |
11336 | } |
11337 | } | |
5a65f358 PZ |
11338 | |
11339 | if (num_connectors == 0) | |
11340 | encoder->new_crtc = NULL; | |
11341 | else if (num_connectors > 1) | |
11342 | return -EINVAL; | |
11343 | ||
9a935856 DV |
11344 | /* Only now check for crtc changes so we don't miss encoders |
11345 | * that will be disabled. */ | |
11346 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 11347 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 11348 | config->mode_changed = true; |
50f56119 DV |
11349 | } |
11350 | } | |
9a935856 | 11351 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
0e32b39c DA |
11352 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11353 | base.head) { | |
11354 | if (connector->new_encoder) | |
11355 | if (connector->new_encoder != connector->encoder) | |
11356 | connector->encoder = connector->new_encoder; | |
11357 | } | |
d3fcc808 | 11358 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
11359 | crtc->new_enabled = false; |
11360 | ||
b2784e15 | 11361 | for_each_intel_encoder(dev, encoder) { |
7668851f VS |
11362 | if (encoder->new_crtc == crtc) { |
11363 | crtc->new_enabled = true; | |
11364 | break; | |
11365 | } | |
11366 | } | |
11367 | ||
11368 | if (crtc->new_enabled != crtc->base.enabled) { | |
11369 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", | |
11370 | crtc->new_enabled ? "en" : "dis"); | |
11371 | config->mode_changed = true; | |
11372 | } | |
7bd0a8e7 VS |
11373 | |
11374 | if (crtc->new_enabled) | |
11375 | crtc->new_config = &crtc->config; | |
11376 | else | |
11377 | crtc->new_config = NULL; | |
7668851f VS |
11378 | } |
11379 | ||
2e431051 DV |
11380 | return 0; |
11381 | } | |
11382 | ||
7d00a1f5 VS |
11383 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
11384 | { | |
11385 | struct drm_device *dev = crtc->base.dev; | |
11386 | struct intel_encoder *encoder; | |
11387 | struct intel_connector *connector; | |
11388 | ||
11389 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
11390 | pipe_name(crtc->pipe)); | |
11391 | ||
11392 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { | |
11393 | if (connector->new_encoder && | |
11394 | connector->new_encoder->new_crtc == crtc) | |
11395 | connector->new_encoder = NULL; | |
11396 | } | |
11397 | ||
b2784e15 | 11398 | for_each_intel_encoder(dev, encoder) { |
7d00a1f5 VS |
11399 | if (encoder->new_crtc == crtc) |
11400 | encoder->new_crtc = NULL; | |
11401 | } | |
11402 | ||
11403 | crtc->new_enabled = false; | |
7bd0a8e7 | 11404 | crtc->new_config = NULL; |
7d00a1f5 VS |
11405 | } |
11406 | ||
2e431051 DV |
11407 | static int intel_crtc_set_config(struct drm_mode_set *set) |
11408 | { | |
11409 | struct drm_device *dev; | |
2e431051 DV |
11410 | struct drm_mode_set save_set; |
11411 | struct intel_set_config *config; | |
50f52756 JB |
11412 | struct intel_crtc_config *pipe_config; |
11413 | unsigned modeset_pipes, prepare_pipes, disable_pipes; | |
2e431051 | 11414 | int ret; |
2e431051 | 11415 | |
8d3e375e DV |
11416 | BUG_ON(!set); |
11417 | BUG_ON(!set->crtc); | |
11418 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 11419 | |
7e53f3a4 DV |
11420 | /* Enforce sane interface api - has been abused by the fb helper. */ |
11421 | BUG_ON(!set->mode && set->fb); | |
11422 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 11423 | |
2e431051 DV |
11424 | if (set->fb) { |
11425 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
11426 | set->crtc->base.id, set->fb->base.id, | |
11427 | (int)set->num_connectors, set->x, set->y); | |
11428 | } else { | |
11429 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
11430 | } |
11431 | ||
11432 | dev = set->crtc->dev; | |
11433 | ||
11434 | ret = -ENOMEM; | |
11435 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
11436 | if (!config) | |
11437 | goto out_config; | |
11438 | ||
11439 | ret = intel_set_config_save_state(dev, config); | |
11440 | if (ret) | |
11441 | goto out_config; | |
11442 | ||
11443 | save_set.crtc = set->crtc; | |
11444 | save_set.mode = &set->crtc->mode; | |
11445 | save_set.x = set->crtc->x; | |
11446 | save_set.y = set->crtc->y; | |
f4510a27 | 11447 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
11448 | |
11449 | /* Compute whether we need a full modeset, only an fb base update or no | |
11450 | * change at all. In the future we might also check whether only the | |
11451 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
11452 | * such cases. */ | |
11453 | intel_set_config_compute_mode_changes(set, config); | |
11454 | ||
9a935856 | 11455 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
11456 | if (ret) |
11457 | goto fail; | |
11458 | ||
50f52756 JB |
11459 | pipe_config = intel_modeset_compute_config(set->crtc, set->mode, |
11460 | set->fb, | |
11461 | &modeset_pipes, | |
11462 | &prepare_pipes, | |
11463 | &disable_pipes); | |
20664591 | 11464 | if (IS_ERR(pipe_config)) { |
6ac0483b | 11465 | ret = PTR_ERR(pipe_config); |
50f52756 | 11466 | goto fail; |
20664591 | 11467 | } else if (pipe_config) { |
b9950a13 | 11468 | if (pipe_config->has_audio != |
20664591 JB |
11469 | to_intel_crtc(set->crtc)->config.has_audio) |
11470 | config->mode_changed = true; | |
11471 | ||
11472 | /* Force mode sets for any infoframe stuff */ | |
b9950a13 | 11473 | if (pipe_config->has_infoframe || |
20664591 JB |
11474 | to_intel_crtc(set->crtc)->config.has_infoframe) |
11475 | config->mode_changed = true; | |
11476 | } | |
50f52756 JB |
11477 | |
11478 | /* set_mode will free it in the mode_changed case */ | |
11479 | if (!config->mode_changed) | |
11480 | kfree(pipe_config); | |
11481 | ||
1f9954d0 JB |
11482 | intel_update_pipe_size(to_intel_crtc(set->crtc)); |
11483 | ||
5e2b584e | 11484 | if (config->mode_changed) { |
50f52756 JB |
11485 | ret = intel_set_mode_pipes(set->crtc, set->mode, |
11486 | set->x, set->y, set->fb, pipe_config, | |
11487 | modeset_pipes, prepare_pipes, | |
11488 | disable_pipes); | |
5e2b584e | 11489 | } else if (config->fb_changed) { |
3b150f08 | 11490 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
455a6808 GP |
11491 | struct drm_plane *primary = set->crtc->primary; |
11492 | int vdisplay, hdisplay; | |
11493 | ||
11494 | drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay); | |
11495 | ret = primary->funcs->update_plane(primary, set->crtc, set->fb, | |
11496 | 0, 0, hdisplay, vdisplay, | |
11497 | set->x << 16, set->y << 16, | |
11498 | hdisplay << 16, vdisplay << 16); | |
3b150f08 MR |
11499 | |
11500 | /* | |
11501 | * We need to make sure the primary plane is re-enabled if it | |
11502 | * has previously been turned off. | |
11503 | */ | |
11504 | if (!intel_crtc->primary_enabled && ret == 0) { | |
11505 | WARN_ON(!intel_crtc->active); | |
fdd508a6 | 11506 | intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); |
3b150f08 MR |
11507 | } |
11508 | ||
7ca51a3a JB |
11509 | /* |
11510 | * In the fastboot case this may be our only check of the | |
11511 | * state after boot. It would be better to only do it on | |
11512 | * the first update, but we don't have a nice way of doing that | |
11513 | * (and really, set_config isn't used much for high freq page | |
11514 | * flipping, so increasing its cost here shouldn't be a big | |
11515 | * deal). | |
11516 | */ | |
d330a953 | 11517 | if (i915.fastboot && ret == 0) |
7ca51a3a | 11518 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
11519 | } |
11520 | ||
2d05eae1 | 11521 | if (ret) { |
bf67dfeb DV |
11522 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
11523 | set->crtc->base.id, ret); | |
50f56119 | 11524 | fail: |
2d05eae1 | 11525 | intel_set_config_restore_state(dev, config); |
50f56119 | 11526 | |
7d00a1f5 VS |
11527 | /* |
11528 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
11529 | * force the pipe off to avoid oopsing in the modeset code | |
11530 | * due to fb==NULL. This should only happen during boot since | |
11531 | * we don't yet reconstruct the FB from the hardware state. | |
11532 | */ | |
11533 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
11534 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
11535 | ||
2d05eae1 CW |
11536 | /* Try to restore the config */ |
11537 | if (config->mode_changed && | |
11538 | intel_set_mode(save_set.crtc, save_set.mode, | |
11539 | save_set.x, save_set.y, save_set.fb)) | |
11540 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
11541 | } | |
50f56119 | 11542 | |
d9e55608 DV |
11543 | out_config: |
11544 | intel_set_config_free(config); | |
50f56119 DV |
11545 | return ret; |
11546 | } | |
f6e5b160 CW |
11547 | |
11548 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 11549 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 11550 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
11551 | .destroy = intel_crtc_destroy, |
11552 | .page_flip = intel_crtc_page_flip, | |
11553 | }; | |
11554 | ||
5358901f DV |
11555 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
11556 | struct intel_shared_dpll *pll, | |
11557 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 11558 | { |
5358901f | 11559 | uint32_t val; |
ee7b9f93 | 11560 | |
f458ebbc | 11561 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
11562 | return false; |
11563 | ||
5358901f | 11564 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
11565 | hw_state->dpll = val; |
11566 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
11567 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
11568 | |
11569 | return val & DPLL_VCO_ENABLE; | |
11570 | } | |
11571 | ||
15bdd4cf DV |
11572 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
11573 | struct intel_shared_dpll *pll) | |
11574 | { | |
3e369b76 ACO |
11575 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
11576 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
11577 | } |
11578 | ||
e7b903d2 DV |
11579 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
11580 | struct intel_shared_dpll *pll) | |
11581 | { | |
e7b903d2 | 11582 | /* PCH refclock must be enabled first */ |
89eff4be | 11583 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 11584 | |
3e369b76 | 11585 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
11586 | |
11587 | /* Wait for the clocks to stabilize. */ | |
11588 | POSTING_READ(PCH_DPLL(pll->id)); | |
11589 | udelay(150); | |
11590 | ||
11591 | /* The pixel multiplier can only be updated once the | |
11592 | * DPLL is enabled and the clocks are stable. | |
11593 | * | |
11594 | * So write it again. | |
11595 | */ | |
3e369b76 | 11596 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 11597 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
11598 | udelay(200); |
11599 | } | |
11600 | ||
11601 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
11602 | struct intel_shared_dpll *pll) | |
11603 | { | |
11604 | struct drm_device *dev = dev_priv->dev; | |
11605 | struct intel_crtc *crtc; | |
e7b903d2 DV |
11606 | |
11607 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 11608 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
11609 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
11610 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
11611 | } |
11612 | ||
15bdd4cf DV |
11613 | I915_WRITE(PCH_DPLL(pll->id), 0); |
11614 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
11615 | udelay(200); |
11616 | } | |
11617 | ||
46edb027 DV |
11618 | static char *ibx_pch_dpll_names[] = { |
11619 | "PCH DPLL A", | |
11620 | "PCH DPLL B", | |
11621 | }; | |
11622 | ||
7c74ade1 | 11623 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 11624 | { |
e7b903d2 | 11625 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
11626 | int i; |
11627 | ||
7c74ade1 | 11628 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 11629 | |
e72f9fbf | 11630 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
11631 | dev_priv->shared_dplls[i].id = i; |
11632 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 11633 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
11634 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
11635 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
11636 | dev_priv->shared_dplls[i].get_hw_state = |
11637 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
11638 | } |
11639 | } | |
11640 | ||
7c74ade1 DV |
11641 | static void intel_shared_dpll_init(struct drm_device *dev) |
11642 | { | |
e7b903d2 | 11643 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 11644 | |
9cd86933 DV |
11645 | if (HAS_DDI(dev)) |
11646 | intel_ddi_pll_init(dev); | |
11647 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
11648 | ibx_pch_dpll_init(dev); |
11649 | else | |
11650 | dev_priv->num_shared_dpll = 0; | |
11651 | ||
11652 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
11653 | } |
11654 | ||
6beb8c23 MR |
11655 | /** |
11656 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
11657 | * @plane: drm plane to prepare for | |
11658 | * @fb: framebuffer to prepare for presentation | |
11659 | * | |
11660 | * Prepares a framebuffer for usage on a display plane. Generally this | |
11661 | * involves pinning the underlying object and updating the frontbuffer tracking | |
11662 | * bits. Some older platforms need special physical address handling for | |
11663 | * cursor planes. | |
11664 | * | |
11665 | * Returns 0 on success, negative error code on failure. | |
11666 | */ | |
11667 | int | |
11668 | intel_prepare_plane_fb(struct drm_plane *plane, | |
11669 | struct drm_framebuffer *fb) | |
11670 | { | |
11671 | struct drm_device *dev = plane->dev; | |
11672 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
11673 | enum pipe pipe = intel_plane->pipe; | |
11674 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
11675 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
11676 | unsigned frontbuffer_bits = 0; | |
11677 | int ret = 0; | |
11678 | ||
11679 | if (WARN_ON(fb == plane->fb || !obj)) | |
11680 | return 0; | |
11681 | ||
11682 | switch (plane->type) { | |
11683 | case DRM_PLANE_TYPE_PRIMARY: | |
11684 | frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe); | |
11685 | break; | |
11686 | case DRM_PLANE_TYPE_CURSOR: | |
11687 | frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe); | |
11688 | break; | |
11689 | case DRM_PLANE_TYPE_OVERLAY: | |
11690 | frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe); | |
11691 | break; | |
11692 | } | |
11693 | ||
11694 | mutex_lock(&dev->struct_mutex); | |
11695 | ||
11696 | if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
11697 | INTEL_INFO(dev)->cursor_needs_physical) { | |
11698 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
11699 | ret = i915_gem_object_attach_phys(obj, align); | |
11700 | if (ret) | |
11701 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
11702 | } else { | |
11703 | ret = intel_pin_and_fence_fb_obj(plane, fb, NULL); | |
11704 | } | |
11705 | ||
11706 | if (ret == 0) | |
11707 | i915_gem_track_fb(old_obj, obj, frontbuffer_bits); | |
11708 | ||
11709 | mutex_unlock(&dev->struct_mutex); | |
11710 | ||
11711 | return ret; | |
11712 | } | |
11713 | ||
38f3ce3a MR |
11714 | /** |
11715 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
11716 | * @plane: drm plane to clean up for | |
11717 | * @fb: old framebuffer that was on plane | |
11718 | * | |
11719 | * Cleans up a framebuffer that has just been removed from a plane. | |
11720 | */ | |
11721 | void | |
11722 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
11723 | struct drm_framebuffer *fb) | |
11724 | { | |
11725 | struct drm_device *dev = plane->dev; | |
11726 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
11727 | ||
11728 | if (WARN_ON(!obj)) | |
11729 | return; | |
11730 | ||
11731 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
11732 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
11733 | mutex_lock(&dev->struct_mutex); | |
11734 | intel_unpin_fb_obj(obj); | |
11735 | mutex_unlock(&dev->struct_mutex); | |
11736 | } | |
11737 | } | |
11738 | ||
465c120c | 11739 | static int |
3c692a41 GP |
11740 | intel_check_primary_plane(struct drm_plane *plane, |
11741 | struct intel_plane_state *state) | |
11742 | { | |
2b875c22 MR |
11743 | struct drm_crtc *crtc = state->base.crtc; |
11744 | struct drm_framebuffer *fb = state->base.fb; | |
3c692a41 GP |
11745 | struct drm_rect *dest = &state->dst; |
11746 | struct drm_rect *src = &state->src; | |
11747 | const struct drm_rect *clip = &state->clip; | |
c59cb179 MR |
11748 | int ret; |
11749 | ||
11750 | ret = drm_plane_helper_check_update(plane, crtc, fb, | |
11751 | src, dest, clip, | |
11752 | DRM_PLANE_HELPER_NO_SCALING, | |
11753 | DRM_PLANE_HELPER_NO_SCALING, | |
11754 | false, true, &state->visible); | |
11755 | if (ret) | |
11756 | return ret; | |
ccc759dc | 11757 | |
c59cb179 MR |
11758 | intel_crtc_wait_for_pending_flips(crtc); |
11759 | if (intel_crtc_has_pending_flip(crtc)) { | |
11760 | DRM_ERROR("pipe is still busy with an old pageflip\n"); | |
11761 | return -EBUSY; | |
11762 | } | |
11763 | ||
11764 | return 0; | |
3c692a41 GP |
11765 | } |
11766 | ||
14af293f GP |
11767 | static void |
11768 | intel_commit_primary_plane(struct drm_plane *plane, | |
11769 | struct intel_plane_state *state) | |
11770 | { | |
2b875c22 MR |
11771 | struct drm_crtc *crtc = state->base.crtc; |
11772 | struct drm_framebuffer *fb = state->base.fb; | |
11773 | struct drm_device *dev = plane->dev; | |
14af293f GP |
11774 | struct drm_i915_private *dev_priv = dev->dev_private; |
11775 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14af293f | 11776 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
14af293f GP |
11777 | struct intel_plane *intel_plane = to_intel_plane(plane); |
11778 | struct drm_rect *src = &state->src; | |
cf4c7c12 | 11779 | enum pipe pipe = intel_plane->pipe; |
14af293f | 11780 | |
cf4c7c12 MR |
11781 | if (!fb) { |
11782 | /* | |
11783 | * 'prepare' is never called when plane is being disabled, so | |
11784 | * we need to handle frontbuffer tracking here | |
11785 | */ | |
11786 | mutex_lock(&dev->struct_mutex); | |
11787 | i915_gem_track_fb(intel_fb_obj(plane->fb), NULL, | |
11788 | INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
11789 | mutex_unlock(&dev->struct_mutex); | |
11790 | } | |
11791 | ||
11792 | plane->fb = fb; | |
9dc806fc MR |
11793 | crtc->x = src->x1 >> 16; |
11794 | crtc->y = src->y1 >> 16; | |
ccc759dc GP |
11795 | |
11796 | intel_plane->crtc_x = state->orig_dst.x1; | |
11797 | intel_plane->crtc_y = state->orig_dst.y1; | |
11798 | intel_plane->crtc_w = drm_rect_width(&state->orig_dst); | |
11799 | intel_plane->crtc_h = drm_rect_height(&state->orig_dst); | |
11800 | intel_plane->src_x = state->orig_src.x1; | |
11801 | intel_plane->src_y = state->orig_src.y1; | |
11802 | intel_plane->src_w = drm_rect_width(&state->orig_src); | |
11803 | intel_plane->src_h = drm_rect_height(&state->orig_src); | |
11804 | intel_plane->obj = obj; | |
4c34574f | 11805 | |
ccc759dc | 11806 | if (intel_crtc->active) { |
465c120c | 11807 | /* |
ccc759dc GP |
11808 | * FBC does not work on some platforms for rotated |
11809 | * planes, so disable it when rotation is not 0 and | |
11810 | * update it when rotation is set back to 0. | |
11811 | * | |
11812 | * FIXME: This is redundant with the fbc update done in | |
11813 | * the primary plane enable function except that that | |
11814 | * one is done too late. We eventually need to unify | |
11815 | * this. | |
465c120c | 11816 | */ |
ccc759dc GP |
11817 | if (intel_crtc->primary_enabled && |
11818 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
11819 | dev_priv->fbc.plane == intel_crtc->plane && | |
11820 | intel_plane->rotation != BIT(DRM_ROTATE_0)) { | |
11821 | intel_disable_fbc(dev); | |
465c120c MR |
11822 | } |
11823 | ||
ccc759dc GP |
11824 | if (state->visible) { |
11825 | bool was_enabled = intel_crtc->primary_enabled; | |
465c120c | 11826 | |
ccc759dc GP |
11827 | /* FIXME: kill this fastboot hack */ |
11828 | intel_update_pipe_size(intel_crtc); | |
465c120c | 11829 | |
ccc759dc | 11830 | intel_crtc->primary_enabled = true; |
465c120c | 11831 | |
ccc759dc GP |
11832 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
11833 | crtc->x, crtc->y); | |
4c34574f | 11834 | |
48404c1e | 11835 | /* |
ccc759dc GP |
11836 | * BDW signals flip done immediately if the plane |
11837 | * is disabled, even if the plane enable is already | |
11838 | * armed to occur at the next vblank :( | |
48404c1e | 11839 | */ |
ccc759dc GP |
11840 | if (IS_BROADWELL(dev) && !was_enabled) |
11841 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
11842 | } else { | |
11843 | /* | |
11844 | * If clipping results in a non-visible primary plane, | |
11845 | * we'll disable the primary plane. Note that this is | |
11846 | * a bit different than what happens if userspace | |
11847 | * explicitly disables the plane by passing fb=0 | |
11848 | * because plane->fb still gets set and pinned. | |
11849 | */ | |
11850 | intel_disable_primary_hw_plane(plane, crtc); | |
48404c1e | 11851 | } |
465c120c | 11852 | |
ccc759dc GP |
11853 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
11854 | ||
11855 | mutex_lock(&dev->struct_mutex); | |
11856 | intel_update_fbc(dev); | |
11857 | mutex_unlock(&dev->struct_mutex); | |
ce54d85a | 11858 | } |
465c120c MR |
11859 | } |
11860 | ||
c59cb179 MR |
11861 | int |
11862 | intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, | |
11863 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
11864 | unsigned int crtc_w, unsigned int crtc_h, | |
11865 | uint32_t src_x, uint32_t src_y, | |
11866 | uint32_t src_w, uint32_t src_h) | |
3c692a41 | 11867 | { |
38f3ce3a | 11868 | struct drm_device *dev = plane->dev; |
6beb8c23 | 11869 | struct drm_framebuffer *old_fb = plane->fb; |
3c692a41 | 11870 | struct intel_plane_state state; |
c59cb179 | 11871 | struct intel_plane *intel_plane = to_intel_plane(plane); |
3c692a41 GP |
11872 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11873 | int ret; | |
11874 | ||
e614c3c9 | 11875 | state.base.crtc = crtc ? crtc : plane->crtc; |
2b875c22 | 11876 | state.base.fb = fb; |
3c692a41 GP |
11877 | |
11878 | /* sample coordinates in 16.16 fixed point */ | |
11879 | state.src.x1 = src_x; | |
11880 | state.src.x2 = src_x + src_w; | |
11881 | state.src.y1 = src_y; | |
11882 | state.src.y2 = src_y + src_h; | |
11883 | ||
11884 | /* integer pixels */ | |
11885 | state.dst.x1 = crtc_x; | |
11886 | state.dst.x2 = crtc_x + crtc_w; | |
11887 | state.dst.y1 = crtc_y; | |
11888 | state.dst.y2 = crtc_y + crtc_h; | |
11889 | ||
11890 | state.clip.x1 = 0; | |
11891 | state.clip.y1 = 0; | |
11892 | state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0; | |
11893 | state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0; | |
11894 | ||
11895 | state.orig_src = state.src; | |
11896 | state.orig_dst = state.dst; | |
11897 | ||
c59cb179 | 11898 | ret = intel_plane->check_plane(plane, &state); |
3c692a41 GP |
11899 | if (ret) |
11900 | return ret; | |
11901 | ||
6beb8c23 MR |
11902 | if (fb != old_fb && fb) { |
11903 | ret = intel_prepare_plane_fb(plane, fb); | |
11904 | if (ret) | |
11905 | return ret; | |
11906 | } | |
3c692a41 | 11907 | |
c59cb179 | 11908 | intel_plane->commit_plane(plane, &state); |
3c692a41 | 11909 | |
38f3ce3a MR |
11910 | if (fb != old_fb && old_fb) { |
11911 | if (intel_crtc->active) | |
11912 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
11913 | intel_cleanup_plane_fb(plane, old_fb); | |
11914 | } | |
11915 | ||
c59cb179 MR |
11916 | plane->fb = fb; |
11917 | ||
3c692a41 GP |
11918 | return 0; |
11919 | } | |
11920 | ||
cf4c7c12 MR |
11921 | /** |
11922 | * intel_disable_plane - disable a plane | |
11923 | * @plane: plane to disable | |
11924 | * | |
11925 | * General disable handler for all plane types. | |
11926 | */ | |
11927 | int | |
11928 | intel_disable_plane(struct drm_plane *plane) | |
11929 | { | |
11930 | if (!plane->fb) | |
11931 | return 0; | |
11932 | ||
11933 | if (WARN_ON(!plane->crtc)) | |
11934 | return -EINVAL; | |
11935 | ||
11936 | return plane->funcs->update_plane(plane, plane->crtc, NULL, | |
11937 | 0, 0, 0, 0, 0, 0, 0, 0); | |
11938 | } | |
11939 | ||
3d7d6510 MR |
11940 | /* Common destruction function for both primary and cursor planes */ |
11941 | static void intel_plane_destroy(struct drm_plane *plane) | |
465c120c MR |
11942 | { |
11943 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
11944 | drm_plane_cleanup(plane); | |
11945 | kfree(intel_plane); | |
11946 | } | |
11947 | ||
11948 | static const struct drm_plane_funcs intel_primary_plane_funcs = { | |
c59cb179 | 11949 | .update_plane = intel_update_plane, |
cf4c7c12 | 11950 | .disable_plane = intel_disable_plane, |
3d7d6510 | 11951 | .destroy = intel_plane_destroy, |
48404c1e | 11952 | .set_property = intel_plane_set_property |
465c120c MR |
11953 | }; |
11954 | ||
11955 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
11956 | int pipe) | |
11957 | { | |
11958 | struct intel_plane *primary; | |
11959 | const uint32_t *intel_primary_formats; | |
11960 | int num_formats; | |
11961 | ||
11962 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
11963 | if (primary == NULL) | |
11964 | return NULL; | |
11965 | ||
11966 | primary->can_scale = false; | |
11967 | primary->max_downscale = 1; | |
11968 | primary->pipe = pipe; | |
11969 | primary->plane = pipe; | |
48404c1e | 11970 | primary->rotation = BIT(DRM_ROTATE_0); |
c59cb179 MR |
11971 | primary->check_plane = intel_check_primary_plane; |
11972 | primary->commit_plane = intel_commit_primary_plane; | |
465c120c MR |
11973 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
11974 | primary->plane = !pipe; | |
11975 | ||
11976 | if (INTEL_INFO(dev)->gen <= 3) { | |
11977 | intel_primary_formats = intel_primary_formats_gen2; | |
11978 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
11979 | } else { | |
11980 | intel_primary_formats = intel_primary_formats_gen4; | |
11981 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
11982 | } | |
11983 | ||
11984 | drm_universal_plane_init(dev, &primary->base, 0, | |
11985 | &intel_primary_plane_funcs, | |
11986 | intel_primary_formats, num_formats, | |
11987 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e SJ |
11988 | |
11989 | if (INTEL_INFO(dev)->gen >= 4) { | |
11990 | if (!dev->mode_config.rotation_property) | |
11991 | dev->mode_config.rotation_property = | |
11992 | drm_mode_create_rotation_property(dev, | |
11993 | BIT(DRM_ROTATE_0) | | |
11994 | BIT(DRM_ROTATE_180)); | |
11995 | if (dev->mode_config.rotation_property) | |
11996 | drm_object_attach_property(&primary->base.base, | |
11997 | dev->mode_config.rotation_property, | |
11998 | primary->rotation); | |
11999 | } | |
12000 | ||
465c120c MR |
12001 | return &primary->base; |
12002 | } | |
12003 | ||
3d7d6510 | 12004 | static int |
852e787c GP |
12005 | intel_check_cursor_plane(struct drm_plane *plane, |
12006 | struct intel_plane_state *state) | |
3d7d6510 | 12007 | { |
2b875c22 | 12008 | struct drm_crtc *crtc = state->base.crtc; |
757f9a3e | 12009 | struct drm_device *dev = crtc->dev; |
2b875c22 | 12010 | struct drm_framebuffer *fb = state->base.fb; |
852e787c GP |
12011 | struct drm_rect *dest = &state->dst; |
12012 | struct drm_rect *src = &state->src; | |
12013 | const struct drm_rect *clip = &state->clip; | |
757f9a3e GP |
12014 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
12015 | int crtc_w, crtc_h; | |
12016 | unsigned stride; | |
12017 | int ret; | |
3d7d6510 | 12018 | |
757f9a3e | 12019 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
852e787c | 12020 | src, dest, clip, |
3d7d6510 MR |
12021 | DRM_PLANE_HELPER_NO_SCALING, |
12022 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 12023 | true, true, &state->visible); |
757f9a3e GP |
12024 | if (ret) |
12025 | return ret; | |
12026 | ||
12027 | ||
12028 | /* if we want to turn off the cursor ignore width and height */ | |
12029 | if (!obj) | |
12030 | return 0; | |
12031 | ||
757f9a3e GP |
12032 | /* Check for which cursor types we support */ |
12033 | crtc_w = drm_rect_width(&state->orig_dst); | |
12034 | crtc_h = drm_rect_height(&state->orig_dst); | |
12035 | if (!cursor_size_ok(dev, crtc_w, crtc_h)) { | |
12036 | DRM_DEBUG("Cursor dimension not supported\n"); | |
12037 | return -EINVAL; | |
12038 | } | |
12039 | ||
12040 | stride = roundup_pow_of_two(crtc_w) * 4; | |
12041 | if (obj->base.size < stride * crtc_h) { | |
12042 | DRM_DEBUG_KMS("buffer is too small\n"); | |
12043 | return -ENOMEM; | |
12044 | } | |
12045 | ||
e391ea88 GP |
12046 | if (fb == crtc->cursor->fb) |
12047 | return 0; | |
12048 | ||
757f9a3e GP |
12049 | /* we only need to pin inside GTT if cursor is non-phy */ |
12050 | mutex_lock(&dev->struct_mutex); | |
12051 | if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) { | |
12052 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); | |
12053 | ret = -EINVAL; | |
12054 | } | |
12055 | mutex_unlock(&dev->struct_mutex); | |
12056 | ||
12057 | return ret; | |
852e787c | 12058 | } |
3d7d6510 | 12059 | |
f4a2cf29 | 12060 | static void |
852e787c GP |
12061 | intel_commit_cursor_plane(struct drm_plane *plane, |
12062 | struct intel_plane_state *state) | |
12063 | { | |
2b875c22 | 12064 | struct drm_crtc *crtc = state->base.crtc; |
a912f12f | 12065 | struct drm_device *dev = crtc->dev; |
852e787c | 12066 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
a919db90 | 12067 | struct intel_plane *intel_plane = to_intel_plane(plane); |
2b875c22 | 12068 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
6beb8c23 | 12069 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); |
a912f12f GP |
12070 | enum pipe pipe = intel_crtc->pipe; |
12071 | unsigned old_width; | |
12072 | uint32_t addr; | |
852e787c | 12073 | |
2b875c22 | 12074 | plane->fb = state->base.fb; |
852e787c GP |
12075 | crtc->cursor_x = state->orig_dst.x1; |
12076 | crtc->cursor_y = state->orig_dst.y1; | |
a919db90 SJ |
12077 | |
12078 | intel_plane->crtc_x = state->orig_dst.x1; | |
12079 | intel_plane->crtc_y = state->orig_dst.y1; | |
12080 | intel_plane->crtc_w = drm_rect_width(&state->orig_dst); | |
12081 | intel_plane->crtc_h = drm_rect_height(&state->orig_dst); | |
12082 | intel_plane->src_x = state->orig_src.x1; | |
12083 | intel_plane->src_y = state->orig_src.y1; | |
12084 | intel_plane->src_w = drm_rect_width(&state->orig_src); | |
12085 | intel_plane->src_h = drm_rect_height(&state->orig_src); | |
12086 | intel_plane->obj = obj; | |
12087 | ||
a912f12f GP |
12088 | if (intel_crtc->cursor_bo == obj) |
12089 | goto update; | |
12090 | ||
6beb8c23 MR |
12091 | /* |
12092 | * 'prepare' is only called when fb != NULL; we still need to update | |
12093 | * frontbuffer tracking for the 'disable' case here. | |
12094 | */ | |
12095 | if (!obj) { | |
12096 | mutex_lock(&dev->struct_mutex); | |
12097 | i915_gem_track_fb(old_obj, NULL, | |
12098 | INTEL_FRONTBUFFER_CURSOR(pipe)); | |
12099 | mutex_unlock(&dev->struct_mutex); | |
12100 | } | |
12101 | ||
f4a2cf29 | 12102 | if (!obj) |
a912f12f | 12103 | addr = 0; |
f4a2cf29 | 12104 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 12105 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 12106 | else |
a912f12f | 12107 | addr = obj->phys_handle->busaddr; |
4ed91096 | 12108 | |
a912f12f GP |
12109 | intel_crtc->cursor_addr = addr; |
12110 | intel_crtc->cursor_bo = obj; | |
12111 | update: | |
12112 | old_width = intel_crtc->cursor_width; | |
12113 | ||
12114 | intel_crtc->cursor_width = drm_rect_width(&state->orig_dst); | |
12115 | intel_crtc->cursor_height = drm_rect_height(&state->orig_dst); | |
12116 | ||
12117 | if (intel_crtc->active) { | |
12118 | if (old_width != intel_crtc->cursor_width) | |
12119 | intel_update_watermarks(crtc); | |
12120 | intel_crtc_update_cursor(crtc, state->visible); | |
12121 | ||
12122 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe)); | |
3d7d6510 MR |
12123 | } |
12124 | } | |
852e787c | 12125 | |
3d7d6510 | 12126 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { |
c59cb179 | 12127 | .update_plane = intel_update_plane, |
cf4c7c12 | 12128 | .disable_plane = intel_disable_plane, |
3d7d6510 | 12129 | .destroy = intel_plane_destroy, |
4398ad45 | 12130 | .set_property = intel_plane_set_property, |
3d7d6510 MR |
12131 | }; |
12132 | ||
12133 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, | |
12134 | int pipe) | |
12135 | { | |
12136 | struct intel_plane *cursor; | |
12137 | ||
12138 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
12139 | if (cursor == NULL) | |
12140 | return NULL; | |
12141 | ||
12142 | cursor->can_scale = false; | |
12143 | cursor->max_downscale = 1; | |
12144 | cursor->pipe = pipe; | |
12145 | cursor->plane = pipe; | |
4398ad45 | 12146 | cursor->rotation = BIT(DRM_ROTATE_0); |
c59cb179 MR |
12147 | cursor->check_plane = intel_check_cursor_plane; |
12148 | cursor->commit_plane = intel_commit_cursor_plane; | |
3d7d6510 MR |
12149 | |
12150 | drm_universal_plane_init(dev, &cursor->base, 0, | |
12151 | &intel_cursor_plane_funcs, | |
12152 | intel_cursor_formats, | |
12153 | ARRAY_SIZE(intel_cursor_formats), | |
12154 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
12155 | |
12156 | if (INTEL_INFO(dev)->gen >= 4) { | |
12157 | if (!dev->mode_config.rotation_property) | |
12158 | dev->mode_config.rotation_property = | |
12159 | drm_mode_create_rotation_property(dev, | |
12160 | BIT(DRM_ROTATE_0) | | |
12161 | BIT(DRM_ROTATE_180)); | |
12162 | if (dev->mode_config.rotation_property) | |
12163 | drm_object_attach_property(&cursor->base.base, | |
12164 | dev->mode_config.rotation_property, | |
12165 | cursor->rotation); | |
12166 | } | |
12167 | ||
3d7d6510 MR |
12168 | return &cursor->base; |
12169 | } | |
12170 | ||
b358d0a6 | 12171 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 12172 | { |
fbee40df | 12173 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 12174 | struct intel_crtc *intel_crtc; |
3d7d6510 MR |
12175 | struct drm_plane *primary = NULL; |
12176 | struct drm_plane *cursor = NULL; | |
465c120c | 12177 | int i, ret; |
79e53945 | 12178 | |
955382f3 | 12179 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
12180 | if (intel_crtc == NULL) |
12181 | return; | |
12182 | ||
465c120c | 12183 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
12184 | if (!primary) |
12185 | goto fail; | |
12186 | ||
12187 | cursor = intel_cursor_plane_create(dev, pipe); | |
12188 | if (!cursor) | |
12189 | goto fail; | |
12190 | ||
465c120c | 12191 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
12192 | cursor, &intel_crtc_funcs); |
12193 | if (ret) | |
12194 | goto fail; | |
79e53945 JB |
12195 | |
12196 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
12197 | for (i = 0; i < 256; i++) { |
12198 | intel_crtc->lut_r[i] = i; | |
12199 | intel_crtc->lut_g[i] = i; | |
12200 | intel_crtc->lut_b[i] = i; | |
12201 | } | |
12202 | ||
1f1c2e24 VS |
12203 | /* |
12204 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 12205 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 12206 | */ |
80824003 JB |
12207 | intel_crtc->pipe = pipe; |
12208 | intel_crtc->plane = pipe; | |
3a77c4c4 | 12209 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 12210 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 12211 | intel_crtc->plane = !pipe; |
80824003 JB |
12212 | } |
12213 | ||
4b0e333e CW |
12214 | intel_crtc->cursor_base = ~0; |
12215 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 12216 | intel_crtc->cursor_size = ~0; |
8d7849db | 12217 | |
22fd0fab JB |
12218 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
12219 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
12220 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
12221 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
12222 | ||
9362c7c5 ACO |
12223 | INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func); |
12224 | ||
79e53945 | 12225 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
12226 | |
12227 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
12228 | return; |
12229 | ||
12230 | fail: | |
12231 | if (primary) | |
12232 | drm_plane_cleanup(primary); | |
12233 | if (cursor) | |
12234 | drm_plane_cleanup(cursor); | |
12235 | kfree(intel_crtc); | |
79e53945 JB |
12236 | } |
12237 | ||
752aa88a JB |
12238 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
12239 | { | |
12240 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 12241 | struct drm_device *dev = connector->base.dev; |
752aa88a | 12242 | |
51fd371b | 12243 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 12244 | |
d3babd3f | 12245 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
12246 | return INVALID_PIPE; |
12247 | ||
12248 | return to_intel_crtc(encoder->crtc)->pipe; | |
12249 | } | |
12250 | ||
08d7b3d1 | 12251 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 12252 | struct drm_file *file) |
08d7b3d1 | 12253 | { |
08d7b3d1 | 12254 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 12255 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 12256 | struct intel_crtc *crtc; |
08d7b3d1 | 12257 | |
1cff8f6b DV |
12258 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
12259 | return -ENODEV; | |
08d7b3d1 | 12260 | |
7707e653 | 12261 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 12262 | |
7707e653 | 12263 | if (!drmmode_crtc) { |
08d7b3d1 | 12264 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 12265 | return -ENOENT; |
08d7b3d1 CW |
12266 | } |
12267 | ||
7707e653 | 12268 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 12269 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 12270 | |
c05422d5 | 12271 | return 0; |
08d7b3d1 CW |
12272 | } |
12273 | ||
66a9278e | 12274 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 12275 | { |
66a9278e DV |
12276 | struct drm_device *dev = encoder->base.dev; |
12277 | struct intel_encoder *source_encoder; | |
79e53945 | 12278 | int index_mask = 0; |
79e53945 JB |
12279 | int entry = 0; |
12280 | ||
b2784e15 | 12281 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 12282 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
12283 | index_mask |= (1 << entry); |
12284 | ||
79e53945 JB |
12285 | entry++; |
12286 | } | |
4ef69c7a | 12287 | |
79e53945 JB |
12288 | return index_mask; |
12289 | } | |
12290 | ||
4d302442 CW |
12291 | static bool has_edp_a(struct drm_device *dev) |
12292 | { | |
12293 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12294 | ||
12295 | if (!IS_MOBILE(dev)) | |
12296 | return false; | |
12297 | ||
12298 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
12299 | return false; | |
12300 | ||
e3589908 | 12301 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
12302 | return false; |
12303 | ||
12304 | return true; | |
12305 | } | |
12306 | ||
ba0fbca4 DL |
12307 | const char *intel_output_name(int output) |
12308 | { | |
12309 | static const char *names[] = { | |
12310 | [INTEL_OUTPUT_UNUSED] = "Unused", | |
12311 | [INTEL_OUTPUT_ANALOG] = "Analog", | |
12312 | [INTEL_OUTPUT_DVO] = "DVO", | |
12313 | [INTEL_OUTPUT_SDVO] = "SDVO", | |
12314 | [INTEL_OUTPUT_LVDS] = "LVDS", | |
12315 | [INTEL_OUTPUT_TVOUT] = "TV", | |
12316 | [INTEL_OUTPUT_HDMI] = "HDMI", | |
12317 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", | |
12318 | [INTEL_OUTPUT_EDP] = "eDP", | |
12319 | [INTEL_OUTPUT_DSI] = "DSI", | |
12320 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", | |
12321 | }; | |
12322 | ||
12323 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) | |
12324 | return "Invalid"; | |
12325 | ||
12326 | return names[output]; | |
12327 | } | |
12328 | ||
84b4e042 JB |
12329 | static bool intel_crt_present(struct drm_device *dev) |
12330 | { | |
12331 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12332 | ||
884497ed DL |
12333 | if (INTEL_INFO(dev)->gen >= 9) |
12334 | return false; | |
12335 | ||
cf404ce4 | 12336 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
12337 | return false; |
12338 | ||
12339 | if (IS_CHERRYVIEW(dev)) | |
12340 | return false; | |
12341 | ||
12342 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
12343 | return false; | |
12344 | ||
12345 | return true; | |
12346 | } | |
12347 | ||
79e53945 JB |
12348 | static void intel_setup_outputs(struct drm_device *dev) |
12349 | { | |
725e30ad | 12350 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 12351 | struct intel_encoder *encoder; |
cb0953d7 | 12352 | bool dpd_is_edp = false; |
79e53945 | 12353 | |
c9093354 | 12354 | intel_lvds_init(dev); |
79e53945 | 12355 | |
84b4e042 | 12356 | if (intel_crt_present(dev)) |
79935fca | 12357 | intel_crt_init(dev); |
cb0953d7 | 12358 | |
affa9354 | 12359 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
12360 | int found; |
12361 | ||
12362 | /* Haswell uses DDI functions to detect digital outputs */ | |
12363 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
12364 | /* DDI A only supports eDP */ | |
12365 | if (found) | |
12366 | intel_ddi_init(dev, PORT_A); | |
12367 | ||
12368 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
12369 | * register */ | |
12370 | found = I915_READ(SFUSE_STRAP); | |
12371 | ||
12372 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
12373 | intel_ddi_init(dev, PORT_B); | |
12374 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
12375 | intel_ddi_init(dev, PORT_C); | |
12376 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
12377 | intel_ddi_init(dev, PORT_D); | |
12378 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 12379 | int found; |
5d8a7752 | 12380 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
12381 | |
12382 | if (has_edp_a(dev)) | |
12383 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 12384 | |
dc0fa718 | 12385 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 12386 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 12387 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 12388 | if (!found) |
e2debe91 | 12389 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 12390 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 12391 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
12392 | } |
12393 | ||
dc0fa718 | 12394 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 12395 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 12396 | |
dc0fa718 | 12397 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 12398 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 12399 | |
5eb08b69 | 12400 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 12401 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 12402 | |
270b3042 | 12403 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 12404 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 12405 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
12406 | /* |
12407 | * The DP_DETECTED bit is the latched state of the DDC | |
12408 | * SDA pin at boot. However since eDP doesn't require DDC | |
12409 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
12410 | * eDP ports may have been muxed to an alternate function. | |
12411 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
12412 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
12413 | * detect eDP ports. | |
12414 | */ | |
12415 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) | |
585a94b8 AB |
12416 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
12417 | PORT_B); | |
e17ac6db VS |
12418 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
12419 | intel_dp_is_edp(dev, PORT_B)) | |
12420 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 12421 | |
e17ac6db | 12422 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) |
6f6005a5 JB |
12423 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
12424 | PORT_C); | |
e17ac6db VS |
12425 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
12426 | intel_dp_is_edp(dev, PORT_C)) | |
12427 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 12428 | |
9418c1f1 | 12429 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 12430 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
12431 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
12432 | PORT_D); | |
e17ac6db VS |
12433 | /* eDP not supported on port D, so don't check VBT */ |
12434 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
12435 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
12436 | } |
12437 | ||
3cfca973 | 12438 | intel_dsi_init(dev); |
103a196f | 12439 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 12440 | bool found = false; |
7d57382e | 12441 | |
e2debe91 | 12442 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 12443 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 12444 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
12445 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
12446 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 12447 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 12448 | } |
27185ae1 | 12449 | |
e7281eab | 12450 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 12451 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 12452 | } |
13520b05 KH |
12453 | |
12454 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 12455 | |
e2debe91 | 12456 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 12457 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 12458 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 12459 | } |
27185ae1 | 12460 | |
e2debe91 | 12461 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 12462 | |
b01f2c3a JB |
12463 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
12464 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 12465 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 12466 | } |
e7281eab | 12467 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 12468 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 12469 | } |
27185ae1 | 12470 | |
b01f2c3a | 12471 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 12472 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 12473 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 12474 | } else if (IS_GEN2(dev)) |
79e53945 JB |
12475 | intel_dvo_init(dev); |
12476 | ||
103a196f | 12477 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
12478 | intel_tv_init(dev); |
12479 | ||
0bc12bcb | 12480 | intel_psr_init(dev); |
7c8f8a70 | 12481 | |
b2784e15 | 12482 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
12483 | encoder->base.possible_crtcs = encoder->crtc_mask; |
12484 | encoder->base.possible_clones = | |
66a9278e | 12485 | intel_encoder_clones(encoder); |
79e53945 | 12486 | } |
47356eb6 | 12487 | |
dde86e2d | 12488 | intel_init_pch_refclk(dev); |
270b3042 DV |
12489 | |
12490 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
12491 | } |
12492 | ||
12493 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
12494 | { | |
60a5ca01 | 12495 | struct drm_device *dev = fb->dev; |
79e53945 | 12496 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 12497 | |
ef2d633e | 12498 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 12499 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 12500 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
12501 | drm_gem_object_unreference(&intel_fb->obj->base); |
12502 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12503 | kfree(intel_fb); |
12504 | } | |
12505 | ||
12506 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 12507 | struct drm_file *file, |
79e53945 JB |
12508 | unsigned int *handle) |
12509 | { | |
12510 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 12511 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 12512 | |
05394f39 | 12513 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
12514 | } |
12515 | ||
12516 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
12517 | .destroy = intel_user_framebuffer_destroy, | |
12518 | .create_handle = intel_user_framebuffer_create_handle, | |
12519 | }; | |
12520 | ||
b5ea642a DV |
12521 | static int intel_framebuffer_init(struct drm_device *dev, |
12522 | struct intel_framebuffer *intel_fb, | |
12523 | struct drm_mode_fb_cmd2 *mode_cmd, | |
12524 | struct drm_i915_gem_object *obj) | |
79e53945 | 12525 | { |
a57ce0b2 | 12526 | int aligned_height; |
a35cdaa0 | 12527 | int pitch_limit; |
79e53945 JB |
12528 | int ret; |
12529 | ||
dd4916c5 DV |
12530 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
12531 | ||
c16ed4be CW |
12532 | if (obj->tiling_mode == I915_TILING_Y) { |
12533 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 12534 | return -EINVAL; |
c16ed4be | 12535 | } |
57cd6508 | 12536 | |
c16ed4be CW |
12537 | if (mode_cmd->pitches[0] & 63) { |
12538 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
12539 | mode_cmd->pitches[0]); | |
57cd6508 | 12540 | return -EINVAL; |
c16ed4be | 12541 | } |
57cd6508 | 12542 | |
a35cdaa0 CW |
12543 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
12544 | pitch_limit = 32*1024; | |
12545 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
12546 | if (obj->tiling_mode) | |
12547 | pitch_limit = 16*1024; | |
12548 | else | |
12549 | pitch_limit = 32*1024; | |
12550 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
12551 | if (obj->tiling_mode) | |
12552 | pitch_limit = 8*1024; | |
12553 | else | |
12554 | pitch_limit = 16*1024; | |
12555 | } else | |
12556 | /* XXX DSPC is limited to 4k tiled */ | |
12557 | pitch_limit = 8*1024; | |
12558 | ||
12559 | if (mode_cmd->pitches[0] > pitch_limit) { | |
12560 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
12561 | obj->tiling_mode ? "tiled" : "linear", | |
12562 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 12563 | return -EINVAL; |
c16ed4be | 12564 | } |
5d7bd705 VS |
12565 | |
12566 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
12567 | mode_cmd->pitches[0] != obj->stride) { |
12568 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
12569 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 12570 | return -EINVAL; |
c16ed4be | 12571 | } |
5d7bd705 | 12572 | |
57779d06 | 12573 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 12574 | switch (mode_cmd->pixel_format) { |
57779d06 | 12575 | case DRM_FORMAT_C8: |
04b3924d VS |
12576 | case DRM_FORMAT_RGB565: |
12577 | case DRM_FORMAT_XRGB8888: | |
12578 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
12579 | break; |
12580 | case DRM_FORMAT_XRGB1555: | |
12581 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 12582 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
12583 | DRM_DEBUG("unsupported pixel format: %s\n", |
12584 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12585 | return -EINVAL; |
c16ed4be | 12586 | } |
57779d06 VS |
12587 | break; |
12588 | case DRM_FORMAT_XBGR8888: | |
12589 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
12590 | case DRM_FORMAT_XRGB2101010: |
12591 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
12592 | case DRM_FORMAT_XBGR2101010: |
12593 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 12594 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
12595 | DRM_DEBUG("unsupported pixel format: %s\n", |
12596 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12597 | return -EINVAL; |
c16ed4be | 12598 | } |
b5626747 | 12599 | break; |
04b3924d VS |
12600 | case DRM_FORMAT_YUYV: |
12601 | case DRM_FORMAT_UYVY: | |
12602 | case DRM_FORMAT_YVYU: | |
12603 | case DRM_FORMAT_VYUY: | |
c16ed4be | 12604 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
12605 | DRM_DEBUG("unsupported pixel format: %s\n", |
12606 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12607 | return -EINVAL; |
c16ed4be | 12608 | } |
57cd6508 CW |
12609 | break; |
12610 | default: | |
4ee62c76 VS |
12611 | DRM_DEBUG("unsupported pixel format: %s\n", |
12612 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
12613 | return -EINVAL; |
12614 | } | |
12615 | ||
90f9a336 VS |
12616 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
12617 | if (mode_cmd->offsets[0] != 0) | |
12618 | return -EINVAL; | |
12619 | ||
a57ce0b2 JB |
12620 | aligned_height = intel_align_height(dev, mode_cmd->height, |
12621 | obj->tiling_mode); | |
53155c0a DV |
12622 | /* FIXME drm helper for size checks (especially planar formats)? */ |
12623 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
12624 | return -EINVAL; | |
12625 | ||
c7d73f6a DV |
12626 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
12627 | intel_fb->obj = obj; | |
80075d49 | 12628 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 12629 | |
79e53945 JB |
12630 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
12631 | if (ret) { | |
12632 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
12633 | return ret; | |
12634 | } | |
12635 | ||
79e53945 JB |
12636 | return 0; |
12637 | } | |
12638 | ||
79e53945 JB |
12639 | static struct drm_framebuffer * |
12640 | intel_user_framebuffer_create(struct drm_device *dev, | |
12641 | struct drm_file *filp, | |
308e5bcb | 12642 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 12643 | { |
05394f39 | 12644 | struct drm_i915_gem_object *obj; |
79e53945 | 12645 | |
308e5bcb JB |
12646 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
12647 | mode_cmd->handles[0])); | |
c8725226 | 12648 | if (&obj->base == NULL) |
cce13ff7 | 12649 | return ERR_PTR(-ENOENT); |
79e53945 | 12650 | |
d2dff872 | 12651 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
12652 | } |
12653 | ||
4520f53a | 12654 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 12655 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
12656 | { |
12657 | } | |
12658 | #endif | |
12659 | ||
79e53945 | 12660 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 12661 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 12662 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
12663 | }; |
12664 | ||
e70236a8 JB |
12665 | /* Set up chip specific display functions */ |
12666 | static void intel_init_display(struct drm_device *dev) | |
12667 | { | |
12668 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12669 | ||
ee9300bb DV |
12670 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
12671 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
12672 | else if (IS_CHERRYVIEW(dev)) |
12673 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
12674 | else if (IS_VALLEYVIEW(dev)) |
12675 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
12676 | else if (IS_PINEVIEW(dev)) | |
12677 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
12678 | else | |
12679 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
12680 | ||
affa9354 | 12681 | if (HAS_DDI(dev)) { |
0e8ffe1b | 12682 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
4c6baa59 | 12683 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
797d0259 ACO |
12684 | dev_priv->display.crtc_compute_clock = |
12685 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
12686 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
12687 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 12688 | dev_priv->display.off = ironlake_crtc_off; |
70d21f0e DL |
12689 | if (INTEL_INFO(dev)->gen >= 9) |
12690 | dev_priv->display.update_primary_plane = | |
12691 | skylake_update_primary_plane; | |
12692 | else | |
12693 | dev_priv->display.update_primary_plane = | |
12694 | ironlake_update_primary_plane; | |
09b4ddf9 | 12695 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 12696 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
4c6baa59 | 12697 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
3fb37703 ACO |
12698 | dev_priv->display.crtc_compute_clock = |
12699 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
12700 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
12701 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 12702 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
12703 | dev_priv->display.update_primary_plane = |
12704 | ironlake_update_primary_plane; | |
89b667f8 JB |
12705 | } else if (IS_VALLEYVIEW(dev)) { |
12706 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
1ad292b5 | 12707 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
d6dfee7a | 12708 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
12709 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
12710 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
12711 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
12712 | dev_priv->display.update_primary_plane = |
12713 | i9xx_update_primary_plane; | |
f564048e | 12714 | } else { |
0e8ffe1b | 12715 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
1ad292b5 | 12716 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
d6dfee7a | 12717 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
12718 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
12719 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 12720 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
12721 | dev_priv->display.update_primary_plane = |
12722 | i9xx_update_primary_plane; | |
f564048e | 12723 | } |
e70236a8 | 12724 | |
e70236a8 | 12725 | /* Returns the core display clock speed */ |
25eb05fc JB |
12726 | if (IS_VALLEYVIEW(dev)) |
12727 | dev_priv->display.get_display_clock_speed = | |
12728 | valleyview_get_display_clock_speed; | |
12729 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
12730 | dev_priv->display.get_display_clock_speed = |
12731 | i945_get_display_clock_speed; | |
12732 | else if (IS_I915G(dev)) | |
12733 | dev_priv->display.get_display_clock_speed = | |
12734 | i915_get_display_clock_speed; | |
257a7ffc | 12735 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
12736 | dev_priv->display.get_display_clock_speed = |
12737 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
12738 | else if (IS_PINEVIEW(dev)) |
12739 | dev_priv->display.get_display_clock_speed = | |
12740 | pnv_get_display_clock_speed; | |
e70236a8 JB |
12741 | else if (IS_I915GM(dev)) |
12742 | dev_priv->display.get_display_clock_speed = | |
12743 | i915gm_get_display_clock_speed; | |
12744 | else if (IS_I865G(dev)) | |
12745 | dev_priv->display.get_display_clock_speed = | |
12746 | i865_get_display_clock_speed; | |
f0f8a9ce | 12747 | else if (IS_I85X(dev)) |
e70236a8 JB |
12748 | dev_priv->display.get_display_clock_speed = |
12749 | i855_get_display_clock_speed; | |
12750 | else /* 852, 830 */ | |
12751 | dev_priv->display.get_display_clock_speed = | |
12752 | i830_get_display_clock_speed; | |
12753 | ||
7c10a2b5 | 12754 | if (IS_GEN5(dev)) { |
3bb11b53 | 12755 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
12756 | } else if (IS_GEN6(dev)) { |
12757 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
12758 | } else if (IS_IVYBRIDGE(dev)) { |
12759 | /* FIXME: detect B0+ stepping and use auto training */ | |
12760 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
3bb11b53 SJ |
12761 | dev_priv->display.modeset_global_resources = |
12762 | ivb_modeset_global_resources; | |
059b2fe9 | 12763 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 12764 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
30a970c6 JB |
12765 | } else if (IS_VALLEYVIEW(dev)) { |
12766 | dev_priv->display.modeset_global_resources = | |
12767 | valleyview_modeset_global_resources; | |
e70236a8 | 12768 | } |
8c9f3aaf JB |
12769 | |
12770 | /* Default just returns -ENODEV to indicate unsupported */ | |
12771 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
12772 | ||
12773 | switch (INTEL_INFO(dev)->gen) { | |
12774 | case 2: | |
12775 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
12776 | break; | |
12777 | ||
12778 | case 3: | |
12779 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
12780 | break; | |
12781 | ||
12782 | case 4: | |
12783 | case 5: | |
12784 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
12785 | break; | |
12786 | ||
12787 | case 6: | |
12788 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
12789 | break; | |
7c9017e5 | 12790 | case 7: |
4e0bbc31 | 12791 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
12792 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
12793 | break; | |
830c81db DL |
12794 | case 9: |
12795 | dev_priv->display.queue_flip = intel_gen9_queue_flip; | |
12796 | break; | |
8c9f3aaf | 12797 | } |
7bd688cd JN |
12798 | |
12799 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
12800 | |
12801 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
12802 | } |
12803 | ||
b690e96c JB |
12804 | /* |
12805 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
12806 | * resume, or other times. This quirk makes sure that's the case for | |
12807 | * affected systems. | |
12808 | */ | |
0206e353 | 12809 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
12810 | { |
12811 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12812 | ||
12813 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 12814 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
12815 | } |
12816 | ||
b6b5d049 VS |
12817 | static void quirk_pipeb_force(struct drm_device *dev) |
12818 | { | |
12819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12820 | ||
12821 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
12822 | DRM_INFO("applying pipe b force quirk\n"); | |
12823 | } | |
12824 | ||
435793df KP |
12825 | /* |
12826 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
12827 | */ | |
12828 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
12829 | { | |
12830 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12831 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 12832 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
12833 | } |
12834 | ||
4dca20ef | 12835 | /* |
5a15ab5b CE |
12836 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
12837 | * brightness value | |
4dca20ef CE |
12838 | */ |
12839 | static void quirk_invert_brightness(struct drm_device *dev) | |
12840 | { | |
12841 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12842 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 12843 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
12844 | } |
12845 | ||
9c72cc6f SD |
12846 | /* Some VBT's incorrectly indicate no backlight is present */ |
12847 | static void quirk_backlight_present(struct drm_device *dev) | |
12848 | { | |
12849 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12850 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
12851 | DRM_INFO("applying backlight present quirk\n"); | |
12852 | } | |
12853 | ||
b690e96c JB |
12854 | struct intel_quirk { |
12855 | int device; | |
12856 | int subsystem_vendor; | |
12857 | int subsystem_device; | |
12858 | void (*hook)(struct drm_device *dev); | |
12859 | }; | |
12860 | ||
5f85f176 EE |
12861 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
12862 | struct intel_dmi_quirk { | |
12863 | void (*hook)(struct drm_device *dev); | |
12864 | const struct dmi_system_id (*dmi_id_list)[]; | |
12865 | }; | |
12866 | ||
12867 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
12868 | { | |
12869 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
12870 | return 1; | |
12871 | } | |
12872 | ||
12873 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
12874 | { | |
12875 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
12876 | { | |
12877 | .callback = intel_dmi_reverse_brightness, | |
12878 | .ident = "NCR Corporation", | |
12879 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
12880 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
12881 | }, | |
12882 | }, | |
12883 | { } /* terminating entry */ | |
12884 | }, | |
12885 | .hook = quirk_invert_brightness, | |
12886 | }, | |
12887 | }; | |
12888 | ||
c43b5634 | 12889 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 12890 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 12891 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 12892 | |
b690e96c JB |
12893 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
12894 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
12895 | ||
b690e96c JB |
12896 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
12897 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
12898 | ||
5f080c0f VS |
12899 | /* 830 needs to leave pipe A & dpll A up */ |
12900 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
12901 | ||
b6b5d049 VS |
12902 | /* 830 needs to leave pipe B & dpll B up */ |
12903 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
12904 | ||
435793df KP |
12905 | /* Lenovo U160 cannot use SSC on LVDS */ |
12906 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
12907 | |
12908 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
12909 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 12910 | |
be505f64 AH |
12911 | /* Acer Aspire 5734Z must invert backlight brightness */ |
12912 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
12913 | ||
12914 | /* Acer/eMachines G725 */ | |
12915 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
12916 | ||
12917 | /* Acer/eMachines e725 */ | |
12918 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
12919 | ||
12920 | /* Acer/Packard Bell NCL20 */ | |
12921 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
12922 | ||
12923 | /* Acer Aspire 4736Z */ | |
12924 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
12925 | |
12926 | /* Acer Aspire 5336 */ | |
12927 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
12928 | |
12929 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
12930 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 12931 | |
dfb3d47b SD |
12932 | /* Acer C720 Chromebook (Core i3 4005U) */ |
12933 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
12934 | ||
b2a9601c | 12935 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
12936 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
12937 | ||
d4967d8c SD |
12938 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
12939 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
12940 | |
12941 | /* HP Chromebook 14 (Celeron 2955U) */ | |
12942 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
b690e96c JB |
12943 | }; |
12944 | ||
12945 | static void intel_init_quirks(struct drm_device *dev) | |
12946 | { | |
12947 | struct pci_dev *d = dev->pdev; | |
12948 | int i; | |
12949 | ||
12950 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
12951 | struct intel_quirk *q = &intel_quirks[i]; | |
12952 | ||
12953 | if (d->device == q->device && | |
12954 | (d->subsystem_vendor == q->subsystem_vendor || | |
12955 | q->subsystem_vendor == PCI_ANY_ID) && | |
12956 | (d->subsystem_device == q->subsystem_device || | |
12957 | q->subsystem_device == PCI_ANY_ID)) | |
12958 | q->hook(dev); | |
12959 | } | |
5f85f176 EE |
12960 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
12961 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
12962 | intel_dmi_quirks[i].hook(dev); | |
12963 | } | |
b690e96c JB |
12964 | } |
12965 | ||
9cce37f4 JB |
12966 | /* Disable the VGA plane that we never use */ |
12967 | static void i915_disable_vga(struct drm_device *dev) | |
12968 | { | |
12969 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12970 | u8 sr1; | |
766aa1c4 | 12971 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 12972 | |
2b37c616 | 12973 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 12974 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 12975 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
12976 | sr1 = inb(VGA_SR_DATA); |
12977 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
12978 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
12979 | udelay(300); | |
12980 | ||
69769f9a VS |
12981 | /* |
12982 | * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming | |
12983 | * from S3 without preserving (some of?) the other bits. | |
12984 | */ | |
12985 | I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE); | |
9cce37f4 JB |
12986 | POSTING_READ(vga_reg); |
12987 | } | |
12988 | ||
f817586c DV |
12989 | void intel_modeset_init_hw(struct drm_device *dev) |
12990 | { | |
a8f78b58 ED |
12991 | intel_prepare_ddi(dev); |
12992 | ||
f8bf63fd VS |
12993 | if (IS_VALLEYVIEW(dev)) |
12994 | vlv_update_cdclk(dev); | |
12995 | ||
f817586c DV |
12996 | intel_init_clock_gating(dev); |
12997 | ||
8090c6b9 | 12998 | intel_enable_gt_powersave(dev); |
f817586c DV |
12999 | } |
13000 | ||
79e53945 JB |
13001 | void intel_modeset_init(struct drm_device *dev) |
13002 | { | |
652c393a | 13003 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 13004 | int sprite, ret; |
8cc87b75 | 13005 | enum pipe pipe; |
46f297fb | 13006 | struct intel_crtc *crtc; |
79e53945 JB |
13007 | |
13008 | drm_mode_config_init(dev); | |
13009 | ||
13010 | dev->mode_config.min_width = 0; | |
13011 | dev->mode_config.min_height = 0; | |
13012 | ||
019d96cb DA |
13013 | dev->mode_config.preferred_depth = 24; |
13014 | dev->mode_config.prefer_shadow = 1; | |
13015 | ||
e6ecefaa | 13016 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 13017 | |
b690e96c JB |
13018 | intel_init_quirks(dev); |
13019 | ||
1fa61106 ED |
13020 | intel_init_pm(dev); |
13021 | ||
e3c74757 BW |
13022 | if (INTEL_INFO(dev)->num_pipes == 0) |
13023 | return; | |
13024 | ||
e70236a8 | 13025 | intel_init_display(dev); |
7c10a2b5 | 13026 | intel_init_audio(dev); |
e70236a8 | 13027 | |
a6c45cf0 CW |
13028 | if (IS_GEN2(dev)) { |
13029 | dev->mode_config.max_width = 2048; | |
13030 | dev->mode_config.max_height = 2048; | |
13031 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
13032 | dev->mode_config.max_width = 4096; |
13033 | dev->mode_config.max_height = 4096; | |
79e53945 | 13034 | } else { |
a6c45cf0 CW |
13035 | dev->mode_config.max_width = 8192; |
13036 | dev->mode_config.max_height = 8192; | |
79e53945 | 13037 | } |
068be561 | 13038 | |
dc41c154 VS |
13039 | if (IS_845G(dev) || IS_I865G(dev)) { |
13040 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
13041 | dev->mode_config.cursor_height = 1023; | |
13042 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
13043 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
13044 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
13045 | } else { | |
13046 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
13047 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
13048 | } | |
13049 | ||
5d4545ae | 13050 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 13051 | |
28c97730 | 13052 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
13053 | INTEL_INFO(dev)->num_pipes, |
13054 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 13055 | |
055e393f | 13056 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 13057 | intel_crtc_init(dev, pipe); |
1fe47785 DL |
13058 | for_each_sprite(pipe, sprite) { |
13059 | ret = intel_plane_init(dev, pipe, sprite); | |
7f1f3851 | 13060 | if (ret) |
06da8da2 | 13061 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 13062 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 13063 | } |
79e53945 JB |
13064 | } |
13065 | ||
f42bb70d JB |
13066 | intel_init_dpio(dev); |
13067 | ||
e72f9fbf | 13068 | intel_shared_dpll_init(dev); |
ee7b9f93 | 13069 | |
69769f9a VS |
13070 | /* save the BIOS value before clobbering it */ |
13071 | dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev)); | |
9cce37f4 JB |
13072 | /* Just disable it once at startup */ |
13073 | i915_disable_vga(dev); | |
79e53945 | 13074 | intel_setup_outputs(dev); |
11be49eb CW |
13075 | |
13076 | /* Just in case the BIOS is doing something questionable. */ | |
13077 | intel_disable_fbc(dev); | |
fa9fa083 | 13078 | |
6e9f798d | 13079 | drm_modeset_lock_all(dev); |
fa9fa083 | 13080 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 13081 | drm_modeset_unlock_all(dev); |
46f297fb | 13082 | |
d3fcc808 | 13083 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
13084 | if (!crtc->active) |
13085 | continue; | |
13086 | ||
46f297fb | 13087 | /* |
46f297fb JB |
13088 | * Note that reserving the BIOS fb up front prevents us |
13089 | * from stuffing other stolen allocations like the ring | |
13090 | * on top. This prevents some ugliness at boot time, and | |
13091 | * can even allow for smooth boot transitions if the BIOS | |
13092 | * fb is large enough for the active pipe configuration. | |
13093 | */ | |
13094 | if (dev_priv->display.get_plane_config) { | |
13095 | dev_priv->display.get_plane_config(crtc, | |
13096 | &crtc->plane_config); | |
13097 | /* | |
13098 | * If the fb is shared between multiple heads, we'll | |
13099 | * just get the first one. | |
13100 | */ | |
484b41dd | 13101 | intel_find_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 13102 | } |
46f297fb | 13103 | } |
2c7111db CW |
13104 | } |
13105 | ||
7fad798e DV |
13106 | static void intel_enable_pipe_a(struct drm_device *dev) |
13107 | { | |
13108 | struct intel_connector *connector; | |
13109 | struct drm_connector *crt = NULL; | |
13110 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 13111 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
13112 | |
13113 | /* We can't just switch on the pipe A, we need to set things up with a | |
13114 | * proper mode and output configuration. As a gross hack, enable pipe A | |
13115 | * by enabling the load detect pipe once. */ | |
13116 | list_for_each_entry(connector, | |
13117 | &dev->mode_config.connector_list, | |
13118 | base.head) { | |
13119 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
13120 | crt = &connector->base; | |
13121 | break; | |
13122 | } | |
13123 | } | |
13124 | ||
13125 | if (!crt) | |
13126 | return; | |
13127 | ||
208bf9fd VS |
13128 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
13129 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
7fad798e DV |
13130 | } |
13131 | ||
fa555837 DV |
13132 | static bool |
13133 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
13134 | { | |
7eb552ae BW |
13135 | struct drm_device *dev = crtc->base.dev; |
13136 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
13137 | u32 reg, val; |
13138 | ||
7eb552ae | 13139 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
13140 | return true; |
13141 | ||
13142 | reg = DSPCNTR(!crtc->plane); | |
13143 | val = I915_READ(reg); | |
13144 | ||
13145 | if ((val & DISPLAY_PLANE_ENABLE) && | |
13146 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
13147 | return false; | |
13148 | ||
13149 | return true; | |
13150 | } | |
13151 | ||
24929352 DV |
13152 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
13153 | { | |
13154 | struct drm_device *dev = crtc->base.dev; | |
13155 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 13156 | u32 reg; |
24929352 | 13157 | |
24929352 | 13158 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 13159 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
13160 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
13161 | ||
d3eaf884 | 13162 | /* restore vblank interrupts to correct state */ |
d297e103 VS |
13163 | if (crtc->active) { |
13164 | update_scanline_offset(crtc); | |
d3eaf884 | 13165 | drm_vblank_on(dev, crtc->pipe); |
d297e103 | 13166 | } else |
d3eaf884 VS |
13167 | drm_vblank_off(dev, crtc->pipe); |
13168 | ||
24929352 | 13169 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
13170 | * disable the crtc (and hence change the state) if it is wrong. Note |
13171 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
13172 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
13173 | struct intel_connector *connector; |
13174 | bool plane; | |
13175 | ||
24929352 DV |
13176 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
13177 | crtc->base.base.id); | |
13178 | ||
13179 | /* Pipe has the wrong plane attached and the plane is active. | |
13180 | * Temporarily change the plane mapping and disable everything | |
13181 | * ... */ | |
13182 | plane = crtc->plane; | |
13183 | crtc->plane = !plane; | |
9c8958bc | 13184 | crtc->primary_enabled = true; |
24929352 DV |
13185 | dev_priv->display.crtc_disable(&crtc->base); |
13186 | crtc->plane = plane; | |
13187 | ||
13188 | /* ... and break all links. */ | |
13189 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
13190 | base.head) { | |
13191 | if (connector->encoder->base.crtc != &crtc->base) | |
13192 | continue; | |
13193 | ||
7f1950fb EE |
13194 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
13195 | connector->base.encoder = NULL; | |
24929352 | 13196 | } |
7f1950fb EE |
13197 | /* multiple connectors may have the same encoder: |
13198 | * handle them and break crtc link separately */ | |
13199 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
13200 | base.head) | |
13201 | if (connector->encoder->base.crtc == &crtc->base) { | |
13202 | connector->encoder->base.crtc = NULL; | |
13203 | connector->encoder->connectors_active = false; | |
13204 | } | |
24929352 DV |
13205 | |
13206 | WARN_ON(crtc->active); | |
13207 | crtc->base.enabled = false; | |
13208 | } | |
24929352 | 13209 | |
7fad798e DV |
13210 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
13211 | crtc->pipe == PIPE_A && !crtc->active) { | |
13212 | /* BIOS forgot to enable pipe A, this mostly happens after | |
13213 | * resume. Force-enable the pipe to fix this, the update_dpms | |
13214 | * call below we restore the pipe to the right state, but leave | |
13215 | * the required bits on. */ | |
13216 | intel_enable_pipe_a(dev); | |
13217 | } | |
13218 | ||
24929352 DV |
13219 | /* Adjust the state of the output pipe according to whether we |
13220 | * have active connectors/encoders. */ | |
13221 | intel_crtc_update_dpms(&crtc->base); | |
13222 | ||
13223 | if (crtc->active != crtc->base.enabled) { | |
13224 | struct intel_encoder *encoder; | |
13225 | ||
13226 | /* This can happen either due to bugs in the get_hw_state | |
13227 | * functions or because the pipe is force-enabled due to the | |
13228 | * pipe A quirk. */ | |
13229 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
13230 | crtc->base.base.id, | |
13231 | crtc->base.enabled ? "enabled" : "disabled", | |
13232 | crtc->active ? "enabled" : "disabled"); | |
13233 | ||
13234 | crtc->base.enabled = crtc->active; | |
13235 | ||
13236 | /* Because we only establish the connector -> encoder -> | |
13237 | * crtc links if something is active, this means the | |
13238 | * crtc is now deactivated. Break the links. connector | |
13239 | * -> encoder links are only establish when things are | |
13240 | * actually up, hence no need to break them. */ | |
13241 | WARN_ON(crtc->active); | |
13242 | ||
13243 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
13244 | WARN_ON(encoder->connectors_active); | |
13245 | encoder->base.crtc = NULL; | |
13246 | } | |
13247 | } | |
c5ab3bc0 | 13248 | |
a3ed6aad | 13249 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
13250 | /* |
13251 | * We start out with underrun reporting disabled to avoid races. | |
13252 | * For correct bookkeeping mark this on active crtcs. | |
13253 | * | |
c5ab3bc0 DV |
13254 | * Also on gmch platforms we dont have any hardware bits to |
13255 | * disable the underrun reporting. Which means we need to start | |
13256 | * out with underrun reporting disabled also on inactive pipes, | |
13257 | * since otherwise we'll complain about the garbage we read when | |
13258 | * e.g. coming up after runtime pm. | |
13259 | * | |
4cc31489 DV |
13260 | * No protection against concurrent access is required - at |
13261 | * worst a fifo underrun happens which also sets this to false. | |
13262 | */ | |
13263 | crtc->cpu_fifo_underrun_disabled = true; | |
13264 | crtc->pch_fifo_underrun_disabled = true; | |
13265 | } | |
24929352 DV |
13266 | } |
13267 | ||
13268 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
13269 | { | |
13270 | struct intel_connector *connector; | |
13271 | struct drm_device *dev = encoder->base.dev; | |
13272 | ||
13273 | /* We need to check both for a crtc link (meaning that the | |
13274 | * encoder is active and trying to read from a pipe) and the | |
13275 | * pipe itself being active. */ | |
13276 | bool has_active_crtc = encoder->base.crtc && | |
13277 | to_intel_crtc(encoder->base.crtc)->active; | |
13278 | ||
13279 | if (encoder->connectors_active && !has_active_crtc) { | |
13280 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
13281 | encoder->base.base.id, | |
8e329a03 | 13282 | encoder->base.name); |
24929352 DV |
13283 | |
13284 | /* Connector is active, but has no active pipe. This is | |
13285 | * fallout from our resume register restoring. Disable | |
13286 | * the encoder manually again. */ | |
13287 | if (encoder->base.crtc) { | |
13288 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
13289 | encoder->base.base.id, | |
8e329a03 | 13290 | encoder->base.name); |
24929352 | 13291 | encoder->disable(encoder); |
a62d1497 VS |
13292 | if (encoder->post_disable) |
13293 | encoder->post_disable(encoder); | |
24929352 | 13294 | } |
7f1950fb EE |
13295 | encoder->base.crtc = NULL; |
13296 | encoder->connectors_active = false; | |
24929352 DV |
13297 | |
13298 | /* Inconsistent output/port/pipe state happens presumably due to | |
13299 | * a bug in one of the get_hw_state functions. Or someplace else | |
13300 | * in our code, like the register restore mess on resume. Clamp | |
13301 | * things to off as a safer default. */ | |
13302 | list_for_each_entry(connector, | |
13303 | &dev->mode_config.connector_list, | |
13304 | base.head) { | |
13305 | if (connector->encoder != encoder) | |
13306 | continue; | |
7f1950fb EE |
13307 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
13308 | connector->base.encoder = NULL; | |
24929352 DV |
13309 | } |
13310 | } | |
13311 | /* Enabled encoders without active connectors will be fixed in | |
13312 | * the crtc fixup. */ | |
13313 | } | |
13314 | ||
04098753 | 13315 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
13316 | { |
13317 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 13318 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 13319 | |
04098753 ID |
13320 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
13321 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
13322 | i915_disable_vga(dev); | |
13323 | } | |
13324 | } | |
13325 | ||
13326 | void i915_redisable_vga(struct drm_device *dev) | |
13327 | { | |
13328 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13329 | ||
8dc8a27c PZ |
13330 | /* This function can be called both from intel_modeset_setup_hw_state or |
13331 | * at a very early point in our resume sequence, where the power well | |
13332 | * structures are not yet restored. Since this function is at a very | |
13333 | * paranoid "someone might have enabled VGA while we were not looking" | |
13334 | * level, just check if the power well is enabled instead of trying to | |
13335 | * follow the "don't touch the power well if we don't need it" policy | |
13336 | * the rest of the driver uses. */ | |
f458ebbc | 13337 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
13338 | return; |
13339 | ||
04098753 | 13340 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
13341 | } |
13342 | ||
98ec7739 VS |
13343 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
13344 | { | |
13345 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
13346 | ||
13347 | if (!crtc->active) | |
13348 | return false; | |
13349 | ||
13350 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
13351 | } | |
13352 | ||
30e984df | 13353 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
13354 | { |
13355 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13356 | enum pipe pipe; | |
24929352 DV |
13357 | struct intel_crtc *crtc; |
13358 | struct intel_encoder *encoder; | |
13359 | struct intel_connector *connector; | |
5358901f | 13360 | int i; |
24929352 | 13361 | |
d3fcc808 | 13362 | for_each_intel_crtc(dev, crtc) { |
88adfff1 | 13363 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 13364 | |
9953599b DV |
13365 | crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
13366 | ||
0e8ffe1b DV |
13367 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
13368 | &crtc->config); | |
24929352 DV |
13369 | |
13370 | crtc->base.enabled = crtc->active; | |
98ec7739 | 13371 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
13372 | |
13373 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
13374 | crtc->base.base.id, | |
13375 | crtc->active ? "enabled" : "disabled"); | |
13376 | } | |
13377 | ||
5358901f DV |
13378 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
13379 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13380 | ||
3e369b76 ACO |
13381 | pll->on = pll->get_hw_state(dev_priv, pll, |
13382 | &pll->config.hw_state); | |
5358901f | 13383 | pll->active = 0; |
3e369b76 | 13384 | pll->config.crtc_mask = 0; |
d3fcc808 | 13385 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 13386 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 13387 | pll->active++; |
3e369b76 | 13388 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 13389 | } |
5358901f | 13390 | } |
5358901f | 13391 | |
1e6f2ddc | 13392 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 13393 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 13394 | |
3e369b76 | 13395 | if (pll->config.crtc_mask) |
bd2bb1b9 | 13396 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
13397 | } |
13398 | ||
b2784e15 | 13399 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
13400 | pipe = 0; |
13401 | ||
13402 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
13403 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
13404 | encoder->base.crtc = &crtc->base; | |
1d37b689 | 13405 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
13406 | } else { |
13407 | encoder->base.crtc = NULL; | |
13408 | } | |
13409 | ||
13410 | encoder->connectors_active = false; | |
6f2bcceb | 13411 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 13412 | encoder->base.base.id, |
8e329a03 | 13413 | encoder->base.name, |
24929352 | 13414 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 13415 | pipe_name(pipe)); |
24929352 DV |
13416 | } |
13417 | ||
13418 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
13419 | base.head) { | |
13420 | if (connector->get_hw_state(connector)) { | |
13421 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
13422 | connector->encoder->connectors_active = true; | |
13423 | connector->base.encoder = &connector->encoder->base; | |
13424 | } else { | |
13425 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
13426 | connector->base.encoder = NULL; | |
13427 | } | |
13428 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
13429 | connector->base.base.id, | |
c23cc417 | 13430 | connector->base.name, |
24929352 DV |
13431 | connector->base.encoder ? "enabled" : "disabled"); |
13432 | } | |
30e984df DV |
13433 | } |
13434 | ||
13435 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
13436 | * and i915 state tracking structures. */ | |
13437 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
13438 | bool force_restore) | |
13439 | { | |
13440 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13441 | enum pipe pipe; | |
30e984df DV |
13442 | struct intel_crtc *crtc; |
13443 | struct intel_encoder *encoder; | |
35c95375 | 13444 | int i; |
30e984df DV |
13445 | |
13446 | intel_modeset_readout_hw_state(dev); | |
24929352 | 13447 | |
babea61d JB |
13448 | /* |
13449 | * Now that we have the config, copy it to each CRTC struct | |
13450 | * Note that this could go away if we move to using crtc_config | |
13451 | * checking everywhere. | |
13452 | */ | |
d3fcc808 | 13453 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 13454 | if (crtc->active && i915.fastboot) { |
f6a83288 | 13455 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
babea61d JB |
13456 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
13457 | crtc->base.base.id); | |
13458 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
13459 | } | |
13460 | } | |
13461 | ||
24929352 | 13462 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 13463 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
13464 | intel_sanitize_encoder(encoder); |
13465 | } | |
13466 | ||
055e393f | 13467 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
13468 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
13469 | intel_sanitize_crtc(crtc); | |
c0b03411 | 13470 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 13471 | } |
9a935856 | 13472 | |
35c95375 DV |
13473 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
13474 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13475 | ||
13476 | if (!pll->on || pll->active) | |
13477 | continue; | |
13478 | ||
13479 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
13480 | ||
13481 | pll->disable(dev_priv, pll); | |
13482 | pll->on = false; | |
13483 | } | |
13484 | ||
3078999f PB |
13485 | if (IS_GEN9(dev)) |
13486 | skl_wm_get_hw_state(dev); | |
13487 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 VS |
13488 | ilk_wm_get_hw_state(dev); |
13489 | ||
45e2b5f6 | 13490 | if (force_restore) { |
7d0bc1ea VS |
13491 | i915_redisable_vga(dev); |
13492 | ||
f30da187 DV |
13493 | /* |
13494 | * We need to use raw interfaces for restoring state to avoid | |
13495 | * checking (bogus) intermediate states. | |
13496 | */ | |
055e393f | 13497 | for_each_pipe(dev_priv, pipe) { |
b5644d05 JB |
13498 | struct drm_crtc *crtc = |
13499 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 | 13500 | |
7f27126e JB |
13501 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, |
13502 | crtc->primary->fb); | |
45e2b5f6 DV |
13503 | } |
13504 | } else { | |
13505 | intel_modeset_update_staged_output_state(dev); | |
13506 | } | |
8af6cf88 DV |
13507 | |
13508 | intel_modeset_check_state(dev); | |
2c7111db CW |
13509 | } |
13510 | ||
13511 | void intel_modeset_gem_init(struct drm_device *dev) | |
13512 | { | |
92122789 | 13513 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd | 13514 | struct drm_crtc *c; |
2ff8fde1 | 13515 | struct drm_i915_gem_object *obj; |
484b41dd | 13516 | |
ae48434c ID |
13517 | mutex_lock(&dev->struct_mutex); |
13518 | intel_init_gt_powersave(dev); | |
13519 | mutex_unlock(&dev->struct_mutex); | |
13520 | ||
92122789 JB |
13521 | /* |
13522 | * There may be no VBT; and if the BIOS enabled SSC we can | |
13523 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
13524 | * BIOS isn't using it, don't assume it will work even if the VBT | |
13525 | * indicates as much. | |
13526 | */ | |
13527 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
13528 | dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
13529 | DREF_SSC1_ENABLE); | |
13530 | ||
1833b134 | 13531 | intel_modeset_init_hw(dev); |
02e792fb DV |
13532 | |
13533 | intel_setup_overlay(dev); | |
484b41dd JB |
13534 | |
13535 | /* | |
13536 | * Make sure any fbs we allocated at startup are properly | |
13537 | * pinned & fenced. When we do the allocation it's too early | |
13538 | * for this. | |
13539 | */ | |
13540 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 13541 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
13542 | obj = intel_fb_obj(c->primary->fb); |
13543 | if (obj == NULL) | |
484b41dd JB |
13544 | continue; |
13545 | ||
850c4cdc TU |
13546 | if (intel_pin_and_fence_fb_obj(c->primary, |
13547 | c->primary->fb, | |
13548 | NULL)) { | |
484b41dd JB |
13549 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
13550 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
13551 | drm_framebuffer_unreference(c->primary->fb); |
13552 | c->primary->fb = NULL; | |
484b41dd JB |
13553 | } |
13554 | } | |
13555 | mutex_unlock(&dev->struct_mutex); | |
0962c3c9 VS |
13556 | |
13557 | intel_backlight_register(dev); | |
79e53945 JB |
13558 | } |
13559 | ||
4932e2c3 ID |
13560 | void intel_connector_unregister(struct intel_connector *intel_connector) |
13561 | { | |
13562 | struct drm_connector *connector = &intel_connector->base; | |
13563 | ||
13564 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 13565 | drm_connector_unregister(connector); |
4932e2c3 ID |
13566 | } |
13567 | ||
79e53945 JB |
13568 | void intel_modeset_cleanup(struct drm_device *dev) |
13569 | { | |
652c393a | 13570 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 13571 | struct drm_connector *connector; |
652c393a | 13572 | |
2eb5252e ID |
13573 | intel_disable_gt_powersave(dev); |
13574 | ||
0962c3c9 VS |
13575 | intel_backlight_unregister(dev); |
13576 | ||
fd0c0642 DV |
13577 | /* |
13578 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 13579 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
13580 | * experience fancy races otherwise. |
13581 | */ | |
2aeb7d3a | 13582 | intel_irq_uninstall(dev_priv); |
eb21b92b | 13583 | |
fd0c0642 DV |
13584 | /* |
13585 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
13586 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
13587 | */ | |
f87ea761 | 13588 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 13589 | |
652c393a JB |
13590 | mutex_lock(&dev->struct_mutex); |
13591 | ||
723bfd70 JB |
13592 | intel_unregister_dsm_handler(); |
13593 | ||
973d04f9 | 13594 | intel_disable_fbc(dev); |
e70236a8 | 13595 | |
930ebb46 DV |
13596 | ironlake_teardown_rc6(dev); |
13597 | ||
69341a5e KH |
13598 | mutex_unlock(&dev->struct_mutex); |
13599 | ||
1630fe75 CW |
13600 | /* flush any delayed tasks or pending work */ |
13601 | flush_scheduled_work(); | |
13602 | ||
db31af1d JN |
13603 | /* destroy the backlight and sysfs files before encoders/connectors */ |
13604 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
13605 | struct intel_connector *intel_connector; |
13606 | ||
13607 | intel_connector = to_intel_connector(connector); | |
13608 | intel_connector->unregister(intel_connector); | |
db31af1d | 13609 | } |
d9255d57 | 13610 | |
79e53945 | 13611 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
13612 | |
13613 | intel_cleanup_overlay(dev); | |
ae48434c ID |
13614 | |
13615 | mutex_lock(&dev->struct_mutex); | |
13616 | intel_cleanup_gt_powersave(dev); | |
13617 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13618 | } |
13619 | ||
f1c79df3 ZW |
13620 | /* |
13621 | * Return which encoder is currently attached for connector. | |
13622 | */ | |
df0e9248 | 13623 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 13624 | { |
df0e9248 CW |
13625 | return &intel_attached_encoder(connector)->base; |
13626 | } | |
f1c79df3 | 13627 | |
df0e9248 CW |
13628 | void intel_connector_attach_encoder(struct intel_connector *connector, |
13629 | struct intel_encoder *encoder) | |
13630 | { | |
13631 | connector->encoder = encoder; | |
13632 | drm_mode_connector_attach_encoder(&connector->base, | |
13633 | &encoder->base); | |
79e53945 | 13634 | } |
28d52043 DA |
13635 | |
13636 | /* | |
13637 | * set vga decode state - true == enable VGA decode | |
13638 | */ | |
13639 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
13640 | { | |
13641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 13642 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
13643 | u16 gmch_ctrl; |
13644 | ||
75fa041d CW |
13645 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
13646 | DRM_ERROR("failed to read control word\n"); | |
13647 | return -EIO; | |
13648 | } | |
13649 | ||
c0cc8a55 CW |
13650 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
13651 | return 0; | |
13652 | ||
28d52043 DA |
13653 | if (state) |
13654 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
13655 | else | |
13656 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
13657 | |
13658 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
13659 | DRM_ERROR("failed to write control word\n"); | |
13660 | return -EIO; | |
13661 | } | |
13662 | ||
28d52043 DA |
13663 | return 0; |
13664 | } | |
c4a1d9e4 | 13665 | |
c4a1d9e4 | 13666 | struct intel_display_error_state { |
ff57f1b0 PZ |
13667 | |
13668 | u32 power_well_driver; | |
13669 | ||
63b66e5b CW |
13670 | int num_transcoders; |
13671 | ||
c4a1d9e4 CW |
13672 | struct intel_cursor_error_state { |
13673 | u32 control; | |
13674 | u32 position; | |
13675 | u32 base; | |
13676 | u32 size; | |
52331309 | 13677 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
13678 | |
13679 | struct intel_pipe_error_state { | |
ddf9c536 | 13680 | bool power_domain_on; |
c4a1d9e4 | 13681 | u32 source; |
f301b1e1 | 13682 | u32 stat; |
52331309 | 13683 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
13684 | |
13685 | struct intel_plane_error_state { | |
13686 | u32 control; | |
13687 | u32 stride; | |
13688 | u32 size; | |
13689 | u32 pos; | |
13690 | u32 addr; | |
13691 | u32 surface; | |
13692 | u32 tile_offset; | |
52331309 | 13693 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
13694 | |
13695 | struct intel_transcoder_error_state { | |
ddf9c536 | 13696 | bool power_domain_on; |
63b66e5b CW |
13697 | enum transcoder cpu_transcoder; |
13698 | ||
13699 | u32 conf; | |
13700 | ||
13701 | u32 htotal; | |
13702 | u32 hblank; | |
13703 | u32 hsync; | |
13704 | u32 vtotal; | |
13705 | u32 vblank; | |
13706 | u32 vsync; | |
13707 | } transcoder[4]; | |
c4a1d9e4 CW |
13708 | }; |
13709 | ||
13710 | struct intel_display_error_state * | |
13711 | intel_display_capture_error_state(struct drm_device *dev) | |
13712 | { | |
fbee40df | 13713 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 13714 | struct intel_display_error_state *error; |
63b66e5b CW |
13715 | int transcoders[] = { |
13716 | TRANSCODER_A, | |
13717 | TRANSCODER_B, | |
13718 | TRANSCODER_C, | |
13719 | TRANSCODER_EDP, | |
13720 | }; | |
c4a1d9e4 CW |
13721 | int i; |
13722 | ||
63b66e5b CW |
13723 | if (INTEL_INFO(dev)->num_pipes == 0) |
13724 | return NULL; | |
13725 | ||
9d1cb914 | 13726 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
13727 | if (error == NULL) |
13728 | return NULL; | |
13729 | ||
190be112 | 13730 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
13731 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
13732 | ||
055e393f | 13733 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 13734 | error->pipe[i].power_domain_on = |
f458ebbc DV |
13735 | __intel_display_power_is_enabled(dev_priv, |
13736 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 13737 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
13738 | continue; |
13739 | ||
5efb3e28 VS |
13740 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
13741 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
13742 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
13743 | |
13744 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
13745 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 13746 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 13747 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
13748 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
13749 | } | |
ca291363 PZ |
13750 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
13751 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
13752 | if (INTEL_INFO(dev)->gen >= 4) { |
13753 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
13754 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
13755 | } | |
13756 | ||
c4a1d9e4 | 13757 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 13758 | |
3abfce77 | 13759 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 13760 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
13761 | } |
13762 | ||
13763 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
13764 | if (HAS_DDI(dev_priv->dev)) | |
13765 | error->num_transcoders++; /* Account for eDP. */ | |
13766 | ||
13767 | for (i = 0; i < error->num_transcoders; i++) { | |
13768 | enum transcoder cpu_transcoder = transcoders[i]; | |
13769 | ||
ddf9c536 | 13770 | error->transcoder[i].power_domain_on = |
f458ebbc | 13771 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 13772 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 13773 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
13774 | continue; |
13775 | ||
63b66e5b CW |
13776 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
13777 | ||
13778 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
13779 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
13780 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
13781 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
13782 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
13783 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
13784 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
13785 | } |
13786 | ||
13787 | return error; | |
13788 | } | |
13789 | ||
edc3d884 MK |
13790 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
13791 | ||
c4a1d9e4 | 13792 | void |
edc3d884 | 13793 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
13794 | struct drm_device *dev, |
13795 | struct intel_display_error_state *error) | |
13796 | { | |
055e393f | 13797 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
13798 | int i; |
13799 | ||
63b66e5b CW |
13800 | if (!error) |
13801 | return; | |
13802 | ||
edc3d884 | 13803 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 13804 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 13805 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 13806 | error->power_well_driver); |
055e393f | 13807 | for_each_pipe(dev_priv, i) { |
edc3d884 | 13808 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
13809 | err_printf(m, " Power: %s\n", |
13810 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 13811 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 13812 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
13813 | |
13814 | err_printf(m, "Plane [%d]:\n", i); | |
13815 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
13816 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 13817 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
13818 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
13819 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 13820 | } |
4b71a570 | 13821 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 13822 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 13823 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
13824 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
13825 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
13826 | } |
13827 | ||
edc3d884 MK |
13828 | err_printf(m, "Cursor [%d]:\n", i); |
13829 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
13830 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
13831 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 13832 | } |
63b66e5b CW |
13833 | |
13834 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 13835 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 13836 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
13837 | err_printf(m, " Power: %s\n", |
13838 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
13839 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
13840 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
13841 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
13842 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
13843 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
13844 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
13845 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
13846 | } | |
c4a1d9e4 | 13847 | } |
e2fcdaa9 VS |
13848 | |
13849 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
13850 | { | |
13851 | struct intel_crtc *crtc; | |
13852 | ||
13853 | for_each_intel_crtc(dev, crtc) { | |
13854 | struct intel_unpin_work *work; | |
e2fcdaa9 | 13855 | |
5e2d7afc | 13856 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
13857 | |
13858 | work = crtc->unpin_work; | |
13859 | ||
13860 | if (work && work->event && | |
13861 | work->event->base.file_priv == file) { | |
13862 | kfree(work->event); | |
13863 | work->event = NULL; | |
13864 | } | |
13865 | ||
5e2d7afc | 13866 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
13867 | } |
13868 | } |