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drm/i915: conditionally disable pch resources in ilk_crtc_disable
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
d4906093 62};
79e53945 63
2377b741
JB		 64/* FDI */
65#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
d2acd215
DV		 67int
68intel_pch_rawclk(struct drm_device *dev)
69{
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75}
76
021357ac
CW		 77static inline u32 /* units of 100MHz */
78intel_fdi_link_freq(struct drm_device *dev)
79{
8b99e68c
CW		 80 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
021357ac
CW		 85}
86
e4b36699 87static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 98};
99
100static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
e4b36699 111};
273e27ca 112
e4b36699 113static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 137};
138
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
044c7c41 152 },
e4b36699
KP		 153};
154
155static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
044c7c41 179 },
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
044c7c41 193 },
e4b36699
KP		 194};
195
f2b115e6 196static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 199 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
273e27ca 202 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
f2b115e6 211static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 222};
223
273e27ca
EA		 224/* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
b91ad0ec 229static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
b91ad0ec 242static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 253};
254
255static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 266};
267
273e27ca 268/* LVDS 100mhz refclk limits. */
b91ad0ec 269static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
0206e353 277 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 280};
281
282static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
0206e353 290 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 293};
294
a0c4da24
JB		 295static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
75e53986 303 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 306};
307
308static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 319};
320
321static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 324 .n = { .min = 1, .max = 7 },
74a4dd2e 325 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
75e53986 329 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 332};
333
1b894b59
CW		 334static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
2c07245f 336{
b91ad0ec 337 struct drm_device *dev = crtc->dev;
2c07245f 338 const intel_limit_t *limit;
b91ad0ec
ZW		 339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 341 if (intel_is_dual_link_lvds(dev)) {
1b894b59 342 if (refclk == 100000)
b91ad0ec
ZW		 343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
c6bb3538 352 } else
b91ad0ec 353 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 354
355 return limit;
356}
357
044c7c41
ML		 358static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359{
360 struct drm_device *dev = crtc->dev;
044c7c41
ML		 361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 364 if (intel_is_dual_link_lvds(dev))
e4b36699 365 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 366 else
e4b36699 367 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 370 limit = &intel_limits_g4x_hdmi;
044c7c41 371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 372 limit = &intel_limits_g4x_sdvo;
044c7c41 373 } else /* The option is for other outputs */
e4b36699 374 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 375
376 return limit;
377}
378
1b894b59 379static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 380{
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
bad720ff 384 if (HAS_PCH_SPLIT(dev))
1b894b59 385 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 386 else if (IS_G4X(dev)) {
044c7c41 387 limit = intel_g4x_limit(crtc);
f2b115e6 388 } else if (IS_PINEVIEW(dev)) {
2177832f 389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 390 limit = &intel_limits_pineview_lvds;
2177832f 391 else
f2b115e6 392 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 407 limit = &intel_limits_i8xx_lvds;
79e53945 408 else
e4b36699 409 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 410 }
411 return limit;
412}
413
f2b115e6
AJ		 414/* m1 is reserved as 0 in Pineview, n is a ring counter */
415static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 416{
2177832f
SL		 417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421}
422
7429e9d4
DV		 423static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424{
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426}
427
ac58c3f0 428static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 429{
7429e9d4 430 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434}
435
79e53945
JB		 436/**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
4ef69c7a 439bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 440{
4ef69c7a 441 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 442 struct intel_encoder *encoder;
443
6c2b7c12
DV		 444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
4ef69c7a
CW		 446 return true;
447
448 return false;
79e53945
JB		 449}
450
7c04d1d9 451#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 452/**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
1b894b59
CW		 457static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
79e53945 460{
79e53945 461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 462 INTELPllInvalid("p1 out of range\n");
79e53945 463 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 464 INTELPllInvalid("p out of range\n");
79e53945 465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 466 INTELPllInvalid("m2 out of range\n");
79e53945 467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 468 INTELPllInvalid("m1 out of range\n");
f2b115e6 469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 470 INTELPllInvalid("m1 <= m2\n");
79e53945 471 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 472 INTELPllInvalid("m out of range\n");
79e53945 473 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 474 INTELPllInvalid("n out of range\n");
79e53945 475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 476 INTELPllInvalid("vco out of range\n");
79e53945
JB		 477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 481 INTELPllInvalid("dot out of range\n");
79e53945
JB		 482
483 return true;
484}
485
d4906093 486static bool
ee9300bb 487i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
ac58c3f0
DV		 490{
491 struct drm_device *dev = crtc->dev;
492 intel_clock_t clock;
493 int err = target;
494
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
496 /*
497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
500 */
501 if (intel_is_dual_link_lvds(dev))
502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
512 memset(best_clock, 0, sizeof(*best_clock));
513
514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 518 if (clock.m2 >= clock.m1)
ac58c3f0
DV		 519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
524 int this_err;
d4906093 525
ac58c3f0
DV		 526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545}
546
547static bool
ee9300bb
DV		 548pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
79e53945
JB		 551{
552 struct drm_device *dev = crtc->dev;
79e53945 553 intel_clock_t clock;
79e53945
JB		 554 int err = target;
555
a210b028 556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 557 /*
a210b028
DV		 558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
79e53945 561 */
1974cad0 562 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
0206e353 573 memset(best_clock, 0, sizeof(*best_clock));
79e53945 574
42158660
ZY		 575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 583 int this_err;
584
ac58c3f0 585 pineview_clock(refclk, &clock);
1b894b59
CW		 586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
79e53945 588 continue;
cec2f356
SP		 589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
79e53945
JB		 592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604}
605
d4906093 606static bool
ee9300bb
DV		 607g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
d4906093
ML		 610{
611 struct drm_device *dev = crtc->dev;
d4906093
ML		 612 intel_clock_t clock;
613 int max_n;
614 bool found;
6ba770dc
AJ		 615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 620 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
f77f13e2 633 /* based on hardware requirement, prefer smaller n to precision */
d4906093 634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 635 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
ac58c3f0 644 i9xx_clock(refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
d4906093 647 continue;
1b894b59
CW		 648
649 this_err = abs(clock.dot - target);
d4906093
ML		 650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
2c07245f
ZW		 660 return found;
661}
662
a0c4da24 663static bool
ee9300bb
DV		 664vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
a0c4da24
JB		 667{
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
af447bd3 674 flag = 0;
a0c4da24
JB		 675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730}
a4fc5ed6 731
a5c961d1
PZ		 732enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734{
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
3b117c8f 738 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 739}
740
a928d536
PZ		 741static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742{
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750}
751
9d0498a2
JB		 752/**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 761{
9d0498a2 762 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 763 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 764
a928d536
PZ		 765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
300387c0
CW		 770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
9d0498a2 786 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
9d0498a2
JB		 790 DRM_DEBUG_KMS("vblank wait timed out\n");
791}
792
ab7ad7f6
KP		 793/*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
ab7ad7f6
KP		 802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
58e10eb9 808 *
9d0498a2 809 */
58e10eb9 810void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 811{
812 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
ab7ad7f6
KP		 815
816 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 817 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 818
819 /* Wait for the Pipe State to go off */
58e10eb9
CW		 820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
284637d9 822 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 823 } else {
837ba00f 824 u32 last_line, line_mask;
58e10eb9 825 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
837ba00f
PZ		 828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
ab7ad7f6
KP		 833 /* Wait for the display line to settle */
834 do {
837ba00f 835 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 836 mdelay(5);
837ba00f 837 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
284637d9 840 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 841 }
79e53945
JB		 842}
843
b0ea7d37
DL		 844/*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853{
854 u32 bit;
855
c36346e3
DL		 856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
b0ea7d37
DL		 884 }
885
886 return I915_READ(SDEISR) & bit;
887}
888
b24e7179
JB		 889static const char *state_string(bool enabled)
890{
891 return enabled ? "on" : "off";
892}
893
894/* Only for pre-ILK configs */
895static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897{
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908}
909#define assert_pll_enabled(d, p) assert_pll(d, p, true)
910#define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
040484af
JB		 912/* For ILK+ */
913static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 914 struct intel_pch_pll *pll,
915 struct intel_crtc *crtc,
916 bool state)
040484af 917{
040484af
JB		 918 u32 val;
919 bool cur_state;
920
9d82aa17
ED		 921 if (HAS_PCH_LPT(dev_priv->dev)) {
922 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
923 return;
924 }
925
92b27b08
CW		 926 if (WARN (!pll,
927 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 928 return;
ee7b9f93 929
92b27b08
CW		 930 val = I915_READ(pll->pll_reg);
931 cur_state = !!(val & DPLL_VCO_ENABLE);
932 WARN(cur_state != state,
933 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
934 pll->pll_reg, state_string(state), state_string(cur_state), val);
935
936 /* Make sure the selected PLL is correctly attached to the transcoder */
937 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 938 u32 pch_dpll;
939
940 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 941 cur_state = pll->pll_reg == _PCH_DPLL_B;
942 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 943 "PLL[%d] not attached to this transcoder %c: %08x\n",
944 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 945 cur_state = !!(val >> (4*crtc->pipe + 3));
946 WARN(cur_state != state,
4bb6f1f3 947 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 948 pll->pll_reg == _PCH_DPLL_B,
949 state_string(state),
4bb6f1f3 950 pipe_name(crtc->pipe),
92b27b08
CW		 951 val);
952 }
d3ccbe86 953 }
040484af 954}
92b27b08
CW		 955#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
956#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 957
958static void assert_fdi_tx(struct drm_i915_private *dev_priv,
959 enum pipe pipe, bool state)
960{
961 int reg;
962 u32 val;
963 bool cur_state;
ad80a810
PZ		 964 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
965 pipe);
040484af 966
affa9354
PZ		 967 if (HAS_DDI(dev_priv->dev)) {
968 /* DDI does not have a specific FDI_TX register */
ad80a810 969 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 970 val = I915_READ(reg);
ad80a810 971 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 972 } else {
973 reg = FDI_TX_CTL(pipe);
974 val = I915_READ(reg);
975 cur_state = !!(val & FDI_TX_ENABLE);
976 }
040484af
JB		 977 WARN(cur_state != state,
978 "FDI TX state assertion failure (expected %s, current %s)\n",
979 state_string(state), state_string(cur_state));
980}
981#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
982#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
983
984static void assert_fdi_rx(struct drm_i915_private *dev_priv,
985 enum pipe pipe, bool state)
986{
987 int reg;
988 u32 val;
989 bool cur_state;
990
d63fa0dc
PZ		 991 reg = FDI_RX_CTL(pipe);
992 val = I915_READ(reg);
993 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 994 WARN(cur_state != state,
995 "FDI RX state assertion failure (expected %s, current %s)\n",
996 state_string(state), state_string(cur_state));
997}
998#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
999#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1000
1001static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe)
1003{
1004 int reg;
1005 u32 val;
1006
1007 /* ILK FDI PLL is always enabled */
1008 if (dev_priv->info->gen == 5)
1009 return;
1010
bf507ef7 1011 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1012 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1013 return;
1014
040484af
JB		 1015 reg = FDI_TX_CTL(pipe);
1016 val = I915_READ(reg);
1017 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1018}
1019
1020static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1021 enum pipe pipe)
1022{
1023 int reg;
1024 u32 val;
1025
1026 reg = FDI_RX_CTL(pipe);
1027 val = I915_READ(reg);
1028 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1029}
1030
ea0760cf
JB		 1031static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1032 enum pipe pipe)
1033{
1034 int pp_reg, lvds_reg;
1035 u32 val;
1036 enum pipe panel_pipe = PIPE_A;
0de3b485 1037 bool locked = true;
ea0760cf
JB		 1038
1039 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1040 pp_reg = PCH_PP_CONTROL;
1041 lvds_reg = PCH_LVDS;
1042 } else {
1043 pp_reg = PP_CONTROL;
1044 lvds_reg = LVDS;
1045 }
1046
1047 val = I915_READ(pp_reg);
1048 if (!(val & PANEL_POWER_ON) ||
1049 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1050 locked = false;
1051
1052 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1053 panel_pipe = PIPE_B;
1054
1055 WARN(panel_pipe == pipe && locked,
1056 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1057 pipe_name(pipe));
ea0760cf
JB		 1058}
1059
b840d907
JB		 1060void assert_pipe(struct drm_i915_private *dev_priv,
1061 enum pipe pipe, bool state)
b24e7179
JB		 1062{
1063 int reg;
1064 u32 val;
63d7bbe9 1065 bool cur_state;
702e7a56
PZ		 1066 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1067 pipe);
b24e7179 1068
8e636784
DV		 1069 /* if we need the pipe A quirk it must be always on */
1070 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1071 state = true;
1072
b97186f0
PZ		 1073 if (!intel_display_power_enabled(dev_priv->dev,
1074 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1075 cur_state = false;
1076 } else {
1077 reg = PIPECONF(cpu_transcoder);
1078 val = I915_READ(reg);
1079 cur_state = !!(val & PIPECONF_ENABLE);
1080 }
1081
63d7bbe9
JB		 1082 WARN(cur_state != state,
1083 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1084 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1085}
1086
931872fc
CW		 1087static void assert_plane(struct drm_i915_private *dev_priv,
1088 enum plane plane, bool state)
b24e7179
JB		 1089{
1090 int reg;
1091 u32 val;
931872fc 1092 bool cur_state;
b24e7179
JB		 1093
1094 reg = DSPCNTR(plane);
1095 val = I915_READ(reg);
931872fc
CW		 1096 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1097 WARN(cur_state != state,
1098 "plane %c assertion failure (expected %s, current %s)\n",
1099 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1100}
1101
931872fc
CW		 1102#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1103#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1104
b24e7179
JB		 1105static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1106 enum pipe pipe)
1107{
653e1026 1108 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1109 int reg, i;
1110 u32 val;
1111 int cur_pipe;
1112
653e1026
VS		 1113 /* Primary planes are fixed to pipes on gen4+ */
1114 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1115 reg = DSPCNTR(pipe);
1116 val = I915_READ(reg);
1117 WARN((val & DISPLAY_PLANE_ENABLE),
1118 "plane %c assertion failure, should be disabled but not\n",
1119 plane_name(pipe));
19ec1358 1120 return;
28c05794 1121 }
19ec1358 1122
b24e7179 1123 /* Need to check both planes against the pipe */
653e1026 1124 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
b24e7179
JB		 1125 reg = DSPCNTR(i);
1126 val = I915_READ(reg);
1127 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1128 DISPPLANE_SEL_PIPE_SHIFT;
1129 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1130 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1131 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1132 }
1133}
1134
19332d7a
JB		 1135static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1136 enum pipe pipe)
1137{
20674eef 1138 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1139 int reg, i;
1140 u32 val;
1141
20674eef
VS		 1142 if (IS_VALLEYVIEW(dev)) {
1143 for (i = 0; i < dev_priv->num_plane; i++) {
1144 reg = SPCNTR(pipe, i);
1145 val = I915_READ(reg);
1146 WARN((val & SP_ENABLE),
1147 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1148 sprite_name(pipe, i), pipe_name(pipe));
1149 }
1150 } else if (INTEL_INFO(dev)->gen >= 7) {
1151 reg = SPRCTL(pipe);
1152 val = I915_READ(reg);
1153 WARN((val & SPRITE_ENABLE),
1154 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1155 plane_name(pipe), pipe_name(pipe));
1156 } else if (INTEL_INFO(dev)->gen >= 5) {
1157 reg = DVSCNTR(pipe);
19332d7a 1158 val = I915_READ(reg);
20674eef 1159 WARN((val & DVS_ENABLE),
06da8da2 1160 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1161 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1162 }
1163}
1164
92f2584a
JB		 1165static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1166{
1167 u32 val;
1168 bool enabled;
1169
9d82aa17
ED		 1170 if (HAS_PCH_LPT(dev_priv->dev)) {
1171 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1172 return;
1173 }
1174
92f2584a
JB		 1175 val = I915_READ(PCH_DREF_CONTROL);
1176 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1177 DREF_SUPERSPREAD_SOURCE_MASK));
1178 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1179}
1180
ab9412ba
DV		 1181static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1182 enum pipe pipe)
92f2584a
JB		 1183{
1184 int reg;
1185 u32 val;
1186 bool enabled;
1187
ab9412ba 1188 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1189 val = I915_READ(reg);
1190 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1191 WARN(enabled,
1192 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1193 pipe_name(pipe));
92f2584a
JB		 1194}
1195
4e634389
KP		 1196static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1197 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1198{
1199 if ((val & DP_PORT_EN) == 0)
1200 return false;
1201
1202 if (HAS_PCH_CPT(dev_priv->dev)) {
1203 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1204 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1205 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1206 return false;
1207 } else {
1208 if ((val & DP_PIPE_MASK) != (pipe << 30))
1209 return false;
1210 }
1211 return true;
1212}
1213
1519b995
KP		 1214static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1215 enum pipe pipe, u32 val)
1216{
dc0fa718 1217 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1218 return false;
1219
1220 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1221 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1222 return false;
1223 } else {
dc0fa718 1224 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1225 return false;
1226 }
1227 return true;
1228}
1229
1230static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe, u32 val)
1232{
1233 if ((val & LVDS_PORT_EN) == 0)
1234 return false;
1235
1236 if (HAS_PCH_CPT(dev_priv->dev)) {
1237 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1238 return false;
1239 } else {
1240 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1241 return false;
1242 }
1243 return true;
1244}
1245
1246static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, u32 val)
1248{
1249 if ((val & ADPA_DAC_ENABLE) == 0)
1250 return false;
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1253 return false;
1254 } else {
1255 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1256 return false;
1257 }
1258 return true;
1259}
1260
291906f1 1261static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1262 enum pipe pipe, int reg, u32 port_sel)
291906f1 1263{
47a05eca 1264 u32 val = I915_READ(reg);
4e634389 1265 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1266 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1267 reg, pipe_name(pipe));
de9a35ab 1268
75c5da27
DV		 1269 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1270 && (val & DP_PIPEB_SELECT),
de9a35ab 1271 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1272}
1273
1274static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, int reg)
1276{
47a05eca 1277 u32 val = I915_READ(reg);
b70ad586 1278 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1279 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1280 reg, pipe_name(pipe));
de9a35ab 1281
dc0fa718 1282 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1283 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1284 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1285}
1286
1287static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1288 enum pipe pipe)
1289{
1290 int reg;
1291 u32 val;
291906f1 1292
f0575e92
KP		 1293 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1294 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1295 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1296
1297 reg = PCH_ADPA;
1298 val = I915_READ(reg);
b70ad586 1299 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1300 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1301 pipe_name(pipe));
291906f1
JB		 1302
1303 reg = PCH_LVDS;
1304 val = I915_READ(reg);
b70ad586 1305 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1306 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1307 pipe_name(pipe));
291906f1 1308
e2debe91
PZ		 1309 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1310 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1311 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1312}
1313
63d7bbe9
JB		 1314/**
1315 * intel_enable_pll - enable a PLL
1316 * @dev_priv: i915 private structure
1317 * @pipe: pipe PLL to enable
1318 *
1319 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1320 * make sure the PLL reg is writable first though, since the panel write
1321 * protect mechanism may be enabled.
1322 *
1323 * Note! This is for pre-ILK only.
7434a255
TR		 1324 *
1325 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1326 */
1327static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1328{
1329 int reg;
1330 u32 val;
1331
58c6eaa2
DV		 1332 assert_pipe_disabled(dev_priv, pipe);
1333
63d7bbe9 1334 /* No really, not for ILK+ */
a0c4da24 1335 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1336
1337 /* PLL is protected by panel, make sure we can write it */
1338 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1339 assert_panel_unlocked(dev_priv, pipe);
1340
1341 reg = DPLL(pipe);
1342 val = I915_READ(reg);
1343 val |= DPLL_VCO_ENABLE;
1344
1345 /* We do this three times for luck */
1346 I915_WRITE(reg, val);
1347 POSTING_READ(reg);
1348 udelay(150); /* wait for warmup */
1349 I915_WRITE(reg, val);
1350 POSTING_READ(reg);
1351 udelay(150); /* wait for warmup */
1352 I915_WRITE(reg, val);
1353 POSTING_READ(reg);
1354 udelay(150); /* wait for warmup */
1355}
1356
1357/**
1358 * intel_disable_pll - disable a PLL
1359 * @dev_priv: i915 private structure
1360 * @pipe: pipe PLL to disable
1361 *
1362 * Disable the PLL for @pipe, making sure the pipe is off first.
1363 *
1364 * Note! This is for pre-ILK only.
1365 */
1366static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1367{
1368 int reg;
1369 u32 val;
1370
1371 /* Don't disable pipe A or pipe A PLLs if needed */
1372 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1373 return;
1374
1375 /* Make sure the pipe isn't still relying on us */
1376 assert_pipe_disabled(dev_priv, pipe);
1377
1378 reg = DPLL(pipe);
1379 val = I915_READ(reg);
1380 val &= ~DPLL_VCO_ENABLE;
1381 I915_WRITE(reg, val);
1382 POSTING_READ(reg);
1383}
1384
89b667f8
JB		 1385void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1386{
1387 u32 port_mask;
1388
1389 if (!port)
1390 port_mask = DPLL_PORTB_READY_MASK;
1391 else
1392 port_mask = DPLL_PORTC_READY_MASK;
1393
1394 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1395 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1396 'B' + port, I915_READ(DPLL(0)));
1397}
1398
92f2584a 1399/**
b6b4e185 1400 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1401 * @dev_priv: i915 private structure
1402 * @pipe: pipe PLL to enable
1403 *
1404 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1405 * drives the transcoder clock.
1406 */
b6b4e185 1407static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1408{
ee7b9f93 1409 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1410 struct intel_pch_pll *pll;
92f2584a
JB		 1411 int reg;
1412 u32 val;
1413
48da64a8 1414 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1415 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1416 pll = intel_crtc->pch_pll;
1417 if (pll == NULL)
1418 return;
1419
1420 if (WARN_ON(pll->refcount == 0))
1421 return;
ee7b9f93
JB		 1422
1423 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1424 pll->pll_reg, pll->active, pll->on,
1425 intel_crtc->base.base.id);
92f2584a
JB		 1426
1427 /* PCH refclock must be enabled first */
1428 assert_pch_refclk_enabled(dev_priv);
1429
cdbd2316
DV		 1430 if (pll->active++) {
1431 WARN_ON(!pll->on);
92b27b08 1432 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1433 return;
1434 }
1435
1436 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1437
1438 reg = pll->pll_reg;
92f2584a
JB		 1439 val = I915_READ(reg);
1440 val |= DPLL_VCO_ENABLE;
1441 I915_WRITE(reg, val);
1442 POSTING_READ(reg);
1443 udelay(200);
ee7b9f93
JB		 1444
1445 pll->on = true;
92f2584a
JB		 1446}
1447
ee7b9f93 1448static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1449{
ee7b9f93
JB		 1450 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1451 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1452 int reg;
ee7b9f93 1453 u32 val;
4c609cb8 1454
92f2584a
JB		 1455 /* PCH only available on ILK+ */
1456 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1457 if (pll == NULL)
1458 return;
92f2584a 1459
48da64a8
CW		 1460 if (WARN_ON(pll->refcount == 0))
1461 return;
7a419866 1462
ee7b9f93
JB		 1463 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1464 pll->pll_reg, pll->active, pll->on,
1465 intel_crtc->base.base.id);
7a419866 1466
48da64a8 1467 if (WARN_ON(pll->active == 0)) {
92b27b08 1468 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1469 return;
1470 }
1471
cdbd2316
DV		 1472 assert_pch_pll_enabled(dev_priv, pll, NULL);
1473 if (--pll->active)
7a419866 1474 return;
ee7b9f93
JB		 1475
1476 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1477
1478 /* Make sure transcoder isn't still depending on us */
ab9412ba 1479 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1480
ee7b9f93 1481 reg = pll->pll_reg;
92f2584a
JB		 1482 val = I915_READ(reg);
1483 val &= ~DPLL_VCO_ENABLE;
1484 I915_WRITE(reg, val);
1485 POSTING_READ(reg);
1486 udelay(200);
ee7b9f93
JB		 1487
1488 pll->on = false;
92f2584a
JB		 1489}
1490
b8a4f404
PZ		 1491static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1492 enum pipe pipe)
040484af 1493{
23670b32 1494 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1495 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1496 uint32_t reg, val, pipeconf_val;
040484af
JB		 1497
1498 /* PCH only available on ILK+ */
1499 BUG_ON(dev_priv->info->gen < 5);
1500
1501 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1502 assert_pch_pll_enabled(dev_priv,
1503 to_intel_crtc(crtc)->pch_pll,
1504 to_intel_crtc(crtc));
040484af
JB		 1505
1506 /* FDI must be feeding us bits for PCH ports */
1507 assert_fdi_tx_enabled(dev_priv, pipe);
1508 assert_fdi_rx_enabled(dev_priv, pipe);
1509
23670b32
DV		 1510 if (HAS_PCH_CPT(dev)) {
1511 /* Workaround: Set the timing override bit before enabling the
1512 * pch transcoder. */
1513 reg = TRANS_CHICKEN2(pipe);
1514 val = I915_READ(reg);
1515 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1516 I915_WRITE(reg, val);
59c859d6 1517 }
23670b32 1518
ab9412ba 1519 reg = PCH_TRANSCONF(pipe);
040484af 1520 val = I915_READ(reg);
5f7f726d 1521 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1522
1523 if (HAS_PCH_IBX(dev_priv->dev)) {
1524 /*
1525 * make the BPC in transcoder be consistent with
1526 * that in pipeconf reg.
1527 */
dfd07d72
DV		 1528 val &= ~PIPECONF_BPC_MASK;
1529 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1530 }
5f7f726d
PZ		 1531
1532 val &= ~TRANS_INTERLACE_MASK;
1533 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1534 if (HAS_PCH_IBX(dev_priv->dev) &&
1535 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1536 val |= TRANS_LEGACY_INTERLACED_ILK;
1537 else
1538 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1539 else
1540 val |= TRANS_PROGRESSIVE;
1541
040484af
JB		 1542 I915_WRITE(reg, val | TRANS_ENABLE);
1543 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1544 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1545}
1546
8fb033d7 1547static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1548 enum transcoder cpu_transcoder)
040484af 1549{
8fb033d7 1550 u32 val, pipeconf_val;
8fb033d7
PZ		 1551
1552 /* PCH only available on ILK+ */
1553 BUG_ON(dev_priv->info->gen < 5);
1554
8fb033d7 1555 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1556 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1557 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1558
223a6fdf
PZ		 1559 /* Workaround: set timing override bit. */
1560 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1561 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1562 I915_WRITE(_TRANSA_CHICKEN2, val);
1563
25f3ef11 1564 val = TRANS_ENABLE;
937bb610 1565 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1566
9a76b1c6
PZ		 1567 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1568 PIPECONF_INTERLACED_ILK)
a35f2679 1569 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1570 else
1571 val |= TRANS_PROGRESSIVE;
1572
ab9412ba
DV		 1573 I915_WRITE(LPT_TRANSCONF, val);
1574 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1575 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1576}
1577
b8a4f404
PZ		 1578static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1579 enum pipe pipe)
040484af 1580{
23670b32
DV		 1581 struct drm_device *dev = dev_priv->dev;
1582 uint32_t reg, val;
040484af
JB		 1583
1584 /* FDI relies on the transcoder */
1585 assert_fdi_tx_disabled(dev_priv, pipe);
1586 assert_fdi_rx_disabled(dev_priv, pipe);
1587
291906f1
JB		 1588 /* Ports must be off as well */
1589 assert_pch_ports_disabled(dev_priv, pipe);
1590
ab9412ba 1591 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1592 val = I915_READ(reg);
1593 val &= ~TRANS_ENABLE;
1594 I915_WRITE(reg, val);
1595 /* wait for PCH transcoder off, transcoder state */
1596 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1597 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1598
1599 if (!HAS_PCH_IBX(dev)) {
1600 /* Workaround: Clear the timing override chicken bit again. */
1601 reg = TRANS_CHICKEN2(pipe);
1602 val = I915_READ(reg);
1603 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1604 I915_WRITE(reg, val);
1605 }
040484af
JB		 1606}
1607
ab4d966c 1608static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1609{
8fb033d7
PZ		 1610 u32 val;
1611
ab9412ba 1612 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1613 val &= ~TRANS_ENABLE;
ab9412ba 1614 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1615 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1616 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1617 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1618
1619 /* Workaround: clear timing override bit. */
1620 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1621 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1622 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1623}
1624
b24e7179 1625/**
309cfea8 1626 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1627 * @dev_priv: i915 private structure
1628 * @pipe: pipe to enable
040484af 1629 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1630 *
1631 * Enable @pipe, making sure that various hardware specific requirements
1632 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1633 *
1634 * @pipe should be %PIPE_A or %PIPE_B.
1635 *
1636 * Will wait until the pipe is actually running (i.e. first vblank) before
1637 * returning.
1638 */
040484af
JB		 1639static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1640 bool pch_port)
b24e7179 1641{
702e7a56
PZ		 1642 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1643 pipe);
1a240d4d 1644 enum pipe pch_transcoder;
b24e7179
JB		 1645 int reg;
1646 u32 val;
1647
58c6eaa2
DV		 1648 assert_planes_disabled(dev_priv, pipe);
1649 assert_sprites_disabled(dev_priv, pipe);
1650
681e5811 1651 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1652 pch_transcoder = TRANSCODER_A;
1653 else
1654 pch_transcoder = pipe;
1655
b24e7179
JB		 1656 /*
1657 * A pipe without a PLL won't actually be able to drive bits from
1658 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1659 * need the check.
1660 */
1661 if (!HAS_PCH_SPLIT(dev_priv->dev))
1662 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1663 else {
1664 if (pch_port) {
1665 /* if driving the PCH, we need FDI enabled */
cc391bbb 1666 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1667 assert_fdi_tx_pll_enabled(dev_priv,
1668 (enum pipe) cpu_transcoder);
040484af
JB		 1669 }
1670 /* FIXME: assert CPU port conditions for SNB+ */
1671 }
b24e7179 1672
702e7a56 1673 reg = PIPECONF(cpu_transcoder);
b24e7179 1674 val = I915_READ(reg);
00d70b15
CW		 1675 if (val & PIPECONF_ENABLE)
1676 return;
1677
1678 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1679 intel_wait_for_vblank(dev_priv->dev, pipe);
1680}
1681
1682/**
309cfea8 1683 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1684 * @dev_priv: i915 private structure
1685 * @pipe: pipe to disable
1686 *
1687 * Disable @pipe, making sure that various hardware specific requirements
1688 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1689 *
1690 * @pipe should be %PIPE_A or %PIPE_B.
1691 *
1692 * Will wait until the pipe has shut down before returning.
1693 */
1694static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1695 enum pipe pipe)
1696{
702e7a56
PZ		 1697 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1698 pipe);
b24e7179
JB		 1699 int reg;
1700 u32 val;
1701
1702 /*
1703 * Make sure planes won't keep trying to pump pixels to us,
1704 * or we might hang the display.
1705 */
1706 assert_planes_disabled(dev_priv, pipe);
19332d7a 1707 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1708
1709 /* Don't disable pipe A or pipe A PLLs if needed */
1710 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1711 return;
1712
702e7a56 1713 reg = PIPECONF(cpu_transcoder);
b24e7179 1714 val = I915_READ(reg);
00d70b15
CW		 1715 if ((val & PIPECONF_ENABLE) == 0)
1716 return;
1717
1718 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1719 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1720}
1721
d74362c9
KP		 1722/*
1723 * Plane regs are double buffered, going from enabled->disabled needs a
1724 * trigger in order to latch. The display address reg provides this.
1725 */
6f1d69b0 1726void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1727 enum plane plane)
1728{
14f86147
DL		 1729 if (dev_priv->info->gen >= 4)
1730 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1731 else
1732 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1733}
1734
b24e7179
JB		 1735/**
1736 * intel_enable_plane - enable a display plane on a given pipe
1737 * @dev_priv: i915 private structure
1738 * @plane: plane to enable
1739 * @pipe: pipe being fed
1740 *
1741 * Enable @plane on @pipe, making sure that @pipe is running first.
1742 */
1743static void intel_enable_plane(struct drm_i915_private *dev_priv,
1744 enum plane plane, enum pipe pipe)
1745{
1746 int reg;
1747 u32 val;
1748
1749 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1750 assert_pipe_enabled(dev_priv, pipe);
1751
1752 reg = DSPCNTR(plane);
1753 val = I915_READ(reg);
00d70b15
CW		 1754 if (val & DISPLAY_PLANE_ENABLE)
1755 return;
1756
1757 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1758 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1759 intel_wait_for_vblank(dev_priv->dev, pipe);
1760}
1761
b24e7179
JB		 1762/**
1763 * intel_disable_plane - disable a display plane
1764 * @dev_priv: i915 private structure
1765 * @plane: plane to disable
1766 * @pipe: pipe consuming the data
1767 *
1768 * Disable @plane; should be an independent operation.
1769 */
1770static void intel_disable_plane(struct drm_i915_private *dev_priv,
1771 enum plane plane, enum pipe pipe)
1772{
1773 int reg;
1774 u32 val;
1775
1776 reg = DSPCNTR(plane);
1777 val = I915_READ(reg);
00d70b15
CW		 1778 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1779 return;
1780
1781 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1782 intel_flush_display_plane(dev_priv, plane);
1783 intel_wait_for_vblank(dev_priv->dev, pipe);
1784}
1785
693db184
CW		 1786static bool need_vtd_wa(struct drm_device *dev)
1787{
1788#ifdef CONFIG_INTEL_IOMMU
1789 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1790 return true;
1791#endif
1792 return false;
1793}
1794
127bd2ac 1795int
48b956c5 1796intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1797 struct drm_i915_gem_object *obj,
919926ae 1798 struct intel_ring_buffer *pipelined)
6b95a207 1799{
ce453d81 1800 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1801 u32 alignment;
1802 int ret;
1803
05394f39 1804 switch (obj->tiling_mode) {
6b95a207 1805 case I915_TILING_NONE:
534843da
CW		 1806 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1807 alignment = 128 * 1024;
a6c45cf0 1808 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1809 alignment = 4 * 1024;
1810 else
1811 alignment = 64 * 1024;
6b95a207
KH		 1812 break;
1813 case I915_TILING_X:
1814 /* pin() will align the object as required by fence */
1815 alignment = 0;
1816 break;
1817 case I915_TILING_Y:
8bb6e959
DV		 1818 /* Despite that we check this in framebuffer_init userspace can
1819 * screw us over and change the tiling after the fact. Only
1820 * pinned buffers can't change their tiling. */
1821 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1822 return -EINVAL;
1823 default:
1824 BUG();
1825 }
1826
693db184
CW		 1827 /* Note that the w/a also requires 64 PTE of padding following the
1828 * bo. We currently fill all unused PTE with the shadow page and so
1829 * we should always have valid PTE following the scanout preventing
1830 * the VT-d warning.
1831 */
1832 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1833 alignment = 256 * 1024;
1834
ce453d81 1835 dev_priv->mm.interruptible = false;
2da3b9b9 1836 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1837 if (ret)
ce453d81 1838 goto err_interruptible;
6b95a207
KH		 1839
1840 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1841 * fence, whereas 965+ only requires a fence if using
1842 * framebuffer compression. For simplicity, we always install
1843 * a fence as the cost is not that onerous.
1844 */
06d98131 1845 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1846 if (ret)
1847 goto err_unpin;
1690e1eb 1848
9a5a53b3 1849 i915_gem_object_pin_fence(obj);
6b95a207 1850
ce453d81 1851 dev_priv->mm.interruptible = true;
6b95a207 1852 return 0;
48b956c5
CW		 1853
1854err_unpin:
1855 i915_gem_object_unpin(obj);
ce453d81
CW		 1856err_interruptible:
1857 dev_priv->mm.interruptible = true;
48b956c5 1858 return ret;
6b95a207
KH		 1859}
1860
1690e1eb
CW		 1861void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1862{
1863 i915_gem_object_unpin_fence(obj);
1864 i915_gem_object_unpin(obj);
1865}
1866
c2c75131
DV		 1867/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1868 * is assumed to be a power-of-two. */
bc752862
CW		 1869unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1870 unsigned int tiling_mode,
1871 unsigned int cpp,
1872 unsigned int pitch)
c2c75131 1873{
bc752862
CW		 1874 if (tiling_mode != I915_TILING_NONE) {
1875 unsigned int tile_rows, tiles;
c2c75131 1876
bc752862
CW		 1877 tile_rows = *y / 8;
1878 *y %= 8;
c2c75131 1879
bc752862
CW		 1880 tiles = *x / (512/cpp);
1881 *x %= 512/cpp;
1882
1883 return tile_rows * pitch * 8 + tiles * 4096;
1884 } else {
1885 unsigned int offset;
1886
1887 offset = *y * pitch + *x * cpp;
1888 *y = 0;
1889 *x = (offset & 4095) / cpp;
1890 return offset & -4096;
1891 }
c2c75131
DV		 1892}
1893
17638cd6
JB		 1894static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1895 int x, int y)
81255565
JB		 1896{
1897 struct drm_device *dev = crtc->dev;
1898 struct drm_i915_private *dev_priv = dev->dev_private;
1899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1900 struct intel_framebuffer *intel_fb;
05394f39 1901 struct drm_i915_gem_object *obj;
81255565 1902 int plane = intel_crtc->plane;
e506a0c6 1903 unsigned long linear_offset;
81255565 1904 u32 dspcntr;
5eddb70b 1905 u32 reg;
81255565
JB		 1906
1907 switch (plane) {
1908 case 0:
1909 case 1:
1910 break;
1911 default:
84f44ce7 1912 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1913 return -EINVAL;
1914 }
1915
1916 intel_fb = to_intel_framebuffer(fb);
1917 obj = intel_fb->obj;
81255565 1918
5eddb70b
CW		 1919 reg = DSPCNTR(plane);
1920 dspcntr = I915_READ(reg);
81255565
JB		 1921 /* Mask out pixel format bits in case we change it */
1922 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1923 switch (fb->pixel_format) {
1924 case DRM_FORMAT_C8:
81255565
JB		 1925 dspcntr |= DISPPLANE_8BPP;
1926 break;
57779d06
VS		 1927 case DRM_FORMAT_XRGB1555:
1928 case DRM_FORMAT_ARGB1555:
1929 dspcntr |= DISPPLANE_BGRX555;
81255565 1930 break;
57779d06
VS		 1931 case DRM_FORMAT_RGB565:
1932 dspcntr |= DISPPLANE_BGRX565;
1933 break;
1934 case DRM_FORMAT_XRGB8888:
1935 case DRM_FORMAT_ARGB8888:
1936 dspcntr |= DISPPLANE_BGRX888;
1937 break;
1938 case DRM_FORMAT_XBGR8888:
1939 case DRM_FORMAT_ABGR8888:
1940 dspcntr |= DISPPLANE_RGBX888;
1941 break;
1942 case DRM_FORMAT_XRGB2101010:
1943 case DRM_FORMAT_ARGB2101010:
1944 dspcntr |= DISPPLANE_BGRX101010;
1945 break;
1946 case DRM_FORMAT_XBGR2101010:
1947 case DRM_FORMAT_ABGR2101010:
1948 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1949 break;
1950 default:
baba133a 1951 BUG();
81255565 1952 }
57779d06 1953
a6c45cf0 1954 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1955 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1956 dspcntr |= DISPPLANE_TILED;
1957 else
1958 dspcntr &= ~DISPPLANE_TILED;
1959 }
1960
de1aa629
VS		 1961 if (IS_G4X(dev))
1962 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1963
5eddb70b 1964 I915_WRITE(reg, dspcntr);
81255565 1965
e506a0c6 1966 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1967
c2c75131
DV		 1968 if (INTEL_INFO(dev)->gen >= 4) {
1969 intel_crtc->dspaddr_offset =
bc752862
CW		 1970 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1971 fb->bits_per_pixel / 8,
1972 fb->pitches[0]);
c2c75131
DV		 1973 linear_offset -= intel_crtc->dspaddr_offset;
1974 } else {
e506a0c6 1975 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1976 }
e506a0c6
DV		 1977
1978 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1979 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1980 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1981 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1982 I915_MODIFY_DISPBASE(DSPSURF(plane),
1983 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1984 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1985 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1986 } else
e506a0c6 1987 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 1988 POSTING_READ(reg);
81255565 1989
17638cd6
JB		 1990 return 0;
1991}
1992
1993static int ironlake_update_plane(struct drm_crtc *crtc,
1994 struct drm_framebuffer *fb, int x, int y)
1995{
1996 struct drm_device *dev = crtc->dev;
1997 struct drm_i915_private *dev_priv = dev->dev_private;
1998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1999 struct intel_framebuffer *intel_fb;
2000 struct drm_i915_gem_object *obj;
2001 int plane = intel_crtc->plane;
e506a0c6 2002 unsigned long linear_offset;
17638cd6
JB		 2003 u32 dspcntr;
2004 u32 reg;
2005
2006 switch (plane) {
2007 case 0:
2008 case 1:
27f8227b 2009 case 2:
17638cd6
JB		 2010 break;
2011 default:
84f44ce7 2012 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2013 return -EINVAL;
2014 }
2015
2016 intel_fb = to_intel_framebuffer(fb);
2017 obj = intel_fb->obj;
2018
2019 reg = DSPCNTR(plane);
2020 dspcntr = I915_READ(reg);
2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2023 switch (fb->pixel_format) {
2024 case DRM_FORMAT_C8:
17638cd6
JB		 2025 dspcntr |= DISPPLANE_8BPP;
2026 break;
57779d06
VS		 2027 case DRM_FORMAT_RGB565:
2028 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2029 break;
57779d06
VS		 2030 case DRM_FORMAT_XRGB8888:
2031 case DRM_FORMAT_ARGB8888:
2032 dspcntr |= DISPPLANE_BGRX888;
2033 break;
2034 case DRM_FORMAT_XBGR8888:
2035 case DRM_FORMAT_ABGR8888:
2036 dspcntr |= DISPPLANE_RGBX888;
2037 break;
2038 case DRM_FORMAT_XRGB2101010:
2039 case DRM_FORMAT_ARGB2101010:
2040 dspcntr |= DISPPLANE_BGRX101010;
2041 break;
2042 case DRM_FORMAT_XBGR2101010:
2043 case DRM_FORMAT_ABGR2101010:
2044 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2045 break;
2046 default:
baba133a 2047 BUG();
17638cd6
JB		 2048 }
2049
2050 if (obj->tiling_mode != I915_TILING_NONE)
2051 dspcntr |= DISPPLANE_TILED;
2052 else
2053 dspcntr &= ~DISPPLANE_TILED;
2054
2055 /* must disable */
2056 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2057
2058 I915_WRITE(reg, dspcntr);
2059
e506a0c6 2060 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2061 intel_crtc->dspaddr_offset =
bc752862
CW		 2062 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2063 fb->bits_per_pixel / 8,
2064 fb->pitches[0]);
c2c75131 2065 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2066
e506a0c6
DV		 2067 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2068 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2069 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2070 I915_MODIFY_DISPBASE(DSPSURF(plane),
2071 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2072 if (IS_HASWELL(dev)) {
2073 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2074 } else {
2075 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2076 I915_WRITE(DSPLINOFF(plane), linear_offset);
2077 }
17638cd6
JB		 2078 POSTING_READ(reg);
2079
2080 return 0;
2081}
2082
2083/* Assume fb object is pinned & idle & fenced and just update base pointers */
2084static int
2085intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2086 int x, int y, enum mode_set_atomic state)
2087{
2088 struct drm_device *dev = crtc->dev;
2089 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2090
6b8e6ed0
CW		 2091 if (dev_priv->display.disable_fbc)
2092 dev_priv->display.disable_fbc(dev);
3dec0095 2093 intel_increase_pllclock(crtc);
81255565 2094
6b8e6ed0 2095 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2096}
2097
96a02917
VS		 2098void intel_display_handle_reset(struct drm_device *dev)
2099{
2100 struct drm_i915_private *dev_priv = dev->dev_private;
2101 struct drm_crtc *crtc;
2102
2103 /*
2104 * Flips in the rings have been nuked by the reset,
2105 * so complete all pending flips so that user space
2106 * will get its events and not get stuck.
2107 *
2108 * Also update the base address of all primary
2109 * planes to the the last fb to make sure we're
2110 * showing the correct fb after a reset.
2111 *
2112 * Need to make two loops over the crtcs so that we
2113 * don't try to grab a crtc mutex before the
2114 * pending_flip_queue really got woken up.
2115 */
2116
2117 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2119 enum plane plane = intel_crtc->plane;
2120
2121 intel_prepare_page_flip(dev, plane);
2122 intel_finish_page_flip_plane(dev, plane);
2123 }
2124
2125 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2127
2128 mutex_lock(&crtc->mutex);
2129 if (intel_crtc->active)
2130 dev_priv->display.update_plane(crtc, crtc->fb,
2131 crtc->x, crtc->y);
2132 mutex_unlock(&crtc->mutex);
2133 }
2134}
2135
14667a4b
CW		 2136static int
2137intel_finish_fb(struct drm_framebuffer *old_fb)
2138{
2139 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2140 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2141 bool was_interruptible = dev_priv->mm.interruptible;
2142 int ret;
2143
14667a4b
CW		 2144 /* Big Hammer, we also need to ensure that any pending
2145 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2146 * current scanout is retired before unpinning the old
2147 * framebuffer.
2148 *
2149 * This should only fail upon a hung GPU, in which case we
2150 * can safely continue.
2151 */
2152 dev_priv->mm.interruptible = false;
2153 ret = i915_gem_object_finish_gpu(obj);
2154 dev_priv->mm.interruptible = was_interruptible;
2155
2156 return ret;
2157}
2158
198598d0
VS		 2159static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2160{
2161 struct drm_device *dev = crtc->dev;
2162 struct drm_i915_master_private *master_priv;
2163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2164
2165 if (!dev->primary->master)
2166 return;
2167
2168 master_priv = dev->primary->master->driver_priv;
2169 if (!master_priv->sarea_priv)
2170 return;
2171
2172 switch (intel_crtc->pipe) {
2173 case 0:
2174 master_priv->sarea_priv->pipeA_x = x;
2175 master_priv->sarea_priv->pipeA_y = y;
2176 break;
2177 case 1:
2178 master_priv->sarea_priv->pipeB_x = x;
2179 master_priv->sarea_priv->pipeB_y = y;
2180 break;
2181 default:
2182 break;
2183 }
2184}
2185
5c3b82e2 2186static int
3c4fdcfb 2187intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2188 struct drm_framebuffer *fb)
79e53945
JB		 2189{
2190 struct drm_device *dev = crtc->dev;
6b8e6ed0 2191 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2193 struct drm_framebuffer *old_fb;
5c3b82e2 2194 int ret;
79e53945
JB		 2195
2196 /* no fb bound */
94352cf9 2197 if (!fb) {
a5071c2f 2198 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2199 return 0;
2200 }
2201
7eb552ae 2202 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2203 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2204 plane_name(intel_crtc->plane),
2205 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2206 return -EINVAL;
79e53945
JB		 2207 }
2208
5c3b82e2 2209 mutex_lock(&dev->struct_mutex);
265db958 2210 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2211 to_intel_framebuffer(fb)->obj,
919926ae 2212 NULL);
5c3b82e2
CW		 2213 if (ret != 0) {
2214 mutex_unlock(&dev->struct_mutex);
a5071c2f 2215 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2216 return ret;
2217 }
79e53945 2218
94352cf9 2219 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2220 if (ret) {
94352cf9 2221 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2222 mutex_unlock(&dev->struct_mutex);
a5071c2f 2223 DRM_ERROR("failed to update base address\n");
4e6cfefc 2224 return ret;
79e53945 2225 }
3c4fdcfb 2226
94352cf9
DV		 2227 old_fb = crtc->fb;
2228 crtc->fb = fb;
6c4c86f5
DV		 2229 crtc->x = x;
2230 crtc->y = y;
94352cf9 2231
b7f1de28 2232 if (old_fb) {
d7697eea
DV		 2233 if (intel_crtc->active && old_fb != fb)
2234 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2235 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2236 }
652c393a 2237
6b8e6ed0 2238 intel_update_fbc(dev);
5c3b82e2 2239 mutex_unlock(&dev->struct_mutex);
79e53945 2240
198598d0 2241 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2242
2243 return 0;
79e53945
JB		 2244}
2245
5e84e1a4
ZW		 2246static void intel_fdi_normal_train(struct drm_crtc *crtc)
2247{
2248 struct drm_device *dev = crtc->dev;
2249 struct drm_i915_private *dev_priv = dev->dev_private;
2250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2251 int pipe = intel_crtc->pipe;
2252 u32 reg, temp;
2253
2254 /* enable normal train */
2255 reg = FDI_TX_CTL(pipe);
2256 temp = I915_READ(reg);
61e499bf 2257 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2258 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2259 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2260 } else {
2261 temp &= ~FDI_LINK_TRAIN_NONE;
2262 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2263 }
5e84e1a4
ZW		 2264 I915_WRITE(reg, temp);
2265
2266 reg = FDI_RX_CTL(pipe);
2267 temp = I915_READ(reg);
2268 if (HAS_PCH_CPT(dev)) {
2269 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2270 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2271 } else {
2272 temp &= ~FDI_LINK_TRAIN_NONE;
2273 temp |= FDI_LINK_TRAIN_NONE;
2274 }
2275 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2276
2277 /* wait one idle pattern time */
2278 POSTING_READ(reg);
2279 udelay(1000);
357555c0
JB		 2280
2281 /* IVB wants error correction enabled */
2282 if (IS_IVYBRIDGE(dev))
2283 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2284 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2285}
2286
1e833f40
DV		 2287static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2288{
2289 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2290}
2291
01a415fd
DV		 2292static void ivb_modeset_global_resources(struct drm_device *dev)
2293{
2294 struct drm_i915_private *dev_priv = dev->dev_private;
2295 struct intel_crtc *pipe_B_crtc =
2296 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2297 struct intel_crtc *pipe_C_crtc =
2298 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2299 uint32_t temp;
2300
1e833f40
DV		 2301 /*
2302 * When everything is off disable fdi C so that we could enable fdi B
2303 * with all lanes. Note that we don't care about enabled pipes without
2304 * an enabled pch encoder.
2305 */
2306 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2307 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2308 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2309 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2310
2311 temp = I915_READ(SOUTH_CHICKEN1);
2312 temp &= ~FDI_BC_BIFURCATION_SELECT;
2313 DRM_DEBUG_KMS("disabling fdi C rx\n");
2314 I915_WRITE(SOUTH_CHICKEN1, temp);
2315 }
2316}
2317
8db9d77b
ZW		 2318/* The FDI link training functions for ILK/Ibexpeak. */
2319static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2320{
2321 struct drm_device *dev = crtc->dev;
2322 struct drm_i915_private *dev_priv = dev->dev_private;
2323 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2324 int pipe = intel_crtc->pipe;
0fc932b8 2325 int plane = intel_crtc->plane;
5eddb70b 2326 u32 reg, temp, tries;
8db9d77b 2327
0fc932b8
JB		 2328 /* FDI needs bits from pipe & plane first */
2329 assert_pipe_enabled(dev_priv, pipe);
2330 assert_plane_enabled(dev_priv, plane);
2331
e1a44743
AJ		 2332 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2333 for train result */
5eddb70b
CW		 2334 reg = FDI_RX_IMR(pipe);
2335 temp = I915_READ(reg);
e1a44743
AJ		 2336 temp &= ~FDI_RX_SYMBOL_LOCK;
2337 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2338 I915_WRITE(reg, temp);
2339 I915_READ(reg);
e1a44743
AJ		 2340 udelay(150);
2341
8db9d77b 2342 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2343 reg = FDI_TX_CTL(pipe);
2344 temp = I915_READ(reg);
627eb5a3
DV		 2345 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2346 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2347 temp &= ~FDI_LINK_TRAIN_NONE;
2348 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2349 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2350
5eddb70b
CW		 2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
8db9d77b
ZW		 2353 temp &= ~FDI_LINK_TRAIN_NONE;
2354 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2355 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2356
2357 POSTING_READ(reg);
8db9d77b
ZW		 2358 udelay(150);
2359
5b2adf89 2360 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2361 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2362 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2363 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2364
5eddb70b 2365 reg = FDI_RX_IIR(pipe);
e1a44743 2366 for (tries = 0; tries < 5; tries++) {
5eddb70b 2367 temp = I915_READ(reg);
8db9d77b
ZW		 2368 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2369
2370 if ((temp & FDI_RX_BIT_LOCK)) {
2371 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2372 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2373 break;
2374 }
8db9d77b 2375 }
e1a44743 2376 if (tries == 5)
5eddb70b 2377 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2378
2379 /* Train 2 */
5eddb70b
CW		 2380 reg = FDI_TX_CTL(pipe);
2381 temp = I915_READ(reg);
8db9d77b
ZW		 2382 temp &= ~FDI_LINK_TRAIN_NONE;
2383 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2384 I915_WRITE(reg, temp);
8db9d77b 2385
5eddb70b
CW		 2386 reg = FDI_RX_CTL(pipe);
2387 temp = I915_READ(reg);
8db9d77b
ZW		 2388 temp &= ~FDI_LINK_TRAIN_NONE;
2389 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2390 I915_WRITE(reg, temp);
8db9d77b 2391
5eddb70b
CW		 2392 POSTING_READ(reg);
2393 udelay(150);
8db9d77b 2394
5eddb70b 2395 reg = FDI_RX_IIR(pipe);
e1a44743 2396 for (tries = 0; tries < 5; tries++) {
5eddb70b 2397 temp = I915_READ(reg);
8db9d77b
ZW		 2398 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2399
2400 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2401 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2402 DRM_DEBUG_KMS("FDI train 2 done.\n");
2403 break;
2404 }
8db9d77b 2405 }
e1a44743 2406 if (tries == 5)
5eddb70b 2407 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2408
2409 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2410
8db9d77b
ZW		 2411}
2412
0206e353 2413static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2414 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2415 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2416 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2417 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2418};
2419
2420/* The FDI link training functions for SNB/Cougarpoint. */
2421static void gen6_fdi_link_train(struct drm_crtc *crtc)
2422{
2423 struct drm_device *dev = crtc->dev;
2424 struct drm_i915_private *dev_priv = dev->dev_private;
2425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2426 int pipe = intel_crtc->pipe;
fa37d39e 2427 u32 reg, temp, i, retry;
8db9d77b 2428
e1a44743
AJ		 2429 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2430 for train result */
5eddb70b
CW		 2431 reg = FDI_RX_IMR(pipe);
2432 temp = I915_READ(reg);
e1a44743
AJ		 2433 temp &= ~FDI_RX_SYMBOL_LOCK;
2434 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2435 I915_WRITE(reg, temp);
2436
2437 POSTING_READ(reg);
e1a44743
AJ		 2438 udelay(150);
2439
8db9d77b 2440 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2441 reg = FDI_TX_CTL(pipe);
2442 temp = I915_READ(reg);
627eb5a3
DV		 2443 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2444 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2445 temp &= ~FDI_LINK_TRAIN_NONE;
2446 temp |= FDI_LINK_TRAIN_PATTERN_1;
2447 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2448 /* SNB-B */
2449 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2450 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2451
d74cf324
DV		 2452 I915_WRITE(FDI_RX_MISC(pipe),
2453 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2454
5eddb70b
CW		 2455 reg = FDI_RX_CTL(pipe);
2456 temp = I915_READ(reg);
8db9d77b
ZW		 2457 if (HAS_PCH_CPT(dev)) {
2458 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2459 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2460 } else {
2461 temp &= ~FDI_LINK_TRAIN_NONE;
2462 temp |= FDI_LINK_TRAIN_PATTERN_1;
2463 }
5eddb70b
CW		 2464 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2465
2466 POSTING_READ(reg);
8db9d77b
ZW		 2467 udelay(150);
2468
0206e353 2469 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2470 reg = FDI_TX_CTL(pipe);
2471 temp = I915_READ(reg);
8db9d77b
ZW		 2472 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2473 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2474 I915_WRITE(reg, temp);
2475
2476 POSTING_READ(reg);
8db9d77b
ZW		 2477 udelay(500);
2478
fa37d39e
SP		 2479 for (retry = 0; retry < 5; retry++) {
2480 reg = FDI_RX_IIR(pipe);
2481 temp = I915_READ(reg);
2482 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2483 if (temp & FDI_RX_BIT_LOCK) {
2484 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2485 DRM_DEBUG_KMS("FDI train 1 done.\n");
2486 break;
2487 }
2488 udelay(50);
8db9d77b 2489 }
fa37d39e
SP		 2490 if (retry < 5)
2491 break;
8db9d77b
ZW		 2492 }
2493 if (i == 4)
5eddb70b 2494 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2495
2496 /* Train 2 */
5eddb70b
CW		 2497 reg = FDI_TX_CTL(pipe);
2498 temp = I915_READ(reg);
8db9d77b
ZW		 2499 temp &= ~FDI_LINK_TRAIN_NONE;
2500 temp |= FDI_LINK_TRAIN_PATTERN_2;
2501 if (IS_GEN6(dev)) {
2502 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503 /* SNB-B */
2504 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2505 }
5eddb70b 2506 I915_WRITE(reg, temp);
8db9d77b 2507
5eddb70b
CW		 2508 reg = FDI_RX_CTL(pipe);
2509 temp = I915_READ(reg);
8db9d77b
ZW		 2510 if (HAS_PCH_CPT(dev)) {
2511 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2512 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2513 } else {
2514 temp &= ~FDI_LINK_TRAIN_NONE;
2515 temp |= FDI_LINK_TRAIN_PATTERN_2;
2516 }
5eddb70b
CW		 2517 I915_WRITE(reg, temp);
2518
2519 POSTING_READ(reg);
8db9d77b
ZW		 2520 udelay(150);
2521
0206e353 2522 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2523 reg = FDI_TX_CTL(pipe);
2524 temp = I915_READ(reg);
8db9d77b
ZW		 2525 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2526 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2527 I915_WRITE(reg, temp);
2528
2529 POSTING_READ(reg);
8db9d77b
ZW		 2530 udelay(500);
2531
fa37d39e
SP		 2532 for (retry = 0; retry < 5; retry++) {
2533 reg = FDI_RX_IIR(pipe);
2534 temp = I915_READ(reg);
2535 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2536 if (temp & FDI_RX_SYMBOL_LOCK) {
2537 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2538 DRM_DEBUG_KMS("FDI train 2 done.\n");
2539 break;
2540 }
2541 udelay(50);
8db9d77b 2542 }
fa37d39e
SP		 2543 if (retry < 5)
2544 break;
8db9d77b
ZW		 2545 }
2546 if (i == 4)
5eddb70b 2547 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2548
2549 DRM_DEBUG_KMS("FDI train done.\n");
2550}
2551
357555c0
JB		 2552/* Manual link training for Ivy Bridge A0 parts */
2553static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2554{
2555 struct drm_device *dev = crtc->dev;
2556 struct drm_i915_private *dev_priv = dev->dev_private;
2557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2558 int pipe = intel_crtc->pipe;
2559 u32 reg, temp, i;
2560
2561 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2562 for train result */
2563 reg = FDI_RX_IMR(pipe);
2564 temp = I915_READ(reg);
2565 temp &= ~FDI_RX_SYMBOL_LOCK;
2566 temp &= ~FDI_RX_BIT_LOCK;
2567 I915_WRITE(reg, temp);
2568
2569 POSTING_READ(reg);
2570 udelay(150);
2571
01a415fd
DV		 2572 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2573 I915_READ(FDI_RX_IIR(pipe)));
2574
357555c0
JB		 2575 /* enable CPU FDI TX and PCH FDI RX */
2576 reg = FDI_TX_CTL(pipe);
2577 temp = I915_READ(reg);
627eb5a3
DV		 2578 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2579 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2580 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2581 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2582 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2583 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2584 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2585 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2586
d74cf324
DV		 2587 I915_WRITE(FDI_RX_MISC(pipe),
2588 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2589
357555c0
JB		 2590 reg = FDI_RX_CTL(pipe);
2591 temp = I915_READ(reg);
2592 temp &= ~FDI_LINK_TRAIN_AUTO;
2593 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2594 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2595 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2596 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2597
2598 POSTING_READ(reg);
2599 udelay(150);
2600
0206e353 2601 for (i = 0; i < 4; i++) {
357555c0
JB		 2602 reg = FDI_TX_CTL(pipe);
2603 temp = I915_READ(reg);
2604 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2605 temp |= snb_b_fdi_train_param[i];
2606 I915_WRITE(reg, temp);
2607
2608 POSTING_READ(reg);
2609 udelay(500);
2610
2611 reg = FDI_RX_IIR(pipe);
2612 temp = I915_READ(reg);
2613 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2614
2615 if (temp & FDI_RX_BIT_LOCK ||
2616 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2617 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2618 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2619 break;
2620 }
2621 }
2622 if (i == 4)
2623 DRM_ERROR("FDI train 1 fail!\n");
2624
2625 /* Train 2 */
2626 reg = FDI_TX_CTL(pipe);
2627 temp = I915_READ(reg);
2628 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2629 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2630 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2631 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2632 I915_WRITE(reg, temp);
2633
2634 reg = FDI_RX_CTL(pipe);
2635 temp = I915_READ(reg);
2636 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2637 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2638 I915_WRITE(reg, temp);
2639
2640 POSTING_READ(reg);
2641 udelay(150);
2642
0206e353 2643 for (i = 0; i < 4; i++) {
357555c0
JB		 2644 reg = FDI_TX_CTL(pipe);
2645 temp = I915_READ(reg);
2646 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2647 temp |= snb_b_fdi_train_param[i];
2648 I915_WRITE(reg, temp);
2649
2650 POSTING_READ(reg);
2651 udelay(500);
2652
2653 reg = FDI_RX_IIR(pipe);
2654 temp = I915_READ(reg);
2655 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2656
2657 if (temp & FDI_RX_SYMBOL_LOCK) {
2658 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2659 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2660 break;
2661 }
2662 }
2663 if (i == 4)
2664 DRM_ERROR("FDI train 2 fail!\n");
2665
2666 DRM_DEBUG_KMS("FDI train done.\n");
2667}
2668
88cefb6c 2669static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2670{
88cefb6c 2671 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2672 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2673 int pipe = intel_crtc->pipe;
5eddb70b 2674 u32 reg, temp;
79e53945 2675
c64e311e 2676
c98e9dcf 2677 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2678 reg = FDI_RX_CTL(pipe);
2679 temp = I915_READ(reg);
627eb5a3
DV		 2680 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2681 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2682 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2683 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2684
2685 POSTING_READ(reg);
c98e9dcf
JB		 2686 udelay(200);
2687
2688 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2689 temp = I915_READ(reg);
2690 I915_WRITE(reg, temp | FDI_PCDCLK);
2691
2692 POSTING_READ(reg);
c98e9dcf
JB		 2693 udelay(200);
2694
20749730
PZ		 2695 /* Enable CPU FDI TX PLL, always on for Ironlake */
2696 reg = FDI_TX_CTL(pipe);
2697 temp = I915_READ(reg);
2698 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2699 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2700
20749730
PZ		 2701 POSTING_READ(reg);
2702 udelay(100);
6be4a607 2703 }
0e23b99d
JB		 2704}
2705
88cefb6c
DV		 2706static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2707{
2708 struct drm_device *dev = intel_crtc->base.dev;
2709 struct drm_i915_private *dev_priv = dev->dev_private;
2710 int pipe = intel_crtc->pipe;
2711 u32 reg, temp;
2712
2713 /* Switch from PCDclk to Rawclk */
2714 reg = FDI_RX_CTL(pipe);
2715 temp = I915_READ(reg);
2716 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2717
2718 /* Disable CPU FDI TX PLL */
2719 reg = FDI_TX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2722
2723 POSTING_READ(reg);
2724 udelay(100);
2725
2726 reg = FDI_RX_CTL(pipe);
2727 temp = I915_READ(reg);
2728 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2729
2730 /* Wait for the clocks to turn off. */
2731 POSTING_READ(reg);
2732 udelay(100);
2733}
2734
0fc932b8
JB		 2735static void ironlake_fdi_disable(struct drm_crtc *crtc)
2736{
2737 struct drm_device *dev = crtc->dev;
2738 struct drm_i915_private *dev_priv = dev->dev_private;
2739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2740 int pipe = intel_crtc->pipe;
2741 u32 reg, temp;
2742
2743 /* disable CPU FDI tx and PCH FDI rx */
2744 reg = FDI_TX_CTL(pipe);
2745 temp = I915_READ(reg);
2746 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2747 POSTING_READ(reg);
2748
2749 reg = FDI_RX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 temp &= ~(0x7 << 16);
dfd07d72 2752 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2753 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2754
2755 POSTING_READ(reg);
2756 udelay(100);
2757
2758 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2759 if (HAS_PCH_IBX(dev)) {
2760 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2761 }
0fc932b8
JB		 2762
2763 /* still set train pattern 1 */
2764 reg = FDI_TX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 temp &= ~FDI_LINK_TRAIN_NONE;
2767 temp |= FDI_LINK_TRAIN_PATTERN_1;
2768 I915_WRITE(reg, temp);
2769
2770 reg = FDI_RX_CTL(pipe);
2771 temp = I915_READ(reg);
2772 if (HAS_PCH_CPT(dev)) {
2773 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2774 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2775 } else {
2776 temp &= ~FDI_LINK_TRAIN_NONE;
2777 temp |= FDI_LINK_TRAIN_PATTERN_1;
2778 }
2779 /* BPC in FDI rx is consistent with that in PIPECONF */
2780 temp &= ~(0x07 << 16);
dfd07d72 2781 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2782 I915_WRITE(reg, temp);
2783
2784 POSTING_READ(reg);
2785 udelay(100);
2786}
2787
5bb61643
CW		 2788static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2789{
2790 struct drm_device *dev = crtc->dev;
2791 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2793 unsigned long flags;
2794 bool pending;
2795
10d83730
VS		 2796 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2797 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2798 return false;
2799
2800 spin_lock_irqsave(&dev->event_lock, flags);
2801 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2802 spin_unlock_irqrestore(&dev->event_lock, flags);
2803
2804 return pending;
2805}
2806
e6c3a2a6
CW		 2807static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2808{
0f91128d 2809 struct drm_device *dev = crtc->dev;
5bb61643 2810 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2811
2812 if (crtc->fb == NULL)
2813 return;
2814
2c10d571
DV		 2815 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2816
5bb61643
CW		 2817 wait_event(dev_priv->pending_flip_queue,
2818 !intel_crtc_has_pending_flip(crtc));
2819
0f91128d
CW		 2820 mutex_lock(&dev->struct_mutex);
2821 intel_finish_fb(crtc->fb);
2822 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2823}
2824
e615efe4
ED		 2825/* Program iCLKIP clock to the desired frequency */
2826static void lpt_program_iclkip(struct drm_crtc *crtc)
2827{
2828 struct drm_device *dev = crtc->dev;
2829 struct drm_i915_private *dev_priv = dev->dev_private;
2830 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2831 u32 temp;
2832
09153000
DV		 2833 mutex_lock(&dev_priv->dpio_lock);
2834
e615efe4
ED		 2835 /* It is necessary to ungate the pixclk gate prior to programming
2836 * the divisors, and gate it back when it is done.
2837 */
2838 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2839
2840 /* Disable SSCCTL */
2841 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2842 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2843 SBI_SSCCTL_DISABLE,
2844 SBI_ICLK);
e615efe4
ED		 2845
2846 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2847 if (crtc->mode.clock == 20000) {
2848 auxdiv = 1;
2849 divsel = 0x41;
2850 phaseinc = 0x20;
2851 } else {
2852 /* The iCLK virtual clock root frequency is in MHz,
2853 * but the crtc->mode.clock in in KHz. To get the divisors,
2854 * it is necessary to divide one by another, so we
2855 * convert the virtual clock precision to KHz here for higher
2856 * precision.
2857 */
2858 u32 iclk_virtual_root_freq = 172800 * 1000;
2859 u32 iclk_pi_range = 64;
2860 u32 desired_divisor, msb_divisor_value, pi_value;
2861
2862 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2863 msb_divisor_value = desired_divisor / iclk_pi_range;
2864 pi_value = desired_divisor % iclk_pi_range;
2865
2866 auxdiv = 0;
2867 divsel = msb_divisor_value - 2;
2868 phaseinc = pi_value;
2869 }
2870
2871 /* This should not happen with any sane values */
2872 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2873 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2874 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2875 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2876
2877 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2878 crtc->mode.clock,
2879 auxdiv,
2880 divsel,
2881 phasedir,
2882 phaseinc);
2883
2884 /* Program SSCDIVINTPHASE6 */
988d6ee8 2885 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2886 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2887 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2888 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2889 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2890 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2891 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2892 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2893
2894 /* Program SSCAUXDIV */
988d6ee8 2895 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2896 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2897 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2898 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2899
2900 /* Enable modulator and associated divider */
988d6ee8 2901 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2902 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2903 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2904
2905 /* Wait for initialization time */
2906 udelay(24);
2907
2908 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2909
2910 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2911}
2912
275f01b2
DV		 2913static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2914 enum pipe pch_transcoder)
2915{
2916 struct drm_device *dev = crtc->base.dev;
2917 struct drm_i915_private *dev_priv = dev->dev_private;
2918 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2919
2920 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2921 I915_READ(HTOTAL(cpu_transcoder)));
2922 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2923 I915_READ(HBLANK(cpu_transcoder)));
2924 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2925 I915_READ(HSYNC(cpu_transcoder)));
2926
2927 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2928 I915_READ(VTOTAL(cpu_transcoder)));
2929 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2930 I915_READ(VBLANK(cpu_transcoder)));
2931 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2932 I915_READ(VSYNC(cpu_transcoder)));
2933 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2934 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2935}
2936
f67a559d
JB		 2937/*
2938 * Enable PCH resources required for PCH ports:
2939 * - PCH PLLs
2940 * - FDI training & RX/TX
2941 * - update transcoder timings
2942 * - DP transcoding bits
2943 * - transcoder
2944 */
2945static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2946{
2947 struct drm_device *dev = crtc->dev;
2948 struct drm_i915_private *dev_priv = dev->dev_private;
2949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2950 int pipe = intel_crtc->pipe;
ee7b9f93 2951 u32 reg, temp;
2c07245f 2952
ab9412ba 2953 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2954
cd986abb
DV		 2955 /* Write the TU size bits before fdi link training, so that error
2956 * detection works. */
2957 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2958 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2959
c98e9dcf 2960 /* For PCH output, training FDI link */
674cf967 2961 dev_priv->display.fdi_link_train(crtc);
2c07245f 2962
572deb37
DV		 2963 /* XXX: pch pll's can be enabled any time before we enable the PCH
2964 * transcoder, and we actually should do this to not upset any PCH
2965 * transcoder that already use the clock when we share it.
2966 *
2967 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
2968 * unconditionally resets the pll - we need that to have the right LVDS
2969 * enable sequence. */
b6b4e185 2970 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 2971
303b81e0 2972 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2973 u32 sel;
4b645f14 2974
c98e9dcf 2975 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2976 switch (pipe) {
2977 default:
2978 case 0:
2979 temp |= TRANSA_DPLL_ENABLE;
2980 sel = TRANSA_DPLLB_SEL;
2981 break;
2982 case 1:
2983 temp |= TRANSB_DPLL_ENABLE;
2984 sel = TRANSB_DPLLB_SEL;
2985 break;
2986 case 2:
2987 temp |= TRANSC_DPLL_ENABLE;
2988 sel = TRANSC_DPLLB_SEL;
2989 break;
d64311ab 2990 }
ee7b9f93
JB		 2991 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2992 temp |= sel;
2993 else
2994 temp &= ~sel;
c98e9dcf 2995 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2996 }
5eddb70b 2997
d9b6cb56
JB		 2998 /* set transcoder timing, panel must allow it */
2999 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3000 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3001
303b81e0 3002 intel_fdi_normal_train(crtc);
5e84e1a4 3003
c98e9dcf
JB		 3004 /* For PCH DP, enable TRANS_DP_CTL */
3005 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3006 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3007 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3008 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3009 reg = TRANS_DP_CTL(pipe);
3010 temp = I915_READ(reg);
3011 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3012 TRANS_DP_SYNC_MASK |
3013 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3014 temp |= (TRANS_DP_OUTPUT_ENABLE |
3015 TRANS_DP_ENH_FRAMING);
9325c9f0 3016 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3017
3018 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3019 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3020 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3021 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3022
3023 switch (intel_trans_dp_port_sel(crtc)) {
3024 case PCH_DP_B:
5eddb70b 3025 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3026 break;
3027 case PCH_DP_C:
5eddb70b 3028 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3029 break;
3030 case PCH_DP_D:
5eddb70b 3031 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3032 break;
3033 default:
e95d41e1 3034 BUG();
32f9d658 3035 }
2c07245f 3036
5eddb70b 3037 I915_WRITE(reg, temp);
6be4a607 3038 }
b52eb4dc 3039
b8a4f404 3040 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3041}
3042
1507e5bd
PZ		 3043static void lpt_pch_enable(struct drm_crtc *crtc)
3044{
3045 struct drm_device *dev = crtc->dev;
3046 struct drm_i915_private *dev_priv = dev->dev_private;
3047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3048 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3049
ab9412ba 3050 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3051
8c52b5e8 3052 lpt_program_iclkip(crtc);
1507e5bd 3053
0540e488 3054 /* Set transcoder timing. */
275f01b2 3055 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3056
937bb610 3057 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3058}
3059
ee7b9f93
JB		 3060static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3061{
3062 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3063
3064 if (pll == NULL)
3065 return;
3066
3067 if (pll->refcount == 0) {
3068 WARN(1, "bad PCH PLL refcount\n");
3069 return;
3070 }
3071
3072 --pll->refcount;
3073 intel_crtc->pch_pll = NULL;
3074}
3075
3076static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3077{
3078 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3079 struct intel_pch_pll *pll;
3080 int i;
3081
3082 pll = intel_crtc->pch_pll;
3083 if (pll) {
cdbd2316 3084 DRM_DEBUG_KMS("CRTC:%d dropping existing PCH PLL %x\n",
ee7b9f93 3085 intel_crtc->base.base.id, pll->pll_reg);
cdbd2316 3086 intel_put_pch_pll(intel_crtc);
ee7b9f93
JB		 3087 }
3088
98b6bd99
DV		 3089 if (HAS_PCH_IBX(dev_priv->dev)) {
3090 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3091 i = intel_crtc->pipe;
3092 pll = &dev_priv->pch_plls[i];
3093
3094 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3095 intel_crtc->base.base.id, pll->pll_reg);
3096
3097 goto found;
3098 }
3099
ee7b9f93
JB		 3100 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3101 pll = &dev_priv->pch_plls[i];
3102
3103 /* Only want to check enabled timings first */
3104 if (pll->refcount == 0)
3105 continue;
3106
3107 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3108 fp == I915_READ(pll->fp0_reg)) {
3109 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3110 intel_crtc->base.base.id,
3111 pll->pll_reg, pll->refcount, pll->active);
3112
3113 goto found;
3114 }
3115 }
3116
3117 /* Ok no matching timings, maybe there's a free one? */
3118 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3119 pll = &dev_priv->pch_plls[i];
3120 if (pll->refcount == 0) {
3121 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3122 intel_crtc->base.base.id, pll->pll_reg);
3123 goto found;
3124 }
3125 }
3126
3127 return NULL;
3128
3129found:
3130 intel_crtc->pch_pll = pll;
84f44ce7 3131 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
cdbd2316
DV		 3132 if (pll->active == 0) {
3133 DRM_DEBUG_DRIVER("setting up pll %d\n", i);
3134 WARN_ON(pll->on);
3135 assert_pch_pll_disabled(dev_priv, pll, NULL);
ee7b9f93 3136
cdbd2316
DV		 3137 /* Wait for the clocks to stabilize before rewriting the regs */
3138 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3139 POSTING_READ(pll->pll_reg);
3140 udelay(150);
3141
3142 I915_WRITE(pll->fp0_reg, fp);
3143 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3144 }
3145 pll->refcount++;
e04c7350 3146
ee7b9f93
JB		 3147 return pll;
3148}
3149
a1520318 3150static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3151{
3152 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3153 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3154 u32 temp;
3155
3156 temp = I915_READ(dslreg);
3157 udelay(500);
3158 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3159 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3160 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3161 }
3162}
3163
b074cec8
JB		 3164static void ironlake_pfit_enable(struct intel_crtc *crtc)
3165{
3166 struct drm_device *dev = crtc->base.dev;
3167 struct drm_i915_private *dev_priv = dev->dev_private;
3168 int pipe = crtc->pipe;
3169
0ef37f3f 3170 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3171 /* Force use of hard-coded filter coefficients
3172 * as some pre-programmed values are broken,
3173 * e.g. x201.
3174 */
3175 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3176 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3177 PF_PIPE_SEL_IVB(pipe));
3178 else
3179 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3180 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3181 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3182 }
3183}
3184
bb53d4ae
VS		 3185static void intel_enable_planes(struct drm_crtc *crtc)
3186{
3187 struct drm_device *dev = crtc->dev;
3188 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3189 struct intel_plane *intel_plane;
3190
3191 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3192 if (intel_plane->pipe == pipe)
3193 intel_plane_restore(&intel_plane->base);
3194}
3195
3196static void intel_disable_planes(struct drm_crtc *crtc)
3197{
3198 struct drm_device *dev = crtc->dev;
3199 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3200 struct intel_plane *intel_plane;
3201
3202 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3203 if (intel_plane->pipe == pipe)
3204 intel_plane_disable(&intel_plane->base);
3205}
3206
f67a559d
JB		 3207static void ironlake_crtc_enable(struct drm_crtc *crtc)
3208{
3209 struct drm_device *dev = crtc->dev;
3210 struct drm_i915_private *dev_priv = dev->dev_private;
3211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3212 struct intel_encoder *encoder;
f67a559d
JB		 3213 int pipe = intel_crtc->pipe;
3214 int plane = intel_crtc->plane;
3215 u32 temp;
f67a559d 3216
08a48469
DV		 3217 WARN_ON(!crtc->enabled);
3218
f67a559d
JB		 3219 if (intel_crtc->active)
3220 return;
3221
3222 intel_crtc->active = true;
8664281b
PZ		 3223
3224 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3225 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3226
f67a559d
JB		 3227 intel_update_watermarks(dev);
3228
3229 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3230 temp = I915_READ(PCH_LVDS);
3231 if ((temp & LVDS_PORT_EN) == 0)
3232 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3233 }
3234
f67a559d 3235
5bfe2ac0 3236 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3237 /* Note: FDI PLL enabling _must_ be done before we enable the
3238 * cpu pipes, hence this is separate from all the other fdi/pch
3239 * enabling. */
88cefb6c 3240 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3241 } else {
3242 assert_fdi_tx_disabled(dev_priv, pipe);
3243 assert_fdi_rx_disabled(dev_priv, pipe);
3244 }
f67a559d 3245
bf49ec8c
DV		 3246 for_each_encoder_on_crtc(dev, crtc, encoder)
3247 if (encoder->pre_enable)
3248 encoder->pre_enable(encoder);
f67a559d
JB		 3249
3250 /* Enable panel fitting for LVDS */
b074cec8 3251 ironlake_pfit_enable(intel_crtc);
f67a559d 3252
9c54c0dd
JB		 3253 /*
3254 * On ILK+ LUT must be loaded before the pipe is running but with
3255 * clocks enabled
3256 */
3257 intel_crtc_load_lut(crtc);
3258
5bfe2ac0
DV		 3259 intel_enable_pipe(dev_priv, pipe,
3260 intel_crtc->config.has_pch_encoder);
f67a559d 3261 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3262 intel_enable_planes(crtc);
5c38d48c 3263 intel_crtc_update_cursor(crtc, true);
f67a559d 3264
5bfe2ac0 3265 if (intel_crtc->config.has_pch_encoder)
f67a559d 3266 ironlake_pch_enable(crtc);
c98e9dcf 3267
d1ebd816 3268 mutex_lock(&dev->struct_mutex);
bed4a673 3269 intel_update_fbc(dev);
d1ebd816
BW		 3270 mutex_unlock(&dev->struct_mutex);
3271
fa5c73b1
DV		 3272 for_each_encoder_on_crtc(dev, crtc, encoder)
3273 encoder->enable(encoder);
61b77ddd
DV		 3274
3275 if (HAS_PCH_CPT(dev))
a1520318 3276 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3277
3278 /*
3279 * There seems to be a race in PCH platform hw (at least on some
3280 * outputs) where an enabled pipe still completes any pageflip right
3281 * away (as if the pipe is off) instead of waiting for vblank. As soon
3282 * as the first vblank happend, everything works as expected. Hence just
3283 * wait for one vblank before returning to avoid strange things
3284 * happening.
3285 */
3286 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3287}
3288
42db64ef
PZ		 3289/* IPS only exists on ULT machines and is tied to pipe A. */
3290static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3291{
3292 return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3293}
3294
3295static void hsw_enable_ips(struct intel_crtc *crtc)
3296{
3297 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3298
3299 if (!crtc->config.ips_enabled)
3300 return;
3301
3302 /* We can only enable IPS after we enable a plane and wait for a vblank.
3303 * We guarantee that the plane is enabled by calling intel_enable_ips
3304 * only after intel_enable_plane. And intel_enable_plane already waits
3305 * for a vblank, so all we need to do here is to enable the IPS bit. */
3306 assert_plane_enabled(dev_priv, crtc->plane);
3307 I915_WRITE(IPS_CTL, IPS_ENABLE);
3308}
3309
3310static void hsw_disable_ips(struct intel_crtc *crtc)
3311{
3312 struct drm_device *dev = crtc->base.dev;
3313 struct drm_i915_private *dev_priv = dev->dev_private;
3314
3315 if (!crtc->config.ips_enabled)
3316 return;
3317
3318 assert_plane_enabled(dev_priv, crtc->plane);
3319 I915_WRITE(IPS_CTL, 0);
3320
3321 /* We need to wait for a vblank before we can disable the plane. */
3322 intel_wait_for_vblank(dev, crtc->pipe);
3323}
3324
4f771f10
PZ		 3325static void haswell_crtc_enable(struct drm_crtc *crtc)
3326{
3327 struct drm_device *dev = crtc->dev;
3328 struct drm_i915_private *dev_priv = dev->dev_private;
3329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3330 struct intel_encoder *encoder;
3331 int pipe = intel_crtc->pipe;
3332 int plane = intel_crtc->plane;
4f771f10
PZ		 3333
3334 WARN_ON(!crtc->enabled);
3335
3336 if (intel_crtc->active)
3337 return;
3338
3339 intel_crtc->active = true;
8664281b
PZ		 3340
3341 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3342 if (intel_crtc->config.has_pch_encoder)
3343 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3344
4f771f10
PZ		 3345 intel_update_watermarks(dev);
3346
5bfe2ac0 3347 if (intel_crtc->config.has_pch_encoder)
04945641 3348 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3349
3350 for_each_encoder_on_crtc(dev, crtc, encoder)
3351 if (encoder->pre_enable)
3352 encoder->pre_enable(encoder);
3353
1f544388 3354 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3355
1f544388 3356 /* Enable panel fitting for eDP */
b074cec8 3357 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3358
3359 /*
3360 * On ILK+ LUT must be loaded before the pipe is running but with
3361 * clocks enabled
3362 */
3363 intel_crtc_load_lut(crtc);
3364
1f544388 3365 intel_ddi_set_pipe_settings(crtc);
8228c251 3366 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3367
5bfe2ac0
DV		 3368 intel_enable_pipe(dev_priv, pipe,
3369 intel_crtc->config.has_pch_encoder);
4f771f10 3370 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3371 intel_enable_planes(crtc);
5c38d48c 3372 intel_crtc_update_cursor(crtc, true);
4f771f10 3373
42db64ef
PZ		 3374 hsw_enable_ips(intel_crtc);
3375
5bfe2ac0 3376 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3377 lpt_pch_enable(crtc);
4f771f10
PZ		 3378
3379 mutex_lock(&dev->struct_mutex);
3380 intel_update_fbc(dev);
3381 mutex_unlock(&dev->struct_mutex);
3382
4f771f10
PZ		 3383 for_each_encoder_on_crtc(dev, crtc, encoder)
3384 encoder->enable(encoder);
3385
4f771f10
PZ		 3386 /*
3387 * There seems to be a race in PCH platform hw (at least on some
3388 * outputs) where an enabled pipe still completes any pageflip right
3389 * away (as if the pipe is off) instead of waiting for vblank. As soon
3390 * as the first vblank happend, everything works as expected. Hence just
3391 * wait for one vblank before returning to avoid strange things
3392 * happening.
3393 */
3394 intel_wait_for_vblank(dev, intel_crtc->pipe);
3395}
3396
3f8dce3a
DV		 3397static void ironlake_pfit_disable(struct intel_crtc *crtc)
3398{
3399 struct drm_device *dev = crtc->base.dev;
3400 struct drm_i915_private *dev_priv = dev->dev_private;
3401 int pipe = crtc->pipe;
3402
3403 /* To avoid upsetting the power well on haswell only disable the pfit if
3404 * it's in use. The hw state code will make sure we get this right. */
3405 if (crtc->config.pch_pfit.size) {
3406 I915_WRITE(PF_CTL(pipe), 0);
3407 I915_WRITE(PF_WIN_POS(pipe), 0);
3408 I915_WRITE(PF_WIN_SZ(pipe), 0);
3409 }
3410}
3411
6be4a607
JB		 3412static void ironlake_crtc_disable(struct drm_crtc *crtc)
3413{
3414 struct drm_device *dev = crtc->dev;
3415 struct drm_i915_private *dev_priv = dev->dev_private;
3416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3417 struct intel_encoder *encoder;
6be4a607
JB		 3418 int pipe = intel_crtc->pipe;
3419 int plane = intel_crtc->plane;
5eddb70b 3420 u32 reg, temp;
b52eb4dc 3421
ef9c3aee 3422
f7abfe8b
CW		 3423 if (!intel_crtc->active)
3424 return;
3425
ea9d758d
DV		 3426 for_each_encoder_on_crtc(dev, crtc, encoder)
3427 encoder->disable(encoder);
3428
e6c3a2a6 3429 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3430 drm_vblank_off(dev, pipe);
913d8d11 3431
973d04f9
CW		 3432 if (dev_priv->cfb_plane == plane)
3433 intel_disable_fbc(dev);
2c07245f 3434
0d5b8c61 3435 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3436 intel_disable_planes(crtc);
0d5b8c61
VS		 3437 intel_disable_plane(dev_priv, plane, pipe);
3438
d925c59a
DV		 3439 if (intel_crtc->config.has_pch_encoder)
3440 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3441
b24e7179 3442 intel_disable_pipe(dev_priv, pipe);
32f9d658 3443
3f8dce3a 3444 ironlake_pfit_disable(intel_crtc);
2c07245f 3445
bf49ec8c
DV		 3446 for_each_encoder_on_crtc(dev, crtc, encoder)
3447 if (encoder->post_disable)
3448 encoder->post_disable(encoder);
2c07245f 3449
d925c59a
DV		 3450 if (intel_crtc->config.has_pch_encoder) {
3451 ironlake_fdi_disable(crtc);
249c0e64 3452
d925c59a
DV		 3453 ironlake_disable_pch_transcoder(dev_priv, pipe);
3454 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3455
d925c59a
DV		 3456 if (HAS_PCH_CPT(dev)) {
3457 /* disable TRANS_DP_CTL */
3458 reg = TRANS_DP_CTL(pipe);
3459 temp = I915_READ(reg);
3460 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3461 TRANS_DP_PORT_SEL_MASK);
3462 temp |= TRANS_DP_PORT_SEL_NONE;
3463 I915_WRITE(reg, temp);
3464
3465 /* disable DPLL_SEL */
3466 temp = I915_READ(PCH_DPLL_SEL);
3467 switch (pipe) {
3468 case 0:
3469 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3470 break;
3471 case 1:
3472 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3473 break;
3474 case 2:
3475 /* C shares PLL A or B */
3476 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3477 break;
3478 default:
3479 BUG(); /* wtf */
3480 }
3481 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3482 }
e3421a18 3483
d925c59a
DV		 3484 /* disable PCH DPLL */
3485 intel_disable_pch_pll(intel_crtc);
8db9d77b 3486
d925c59a
DV		 3487 ironlake_fdi_pll_disable(intel_crtc);
3488 }
6b383a7f 3489
f7abfe8b 3490 intel_crtc->active = false;
6b383a7f 3491 intel_update_watermarks(dev);
d1ebd816
BW		 3492
3493 mutex_lock(&dev->struct_mutex);
6b383a7f 3494 intel_update_fbc(dev);
d1ebd816 3495 mutex_unlock(&dev->struct_mutex);
6be4a607 3496}
1b3c7a47 3497
4f771f10 3498static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3499{
4f771f10
PZ		 3500 struct drm_device *dev = crtc->dev;
3501 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3503 struct intel_encoder *encoder;
3504 int pipe = intel_crtc->pipe;
3505 int plane = intel_crtc->plane;
3b117c8f 3506 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3507
4f771f10
PZ		 3508 if (!intel_crtc->active)
3509 return;
3510
3511 for_each_encoder_on_crtc(dev, crtc, encoder)
3512 encoder->disable(encoder);
3513
3514 intel_crtc_wait_for_pending_flips(crtc);
3515 drm_vblank_off(dev, pipe);
4f771f10 3516
891348b2 3517 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3518 if (dev_priv->cfb_plane == plane)
3519 intel_disable_fbc(dev);
3520
42db64ef
PZ		 3521 hsw_disable_ips(intel_crtc);
3522
0d5b8c61 3523 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3524 intel_disable_planes(crtc);
891348b2
RV		 3525 intel_disable_plane(dev_priv, plane, pipe);
3526
8664281b
PZ		 3527 if (intel_crtc->config.has_pch_encoder)
3528 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3529 intel_disable_pipe(dev_priv, pipe);
3530
ad80a810 3531 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3532
3f8dce3a 3533 ironlake_pfit_disable(intel_crtc);
4f771f10 3534
1f544388 3535 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3536
3537 for_each_encoder_on_crtc(dev, crtc, encoder)
3538 if (encoder->post_disable)
3539 encoder->post_disable(encoder);
3540
88adfff1 3541 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3542 lpt_disable_pch_transcoder(dev_priv);
8664281b 3543 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3544 intel_ddi_fdi_disable(crtc);
83616634 3545 }
4f771f10
PZ		 3546
3547 intel_crtc->active = false;
3548 intel_update_watermarks(dev);
3549
3550 mutex_lock(&dev->struct_mutex);
3551 intel_update_fbc(dev);
3552 mutex_unlock(&dev->struct_mutex);
3553}
3554
ee7b9f93
JB		 3555static void ironlake_crtc_off(struct drm_crtc *crtc)
3556{
3557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3558 intel_put_pch_pll(intel_crtc);
3559}
3560
6441ab5f
PZ		 3561static void haswell_crtc_off(struct drm_crtc *crtc)
3562{
3563 intel_ddi_put_crtc_pll(crtc);
3564}
3565
02e792fb
DV		 3566static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3567{
02e792fb 3568 if (!enable && intel_crtc->overlay) {
23f09ce3 3569 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3570 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3571
23f09ce3 3572 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3573 dev_priv->mm.interruptible = false;
3574 (void) intel_overlay_switch_off(intel_crtc->overlay);
3575 dev_priv->mm.interruptible = true;
23f09ce3 3576 mutex_unlock(&dev->struct_mutex);
02e792fb 3577 }
02e792fb 3578
5dcdbcb0
CW		 3579 /* Let userspace switch the overlay on again. In most cases userspace
3580 * has to recompute where to put it anyway.
3581 */
02e792fb
DV		 3582}
3583
61bc95c1
EE		 3584/**
3585 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3586 * cursor plane briefly if not already running after enabling the display
3587 * plane.
3588 * This workaround avoids occasional blank screens when self refresh is
3589 * enabled.
3590 */
3591static void
3592g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3593{
3594 u32 cntl = I915_READ(CURCNTR(pipe));
3595
3596 if ((cntl & CURSOR_MODE) == 0) {
3597 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3598
3599 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3600 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3601 intel_wait_for_vblank(dev_priv->dev, pipe);
3602 I915_WRITE(CURCNTR(pipe), cntl);
3603 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3604 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3605 }
3606}
3607
2dd24552
JB		 3608static void i9xx_pfit_enable(struct intel_crtc *crtc)
3609{
3610 struct drm_device *dev = crtc->base.dev;
3611 struct drm_i915_private *dev_priv = dev->dev_private;
3612 struct intel_crtc_config *pipe_config = &crtc->config;
3613
328d8e82 3614 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3615 return;
3616
2dd24552 3617 /*
c0b03411
DV		 3618 * The panel fitter should only be adjusted whilst the pipe is disabled,
3619 * according to register description and PRM.
2dd24552 3620 */
c0b03411
DV		 3621 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3622 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3623
b074cec8
JB		 3624 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3625 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3626
3627 /* Border color in case we don't scale up to the full screen. Black by
3628 * default, change to something else for debugging. */
3629 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3630}
3631
89b667f8
JB		 3632static void valleyview_crtc_enable(struct drm_crtc *crtc)
3633{
3634 struct drm_device *dev = crtc->dev;
3635 struct drm_i915_private *dev_priv = dev->dev_private;
3636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3637 struct intel_encoder *encoder;
3638 int pipe = intel_crtc->pipe;
3639 int plane = intel_crtc->plane;
3640
3641 WARN_ON(!crtc->enabled);
3642
3643 if (intel_crtc->active)
3644 return;
3645
3646 intel_crtc->active = true;
3647 intel_update_watermarks(dev);
3648
3649 mutex_lock(&dev_priv->dpio_lock);
3650
3651 for_each_encoder_on_crtc(dev, crtc, encoder)
3652 if (encoder->pre_pll_enable)
3653 encoder->pre_pll_enable(encoder);
3654
3655 intel_enable_pll(dev_priv, pipe);
3656
3657 for_each_encoder_on_crtc(dev, crtc, encoder)
3658 if (encoder->pre_enable)
3659 encoder->pre_enable(encoder);
3660
3661 /* VLV wants encoder enabling _before_ the pipe is up. */
3662 for_each_encoder_on_crtc(dev, crtc, encoder)
3663 encoder->enable(encoder);
3664
2dd24552
JB		 3665 /* Enable panel fitting for eDP */
3666 i9xx_pfit_enable(intel_crtc);
3667
63cbb074
VS		 3668 intel_crtc_load_lut(crtc);
3669
89b667f8
JB		 3670 intel_enable_pipe(dev_priv, pipe, false);
3671 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3672 intel_enable_planes(crtc);
5c38d48c 3673 intel_crtc_update_cursor(crtc, true);
89b667f8 3674
f440eb13
VS		 3675 intel_update_fbc(dev);
3676
89b667f8
JB		 3677 mutex_unlock(&dev_priv->dpio_lock);
3678}
3679
0b8765c6 3680static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3681{
3682 struct drm_device *dev = crtc->dev;
79e53945
JB		 3683 struct drm_i915_private *dev_priv = dev->dev_private;
3684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3685 struct intel_encoder *encoder;
79e53945 3686 int pipe = intel_crtc->pipe;
80824003 3687 int plane = intel_crtc->plane;
79e53945 3688
08a48469
DV		 3689 WARN_ON(!crtc->enabled);
3690
f7abfe8b
CW		 3691 if (intel_crtc->active)
3692 return;
3693
3694 intel_crtc->active = true;
6b383a7f
CW		 3695 intel_update_watermarks(dev);
3696
63d7bbe9 3697 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3698
3699 for_each_encoder_on_crtc(dev, crtc, encoder)
3700 if (encoder->pre_enable)
3701 encoder->pre_enable(encoder);
3702
2dd24552
JB		 3703 /* Enable panel fitting for LVDS */
3704 i9xx_pfit_enable(intel_crtc);
3705
63cbb074
VS		 3706 intel_crtc_load_lut(crtc);
3707
040484af 3708 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3709 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3710 intel_enable_planes(crtc);
22e407d7 3711 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3712 if (IS_G4X(dev))
3713 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3714 intel_crtc_update_cursor(crtc, true);
79e53945 3715
0b8765c6
JB		 3716 /* Give the overlay scaler a chance to enable if it's on this pipe */
3717 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3718
f440eb13
VS		 3719 intel_update_fbc(dev);
3720
fa5c73b1
DV		 3721 for_each_encoder_on_crtc(dev, crtc, encoder)
3722 encoder->enable(encoder);
0b8765c6 3723}
79e53945 3724
87476d63
DV		 3725static void i9xx_pfit_disable(struct intel_crtc *crtc)
3726{
3727 struct drm_device *dev = crtc->base.dev;
3728 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3729
328d8e82
DV		 3730 if (!crtc->config.gmch_pfit.control)
3731 return;
87476d63 3732
328d8e82 3733 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3734
328d8e82
DV		 3735 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3736 I915_READ(PFIT_CONTROL));
3737 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3738}
3739
0b8765c6
JB		 3740static void i9xx_crtc_disable(struct drm_crtc *crtc)
3741{
3742 struct drm_device *dev = crtc->dev;
3743 struct drm_i915_private *dev_priv = dev->dev_private;
3744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3745 struct intel_encoder *encoder;
0b8765c6
JB		 3746 int pipe = intel_crtc->pipe;
3747 int plane = intel_crtc->plane;
ef9c3aee 3748
f7abfe8b
CW		 3749 if (!intel_crtc->active)
3750 return;
3751
ea9d758d
DV		 3752 for_each_encoder_on_crtc(dev, crtc, encoder)
3753 encoder->disable(encoder);
3754
0b8765c6 3755 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3756 intel_crtc_wait_for_pending_flips(crtc);
3757 drm_vblank_off(dev, pipe);
0b8765c6 3758
973d04f9
CW		 3759 if (dev_priv->cfb_plane == plane)
3760 intel_disable_fbc(dev);
79e53945 3761
0d5b8c61
VS		 3762 intel_crtc_dpms_overlay(intel_crtc, false);
3763 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3764 intel_disable_planes(crtc);
b24e7179 3765 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3766
b24e7179 3767 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3768
87476d63 3769 i9xx_pfit_disable(intel_crtc);
24a1f16d 3770
89b667f8
JB		 3771 for_each_encoder_on_crtc(dev, crtc, encoder)
3772 if (encoder->post_disable)
3773 encoder->post_disable(encoder);
3774
63d7bbe9 3775 intel_disable_pll(dev_priv, pipe);
0b8765c6 3776
f7abfe8b 3777 intel_crtc->active = false;
6b383a7f
CW		 3778 intel_update_fbc(dev);
3779 intel_update_watermarks(dev);
0b8765c6
JB		 3780}
3781
ee7b9f93
JB		 3782static void i9xx_crtc_off(struct drm_crtc *crtc)
3783{
3784}
3785
976f8a20
DV		 3786static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3787 bool enabled)
2c07245f
ZW		 3788{
3789 struct drm_device *dev = crtc->dev;
3790 struct drm_i915_master_private *master_priv;
3791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3792 int pipe = intel_crtc->pipe;
79e53945
JB		 3793
3794 if (!dev->primary->master)
3795 return;
3796
3797 master_priv = dev->primary->master->driver_priv;
3798 if (!master_priv->sarea_priv)
3799 return;
3800
79e53945
JB		 3801 switch (pipe) {
3802 case 0:
3803 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3804 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3805 break;
3806 case 1:
3807 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3808 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3809 break;
3810 default:
9db4a9c7 3811 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3812 break;
3813 }
79e53945
JB		 3814}
3815
976f8a20
DV		 3816/**
3817 * Sets the power management mode of the pipe and plane.
3818 */
3819void intel_crtc_update_dpms(struct drm_crtc *crtc)
3820{
3821 struct drm_device *dev = crtc->dev;
3822 struct drm_i915_private *dev_priv = dev->dev_private;
3823 struct intel_encoder *intel_encoder;
3824 bool enable = false;
3825
3826 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3827 enable |= intel_encoder->connectors_active;
3828
3829 if (enable)
3830 dev_priv->display.crtc_enable(crtc);
3831 else
3832 dev_priv->display.crtc_disable(crtc);
3833
3834 intel_crtc_update_sarea(crtc, enable);
3835}
3836
cdd59983
CW		 3837static void intel_crtc_disable(struct drm_crtc *crtc)
3838{
cdd59983 3839 struct drm_device *dev = crtc->dev;
976f8a20 3840 struct drm_connector *connector;
ee7b9f93 3841 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3843
976f8a20
DV		 3844 /* crtc should still be enabled when we disable it. */
3845 WARN_ON(!crtc->enabled);
3846
3847 dev_priv->display.crtc_disable(crtc);
c77bf565 3848 intel_crtc->eld_vld = false;
976f8a20 3849 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3850 dev_priv->display.off(crtc);
3851
931872fc
CW		 3852 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3853 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3854
3855 if (crtc->fb) {
3856 mutex_lock(&dev->struct_mutex);
1690e1eb 3857 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3858 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3859 crtc->fb = NULL;
3860 }
3861
3862 /* Update computed state. */
3863 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3864 if (!connector->encoder || !connector->encoder->crtc)
3865 continue;
3866
3867 if (connector->encoder->crtc != crtc)
3868 continue;
3869
3870 connector->dpms = DRM_MODE_DPMS_OFF;
3871 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3872 }
3873}
3874
a261b246 3875void intel_modeset_disable(struct drm_device *dev)
79e53945 3876{
a261b246
DV		 3877 struct drm_crtc *crtc;
3878
3879 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3880 if (crtc->enabled)
3881 intel_crtc_disable(crtc);
3882 }
79e53945
JB		 3883}
3884
ea5b213a 3885void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3886{
4ef69c7a 3887 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3888
ea5b213a
CW		 3889 drm_encoder_cleanup(encoder);
3890 kfree(intel_encoder);
7e7d76c3
JB		 3891}
3892
5ab432ef
DV		 3893/* Simple dpms helper for encodres with just one connector, no cloning and only
3894 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3895 * state of the entire output pipe. */
3896void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3897{
5ab432ef
DV		 3898 if (mode == DRM_MODE_DPMS_ON) {
3899 encoder->connectors_active = true;
3900
b2cabb0e 3901 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3902 } else {
3903 encoder->connectors_active = false;
3904
b2cabb0e 3905 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3906 }
79e53945
JB		 3907}
3908
0a91ca29
DV		 3909/* Cross check the actual hw state with our own modeset state tracking (and it's
3910 * internal consistency). */
b980514c 3911static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3912{
0a91ca29
DV		 3913 if (connector->get_hw_state(connector)) {
3914 struct intel_encoder *encoder = connector->encoder;
3915 struct drm_crtc *crtc;
3916 bool encoder_enabled;
3917 enum pipe pipe;
3918
3919 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3920 connector->base.base.id,
3921 drm_get_connector_name(&connector->base));
3922
3923 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3924 "wrong connector dpms state\n");
3925 WARN(connector->base.encoder != &encoder->base,
3926 "active connector not linked to encoder\n");
3927 WARN(!encoder->connectors_active,
3928 "encoder->connectors_active not set\n");
3929
3930 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3931 WARN(!encoder_enabled, "encoder not enabled\n");
3932 if (WARN_ON(!encoder->base.crtc))
3933 return;
3934
3935 crtc = encoder->base.crtc;
3936
3937 WARN(!crtc->enabled, "crtc not enabled\n");
3938 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3939 WARN(pipe != to_intel_crtc(crtc)->pipe,
3940 "encoder active on the wrong pipe\n");
3941 }
79e53945
JB		 3942}
3943
5ab432ef
DV		 3944/* Even simpler default implementation, if there's really no special case to
3945 * consider. */
3946void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3947{
5ab432ef 3948 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3949
5ab432ef
DV		 3950 /* All the simple cases only support two dpms states. */
3951 if (mode != DRM_MODE_DPMS_ON)
3952 mode = DRM_MODE_DPMS_OFF;
d4270e57 3953
5ab432ef
DV		 3954 if (mode == connector->dpms)
3955 return;
3956
3957 connector->dpms = mode;
3958
3959 /* Only need to change hw state when actually enabled */
3960 if (encoder->base.crtc)
3961 intel_encoder_dpms(encoder, mode);
3962 else
8af6cf88 3963 WARN_ON(encoder->connectors_active != false);
0a91ca29 3964
b980514c 3965 intel_modeset_check_state(connector->dev);
79e53945
JB		 3966}
3967
f0947c37
DV		 3968/* Simple connector->get_hw_state implementation for encoders that support only
3969 * one connector and no cloning and hence the encoder state determines the state
3970 * of the connector. */
3971bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3972{
24929352 3973 enum pipe pipe = 0;
f0947c37 3974 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3975
f0947c37 3976 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3977}
3978
1857e1da
DV		 3979static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3980 struct intel_crtc_config *pipe_config)
3981{
3982 struct drm_i915_private *dev_priv = dev->dev_private;
3983 struct intel_crtc *pipe_B_crtc =
3984 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3985
3986 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3987 pipe_name(pipe), pipe_config->fdi_lanes);
3988 if (pipe_config->fdi_lanes > 4) {
3989 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3990 pipe_name(pipe), pipe_config->fdi_lanes);
3991 return false;
3992 }
3993
3994 if (IS_HASWELL(dev)) {
3995 if (pipe_config->fdi_lanes > 2) {
3996 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3997 pipe_config->fdi_lanes);
3998 return false;
3999 } else {
4000 return true;
4001 }
4002 }
4003
4004 if (INTEL_INFO(dev)->num_pipes == 2)
4005 return true;
4006
4007 /* Ivybridge 3 pipe is really complicated */
4008 switch (pipe) {
4009 case PIPE_A:
4010 return true;
4011 case PIPE_B:
4012 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4013 pipe_config->fdi_lanes > 2) {
4014 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4015 pipe_name(pipe), pipe_config->fdi_lanes);
4016 return false;
4017 }
4018 return true;
4019 case PIPE_C:
1e833f40 4020 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4021 pipe_B_crtc->config.fdi_lanes <= 2) {
4022 if (pipe_config->fdi_lanes > 2) {
4023 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4024 pipe_name(pipe), pipe_config->fdi_lanes);
4025 return false;
4026 }
4027 } else {
4028 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4029 return false;
4030 }
4031 return true;
4032 default:
4033 BUG();
4034 }
4035}
4036
e29c22c0
DV		 4037#define RETRY 1
4038static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4039 struct intel_crtc_config *pipe_config)
877d48d5 4040{
1857e1da 4041 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4042 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4043 int lane, link_bw, fdi_dotclock;
e29c22c0 4044 bool setup_ok, needs_recompute = false;
877d48d5 4045
e29c22c0 4046retry:
877d48d5
DV		 4047 /* FDI is a binary signal running at ~2.7GHz, encoding
4048 * each output octet as 10 bits. The actual frequency
4049 * is stored as a divider into a 100MHz clock, and the
4050 * mode pixel clock is stored in units of 1KHz.
4051 * Hence the bw of each lane in terms of the mode signal
4052 * is:
4053 */
4054 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4055
ff9a6750 4056 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4057 fdi_dotclock /= pipe_config->pixel_multiplier;
2bd89a07
DV		 4058
4059 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4060 pipe_config->pipe_bpp);
4061
4062 pipe_config->fdi_lanes = lane;
4063
2bd89a07 4064 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4065 link_bw, &pipe_config->fdi_m_n);
1857e1da 4066
e29c22c0
DV		 4067 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4068 intel_crtc->pipe, pipe_config);
4069 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4070 pipe_config->pipe_bpp -= 2*3;
4071 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4072 pipe_config->pipe_bpp);
4073 needs_recompute = true;
4074 pipe_config->bw_constrained = true;
4075
4076 goto retry;
4077 }
4078
4079 if (needs_recompute)
4080 return RETRY;
4081
4082 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4083}
4084
42db64ef
PZ		 4085static void hsw_compute_ips_config(struct intel_crtc *crtc,
4086 struct intel_crtc_config *pipe_config)
4087{
3c4ca58c
PZ		 4088 pipe_config->ips_enabled = i915_enable_ips &&
4089 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4090 pipe_config->pipe_bpp == 24;
4091}
4092
e29c22c0
DV		 4093static int intel_crtc_compute_config(struct drm_crtc *crtc,
4094 struct intel_crtc_config *pipe_config)
79e53945 4095{
2c07245f 4096 struct drm_device *dev = crtc->dev;
b8cecdf5 4097 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
42db64ef 4098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
89749350 4099
bad720ff 4100 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4101 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4102 if (pipe_config->requested_mode.clock * 3
4103 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4104 return -EINVAL;
2c07245f 4105 }
89749350 4106
f9bef081
DV		 4107 /* All interlaced capable intel hw wants timings in frames. Note though
4108 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4109 * timings, so we need to be careful not to clobber these.*/
7ae89233 4110 if (!pipe_config->timings_set)
f9bef081 4111 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4112
8693a824
DL		 4113 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4114 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4115 */
4116 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4117 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4118 return -EINVAL;
44f46b42 4119
bd080ee5 4120 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4121 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4122 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4123 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4124 * for lvds. */
4125 pipe_config->pipe_bpp = 8*3;
4126 }
4127
42db64ef
PZ		 4128 if (IS_HASWELL(dev))
4129 hsw_compute_ips_config(intel_crtc, pipe_config);
4130
877d48d5 4131 if (pipe_config->has_pch_encoder)
42db64ef 4132 return ironlake_fdi_compute_config(intel_crtc, pipe_config);
877d48d5 4133
e29c22c0 4134 return 0;
79e53945
JB		 4135}
4136
25eb05fc
JB		 4137static int valleyview_get_display_clock_speed(struct drm_device *dev)
4138{
4139 return 400000; /* FIXME */
4140}
4141
e70236a8
JB		 4142static int i945_get_display_clock_speed(struct drm_device *dev)
4143{
4144 return 400000;
4145}
79e53945 4146
e70236a8 4147static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4148{
e70236a8
JB		 4149 return 333000;
4150}
79e53945 4151
e70236a8
JB		 4152static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4153{
4154 return 200000;
4155}
79e53945 4156
e70236a8
JB		 4157static int i915gm_get_display_clock_speed(struct drm_device *dev)
4158{
4159 u16 gcfgc = 0;
79e53945 4160
e70236a8
JB		 4161 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4162
4163 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4164 return 133000;
4165 else {
4166 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4167 case GC_DISPLAY_CLOCK_333_MHZ:
4168 return 333000;
4169 default:
4170 case GC_DISPLAY_CLOCK_190_200_MHZ:
4171 return 190000;
79e53945 4172 }
e70236a8
JB		 4173 }
4174}
4175
4176static int i865_get_display_clock_speed(struct drm_device *dev)
4177{
4178 return 266000;
4179}
4180
4181static int i855_get_display_clock_speed(struct drm_device *dev)
4182{
4183 u16 hpllcc = 0;
4184 /* Assume that the hardware is in the high speed state. This
4185 * should be the default.
4186 */
4187 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4188 case GC_CLOCK_133_200:
4189 case GC_CLOCK_100_200:
4190 return 200000;
4191 case GC_CLOCK_166_250:
4192 return 250000;
4193 case GC_CLOCK_100_133:
79e53945 4194 return 133000;
e70236a8 4195 }
79e53945 4196
e70236a8
JB		 4197 /* Shouldn't happen */
4198 return 0;
4199}
79e53945 4200
e70236a8
JB		 4201static int i830_get_display_clock_speed(struct drm_device *dev)
4202{
4203 return 133000;
79e53945
JB		 4204}
4205
2c07245f 4206static void
a65851af 4207intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4208{
a65851af
VS		 4209 while (*num > DATA_LINK_M_N_MASK ||
4210 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4211 *num >>= 1;
4212 *den >>= 1;
4213 }
4214}
4215
a65851af
VS		 4216static void compute_m_n(unsigned int m, unsigned int n,
4217 uint32_t *ret_m, uint32_t *ret_n)
4218{
4219 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4220 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4221 intel_reduce_m_n_ratio(ret_m, ret_n);
4222}
4223
e69d0bc1
DV		 4224void
4225intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4226 int pixel_clock, int link_clock,
4227 struct intel_link_m_n *m_n)
2c07245f 4228{
e69d0bc1 4229 m_n->tu = 64;
a65851af
VS		 4230
4231 compute_m_n(bits_per_pixel * pixel_clock,
4232 link_clock * nlanes * 8,
4233 &m_n->gmch_m, &m_n->gmch_n);
4234
4235 compute_m_n(pixel_clock, link_clock,
4236 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4237}
4238
a7615030
CW		 4239static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4240{
72bbe58c
KP		 4241 if (i915_panel_use_ssc >= 0)
4242 return i915_panel_use_ssc != 0;
41aa3448 4243 return dev_priv->vbt.lvds_use_ssc
435793df 4244 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4245}
4246
a0c4da24
JB		 4247static int vlv_get_refclk(struct drm_crtc *crtc)
4248{
4249 struct drm_device *dev = crtc->dev;
4250 struct drm_i915_private *dev_priv = dev->dev_private;
4251 int refclk = 27000; /* for DP & HDMI */
4252
4253 return 100000; /* only one validated so far */
4254
4255 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4256 refclk = 96000;
4257 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4258 if (intel_panel_use_ssc(dev_priv))
4259 refclk = 100000;
4260 else
4261 refclk = 96000;
4262 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4263 refclk = 100000;
4264 }
4265
4266 return refclk;
4267}
4268
c65d77d8
JB		 4269static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4270{
4271 struct drm_device *dev = crtc->dev;
4272 struct drm_i915_private *dev_priv = dev->dev_private;
4273 int refclk;
4274
a0c4da24
JB		 4275 if (IS_VALLEYVIEW(dev)) {
4276 refclk = vlv_get_refclk(crtc);
4277 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4278 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4279 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4280 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4281 refclk / 1000);
4282 } else if (!IS_GEN2(dev)) {
4283 refclk = 96000;
4284 } else {
4285 refclk = 48000;
4286 }
4287
4288 return refclk;
4289}
4290
7429e9d4
DV		 4291static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4292{
4293 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4294}
4295
4296static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4297{
4298 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4299}
4300
f47709a9 4301static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4302 intel_clock_t *reduced_clock)
4303{
f47709a9 4304 struct drm_device *dev = crtc->base.dev;
a7516a05 4305 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4306 int pipe = crtc->pipe;
a7516a05
JB		 4307 u32 fp, fp2 = 0;
4308
4309 if (IS_PINEVIEW(dev)) {
7429e9d4 4310 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4311 if (reduced_clock)
7429e9d4 4312 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4313 } else {
7429e9d4 4314 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4315 if (reduced_clock)
7429e9d4 4316 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4317 }
4318
4319 I915_WRITE(FP0(pipe), fp);
4320
f47709a9
DV		 4321 crtc->lowfreq_avail = false;
4322 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4323 reduced_clock && i915_powersave) {
4324 I915_WRITE(FP1(pipe), fp2);
f47709a9 4325 crtc->lowfreq_avail = true;
a7516a05
JB		 4326 } else {
4327 I915_WRITE(FP1(pipe), fp);
4328 }
4329}
4330
89b667f8
JB		 4331static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4332{
4333 u32 reg_val;
4334
4335 /*
4336 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4337 * and set it to a reasonable value instead.
4338 */
ae99258f 4339 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4340 reg_val &= 0xffffff00;
4341 reg_val |= 0x00000030;
ae99258f 4342 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4343
ae99258f 4344 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4345 reg_val &= 0x8cffffff;
4346 reg_val = 0x8c000000;
ae99258f 4347 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4348
ae99258f 4349 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4350 reg_val &= 0xffffff00;
ae99258f 4351 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4352
ae99258f 4353 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4354 reg_val &= 0x00ffffff;
4355 reg_val |= 0xb0000000;
ae99258f 4356 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4357}
4358
b551842d
DV		 4359static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4360 struct intel_link_m_n *m_n)
4361{
4362 struct drm_device *dev = crtc->base.dev;
4363 struct drm_i915_private *dev_priv = dev->dev_private;
4364 int pipe = crtc->pipe;
4365
e3b95f1e
DV		 4366 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4367 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4368 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4369 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4370}
4371
4372static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4373 struct intel_link_m_n *m_n)
4374{
4375 struct drm_device *dev = crtc->base.dev;
4376 struct drm_i915_private *dev_priv = dev->dev_private;
4377 int pipe = crtc->pipe;
4378 enum transcoder transcoder = crtc->config.cpu_transcoder;
4379
4380 if (INTEL_INFO(dev)->gen >= 5) {
4381 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4382 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4383 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4384 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4385 } else {
e3b95f1e
DV		 4386 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4387 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4388 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4389 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4390 }
4391}
4392
03afc4a2
DV		 4393static void intel_dp_set_m_n(struct intel_crtc *crtc)
4394{
4395 if (crtc->config.has_pch_encoder)
4396 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4397 else
4398 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4399}
4400
f47709a9 4401static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4402{
f47709a9 4403 struct drm_device *dev = crtc->base.dev;
a0c4da24 4404 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8 4405 struct intel_encoder *encoder;
f47709a9 4406 int pipe = crtc->pipe;
89b667f8 4407 u32 dpll, mdiv;
a0c4da24 4408 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4409 bool is_hdmi;
198a037f 4410 u32 coreclk, reg_val, dpll_md;
a0c4da24 4411
09153000
DV		 4412 mutex_lock(&dev_priv->dpio_lock);
4413
89b667f8 4414 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4415
f47709a9
DV		 4416 bestn = crtc->config.dpll.n;
4417 bestm1 = crtc->config.dpll.m1;
4418 bestm2 = crtc->config.dpll.m2;
4419 bestp1 = crtc->config.dpll.p1;
4420 bestp2 = crtc->config.dpll.p2;
a0c4da24 4421
89b667f8
JB		 4422 /* See eDP HDMI DPIO driver vbios notes doc */
4423
4424 /* PLL B needs special handling */
4425 if (pipe)
4426 vlv_pllb_recal_opamp(dev_priv);
4427
4428 /* Set up Tx target for periodic Rcomp update */
ae99258f 4429 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4430
4431 /* Disable target IRef on PLL */
ae99258f 4432 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4433 reg_val &= 0x00ffffff;
ae99258f 4434 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4435
4436 /* Disable fast lock */
ae99258f 4437 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4438
4439 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4440 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4441 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4442 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4443 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4444
4445 /*
4446 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4447 * but we don't support that).
4448 * Note: don't use the DAC post divider as it seems unstable.
4449 */
4450 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4451 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4452
89b667f8 4453 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4454 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4455
89b667f8 4456 /* Set HBR and RBR LPF coefficients */
ff9a6750 4457 if (crtc->config.port_clock == 162000 ||
89b667f8 4458 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
ae99258f 4459 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4460 0x005f0021);
4461 else
ae99258f 4462 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4463 0x00d0000f);
4464
4465 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4466 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4467 /* Use SSC source */
4468 if (!pipe)
ae99258f 4469 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4470 0x0df40000);
4471 else
ae99258f 4472 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4473 0x0df70000);
4474 } else { /* HDMI or VGA */
4475 /* Use bend source */
4476 if (!pipe)
ae99258f 4477 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4478 0x0df70000);
4479 else
ae99258f 4480 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4481 0x0df40000);
4482 }
a0c4da24 4483
ae99258f 4484 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4485 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4486 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4487 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4488 coreclk |= 0x01000000;
ae99258f 4489 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4490
ae99258f 4491 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4492
89b667f8
JB		 4493 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4494 if (encoder->pre_pll_enable)
4495 encoder->pre_pll_enable(encoder);
2a8f64ca 4496
89b667f8
JB		 4497 /* Enable DPIO clock input */
4498 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4499 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4500 if (pipe)
4501 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4502
89b667f8 4503 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4504 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4505 POSTING_READ(DPLL(pipe));
4506 udelay(150);
a0c4da24 4507
89b667f8
JB		 4508 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4509 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4510
ef1b460d
DV		 4511 dpll_md = (crtc->config.pixel_multiplier - 1)
4512 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f
DV		 4513 I915_WRITE(DPLL_MD(pipe), dpll_md);
4514 POSTING_READ(DPLL_MD(pipe));
f47709a9 4515
89b667f8
JB		 4516 if (crtc->config.has_dp_encoder)
4517 intel_dp_set_m_n(crtc);
09153000
DV		 4518
4519 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4520}
4521
f47709a9
DV		 4522static void i9xx_update_pll(struct intel_crtc *crtc,
4523 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4524 int num_connectors)
4525{
f47709a9 4526 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4527 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4528 struct intel_encoder *encoder;
f47709a9 4529 int pipe = crtc->pipe;
eb1cbe48
DV		 4530 u32 dpll;
4531 bool is_sdvo;
f47709a9 4532 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4533
f47709a9 4534 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4535
f47709a9
DV		 4536 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4537 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4538
4539 dpll = DPLL_VGA_MODE_DIS;
4540
f47709a9 4541 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4542 dpll |= DPLLB_MODE_LVDS;
4543 else
4544 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4545
ef1b460d 4546 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4547 dpll |= (crtc->config.pixel_multiplier - 1)
4548 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4549 }
198a037f
DV		 4550
4551 if (is_sdvo)
4552 dpll |= DPLL_DVO_HIGH_SPEED;
4553
f47709a9 4554 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4555 dpll |= DPLL_DVO_HIGH_SPEED;
4556
4557 /* compute bitmask from p1 value */
4558 if (IS_PINEVIEW(dev))
4559 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4560 else {
4561 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4562 if (IS_G4X(dev) && reduced_clock)
4563 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4564 }
4565 switch (clock->p2) {
4566 case 5:
4567 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4568 break;
4569 case 7:
4570 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4571 break;
4572 case 10:
4573 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4574 break;
4575 case 14:
4576 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4577 break;
4578 }
4579 if (INTEL_INFO(dev)->gen >= 4)
4580 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4581
09ede541 4582 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4583 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4584 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4585 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4586 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4587 else
4588 dpll |= PLL_REF_INPUT_DREFCLK;
4589
4590 dpll |= DPLL_VCO_ENABLE;
4591 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4592 POSTING_READ(DPLL(pipe));
4593 udelay(150);
4594
f47709a9 4595 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4596 if (encoder->pre_pll_enable)
4597 encoder->pre_pll_enable(encoder);
eb1cbe48 4598
f47709a9
DV		 4599 if (crtc->config.has_dp_encoder)
4600 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4601
4602 I915_WRITE(DPLL(pipe), dpll);
4603
4604 /* Wait for the clocks to stabilize. */
4605 POSTING_READ(DPLL(pipe));
4606 udelay(150);
4607
4608 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4609 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4610 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f 4611 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4612 } else {
4613 /* The pixel multiplier can only be updated once the
4614 * DPLL is enabled and the clocks are stable.
4615 *
4616 * So write it again.
4617 */
4618 I915_WRITE(DPLL(pipe), dpll);
4619 }
4620}
4621
f47709a9 4622static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4623 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4624 int num_connectors)
4625{
f47709a9 4626 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4627 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4628 struct intel_encoder *encoder;
f47709a9 4629 int pipe = crtc->pipe;
eb1cbe48 4630 u32 dpll;
f47709a9 4631 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4632
f47709a9 4633 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4634
eb1cbe48
DV		 4635 dpll = DPLL_VGA_MODE_DIS;
4636
f47709a9 4637 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4638 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4639 } else {
4640 if (clock->p1 == 2)
4641 dpll |= PLL_P1_DIVIDE_BY_TWO;
4642 else
4643 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4644 if (clock->p2 == 4)
4645 dpll |= PLL_P2_DIVIDE_BY_4;
4646 }
4647
f47709a9 4648 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4649 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4650 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4651 else
4652 dpll |= PLL_REF_INPUT_DREFCLK;
4653
4654 dpll |= DPLL_VCO_ENABLE;
4655 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4656 POSTING_READ(DPLL(pipe));
4657 udelay(150);
4658
f47709a9 4659 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4660 if (encoder->pre_pll_enable)
4661 encoder->pre_pll_enable(encoder);
eb1cbe48 4662
5b5896e4
DV		 4663 I915_WRITE(DPLL(pipe), dpll);
4664
4665 /* Wait for the clocks to stabilize. */
4666 POSTING_READ(DPLL(pipe));
4667 udelay(150);
4668
eb1cbe48
DV		 4669 /* The pixel multiplier can only be updated once the
4670 * DPLL is enabled and the clocks are stable.
4671 *
4672 * So write it again.
4673 */
4674 I915_WRITE(DPLL(pipe), dpll);
4675}
4676
8a654f3b 4677static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4678{
4679 struct drm_device *dev = intel_crtc->base.dev;
4680 struct drm_i915_private *dev_priv = dev->dev_private;
4681 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4682 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4683 struct drm_display_mode *adjusted_mode =
4684 &intel_crtc->config.adjusted_mode;
4685 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4686 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4687
4688 /* We need to be careful not to changed the adjusted mode, for otherwise
4689 * the hw state checker will get angry at the mismatch. */
4690 crtc_vtotal = adjusted_mode->crtc_vtotal;
4691 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4692
4693 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4694 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4695 crtc_vtotal -= 1;
4696 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4697 vsyncshift = adjusted_mode->crtc_hsync_start
4698 - adjusted_mode->crtc_htotal / 2;
4699 } else {
4700 vsyncshift = 0;
4701 }
4702
4703 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4704 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4705
fe2b8f9d 4706 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4707 (adjusted_mode->crtc_hdisplay - 1) |
4708 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4709 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4710 (adjusted_mode->crtc_hblank_start - 1) |
4711 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4712 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4713 (adjusted_mode->crtc_hsync_start - 1) |
4714 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4715
fe2b8f9d 4716 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4717 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4718 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4719 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4720 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4721 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4722 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4723 (adjusted_mode->crtc_vsync_start - 1) |
4724 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4725
b5e508d4
PZ		 4726 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4727 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4728 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4729 * bits. */
4730 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4731 (pipe == PIPE_B || pipe == PIPE_C))
4732 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4733
b0e77b9c
PZ		 4734 /* pipesrc controls the size that is scaled from, which should
4735 * always be the user's requested size.
4736 */
4737 I915_WRITE(PIPESRC(pipe),
4738 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4739}
4740
1bd1bd80
DV		 4741static void intel_get_pipe_timings(struct intel_crtc *crtc,
4742 struct intel_crtc_config *pipe_config)
4743{
4744 struct drm_device *dev = crtc->base.dev;
4745 struct drm_i915_private *dev_priv = dev->dev_private;
4746 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4747 uint32_t tmp;
4748
4749 tmp = I915_READ(HTOTAL(cpu_transcoder));
4750 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4751 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4752 tmp = I915_READ(HBLANK(cpu_transcoder));
4753 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4754 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4755 tmp = I915_READ(HSYNC(cpu_transcoder));
4756 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4757 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4758
4759 tmp = I915_READ(VTOTAL(cpu_transcoder));
4760 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4761 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4762 tmp = I915_READ(VBLANK(cpu_transcoder));
4763 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4764 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4765 tmp = I915_READ(VSYNC(cpu_transcoder));
4766 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4767 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4768
4769 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4770 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4771 pipe_config->adjusted_mode.crtc_vtotal += 1;
4772 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4773 }
4774
4775 tmp = I915_READ(PIPESRC(crtc->pipe));
4776 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4777 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4778}
4779
84b046f3
DV		 4780static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4781{
4782 struct drm_device *dev = intel_crtc->base.dev;
4783 struct drm_i915_private *dev_priv = dev->dev_private;
4784 uint32_t pipeconf;
4785
4786 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4787
4788 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4789 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4790 * core speed.
4791 *
4792 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4793 * pipe == 0 check?
4794 */
4795 if (intel_crtc->config.requested_mode.clock >
4796 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4797 pipeconf |= PIPECONF_DOUBLE_WIDE;
4798 else
4799 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4800 }
4801
ff9ce46e
DV		 4802 /* only g4x and later have fancy bpc/dither controls */
4803 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4804 pipeconf &= ~(PIPECONF_BPC_MASK |
4805 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4806
4807 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4808 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4809 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4810 PIPECONF_DITHER_TYPE_SP;
84b046f3 4811
ff9ce46e
DV		 4812 switch (intel_crtc->config.pipe_bpp) {
4813 case 18:
4814 pipeconf |= PIPECONF_6BPC;
4815 break;
4816 case 24:
4817 pipeconf |= PIPECONF_8BPC;
4818 break;
4819 case 30:
4820 pipeconf |= PIPECONF_10BPC;
4821 break;
4822 default:
4823 /* Case prevented by intel_choose_pipe_bpp_dither. */
4824 BUG();
84b046f3
DV		 4825 }
4826 }
4827
4828 if (HAS_PIPE_CXSR(dev)) {
4829 if (intel_crtc->lowfreq_avail) {
4830 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4831 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4832 } else {
4833 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4834 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4835 }
4836 }
4837
4838 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4839 if (!IS_GEN2(dev) &&
4840 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4841 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4842 else
4843 pipeconf |= PIPECONF_PROGRESSIVE;
4844
9c8e09b7
VS		 4845 if (IS_VALLEYVIEW(dev)) {
4846 if (intel_crtc->config.limited_color_range)
4847 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4848 else
4849 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4850 }
4851
84b046f3
DV		 4852 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4853 POSTING_READ(PIPECONF(intel_crtc->pipe));
4854}
4855
f564048e 4856static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4857 int x, int y,
94352cf9 4858 struct drm_framebuffer *fb)
79e53945
JB		 4859{
4860 struct drm_device *dev = crtc->dev;
4861 struct drm_i915_private *dev_priv = dev->dev_private;
4862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4863 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4864 int pipe = intel_crtc->pipe;
80824003 4865 int plane = intel_crtc->plane;
c751ce4f 4866 int refclk, num_connectors = 0;
652c393a 4867 intel_clock_t clock, reduced_clock;
84b046f3 4868 u32 dspcntr;
a16af721
DV		 4869 bool ok, has_reduced_clock = false;
4870 bool is_lvds = false;
5eddb70b 4871 struct intel_encoder *encoder;
d4906093 4872 const intel_limit_t *limit;
5c3b82e2 4873 int ret;
79e53945 4874
6c2b7c12 4875 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4876 switch (encoder->type) {
79e53945
JB		 4877 case INTEL_OUTPUT_LVDS:
4878 is_lvds = true;
4879 break;
79e53945 4880 }
43565a06 4881
c751ce4f 4882 num_connectors++;
79e53945
JB		 4883 }
4884
c65d77d8 4885 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4886
d4906093
ML		 4887 /*
4888 * Returns a set of divisors for the desired target clock with the given
4889 * refclk, or FALSE. The returned values represent the clock equation:
4890 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4891 */
1b894b59 4892 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4893 ok = dev_priv->display.find_dpll(limit, crtc,
4894 intel_crtc->config.port_clock,
ee9300bb
DV		 4895 refclk, NULL, &clock);
4896 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4897 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4898 return -EINVAL;
79e53945
JB		 4899 }
4900
cda4b7d3 4901 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4902 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4903
ddc9003c 4904 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4905 /*
4906 * Ensure we match the reduced clock's P to the target clock.
4907 * If the clocks don't match, we can't switch the display clock
4908 * by using the FP0/FP1. In such case we will disable the LVDS
4909 * downclock feature.
4910 */
ee9300bb
DV		 4911 has_reduced_clock =
4912 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4913 dev_priv->lvds_downclock,
ee9300bb 4914 refclk, &clock,
5eddb70b 4915 &reduced_clock);
7026d4ac 4916 }
f47709a9
DV		 4917 /* Compat-code for transition, will disappear. */
4918 if (!intel_crtc->config.clock_set) {
4919 intel_crtc->config.dpll.n = clock.n;
4920 intel_crtc->config.dpll.m1 = clock.m1;
4921 intel_crtc->config.dpll.m2 = clock.m2;
4922 intel_crtc->config.dpll.p1 = clock.p1;
4923 intel_crtc->config.dpll.p2 = clock.p2;
4924 }
7026d4ac 4925
eb1cbe48 4926 if (IS_GEN2(dev))
8a654f3b 4927 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4928 has_reduced_clock ? &reduced_clock : NULL,
4929 num_connectors);
a0c4da24 4930 else if (IS_VALLEYVIEW(dev))
f47709a9 4931 vlv_update_pll(intel_crtc);
79e53945 4932 else
f47709a9 4933 i9xx_update_pll(intel_crtc,
eb1cbe48 4934 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4935 num_connectors);
79e53945 4936
79e53945
JB		 4937 /* Set up the display plane register */
4938 dspcntr = DISPPLANE_GAMMA_ENABLE;
4939
da6ecc5d
JB		 4940 if (!IS_VALLEYVIEW(dev)) {
4941 if (pipe == 0)
4942 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4943 else
4944 dspcntr |= DISPPLANE_SEL_PIPE_B;
4945 }
79e53945 4946
8a654f3b 4947 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4948
4949 /* pipesrc and dspsize control the size that is scaled from,
4950 * which should always be the user's requested size.
79e53945 4951 */
929c77fb
EA		 4952 I915_WRITE(DSPSIZE(plane),
4953 ((mode->vdisplay - 1) << 16) |
4954 (mode->hdisplay - 1));
4955 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4956
84b046f3
DV		 4957 i9xx_set_pipeconf(intel_crtc);
4958
f564048e
EA		 4959 I915_WRITE(DSPCNTR(plane), dspcntr);
4960 POSTING_READ(DSPCNTR(plane));
4961
94352cf9 4962 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4963
4964 intel_update_watermarks(dev);
4965
f564048e
EA		 4966 return ret;
4967}
4968
2fa2fe9a
DV		 4969static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4970 struct intel_crtc_config *pipe_config)
4971{
4972 struct drm_device *dev = crtc->base.dev;
4973 struct drm_i915_private *dev_priv = dev->dev_private;
4974 uint32_t tmp;
4975
4976 tmp = I915_READ(PFIT_CONTROL);
4977
4978 if (INTEL_INFO(dev)->gen < 4) {
4979 if (crtc->pipe != PIPE_B)
4980 return;
4981
4982 /* gen2/3 store dither state in pfit control, needs to match */
4983 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4984 } else {
4985 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4986 return;
4987 }
4988
4989 if (!(tmp & PFIT_ENABLE))
4990 return;
4991
4992 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4993 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4994 if (INTEL_INFO(dev)->gen < 5)
4995 pipe_config->gmch_pfit.lvds_border_bits =
4996 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4997}
4998
0e8ffe1b
DV		 4999static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5000 struct intel_crtc_config *pipe_config)
5001{
5002 struct drm_device *dev = crtc->base.dev;
5003 struct drm_i915_private *dev_priv = dev->dev_private;
5004 uint32_t tmp;
5005
eccb140b
DV		 5006 pipe_config->cpu_transcoder = crtc->pipe;
5007
0e8ffe1b
DV		 5008 tmp = I915_READ(PIPECONF(crtc->pipe));
5009 if (!(tmp & PIPECONF_ENABLE))
5010 return false;
5011
1bd1bd80
DV		 5012 intel_get_pipe_timings(crtc, pipe_config);
5013
2fa2fe9a
DV		 5014 i9xx_get_pfit_config(crtc, pipe_config);
5015
6c49f241
DV		 5016 if (INTEL_INFO(dev)->gen >= 4) {
5017 tmp = I915_READ(DPLL_MD(crtc->pipe));
5018 pipe_config->pixel_multiplier =
5019 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5020 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5021 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5022 tmp = I915_READ(DPLL(crtc->pipe));
5023 pipe_config->pixel_multiplier =
5024 ((tmp & SDVO_MULTIPLIER_MASK)
5025 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5026 } else {
5027 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5028 * port and will be fixed up in the encoder->get_config
5029 * function. */
5030 pipe_config->pixel_multiplier = 1;
5031 }
5032
0e8ffe1b
DV		 5033 return true;
5034}
5035
dde86e2d 5036static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5037{
5038 struct drm_i915_private *dev_priv = dev->dev_private;
5039 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5040 struct intel_encoder *encoder;
74cfd7ac 5041 u32 val, final;
13d83a67 5042 bool has_lvds = false;
199e5d79 5043 bool has_cpu_edp = false;
199e5d79 5044 bool has_panel = false;
99eb6a01
KP		 5045 bool has_ck505 = false;
5046 bool can_ssc = false;
13d83a67
JB		 5047
5048 /* We need to take the global config into account */
199e5d79
KP		 5049 list_for_each_entry(encoder, &mode_config->encoder_list,
5050 base.head) {
5051 switch (encoder->type) {
5052 case INTEL_OUTPUT_LVDS:
5053 has_panel = true;
5054 has_lvds = true;
5055 break;
5056 case INTEL_OUTPUT_EDP:
5057 has_panel = true;
2de6905f 5058 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5059 has_cpu_edp = true;
5060 break;
13d83a67
JB		 5061 }
5062 }
5063
99eb6a01 5064 if (HAS_PCH_IBX(dev)) {
41aa3448 5065 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5066 can_ssc = has_ck505;
5067 } else {
5068 has_ck505 = false;
5069 can_ssc = true;
5070 }
5071
2de6905f
ID		 5072 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5073 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5074
5075 /* Ironlake: try to setup display ref clock before DPLL
5076 * enabling. This is only under driver's control after
5077 * PCH B stepping, previous chipset stepping should be
5078 * ignoring this setting.
5079 */
74cfd7ac
CW		 5080 val = I915_READ(PCH_DREF_CONTROL);
5081
5082 /* As we must carefully and slowly disable/enable each source in turn,
5083 * compute the final state we want first and check if we need to
5084 * make any changes at all.
5085 */
5086 final = val;
5087 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5088 if (has_ck505)
5089 final |= DREF_NONSPREAD_CK505_ENABLE;
5090 else
5091 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5092
5093 final &= ~DREF_SSC_SOURCE_MASK;
5094 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5095 final &= ~DREF_SSC1_ENABLE;
5096
5097 if (has_panel) {
5098 final |= DREF_SSC_SOURCE_ENABLE;
5099
5100 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5101 final |= DREF_SSC1_ENABLE;
5102
5103 if (has_cpu_edp) {
5104 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5105 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5106 else
5107 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5108 } else
5109 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5110 } else {
5111 final |= DREF_SSC_SOURCE_DISABLE;
5112 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5113 }
5114
5115 if (final == val)
5116 return;
5117
13d83a67 5118 /* Always enable nonspread source */
74cfd7ac 5119 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5120
99eb6a01 5121 if (has_ck505)
74cfd7ac 5122 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5123 else
74cfd7ac 5124 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5125
199e5d79 5126 if (has_panel) {
74cfd7ac
CW		 5127 val &= ~DREF_SSC_SOURCE_MASK;
5128 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5129
199e5d79 5130 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5131 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5132 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5133 val |= DREF_SSC1_ENABLE;
e77166b5 5134 } else
74cfd7ac 5135 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5136
5137 /* Get SSC going before enabling the outputs */
74cfd7ac 5138 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5139 POSTING_READ(PCH_DREF_CONTROL);
5140 udelay(200);
5141
74cfd7ac 5142 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5143
5144 /* Enable CPU source on CPU attached eDP */
199e5d79 5145 if (has_cpu_edp) {
99eb6a01 5146 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5147 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5148 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5149 }
13d83a67 5150 else
74cfd7ac 5151 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5152 } else
74cfd7ac 5153 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5154
74cfd7ac 5155 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5156 POSTING_READ(PCH_DREF_CONTROL);
5157 udelay(200);
5158 } else {
5159 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5160
74cfd7ac 5161 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5162
5163 /* Turn off CPU output */
74cfd7ac 5164 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5165
74cfd7ac 5166 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5167 POSTING_READ(PCH_DREF_CONTROL);
5168 udelay(200);
5169
5170 /* Turn off the SSC source */
74cfd7ac
CW		 5171 val &= ~DREF_SSC_SOURCE_MASK;
5172 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5173
5174 /* Turn off SSC1 */
74cfd7ac 5175 val &= ~DREF_SSC1_ENABLE;
199e5d79 5176
74cfd7ac 5177 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5178 POSTING_READ(PCH_DREF_CONTROL);
5179 udelay(200);
5180 }
74cfd7ac
CW		 5181
5182 BUG_ON(val != final);
13d83a67
JB		 5183}
5184
dde86e2d
PZ		 5185/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5186static void lpt_init_pch_refclk(struct drm_device *dev)
5187{
5188 struct drm_i915_private *dev_priv = dev->dev_private;
5189 struct drm_mode_config *mode_config = &dev->mode_config;
5190 struct intel_encoder *encoder;
5191 bool has_vga = false;
5192 bool is_sdv = false;
5193 u32 tmp;
5194
5195 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5196 switch (encoder->type) {
5197 case INTEL_OUTPUT_ANALOG:
5198 has_vga = true;
5199 break;
5200 }
5201 }
5202
5203 if (!has_vga)
5204 return;
5205
c00db246
DV		 5206 mutex_lock(&dev_priv->dpio_lock);
5207
dde86e2d
PZ		 5208 /* XXX: Rip out SDV support once Haswell ships for real. */
5209 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5210 is_sdv = true;
5211
5212 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5213 tmp &= ~SBI_SSCCTL_DISABLE;
5214 tmp |= SBI_SSCCTL_PATHALT;
5215 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5216
5217 udelay(24);
5218
5219 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5220 tmp &= ~SBI_SSCCTL_PATHALT;
5221 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5222
5223 if (!is_sdv) {
5224 tmp = I915_READ(SOUTH_CHICKEN2);
5225 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5226 I915_WRITE(SOUTH_CHICKEN2, tmp);
5227
5228 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5229 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5230 DRM_ERROR("FDI mPHY reset assert timeout\n");
5231
5232 tmp = I915_READ(SOUTH_CHICKEN2);
5233 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5234 I915_WRITE(SOUTH_CHICKEN2, tmp);
5235
5236 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5237 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5238 100))
5239 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5240 }
5241
5242 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5243 tmp &= ~(0xFF << 24);
5244 tmp |= (0x12 << 24);
5245 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5246
dde86e2d
PZ		 5247 if (is_sdv) {
5248 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5249 tmp |= 0x7FFF;
5250 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5251 }
5252
5253 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5254 tmp |= (1 << 11);
5255 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5256
5257 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5258 tmp |= (1 << 11);
5259 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5260
5261 if (is_sdv) {
5262 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5263 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5264 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5265
5266 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5267 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5268 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5269
5270 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5271 tmp |= (0x3F << 8);
5272 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5273
5274 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5275 tmp |= (0x3F << 8);
5276 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5277 }
5278
5279 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5280 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5281 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5282
5283 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5284 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5285 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5286
5287 if (!is_sdv) {
5288 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5289 tmp &= ~(7 << 13);
5290 tmp |= (5 << 13);
5291 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5292
5293 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5294 tmp &= ~(7 << 13);
5295 tmp |= (5 << 13);
5296 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5297 }
5298
5299 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5300 tmp &= ~0xFF;
5301 tmp |= 0x1C;
5302 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5303
5304 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5305 tmp &= ~0xFF;
5306 tmp |= 0x1C;
5307 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5308
5309 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5310 tmp &= ~(0xFF << 16);
5311 tmp |= (0x1C << 16);
5312 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5313
5314 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5315 tmp &= ~(0xFF << 16);
5316 tmp |= (0x1C << 16);
5317 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5318
5319 if (!is_sdv) {
5320 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5321 tmp |= (1 << 27);
5322 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5323
5324 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5325 tmp |= (1 << 27);
5326 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5327
5328 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5329 tmp &= ~(0xF << 28);
5330 tmp |= (4 << 28);
5331 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5332
5333 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5334 tmp &= ~(0xF << 28);
5335 tmp |= (4 << 28);
5336 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5337 }
5338
5339 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5340 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5341 tmp |= SBI_DBUFF0_ENABLE;
5342 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5343
5344 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5345}
5346
5347/*
5348 * Initialize reference clocks when the driver loads
5349 */
5350void intel_init_pch_refclk(struct drm_device *dev)
5351{
5352 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5353 ironlake_init_pch_refclk(dev);
5354 else if (HAS_PCH_LPT(dev))
5355 lpt_init_pch_refclk(dev);
5356}
5357
d9d444cb
JB		 5358static int ironlake_get_refclk(struct drm_crtc *crtc)
5359{
5360 struct drm_device *dev = crtc->dev;
5361 struct drm_i915_private *dev_priv = dev->dev_private;
5362 struct intel_encoder *encoder;
d9d444cb
JB		 5363 int num_connectors = 0;
5364 bool is_lvds = false;
5365
6c2b7c12 5366 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5367 switch (encoder->type) {
5368 case INTEL_OUTPUT_LVDS:
5369 is_lvds = true;
5370 break;
d9d444cb
JB		 5371 }
5372 num_connectors++;
5373 }
5374
5375 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5376 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5377 dev_priv->vbt.lvds_ssc_freq);
5378 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5379 }
5380
5381 return 120000;
5382}
5383
6ff93609 5384static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5385{
c8203565 5386 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5388 int pipe = intel_crtc->pipe;
c8203565
PZ		 5389 uint32_t val;
5390
5391 val = I915_READ(PIPECONF(pipe));
5392
dfd07d72 5393 val &= ~PIPECONF_BPC_MASK;
965e0c48 5394 switch (intel_crtc->config.pipe_bpp) {
c8203565 5395 case 18:
dfd07d72 5396 val |= PIPECONF_6BPC;
c8203565
PZ		 5397 break;
5398 case 24:
dfd07d72 5399 val |= PIPECONF_8BPC;
c8203565
PZ		 5400 break;
5401 case 30:
dfd07d72 5402 val |= PIPECONF_10BPC;
c8203565
PZ		 5403 break;
5404 case 36:
dfd07d72 5405 val |= PIPECONF_12BPC;
c8203565
PZ		 5406 break;
5407 default:
cc769b62
PZ		 5408 /* Case prevented by intel_choose_pipe_bpp_dither. */
5409 BUG();
c8203565
PZ		 5410 }
5411
5412 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5413 if (intel_crtc->config.dither)
c8203565
PZ		 5414 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5415
5416 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5417 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5418 val |= PIPECONF_INTERLACED_ILK;
5419 else
5420 val |= PIPECONF_PROGRESSIVE;
5421
50f3b016 5422 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5423 val |= PIPECONF_COLOR_RANGE_SELECT;
5424 else
5425 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5426
c8203565
PZ		 5427 I915_WRITE(PIPECONF(pipe), val);
5428 POSTING_READ(PIPECONF(pipe));
5429}
5430
86d3efce
VS		 5431/*
5432 * Set up the pipe CSC unit.
5433 *
5434 * Currently only full range RGB to limited range RGB conversion
5435 * is supported, but eventually this should handle various
5436 * RGB<->YCbCr scenarios as well.
5437 */
50f3b016 5438static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5439{
5440 struct drm_device *dev = crtc->dev;
5441 struct drm_i915_private *dev_priv = dev->dev_private;
5442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5443 int pipe = intel_crtc->pipe;
5444 uint16_t coeff = 0x7800; /* 1.0 */
5445
5446 /*
5447 * TODO: Check what kind of values actually come out of the pipe
5448 * with these coeff/postoff values and adjust to get the best
5449 * accuracy. Perhaps we even need to take the bpc value into
5450 * consideration.
5451 */
5452
50f3b016 5453 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5454 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5455
5456 /*
5457 * GY/GU and RY/RU should be the other way around according
5458 * to BSpec, but reality doesn't agree. Just set them up in
5459 * a way that results in the correct picture.
5460 */
5461 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5462 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5463
5464 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5465 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5466
5467 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5468 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5469
5470 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5471 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5472 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5473
5474 if (INTEL_INFO(dev)->gen > 6) {
5475 uint16_t postoff = 0;
5476
50f3b016 5477 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5478 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5479
5480 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5481 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5482 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5483
5484 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5485 } else {
5486 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5487
50f3b016 5488 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5489 mode |= CSC_BLACK_SCREEN_OFFSET;
5490
5491 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5492 }
5493}
5494
6ff93609 5495static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5496{
5497 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5499 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5500 uint32_t val;
5501
702e7a56 5502 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5503
5504 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5505 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5506 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5507
5508 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5509 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5510 val |= PIPECONF_INTERLACED_ILK;
5511 else
5512 val |= PIPECONF_PROGRESSIVE;
5513
702e7a56
PZ		 5514 I915_WRITE(PIPECONF(cpu_transcoder), val);
5515 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5516}
5517
6591c6e4 5518static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5519 intel_clock_t *clock,
5520 bool *has_reduced_clock,
5521 intel_clock_t *reduced_clock)
5522{
5523 struct drm_device *dev = crtc->dev;
5524 struct drm_i915_private *dev_priv = dev->dev_private;
5525 struct intel_encoder *intel_encoder;
5526 int refclk;
d4906093 5527 const intel_limit_t *limit;
a16af721 5528 bool ret, is_lvds = false;
79e53945 5529
6591c6e4
PZ		 5530 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5531 switch (intel_encoder->type) {
79e53945
JB		 5532 case INTEL_OUTPUT_LVDS:
5533 is_lvds = true;
5534 break;
79e53945
JB		 5535 }
5536 }
5537
d9d444cb 5538 refclk = ironlake_get_refclk(crtc);
79e53945 5539
d4906093
ML		 5540 /*
5541 * Returns a set of divisors for the desired target clock with the given
5542 * refclk, or FALSE. The returned values represent the clock equation:
5543 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5544 */
1b894b59 5545 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5546 ret = dev_priv->display.find_dpll(limit, crtc,
5547 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5548 refclk, NULL, clock);
6591c6e4
PZ		 5549 if (!ret)
5550 return false;
cda4b7d3 5551
ddc9003c 5552 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5553 /*
5554 * Ensure we match the reduced clock's P to the target clock.
5555 * If the clocks don't match, we can't switch the display clock
5556 * by using the FP0/FP1. In such case we will disable the LVDS
5557 * downclock feature.
5558 */
ee9300bb
DV		 5559 *has_reduced_clock =
5560 dev_priv->display.find_dpll(limit, crtc,
5561 dev_priv->lvds_downclock,
5562 refclk, clock,
5563 reduced_clock);
652c393a 5564 }
61e9653f 5565
6591c6e4
PZ		 5566 return true;
5567}
5568
01a415fd
DV		 5569static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5570{
5571 struct drm_i915_private *dev_priv = dev->dev_private;
5572 uint32_t temp;
5573
5574 temp = I915_READ(SOUTH_CHICKEN1);
5575 if (temp & FDI_BC_BIFURCATION_SELECT)
5576 return;
5577
5578 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5579 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5580
5581 temp |= FDI_BC_BIFURCATION_SELECT;
5582 DRM_DEBUG_KMS("enabling fdi C rx\n");
5583 I915_WRITE(SOUTH_CHICKEN1, temp);
5584 POSTING_READ(SOUTH_CHICKEN1);
5585}
5586
ebfd86fd
DV		 5587static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5588{
5589 struct drm_device *dev = intel_crtc->base.dev;
5590 struct drm_i915_private *dev_priv = dev->dev_private;
5591
5592 switch (intel_crtc->pipe) {
5593 case PIPE_A:
5594 break;
5595 case PIPE_B:
5596 if (intel_crtc->config.fdi_lanes > 2)
5597 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5598 else
5599 cpt_enable_fdi_bc_bifurcation(dev);
5600
5601 break;
5602 case PIPE_C:
01a415fd
DV		 5603 cpt_enable_fdi_bc_bifurcation(dev);
5604
ebfd86fd 5605 break;
01a415fd
DV		 5606 default:
5607 BUG();
5608 }
5609}
5610
d4b1931c
PZ		 5611int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5612{
5613 /*
5614 * Account for spread spectrum to avoid
5615 * oversubscribing the link. Max center spread
5616 * is 2.5%; use 5% for safety's sake.
5617 */
5618 u32 bps = target_clock * bpp * 21 / 20;
5619 return bps / (link_bw * 8) + 1;
5620}
5621
7429e9d4
DV		 5622static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5623{
5624 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5625}
5626
de13a2e3 5627static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5628 u32 *fp,
9a7c7890 5629 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5630{
de13a2e3 5631 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5632 struct drm_device *dev = crtc->dev;
5633 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5634 struct intel_encoder *intel_encoder;
5635 uint32_t dpll;
6cc5f341 5636 int factor, num_connectors = 0;
09ede541 5637 bool is_lvds = false, is_sdvo = false;
79e53945 5638
de13a2e3
PZ		 5639 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5640 switch (intel_encoder->type) {
79e53945
JB		 5641 case INTEL_OUTPUT_LVDS:
5642 is_lvds = true;
5643 break;
5644 case INTEL_OUTPUT_SDVO:
7d57382e 5645 case INTEL_OUTPUT_HDMI:
79e53945
JB		 5646 is_sdvo = true;
5647 break;
79e53945 5648 }
43565a06 5649
c751ce4f 5650 num_connectors++;
79e53945 5651 }
79e53945 5652
c1858123 5653 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5654 factor = 21;
5655 if (is_lvds) {
5656 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5657 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5658 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5659 factor = 25;
09ede541 5660 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5661 factor = 20;
c1858123 5662
7429e9d4 5663 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5664 *fp |= FP_CB_TUNE;
2c07245f 5665
9a7c7890
DV		 5666 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5667 *fp2 |= FP_CB_TUNE;
5668
5eddb70b 5669 dpll = 0;
2c07245f 5670
a07d6787
EA		 5671 if (is_lvds)
5672 dpll |= DPLLB_MODE_LVDS;
5673 else
5674 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5675
ef1b460d
DV		 5676 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5677 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5678
5679 if (is_sdvo)
5680 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5681 if (intel_crtc->config.has_dp_encoder)
a07d6787 5682 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5683
a07d6787 5684 /* compute bitmask from p1 value */
7429e9d4 5685 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5686 /* also FPA1 */
7429e9d4 5687 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5688
7429e9d4 5689 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5690 case 5:
5691 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5692 break;
5693 case 7:
5694 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5695 break;
5696 case 10:
5697 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5698 break;
5699 case 14:
5700 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5701 break;
79e53945
JB		 5702 }
5703
b4c09f3b 5704 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5705 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5706 else
5707 dpll |= PLL_REF_INPUT_DREFCLK;
5708
de13a2e3
PZ		 5709 return dpll;
5710}
5711
5712static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5713 int x, int y,
5714 struct drm_framebuffer *fb)
5715{
5716 struct drm_device *dev = crtc->dev;
5717 struct drm_i915_private *dev_priv = dev->dev_private;
5718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5719 int pipe = intel_crtc->pipe;
5720 int plane = intel_crtc->plane;
5721 int num_connectors = 0;
5722 intel_clock_t clock, reduced_clock;
cbbab5bd 5723 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5724 bool ok, has_reduced_clock = false;
8b47047b 5725 bool is_lvds = false;
de13a2e3 5726 struct intel_encoder *encoder;
de13a2e3 5727 int ret;
de13a2e3
PZ		 5728
5729 for_each_encoder_on_crtc(dev, crtc, encoder) {
5730 switch (encoder->type) {
5731 case INTEL_OUTPUT_LVDS:
5732 is_lvds = true;
5733 break;
de13a2e3
PZ		 5734 }
5735
5736 num_connectors++;
a07d6787 5737 }
79e53945 5738
5dc5298b
PZ		 5739 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5740 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5741
ff9a6750 5742 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5743 &has_reduced_clock, &reduced_clock);
ee9300bb 5744 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5745 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5746 return -EINVAL;
79e53945 5747 }
f47709a9
DV		 5748 /* Compat-code for transition, will disappear. */
5749 if (!intel_crtc->config.clock_set) {
5750 intel_crtc->config.dpll.n = clock.n;
5751 intel_crtc->config.dpll.m1 = clock.m1;
5752 intel_crtc->config.dpll.m2 = clock.m2;
5753 intel_crtc->config.dpll.p1 = clock.p1;
5754 intel_crtc->config.dpll.p2 = clock.p2;
5755 }
79e53945 5756
de13a2e3
PZ		 5757 /* Ensure that the cursor is valid for the new mode before changing... */
5758 intel_crtc_update_cursor(crtc, true);
5759
5dc5298b 5760 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5761 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5762 struct intel_pch_pll *pll;
4b645f14 5763
7429e9d4 5764 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5765 if (has_reduced_clock)
7429e9d4 5766 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5767
7429e9d4 5768 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5769 &fp, &reduced_clock,
5770 has_reduced_clock ? &fp2 : NULL);
5771
ee7b9f93
JB		 5772 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5773 if (pll == NULL) {
84f44ce7
VS		 5774 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5775 pipe_name(pipe));
4b645f14
JB		 5776 return -EINVAL;
5777 }
ee7b9f93
JB		 5778 } else
5779 intel_put_pch_pll(intel_crtc);
79e53945 5780
03afc4a2
DV		 5781 if (intel_crtc->config.has_dp_encoder)
5782 intel_dp_set_m_n(intel_crtc);
79e53945 5783
dafd226c
DV		 5784 for_each_encoder_on_crtc(dev, crtc, encoder)
5785 if (encoder->pre_pll_enable)
5786 encoder->pre_pll_enable(encoder);
79e53945 5787
ee7b9f93
JB		 5788 if (intel_crtc->pch_pll) {
5789 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5790
32f9d658 5791 /* Wait for the clocks to stabilize. */
ee7b9f93 5792 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5793 udelay(150);
5794
8febb297
EA		 5795 /* The pixel multiplier can only be updated once the
5796 * DPLL is enabled and the clocks are stable.
5797 *
5798 * So write it again.
5799 */
ee7b9f93 5800 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5801 }
79e53945 5802
5eddb70b 5803 intel_crtc->lowfreq_avail = false;
ee7b9f93 5804 if (intel_crtc->pch_pll) {
4b645f14 5805 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5806 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5807 intel_crtc->lowfreq_avail = true;
4b645f14 5808 } else {
ee7b9f93 5809 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5810 }
5811 }
5812
8a654f3b 5813 intel_set_pipe_timings(intel_crtc);
5eddb70b 5814
ca3a0ff8 5815 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5816 intel_cpu_transcoder_set_m_n(intel_crtc,
5817 &intel_crtc->config.fdi_m_n);
5818 }
2c07245f 5819
ebfd86fd
DV		 5820 if (IS_IVYBRIDGE(dev))
5821 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5822
6ff93609 5823 ironlake_set_pipeconf(crtc);
79e53945 5824
a1f9e77e
PZ		 5825 /* Set up the display plane register */
5826 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5827 POSTING_READ(DSPCNTR(plane));
79e53945 5828
94352cf9 5829 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5830
5831 intel_update_watermarks(dev);
5832
1857e1da 5833 return ret;
79e53945
JB		 5834}
5835
72419203
DV		 5836static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5837 struct intel_crtc_config *pipe_config)
5838{
5839 struct drm_device *dev = crtc->base.dev;
5840 struct drm_i915_private *dev_priv = dev->dev_private;
5841 enum transcoder transcoder = pipe_config->cpu_transcoder;
5842
5843 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5844 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5845 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5846 & ~TU_SIZE_MASK;
5847 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5848 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5849 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5850}
5851
2fa2fe9a
DV		 5852static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5853 struct intel_crtc_config *pipe_config)
5854{
5855 struct drm_device *dev = crtc->base.dev;
5856 struct drm_i915_private *dev_priv = dev->dev_private;
5857 uint32_t tmp;
5858
5859 tmp = I915_READ(PF_CTL(crtc->pipe));
5860
5861 if (tmp & PF_ENABLE) {
5862 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5863 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5864
5865 /* We currently do not free assignements of panel fitters on
5866 * ivb/hsw (since we don't use the higher upscaling modes which
5867 * differentiates them) so just WARN about this case for now. */
5868 if (IS_GEN7(dev)) {
5869 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5870 PF_PIPE_SEL_IVB(crtc->pipe));
5871 }
2fa2fe9a
DV		 5872 }
5873}
5874
0e8ffe1b
DV		 5875static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5876 struct intel_crtc_config *pipe_config)
5877{
5878 struct drm_device *dev = crtc->base.dev;
5879 struct drm_i915_private *dev_priv = dev->dev_private;
5880 uint32_t tmp;
5881
eccb140b
DV		 5882 pipe_config->cpu_transcoder = crtc->pipe;
5883
0e8ffe1b
DV		 5884 tmp = I915_READ(PIPECONF(crtc->pipe));
5885 if (!(tmp & PIPECONF_ENABLE))
5886 return false;
5887
ab9412ba 5888 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5889 pipe_config->has_pch_encoder = true;
5890
627eb5a3
DV		 5891 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5892 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5893 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5894
5895 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241
DV		 5896
5897 /* XXX: Can't properly read out the pch dpll pixel multiplier
5898 * since we don't have state tracking for pch clocks yet. */
5899 pipe_config->pixel_multiplier = 1;
5900 } else {
5901 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5902 }
5903
1bd1bd80
DV		 5904 intel_get_pipe_timings(crtc, pipe_config);
5905
2fa2fe9a
DV		 5906 ironlake_get_pfit_config(crtc, pipe_config);
5907
0e8ffe1b
DV		 5908 return true;
5909}
5910
d6dd9eb1
DV		 5911static void haswell_modeset_global_resources(struct drm_device *dev)
5912{
d6dd9eb1
DV		 5913 bool enable = false;
5914 struct intel_crtc *crtc;
d6dd9eb1
DV		 5915
5916 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5917 if (!crtc->base.enabled)
5918 continue;
d6dd9eb1 5919
e7a639c4
DV		 5920 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5921 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5922 enable = true;
5923 }
5924
d6dd9eb1
DV		 5925 intel_set_power_well(dev, enable);
5926}
5927
09b4ddf9 5928static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5929 int x, int y,
5930 struct drm_framebuffer *fb)
5931{
5932 struct drm_device *dev = crtc->dev;
5933 struct drm_i915_private *dev_priv = dev->dev_private;
5934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5935 int plane = intel_crtc->plane;
09b4ddf9 5936 int ret;
09b4ddf9 5937
ff9a6750 5938 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5939 return -EINVAL;
5940
09b4ddf9
PZ		 5941 /* Ensure that the cursor is valid for the new mode before changing... */
5942 intel_crtc_update_cursor(crtc, true);
5943
03afc4a2
DV		 5944 if (intel_crtc->config.has_dp_encoder)
5945 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5946
5947 intel_crtc->lowfreq_avail = false;
09b4ddf9 5948
8a654f3b 5949 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5950
ca3a0ff8 5951 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5952 intel_cpu_transcoder_set_m_n(intel_crtc,
5953 &intel_crtc->config.fdi_m_n);
5954 }
09b4ddf9 5955
6ff93609 5956 haswell_set_pipeconf(crtc);
09b4ddf9 5957
50f3b016 5958 intel_set_pipe_csc(crtc);
86d3efce 5959
09b4ddf9 5960 /* Set up the display plane register */
86d3efce 5961 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5962 POSTING_READ(DSPCNTR(plane));
5963
5964 ret = intel_pipe_set_base(crtc, x, y, fb);
5965
5966 intel_update_watermarks(dev);
5967
1f803ee5 5968 return ret;
79e53945
JB		 5969}
5970
0e8ffe1b
DV		 5971static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5972 struct intel_crtc_config *pipe_config)
5973{
5974 struct drm_device *dev = crtc->base.dev;
5975 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5976 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5977 uint32_t tmp;
5978
eccb140b
DV		 5979 pipe_config->cpu_transcoder = crtc->pipe;
5980 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5981 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5982 enum pipe trans_edp_pipe;
5983 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5984 default:
5985 WARN(1, "unknown pipe linked to edp transcoder\n");
5986 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5987 case TRANS_DDI_EDP_INPUT_A_ON:
5988 trans_edp_pipe = PIPE_A;
5989 break;
5990 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5991 trans_edp_pipe = PIPE_B;
5992 break;
5993 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5994 trans_edp_pipe = PIPE_C;
5995 break;
5996 }
5997
5998 if (trans_edp_pipe == crtc->pipe)
5999 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6000 }
6001
b97186f0 6002 if (!intel_display_power_enabled(dev,
eccb140b 6003 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6004 return false;
6005
eccb140b 6006 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6007 if (!(tmp & PIPECONF_ENABLE))
6008 return false;
6009
88adfff1 6010 /*
f196e6be 6011 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6012 * DDI E. So just check whether this pipe is wired to DDI E and whether
6013 * the PCH transcoder is on.
6014 */
eccb140b 6015 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6016 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6017 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6018 pipe_config->has_pch_encoder = true;
6019
627eb5a3
DV		 6020 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6021 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6022 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6023
6024 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6025 }
6026
1bd1bd80
DV		 6027 intel_get_pipe_timings(crtc, pipe_config);
6028
2fa2fe9a
DV		 6029 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6030 if (intel_display_power_enabled(dev, pfit_domain))
6031 ironlake_get_pfit_config(crtc, pipe_config);
6032
42db64ef
PZ		 6033 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6034 (I915_READ(IPS_CTL) & IPS_ENABLE);
6035
6c49f241
DV		 6036 pipe_config->pixel_multiplier = 1;
6037
0e8ffe1b
DV		 6038 return true;
6039}
6040
f564048e 6041static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6042 int x, int y,
94352cf9 6043 struct drm_framebuffer *fb)
f564048e
EA		 6044{
6045 struct drm_device *dev = crtc->dev;
6046 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6047 struct drm_encoder_helper_funcs *encoder_funcs;
6048 struct intel_encoder *encoder;
0b701d27 6049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6050 struct drm_display_mode *adjusted_mode =
6051 &intel_crtc->config.adjusted_mode;
6052 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6053 int pipe = intel_crtc->pipe;
f564048e
EA		 6054 int ret;
6055
0b701d27 6056 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6057
b8cecdf5
DV		 6058 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6059
79e53945 6060 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6061
9256aa19
DV		 6062 if (ret != 0)
6063 return ret;
6064
6065 for_each_encoder_on_crtc(dev, crtc, encoder) {
6066 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6067 encoder->base.base.id,
6068 drm_get_encoder_name(&encoder->base),
6069 mode->base.id, mode->name);
6cc5f341
DV		 6070 if (encoder->mode_set) {
6071 encoder->mode_set(encoder);
6072 } else {
6073 encoder_funcs = encoder->base.helper_private;
6074 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6075 }
9256aa19
DV		 6076 }
6077
6078 return 0;
79e53945
JB		 6079}
6080
3a9627f4
WF		 6081static bool intel_eld_uptodate(struct drm_connector *connector,
6082 int reg_eldv, uint32_t bits_eldv,
6083 int reg_elda, uint32_t bits_elda,
6084 int reg_edid)
6085{
6086 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6087 uint8_t *eld = connector->eld;
6088 uint32_t i;
6089
6090 i = I915_READ(reg_eldv);
6091 i &= bits_eldv;
6092
6093 if (!eld[0])
6094 return !i;
6095
6096 if (!i)
6097 return false;
6098
6099 i = I915_READ(reg_elda);
6100 i &= ~bits_elda;
6101 I915_WRITE(reg_elda, i);
6102
6103 for (i = 0; i < eld[2]; i++)
6104 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6105 return false;
6106
6107 return true;
6108}
6109
e0dac65e
WF		 6110static void g4x_write_eld(struct drm_connector *connector,
6111 struct drm_crtc *crtc)
6112{
6113 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6114 uint8_t *eld = connector->eld;
6115 uint32_t eldv;
6116 uint32_t len;
6117 uint32_t i;
6118
6119 i = I915_READ(G4X_AUD_VID_DID);
6120
6121 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6122 eldv = G4X_ELDV_DEVCL_DEVBLC;
6123 else
6124 eldv = G4X_ELDV_DEVCTG;
6125
3a9627f4
WF		 6126 if (intel_eld_uptodate(connector,
6127 G4X_AUD_CNTL_ST, eldv,
6128 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6129 G4X_HDMIW_HDMIEDID))
6130 return;
6131
e0dac65e
WF		 6132 i = I915_READ(G4X_AUD_CNTL_ST);
6133 i &= ~(eldv | G4X_ELD_ADDR);
6134 len = (i >> 9) & 0x1f; /* ELD buffer size */
6135 I915_WRITE(G4X_AUD_CNTL_ST, i);
6136
6137 if (!eld[0])
6138 return;
6139
6140 len = min_t(uint8_t, eld[2], len);
6141 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6142 for (i = 0; i < len; i++)
6143 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6144
6145 i = I915_READ(G4X_AUD_CNTL_ST);
6146 i |= eldv;
6147 I915_WRITE(G4X_AUD_CNTL_ST, i);
6148}
6149
83358c85
WX		 6150static void haswell_write_eld(struct drm_connector *connector,
6151 struct drm_crtc *crtc)
6152{
6153 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6154 uint8_t *eld = connector->eld;
6155 struct drm_device *dev = crtc->dev;
7b9f35a6 6156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6157 uint32_t eldv;
6158 uint32_t i;
6159 int len;
6160 int pipe = to_intel_crtc(crtc)->pipe;
6161 int tmp;
6162
6163 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6164 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6165 int aud_config = HSW_AUD_CFG(pipe);
6166 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6167
6168
6169 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6170
6171 /* Audio output enable */
6172 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6173 tmp = I915_READ(aud_cntrl_st2);
6174 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6175 I915_WRITE(aud_cntrl_st2, tmp);
6176
6177 /* Wait for 1 vertical blank */
6178 intel_wait_for_vblank(dev, pipe);
6179
6180 /* Set ELD valid state */
6181 tmp = I915_READ(aud_cntrl_st2);
6182 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6183 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6184 I915_WRITE(aud_cntrl_st2, tmp);
6185 tmp = I915_READ(aud_cntrl_st2);
6186 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6187
6188 /* Enable HDMI mode */
6189 tmp = I915_READ(aud_config);
6190 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6191 /* clear N_programing_enable and N_value_index */
6192 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6193 I915_WRITE(aud_config, tmp);
6194
6195 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6196
6197 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6198 intel_crtc->eld_vld = true;
83358c85
WX		 6199
6200 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6201 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6202 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6203 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6204 } else
6205 I915_WRITE(aud_config, 0);
6206
6207 if (intel_eld_uptodate(connector,
6208 aud_cntrl_st2, eldv,
6209 aud_cntl_st, IBX_ELD_ADDRESS,
6210 hdmiw_hdmiedid))
6211 return;
6212
6213 i = I915_READ(aud_cntrl_st2);
6214 i &= ~eldv;
6215 I915_WRITE(aud_cntrl_st2, i);
6216
6217 if (!eld[0])
6218 return;
6219
6220 i = I915_READ(aud_cntl_st);
6221 i &= ~IBX_ELD_ADDRESS;
6222 I915_WRITE(aud_cntl_st, i);
6223 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6224 DRM_DEBUG_DRIVER("port num:%d\n", i);
6225
6226 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6227 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6228 for (i = 0; i < len; i++)
6229 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6230
6231 i = I915_READ(aud_cntrl_st2);
6232 i |= eldv;
6233 I915_WRITE(aud_cntrl_st2, i);
6234
6235}
6236
e0dac65e
WF		 6237static void ironlake_write_eld(struct drm_connector *connector,
6238 struct drm_crtc *crtc)
6239{
6240 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6241 uint8_t *eld = connector->eld;
6242 uint32_t eldv;
6243 uint32_t i;
6244 int len;
6245 int hdmiw_hdmiedid;
b6daa025 6246 int aud_config;
e0dac65e
WF		 6247 int aud_cntl_st;
6248 int aud_cntrl_st2;
9b138a83 6249 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6250
b3f33cbf 6251 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6252 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6253 aud_config = IBX_AUD_CFG(pipe);
6254 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6255 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6256 } else {
9b138a83
WX		 6257 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6258 aud_config = CPT_AUD_CFG(pipe);
6259 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6260 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6261 }
6262
9b138a83 6263 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6264
6265 i = I915_READ(aud_cntl_st);
9b138a83 6266 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6267 if (!i) {
6268 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6269 /* operate blindly on all ports */
1202b4c6
WF		 6270 eldv = IBX_ELD_VALIDB;
6271 eldv |= IBX_ELD_VALIDB << 4;
6272 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6273 } else {
2582a850 6274 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6275 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6276 }
6277
3a9627f4
WF		 6278 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6279 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6280 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6281 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6282 } else
6283 I915_WRITE(aud_config, 0);
e0dac65e 6284
3a9627f4
WF		 6285 if (intel_eld_uptodate(connector,
6286 aud_cntrl_st2, eldv,
6287 aud_cntl_st, IBX_ELD_ADDRESS,
6288 hdmiw_hdmiedid))
6289 return;
6290
e0dac65e
WF		 6291 i = I915_READ(aud_cntrl_st2);
6292 i &= ~eldv;
6293 I915_WRITE(aud_cntrl_st2, i);
6294
6295 if (!eld[0])
6296 return;
6297
e0dac65e 6298 i = I915_READ(aud_cntl_st);
1202b4c6 6299 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6300 I915_WRITE(aud_cntl_st, i);
6301
6302 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6303 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6304 for (i = 0; i < len; i++)
6305 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6306
6307 i = I915_READ(aud_cntrl_st2);
6308 i |= eldv;
6309 I915_WRITE(aud_cntrl_st2, i);
6310}
6311
6312void intel_write_eld(struct drm_encoder *encoder,
6313 struct drm_display_mode *mode)
6314{
6315 struct drm_crtc *crtc = encoder->crtc;
6316 struct drm_connector *connector;
6317 struct drm_device *dev = encoder->dev;
6318 struct drm_i915_private *dev_priv = dev->dev_private;
6319
6320 connector = drm_select_eld(encoder, mode);
6321 if (!connector)
6322 return;
6323
6324 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6325 connector->base.id,
6326 drm_get_connector_name(connector),
6327 connector->encoder->base.id,
6328 drm_get_encoder_name(connector->encoder));
6329
6330 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6331
6332 if (dev_priv->display.write_eld)
6333 dev_priv->display.write_eld(connector, crtc);
6334}
6335
79e53945
JB		 6336/** Loads the palette/gamma unit for the CRTC with the prepared values */
6337void intel_crtc_load_lut(struct drm_crtc *crtc)
6338{
6339 struct drm_device *dev = crtc->dev;
6340 struct drm_i915_private *dev_priv = dev->dev_private;
6341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6342 enum pipe pipe = intel_crtc->pipe;
6343 int palreg = PALETTE(pipe);
79e53945 6344 int i;
42db64ef 6345 bool reenable_ips = false;
79e53945
JB		 6346
6347 /* The clocks have to be on to load the palette. */
aed3f09d 6348 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6349 return;
6350
14420bd0
VS		 6351 if (!HAS_PCH_SPLIT(dev_priv->dev))
6352 assert_pll_enabled(dev_priv, pipe);
6353
f2b115e6 6354 /* use legacy palette for Ironlake */
bad720ff 6355 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6356 palreg = LGC_PALETTE(pipe);
6357
6358 /* Workaround : Do not read or write the pipe palette/gamma data while
6359 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6360 */
6361 if (intel_crtc->config.ips_enabled &&
6362 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6363 GAMMA_MODE_MODE_SPLIT)) {
6364 hsw_disable_ips(intel_crtc);
6365 reenable_ips = true;
6366 }
2c07245f 6367
79e53945
JB		 6368 for (i = 0; i < 256; i++) {
6369 I915_WRITE(palreg + 4 * i,
6370 (intel_crtc->lut_r[i] << 16) |
6371 (intel_crtc->lut_g[i] << 8) |
6372 intel_crtc->lut_b[i]);
6373 }
42db64ef
PZ		 6374
6375 if (reenable_ips)
6376 hsw_enable_ips(intel_crtc);
79e53945
JB		 6377}
6378
560b85bb
CW		 6379static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6380{
6381 struct drm_device *dev = crtc->dev;
6382 struct drm_i915_private *dev_priv = dev->dev_private;
6383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6384 bool visible = base != 0;
6385 u32 cntl;
6386
6387 if (intel_crtc->cursor_visible == visible)
6388 return;
6389
9db4a9c7 6390 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6391 if (visible) {
6392 /* On these chipsets we can only modify the base whilst
6393 * the cursor is disabled.
6394 */
9db4a9c7 6395 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6396
6397 cntl &= ~(CURSOR_FORMAT_MASK);
6398 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6399 cntl |= CURSOR_ENABLE |
6400 CURSOR_GAMMA_ENABLE |
6401 CURSOR_FORMAT_ARGB;
6402 } else
6403 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6404 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6405
6406 intel_crtc->cursor_visible = visible;
6407}
6408
6409static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6410{
6411 struct drm_device *dev = crtc->dev;
6412 struct drm_i915_private *dev_priv = dev->dev_private;
6413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6414 int pipe = intel_crtc->pipe;
6415 bool visible = base != 0;
6416
6417 if (intel_crtc->cursor_visible != visible) {
548f245b 6418 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6419 if (base) {
6420 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6421 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6422 cntl |= pipe << 28; /* Connect to correct pipe */
6423 } else {
6424 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6425 cntl |= CURSOR_MODE_DISABLE;
6426 }
9db4a9c7 6427 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6428
6429 intel_crtc->cursor_visible = visible;
6430 }
6431 /* and commit changes on next vblank */
9db4a9c7 6432 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6433}
6434
65a21cd6
JB		 6435static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6436{
6437 struct drm_device *dev = crtc->dev;
6438 struct drm_i915_private *dev_priv = dev->dev_private;
6439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6440 int pipe = intel_crtc->pipe;
6441 bool visible = base != 0;
6442
6443 if (intel_crtc->cursor_visible != visible) {
6444 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6445 if (base) {
6446 cntl &= ~CURSOR_MODE;
6447 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6448 } else {
6449 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6450 cntl |= CURSOR_MODE_DISABLE;
6451 }
86d3efce
VS		 6452 if (IS_HASWELL(dev))
6453 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6454 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6455
6456 intel_crtc->cursor_visible = visible;
6457 }
6458 /* and commit changes on next vblank */
6459 I915_WRITE(CURBASE_IVB(pipe), base);
6460}
6461
cda4b7d3 6462/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6463static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6464 bool on)
cda4b7d3
CW		 6465{
6466 struct drm_device *dev = crtc->dev;
6467 struct drm_i915_private *dev_priv = dev->dev_private;
6468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6469 int pipe = intel_crtc->pipe;
6470 int x = intel_crtc->cursor_x;
6471 int y = intel_crtc->cursor_y;
560b85bb 6472 u32 base, pos;
cda4b7d3
CW		 6473 bool visible;
6474
6475 pos = 0;
6476
6b383a7f 6477 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6478 base = intel_crtc->cursor_addr;
6479 if (x > (int) crtc->fb->width)
6480 base = 0;
6481
6482 if (y > (int) crtc->fb->height)
6483 base = 0;
6484 } else
6485 base = 0;
6486
6487 if (x < 0) {
6488 if (x + intel_crtc->cursor_width < 0)
6489 base = 0;
6490
6491 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6492 x = -x;
6493 }
6494 pos |= x << CURSOR_X_SHIFT;
6495
6496 if (y < 0) {
6497 if (y + intel_crtc->cursor_height < 0)
6498 base = 0;
6499
6500 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6501 y = -y;
6502 }
6503 pos |= y << CURSOR_Y_SHIFT;
6504
6505 visible = base != 0;
560b85bb 6506 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6507 return;
6508
0cd83aa9 6509 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6510 I915_WRITE(CURPOS_IVB(pipe), pos);
6511 ivb_update_cursor(crtc, base);
6512 } else {
6513 I915_WRITE(CURPOS(pipe), pos);
6514 if (IS_845G(dev) || IS_I865G(dev))
6515 i845_update_cursor(crtc, base);
6516 else
6517 i9xx_update_cursor(crtc, base);
6518 }
cda4b7d3
CW		 6519}
6520
79e53945 6521static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6522 struct drm_file *file,
79e53945
JB		 6523 uint32_t handle,
6524 uint32_t width, uint32_t height)
6525{
6526 struct drm_device *dev = crtc->dev;
6527 struct drm_i915_private *dev_priv = dev->dev_private;
6528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6529 struct drm_i915_gem_object *obj;
cda4b7d3 6530 uint32_t addr;
3f8bc370 6531 int ret;
79e53945 6532
79e53945
JB		 6533 /* if we want to turn off the cursor ignore width and height */
6534 if (!handle) {
28c97730 6535 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6536 addr = 0;
05394f39 6537 obj = NULL;
5004417d 6538 mutex_lock(&dev->struct_mutex);
3f8bc370 6539 goto finish;
79e53945
JB		 6540 }
6541
6542 /* Currently we only support 64x64 cursors */
6543 if (width != 64 || height != 64) {
6544 DRM_ERROR("we currently only support 64x64 cursors\n");
6545 return -EINVAL;
6546 }
6547
05394f39 6548 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6549 if (&obj->base == NULL)
79e53945
JB		 6550 return -ENOENT;
6551
05394f39 6552 if (obj->base.size < width * height * 4) {
79e53945 6553 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6554 ret = -ENOMEM;
6555 goto fail;
79e53945
JB		 6556 }
6557
71acb5eb 6558 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6559 mutex_lock(&dev->struct_mutex);
b295d1b6 6560 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6561 unsigned alignment;
6562
d9e86c0e
CW		 6563 if (obj->tiling_mode) {
6564 DRM_ERROR("cursor cannot be tiled\n");
6565 ret = -EINVAL;
6566 goto fail_locked;
6567 }
6568
693db184
CW		 6569 /* Note that the w/a also requires 2 PTE of padding following
6570 * the bo. We currently fill all unused PTE with the shadow
6571 * page and so we should always have valid PTE following the
6572 * cursor preventing the VT-d warning.
6573 */
6574 alignment = 0;
6575 if (need_vtd_wa(dev))
6576 alignment = 64*1024;
6577
6578 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6579 if (ret) {
6580 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6581 goto fail_locked;
e7b526bb
CW		 6582 }
6583
d9e86c0e
CW		 6584 ret = i915_gem_object_put_fence(obj);
6585 if (ret) {
2da3b9b9 6586 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6587 goto fail_unpin;
6588 }
6589
05394f39 6590 addr = obj->gtt_offset;
71acb5eb 6591 } else {
6eeefaf3 6592 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6593 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6594 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6595 align);
71acb5eb
DA		 6596 if (ret) {
6597 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6598 goto fail_locked;
71acb5eb 6599 }
05394f39 6600 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6601 }
6602
a6c45cf0 6603 if (IS_GEN2(dev))
14b60391
JB		 6604 I915_WRITE(CURSIZE, (height << 12) | width);
6605
3f8bc370 6606 finish:
3f8bc370 6607 if (intel_crtc->cursor_bo) {
b295d1b6 6608 if (dev_priv->info->cursor_needs_physical) {
05394f39 6609 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6610 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6611 } else
6612 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6613 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6614 }
80824003 6615
7f9872e0 6616 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6617
6618 intel_crtc->cursor_addr = addr;
05394f39 6619 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6620 intel_crtc->cursor_width = width;
6621 intel_crtc->cursor_height = height;
6622
40ccc72b 6623 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6624
79e53945 6625 return 0;
e7b526bb 6626fail_unpin:
05394f39 6627 i915_gem_object_unpin(obj);
7f9872e0 6628fail_locked:
34b8686e 6629 mutex_unlock(&dev->struct_mutex);
bc9025bd 6630fail:
05394f39 6631 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6632 return ret;
79e53945
JB		 6633}
6634
6635static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6636{
79e53945 6637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6638
cda4b7d3
CW		 6639 intel_crtc->cursor_x = x;
6640 intel_crtc->cursor_y = y;
652c393a 6641
40ccc72b 6642 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6643
6644 return 0;
6645}
6646
6647/** Sets the color ramps on behalf of RandR */
6648void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6649 u16 blue, int regno)
6650{
6651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6652
6653 intel_crtc->lut_r[regno] = red >> 8;
6654 intel_crtc->lut_g[regno] = green >> 8;
6655 intel_crtc->lut_b[regno] = blue >> 8;
6656}
6657
b8c00ac5
DA		 6658void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6659 u16 *blue, int regno)
6660{
6661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6662
6663 *red = intel_crtc->lut_r[regno] << 8;
6664 *green = intel_crtc->lut_g[regno] << 8;
6665 *blue = intel_crtc->lut_b[regno] << 8;
6666}
6667
79e53945 6668static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6669 u16 *blue, uint32_t start, uint32_t size)
79e53945 6670{
7203425a 6671 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6673
7203425a 6674 for (i = start; i < end; i++) {
79e53945
JB		 6675 intel_crtc->lut_r[i] = red[i] >> 8;
6676 intel_crtc->lut_g[i] = green[i] >> 8;
6677 intel_crtc->lut_b[i] = blue[i] >> 8;
6678 }
6679
6680 intel_crtc_load_lut(crtc);
6681}
6682
79e53945
JB		 6683/* VESA 640x480x72Hz mode to set on the pipe */
6684static struct drm_display_mode load_detect_mode = {
6685 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6686 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6687};
6688
d2dff872
CW		 6689static struct drm_framebuffer *
6690intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6691 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6692 struct drm_i915_gem_object *obj)
6693{
6694 struct intel_framebuffer *intel_fb;
6695 int ret;
6696
6697 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6698 if (!intel_fb) {
6699 drm_gem_object_unreference_unlocked(&obj->base);
6700 return ERR_PTR(-ENOMEM);
6701 }
6702
6703 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6704 if (ret) {
6705 drm_gem_object_unreference_unlocked(&obj->base);
6706 kfree(intel_fb);
6707 return ERR_PTR(ret);
6708 }
6709
6710 return &intel_fb->base;
6711}
6712
6713static u32
6714intel_framebuffer_pitch_for_width(int width, int bpp)
6715{
6716 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6717 return ALIGN(pitch, 64);
6718}
6719
6720static u32
6721intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6722{
6723 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6724 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6725}
6726
6727static struct drm_framebuffer *
6728intel_framebuffer_create_for_mode(struct drm_device *dev,
6729 struct drm_display_mode *mode,
6730 int depth, int bpp)
6731{
6732 struct drm_i915_gem_object *obj;
0fed39bd 6733 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6734
6735 obj = i915_gem_alloc_object(dev,
6736 intel_framebuffer_size_for_mode(mode, bpp));
6737 if (obj == NULL)
6738 return ERR_PTR(-ENOMEM);
6739
6740 mode_cmd.width = mode->hdisplay;
6741 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6742 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6743 bpp);
5ca0c34a 6744 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6745
6746 return intel_framebuffer_create(dev, &mode_cmd, obj);
6747}
6748
6749static struct drm_framebuffer *
6750mode_fits_in_fbdev(struct drm_device *dev,
6751 struct drm_display_mode *mode)
6752{
6753 struct drm_i915_private *dev_priv = dev->dev_private;
6754 struct drm_i915_gem_object *obj;
6755 struct drm_framebuffer *fb;
6756
6757 if (dev_priv->fbdev == NULL)
6758 return NULL;
6759
6760 obj = dev_priv->fbdev->ifb.obj;
6761 if (obj == NULL)
6762 return NULL;
6763
6764 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6765 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6766 fb->bits_per_pixel))
d2dff872
CW		 6767 return NULL;
6768
01f2c773 6769 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6770 return NULL;
6771
6772 return fb;
6773}
6774
d2434ab7 6775bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6776 struct drm_display_mode *mode,
8261b191 6777 struct intel_load_detect_pipe *old)
79e53945
JB		 6778{
6779 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6780 struct intel_encoder *intel_encoder =
6781 intel_attached_encoder(connector);
79e53945 6782 struct drm_crtc *possible_crtc;
4ef69c7a 6783 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6784 struct drm_crtc *crtc = NULL;
6785 struct drm_device *dev = encoder->dev;
94352cf9 6786 struct drm_framebuffer *fb;
79e53945
JB		 6787 int i = -1;
6788
d2dff872
CW		 6789 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6790 connector->base.id, drm_get_connector_name(connector),
6791 encoder->base.id, drm_get_encoder_name(encoder));
6792
79e53945
JB		 6793 /*
6794 * Algorithm gets a little messy:
7a5e4805 6795 *
79e53945
JB		 6796 * - if the connector already has an assigned crtc, use it (but make
6797 * sure it's on first)
7a5e4805 6798 *
79e53945
JB		 6799 * - try to find the first unused crtc that can drive this connector,
6800 * and use that if we find one
79e53945
JB		 6801 */
6802
6803 /* See if we already have a CRTC for this connector */
6804 if (encoder->crtc) {
6805 crtc = encoder->crtc;
8261b191 6806
7b24056b
DV		 6807 mutex_lock(&crtc->mutex);
6808
24218aac 6809 old->dpms_mode = connector->dpms;
8261b191
CW		 6810 old->load_detect_temp = false;
6811
6812 /* Make sure the crtc and connector are running */
24218aac
DV		 6813 if (connector->dpms != DRM_MODE_DPMS_ON)
6814 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6815
7173188d 6816 return true;
79e53945
JB		 6817 }
6818
6819 /* Find an unused one (if possible) */
6820 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6821 i++;
6822 if (!(encoder->possible_crtcs & (1 << i)))
6823 continue;
6824 if (!possible_crtc->enabled) {
6825 crtc = possible_crtc;
6826 break;
6827 }
79e53945
JB		 6828 }
6829
6830 /*
6831 * If we didn't find an unused CRTC, don't use any.
6832 */
6833 if (!crtc) {
7173188d
CW		 6834 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6835 return false;
79e53945
JB		 6836 }
6837
7b24056b 6838 mutex_lock(&crtc->mutex);
fc303101
DV		 6839 intel_encoder->new_crtc = to_intel_crtc(crtc);
6840 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6841
6842 intel_crtc = to_intel_crtc(crtc);
24218aac 6843 old->dpms_mode = connector->dpms;
8261b191 6844 old->load_detect_temp = true;
d2dff872 6845 old->release_fb = NULL;
79e53945 6846
6492711d
CW		 6847 if (!mode)
6848 mode = &load_detect_mode;
79e53945 6849
d2dff872
CW		 6850 /* We need a framebuffer large enough to accommodate all accesses
6851 * that the plane may generate whilst we perform load detection.
6852 * We can not rely on the fbcon either being present (we get called
6853 * during its initialisation to detect all boot displays, or it may
6854 * not even exist) or that it is large enough to satisfy the
6855 * requested mode.
6856 */
94352cf9
DV		 6857 fb = mode_fits_in_fbdev(dev, mode);
6858 if (fb == NULL) {
d2dff872 6859 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6860 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6861 old->release_fb = fb;
d2dff872
CW		 6862 } else
6863 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6864 if (IS_ERR(fb)) {
d2dff872 6865 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6866 mutex_unlock(&crtc->mutex);
0e8b3d3e 6867 return false;
79e53945 6868 }
79e53945 6869
c0c36b94 6870 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6871 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6872 if (old->release_fb)
6873 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6874 mutex_unlock(&crtc->mutex);
0e8b3d3e 6875 return false;
79e53945 6876 }
7173188d 6877
79e53945 6878 /* let the connector get through one full cycle before testing */
9d0498a2 6879 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6880 return true;
79e53945
JB		 6881}
6882
d2434ab7 6883void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6884 struct intel_load_detect_pipe *old)
79e53945 6885{
d2434ab7
DV		 6886 struct intel_encoder *intel_encoder =
6887 intel_attached_encoder(connector);
4ef69c7a 6888 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6889 struct drm_crtc *crtc = encoder->crtc;
79e53945 6890
d2dff872
CW		 6891 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6892 connector->base.id, drm_get_connector_name(connector),
6893 encoder->base.id, drm_get_encoder_name(encoder));
6894
8261b191 6895 if (old->load_detect_temp) {
fc303101
DV		 6896 to_intel_connector(connector)->new_encoder = NULL;
6897 intel_encoder->new_crtc = NULL;
6898 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6899
36206361
DV		 6900 if (old->release_fb) {
6901 drm_framebuffer_unregister_private(old->release_fb);
6902 drm_framebuffer_unreference(old->release_fb);
6903 }
d2dff872 6904
67c96400 6905 mutex_unlock(&crtc->mutex);
0622a53c 6906 return;
79e53945
JB		 6907 }
6908
c751ce4f 6909 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6910 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6911 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6912
6913 mutex_unlock(&crtc->mutex);
79e53945
JB		 6914}
6915
6916/* Returns the clock of the currently programmed mode of the given pipe. */
6917static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6918{
6919 struct drm_i915_private *dev_priv = dev->dev_private;
6920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6921 int pipe = intel_crtc->pipe;
548f245b 6922 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6923 u32 fp;
6924 intel_clock_t clock;
6925
6926 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6927 fp = I915_READ(FP0(pipe));
79e53945 6928 else
39adb7a5 6929 fp = I915_READ(FP1(pipe));
79e53945
JB		 6930
6931 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6932 if (IS_PINEVIEW(dev)) {
6933 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6934 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6935 } else {
6936 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6937 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6938 }
6939
a6c45cf0 6940 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6941 if (IS_PINEVIEW(dev))
6942 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6943 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6944 else
6945 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6946 DPLL_FPA01_P1_POST_DIV_SHIFT);
6947
6948 switch (dpll & DPLL_MODE_MASK) {
6949 case DPLLB_MODE_DAC_SERIAL:
6950 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6951 5 : 10;
6952 break;
6953 case DPLLB_MODE_LVDS:
6954 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6955 7 : 14;
6956 break;
6957 default:
28c97730 6958 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6959 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6960 return 0;
6961 }
6962
ac58c3f0
DV		 6963 if (IS_PINEVIEW(dev))
6964 pineview_clock(96000, &clock);
6965 else
6966 i9xx_clock(96000, &clock);
79e53945
JB		 6967 } else {
6968 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6969
6970 if (is_lvds) {
6971 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6972 DPLL_FPA01_P1_POST_DIV_SHIFT);
6973 clock.p2 = 14;
6974
6975 if ((dpll & PLL_REF_INPUT_MASK) ==
6976 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6977 /* XXX: might not be 66MHz */
ac58c3f0 6978 i9xx_clock(66000, &clock);
79e53945 6979 } else
ac58c3f0 6980 i9xx_clock(48000, &clock);
79e53945
JB		 6981 } else {
6982 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6983 clock.p1 = 2;
6984 else {
6985 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6986 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6987 }
6988 if (dpll & PLL_P2_DIVIDE_BY_4)
6989 clock.p2 = 4;
6990 else
6991 clock.p2 = 2;
6992
ac58c3f0 6993 i9xx_clock(48000, &clock);
79e53945
JB		 6994 }
6995 }
6996
6997 /* XXX: It would be nice to validate the clocks, but we can't reuse
6998 * i830PllIsValid() because it relies on the xf86_config connector
6999 * configuration being accurate, which it isn't necessarily.
7000 */
7001
7002 return clock.dot;
7003}
7004
7005/** Returns the currently programmed mode of the given pipe. */
7006struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7007 struct drm_crtc *crtc)
7008{
548f245b 7009 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7011 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7012 struct drm_display_mode *mode;
fe2b8f9d
PZ		 7013 int htot = I915_READ(HTOTAL(cpu_transcoder));
7014 int hsync = I915_READ(HSYNC(cpu_transcoder));
7015 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7016 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7017
7018 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7019 if (!mode)
7020 return NULL;
7021
7022 mode->clock = intel_crtc_clock_get(dev, crtc);
7023 mode->hdisplay = (htot & 0xffff) + 1;
7024 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7025 mode->hsync_start = (hsync & 0xffff) + 1;
7026 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7027 mode->vdisplay = (vtot & 0xffff) + 1;
7028 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7029 mode->vsync_start = (vsync & 0xffff) + 1;
7030 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7031
7032 drm_mode_set_name(mode);
79e53945
JB		 7033
7034 return mode;
7035}
7036
3dec0095 7037static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7038{
7039 struct drm_device *dev = crtc->dev;
7040 drm_i915_private_t *dev_priv = dev->dev_private;
7041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7042 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7043 int dpll_reg = DPLL(pipe);
7044 int dpll;
652c393a 7045
bad720ff 7046 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7047 return;
7048
7049 if (!dev_priv->lvds_downclock_avail)
7050 return;
7051
dbdc6479 7052 dpll = I915_READ(dpll_reg);
652c393a 7053 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7054 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7055
8ac5a6d5 7056 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7057
7058 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7059 I915_WRITE(dpll_reg, dpll);
9d0498a2 7060 intel_wait_for_vblank(dev, pipe);
dbdc6479 7061
652c393a
JB		 7062 dpll = I915_READ(dpll_reg);
7063 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7064 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7065 }
652c393a
JB		 7066}
7067
7068static void intel_decrease_pllclock(struct drm_crtc *crtc)
7069{
7070 struct drm_device *dev = crtc->dev;
7071 drm_i915_private_t *dev_priv = dev->dev_private;
7072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7073
bad720ff 7074 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7075 return;
7076
7077 if (!dev_priv->lvds_downclock_avail)
7078 return;
7079
7080 /*
7081 * Since this is called by a timer, we should never get here in
7082 * the manual case.
7083 */
7084 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7085 int pipe = intel_crtc->pipe;
7086 int dpll_reg = DPLL(pipe);
7087 int dpll;
f6e5b160 7088
44d98a61 7089 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7090
8ac5a6d5 7091 assert_panel_unlocked(dev_priv, pipe);
652c393a 7092
dc257cf1 7093 dpll = I915_READ(dpll_reg);
652c393a
JB		 7094 dpll |= DISPLAY_RATE_SELECT_FPA1;
7095 I915_WRITE(dpll_reg, dpll);
9d0498a2 7096 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7097 dpll = I915_READ(dpll_reg);
7098 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7099 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7100 }
7101
7102}
7103
f047e395
CW		 7104void intel_mark_busy(struct drm_device *dev)
7105{
f047e395
CW		 7106 i915_update_gfx_val(dev->dev_private);
7107}
7108
7109void intel_mark_idle(struct drm_device *dev)
652c393a 7110{
652c393a 7111 struct drm_crtc *crtc;
652c393a
JB		 7112
7113 if (!i915_powersave)
7114 return;
7115
652c393a 7116 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7117 if (!crtc->fb)
7118 continue;
7119
725a5b54 7120 intel_decrease_pllclock(crtc);
652c393a 7121 }
652c393a
JB		 7122}
7123
c65355bb
CW		 7124void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7125 struct intel_ring_buffer *ring)
652c393a 7126{
f047e395
CW		 7127 struct drm_device *dev = obj->base.dev;
7128 struct drm_crtc *crtc;
652c393a 7129
f047e395 7130 if (!i915_powersave)
acb87dfb
CW		 7131 return;
7132
652c393a
JB		 7133 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7134 if (!crtc->fb)
7135 continue;
7136
c65355bb
CW		 7137 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7138 continue;
7139
7140 intel_increase_pllclock(crtc);
7141 if (ring && intel_fbc_enabled(dev))
7142 ring->fbc_dirty = true;
652c393a
JB		 7143 }
7144}
7145
79e53945
JB		 7146static void intel_crtc_destroy(struct drm_crtc *crtc)
7147{
7148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7149 struct drm_device *dev = crtc->dev;
7150 struct intel_unpin_work *work;
7151 unsigned long flags;
7152
7153 spin_lock_irqsave(&dev->event_lock, flags);
7154 work = intel_crtc->unpin_work;
7155 intel_crtc->unpin_work = NULL;
7156 spin_unlock_irqrestore(&dev->event_lock, flags);
7157
7158 if (work) {
7159 cancel_work_sync(&work->work);
7160 kfree(work);
7161 }
79e53945 7162
40ccc72b
MK		 7163 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7164
79e53945 7165 drm_crtc_cleanup(crtc);
67e77c5a 7166
79e53945
JB		 7167 kfree(intel_crtc);
7168}
7169
6b95a207
KH		 7170static void intel_unpin_work_fn(struct work_struct *__work)
7171{
7172 struct intel_unpin_work *work =
7173 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7174 struct drm_device *dev = work->crtc->dev;
6b95a207 7175
b4a98e57 7176 mutex_lock(&dev->struct_mutex);
1690e1eb 7177 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7178 drm_gem_object_unreference(&work->pending_flip_obj->base);
7179 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7180
b4a98e57
CW		 7181 intel_update_fbc(dev);
7182 mutex_unlock(&dev->struct_mutex);
7183
7184 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7185 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7186
6b95a207
KH		 7187 kfree(work);
7188}
7189
1afe3e9d 7190static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7191 struct drm_crtc *crtc)
6b95a207
KH		 7192{
7193 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7195 struct intel_unpin_work *work;
6b95a207
KH		 7196 unsigned long flags;
7197
7198 /* Ignore early vblank irqs */
7199 if (intel_crtc == NULL)
7200 return;
7201
7202 spin_lock_irqsave(&dev->event_lock, flags);
7203 work = intel_crtc->unpin_work;
e7d841ca
CW		 7204
7205 /* Ensure we don't miss a work->pending update ... */
7206 smp_rmb();
7207
7208 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7209 spin_unlock_irqrestore(&dev->event_lock, flags);
7210 return;
7211 }
7212
e7d841ca
CW		 7213 /* and that the unpin work is consistent wrt ->pending. */
7214 smp_rmb();
7215
6b95a207 7216 intel_crtc->unpin_work = NULL;
6b95a207 7217
45a066eb
RC		 7218 if (work->event)
7219 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7220
0af7e4df
MK		 7221 drm_vblank_put(dev, intel_crtc->pipe);
7222
6b95a207
KH		 7223 spin_unlock_irqrestore(&dev->event_lock, flags);
7224
2c10d571 7225 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7226
7227 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7228
7229 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7230}
7231
1afe3e9d
JB		 7232void intel_finish_page_flip(struct drm_device *dev, int pipe)
7233{
7234 drm_i915_private_t *dev_priv = dev->dev_private;
7235 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7236
49b14a5c 7237 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7238}
7239
7240void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7241{
7242 drm_i915_private_t *dev_priv = dev->dev_private;
7243 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7244
49b14a5c 7245 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7246}
7247
6b95a207
KH		 7248void intel_prepare_page_flip(struct drm_device *dev, int plane)
7249{
7250 drm_i915_private_t *dev_priv = dev->dev_private;
7251 struct intel_crtc *intel_crtc =
7252 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7253 unsigned long flags;
7254
e7d841ca
CW		 7255 /* NB: An MMIO update of the plane base pointer will also
7256 * generate a page-flip completion irq, i.e. every modeset
7257 * is also accompanied by a spurious intel_prepare_page_flip().
7258 */
6b95a207 7259 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7260 if (intel_crtc->unpin_work)
7261 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7262 spin_unlock_irqrestore(&dev->event_lock, flags);
7263}
7264
e7d841ca
CW		 7265inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7266{
7267 /* Ensure that the work item is consistent when activating it ... */
7268 smp_wmb();
7269 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7270 /* and that it is marked active as soon as the irq could fire. */
7271 smp_wmb();
7272}
7273
8c9f3aaf
JB		 7274static int intel_gen2_queue_flip(struct drm_device *dev,
7275 struct drm_crtc *crtc,
7276 struct drm_framebuffer *fb,
7277 struct drm_i915_gem_object *obj)
7278{
7279 struct drm_i915_private *dev_priv = dev->dev_private;
7280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7281 u32 flip_mask;
6d90c952 7282 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7283 int ret;
7284
6d90c952 7285 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7286 if (ret)
83d4092b 7287 goto err;
8c9f3aaf 7288
6d90c952 7289 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7290 if (ret)
83d4092b 7291 goto err_unpin;
8c9f3aaf
JB		 7292
7293 /* Can't queue multiple flips, so wait for the previous
7294 * one to finish before executing the next.
7295 */
7296 if (intel_crtc->plane)
7297 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7298 else
7299 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7300 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7301 intel_ring_emit(ring, MI_NOOP);
7302 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7303 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7304 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7305 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7306 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7307
7308 intel_mark_page_flip_active(intel_crtc);
6d90c952 7309 intel_ring_advance(ring);
83d4092b
CW		 7310 return 0;
7311
7312err_unpin:
7313 intel_unpin_fb_obj(obj);
7314err:
8c9f3aaf
JB		 7315 return ret;
7316}
7317
7318static int intel_gen3_queue_flip(struct drm_device *dev,
7319 struct drm_crtc *crtc,
7320 struct drm_framebuffer *fb,
7321 struct drm_i915_gem_object *obj)
7322{
7323 struct drm_i915_private *dev_priv = dev->dev_private;
7324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7325 u32 flip_mask;
6d90c952 7326 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7327 int ret;
7328
6d90c952 7329 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7330 if (ret)
83d4092b 7331 goto err;
8c9f3aaf 7332
6d90c952 7333 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7334 if (ret)
83d4092b 7335 goto err_unpin;
8c9f3aaf
JB		 7336
7337 if (intel_crtc->plane)
7338 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7339 else
7340 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7341 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7342 intel_ring_emit(ring, MI_NOOP);
7343 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7344 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7345 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7346 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7347 intel_ring_emit(ring, MI_NOOP);
7348
e7d841ca 7349 intel_mark_page_flip_active(intel_crtc);
6d90c952 7350 intel_ring_advance(ring);
83d4092b
CW		 7351 return 0;
7352
7353err_unpin:
7354 intel_unpin_fb_obj(obj);
7355err:
8c9f3aaf
JB		 7356 return ret;
7357}
7358
7359static int intel_gen4_queue_flip(struct drm_device *dev,
7360 struct drm_crtc *crtc,
7361 struct drm_framebuffer *fb,
7362 struct drm_i915_gem_object *obj)
7363{
7364 struct drm_i915_private *dev_priv = dev->dev_private;
7365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7366 uint32_t pf, pipesrc;
6d90c952 7367 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7368 int ret;
7369
6d90c952 7370 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7371 if (ret)
83d4092b 7372 goto err;
8c9f3aaf 7373
6d90c952 7374 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7375 if (ret)
83d4092b 7376 goto err_unpin;
8c9f3aaf
JB		 7377
7378 /* i965+ uses the linear or tiled offsets from the
7379 * Display Registers (which do not change across a page-flip)
7380 * so we need only reprogram the base address.
7381 */
6d90c952
DV		 7382 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7383 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7384 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7385 intel_ring_emit(ring,
7386 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7387 obj->tiling_mode);
8c9f3aaf
JB		 7388
7389 /* XXX Enabling the panel-fitter across page-flip is so far
7390 * untested on non-native modes, so ignore it for now.
7391 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7392 */
7393 pf = 0;
7394 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7395 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7396
7397 intel_mark_page_flip_active(intel_crtc);
6d90c952 7398 intel_ring_advance(ring);
83d4092b
CW		 7399 return 0;
7400
7401err_unpin:
7402 intel_unpin_fb_obj(obj);
7403err:
8c9f3aaf
JB		 7404 return ret;
7405}
7406
7407static int intel_gen6_queue_flip(struct drm_device *dev,
7408 struct drm_crtc *crtc,
7409 struct drm_framebuffer *fb,
7410 struct drm_i915_gem_object *obj)
7411{
7412 struct drm_i915_private *dev_priv = dev->dev_private;
7413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7414 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7415 uint32_t pf, pipesrc;
7416 int ret;
7417
6d90c952 7418 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7419 if (ret)
83d4092b 7420 goto err;
8c9f3aaf 7421
6d90c952 7422 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7423 if (ret)
83d4092b 7424 goto err_unpin;
8c9f3aaf 7425
6d90c952
DV		 7426 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7427 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7428 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7429 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7430
dc257cf1
DV		 7431 /* Contrary to the suggestions in the documentation,
7432 * "Enable Panel Fitter" does not seem to be required when page
7433 * flipping with a non-native mode, and worse causes a normal
7434 * modeset to fail.
7435 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7436 */
7437 pf = 0;
8c9f3aaf 7438 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7439 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7440
7441 intel_mark_page_flip_active(intel_crtc);
6d90c952 7442 intel_ring_advance(ring);
83d4092b
CW		 7443 return 0;
7444
7445err_unpin:
7446 intel_unpin_fb_obj(obj);
7447err:
8c9f3aaf
JB		 7448 return ret;
7449}
7450
7c9017e5
JB		 7451/*
7452 * On gen7 we currently use the blit ring because (in early silicon at least)
7453 * the render ring doesn't give us interrpts for page flip completion, which
7454 * means clients will hang after the first flip is queued. Fortunately the
7455 * blit ring generates interrupts properly, so use it instead.
7456 */
7457static int intel_gen7_queue_flip(struct drm_device *dev,
7458 struct drm_crtc *crtc,
7459 struct drm_framebuffer *fb,
7460 struct drm_i915_gem_object *obj)
7461{
7462 struct drm_i915_private *dev_priv = dev->dev_private;
7463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7464 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7465 uint32_t plane_bit = 0;
7c9017e5
JB		 7466 int ret;
7467
7468 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7469 if (ret)
83d4092b 7470 goto err;
7c9017e5 7471
cb05d8de
DV		 7472 switch(intel_crtc->plane) {
7473 case PLANE_A:
7474 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7475 break;
7476 case PLANE_B:
7477 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7478 break;
7479 case PLANE_C:
7480 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7481 break;
7482 default:
7483 WARN_ONCE(1, "unknown plane in flip command\n");
7484 ret = -ENODEV;
ab3951eb 7485 goto err_unpin;
cb05d8de
DV		 7486 }
7487
7c9017e5
JB		 7488 ret = intel_ring_begin(ring, 4);
7489 if (ret)
83d4092b 7490 goto err_unpin;
7c9017e5 7491
cb05d8de 7492 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7493 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7494 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7495 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7496
7497 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7498 intel_ring_advance(ring);
83d4092b
CW		 7499 return 0;
7500
7501err_unpin:
7502 intel_unpin_fb_obj(obj);
7503err:
7c9017e5
JB		 7504 return ret;
7505}
7506
8c9f3aaf
JB		 7507static int intel_default_queue_flip(struct drm_device *dev,
7508 struct drm_crtc *crtc,
7509 struct drm_framebuffer *fb,
7510 struct drm_i915_gem_object *obj)
7511{
7512 return -ENODEV;
7513}
7514
6b95a207
KH		 7515static int intel_crtc_page_flip(struct drm_crtc *crtc,
7516 struct drm_framebuffer *fb,
7517 struct drm_pending_vblank_event *event)
7518{
7519 struct drm_device *dev = crtc->dev;
7520 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7521 struct drm_framebuffer *old_fb = crtc->fb;
7522 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7524 struct intel_unpin_work *work;
8c9f3aaf 7525 unsigned long flags;
52e68630 7526 int ret;
6b95a207 7527
e6a595d2
VS		 7528 /* Can't change pixel format via MI display flips. */
7529 if (fb->pixel_format != crtc->fb->pixel_format)
7530 return -EINVAL;
7531
7532 /*
7533 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7534 * Note that pitch changes could also affect these register.
7535 */
7536 if (INTEL_INFO(dev)->gen > 3 &&
7537 (fb->offsets[0] != crtc->fb->offsets[0] ||
7538 fb->pitches[0] != crtc->fb->pitches[0]))
7539 return -EINVAL;
7540
6b95a207
KH		 7541 work = kzalloc(sizeof *work, GFP_KERNEL);
7542 if (work == NULL)
7543 return -ENOMEM;
7544
6b95a207 7545 work->event = event;
b4a98e57 7546 work->crtc = crtc;
4a35f83b 7547 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7548 INIT_WORK(&work->work, intel_unpin_work_fn);
7549
7317c75e
JB		 7550 ret = drm_vblank_get(dev, intel_crtc->pipe);
7551 if (ret)
7552 goto free_work;
7553
6b95a207
KH		 7554 /* We borrow the event spin lock for protecting unpin_work */
7555 spin_lock_irqsave(&dev->event_lock, flags);
7556 if (intel_crtc->unpin_work) {
7557 spin_unlock_irqrestore(&dev->event_lock, flags);
7558 kfree(work);
7317c75e 7559 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7560
7561 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7562 return -EBUSY;
7563 }
7564 intel_crtc->unpin_work = work;
7565 spin_unlock_irqrestore(&dev->event_lock, flags);
7566
b4a98e57
CW		 7567 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7568 flush_workqueue(dev_priv->wq);
7569
79158103
CW		 7570 ret = i915_mutex_lock_interruptible(dev);
7571 if (ret)
7572 goto cleanup;
6b95a207 7573
75dfca80 7574 /* Reference the objects for the scheduled work. */
05394f39
CW		 7575 drm_gem_object_reference(&work->old_fb_obj->base);
7576 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7577
7578 crtc->fb = fb;
96b099fd 7579
e1f99ce6 7580 work->pending_flip_obj = obj;
e1f99ce6 7581
4e5359cd
SF		 7582 work->enable_stall_check = true;
7583
b4a98e57 7584 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7585 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7586
8c9f3aaf
JB		 7587 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7588 if (ret)
7589 goto cleanup_pending;
6b95a207 7590
7782de3b 7591 intel_disable_fbc(dev);
c65355bb 7592 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 7593 mutex_unlock(&dev->struct_mutex);
7594
e5510fac
JB		 7595 trace_i915_flip_request(intel_crtc->plane, obj);
7596
6b95a207 7597 return 0;
96b099fd 7598
8c9f3aaf 7599cleanup_pending:
b4a98e57 7600 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7601 crtc->fb = old_fb;
05394f39
CW		 7602 drm_gem_object_unreference(&work->old_fb_obj->base);
7603 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7604 mutex_unlock(&dev->struct_mutex);
7605
79158103 7606cleanup:
96b099fd
CW		 7607 spin_lock_irqsave(&dev->event_lock, flags);
7608 intel_crtc->unpin_work = NULL;
7609 spin_unlock_irqrestore(&dev->event_lock, flags);
7610
7317c75e
JB		 7611 drm_vblank_put(dev, intel_crtc->pipe);
7612free_work:
96b099fd
CW		 7613 kfree(work);
7614
7615 return ret;
6b95a207
KH		 7616}
7617
f6e5b160 7618static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7619 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7620 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7621};
7622
50f56119
DV		 7623static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7624 struct drm_crtc *crtc)
7625{
7626 struct drm_device *dev;
7627 struct drm_crtc *tmp;
7628 int crtc_mask = 1;
47f1c6c9 7629
50f56119 7630 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7631
50f56119 7632 dev = crtc->dev;
47f1c6c9 7633
50f56119
DV		 7634 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7635 if (tmp == crtc)
7636 break;
7637 crtc_mask <<= 1;
7638 }
47f1c6c9 7639
50f56119
DV		 7640 if (encoder->possible_crtcs & crtc_mask)
7641 return true;
7642 return false;
47f1c6c9 7643}
79e53945 7644
9a935856
DV		 7645/**
7646 * intel_modeset_update_staged_output_state
7647 *
7648 * Updates the staged output configuration state, e.g. after we've read out the
7649 * current hw state.
7650 */
7651static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7652{
9a935856
DV		 7653 struct intel_encoder *encoder;
7654 struct intel_connector *connector;
f6e5b160 7655
9a935856
DV		 7656 list_for_each_entry(connector, &dev->mode_config.connector_list,
7657 base.head) {
7658 connector->new_encoder =
7659 to_intel_encoder(connector->base.encoder);
7660 }
f6e5b160 7661
9a935856
DV		 7662 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7663 base.head) {
7664 encoder->new_crtc =
7665 to_intel_crtc(encoder->base.crtc);
7666 }
f6e5b160
CW		 7667}
7668
9a935856
DV		 7669/**
7670 * intel_modeset_commit_output_state
7671 *
7672 * This function copies the stage display pipe configuration to the real one.
7673 */
7674static void intel_modeset_commit_output_state(struct drm_device *dev)
7675{
7676 struct intel_encoder *encoder;
7677 struct intel_connector *connector;
f6e5b160 7678
9a935856
DV		 7679 list_for_each_entry(connector, &dev->mode_config.connector_list,
7680 base.head) {
7681 connector->base.encoder = &connector->new_encoder->base;
7682 }
f6e5b160 7683
9a935856
DV		 7684 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7685 base.head) {
7686 encoder->base.crtc = &encoder->new_crtc->base;
7687 }
7688}
7689
050f7aeb
DV		 7690static void
7691connected_sink_compute_bpp(struct intel_connector * connector,
7692 struct intel_crtc_config *pipe_config)
7693{
7694 int bpp = pipe_config->pipe_bpp;
7695
7696 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7697 connector->base.base.id,
7698 drm_get_connector_name(&connector->base));
7699
7700 /* Don't use an invalid EDID bpc value */
7701 if (connector->base.display_info.bpc &&
7702 connector->base.display_info.bpc * 3 < bpp) {
7703 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7704 bpp, connector->base.display_info.bpc*3);
7705 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7706 }
7707
7708 /* Clamp bpp to 8 on screens without EDID 1.4 */
7709 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7710 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7711 bpp);
7712 pipe_config->pipe_bpp = 24;
7713 }
7714}
7715
4e53c2e0 7716static int
050f7aeb
DV		 7717compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7718 struct drm_framebuffer *fb,
7719 struct intel_crtc_config *pipe_config)
4e53c2e0 7720{
050f7aeb
DV		 7721 struct drm_device *dev = crtc->base.dev;
7722 struct intel_connector *connector;
4e53c2e0
DV		 7723 int bpp;
7724
d42264b1
DV		 7725 switch (fb->pixel_format) {
7726 case DRM_FORMAT_C8:
4e53c2e0
DV		 7727 bpp = 8*3; /* since we go through a colormap */
7728 break;
d42264b1
DV		 7729 case DRM_FORMAT_XRGB1555:
7730 case DRM_FORMAT_ARGB1555:
7731 /* checked in intel_framebuffer_init already */
7732 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7733 return -EINVAL;
7734 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7735 bpp = 6*3; /* min is 18bpp */
7736 break;
d42264b1
DV		 7737 case DRM_FORMAT_XBGR8888:
7738 case DRM_FORMAT_ABGR8888:
7739 /* checked in intel_framebuffer_init already */
7740 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7741 return -EINVAL;
7742 case DRM_FORMAT_XRGB8888:
7743 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7744 bpp = 8*3;
7745 break;
d42264b1
DV		 7746 case DRM_FORMAT_XRGB2101010:
7747 case DRM_FORMAT_ARGB2101010:
7748 case DRM_FORMAT_XBGR2101010:
7749 case DRM_FORMAT_ABGR2101010:
7750 /* checked in intel_framebuffer_init already */
7751 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7752 return -EINVAL;
4e53c2e0
DV		 7753 bpp = 10*3;
7754 break;
baba133a 7755 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7756 default:
7757 DRM_DEBUG_KMS("unsupported depth\n");
7758 return -EINVAL;
7759 }
7760
4e53c2e0
DV		 7761 pipe_config->pipe_bpp = bpp;
7762
7763 /* Clamp display bpp to EDID value */
7764 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7765 base.head) {
1b829e05
DV		 7766 if (!connector->new_encoder ||
7767 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7768 continue;
7769
050f7aeb 7770 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7771 }
7772
7773 return bpp;
7774}
7775
c0b03411
DV		 7776static void intel_dump_pipe_config(struct intel_crtc *crtc,
7777 struct intel_crtc_config *pipe_config,
7778 const char *context)
7779{
7780 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7781 context, pipe_name(crtc->pipe));
7782
7783 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7784 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7785 pipe_config->pipe_bpp, pipe_config->dither);
7786 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7787 pipe_config->has_pch_encoder,
7788 pipe_config->fdi_lanes,
7789 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7790 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7791 pipe_config->fdi_m_n.tu);
7792 DRM_DEBUG_KMS("requested mode:\n");
7793 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7794 DRM_DEBUG_KMS("adjusted mode:\n");
7795 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7796 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7797 pipe_config->gmch_pfit.control,
7798 pipe_config->gmch_pfit.pgm_ratios,
7799 pipe_config->gmch_pfit.lvds_border_bits);
7800 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7801 pipe_config->pch_pfit.pos,
7802 pipe_config->pch_pfit.size);
42db64ef 7803 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7804}
7805
accfc0c5
DV		 7806static bool check_encoder_cloning(struct drm_crtc *crtc)
7807{
7808 int num_encoders = 0;
7809 bool uncloneable_encoders = false;
7810 struct intel_encoder *encoder;
7811
7812 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7813 base.head) {
7814 if (&encoder->new_crtc->base != crtc)
7815 continue;
7816
7817 num_encoders++;
7818 if (!encoder->cloneable)
7819 uncloneable_encoders = true;
7820 }
7821
7822 return !(num_encoders > 1 && uncloneable_encoders);
7823}
7824
b8cecdf5
DV		 7825static struct intel_crtc_config *
7826intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7827 struct drm_framebuffer *fb,
b8cecdf5 7828 struct drm_display_mode *mode)
ee7b9f93 7829{
7758a113 7830 struct drm_device *dev = crtc->dev;
7758a113
DV		 7831 struct drm_encoder_helper_funcs *encoder_funcs;
7832 struct intel_encoder *encoder;
b8cecdf5 7833 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7834 int plane_bpp, ret = -EINVAL;
7835 bool retry = true;
ee7b9f93 7836
accfc0c5
DV		 7837 if (!check_encoder_cloning(crtc)) {
7838 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7839 return ERR_PTR(-EINVAL);
7840 }
7841
b8cecdf5
DV		 7842 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7843 if (!pipe_config)
7758a113
DV		 7844 return ERR_PTR(-ENOMEM);
7845
b8cecdf5
DV		 7846 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7847 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7848 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
b8cecdf5 7849
050f7aeb
DV		 7850 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7851 * plane pixel format and any sink constraints into account. Returns the
7852 * source plane bpp so that dithering can be selected on mismatches
7853 * after encoders and crtc also have had their say. */
7854 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7855 fb, pipe_config);
4e53c2e0
DV		 7856 if (plane_bpp < 0)
7857 goto fail;
7858
e29c22c0 7859encoder_retry:
ef1b460d 7860 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 7861 pipe_config->port_clock = 0;
ef1b460d 7862 pipe_config->pixel_multiplier = 1;
ff9a6750 7863
7758a113
DV		 7864 /* Pass our mode to the connectors and the CRTC to give them a chance to
7865 * adjust it according to limitations or connector properties, and also
7866 * a chance to reject the mode entirely.
47f1c6c9 7867 */
7758a113
DV		 7868 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7869 base.head) {
47f1c6c9 7870
7758a113
DV		 7871 if (&encoder->new_crtc->base != crtc)
7872 continue;
7ae89233
DV		 7873
7874 if (encoder->compute_config) {
7875 if (!(encoder->compute_config(encoder, pipe_config))) {
7876 DRM_DEBUG_KMS("Encoder config failure\n");
7877 goto fail;
7878 }
7879
7880 continue;
7881 }
7882
7758a113 7883 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7884 if (!(encoder_funcs->mode_fixup(&encoder->base,
7885 &pipe_config->requested_mode,
7886 &pipe_config->adjusted_mode))) {
7758a113
DV		 7887 DRM_DEBUG_KMS("Encoder fixup failed\n");
7888 goto fail;
7889 }
ee7b9f93 7890 }
47f1c6c9 7891
ff9a6750
DV		 7892 /* Set default port clock if not overwritten by the encoder. Needs to be
7893 * done afterwards in case the encoder adjusts the mode. */
7894 if (!pipe_config->port_clock)
7895 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7896
e29c22c0
DV		 7897 ret = intel_crtc_compute_config(crtc, pipe_config);
7898 if (ret < 0) {
7758a113
DV		 7899 DRM_DEBUG_KMS("CRTC fixup failed\n");
7900 goto fail;
ee7b9f93 7901 }
e29c22c0
DV		 7902
7903 if (ret == RETRY) {
7904 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7905 ret = -EINVAL;
7906 goto fail;
7907 }
7908
7909 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7910 retry = false;
7911 goto encoder_retry;
7912 }
7913
4e53c2e0
DV		 7914 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7915 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7916 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7917
b8cecdf5 7918 return pipe_config;
7758a113 7919fail:
b8cecdf5 7920 kfree(pipe_config);
e29c22c0 7921 return ERR_PTR(ret);
ee7b9f93 7922}
47f1c6c9 7923
e2e1ed41
DV		 7924/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7925 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7926static void
7927intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7928 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7929{
7930 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7931 struct drm_device *dev = crtc->dev;
7932 struct intel_encoder *encoder;
7933 struct intel_connector *connector;
7934 struct drm_crtc *tmp_crtc;
79e53945 7935
e2e1ed41 7936 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7937
e2e1ed41
DV		 7938 /* Check which crtcs have changed outputs connected to them, these need
7939 * to be part of the prepare_pipes mask. We don't (yet) support global
7940 * modeset across multiple crtcs, so modeset_pipes will only have one
7941 * bit set at most. */
7942 list_for_each_entry(connector, &dev->mode_config.connector_list,
7943 base.head) {
7944 if (connector->base.encoder == &connector->new_encoder->base)
7945 continue;
79e53945 7946
e2e1ed41
DV		 7947 if (connector->base.encoder) {
7948 tmp_crtc = connector->base.encoder->crtc;
7949
7950 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7951 }
7952
7953 if (connector->new_encoder)
7954 *prepare_pipes |=
7955 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7956 }
7957
e2e1ed41
DV		 7958 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7959 base.head) {
7960 if (encoder->base.crtc == &encoder->new_crtc->base)
7961 continue;
7962
7963 if (encoder->base.crtc) {
7964 tmp_crtc = encoder->base.crtc;
7965
7966 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7967 }
7968
7969 if (encoder->new_crtc)
7970 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7971 }
7972
e2e1ed41
DV		 7973 /* Check for any pipes that will be fully disabled ... */
7974 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7975 base.head) {
7976 bool used = false;
22fd0fab 7977
e2e1ed41
DV		 7978 /* Don't try to disable disabled crtcs. */
7979 if (!intel_crtc->base.enabled)
7980 continue;
7e7d76c3 7981
e2e1ed41
DV		 7982 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7983 base.head) {
7984 if (encoder->new_crtc == intel_crtc)
7985 used = true;
7986 }
7987
7988 if (!used)
7989 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7990 }
7991
e2e1ed41
DV		 7992
7993 /* set_mode is also used to update properties on life display pipes. */
7994 intel_crtc = to_intel_crtc(crtc);
7995 if (crtc->enabled)
7996 *prepare_pipes |= 1 << intel_crtc->pipe;
7997
b6c5164d
DV		 7998 /*
7999 * For simplicity do a full modeset on any pipe where the output routing
8000 * changed. We could be more clever, but that would require us to be
8001 * more careful with calling the relevant encoder->mode_set functions.
8002 */
e2e1ed41
DV		 8003 if (*prepare_pipes)
8004 *modeset_pipes = *prepare_pipes;
8005
8006 /* ... and mask these out. */
8007 *modeset_pipes &= ~(*disable_pipes);
8008 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8009
8010 /*
8011 * HACK: We don't (yet) fully support global modesets. intel_set_config
8012 * obies this rule, but the modeset restore mode of
8013 * intel_modeset_setup_hw_state does not.
8014 */
8015 *modeset_pipes &= 1 << intel_crtc->pipe;
8016 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8017
8018 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8019 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8020}
79e53945 8021
ea9d758d 8022static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8023{
ea9d758d 8024 struct drm_encoder *encoder;
f6e5b160 8025 struct drm_device *dev = crtc->dev;
f6e5b160 8026
ea9d758d
DV		 8027 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8028 if (encoder->crtc == crtc)
8029 return true;
8030
8031 return false;
8032}
8033
8034static void
8035intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8036{
8037 struct intel_encoder *intel_encoder;
8038 struct intel_crtc *intel_crtc;
8039 struct drm_connector *connector;
8040
8041 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8042 base.head) {
8043 if (!intel_encoder->base.crtc)
8044 continue;
8045
8046 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8047
8048 if (prepare_pipes & (1 << intel_crtc->pipe))
8049 intel_encoder->connectors_active = false;
8050 }
8051
8052 intel_modeset_commit_output_state(dev);
8053
8054 /* Update computed state. */
8055 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8056 base.head) {
8057 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8058 }
8059
8060 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8061 if (!connector->encoder || !connector->encoder->crtc)
8062 continue;
8063
8064 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8065
8066 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8067 struct drm_property *dpms_property =
8068 dev->mode_config.dpms_property;
8069
ea9d758d 8070 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8071 drm_object_property_set_value(&connector->base,
68d34720
DV		 8072 dpms_property,
8073 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8074
8075 intel_encoder = to_intel_encoder(connector->encoder);
8076 intel_encoder->connectors_active = true;
8077 }
8078 }
8079
8080}
8081
25c5b266
DV		 8082#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8083 list_for_each_entry((intel_crtc), \
8084 &(dev)->mode_config.crtc_list, \
8085 base.head) \
0973f18f 8086 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8087
0e8ffe1b 8088static bool
2fa2fe9a
DV		 8089intel_pipe_config_compare(struct drm_device *dev,
8090 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8091 struct intel_crtc_config *pipe_config)
8092{
08a24034
DV		 8093#define PIPE_CONF_CHECK_I(name) \
8094 if (current_config->name != pipe_config->name) { \
8095 DRM_ERROR("mismatch in " #name " " \
8096 "(expected %i, found %i)\n", \
8097 current_config->name, \
8098 pipe_config->name); \
8099 return false; \
88adfff1
DV		 8100 }
8101
1bd1bd80
DV		 8102#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8103 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8104 DRM_ERROR("mismatch in " #name " " \
8105 "(expected %i, found %i)\n", \
8106 current_config->name & (mask), \
8107 pipe_config->name & (mask)); \
8108 return false; \
8109 }
8110
bb760063
DV		 8111#define PIPE_CONF_QUIRK(quirk) \
8112 ((current_config->quirks | pipe_config->quirks) & (quirk))
8113
eccb140b
DV		 8114 PIPE_CONF_CHECK_I(cpu_transcoder);
8115
08a24034
DV		 8116 PIPE_CONF_CHECK_I(has_pch_encoder);
8117 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8118 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8119 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8120 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8121 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8122 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8123
1bd1bd80
DV		 8124 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8125 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8126 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8127 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8128 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8129 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8130
8131 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8132 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8133 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8134 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8135 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8136 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8137
6c49f241
DV		 8138 if (!HAS_PCH_SPLIT(dev))
8139 PIPE_CONF_CHECK_I(pixel_multiplier);
8140
1bd1bd80
DV		 8141 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8142 DRM_MODE_FLAG_INTERLACE);
8143
bb760063
DV		 8144 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8145 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8146 DRM_MODE_FLAG_PHSYNC);
8147 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8148 DRM_MODE_FLAG_NHSYNC);
8149 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8150 DRM_MODE_FLAG_PVSYNC);
8151 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8152 DRM_MODE_FLAG_NVSYNC);
8153 }
045ac3b5 8154
1bd1bd80
DV		 8155 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8156 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8157
2fa2fe9a
DV		 8158 PIPE_CONF_CHECK_I(gmch_pfit.control);
8159 /* pfit ratios are autocomputed by the hw on gen4+ */
8160 if (INTEL_INFO(dev)->gen < 4)
8161 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8162 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8163 PIPE_CONF_CHECK_I(pch_pfit.pos);
8164 PIPE_CONF_CHECK_I(pch_pfit.size);
8165
42db64ef
PZ		 8166 PIPE_CONF_CHECK_I(ips_enabled);
8167
08a24034 8168#undef PIPE_CONF_CHECK_I
1bd1bd80 8169#undef PIPE_CONF_CHECK_FLAGS
bb760063 8170#undef PIPE_CONF_QUIRK
627eb5a3 8171
0e8ffe1b
DV		 8172 return true;
8173}
8174
b980514c 8175void
8af6cf88
DV		 8176intel_modeset_check_state(struct drm_device *dev)
8177{
0e8ffe1b 8178 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 8179 struct intel_crtc *crtc;
8180 struct intel_encoder *encoder;
8181 struct intel_connector *connector;
0e8ffe1b 8182 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8183
8184 list_for_each_entry(connector, &dev->mode_config.connector_list,
8185 base.head) {
8186 /* This also checks the encoder/connector hw state with the
8187 * ->get_hw_state callbacks. */
8188 intel_connector_check_state(connector);
8189
8190 WARN(&connector->new_encoder->base != connector->base.encoder,
8191 "connector's staged encoder doesn't match current encoder\n");
8192 }
8193
8194 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8195 base.head) {
8196 bool enabled = false;
8197 bool active = false;
8198 enum pipe pipe, tracked_pipe;
8199
8200 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8201 encoder->base.base.id,
8202 drm_get_encoder_name(&encoder->base));
8203
8204 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8205 "encoder's stage crtc doesn't match current crtc\n");
8206 WARN(encoder->connectors_active && !encoder->base.crtc,
8207 "encoder's active_connectors set, but no crtc\n");
8208
8209 list_for_each_entry(connector, &dev->mode_config.connector_list,
8210 base.head) {
8211 if (connector->base.encoder != &encoder->base)
8212 continue;
8213 enabled = true;
8214 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8215 active = true;
8216 }
8217 WARN(!!encoder->base.crtc != enabled,
8218 "encoder's enabled state mismatch "
8219 "(expected %i, found %i)\n",
8220 !!encoder->base.crtc, enabled);
8221 WARN(active && !encoder->base.crtc,
8222 "active encoder with no crtc\n");
8223
8224 WARN(encoder->connectors_active != active,
8225 "encoder's computed active state doesn't match tracked active state "
8226 "(expected %i, found %i)\n", active, encoder->connectors_active);
8227
8228 active = encoder->get_hw_state(encoder, &pipe);
8229 WARN(active != encoder->connectors_active,
8230 "encoder's hw state doesn't match sw tracking "
8231 "(expected %i, found %i)\n",
8232 encoder->connectors_active, active);
8233
8234 if (!encoder->base.crtc)
8235 continue;
8236
8237 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8238 WARN(active && pipe != tracked_pipe,
8239 "active encoder's pipe doesn't match"
8240 "(expected %i, found %i)\n",
8241 tracked_pipe, pipe);
8242
8243 }
8244
8245 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8246 base.head) {
8247 bool enabled = false;
8248 bool active = false;
8249
045ac3b5
JB		 8250 memset(&pipe_config, 0, sizeof(pipe_config));
8251
8af6cf88
DV		 8252 DRM_DEBUG_KMS("[CRTC:%d]\n",
8253 crtc->base.base.id);
8254
8255 WARN(crtc->active && !crtc->base.enabled,
8256 "active crtc, but not enabled in sw tracking\n");
8257
8258 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8259 base.head) {
8260 if (encoder->base.crtc != &crtc->base)
8261 continue;
8262 enabled = true;
8263 if (encoder->connectors_active)
8264 active = true;
8265 }
6c49f241 8266
8af6cf88
DV		 8267 WARN(active != crtc->active,
8268 "crtc's computed active state doesn't match tracked active state "
8269 "(expected %i, found %i)\n", active, crtc->active);
8270 WARN(enabled != crtc->base.enabled,
8271 "crtc's computed enabled state doesn't match tracked enabled state "
8272 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8273
0e8ffe1b
DV		 8274 active = dev_priv->display.get_pipe_config(crtc,
8275 &pipe_config);
6c49f241
DV		 8276 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8277 base.head) {
8278 if (encoder->base.crtc != &crtc->base)
8279 continue;
8280 if (encoder->get_config)
8281 encoder->get_config(encoder, &pipe_config);
8282 }
8283
0e8ffe1b
DV		 8284 WARN(crtc->active != active,
8285 "crtc active state doesn't match with hw state "
8286 "(expected %i, found %i)\n", crtc->active, active);
8287
c0b03411
DV		 8288 if (active &&
8289 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8290 WARN(1, "pipe state doesn't match!\n");
8291 intel_dump_pipe_config(crtc, &pipe_config,
8292 "[hw state]");
8293 intel_dump_pipe_config(crtc, &crtc->config,
8294 "[sw state]");
8295 }
8af6cf88
DV		 8296 }
8297}
8298
f30da187
DV		 8299static int __intel_set_mode(struct drm_crtc *crtc,
8300 struct drm_display_mode *mode,
8301 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8302{
8303 struct drm_device *dev = crtc->dev;
dbf2b54e 8304 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8305 struct drm_display_mode *saved_mode, *saved_hwmode;
8306 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8307 struct intel_crtc *intel_crtc;
8308 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8309 int ret = 0;
a6778b3c 8310
3ac18232 8311 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8312 if (!saved_mode)
8313 return -ENOMEM;
3ac18232 8314 saved_hwmode = saved_mode + 1;
a6778b3c 8315
e2e1ed41 8316 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8317 &prepare_pipes, &disable_pipes);
8318
3ac18232
TG		 8319 *saved_hwmode = crtc->hwmode;
8320 *saved_mode = crtc->mode;
a6778b3c 8321
25c5b266
DV		 8322 /* Hack: Because we don't (yet) support global modeset on multiple
8323 * crtcs, we don't keep track of the new mode for more than one crtc.
8324 * Hence simply check whether any bit is set in modeset_pipes in all the
8325 * pieces of code that are not yet converted to deal with mutliple crtcs
8326 * changing their mode at the same time. */
25c5b266 8327 if (modeset_pipes) {
4e53c2e0 8328 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8329 if (IS_ERR(pipe_config)) {
8330 ret = PTR_ERR(pipe_config);
8331 pipe_config = NULL;
8332
3ac18232 8333 goto out;
25c5b266 8334 }
c0b03411
DV		 8335 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8336 "[modeset]");
25c5b266 8337 }
a6778b3c 8338
460da916
DV		 8339 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8340 intel_crtc_disable(&intel_crtc->base);
8341
ea9d758d
DV		 8342 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8343 if (intel_crtc->base.enabled)
8344 dev_priv->display.crtc_disable(&intel_crtc->base);
8345 }
a6778b3c 8346
6c4c86f5
DV		 8347 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8348 * to set it here already despite that we pass it down the callchain.
f6e5b160 8349 */
b8cecdf5 8350 if (modeset_pipes) {
25c5b266 8351 crtc->mode = *mode;
b8cecdf5
DV		 8352 /* mode_set/enable/disable functions rely on a correct pipe
8353 * config. */
8354 to_intel_crtc(crtc)->config = *pipe_config;
8355 }
7758a113 8356
ea9d758d
DV		 8357 /* Only after disabling all output pipelines that will be changed can we
8358 * update the the output configuration. */
8359 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8360
47fab737
DV		 8361 if (dev_priv->display.modeset_global_resources)
8362 dev_priv->display.modeset_global_resources(dev);
8363
a6778b3c
DV		 8364 /* Set up the DPLL and any encoders state that needs to adjust or depend
8365 * on the DPLL.
f6e5b160 8366 */
25c5b266 8367 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8368 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8369 x, y, fb);
8370 if (ret)
8371 goto done;
a6778b3c
DV		 8372 }
8373
8374 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8375 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8376 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8377
25c5b266
DV		 8378 if (modeset_pipes) {
8379 /* Store real post-adjustment hardware mode. */
b8cecdf5 8380 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8381
25c5b266
DV		 8382 /* Calculate and store various constants which
8383 * are later needed by vblank and swap-completion
8384 * timestamping. They are derived from true hwmode.
8385 */
8386 drm_calc_timestamping_constants(crtc);
8387 }
a6778b3c
DV		 8388
8389 /* FIXME: add subpixel order */
8390done:
c0c36b94 8391 if (ret && crtc->enabled) {
3ac18232
TG		 8392 crtc->hwmode = *saved_hwmode;
8393 crtc->mode = *saved_mode;
a6778b3c
DV		 8394 }
8395
3ac18232 8396out:
b8cecdf5 8397 kfree(pipe_config);
3ac18232 8398 kfree(saved_mode);
a6778b3c 8399 return ret;
f6e5b160
CW		 8400}
8401
f30da187
DV		 8402int intel_set_mode(struct drm_crtc *crtc,
8403 struct drm_display_mode *mode,
8404 int x, int y, struct drm_framebuffer *fb)
8405{
8406 int ret;
8407
8408 ret = __intel_set_mode(crtc, mode, x, y, fb);
8409
8410 if (ret == 0)
8411 intel_modeset_check_state(crtc->dev);
8412
8413 return ret;
8414}
8415
c0c36b94
CW		 8416void intel_crtc_restore_mode(struct drm_crtc *crtc)
8417{
8418 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8419}
8420
25c5b266
DV		 8421#undef for_each_intel_crtc_masked
8422
d9e55608
DV		 8423static void intel_set_config_free(struct intel_set_config *config)
8424{
8425 if (!config)
8426 return;
8427
1aa4b628
DV		 8428 kfree(config->save_connector_encoders);
8429 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8430 kfree(config);
8431}
8432
85f9eb71
DV		 8433static int intel_set_config_save_state(struct drm_device *dev,
8434 struct intel_set_config *config)
8435{
85f9eb71
DV		 8436 struct drm_encoder *encoder;
8437 struct drm_connector *connector;
8438 int count;
8439
1aa4b628
DV		 8440 config->save_encoder_crtcs =
8441 kcalloc(dev->mode_config.num_encoder,
8442 sizeof(struct drm_crtc *), GFP_KERNEL);
8443 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8444 return -ENOMEM;
8445
1aa4b628
DV		 8446 config->save_connector_encoders =
8447 kcalloc(dev->mode_config.num_connector,
8448 sizeof(struct drm_encoder *), GFP_KERNEL);
8449 if (!config->save_connector_encoders)
85f9eb71
DV		 8450 return -ENOMEM;
8451
8452 /* Copy data. Note that driver private data is not affected.
8453 * Should anything bad happen only the expected state is
8454 * restored, not the drivers personal bookkeeping.
8455 */
85f9eb71
DV		 8456 count = 0;
8457 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8458 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8459 }
8460
8461 count = 0;
8462 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8463 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8464 }
8465
8466 return 0;
8467}
8468
8469static void intel_set_config_restore_state(struct drm_device *dev,
8470 struct intel_set_config *config)
8471{
9a935856
DV		 8472 struct intel_encoder *encoder;
8473 struct intel_connector *connector;
85f9eb71
DV		 8474 int count;
8475
85f9eb71 8476 count = 0;
9a935856
DV		 8477 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8478 encoder->new_crtc =
8479 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8480 }
8481
8482 count = 0;
9a935856
DV		 8483 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8484 connector->new_encoder =
8485 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8486 }
8487}
8488
5e2b584e
DV		 8489static void
8490intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8491 struct intel_set_config *config)
8492{
8493
8494 /* We should be able to check here if the fb has the same properties
8495 * and then just flip_or_move it */
8496 if (set->crtc->fb != set->fb) {
8497 /* If we have no fb then treat it as a full mode set */
8498 if (set->crtc->fb == NULL) {
8499 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8500 config->mode_changed = true;
8501 } else if (set->fb == NULL) {
8502 config->mode_changed = true;
72f4901e
DV		 8503 } else if (set->fb->pixel_format !=
8504 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8505 config->mode_changed = true;
8506 } else
8507 config->fb_changed = true;
8508 }
8509
835c5873 8510 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8511 config->fb_changed = true;
8512
8513 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8514 DRM_DEBUG_KMS("modes are different, full mode set\n");
8515 drm_mode_debug_printmodeline(&set->crtc->mode);
8516 drm_mode_debug_printmodeline(set->mode);
8517 config->mode_changed = true;
8518 }
8519}
8520
2e431051 8521static int
9a935856
DV		 8522intel_modeset_stage_output_state(struct drm_device *dev,
8523 struct drm_mode_set *set,
8524 struct intel_set_config *config)
50f56119 8525{
85f9eb71 8526 struct drm_crtc *new_crtc;
9a935856
DV		 8527 struct intel_connector *connector;
8528 struct intel_encoder *encoder;
2e431051 8529 int count, ro;
50f56119 8530
9abdda74 8531 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8532 * of connectors. For paranoia, double-check this. */
8533 WARN_ON(!set->fb && (set->num_connectors != 0));
8534 WARN_ON(set->fb && (set->num_connectors == 0));
8535
50f56119 8536 count = 0;
9a935856
DV		 8537 list_for_each_entry(connector, &dev->mode_config.connector_list,
8538 base.head) {
8539 /* Otherwise traverse passed in connector list and get encoders
8540 * for them. */
50f56119 8541 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8542 if (set->connectors[ro] == &connector->base) {
8543 connector->new_encoder = connector->encoder;
50f56119
DV		 8544 break;
8545 }
8546 }
8547
9a935856
DV		 8548 /* If we disable the crtc, disable all its connectors. Also, if
8549 * the connector is on the changing crtc but not on the new
8550 * connector list, disable it. */
8551 if ((!set->fb || ro == set->num_connectors) &&
8552 connector->base.encoder &&
8553 connector->base.encoder->crtc == set->crtc) {
8554 connector->new_encoder = NULL;
8555
8556 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8557 connector->base.base.id,
8558 drm_get_connector_name(&connector->base));
8559 }
8560
8561
8562 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8563 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8564 config->mode_changed = true;
50f56119
DV		 8565 }
8566 }
9a935856 8567 /* connector->new_encoder is now updated for all connectors. */
50f56119 8568
9a935856 8569 /* Update crtc of enabled connectors. */
50f56119 8570 count = 0;
9a935856
DV		 8571 list_for_each_entry(connector, &dev->mode_config.connector_list,
8572 base.head) {
8573 if (!connector->new_encoder)
50f56119
DV		 8574 continue;
8575
9a935856 8576 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8577
8578 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8579 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8580 new_crtc = set->crtc;
8581 }
8582
8583 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8584 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8585 new_crtc)) {
5e2b584e 8586 return -EINVAL;
50f56119 8587 }
9a935856
DV		 8588 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8589
8590 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8591 connector->base.base.id,
8592 drm_get_connector_name(&connector->base),
8593 new_crtc->base.id);
8594 }
8595
8596 /* Check for any encoders that needs to be disabled. */
8597 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8598 base.head) {
8599 list_for_each_entry(connector,
8600 &dev->mode_config.connector_list,
8601 base.head) {
8602 if (connector->new_encoder == encoder) {
8603 WARN_ON(!connector->new_encoder->new_crtc);
8604
8605 goto next_encoder;
8606 }
8607 }
8608 encoder->new_crtc = NULL;
8609next_encoder:
8610 /* Only now check for crtc changes so we don't miss encoders
8611 * that will be disabled. */
8612 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8613 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8614 config->mode_changed = true;
50f56119
DV		 8615 }
8616 }
9a935856 8617 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8618
2e431051
DV		 8619 return 0;
8620}
8621
8622static int intel_crtc_set_config(struct drm_mode_set *set)
8623{
8624 struct drm_device *dev;
2e431051
DV		 8625 struct drm_mode_set save_set;
8626 struct intel_set_config *config;
8627 int ret;
2e431051 8628
8d3e375e
DV		 8629 BUG_ON(!set);
8630 BUG_ON(!set->crtc);
8631 BUG_ON(!set->crtc->helper_private);
2e431051 8632
7e53f3a4
DV		 8633 /* Enforce sane interface api - has been abused by the fb helper. */
8634 BUG_ON(!set->mode && set->fb);
8635 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8636
2e431051
DV		 8637 if (set->fb) {
8638 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8639 set->crtc->base.id, set->fb->base.id,
8640 (int)set->num_connectors, set->x, set->y);
8641 } else {
8642 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8643 }
8644
8645 dev = set->crtc->dev;
8646
8647 ret = -ENOMEM;
8648 config = kzalloc(sizeof(*config), GFP_KERNEL);
8649 if (!config)
8650 goto out_config;
8651
8652 ret = intel_set_config_save_state(dev, config);
8653 if (ret)
8654 goto out_config;
8655
8656 save_set.crtc = set->crtc;
8657 save_set.mode = &set->crtc->mode;
8658 save_set.x = set->crtc->x;
8659 save_set.y = set->crtc->y;
8660 save_set.fb = set->crtc->fb;
8661
8662 /* Compute whether we need a full modeset, only an fb base update or no
8663 * change at all. In the future we might also check whether only the
8664 * mode changed, e.g. for LVDS where we only change the panel fitter in
8665 * such cases. */
8666 intel_set_config_compute_mode_changes(set, config);
8667
9a935856 8668 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8669 if (ret)
8670 goto fail;
8671
5e2b584e 8672 if (config->mode_changed) {
c0c36b94
CW		 8673 ret = intel_set_mode(set->crtc, set->mode,
8674 set->x, set->y, set->fb);
8675 if (ret) {
8676 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8677 set->crtc->base.id, ret);
87f1faa6
DV		 8678 goto fail;
8679 }
5e2b584e 8680 } else if (config->fb_changed) {
4878cae2
VS		 8681 intel_crtc_wait_for_pending_flips(set->crtc);
8682
4f660f49 8683 ret = intel_pipe_set_base(set->crtc,
94352cf9 8684 set->x, set->y, set->fb);
50f56119
DV		 8685 }
8686
d9e55608
DV		 8687 intel_set_config_free(config);
8688
50f56119
DV		 8689 return 0;
8690
8691fail:
85f9eb71 8692 intel_set_config_restore_state(dev, config);
50f56119
DV		 8693
8694 /* Try to restore the config */
5e2b584e 8695 if (config->mode_changed &&
c0c36b94
CW		 8696 intel_set_mode(save_set.crtc, save_set.mode,
8697 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8698 DRM_ERROR("failed to restore config after modeset failure\n");
8699
d9e55608
DV		 8700out_config:
8701 intel_set_config_free(config);
50f56119
DV		 8702 return ret;
8703}
f6e5b160
CW		 8704
8705static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8706 .cursor_set = intel_crtc_cursor_set,
8707 .cursor_move = intel_crtc_cursor_move,
8708 .gamma_set = intel_crtc_gamma_set,
50f56119 8709 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8710 .destroy = intel_crtc_destroy,
8711 .page_flip = intel_crtc_page_flip,
8712};
8713
79f689aa
PZ		 8714static void intel_cpu_pll_init(struct drm_device *dev)
8715{
affa9354 8716 if (HAS_DDI(dev))
79f689aa
PZ		 8717 intel_ddi_pll_init(dev);
8718}
8719
ee7b9f93
JB		 8720static void intel_pch_pll_init(struct drm_device *dev)
8721{
8722 drm_i915_private_t *dev_priv = dev->dev_private;
8723 int i;
8724
8725 if (dev_priv->num_pch_pll == 0) {
8726 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8727 return;
8728 }
8729
8730 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8731 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8732 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8733 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8734 }
8735}
8736
b358d0a6 8737static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8738{
22fd0fab 8739 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8740 struct intel_crtc *intel_crtc;
8741 int i;
8742
8743 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8744 if (intel_crtc == NULL)
8745 return;
8746
8747 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8748
8749 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8750 for (i = 0; i < 256; i++) {
8751 intel_crtc->lut_r[i] = i;
8752 intel_crtc->lut_g[i] = i;
8753 intel_crtc->lut_b[i] = i;
8754 }
8755
80824003
JB		 8756 /* Swap pipes & planes for FBC on pre-965 */
8757 intel_crtc->pipe = pipe;
8758 intel_crtc->plane = pipe;
e2e767ab 8759 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8760 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8761 intel_crtc->plane = !pipe;
80824003
JB		 8762 }
8763
22fd0fab
JB		 8764 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8765 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8766 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8767 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8768
79e53945 8769 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8770}
8771
08d7b3d1 8772int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8773 struct drm_file *file)
08d7b3d1 8774{
08d7b3d1 8775 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8776 struct drm_mode_object *drmmode_obj;
8777 struct intel_crtc *crtc;
08d7b3d1 8778
1cff8f6b
DV		 8779 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8780 return -ENODEV;
08d7b3d1 8781
c05422d5
DV		 8782 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8783 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8784
c05422d5 8785 if (!drmmode_obj) {
08d7b3d1
CW		 8786 DRM_ERROR("no such CRTC id\n");
8787 return -EINVAL;
8788 }
8789
c05422d5
DV		 8790 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8791 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8792
c05422d5 8793 return 0;
08d7b3d1
CW		 8794}
8795
66a9278e 8796static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8797{
66a9278e
DV		 8798 struct drm_device *dev = encoder->base.dev;
8799 struct intel_encoder *source_encoder;
79e53945 8800 int index_mask = 0;
79e53945
JB		 8801 int entry = 0;
8802
66a9278e
DV		 8803 list_for_each_entry(source_encoder,
8804 &dev->mode_config.encoder_list, base.head) {
8805
8806 if (encoder == source_encoder)
79e53945 8807 index_mask |= (1 << entry);
66a9278e
DV		 8808
8809 /* Intel hw has only one MUX where enocoders could be cloned. */
8810 if (encoder->cloneable && source_encoder->cloneable)
8811 index_mask |= (1 << entry);
8812
79e53945
JB		 8813 entry++;
8814 }
4ef69c7a 8815
79e53945
JB		 8816 return index_mask;
8817}
8818
4d302442
CW		 8819static bool has_edp_a(struct drm_device *dev)
8820{
8821 struct drm_i915_private *dev_priv = dev->dev_private;
8822
8823 if (!IS_MOBILE(dev))
8824 return false;
8825
8826 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8827 return false;
8828
8829 if (IS_GEN5(dev) &&
8830 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8831 return false;
8832
8833 return true;
8834}
8835
79e53945
JB		 8836static void intel_setup_outputs(struct drm_device *dev)
8837{
725e30ad 8838 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8839 struct intel_encoder *encoder;
cb0953d7 8840 bool dpd_is_edp = false;
f3cfcba6 8841 bool has_lvds;
79e53945 8842
f3cfcba6 8843 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8844 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8845 /* disable the panel fitter on everything but LVDS */
8846 I915_WRITE(PFIT_CONTROL, 0);
8847 }
79e53945 8848
c40c0f5b 8849 if (!IS_ULT(dev))
79935fca 8850 intel_crt_init(dev);
cb0953d7 8851
affa9354 8852 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8853 int found;
8854
8855 /* Haswell uses DDI functions to detect digital outputs */
8856 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8857 /* DDI A only supports eDP */
8858 if (found)
8859 intel_ddi_init(dev, PORT_A);
8860
8861 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8862 * register */
8863 found = I915_READ(SFUSE_STRAP);
8864
8865 if (found & SFUSE_STRAP_DDIB_DETECTED)
8866 intel_ddi_init(dev, PORT_B);
8867 if (found & SFUSE_STRAP_DDIC_DETECTED)
8868 intel_ddi_init(dev, PORT_C);
8869 if (found & SFUSE_STRAP_DDID_DETECTED)
8870 intel_ddi_init(dev, PORT_D);
8871 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8872 int found;
270b3042
DV		 8873 dpd_is_edp = intel_dpd_is_edp(dev);
8874
8875 if (has_edp_a(dev))
8876 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8877
dc0fa718 8878 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8879 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8880 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8881 if (!found)
e2debe91 8882 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8883 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8884 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8885 }
8886
dc0fa718 8887 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8888 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8889
dc0fa718 8890 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8891 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8892
5eb08b69 8893 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8894 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8895
270b3042 8896 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8897 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8898 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8899 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8900 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8901 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8902
dc0fa718 8903 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8904 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8905 PORT_B);
67cfc203
VS		 8906 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8907 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8908 }
103a196f 8909 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8910 bool found = false;
7d57382e 8911
e2debe91 8912 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8913 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8914 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8915 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8916 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8917 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8918 }
27185ae1 8919
e7281eab 8920 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8921 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 8922 }
13520b05
KH		 8923
8924 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8925
e2debe91 8926 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8927 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8928 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8929 }
27185ae1 8930
e2debe91 8931 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8932
b01f2c3a
JB		 8933 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8934 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8935 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 8936 }
e7281eab 8937 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8938 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 8939 }
27185ae1 8940
b01f2c3a 8941 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 8942 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 8943 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 8944 } else if (IS_GEN2(dev))
79e53945
JB		 8945 intel_dvo_init(dev);
8946
103a196f 8947 if (SUPPORTS_TV(dev))
79e53945
JB		 8948 intel_tv_init(dev);
8949
4ef69c7a
CW		 8950 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8951 encoder->base.possible_crtcs = encoder->crtc_mask;
8952 encoder->base.possible_clones =
66a9278e 8953 intel_encoder_clones(encoder);
79e53945 8954 }
47356eb6 8955
dde86e2d 8956 intel_init_pch_refclk(dev);
270b3042
DV		 8957
8958 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8959}
8960
8961static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8962{
8963 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8964
8965 drm_framebuffer_cleanup(fb);
05394f39 8966 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8967
8968 kfree(intel_fb);
8969}
8970
8971static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8972 struct drm_file *file,
79e53945
JB		 8973 unsigned int *handle)
8974{
8975 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8976 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8977
05394f39 8978 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8979}
8980
8981static const struct drm_framebuffer_funcs intel_fb_funcs = {
8982 .destroy = intel_user_framebuffer_destroy,
8983 .create_handle = intel_user_framebuffer_create_handle,
8984};
8985
38651674
DA		 8986int intel_framebuffer_init(struct drm_device *dev,
8987 struct intel_framebuffer *intel_fb,
308e5bcb 8988 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8989 struct drm_i915_gem_object *obj)
79e53945 8990{
79e53945
JB		 8991 int ret;
8992
c16ed4be
CW		 8993 if (obj->tiling_mode == I915_TILING_Y) {
8994 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8995 return -EINVAL;
c16ed4be 8996 }
57cd6508 8997
c16ed4be
CW		 8998 if (mode_cmd->pitches[0] & 63) {
8999 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9000 mode_cmd->pitches[0]);
57cd6508 9001 return -EINVAL;
c16ed4be 9002 }
57cd6508 9003
5d7bd705 9004 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 9005 if (mode_cmd->pitches[0] > 32768) {
9006 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
9007 mode_cmd->pitches[0]);
5d7bd705 9008 return -EINVAL;
c16ed4be 9009 }
5d7bd705
VS		 9010
9011 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9012 mode_cmd->pitches[0] != obj->stride) {
9013 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9014 mode_cmd->pitches[0], obj->stride);
5d7bd705 9015 return -EINVAL;
c16ed4be 9016 }
5d7bd705 9017
57779d06 9018 /* Reject formats not supported by any plane early. */
308e5bcb 9019 switch (mode_cmd->pixel_format) {
57779d06 9020 case DRM_FORMAT_C8:
04b3924d
VS		 9021 case DRM_FORMAT_RGB565:
9022 case DRM_FORMAT_XRGB8888:
9023 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9024 break;
9025 case DRM_FORMAT_XRGB1555:
9026 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 9027 if (INTEL_INFO(dev)->gen > 3) {
9028 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9029 return -EINVAL;
c16ed4be 9030 }
57779d06
VS		 9031 break;
9032 case DRM_FORMAT_XBGR8888:
9033 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9034 case DRM_FORMAT_XRGB2101010:
9035 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9036 case DRM_FORMAT_XBGR2101010:
9037 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 9038 if (INTEL_INFO(dev)->gen < 4) {
9039 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9040 return -EINVAL;
c16ed4be 9041 }
b5626747 9042 break;
04b3924d
VS		 9043 case DRM_FORMAT_YUYV:
9044 case DRM_FORMAT_UYVY:
9045 case DRM_FORMAT_YVYU:
9046 case DRM_FORMAT_VYUY:
c16ed4be
CW		 9047 if (INTEL_INFO(dev)->gen < 5) {
9048 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 9049 return -EINVAL;
c16ed4be 9050 }
57cd6508
CW		 9051 break;
9052 default:
c16ed4be 9053 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 9054 return -EINVAL;
9055 }
9056
90f9a336
VS		 9057 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9058 if (mode_cmd->offsets[0] != 0)
9059 return -EINVAL;
9060
c7d73f6a
DV		 9061 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9062 intel_fb->obj = obj;
9063
79e53945
JB		 9064 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9065 if (ret) {
9066 DRM_ERROR("framebuffer init failed %d\n", ret);
9067 return ret;
9068 }
9069
79e53945
JB		 9070 return 0;
9071}
9072
79e53945
JB		 9073static struct drm_framebuffer *
9074intel_user_framebuffer_create(struct drm_device *dev,
9075 struct drm_file *filp,
308e5bcb 9076 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9077{
05394f39 9078 struct drm_i915_gem_object *obj;
79e53945 9079
308e5bcb
JB		 9080 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9081 mode_cmd->handles[0]));
c8725226 9082 if (&obj->base == NULL)
cce13ff7 9083 return ERR_PTR(-ENOENT);
79e53945 9084
d2dff872 9085 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9086}
9087
79e53945 9088static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9089 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9090 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9091};
9092
e70236a8
JB		 9093/* Set up chip specific display functions */
9094static void intel_init_display(struct drm_device *dev)
9095{
9096 struct drm_i915_private *dev_priv = dev->dev_private;
9097
ee9300bb
DV		 9098 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9099 dev_priv->display.find_dpll = g4x_find_best_dpll;
9100 else if (IS_VALLEYVIEW(dev))
9101 dev_priv->display.find_dpll = vlv_find_best_dpll;
9102 else if (IS_PINEVIEW(dev))
9103 dev_priv->display.find_dpll = pnv_find_best_dpll;
9104 else
9105 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9106
affa9354 9107 if (HAS_DDI(dev)) {
0e8ffe1b 9108 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9109 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9110 dev_priv->display.crtc_enable = haswell_crtc_enable;
9111 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9112 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9113 dev_priv->display.update_plane = ironlake_update_plane;
9114 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9115 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9116 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9117 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9118 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9119 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9120 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9121 } else if (IS_VALLEYVIEW(dev)) {
9122 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9123 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9124 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9125 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9126 dev_priv->display.off = i9xx_crtc_off;
9127 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9128 } else {
0e8ffe1b 9129 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9130 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9131 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9132 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9133 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9134 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9135 }
e70236a8 9136
e70236a8 9137 /* Returns the core display clock speed */
25eb05fc
JB		 9138 if (IS_VALLEYVIEW(dev))
9139 dev_priv->display.get_display_clock_speed =
9140 valleyview_get_display_clock_speed;
9141 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9142 dev_priv->display.get_display_clock_speed =
9143 i945_get_display_clock_speed;
9144 else if (IS_I915G(dev))
9145 dev_priv->display.get_display_clock_speed =
9146 i915_get_display_clock_speed;
f2b115e6 9147 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9148 dev_priv->display.get_display_clock_speed =
9149 i9xx_misc_get_display_clock_speed;
9150 else if (IS_I915GM(dev))
9151 dev_priv->display.get_display_clock_speed =
9152 i915gm_get_display_clock_speed;
9153 else if (IS_I865G(dev))
9154 dev_priv->display.get_display_clock_speed =
9155 i865_get_display_clock_speed;
f0f8a9ce 9156 else if (IS_I85X(dev))
e70236a8
JB		 9157 dev_priv->display.get_display_clock_speed =
9158 i855_get_display_clock_speed;
9159 else /* 852, 830 */
9160 dev_priv->display.get_display_clock_speed =
9161 i830_get_display_clock_speed;
9162
7f8a8569 9163 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9164 if (IS_GEN5(dev)) {
674cf967 9165 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9166 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9167 } else if (IS_GEN6(dev)) {
674cf967 9168 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9169 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9170 } else if (IS_IVYBRIDGE(dev)) {
9171 /* FIXME: detect B0+ stepping and use auto training */
9172 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9173 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9174 dev_priv->display.modeset_global_resources =
9175 ivb_modeset_global_resources;
c82e4d26
ED		 9176 } else if (IS_HASWELL(dev)) {
9177 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9178 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9179 dev_priv->display.modeset_global_resources =
9180 haswell_modeset_global_resources;
a0e63c22 9181 }
6067aaea 9182 } else if (IS_G4X(dev)) {
e0dac65e 9183 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9184 }
8c9f3aaf
JB		 9185
9186 /* Default just returns -ENODEV to indicate unsupported */
9187 dev_priv->display.queue_flip = intel_default_queue_flip;
9188
9189 switch (INTEL_INFO(dev)->gen) {
9190 case 2:
9191 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9192 break;
9193
9194 case 3:
9195 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9196 break;
9197
9198 case 4:
9199 case 5:
9200 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9201 break;
9202
9203 case 6:
9204 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9205 break;
7c9017e5
JB		 9206 case 7:
9207 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9208 break;
8c9f3aaf 9209 }
e70236a8
JB		 9210}
9211
b690e96c
JB		 9212/*
9213 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9214 * resume, or other times. This quirk makes sure that's the case for
9215 * affected systems.
9216 */
0206e353 9217static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9218{
9219 struct drm_i915_private *dev_priv = dev->dev_private;
9220
9221 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9222 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9223}
9224
435793df
KP		 9225/*
9226 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9227 */
9228static void quirk_ssc_force_disable(struct drm_device *dev)
9229{
9230 struct drm_i915_private *dev_priv = dev->dev_private;
9231 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9232 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9233}
9234
4dca20ef 9235/*
5a15ab5b
CE		 9236 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9237 * brightness value
4dca20ef
CE		 9238 */
9239static void quirk_invert_brightness(struct drm_device *dev)
9240{
9241 struct drm_i915_private *dev_priv = dev->dev_private;
9242 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9243 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9244}
9245
b690e96c
JB		 9246struct intel_quirk {
9247 int device;
9248 int subsystem_vendor;
9249 int subsystem_device;
9250 void (*hook)(struct drm_device *dev);
9251};
9252
5f85f176
EE		 9253/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9254struct intel_dmi_quirk {
9255 void (*hook)(struct drm_device *dev);
9256 const struct dmi_system_id (*dmi_id_list)[];
9257};
9258
9259static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9260{
9261 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9262 return 1;
9263}
9264
9265static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9266 {
9267 .dmi_id_list = &(const struct dmi_system_id[]) {
9268 {
9269 .callback = intel_dmi_reverse_brightness,
9270 .ident = "NCR Corporation",
9271 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9272 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9273 },
9274 },
9275 { } /* terminating entry */
9276 },
9277 .hook = quirk_invert_brightness,
9278 },
9279};
9280
c43b5634 9281static struct intel_quirk intel_quirks[] = {
b690e96c 9282 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9283 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9284
b690e96c
JB		 9285 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9286 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9287
b690e96c
JB		 9288 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9289 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9290
ccd0d36e 9291 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9292 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9293 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9294
9295 /* Lenovo U160 cannot use SSC on LVDS */
9296 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9297
9298 /* Sony Vaio Y cannot use SSC on LVDS */
9299 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9300
9301 /* Acer Aspire 5734Z must invert backlight brightness */
9302 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9303
9304 /* Acer/eMachines G725 */
9305 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9306
9307 /* Acer/eMachines e725 */
9308 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9309
9310 /* Acer/Packard Bell NCL20 */
9311 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9312
9313 /* Acer Aspire 4736Z */
9314 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9315};
9316
9317static void intel_init_quirks(struct drm_device *dev)
9318{
9319 struct pci_dev *d = dev->pdev;
9320 int i;
9321
9322 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9323 struct intel_quirk *q = &intel_quirks[i];
9324
9325 if (d->device == q->device &&
9326 (d->subsystem_vendor == q->subsystem_vendor ||
9327 q->subsystem_vendor == PCI_ANY_ID) &&
9328 (d->subsystem_device == q->subsystem_device ||
9329 q->subsystem_device == PCI_ANY_ID))
9330 q->hook(dev);
9331 }
5f85f176
EE		 9332 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9333 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9334 intel_dmi_quirks[i].hook(dev);
9335 }
b690e96c
JB		 9336}
9337
9cce37f4
JB		 9338/* Disable the VGA plane that we never use */
9339static void i915_disable_vga(struct drm_device *dev)
9340{
9341 struct drm_i915_private *dev_priv = dev->dev_private;
9342 u8 sr1;
766aa1c4 9343 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9344
9345 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9346 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9347 sr1 = inb(VGA_SR_DATA);
9348 outb(sr1 | 1<<5, VGA_SR_DATA);
9349 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9350 udelay(300);
9351
9352 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9353 POSTING_READ(vga_reg);
9354}
9355
f817586c
DV		 9356void intel_modeset_init_hw(struct drm_device *dev)
9357{
fa42e23c 9358 intel_init_power_well(dev);
0232e927 9359
a8f78b58
ED		 9360 intel_prepare_ddi(dev);
9361
f817586c
DV		 9362 intel_init_clock_gating(dev);
9363
79f5b2c7 9364 mutex_lock(&dev->struct_mutex);
8090c6b9 9365 intel_enable_gt_powersave(dev);
79f5b2c7 9366 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9367}
9368
7d708ee4
ID		 9369void intel_modeset_suspend_hw(struct drm_device *dev)
9370{
9371 intel_suspend_hw(dev);
9372}
9373
79e53945
JB		 9374void intel_modeset_init(struct drm_device *dev)
9375{
652c393a 9376 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9377 int i, j, ret;
79e53945
JB		 9378
9379 drm_mode_config_init(dev);
9380
9381 dev->mode_config.min_width = 0;
9382 dev->mode_config.min_height = 0;
9383
019d96cb
DA		 9384 dev->mode_config.preferred_depth = 24;
9385 dev->mode_config.prefer_shadow = 1;
9386
e6ecefaa 9387 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9388
b690e96c
JB		 9389 intel_init_quirks(dev);
9390
1fa61106
ED		 9391 intel_init_pm(dev);
9392
e3c74757
BW		 9393 if (INTEL_INFO(dev)->num_pipes == 0)
9394 return;
9395
e70236a8
JB		 9396 intel_init_display(dev);
9397
a6c45cf0
CW		 9398 if (IS_GEN2(dev)) {
9399 dev->mode_config.max_width = 2048;
9400 dev->mode_config.max_height = 2048;
9401 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9402 dev->mode_config.max_width = 4096;
9403 dev->mode_config.max_height = 4096;
79e53945 9404 } else {
a6c45cf0
CW		 9405 dev->mode_config.max_width = 8192;
9406 dev->mode_config.max_height = 8192;
79e53945 9407 }
5d4545ae 9408 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9409
28c97730 9410 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9411 INTEL_INFO(dev)->num_pipes,
9412 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9413
7eb552ae 9414 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9415 intel_crtc_init(dev, i);
7f1f3851
JB		 9416 for (j = 0; j < dev_priv->num_plane; j++) {
9417 ret = intel_plane_init(dev, i, j);
9418 if (ret)
06da8da2
VS		 9419 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9420 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9421 }
79e53945
JB		 9422 }
9423
79f689aa 9424 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9425 intel_pch_pll_init(dev);
9426
9cce37f4
JB		 9427 /* Just disable it once at startup */
9428 i915_disable_vga(dev);
79e53945 9429 intel_setup_outputs(dev);
11be49eb
CW		 9430
9431 /* Just in case the BIOS is doing something questionable. */
9432 intel_disable_fbc(dev);
2c7111db
CW		 9433}
9434
24929352
DV		 9435static void
9436intel_connector_break_all_links(struct intel_connector *connector)
9437{
9438 connector->base.dpms = DRM_MODE_DPMS_OFF;
9439 connector->base.encoder = NULL;
9440 connector->encoder->connectors_active = false;
9441 connector->encoder->base.crtc = NULL;
9442}
9443
7fad798e
DV		 9444static void intel_enable_pipe_a(struct drm_device *dev)
9445{
9446 struct intel_connector *connector;
9447 struct drm_connector *crt = NULL;
9448 struct intel_load_detect_pipe load_detect_temp;
9449
9450 /* We can't just switch on the pipe A, we need to set things up with a
9451 * proper mode and output configuration. As a gross hack, enable pipe A
9452 * by enabling the load detect pipe once. */
9453 list_for_each_entry(connector,
9454 &dev->mode_config.connector_list,
9455 base.head) {
9456 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9457 crt = &connector->base;
9458 break;
9459 }
9460 }
9461
9462 if (!crt)
9463 return;
9464
9465 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9466 intel_release_load_detect_pipe(crt, &load_detect_temp);
9467
652c393a 9468
7fad798e
DV		 9469}
9470
fa555837
DV		 9471static bool
9472intel_check_plane_mapping(struct intel_crtc *crtc)
9473{
7eb552ae
BW		 9474 struct drm_device *dev = crtc->base.dev;
9475 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9476 u32 reg, val;
9477
7eb552ae 9478 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9479 return true;
9480
9481 reg = DSPCNTR(!crtc->plane);
9482 val = I915_READ(reg);
9483
9484 if ((val & DISPLAY_PLANE_ENABLE) &&
9485 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9486 return false;
9487
9488 return true;
9489}
9490
24929352
DV		 9491static void intel_sanitize_crtc(struct intel_crtc *crtc)
9492{
9493 struct drm_device *dev = crtc->base.dev;
9494 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9495 u32 reg;
24929352 9496
24929352 9497 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9498 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9499 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9500
9501 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9502 * disable the crtc (and hence change the state) if it is wrong. Note
9503 * that gen4+ has a fixed plane -> pipe mapping. */
9504 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9505 struct intel_connector *connector;
9506 bool plane;
9507
24929352
DV		 9508 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9509 crtc->base.base.id);
9510
9511 /* Pipe has the wrong plane attached and the plane is active.
9512 * Temporarily change the plane mapping and disable everything
9513 * ... */
9514 plane = crtc->plane;
9515 crtc->plane = !plane;
9516 dev_priv->display.crtc_disable(&crtc->base);
9517 crtc->plane = plane;
9518
9519 /* ... and break all links. */
9520 list_for_each_entry(connector, &dev->mode_config.connector_list,
9521 base.head) {
9522 if (connector->encoder->base.crtc != &crtc->base)
9523 continue;
9524
9525 intel_connector_break_all_links(connector);
9526 }
9527
9528 WARN_ON(crtc->active);
9529 crtc->base.enabled = false;
9530 }
24929352 9531
7fad798e
DV		 9532 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9533 crtc->pipe == PIPE_A && !crtc->active) {
9534 /* BIOS forgot to enable pipe A, this mostly happens after
9535 * resume. Force-enable the pipe to fix this, the update_dpms
9536 * call below we restore the pipe to the right state, but leave
9537 * the required bits on. */
9538 intel_enable_pipe_a(dev);
9539 }
9540
24929352
DV		 9541 /* Adjust the state of the output pipe according to whether we
9542 * have active connectors/encoders. */
9543 intel_crtc_update_dpms(&crtc->base);
9544
9545 if (crtc->active != crtc->base.enabled) {
9546 struct intel_encoder *encoder;
9547
9548 /* This can happen either due to bugs in the get_hw_state
9549 * functions or because the pipe is force-enabled due to the
9550 * pipe A quirk. */
9551 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9552 crtc->base.base.id,
9553 crtc->base.enabled ? "enabled" : "disabled",
9554 crtc->active ? "enabled" : "disabled");
9555
9556 crtc->base.enabled = crtc->active;
9557
9558 /* Because we only establish the connector -> encoder ->
9559 * crtc links if something is active, this means the
9560 * crtc is now deactivated. Break the links. connector
9561 * -> encoder links are only establish when things are
9562 * actually up, hence no need to break them. */
9563 WARN_ON(crtc->active);
9564
9565 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9566 WARN_ON(encoder->connectors_active);
9567 encoder->base.crtc = NULL;
9568 }
9569 }
9570}
9571
9572static void intel_sanitize_encoder(struct intel_encoder *encoder)
9573{
9574 struct intel_connector *connector;
9575 struct drm_device *dev = encoder->base.dev;
9576
9577 /* We need to check both for a crtc link (meaning that the
9578 * encoder is active and trying to read from a pipe) and the
9579 * pipe itself being active. */
9580 bool has_active_crtc = encoder->base.crtc &&
9581 to_intel_crtc(encoder->base.crtc)->active;
9582
9583 if (encoder->connectors_active && !has_active_crtc) {
9584 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9585 encoder->base.base.id,
9586 drm_get_encoder_name(&encoder->base));
9587
9588 /* Connector is active, but has no active pipe. This is
9589 * fallout from our resume register restoring. Disable
9590 * the encoder manually again. */
9591 if (encoder->base.crtc) {
9592 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9593 encoder->base.base.id,
9594 drm_get_encoder_name(&encoder->base));
9595 encoder->disable(encoder);
9596 }
9597
9598 /* Inconsistent output/port/pipe state happens presumably due to
9599 * a bug in one of the get_hw_state functions. Or someplace else
9600 * in our code, like the register restore mess on resume. Clamp
9601 * things to off as a safer default. */
9602 list_for_each_entry(connector,
9603 &dev->mode_config.connector_list,
9604 base.head) {
9605 if (connector->encoder != encoder)
9606 continue;
9607
9608 intel_connector_break_all_links(connector);
9609 }
9610 }
9611 /* Enabled encoders without active connectors will be fixed in
9612 * the crtc fixup. */
9613}
9614
44cec740 9615void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9616{
9617 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9618 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9619
9620 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9621 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9622 i915_disable_vga(dev);
0fde901f
KM		 9623 }
9624}
9625
24929352
DV		 9626/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9627 * and i915 state tracking structures. */
45e2b5f6
DV		 9628void intel_modeset_setup_hw_state(struct drm_device *dev,
9629 bool force_restore)
24929352
DV		 9630{
9631 struct drm_i915_private *dev_priv = dev->dev_private;
9632 enum pipe pipe;
b5644d05 9633 struct drm_plane *plane;
24929352
DV		 9634 struct intel_crtc *crtc;
9635 struct intel_encoder *encoder;
9636 struct intel_connector *connector;
9637
0e8ffe1b
DV		 9638 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9639 base.head) {
88adfff1 9640 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9641
0e8ffe1b
DV		 9642 crtc->active = dev_priv->display.get_pipe_config(crtc,
9643 &crtc->config);
24929352
DV		 9644
9645 crtc->base.enabled = crtc->active;
9646
9647 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9648 crtc->base.base.id,
9649 crtc->active ? "enabled" : "disabled");
9650 }
9651
affa9354 9652 if (HAS_DDI(dev))
6441ab5f
PZ		 9653 intel_ddi_setup_hw_pll_state(dev);
9654
24929352
DV		 9655 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9656 base.head) {
9657 pipe = 0;
9658
9659 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9660 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9661 encoder->base.crtc = &crtc->base;
9662 if (encoder->get_config)
9663 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9664 } else {
9665 encoder->base.crtc = NULL;
9666 }
9667
9668 encoder->connectors_active = false;
9669 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9670 encoder->base.base.id,
9671 drm_get_encoder_name(&encoder->base),
9672 encoder->base.crtc ? "enabled" : "disabled",
9673 pipe);
9674 }
9675
9676 list_for_each_entry(connector, &dev->mode_config.connector_list,
9677 base.head) {
9678 if (connector->get_hw_state(connector)) {
9679 connector->base.dpms = DRM_MODE_DPMS_ON;
9680 connector->encoder->connectors_active = true;
9681 connector->base.encoder = &connector->encoder->base;
9682 } else {
9683 connector->base.dpms = DRM_MODE_DPMS_OFF;
9684 connector->base.encoder = NULL;
9685 }
9686 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9687 connector->base.base.id,
9688 drm_get_connector_name(&connector->base),
9689 connector->base.encoder ? "enabled" : "disabled");
9690 }
9691
9692 /* HW state is read out, now we need to sanitize this mess. */
9693 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9694 base.head) {
9695 intel_sanitize_encoder(encoder);
9696 }
9697
9698 for_each_pipe(pipe) {
9699 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9700 intel_sanitize_crtc(crtc);
c0b03411 9701 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 9702 }
9a935856 9703
45e2b5f6 9704 if (force_restore) {
f30da187
DV		 9705 /*
9706 * We need to use raw interfaces for restoring state to avoid
9707 * checking (bogus) intermediate states.
9708 */
45e2b5f6 9709 for_each_pipe(pipe) {
b5644d05
JB		 9710 struct drm_crtc *crtc =
9711 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9712
9713 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9714 crtc->fb);
45e2b5f6 9715 }
b5644d05
JB		 9716 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9717 intel_plane_restore(plane);
0fde901f
KM		 9718
9719 i915_redisable_vga(dev);
45e2b5f6
DV		 9720 } else {
9721 intel_modeset_update_staged_output_state(dev);
9722 }
8af6cf88
DV		 9723
9724 intel_modeset_check_state(dev);
2e938892
DV		 9725
9726 drm_mode_config_reset(dev);
2c7111db
CW		 9727}
9728
9729void intel_modeset_gem_init(struct drm_device *dev)
9730{
1833b134 9731 intel_modeset_init_hw(dev);
02e792fb
DV		 9732
9733 intel_setup_overlay(dev);
24929352 9734
45e2b5f6 9735 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9736}
9737
9738void intel_modeset_cleanup(struct drm_device *dev)
9739{
652c393a
JB		 9740 struct drm_i915_private *dev_priv = dev->dev_private;
9741 struct drm_crtc *crtc;
9742 struct intel_crtc *intel_crtc;
9743
fd0c0642
DV		 9744 /*
9745 * Interrupts and polling as the first thing to avoid creating havoc.
9746 * Too much stuff here (turning of rps, connectors, ...) would
9747 * experience fancy races otherwise.
9748 */
9749 drm_irq_uninstall(dev);
9750 cancel_work_sync(&dev_priv->hotplug_work);
9751 /*
9752 * Due to the hpd irq storm handling the hotplug work can re-arm the
9753 * poll handlers. Hence disable polling after hpd handling is shut down.
9754 */
f87ea761 9755 drm_kms_helper_poll_fini(dev);
fd0c0642 9756
652c393a
JB		 9757 mutex_lock(&dev->struct_mutex);
9758
723bfd70
JB		 9759 intel_unregister_dsm_handler();
9760
652c393a
JB		 9761 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9762 /* Skip inactive CRTCs */
9763 if (!crtc->fb)
9764 continue;
9765
9766 intel_crtc = to_intel_crtc(crtc);
3dec0095 9767 intel_increase_pllclock(crtc);
652c393a
JB		 9768 }
9769
973d04f9 9770 intel_disable_fbc(dev);
e70236a8 9771
8090c6b9 9772 intel_disable_gt_powersave(dev);
0cdab21f 9773
930ebb46
DV		 9774 ironlake_teardown_rc6(dev);
9775
69341a5e
KH		 9776 mutex_unlock(&dev->struct_mutex);
9777
1630fe75
CW		 9778 /* flush any delayed tasks or pending work */
9779 flush_scheduled_work();
9780
dc652f90
JN		 9781 /* destroy backlight, if any, before the connectors */
9782 intel_panel_destroy_backlight(dev);
9783
79e53945 9784 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9785
9786 intel_cleanup_overlay(dev);
79e53945
JB		 9787}
9788
f1c79df3
ZW		 9789/*
9790 * Return which encoder is currently attached for connector.
9791 */
df0e9248 9792struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9793{
df0e9248
CW		 9794 return &intel_attached_encoder(connector)->base;
9795}
f1c79df3 9796
df0e9248
CW		 9797void intel_connector_attach_encoder(struct intel_connector *connector,
9798 struct intel_encoder *encoder)
9799{
9800 connector->encoder = encoder;
9801 drm_mode_connector_attach_encoder(&connector->base,
9802 &encoder->base);
79e53945 9803}
28d52043
DA		 9804
9805/*
9806 * set vga decode state - true == enable VGA decode
9807 */
9808int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9809{
9810 struct drm_i915_private *dev_priv = dev->dev_private;
9811 u16 gmch_ctrl;
9812
9813 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9814 if (state)
9815 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9816 else
9817 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9818 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9819 return 0;
9820}
c4a1d9e4
CW		 9821
9822#ifdef CONFIG_DEBUG_FS
9823#include <linux/seq_file.h>
9824
9825struct intel_display_error_state {
ff57f1b0
PZ		 9826
9827 u32 power_well_driver;
9828
c4a1d9e4
CW		 9829 struct intel_cursor_error_state {
9830 u32 control;
9831 u32 position;
9832 u32 base;
9833 u32 size;
52331309 9834 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9835
9836 struct intel_pipe_error_state {
ff57f1b0 9837 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9838 u32 conf;
9839 u32 source;
9840
9841 u32 htotal;
9842 u32 hblank;
9843 u32 hsync;
9844 u32 vtotal;
9845 u32 vblank;
9846 u32 vsync;
52331309 9847 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9848
9849 struct intel_plane_error_state {
9850 u32 control;
9851 u32 stride;
9852 u32 size;
9853 u32 pos;
9854 u32 addr;
9855 u32 surface;
9856 u32 tile_offset;
52331309 9857 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9858};
9859
9860struct intel_display_error_state *
9861intel_display_capture_error_state(struct drm_device *dev)
9862{
0206e353 9863 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9864 struct intel_display_error_state *error;
702e7a56 9865 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9866 int i;
9867
9868 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9869 if (error == NULL)
9870 return NULL;
9871
ff57f1b0
PZ		 9872 if (HAS_POWER_WELL(dev))
9873 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9874
52331309 9875 for_each_pipe(i) {
702e7a56 9876 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 9877 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 9878
a18c4c3d
PZ		 9879 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9880 error->cursor[i].control = I915_READ(CURCNTR(i));
9881 error->cursor[i].position = I915_READ(CURPOS(i));
9882 error->cursor[i].base = I915_READ(CURBASE(i));
9883 } else {
9884 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9885 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9886 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9887 }
c4a1d9e4
CW		 9888
9889 error->plane[i].control = I915_READ(DSPCNTR(i));
9890 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9891 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9892 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9893 error->plane[i].pos = I915_READ(DSPPOS(i));
9894 }
ca291363
PZ		 9895 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9896 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9897 if (INTEL_INFO(dev)->gen >= 4) {
9898 error->plane[i].surface = I915_READ(DSPSURF(i));
9899 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9900 }
9901
702e7a56 9902 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9903 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9904 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9905 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9906 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9907 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9908 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9909 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9910 }
9911
12d217c7
PZ		 9912 /* In the code above we read the registers without checking if the power
9913 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9914 * prevent the next I915_WRITE from detecting it and printing an error
9915 * message. */
9916 if (HAS_POWER_WELL(dev))
9917 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9918
c4a1d9e4
CW		 9919 return error;
9920}
9921
edc3d884
MK		 9922#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9923
c4a1d9e4 9924void
edc3d884 9925intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 9926 struct drm_device *dev,
9927 struct intel_display_error_state *error)
9928{
9929 int i;
9930
edc3d884 9931 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 9932 if (HAS_POWER_WELL(dev))
edc3d884 9933 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 9934 error->power_well_driver);
52331309 9935 for_each_pipe(i) {
edc3d884
MK		 9936 err_printf(m, "Pipe [%d]:\n", i);
9937 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 9938 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 9939 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9940 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
9941 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9942 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9943 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9944 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9945 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9946 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9947
9948 err_printf(m, "Plane [%d]:\n", i);
9949 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
9950 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9951 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 9952 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
9953 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 9954 }
4b71a570 9955 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 9956 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 9957 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 9958 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
9959 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 9960 }
9961
edc3d884
MK		 9962 err_printf(m, "Cursor [%d]:\n", i);
9963 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9964 err_printf(m, " POS: %08x\n", error->cursor[i].position);
9965 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 9966 }
9967}
9968#endif
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