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drm/i915: call crtc functions directly
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
a0c4da24
JB		 101static bool
102intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
021357ac
CW		 106static inline u32 /* units of 100MHz */
107intel_fdi_link_freq(struct drm_device *dev)
108{
8b99e68c
CW		 109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
021357ac
CW		 114}
115
e4b36699 116static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
d4906093 127 .find_pll = intel_find_best_PLL,
e4b36699
KP		 128};
129
130static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
d4906093 141 .find_pll = intel_find_best_PLL,
e4b36699 142};
273e27ca 143
e4b36699 144static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
d4906093 155 .find_pll = intel_find_best_PLL,
e4b36699
KP		 156};
157
158static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
d4906093 169 .find_pll = intel_find_best_PLL,
e4b36699
KP		 170};
171
273e27ca 172
e4b36699 173static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
044c7c41 185 },
d4906093 186 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 187};
188
189static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
d4906093 200 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 201};
202
203static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
044c7c41 214 },
d4906093 215 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 216};
217
218static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
044c7c41 229 },
d4906093 230 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 231};
232
233static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
273e27ca 243 .p2_slow = 10, .p2_fast = 10 },
0206e353 244 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 245};
246
f2b115e6 247static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 250 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
273e27ca 253 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
6115707b 260 .find_pll = intel_find_best_PLL,
e4b36699
KP		 261};
262
f2b115e6 263static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
6115707b 274 .find_pll = intel_find_best_PLL,
e4b36699
KP		 275};
276
273e27ca
EA		 277/* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
b91ad0ec 282static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
4547668a 293 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 294};
295
b91ad0ec 296static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 307 .find_pll = intel_g4x_find_best_PLL,
308};
309
310static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 321 .find_pll = intel_g4x_find_best_PLL,
322};
323
273e27ca 324/* LVDS 100mhz refclk limits. */
b91ad0ec 325static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
0206e353 333 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 336 .find_pll = intel_g4x_find_best_PLL,
337};
338
339static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
0206e353 347 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 350 .find_pll = intel_g4x_find_best_PLL,
351};
352
353static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
273e27ca 363 .p2_slow = 10, .p2_fast = 10 },
0206e353 364 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 365};
366
a0c4da24
JB		 367static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379};
380
381static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393};
394
395static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407};
408
57f350b6
JB		 409u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410{
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432}
433
a0c4da24
JB		 434static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436{
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454}
455
57f350b6
JB		 456static void vlv_init_dpio(struct drm_device *dev)
457{
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465}
466
618563e3
DV		 467static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468{
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471}
472
473static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483};
484
b0354385
TI		 485static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487{
488 unsigned int val;
489
121d527a
TI		 490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
618563e3
DV		 494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
b0354385
TI		 497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
14d94a3d 506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511}
512
1b894b59
CW		 513static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
2c07245f 515{
b91ad0ec
ZW		 516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 518 const intel_limit_t *limit;
b91ad0ec
ZW		 519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 522 /* LVDS dual channel */
1b894b59 523 if (refclk == 100000)
b91ad0ec
ZW		 524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
1b894b59 528 if (refclk == 100000)
b91ad0ec
ZW		 529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
2c07245f 536 else
b91ad0ec 537 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 538
539 return limit;
540}
541
044c7c41
ML		 542static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543{
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 549 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 550 /* LVDS with dual channel */
e4b36699 551 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 552 else
553 /* LVDS with dual channel */
e4b36699 554 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 557 limit = &intel_limits_g4x_hdmi;
044c7c41 558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 559 limit = &intel_limits_g4x_sdvo;
0206e353 560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 561 limit = &intel_limits_g4x_display_port;
044c7c41 562 } else /* The option is for other outputs */
e4b36699 563 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 564
565 return limit;
566}
567
1b894b59 568static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 569{
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
bad720ff 573 if (HAS_PCH_SPLIT(dev))
1b894b59 574 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 575 else if (IS_G4X(dev)) {
044c7c41 576 limit = intel_g4x_limit(crtc);
f2b115e6 577 } else if (IS_PINEVIEW(dev)) {
2177832f 578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 579 limit = &intel_limits_pineview_lvds;
2177832f 580 else
f2b115e6 581 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 596 limit = &intel_limits_i8xx_lvds;
79e53945 597 else
e4b36699 598 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 599 }
600 return limit;
601}
602
f2b115e6
AJ		 603/* m1 is reserved as 0 in Pineview, n is a ring counter */
604static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 605{
2177832f
SL		 606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610}
611
612static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613{
f2b115e6
AJ		 614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
2177832f
SL		 616 return;
617 }
79e53945
JB		 618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622}
623
79e53945
JB		 624/**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
4ef69c7a 627bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 628{
4ef69c7a 629 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 630 struct intel_encoder *encoder;
631
6c2b7c12
DV		 632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
4ef69c7a
CW		 634 return true;
635
636 return false;
79e53945
JB		 637}
638
7c04d1d9 639#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 640/**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
1b894b59
CW		 645static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
79e53945 648{
79e53945 649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 650 INTELPllInvalid("p1 out of range\n");
79e53945 651 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 652 INTELPllInvalid("p out of range\n");
79e53945 653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 654 INTELPllInvalid("m2 out of range\n");
79e53945 655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 656 INTELPllInvalid("m1 out of range\n");
f2b115e6 657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 658 INTELPllInvalid("m1 <= m2\n");
79e53945 659 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 660 INTELPllInvalid("m out of range\n");
79e53945 661 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 662 INTELPllInvalid("n out of range\n");
79e53945 663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 664 INTELPllInvalid("vco out of range\n");
79e53945
JB		 665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 669 INTELPllInvalid("dot out of range\n");
79e53945
JB		 670
671 return true;
672}
673
d4906093
ML		 674static bool
675intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
d4906093 678
79e53945
JB		 679{
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
79e53945
JB		 683 int err = target;
684
bc5e5718 685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 686 (I915_READ(LVDS)) != 0) {
79e53945
JB		 687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
b0354385 693 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
0206e353 704 memset(best_clock, 0, sizeof(*best_clock));
79e53945 705
42158660
ZY		 706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 717 int this_err;
718
2177832f 719 intel_clock(dev, refclk, &clock);
1b894b59
CW		 720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
79e53945 722 continue;
cec2f356
SP		 723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
79e53945
JB		 726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738}
739
d4906093
ML		 740static bool
741intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
d4906093
ML		 744{
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
6ba770dc
AJ		 750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 755 int lvds_reg;
756
c619eed4 757 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
f77f13e2 775 /* based on hardware requirement, prefer smaller n to precision */
d4906093 776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 777 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
2177832f 786 intel_clock(dev, refclk, &clock);
1b894b59
CW		 787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
d4906093 789 continue;
cec2f356
SP		 790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
1b894b59
CW		 793
794 this_err = abs(clock.dot - target);
d4906093
ML		 795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
2c07245f
ZW		 805 return found;
806}
807
5eb08b69 808static bool
f2b115e6 809intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
5eb08b69
ZW		 812{
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
4547668a 815
5eb08b69
ZW		 816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832}
833
a4fc5ed6
KP		 834/* DisplayPort has only two frequencies, 162MHz and 270MHz */
835static bool
836intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
a4fc5ed6 839{
5eddb70b
CW		 840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
a4fc5ed6 860}
a0c4da24
JB		 861static bool
862intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865{
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
af447bd3 872 flag = 0;
a0c4da24
JB		 873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928}
a4fc5ed6 929
a928d536
PZ		 930static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931{
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939}
940
9d0498a2
JB		 941/**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 950{
9d0498a2 951 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 952 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 953
a928d536
PZ		 954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
300387c0
CW		 959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
9d0498a2 975 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
9d0498a2
JB		 979 DRM_DEBUG_KMS("vblank wait timed out\n");
980}
981
ab7ad7f6
KP		 982/*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
ab7ad7f6
KP		 991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
58e10eb9 997 *
9d0498a2 998 */
58e10eb9 999void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1000{
1001 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 1002
1003 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 1004 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 1005
1006 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
ab7ad7f6
KP		 1009 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1010 } else {
837ba00f 1011 u32 last_line, line_mask;
58e10eb9 1012 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
837ba00f
PZ		 1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
ab7ad7f6
KP		 1020 /* Wait for the display line to settle */
1021 do {
837ba00f 1022 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1023 mdelay(5);
837ba00f 1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
1027 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1028 }
79e53945
JB		 1029}
1030
b24e7179
JB		 1031static const char *state_string(bool enabled)
1032{
1033 return enabled ? "on" : "off";
1034}
1035
1036/* Only for pre-ILK configs */
1037static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039{
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050}
1051#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
040484af
JB		 1054/* For ILK+ */
1055static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
040484af 1059{
040484af
JB		 1060 u32 val;
1061 bool cur_state;
1062
9d82aa17
ED		 1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
92b27b08
CW		 1068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1070 return;
ee7b9f93 1071
92b27b08
CW		 1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
d3ccbe86 1095 }
040484af 1096}
92b27b08
CW		 1097#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1099
1100static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102{
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
bf507ef7
ED		 1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
040484af
JB		 1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120}
1121#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126{
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
59c859d6
ED		 1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
040484af
JB		 1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142}
1143#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148{
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
bf507ef7
ED		 1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
040484af
JB		 1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163}
1164
1165static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167{
1168 int reg;
1169 u32 val;
1170
59c859d6
ED		 1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
040484af
JB		 1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178}
1179
ea0760cf
JB		 1180static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182{
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
0de3b485 1186 bool locked = true;
ea0760cf
JB		 1187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1206 pipe_name(pipe));
ea0760cf
JB		 1207}
1208
b840d907
JB		 1209void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
b24e7179
JB		 1211{
1212 int reg;
1213 u32 val;
63d7bbe9 1214 bool cur_state;
b24e7179 1215
8e636784
DV		 1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
b24e7179
JB		 1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
63d7bbe9
JB		 1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1225 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1226}
1227
931872fc
CW		 1228static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
b24e7179
JB		 1230{
1231 int reg;
1232 u32 val;
931872fc 1233 bool cur_state;
b24e7179
JB		 1234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
931872fc
CW		 1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1241}
1242
931872fc
CW		 1243#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
b24e7179
JB		 1246static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248{
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
19ec1358 1253 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
19ec1358 1260 return;
28c05794 1261 }
19ec1358 1262
b24e7179
JB		 1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1272 }
1273}
1274
92f2584a
JB		 1275static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276{
1277 u32 val;
1278 bool enabled;
1279
9d82aa17
ED		 1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
92f2584a
JB		 1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289}
1290
1291static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
92f2584a
JB		 1304}
1305
4e634389
KP		 1306static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1308{
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322}
1323
1519b995
KP		 1324static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326{
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338}
1339
1340static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369}
1370
291906f1 1371static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1372 enum pipe pipe, int reg, u32 port_sel)
291906f1 1373{
47a05eca 1374 u32 val = I915_READ(reg);
4e634389 1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1377 reg, pipe_name(pipe));
de9a35ab
DV		 1378
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1381}
1382
1383static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384 enum pipe pipe, int reg)
1385{
47a05eca 1386 u32 val = I915_READ(reg);
e9a851ed 1387 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1389 reg, pipe_name(pipe));
de9a35ab
DV		 1390
1391 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1393}
1394
1395static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397{
1398 int reg;
1399 u32 val;
291906f1 1400
f0575e92
KP		 1401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1404
1405 reg = PCH_ADPA;
1406 val = I915_READ(reg);
e9a851ed 1407 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1408 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1409 pipe_name(pipe));
291906f1
JB		 1410
1411 reg = PCH_LVDS;
1412 val = I915_READ(reg);
e9a851ed 1413 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1414 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 pipe_name(pipe));
291906f1
JB		 1416
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420}
1421
63d7bbe9
JB		 1422/**
1423 * intel_enable_pll - enable a PLL
1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1426 *
1427 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1428 * make sure the PLL reg is writable first though, since the panel write
1429 * protect mechanism may be enabled.
1430 *
1431 * Note! This is for pre-ILK only.
7434a255
TR		 1432 *
1433 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1434 */
a37b9b34 1435static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1436{
1437 int reg;
1438 u32 val;
1439
1440 /* No really, not for ILK+ */
a0c4da24 1441 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1442
1443 /* PLL is protected by panel, make sure we can write it */
1444 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445 assert_panel_unlocked(dev_priv, pipe);
1446
1447 reg = DPLL(pipe);
1448 val = I915_READ(reg);
1449 val |= DPLL_VCO_ENABLE;
1450
1451 /* We do this three times for luck */
1452 I915_WRITE(reg, val);
1453 POSTING_READ(reg);
1454 udelay(150); /* wait for warmup */
1455 I915_WRITE(reg, val);
1456 POSTING_READ(reg);
1457 udelay(150); /* wait for warmup */
1458 I915_WRITE(reg, val);
1459 POSTING_READ(reg);
1460 udelay(150); /* wait for warmup */
1461}
1462
1463/**
1464 * intel_disable_pll - disable a PLL
1465 * @dev_priv: i915 private structure
1466 * @pipe: pipe PLL to disable
1467 *
1468 * Disable the PLL for @pipe, making sure the pipe is off first.
1469 *
1470 * Note! This is for pre-ILK only.
1471 */
1472static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473{
1474 int reg;
1475 u32 val;
1476
1477 /* Don't disable pipe A or pipe A PLLs if needed */
1478 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1479 return;
1480
1481 /* Make sure the pipe isn't still relying on us */
1482 assert_pipe_disabled(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val &= ~DPLL_VCO_ENABLE;
1487 I915_WRITE(reg, val);
1488 POSTING_READ(reg);
1489}
1490
a416edef
ED		 1491/* SBI access */
1492static void
1493intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1494{
1495 unsigned long flags;
1496
1497 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1498 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1499 100)) {
1500 DRM_ERROR("timeout waiting for SBI to become ready\n");
1501 goto out_unlock;
1502 }
1503
1504 I915_WRITE(SBI_ADDR,
1505 (reg << 16));
1506 I915_WRITE(SBI_DATA,
1507 value);
1508 I915_WRITE(SBI_CTL_STAT,
1509 SBI_BUSY |
1510 SBI_CTL_OP_CRWR);
1511
39fb50f6 1512 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1513 100)) {
1514 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1515 goto out_unlock;
1516 }
1517
1518out_unlock:
1519 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1520}
1521
1522static u32
1523intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1524{
1525 unsigned long flags;
39fb50f6 1526 u32 value = 0;
a416edef
ED		 1527
1528 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1529 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1530 100)) {
1531 DRM_ERROR("timeout waiting for SBI to become ready\n");
1532 goto out_unlock;
1533 }
1534
1535 I915_WRITE(SBI_ADDR,
1536 (reg << 16));
1537 I915_WRITE(SBI_CTL_STAT,
1538 SBI_BUSY |
1539 SBI_CTL_OP_CRRD);
1540
39fb50f6 1541 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1542 100)) {
1543 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1544 goto out_unlock;
1545 }
1546
1547 value = I915_READ(SBI_DATA);
1548
1549out_unlock:
1550 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1551 return value;
1552}
1553
92f2584a
JB		 1554/**
1555 * intel_enable_pch_pll - enable PCH PLL
1556 * @dev_priv: i915 private structure
1557 * @pipe: pipe PLL to enable
1558 *
1559 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560 * drives the transcoder clock.
1561 */
ee7b9f93 1562static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1563{
ee7b9f93 1564 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1565 struct intel_pch_pll *pll;
92f2584a
JB		 1566 int reg;
1567 u32 val;
1568
48da64a8 1569 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1570 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1571 pll = intel_crtc->pch_pll;
1572 if (pll == NULL)
1573 return;
1574
1575 if (WARN_ON(pll->refcount == 0))
1576 return;
ee7b9f93
JB		 1577
1578 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579 pll->pll_reg, pll->active, pll->on,
1580 intel_crtc->base.base.id);
92f2584a
JB		 1581
1582 /* PCH refclock must be enabled first */
1583 assert_pch_refclk_enabled(dev_priv);
1584
ee7b9f93 1585 if (pll->active++ && pll->on) {
92b27b08 1586 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1587 return;
1588 }
1589
1590 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1591
1592 reg = pll->pll_reg;
92f2584a
JB		 1593 val = I915_READ(reg);
1594 val |= DPLL_VCO_ENABLE;
1595 I915_WRITE(reg, val);
1596 POSTING_READ(reg);
1597 udelay(200);
ee7b9f93
JB		 1598
1599 pll->on = true;
92f2584a
JB		 1600}
1601
ee7b9f93 1602static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1603{
ee7b9f93
JB		 1604 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1606 int reg;
ee7b9f93 1607 u32 val;
4c609cb8 1608
92f2584a
JB		 1609 /* PCH only available on ILK+ */
1610 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1611 if (pll == NULL)
1612 return;
92f2584a 1613
48da64a8
CW		 1614 if (WARN_ON(pll->refcount == 0))
1615 return;
7a419866 1616
ee7b9f93
JB		 1617 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618 pll->pll_reg, pll->active, pll->on,
1619 intel_crtc->base.base.id);
7a419866 1620
48da64a8 1621 if (WARN_ON(pll->active == 0)) {
92b27b08 1622 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1623 return;
1624 }
1625
ee7b9f93 1626 if (--pll->active) {
92b27b08 1627 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1628 return;
ee7b9f93
JB		 1629 }
1630
1631 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1632
1633 /* Make sure transcoder isn't still depending on us */
1634 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1635
ee7b9f93 1636 reg = pll->pll_reg;
92f2584a
JB		 1637 val = I915_READ(reg);
1638 val &= ~DPLL_VCO_ENABLE;
1639 I915_WRITE(reg, val);
1640 POSTING_READ(reg);
1641 udelay(200);
ee7b9f93
JB		 1642
1643 pll->on = false;
92f2584a
JB		 1644}
1645
040484af
JB		 1646static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1647 enum pipe pipe)
1648{
1649 int reg;
5f7f726d 1650 u32 val, pipeconf_val;
7c26e5c6 1651 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1652
1653 /* PCH only available on ILK+ */
1654 BUG_ON(dev_priv->info->gen < 5);
1655
1656 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1657 assert_pch_pll_enabled(dev_priv,
1658 to_intel_crtc(crtc)->pch_pll,
1659 to_intel_crtc(crtc));
040484af
JB		 1660
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1664
59c859d6
ED		 1665 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1667 return;
1668 }
040484af
JB		 1669 reg = TRANSCONF(pipe);
1670 val = I915_READ(reg);
5f7f726d 1671 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1672
1673 if (HAS_PCH_IBX(dev_priv->dev)) {
1674 /*
1675 * make the BPC in transcoder be consistent with
1676 * that in pipeconf reg.
1677 */
1678 val &= ~PIPE_BPC_MASK;
5f7f726d 1679 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1680 }
5f7f726d
PZ		 1681
1682 val &= ~TRANS_INTERLACE_MASK;
1683 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1684 if (HAS_PCH_IBX(dev_priv->dev) &&
1685 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686 val |= TRANS_LEGACY_INTERLACED_ILK;
1687 else
1688 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1689 else
1690 val |= TRANS_PROGRESSIVE;
1691
040484af
JB		 1692 I915_WRITE(reg, val | TRANS_ENABLE);
1693 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1695}
1696
1697static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1698 enum pipe pipe)
1699{
1700 int reg;
1701 u32 val;
1702
1703 /* FDI relies on the transcoder */
1704 assert_fdi_tx_disabled(dev_priv, pipe);
1705 assert_fdi_rx_disabled(dev_priv, pipe);
1706
291906f1
JB		 1707 /* Ports must be off as well */
1708 assert_pch_ports_disabled(dev_priv, pipe);
1709
040484af
JB		 1710 reg = TRANSCONF(pipe);
1711 val = I915_READ(reg);
1712 val &= ~TRANS_ENABLE;
1713 I915_WRITE(reg, val);
1714 /* wait for PCH transcoder off, transcoder state */
1715 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1716 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1717}
1718
b24e7179 1719/**
309cfea8 1720 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1721 * @dev_priv: i915 private structure
1722 * @pipe: pipe to enable
040484af 1723 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1724 *
1725 * Enable @pipe, making sure that various hardware specific requirements
1726 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1727 *
1728 * @pipe should be %PIPE_A or %PIPE_B.
1729 *
1730 * Will wait until the pipe is actually running (i.e. first vblank) before
1731 * returning.
1732 */
040484af
JB		 1733static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1734 bool pch_port)
b24e7179
JB		 1735{
1736 int reg;
1737 u32 val;
1738
1739 /*
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1742 * need the check.
1743 */
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1746 else {
1747 if (pch_port) {
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1751 }
1752 /* FIXME: assert CPU port conditions for SNB+ */
1753 }
b24e7179
JB		 1754
1755 reg = PIPECONF(pipe);
1756 val = I915_READ(reg);
00d70b15
CW		 1757 if (val & PIPECONF_ENABLE)
1758 return;
1759
1760 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1761 intel_wait_for_vblank(dev_priv->dev, pipe);
1762}
1763
1764/**
309cfea8 1765 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe to disable
1768 *
1769 * Disable @pipe, making sure that various hardware specific requirements
1770 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1771 *
1772 * @pipe should be %PIPE_A or %PIPE_B.
1773 *
1774 * Will wait until the pipe has shut down before returning.
1775 */
1776static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1777 enum pipe pipe)
1778{
1779 int reg;
1780 u32 val;
1781
1782 /*
1783 * Make sure planes won't keep trying to pump pixels to us,
1784 * or we might hang the display.
1785 */
1786 assert_planes_disabled(dev_priv, pipe);
1787
1788 /* Don't disable pipe A or pipe A PLLs if needed */
1789 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1790 return;
1791
1792 reg = PIPECONF(pipe);
1793 val = I915_READ(reg);
00d70b15
CW		 1794 if ((val & PIPECONF_ENABLE) == 0)
1795 return;
1796
1797 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1798 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1799}
1800
d74362c9
KP		 1801/*
1802 * Plane regs are double buffered, going from enabled->disabled needs a
1803 * trigger in order to latch. The display address reg provides this.
1804 */
6f1d69b0 1805void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1806 enum plane plane)
1807{
1808 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1810}
1811
b24e7179
JB		 1812/**
1813 * intel_enable_plane - enable a display plane on a given pipe
1814 * @dev_priv: i915 private structure
1815 * @plane: plane to enable
1816 * @pipe: pipe being fed
1817 *
1818 * Enable @plane on @pipe, making sure that @pipe is running first.
1819 */
1820static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane, enum pipe pipe)
1822{
1823 int reg;
1824 u32 val;
1825
1826 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827 assert_pipe_enabled(dev_priv, pipe);
1828
1829 reg = DSPCNTR(plane);
1830 val = I915_READ(reg);
00d70b15
CW		 1831 if (val & DISPLAY_PLANE_ENABLE)
1832 return;
1833
1834 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1835 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1836 intel_wait_for_vblank(dev_priv->dev, pipe);
1837}
1838
b24e7179
JB		 1839/**
1840 * intel_disable_plane - disable a display plane
1841 * @dev_priv: i915 private structure
1842 * @plane: plane to disable
1843 * @pipe: pipe consuming the data
1844 *
1845 * Disable @plane; should be an independent operation.
1846 */
1847static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848 enum plane plane, enum pipe pipe)
1849{
1850 int reg;
1851 u32 val;
1852
1853 reg = DSPCNTR(plane);
1854 val = I915_READ(reg);
00d70b15
CW		 1855 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1856 return;
1857
1858 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1859 intel_flush_display_plane(dev_priv, plane);
1860 intel_wait_for_vblank(dev_priv->dev, pipe);
1861}
1862
47a05eca 1863static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1864 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1865{
1866 u32 val = I915_READ(reg);
4e634389 1867 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1868 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1869 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1870 }
47a05eca
JB		 1871}
1872
1873static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1874 enum pipe pipe, int reg)
1875{
1876 u32 val = I915_READ(reg);
e9a851ed 1877 if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
f0575e92
KP		 1878 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1879 reg, pipe);
47a05eca 1880 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1881 }
47a05eca
JB		 1882}
1883
1884/* Disable any ports connected to this transcoder */
1885static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1886 enum pipe pipe)
1887{
1888 u32 reg, val;
1889
1890 val = I915_READ(PCH_PP_CONTROL);
1891 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1892
f0575e92
KP		 1893 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1894 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1895 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1896
1897 reg = PCH_ADPA;
1898 val = I915_READ(reg);
e9a851ed 1899 if (adpa_pipe_enabled(dev_priv, pipe, val))
47a05eca
JB		 1900 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1901
1902 reg = PCH_LVDS;
1903 val = I915_READ(reg);
e9a851ed 1904 if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1519b995 1905 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1906 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1907 POSTING_READ(reg);
1908 udelay(100);
1909 }
1910
1911 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1912 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1913 disable_pch_hdmi(dev_priv, pipe, HDMID);
1914}
1915
127bd2ac 1916int
48b956c5 1917intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1918 struct drm_i915_gem_object *obj,
919926ae 1919 struct intel_ring_buffer *pipelined)
6b95a207 1920{
ce453d81 1921 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1922 u32 alignment;
1923 int ret;
1924
05394f39 1925 switch (obj->tiling_mode) {
6b95a207 1926 case I915_TILING_NONE:
534843da
CW		 1927 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1928 alignment = 128 * 1024;
a6c45cf0 1929 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1930 alignment = 4 * 1024;
1931 else
1932 alignment = 64 * 1024;
6b95a207
KH		 1933 break;
1934 case I915_TILING_X:
1935 /* pin() will align the object as required by fence */
1936 alignment = 0;
1937 break;
1938 case I915_TILING_Y:
1939 /* FIXME: Is this true? */
1940 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1941 return -EINVAL;
1942 default:
1943 BUG();
1944 }
1945
ce453d81 1946 dev_priv->mm.interruptible = false;
2da3b9b9 1947 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1948 if (ret)
ce453d81 1949 goto err_interruptible;
6b95a207
KH		 1950
1951 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952 * fence, whereas 965+ only requires a fence if using
1953 * framebuffer compression. For simplicity, we always install
1954 * a fence as the cost is not that onerous.
1955 */
06d98131 1956 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1957 if (ret)
1958 goto err_unpin;
1690e1eb 1959
9a5a53b3 1960 i915_gem_object_pin_fence(obj);
6b95a207 1961
ce453d81 1962 dev_priv->mm.interruptible = true;
6b95a207 1963 return 0;
48b956c5
CW		 1964
1965err_unpin:
1966 i915_gem_object_unpin(obj);
ce453d81
CW		 1967err_interruptible:
1968 dev_priv->mm.interruptible = true;
48b956c5 1969 return ret;
6b95a207
KH		 1970}
1971
1690e1eb
CW		 1972void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1973{
1974 i915_gem_object_unpin_fence(obj);
1975 i915_gem_object_unpin(obj);
1976}
1977
c2c75131
DV		 1978/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979 * is assumed to be a power-of-two. */
1980static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1981 unsigned int bpp,
1982 unsigned int pitch)
1983{
1984 int tile_rows, tiles;
1985
1986 tile_rows = *y / 8;
1987 *y %= 8;
1988 tiles = *x / (512/bpp);
1989 *x %= 512/bpp;
1990
1991 return tile_rows * pitch * 8 + tiles * 4096;
1992}
1993
17638cd6
JB		 1994static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1995 int x, int y)
81255565
JB		 1996{
1997 struct drm_device *dev = crtc->dev;
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000 struct intel_framebuffer *intel_fb;
05394f39 2001 struct drm_i915_gem_object *obj;
81255565 2002 int plane = intel_crtc->plane;
e506a0c6 2003 unsigned long linear_offset;
81255565 2004 u32 dspcntr;
5eddb70b 2005 u32 reg;
81255565
JB		 2006
2007 switch (plane) {
2008 case 0:
2009 case 1:
2010 break;
2011 default:
2012 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2013 return -EINVAL;
2014 }
2015
2016 intel_fb = to_intel_framebuffer(fb);
2017 obj = intel_fb->obj;
81255565 2018
5eddb70b
CW		 2019 reg = DSPCNTR(plane);
2020 dspcntr = I915_READ(reg);
81255565
JB		 2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023 switch (fb->bits_per_pixel) {
2024 case 8:
2025 dspcntr |= DISPPLANE_8BPP;
2026 break;
2027 case 16:
2028 if (fb->depth == 15)
2029 dspcntr |= DISPPLANE_15_16BPP;
2030 else
2031 dspcntr |= DISPPLANE_16BPP;
2032 break;
2033 case 24:
2034 case 32:
2035 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2036 break;
2037 default:
17638cd6 2038 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2039 return -EINVAL;
2040 }
a6c45cf0 2041 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2042 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2043 dspcntr |= DISPPLANE_TILED;
2044 else
2045 dspcntr &= ~DISPPLANE_TILED;
2046 }
2047
5eddb70b 2048 I915_WRITE(reg, dspcntr);
81255565 2049
e506a0c6 2050 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2051
c2c75131
DV		 2052 if (INTEL_INFO(dev)->gen >= 4) {
2053 intel_crtc->dspaddr_offset =
2054 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2055 fb->bits_per_pixel / 8,
2056 fb->pitches[0]);
2057 linear_offset -= intel_crtc->dspaddr_offset;
2058 } else {
e506a0c6 2059 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2060 }
e506a0c6
DV		 2061
2062 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2063 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2064 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2065 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2066 I915_MODIFY_DISPBASE(DSPSURF(plane),
2067 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2068 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2069 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2070 } else
e506a0c6 2071 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2072 POSTING_READ(reg);
81255565 2073
17638cd6
JB		 2074 return 0;
2075}
2076
2077static int ironlake_update_plane(struct drm_crtc *crtc,
2078 struct drm_framebuffer *fb, int x, int y)
2079{
2080 struct drm_device *dev = crtc->dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083 struct intel_framebuffer *intel_fb;
2084 struct drm_i915_gem_object *obj;
2085 int plane = intel_crtc->plane;
e506a0c6 2086 unsigned long linear_offset;
17638cd6
JB		 2087 u32 dspcntr;
2088 u32 reg;
2089
2090 switch (plane) {
2091 case 0:
2092 case 1:
27f8227b 2093 case 2:
17638cd6
JB		 2094 break;
2095 default:
2096 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2097 return -EINVAL;
2098 }
2099
2100 intel_fb = to_intel_framebuffer(fb);
2101 obj = intel_fb->obj;
2102
2103 reg = DSPCNTR(plane);
2104 dspcntr = I915_READ(reg);
2105 /* Mask out pixel format bits in case we change it */
2106 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2107 switch (fb->bits_per_pixel) {
2108 case 8:
2109 dspcntr |= DISPPLANE_8BPP;
2110 break;
2111 case 16:
2112 if (fb->depth != 16)
2113 return -EINVAL;
2114
2115 dspcntr |= DISPPLANE_16BPP;
2116 break;
2117 case 24:
2118 case 32:
2119 if (fb->depth == 24)
2120 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121 else if (fb->depth == 30)
2122 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2123 else
2124 return -EINVAL;
2125 break;
2126 default:
2127 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2128 return -EINVAL;
2129 }
2130
2131 if (obj->tiling_mode != I915_TILING_NONE)
2132 dspcntr |= DISPPLANE_TILED;
2133 else
2134 dspcntr &= ~DISPPLANE_TILED;
2135
2136 /* must disable */
2137 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2138
2139 I915_WRITE(reg, dspcntr);
2140
e506a0c6 2141 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131
DV		 2142 intel_crtc->dspaddr_offset =
2143 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2144 fb->bits_per_pixel / 8,
2145 fb->pitches[0]);
2146 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2147
e506a0c6
DV		 2148 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2149 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2150 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2151 I915_MODIFY_DISPBASE(DSPSURF(plane),
2152 obj->gtt_offset + intel_crtc->dspaddr_offset);
17638cd6 2153 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2154 I915_WRITE(DSPLINOFF(plane), linear_offset);
17638cd6
JB		 2155 POSTING_READ(reg);
2156
2157 return 0;
2158}
2159
2160/* Assume fb object is pinned & idle & fenced and just update base pointers */
2161static int
2162intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2163 int x, int y, enum mode_set_atomic state)
2164{
2165 struct drm_device *dev = crtc->dev;
2166 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2167
6b8e6ed0
CW		 2168 if (dev_priv->display.disable_fbc)
2169 dev_priv->display.disable_fbc(dev);
3dec0095 2170 intel_increase_pllclock(crtc);
81255565 2171
6b8e6ed0 2172 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2173}
2174
14667a4b
CW		 2175static int
2176intel_finish_fb(struct drm_framebuffer *old_fb)
2177{
2178 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2179 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2180 bool was_interruptible = dev_priv->mm.interruptible;
2181 int ret;
2182
2183 wait_event(dev_priv->pending_flip_queue,
2184 atomic_read(&dev_priv->mm.wedged) ||
2185 atomic_read(&obj->pending_flip) == 0);
2186
2187 /* Big Hammer, we also need to ensure that any pending
2188 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2189 * current scanout is retired before unpinning the old
2190 * framebuffer.
2191 *
2192 * This should only fail upon a hung GPU, in which case we
2193 * can safely continue.
2194 */
2195 dev_priv->mm.interruptible = false;
2196 ret = i915_gem_object_finish_gpu(obj);
2197 dev_priv->mm.interruptible = was_interruptible;
2198
2199 return ret;
2200}
2201
5c3b82e2 2202static int
3c4fdcfb
KH		 2203intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2204 struct drm_framebuffer *old_fb)
79e53945
JB		 2205{
2206 struct drm_device *dev = crtc->dev;
6b8e6ed0 2207 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2208 struct drm_i915_master_private *master_priv;
2209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2210 int ret;
79e53945
JB		 2211
2212 /* no fb bound */
2213 if (!crtc->fb) {
a5071c2f 2214 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2215 return 0;
2216 }
2217
5826eca5
ED		 2218 if(intel_crtc->plane > dev_priv->num_pipe) {
2219 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2220 intel_crtc->plane,
2221 dev_priv->num_pipe);
5c3b82e2 2222 return -EINVAL;
79e53945
JB		 2223 }
2224
5c3b82e2 2225 mutex_lock(&dev->struct_mutex);
265db958
CW		 2226 ret = intel_pin_and_fence_fb_obj(dev,
2227 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2228 NULL);
5c3b82e2
CW		 2229 if (ret != 0) {
2230 mutex_unlock(&dev->struct_mutex);
a5071c2f 2231 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2232 return ret;
2233 }
79e53945 2234
14667a4b
CW		 2235 if (old_fb)
2236 intel_finish_fb(old_fb);
265db958 2237
6b8e6ed0 2238 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
4e6cfefc 2239 if (ret) {
1690e1eb 2240 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2241 mutex_unlock(&dev->struct_mutex);
a5071c2f 2242 DRM_ERROR("failed to update base address\n");
4e6cfefc 2243 return ret;
79e53945 2244 }
3c4fdcfb 2245
b7f1de28
CW		 2246 if (old_fb) {
2247 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2248 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2249 }
652c393a 2250
6b8e6ed0 2251 intel_update_fbc(dev);
5c3b82e2 2252 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2253
2254 if (!dev->primary->master)
5c3b82e2 2255 return 0;
79e53945
JB		 2256
2257 master_priv = dev->primary->master->driver_priv;
2258 if (!master_priv->sarea_priv)
5c3b82e2 2259 return 0;
79e53945 2260
265db958 2261 if (intel_crtc->pipe) {
79e53945
JB		 2262 master_priv->sarea_priv->pipeB_x = x;
2263 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2264 } else {
2265 master_priv->sarea_priv->pipeA_x = x;
2266 master_priv->sarea_priv->pipeA_y = y;
79e53945 2267 }
5c3b82e2
CW		 2268
2269 return 0;
79e53945
JB		 2270}
2271
5eddb70b 2272static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2273{
2274 struct drm_device *dev = crtc->dev;
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276 u32 dpa_ctl;
2277
28c97730 2278 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2279 dpa_ctl = I915_READ(DP_A);
2280 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2281
2282 if (clock < 200000) {
2283 u32 temp;
2284 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2285 /* workaround for 160Mhz:
2286 1) program 0x4600c bits 15:0 = 0x8124
2287 2) program 0x46010 bit 0 = 1
2288 3) program 0x46034 bit 24 = 1
2289 4) program 0x64000 bit 14 = 1
2290 */
2291 temp = I915_READ(0x4600c);
2292 temp &= 0xffff0000;
2293 I915_WRITE(0x4600c, temp | 0x8124);
2294
2295 temp = I915_READ(0x46010);
2296 I915_WRITE(0x46010, temp | 1);
2297
2298 temp = I915_READ(0x46034);
2299 I915_WRITE(0x46034, temp | (1 << 24));
2300 } else {
2301 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2302 }
2303 I915_WRITE(DP_A, dpa_ctl);
2304
5eddb70b 2305 POSTING_READ(DP_A);
32f9d658
ZW		 2306 udelay(500);
2307}
2308
5e84e1a4
ZW		 2309static void intel_fdi_normal_train(struct drm_crtc *crtc)
2310{
2311 struct drm_device *dev = crtc->dev;
2312 struct drm_i915_private *dev_priv = dev->dev_private;
2313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2314 int pipe = intel_crtc->pipe;
2315 u32 reg, temp;
2316
2317 /* enable normal train */
2318 reg = FDI_TX_CTL(pipe);
2319 temp = I915_READ(reg);
61e499bf 2320 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2321 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2322 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2323 } else {
2324 temp &= ~FDI_LINK_TRAIN_NONE;
2325 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2326 }
5e84e1a4
ZW		 2327 I915_WRITE(reg, temp);
2328
2329 reg = FDI_RX_CTL(pipe);
2330 temp = I915_READ(reg);
2331 if (HAS_PCH_CPT(dev)) {
2332 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2333 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2334 } else {
2335 temp &= ~FDI_LINK_TRAIN_NONE;
2336 temp |= FDI_LINK_TRAIN_NONE;
2337 }
2338 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2339
2340 /* wait one idle pattern time */
2341 POSTING_READ(reg);
2342 udelay(1000);
357555c0
JB		 2343
2344 /* IVB wants error correction enabled */
2345 if (IS_IVYBRIDGE(dev))
2346 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2347 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2348}
2349
291427f5
JB		 2350static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2351{
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 u32 flags = I915_READ(SOUTH_CHICKEN1);
2354
2355 flags |= FDI_PHASE_SYNC_OVR(pipe);
2356 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2357 flags |= FDI_PHASE_SYNC_EN(pipe);
2358 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2359 POSTING_READ(SOUTH_CHICKEN1);
2360}
2361
8db9d77b
ZW		 2362/* The FDI link training functions for ILK/Ibexpeak. */
2363static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2364{
2365 struct drm_device *dev = crtc->dev;
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368 int pipe = intel_crtc->pipe;
0fc932b8 2369 int plane = intel_crtc->plane;
5eddb70b 2370 u32 reg, temp, tries;
8db9d77b 2371
0fc932b8
JB		 2372 /* FDI needs bits from pipe & plane first */
2373 assert_pipe_enabled(dev_priv, pipe);
2374 assert_plane_enabled(dev_priv, plane);
2375
e1a44743
AJ		 2376 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2377 for train result */
5eddb70b
CW		 2378 reg = FDI_RX_IMR(pipe);
2379 temp = I915_READ(reg);
e1a44743
AJ		 2380 temp &= ~FDI_RX_SYMBOL_LOCK;
2381 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2382 I915_WRITE(reg, temp);
2383 I915_READ(reg);
e1a44743
AJ		 2384 udelay(150);
2385
8db9d77b 2386 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2387 reg = FDI_TX_CTL(pipe);
2388 temp = I915_READ(reg);
77ffb597
AJ		 2389 temp &= ~(7 << 19);
2390 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2391 temp &= ~FDI_LINK_TRAIN_NONE;
2392 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2393 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2394
5eddb70b
CW		 2395 reg = FDI_RX_CTL(pipe);
2396 temp = I915_READ(reg);
8db9d77b
ZW		 2397 temp &= ~FDI_LINK_TRAIN_NONE;
2398 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2399 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2400
2401 POSTING_READ(reg);
8db9d77b
ZW		 2402 udelay(150);
2403
5b2adf89 2404 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2405 if (HAS_PCH_IBX(dev)) {
2406 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2407 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2408 FDI_RX_PHASE_SYNC_POINTER_EN);
2409 }
5b2adf89 2410
5eddb70b 2411 reg = FDI_RX_IIR(pipe);
e1a44743 2412 for (tries = 0; tries < 5; tries++) {
5eddb70b 2413 temp = I915_READ(reg);
8db9d77b
ZW		 2414 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2415
2416 if ((temp & FDI_RX_BIT_LOCK)) {
2417 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2418 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2419 break;
2420 }
8db9d77b 2421 }
e1a44743 2422 if (tries == 5)
5eddb70b 2423 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2424
2425 /* Train 2 */
5eddb70b
CW		 2426 reg = FDI_TX_CTL(pipe);
2427 temp = I915_READ(reg);
8db9d77b
ZW		 2428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2430 I915_WRITE(reg, temp);
8db9d77b 2431
5eddb70b
CW		 2432 reg = FDI_RX_CTL(pipe);
2433 temp = I915_READ(reg);
8db9d77b
ZW		 2434 temp &= ~FDI_LINK_TRAIN_NONE;
2435 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2436 I915_WRITE(reg, temp);
8db9d77b 2437
5eddb70b
CW		 2438 POSTING_READ(reg);
2439 udelay(150);
8db9d77b 2440
5eddb70b 2441 reg = FDI_RX_IIR(pipe);
e1a44743 2442 for (tries = 0; tries < 5; tries++) {
5eddb70b 2443 temp = I915_READ(reg);
8db9d77b
ZW		 2444 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2445
2446 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2447 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2448 DRM_DEBUG_KMS("FDI train 2 done.\n");
2449 break;
2450 }
8db9d77b 2451 }
e1a44743 2452 if (tries == 5)
5eddb70b 2453 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2454
2455 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2456
8db9d77b
ZW		 2457}
2458
0206e353 2459static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2460 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2461 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2462 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2463 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2464};
2465
2466/* The FDI link training functions for SNB/Cougarpoint. */
2467static void gen6_fdi_link_train(struct drm_crtc *crtc)
2468{
2469 struct drm_device *dev = crtc->dev;
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2472 int pipe = intel_crtc->pipe;
fa37d39e 2473 u32 reg, temp, i, retry;
8db9d77b 2474
e1a44743
AJ		 2475 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2476 for train result */
5eddb70b
CW		 2477 reg = FDI_RX_IMR(pipe);
2478 temp = I915_READ(reg);
e1a44743
AJ		 2479 temp &= ~FDI_RX_SYMBOL_LOCK;
2480 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2481 I915_WRITE(reg, temp);
2482
2483 POSTING_READ(reg);
e1a44743
AJ		 2484 udelay(150);
2485
8db9d77b 2486 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2487 reg = FDI_TX_CTL(pipe);
2488 temp = I915_READ(reg);
77ffb597
AJ		 2489 temp &= ~(7 << 19);
2490 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
2493 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2494 /* SNB-B */
2495 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2496 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2497
5eddb70b
CW		 2498 reg = FDI_RX_CTL(pipe);
2499 temp = I915_READ(reg);
8db9d77b
ZW		 2500 if (HAS_PCH_CPT(dev)) {
2501 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2502 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2503 } else {
2504 temp &= ~FDI_LINK_TRAIN_NONE;
2505 temp |= FDI_LINK_TRAIN_PATTERN_1;
2506 }
5eddb70b
CW		 2507 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2508
2509 POSTING_READ(reg);
8db9d77b
ZW		 2510 udelay(150);
2511
291427f5
JB		 2512 if (HAS_PCH_CPT(dev))
2513 cpt_phase_pointer_enable(dev, pipe);
2514
0206e353 2515 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
8db9d77b
ZW		 2518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2519 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
8db9d77b
ZW		 2523 udelay(500);
2524
fa37d39e
SP		 2525 for (retry = 0; retry < 5; retry++) {
2526 reg = FDI_RX_IIR(pipe);
2527 temp = I915_READ(reg);
2528 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2529 if (temp & FDI_RX_BIT_LOCK) {
2530 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2531 DRM_DEBUG_KMS("FDI train 1 done.\n");
2532 break;
2533 }
2534 udelay(50);
8db9d77b 2535 }
fa37d39e
SP		 2536 if (retry < 5)
2537 break;
8db9d77b
ZW		 2538 }
2539 if (i == 4)
5eddb70b 2540 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2541
2542 /* Train 2 */
5eddb70b
CW		 2543 reg = FDI_TX_CTL(pipe);
2544 temp = I915_READ(reg);
8db9d77b
ZW		 2545 temp &= ~FDI_LINK_TRAIN_NONE;
2546 temp |= FDI_LINK_TRAIN_PATTERN_2;
2547 if (IS_GEN6(dev)) {
2548 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2549 /* SNB-B */
2550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2551 }
5eddb70b 2552 I915_WRITE(reg, temp);
8db9d77b 2553
5eddb70b
CW		 2554 reg = FDI_RX_CTL(pipe);
2555 temp = I915_READ(reg);
8db9d77b
ZW		 2556 if (HAS_PCH_CPT(dev)) {
2557 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2558 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2559 } else {
2560 temp &= ~FDI_LINK_TRAIN_NONE;
2561 temp |= FDI_LINK_TRAIN_PATTERN_2;
2562 }
5eddb70b
CW		 2563 I915_WRITE(reg, temp);
2564
2565 POSTING_READ(reg);
8db9d77b
ZW		 2566 udelay(150);
2567
0206e353 2568 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
8db9d77b
ZW		 2571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
8db9d77b
ZW		 2576 udelay(500);
2577
fa37d39e
SP		 2578 for (retry = 0; retry < 5; retry++) {
2579 reg = FDI_RX_IIR(pipe);
2580 temp = I915_READ(reg);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582 if (temp & FDI_RX_SYMBOL_LOCK) {
2583 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2584 DRM_DEBUG_KMS("FDI train 2 done.\n");
2585 break;
2586 }
2587 udelay(50);
8db9d77b 2588 }
fa37d39e
SP		 2589 if (retry < 5)
2590 break;
8db9d77b
ZW		 2591 }
2592 if (i == 4)
5eddb70b 2593 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2594
2595 DRM_DEBUG_KMS("FDI train done.\n");
2596}
2597
357555c0
JB		 2598/* Manual link training for Ivy Bridge A0 parts */
2599static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2600{
2601 struct drm_device *dev = crtc->dev;
2602 struct drm_i915_private *dev_priv = dev->dev_private;
2603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2604 int pipe = intel_crtc->pipe;
2605 u32 reg, temp, i;
2606
2607 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2608 for train result */
2609 reg = FDI_RX_IMR(pipe);
2610 temp = I915_READ(reg);
2611 temp &= ~FDI_RX_SYMBOL_LOCK;
2612 temp &= ~FDI_RX_BIT_LOCK;
2613 I915_WRITE(reg, temp);
2614
2615 POSTING_READ(reg);
2616 udelay(150);
2617
2618 /* enable CPU FDI TX and PCH FDI RX */
2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~(7 << 19);
2622 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2623 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2624 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2625 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2627 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2628 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2629
2630 reg = FDI_RX_CTL(pipe);
2631 temp = I915_READ(reg);
2632 temp &= ~FDI_LINK_TRAIN_AUTO;
2633 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2635 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2636 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2637
2638 POSTING_READ(reg);
2639 udelay(150);
2640
291427f5
JB		 2641 if (HAS_PCH_CPT(dev))
2642 cpt_phase_pointer_enable(dev, pipe);
2643
0206e353 2644 for (i = 0; i < 4; i++) {
357555c0
JB		 2645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648 temp |= snb_b_fdi_train_param[i];
2649 I915_WRITE(reg, temp);
2650
2651 POSTING_READ(reg);
2652 udelay(500);
2653
2654 reg = FDI_RX_IIR(pipe);
2655 temp = I915_READ(reg);
2656 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2657
2658 if (temp & FDI_RX_BIT_LOCK ||
2659 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2660 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2661 DRM_DEBUG_KMS("FDI train 1 done.\n");
2662 break;
2663 }
2664 }
2665 if (i == 4)
2666 DRM_ERROR("FDI train 1 fail!\n");
2667
2668 /* Train 2 */
2669 reg = FDI_TX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2672 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2673 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2674 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2675 I915_WRITE(reg, temp);
2676
2677 reg = FDI_RX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2680 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2681 I915_WRITE(reg, temp);
2682
2683 POSTING_READ(reg);
2684 udelay(150);
2685
0206e353 2686 for (i = 0; i < 4; i++) {
357555c0
JB		 2687 reg = FDI_TX_CTL(pipe);
2688 temp = I915_READ(reg);
2689 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690 temp |= snb_b_fdi_train_param[i];
2691 I915_WRITE(reg, temp);
2692
2693 POSTING_READ(reg);
2694 udelay(500);
2695
2696 reg = FDI_RX_IIR(pipe);
2697 temp = I915_READ(reg);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700 if (temp & FDI_RX_SYMBOL_LOCK) {
2701 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2702 DRM_DEBUG_KMS("FDI train 2 done.\n");
2703 break;
2704 }
2705 }
2706 if (i == 4)
2707 DRM_ERROR("FDI train 2 fail!\n");
2708
2709 DRM_DEBUG_KMS("FDI train done.\n");
2710}
2711
88cefb6c 2712static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2713{
88cefb6c 2714 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2715 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2716 int pipe = intel_crtc->pipe;
5eddb70b 2717 u32 reg, temp;
79e53945 2718
c64e311e 2719 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2720 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2721 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2722
c98e9dcf 2723 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2724 reg = FDI_RX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2727 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2728 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2729 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2730
2731 POSTING_READ(reg);
c98e9dcf
JB		 2732 udelay(200);
2733
2734 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2735 temp = I915_READ(reg);
2736 I915_WRITE(reg, temp | FDI_PCDCLK);
2737
2738 POSTING_READ(reg);
c98e9dcf
JB		 2739 udelay(200);
2740
bf507ef7
ED		 2741 /* On Haswell, the PLL configuration for ports and pipes is handled
2742 * separately, as part of DDI setup */
2743 if (!IS_HASWELL(dev)) {
2744 /* Enable CPU FDI TX PLL, always on for Ironlake */
2745 reg = FDI_TX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2748 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2749
bf507ef7
ED		 2750 POSTING_READ(reg);
2751 udelay(100);
2752 }
6be4a607 2753 }
0e23b99d
JB		 2754}
2755
88cefb6c
DV		 2756static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2757{
2758 struct drm_device *dev = intel_crtc->base.dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 int pipe = intel_crtc->pipe;
2761 u32 reg, temp;
2762
2763 /* Switch from PCDclk to Rawclk */
2764 reg = FDI_RX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2767
2768 /* Disable CPU FDI TX PLL */
2769 reg = FDI_TX_CTL(pipe);
2770 temp = I915_READ(reg);
2771 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2772
2773 POSTING_READ(reg);
2774 udelay(100);
2775
2776 reg = FDI_RX_CTL(pipe);
2777 temp = I915_READ(reg);
2778 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2779
2780 /* Wait for the clocks to turn off. */
2781 POSTING_READ(reg);
2782 udelay(100);
2783}
2784
291427f5
JB		 2785static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2786{
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 u32 flags = I915_READ(SOUTH_CHICKEN1);
2789
2790 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2791 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2792 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2793 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2794 POSTING_READ(SOUTH_CHICKEN1);
2795}
0fc932b8
JB		 2796static void ironlake_fdi_disable(struct drm_crtc *crtc)
2797{
2798 struct drm_device *dev = crtc->dev;
2799 struct drm_i915_private *dev_priv = dev->dev_private;
2800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2801 int pipe = intel_crtc->pipe;
2802 u32 reg, temp;
2803
2804 /* disable CPU FDI tx and PCH FDI rx */
2805 reg = FDI_TX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2808 POSTING_READ(reg);
2809
2810 reg = FDI_RX_CTL(pipe);
2811 temp = I915_READ(reg);
2812 temp &= ~(0x7 << 16);
2813 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2814 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2815
2816 POSTING_READ(reg);
2817 udelay(100);
2818
2819 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2820 if (HAS_PCH_IBX(dev)) {
2821 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2822 I915_WRITE(FDI_RX_CHICKEN(pipe),
2823 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2824 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2825 } else if (HAS_PCH_CPT(dev)) {
2826 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2827 }
0fc932b8
JB		 2828
2829 /* still set train pattern 1 */
2830 reg = FDI_TX_CTL(pipe);
2831 temp = I915_READ(reg);
2832 temp &= ~FDI_LINK_TRAIN_NONE;
2833 temp |= FDI_LINK_TRAIN_PATTERN_1;
2834 I915_WRITE(reg, temp);
2835
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 if (HAS_PCH_CPT(dev)) {
2839 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2840 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2841 } else {
2842 temp &= ~FDI_LINK_TRAIN_NONE;
2843 temp |= FDI_LINK_TRAIN_PATTERN_1;
2844 }
2845 /* BPC in FDI rx is consistent with that in PIPECONF */
2846 temp &= ~(0x07 << 16);
2847 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2848 I915_WRITE(reg, temp);
2849
2850 POSTING_READ(reg);
2851 udelay(100);
2852}
2853
e6c3a2a6
CW		 2854static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2855{
0f91128d 2856 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2857
2858 if (crtc->fb == NULL)
2859 return;
2860
0f91128d
CW		 2861 mutex_lock(&dev->struct_mutex);
2862 intel_finish_fb(crtc->fb);
2863 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2864}
2865
040484af
JB		 2866static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2867{
2868 struct drm_device *dev = crtc->dev;
228d3e36 2869 struct intel_encoder *intel_encoder;
040484af
JB		 2870
2871 /*
2872 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2873 * must be driven by its own crtc; no sharing is possible.
2874 */
228d3e36 2875 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
040484af 2876
6ee8bab0
ED		 2877 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2878 * CPU handles all others */
2879 if (IS_HASWELL(dev)) {
2880 /* It is still unclear how this will work on PPT, so throw up a warning */
2881 WARN_ON(!HAS_PCH_LPT(dev));
2882
228d3e36 2883 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
6ee8bab0
ED		 2884 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2885 return true;
2886 } else {
2887 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
228d3e36 2888 intel_encoder->type);
6ee8bab0
ED		 2889 return false;
2890 }
2891 }
2892
228d3e36 2893 switch (intel_encoder->type) {
040484af 2894 case INTEL_OUTPUT_EDP:
228d3e36 2895 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2896 return false;
2897 continue;
2898 }
2899 }
2900
2901 return true;
2902}
2903
e615efe4
ED		 2904/* Program iCLKIP clock to the desired frequency */
2905static void lpt_program_iclkip(struct drm_crtc *crtc)
2906{
2907 struct drm_device *dev = crtc->dev;
2908 struct drm_i915_private *dev_priv = dev->dev_private;
2909 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2910 u32 temp;
2911
2912 /* It is necessary to ungate the pixclk gate prior to programming
2913 * the divisors, and gate it back when it is done.
2914 */
2915 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2916
2917 /* Disable SSCCTL */
2918 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2919 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2920 SBI_SSCCTL_DISABLE);
2921
2922 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2923 if (crtc->mode.clock == 20000) {
2924 auxdiv = 1;
2925 divsel = 0x41;
2926 phaseinc = 0x20;
2927 } else {
2928 /* The iCLK virtual clock root frequency is in MHz,
2929 * but the crtc->mode.clock in in KHz. To get the divisors,
2930 * it is necessary to divide one by another, so we
2931 * convert the virtual clock precision to KHz here for higher
2932 * precision.
2933 */
2934 u32 iclk_virtual_root_freq = 172800 * 1000;
2935 u32 iclk_pi_range = 64;
2936 u32 desired_divisor, msb_divisor_value, pi_value;
2937
2938 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2939 msb_divisor_value = desired_divisor / iclk_pi_range;
2940 pi_value = desired_divisor % iclk_pi_range;
2941
2942 auxdiv = 0;
2943 divsel = msb_divisor_value - 2;
2944 phaseinc = pi_value;
2945 }
2946
2947 /* This should not happen with any sane values */
2948 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2949 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2950 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2951 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2952
2953 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2954 crtc->mode.clock,
2955 auxdiv,
2956 divsel,
2957 phasedir,
2958 phaseinc);
2959
2960 /* Program SSCDIVINTPHASE6 */
2961 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2962 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2963 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2964 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2965 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2966 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2967 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2968
2969 intel_sbi_write(dev_priv,
2970 SBI_SSCDIVINTPHASE6,
2971 temp);
2972
2973 /* Program SSCAUXDIV */
2974 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2975 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2976 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2977 intel_sbi_write(dev_priv,
2978 SBI_SSCAUXDIV6,
2979 temp);
2980
2981
2982 /* Enable modulator and associated divider */
2983 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2984 temp &= ~SBI_SSCCTL_DISABLE;
2985 intel_sbi_write(dev_priv,
2986 SBI_SSCCTL6,
2987 temp);
2988
2989 /* Wait for initialization time */
2990 udelay(24);
2991
2992 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2993}
2994
f67a559d
JB		 2995/*
2996 * Enable PCH resources required for PCH ports:
2997 * - PCH PLLs
2998 * - FDI training & RX/TX
2999 * - update transcoder timings
3000 * - DP transcoding bits
3001 * - transcoder
3002 */
3003static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3004{
3005 struct drm_device *dev = crtc->dev;
3006 struct drm_i915_private *dev_priv = dev->dev_private;
3007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3008 int pipe = intel_crtc->pipe;
ee7b9f93 3009 u32 reg, temp;
2c07245f 3010
e7e164db
CW		 3011 assert_transcoder_disabled(dev_priv, pipe);
3012
c98e9dcf 3013 /* For PCH output, training FDI link */
674cf967 3014 dev_priv->display.fdi_link_train(crtc);
2c07245f 3015
6f13b7b5
CW		 3016 intel_enable_pch_pll(intel_crtc);
3017
e615efe4
ED		 3018 if (HAS_PCH_LPT(dev)) {
3019 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3020 lpt_program_iclkip(crtc);
3021 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 3022 u32 sel;
4b645f14 3023
c98e9dcf 3024 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3025 switch (pipe) {
3026 default:
3027 case 0:
3028 temp |= TRANSA_DPLL_ENABLE;
3029 sel = TRANSA_DPLLB_SEL;
3030 break;
3031 case 1:
3032 temp |= TRANSB_DPLL_ENABLE;
3033 sel = TRANSB_DPLLB_SEL;
3034 break;
3035 case 2:
3036 temp |= TRANSC_DPLL_ENABLE;
3037 sel = TRANSC_DPLLB_SEL;
3038 break;
d64311ab 3039 }
ee7b9f93
JB		 3040 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3041 temp |= sel;
3042 else
3043 temp &= ~sel;
c98e9dcf 3044 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3045 }
5eddb70b 3046
d9b6cb56
JB		 3047 /* set transcoder timing, panel must allow it */
3048 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3049 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3050 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3051 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3052
5eddb70b
CW		 3053 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3054 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3055 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3056 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3057
f57e1e3a
ED		 3058 if (!IS_HASWELL(dev))
3059 intel_fdi_normal_train(crtc);
5e84e1a4 3060
c98e9dcf
JB		 3061 /* For PCH DP, enable TRANS_DP_CTL */
3062 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3063 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3064 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3065 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3066 reg = TRANS_DP_CTL(pipe);
3067 temp = I915_READ(reg);
3068 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3069 TRANS_DP_SYNC_MASK |
3070 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3071 temp |= (TRANS_DP_OUTPUT_ENABLE |
3072 TRANS_DP_ENH_FRAMING);
9325c9f0 3073 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3074
3075 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3076 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3077 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3078 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3079
3080 switch (intel_trans_dp_port_sel(crtc)) {
3081 case PCH_DP_B:
5eddb70b 3082 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3083 break;
3084 case PCH_DP_C:
5eddb70b 3085 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3086 break;
3087 case PCH_DP_D:
5eddb70b 3088 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3089 break;
3090 default:
3091 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 3092 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 3093 break;
32f9d658 3094 }
2c07245f 3095
5eddb70b 3096 I915_WRITE(reg, temp);
6be4a607 3097 }
b52eb4dc 3098
040484af 3099 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3100}
3101
ee7b9f93
JB		 3102static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3103{
3104 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3105
3106 if (pll == NULL)
3107 return;
3108
3109 if (pll->refcount == 0) {
3110 WARN(1, "bad PCH PLL refcount\n");
3111 return;
3112 }
3113
3114 --pll->refcount;
3115 intel_crtc->pch_pll = NULL;
3116}
3117
3118static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3119{
3120 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3121 struct intel_pch_pll *pll;
3122 int i;
3123
3124 pll = intel_crtc->pch_pll;
3125 if (pll) {
3126 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3127 intel_crtc->base.base.id, pll->pll_reg);
3128 goto prepare;
3129 }
3130
98b6bd99
DV		 3131 if (HAS_PCH_IBX(dev_priv->dev)) {
3132 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3133 i = intel_crtc->pipe;
3134 pll = &dev_priv->pch_plls[i];
3135
3136 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3137 intel_crtc->base.base.id, pll->pll_reg);
3138
3139 goto found;
3140 }
3141
ee7b9f93
JB		 3142 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3143 pll = &dev_priv->pch_plls[i];
3144
3145 /* Only want to check enabled timings first */
3146 if (pll->refcount == 0)
3147 continue;
3148
3149 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3150 fp == I915_READ(pll->fp0_reg)) {
3151 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3152 intel_crtc->base.base.id,
3153 pll->pll_reg, pll->refcount, pll->active);
3154
3155 goto found;
3156 }
3157 }
3158
3159 /* Ok no matching timings, maybe there's a free one? */
3160 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3161 pll = &dev_priv->pch_plls[i];
3162 if (pll->refcount == 0) {
3163 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3164 intel_crtc->base.base.id, pll->pll_reg);
3165 goto found;
3166 }
3167 }
3168
3169 return NULL;
3170
3171found:
3172 intel_crtc->pch_pll = pll;
3173 pll->refcount++;
3174 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3175prepare: /* separate function? */
3176 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3177
e04c7350
CW		 3178 /* Wait for the clocks to stabilize before rewriting the regs */
3179 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3180 POSTING_READ(pll->pll_reg);
3181 udelay(150);
e04c7350
CW		 3182
3183 I915_WRITE(pll->fp0_reg, fp);
3184 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3185 pll->on = false;
3186 return pll;
3187}
3188
d4270e57
JB		 3189void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3190{
3191 struct drm_i915_private *dev_priv = dev->dev_private;
3192 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3193 u32 temp;
3194
3195 temp = I915_READ(dslreg);
3196 udelay(500);
3197 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3198 /* Without this, mode sets may fail silently on FDI */
3199 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3200 udelay(250);
3201 I915_WRITE(tc2reg, 0);
3202 if (wait_for(I915_READ(dslreg) != temp, 5))
3203 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3204 }
3205}
3206
f67a559d
JB		 3207static void ironlake_crtc_enable(struct drm_crtc *crtc)
3208{
3209 struct drm_device *dev = crtc->dev;
3210 struct drm_i915_private *dev_priv = dev->dev_private;
3211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3212 struct intel_encoder *encoder;
f67a559d
JB		 3213 int pipe = intel_crtc->pipe;
3214 int plane = intel_crtc->plane;
3215 u32 temp;
3216 bool is_pch_port;
3217
ef9c3aee
DV		 3218 /* XXX: For compatability with the crtc helper code, call the encoder's
3219 * enable function unconditionally for now. */
f67a559d 3220 if (intel_crtc->active)
ef9c3aee 3221 goto encoders;
f67a559d
JB		 3222
3223 intel_crtc->active = true;
3224 intel_update_watermarks(dev);
3225
3226 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3227 temp = I915_READ(PCH_LVDS);
3228 if ((temp & LVDS_PORT_EN) == 0)
3229 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3230 }
3231
3232 is_pch_port = intel_crtc_driving_pch(crtc);
3233
3234 if (is_pch_port)
88cefb6c 3235 ironlake_fdi_pll_enable(intel_crtc);
f67a559d
JB		 3236 else
3237 ironlake_fdi_disable(crtc);
3238
3239 /* Enable panel fitting for LVDS */
3240 if (dev_priv->pch_pf_size &&
3241 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3242 /* Force use of hard-coded filter coefficients
3243 * as some pre-programmed values are broken,
3244 * e.g. x201.
3245 */
9db4a9c7
JB		 3246 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3247 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3248 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3249 }
3250
9c54c0dd
JB		 3251 /*
3252 * On ILK+ LUT must be loaded before the pipe is running but with
3253 * clocks enabled
3254 */
3255 intel_crtc_load_lut(crtc);
3256
f67a559d
JB		 3257 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3258 intel_enable_plane(dev_priv, plane, pipe);
3259
3260 if (is_pch_port)
3261 ironlake_pch_enable(crtc);
c98e9dcf 3262
d1ebd816 3263 mutex_lock(&dev->struct_mutex);
bed4a673 3264 intel_update_fbc(dev);
d1ebd816
BW		 3265 mutex_unlock(&dev->struct_mutex);
3266
6b383a7f 3267 intel_crtc_update_cursor(crtc, true);
ef9c3aee
DV		 3268
3269encoders:
fa5c73b1
DV		 3270 for_each_encoder_on_crtc(dev, crtc, encoder)
3271 encoder->enable(encoder);
61b77ddd
DV		 3272
3273 if (HAS_PCH_CPT(dev))
3274 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 3275}
3276
3277static void ironlake_crtc_disable(struct drm_crtc *crtc)
3278{
3279 struct drm_device *dev = crtc->dev;
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3282 struct intel_encoder *encoder;
6be4a607
JB		 3283 int pipe = intel_crtc->pipe;
3284 int plane = intel_crtc->plane;
5eddb70b 3285 u32 reg, temp;
b52eb4dc 3286
ef9c3aee
DV		 3287 /* XXX: For compatability with the crtc helper code, call the encoder's
3288 * disable function unconditionally for now. */
fa5c73b1
DV		 3289 for_each_encoder_on_crtc(dev, crtc, encoder)
3290 encoder->disable(encoder);
ef9c3aee 3291
f7abfe8b
CW		 3292 if (!intel_crtc->active)
3293 return;
3294
e6c3a2a6 3295 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3296 drm_vblank_off(dev, pipe);
6b383a7f 3297 intel_crtc_update_cursor(crtc, false);
5eddb70b 3298
b24e7179 3299 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3300
973d04f9
CW		 3301 if (dev_priv->cfb_plane == plane)
3302 intel_disable_fbc(dev);
2c07245f 3303
b24e7179 3304 intel_disable_pipe(dev_priv, pipe);
32f9d658 3305
6be4a607 3306 /* Disable PF */
9db4a9c7
JB		 3307 I915_WRITE(PF_CTL(pipe), 0);
3308 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3309
0fc932b8 3310 ironlake_fdi_disable(crtc);
2c07245f 3311
47a05eca
JB		 3312 /* This is a horrible layering violation; we should be doing this in
3313 * the connector/encoder ->prepare instead, but we don't always have
3314 * enough information there about the config to know whether it will
3315 * actually be necessary or just cause undesired flicker.
3316 */
3317 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3318
040484af 3319 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3320
6be4a607
JB		 3321 if (HAS_PCH_CPT(dev)) {
3322 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3323 reg = TRANS_DP_CTL(pipe);
3324 temp = I915_READ(reg);
3325 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3326 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3327 I915_WRITE(reg, temp);
6be4a607
JB		 3328
3329 /* disable DPLL_SEL */
3330 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3331 switch (pipe) {
3332 case 0:
d64311ab 3333 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3334 break;
3335 case 1:
6be4a607 3336 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3337 break;
3338 case 2:
4b645f14 3339 /* C shares PLL A or B */
d64311ab 3340 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3341 break;
3342 default:
3343 BUG(); /* wtf */
3344 }
6be4a607 3345 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3346 }
e3421a18 3347
6be4a607 3348 /* disable PCH DPLL */
ee7b9f93 3349 intel_disable_pch_pll(intel_crtc);
8db9d77b 3350
88cefb6c 3351 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3352
f7abfe8b 3353 intel_crtc->active = false;
6b383a7f 3354 intel_update_watermarks(dev);
d1ebd816
BW		 3355
3356 mutex_lock(&dev->struct_mutex);
6b383a7f 3357 intel_update_fbc(dev);
d1ebd816 3358 mutex_unlock(&dev->struct_mutex);
6be4a607 3359}
1b3c7a47 3360
ee7b9f93
JB		 3361static void ironlake_crtc_off(struct drm_crtc *crtc)
3362{
3363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3364 intel_put_pch_pll(intel_crtc);
3365}
3366
02e792fb
DV		 3367static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3368{
02e792fb 3369 if (!enable && intel_crtc->overlay) {
23f09ce3 3370 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3371 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3372
23f09ce3 3373 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3374 dev_priv->mm.interruptible = false;
3375 (void) intel_overlay_switch_off(intel_crtc->overlay);
3376 dev_priv->mm.interruptible = true;
23f09ce3 3377 mutex_unlock(&dev->struct_mutex);
02e792fb 3378 }
02e792fb 3379
5dcdbcb0
CW		 3380 /* Let userspace switch the overlay on again. In most cases userspace
3381 * has to recompute where to put it anyway.
3382 */
02e792fb
DV		 3383}
3384
0b8765c6 3385static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3386{
3387 struct drm_device *dev = crtc->dev;
79e53945
JB		 3388 struct drm_i915_private *dev_priv = dev->dev_private;
3389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3390 struct intel_encoder *encoder;
79e53945 3391 int pipe = intel_crtc->pipe;
80824003 3392 int plane = intel_crtc->plane;
79e53945 3393
ef9c3aee
DV		 3394 /* XXX: For compatability with the crtc helper code, call the encoder's
3395 * enable function unconditionally for now. */
f7abfe8b 3396 if (intel_crtc->active)
ef9c3aee 3397 goto encoders;
f7abfe8b
CW		 3398
3399 intel_crtc->active = true;
6b383a7f
CW		 3400 intel_update_watermarks(dev);
3401
63d7bbe9 3402 intel_enable_pll(dev_priv, pipe);
040484af 3403 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3404 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3405
0b8765c6 3406 intel_crtc_load_lut(crtc);
bed4a673 3407 intel_update_fbc(dev);
79e53945 3408
0b8765c6
JB		 3409 /* Give the overlay scaler a chance to enable if it's on this pipe */
3410 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3411 intel_crtc_update_cursor(crtc, true);
ef9c3aee
DV		 3412
3413encoders:
fa5c73b1
DV		 3414 for_each_encoder_on_crtc(dev, crtc, encoder)
3415 encoder->enable(encoder);
0b8765c6 3416}
79e53945 3417
0b8765c6
JB		 3418static void i9xx_crtc_disable(struct drm_crtc *crtc)
3419{
3420 struct drm_device *dev = crtc->dev;
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3423 struct intel_encoder *encoder;
0b8765c6
JB		 3424 int pipe = intel_crtc->pipe;
3425 int plane = intel_crtc->plane;
b690e96c 3426
ef9c3aee
DV		 3427 /* XXX: For compatability with the crtc helper code, call the encoder's
3428 * disable function unconditionally for now. */
fa5c73b1
DV		 3429 for_each_encoder_on_crtc(dev, crtc, encoder)
3430 encoder->disable(encoder);
ef9c3aee 3431
f7abfe8b
CW		 3432 if (!intel_crtc->active)
3433 return;
3434
0b8765c6 3435 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3436 intel_crtc_wait_for_pending_flips(crtc);
3437 drm_vblank_off(dev, pipe);
0b8765c6 3438 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3439 intel_crtc_update_cursor(crtc, false);
0b8765c6 3440
973d04f9
CW		 3441 if (dev_priv->cfb_plane == plane)
3442 intel_disable_fbc(dev);
79e53945 3443
b24e7179 3444 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3445 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3446 intel_disable_pll(dev_priv, pipe);
0b8765c6 3447
f7abfe8b 3448 intel_crtc->active = false;
6b383a7f
CW		 3449 intel_update_fbc(dev);
3450 intel_update_watermarks(dev);
0b8765c6
JB		 3451}
3452
ee7b9f93
JB		 3453static void i9xx_crtc_off(struct drm_crtc *crtc)
3454{
3455}
3456
2c07245f
ZW		 3457/**
3458 * Sets the power management mode of the pipe and plane.
2c07245f 3459 */
b2cabb0e 3460void intel_crtc_update_dpms(struct drm_crtc *crtc)
2c07245f
ZW		 3461{
3462 struct drm_device *dev = crtc->dev;
e70236a8 3463 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3464 struct drm_i915_master_private *master_priv;
3465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b2cabb0e 3466 struct intel_encoder *intel_encoder;
2c07245f 3467 int pipe = intel_crtc->pipe;
b2cabb0e
DV		 3468 bool enabled, enable = false;
3469 int mode;
3470
3471 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3472 enable |= intel_encoder->connectors_active;
3473
3474 mode = enable ? DRM_MODE_DPMS_ON : DRM_MODE_DPMS_OFF;
2c07245f 3475
032d2a0d
CW		 3476 if (intel_crtc->dpms_mode == mode)
3477 return;
3478
65655d4a 3479 intel_crtc->dpms_mode = mode;
debcaddc 3480
b2cabb0e 3481 if (enable)
76e5a89c 3482 dev_priv->display.crtc_enable(crtc);
b2cabb0e 3483 else
76e5a89c 3484 dev_priv->display.crtc_disable(crtc);
79e53945
JB		 3485
3486 if (!dev->primary->master)
3487 return;
3488
3489 master_priv = dev->primary->master->driver_priv;
3490 if (!master_priv->sarea_priv)
3491 return;
3492
b2cabb0e 3493 enabled = crtc->enabled && enable;
79e53945
JB		 3494
3495 switch (pipe) {
3496 case 0:
3497 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3498 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3499 break;
3500 case 1:
3501 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3502 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3503 break;
3504 default:
9db4a9c7 3505 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3506 break;
3507 }
79e53945
JB		 3508}
3509
cdd59983
CW		 3510static void intel_crtc_disable(struct drm_crtc *crtc)
3511{
cdd59983 3512 struct drm_device *dev = crtc->dev;
ee7b9f93 3513 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3514
b2cabb0e
DV		 3515 /* crtc->disable is only called when we have no encoders, hence this
3516 * will disable the pipe. */
3517 intel_crtc_update_dpms(crtc);
ee7b9f93
JB		 3518 dev_priv->display.off(crtc);
3519
931872fc
CW		 3520 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3521 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3522
3523 if (crtc->fb) {
3524 mutex_lock(&dev->struct_mutex);
1690e1eb 3525 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3526 mutex_unlock(&dev->struct_mutex);
3527 }
3528}
3529
5ab432ef
DV		 3530void intel_encoder_disable(struct drm_encoder *encoder)
3531{
3532 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3533
3534 intel_encoder->disable(intel_encoder);
3535}
3536
ea5b213a
CW		 3537void intel_encoder_destroy(struct drm_encoder *encoder)
3538{
4ef69c7a 3539 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3540
ea5b213a
CW		 3541 drm_encoder_cleanup(encoder);
3542 kfree(intel_encoder);
3543}
3544
5ab432ef
DV		 3545/* Simple dpms helper for encodres with just one connector, no cloning and only
3546 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3547 * state of the entire output pipe. */
3548void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3549{
3550 if (mode == DRM_MODE_DPMS_ON) {
3551 encoder->connectors_active = true;
3552
b2cabb0e 3553 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3554 } else {
3555 encoder->connectors_active = false;
3556
b2cabb0e 3557 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3558 }
3559}
3560
3561/* Even simpler default implementation, if there's really no special case to
3562 * consider. */
3563void intel_connector_dpms(struct drm_connector *connector, int mode)
3564{
3565 struct intel_encoder *encoder = intel_attached_encoder(connector);
3566
3567 /* All the simple cases only support two dpms states. */
3568 if (mode != DRM_MODE_DPMS_ON)
3569 mode = DRM_MODE_DPMS_OFF;
3570
3571 if (mode == connector->dpms)
3572 return;
3573
3574 connector->dpms = mode;
3575
3576 /* Only need to change hw state when actually enabled */
3577 if (encoder->base.crtc)
3578 intel_encoder_dpms(encoder, mode);
3579 else
3580 encoder->connectors_active = false;
3581}
3582
79e53945 3583static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3584 const struct drm_display_mode *mode,
79e53945
JB		 3585 struct drm_display_mode *adjusted_mode)
3586{
2c07245f 3587 struct drm_device *dev = crtc->dev;
89749350 3588
bad720ff 3589 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3590 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3591 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3592 return false;
2c07245f 3593 }
89749350 3594
f9bef081
DV		 3595 /* All interlaced capable intel hw wants timings in frames. Note though
3596 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3597 * timings, so we need to be careful not to clobber these.*/
3598 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3599 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3600
79e53945
JB		 3601 return true;
3602}
3603
25eb05fc
JB		 3604static int valleyview_get_display_clock_speed(struct drm_device *dev)
3605{
3606 return 400000; /* FIXME */
3607}
3608
e70236a8
JB		 3609static int i945_get_display_clock_speed(struct drm_device *dev)
3610{
3611 return 400000;
3612}
79e53945 3613
e70236a8 3614static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3615{
e70236a8
JB		 3616 return 333000;
3617}
79e53945 3618
e70236a8
JB		 3619static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3620{
3621 return 200000;
3622}
79e53945 3623
e70236a8
JB		 3624static int i915gm_get_display_clock_speed(struct drm_device *dev)
3625{
3626 u16 gcfgc = 0;
79e53945 3627
e70236a8
JB		 3628 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3629
3630 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3631 return 133000;
3632 else {
3633 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3634 case GC_DISPLAY_CLOCK_333_MHZ:
3635 return 333000;
3636 default:
3637 case GC_DISPLAY_CLOCK_190_200_MHZ:
3638 return 190000;
79e53945 3639 }
e70236a8
JB		 3640 }
3641}
3642
3643static int i865_get_display_clock_speed(struct drm_device *dev)
3644{
3645 return 266000;
3646}
3647
3648static int i855_get_display_clock_speed(struct drm_device *dev)
3649{
3650 u16 hpllcc = 0;
3651 /* Assume that the hardware is in the high speed state. This
3652 * should be the default.
3653 */
3654 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3655 case GC_CLOCK_133_200:
3656 case GC_CLOCK_100_200:
3657 return 200000;
3658 case GC_CLOCK_166_250:
3659 return 250000;
3660 case GC_CLOCK_100_133:
79e53945 3661 return 133000;
e70236a8 3662 }
79e53945 3663
e70236a8
JB		 3664 /* Shouldn't happen */
3665 return 0;
3666}
79e53945 3667
e70236a8
JB		 3668static int i830_get_display_clock_speed(struct drm_device *dev)
3669{
3670 return 133000;
79e53945
JB		 3671}
3672
2c07245f
ZW		 3673struct fdi_m_n {
3674 u32 tu;
3675 u32 gmch_m;
3676 u32 gmch_n;
3677 u32 link_m;
3678 u32 link_n;
3679};
3680
3681static void
3682fdi_reduce_ratio(u32 *num, u32 *den)
3683{
3684 while (*num > 0xffffff || *den > 0xffffff) {
3685 *num >>= 1;
3686 *den >>= 1;
3687 }
3688}
3689
2c07245f 3690static void
f2b115e6
AJ		 3691ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3692 int link_clock, struct fdi_m_n *m_n)
2c07245f 3693{
2c07245f
ZW		 3694 m_n->tu = 64; /* default size */
3695
22ed1113
CW		 3696 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3697 m_n->gmch_m = bits_per_pixel * pixel_clock;
3698 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3699 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3700
22ed1113
CW		 3701 m_n->link_m = pixel_clock;
3702 m_n->link_n = link_clock;
2c07245f
ZW		 3703 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3704}
3705
a7615030
CW		 3706static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3707{
72bbe58c
KP		 3708 if (i915_panel_use_ssc >= 0)
3709 return i915_panel_use_ssc != 0;
3710 return dev_priv->lvds_use_ssc
435793df 3711 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3712}
3713
5a354204
JB		 3714/**
3715 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3716 * @crtc: CRTC structure
3b5c78a3 3717 * @mode: requested mode
5a354204
JB		 3718 *
3719 * A pipe may be connected to one or more outputs. Based on the depth of the
3720 * attached framebuffer, choose a good color depth to use on the pipe.
3721 *
3722 * If possible, match the pipe depth to the fb depth. In some cases, this
3723 * isn't ideal, because the connected output supports a lesser or restricted
3724 * set of depths. Resolve that here:
3725 * LVDS typically supports only 6bpc, so clamp down in that case
3726 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3727 * Displays may support a restricted set as well, check EDID and clamp as
3728 * appropriate.
3b5c78a3 3729 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3730 *
3731 * RETURNS:
3732 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3733 * true if they don't match).
3734 */
3735static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 3736 unsigned int *pipe_bpp,
3737 struct drm_display_mode *mode)
5a354204
JB		 3738{
3739 struct drm_device *dev = crtc->dev;
3740 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 3741 struct drm_connector *connector;
6c2b7c12 3742 struct intel_encoder *intel_encoder;
5a354204
JB		 3743 unsigned int display_bpc = UINT_MAX, bpc;
3744
3745 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 3746 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 3747
3748 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3749 unsigned int lvds_bpc;
3750
3751 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3752 LVDS_A3_POWER_UP)
3753 lvds_bpc = 8;
3754 else
3755 lvds_bpc = 6;
3756
3757 if (lvds_bpc < display_bpc) {
82820490 3758 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3759 display_bpc = lvds_bpc;
3760 }
3761 continue;
3762 }
3763
5a354204
JB		 3764 /* Not one of the known troublemakers, check the EDID */
3765 list_for_each_entry(connector, &dev->mode_config.connector_list,
3766 head) {
6c2b7c12 3767 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 3768 continue;
3769
62ac41a6
JB		 3770 /* Don't use an invalid EDID bpc value */
3771 if (connector->display_info.bpc &&
3772 connector->display_info.bpc < display_bpc) {
82820490 3773 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3774 display_bpc = connector->display_info.bpc;
3775 }
3776 }
3777
3778 /*
3779 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3780 * through, clamp it down. (Note: >12bpc will be caught below.)
3781 */
3782 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3783 if (display_bpc > 8 && display_bpc < 12) {
82820490 3784 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3785 display_bpc = 12;
3786 } else {
82820490 3787 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3788 display_bpc = 8;
3789 }
3790 }
3791 }
3792
3b5c78a3
AJ		 3793 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3794 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3795 display_bpc = 6;
3796 }
3797
5a354204
JB		 3798 /*
3799 * We could just drive the pipe at the highest bpc all the time and
3800 * enable dithering as needed, but that costs bandwidth. So choose
3801 * the minimum value that expresses the full color range of the fb but
3802 * also stays within the max display bpc discovered above.
3803 */
3804
3805 switch (crtc->fb->depth) {
3806 case 8:
3807 bpc = 8; /* since we go through a colormap */
3808 break;
3809 case 15:
3810 case 16:
3811 bpc = 6; /* min is 18bpp */
3812 break;
3813 case 24:
578393cd 3814 bpc = 8;
5a354204
JB		 3815 break;
3816 case 30:
578393cd 3817 bpc = 10;
5a354204
JB		 3818 break;
3819 case 48:
578393cd 3820 bpc = 12;
5a354204
JB		 3821 break;
3822 default:
3823 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3824 bpc = min((unsigned int)8, display_bpc);
3825 break;
3826 }
3827
578393cd
KP		 3828 display_bpc = min(display_bpc, bpc);
3829
82820490
AJ		 3830 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3831 bpc, display_bpc);
5a354204 3832
578393cd 3833 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3834
3835 return display_bpc != bpc;
3836}
3837
a0c4da24
JB		 3838static int vlv_get_refclk(struct drm_crtc *crtc)
3839{
3840 struct drm_device *dev = crtc->dev;
3841 struct drm_i915_private *dev_priv = dev->dev_private;
3842 int refclk = 27000; /* for DP & HDMI */
3843
3844 return 100000; /* only one validated so far */
3845
3846 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3847 refclk = 96000;
3848 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3849 if (intel_panel_use_ssc(dev_priv))
3850 refclk = 100000;
3851 else
3852 refclk = 96000;
3853 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3854 refclk = 100000;
3855 }
3856
3857 return refclk;
3858}
3859
c65d77d8
JB		 3860static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3861{
3862 struct drm_device *dev = crtc->dev;
3863 struct drm_i915_private *dev_priv = dev->dev_private;
3864 int refclk;
3865
a0c4da24
JB		 3866 if (IS_VALLEYVIEW(dev)) {
3867 refclk = vlv_get_refclk(crtc);
3868 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 3869 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3870 refclk = dev_priv->lvds_ssc_freq * 1000;
3871 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3872 refclk / 1000);
3873 } else if (!IS_GEN2(dev)) {
3874 refclk = 96000;
3875 } else {
3876 refclk = 48000;
3877 }
3878
3879 return refclk;
3880}
3881
3882static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3883 intel_clock_t *clock)
3884{
3885 /* SDVO TV has fixed PLL values depend on its clock range,
3886 this mirrors vbios setting. */
3887 if (adjusted_mode->clock >= 100000
3888 && adjusted_mode->clock < 140500) {
3889 clock->p1 = 2;
3890 clock->p2 = 10;
3891 clock->n = 3;
3892 clock->m1 = 16;
3893 clock->m2 = 8;
3894 } else if (adjusted_mode->clock >= 140500
3895 && adjusted_mode->clock <= 200000) {
3896 clock->p1 = 1;
3897 clock->p2 = 10;
3898 clock->n = 6;
3899 clock->m1 = 12;
3900 clock->m2 = 8;
3901 }
3902}
3903
a7516a05
JB		 3904static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3905 intel_clock_t *clock,
3906 intel_clock_t *reduced_clock)
3907{
3908 struct drm_device *dev = crtc->dev;
3909 struct drm_i915_private *dev_priv = dev->dev_private;
3910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3911 int pipe = intel_crtc->pipe;
3912 u32 fp, fp2 = 0;
3913
3914 if (IS_PINEVIEW(dev)) {
3915 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3916 if (reduced_clock)
3917 fp2 = (1 << reduced_clock->n) << 16 |
3918 reduced_clock->m1 << 8 | reduced_clock->m2;
3919 } else {
3920 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3921 if (reduced_clock)
3922 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3923 reduced_clock->m2;
3924 }
3925
3926 I915_WRITE(FP0(pipe), fp);
3927
3928 intel_crtc->lowfreq_avail = false;
3929 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3930 reduced_clock && i915_powersave) {
3931 I915_WRITE(FP1(pipe), fp2);
3932 intel_crtc->lowfreq_avail = true;
3933 } else {
3934 I915_WRITE(FP1(pipe), fp);
3935 }
3936}
3937
93e537a1
DV		 3938static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3939 struct drm_display_mode *adjusted_mode)
3940{
3941 struct drm_device *dev = crtc->dev;
3942 struct drm_i915_private *dev_priv = dev->dev_private;
3943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3944 int pipe = intel_crtc->pipe;
284d5df5 3945 u32 temp;
93e537a1
DV		 3946
3947 temp = I915_READ(LVDS);
3948 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3949 if (pipe == 1) {
3950 temp |= LVDS_PIPEB_SELECT;
3951 } else {
3952 temp &= ~LVDS_PIPEB_SELECT;
3953 }
3954 /* set the corresponsding LVDS_BORDER bit */
3955 temp |= dev_priv->lvds_border_bits;
3956 /* Set the B0-B3 data pairs corresponding to whether we're going to
3957 * set the DPLLs for dual-channel mode or not.
3958 */
3959 if (clock->p2 == 7)
3960 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3961 else
3962 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3963
3964 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3965 * appropriately here, but we need to look more thoroughly into how
3966 * panels behave in the two modes.
3967 */
3968 /* set the dithering flag on LVDS as needed */
3969 if (INTEL_INFO(dev)->gen >= 4) {
3970 if (dev_priv->lvds_dither)
3971 temp |= LVDS_ENABLE_DITHER;
3972 else
3973 temp &= ~LVDS_ENABLE_DITHER;
3974 }
284d5df5 3975 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 3976 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 3977 temp |= LVDS_HSYNC_POLARITY;
93e537a1 3978 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 3979 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 3980 I915_WRITE(LVDS, temp);
3981}
3982
a0c4da24
JB		 3983static void vlv_update_pll(struct drm_crtc *crtc,
3984 struct drm_display_mode *mode,
3985 struct drm_display_mode *adjusted_mode,
3986 intel_clock_t *clock, intel_clock_t *reduced_clock,
3987 int refclk, int num_connectors)
3988{
3989 struct drm_device *dev = crtc->dev;
3990 struct drm_i915_private *dev_priv = dev->dev_private;
3991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3992 int pipe = intel_crtc->pipe;
3993 u32 dpll, mdiv, pdiv;
3994 u32 bestn, bestm1, bestm2, bestp1, bestp2;
3995 bool is_hdmi;
3996
3997 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3998
3999 bestn = clock->n;
4000 bestm1 = clock->m1;
4001 bestm2 = clock->m2;
4002 bestp1 = clock->p1;
4003 bestp2 = clock->p2;
4004
4005 /* Enable DPIO clock input */
4006 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4007 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4008 I915_WRITE(DPLL(pipe), dpll);
4009 POSTING_READ(DPLL(pipe));
4010
4011 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4012 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4013 mdiv |= ((bestn << DPIO_N_SHIFT));
4014 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4015 mdiv |= (1 << DPIO_K_SHIFT);
4016 mdiv |= DPIO_ENABLE_CALIBRATION;
4017 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4018
4019 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4020
4021 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4022 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4023 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4024 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4025
4026 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4027
4028 dpll |= DPLL_VCO_ENABLE;
4029 I915_WRITE(DPLL(pipe), dpll);
4030 POSTING_READ(DPLL(pipe));
4031 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4032 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4033
4034 if (is_hdmi) {
4035 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4036
4037 if (temp > 1)
4038 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4039 else
4040 temp = 0;
4041
4042 I915_WRITE(DPLL_MD(pipe), temp);
4043 POSTING_READ(DPLL_MD(pipe));
4044 }
4045
4046 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4047}
4048
eb1cbe48
DV		 4049static void i9xx_update_pll(struct drm_crtc *crtc,
4050 struct drm_display_mode *mode,
4051 struct drm_display_mode *adjusted_mode,
4052 intel_clock_t *clock, intel_clock_t *reduced_clock,
4053 int num_connectors)
4054{
4055 struct drm_device *dev = crtc->dev;
4056 struct drm_i915_private *dev_priv = dev->dev_private;
4057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4058 int pipe = intel_crtc->pipe;
4059 u32 dpll;
4060 bool is_sdvo;
4061
4062 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4063 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4064
4065 dpll = DPLL_VGA_MODE_DIS;
4066
4067 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4068 dpll |= DPLLB_MODE_LVDS;
4069 else
4070 dpll |= DPLLB_MODE_DAC_SERIAL;
4071 if (is_sdvo) {
4072 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4073 if (pixel_multiplier > 1) {
4074 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4075 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4076 }
4077 dpll |= DPLL_DVO_HIGH_SPEED;
4078 }
4079 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4080 dpll |= DPLL_DVO_HIGH_SPEED;
4081
4082 /* compute bitmask from p1 value */
4083 if (IS_PINEVIEW(dev))
4084 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4085 else {
4086 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4087 if (IS_G4X(dev) && reduced_clock)
4088 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4089 }
4090 switch (clock->p2) {
4091 case 5:
4092 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4093 break;
4094 case 7:
4095 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4096 break;
4097 case 10:
4098 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4099 break;
4100 case 14:
4101 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4102 break;
4103 }
4104 if (INTEL_INFO(dev)->gen >= 4)
4105 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4106
4107 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4108 dpll |= PLL_REF_INPUT_TVCLKINBC;
4109 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4110 /* XXX: just matching BIOS for now */
4111 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4112 dpll |= 3;
4113 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4114 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4115 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4116 else
4117 dpll |= PLL_REF_INPUT_DREFCLK;
4118
4119 dpll |= DPLL_VCO_ENABLE;
4120 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4121 POSTING_READ(DPLL(pipe));
4122 udelay(150);
4123
4124 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4125 * This is an exception to the general rule that mode_set doesn't turn
4126 * things on.
4127 */
4128 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4129 intel_update_lvds(crtc, clock, adjusted_mode);
4130
4131 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4132 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4133
4134 I915_WRITE(DPLL(pipe), dpll);
4135
4136 /* Wait for the clocks to stabilize. */
4137 POSTING_READ(DPLL(pipe));
4138 udelay(150);
4139
4140 if (INTEL_INFO(dev)->gen >= 4) {
4141 u32 temp = 0;
4142 if (is_sdvo) {
4143 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4144 if (temp > 1)
4145 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4146 else
4147 temp = 0;
4148 }
4149 I915_WRITE(DPLL_MD(pipe), temp);
4150 } else {
4151 /* The pixel multiplier can only be updated once the
4152 * DPLL is enabled and the clocks are stable.
4153 *
4154 * So write it again.
4155 */
4156 I915_WRITE(DPLL(pipe), dpll);
4157 }
4158}
4159
4160static void i8xx_update_pll(struct drm_crtc *crtc,
4161 struct drm_display_mode *adjusted_mode,
4162 intel_clock_t *clock,
4163 int num_connectors)
4164{
4165 struct drm_device *dev = crtc->dev;
4166 struct drm_i915_private *dev_priv = dev->dev_private;
4167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4168 int pipe = intel_crtc->pipe;
4169 u32 dpll;
4170
4171 dpll = DPLL_VGA_MODE_DIS;
4172
4173 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4174 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4175 } else {
4176 if (clock->p1 == 2)
4177 dpll |= PLL_P1_DIVIDE_BY_TWO;
4178 else
4179 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4180 if (clock->p2 == 4)
4181 dpll |= PLL_P2_DIVIDE_BY_4;
4182 }
4183
4184 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4185 /* XXX: just matching BIOS for now */
4186 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4187 dpll |= 3;
4188 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4189 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4190 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4191 else
4192 dpll |= PLL_REF_INPUT_DREFCLK;
4193
4194 dpll |= DPLL_VCO_ENABLE;
4195 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4196 POSTING_READ(DPLL(pipe));
4197 udelay(150);
4198
4199 I915_WRITE(DPLL(pipe), dpll);
4200
4201 /* Wait for the clocks to stabilize. */
4202 POSTING_READ(DPLL(pipe));
4203 udelay(150);
4204
4205 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4206 * This is an exception to the general rule that mode_set doesn't turn
4207 * things on.
4208 */
4209 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4210 intel_update_lvds(crtc, clock, adjusted_mode);
4211
4212 /* The pixel multiplier can only be updated once the
4213 * DPLL is enabled and the clocks are stable.
4214 *
4215 * So write it again.
4216 */
4217 I915_WRITE(DPLL(pipe), dpll);
4218}
4219
f564048e
EA		 4220static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4221 struct drm_display_mode *mode,
4222 struct drm_display_mode *adjusted_mode,
4223 int x, int y,
4224 struct drm_framebuffer *old_fb)
79e53945
JB		 4225{
4226 struct drm_device *dev = crtc->dev;
4227 struct drm_i915_private *dev_priv = dev->dev_private;
4228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4229 int pipe = intel_crtc->pipe;
80824003 4230 int plane = intel_crtc->plane;
c751ce4f 4231 int refclk, num_connectors = 0;
652c393a 4232 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 4233 u32 dspcntr, pipeconf, vsyncshift;
4234 bool ok, has_reduced_clock = false, is_sdvo = false;
4235 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4236 struct intel_encoder *encoder;
d4906093 4237 const intel_limit_t *limit;
5c3b82e2 4238 int ret;
79e53945 4239
6c2b7c12 4240 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4241 switch (encoder->type) {
79e53945
JB		 4242 case INTEL_OUTPUT_LVDS:
4243 is_lvds = true;
4244 break;
4245 case INTEL_OUTPUT_SDVO:
7d57382e 4246 case INTEL_OUTPUT_HDMI:
79e53945 4247 is_sdvo = true;
5eddb70b 4248 if (encoder->needs_tv_clock)
e2f0ba97 4249 is_tv = true;
79e53945 4250 break;
79e53945
JB		 4251 case INTEL_OUTPUT_TVOUT:
4252 is_tv = true;
4253 break;
a4fc5ed6
KP		 4254 case INTEL_OUTPUT_DISPLAYPORT:
4255 is_dp = true;
4256 break;
79e53945 4257 }
43565a06 4258
c751ce4f 4259 num_connectors++;
79e53945
JB		 4260 }
4261
c65d77d8 4262 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4263
d4906093
ML		 4264 /*
4265 * Returns a set of divisors for the desired target clock with the given
4266 * refclk, or FALSE. The returned values represent the clock equation:
4267 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4268 */
1b894b59 4269 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4270 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4271 &clock);
79e53945
JB		 4272 if (!ok) {
4273 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4274 return -EINVAL;
79e53945
JB		 4275 }
4276
cda4b7d3 4277 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4278 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4279
ddc9003c 4280 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4281 /*
4282 * Ensure we match the reduced clock's P to the target clock.
4283 * If the clocks don't match, we can't switch the display clock
4284 * by using the FP0/FP1. In such case we will disable the LVDS
4285 * downclock feature.
4286 */
ddc9003c 4287 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4288 dev_priv->lvds_downclock,
4289 refclk,
cec2f356 4290 &clock,
5eddb70b 4291 &reduced_clock);
7026d4ac
ZW		 4292 }
4293
c65d77d8
JB		 4294 if (is_sdvo && is_tv)
4295 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4296
a7516a05
JB		 4297 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4298 &reduced_clock : NULL);
79e53945 4299
eb1cbe48
DV		 4300 if (IS_GEN2(dev))
4301 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
a0c4da24
JB		 4302 else if (IS_VALLEYVIEW(dev))
4303 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4304 refclk, num_connectors);
79e53945 4305 else
eb1cbe48
DV		 4306 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4307 has_reduced_clock ? &reduced_clock : NULL,
4308 num_connectors);
79e53945
JB		 4309
4310 /* setup pipeconf */
5eddb70b 4311 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4312
4313 /* Set up the display plane register */
4314 dspcntr = DISPPLANE_GAMMA_ENABLE;
4315
929c77fb
EA		 4316 if (pipe == 0)
4317 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4318 else
4319 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4320
a6c45cf0 4321 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4322 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4323 * core speed.
4324 *
4325 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4326 * pipe == 0 check?
4327 */
e70236a8
JB		 4328 if (mode->clock >
4329 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4330 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4331 else
5eddb70b 4332 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4333 }
4334
3b5c78a3
AJ		 4335 /* default to 8bpc */
4336 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4337 if (is_dp) {
4338 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4339 pipeconf |= PIPECONF_BPP_6 |
4340 PIPECONF_DITHER_EN |
4341 PIPECONF_DITHER_TYPE_SP;
4342 }
4343 }
4344
28c97730 4345 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4346 drm_mode_debug_printmodeline(mode);
4347
a7516a05
JB		 4348 if (HAS_PIPE_CXSR(dev)) {
4349 if (intel_crtc->lowfreq_avail) {
28c97730 4350 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4351 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4352 } else {
28c97730 4353 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4354 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4355 }
4356 }
4357
617cf884 4358 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 4359 if (!IS_GEN2(dev) &&
4360 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 4361 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4362 /* the chip adds 2 halflines automatically */
734b4157 4363 adjusted_mode->crtc_vtotal -= 1;
734b4157 4364 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4365 vsyncshift = adjusted_mode->crtc_hsync_start
4366 - adjusted_mode->crtc_htotal/2;
4367 } else {
617cf884 4368 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4369 vsyncshift = 0;
4370 }
4371
4372 if (!IS_GEN3(dev))
4373 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 4374
5eddb70b
CW		 4375 I915_WRITE(HTOTAL(pipe),
4376 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4377 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4378 I915_WRITE(HBLANK(pipe),
4379 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4380 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4381 I915_WRITE(HSYNC(pipe),
4382 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4383 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4384
4385 I915_WRITE(VTOTAL(pipe),
4386 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4387 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4388 I915_WRITE(VBLANK(pipe),
4389 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4390 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4391 I915_WRITE(VSYNC(pipe),
4392 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4393 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4394
4395 /* pipesrc and dspsize control the size that is scaled from,
4396 * which should always be the user's requested size.
79e53945 4397 */
929c77fb
EA		 4398 I915_WRITE(DSPSIZE(plane),
4399 ((mode->vdisplay - 1) << 16) |
4400 (mode->hdisplay - 1));
4401 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4402 I915_WRITE(PIPESRC(pipe),
4403 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4404
f564048e
EA		 4405 I915_WRITE(PIPECONF(pipe), pipeconf);
4406 POSTING_READ(PIPECONF(pipe));
929c77fb 4407 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4408
4409 intel_wait_for_vblank(dev, pipe);
4410
f564048e
EA		 4411 I915_WRITE(DSPCNTR(plane), dspcntr);
4412 POSTING_READ(DSPCNTR(plane));
4413
4414 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4415
4416 intel_update_watermarks(dev);
4417
f564048e
EA		 4418 return ret;
4419}
4420
9fb526db
KP		 4421/*
4422 * Initialize reference clocks when the driver loads
4423 */
4424void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4425{
4426 struct drm_i915_private *dev_priv = dev->dev_private;
4427 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4428 struct intel_encoder *encoder;
13d83a67
JB		 4429 u32 temp;
4430 bool has_lvds = false;
199e5d79
KP		 4431 bool has_cpu_edp = false;
4432 bool has_pch_edp = false;
4433 bool has_panel = false;
99eb6a01
KP		 4434 bool has_ck505 = false;
4435 bool can_ssc = false;
13d83a67
JB		 4436
4437 /* We need to take the global config into account */
199e5d79
KP		 4438 list_for_each_entry(encoder, &mode_config->encoder_list,
4439 base.head) {
4440 switch (encoder->type) {
4441 case INTEL_OUTPUT_LVDS:
4442 has_panel = true;
4443 has_lvds = true;
4444 break;
4445 case INTEL_OUTPUT_EDP:
4446 has_panel = true;
4447 if (intel_encoder_is_pch_edp(&encoder->base))
4448 has_pch_edp = true;
4449 else
4450 has_cpu_edp = true;
4451 break;
13d83a67
JB		 4452 }
4453 }
4454
99eb6a01
KP		 4455 if (HAS_PCH_IBX(dev)) {
4456 has_ck505 = dev_priv->display_clock_mode;
4457 can_ssc = has_ck505;
4458 } else {
4459 has_ck505 = false;
4460 can_ssc = true;
4461 }
4462
4463 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4464 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4465 has_ck505);
13d83a67
JB		 4466
4467 /* Ironlake: try to setup display ref clock before DPLL
4468 * enabling. This is only under driver's control after
4469 * PCH B stepping, previous chipset stepping should be
4470 * ignoring this setting.
4471 */
4472 temp = I915_READ(PCH_DREF_CONTROL);
4473 /* Always enable nonspread source */
4474 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4475
99eb6a01
KP		 4476 if (has_ck505)
4477 temp |= DREF_NONSPREAD_CK505_ENABLE;
4478 else
4479 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4480
199e5d79
KP		 4481 if (has_panel) {
4482 temp &= ~DREF_SSC_SOURCE_MASK;
4483 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4484
199e5d79 4485 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4486 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4487 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4488 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4489 } else
4490 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4491
4492 /* Get SSC going before enabling the outputs */
4493 I915_WRITE(PCH_DREF_CONTROL, temp);
4494 POSTING_READ(PCH_DREF_CONTROL);
4495 udelay(200);
4496
13d83a67
JB		 4497 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4498
4499 /* Enable CPU source on CPU attached eDP */
199e5d79 4500 if (has_cpu_edp) {
99eb6a01 4501 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4502 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4503 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4504 }
13d83a67
JB		 4505 else
4506 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4507 } else
4508 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4509
4510 I915_WRITE(PCH_DREF_CONTROL, temp);
4511 POSTING_READ(PCH_DREF_CONTROL);
4512 udelay(200);
4513 } else {
4514 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4515
4516 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4517
4518 /* Turn off CPU output */
4519 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4520
4521 I915_WRITE(PCH_DREF_CONTROL, temp);
4522 POSTING_READ(PCH_DREF_CONTROL);
4523 udelay(200);
4524
4525 /* Turn off the SSC source */
4526 temp &= ~DREF_SSC_SOURCE_MASK;
4527 temp |= DREF_SSC_SOURCE_DISABLE;
4528
4529 /* Turn off SSC1 */
4530 temp &= ~ DREF_SSC1_ENABLE;
4531
13d83a67
JB		 4532 I915_WRITE(PCH_DREF_CONTROL, temp);
4533 POSTING_READ(PCH_DREF_CONTROL);
4534 udelay(200);
4535 }
4536}
4537
d9d444cb
JB		 4538static int ironlake_get_refclk(struct drm_crtc *crtc)
4539{
4540 struct drm_device *dev = crtc->dev;
4541 struct drm_i915_private *dev_priv = dev->dev_private;
4542 struct intel_encoder *encoder;
d9d444cb
JB		 4543 struct intel_encoder *edp_encoder = NULL;
4544 int num_connectors = 0;
4545 bool is_lvds = false;
4546
6c2b7c12 4547 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4548 switch (encoder->type) {
4549 case INTEL_OUTPUT_LVDS:
4550 is_lvds = true;
4551 break;
4552 case INTEL_OUTPUT_EDP:
4553 edp_encoder = encoder;
4554 break;
4555 }
4556 num_connectors++;
4557 }
4558
4559 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4560 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4561 dev_priv->lvds_ssc_freq);
4562 return dev_priv->lvds_ssc_freq * 1000;
4563 }
4564
4565 return 120000;
4566}
4567
f564048e
EA		 4568static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4569 struct drm_display_mode *mode,
4570 struct drm_display_mode *adjusted_mode,
4571 int x, int y,
4572 struct drm_framebuffer *old_fb)
79e53945
JB		 4573{
4574 struct drm_device *dev = crtc->dev;
4575 struct drm_i915_private *dev_priv = dev->dev_private;
4576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4577 int pipe = intel_crtc->pipe;
80824003 4578 int plane = intel_crtc->plane;
c751ce4f 4579 int refclk, num_connectors = 0;
652c393a 4580 intel_clock_t clock, reduced_clock;
5eddb70b 4581 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4582 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4583 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
e3aef172 4584 struct intel_encoder *encoder, *edp_encoder = NULL;
d4906093 4585 const intel_limit_t *limit;
5c3b82e2 4586 int ret;
2c07245f 4587 struct fdi_m_n m_n = {0};
fae14981 4588 u32 temp;
5a354204
JB		 4589 int target_clock, pixel_multiplier, lane, link_bw, factor;
4590 unsigned int pipe_bpp;
4591 bool dither;
e3aef172 4592 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 4593
6c2b7c12 4594 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4595 switch (encoder->type) {
79e53945
JB		 4596 case INTEL_OUTPUT_LVDS:
4597 is_lvds = true;
4598 break;
4599 case INTEL_OUTPUT_SDVO:
7d57382e 4600 case INTEL_OUTPUT_HDMI:
79e53945 4601 is_sdvo = true;
5eddb70b 4602 if (encoder->needs_tv_clock)
e2f0ba97 4603 is_tv = true;
79e53945 4604 break;
79e53945
JB		 4605 case INTEL_OUTPUT_TVOUT:
4606 is_tv = true;
4607 break;
4608 case INTEL_OUTPUT_ANALOG:
4609 is_crt = true;
4610 break;
a4fc5ed6
KP		 4611 case INTEL_OUTPUT_DISPLAYPORT:
4612 is_dp = true;
4613 break;
32f9d658 4614 case INTEL_OUTPUT_EDP:
e3aef172
JB		 4615 is_dp = true;
4616 if (intel_encoder_is_pch_edp(&encoder->base))
4617 is_pch_edp = true;
4618 else
4619 is_cpu_edp = true;
4620 edp_encoder = encoder;
32f9d658 4621 break;
79e53945 4622 }
43565a06 4623
c751ce4f 4624 num_connectors++;
79e53945
JB		 4625 }
4626
d9d444cb 4627 refclk = ironlake_get_refclk(crtc);
79e53945 4628
d4906093
ML		 4629 /*
4630 * Returns a set of divisors for the desired target clock with the given
4631 * refclk, or FALSE. The returned values represent the clock equation:
4632 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4633 */
1b894b59 4634 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4635 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4636 &clock);
79e53945
JB		 4637 if (!ok) {
4638 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4639 return -EINVAL;
79e53945
JB		 4640 }
4641
cda4b7d3 4642 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4643 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4644
ddc9003c 4645 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4646 /*
4647 * Ensure we match the reduced clock's P to the target clock.
4648 * If the clocks don't match, we can't switch the display clock
4649 * by using the FP0/FP1. In such case we will disable the LVDS
4650 * downclock feature.
4651 */
ddc9003c 4652 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4653 dev_priv->lvds_downclock,
4654 refclk,
cec2f356 4655 &clock,
5eddb70b 4656 &reduced_clock);
652c393a 4657 }
61e9653f
DV		 4658
4659 if (is_sdvo && is_tv)
4660 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4661
7026d4ac 4662
2c07245f 4663 /* FDI link */
8febb297
EA		 4664 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4665 lane = 0;
4666 /* CPU eDP doesn't require FDI link, so just set DP M/N
4667 according to current link config */
e3aef172 4668 if (is_cpu_edp) {
e3aef172 4669 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 4670 } else {
8febb297
EA		 4671 /* FDI is a binary signal running at ~2.7GHz, encoding
4672 * each output octet as 10 bits. The actual frequency
4673 * is stored as a divider into a 100MHz clock, and the
4674 * mode pixel clock is stored in units of 1KHz.
4675 * Hence the bw of each lane in terms of the mode signal
4676 * is:
4677 */
4678 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4679 }
58a27471 4680
94bf2ced
DV		 4681 /* [e]DP over FDI requires target mode clock instead of link clock. */
4682 if (edp_encoder)
4683 target_clock = intel_edp_target_clock(edp_encoder, mode);
4684 else if (is_dp)
4685 target_clock = mode->clock;
4686 else
4687 target_clock = adjusted_mode->clock;
4688
8febb297
EA		 4689 /* determine panel color depth */
4690 temp = I915_READ(PIPECONF(pipe));
4691 temp &= ~PIPE_BPC_MASK;
3b5c78a3 4692 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 4693 switch (pipe_bpp) {
4694 case 18:
4695 temp |= PIPE_6BPC;
8febb297 4696 break;
5a354204
JB		 4697 case 24:
4698 temp |= PIPE_8BPC;
8febb297 4699 break;
5a354204
JB		 4700 case 30:
4701 temp |= PIPE_10BPC;
8febb297 4702 break;
5a354204
JB		 4703 case 36:
4704 temp |= PIPE_12BPC;
8febb297
EA		 4705 break;
4706 default:
62ac41a6
JB		 4707 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4708 pipe_bpp);
5a354204
JB		 4709 temp |= PIPE_8BPC;
4710 pipe_bpp = 24;
4711 break;
8febb297 4712 }
77ffb597 4713
5a354204
JB		 4714 intel_crtc->bpp = pipe_bpp;
4715 I915_WRITE(PIPECONF(pipe), temp);
4716
8febb297
EA		 4717 if (!lane) {
4718 /*
4719 * Account for spread spectrum to avoid
4720 * oversubscribing the link. Max center spread
4721 * is 2.5%; use 5% for safety's sake.
4722 */
5a354204 4723 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 4724 lane = bps / (link_bw * 8) + 1;
5eb08b69 4725 }
2c07245f 4726
8febb297
EA		 4727 intel_crtc->fdi_lanes = lane;
4728
4729 if (pixel_multiplier > 1)
4730 link_bw *= pixel_multiplier;
5a354204
JB		 4731 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4732 &m_n);
8febb297 4733
a07d6787
EA		 4734 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4735 if (has_reduced_clock)
4736 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4737 reduced_clock.m2;
79e53945 4738
c1858123 4739 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4740 factor = 21;
4741 if (is_lvds) {
4742 if ((intel_panel_use_ssc(dev_priv) &&
4743 dev_priv->lvds_ssc_freq == 100) ||
4744 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4745 factor = 25;
4746 } else if (is_sdvo && is_tv)
4747 factor = 20;
c1858123 4748
cb0e0931 4749 if (clock.m < factor * clock.n)
8febb297 4750 fp |= FP_CB_TUNE;
2c07245f 4751
5eddb70b 4752 dpll = 0;
2c07245f 4753
a07d6787
EA		 4754 if (is_lvds)
4755 dpll |= DPLLB_MODE_LVDS;
4756 else
4757 dpll |= DPLLB_MODE_DAC_SERIAL;
4758 if (is_sdvo) {
4759 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4760 if (pixel_multiplier > 1) {
4761 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4762 }
a07d6787
EA		 4763 dpll |= DPLL_DVO_HIGH_SPEED;
4764 }
e3aef172 4765 if (is_dp && !is_cpu_edp)
a07d6787 4766 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4767
a07d6787
EA		 4768 /* compute bitmask from p1 value */
4769 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4770 /* also FPA1 */
4771 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4772
4773 switch (clock.p2) {
4774 case 5:
4775 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4776 break;
4777 case 7:
4778 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4779 break;
4780 case 10:
4781 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4782 break;
4783 case 14:
4784 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4785 break;
79e53945
JB		 4786 }
4787
43565a06
KH		 4788 if (is_sdvo && is_tv)
4789 dpll |= PLL_REF_INPUT_TVCLKINBC;
4790 else if (is_tv)
79e53945 4791 /* XXX: just matching BIOS for now */
43565a06 4792 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4793 dpll |= 3;
a7615030 4794 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4795 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4796 else
4797 dpll |= PLL_REF_INPUT_DREFCLK;
4798
4799 /* setup pipeconf */
5eddb70b 4800 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4801
4802 /* Set up the display plane register */
4803 dspcntr = DISPPLANE_GAMMA_ENABLE;
4804
f7cb34d4 4805 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 4806 drm_mode_debug_printmodeline(mode);
4807
9d82aa17
ED		 4808 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4809 * pre-Haswell/LPT generation */
4810 if (HAS_PCH_LPT(dev)) {
4811 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4812 pipe);
4813 } else if (!is_cpu_edp) {
ee7b9f93 4814 struct intel_pch_pll *pll;
4b645f14 4815
ee7b9f93
JB		 4816 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4817 if (pll == NULL) {
4818 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4819 pipe);
4b645f14
JB		 4820 return -EINVAL;
4821 }
ee7b9f93
JB		 4822 } else
4823 intel_put_pch_pll(intel_crtc);
79e53945
JB		 4824
4825 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4826 * This is an exception to the general rule that mode_set doesn't turn
4827 * things on.
4828 */
4829 if (is_lvds) {
fae14981 4830 temp = I915_READ(PCH_LVDS);
5eddb70b 4831 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 4832 if (HAS_PCH_CPT(dev)) {
4833 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 4834 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 4835 } else {
4836 if (pipe == 1)
4837 temp |= LVDS_PIPEB_SELECT;
4838 else
4839 temp &= ~LVDS_PIPEB_SELECT;
4840 }
4b645f14 4841
a3e17eb8 4842 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4843 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4844 /* Set the B0-B3 data pairs corresponding to whether we're going to
4845 * set the DPLLs for dual-channel mode or not.
4846 */
4847 if (clock.p2 == 7)
5eddb70b 4848 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4849 else
5eddb70b 4850 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4851
4852 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4853 * appropriately here, but we need to look more thoroughly into how
4854 * panels behave in the two modes.
4855 */
284d5df5 4856 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 4857 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4858 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 4859 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4860 temp |= LVDS_VSYNC_POLARITY;
fae14981 4861 I915_WRITE(PCH_LVDS, temp);
79e53945 4862 }
434ed097 4863
8febb297
EA		 4864 pipeconf &= ~PIPECONF_DITHER_EN;
4865 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 4866 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 4867 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 4868 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 4869 }
e3aef172 4870 if (is_dp && !is_cpu_edp) {
a4fc5ed6 4871 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 4872 } else {
8db9d77b 4873 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 4874 I915_WRITE(TRANSDATA_M1(pipe), 0);
4875 I915_WRITE(TRANSDATA_N1(pipe), 0);
4876 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4877 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 4878 }
79e53945 4879
ee7b9f93
JB		 4880 if (intel_crtc->pch_pll) {
4881 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 4882
32f9d658 4883 /* Wait for the clocks to stabilize. */
ee7b9f93 4884 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 4885 udelay(150);
4886
8febb297
EA		 4887 /* The pixel multiplier can only be updated once the
4888 * DPLL is enabled and the clocks are stable.
4889 *
4890 * So write it again.
4891 */
ee7b9f93 4892 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 4893 }
79e53945 4894
5eddb70b 4895 intel_crtc->lowfreq_avail = false;
ee7b9f93 4896 if (intel_crtc->pch_pll) {
4b645f14 4897 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 4898 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 4899 intel_crtc->lowfreq_avail = true;
4b645f14 4900 } else {
ee7b9f93 4901 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 4902 }
4903 }
4904
617cf884 4905 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 4906 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 4907 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 4908 /* the chip adds 2 halflines automatically */
734b4157 4909 adjusted_mode->crtc_vtotal -= 1;
734b4157 4910 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4911 I915_WRITE(VSYNCSHIFT(pipe),
4912 adjusted_mode->crtc_hsync_start
4913 - adjusted_mode->crtc_htotal/2);
4914 } else {
617cf884 4915 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4916 I915_WRITE(VSYNCSHIFT(pipe), 0);
4917 }
734b4157 4918
5eddb70b
CW		 4919 I915_WRITE(HTOTAL(pipe),
4920 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4921 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4922 I915_WRITE(HBLANK(pipe),
4923 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4924 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4925 I915_WRITE(HSYNC(pipe),
4926 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4927 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4928
4929 I915_WRITE(VTOTAL(pipe),
4930 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4931 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4932 I915_WRITE(VBLANK(pipe),
4933 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4934 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4935 I915_WRITE(VSYNC(pipe),
4936 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4937 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 4938
8febb297
EA		 4939 /* pipesrc controls the size that is scaled from, which should
4940 * always be the user's requested size.
79e53945 4941 */
5eddb70b
CW		 4942 I915_WRITE(PIPESRC(pipe),
4943 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4944
8febb297
EA		 4945 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4946 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4947 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4948 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 4949
e3aef172 4950 if (is_cpu_edp)
8febb297 4951 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 4952
5eddb70b
CW		 4953 I915_WRITE(PIPECONF(pipe), pipeconf);
4954 POSTING_READ(PIPECONF(pipe));
79e53945 4955
9d0498a2 4956 intel_wait_for_vblank(dev, pipe);
79e53945 4957
5eddb70b 4958 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 4959 POSTING_READ(DSPCNTR(plane));
79e53945 4960
5c3b82e2 4961 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 4962
4963 intel_update_watermarks(dev);
4964
1f8eeabf
ED		 4965 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4966
1f803ee5 4967 return ret;
79e53945
JB		 4968}
4969
f564048e
EA		 4970static int intel_crtc_mode_set(struct drm_crtc *crtc,
4971 struct drm_display_mode *mode,
4972 struct drm_display_mode *adjusted_mode,
4973 int x, int y,
4974 struct drm_framebuffer *old_fb)
4975{
4976 struct drm_device *dev = crtc->dev;
4977 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 4978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4979 int pipe = intel_crtc->pipe;
f564048e
EA		 4980 int ret;
4981
0b701d27 4982 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 4983
f564048e
EA		 4984 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4985 x, y, old_fb);
79e53945 4986 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 4987
d8e70a25
JB		 4988 if (ret)
4989 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4990 else
4991 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 4992
1f803ee5 4993 return ret;
79e53945
JB		 4994}
4995
3a9627f4
WF		 4996static bool intel_eld_uptodate(struct drm_connector *connector,
4997 int reg_eldv, uint32_t bits_eldv,
4998 int reg_elda, uint32_t bits_elda,
4999 int reg_edid)
5000{
5001 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5002 uint8_t *eld = connector->eld;
5003 uint32_t i;
5004
5005 i = I915_READ(reg_eldv);
5006 i &= bits_eldv;
5007
5008 if (!eld[0])
5009 return !i;
5010
5011 if (!i)
5012 return false;
5013
5014 i = I915_READ(reg_elda);
5015 i &= ~bits_elda;
5016 I915_WRITE(reg_elda, i);
5017
5018 for (i = 0; i < eld[2]; i++)
5019 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5020 return false;
5021
5022 return true;
5023}
5024
e0dac65e
WF		 5025static void g4x_write_eld(struct drm_connector *connector,
5026 struct drm_crtc *crtc)
5027{
5028 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5029 uint8_t *eld = connector->eld;
5030 uint32_t eldv;
5031 uint32_t len;
5032 uint32_t i;
5033
5034 i = I915_READ(G4X_AUD_VID_DID);
5035
5036 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5037 eldv = G4X_ELDV_DEVCL_DEVBLC;
5038 else
5039 eldv = G4X_ELDV_DEVCTG;
5040
3a9627f4
WF		 5041 if (intel_eld_uptodate(connector,
5042 G4X_AUD_CNTL_ST, eldv,
5043 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5044 G4X_HDMIW_HDMIEDID))
5045 return;
5046
e0dac65e
WF		 5047 i = I915_READ(G4X_AUD_CNTL_ST);
5048 i &= ~(eldv | G4X_ELD_ADDR);
5049 len = (i >> 9) & 0x1f; /* ELD buffer size */
5050 I915_WRITE(G4X_AUD_CNTL_ST, i);
5051
5052 if (!eld[0])
5053 return;
5054
5055 len = min_t(uint8_t, eld[2], len);
5056 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5057 for (i = 0; i < len; i++)
5058 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5059
5060 i = I915_READ(G4X_AUD_CNTL_ST);
5061 i |= eldv;
5062 I915_WRITE(G4X_AUD_CNTL_ST, i);
5063}
5064
83358c85
WX		 5065static void haswell_write_eld(struct drm_connector *connector,
5066 struct drm_crtc *crtc)
5067{
5068 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5069 uint8_t *eld = connector->eld;
5070 struct drm_device *dev = crtc->dev;
5071 uint32_t eldv;
5072 uint32_t i;
5073 int len;
5074 int pipe = to_intel_crtc(crtc)->pipe;
5075 int tmp;
5076
5077 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5078 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5079 int aud_config = HSW_AUD_CFG(pipe);
5080 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5081
5082
5083 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5084
5085 /* Audio output enable */
5086 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5087 tmp = I915_READ(aud_cntrl_st2);
5088 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5089 I915_WRITE(aud_cntrl_st2, tmp);
5090
5091 /* Wait for 1 vertical blank */
5092 intel_wait_for_vblank(dev, pipe);
5093
5094 /* Set ELD valid state */
5095 tmp = I915_READ(aud_cntrl_st2);
5096 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5097 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5098 I915_WRITE(aud_cntrl_st2, tmp);
5099 tmp = I915_READ(aud_cntrl_st2);
5100 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5101
5102 /* Enable HDMI mode */
5103 tmp = I915_READ(aud_config);
5104 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5105 /* clear N_programing_enable and N_value_index */
5106 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5107 I915_WRITE(aud_config, tmp);
5108
5109 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5110
5111 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5112
5113 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5114 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5115 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5116 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5117 } else
5118 I915_WRITE(aud_config, 0);
5119
5120 if (intel_eld_uptodate(connector,
5121 aud_cntrl_st2, eldv,
5122 aud_cntl_st, IBX_ELD_ADDRESS,
5123 hdmiw_hdmiedid))
5124 return;
5125
5126 i = I915_READ(aud_cntrl_st2);
5127 i &= ~eldv;
5128 I915_WRITE(aud_cntrl_st2, i);
5129
5130 if (!eld[0])
5131 return;
5132
5133 i = I915_READ(aud_cntl_st);
5134 i &= ~IBX_ELD_ADDRESS;
5135 I915_WRITE(aud_cntl_st, i);
5136 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5137 DRM_DEBUG_DRIVER("port num:%d\n", i);
5138
5139 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5140 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5141 for (i = 0; i < len; i++)
5142 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5143
5144 i = I915_READ(aud_cntrl_st2);
5145 i |= eldv;
5146 I915_WRITE(aud_cntrl_st2, i);
5147
5148}
5149
e0dac65e
WF		 5150static void ironlake_write_eld(struct drm_connector *connector,
5151 struct drm_crtc *crtc)
5152{
5153 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5154 uint8_t *eld = connector->eld;
5155 uint32_t eldv;
5156 uint32_t i;
5157 int len;
5158 int hdmiw_hdmiedid;
b6daa025 5159 int aud_config;
e0dac65e
WF		 5160 int aud_cntl_st;
5161 int aud_cntrl_st2;
9b138a83 5162 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5163
b3f33cbf 5164 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5165 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5166 aud_config = IBX_AUD_CFG(pipe);
5167 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5168 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5169 } else {
9b138a83
WX		 5170 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5171 aud_config = CPT_AUD_CFG(pipe);
5172 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5173 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5174 }
5175
9b138a83 5176 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5177
5178 i = I915_READ(aud_cntl_st);
9b138a83 5179 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5180 if (!i) {
5181 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5182 /* operate blindly on all ports */
1202b4c6
WF		 5183 eldv = IBX_ELD_VALIDB;
5184 eldv |= IBX_ELD_VALIDB << 4;
5185 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5186 } else {
5187 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5188 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5189 }
5190
3a9627f4
WF		 5191 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5192 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5193 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5194 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5195 } else
5196 I915_WRITE(aud_config, 0);
e0dac65e 5197
3a9627f4
WF		 5198 if (intel_eld_uptodate(connector,
5199 aud_cntrl_st2, eldv,
5200 aud_cntl_st, IBX_ELD_ADDRESS,
5201 hdmiw_hdmiedid))
5202 return;
5203
e0dac65e
WF		 5204 i = I915_READ(aud_cntrl_st2);
5205 i &= ~eldv;
5206 I915_WRITE(aud_cntrl_st2, i);
5207
5208 if (!eld[0])
5209 return;
5210
e0dac65e 5211 i = I915_READ(aud_cntl_st);
1202b4c6 5212 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5213 I915_WRITE(aud_cntl_st, i);
5214
5215 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5216 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5217 for (i = 0; i < len; i++)
5218 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5219
5220 i = I915_READ(aud_cntrl_st2);
5221 i |= eldv;
5222 I915_WRITE(aud_cntrl_st2, i);
5223}
5224
5225void intel_write_eld(struct drm_encoder *encoder,
5226 struct drm_display_mode *mode)
5227{
5228 struct drm_crtc *crtc = encoder->crtc;
5229 struct drm_connector *connector;
5230 struct drm_device *dev = encoder->dev;
5231 struct drm_i915_private *dev_priv = dev->dev_private;
5232
5233 connector = drm_select_eld(encoder, mode);
5234 if (!connector)
5235 return;
5236
5237 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5238 connector->base.id,
5239 drm_get_connector_name(connector),
5240 connector->encoder->base.id,
5241 drm_get_encoder_name(connector->encoder));
5242
5243 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5244
5245 if (dev_priv->display.write_eld)
5246 dev_priv->display.write_eld(connector, crtc);
5247}
5248
79e53945
JB		 5249/** Loads the palette/gamma unit for the CRTC with the prepared values */
5250void intel_crtc_load_lut(struct drm_crtc *crtc)
5251{
5252 struct drm_device *dev = crtc->dev;
5253 struct drm_i915_private *dev_priv = dev->dev_private;
5254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5255 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5256 int i;
5257
5258 /* The clocks have to be on to load the palette. */
aed3f09d 5259 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5260 return;
5261
f2b115e6 5262 /* use legacy palette for Ironlake */
bad720ff 5263 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5264 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5265
79e53945
JB		 5266 for (i = 0; i < 256; i++) {
5267 I915_WRITE(palreg + 4 * i,
5268 (intel_crtc->lut_r[i] << 16) |
5269 (intel_crtc->lut_g[i] << 8) |
5270 intel_crtc->lut_b[i]);
5271 }
5272}
5273
560b85bb
CW		 5274static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5275{
5276 struct drm_device *dev = crtc->dev;
5277 struct drm_i915_private *dev_priv = dev->dev_private;
5278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5279 bool visible = base != 0;
5280 u32 cntl;
5281
5282 if (intel_crtc->cursor_visible == visible)
5283 return;
5284
9db4a9c7 5285 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5286 if (visible) {
5287 /* On these chipsets we can only modify the base whilst
5288 * the cursor is disabled.
5289 */
9db4a9c7 5290 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5291
5292 cntl &= ~(CURSOR_FORMAT_MASK);
5293 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5294 cntl |= CURSOR_ENABLE |
5295 CURSOR_GAMMA_ENABLE |
5296 CURSOR_FORMAT_ARGB;
5297 } else
5298 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5299 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5300
5301 intel_crtc->cursor_visible = visible;
5302}
5303
5304static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5305{
5306 struct drm_device *dev = crtc->dev;
5307 struct drm_i915_private *dev_priv = dev->dev_private;
5308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5309 int pipe = intel_crtc->pipe;
5310 bool visible = base != 0;
5311
5312 if (intel_crtc->cursor_visible != visible) {
548f245b 5313 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5314 if (base) {
5315 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5316 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5317 cntl |= pipe << 28; /* Connect to correct pipe */
5318 } else {
5319 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5320 cntl |= CURSOR_MODE_DISABLE;
5321 }
9db4a9c7 5322 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5323
5324 intel_crtc->cursor_visible = visible;
5325 }
5326 /* and commit changes on next vblank */
9db4a9c7 5327 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5328}
5329
65a21cd6
JB		 5330static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5331{
5332 struct drm_device *dev = crtc->dev;
5333 struct drm_i915_private *dev_priv = dev->dev_private;
5334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5335 int pipe = intel_crtc->pipe;
5336 bool visible = base != 0;
5337
5338 if (intel_crtc->cursor_visible != visible) {
5339 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5340 if (base) {
5341 cntl &= ~CURSOR_MODE;
5342 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5343 } else {
5344 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5345 cntl |= CURSOR_MODE_DISABLE;
5346 }
5347 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5348
5349 intel_crtc->cursor_visible = visible;
5350 }
5351 /* and commit changes on next vblank */
5352 I915_WRITE(CURBASE_IVB(pipe), base);
5353}
5354
cda4b7d3 5355/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5356static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5357 bool on)
cda4b7d3
CW		 5358{
5359 struct drm_device *dev = crtc->dev;
5360 struct drm_i915_private *dev_priv = dev->dev_private;
5361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5362 int pipe = intel_crtc->pipe;
5363 int x = intel_crtc->cursor_x;
5364 int y = intel_crtc->cursor_y;
560b85bb 5365 u32 base, pos;
cda4b7d3
CW		 5366 bool visible;
5367
5368 pos = 0;
5369
6b383a7f 5370 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5371 base = intel_crtc->cursor_addr;
5372 if (x > (int) crtc->fb->width)
5373 base = 0;
5374
5375 if (y > (int) crtc->fb->height)
5376 base = 0;
5377 } else
5378 base = 0;
5379
5380 if (x < 0) {
5381 if (x + intel_crtc->cursor_width < 0)
5382 base = 0;
5383
5384 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5385 x = -x;
5386 }
5387 pos |= x << CURSOR_X_SHIFT;
5388
5389 if (y < 0) {
5390 if (y + intel_crtc->cursor_height < 0)
5391 base = 0;
5392
5393 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5394 y = -y;
5395 }
5396 pos |= y << CURSOR_Y_SHIFT;
5397
5398 visible = base != 0;
560b85bb 5399 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5400 return;
5401
0cd83aa9 5402 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 5403 I915_WRITE(CURPOS_IVB(pipe), pos);
5404 ivb_update_cursor(crtc, base);
5405 } else {
5406 I915_WRITE(CURPOS(pipe), pos);
5407 if (IS_845G(dev) || IS_I865G(dev))
5408 i845_update_cursor(crtc, base);
5409 else
5410 i9xx_update_cursor(crtc, base);
5411 }
cda4b7d3
CW		 5412}
5413
79e53945 5414static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5415 struct drm_file *file,
79e53945
JB		 5416 uint32_t handle,
5417 uint32_t width, uint32_t height)
5418{
5419 struct drm_device *dev = crtc->dev;
5420 struct drm_i915_private *dev_priv = dev->dev_private;
5421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5422 struct drm_i915_gem_object *obj;
cda4b7d3 5423 uint32_t addr;
3f8bc370 5424 int ret;
79e53945 5425
28c97730 5426 DRM_DEBUG_KMS("\n");
79e53945
JB		 5427
5428 /* if we want to turn off the cursor ignore width and height */
5429 if (!handle) {
28c97730 5430 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5431 addr = 0;
05394f39 5432 obj = NULL;
5004417d 5433 mutex_lock(&dev->struct_mutex);
3f8bc370 5434 goto finish;
79e53945
JB		 5435 }
5436
5437 /* Currently we only support 64x64 cursors */
5438 if (width != 64 || height != 64) {
5439 DRM_ERROR("we currently only support 64x64 cursors\n");
5440 return -EINVAL;
5441 }
5442
05394f39 5443 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5444 if (&obj->base == NULL)
79e53945
JB		 5445 return -ENOENT;
5446
05394f39 5447 if (obj->base.size < width * height * 4) {
79e53945 5448 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5449 ret = -ENOMEM;
5450 goto fail;
79e53945
JB		 5451 }
5452
71acb5eb 5453 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5454 mutex_lock(&dev->struct_mutex);
b295d1b6 5455 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5456 if (obj->tiling_mode) {
5457 DRM_ERROR("cursor cannot be tiled\n");
5458 ret = -EINVAL;
5459 goto fail_locked;
5460 }
5461
2da3b9b9 5462 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5463 if (ret) {
5464 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5465 goto fail_locked;
e7b526bb
CW		 5466 }
5467
d9e86c0e
CW		 5468 ret = i915_gem_object_put_fence(obj);
5469 if (ret) {
2da3b9b9 5470 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5471 goto fail_unpin;
5472 }
5473
05394f39 5474 addr = obj->gtt_offset;
71acb5eb 5475 } else {
6eeefaf3 5476 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5477 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5478 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5479 align);
71acb5eb
DA		 5480 if (ret) {
5481 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5482 goto fail_locked;
71acb5eb 5483 }
05394f39 5484 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5485 }
5486
a6c45cf0 5487 if (IS_GEN2(dev))
14b60391
JB		 5488 I915_WRITE(CURSIZE, (height << 12) | width);
5489
3f8bc370 5490 finish:
3f8bc370 5491 if (intel_crtc->cursor_bo) {
b295d1b6 5492 if (dev_priv->info->cursor_needs_physical) {
05394f39 5493 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5494 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5495 } else
5496 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5497 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5498 }
80824003 5499
7f9872e0 5500 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5501
5502 intel_crtc->cursor_addr = addr;
05394f39 5503 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5504 intel_crtc->cursor_width = width;
5505 intel_crtc->cursor_height = height;
5506
6b383a7f 5507 intel_crtc_update_cursor(crtc, true);
3f8bc370 5508
79e53945 5509 return 0;
e7b526bb 5510fail_unpin:
05394f39 5511 i915_gem_object_unpin(obj);
7f9872e0 5512fail_locked:
34b8686e 5513 mutex_unlock(&dev->struct_mutex);
bc9025bd 5514fail:
05394f39 5515 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5516 return ret;
79e53945
JB		 5517}
5518
5519static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5520{
79e53945 5521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5522
cda4b7d3
CW		 5523 intel_crtc->cursor_x = x;
5524 intel_crtc->cursor_y = y;
652c393a 5525
6b383a7f 5526 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5527
5528 return 0;
5529}
5530
5531/** Sets the color ramps on behalf of RandR */
5532void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5533 u16 blue, int regno)
5534{
5535 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5536
5537 intel_crtc->lut_r[regno] = red >> 8;
5538 intel_crtc->lut_g[regno] = green >> 8;
5539 intel_crtc->lut_b[regno] = blue >> 8;
5540}
5541
b8c00ac5
DA		 5542void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5543 u16 *blue, int regno)
5544{
5545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5546
5547 *red = intel_crtc->lut_r[regno] << 8;
5548 *green = intel_crtc->lut_g[regno] << 8;
5549 *blue = intel_crtc->lut_b[regno] << 8;
5550}
5551
79e53945 5552static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5553 u16 *blue, uint32_t start, uint32_t size)
79e53945 5554{
7203425a 5555 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5557
7203425a 5558 for (i = start; i < end; i++) {
79e53945
JB		 5559 intel_crtc->lut_r[i] = red[i] >> 8;
5560 intel_crtc->lut_g[i] = green[i] >> 8;
5561 intel_crtc->lut_b[i] = blue[i] >> 8;
5562 }
5563
5564 intel_crtc_load_lut(crtc);
5565}
5566
5567/**
5568 * Get a pipe with a simple mode set on it for doing load-based monitor
5569 * detection.
5570 *
5571 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5572 * its requirements. The pipe will be connected to no other encoders.
79e53945 5573 *
c751ce4f 5574 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5575 * configured for it. In the future, it could choose to temporarily disable
5576 * some outputs to free up a pipe for its use.
5577 *
5578 * \return crtc, or NULL if no pipes are available.
5579 */
5580
5581/* VESA 640x480x72Hz mode to set on the pipe */
5582static struct drm_display_mode load_detect_mode = {
5583 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5584 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5585};
5586
d2dff872
CW		 5587static struct drm_framebuffer *
5588intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5589 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5590 struct drm_i915_gem_object *obj)
5591{
5592 struct intel_framebuffer *intel_fb;
5593 int ret;
5594
5595 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5596 if (!intel_fb) {
5597 drm_gem_object_unreference_unlocked(&obj->base);
5598 return ERR_PTR(-ENOMEM);
5599 }
5600
5601 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5602 if (ret) {
5603 drm_gem_object_unreference_unlocked(&obj->base);
5604 kfree(intel_fb);
5605 return ERR_PTR(ret);
5606 }
5607
5608 return &intel_fb->base;
5609}
5610
5611static u32
5612intel_framebuffer_pitch_for_width(int width, int bpp)
5613{
5614 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5615 return ALIGN(pitch, 64);
5616}
5617
5618static u32
5619intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5620{
5621 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5622 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5623}
5624
5625static struct drm_framebuffer *
5626intel_framebuffer_create_for_mode(struct drm_device *dev,
5627 struct drm_display_mode *mode,
5628 int depth, int bpp)
5629{
5630 struct drm_i915_gem_object *obj;
308e5bcb 5631 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5632
5633 obj = i915_gem_alloc_object(dev,
5634 intel_framebuffer_size_for_mode(mode, bpp));
5635 if (obj == NULL)
5636 return ERR_PTR(-ENOMEM);
5637
5638 mode_cmd.width = mode->hdisplay;
5639 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5640 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5641 bpp);
5ca0c34a 5642 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5643
5644 return intel_framebuffer_create(dev, &mode_cmd, obj);
5645}
5646
5647static struct drm_framebuffer *
5648mode_fits_in_fbdev(struct drm_device *dev,
5649 struct drm_display_mode *mode)
5650{
5651 struct drm_i915_private *dev_priv = dev->dev_private;
5652 struct drm_i915_gem_object *obj;
5653 struct drm_framebuffer *fb;
5654
5655 if (dev_priv->fbdev == NULL)
5656 return NULL;
5657
5658 obj = dev_priv->fbdev->ifb.obj;
5659 if (obj == NULL)
5660 return NULL;
5661
5662 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5663 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5664 fb->bits_per_pixel))
d2dff872
CW		 5665 return NULL;
5666
01f2c773 5667 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5668 return NULL;
5669
5670 return fb;
5671}
5672
d2434ab7 5673bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 5674 struct drm_display_mode *mode,
8261b191 5675 struct intel_load_detect_pipe *old)
79e53945
JB		 5676{
5677 struct intel_crtc *intel_crtc;
d2434ab7
DV		 5678 struct intel_encoder *intel_encoder =
5679 intel_attached_encoder(connector);
79e53945 5680 struct drm_crtc *possible_crtc;
4ef69c7a 5681 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5682 struct drm_crtc *crtc = NULL;
5683 struct drm_device *dev = encoder->dev;
d2dff872 5684 struct drm_framebuffer *old_fb;
79e53945
JB		 5685 int i = -1;
5686
d2dff872
CW		 5687 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5688 connector->base.id, drm_get_connector_name(connector),
5689 encoder->base.id, drm_get_encoder_name(encoder));
5690
79e53945
JB		 5691 /*
5692 * Algorithm gets a little messy:
7a5e4805 5693 *
79e53945
JB		 5694 * - if the connector already has an assigned crtc, use it (but make
5695 * sure it's on first)
7a5e4805 5696 *
79e53945
JB		 5697 * - try to find the first unused crtc that can drive this connector,
5698 * and use that if we find one
79e53945
JB		 5699 */
5700
5701 /* See if we already have a CRTC for this connector */
5702 if (encoder->crtc) {
5703 crtc = encoder->crtc;
8261b191 5704
24218aac 5705 old->dpms_mode = connector->dpms;
8261b191
CW		 5706 old->load_detect_temp = false;
5707
5708 /* Make sure the crtc and connector are running */
24218aac
DV		 5709 if (connector->dpms != DRM_MODE_DPMS_ON)
5710 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 5711
7173188d 5712 return true;
79e53945
JB		 5713 }
5714
5715 /* Find an unused one (if possible) */
5716 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5717 i++;
5718 if (!(encoder->possible_crtcs & (1 << i)))
5719 continue;
5720 if (!possible_crtc->enabled) {
5721 crtc = possible_crtc;
5722 break;
5723 }
79e53945
JB		 5724 }
5725
5726 /*
5727 * If we didn't find an unused CRTC, don't use any.
5728 */
5729 if (!crtc) {
7173188d
CW		 5730 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5731 return false;
79e53945
JB		 5732 }
5733
5734 encoder->crtc = crtc;
c1c43977 5735 connector->encoder = encoder;
79e53945
JB		 5736
5737 intel_crtc = to_intel_crtc(crtc);
24218aac 5738 old->dpms_mode = connector->dpms;
8261b191 5739 old->load_detect_temp = true;
d2dff872 5740 old->release_fb = NULL;
79e53945 5741
6492711d
CW		 5742 if (!mode)
5743 mode = &load_detect_mode;
79e53945 5744
d2dff872
CW		 5745 old_fb = crtc->fb;
5746
5747 /* We need a framebuffer large enough to accommodate all accesses
5748 * that the plane may generate whilst we perform load detection.
5749 * We can not rely on the fbcon either being present (we get called
5750 * during its initialisation to detect all boot displays, or it may
5751 * not even exist) or that it is large enough to satisfy the
5752 * requested mode.
5753 */
5754 crtc->fb = mode_fits_in_fbdev(dev, mode);
5755 if (crtc->fb == NULL) {
5756 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5757 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5758 old->release_fb = crtc->fb;
5759 } else
5760 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5761 if (IS_ERR(crtc->fb)) {
5762 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 5763 goto fail;
79e53945 5764 }
79e53945 5765
a6778b3c 5766 if (!intel_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5767 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5768 if (old->release_fb)
5769 old->release_fb->funcs->destroy(old->release_fb);
24218aac 5770 goto fail;
79e53945 5771 }
7173188d 5772
79e53945 5773 /* let the connector get through one full cycle before testing */
9d0498a2 5774 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5775
7173188d 5776 return true;
24218aac
DV		 5777fail:
5778 connector->encoder = NULL;
5779 encoder->crtc = NULL;
5780 crtc->fb = old_fb;
5781 return false;
79e53945
JB		 5782}
5783
d2434ab7 5784void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 5785 struct intel_load_detect_pipe *old)
79e53945 5786{
d2434ab7
DV		 5787 struct intel_encoder *intel_encoder =
5788 intel_attached_encoder(connector);
4ef69c7a 5789 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 5790 struct drm_device *dev = encoder->dev;
79e53945 5791
d2dff872
CW		 5792 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5793 connector->base.id, drm_get_connector_name(connector),
5794 encoder->base.id, drm_get_encoder_name(encoder));
5795
8261b191 5796 if (old->load_detect_temp) {
c1c43977 5797 connector->encoder = NULL;
24218aac 5798 encoder->crtc = NULL;
79e53945 5799 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5800
5801 if (old->release_fb)
5802 old->release_fb->funcs->destroy(old->release_fb);
5803
0622a53c 5804 return;
79e53945
JB		 5805 }
5806
c751ce4f 5807 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 5808 if (old->dpms_mode != DRM_MODE_DPMS_ON)
5809 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 5810}
5811
5812/* Returns the clock of the currently programmed mode of the given pipe. */
5813static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5814{
5815 struct drm_i915_private *dev_priv = dev->dev_private;
5816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5817 int pipe = intel_crtc->pipe;
548f245b 5818 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5819 u32 fp;
5820 intel_clock_t clock;
5821
5822 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5823 fp = I915_READ(FP0(pipe));
79e53945 5824 else
39adb7a5 5825 fp = I915_READ(FP1(pipe));
79e53945
JB		 5826
5827 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5828 if (IS_PINEVIEW(dev)) {
5829 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5830 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5831 } else {
5832 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5833 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5834 }
5835
a6c45cf0 5836 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5837 if (IS_PINEVIEW(dev))
5838 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5839 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5840 else
5841 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5842 DPLL_FPA01_P1_POST_DIV_SHIFT);
5843
5844 switch (dpll & DPLL_MODE_MASK) {
5845 case DPLLB_MODE_DAC_SERIAL:
5846 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5847 5 : 10;
5848 break;
5849 case DPLLB_MODE_LVDS:
5850 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5851 7 : 14;
5852 break;
5853 default:
28c97730 5854 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5855 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5856 return 0;
5857 }
5858
5859 /* XXX: Handle the 100Mhz refclk */
2177832f 5860 intel_clock(dev, 96000, &clock);
79e53945
JB		 5861 } else {
5862 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5863
5864 if (is_lvds) {
5865 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5866 DPLL_FPA01_P1_POST_DIV_SHIFT);
5867 clock.p2 = 14;
5868
5869 if ((dpll & PLL_REF_INPUT_MASK) ==
5870 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5871 /* XXX: might not be 66MHz */
2177832f 5872 intel_clock(dev, 66000, &clock);
79e53945 5873 } else
2177832f 5874 intel_clock(dev, 48000, &clock);
79e53945
JB		 5875 } else {
5876 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5877 clock.p1 = 2;
5878 else {
5879 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5880 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5881 }
5882 if (dpll & PLL_P2_DIVIDE_BY_4)
5883 clock.p2 = 4;
5884 else
5885 clock.p2 = 2;
5886
2177832f 5887 intel_clock(dev, 48000, &clock);
79e53945
JB		 5888 }
5889 }
5890
5891 /* XXX: It would be nice to validate the clocks, but we can't reuse
5892 * i830PllIsValid() because it relies on the xf86_config connector
5893 * configuration being accurate, which it isn't necessarily.
5894 */
5895
5896 return clock.dot;
5897}
5898
5899/** Returns the currently programmed mode of the given pipe. */
5900struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5901 struct drm_crtc *crtc)
5902{
548f245b 5903 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5905 int pipe = intel_crtc->pipe;
5906 struct drm_display_mode *mode;
548f245b
JB		 5907 int htot = I915_READ(HTOTAL(pipe));
5908 int hsync = I915_READ(HSYNC(pipe));
5909 int vtot = I915_READ(VTOTAL(pipe));
5910 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5911
5912 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5913 if (!mode)
5914 return NULL;
5915
5916 mode->clock = intel_crtc_clock_get(dev, crtc);
5917 mode->hdisplay = (htot & 0xffff) + 1;
5918 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5919 mode->hsync_start = (hsync & 0xffff) + 1;
5920 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5921 mode->vdisplay = (vtot & 0xffff) + 1;
5922 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5923 mode->vsync_start = (vsync & 0xffff) + 1;
5924 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5925
5926 drm_mode_set_name(mode);
79e53945
JB		 5927
5928 return mode;
5929}
5930
3dec0095 5931static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5932{
5933 struct drm_device *dev = crtc->dev;
5934 drm_i915_private_t *dev_priv = dev->dev_private;
5935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5936 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5937 int dpll_reg = DPLL(pipe);
5938 int dpll;
652c393a 5939
bad720ff 5940 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5941 return;
5942
5943 if (!dev_priv->lvds_downclock_avail)
5944 return;
5945
dbdc6479 5946 dpll = I915_READ(dpll_reg);
652c393a 5947 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 5948 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 5949
8ac5a6d5 5950 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 5951
5952 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5953 I915_WRITE(dpll_reg, dpll);
9d0498a2 5954 intel_wait_for_vblank(dev, pipe);
dbdc6479 5955
652c393a
JB		 5956 dpll = I915_READ(dpll_reg);
5957 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 5958 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 5959 }
652c393a
JB		 5960}
5961
5962static void intel_decrease_pllclock(struct drm_crtc *crtc)
5963{
5964 struct drm_device *dev = crtc->dev;
5965 drm_i915_private_t *dev_priv = dev->dev_private;
5966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 5967
bad720ff 5968 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5969 return;
5970
5971 if (!dev_priv->lvds_downclock_avail)
5972 return;
5973
5974 /*
5975 * Since this is called by a timer, we should never get here in
5976 * the manual case.
5977 */
5978 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 5979 int pipe = intel_crtc->pipe;
5980 int dpll_reg = DPLL(pipe);
5981 int dpll;
f6e5b160 5982
44d98a61 5983 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 5984
8ac5a6d5 5985 assert_panel_unlocked(dev_priv, pipe);
652c393a 5986
dc257cf1 5987 dpll = I915_READ(dpll_reg);
652c393a
JB		 5988 dpll |= DISPLAY_RATE_SELECT_FPA1;
5989 I915_WRITE(dpll_reg, dpll);
9d0498a2 5990 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 5991 dpll = I915_READ(dpll_reg);
5992 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 5993 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 5994 }
5995
5996}
5997
f047e395
CW		 5998void intel_mark_busy(struct drm_device *dev)
5999{
f047e395
CW		 6000 i915_update_gfx_val(dev->dev_private);
6001}
6002
6003void intel_mark_idle(struct drm_device *dev)
652c393a 6004{
f047e395
CW		 6005}
6006
6007void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6008{
6009 struct drm_device *dev = obj->base.dev;
652c393a 6010 struct drm_crtc *crtc;
652c393a
JB		 6011
6012 if (!i915_powersave)
6013 return;
6014
652c393a 6015 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6016 if (!crtc->fb)
6017 continue;
6018
f047e395
CW		 6019 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6020 intel_increase_pllclock(crtc);
652c393a 6021 }
652c393a
JB		 6022}
6023
f047e395 6024void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6025{
f047e395
CW		 6026 struct drm_device *dev = obj->base.dev;
6027 struct drm_crtc *crtc;
652c393a 6028
f047e395 6029 if (!i915_powersave)
acb87dfb
CW		 6030 return;
6031
652c393a
JB		 6032 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6033 if (!crtc->fb)
6034 continue;
6035
f047e395
CW		 6036 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6037 intel_decrease_pllclock(crtc);
652c393a
JB		 6038 }
6039}
6040
79e53945
JB		 6041static void intel_crtc_destroy(struct drm_crtc *crtc)
6042{
6043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6044 struct drm_device *dev = crtc->dev;
6045 struct intel_unpin_work *work;
6046 unsigned long flags;
6047
6048 spin_lock_irqsave(&dev->event_lock, flags);
6049 work = intel_crtc->unpin_work;
6050 intel_crtc->unpin_work = NULL;
6051 spin_unlock_irqrestore(&dev->event_lock, flags);
6052
6053 if (work) {
6054 cancel_work_sync(&work->work);
6055 kfree(work);
6056 }
79e53945
JB		 6057
6058 drm_crtc_cleanup(crtc);
67e77c5a 6059
79e53945
JB		 6060 kfree(intel_crtc);
6061}
6062
6b95a207
KH		 6063static void intel_unpin_work_fn(struct work_struct *__work)
6064{
6065 struct intel_unpin_work *work =
6066 container_of(__work, struct intel_unpin_work, work);
6067
6068 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6069 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6070 drm_gem_object_unreference(&work->pending_flip_obj->base);
6071 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6072
7782de3b 6073 intel_update_fbc(work->dev);
6b95a207
KH		 6074 mutex_unlock(&work->dev->struct_mutex);
6075 kfree(work);
6076}
6077
1afe3e9d 6078static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6079 struct drm_crtc *crtc)
6b95a207
KH		 6080{
6081 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6083 struct intel_unpin_work *work;
05394f39 6084 struct drm_i915_gem_object *obj;
6b95a207 6085 struct drm_pending_vblank_event *e;
49b14a5c 6086 struct timeval tnow, tvbl;
6b95a207
KH		 6087 unsigned long flags;
6088
6089 /* Ignore early vblank irqs */
6090 if (intel_crtc == NULL)
6091 return;
6092
49b14a5c
MK		 6093 do_gettimeofday(&tnow);
6094
6b95a207
KH		 6095 spin_lock_irqsave(&dev->event_lock, flags);
6096 work = intel_crtc->unpin_work;
6097 if (work == NULL || !work->pending) {
6098 spin_unlock_irqrestore(&dev->event_lock, flags);
6099 return;
6100 }
6101
6102 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6103
6104 if (work->event) {
6105 e = work->event;
49b14a5c 6106 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6107
6108 /* Called before vblank count and timestamps have
6109 * been updated for the vblank interval of flip
6110 * completion? Need to increment vblank count and
6111 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6112 * to account for this. We assume this happened if we
6113 * get called over 0.9 frame durations after the last
6114 * timestamped vblank.
6115 *
6116 * This calculation can not be used with vrefresh rates
6117 * below 5Hz (10Hz to be on the safe side) without
6118 * promoting to 64 integers.
0af7e4df 6119 */
49b14a5c
MK		 6120 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6121 9 * crtc->framedur_ns) {
0af7e4df 6122 e->event.sequence++;
49b14a5c
MK		 6123 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6124 crtc->framedur_ns);
0af7e4df
MK		 6125 }
6126
49b14a5c
MK		 6127 e->event.tv_sec = tvbl.tv_sec;
6128 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6129
6b95a207
KH		 6130 list_add_tail(&e->base.link,
6131 &e->base.file_priv->event_list);
6132 wake_up_interruptible(&e->base.file_priv->event_wait);
6133 }
6134
0af7e4df
MK		 6135 drm_vblank_put(dev, intel_crtc->pipe);
6136
6b95a207
KH		 6137 spin_unlock_irqrestore(&dev->event_lock, flags);
6138
05394f39 6139 obj = work->old_fb_obj;
d9e86c0e 6140
e59f2bac 6141 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6142 &obj->pending_flip.counter);
6143 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6144 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6145
6b95a207 6146 schedule_work(&work->work);
e5510fac
JB		 6147
6148 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6149}
6150
1afe3e9d
JB		 6151void intel_finish_page_flip(struct drm_device *dev, int pipe)
6152{
6153 drm_i915_private_t *dev_priv = dev->dev_private;
6154 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6155
49b14a5c 6156 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6157}
6158
6159void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6160{
6161 drm_i915_private_t *dev_priv = dev->dev_private;
6162 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6163
49b14a5c 6164 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6165}
6166
6b95a207
KH		 6167void intel_prepare_page_flip(struct drm_device *dev, int plane)
6168{
6169 drm_i915_private_t *dev_priv = dev->dev_private;
6170 struct intel_crtc *intel_crtc =
6171 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6172 unsigned long flags;
6173
6174 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6175 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6176 if ((++intel_crtc->unpin_work->pending) > 1)
6177 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6178 } else {
6179 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6180 }
6b95a207
KH		 6181 spin_unlock_irqrestore(&dev->event_lock, flags);
6182}
6183
8c9f3aaf
JB		 6184static int intel_gen2_queue_flip(struct drm_device *dev,
6185 struct drm_crtc *crtc,
6186 struct drm_framebuffer *fb,
6187 struct drm_i915_gem_object *obj)
6188{
6189 struct drm_i915_private *dev_priv = dev->dev_private;
6190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6191 u32 flip_mask;
6d90c952 6192 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6193 int ret;
6194
6d90c952 6195 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6196 if (ret)
83d4092b 6197 goto err;
8c9f3aaf 6198
6d90c952 6199 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6200 if (ret)
83d4092b 6201 goto err_unpin;
8c9f3aaf
JB		 6202
6203 /* Can't queue multiple flips, so wait for the previous
6204 * one to finish before executing the next.
6205 */
6206 if (intel_crtc->plane)
6207 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6208 else
6209 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6210 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6211 intel_ring_emit(ring, MI_NOOP);
6212 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6213 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6214 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6215 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6216 intel_ring_emit(ring, 0); /* aux display base address, unused */
6217 intel_ring_advance(ring);
83d4092b
CW		 6218 return 0;
6219
6220err_unpin:
6221 intel_unpin_fb_obj(obj);
6222err:
8c9f3aaf
JB		 6223 return ret;
6224}
6225
6226static int intel_gen3_queue_flip(struct drm_device *dev,
6227 struct drm_crtc *crtc,
6228 struct drm_framebuffer *fb,
6229 struct drm_i915_gem_object *obj)
6230{
6231 struct drm_i915_private *dev_priv = dev->dev_private;
6232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6233 u32 flip_mask;
6d90c952 6234 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6235 int ret;
6236
6d90c952 6237 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6238 if (ret)
83d4092b 6239 goto err;
8c9f3aaf 6240
6d90c952 6241 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6242 if (ret)
83d4092b 6243 goto err_unpin;
8c9f3aaf
JB		 6244
6245 if (intel_crtc->plane)
6246 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6247 else
6248 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6249 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6250 intel_ring_emit(ring, MI_NOOP);
6251 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6252 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6253 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6254 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6255 intel_ring_emit(ring, MI_NOOP);
6256
6257 intel_ring_advance(ring);
83d4092b
CW		 6258 return 0;
6259
6260err_unpin:
6261 intel_unpin_fb_obj(obj);
6262err:
8c9f3aaf
JB		 6263 return ret;
6264}
6265
6266static int intel_gen4_queue_flip(struct drm_device *dev,
6267 struct drm_crtc *crtc,
6268 struct drm_framebuffer *fb,
6269 struct drm_i915_gem_object *obj)
6270{
6271 struct drm_i915_private *dev_priv = dev->dev_private;
6272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6273 uint32_t pf, pipesrc;
6d90c952 6274 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6275 int ret;
6276
6d90c952 6277 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6278 if (ret)
83d4092b 6279 goto err;
8c9f3aaf 6280
6d90c952 6281 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6282 if (ret)
83d4092b 6283 goto err_unpin;
8c9f3aaf
JB		 6284
6285 /* i965+ uses the linear or tiled offsets from the
6286 * Display Registers (which do not change across a page-flip)
6287 * so we need only reprogram the base address.
6288 */
6d90c952
DV		 6289 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6290 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6291 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6292 intel_ring_emit(ring,
6293 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6294 obj->tiling_mode);
8c9f3aaf
JB		 6295
6296 /* XXX Enabling the panel-fitter across page-flip is so far
6297 * untested on non-native modes, so ignore it for now.
6298 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6299 */
6300 pf = 0;
6301 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6302 intel_ring_emit(ring, pf | pipesrc);
6303 intel_ring_advance(ring);
83d4092b
CW		 6304 return 0;
6305
6306err_unpin:
6307 intel_unpin_fb_obj(obj);
6308err:
8c9f3aaf
JB		 6309 return ret;
6310}
6311
6312static int intel_gen6_queue_flip(struct drm_device *dev,
6313 struct drm_crtc *crtc,
6314 struct drm_framebuffer *fb,
6315 struct drm_i915_gem_object *obj)
6316{
6317 struct drm_i915_private *dev_priv = dev->dev_private;
6318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6319 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6320 uint32_t pf, pipesrc;
6321 int ret;
6322
6d90c952 6323 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6324 if (ret)
83d4092b 6325 goto err;
8c9f3aaf 6326
6d90c952 6327 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6328 if (ret)
83d4092b 6329 goto err_unpin;
8c9f3aaf 6330
6d90c952
DV		 6331 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6332 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6333 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 6334 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 6335
dc257cf1
DV		 6336 /* Contrary to the suggestions in the documentation,
6337 * "Enable Panel Fitter" does not seem to be required when page
6338 * flipping with a non-native mode, and worse causes a normal
6339 * modeset to fail.
6340 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6341 */
6342 pf = 0;
8c9f3aaf 6343 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6344 intel_ring_emit(ring, pf | pipesrc);
6345 intel_ring_advance(ring);
83d4092b
CW		 6346 return 0;
6347
6348err_unpin:
6349 intel_unpin_fb_obj(obj);
6350err:
8c9f3aaf
JB		 6351 return ret;
6352}
6353
7c9017e5
JB		 6354/*
6355 * On gen7 we currently use the blit ring because (in early silicon at least)
6356 * the render ring doesn't give us interrpts for page flip completion, which
6357 * means clients will hang after the first flip is queued. Fortunately the
6358 * blit ring generates interrupts properly, so use it instead.
6359 */
6360static int intel_gen7_queue_flip(struct drm_device *dev,
6361 struct drm_crtc *crtc,
6362 struct drm_framebuffer *fb,
6363 struct drm_i915_gem_object *obj)
6364{
6365 struct drm_i915_private *dev_priv = dev->dev_private;
6366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6367 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 6368 uint32_t plane_bit = 0;
7c9017e5
JB		 6369 int ret;
6370
6371 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6372 if (ret)
83d4092b 6373 goto err;
7c9017e5 6374
cb05d8de
DV		 6375 switch(intel_crtc->plane) {
6376 case PLANE_A:
6377 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6378 break;
6379 case PLANE_B:
6380 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6381 break;
6382 case PLANE_C:
6383 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6384 break;
6385 default:
6386 WARN_ONCE(1, "unknown plane in flip command\n");
6387 ret = -ENODEV;
ab3951eb 6388 goto err_unpin;
cb05d8de
DV		 6389 }
6390
7c9017e5
JB		 6391 ret = intel_ring_begin(ring, 4);
6392 if (ret)
83d4092b 6393 goto err_unpin;
7c9017e5 6394
cb05d8de 6395 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 6396 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 6397 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 6398 intel_ring_emit(ring, (MI_NOOP));
6399 intel_ring_advance(ring);
83d4092b
CW		 6400 return 0;
6401
6402err_unpin:
6403 intel_unpin_fb_obj(obj);
6404err:
7c9017e5
JB		 6405 return ret;
6406}
6407
8c9f3aaf
JB		 6408static int intel_default_queue_flip(struct drm_device *dev,
6409 struct drm_crtc *crtc,
6410 struct drm_framebuffer *fb,
6411 struct drm_i915_gem_object *obj)
6412{
6413 return -ENODEV;
6414}
6415
6b95a207
KH		 6416static int intel_crtc_page_flip(struct drm_crtc *crtc,
6417 struct drm_framebuffer *fb,
6418 struct drm_pending_vblank_event *event)
6419{
6420 struct drm_device *dev = crtc->dev;
6421 struct drm_i915_private *dev_priv = dev->dev_private;
6422 struct intel_framebuffer *intel_fb;
05394f39 6423 struct drm_i915_gem_object *obj;
6b95a207
KH		 6424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6425 struct intel_unpin_work *work;
8c9f3aaf 6426 unsigned long flags;
52e68630 6427 int ret;
6b95a207 6428
e6a595d2
VS		 6429 /* Can't change pixel format via MI display flips. */
6430 if (fb->pixel_format != crtc->fb->pixel_format)
6431 return -EINVAL;
6432
6433 /*
6434 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6435 * Note that pitch changes could also affect these register.
6436 */
6437 if (INTEL_INFO(dev)->gen > 3 &&
6438 (fb->offsets[0] != crtc->fb->offsets[0] ||
6439 fb->pitches[0] != crtc->fb->pitches[0]))
6440 return -EINVAL;
6441
6b95a207
KH		 6442 work = kzalloc(sizeof *work, GFP_KERNEL);
6443 if (work == NULL)
6444 return -ENOMEM;
6445
6b95a207
KH		 6446 work->event = event;
6447 work->dev = crtc->dev;
6448 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6449 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6450 INIT_WORK(&work->work, intel_unpin_work_fn);
6451
7317c75e
JB		 6452 ret = drm_vblank_get(dev, intel_crtc->pipe);
6453 if (ret)
6454 goto free_work;
6455
6b95a207
KH		 6456 /* We borrow the event spin lock for protecting unpin_work */
6457 spin_lock_irqsave(&dev->event_lock, flags);
6458 if (intel_crtc->unpin_work) {
6459 spin_unlock_irqrestore(&dev->event_lock, flags);
6460 kfree(work);
7317c75e 6461 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6462
6463 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6464 return -EBUSY;
6465 }
6466 intel_crtc->unpin_work = work;
6467 spin_unlock_irqrestore(&dev->event_lock, flags);
6468
6469 intel_fb = to_intel_framebuffer(fb);
6470 obj = intel_fb->obj;
6471
79158103
CW		 6472 ret = i915_mutex_lock_interruptible(dev);
6473 if (ret)
6474 goto cleanup;
6b95a207 6475
75dfca80 6476 /* Reference the objects for the scheduled work. */
05394f39
CW		 6477 drm_gem_object_reference(&work->old_fb_obj->base);
6478 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6479
6480 crtc->fb = fb;
96b099fd 6481
e1f99ce6 6482 work->pending_flip_obj = obj;
e1f99ce6 6483
4e5359cd
SF		 6484 work->enable_stall_check = true;
6485
e1f99ce6
CW		 6486 /* Block clients from rendering to the new back buffer until
6487 * the flip occurs and the object is no longer visible.
6488 */
05394f39 6489 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6490
8c9f3aaf
JB		 6491 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6492 if (ret)
6493 goto cleanup_pending;
6b95a207 6494
7782de3b 6495 intel_disable_fbc(dev);
f047e395 6496 intel_mark_fb_busy(obj);
6b95a207
KH		 6497 mutex_unlock(&dev->struct_mutex);
6498
e5510fac
JB		 6499 trace_i915_flip_request(intel_crtc->plane, obj);
6500
6b95a207 6501 return 0;
96b099fd 6502
8c9f3aaf
JB		 6503cleanup_pending:
6504 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6505 drm_gem_object_unreference(&work->old_fb_obj->base);
6506 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6507 mutex_unlock(&dev->struct_mutex);
6508
79158103 6509cleanup:
96b099fd
CW		 6510 spin_lock_irqsave(&dev->event_lock, flags);
6511 intel_crtc->unpin_work = NULL;
6512 spin_unlock_irqrestore(&dev->event_lock, flags);
6513
7317c75e
JB		 6514 drm_vblank_put(dev, intel_crtc->pipe);
6515free_work:
96b099fd
CW		 6516 kfree(work);
6517
6518 return ret;
6b95a207
KH		 6519}
6520
47f1c6c9
CW		 6521static void intel_sanitize_modesetting(struct drm_device *dev,
6522 int pipe, int plane)
6523{
6524 struct drm_i915_private *dev_priv = dev->dev_private;
6525 u32 reg, val;
a9dcf84b 6526 int i;
47f1c6c9 6527
f47166d2 6528 /* Clear any frame start delays used for debugging left by the BIOS */
a9dcf84b
DV		 6529 for_each_pipe(i) {
6530 reg = PIPECONF(i);
f47166d2
CW		 6531 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6532 }
6533
47f1c6c9
CW		 6534 if (HAS_PCH_SPLIT(dev))
6535 return;
6536
6537 /* Who knows what state these registers were left in by the BIOS or
6538 * grub?
6539 *
6540 * If we leave the registers in a conflicting state (e.g. with the
6541 * display plane reading from the other pipe than the one we intend
6542 * to use) then when we attempt to teardown the active mode, we will
6543 * not disable the pipes and planes in the correct order -- leaving
6544 * a plane reading from a disabled pipe and possibly leading to
6545 * undefined behaviour.
6546 */
6547
6548 reg = DSPCNTR(plane);
6549 val = I915_READ(reg);
6550
6551 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6552 return;
6553 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6554 return;
6555
6556 /* This display plane is active and attached to the other CPU pipe. */
6557 pipe = !pipe;
6558
6559 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6560 intel_disable_plane(dev_priv, plane, pipe);
6561 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6562}
79e53945 6563
f6e5b160
CW		 6564static void intel_crtc_reset(struct drm_crtc *crtc)
6565{
6566 struct drm_device *dev = crtc->dev;
6567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6568
6569 /* Reset flags back to the 'unknown' status so that they
6570 * will be correctly set on the initial modeset.
6571 */
6572 intel_crtc->dpms_mode = -1;
6573
6574 /* We need to fix up any BIOS configuration that conflicts with
6575 * our expectations.
6576 */
6577 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6578}
6579
6580static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 6581 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6582 .load_lut = intel_crtc_load_lut,
6583 .disable = intel_crtc_disable,
6584};
6585
50f56119
DV		 6586static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6587 struct drm_crtc *crtc)
6588{
6589 struct drm_device *dev;
6590 struct drm_crtc *tmp;
6591 int crtc_mask = 1;
6592
6593 WARN(!crtc, "checking null crtc?\n");
6594
6595 dev = crtc->dev;
6596
6597 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6598 if (tmp == crtc)
6599 break;
6600 crtc_mask <<= 1;
6601 }
6602
6603 if (encoder->possible_crtcs & crtc_mask)
6604 return true;
6605 return false;
6606}
6607
6608static int
6609intel_crtc_helper_disable(struct drm_crtc *crtc)
6610{
6611 struct drm_device *dev = crtc->dev;
6612 struct drm_connector *connector;
6613 struct drm_encoder *encoder;
6614
6615 /* Decouple all encoders and their attached connectors from this crtc */
6616 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6617 if (encoder->crtc != crtc)
6618 continue;
6619
6620 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6621 if (connector->encoder != encoder)
6622 continue;
6623
6624 connector->encoder = NULL;
6625 }
6626 }
6627
6628 drm_helper_disable_unused_functions(dev);
6629 return 0;
6630}
6631
a6778b3c
DV		 6632static void
6633intel_crtc_prepare_encoders(struct drm_device *dev)
6634{
821112aa 6635 struct intel_encoder *encoder;
a6778b3c 6636
821112aa 6637 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
a6778b3c 6638 /* Disable unused encoders */
821112aa
DV		 6639 if (encoder->base.crtc == NULL)
6640 encoder->disable(encoder);
a6778b3c
DV		 6641 }
6642}
6643
6644bool intel_set_mode(struct drm_crtc *crtc,
6645 struct drm_display_mode *mode,
6646 int x, int y, struct drm_framebuffer *old_fb)
6647{
6648 struct drm_device *dev = crtc->dev;
dbf2b54e 6649 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 6650 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
a6778b3c
DV		 6651 struct drm_encoder_helper_funcs *encoder_funcs;
6652 int saved_x, saved_y;
6653 struct drm_encoder *encoder;
6654 bool ret = true;
6655
6656 crtc->enabled = drm_helper_crtc_in_use(crtc);
6657 if (!crtc->enabled)
6658 return true;
6659
6660 adjusted_mode = drm_mode_duplicate(dev, mode);
6661 if (!adjusted_mode)
6662 return false;
6663
6664 saved_hwmode = crtc->hwmode;
6665 saved_mode = crtc->mode;
6666 saved_x = crtc->x;
6667 saved_y = crtc->y;
6668
6669 /* Update crtc values up front so the driver can rely on them for mode
6670 * setting.
6671 */
6672 crtc->mode = *mode;
6673 crtc->x = x;
6674 crtc->y = y;
6675
6676 /* Pass our mode to the connectors and the CRTC to give them a chance to
6677 * adjust it according to limitations or connector properties, and also
6678 * a chance to reject the mode entirely.
6679 */
6680 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6681
6682 if (encoder->crtc != crtc)
6683 continue;
6684 encoder_funcs = encoder->helper_private;
6685 if (!(ret = encoder_funcs->mode_fixup(encoder, mode,
6686 adjusted_mode))) {
6687 DRM_DEBUG_KMS("Encoder fixup failed\n");
6688 goto done;
6689 }
6690 }
6691
dbf2b54e 6692 if (!(ret = intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
a6778b3c
DV		 6693 DRM_DEBUG_KMS("CRTC fixup failed\n");
6694 goto done;
6695 }
6696 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6697
a6778b3c
DV		 6698 intel_crtc_prepare_encoders(dev);
6699
dbf2b54e 6700 dev_priv->display.crtc_disable(crtc);
a6778b3c
DV		 6701
6702 /* Set up the DPLL and any encoders state that needs to adjust or depend
6703 * on the DPLL.
6704 */
dbf2b54e 6705 ret = !intel_crtc_mode_set(crtc, mode, adjusted_mode, x, y, old_fb);
a6778b3c
DV		 6706 if (!ret)
6707 goto done;
6708
6709 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6710
6711 if (encoder->crtc != crtc)
6712 continue;
6713
6714 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6715 encoder->base.id, drm_get_encoder_name(encoder),
6716 mode->base.id, mode->name);
6717 encoder_funcs = encoder->helper_private;
6718 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
6719 }
6720
6721 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
dbf2b54e 6722 dev_priv->display.crtc_enable(crtc);
a6778b3c 6723
a6778b3c
DV		 6724 /* Store real post-adjustment hardware mode. */
6725 crtc->hwmode = *adjusted_mode;
6726
6727 /* Calculate and store various constants which
6728 * are later needed by vblank and swap-completion
6729 * timestamping. They are derived from true hwmode.
6730 */
6731 drm_calc_timestamping_constants(crtc);
6732
6733 /* FIXME: add subpixel order */
6734done:
6735 drm_mode_destroy(dev, adjusted_mode);
6736 if (!ret) {
6737 crtc->hwmode = saved_hwmode;
6738 crtc->mode = saved_mode;
6739 crtc->x = saved_x;
6740 crtc->y = saved_y;
6741 }
6742
6743 return ret;
6744}
6745
50f56119
DV		 6746static int intel_crtc_set_config(struct drm_mode_set *set)
6747{
6748 struct drm_device *dev;
6749 struct drm_crtc *save_crtcs, *new_crtc, *crtc;
6750 struct drm_encoder *save_encoders, *new_encoder, *encoder;
6751 struct drm_framebuffer *old_fb = NULL;
6752 bool mode_changed = false; /* if true do a full mode set */
6753 bool fb_changed = false; /* if true and !mode_changed just do a flip */
6754 struct drm_connector *save_connectors, *connector;
6d832d18 6755 int count = 0, ro;
50f56119
DV		 6756 struct drm_mode_set save_set;
6757 int ret;
6758 int i;
6759
6760 DRM_DEBUG_KMS("\n");
6761
6762 if (!set)
6763 return -EINVAL;
6764
6765 if (!set->crtc)
6766 return -EINVAL;
6767
6768 if (!set->crtc->helper_private)
6769 return -EINVAL;
6770
50f56119
DV		 6771 if (!set->mode)
6772 set->fb = NULL;
6773
6774 if (set->fb) {
6775 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
6776 set->crtc->base.id, set->fb->base.id,
6777 (int)set->num_connectors, set->x, set->y);
6778 } else {
6779 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
6780 return intel_crtc_helper_disable(set->crtc);
6781 }
6782
6783 dev = set->crtc->dev;
6784
6785 /* Allocate space for the backup of all (non-pointer) crtc, encoder and
6786 * connector data. */
6787 save_crtcs = kzalloc(dev->mode_config.num_crtc *
6788 sizeof(struct drm_crtc), GFP_KERNEL);
6789 if (!save_crtcs)
6790 return -ENOMEM;
6791
6792 save_encoders = kzalloc(dev->mode_config.num_encoder *
6793 sizeof(struct drm_encoder), GFP_KERNEL);
6794 if (!save_encoders) {
6795 kfree(save_crtcs);
6796 return -ENOMEM;
6797 }
6798
6799 save_connectors = kzalloc(dev->mode_config.num_connector *
6800 sizeof(struct drm_connector), GFP_KERNEL);
6801 if (!save_connectors) {
6802 kfree(save_crtcs);
6803 kfree(save_encoders);
6804 return -ENOMEM;
6805 }
6806
6807 /* Copy data. Note that driver private data is not affected.
6808 * Should anything bad happen only the expected state is
6809 * restored, not the drivers personal bookkeeping.
6810 */
6811 count = 0;
6812 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6813 save_crtcs[count++] = *crtc;
6814 }
6815
6816 count = 0;
6817 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6818 save_encoders[count++] = *encoder;
6819 }
6820
6821 count = 0;
6822 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6823 save_connectors[count++] = *connector;
6824 }
6825
6826 save_set.crtc = set->crtc;
6827 save_set.mode = &set->crtc->mode;
6828 save_set.x = set->crtc->x;
6829 save_set.y = set->crtc->y;
6830 save_set.fb = set->crtc->fb;
6831
6832 /* We should be able to check here if the fb has the same properties
6833 * and then just flip_or_move it */
6834 if (set->crtc->fb != set->fb) {
6835 /* If we have no fb then treat it as a full mode set */
6836 if (set->crtc->fb == NULL) {
6837 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
6838 mode_changed = true;
6839 } else if (set->fb == NULL) {
6840 mode_changed = true;
6841 } else if (set->fb->depth != set->crtc->fb->depth) {
6842 mode_changed = true;
6843 } else if (set->fb->bits_per_pixel !=
6844 set->crtc->fb->bits_per_pixel) {
6845 mode_changed = true;
6846 } else
6847 fb_changed = true;
6848 }
6849
6850 if (set->x != set->crtc->x || set->y != set->crtc->y)
6851 fb_changed = true;
6852
6853 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
6854 DRM_DEBUG_KMS("modes are different, full mode set\n");
6855 drm_mode_debug_printmodeline(&set->crtc->mode);
6856 drm_mode_debug_printmodeline(set->mode);
6857 mode_changed = true;
6858 }
6859
6860 /* a) traverse passed in connector list and get encoders for them */
6861 count = 0;
6862 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
50f56119
DV		 6863 new_encoder = connector->encoder;
6864 for (ro = 0; ro < set->num_connectors; ro++) {
6865 if (set->connectors[ro] == connector) {
6d832d18
DV		 6866 new_encoder =
6867 &intel_attached_encoder(connector)->base;
50f56119
DV		 6868 break;
6869 }
6870 }
6871
6872 if (new_encoder != connector->encoder) {
6873 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
6874 mode_changed = true;
6875 /* If the encoder is reused for another connector, then
6876 * the appropriate crtc will be set later.
6877 */
6878 if (connector->encoder)
6879 connector->encoder->crtc = NULL;
6880 connector->encoder = new_encoder;
6881 }
6882 }
6883
50f56119
DV		 6884 count = 0;
6885 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6886 if (!connector->encoder)
6887 continue;
6888
6889 if (connector->encoder->crtc == set->crtc)
6890 new_crtc = NULL;
6891 else
6892 new_crtc = connector->encoder->crtc;
6893
6894 for (ro = 0; ro < set->num_connectors; ro++) {
6895 if (set->connectors[ro] == connector)
6896 new_crtc = set->crtc;
6897 }
6898
6899 /* Make sure the new CRTC will work with the encoder */
6900 if (new_crtc &&
6901 !intel_encoder_crtc_ok(connector->encoder, new_crtc)) {
6902 ret = -EINVAL;
6903 goto fail;
6904 }
6905 if (new_crtc != connector->encoder->crtc) {
6906 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
6907 mode_changed = true;
6908 connector->encoder->crtc = new_crtc;
6909 }
6910 if (new_crtc) {
6911 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
6912 connector->base.id, drm_get_connector_name(connector),
6913 new_crtc->base.id);
6914 } else {
6915 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
6916 connector->base.id, drm_get_connector_name(connector));
6917 }
6918 }
6919
50f56119
DV		 6920 if (mode_changed) {
6921 set->crtc->enabled = drm_helper_crtc_in_use(set->crtc);
6922 if (set->crtc->enabled) {
6923 DRM_DEBUG_KMS("attempting to set mode from"
6924 " userspace\n");
6925 drm_mode_debug_printmodeline(set->mode);
6926 old_fb = set->crtc->fb;
6927 set->crtc->fb = set->fb;
a6778b3c
DV		 6928 if (!intel_set_mode(set->crtc, set->mode,
6929 set->x, set->y, old_fb)) {
50f56119
DV		 6930 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
6931 set->crtc->base.id);
6932 set->crtc->fb = old_fb;
6933 ret = -EINVAL;
6934 goto fail;
6935 }
6936 DRM_DEBUG_KMS("Setting connector DPMS state to on\n");
6937 for (i = 0; i < set->num_connectors; i++) {
6938 DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id,
6939 drm_get_connector_name(set->connectors[i]));
6940 set->connectors[i]->funcs->dpms(set->connectors[i], DRM_MODE_DPMS_ON);
6941 }
6942 }
6943 drm_helper_disable_unused_functions(dev);
6944 } else if (fb_changed) {
6945 set->crtc->x = set->x;
6946 set->crtc->y = set->y;
6947
6948 old_fb = set->crtc->fb;
6949 if (set->crtc->fb != set->fb)
6950 set->crtc->fb = set->fb;
4f660f49
DV		 6951 ret = intel_pipe_set_base(set->crtc,
6952 set->x, set->y, old_fb);
50f56119
DV		 6953 if (ret != 0) {
6954 set->crtc->fb = old_fb;
6955 goto fail;
6956 }
6957 }
6958
6959 kfree(save_connectors);
6960 kfree(save_encoders);
6961 kfree(save_crtcs);
6962 return 0;
6963
6964fail:
6965 /* Restore all previous data. */
6966 count = 0;
6967 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6968 *crtc = save_crtcs[count++];
6969 }
6970
6971 count = 0;
6972 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6973 *encoder = save_encoders[count++];
6974 }
6975
6976 count = 0;
6977 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6978 *connector = save_connectors[count++];
6979 }
6980
6981 /* Try to restore the config */
6982 if (mode_changed &&
a6778b3c
DV		 6983 !intel_set_mode(save_set.crtc, save_set.mode,
6984 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 6985 DRM_ERROR("failed to restore config after modeset failure\n");
6986
6987 kfree(save_connectors);
6988 kfree(save_encoders);
6989 kfree(save_crtcs);
6990 return ret;
6991}
6992
f6e5b160
CW		 6993static const struct drm_crtc_funcs intel_crtc_funcs = {
6994 .reset = intel_crtc_reset,
6995 .cursor_set = intel_crtc_cursor_set,
6996 .cursor_move = intel_crtc_cursor_move,
6997 .gamma_set = intel_crtc_gamma_set,
50f56119 6998 .set_config = intel_crtc_set_config,
f6e5b160
CW		 6999 .destroy = intel_crtc_destroy,
7000 .page_flip = intel_crtc_page_flip,
7001};
7002
ee7b9f93
JB		 7003static void intel_pch_pll_init(struct drm_device *dev)
7004{
7005 drm_i915_private_t *dev_priv = dev->dev_private;
7006 int i;
7007
7008 if (dev_priv->num_pch_pll == 0) {
7009 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7010 return;
7011 }
7012
7013 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7014 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7015 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7016 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7017 }
7018}
7019
b358d0a6 7020static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7021{
22fd0fab 7022 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7023 struct intel_crtc *intel_crtc;
7024 int i;
7025
7026 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7027 if (intel_crtc == NULL)
7028 return;
7029
7030 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7031
7032 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7033 for (i = 0; i < 256; i++) {
7034 intel_crtc->lut_r[i] = i;
7035 intel_crtc->lut_g[i] = i;
7036 intel_crtc->lut_b[i] = i;
7037 }
7038
80824003
JB		 7039 /* Swap pipes & planes for FBC on pre-965 */
7040 intel_crtc->pipe = pipe;
7041 intel_crtc->plane = pipe;
e2e767ab 7042 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7043 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7044 intel_crtc->plane = !pipe;
80824003
JB		 7045 }
7046
22fd0fab
JB		 7047 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7048 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7049 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7050 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7051
5d1d0cc8 7052 intel_crtc_reset(&intel_crtc->base);
04dbff52 7053 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 7054 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 7055
79e53945 7056 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 7057}
7058
08d7b3d1 7059int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7060 struct drm_file *file)
08d7b3d1 7061{
08d7b3d1 7062 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7063 struct drm_mode_object *drmmode_obj;
7064 struct intel_crtc *crtc;
08d7b3d1 7065
1cff8f6b
DV		 7066 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7067 return -ENODEV;
08d7b3d1 7068
c05422d5
DV		 7069 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7070 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7071
c05422d5 7072 if (!drmmode_obj) {
08d7b3d1
CW		 7073 DRM_ERROR("no such CRTC id\n");
7074 return -EINVAL;
7075 }
7076
c05422d5
DV		 7077 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7078 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7079
c05422d5 7080 return 0;
08d7b3d1
CW		 7081}
7082
66a9278e 7083static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 7084{
66a9278e
DV		 7085 struct drm_device *dev = encoder->base.dev;
7086 struct intel_encoder *source_encoder;
79e53945 7087 int index_mask = 0;
79e53945
JB		 7088 int entry = 0;
7089
66a9278e
DV		 7090 list_for_each_entry(source_encoder,
7091 &dev->mode_config.encoder_list, base.head) {
7092
7093 if (encoder == source_encoder)
79e53945 7094 index_mask |= (1 << entry);
66a9278e
DV		 7095
7096 /* Intel hw has only one MUX where enocoders could be cloned. */
7097 if (encoder->cloneable && source_encoder->cloneable)
7098 index_mask |= (1 << entry);
7099
79e53945
JB		 7100 entry++;
7101 }
4ef69c7a 7102
79e53945
JB		 7103 return index_mask;
7104}
7105
4d302442
CW		 7106static bool has_edp_a(struct drm_device *dev)
7107{
7108 struct drm_i915_private *dev_priv = dev->dev_private;
7109
7110 if (!IS_MOBILE(dev))
7111 return false;
7112
7113 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7114 return false;
7115
7116 if (IS_GEN5(dev) &&
7117 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7118 return false;
7119
7120 return true;
7121}
7122
79e53945
JB		 7123static void intel_setup_outputs(struct drm_device *dev)
7124{
725e30ad 7125 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7126 struct intel_encoder *encoder;
cb0953d7 7127 bool dpd_is_edp = false;
f3cfcba6 7128 bool has_lvds;
79e53945 7129
f3cfcba6 7130 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 7131 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7132 /* disable the panel fitter on everything but LVDS */
7133 I915_WRITE(PFIT_CONTROL, 0);
7134 }
79e53945 7135
bad720ff 7136 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7137 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7138
4d302442 7139 if (has_edp_a(dev))
ab9d7c30 7140 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 7141
cb0953d7 7142 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 7143 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 7144 }
7145
7146 intel_crt_init(dev);
7147
0e72a5b5
ED		 7148 if (IS_HASWELL(dev)) {
7149 int found;
7150
7151 /* Haswell uses DDI functions to detect digital outputs */
7152 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7153 /* DDI A only supports eDP */
7154 if (found)
7155 intel_ddi_init(dev, PORT_A);
7156
7157 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7158 * register */
7159 found = I915_READ(SFUSE_STRAP);
7160
7161 if (found & SFUSE_STRAP_DDIB_DETECTED)
7162 intel_ddi_init(dev, PORT_B);
7163 if (found & SFUSE_STRAP_DDIC_DETECTED)
7164 intel_ddi_init(dev, PORT_C);
7165 if (found & SFUSE_STRAP_DDID_DETECTED)
7166 intel_ddi_init(dev, PORT_D);
7167 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 7168 int found;
7169
30ad48b7 7170 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 7171 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 7172 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 7173 if (!found)
08d644ad 7174 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 7175 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 7176 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 7177 }
7178
7179 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 7180 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 7181
b708a1d5 7182 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 7183 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 7184
5eb08b69 7185 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 7186 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 7187
cb0953d7 7188 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 7189 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 7190 } else if (IS_VALLEYVIEW(dev)) {
7191 int found;
7192
7193 if (I915_READ(SDVOB) & PORT_DETECTED) {
7194 /* SDVOB multiplex with HDMIB */
7195 found = intel_sdvo_init(dev, SDVOB, true);
7196 if (!found)
08d644ad 7197 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 7198 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 7199 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 7200 }
7201
7202 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 7203 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 7204
4a87d65d
JB		 7205 /* Shares lanes with HDMI on SDVOC */
7206 if (I915_READ(DP_C) & DP_DETECTED)
ab9d7c30 7207 intel_dp_init(dev, DP_C, PORT_C);
103a196f 7208 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7209 bool found = false;
7d57382e 7210
725e30ad 7211 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7212 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 7213 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 7214 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7215 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 7216 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 7217 }
27185ae1 7218
b01f2c3a
JB		 7219 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7220 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 7221 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 7222 }
725e30ad 7223 }
13520b05
KH		 7224
7225 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7226
b01f2c3a
JB		 7227 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7228 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 7229 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 7230 }
27185ae1
ML		 7231
7232 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7233
b01f2c3a
JB		 7234 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7235 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 7236 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 7237 }
7238 if (SUPPORTS_INTEGRATED_DP(dev)) {
7239 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 7240 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 7241 }
725e30ad 7242 }
27185ae1 7243
b01f2c3a
JB		 7244 if (SUPPORTS_INTEGRATED_DP(dev) &&
7245 (I915_READ(DP_D) & DP_DETECTED)) {
7246 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 7247 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 7248 }
bad720ff 7249 } else if (IS_GEN2(dev))
79e53945
JB		 7250 intel_dvo_init(dev);
7251
103a196f 7252 if (SUPPORTS_TV(dev))
79e53945
JB		 7253 intel_tv_init(dev);
7254
4ef69c7a
CW		 7255 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7256 encoder->base.possible_crtcs = encoder->crtc_mask;
7257 encoder->base.possible_clones =
66a9278e 7258 intel_encoder_clones(encoder);
79e53945 7259 }
47356eb6 7260
2c7111db
CW		 7261 /* disable all the possible outputs/crtcs before entering KMS mode */
7262 drm_helper_disable_unused_functions(dev);
9fb526db 7263
40579abe 7264 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 7265 ironlake_init_pch_refclk(dev);
79e53945
JB		 7266}
7267
7268static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7269{
7270 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7271
7272 drm_framebuffer_cleanup(fb);
05394f39 7273 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7274
7275 kfree(intel_fb);
7276}
7277
7278static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7279 struct drm_file *file,
79e53945
JB		 7280 unsigned int *handle)
7281{
7282 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7283 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7284
05394f39 7285 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7286}
7287
7288static const struct drm_framebuffer_funcs intel_fb_funcs = {
7289 .destroy = intel_user_framebuffer_destroy,
7290 .create_handle = intel_user_framebuffer_create_handle,
7291};
7292
38651674
DA		 7293int intel_framebuffer_init(struct drm_device *dev,
7294 struct intel_framebuffer *intel_fb,
308e5bcb 7295 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 7296 struct drm_i915_gem_object *obj)
79e53945 7297{
79e53945
JB		 7298 int ret;
7299
05394f39 7300 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7301 return -EINVAL;
7302
308e5bcb 7303 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 7304 return -EINVAL;
7305
308e5bcb 7306 switch (mode_cmd->pixel_format) {
04b3924d
VS		 7307 case DRM_FORMAT_RGB332:
7308 case DRM_FORMAT_RGB565:
7309 case DRM_FORMAT_XRGB8888:
b250da79 7310 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 7311 case DRM_FORMAT_ARGB8888:
7312 case DRM_FORMAT_XRGB2101010:
7313 case DRM_FORMAT_ARGB2101010:
308e5bcb 7314 /* RGB formats are common across chipsets */
b5626747 7315 break;
04b3924d
VS		 7316 case DRM_FORMAT_YUYV:
7317 case DRM_FORMAT_UYVY:
7318 case DRM_FORMAT_YVYU:
7319 case DRM_FORMAT_VYUY:
57cd6508
CW		 7320 break;
7321 default:
aca25848
ED		 7322 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7323 mode_cmd->pixel_format);
57cd6508
CW		 7324 return -EINVAL;
7325 }
7326
79e53945
JB		 7327 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7328 if (ret) {
7329 DRM_ERROR("framebuffer init failed %d\n", ret);
7330 return ret;
7331 }
7332
7333 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7334 intel_fb->obj = obj;
79e53945
JB		 7335 return 0;
7336}
7337
79e53945
JB		 7338static struct drm_framebuffer *
7339intel_user_framebuffer_create(struct drm_device *dev,
7340 struct drm_file *filp,
308e5bcb 7341 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 7342{
05394f39 7343 struct drm_i915_gem_object *obj;
79e53945 7344
308e5bcb
JB		 7345 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7346 mode_cmd->handles[0]));
c8725226 7347 if (&obj->base == NULL)
cce13ff7 7348 return ERR_PTR(-ENOENT);
79e53945 7349
d2dff872 7350 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7351}
7352
79e53945 7353static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7354 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7355 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7356};
7357
e70236a8
JB		 7358/* Set up chip specific display functions */
7359static void intel_init_display(struct drm_device *dev)
7360{
7361 struct drm_i915_private *dev_priv = dev->dev_private;
7362
7363 /* We always want a DPMS function */
f564048e 7364 if (HAS_PCH_SPLIT(dev)) {
f564048e 7365 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 7366 dev_priv->display.crtc_enable = ironlake_crtc_enable;
7367 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 7368 dev_priv->display.off = ironlake_crtc_off;
17638cd6 7369 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 7370 } else {
f564048e 7371 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 7372 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7373 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 7374 dev_priv->display.off = i9xx_crtc_off;
17638cd6 7375 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 7376 }
e70236a8 7377
e70236a8 7378 /* Returns the core display clock speed */
25eb05fc
JB		 7379 if (IS_VALLEYVIEW(dev))
7380 dev_priv->display.get_display_clock_speed =
7381 valleyview_get_display_clock_speed;
7382 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 7383 dev_priv->display.get_display_clock_speed =
7384 i945_get_display_clock_speed;
7385 else if (IS_I915G(dev))
7386 dev_priv->display.get_display_clock_speed =
7387 i915_get_display_clock_speed;
f2b115e6 7388 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7389 dev_priv->display.get_display_clock_speed =
7390 i9xx_misc_get_display_clock_speed;
7391 else if (IS_I915GM(dev))
7392 dev_priv->display.get_display_clock_speed =
7393 i915gm_get_display_clock_speed;
7394 else if (IS_I865G(dev))
7395 dev_priv->display.get_display_clock_speed =
7396 i865_get_display_clock_speed;
f0f8a9ce 7397 else if (IS_I85X(dev))
e70236a8
JB		 7398 dev_priv->display.get_display_clock_speed =
7399 i855_get_display_clock_speed;
7400 else /* 852, 830 */
7401 dev_priv->display.get_display_clock_speed =
7402 i830_get_display_clock_speed;
7403
7f8a8569 7404 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 7405 if (IS_GEN5(dev)) {
674cf967 7406 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 7407 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 7408 } else if (IS_GEN6(dev)) {
674cf967 7409 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 7410 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 7411 } else if (IS_IVYBRIDGE(dev)) {
7412 /* FIXME: detect B0+ stepping and use auto training */
7413 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 7414 dev_priv->display.write_eld = ironlake_write_eld;
c82e4d26
ED		 7415 } else if (IS_HASWELL(dev)) {
7416 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 7417 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 7418 } else
7419 dev_priv->display.update_wm = NULL;
6067aaea 7420 } else if (IS_G4X(dev)) {
e0dac65e 7421 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 7422 }
8c9f3aaf
JB		 7423
7424 /* Default just returns -ENODEV to indicate unsupported */
7425 dev_priv->display.queue_flip = intel_default_queue_flip;
7426
7427 switch (INTEL_INFO(dev)->gen) {
7428 case 2:
7429 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7430 break;
7431
7432 case 3:
7433 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7434 break;
7435
7436 case 4:
7437 case 5:
7438 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7439 break;
7440
7441 case 6:
7442 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7443 break;
7c9017e5
JB		 7444 case 7:
7445 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7446 break;
8c9f3aaf 7447 }
e70236a8
JB		 7448}
7449
b690e96c
JB		 7450/*
7451 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7452 * resume, or other times. This quirk makes sure that's the case for
7453 * affected systems.
7454 */
0206e353 7455static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 7456{
7457 struct drm_i915_private *dev_priv = dev->dev_private;
7458
7459 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 7460 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 7461}
7462
435793df
KP		 7463/*
7464 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7465 */
7466static void quirk_ssc_force_disable(struct drm_device *dev)
7467{
7468 struct drm_i915_private *dev_priv = dev->dev_private;
7469 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 7470 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 7471}
7472
4dca20ef 7473/*
5a15ab5b
CE		 7474 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7475 * brightness value
4dca20ef
CE		 7476 */
7477static void quirk_invert_brightness(struct drm_device *dev)
7478{
7479 struct drm_i915_private *dev_priv = dev->dev_private;
7480 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 7481 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 7482}
7483
b690e96c
JB		 7484struct intel_quirk {
7485 int device;
7486 int subsystem_vendor;
7487 int subsystem_device;
7488 void (*hook)(struct drm_device *dev);
7489};
7490
c43b5634 7491static struct intel_quirk intel_quirks[] = {
b690e96c 7492 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 7493 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 7494
b690e96c
JB		 7495 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7496 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7497
b690e96c
JB		 7498 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7499 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7500
7501 /* 855 & before need to leave pipe A & dpll A up */
7502 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7503 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 7504 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 7505
7506 /* Lenovo U160 cannot use SSC on LVDS */
7507 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 7508
7509 /* Sony Vaio Y cannot use SSC on LVDS */
7510 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 7511
7512 /* Acer Aspire 5734Z must invert backlight brightness */
7513 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 7514};
7515
7516static void intel_init_quirks(struct drm_device *dev)
7517{
7518 struct pci_dev *d = dev->pdev;
7519 int i;
7520
7521 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7522 struct intel_quirk *q = &intel_quirks[i];
7523
7524 if (d->device == q->device &&
7525 (d->subsystem_vendor == q->subsystem_vendor ||
7526 q->subsystem_vendor == PCI_ANY_ID) &&
7527 (d->subsystem_device == q->subsystem_device ||
7528 q->subsystem_device == PCI_ANY_ID))
7529 q->hook(dev);
7530 }
7531}
7532
9cce37f4
JB		 7533/* Disable the VGA plane that we never use */
7534static void i915_disable_vga(struct drm_device *dev)
7535{
7536 struct drm_i915_private *dev_priv = dev->dev_private;
7537 u8 sr1;
7538 u32 vga_reg;
7539
7540 if (HAS_PCH_SPLIT(dev))
7541 vga_reg = CPU_VGACNTRL;
7542 else
7543 vga_reg = VGACNTRL;
7544
7545 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 7546 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 7547 sr1 = inb(VGA_SR_DATA);
7548 outb(sr1 | 1<<5, VGA_SR_DATA);
7549 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7550 udelay(300);
7551
7552 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7553 POSTING_READ(vga_reg);
7554}
7555
f817586c
DV		 7556void intel_modeset_init_hw(struct drm_device *dev)
7557{
0232e927
ED		 7558 /* We attempt to init the necessary power wells early in the initialization
7559 * time, so the subsystems that expect power to be enabled can work.
7560 */
7561 intel_init_power_wells(dev);
7562
a8f78b58
ED		 7563 intel_prepare_ddi(dev);
7564
f817586c
DV		 7565 intel_init_clock_gating(dev);
7566
79f5b2c7 7567 mutex_lock(&dev->struct_mutex);
8090c6b9 7568 intel_enable_gt_powersave(dev);
79f5b2c7 7569 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 7570}
7571
79e53945
JB		 7572void intel_modeset_init(struct drm_device *dev)
7573{
652c393a 7574 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 7575 int i, ret;
79e53945
JB		 7576
7577 drm_mode_config_init(dev);
7578
7579 dev->mode_config.min_width = 0;
7580 dev->mode_config.min_height = 0;
7581
019d96cb
DA		 7582 dev->mode_config.preferred_depth = 24;
7583 dev->mode_config.prefer_shadow = 1;
7584
e6ecefaa 7585 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 7586
b690e96c
JB		 7587 intel_init_quirks(dev);
7588
1fa61106
ED		 7589 intel_init_pm(dev);
7590
e70236a8
JB		 7591 intel_init_display(dev);
7592
a6c45cf0
CW		 7593 if (IS_GEN2(dev)) {
7594 dev->mode_config.max_width = 2048;
7595 dev->mode_config.max_height = 2048;
7596 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 7597 dev->mode_config.max_width = 4096;
7598 dev->mode_config.max_height = 4096;
79e53945 7599 } else {
a6c45cf0
CW		 7600 dev->mode_config.max_width = 8192;
7601 dev->mode_config.max_height = 8192;
79e53945 7602 }
dd2757f8 7603 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 7604
28c97730 7605 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 7606 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 7607
a3524f1b 7608 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 7609 intel_crtc_init(dev, i);
00c2064b
JB		 7610 ret = intel_plane_init(dev, i);
7611 if (ret)
7612 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 7613 }
7614
ee7b9f93
JB		 7615 intel_pch_pll_init(dev);
7616
9cce37f4
JB		 7617 /* Just disable it once at startup */
7618 i915_disable_vga(dev);
79e53945 7619 intel_setup_outputs(dev);
2c7111db
CW		 7620}
7621
7622void intel_modeset_gem_init(struct drm_device *dev)
7623{
1833b134 7624 intel_modeset_init_hw(dev);
02e792fb
DV		 7625
7626 intel_setup_overlay(dev);
79e53945
JB		 7627}
7628
7629void intel_modeset_cleanup(struct drm_device *dev)
7630{
652c393a
JB		 7631 struct drm_i915_private *dev_priv = dev->dev_private;
7632 struct drm_crtc *crtc;
7633 struct intel_crtc *intel_crtc;
7634
f87ea761 7635 drm_kms_helper_poll_fini(dev);
652c393a
JB		 7636 mutex_lock(&dev->struct_mutex);
7637
723bfd70
JB		 7638 intel_unregister_dsm_handler();
7639
7640
652c393a
JB		 7641 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7642 /* Skip inactive CRTCs */
7643 if (!crtc->fb)
7644 continue;
7645
7646 intel_crtc = to_intel_crtc(crtc);
3dec0095 7647 intel_increase_pllclock(crtc);
652c393a
JB		 7648 }
7649
973d04f9 7650 intel_disable_fbc(dev);
e70236a8 7651
8090c6b9 7652 intel_disable_gt_powersave(dev);
0cdab21f 7653
930ebb46
DV		 7654 ironlake_teardown_rc6(dev);
7655
57f350b6
JB		 7656 if (IS_VALLEYVIEW(dev))
7657 vlv_init_dpio(dev);
7658
69341a5e
KH		 7659 mutex_unlock(&dev->struct_mutex);
7660
6c0d9350
DV		 7661 /* Disable the irq before mode object teardown, for the irq might
7662 * enqueue unpin/hotplug work. */
7663 drm_irq_uninstall(dev);
7664 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 7665 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 7666
1630fe75
CW		 7667 /* flush any delayed tasks or pending work */
7668 flush_scheduled_work();
7669
79e53945
JB		 7670 drm_mode_config_cleanup(dev);
7671}
7672
f1c79df3
ZW		 7673/*
7674 * Return which encoder is currently attached for connector.
7675 */
df0e9248 7676struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 7677{
df0e9248
CW		 7678 return &intel_attached_encoder(connector)->base;
7679}
f1c79df3 7680
df0e9248
CW		 7681void intel_connector_attach_encoder(struct intel_connector *connector,
7682 struct intel_encoder *encoder)
7683{
7684 connector->encoder = encoder;
7685 drm_mode_connector_attach_encoder(&connector->base,
7686 &encoder->base);
79e53945 7687}
28d52043
DA		 7688
7689/*
7690 * set vga decode state - true == enable VGA decode
7691 */
7692int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7693{
7694 struct drm_i915_private *dev_priv = dev->dev_private;
7695 u16 gmch_ctrl;
7696
7697 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7698 if (state)
7699 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7700 else
7701 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7702 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7703 return 0;
7704}
c4a1d9e4
CW		 7705
7706#ifdef CONFIG_DEBUG_FS
7707#include <linux/seq_file.h>
7708
7709struct intel_display_error_state {
7710 struct intel_cursor_error_state {
7711 u32 control;
7712 u32 position;
7713 u32 base;
7714 u32 size;
52331309 7715 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 7716
7717 struct intel_pipe_error_state {
7718 u32 conf;
7719 u32 source;
7720
7721 u32 htotal;
7722 u32 hblank;
7723 u32 hsync;
7724 u32 vtotal;
7725 u32 vblank;
7726 u32 vsync;
52331309 7727 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 7728
7729 struct intel_plane_error_state {
7730 u32 control;
7731 u32 stride;
7732 u32 size;
7733 u32 pos;
7734 u32 addr;
7735 u32 surface;
7736 u32 tile_offset;
52331309 7737 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 7738};
7739
7740struct intel_display_error_state *
7741intel_display_capture_error_state(struct drm_device *dev)
7742{
0206e353 7743 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 7744 struct intel_display_error_state *error;
7745 int i;
7746
7747 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7748 if (error == NULL)
7749 return NULL;
7750
52331309 7751 for_each_pipe(i) {
c4a1d9e4
CW		 7752 error->cursor[i].control = I915_READ(CURCNTR(i));
7753 error->cursor[i].position = I915_READ(CURPOS(i));
7754 error->cursor[i].base = I915_READ(CURBASE(i));
7755
7756 error->plane[i].control = I915_READ(DSPCNTR(i));
7757 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7758 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 7759 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 7760 error->plane[i].addr = I915_READ(DSPADDR(i));
7761 if (INTEL_INFO(dev)->gen >= 4) {
7762 error->plane[i].surface = I915_READ(DSPSURF(i));
7763 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7764 }
7765
7766 error->pipe[i].conf = I915_READ(PIPECONF(i));
7767 error->pipe[i].source = I915_READ(PIPESRC(i));
7768 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7769 error->pipe[i].hblank = I915_READ(HBLANK(i));
7770 error->pipe[i].hsync = I915_READ(HSYNC(i));
7771 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7772 error->pipe[i].vblank = I915_READ(VBLANK(i));
7773 error->pipe[i].vsync = I915_READ(VSYNC(i));
7774 }
7775
7776 return error;
7777}
7778
7779void
7780intel_display_print_error_state(struct seq_file *m,
7781 struct drm_device *dev,
7782 struct intel_display_error_state *error)
7783{
52331309 7784 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 7785 int i;
7786
52331309
DL		 7787 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
7788 for_each_pipe(i) {
c4a1d9e4
CW		 7789 seq_printf(m, "Pipe [%d]:\n", i);
7790 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7791 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7792 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7793 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7794 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7795 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7796 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7797 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7798
7799 seq_printf(m, "Plane [%d]:\n", i);
7800 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7801 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7802 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7803 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7804 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7805 if (INTEL_INFO(dev)->gen >= 4) {
7806 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7807 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7808 }
7809
7810 seq_printf(m, "Cursor [%d]:\n", i);
7811 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7812 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7813 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7814 }
7815}
7816#endif
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