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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
23b2f8bb | 27 | #include <linux/cpufreq.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
79e53945 JB |
35 | #include "drmP.h" |
36 | #include "intel_drv.h" | |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
e5510fac | 39 | #include "i915_trace.h" |
ab2c0672 | 40 | #include "drm_dp_helper.h" |
79e53945 | 41 | #include "drm_crtc_helper.h" |
c0f372b3 | 42 | #include <linux/dma_remapping.h> |
79e53945 | 43 | |
32f9d658 ZW |
44 | #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) |
45 | ||
0206e353 | 46 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type); |
7662c8bd | 47 | static void intel_update_watermarks(struct drm_device *dev); |
3dec0095 | 48 | static void intel_increase_pllclock(struct drm_crtc *crtc); |
6b383a7f | 49 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 JB |
50 | |
51 | typedef struct { | |
0206e353 AJ |
52 | /* given values */ |
53 | int n; | |
54 | int m1, m2; | |
55 | int p1, p2; | |
56 | /* derived values */ | |
57 | int dot; | |
58 | int vco; | |
59 | int m; | |
60 | int p; | |
79e53945 JB |
61 | } intel_clock_t; |
62 | ||
63 | typedef struct { | |
0206e353 | 64 | int min, max; |
79e53945 JB |
65 | } intel_range_t; |
66 | ||
67 | typedef struct { | |
0206e353 AJ |
68 | int dot_limit; |
69 | int p2_slow, p2_fast; | |
79e53945 JB |
70 | } intel_p2_t; |
71 | ||
72 | #define INTEL_P2_NUM 2 | |
d4906093 ML |
73 | typedef struct intel_limit intel_limit_t; |
74 | struct intel_limit { | |
0206e353 AJ |
75 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
76 | intel_p2_t p2; | |
77 | bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, | |
cec2f356 | 78 | int, int, intel_clock_t *, intel_clock_t *); |
d4906093 | 79 | }; |
79e53945 | 80 | |
2377b741 JB |
81 | /* FDI */ |
82 | #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ | |
83 | ||
d4906093 ML |
84 | static bool |
85 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
86 | int target, int refclk, intel_clock_t *match_clock, |
87 | intel_clock_t *best_clock); | |
d4906093 ML |
88 | static bool |
89 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
90 | int target, int refclk, intel_clock_t *match_clock, |
91 | intel_clock_t *best_clock); | |
79e53945 | 92 | |
a4fc5ed6 KP |
93 | static bool |
94 | intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, | |
cec2f356 SP |
95 | int target, int refclk, intel_clock_t *match_clock, |
96 | intel_clock_t *best_clock); | |
5eb08b69 | 97 | static bool |
f2b115e6 | 98 | intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, |
cec2f356 SP |
99 | int target, int refclk, intel_clock_t *match_clock, |
100 | intel_clock_t *best_clock); | |
a4fc5ed6 | 101 | |
021357ac CW |
102 | static inline u32 /* units of 100MHz */ |
103 | intel_fdi_link_freq(struct drm_device *dev) | |
104 | { | |
8b99e68c CW |
105 | if (IS_GEN5(dev)) { |
106 | struct drm_i915_private *dev_priv = dev->dev_private; | |
107 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
108 | } else | |
109 | return 27; | |
021357ac CW |
110 | } |
111 | ||
e4b36699 | 112 | static const intel_limit_t intel_limits_i8xx_dvo = { |
0206e353 AJ |
113 | .dot = { .min = 25000, .max = 350000 }, |
114 | .vco = { .min = 930000, .max = 1400000 }, | |
115 | .n = { .min = 3, .max = 16 }, | |
116 | .m = { .min = 96, .max = 140 }, | |
117 | .m1 = { .min = 18, .max = 26 }, | |
118 | .m2 = { .min = 6, .max = 16 }, | |
119 | .p = { .min = 4, .max = 128 }, | |
120 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
121 | .p2 = { .dot_limit = 165000, |
122 | .p2_slow = 4, .p2_fast = 2 }, | |
d4906093 | 123 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
124 | }; |
125 | ||
126 | static const intel_limit_t intel_limits_i8xx_lvds = { | |
0206e353 AJ |
127 | .dot = { .min = 25000, .max = 350000 }, |
128 | .vco = { .min = 930000, .max = 1400000 }, | |
129 | .n = { .min = 3, .max = 16 }, | |
130 | .m = { .min = 96, .max = 140 }, | |
131 | .m1 = { .min = 18, .max = 26 }, | |
132 | .m2 = { .min = 6, .max = 16 }, | |
133 | .p = { .min = 4, .max = 128 }, | |
134 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
135 | .p2 = { .dot_limit = 165000, |
136 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 137 | .find_pll = intel_find_best_PLL, |
e4b36699 | 138 | }; |
273e27ca | 139 | |
e4b36699 | 140 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
141 | .dot = { .min = 20000, .max = 400000 }, |
142 | .vco = { .min = 1400000, .max = 2800000 }, | |
143 | .n = { .min = 1, .max = 6 }, | |
144 | .m = { .min = 70, .max = 120 }, | |
145 | .m1 = { .min = 10, .max = 22 }, | |
146 | .m2 = { .min = 5, .max = 9 }, | |
147 | .p = { .min = 5, .max = 80 }, | |
148 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
149 | .p2 = { .dot_limit = 200000, |
150 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 151 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
152 | }; |
153 | ||
154 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
155 | .dot = { .min = 20000, .max = 400000 }, |
156 | .vco = { .min = 1400000, .max = 2800000 }, | |
157 | .n = { .min = 1, .max = 6 }, | |
158 | .m = { .min = 70, .max = 120 }, | |
159 | .m1 = { .min = 10, .max = 22 }, | |
160 | .m2 = { .min = 5, .max = 9 }, | |
161 | .p = { .min = 7, .max = 98 }, | |
162 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
163 | .p2 = { .dot_limit = 112000, |
164 | .p2_slow = 14, .p2_fast = 7 }, | |
d4906093 | 165 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
166 | }; |
167 | ||
273e27ca | 168 | |
e4b36699 | 169 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
170 | .dot = { .min = 25000, .max = 270000 }, |
171 | .vco = { .min = 1750000, .max = 3500000}, | |
172 | .n = { .min = 1, .max = 4 }, | |
173 | .m = { .min = 104, .max = 138 }, | |
174 | .m1 = { .min = 17, .max = 23 }, | |
175 | .m2 = { .min = 5, .max = 11 }, | |
176 | .p = { .min = 10, .max = 30 }, | |
177 | .p1 = { .min = 1, .max = 3}, | |
178 | .p2 = { .dot_limit = 270000, | |
179 | .p2_slow = 10, | |
180 | .p2_fast = 10 | |
044c7c41 | 181 | }, |
d4906093 | 182 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
183 | }; |
184 | ||
185 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
186 | .dot = { .min = 22000, .max = 400000 }, |
187 | .vco = { .min = 1750000, .max = 3500000}, | |
188 | .n = { .min = 1, .max = 4 }, | |
189 | .m = { .min = 104, .max = 138 }, | |
190 | .m1 = { .min = 16, .max = 23 }, | |
191 | .m2 = { .min = 5, .max = 11 }, | |
192 | .p = { .min = 5, .max = 80 }, | |
193 | .p1 = { .min = 1, .max = 8}, | |
194 | .p2 = { .dot_limit = 165000, | |
195 | .p2_slow = 10, .p2_fast = 5 }, | |
d4906093 | 196 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
197 | }; |
198 | ||
199 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
200 | .dot = { .min = 20000, .max = 115000 }, |
201 | .vco = { .min = 1750000, .max = 3500000 }, | |
202 | .n = { .min = 1, .max = 3 }, | |
203 | .m = { .min = 104, .max = 138 }, | |
204 | .m1 = { .min = 17, .max = 23 }, | |
205 | .m2 = { .min = 5, .max = 11 }, | |
206 | .p = { .min = 28, .max = 112 }, | |
207 | .p1 = { .min = 2, .max = 8 }, | |
208 | .p2 = { .dot_limit = 0, | |
209 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 210 | }, |
d4906093 | 211 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
212 | }; |
213 | ||
214 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
215 | .dot = { .min = 80000, .max = 224000 }, |
216 | .vco = { .min = 1750000, .max = 3500000 }, | |
217 | .n = { .min = 1, .max = 3 }, | |
218 | .m = { .min = 104, .max = 138 }, | |
219 | .m1 = { .min = 17, .max = 23 }, | |
220 | .m2 = { .min = 5, .max = 11 }, | |
221 | .p = { .min = 14, .max = 42 }, | |
222 | .p1 = { .min = 2, .max = 6 }, | |
223 | .p2 = { .dot_limit = 0, | |
224 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 225 | }, |
d4906093 | 226 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
227 | }; |
228 | ||
229 | static const intel_limit_t intel_limits_g4x_display_port = { | |
0206e353 AJ |
230 | .dot = { .min = 161670, .max = 227000 }, |
231 | .vco = { .min = 1750000, .max = 3500000}, | |
232 | .n = { .min = 1, .max = 2 }, | |
233 | .m = { .min = 97, .max = 108 }, | |
234 | .m1 = { .min = 0x10, .max = 0x12 }, | |
235 | .m2 = { .min = 0x05, .max = 0x06 }, | |
236 | .p = { .min = 10, .max = 20 }, | |
237 | .p1 = { .min = 1, .max = 2}, | |
238 | .p2 = { .dot_limit = 0, | |
273e27ca | 239 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 240 | .find_pll = intel_find_pll_g4x_dp, |
e4b36699 KP |
241 | }; |
242 | ||
f2b115e6 | 243 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
244 | .dot = { .min = 20000, .max = 400000}, |
245 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 246 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
247 | .n = { .min = 3, .max = 6 }, |
248 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 249 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
250 | .m1 = { .min = 0, .max = 0 }, |
251 | .m2 = { .min = 0, .max = 254 }, | |
252 | .p = { .min = 5, .max = 80 }, | |
253 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
254 | .p2 = { .dot_limit = 200000, |
255 | .p2_slow = 10, .p2_fast = 5 }, | |
6115707b | 256 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
257 | }; |
258 | ||
f2b115e6 | 259 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
260 | .dot = { .min = 20000, .max = 400000 }, |
261 | .vco = { .min = 1700000, .max = 3500000 }, | |
262 | .n = { .min = 3, .max = 6 }, | |
263 | .m = { .min = 2, .max = 256 }, | |
264 | .m1 = { .min = 0, .max = 0 }, | |
265 | .m2 = { .min = 0, .max = 254 }, | |
266 | .p = { .min = 7, .max = 112 }, | |
267 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
268 | .p2 = { .dot_limit = 112000, |
269 | .p2_slow = 14, .p2_fast = 14 }, | |
6115707b | 270 | .find_pll = intel_find_best_PLL, |
e4b36699 KP |
271 | }; |
272 | ||
273e27ca EA |
273 | /* Ironlake / Sandybridge |
274 | * | |
275 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
276 | * the range value for them is (actual_value - 2). | |
277 | */ | |
b91ad0ec | 278 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
279 | .dot = { .min = 25000, .max = 350000 }, |
280 | .vco = { .min = 1760000, .max = 3510000 }, | |
281 | .n = { .min = 1, .max = 5 }, | |
282 | .m = { .min = 79, .max = 127 }, | |
283 | .m1 = { .min = 12, .max = 22 }, | |
284 | .m2 = { .min = 5, .max = 9 }, | |
285 | .p = { .min = 5, .max = 80 }, | |
286 | .p1 = { .min = 1, .max = 8 }, | |
287 | .p2 = { .dot_limit = 225000, | |
288 | .p2_slow = 10, .p2_fast = 5 }, | |
4547668a | 289 | .find_pll = intel_g4x_find_best_PLL, |
e4b36699 KP |
290 | }; |
291 | ||
b91ad0ec | 292 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
293 | .dot = { .min = 25000, .max = 350000 }, |
294 | .vco = { .min = 1760000, .max = 3510000 }, | |
295 | .n = { .min = 1, .max = 3 }, | |
296 | .m = { .min = 79, .max = 118 }, | |
297 | .m1 = { .min = 12, .max = 22 }, | |
298 | .m2 = { .min = 5, .max = 9 }, | |
299 | .p = { .min = 28, .max = 112 }, | |
300 | .p1 = { .min = 2, .max = 8 }, | |
301 | .p2 = { .dot_limit = 225000, | |
302 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
303 | .find_pll = intel_g4x_find_best_PLL, |
304 | }; | |
305 | ||
306 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
307 | .dot = { .min = 25000, .max = 350000 }, |
308 | .vco = { .min = 1760000, .max = 3510000 }, | |
309 | .n = { .min = 1, .max = 3 }, | |
310 | .m = { .min = 79, .max = 127 }, | |
311 | .m1 = { .min = 12, .max = 22 }, | |
312 | .m2 = { .min = 5, .max = 9 }, | |
313 | .p = { .min = 14, .max = 56 }, | |
314 | .p1 = { .min = 2, .max = 8 }, | |
315 | .p2 = { .dot_limit = 225000, | |
316 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
317 | .find_pll = intel_g4x_find_best_PLL, |
318 | }; | |
319 | ||
273e27ca | 320 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 321 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
322 | .dot = { .min = 25000, .max = 350000 }, |
323 | .vco = { .min = 1760000, .max = 3510000 }, | |
324 | .n = { .min = 1, .max = 2 }, | |
325 | .m = { .min = 79, .max = 126 }, | |
326 | .m1 = { .min = 12, .max = 22 }, | |
327 | .m2 = { .min = 5, .max = 9 }, | |
328 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 329 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
330 | .p2 = { .dot_limit = 225000, |
331 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
332 | .find_pll = intel_g4x_find_best_PLL, |
333 | }; | |
334 | ||
335 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
336 | .dot = { .min = 25000, .max = 350000 }, |
337 | .vco = { .min = 1760000, .max = 3510000 }, | |
338 | .n = { .min = 1, .max = 3 }, | |
339 | .m = { .min = 79, .max = 126 }, | |
340 | .m1 = { .min = 12, .max = 22 }, | |
341 | .m2 = { .min = 5, .max = 9 }, | |
342 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 343 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
344 | .p2 = { .dot_limit = 225000, |
345 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
346 | .find_pll = intel_g4x_find_best_PLL, |
347 | }; | |
348 | ||
349 | static const intel_limit_t intel_limits_ironlake_display_port = { | |
0206e353 AJ |
350 | .dot = { .min = 25000, .max = 350000 }, |
351 | .vco = { .min = 1760000, .max = 3510000}, | |
352 | .n = { .min = 1, .max = 2 }, | |
353 | .m = { .min = 81, .max = 90 }, | |
354 | .m1 = { .min = 12, .max = 22 }, | |
355 | .m2 = { .min = 5, .max = 9 }, | |
356 | .p = { .min = 10, .max = 20 }, | |
357 | .p1 = { .min = 1, .max = 2}, | |
358 | .p2 = { .dot_limit = 0, | |
273e27ca | 359 | .p2_slow = 10, .p2_fast = 10 }, |
0206e353 | 360 | .find_pll = intel_find_pll_ironlake_dp, |
79e53945 JB |
361 | }; |
362 | ||
1b894b59 CW |
363 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
364 | int refclk) | |
2c07245f | 365 | { |
b91ad0ec ZW |
366 | struct drm_device *dev = crtc->dev; |
367 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2c07245f | 368 | const intel_limit_t *limit; |
b91ad0ec ZW |
369 | |
370 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
b91ad0ec ZW |
371 | if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == |
372 | LVDS_CLKB_POWER_UP) { | |
373 | /* LVDS dual channel */ | |
1b894b59 | 374 | if (refclk == 100000) |
b91ad0ec ZW |
375 | limit = &intel_limits_ironlake_dual_lvds_100m; |
376 | else | |
377 | limit = &intel_limits_ironlake_dual_lvds; | |
378 | } else { | |
1b894b59 | 379 | if (refclk == 100000) |
b91ad0ec ZW |
380 | limit = &intel_limits_ironlake_single_lvds_100m; |
381 | else | |
382 | limit = &intel_limits_ironlake_single_lvds; | |
383 | } | |
384 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || | |
4547668a ZY |
385 | HAS_eDP) |
386 | limit = &intel_limits_ironlake_display_port; | |
2c07245f | 387 | else |
b91ad0ec | 388 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
389 | |
390 | return limit; | |
391 | } | |
392 | ||
044c7c41 ML |
393 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
394 | { | |
395 | struct drm_device *dev = crtc->dev; | |
396 | struct drm_i915_private *dev_priv = dev->dev_private; | |
397 | const intel_limit_t *limit; | |
398 | ||
399 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
400 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
401 | LVDS_CLKB_POWER_UP) | |
402 | /* LVDS with dual channel */ | |
e4b36699 | 403 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 ML |
404 | else |
405 | /* LVDS with dual channel */ | |
e4b36699 | 406 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
407 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
408 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 409 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 410 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 411 | limit = &intel_limits_g4x_sdvo; |
0206e353 | 412 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
e4b36699 | 413 | limit = &intel_limits_g4x_display_port; |
044c7c41 | 414 | } else /* The option is for other outputs */ |
e4b36699 | 415 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
416 | |
417 | return limit; | |
418 | } | |
419 | ||
1b894b59 | 420 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
421 | { |
422 | struct drm_device *dev = crtc->dev; | |
423 | const intel_limit_t *limit; | |
424 | ||
bad720ff | 425 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 426 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 427 | else if (IS_G4X(dev)) { |
044c7c41 | 428 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 429 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 430 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 431 | limit = &intel_limits_pineview_lvds; |
2177832f | 432 | else |
f2b115e6 | 433 | limit = &intel_limits_pineview_sdvo; |
a6c45cf0 CW |
434 | } else if (!IS_GEN2(dev)) { |
435 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
436 | limit = &intel_limits_i9xx_lvds; | |
437 | else | |
438 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
439 | } else { |
440 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 441 | limit = &intel_limits_i8xx_lvds; |
79e53945 | 442 | else |
e4b36699 | 443 | limit = &intel_limits_i8xx_dvo; |
79e53945 JB |
444 | } |
445 | return limit; | |
446 | } | |
447 | ||
f2b115e6 AJ |
448 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
449 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 450 | { |
2177832f SL |
451 | clock->m = clock->m2 + 2; |
452 | clock->p = clock->p1 * clock->p2; | |
453 | clock->vco = refclk * clock->m / clock->n; | |
454 | clock->dot = clock->vco / clock->p; | |
455 | } | |
456 | ||
457 | static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) | |
458 | { | |
f2b115e6 AJ |
459 | if (IS_PINEVIEW(dev)) { |
460 | pineview_clock(refclk, clock); | |
2177832f SL |
461 | return; |
462 | } | |
79e53945 JB |
463 | clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); |
464 | clock->p = clock->p1 * clock->p2; | |
465 | clock->vco = refclk * clock->m / (clock->n + 2); | |
466 | clock->dot = clock->vco / clock->p; | |
467 | } | |
468 | ||
79e53945 JB |
469 | /** |
470 | * Returns whether any output on the specified pipe is of the specified type | |
471 | */ | |
4ef69c7a | 472 | bool intel_pipe_has_type(struct drm_crtc *crtc, int type) |
79e53945 | 473 | { |
4ef69c7a CW |
474 | struct drm_device *dev = crtc->dev; |
475 | struct drm_mode_config *mode_config = &dev->mode_config; | |
476 | struct intel_encoder *encoder; | |
477 | ||
478 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
479 | if (encoder->base.crtc == crtc && encoder->type == type) | |
480 | return true; | |
481 | ||
482 | return false; | |
79e53945 JB |
483 | } |
484 | ||
7c04d1d9 | 485 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
486 | /** |
487 | * Returns whether the given set of divisors are valid for a given refclk with | |
488 | * the given connectors. | |
489 | */ | |
490 | ||
1b894b59 CW |
491 | static bool intel_PLL_is_valid(struct drm_device *dev, |
492 | const intel_limit_t *limit, | |
493 | const intel_clock_t *clock) | |
79e53945 | 494 | { |
79e53945 | 495 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 496 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 497 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
0206e353 | 498 | INTELPllInvalid("p out of range\n"); |
79e53945 | 499 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 500 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 501 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 502 | INTELPllInvalid("m1 out of range\n"); |
f2b115e6 | 503 | if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) |
0206e353 | 504 | INTELPllInvalid("m1 <= m2\n"); |
79e53945 | 505 | if (clock->m < limit->m.min || limit->m.max < clock->m) |
0206e353 | 506 | INTELPllInvalid("m out of range\n"); |
79e53945 | 507 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
0206e353 | 508 | INTELPllInvalid("n out of range\n"); |
79e53945 | 509 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 510 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
511 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
512 | * connector, etc., rather than just a single range. | |
513 | */ | |
514 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 515 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
516 | |
517 | return true; | |
518 | } | |
519 | ||
d4906093 ML |
520 | static bool |
521 | intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
522 | int target, int refclk, intel_clock_t *match_clock, |
523 | intel_clock_t *best_clock) | |
d4906093 | 524 | |
79e53945 JB |
525 | { |
526 | struct drm_device *dev = crtc->dev; | |
527 | struct drm_i915_private *dev_priv = dev->dev_private; | |
528 | intel_clock_t clock; | |
79e53945 JB |
529 | int err = target; |
530 | ||
bc5e5718 | 531 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
832cc28d | 532 | (I915_READ(LVDS)) != 0) { |
79e53945 JB |
533 | /* |
534 | * For LVDS, if the panel is on, just rely on its current | |
535 | * settings for dual-channel. We haven't figured out how to | |
536 | * reliably set up different single/dual channel state, if we | |
537 | * even can. | |
538 | */ | |
539 | if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) == | |
540 | LVDS_CLKB_POWER_UP) | |
541 | clock.p2 = limit->p2.p2_fast; | |
542 | else | |
543 | clock.p2 = limit->p2.p2_slow; | |
544 | } else { | |
545 | if (target < limit->p2.dot_limit) | |
546 | clock.p2 = limit->p2.p2_slow; | |
547 | else | |
548 | clock.p2 = limit->p2.p2_fast; | |
549 | } | |
550 | ||
0206e353 | 551 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 552 | |
42158660 ZY |
553 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
554 | clock.m1++) { | |
555 | for (clock.m2 = limit->m2.min; | |
556 | clock.m2 <= limit->m2.max; clock.m2++) { | |
f2b115e6 AJ |
557 | /* m1 is always 0 in Pineview */ |
558 | if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) | |
42158660 ZY |
559 | break; |
560 | for (clock.n = limit->n.min; | |
561 | clock.n <= limit->n.max; clock.n++) { | |
562 | for (clock.p1 = limit->p1.min; | |
563 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
564 | int this_err; |
565 | ||
2177832f | 566 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
567 | if (!intel_PLL_is_valid(dev, limit, |
568 | &clock)) | |
79e53945 | 569 | continue; |
cec2f356 SP |
570 | if (match_clock && |
571 | clock.p != match_clock->p) | |
572 | continue; | |
79e53945 JB |
573 | |
574 | this_err = abs(clock.dot - target); | |
575 | if (this_err < err) { | |
576 | *best_clock = clock; | |
577 | err = this_err; | |
578 | } | |
579 | } | |
580 | } | |
581 | } | |
582 | } | |
583 | ||
584 | return (err != target); | |
585 | } | |
586 | ||
d4906093 ML |
587 | static bool |
588 | intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
589 | int target, int refclk, intel_clock_t *match_clock, |
590 | intel_clock_t *best_clock) | |
d4906093 ML |
591 | { |
592 | struct drm_device *dev = crtc->dev; | |
593 | struct drm_i915_private *dev_priv = dev->dev_private; | |
594 | intel_clock_t clock; | |
595 | int max_n; | |
596 | bool found; | |
6ba770dc AJ |
597 | /* approximately equals target * 0.00585 */ |
598 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
599 | found = false; |
600 | ||
601 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
4547668a ZY |
602 | int lvds_reg; |
603 | ||
c619eed4 | 604 | if (HAS_PCH_SPLIT(dev)) |
4547668a ZY |
605 | lvds_reg = PCH_LVDS; |
606 | else | |
607 | lvds_reg = LVDS; | |
608 | if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) == | |
d4906093 ML |
609 | LVDS_CLKB_POWER_UP) |
610 | clock.p2 = limit->p2.p2_fast; | |
611 | else | |
612 | clock.p2 = limit->p2.p2_slow; | |
613 | } else { | |
614 | if (target < limit->p2.dot_limit) | |
615 | clock.p2 = limit->p2.p2_slow; | |
616 | else | |
617 | clock.p2 = limit->p2.p2_fast; | |
618 | } | |
619 | ||
620 | memset(best_clock, 0, sizeof(*best_clock)); | |
621 | max_n = limit->n.max; | |
f77f13e2 | 622 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 623 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 624 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
625 | for (clock.m1 = limit->m1.max; |
626 | clock.m1 >= limit->m1.min; clock.m1--) { | |
627 | for (clock.m2 = limit->m2.max; | |
628 | clock.m2 >= limit->m2.min; clock.m2--) { | |
629 | for (clock.p1 = limit->p1.max; | |
630 | clock.p1 >= limit->p1.min; clock.p1--) { | |
631 | int this_err; | |
632 | ||
2177832f | 633 | intel_clock(dev, refclk, &clock); |
1b894b59 CW |
634 | if (!intel_PLL_is_valid(dev, limit, |
635 | &clock)) | |
d4906093 | 636 | continue; |
cec2f356 SP |
637 | if (match_clock && |
638 | clock.p != match_clock->p) | |
639 | continue; | |
1b894b59 CW |
640 | |
641 | this_err = abs(clock.dot - target); | |
d4906093 ML |
642 | if (this_err < err_most) { |
643 | *best_clock = clock; | |
644 | err_most = this_err; | |
645 | max_n = clock.n; | |
646 | found = true; | |
647 | } | |
648 | } | |
649 | } | |
650 | } | |
651 | } | |
2c07245f ZW |
652 | return found; |
653 | } | |
654 | ||
5eb08b69 | 655 | static bool |
f2b115e6 | 656 | intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
657 | int target, int refclk, intel_clock_t *match_clock, |
658 | intel_clock_t *best_clock) | |
5eb08b69 ZW |
659 | { |
660 | struct drm_device *dev = crtc->dev; | |
661 | intel_clock_t clock; | |
4547668a | 662 | |
5eb08b69 ZW |
663 | if (target < 200000) { |
664 | clock.n = 1; | |
665 | clock.p1 = 2; | |
666 | clock.p2 = 10; | |
667 | clock.m1 = 12; | |
668 | clock.m2 = 9; | |
669 | } else { | |
670 | clock.n = 2; | |
671 | clock.p1 = 1; | |
672 | clock.p2 = 10; | |
673 | clock.m1 = 14; | |
674 | clock.m2 = 8; | |
675 | } | |
676 | intel_clock(dev, refclk, &clock); | |
677 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
678 | return true; | |
679 | } | |
680 | ||
a4fc5ed6 KP |
681 | /* DisplayPort has only two frequencies, 162MHz and 270MHz */ |
682 | static bool | |
683 | intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, | |
cec2f356 SP |
684 | int target, int refclk, intel_clock_t *match_clock, |
685 | intel_clock_t *best_clock) | |
a4fc5ed6 | 686 | { |
5eddb70b CW |
687 | intel_clock_t clock; |
688 | if (target < 200000) { | |
689 | clock.p1 = 2; | |
690 | clock.p2 = 10; | |
691 | clock.n = 2; | |
692 | clock.m1 = 23; | |
693 | clock.m2 = 8; | |
694 | } else { | |
695 | clock.p1 = 1; | |
696 | clock.p2 = 10; | |
697 | clock.n = 1; | |
698 | clock.m1 = 14; | |
699 | clock.m2 = 2; | |
700 | } | |
701 | clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); | |
702 | clock.p = (clock.p1 * clock.p2); | |
703 | clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; | |
704 | clock.vco = 0; | |
705 | memcpy(best_clock, &clock, sizeof(intel_clock_t)); | |
706 | return true; | |
a4fc5ed6 KP |
707 | } |
708 | ||
9d0498a2 JB |
709 | /** |
710 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
711 | * @dev: drm device | |
712 | * @pipe: pipe to wait for | |
713 | * | |
714 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
715 | * mode setting code. | |
716 | */ | |
717 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 718 | { |
9d0498a2 | 719 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 720 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 721 | |
300387c0 CW |
722 | /* Clear existing vblank status. Note this will clear any other |
723 | * sticky status fields as well. | |
724 | * | |
725 | * This races with i915_driver_irq_handler() with the result | |
726 | * that either function could miss a vblank event. Here it is not | |
727 | * fatal, as we will either wait upon the next vblank interrupt or | |
728 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
729 | * called during modeset at which time the GPU should be idle and | |
730 | * should *not* be performing page flips and thus not waiting on | |
731 | * vblanks... | |
732 | * Currently, the result of us stealing a vblank from the irq | |
733 | * handler is that a single frame will be skipped during swapbuffers. | |
734 | */ | |
735 | I915_WRITE(pipestat_reg, | |
736 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
737 | ||
9d0498a2 | 738 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
739 | if (wait_for(I915_READ(pipestat_reg) & |
740 | PIPE_VBLANK_INTERRUPT_STATUS, | |
741 | 50)) | |
9d0498a2 JB |
742 | DRM_DEBUG_KMS("vblank wait timed out\n"); |
743 | } | |
744 | ||
ab7ad7f6 KP |
745 | /* |
746 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
9d0498a2 JB |
747 | * @dev: drm device |
748 | * @pipe: pipe to wait for | |
749 | * | |
750 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
751 | * spinning on the vblank interrupt status bit, since we won't actually | |
752 | * see an interrupt when the pipe is disabled. | |
753 | * | |
ab7ad7f6 KP |
754 | * On Gen4 and above: |
755 | * wait for the pipe register state bit to turn off | |
756 | * | |
757 | * Otherwise: | |
758 | * wait for the display line value to settle (it usually | |
759 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 760 | * |
9d0498a2 | 761 | */ |
58e10eb9 | 762 | void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) |
9d0498a2 JB |
763 | { |
764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ab7ad7f6 KP |
765 | |
766 | if (INTEL_INFO(dev)->gen >= 4) { | |
58e10eb9 | 767 | int reg = PIPECONF(pipe); |
ab7ad7f6 KP |
768 | |
769 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
770 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
771 | 100)) | |
ab7ad7f6 KP |
772 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); |
773 | } else { | |
774 | u32 last_line; | |
58e10eb9 | 775 | int reg = PIPEDSL(pipe); |
ab7ad7f6 KP |
776 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
777 | ||
778 | /* Wait for the display line to settle */ | |
779 | do { | |
58e10eb9 | 780 | last_line = I915_READ(reg) & DSL_LINEMASK; |
ab7ad7f6 | 781 | mdelay(5); |
58e10eb9 | 782 | } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) && |
ab7ad7f6 KP |
783 | time_after(timeout, jiffies)); |
784 | if (time_after(jiffies, timeout)) | |
785 | DRM_DEBUG_KMS("pipe_off wait timed out\n"); | |
786 | } | |
79e53945 JB |
787 | } |
788 | ||
b24e7179 JB |
789 | static const char *state_string(bool enabled) |
790 | { | |
791 | return enabled ? "on" : "off"; | |
792 | } | |
793 | ||
794 | /* Only for pre-ILK configs */ | |
795 | static void assert_pll(struct drm_i915_private *dev_priv, | |
796 | enum pipe pipe, bool state) | |
797 | { | |
798 | int reg; | |
799 | u32 val; | |
800 | bool cur_state; | |
801 | ||
802 | reg = DPLL(pipe); | |
803 | val = I915_READ(reg); | |
804 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
805 | WARN(cur_state != state, | |
806 | "PLL state assertion failure (expected %s, current %s)\n", | |
807 | state_string(state), state_string(cur_state)); | |
808 | } | |
809 | #define assert_pll_enabled(d, p) assert_pll(d, p, true) | |
810 | #define assert_pll_disabled(d, p) assert_pll(d, p, false) | |
811 | ||
040484af JB |
812 | /* For ILK+ */ |
813 | static void assert_pch_pll(struct drm_i915_private *dev_priv, | |
814 | enum pipe pipe, bool state) | |
815 | { | |
816 | int reg; | |
817 | u32 val; | |
818 | bool cur_state; | |
819 | ||
d3ccbe86 JB |
820 | if (HAS_PCH_CPT(dev_priv->dev)) { |
821 | u32 pch_dpll; | |
822 | ||
823 | pch_dpll = I915_READ(PCH_DPLL_SEL); | |
824 | ||
825 | /* Make sure the selected PLL is enabled to the transcoder */ | |
826 | WARN(!((pch_dpll >> (4 * pipe)) & 8), | |
827 | "transcoder %d PLL not enabled\n", pipe); | |
828 | ||
829 | /* Convert the transcoder pipe number to a pll pipe number */ | |
830 | pipe = (pch_dpll >> (4 * pipe)) & 1; | |
831 | } | |
832 | ||
040484af JB |
833 | reg = PCH_DPLL(pipe); |
834 | val = I915_READ(reg); | |
835 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
836 | WARN(cur_state != state, | |
837 | "PCH PLL state assertion failure (expected %s, current %s)\n", | |
838 | state_string(state), state_string(cur_state)); | |
839 | } | |
840 | #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true) | |
841 | #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false) | |
842 | ||
843 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
844 | enum pipe pipe, bool state) | |
845 | { | |
846 | int reg; | |
847 | u32 val; | |
848 | bool cur_state; | |
849 | ||
850 | reg = FDI_TX_CTL(pipe); | |
851 | val = I915_READ(reg); | |
852 | cur_state = !!(val & FDI_TX_ENABLE); | |
853 | WARN(cur_state != state, | |
854 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
855 | state_string(state), state_string(cur_state)); | |
856 | } | |
857 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
858 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
859 | ||
860 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
861 | enum pipe pipe, bool state) | |
862 | { | |
863 | int reg; | |
864 | u32 val; | |
865 | bool cur_state; | |
866 | ||
867 | reg = FDI_RX_CTL(pipe); | |
868 | val = I915_READ(reg); | |
869 | cur_state = !!(val & FDI_RX_ENABLE); | |
870 | WARN(cur_state != state, | |
871 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
872 | state_string(state), state_string(cur_state)); | |
873 | } | |
874 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
875 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
876 | ||
877 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
878 | enum pipe pipe) | |
879 | { | |
880 | int reg; | |
881 | u32 val; | |
882 | ||
883 | /* ILK FDI PLL is always enabled */ | |
884 | if (dev_priv->info->gen == 5) | |
885 | return; | |
886 | ||
887 | reg = FDI_TX_CTL(pipe); | |
888 | val = I915_READ(reg); | |
889 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
890 | } | |
891 | ||
892 | static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, | |
893 | enum pipe pipe) | |
894 | { | |
895 | int reg; | |
896 | u32 val; | |
897 | ||
898 | reg = FDI_RX_CTL(pipe); | |
899 | val = I915_READ(reg); | |
900 | WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); | |
901 | } | |
902 | ||
ea0760cf JB |
903 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
904 | enum pipe pipe) | |
905 | { | |
906 | int pp_reg, lvds_reg; | |
907 | u32 val; | |
908 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 909 | bool locked = true; |
ea0760cf JB |
910 | |
911 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
912 | pp_reg = PCH_PP_CONTROL; | |
913 | lvds_reg = PCH_LVDS; | |
914 | } else { | |
915 | pp_reg = PP_CONTROL; | |
916 | lvds_reg = LVDS; | |
917 | } | |
918 | ||
919 | val = I915_READ(pp_reg); | |
920 | if (!(val & PANEL_POWER_ON) || | |
921 | ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) | |
922 | locked = false; | |
923 | ||
924 | if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) | |
925 | panel_pipe = PIPE_B; | |
926 | ||
927 | WARN(panel_pipe == pipe && locked, | |
928 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 929 | pipe_name(pipe)); |
ea0760cf JB |
930 | } |
931 | ||
b840d907 JB |
932 | void assert_pipe(struct drm_i915_private *dev_priv, |
933 | enum pipe pipe, bool state) | |
b24e7179 JB |
934 | { |
935 | int reg; | |
936 | u32 val; | |
63d7bbe9 | 937 | bool cur_state; |
b24e7179 | 938 | |
8e636784 DV |
939 | /* if we need the pipe A quirk it must be always on */ |
940 | if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) | |
941 | state = true; | |
942 | ||
b24e7179 JB |
943 | reg = PIPECONF(pipe); |
944 | val = I915_READ(reg); | |
63d7bbe9 JB |
945 | cur_state = !!(val & PIPECONF_ENABLE); |
946 | WARN(cur_state != state, | |
947 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 948 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
949 | } |
950 | ||
931872fc CW |
951 | static void assert_plane(struct drm_i915_private *dev_priv, |
952 | enum plane plane, bool state) | |
b24e7179 JB |
953 | { |
954 | int reg; | |
955 | u32 val; | |
931872fc | 956 | bool cur_state; |
b24e7179 JB |
957 | |
958 | reg = DSPCNTR(plane); | |
959 | val = I915_READ(reg); | |
931872fc CW |
960 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
961 | WARN(cur_state != state, | |
962 | "plane %c assertion failure (expected %s, current %s)\n", | |
963 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
964 | } |
965 | ||
931872fc CW |
966 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
967 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
968 | ||
b24e7179 JB |
969 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
970 | enum pipe pipe) | |
971 | { | |
972 | int reg, i; | |
973 | u32 val; | |
974 | int cur_pipe; | |
975 | ||
19ec1358 | 976 | /* Planes are fixed to pipes on ILK+ */ |
28c05794 AJ |
977 | if (HAS_PCH_SPLIT(dev_priv->dev)) { |
978 | reg = DSPCNTR(pipe); | |
979 | val = I915_READ(reg); | |
980 | WARN((val & DISPLAY_PLANE_ENABLE), | |
981 | "plane %c assertion failure, should be disabled but not\n", | |
982 | plane_name(pipe)); | |
19ec1358 | 983 | return; |
28c05794 | 984 | } |
19ec1358 | 985 | |
b24e7179 JB |
986 | /* Need to check both planes against the pipe */ |
987 | for (i = 0; i < 2; i++) { | |
988 | reg = DSPCNTR(i); | |
989 | val = I915_READ(reg); | |
990 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
991 | DISPPLANE_SEL_PIPE_SHIFT; | |
992 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
993 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
994 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
995 | } |
996 | } | |
997 | ||
92f2584a JB |
998 | static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
999 | { | |
1000 | u32 val; | |
1001 | bool enabled; | |
1002 | ||
1003 | val = I915_READ(PCH_DREF_CONTROL); | |
1004 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1005 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1006 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1007 | } | |
1008 | ||
1009 | static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, | |
1010 | enum pipe pipe) | |
1011 | { | |
1012 | int reg; | |
1013 | u32 val; | |
1014 | bool enabled; | |
1015 | ||
1016 | reg = TRANSCONF(pipe); | |
1017 | val = I915_READ(reg); | |
1018 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1019 | WARN(enabled, |
1020 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1021 | pipe_name(pipe)); | |
92f2584a JB |
1022 | } |
1023 | ||
4e634389 KP |
1024 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1025 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1026 | { |
1027 | if ((val & DP_PORT_EN) == 0) | |
1028 | return false; | |
1029 | ||
1030 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1031 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1032 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1033 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1034 | return false; | |
1035 | } else { | |
1036 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1037 | return false; | |
1038 | } | |
1039 | return true; | |
1040 | } | |
1041 | ||
1519b995 KP |
1042 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1043 | enum pipe pipe, u32 val) | |
1044 | { | |
1045 | if ((val & PORT_ENABLE) == 0) | |
1046 | return false; | |
1047 | ||
1048 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1049 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1050 | return false; | |
1051 | } else { | |
1052 | if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) | |
1053 | return false; | |
1054 | } | |
1055 | return true; | |
1056 | } | |
1057 | ||
1058 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1059 | enum pipe pipe, u32 val) | |
1060 | { | |
1061 | if ((val & LVDS_PORT_EN) == 0) | |
1062 | return false; | |
1063 | ||
1064 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1065 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1066 | return false; | |
1067 | } else { | |
1068 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1069 | return false; | |
1070 | } | |
1071 | return true; | |
1072 | } | |
1073 | ||
1074 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1075 | enum pipe pipe, u32 val) | |
1076 | { | |
1077 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1078 | return false; | |
1079 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1080 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1081 | return false; | |
1082 | } else { | |
1083 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1084 | return false; | |
1085 | } | |
1086 | return true; | |
1087 | } | |
1088 | ||
291906f1 | 1089 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1090 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1091 | { |
47a05eca | 1092 | u32 val = I915_READ(reg); |
4e634389 | 1093 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1094 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1095 | reg, pipe_name(pipe)); |
291906f1 JB |
1096 | } |
1097 | ||
1098 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1099 | enum pipe pipe, int reg) | |
1100 | { | |
47a05eca | 1101 | u32 val = I915_READ(reg); |
1519b995 | 1102 | WARN(hdmi_pipe_enabled(dev_priv, val, pipe), |
23c99e77 | 1103 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1104 | reg, pipe_name(pipe)); |
291906f1 JB |
1105 | } |
1106 | ||
1107 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1108 | enum pipe pipe) | |
1109 | { | |
1110 | int reg; | |
1111 | u32 val; | |
291906f1 | 1112 | |
f0575e92 KP |
1113 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1114 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1115 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1116 | |
1117 | reg = PCH_ADPA; | |
1118 | val = I915_READ(reg); | |
1519b995 | 1119 | WARN(adpa_pipe_enabled(dev_priv, val, pipe), |
291906f1 | 1120 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1121 | pipe_name(pipe)); |
291906f1 JB |
1122 | |
1123 | reg = PCH_LVDS; | |
1124 | val = I915_READ(reg); | |
1519b995 | 1125 | WARN(lvds_pipe_enabled(dev_priv, val, pipe), |
291906f1 | 1126 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1127 | pipe_name(pipe)); |
291906f1 JB |
1128 | |
1129 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); | |
1130 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); | |
1131 | assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); | |
1132 | } | |
1133 | ||
63d7bbe9 JB |
1134 | /** |
1135 | * intel_enable_pll - enable a PLL | |
1136 | * @dev_priv: i915 private structure | |
1137 | * @pipe: pipe PLL to enable | |
1138 | * | |
1139 | * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to | |
1140 | * make sure the PLL reg is writable first though, since the panel write | |
1141 | * protect mechanism may be enabled. | |
1142 | * | |
1143 | * Note! This is for pre-ILK only. | |
1144 | */ | |
1145 | static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1146 | { | |
1147 | int reg; | |
1148 | u32 val; | |
1149 | ||
1150 | /* No really, not for ILK+ */ | |
1151 | BUG_ON(dev_priv->info->gen >= 5); | |
1152 | ||
1153 | /* PLL is protected by panel, make sure we can write it */ | |
1154 | if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) | |
1155 | assert_panel_unlocked(dev_priv, pipe); | |
1156 | ||
1157 | reg = DPLL(pipe); | |
1158 | val = I915_READ(reg); | |
1159 | val |= DPLL_VCO_ENABLE; | |
1160 | ||
1161 | /* We do this three times for luck */ | |
1162 | I915_WRITE(reg, val); | |
1163 | POSTING_READ(reg); | |
1164 | udelay(150); /* wait for warmup */ | |
1165 | I915_WRITE(reg, val); | |
1166 | POSTING_READ(reg); | |
1167 | udelay(150); /* wait for warmup */ | |
1168 | I915_WRITE(reg, val); | |
1169 | POSTING_READ(reg); | |
1170 | udelay(150); /* wait for warmup */ | |
1171 | } | |
1172 | ||
1173 | /** | |
1174 | * intel_disable_pll - disable a PLL | |
1175 | * @dev_priv: i915 private structure | |
1176 | * @pipe: pipe PLL to disable | |
1177 | * | |
1178 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1179 | * | |
1180 | * Note! This is for pre-ILK only. | |
1181 | */ | |
1182 | static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1183 | { | |
1184 | int reg; | |
1185 | u32 val; | |
1186 | ||
1187 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1188 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1189 | return; | |
1190 | ||
1191 | /* Make sure the pipe isn't still relying on us */ | |
1192 | assert_pipe_disabled(dev_priv, pipe); | |
1193 | ||
1194 | reg = DPLL(pipe); | |
1195 | val = I915_READ(reg); | |
1196 | val &= ~DPLL_VCO_ENABLE; | |
1197 | I915_WRITE(reg, val); | |
1198 | POSTING_READ(reg); | |
1199 | } | |
1200 | ||
92f2584a JB |
1201 | /** |
1202 | * intel_enable_pch_pll - enable PCH PLL | |
1203 | * @dev_priv: i915 private structure | |
1204 | * @pipe: pipe PLL to enable | |
1205 | * | |
1206 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1207 | * drives the transcoder clock. | |
1208 | */ | |
1209 | static void intel_enable_pch_pll(struct drm_i915_private *dev_priv, | |
1210 | enum pipe pipe) | |
1211 | { | |
1212 | int reg; | |
1213 | u32 val; | |
1214 | ||
4c609cb8 JB |
1215 | if (pipe > 1) |
1216 | return; | |
1217 | ||
92f2584a JB |
1218 | /* PCH only available on ILK+ */ |
1219 | BUG_ON(dev_priv->info->gen < 5); | |
1220 | ||
1221 | /* PCH refclock must be enabled first */ | |
1222 | assert_pch_refclk_enabled(dev_priv); | |
1223 | ||
1224 | reg = PCH_DPLL(pipe); | |
1225 | val = I915_READ(reg); | |
1226 | val |= DPLL_VCO_ENABLE; | |
1227 | I915_WRITE(reg, val); | |
1228 | POSTING_READ(reg); | |
1229 | udelay(200); | |
1230 | } | |
1231 | ||
1232 | static void intel_disable_pch_pll(struct drm_i915_private *dev_priv, | |
1233 | enum pipe pipe) | |
1234 | { | |
1235 | int reg; | |
7a419866 JB |
1236 | u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL, |
1237 | pll_sel = TRANSC_DPLL_ENABLE; | |
92f2584a | 1238 | |
4c609cb8 JB |
1239 | if (pipe > 1) |
1240 | return; | |
1241 | ||
92f2584a JB |
1242 | /* PCH only available on ILK+ */ |
1243 | BUG_ON(dev_priv->info->gen < 5); | |
1244 | ||
1245 | /* Make sure transcoder isn't still depending on us */ | |
1246 | assert_transcoder_disabled(dev_priv, pipe); | |
1247 | ||
7a419866 JB |
1248 | if (pipe == 0) |
1249 | pll_sel |= TRANSC_DPLLA_SEL; | |
1250 | else if (pipe == 1) | |
1251 | pll_sel |= TRANSC_DPLLB_SEL; | |
1252 | ||
1253 | ||
1254 | if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel) | |
1255 | return; | |
1256 | ||
92f2584a JB |
1257 | reg = PCH_DPLL(pipe); |
1258 | val = I915_READ(reg); | |
1259 | val &= ~DPLL_VCO_ENABLE; | |
1260 | I915_WRITE(reg, val); | |
1261 | POSTING_READ(reg); | |
1262 | udelay(200); | |
1263 | } | |
1264 | ||
040484af JB |
1265 | static void intel_enable_transcoder(struct drm_i915_private *dev_priv, |
1266 | enum pipe pipe) | |
1267 | { | |
1268 | int reg; | |
5f7f726d | 1269 | u32 val, pipeconf_val; |
7c26e5c6 | 1270 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
040484af JB |
1271 | |
1272 | /* PCH only available on ILK+ */ | |
1273 | BUG_ON(dev_priv->info->gen < 5); | |
1274 | ||
1275 | /* Make sure PCH DPLL is enabled */ | |
1276 | assert_pch_pll_enabled(dev_priv, pipe); | |
1277 | ||
1278 | /* FDI must be feeding us bits for PCH ports */ | |
1279 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1280 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1281 | ||
1282 | reg = TRANSCONF(pipe); | |
1283 | val = I915_READ(reg); | |
5f7f726d | 1284 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1285 | |
1286 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1287 | /* | |
1288 | * make the BPC in transcoder be consistent with | |
1289 | * that in pipeconf reg. | |
1290 | */ | |
1291 | val &= ~PIPE_BPC_MASK; | |
5f7f726d | 1292 | val |= pipeconf_val & PIPE_BPC_MASK; |
e9bcff5c | 1293 | } |
5f7f726d PZ |
1294 | |
1295 | val &= ~TRANS_INTERLACE_MASK; | |
1296 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1297 | if (HAS_PCH_IBX(dev_priv->dev) && |
1298 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1299 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1300 | else | |
1301 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1302 | else |
1303 | val |= TRANS_PROGRESSIVE; | |
1304 | ||
040484af JB |
1305 | I915_WRITE(reg, val | TRANS_ENABLE); |
1306 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
1307 | DRM_ERROR("failed to enable transcoder %d\n", pipe); | |
1308 | } | |
1309 | ||
1310 | static void intel_disable_transcoder(struct drm_i915_private *dev_priv, | |
1311 | enum pipe pipe) | |
1312 | { | |
1313 | int reg; | |
1314 | u32 val; | |
1315 | ||
1316 | /* FDI relies on the transcoder */ | |
1317 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1318 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1319 | ||
291906f1 JB |
1320 | /* Ports must be off as well */ |
1321 | assert_pch_ports_disabled(dev_priv, pipe); | |
1322 | ||
040484af JB |
1323 | reg = TRANSCONF(pipe); |
1324 | val = I915_READ(reg); | |
1325 | val &= ~TRANS_ENABLE; | |
1326 | I915_WRITE(reg, val); | |
1327 | /* wait for PCH transcoder off, transcoder state */ | |
1328 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4c9c18c2 | 1329 | DRM_ERROR("failed to disable transcoder %d\n", pipe); |
040484af JB |
1330 | } |
1331 | ||
b24e7179 | 1332 | /** |
309cfea8 | 1333 | * intel_enable_pipe - enable a pipe, asserting requirements |
b24e7179 JB |
1334 | * @dev_priv: i915 private structure |
1335 | * @pipe: pipe to enable | |
040484af | 1336 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
b24e7179 JB |
1337 | * |
1338 | * Enable @pipe, making sure that various hardware specific requirements | |
1339 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | |
1340 | * | |
1341 | * @pipe should be %PIPE_A or %PIPE_B. | |
1342 | * | |
1343 | * Will wait until the pipe is actually running (i.e. first vblank) before | |
1344 | * returning. | |
1345 | */ | |
040484af JB |
1346 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, |
1347 | bool pch_port) | |
b24e7179 JB |
1348 | { |
1349 | int reg; | |
1350 | u32 val; | |
1351 | ||
1352 | /* | |
1353 | * A pipe without a PLL won't actually be able to drive bits from | |
1354 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1355 | * need the check. | |
1356 | */ | |
1357 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
1358 | assert_pll_enabled(dev_priv, pipe); | |
040484af JB |
1359 | else { |
1360 | if (pch_port) { | |
1361 | /* if driving the PCH, we need FDI enabled */ | |
1362 | assert_fdi_rx_pll_enabled(dev_priv, pipe); | |
1363 | assert_fdi_tx_pll_enabled(dev_priv, pipe); | |
1364 | } | |
1365 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1366 | } | |
b24e7179 JB |
1367 | |
1368 | reg = PIPECONF(pipe); | |
1369 | val = I915_READ(reg); | |
00d70b15 CW |
1370 | if (val & PIPECONF_ENABLE) |
1371 | return; | |
1372 | ||
1373 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
b24e7179 JB |
1374 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1375 | } | |
1376 | ||
1377 | /** | |
309cfea8 | 1378 | * intel_disable_pipe - disable a pipe, asserting requirements |
b24e7179 JB |
1379 | * @dev_priv: i915 private structure |
1380 | * @pipe: pipe to disable | |
1381 | * | |
1382 | * Disable @pipe, making sure that various hardware specific requirements | |
1383 | * are met, if applicable, e.g. plane disabled, panel fitter off, etc. | |
1384 | * | |
1385 | * @pipe should be %PIPE_A or %PIPE_B. | |
1386 | * | |
1387 | * Will wait until the pipe has shut down before returning. | |
1388 | */ | |
1389 | static void intel_disable_pipe(struct drm_i915_private *dev_priv, | |
1390 | enum pipe pipe) | |
1391 | { | |
1392 | int reg; | |
1393 | u32 val; | |
1394 | ||
1395 | /* | |
1396 | * Make sure planes won't keep trying to pump pixels to us, | |
1397 | * or we might hang the display. | |
1398 | */ | |
1399 | assert_planes_disabled(dev_priv, pipe); | |
1400 | ||
1401 | /* Don't disable pipe A or pipe A PLLs if needed */ | |
1402 | if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) | |
1403 | return; | |
1404 | ||
1405 | reg = PIPECONF(pipe); | |
1406 | val = I915_READ(reg); | |
00d70b15 CW |
1407 | if ((val & PIPECONF_ENABLE) == 0) |
1408 | return; | |
1409 | ||
1410 | I915_WRITE(reg, val & ~PIPECONF_ENABLE); | |
b24e7179 JB |
1411 | intel_wait_for_pipe_off(dev_priv->dev, pipe); |
1412 | } | |
1413 | ||
d74362c9 KP |
1414 | /* |
1415 | * Plane regs are double buffered, going from enabled->disabled needs a | |
1416 | * trigger in order to latch. The display address reg provides this. | |
1417 | */ | |
1418 | static void intel_flush_display_plane(struct drm_i915_private *dev_priv, | |
1419 | enum plane plane) | |
1420 | { | |
1421 | I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); | |
1422 | I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); | |
1423 | } | |
1424 | ||
b24e7179 JB |
1425 | /** |
1426 | * intel_enable_plane - enable a display plane on a given pipe | |
1427 | * @dev_priv: i915 private structure | |
1428 | * @plane: plane to enable | |
1429 | * @pipe: pipe being fed | |
1430 | * | |
1431 | * Enable @plane on @pipe, making sure that @pipe is running first. | |
1432 | */ | |
1433 | static void intel_enable_plane(struct drm_i915_private *dev_priv, | |
1434 | enum plane plane, enum pipe pipe) | |
1435 | { | |
1436 | int reg; | |
1437 | u32 val; | |
1438 | ||
1439 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
1440 | assert_pipe_enabled(dev_priv, pipe); | |
1441 | ||
1442 | reg = DSPCNTR(plane); | |
1443 | val = I915_READ(reg); | |
00d70b15 CW |
1444 | if (val & DISPLAY_PLANE_ENABLE) |
1445 | return; | |
1446 | ||
1447 | I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); | |
d74362c9 | 1448 | intel_flush_display_plane(dev_priv, plane); |
b24e7179 JB |
1449 | intel_wait_for_vblank(dev_priv->dev, pipe); |
1450 | } | |
1451 | ||
b24e7179 JB |
1452 | /** |
1453 | * intel_disable_plane - disable a display plane | |
1454 | * @dev_priv: i915 private structure | |
1455 | * @plane: plane to disable | |
1456 | * @pipe: pipe consuming the data | |
1457 | * | |
1458 | * Disable @plane; should be an independent operation. | |
1459 | */ | |
1460 | static void intel_disable_plane(struct drm_i915_private *dev_priv, | |
1461 | enum plane plane, enum pipe pipe) | |
1462 | { | |
1463 | int reg; | |
1464 | u32 val; | |
1465 | ||
1466 | reg = DSPCNTR(plane); | |
1467 | val = I915_READ(reg); | |
00d70b15 CW |
1468 | if ((val & DISPLAY_PLANE_ENABLE) == 0) |
1469 | return; | |
1470 | ||
1471 | I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); | |
b24e7179 JB |
1472 | intel_flush_display_plane(dev_priv, plane); |
1473 | intel_wait_for_vblank(dev_priv->dev, pipe); | |
1474 | } | |
1475 | ||
47a05eca | 1476 | static void disable_pch_dp(struct drm_i915_private *dev_priv, |
f0575e92 | 1477 | enum pipe pipe, int reg, u32 port_sel) |
47a05eca JB |
1478 | { |
1479 | u32 val = I915_READ(reg); | |
4e634389 | 1480 | if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) { |
f0575e92 | 1481 | DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe); |
47a05eca | 1482 | I915_WRITE(reg, val & ~DP_PORT_EN); |
f0575e92 | 1483 | } |
47a05eca JB |
1484 | } |
1485 | ||
1486 | static void disable_pch_hdmi(struct drm_i915_private *dev_priv, | |
1487 | enum pipe pipe, int reg) | |
1488 | { | |
1489 | u32 val = I915_READ(reg); | |
1519b995 | 1490 | if (hdmi_pipe_enabled(dev_priv, val, pipe)) { |
f0575e92 KP |
1491 | DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n", |
1492 | reg, pipe); | |
47a05eca | 1493 | I915_WRITE(reg, val & ~PORT_ENABLE); |
f0575e92 | 1494 | } |
47a05eca JB |
1495 | } |
1496 | ||
1497 | /* Disable any ports connected to this transcoder */ | |
1498 | static void intel_disable_pch_ports(struct drm_i915_private *dev_priv, | |
1499 | enum pipe pipe) | |
1500 | { | |
1501 | u32 reg, val; | |
1502 | ||
1503 | val = I915_READ(PCH_PP_CONTROL); | |
1504 | I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS); | |
1505 | ||
f0575e92 KP |
1506 | disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1507 | disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1508 | disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
47a05eca JB |
1509 | |
1510 | reg = PCH_ADPA; | |
1511 | val = I915_READ(reg); | |
1519b995 | 1512 | if (adpa_pipe_enabled(dev_priv, val, pipe)) |
47a05eca JB |
1513 | I915_WRITE(reg, val & ~ADPA_DAC_ENABLE); |
1514 | ||
1515 | reg = PCH_LVDS; | |
1516 | val = I915_READ(reg); | |
1519b995 KP |
1517 | if (lvds_pipe_enabled(dev_priv, val, pipe)) { |
1518 | DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val); | |
47a05eca JB |
1519 | I915_WRITE(reg, val & ~LVDS_PORT_EN); |
1520 | POSTING_READ(reg); | |
1521 | udelay(100); | |
1522 | } | |
1523 | ||
1524 | disable_pch_hdmi(dev_priv, pipe, HDMIB); | |
1525 | disable_pch_hdmi(dev_priv, pipe, HDMIC); | |
1526 | disable_pch_hdmi(dev_priv, pipe, HDMID); | |
1527 | } | |
1528 | ||
43a9539f CW |
1529 | static void i8xx_disable_fbc(struct drm_device *dev) |
1530 | { | |
1531 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1532 | u32 fbc_ctl; | |
1533 | ||
1534 | /* Disable compression */ | |
1535 | fbc_ctl = I915_READ(FBC_CONTROL); | |
1536 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
1537 | return; | |
1538 | ||
1539 | fbc_ctl &= ~FBC_CTL_EN; | |
1540 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
1541 | ||
1542 | /* Wait for compressing bit to clear */ | |
1543 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
1544 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
1545 | return; | |
1546 | } | |
1547 | ||
1548 | DRM_DEBUG_KMS("disabled FBC\n"); | |
1549 | } | |
1550 | ||
80824003 JB |
1551 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1552 | { | |
1553 | struct drm_device *dev = crtc->dev; | |
1554 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1555 | struct drm_framebuffer *fb = crtc->fb; | |
1556 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1557 | struct drm_i915_gem_object *obj = intel_fb->obj; |
80824003 | 1558 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
016b9b61 | 1559 | int cfb_pitch; |
80824003 JB |
1560 | int plane, i; |
1561 | u32 fbc_ctl, fbc_ctl2; | |
1562 | ||
016b9b61 | 1563 | cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; |
01f2c773 VS |
1564 | if (fb->pitches[0] < cfb_pitch) |
1565 | cfb_pitch = fb->pitches[0]; | |
80824003 JB |
1566 | |
1567 | /* FBC_CTL wants 64B units */ | |
016b9b61 CW |
1568 | cfb_pitch = (cfb_pitch / 64) - 1; |
1569 | plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; | |
80824003 JB |
1570 | |
1571 | /* Clear old tags */ | |
1572 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
1573 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
1574 | ||
1575 | /* Set it up... */ | |
de568510 CW |
1576 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; |
1577 | fbc_ctl2 |= plane; | |
80824003 JB |
1578 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
1579 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
1580 | ||
1581 | /* enable it... */ | |
1582 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; | |
ee25df2b | 1583 | if (IS_I945GM(dev)) |
49677901 | 1584 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
016b9b61 | 1585 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
80824003 | 1586 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; |
016b9b61 | 1587 | fbc_ctl |= obj->fence_reg; |
80824003 JB |
1588 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
1589 | ||
016b9b61 CW |
1590 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ", |
1591 | cfb_pitch, crtc->y, intel_crtc->plane); | |
80824003 JB |
1592 | } |
1593 | ||
ee5382ae | 1594 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
80824003 | 1595 | { |
80824003 JB |
1596 | struct drm_i915_private *dev_priv = dev->dev_private; |
1597 | ||
1598 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
1599 | } | |
1600 | ||
74dff282 JB |
1601 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1602 | { | |
1603 | struct drm_device *dev = crtc->dev; | |
1604 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1605 | struct drm_framebuffer *fb = crtc->fb; | |
1606 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1607 | struct drm_i915_gem_object *obj = intel_fb->obj; |
74dff282 | 1608 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1609 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
74dff282 JB |
1610 | unsigned long stall_watermark = 200; |
1611 | u32 dpfc_ctl; | |
1612 | ||
74dff282 | 1613 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; |
016b9b61 | 1614 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
de568510 | 1615 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); |
74dff282 | 1616 | |
74dff282 JB |
1617 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1618 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1619 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1620 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); | |
1621 | ||
1622 | /* enable it... */ | |
1623 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); | |
1624 | ||
28c97730 | 1625 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
74dff282 JB |
1626 | } |
1627 | ||
43a9539f | 1628 | static void g4x_disable_fbc(struct drm_device *dev) |
74dff282 JB |
1629 | { |
1630 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1631 | u32 dpfc_ctl; | |
1632 | ||
1633 | /* Disable compression */ | |
1634 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
bed4a673 CW |
1635 | if (dpfc_ctl & DPFC_CTL_EN) { |
1636 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1637 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
74dff282 | 1638 | |
bed4a673 CW |
1639 | DRM_DEBUG_KMS("disabled FBC\n"); |
1640 | } | |
74dff282 JB |
1641 | } |
1642 | ||
ee5382ae | 1643 | static bool g4x_fbc_enabled(struct drm_device *dev) |
74dff282 | 1644 | { |
74dff282 JB |
1645 | struct drm_i915_private *dev_priv = dev->dev_private; |
1646 | ||
1647 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
1648 | } | |
1649 | ||
4efe0708 JB |
1650 | static void sandybridge_blit_fbc_update(struct drm_device *dev) |
1651 | { | |
1652 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1653 | u32 blt_ecoskpd; | |
1654 | ||
1655 | /* Make sure blitter notifies FBC of writes */ | |
fcca7926 | 1656 | gen6_gt_force_wake_get(dev_priv); |
4efe0708 JB |
1657 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
1658 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << | |
1659 | GEN6_BLITTER_LOCK_SHIFT; | |
1660 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1661 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; | |
1662 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1663 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << | |
1664 | GEN6_BLITTER_LOCK_SHIFT); | |
1665 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
1666 | POSTING_READ(GEN6_BLITTER_ECOSKPD); | |
fcca7926 | 1667 | gen6_gt_force_wake_put(dev_priv); |
4efe0708 JB |
1668 | } |
1669 | ||
b52eb4dc ZY |
1670 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
1671 | { | |
1672 | struct drm_device *dev = crtc->dev; | |
1673 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1674 | struct drm_framebuffer *fb = crtc->fb; | |
1675 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1676 | struct drm_i915_gem_object *obj = intel_fb->obj; |
b52eb4dc | 1677 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5eddb70b | 1678 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; |
b52eb4dc ZY |
1679 | unsigned long stall_watermark = 200; |
1680 | u32 dpfc_ctl; | |
1681 | ||
bed4a673 | 1682 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
b52eb4dc ZY |
1683 | dpfc_ctl &= DPFC_RESERVED; |
1684 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); | |
9ce9d069 CW |
1685 | /* Set persistent mode for front-buffer rendering, ala X. */ |
1686 | dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; | |
016b9b61 | 1687 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); |
de568510 | 1688 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); |
b52eb4dc | 1689 | |
b52eb4dc ZY |
1690 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | |
1691 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
1692 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
1693 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); | |
05394f39 | 1694 | I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); |
b52eb4dc | 1695 | /* enable it... */ |
bed4a673 | 1696 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
b52eb4dc | 1697 | |
9c04f015 YL |
1698 | if (IS_GEN6(dev)) { |
1699 | I915_WRITE(SNB_DPFC_CTL_SA, | |
016b9b61 | 1700 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
9c04f015 | 1701 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
4efe0708 | 1702 | sandybridge_blit_fbc_update(dev); |
9c04f015 YL |
1703 | } |
1704 | ||
b52eb4dc ZY |
1705 | DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); |
1706 | } | |
1707 | ||
43a9539f | 1708 | static void ironlake_disable_fbc(struct drm_device *dev) |
b52eb4dc ZY |
1709 | { |
1710 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1711 | u32 dpfc_ctl; | |
1712 | ||
1713 | /* Disable compression */ | |
1714 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
bed4a673 CW |
1715 | if (dpfc_ctl & DPFC_CTL_EN) { |
1716 | dpfc_ctl &= ~DPFC_CTL_EN; | |
1717 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
b52eb4dc | 1718 | |
bed4a673 CW |
1719 | DRM_DEBUG_KMS("disabled FBC\n"); |
1720 | } | |
b52eb4dc ZY |
1721 | } |
1722 | ||
1723 | static bool ironlake_fbc_enabled(struct drm_device *dev) | |
1724 | { | |
1725 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1726 | ||
1727 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
1728 | } | |
1729 | ||
ee5382ae AJ |
1730 | bool intel_fbc_enabled(struct drm_device *dev) |
1731 | { | |
1732 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1733 | ||
1734 | if (!dev_priv->display.fbc_enabled) | |
1735 | return false; | |
1736 | ||
1737 | return dev_priv->display.fbc_enabled(dev); | |
1738 | } | |
1739 | ||
1630fe75 CW |
1740 | static void intel_fbc_work_fn(struct work_struct *__work) |
1741 | { | |
1742 | struct intel_fbc_work *work = | |
1743 | container_of(to_delayed_work(__work), | |
1744 | struct intel_fbc_work, work); | |
1745 | struct drm_device *dev = work->crtc->dev; | |
1746 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1747 | ||
1748 | mutex_lock(&dev->struct_mutex); | |
1749 | if (work == dev_priv->fbc_work) { | |
1750 | /* Double check that we haven't switched fb without cancelling | |
1751 | * the prior work. | |
1752 | */ | |
016b9b61 | 1753 | if (work->crtc->fb == work->fb) { |
1630fe75 CW |
1754 | dev_priv->display.enable_fbc(work->crtc, |
1755 | work->interval); | |
1756 | ||
016b9b61 CW |
1757 | dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane; |
1758 | dev_priv->cfb_fb = work->crtc->fb->base.id; | |
1759 | dev_priv->cfb_y = work->crtc->y; | |
1760 | } | |
1761 | ||
1630fe75 CW |
1762 | dev_priv->fbc_work = NULL; |
1763 | } | |
1764 | mutex_unlock(&dev->struct_mutex); | |
1765 | ||
1766 | kfree(work); | |
1767 | } | |
1768 | ||
1769 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) | |
1770 | { | |
1771 | if (dev_priv->fbc_work == NULL) | |
1772 | return; | |
1773 | ||
1774 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); | |
1775 | ||
1776 | /* Synchronisation is provided by struct_mutex and checking of | |
1777 | * dev_priv->fbc_work, so we can perform the cancellation | |
1778 | * entirely asynchronously. | |
1779 | */ | |
1780 | if (cancel_delayed_work(&dev_priv->fbc_work->work)) | |
1781 | /* tasklet was killed before being run, clean up */ | |
1782 | kfree(dev_priv->fbc_work); | |
1783 | ||
1784 | /* Mark the work as no longer wanted so that if it does | |
1785 | * wake-up (because the work was already running and waiting | |
1786 | * for our mutex), it will discover that is no longer | |
1787 | * necessary to run. | |
1788 | */ | |
1789 | dev_priv->fbc_work = NULL; | |
1790 | } | |
1791 | ||
43a9539f | 1792 | static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
ee5382ae | 1793 | { |
1630fe75 CW |
1794 | struct intel_fbc_work *work; |
1795 | struct drm_device *dev = crtc->dev; | |
1796 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee5382ae AJ |
1797 | |
1798 | if (!dev_priv->display.enable_fbc) | |
1799 | return; | |
1800 | ||
1630fe75 CW |
1801 | intel_cancel_fbc_work(dev_priv); |
1802 | ||
1803 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
1804 | if (work == NULL) { | |
1805 | dev_priv->display.enable_fbc(crtc, interval); | |
1806 | return; | |
1807 | } | |
1808 | ||
1809 | work->crtc = crtc; | |
1810 | work->fb = crtc->fb; | |
1811 | work->interval = interval; | |
1812 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); | |
1813 | ||
1814 | dev_priv->fbc_work = work; | |
1815 | ||
1816 | DRM_DEBUG_KMS("scheduling delayed FBC enable\n"); | |
1817 | ||
1818 | /* Delay the actual enabling to let pageflipping cease and the | |
016b9b61 CW |
1819 | * display to settle before starting the compression. Note that |
1820 | * this delay also serves a second purpose: it allows for a | |
1821 | * vblank to pass after disabling the FBC before we attempt | |
1822 | * to modify the control registers. | |
1630fe75 CW |
1823 | * |
1824 | * A more complicated solution would involve tracking vblanks | |
1825 | * following the termination of the page-flipping sequence | |
1826 | * and indeed performing the enable as a co-routine and not | |
1827 | * waiting synchronously upon the vblank. | |
1828 | */ | |
1829 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
ee5382ae AJ |
1830 | } |
1831 | ||
1832 | void intel_disable_fbc(struct drm_device *dev) | |
1833 | { | |
1834 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1835 | ||
1630fe75 CW |
1836 | intel_cancel_fbc_work(dev_priv); |
1837 | ||
ee5382ae AJ |
1838 | if (!dev_priv->display.disable_fbc) |
1839 | return; | |
1840 | ||
1841 | dev_priv->display.disable_fbc(dev); | |
016b9b61 | 1842 | dev_priv->cfb_plane = -1; |
ee5382ae AJ |
1843 | } |
1844 | ||
80824003 JB |
1845 | /** |
1846 | * intel_update_fbc - enable/disable FBC as needed | |
bed4a673 | 1847 | * @dev: the drm_device |
80824003 JB |
1848 | * |
1849 | * Set up the framebuffer compression hardware at mode set time. We | |
1850 | * enable it if possible: | |
1851 | * - plane A only (on pre-965) | |
1852 | * - no pixel mulitply/line duplication | |
1853 | * - no alpha buffer discard | |
1854 | * - no dual wide | |
1855 | * - framebuffer <= 2048 in width, 1536 in height | |
1856 | * | |
1857 | * We can't assume that any compression will take place (worst case), | |
1858 | * so the compressed buffer has to be the same size as the uncompressed | |
1859 | * one. It also must reside (along with the line length buffer) in | |
1860 | * stolen memory. | |
1861 | * | |
1862 | * We need to enable/disable FBC on a global basis. | |
1863 | */ | |
bed4a673 | 1864 | static void intel_update_fbc(struct drm_device *dev) |
80824003 | 1865 | { |
80824003 | 1866 | struct drm_i915_private *dev_priv = dev->dev_private; |
bed4a673 CW |
1867 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
1868 | struct intel_crtc *intel_crtc; | |
1869 | struct drm_framebuffer *fb; | |
80824003 | 1870 | struct intel_framebuffer *intel_fb; |
05394f39 | 1871 | struct drm_i915_gem_object *obj; |
cd0de039 | 1872 | int enable_fbc; |
9c928d16 JB |
1873 | |
1874 | DRM_DEBUG_KMS("\n"); | |
80824003 JB |
1875 | |
1876 | if (!i915_powersave) | |
1877 | return; | |
1878 | ||
ee5382ae | 1879 | if (!I915_HAS_FBC(dev)) |
e70236a8 JB |
1880 | return; |
1881 | ||
80824003 JB |
1882 | /* |
1883 | * If FBC is already on, we just have to verify that we can | |
1884 | * keep it that way... | |
1885 | * Need to disable if: | |
9c928d16 | 1886 | * - more than one pipe is active |
80824003 JB |
1887 | * - changing FBC params (stride, fence, mode) |
1888 | * - new fb is too large to fit in compressed buffer | |
1889 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
1890 | */ | |
9c928d16 | 1891 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { |
d210246a | 1892 | if (tmp_crtc->enabled && tmp_crtc->fb) { |
bed4a673 CW |
1893 | if (crtc) { |
1894 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
1895 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; | |
1896 | goto out_disable; | |
1897 | } | |
1898 | crtc = tmp_crtc; | |
1899 | } | |
9c928d16 | 1900 | } |
bed4a673 CW |
1901 | |
1902 | if (!crtc || crtc->fb == NULL) { | |
1903 | DRM_DEBUG_KMS("no output, disabling\n"); | |
1904 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; | |
9c928d16 JB |
1905 | goto out_disable; |
1906 | } | |
bed4a673 CW |
1907 | |
1908 | intel_crtc = to_intel_crtc(crtc); | |
1909 | fb = crtc->fb; | |
1910 | intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 1911 | obj = intel_fb->obj; |
bed4a673 | 1912 | |
cd0de039 KP |
1913 | enable_fbc = i915_enable_fbc; |
1914 | if (enable_fbc < 0) { | |
1915 | DRM_DEBUG_KMS("fbc set to per-chip default\n"); | |
1916 | enable_fbc = 1; | |
d56d8b28 | 1917 | if (INTEL_INFO(dev)->gen <= 6) |
cd0de039 KP |
1918 | enable_fbc = 0; |
1919 | } | |
1920 | if (!enable_fbc) { | |
1921 | DRM_DEBUG_KMS("fbc disabled per module param\n"); | |
c1a9f047 JB |
1922 | dev_priv->no_fbc_reason = FBC_MODULE_PARAM; |
1923 | goto out_disable; | |
1924 | } | |
05394f39 | 1925 | if (intel_fb->obj->base.size > dev_priv->cfb_size) { |
28c97730 | 1926 | DRM_DEBUG_KMS("framebuffer too large, disabling " |
5eddb70b | 1927 | "compression\n"); |
b5e50c3f | 1928 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; |
80824003 JB |
1929 | goto out_disable; |
1930 | } | |
bed4a673 CW |
1931 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
1932 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { | |
28c97730 | 1933 | DRM_DEBUG_KMS("mode incompatible with compression, " |
5eddb70b | 1934 | "disabling\n"); |
b5e50c3f | 1935 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; |
80824003 JB |
1936 | goto out_disable; |
1937 | } | |
bed4a673 CW |
1938 | if ((crtc->mode.hdisplay > 2048) || |
1939 | (crtc->mode.vdisplay > 1536)) { | |
28c97730 | 1940 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
b5e50c3f | 1941 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; |
80824003 JB |
1942 | goto out_disable; |
1943 | } | |
bed4a673 | 1944 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { |
28c97730 | 1945 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); |
b5e50c3f | 1946 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; |
80824003 JB |
1947 | goto out_disable; |
1948 | } | |
de568510 CW |
1949 | |
1950 | /* The use of a CPU fence is mandatory in order to detect writes | |
1951 | * by the CPU to the scanout and trigger updates to the FBC. | |
1952 | */ | |
1953 | if (obj->tiling_mode != I915_TILING_X || | |
1954 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
1955 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); | |
b5e50c3f | 1956 | dev_priv->no_fbc_reason = FBC_NOT_TILED; |
80824003 JB |
1957 | goto out_disable; |
1958 | } | |
1959 | ||
c924b934 JW |
1960 | /* If the kernel debugger is active, always disable compression */ |
1961 | if (in_dbg_master()) | |
1962 | goto out_disable; | |
1963 | ||
016b9b61 CW |
1964 | /* If the scanout has not changed, don't modify the FBC settings. |
1965 | * Note that we make the fundamental assumption that the fb->obj | |
1966 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
1967 | * without first being decoupled from the scanout and FBC disabled. | |
1968 | */ | |
1969 | if (dev_priv->cfb_plane == intel_crtc->plane && | |
1970 | dev_priv->cfb_fb == fb->base.id && | |
1971 | dev_priv->cfb_y == crtc->y) | |
1972 | return; | |
1973 | ||
1974 | if (intel_fbc_enabled(dev)) { | |
1975 | /* We update FBC along two paths, after changing fb/crtc | |
1976 | * configuration (modeswitching) and after page-flipping | |
1977 | * finishes. For the latter, we know that not only did | |
1978 | * we disable the FBC at the start of the page-flip | |
1979 | * sequence, but also more than one vblank has passed. | |
1980 | * | |
1981 | * For the former case of modeswitching, it is possible | |
1982 | * to switch between two FBC valid configurations | |
1983 | * instantaneously so we do need to disable the FBC | |
1984 | * before we can modify its control registers. We also | |
1985 | * have to wait for the next vblank for that to take | |
1986 | * effect. However, since we delay enabling FBC we can | |
1987 | * assume that a vblank has passed since disabling and | |
1988 | * that we can safely alter the registers in the deferred | |
1989 | * callback. | |
1990 | * | |
1991 | * In the scenario that we go from a valid to invalid | |
1992 | * and then back to valid FBC configuration we have | |
1993 | * no strict enforcement that a vblank occurred since | |
1994 | * disabling the FBC. However, along all current pipe | |
1995 | * disabling paths we do need to wait for a vblank at | |
1996 | * some point. And we wait before enabling FBC anyway. | |
1997 | */ | |
1998 | DRM_DEBUG_KMS("disabling active FBC for update\n"); | |
1999 | intel_disable_fbc(dev); | |
2000 | } | |
2001 | ||
bed4a673 | 2002 | intel_enable_fbc(crtc, 500); |
80824003 JB |
2003 | return; |
2004 | ||
2005 | out_disable: | |
80824003 | 2006 | /* Multiple disables should be harmless */ |
a939406f CW |
2007 | if (intel_fbc_enabled(dev)) { |
2008 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
ee5382ae | 2009 | intel_disable_fbc(dev); |
a939406f | 2010 | } |
80824003 JB |
2011 | } |
2012 | ||
127bd2ac | 2013 | int |
48b956c5 | 2014 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 2015 | struct drm_i915_gem_object *obj, |
919926ae | 2016 | struct intel_ring_buffer *pipelined) |
6b95a207 | 2017 | { |
ce453d81 | 2018 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
2019 | u32 alignment; |
2020 | int ret; | |
2021 | ||
05394f39 | 2022 | switch (obj->tiling_mode) { |
6b95a207 | 2023 | case I915_TILING_NONE: |
534843da CW |
2024 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
2025 | alignment = 128 * 1024; | |
a6c45cf0 | 2026 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2027 | alignment = 4 * 1024; |
2028 | else | |
2029 | alignment = 64 * 1024; | |
6b95a207 KH |
2030 | break; |
2031 | case I915_TILING_X: | |
2032 | /* pin() will align the object as required by fence */ | |
2033 | alignment = 0; | |
2034 | break; | |
2035 | case I915_TILING_Y: | |
2036 | /* FIXME: Is this true? */ | |
2037 | DRM_ERROR("Y tiled not allowed for scan out buffers\n"); | |
2038 | return -EINVAL; | |
2039 | default: | |
2040 | BUG(); | |
2041 | } | |
2042 | ||
ce453d81 | 2043 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 2044 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 2045 | if (ret) |
ce453d81 | 2046 | goto err_interruptible; |
6b95a207 KH |
2047 | |
2048 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2049 | * fence, whereas 965+ only requires a fence if using | |
2050 | * framebuffer compression. For simplicity, we always install | |
2051 | * a fence as the cost is not that onerous. | |
2052 | */ | |
05394f39 | 2053 | if (obj->tiling_mode != I915_TILING_NONE) { |
ce453d81 | 2054 | ret = i915_gem_object_get_fence(obj, pipelined); |
48b956c5 CW |
2055 | if (ret) |
2056 | goto err_unpin; | |
1690e1eb CW |
2057 | |
2058 | i915_gem_object_pin_fence(obj); | |
6b95a207 KH |
2059 | } |
2060 | ||
ce453d81 | 2061 | dev_priv->mm.interruptible = true; |
6b95a207 | 2062 | return 0; |
48b956c5 CW |
2063 | |
2064 | err_unpin: | |
2065 | i915_gem_object_unpin(obj); | |
ce453d81 CW |
2066 | err_interruptible: |
2067 | dev_priv->mm.interruptible = true; | |
48b956c5 | 2068 | return ret; |
6b95a207 KH |
2069 | } |
2070 | ||
1690e1eb CW |
2071 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2072 | { | |
2073 | i915_gem_object_unpin_fence(obj); | |
2074 | i915_gem_object_unpin(obj); | |
2075 | } | |
2076 | ||
17638cd6 JB |
2077 | static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
2078 | int x, int y) | |
81255565 JB |
2079 | { |
2080 | struct drm_device *dev = crtc->dev; | |
2081 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2082 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2083 | struct intel_framebuffer *intel_fb; | |
05394f39 | 2084 | struct drm_i915_gem_object *obj; |
81255565 JB |
2085 | int plane = intel_crtc->plane; |
2086 | unsigned long Start, Offset; | |
81255565 | 2087 | u32 dspcntr; |
5eddb70b | 2088 | u32 reg; |
81255565 JB |
2089 | |
2090 | switch (plane) { | |
2091 | case 0: | |
2092 | case 1: | |
2093 | break; | |
2094 | default: | |
2095 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2096 | return -EINVAL; | |
2097 | } | |
2098 | ||
2099 | intel_fb = to_intel_framebuffer(fb); | |
2100 | obj = intel_fb->obj; | |
81255565 | 2101 | |
5eddb70b CW |
2102 | reg = DSPCNTR(plane); |
2103 | dspcntr = I915_READ(reg); | |
81255565 JB |
2104 | /* Mask out pixel format bits in case we change it */ |
2105 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
2106 | switch (fb->bits_per_pixel) { | |
2107 | case 8: | |
2108 | dspcntr |= DISPPLANE_8BPP; | |
2109 | break; | |
2110 | case 16: | |
2111 | if (fb->depth == 15) | |
2112 | dspcntr |= DISPPLANE_15_16BPP; | |
2113 | else | |
2114 | dspcntr |= DISPPLANE_16BPP; | |
2115 | break; | |
2116 | case 24: | |
2117 | case 32: | |
2118 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
2119 | break; | |
2120 | default: | |
17638cd6 | 2121 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); |
81255565 JB |
2122 | return -EINVAL; |
2123 | } | |
a6c45cf0 | 2124 | if (INTEL_INFO(dev)->gen >= 4) { |
05394f39 | 2125 | if (obj->tiling_mode != I915_TILING_NONE) |
81255565 JB |
2126 | dspcntr |= DISPPLANE_TILED; |
2127 | else | |
2128 | dspcntr &= ~DISPPLANE_TILED; | |
2129 | } | |
2130 | ||
5eddb70b | 2131 | I915_WRITE(reg, dspcntr); |
81255565 | 2132 | |
05394f39 | 2133 | Start = obj->gtt_offset; |
01f2c773 | 2134 | Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
81255565 | 2135 | |
4e6cfefc | 2136 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
01f2c773 VS |
2137 | Start, Offset, x, y, fb->pitches[0]); |
2138 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); | |
a6c45cf0 | 2139 | if (INTEL_INFO(dev)->gen >= 4) { |
5eddb70b CW |
2140 | I915_WRITE(DSPSURF(plane), Start); |
2141 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2142 | I915_WRITE(DSPADDR(plane), Offset); | |
2143 | } else | |
2144 | I915_WRITE(DSPADDR(plane), Start + Offset); | |
2145 | POSTING_READ(reg); | |
81255565 | 2146 | |
17638cd6 JB |
2147 | return 0; |
2148 | } | |
2149 | ||
2150 | static int ironlake_update_plane(struct drm_crtc *crtc, | |
2151 | struct drm_framebuffer *fb, int x, int y) | |
2152 | { | |
2153 | struct drm_device *dev = crtc->dev; | |
2154 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2155 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2156 | struct intel_framebuffer *intel_fb; | |
2157 | struct drm_i915_gem_object *obj; | |
2158 | int plane = intel_crtc->plane; | |
2159 | unsigned long Start, Offset; | |
2160 | u32 dspcntr; | |
2161 | u32 reg; | |
2162 | ||
2163 | switch (plane) { | |
2164 | case 0: | |
2165 | case 1: | |
27f8227b | 2166 | case 2: |
17638cd6 JB |
2167 | break; |
2168 | default: | |
2169 | DRM_ERROR("Can't update plane %d in SAREA\n", plane); | |
2170 | return -EINVAL; | |
2171 | } | |
2172 | ||
2173 | intel_fb = to_intel_framebuffer(fb); | |
2174 | obj = intel_fb->obj; | |
2175 | ||
2176 | reg = DSPCNTR(plane); | |
2177 | dspcntr = I915_READ(reg); | |
2178 | /* Mask out pixel format bits in case we change it */ | |
2179 | dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; | |
2180 | switch (fb->bits_per_pixel) { | |
2181 | case 8: | |
2182 | dspcntr |= DISPPLANE_8BPP; | |
2183 | break; | |
2184 | case 16: | |
2185 | if (fb->depth != 16) | |
2186 | return -EINVAL; | |
2187 | ||
2188 | dspcntr |= DISPPLANE_16BPP; | |
2189 | break; | |
2190 | case 24: | |
2191 | case 32: | |
2192 | if (fb->depth == 24) | |
2193 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | |
2194 | else if (fb->depth == 30) | |
2195 | dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA; | |
2196 | else | |
2197 | return -EINVAL; | |
2198 | break; | |
2199 | default: | |
2200 | DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel); | |
2201 | return -EINVAL; | |
2202 | } | |
2203 | ||
2204 | if (obj->tiling_mode != I915_TILING_NONE) | |
2205 | dspcntr |= DISPPLANE_TILED; | |
2206 | else | |
2207 | dspcntr &= ~DISPPLANE_TILED; | |
2208 | ||
2209 | /* must disable */ | |
2210 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2211 | ||
2212 | I915_WRITE(reg, dspcntr); | |
2213 | ||
2214 | Start = obj->gtt_offset; | |
01f2c773 | 2215 | Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); |
17638cd6 JB |
2216 | |
2217 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", | |
01f2c773 VS |
2218 | Start, Offset, x, y, fb->pitches[0]); |
2219 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); | |
17638cd6 JB |
2220 | I915_WRITE(DSPSURF(plane), Start); |
2221 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2222 | I915_WRITE(DSPADDR(plane), Offset); | |
2223 | POSTING_READ(reg); | |
2224 | ||
2225 | return 0; | |
2226 | } | |
2227 | ||
2228 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2229 | static int | |
2230 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2231 | int x, int y, enum mode_set_atomic state) | |
2232 | { | |
2233 | struct drm_device *dev = crtc->dev; | |
2234 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2235 | int ret; | |
2236 | ||
2237 | ret = dev_priv->display.update_plane(crtc, fb, x, y); | |
2238 | if (ret) | |
2239 | return ret; | |
2240 | ||
bed4a673 | 2241 | intel_update_fbc(dev); |
3dec0095 | 2242 | intel_increase_pllclock(crtc); |
81255565 JB |
2243 | |
2244 | return 0; | |
2245 | } | |
2246 | ||
5c3b82e2 | 2247 | static int |
3c4fdcfb KH |
2248 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
2249 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
2250 | { |
2251 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
2252 | struct drm_i915_master_private *master_priv; |
2253 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5c3b82e2 | 2254 | int ret; |
79e53945 JB |
2255 | |
2256 | /* no fb bound */ | |
2257 | if (!crtc->fb) { | |
a5071c2f | 2258 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2259 | return 0; |
2260 | } | |
2261 | ||
265db958 | 2262 | switch (intel_crtc->plane) { |
5c3b82e2 CW |
2263 | case 0: |
2264 | case 1: | |
2265 | break; | |
27f8227b JB |
2266 | case 2: |
2267 | if (IS_IVYBRIDGE(dev)) | |
2268 | break; | |
2269 | /* fall through otherwise */ | |
5c3b82e2 | 2270 | default: |
a5071c2f | 2271 | DRM_ERROR("no plane for crtc\n"); |
5c3b82e2 | 2272 | return -EINVAL; |
79e53945 JB |
2273 | } |
2274 | ||
5c3b82e2 | 2275 | mutex_lock(&dev->struct_mutex); |
265db958 CW |
2276 | ret = intel_pin_and_fence_fb_obj(dev, |
2277 | to_intel_framebuffer(crtc->fb)->obj, | |
919926ae | 2278 | NULL); |
5c3b82e2 CW |
2279 | if (ret != 0) { |
2280 | mutex_unlock(&dev->struct_mutex); | |
a5071c2f | 2281 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2282 | return ret; |
2283 | } | |
79e53945 | 2284 | |
265db958 | 2285 | if (old_fb) { |
e6c3a2a6 | 2286 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 2287 | struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; |
265db958 | 2288 | |
e6c3a2a6 | 2289 | wait_event(dev_priv->pending_flip_queue, |
01eec727 | 2290 | atomic_read(&dev_priv->mm.wedged) || |
05394f39 | 2291 | atomic_read(&obj->pending_flip) == 0); |
85345517 CW |
2292 | |
2293 | /* Big Hammer, we also need to ensure that any pending | |
2294 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2295 | * current scanout is retired before unpinning the old | |
2296 | * framebuffer. | |
01eec727 CW |
2297 | * |
2298 | * This should only fail upon a hung GPU, in which case we | |
2299 | * can safely continue. | |
85345517 | 2300 | */ |
a8198eea | 2301 | ret = i915_gem_object_finish_gpu(obj); |
01eec727 | 2302 | (void) ret; |
265db958 CW |
2303 | } |
2304 | ||
21c74a8e JW |
2305 | ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y, |
2306 | LEAVE_ATOMIC_MODE_SET); | |
4e6cfefc | 2307 | if (ret) { |
1690e1eb | 2308 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
5c3b82e2 | 2309 | mutex_unlock(&dev->struct_mutex); |
a5071c2f | 2310 | DRM_ERROR("failed to update base address\n"); |
4e6cfefc | 2311 | return ret; |
79e53945 | 2312 | } |
3c4fdcfb | 2313 | |
b7f1de28 CW |
2314 | if (old_fb) { |
2315 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1690e1eb | 2316 | intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); |
b7f1de28 | 2317 | } |
652c393a | 2318 | |
5c3b82e2 | 2319 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
2320 | |
2321 | if (!dev->primary->master) | |
5c3b82e2 | 2322 | return 0; |
79e53945 JB |
2323 | |
2324 | master_priv = dev->primary->master->driver_priv; | |
2325 | if (!master_priv->sarea_priv) | |
5c3b82e2 | 2326 | return 0; |
79e53945 | 2327 | |
265db958 | 2328 | if (intel_crtc->pipe) { |
79e53945 JB |
2329 | master_priv->sarea_priv->pipeB_x = x; |
2330 | master_priv->sarea_priv->pipeB_y = y; | |
5c3b82e2 CW |
2331 | } else { |
2332 | master_priv->sarea_priv->pipeA_x = x; | |
2333 | master_priv->sarea_priv->pipeA_y = y; | |
79e53945 | 2334 | } |
5c3b82e2 CW |
2335 | |
2336 | return 0; | |
79e53945 JB |
2337 | } |
2338 | ||
5eddb70b | 2339 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
32f9d658 ZW |
2340 | { |
2341 | struct drm_device *dev = crtc->dev; | |
2342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2343 | u32 dpa_ctl; | |
2344 | ||
28c97730 | 2345 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
32f9d658 ZW |
2346 | dpa_ctl = I915_READ(DP_A); |
2347 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
2348 | ||
2349 | if (clock < 200000) { | |
2350 | u32 temp; | |
2351 | dpa_ctl |= DP_PLL_FREQ_160MHZ; | |
2352 | /* workaround for 160Mhz: | |
2353 | 1) program 0x4600c bits 15:0 = 0x8124 | |
2354 | 2) program 0x46010 bit 0 = 1 | |
2355 | 3) program 0x46034 bit 24 = 1 | |
2356 | 4) program 0x64000 bit 14 = 1 | |
2357 | */ | |
2358 | temp = I915_READ(0x4600c); | |
2359 | temp &= 0xffff0000; | |
2360 | I915_WRITE(0x4600c, temp | 0x8124); | |
2361 | ||
2362 | temp = I915_READ(0x46010); | |
2363 | I915_WRITE(0x46010, temp | 1); | |
2364 | ||
2365 | temp = I915_READ(0x46034); | |
2366 | I915_WRITE(0x46034, temp | (1 << 24)); | |
2367 | } else { | |
2368 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
2369 | } | |
2370 | I915_WRITE(DP_A, dpa_ctl); | |
2371 | ||
5eddb70b | 2372 | POSTING_READ(DP_A); |
32f9d658 ZW |
2373 | udelay(500); |
2374 | } | |
2375 | ||
5e84e1a4 ZW |
2376 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2377 | { | |
2378 | struct drm_device *dev = crtc->dev; | |
2379 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2380 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2381 | int pipe = intel_crtc->pipe; | |
2382 | u32 reg, temp; | |
2383 | ||
2384 | /* enable normal train */ | |
2385 | reg = FDI_TX_CTL(pipe); | |
2386 | temp = I915_READ(reg); | |
61e499bf | 2387 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2388 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2389 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2390 | } else { |
2391 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2392 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2393 | } |
5e84e1a4 ZW |
2394 | I915_WRITE(reg, temp); |
2395 | ||
2396 | reg = FDI_RX_CTL(pipe); | |
2397 | temp = I915_READ(reg); | |
2398 | if (HAS_PCH_CPT(dev)) { | |
2399 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2400 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2401 | } else { | |
2402 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2403 | temp |= FDI_LINK_TRAIN_NONE; | |
2404 | } | |
2405 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2406 | ||
2407 | /* wait one idle pattern time */ | |
2408 | POSTING_READ(reg); | |
2409 | udelay(1000); | |
357555c0 JB |
2410 | |
2411 | /* IVB wants error correction enabled */ | |
2412 | if (IS_IVYBRIDGE(dev)) | |
2413 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2414 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2415 | } |
2416 | ||
291427f5 JB |
2417 | static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe) |
2418 | { | |
2419 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2420 | u32 flags = I915_READ(SOUTH_CHICKEN1); | |
2421 | ||
2422 | flags |= FDI_PHASE_SYNC_OVR(pipe); | |
2423 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */ | |
2424 | flags |= FDI_PHASE_SYNC_EN(pipe); | |
2425 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */ | |
2426 | POSTING_READ(SOUTH_CHICKEN1); | |
2427 | } | |
2428 | ||
8db9d77b ZW |
2429 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2430 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2431 | { | |
2432 | struct drm_device *dev = crtc->dev; | |
2433 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2434 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2435 | int pipe = intel_crtc->pipe; | |
0fc932b8 | 2436 | int plane = intel_crtc->plane; |
5eddb70b | 2437 | u32 reg, temp, tries; |
8db9d77b | 2438 | |
0fc932b8 JB |
2439 | /* FDI needs bits from pipe & plane first */ |
2440 | assert_pipe_enabled(dev_priv, pipe); | |
2441 | assert_plane_enabled(dev_priv, plane); | |
2442 | ||
e1a44743 AJ |
2443 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2444 | for train result */ | |
5eddb70b CW |
2445 | reg = FDI_RX_IMR(pipe); |
2446 | temp = I915_READ(reg); | |
e1a44743 AJ |
2447 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2448 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2449 | I915_WRITE(reg, temp); |
2450 | I915_READ(reg); | |
e1a44743 AJ |
2451 | udelay(150); |
2452 | ||
8db9d77b | 2453 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2454 | reg = FDI_TX_CTL(pipe); |
2455 | temp = I915_READ(reg); | |
77ffb597 AJ |
2456 | temp &= ~(7 << 19); |
2457 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2458 | temp &= ~FDI_LINK_TRAIN_NONE; |
2459 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2460 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2461 | |
5eddb70b CW |
2462 | reg = FDI_RX_CTL(pipe); |
2463 | temp = I915_READ(reg); | |
8db9d77b ZW |
2464 | temp &= ~FDI_LINK_TRAIN_NONE; |
2465 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2466 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2467 | ||
2468 | POSTING_READ(reg); | |
8db9d77b ZW |
2469 | udelay(150); |
2470 | ||
5b2adf89 | 2471 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
6f06ce18 JB |
2472 | if (HAS_PCH_IBX(dev)) { |
2473 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
2474 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
2475 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
2476 | } | |
5b2adf89 | 2477 | |
5eddb70b | 2478 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2479 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2480 | temp = I915_READ(reg); |
8db9d77b ZW |
2481 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2482 | ||
2483 | if ((temp & FDI_RX_BIT_LOCK)) { | |
2484 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 2485 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2486 | break; |
2487 | } | |
8db9d77b | 2488 | } |
e1a44743 | 2489 | if (tries == 5) |
5eddb70b | 2490 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2491 | |
2492 | /* Train 2 */ | |
5eddb70b CW |
2493 | reg = FDI_TX_CTL(pipe); |
2494 | temp = I915_READ(reg); | |
8db9d77b ZW |
2495 | temp &= ~FDI_LINK_TRAIN_NONE; |
2496 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2497 | I915_WRITE(reg, temp); |
8db9d77b | 2498 | |
5eddb70b CW |
2499 | reg = FDI_RX_CTL(pipe); |
2500 | temp = I915_READ(reg); | |
8db9d77b ZW |
2501 | temp &= ~FDI_LINK_TRAIN_NONE; |
2502 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 2503 | I915_WRITE(reg, temp); |
8db9d77b | 2504 | |
5eddb70b CW |
2505 | POSTING_READ(reg); |
2506 | udelay(150); | |
8db9d77b | 2507 | |
5eddb70b | 2508 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 2509 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 2510 | temp = I915_READ(reg); |
8db9d77b ZW |
2511 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2512 | ||
2513 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2514 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2515 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2516 | break; | |
2517 | } | |
8db9d77b | 2518 | } |
e1a44743 | 2519 | if (tries == 5) |
5eddb70b | 2520 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2521 | |
2522 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 2523 | |
8db9d77b ZW |
2524 | } |
2525 | ||
0206e353 | 2526 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
2527 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
2528 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
2529 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
2530 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
2531 | }; | |
2532 | ||
2533 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
2534 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
2535 | { | |
2536 | struct drm_device *dev = crtc->dev; | |
2537 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2538 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2539 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2540 | u32 reg, temp, i; |
8db9d77b | 2541 | |
e1a44743 AJ |
2542 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2543 | for train result */ | |
5eddb70b CW |
2544 | reg = FDI_RX_IMR(pipe); |
2545 | temp = I915_READ(reg); | |
e1a44743 AJ |
2546 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2547 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2548 | I915_WRITE(reg, temp); |
2549 | ||
2550 | POSTING_READ(reg); | |
e1a44743 AJ |
2551 | udelay(150); |
2552 | ||
8db9d77b | 2553 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2554 | reg = FDI_TX_CTL(pipe); |
2555 | temp = I915_READ(reg); | |
77ffb597 AJ |
2556 | temp &= ~(7 << 19); |
2557 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
8db9d77b ZW |
2558 | temp &= ~FDI_LINK_TRAIN_NONE; |
2559 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2560 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2561 | /* SNB-B */ | |
2562 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 2563 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2564 | |
5eddb70b CW |
2565 | reg = FDI_RX_CTL(pipe); |
2566 | temp = I915_READ(reg); | |
8db9d77b ZW |
2567 | if (HAS_PCH_CPT(dev)) { |
2568 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2569 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2570 | } else { | |
2571 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2572 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2573 | } | |
5eddb70b CW |
2574 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2575 | ||
2576 | POSTING_READ(reg); | |
8db9d77b ZW |
2577 | udelay(150); |
2578 | ||
291427f5 JB |
2579 | if (HAS_PCH_CPT(dev)) |
2580 | cpt_phase_pointer_enable(dev, pipe); | |
2581 | ||
0206e353 | 2582 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2583 | reg = FDI_TX_CTL(pipe); |
2584 | temp = I915_READ(reg); | |
8db9d77b ZW |
2585 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2586 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2587 | I915_WRITE(reg, temp); |
2588 | ||
2589 | POSTING_READ(reg); | |
8db9d77b ZW |
2590 | udelay(500); |
2591 | ||
5eddb70b CW |
2592 | reg = FDI_RX_IIR(pipe); |
2593 | temp = I915_READ(reg); | |
8db9d77b ZW |
2594 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2595 | ||
2596 | if (temp & FDI_RX_BIT_LOCK) { | |
5eddb70b | 2597 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
2598 | DRM_DEBUG_KMS("FDI train 1 done.\n"); |
2599 | break; | |
2600 | } | |
2601 | } | |
2602 | if (i == 4) | |
5eddb70b | 2603 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
2604 | |
2605 | /* Train 2 */ | |
5eddb70b CW |
2606 | reg = FDI_TX_CTL(pipe); |
2607 | temp = I915_READ(reg); | |
8db9d77b ZW |
2608 | temp &= ~FDI_LINK_TRAIN_NONE; |
2609 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2610 | if (IS_GEN6(dev)) { | |
2611 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2612 | /* SNB-B */ | |
2613 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2614 | } | |
5eddb70b | 2615 | I915_WRITE(reg, temp); |
8db9d77b | 2616 | |
5eddb70b CW |
2617 | reg = FDI_RX_CTL(pipe); |
2618 | temp = I915_READ(reg); | |
8db9d77b ZW |
2619 | if (HAS_PCH_CPT(dev)) { |
2620 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2621 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2622 | } else { | |
2623 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2624 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
2625 | } | |
5eddb70b CW |
2626 | I915_WRITE(reg, temp); |
2627 | ||
2628 | POSTING_READ(reg); | |
8db9d77b ZW |
2629 | udelay(150); |
2630 | ||
0206e353 | 2631 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
2632 | reg = FDI_TX_CTL(pipe); |
2633 | temp = I915_READ(reg); | |
8db9d77b ZW |
2634 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
2635 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
2636 | I915_WRITE(reg, temp); |
2637 | ||
2638 | POSTING_READ(reg); | |
8db9d77b ZW |
2639 | udelay(500); |
2640 | ||
5eddb70b CW |
2641 | reg = FDI_RX_IIR(pipe); |
2642 | temp = I915_READ(reg); | |
8db9d77b ZW |
2643 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
2644 | ||
2645 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 2646 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
2647 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
2648 | break; | |
2649 | } | |
2650 | } | |
2651 | if (i == 4) | |
5eddb70b | 2652 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
2653 | |
2654 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2655 | } | |
2656 | ||
357555c0 JB |
2657 | /* Manual link training for Ivy Bridge A0 parts */ |
2658 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
2659 | { | |
2660 | struct drm_device *dev = crtc->dev; | |
2661 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2662 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2663 | int pipe = intel_crtc->pipe; | |
2664 | u32 reg, temp, i; | |
2665 | ||
2666 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
2667 | for train result */ | |
2668 | reg = FDI_RX_IMR(pipe); | |
2669 | temp = I915_READ(reg); | |
2670 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
2671 | temp &= ~FDI_RX_BIT_LOCK; | |
2672 | I915_WRITE(reg, temp); | |
2673 | ||
2674 | POSTING_READ(reg); | |
2675 | udelay(150); | |
2676 | ||
2677 | /* enable CPU FDI TX and PCH FDI RX */ | |
2678 | reg = FDI_TX_CTL(pipe); | |
2679 | temp = I915_READ(reg); | |
2680 | temp &= ~(7 << 19); | |
2681 | temp |= (intel_crtc->fdi_lanes - 1) << 19; | |
2682 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
2683 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
2684 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2685 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
c4f9c4c2 | 2686 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2687 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
2688 | ||
2689 | reg = FDI_RX_CTL(pipe); | |
2690 | temp = I915_READ(reg); | |
2691 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
2692 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2693 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
c4f9c4c2 | 2694 | temp |= FDI_COMPOSITE_SYNC; |
357555c0 JB |
2695 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2696 | ||
2697 | POSTING_READ(reg); | |
2698 | udelay(150); | |
2699 | ||
291427f5 JB |
2700 | if (HAS_PCH_CPT(dev)) |
2701 | cpt_phase_pointer_enable(dev, pipe); | |
2702 | ||
0206e353 | 2703 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2704 | reg = FDI_TX_CTL(pipe); |
2705 | temp = I915_READ(reg); | |
2706 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2707 | temp |= snb_b_fdi_train_param[i]; | |
2708 | I915_WRITE(reg, temp); | |
2709 | ||
2710 | POSTING_READ(reg); | |
2711 | udelay(500); | |
2712 | ||
2713 | reg = FDI_RX_IIR(pipe); | |
2714 | temp = I915_READ(reg); | |
2715 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2716 | ||
2717 | if (temp & FDI_RX_BIT_LOCK || | |
2718 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
2719 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
2720 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
2721 | break; | |
2722 | } | |
2723 | } | |
2724 | if (i == 4) | |
2725 | DRM_ERROR("FDI train 1 fail!\n"); | |
2726 | ||
2727 | /* Train 2 */ | |
2728 | reg = FDI_TX_CTL(pipe); | |
2729 | temp = I915_READ(reg); | |
2730 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; | |
2731 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
2732 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2733 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
2734 | I915_WRITE(reg, temp); | |
2735 | ||
2736 | reg = FDI_RX_CTL(pipe); | |
2737 | temp = I915_READ(reg); | |
2738 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2739 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
2740 | I915_WRITE(reg, temp); | |
2741 | ||
2742 | POSTING_READ(reg); | |
2743 | udelay(150); | |
2744 | ||
0206e353 | 2745 | for (i = 0; i < 4; i++) { |
357555c0 JB |
2746 | reg = FDI_TX_CTL(pipe); |
2747 | temp = I915_READ(reg); | |
2748 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
2749 | temp |= snb_b_fdi_train_param[i]; | |
2750 | I915_WRITE(reg, temp); | |
2751 | ||
2752 | POSTING_READ(reg); | |
2753 | udelay(500); | |
2754 | ||
2755 | reg = FDI_RX_IIR(pipe); | |
2756 | temp = I915_READ(reg); | |
2757 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
2758 | ||
2759 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
2760 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
2761 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
2762 | break; | |
2763 | } | |
2764 | } | |
2765 | if (i == 4) | |
2766 | DRM_ERROR("FDI train 2 fail!\n"); | |
2767 | ||
2768 | DRM_DEBUG_KMS("FDI train done.\n"); | |
2769 | } | |
2770 | ||
2771 | static void ironlake_fdi_pll_enable(struct drm_crtc *crtc) | |
2c07245f ZW |
2772 | { |
2773 | struct drm_device *dev = crtc->dev; | |
2774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2775 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2776 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2777 | u32 reg, temp; |
79e53945 | 2778 | |
c64e311e | 2779 | /* Write the TU size bits so error detection works */ |
5eddb70b CW |
2780 | I915_WRITE(FDI_RX_TUSIZE1(pipe), |
2781 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
c64e311e | 2782 | |
c98e9dcf | 2783 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
2784 | reg = FDI_RX_CTL(pipe); |
2785 | temp = I915_READ(reg); | |
2786 | temp &= ~((0x7 << 19) | (0x7 << 16)); | |
c98e9dcf | 2787 | temp |= (intel_crtc->fdi_lanes - 1) << 19; |
5eddb70b CW |
2788 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; |
2789 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); | |
2790 | ||
2791 | POSTING_READ(reg); | |
c98e9dcf JB |
2792 | udelay(200); |
2793 | ||
2794 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
2795 | temp = I915_READ(reg); |
2796 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
2797 | ||
2798 | POSTING_READ(reg); | |
c98e9dcf JB |
2799 | udelay(200); |
2800 | ||
2801 | /* Enable CPU FDI TX PLL, always on for Ironlake */ | |
5eddb70b CW |
2802 | reg = FDI_TX_CTL(pipe); |
2803 | temp = I915_READ(reg); | |
c98e9dcf | 2804 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { |
5eddb70b CW |
2805 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); |
2806 | ||
2807 | POSTING_READ(reg); | |
c98e9dcf | 2808 | udelay(100); |
6be4a607 | 2809 | } |
0e23b99d JB |
2810 | } |
2811 | ||
291427f5 JB |
2812 | static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe) |
2813 | { | |
2814 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2815 | u32 flags = I915_READ(SOUTH_CHICKEN1); | |
2816 | ||
2817 | flags &= ~(FDI_PHASE_SYNC_EN(pipe)); | |
2818 | I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */ | |
2819 | flags &= ~(FDI_PHASE_SYNC_OVR(pipe)); | |
2820 | I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */ | |
2821 | POSTING_READ(SOUTH_CHICKEN1); | |
2822 | } | |
0fc932b8 JB |
2823 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
2824 | { | |
2825 | struct drm_device *dev = crtc->dev; | |
2826 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2827 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2828 | int pipe = intel_crtc->pipe; | |
2829 | u32 reg, temp; | |
2830 | ||
2831 | /* disable CPU FDI tx and PCH FDI rx */ | |
2832 | reg = FDI_TX_CTL(pipe); | |
2833 | temp = I915_READ(reg); | |
2834 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
2835 | POSTING_READ(reg); | |
2836 | ||
2837 | reg = FDI_RX_CTL(pipe); | |
2838 | temp = I915_READ(reg); | |
2839 | temp &= ~(0x7 << 16); | |
2840 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2841 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); | |
2842 | ||
2843 | POSTING_READ(reg); | |
2844 | udelay(100); | |
2845 | ||
2846 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6f06ce18 JB |
2847 | if (HAS_PCH_IBX(dev)) { |
2848 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | |
0fc932b8 JB |
2849 | I915_WRITE(FDI_RX_CHICKEN(pipe), |
2850 | I915_READ(FDI_RX_CHICKEN(pipe) & | |
6f06ce18 | 2851 | ~FDI_RX_PHASE_SYNC_POINTER_EN)); |
291427f5 JB |
2852 | } else if (HAS_PCH_CPT(dev)) { |
2853 | cpt_phase_pointer_disable(dev, pipe); | |
6f06ce18 | 2854 | } |
0fc932b8 JB |
2855 | |
2856 | /* still set train pattern 1 */ | |
2857 | reg = FDI_TX_CTL(pipe); | |
2858 | temp = I915_READ(reg); | |
2859 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2860 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2861 | I915_WRITE(reg, temp); | |
2862 | ||
2863 | reg = FDI_RX_CTL(pipe); | |
2864 | temp = I915_READ(reg); | |
2865 | if (HAS_PCH_CPT(dev)) { | |
2866 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2867 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
2868 | } else { | |
2869 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2870 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
2871 | } | |
2872 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
2873 | temp &= ~(0x07 << 16); | |
2874 | temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11; | |
2875 | I915_WRITE(reg, temp); | |
2876 | ||
2877 | POSTING_READ(reg); | |
2878 | udelay(100); | |
2879 | } | |
2880 | ||
6b383a7f CW |
2881 | /* |
2882 | * When we disable a pipe, we need to clear any pending scanline wait events | |
2883 | * to avoid hanging the ring, which we assume we are waiting on. | |
2884 | */ | |
2885 | static void intel_clear_scanline_wait(struct drm_device *dev) | |
2886 | { | |
2887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8168bd48 | 2888 | struct intel_ring_buffer *ring; |
6b383a7f CW |
2889 | u32 tmp; |
2890 | ||
2891 | if (IS_GEN2(dev)) | |
2892 | /* Can't break the hang on i8xx */ | |
2893 | return; | |
2894 | ||
1ec14ad3 | 2895 | ring = LP_RING(dev_priv); |
8168bd48 CW |
2896 | tmp = I915_READ_CTL(ring); |
2897 | if (tmp & RING_WAIT) | |
2898 | I915_WRITE_CTL(ring, tmp); | |
6b383a7f CW |
2899 | } |
2900 | ||
e6c3a2a6 CW |
2901 | static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
2902 | { | |
05394f39 | 2903 | struct drm_i915_gem_object *obj; |
e6c3a2a6 CW |
2904 | struct drm_i915_private *dev_priv; |
2905 | ||
2906 | if (crtc->fb == NULL) | |
2907 | return; | |
2908 | ||
05394f39 | 2909 | obj = to_intel_framebuffer(crtc->fb)->obj; |
e6c3a2a6 CW |
2910 | dev_priv = crtc->dev->dev_private; |
2911 | wait_event(dev_priv->pending_flip_queue, | |
05394f39 | 2912 | atomic_read(&obj->pending_flip) == 0); |
e6c3a2a6 CW |
2913 | } |
2914 | ||
040484af JB |
2915 | static bool intel_crtc_driving_pch(struct drm_crtc *crtc) |
2916 | { | |
2917 | struct drm_device *dev = crtc->dev; | |
2918 | struct drm_mode_config *mode_config = &dev->mode_config; | |
2919 | struct intel_encoder *encoder; | |
2920 | ||
2921 | /* | |
2922 | * If there's a non-PCH eDP on this crtc, it must be DP_A, and that | |
2923 | * must be driven by its own crtc; no sharing is possible. | |
2924 | */ | |
2925 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
2926 | if (encoder->base.crtc != crtc) | |
2927 | continue; | |
2928 | ||
2929 | switch (encoder->type) { | |
2930 | case INTEL_OUTPUT_EDP: | |
2931 | if (!intel_encoder_is_pch_edp(&encoder->base)) | |
2932 | return false; | |
2933 | continue; | |
2934 | } | |
2935 | } | |
2936 | ||
2937 | return true; | |
2938 | } | |
2939 | ||
f67a559d JB |
2940 | /* |
2941 | * Enable PCH resources required for PCH ports: | |
2942 | * - PCH PLLs | |
2943 | * - FDI training & RX/TX | |
2944 | * - update transcoder timings | |
2945 | * - DP transcoding bits | |
2946 | * - transcoder | |
2947 | */ | |
2948 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
2949 | { |
2950 | struct drm_device *dev = crtc->dev; | |
2951 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2952 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2953 | int pipe = intel_crtc->pipe; | |
4b645f14 | 2954 | u32 reg, temp, transc_sel; |
2c07245f | 2955 | |
c98e9dcf | 2956 | /* For PCH output, training FDI link */ |
674cf967 | 2957 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 2958 | |
92f2584a | 2959 | intel_enable_pch_pll(dev_priv, pipe); |
8db9d77b | 2960 | |
c98e9dcf | 2961 | if (HAS_PCH_CPT(dev)) { |
4b645f14 JB |
2962 | transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL : |
2963 | TRANSC_DPLLB_SEL; | |
2964 | ||
c98e9dcf JB |
2965 | /* Be sure PCH DPLL SEL is set */ |
2966 | temp = I915_READ(PCH_DPLL_SEL); | |
d64311ab JB |
2967 | if (pipe == 0) { |
2968 | temp &= ~(TRANSA_DPLLB_SEL); | |
c98e9dcf | 2969 | temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL); |
d64311ab JB |
2970 | } else if (pipe == 1) { |
2971 | temp &= ~(TRANSB_DPLLB_SEL); | |
c98e9dcf | 2972 | temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
d64311ab JB |
2973 | } else if (pipe == 2) { |
2974 | temp &= ~(TRANSC_DPLLB_SEL); | |
4b645f14 | 2975 | temp |= (TRANSC_DPLL_ENABLE | transc_sel); |
d64311ab | 2976 | } |
c98e9dcf | 2977 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 2978 | } |
5eddb70b | 2979 | |
d9b6cb56 JB |
2980 | /* set transcoder timing, panel must allow it */ |
2981 | assert_panel_unlocked(dev_priv, pipe); | |
5eddb70b CW |
2982 | I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); |
2983 | I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); | |
2984 | I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); | |
8db9d77b | 2985 | |
5eddb70b CW |
2986 | I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); |
2987 | I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); | |
2988 | I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); | |
0529a0d9 | 2989 | I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); |
8db9d77b | 2990 | |
5e84e1a4 ZW |
2991 | intel_fdi_normal_train(crtc); |
2992 | ||
c98e9dcf JB |
2993 | /* For PCH DP, enable TRANS_DP_CTL */ |
2994 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
2995 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
2996 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
9325c9f0 | 2997 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5; |
5eddb70b CW |
2998 | reg = TRANS_DP_CTL(pipe); |
2999 | temp = I915_READ(reg); | |
3000 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3001 | TRANS_DP_SYNC_MASK | |
3002 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3003 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3004 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3005 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3006 | |
3007 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3008 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3009 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3010 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3011 | |
3012 | switch (intel_trans_dp_port_sel(crtc)) { | |
3013 | case PCH_DP_B: | |
5eddb70b | 3014 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3015 | break; |
3016 | case PCH_DP_C: | |
5eddb70b | 3017 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3018 | break; |
3019 | case PCH_DP_D: | |
5eddb70b | 3020 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3021 | break; |
3022 | default: | |
3023 | DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n"); | |
5eddb70b | 3024 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 3025 | break; |
32f9d658 | 3026 | } |
2c07245f | 3027 | |
5eddb70b | 3028 | I915_WRITE(reg, temp); |
6be4a607 | 3029 | } |
b52eb4dc | 3030 | |
040484af | 3031 | intel_enable_transcoder(dev_priv, pipe); |
f67a559d JB |
3032 | } |
3033 | ||
d4270e57 JB |
3034 | void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) |
3035 | { | |
3036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3037 | int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe); | |
3038 | u32 temp; | |
3039 | ||
3040 | temp = I915_READ(dslreg); | |
3041 | udelay(500); | |
3042 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
3043 | /* Without this, mode sets may fail silently on FDI */ | |
3044 | I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS); | |
3045 | udelay(250); | |
3046 | I915_WRITE(tc2reg, 0); | |
3047 | if (wait_for(I915_READ(dslreg) != temp, 5)) | |
3048 | DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); | |
3049 | } | |
3050 | } | |
3051 | ||
f67a559d JB |
3052 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
3053 | { | |
3054 | struct drm_device *dev = crtc->dev; | |
3055 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3056 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3057 | int pipe = intel_crtc->pipe; | |
3058 | int plane = intel_crtc->plane; | |
3059 | u32 temp; | |
3060 | bool is_pch_port; | |
3061 | ||
3062 | if (intel_crtc->active) | |
3063 | return; | |
3064 | ||
3065 | intel_crtc->active = true; | |
3066 | intel_update_watermarks(dev); | |
3067 | ||
3068 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
3069 | temp = I915_READ(PCH_LVDS); | |
3070 | if ((temp & LVDS_PORT_EN) == 0) | |
3071 | I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); | |
3072 | } | |
3073 | ||
3074 | is_pch_port = intel_crtc_driving_pch(crtc); | |
3075 | ||
3076 | if (is_pch_port) | |
357555c0 | 3077 | ironlake_fdi_pll_enable(crtc); |
f67a559d JB |
3078 | else |
3079 | ironlake_fdi_disable(crtc); | |
3080 | ||
3081 | /* Enable panel fitting for LVDS */ | |
3082 | if (dev_priv->pch_pf_size && | |
3083 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) { | |
3084 | /* Force use of hard-coded filter coefficients | |
3085 | * as some pre-programmed values are broken, | |
3086 | * e.g. x201. | |
3087 | */ | |
9db4a9c7 JB |
3088 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); |
3089 | I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); | |
3090 | I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); | |
f67a559d JB |
3091 | } |
3092 | ||
9c54c0dd JB |
3093 | /* |
3094 | * On ILK+ LUT must be loaded before the pipe is running but with | |
3095 | * clocks enabled | |
3096 | */ | |
3097 | intel_crtc_load_lut(crtc); | |
3098 | ||
f67a559d JB |
3099 | intel_enable_pipe(dev_priv, pipe, is_pch_port); |
3100 | intel_enable_plane(dev_priv, plane, pipe); | |
3101 | ||
3102 | if (is_pch_port) | |
3103 | ironlake_pch_enable(crtc); | |
c98e9dcf | 3104 | |
d1ebd816 | 3105 | mutex_lock(&dev->struct_mutex); |
bed4a673 | 3106 | intel_update_fbc(dev); |
d1ebd816 BW |
3107 | mutex_unlock(&dev->struct_mutex); |
3108 | ||
6b383a7f | 3109 | intel_crtc_update_cursor(crtc, true); |
6be4a607 JB |
3110 | } |
3111 | ||
3112 | static void ironlake_crtc_disable(struct drm_crtc *crtc) | |
3113 | { | |
3114 | struct drm_device *dev = crtc->dev; | |
3115 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3116 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3117 | int pipe = intel_crtc->pipe; | |
3118 | int plane = intel_crtc->plane; | |
5eddb70b | 3119 | u32 reg, temp; |
b52eb4dc | 3120 | |
f7abfe8b CW |
3121 | if (!intel_crtc->active) |
3122 | return; | |
3123 | ||
e6c3a2a6 | 3124 | intel_crtc_wait_for_pending_flips(crtc); |
6be4a607 | 3125 | drm_vblank_off(dev, pipe); |
6b383a7f | 3126 | intel_crtc_update_cursor(crtc, false); |
5eddb70b | 3127 | |
b24e7179 | 3128 | intel_disable_plane(dev_priv, plane, pipe); |
913d8d11 | 3129 | |
973d04f9 CW |
3130 | if (dev_priv->cfb_plane == plane) |
3131 | intel_disable_fbc(dev); | |
2c07245f | 3132 | |
b24e7179 | 3133 | intel_disable_pipe(dev_priv, pipe); |
32f9d658 | 3134 | |
6be4a607 | 3135 | /* Disable PF */ |
9db4a9c7 JB |
3136 | I915_WRITE(PF_CTL(pipe), 0); |
3137 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
2c07245f | 3138 | |
0fc932b8 | 3139 | ironlake_fdi_disable(crtc); |
2c07245f | 3140 | |
47a05eca JB |
3141 | /* This is a horrible layering violation; we should be doing this in |
3142 | * the connector/encoder ->prepare instead, but we don't always have | |
3143 | * enough information there about the config to know whether it will | |
3144 | * actually be necessary or just cause undesired flicker. | |
3145 | */ | |
3146 | intel_disable_pch_ports(dev_priv, pipe); | |
249c0e64 | 3147 | |
040484af | 3148 | intel_disable_transcoder(dev_priv, pipe); |
913d8d11 | 3149 | |
6be4a607 JB |
3150 | if (HAS_PCH_CPT(dev)) { |
3151 | /* disable TRANS_DP_CTL */ | |
5eddb70b CW |
3152 | reg = TRANS_DP_CTL(pipe); |
3153 | temp = I915_READ(reg); | |
3154 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); | |
cb3543c6 | 3155 | temp |= TRANS_DP_PORT_SEL_NONE; |
5eddb70b | 3156 | I915_WRITE(reg, temp); |
6be4a607 JB |
3157 | |
3158 | /* disable DPLL_SEL */ | |
3159 | temp = I915_READ(PCH_DPLL_SEL); | |
9db4a9c7 JB |
3160 | switch (pipe) { |
3161 | case 0: | |
d64311ab | 3162 | temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); |
9db4a9c7 JB |
3163 | break; |
3164 | case 1: | |
6be4a607 | 3165 | temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); |
9db4a9c7 JB |
3166 | break; |
3167 | case 2: | |
4b645f14 | 3168 | /* C shares PLL A or B */ |
d64311ab | 3169 | temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); |
9db4a9c7 JB |
3170 | break; |
3171 | default: | |
3172 | BUG(); /* wtf */ | |
3173 | } | |
6be4a607 | 3174 | I915_WRITE(PCH_DPLL_SEL, temp); |
6be4a607 | 3175 | } |
e3421a18 | 3176 | |
6be4a607 | 3177 | /* disable PCH DPLL */ |
4b645f14 JB |
3178 | if (!intel_crtc->no_pll) |
3179 | intel_disable_pch_pll(dev_priv, pipe); | |
8db9d77b | 3180 | |
6be4a607 | 3181 | /* Switch from PCDclk to Rawclk */ |
5eddb70b CW |
3182 | reg = FDI_RX_CTL(pipe); |
3183 | temp = I915_READ(reg); | |
3184 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
8db9d77b | 3185 | |
6be4a607 | 3186 | /* Disable CPU FDI TX PLL */ |
5eddb70b CW |
3187 | reg = FDI_TX_CTL(pipe); |
3188 | temp = I915_READ(reg); | |
3189 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3190 | ||
3191 | POSTING_READ(reg); | |
6be4a607 | 3192 | udelay(100); |
8db9d77b | 3193 | |
5eddb70b CW |
3194 | reg = FDI_RX_CTL(pipe); |
3195 | temp = I915_READ(reg); | |
3196 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
2c07245f | 3197 | |
6be4a607 | 3198 | /* Wait for the clocks to turn off. */ |
5eddb70b | 3199 | POSTING_READ(reg); |
6be4a607 | 3200 | udelay(100); |
6b383a7f | 3201 | |
f7abfe8b | 3202 | intel_crtc->active = false; |
6b383a7f | 3203 | intel_update_watermarks(dev); |
d1ebd816 BW |
3204 | |
3205 | mutex_lock(&dev->struct_mutex); | |
6b383a7f CW |
3206 | intel_update_fbc(dev); |
3207 | intel_clear_scanline_wait(dev); | |
d1ebd816 | 3208 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 3209 | } |
1b3c7a47 | 3210 | |
6be4a607 JB |
3211 | static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode) |
3212 | { | |
3213 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3214 | int pipe = intel_crtc->pipe; | |
3215 | int plane = intel_crtc->plane; | |
8db9d77b | 3216 | |
6be4a607 JB |
3217 | /* XXX: When our outputs are all unaware of DPMS modes other than off |
3218 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
3219 | */ | |
3220 | switch (mode) { | |
3221 | case DRM_MODE_DPMS_ON: | |
3222 | case DRM_MODE_DPMS_STANDBY: | |
3223 | case DRM_MODE_DPMS_SUSPEND: | |
3224 | DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane); | |
3225 | ironlake_crtc_enable(crtc); | |
3226 | break; | |
1b3c7a47 | 3227 | |
6be4a607 JB |
3228 | case DRM_MODE_DPMS_OFF: |
3229 | DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane); | |
3230 | ironlake_crtc_disable(crtc); | |
2c07245f ZW |
3231 | break; |
3232 | } | |
3233 | } | |
3234 | ||
02e792fb DV |
3235 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
3236 | { | |
02e792fb | 3237 | if (!enable && intel_crtc->overlay) { |
23f09ce3 | 3238 | struct drm_device *dev = intel_crtc->base.dev; |
ce453d81 | 3239 | struct drm_i915_private *dev_priv = dev->dev_private; |
03f77ea5 | 3240 | |
23f09ce3 | 3241 | mutex_lock(&dev->struct_mutex); |
ce453d81 CW |
3242 | dev_priv->mm.interruptible = false; |
3243 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
3244 | dev_priv->mm.interruptible = true; | |
23f09ce3 | 3245 | mutex_unlock(&dev->struct_mutex); |
02e792fb | 3246 | } |
02e792fb | 3247 | |
5dcdbcb0 CW |
3248 | /* Let userspace switch the overlay on again. In most cases userspace |
3249 | * has to recompute where to put it anyway. | |
3250 | */ | |
02e792fb DV |
3251 | } |
3252 | ||
0b8765c6 | 3253 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
3254 | { |
3255 | struct drm_device *dev = crtc->dev; | |
79e53945 JB |
3256 | struct drm_i915_private *dev_priv = dev->dev_private; |
3257 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3258 | int pipe = intel_crtc->pipe; | |
80824003 | 3259 | int plane = intel_crtc->plane; |
79e53945 | 3260 | |
f7abfe8b CW |
3261 | if (intel_crtc->active) |
3262 | return; | |
3263 | ||
3264 | intel_crtc->active = true; | |
6b383a7f CW |
3265 | intel_update_watermarks(dev); |
3266 | ||
63d7bbe9 | 3267 | intel_enable_pll(dev_priv, pipe); |
040484af | 3268 | intel_enable_pipe(dev_priv, pipe, false); |
b24e7179 | 3269 | intel_enable_plane(dev_priv, plane, pipe); |
79e53945 | 3270 | |
0b8765c6 | 3271 | intel_crtc_load_lut(crtc); |
bed4a673 | 3272 | intel_update_fbc(dev); |
79e53945 | 3273 | |
0b8765c6 JB |
3274 | /* Give the overlay scaler a chance to enable if it's on this pipe */ |
3275 | intel_crtc_dpms_overlay(intel_crtc, true); | |
6b383a7f | 3276 | intel_crtc_update_cursor(crtc, true); |
0b8765c6 | 3277 | } |
79e53945 | 3278 | |
0b8765c6 JB |
3279 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
3280 | { | |
3281 | struct drm_device *dev = crtc->dev; | |
3282 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3283 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3284 | int pipe = intel_crtc->pipe; | |
3285 | int plane = intel_crtc->plane; | |
b690e96c | 3286 | |
f7abfe8b CW |
3287 | if (!intel_crtc->active) |
3288 | return; | |
3289 | ||
0b8765c6 | 3290 | /* Give the overlay scaler a chance to disable if it's on this pipe */ |
e6c3a2a6 CW |
3291 | intel_crtc_wait_for_pending_flips(crtc); |
3292 | drm_vblank_off(dev, pipe); | |
0b8765c6 | 3293 | intel_crtc_dpms_overlay(intel_crtc, false); |
6b383a7f | 3294 | intel_crtc_update_cursor(crtc, false); |
0b8765c6 | 3295 | |
973d04f9 CW |
3296 | if (dev_priv->cfb_plane == plane) |
3297 | intel_disable_fbc(dev); | |
79e53945 | 3298 | |
b24e7179 | 3299 | intel_disable_plane(dev_priv, plane, pipe); |
b24e7179 | 3300 | intel_disable_pipe(dev_priv, pipe); |
63d7bbe9 | 3301 | intel_disable_pll(dev_priv, pipe); |
0b8765c6 | 3302 | |
f7abfe8b | 3303 | intel_crtc->active = false; |
6b383a7f CW |
3304 | intel_update_fbc(dev); |
3305 | intel_update_watermarks(dev); | |
3306 | intel_clear_scanline_wait(dev); | |
0b8765c6 JB |
3307 | } |
3308 | ||
3309 | static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode) | |
3310 | { | |
3311 | /* XXX: When our outputs are all unaware of DPMS modes other than off | |
3312 | * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC. | |
3313 | */ | |
3314 | switch (mode) { | |
3315 | case DRM_MODE_DPMS_ON: | |
3316 | case DRM_MODE_DPMS_STANDBY: | |
3317 | case DRM_MODE_DPMS_SUSPEND: | |
3318 | i9xx_crtc_enable(crtc); | |
3319 | break; | |
3320 | case DRM_MODE_DPMS_OFF: | |
3321 | i9xx_crtc_disable(crtc); | |
79e53945 JB |
3322 | break; |
3323 | } | |
2c07245f ZW |
3324 | } |
3325 | ||
3326 | /** | |
3327 | * Sets the power management mode of the pipe and plane. | |
2c07245f ZW |
3328 | */ |
3329 | static void intel_crtc_dpms(struct drm_crtc *crtc, int mode) | |
3330 | { | |
3331 | struct drm_device *dev = crtc->dev; | |
e70236a8 | 3332 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f ZW |
3333 | struct drm_i915_master_private *master_priv; |
3334 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3335 | int pipe = intel_crtc->pipe; | |
3336 | bool enabled; | |
3337 | ||
032d2a0d CW |
3338 | if (intel_crtc->dpms_mode == mode) |
3339 | return; | |
3340 | ||
65655d4a | 3341 | intel_crtc->dpms_mode = mode; |
debcaddc | 3342 | |
e70236a8 | 3343 | dev_priv->display.dpms(crtc, mode); |
79e53945 JB |
3344 | |
3345 | if (!dev->primary->master) | |
3346 | return; | |
3347 | ||
3348 | master_priv = dev->primary->master->driver_priv; | |
3349 | if (!master_priv->sarea_priv) | |
3350 | return; | |
3351 | ||
3352 | enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF; | |
3353 | ||
3354 | switch (pipe) { | |
3355 | case 0: | |
3356 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
3357 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
3358 | break; | |
3359 | case 1: | |
3360 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
3361 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
3362 | break; | |
3363 | default: | |
9db4a9c7 | 3364 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
3365 | break; |
3366 | } | |
79e53945 JB |
3367 | } |
3368 | ||
cdd59983 CW |
3369 | static void intel_crtc_disable(struct drm_crtc *crtc) |
3370 | { | |
3371 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
3372 | struct drm_device *dev = crtc->dev; | |
3373 | ||
3374 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); | |
931872fc CW |
3375 | assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); |
3376 | assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); | |
cdd59983 CW |
3377 | |
3378 | if (crtc->fb) { | |
3379 | mutex_lock(&dev->struct_mutex); | |
1690e1eb | 3380 | intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); |
cdd59983 CW |
3381 | mutex_unlock(&dev->struct_mutex); |
3382 | } | |
3383 | } | |
3384 | ||
7e7d76c3 JB |
3385 | /* Prepare for a mode set. |
3386 | * | |
3387 | * Note we could be a lot smarter here. We need to figure out which outputs | |
3388 | * will be enabled, which disabled (in short, how the config will changes) | |
3389 | * and perform the minimum necessary steps to accomplish that, e.g. updating | |
3390 | * watermarks, FBC configuration, making sure PLLs are programmed correctly, | |
3391 | * panel fitting is in the proper state, etc. | |
3392 | */ | |
3393 | static void i9xx_crtc_prepare(struct drm_crtc *crtc) | |
79e53945 | 3394 | { |
7e7d76c3 | 3395 | i9xx_crtc_disable(crtc); |
79e53945 JB |
3396 | } |
3397 | ||
7e7d76c3 | 3398 | static void i9xx_crtc_commit(struct drm_crtc *crtc) |
79e53945 | 3399 | { |
7e7d76c3 | 3400 | i9xx_crtc_enable(crtc); |
7e7d76c3 JB |
3401 | } |
3402 | ||
3403 | static void ironlake_crtc_prepare(struct drm_crtc *crtc) | |
3404 | { | |
7e7d76c3 | 3405 | ironlake_crtc_disable(crtc); |
7e7d76c3 JB |
3406 | } |
3407 | ||
3408 | static void ironlake_crtc_commit(struct drm_crtc *crtc) | |
3409 | { | |
7e7d76c3 | 3410 | ironlake_crtc_enable(crtc); |
79e53945 JB |
3411 | } |
3412 | ||
0206e353 | 3413 | void intel_encoder_prepare(struct drm_encoder *encoder) |
79e53945 JB |
3414 | { |
3415 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
3416 | /* lvds has its own version of prepare see intel_lvds_prepare */ | |
3417 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); | |
3418 | } | |
3419 | ||
0206e353 | 3420 | void intel_encoder_commit(struct drm_encoder *encoder) |
79e53945 JB |
3421 | { |
3422 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
d4270e57 JB |
3423 | struct drm_device *dev = encoder->dev; |
3424 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
3425 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
3426 | ||
79e53945 JB |
3427 | /* lvds has its own version of commit see intel_lvds_commit */ |
3428 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); | |
d4270e57 JB |
3429 | |
3430 | if (HAS_PCH_CPT(dev)) | |
3431 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); | |
79e53945 JB |
3432 | } |
3433 | ||
ea5b213a CW |
3434 | void intel_encoder_destroy(struct drm_encoder *encoder) |
3435 | { | |
4ef69c7a | 3436 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 3437 | |
ea5b213a CW |
3438 | drm_encoder_cleanup(encoder); |
3439 | kfree(intel_encoder); | |
3440 | } | |
3441 | ||
79e53945 JB |
3442 | static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, |
3443 | struct drm_display_mode *mode, | |
3444 | struct drm_display_mode *adjusted_mode) | |
3445 | { | |
2c07245f | 3446 | struct drm_device *dev = crtc->dev; |
89749350 | 3447 | |
bad720ff | 3448 | if (HAS_PCH_SPLIT(dev)) { |
2c07245f | 3449 | /* FDI link clock is fixed at 2.7G */ |
2377b741 JB |
3450 | if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) |
3451 | return false; | |
2c07245f | 3452 | } |
89749350 | 3453 | |
ca9bfa7e DV |
3454 | /* All interlaced capable intel hw wants timings in frames. */ |
3455 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
89749350 | 3456 | |
79e53945 JB |
3457 | return true; |
3458 | } | |
3459 | ||
e70236a8 JB |
3460 | static int i945_get_display_clock_speed(struct drm_device *dev) |
3461 | { | |
3462 | return 400000; | |
3463 | } | |
79e53945 | 3464 | |
e70236a8 | 3465 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 3466 | { |
e70236a8 JB |
3467 | return 333000; |
3468 | } | |
79e53945 | 3469 | |
e70236a8 JB |
3470 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
3471 | { | |
3472 | return 200000; | |
3473 | } | |
79e53945 | 3474 | |
e70236a8 JB |
3475 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
3476 | { | |
3477 | u16 gcfgc = 0; | |
79e53945 | 3478 | |
e70236a8 JB |
3479 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
3480 | ||
3481 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
3482 | return 133000; | |
3483 | else { | |
3484 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
3485 | case GC_DISPLAY_CLOCK_333_MHZ: | |
3486 | return 333000; | |
3487 | default: | |
3488 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
3489 | return 190000; | |
79e53945 | 3490 | } |
e70236a8 JB |
3491 | } |
3492 | } | |
3493 | ||
3494 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
3495 | { | |
3496 | return 266000; | |
3497 | } | |
3498 | ||
3499 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
3500 | { | |
3501 | u16 hpllcc = 0; | |
3502 | /* Assume that the hardware is in the high speed state. This | |
3503 | * should be the default. | |
3504 | */ | |
3505 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
3506 | case GC_CLOCK_133_200: | |
3507 | case GC_CLOCK_100_200: | |
3508 | return 200000; | |
3509 | case GC_CLOCK_166_250: | |
3510 | return 250000; | |
3511 | case GC_CLOCK_100_133: | |
79e53945 | 3512 | return 133000; |
e70236a8 | 3513 | } |
79e53945 | 3514 | |
e70236a8 JB |
3515 | /* Shouldn't happen */ |
3516 | return 0; | |
3517 | } | |
79e53945 | 3518 | |
e70236a8 JB |
3519 | static int i830_get_display_clock_speed(struct drm_device *dev) |
3520 | { | |
3521 | return 133000; | |
79e53945 JB |
3522 | } |
3523 | ||
2c07245f ZW |
3524 | struct fdi_m_n { |
3525 | u32 tu; | |
3526 | u32 gmch_m; | |
3527 | u32 gmch_n; | |
3528 | u32 link_m; | |
3529 | u32 link_n; | |
3530 | }; | |
3531 | ||
3532 | static void | |
3533 | fdi_reduce_ratio(u32 *num, u32 *den) | |
3534 | { | |
3535 | while (*num > 0xffffff || *den > 0xffffff) { | |
3536 | *num >>= 1; | |
3537 | *den >>= 1; | |
3538 | } | |
3539 | } | |
3540 | ||
2c07245f | 3541 | static void |
f2b115e6 AJ |
3542 | ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock, |
3543 | int link_clock, struct fdi_m_n *m_n) | |
2c07245f | 3544 | { |
2c07245f ZW |
3545 | m_n->tu = 64; /* default size */ |
3546 | ||
22ed1113 CW |
3547 | /* BUG_ON(pixel_clock > INT_MAX / 36); */ |
3548 | m_n->gmch_m = bits_per_pixel * pixel_clock; | |
3549 | m_n->gmch_n = link_clock * nlanes * 8; | |
2c07245f ZW |
3550 | fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
3551 | ||
22ed1113 CW |
3552 | m_n->link_m = pixel_clock; |
3553 | m_n->link_n = link_clock; | |
2c07245f ZW |
3554 | fdi_reduce_ratio(&m_n->link_m, &m_n->link_n); |
3555 | } | |
3556 | ||
3557 | ||
7662c8bd SL |
3558 | struct intel_watermark_params { |
3559 | unsigned long fifo_size; | |
3560 | unsigned long max_wm; | |
3561 | unsigned long default_wm; | |
3562 | unsigned long guard_size; | |
3563 | unsigned long cacheline_size; | |
3564 | }; | |
3565 | ||
f2b115e6 | 3566 | /* Pineview has different values for various configs */ |
d210246a | 3567 | static const struct intel_watermark_params pineview_display_wm = { |
f2b115e6 AJ |
3568 | PINEVIEW_DISPLAY_FIFO, |
3569 | PINEVIEW_MAX_WM, | |
3570 | PINEVIEW_DFT_WM, | |
3571 | PINEVIEW_GUARD_WM, | |
3572 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3573 | }; |
d210246a | 3574 | static const struct intel_watermark_params pineview_display_hplloff_wm = { |
f2b115e6 AJ |
3575 | PINEVIEW_DISPLAY_FIFO, |
3576 | PINEVIEW_MAX_WM, | |
3577 | PINEVIEW_DFT_HPLLOFF_WM, | |
3578 | PINEVIEW_GUARD_WM, | |
3579 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3580 | }; |
d210246a | 3581 | static const struct intel_watermark_params pineview_cursor_wm = { |
f2b115e6 AJ |
3582 | PINEVIEW_CURSOR_FIFO, |
3583 | PINEVIEW_CURSOR_MAX_WM, | |
3584 | PINEVIEW_CURSOR_DFT_WM, | |
3585 | PINEVIEW_CURSOR_GUARD_WM, | |
3586 | PINEVIEW_FIFO_LINE_SIZE, | |
7662c8bd | 3587 | }; |
d210246a | 3588 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { |
f2b115e6 AJ |
3589 | PINEVIEW_CURSOR_FIFO, |
3590 | PINEVIEW_CURSOR_MAX_WM, | |
3591 | PINEVIEW_CURSOR_DFT_WM, | |
3592 | PINEVIEW_CURSOR_GUARD_WM, | |
3593 | PINEVIEW_FIFO_LINE_SIZE | |
7662c8bd | 3594 | }; |
d210246a | 3595 | static const struct intel_watermark_params g4x_wm_info = { |
0e442c60 JB |
3596 | G4X_FIFO_SIZE, |
3597 | G4X_MAX_WM, | |
3598 | G4X_MAX_WM, | |
3599 | 2, | |
3600 | G4X_FIFO_LINE_SIZE, | |
3601 | }; | |
d210246a | 3602 | static const struct intel_watermark_params g4x_cursor_wm_info = { |
4fe5e611 ZY |
3603 | I965_CURSOR_FIFO, |
3604 | I965_CURSOR_MAX_WM, | |
3605 | I965_CURSOR_DFT_WM, | |
3606 | 2, | |
3607 | G4X_FIFO_LINE_SIZE, | |
3608 | }; | |
d210246a | 3609 | static const struct intel_watermark_params i965_cursor_wm_info = { |
4fe5e611 ZY |
3610 | I965_CURSOR_FIFO, |
3611 | I965_CURSOR_MAX_WM, | |
3612 | I965_CURSOR_DFT_WM, | |
3613 | 2, | |
3614 | I915_FIFO_LINE_SIZE, | |
3615 | }; | |
d210246a | 3616 | static const struct intel_watermark_params i945_wm_info = { |
dff33cfc | 3617 | I945_FIFO_SIZE, |
7662c8bd SL |
3618 | I915_MAX_WM, |
3619 | 1, | |
dff33cfc JB |
3620 | 2, |
3621 | I915_FIFO_LINE_SIZE | |
7662c8bd | 3622 | }; |
d210246a | 3623 | static const struct intel_watermark_params i915_wm_info = { |
dff33cfc | 3624 | I915_FIFO_SIZE, |
7662c8bd SL |
3625 | I915_MAX_WM, |
3626 | 1, | |
dff33cfc | 3627 | 2, |
7662c8bd SL |
3628 | I915_FIFO_LINE_SIZE |
3629 | }; | |
d210246a | 3630 | static const struct intel_watermark_params i855_wm_info = { |
7662c8bd SL |
3631 | I855GM_FIFO_SIZE, |
3632 | I915_MAX_WM, | |
3633 | 1, | |
dff33cfc | 3634 | 2, |
7662c8bd SL |
3635 | I830_FIFO_LINE_SIZE |
3636 | }; | |
d210246a | 3637 | static const struct intel_watermark_params i830_wm_info = { |
7662c8bd SL |
3638 | I830_FIFO_SIZE, |
3639 | I915_MAX_WM, | |
3640 | 1, | |
dff33cfc | 3641 | 2, |
7662c8bd SL |
3642 | I830_FIFO_LINE_SIZE |
3643 | }; | |
3644 | ||
d210246a | 3645 | static const struct intel_watermark_params ironlake_display_wm_info = { |
7f8a8569 ZW |
3646 | ILK_DISPLAY_FIFO, |
3647 | ILK_DISPLAY_MAXWM, | |
3648 | ILK_DISPLAY_DFTWM, | |
3649 | 2, | |
3650 | ILK_FIFO_LINE_SIZE | |
3651 | }; | |
d210246a | 3652 | static const struct intel_watermark_params ironlake_cursor_wm_info = { |
c936f44d ZY |
3653 | ILK_CURSOR_FIFO, |
3654 | ILK_CURSOR_MAXWM, | |
3655 | ILK_CURSOR_DFTWM, | |
3656 | 2, | |
3657 | ILK_FIFO_LINE_SIZE | |
3658 | }; | |
d210246a | 3659 | static const struct intel_watermark_params ironlake_display_srwm_info = { |
7f8a8569 ZW |
3660 | ILK_DISPLAY_SR_FIFO, |
3661 | ILK_DISPLAY_MAX_SRWM, | |
3662 | ILK_DISPLAY_DFT_SRWM, | |
3663 | 2, | |
3664 | ILK_FIFO_LINE_SIZE | |
3665 | }; | |
d210246a | 3666 | static const struct intel_watermark_params ironlake_cursor_srwm_info = { |
7f8a8569 ZW |
3667 | ILK_CURSOR_SR_FIFO, |
3668 | ILK_CURSOR_MAX_SRWM, | |
3669 | ILK_CURSOR_DFT_SRWM, | |
3670 | 2, | |
3671 | ILK_FIFO_LINE_SIZE | |
3672 | }; | |
3673 | ||
d210246a | 3674 | static const struct intel_watermark_params sandybridge_display_wm_info = { |
1398261a YL |
3675 | SNB_DISPLAY_FIFO, |
3676 | SNB_DISPLAY_MAXWM, | |
3677 | SNB_DISPLAY_DFTWM, | |
3678 | 2, | |
3679 | SNB_FIFO_LINE_SIZE | |
3680 | }; | |
d210246a | 3681 | static const struct intel_watermark_params sandybridge_cursor_wm_info = { |
1398261a YL |
3682 | SNB_CURSOR_FIFO, |
3683 | SNB_CURSOR_MAXWM, | |
3684 | SNB_CURSOR_DFTWM, | |
3685 | 2, | |
3686 | SNB_FIFO_LINE_SIZE | |
3687 | }; | |
d210246a | 3688 | static const struct intel_watermark_params sandybridge_display_srwm_info = { |
1398261a YL |
3689 | SNB_DISPLAY_SR_FIFO, |
3690 | SNB_DISPLAY_MAX_SRWM, | |
3691 | SNB_DISPLAY_DFT_SRWM, | |
3692 | 2, | |
3693 | SNB_FIFO_LINE_SIZE | |
3694 | }; | |
d210246a | 3695 | static const struct intel_watermark_params sandybridge_cursor_srwm_info = { |
1398261a YL |
3696 | SNB_CURSOR_SR_FIFO, |
3697 | SNB_CURSOR_MAX_SRWM, | |
3698 | SNB_CURSOR_DFT_SRWM, | |
3699 | 2, | |
3700 | SNB_FIFO_LINE_SIZE | |
3701 | }; | |
3702 | ||
3703 | ||
dff33cfc JB |
3704 | /** |
3705 | * intel_calculate_wm - calculate watermark level | |
3706 | * @clock_in_khz: pixel clock | |
3707 | * @wm: chip FIFO params | |
3708 | * @pixel_size: display pixel size | |
3709 | * @latency_ns: memory latency for the platform | |
3710 | * | |
3711 | * Calculate the watermark level (the level at which the display plane will | |
3712 | * start fetching from memory again). Each chip has a different display | |
3713 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
3714 | * in the correct intel_watermark_params structure. | |
3715 | * | |
3716 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
3717 | * on the pixel size. When it reaches the watermark level, it'll start | |
3718 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
3719 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
3720 | * will occur, and a display engine hang could result. | |
3721 | */ | |
7662c8bd | 3722 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
d210246a CW |
3723 | const struct intel_watermark_params *wm, |
3724 | int fifo_size, | |
7662c8bd SL |
3725 | int pixel_size, |
3726 | unsigned long latency_ns) | |
3727 | { | |
390c4dd4 | 3728 | long entries_required, wm_size; |
dff33cfc | 3729 | |
d660467c JB |
3730 | /* |
3731 | * Note: we need to make sure we don't overflow for various clock & | |
3732 | * latency values. | |
3733 | * clocks go from a few thousand to several hundred thousand. | |
3734 | * latency is usually a few thousand | |
3735 | */ | |
3736 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
3737 | 1000; | |
8de9b311 | 3738 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
7662c8bd | 3739 | |
bbb0aef5 | 3740 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); |
dff33cfc | 3741 | |
d210246a | 3742 | wm_size = fifo_size - (entries_required + wm->guard_size); |
dff33cfc | 3743 | |
bbb0aef5 | 3744 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); |
7662c8bd | 3745 | |
390c4dd4 JB |
3746 | /* Don't promote wm_size to unsigned... */ |
3747 | if (wm_size > (long)wm->max_wm) | |
7662c8bd | 3748 | wm_size = wm->max_wm; |
c3add4b6 | 3749 | if (wm_size <= 0) |
7662c8bd SL |
3750 | wm_size = wm->default_wm; |
3751 | return wm_size; | |
3752 | } | |
3753 | ||
3754 | struct cxsr_latency { | |
3755 | int is_desktop; | |
95534263 | 3756 | int is_ddr3; |
7662c8bd SL |
3757 | unsigned long fsb_freq; |
3758 | unsigned long mem_freq; | |
3759 | unsigned long display_sr; | |
3760 | unsigned long display_hpll_disable; | |
3761 | unsigned long cursor_sr; | |
3762 | unsigned long cursor_hpll_disable; | |
3763 | }; | |
3764 | ||
403c89ff | 3765 | static const struct cxsr_latency cxsr_latency_table[] = { |
95534263 LP |
3766 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
3767 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
3768 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
3769 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
3770 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
3771 | ||
3772 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
3773 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
3774 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
3775 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
3776 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
3777 | ||
3778 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
3779 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
3780 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
3781 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
3782 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
3783 | ||
3784 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
3785 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
3786 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
3787 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
3788 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
3789 | ||
3790 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
3791 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
3792 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
3793 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
3794 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
3795 | ||
3796 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
3797 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
3798 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
3799 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
3800 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
7662c8bd SL |
3801 | }; |
3802 | ||
403c89ff CW |
3803 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
3804 | int is_ddr3, | |
3805 | int fsb, | |
3806 | int mem) | |
7662c8bd | 3807 | { |
403c89ff | 3808 | const struct cxsr_latency *latency; |
7662c8bd | 3809 | int i; |
7662c8bd SL |
3810 | |
3811 | if (fsb == 0 || mem == 0) | |
3812 | return NULL; | |
3813 | ||
3814 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
3815 | latency = &cxsr_latency_table[i]; | |
3816 | if (is_desktop == latency->is_desktop && | |
95534263 | 3817 | is_ddr3 == latency->is_ddr3 && |
decbbcda JSR |
3818 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
3819 | return latency; | |
7662c8bd | 3820 | } |
decbbcda | 3821 | |
28c97730 | 3822 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
decbbcda JSR |
3823 | |
3824 | return NULL; | |
7662c8bd SL |
3825 | } |
3826 | ||
f2b115e6 | 3827 | static void pineview_disable_cxsr(struct drm_device *dev) |
7662c8bd SL |
3828 | { |
3829 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7662c8bd SL |
3830 | |
3831 | /* deactivate cxsr */ | |
3e33d94d | 3832 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); |
7662c8bd SL |
3833 | } |
3834 | ||
bcc24fb4 JB |
3835 | /* |
3836 | * Latency for FIFO fetches is dependent on several factors: | |
3837 | * - memory configuration (speed, channels) | |
3838 | * - chipset | |
3839 | * - current MCH state | |
3840 | * It can be fairly high in some situations, so here we assume a fairly | |
3841 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
3842 | * set this value too high, the FIFO will fetch frequently to stay full) | |
3843 | * and power consumption (set it too low to save power and we might see | |
3844 | * FIFO underruns and display "flicker"). | |
3845 | * | |
3846 | * A value of 5us seems to be a good balance; safe for very low end | |
3847 | * platforms but not overly aggressive on lower latency configs. | |
3848 | */ | |
69e302a9 | 3849 | static const int latency_ns = 5000; |
7662c8bd | 3850 | |
e70236a8 | 3851 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
dff33cfc JB |
3852 | { |
3853 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3854 | uint32_t dsparb = I915_READ(DSPARB); | |
3855 | int size; | |
3856 | ||
8de9b311 CW |
3857 | size = dsparb & 0x7f; |
3858 | if (plane) | |
3859 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
dff33cfc | 3860 | |
28c97730 | 3861 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3862 | plane ? "B" : "A", size); |
dff33cfc JB |
3863 | |
3864 | return size; | |
3865 | } | |
7662c8bd | 3866 | |
e70236a8 JB |
3867 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
3868 | { | |
3869 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3870 | uint32_t dsparb = I915_READ(DSPARB); | |
3871 | int size; | |
3872 | ||
8de9b311 CW |
3873 | size = dsparb & 0x1ff; |
3874 | if (plane) | |
3875 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
e70236a8 | 3876 | size >>= 1; /* Convert to cachelines */ |
dff33cfc | 3877 | |
28c97730 | 3878 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3879 | plane ? "B" : "A", size); |
dff33cfc JB |
3880 | |
3881 | return size; | |
3882 | } | |
7662c8bd | 3883 | |
e70236a8 JB |
3884 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
3885 | { | |
3886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3887 | uint32_t dsparb = I915_READ(DSPARB); | |
3888 | int size; | |
3889 | ||
3890 | size = dsparb & 0x7f; | |
3891 | size >>= 2; /* Convert to cachelines */ | |
3892 | ||
28c97730 | 3893 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b CW |
3894 | plane ? "B" : "A", |
3895 | size); | |
e70236a8 JB |
3896 | |
3897 | return size; | |
3898 | } | |
3899 | ||
3900 | static int i830_get_fifo_size(struct drm_device *dev, int plane) | |
3901 | { | |
3902 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3903 | uint32_t dsparb = I915_READ(DSPARB); | |
3904 | int size; | |
3905 | ||
3906 | size = dsparb & 0x7f; | |
3907 | size >>= 1; /* Convert to cachelines */ | |
3908 | ||
28c97730 | 3909 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
5eddb70b | 3910 | plane ? "B" : "A", size); |
e70236a8 JB |
3911 | |
3912 | return size; | |
3913 | } | |
3914 | ||
d210246a CW |
3915 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) |
3916 | { | |
3917 | struct drm_crtc *crtc, *enabled = NULL; | |
3918 | ||
3919 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3920 | if (crtc->enabled && crtc->fb) { | |
3921 | if (enabled) | |
3922 | return NULL; | |
3923 | enabled = crtc; | |
3924 | } | |
3925 | } | |
3926 | ||
3927 | return enabled; | |
3928 | } | |
3929 | ||
3930 | static void pineview_update_wm(struct drm_device *dev) | |
d4294342 ZY |
3931 | { |
3932 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a | 3933 | struct drm_crtc *crtc; |
403c89ff | 3934 | const struct cxsr_latency *latency; |
d4294342 ZY |
3935 | u32 reg; |
3936 | unsigned long wm; | |
d4294342 | 3937 | |
403c89ff | 3938 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
95534263 | 3939 | dev_priv->fsb_freq, dev_priv->mem_freq); |
d4294342 ZY |
3940 | if (!latency) { |
3941 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
3942 | pineview_disable_cxsr(dev); | |
3943 | return; | |
3944 | } | |
3945 | ||
d210246a CW |
3946 | crtc = single_enabled_crtc(dev); |
3947 | if (crtc) { | |
3948 | int clock = crtc->mode.clock; | |
3949 | int pixel_size = crtc->fb->bits_per_pixel / 8; | |
d4294342 ZY |
3950 | |
3951 | /* Display SR */ | |
d210246a CW |
3952 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
3953 | pineview_display_wm.fifo_size, | |
d4294342 ZY |
3954 | pixel_size, latency->display_sr); |
3955 | reg = I915_READ(DSPFW1); | |
3956 | reg &= ~DSPFW_SR_MASK; | |
3957 | reg |= wm << DSPFW_SR_SHIFT; | |
3958 | I915_WRITE(DSPFW1, reg); | |
3959 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
3960 | ||
3961 | /* cursor SR */ | |
d210246a CW |
3962 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
3963 | pineview_display_wm.fifo_size, | |
d4294342 ZY |
3964 | pixel_size, latency->cursor_sr); |
3965 | reg = I915_READ(DSPFW3); | |
3966 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
3967 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
3968 | I915_WRITE(DSPFW3, reg); | |
3969 | ||
3970 | /* Display HPLL off SR */ | |
d210246a CW |
3971 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
3972 | pineview_display_hplloff_wm.fifo_size, | |
d4294342 ZY |
3973 | pixel_size, latency->display_hpll_disable); |
3974 | reg = I915_READ(DSPFW3); | |
3975 | reg &= ~DSPFW_HPLL_SR_MASK; | |
3976 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
3977 | I915_WRITE(DSPFW3, reg); | |
3978 | ||
3979 | /* cursor HPLL off SR */ | |
d210246a CW |
3980 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
3981 | pineview_display_hplloff_wm.fifo_size, | |
d4294342 ZY |
3982 | pixel_size, latency->cursor_hpll_disable); |
3983 | reg = I915_READ(DSPFW3); | |
3984 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
3985 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
3986 | I915_WRITE(DSPFW3, reg); | |
3987 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
3988 | ||
3989 | /* activate cxsr */ | |
3e33d94d CW |
3990 | I915_WRITE(DSPFW3, |
3991 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); | |
d4294342 ZY |
3992 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); |
3993 | } else { | |
3994 | pineview_disable_cxsr(dev); | |
3995 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); | |
3996 | } | |
3997 | } | |
3998 | ||
417ae147 CW |
3999 | static bool g4x_compute_wm0(struct drm_device *dev, |
4000 | int plane, | |
4001 | const struct intel_watermark_params *display, | |
4002 | int display_latency_ns, | |
4003 | const struct intel_watermark_params *cursor, | |
4004 | int cursor_latency_ns, | |
4005 | int *plane_wm, | |
4006 | int *cursor_wm) | |
4007 | { | |
4008 | struct drm_crtc *crtc; | |
4009 | int htotal, hdisplay, clock, pixel_size; | |
4010 | int line_time_us, line_count; | |
4011 | int entries, tlb_miss; | |
4012 | ||
4013 | crtc = intel_get_crtc_for_plane(dev, plane); | |
5c72d064 CW |
4014 | if (crtc->fb == NULL || !crtc->enabled) { |
4015 | *cursor_wm = cursor->guard_size; | |
4016 | *plane_wm = display->guard_size; | |
417ae147 | 4017 | return false; |
5c72d064 | 4018 | } |
417ae147 CW |
4019 | |
4020 | htotal = crtc->mode.htotal; | |
4021 | hdisplay = crtc->mode.hdisplay; | |
4022 | clock = crtc->mode.clock; | |
4023 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
4024 | ||
4025 | /* Use the small buffer method to calculate plane watermark */ | |
4026 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
4027 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; | |
4028 | if (tlb_miss > 0) | |
4029 | entries += tlb_miss; | |
4030 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
4031 | *plane_wm = entries + display->guard_size; | |
4032 | if (*plane_wm > (int)display->max_wm) | |
4033 | *plane_wm = display->max_wm; | |
4034 | ||
4035 | /* Use the large buffer method to calculate cursor watermark */ | |
4036 | line_time_us = ((htotal * 1000) / clock); | |
4037 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; | |
4038 | entries = line_count * 64 * pixel_size; | |
4039 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; | |
4040 | if (tlb_miss > 0) | |
4041 | entries += tlb_miss; | |
4042 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
4043 | *cursor_wm = entries + cursor->guard_size; | |
4044 | if (*cursor_wm > (int)cursor->max_wm) | |
4045 | *cursor_wm = (int)cursor->max_wm; | |
4046 | ||
4047 | return true; | |
4048 | } | |
4049 | ||
4050 | /* | |
4051 | * Check the wm result. | |
4052 | * | |
4053 | * If any calculated watermark values is larger than the maximum value that | |
4054 | * can be programmed into the associated watermark register, that watermark | |
4055 | * must be disabled. | |
4056 | */ | |
4057 | static bool g4x_check_srwm(struct drm_device *dev, | |
4058 | int display_wm, int cursor_wm, | |
4059 | const struct intel_watermark_params *display, | |
4060 | const struct intel_watermark_params *cursor) | |
652c393a | 4061 | { |
417ae147 CW |
4062 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", |
4063 | display_wm, cursor_wm); | |
652c393a | 4064 | |
417ae147 | 4065 | if (display_wm > display->max_wm) { |
bbb0aef5 | 4066 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", |
417ae147 CW |
4067 | display_wm, display->max_wm); |
4068 | return false; | |
4069 | } | |
0e442c60 | 4070 | |
417ae147 | 4071 | if (cursor_wm > cursor->max_wm) { |
bbb0aef5 | 4072 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", |
417ae147 CW |
4073 | cursor_wm, cursor->max_wm); |
4074 | return false; | |
4075 | } | |
0e442c60 | 4076 | |
417ae147 CW |
4077 | if (!(display_wm || cursor_wm)) { |
4078 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
4079 | return false; | |
4080 | } | |
0e442c60 | 4081 | |
417ae147 CW |
4082 | return true; |
4083 | } | |
0e442c60 | 4084 | |
417ae147 | 4085 | static bool g4x_compute_srwm(struct drm_device *dev, |
d210246a CW |
4086 | int plane, |
4087 | int latency_ns, | |
417ae147 CW |
4088 | const struct intel_watermark_params *display, |
4089 | const struct intel_watermark_params *cursor, | |
4090 | int *display_wm, int *cursor_wm) | |
4091 | { | |
d210246a CW |
4092 | struct drm_crtc *crtc; |
4093 | int hdisplay, htotal, pixel_size, clock; | |
417ae147 CW |
4094 | unsigned long line_time_us; |
4095 | int line_count, line_size; | |
4096 | int small, large; | |
4097 | int entries; | |
0e442c60 | 4098 | |
417ae147 CW |
4099 | if (!latency_ns) { |
4100 | *display_wm = *cursor_wm = 0; | |
4101 | return false; | |
4102 | } | |
0e442c60 | 4103 | |
d210246a CW |
4104 | crtc = intel_get_crtc_for_plane(dev, plane); |
4105 | hdisplay = crtc->mode.hdisplay; | |
4106 | htotal = crtc->mode.htotal; | |
4107 | clock = crtc->mode.clock; | |
4108 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
4109 | ||
417ae147 CW |
4110 | line_time_us = (htotal * 1000) / clock; |
4111 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
4112 | line_size = hdisplay * pixel_size; | |
0e442c60 | 4113 | |
417ae147 CW |
4114 | /* Use the minimum of the small and large buffer method for primary */ |
4115 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
4116 | large = line_count * line_size; | |
0e442c60 | 4117 | |
417ae147 CW |
4118 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
4119 | *display_wm = entries + display->guard_size; | |
4fe5e611 | 4120 | |
417ae147 CW |
4121 | /* calculate the self-refresh watermark for display cursor */ |
4122 | entries = line_count * pixel_size * 64; | |
4123 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
4124 | *cursor_wm = entries + cursor->guard_size; | |
4fe5e611 | 4125 | |
417ae147 CW |
4126 | return g4x_check_srwm(dev, |
4127 | *display_wm, *cursor_wm, | |
4128 | display, cursor); | |
4129 | } | |
4fe5e611 | 4130 | |
7ccb4a53 | 4131 | #define single_plane_enabled(mask) is_power_of_2(mask) |
d210246a CW |
4132 | |
4133 | static void g4x_update_wm(struct drm_device *dev) | |
417ae147 CW |
4134 | { |
4135 | static const int sr_latency_ns = 12000; | |
4136 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4137 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
d210246a CW |
4138 | int plane_sr, cursor_sr; |
4139 | unsigned int enabled = 0; | |
417ae147 CW |
4140 | |
4141 | if (g4x_compute_wm0(dev, 0, | |
4142 | &g4x_wm_info, latency_ns, | |
4143 | &g4x_cursor_wm_info, latency_ns, | |
4144 | &planea_wm, &cursora_wm)) | |
d210246a | 4145 | enabled |= 1; |
417ae147 CW |
4146 | |
4147 | if (g4x_compute_wm0(dev, 1, | |
4148 | &g4x_wm_info, latency_ns, | |
4149 | &g4x_cursor_wm_info, latency_ns, | |
4150 | &planeb_wm, &cursorb_wm)) | |
d210246a | 4151 | enabled |= 2; |
417ae147 CW |
4152 | |
4153 | plane_sr = cursor_sr = 0; | |
d210246a CW |
4154 | if (single_plane_enabled(enabled) && |
4155 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
4156 | sr_latency_ns, | |
417ae147 CW |
4157 | &g4x_wm_info, |
4158 | &g4x_cursor_wm_info, | |
4159 | &plane_sr, &cursor_sr)) | |
0e442c60 | 4160 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
417ae147 CW |
4161 | else |
4162 | I915_WRITE(FW_BLC_SELF, | |
4163 | I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); | |
0e442c60 | 4164 | |
308977ac CW |
4165 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
4166 | planea_wm, cursora_wm, | |
4167 | planeb_wm, cursorb_wm, | |
4168 | plane_sr, cursor_sr); | |
0e442c60 | 4169 | |
417ae147 CW |
4170 | I915_WRITE(DSPFW1, |
4171 | (plane_sr << DSPFW_SR_SHIFT) | | |
0e442c60 | 4172 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
417ae147 CW |
4173 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
4174 | planea_wm); | |
4175 | I915_WRITE(DSPFW2, | |
4176 | (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | | |
0e442c60 JB |
4177 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
4178 | /* HPLL off in SR has some issues on G4x... disable it */ | |
417ae147 CW |
4179 | I915_WRITE(DSPFW3, |
4180 | (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | | |
0e442c60 | 4181 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
652c393a JB |
4182 | } |
4183 | ||
d210246a | 4184 | static void i965_update_wm(struct drm_device *dev) |
7662c8bd SL |
4185 | { |
4186 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
4187 | struct drm_crtc *crtc; |
4188 | int srwm = 1; | |
4fe5e611 | 4189 | int cursor_sr = 16; |
1dc7546d JB |
4190 | |
4191 | /* Calc sr entries for one plane configs */ | |
d210246a CW |
4192 | crtc = single_enabled_crtc(dev); |
4193 | if (crtc) { | |
1dc7546d | 4194 | /* self-refresh has much higher latency */ |
69e302a9 | 4195 | static const int sr_latency_ns = 12000; |
d210246a CW |
4196 | int clock = crtc->mode.clock; |
4197 | int htotal = crtc->mode.htotal; | |
4198 | int hdisplay = crtc->mode.hdisplay; | |
4199 | int pixel_size = crtc->fb->bits_per_pixel / 8; | |
4200 | unsigned long line_time_us; | |
4201 | int entries; | |
1dc7546d | 4202 | |
d210246a | 4203 | line_time_us = ((htotal * 1000) / clock); |
1dc7546d JB |
4204 | |
4205 | /* Use ns/us then divide to preserve precision */ | |
d210246a CW |
4206 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
4207 | pixel_size * hdisplay; | |
4208 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); | |
d210246a | 4209 | srwm = I965_FIFO_SIZE - entries; |
1dc7546d JB |
4210 | if (srwm < 0) |
4211 | srwm = 1; | |
1b07e04e | 4212 | srwm &= 0x1ff; |
308977ac CW |
4213 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
4214 | entries, srwm); | |
4fe5e611 | 4215 | |
d210246a | 4216 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
5eddb70b | 4217 | pixel_size * 64; |
d210246a | 4218 | entries = DIV_ROUND_UP(entries, |
8de9b311 | 4219 | i965_cursor_wm_info.cacheline_size); |
4fe5e611 | 4220 | cursor_sr = i965_cursor_wm_info.fifo_size - |
d210246a | 4221 | (entries + i965_cursor_wm_info.guard_size); |
4fe5e611 ZY |
4222 | |
4223 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
4224 | cursor_sr = i965_cursor_wm_info.max_wm; | |
4225 | ||
4226 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
4227 | "cursor %d\n", srwm, cursor_sr); | |
4228 | ||
a6c45cf0 | 4229 | if (IS_CRESTLINE(dev)) |
adcdbc66 | 4230 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
33c5fd12 DJ |
4231 | } else { |
4232 | /* Turn off self refresh if both pipes are enabled */ | |
a6c45cf0 | 4233 | if (IS_CRESTLINE(dev)) |
adcdbc66 JB |
4234 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) |
4235 | & ~FW_BLC_SELF_EN); | |
1dc7546d | 4236 | } |
7662c8bd | 4237 | |
1dc7546d JB |
4238 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
4239 | srwm); | |
7662c8bd SL |
4240 | |
4241 | /* 965 has limitations... */ | |
417ae147 CW |
4242 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | |
4243 | (8 << 16) | (8 << 8) | (8 << 0)); | |
7662c8bd | 4244 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); |
4fe5e611 ZY |
4245 | /* update cursor SR watermark */ |
4246 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
7662c8bd SL |
4247 | } |
4248 | ||
d210246a | 4249 | static void i9xx_update_wm(struct drm_device *dev) |
7662c8bd SL |
4250 | { |
4251 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a | 4252 | const struct intel_watermark_params *wm_info; |
dff33cfc JB |
4253 | uint32_t fwater_lo; |
4254 | uint32_t fwater_hi; | |
d210246a CW |
4255 | int cwm, srwm = 1; |
4256 | int fifo_size; | |
dff33cfc | 4257 | int planea_wm, planeb_wm; |
d210246a | 4258 | struct drm_crtc *crtc, *enabled = NULL; |
7662c8bd | 4259 | |
72557b4f | 4260 | if (IS_I945GM(dev)) |
d210246a | 4261 | wm_info = &i945_wm_info; |
a6c45cf0 | 4262 | else if (!IS_GEN2(dev)) |
d210246a | 4263 | wm_info = &i915_wm_info; |
7662c8bd | 4264 | else |
d210246a CW |
4265 | wm_info = &i855_wm_info; |
4266 | ||
4267 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); | |
4268 | crtc = intel_get_crtc_for_plane(dev, 0); | |
4269 | if (crtc->enabled && crtc->fb) { | |
4270 | planea_wm = intel_calculate_wm(crtc->mode.clock, | |
4271 | wm_info, fifo_size, | |
4272 | crtc->fb->bits_per_pixel / 8, | |
4273 | latency_ns); | |
4274 | enabled = crtc; | |
4275 | } else | |
4276 | planea_wm = fifo_size - wm_info->guard_size; | |
4277 | ||
4278 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
4279 | crtc = intel_get_crtc_for_plane(dev, 1); | |
4280 | if (crtc->enabled && crtc->fb) { | |
4281 | planeb_wm = intel_calculate_wm(crtc->mode.clock, | |
4282 | wm_info, fifo_size, | |
4283 | crtc->fb->bits_per_pixel / 8, | |
4284 | latency_ns); | |
4285 | if (enabled == NULL) | |
4286 | enabled = crtc; | |
4287 | else | |
4288 | enabled = NULL; | |
4289 | } else | |
4290 | planeb_wm = fifo_size - wm_info->guard_size; | |
7662c8bd | 4291 | |
28c97730 | 4292 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
7662c8bd SL |
4293 | |
4294 | /* | |
4295 | * Overlay gets an aggressive default since video jitter is bad. | |
4296 | */ | |
4297 | cwm = 2; | |
4298 | ||
18b2190c AL |
4299 | /* Play safe and disable self-refresh before adjusting watermarks. */ |
4300 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
4301 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); | |
4302 | else if (IS_I915GM(dev)) | |
4303 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); | |
4304 | ||
dff33cfc | 4305 | /* Calc sr entries for one plane configs */ |
d210246a | 4306 | if (HAS_FW_BLC(dev) && enabled) { |
dff33cfc | 4307 | /* self-refresh has much higher latency */ |
69e302a9 | 4308 | static const int sr_latency_ns = 6000; |
d210246a CW |
4309 | int clock = enabled->mode.clock; |
4310 | int htotal = enabled->mode.htotal; | |
4311 | int hdisplay = enabled->mode.hdisplay; | |
4312 | int pixel_size = enabled->fb->bits_per_pixel / 8; | |
4313 | unsigned long line_time_us; | |
4314 | int entries; | |
dff33cfc | 4315 | |
d210246a | 4316 | line_time_us = (htotal * 1000) / clock; |
dff33cfc JB |
4317 | |
4318 | /* Use ns/us then divide to preserve precision */ | |
d210246a CW |
4319 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
4320 | pixel_size * hdisplay; | |
4321 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); | |
4322 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
4323 | srwm = wm_info->fifo_size - entries; | |
dff33cfc JB |
4324 | if (srwm < 0) |
4325 | srwm = 1; | |
ee980b80 LP |
4326 | |
4327 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
18b2190c AL |
4328 | I915_WRITE(FW_BLC_SELF, |
4329 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
4330 | else if (IS_I915GM(dev)) | |
ee980b80 | 4331 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
7662c8bd SL |
4332 | } |
4333 | ||
28c97730 | 4334 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
5eddb70b | 4335 | planea_wm, planeb_wm, cwm, srwm); |
7662c8bd | 4336 | |
dff33cfc JB |
4337 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
4338 | fwater_hi = (cwm & 0x1f); | |
4339 | ||
4340 | /* Set request length to 8 cachelines per fetch */ | |
4341 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
4342 | fwater_hi = fwater_hi | (1 << 8); | |
7662c8bd SL |
4343 | |
4344 | I915_WRITE(FW_BLC, fwater_lo); | |
4345 | I915_WRITE(FW_BLC2, fwater_hi); | |
18b2190c | 4346 | |
d210246a CW |
4347 | if (HAS_FW_BLC(dev)) { |
4348 | if (enabled) { | |
4349 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
4350 | I915_WRITE(FW_BLC_SELF, | |
4351 | FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); | |
4352 | else if (IS_I915GM(dev)) | |
4353 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); | |
4354 | DRM_DEBUG_KMS("memory self refresh enabled\n"); | |
4355 | } else | |
4356 | DRM_DEBUG_KMS("memory self refresh disabled\n"); | |
4357 | } | |
7662c8bd SL |
4358 | } |
4359 | ||
d210246a | 4360 | static void i830_update_wm(struct drm_device *dev) |
7662c8bd SL |
4361 | { |
4362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
4363 | struct drm_crtc *crtc; |
4364 | uint32_t fwater_lo; | |
dff33cfc | 4365 | int planea_wm; |
7662c8bd | 4366 | |
d210246a CW |
4367 | crtc = single_enabled_crtc(dev); |
4368 | if (crtc == NULL) | |
4369 | return; | |
7662c8bd | 4370 | |
d210246a CW |
4371 | planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, |
4372 | dev_priv->display.get_fifo_size(dev, 0), | |
4373 | crtc->fb->bits_per_pixel / 8, | |
4374 | latency_ns); | |
4375 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; | |
f3601326 JB |
4376 | fwater_lo |= (3<<8) | planea_wm; |
4377 | ||
28c97730 | 4378 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
7662c8bd SL |
4379 | |
4380 | I915_WRITE(FW_BLC, fwater_lo); | |
4381 | } | |
4382 | ||
7f8a8569 | 4383 | #define ILK_LP0_PLANE_LATENCY 700 |
c936f44d | 4384 | #define ILK_LP0_CURSOR_LATENCY 1300 |
7f8a8569 | 4385 | |
1398261a YL |
4386 | /* |
4387 | * Check the wm result. | |
4388 | * | |
4389 | * If any calculated watermark values is larger than the maximum value that | |
4390 | * can be programmed into the associated watermark register, that watermark | |
4391 | * must be disabled. | |
1398261a | 4392 | */ |
b79d4990 JB |
4393 | static bool ironlake_check_srwm(struct drm_device *dev, int level, |
4394 | int fbc_wm, int display_wm, int cursor_wm, | |
4395 | const struct intel_watermark_params *display, | |
4396 | const struct intel_watermark_params *cursor) | |
1398261a YL |
4397 | { |
4398 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4399 | ||
4400 | DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," | |
4401 | " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); | |
4402 | ||
4403 | if (fbc_wm > SNB_FBC_MAX_SRWM) { | |
4404 | DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", | |
b79d4990 | 4405 | fbc_wm, SNB_FBC_MAX_SRWM, level); |
1398261a YL |
4406 | |
4407 | /* fbc has it's own way to disable FBC WM */ | |
4408 | I915_WRITE(DISP_ARB_CTL, | |
4409 | I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); | |
4410 | return false; | |
4411 | } | |
4412 | ||
b79d4990 | 4413 | if (display_wm > display->max_wm) { |
1398261a | 4414 | DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", |
b79d4990 | 4415 | display_wm, SNB_DISPLAY_MAX_SRWM, level); |
1398261a YL |
4416 | return false; |
4417 | } | |
4418 | ||
b79d4990 | 4419 | if (cursor_wm > cursor->max_wm) { |
1398261a | 4420 | DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", |
b79d4990 | 4421 | cursor_wm, SNB_CURSOR_MAX_SRWM, level); |
1398261a YL |
4422 | return false; |
4423 | } | |
4424 | ||
4425 | if (!(fbc_wm || display_wm || cursor_wm)) { | |
4426 | DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); | |
4427 | return false; | |
4428 | } | |
4429 | ||
4430 | return true; | |
4431 | } | |
4432 | ||
4433 | /* | |
4434 | * Compute watermark values of WM[1-3], | |
4435 | */ | |
d210246a CW |
4436 | static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, |
4437 | int latency_ns, | |
b79d4990 JB |
4438 | const struct intel_watermark_params *display, |
4439 | const struct intel_watermark_params *cursor, | |
4440 | int *fbc_wm, int *display_wm, int *cursor_wm) | |
1398261a | 4441 | { |
d210246a | 4442 | struct drm_crtc *crtc; |
1398261a | 4443 | unsigned long line_time_us; |
d210246a | 4444 | int hdisplay, htotal, pixel_size, clock; |
b79d4990 | 4445 | int line_count, line_size; |
1398261a YL |
4446 | int small, large; |
4447 | int entries; | |
1398261a YL |
4448 | |
4449 | if (!latency_ns) { | |
4450 | *fbc_wm = *display_wm = *cursor_wm = 0; | |
4451 | return false; | |
4452 | } | |
4453 | ||
d210246a CW |
4454 | crtc = intel_get_crtc_for_plane(dev, plane); |
4455 | hdisplay = crtc->mode.hdisplay; | |
4456 | htotal = crtc->mode.htotal; | |
4457 | clock = crtc->mode.clock; | |
4458 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
4459 | ||
1398261a YL |
4460 | line_time_us = (htotal * 1000) / clock; |
4461 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
4462 | line_size = hdisplay * pixel_size; | |
4463 | ||
4464 | /* Use the minimum of the small and large buffer method for primary */ | |
4465 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
4466 | large = line_count * line_size; | |
4467 | ||
b79d4990 JB |
4468 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
4469 | *display_wm = entries + display->guard_size; | |
1398261a YL |
4470 | |
4471 | /* | |
b79d4990 | 4472 | * Spec says: |
1398261a YL |
4473 | * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 |
4474 | */ | |
4475 | *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; | |
4476 | ||
4477 | /* calculate the self-refresh watermark for display cursor */ | |
4478 | entries = line_count * pixel_size * 64; | |
b79d4990 JB |
4479 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
4480 | *cursor_wm = entries + cursor->guard_size; | |
1398261a | 4481 | |
b79d4990 JB |
4482 | return ironlake_check_srwm(dev, level, |
4483 | *fbc_wm, *display_wm, *cursor_wm, | |
4484 | display, cursor); | |
4485 | } | |
4486 | ||
d210246a | 4487 | static void ironlake_update_wm(struct drm_device *dev) |
b79d4990 JB |
4488 | { |
4489 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d210246a CW |
4490 | int fbc_wm, plane_wm, cursor_wm; |
4491 | unsigned int enabled; | |
b79d4990 JB |
4492 | |
4493 | enabled = 0; | |
9f405100 CW |
4494 | if (g4x_compute_wm0(dev, 0, |
4495 | &ironlake_display_wm_info, | |
4496 | ILK_LP0_PLANE_LATENCY, | |
4497 | &ironlake_cursor_wm_info, | |
4498 | ILK_LP0_CURSOR_LATENCY, | |
4499 | &plane_wm, &cursor_wm)) { | |
b79d4990 JB |
4500 | I915_WRITE(WM0_PIPEA_ILK, |
4501 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
4502 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
4503 | " plane %d, " "cursor: %d\n", | |
4504 | plane_wm, cursor_wm); | |
d210246a | 4505 | enabled |= 1; |
b79d4990 JB |
4506 | } |
4507 | ||
9f405100 CW |
4508 | if (g4x_compute_wm0(dev, 1, |
4509 | &ironlake_display_wm_info, | |
4510 | ILK_LP0_PLANE_LATENCY, | |
4511 | &ironlake_cursor_wm_info, | |
4512 | ILK_LP0_CURSOR_LATENCY, | |
4513 | &plane_wm, &cursor_wm)) { | |
b79d4990 JB |
4514 | I915_WRITE(WM0_PIPEB_ILK, |
4515 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
4516 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
4517 | " plane %d, cursor: %d\n", | |
4518 | plane_wm, cursor_wm); | |
d210246a | 4519 | enabled |= 2; |
b79d4990 JB |
4520 | } |
4521 | ||
4522 | /* | |
4523 | * Calculate and update the self-refresh watermark only when one | |
4524 | * display plane is used. | |
4525 | */ | |
4526 | I915_WRITE(WM3_LP_ILK, 0); | |
4527 | I915_WRITE(WM2_LP_ILK, 0); | |
4528 | I915_WRITE(WM1_LP_ILK, 0); | |
4529 | ||
d210246a | 4530 | if (!single_plane_enabled(enabled)) |
b79d4990 | 4531 | return; |
d210246a | 4532 | enabled = ffs(enabled) - 1; |
b79d4990 JB |
4533 | |
4534 | /* WM1 */ | |
d210246a CW |
4535 | if (!ironlake_compute_srwm(dev, 1, enabled, |
4536 | ILK_READ_WM1_LATENCY() * 500, | |
b79d4990 JB |
4537 | &ironlake_display_srwm_info, |
4538 | &ironlake_cursor_srwm_info, | |
4539 | &fbc_wm, &plane_wm, &cursor_wm)) | |
4540 | return; | |
4541 | ||
4542 | I915_WRITE(WM1_LP_ILK, | |
4543 | WM1_LP_SR_EN | | |
4544 | (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4545 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4546 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4547 | cursor_wm); | |
4548 | ||
4549 | /* WM2 */ | |
d210246a CW |
4550 | if (!ironlake_compute_srwm(dev, 2, enabled, |
4551 | ILK_READ_WM2_LATENCY() * 500, | |
b79d4990 JB |
4552 | &ironlake_display_srwm_info, |
4553 | &ironlake_cursor_srwm_info, | |
4554 | &fbc_wm, &plane_wm, &cursor_wm)) | |
4555 | return; | |
4556 | ||
4557 | I915_WRITE(WM2_LP_ILK, | |
4558 | WM2_LP_EN | | |
4559 | (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4560 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4561 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4562 | cursor_wm); | |
4563 | ||
4564 | /* | |
4565 | * WM3 is unsupported on ILK, probably because we don't have latency | |
4566 | * data for that power state | |
4567 | */ | |
1398261a YL |
4568 | } |
4569 | ||
b840d907 | 4570 | void sandybridge_update_wm(struct drm_device *dev) |
1398261a YL |
4571 | { |
4572 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a0fa62d3 | 4573 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ |
47842649 | 4574 | u32 val; |
d210246a CW |
4575 | int fbc_wm, plane_wm, cursor_wm; |
4576 | unsigned int enabled; | |
1398261a YL |
4577 | |
4578 | enabled = 0; | |
9f405100 CW |
4579 | if (g4x_compute_wm0(dev, 0, |
4580 | &sandybridge_display_wm_info, latency, | |
4581 | &sandybridge_cursor_wm_info, latency, | |
4582 | &plane_wm, &cursor_wm)) { | |
47842649 JB |
4583 | val = I915_READ(WM0_PIPEA_ILK); |
4584 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
4585 | I915_WRITE(WM0_PIPEA_ILK, val | | |
4586 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | |
1398261a YL |
4587 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" |
4588 | " plane %d, " "cursor: %d\n", | |
4589 | plane_wm, cursor_wm); | |
d210246a | 4590 | enabled |= 1; |
1398261a YL |
4591 | } |
4592 | ||
9f405100 CW |
4593 | if (g4x_compute_wm0(dev, 1, |
4594 | &sandybridge_display_wm_info, latency, | |
4595 | &sandybridge_cursor_wm_info, latency, | |
4596 | &plane_wm, &cursor_wm)) { | |
47842649 JB |
4597 | val = I915_READ(WM0_PIPEB_ILK); |
4598 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
4599 | I915_WRITE(WM0_PIPEB_ILK, val | | |
4600 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | |
1398261a YL |
4601 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" |
4602 | " plane %d, cursor: %d\n", | |
4603 | plane_wm, cursor_wm); | |
d210246a | 4604 | enabled |= 2; |
1398261a YL |
4605 | } |
4606 | ||
d6c892df JB |
4607 | /* IVB has 3 pipes */ |
4608 | if (IS_IVYBRIDGE(dev) && | |
4609 | g4x_compute_wm0(dev, 2, | |
4610 | &sandybridge_display_wm_info, latency, | |
4611 | &sandybridge_cursor_wm_info, latency, | |
4612 | &plane_wm, &cursor_wm)) { | |
47842649 JB |
4613 | val = I915_READ(WM0_PIPEC_IVB); |
4614 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
4615 | I915_WRITE(WM0_PIPEC_IVB, val | | |
4616 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | |
d6c892df JB |
4617 | DRM_DEBUG_KMS("FIFO watermarks For pipe C -" |
4618 | " plane %d, cursor: %d\n", | |
4619 | plane_wm, cursor_wm); | |
4620 | enabled |= 3; | |
4621 | } | |
4622 | ||
1398261a YL |
4623 | /* |
4624 | * Calculate and update the self-refresh watermark only when one | |
4625 | * display plane is used. | |
4626 | * | |
4627 | * SNB support 3 levels of watermark. | |
4628 | * | |
4629 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, | |
4630 | * and disabled in the descending order | |
4631 | * | |
4632 | */ | |
4633 | I915_WRITE(WM3_LP_ILK, 0); | |
4634 | I915_WRITE(WM2_LP_ILK, 0); | |
4635 | I915_WRITE(WM1_LP_ILK, 0); | |
4636 | ||
b840d907 JB |
4637 | if (!single_plane_enabled(enabled) || |
4638 | dev_priv->sprite_scaling_enabled) | |
1398261a | 4639 | return; |
d210246a | 4640 | enabled = ffs(enabled) - 1; |
1398261a YL |
4641 | |
4642 | /* WM1 */ | |
d210246a CW |
4643 | if (!ironlake_compute_srwm(dev, 1, enabled, |
4644 | SNB_READ_WM1_LATENCY() * 500, | |
b79d4990 JB |
4645 | &sandybridge_display_srwm_info, |
4646 | &sandybridge_cursor_srwm_info, | |
4647 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4648 | return; |
4649 | ||
4650 | I915_WRITE(WM1_LP_ILK, | |
4651 | WM1_LP_SR_EN | | |
4652 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4653 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4654 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4655 | cursor_wm); | |
4656 | ||
4657 | /* WM2 */ | |
d210246a CW |
4658 | if (!ironlake_compute_srwm(dev, 2, enabled, |
4659 | SNB_READ_WM2_LATENCY() * 500, | |
b79d4990 JB |
4660 | &sandybridge_display_srwm_info, |
4661 | &sandybridge_cursor_srwm_info, | |
4662 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4663 | return; |
4664 | ||
4665 | I915_WRITE(WM2_LP_ILK, | |
4666 | WM2_LP_EN | | |
4667 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4668 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4669 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4670 | cursor_wm); | |
4671 | ||
4672 | /* WM3 */ | |
d210246a CW |
4673 | if (!ironlake_compute_srwm(dev, 3, enabled, |
4674 | SNB_READ_WM3_LATENCY() * 500, | |
b79d4990 JB |
4675 | &sandybridge_display_srwm_info, |
4676 | &sandybridge_cursor_srwm_info, | |
4677 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1398261a YL |
4678 | return; |
4679 | ||
4680 | I915_WRITE(WM3_LP_ILK, | |
4681 | WM3_LP_EN | | |
4682 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
4683 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
4684 | (plane_wm << WM1_LP_SR_SHIFT) | | |
4685 | cursor_wm); | |
4686 | } | |
4687 | ||
b840d907 JB |
4688 | static bool |
4689 | sandybridge_compute_sprite_wm(struct drm_device *dev, int plane, | |
4690 | uint32_t sprite_width, int pixel_size, | |
4691 | const struct intel_watermark_params *display, | |
4692 | int display_latency_ns, int *sprite_wm) | |
4693 | { | |
4694 | struct drm_crtc *crtc; | |
4695 | int clock; | |
4696 | int entries, tlb_miss; | |
4697 | ||
4698 | crtc = intel_get_crtc_for_plane(dev, plane); | |
4699 | if (crtc->fb == NULL || !crtc->enabled) { | |
4700 | *sprite_wm = display->guard_size; | |
4701 | return false; | |
4702 | } | |
4703 | ||
4704 | clock = crtc->mode.clock; | |
4705 | ||
4706 | /* Use the small buffer method to calculate the sprite watermark */ | |
4707 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
4708 | tlb_miss = display->fifo_size*display->cacheline_size - | |
4709 | sprite_width * 8; | |
4710 | if (tlb_miss > 0) | |
4711 | entries += tlb_miss; | |
4712 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
4713 | *sprite_wm = entries + display->guard_size; | |
4714 | if (*sprite_wm > (int)display->max_wm) | |
4715 | *sprite_wm = display->max_wm; | |
4716 | ||
4717 | return true; | |
4718 | } | |
4719 | ||
4720 | static bool | |
4721 | sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, | |
4722 | uint32_t sprite_width, int pixel_size, | |
4723 | const struct intel_watermark_params *display, | |
4724 | int latency_ns, int *sprite_wm) | |
4725 | { | |
4726 | struct drm_crtc *crtc; | |
4727 | unsigned long line_time_us; | |
4728 | int clock; | |
4729 | int line_count, line_size; | |
4730 | int small, large; | |
4731 | int entries; | |
4732 | ||
4733 | if (!latency_ns) { | |
4734 | *sprite_wm = 0; | |
4735 | return false; | |
4736 | } | |
4737 | ||
4738 | crtc = intel_get_crtc_for_plane(dev, plane); | |
4739 | clock = crtc->mode.clock; | |
4e9bb47b HL |
4740 | if (!clock) { |
4741 | *sprite_wm = 0; | |
4742 | return false; | |
4743 | } | |
b840d907 JB |
4744 | |
4745 | line_time_us = (sprite_width * 1000) / clock; | |
4e9bb47b HL |
4746 | if (!line_time_us) { |
4747 | *sprite_wm = 0; | |
4748 | return false; | |
4749 | } | |
4750 | ||
b840d907 JB |
4751 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
4752 | line_size = sprite_width * pixel_size; | |
4753 | ||
4754 | /* Use the minimum of the small and large buffer method for primary */ | |
4755 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
4756 | large = line_count * line_size; | |
4757 | ||
4758 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
4759 | *sprite_wm = entries + display->guard_size; | |
4760 | ||
4761 | return *sprite_wm > 0x3ff ? false : true; | |
4762 | } | |
4763 | ||
4764 | static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, | |
4765 | uint32_t sprite_width, int pixel_size) | |
4766 | { | |
4767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4768 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ | |
47842649 | 4769 | u32 val; |
b840d907 JB |
4770 | int sprite_wm, reg; |
4771 | int ret; | |
4772 | ||
4773 | switch (pipe) { | |
4774 | case 0: | |
4775 | reg = WM0_PIPEA_ILK; | |
4776 | break; | |
4777 | case 1: | |
4778 | reg = WM0_PIPEB_ILK; | |
4779 | break; | |
4780 | case 2: | |
4781 | reg = WM0_PIPEC_IVB; | |
4782 | break; | |
4783 | default: | |
4784 | return; /* bad pipe */ | |
4785 | } | |
4786 | ||
4787 | ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size, | |
4788 | &sandybridge_display_wm_info, | |
4789 | latency, &sprite_wm); | |
4790 | if (!ret) { | |
4791 | DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n", | |
4792 | pipe); | |
4793 | return; | |
4794 | } | |
4795 | ||
47842649 JB |
4796 | val = I915_READ(reg); |
4797 | val &= ~WM0_PIPE_SPRITE_MASK; | |
4798 | I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); | |
b840d907 JB |
4799 | DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm); |
4800 | ||
4801 | ||
4802 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, | |
4803 | pixel_size, | |
4804 | &sandybridge_display_srwm_info, | |
4805 | SNB_READ_WM1_LATENCY() * 500, | |
4806 | &sprite_wm); | |
4807 | if (!ret) { | |
4808 | DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n", | |
4809 | pipe); | |
4810 | return; | |
4811 | } | |
4812 | I915_WRITE(WM1S_LP_ILK, sprite_wm); | |
4813 | ||
4814 | /* Only IVB has two more LP watermarks for sprite */ | |
4815 | if (!IS_IVYBRIDGE(dev)) | |
4816 | return; | |
4817 | ||
4818 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, | |
4819 | pixel_size, | |
4820 | &sandybridge_display_srwm_info, | |
4821 | SNB_READ_WM2_LATENCY() * 500, | |
4822 | &sprite_wm); | |
4823 | if (!ret) { | |
4824 | DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n", | |
4825 | pipe); | |
4826 | return; | |
4827 | } | |
4828 | I915_WRITE(WM2S_LP_IVB, sprite_wm); | |
4829 | ||
4830 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, | |
4831 | pixel_size, | |
4832 | &sandybridge_display_srwm_info, | |
4833 | SNB_READ_WM3_LATENCY() * 500, | |
4834 | &sprite_wm); | |
4835 | if (!ret) { | |
4836 | DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n", | |
4837 | pipe); | |
4838 | return; | |
4839 | } | |
4840 | I915_WRITE(WM3S_LP_IVB, sprite_wm); | |
4841 | } | |
4842 | ||
7662c8bd SL |
4843 | /** |
4844 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
4845 | * | |
4846 | * Calculate watermark values for the various WM regs based on current mode | |
4847 | * and plane configuration. | |
4848 | * | |
4849 | * There are several cases to deal with here: | |
4850 | * - normal (i.e. non-self-refresh) | |
4851 | * - self-refresh (SR) mode | |
4852 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
4853 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
4854 | * lines), so need to account for TLB latency | |
4855 | * | |
4856 | * The normal calculation is: | |
4857 | * watermark = dotclock * bytes per pixel * latency | |
4858 | * where latency is platform & configuration dependent (we assume pessimal | |
4859 | * values here). | |
4860 | * | |
4861 | * The SR calculation is: | |
4862 | * watermark = (trunc(latency/line time)+1) * surface width * | |
4863 | * bytes per pixel | |
4864 | * where | |
4865 | * line time = htotal / dotclock | |
fa143215 | 4866 | * surface width = hdisplay for normal plane and 64 for cursor |
7662c8bd SL |
4867 | * and latency is assumed to be high, as above. |
4868 | * | |
4869 | * The final value programmed to the register should always be rounded up, | |
4870 | * and include an extra 2 entries to account for clock crossings. | |
4871 | * | |
4872 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
4873 | * to set the non-SR watermarks to 8. | |
5eddb70b | 4874 | */ |
7662c8bd SL |
4875 | static void intel_update_watermarks(struct drm_device *dev) |
4876 | { | |
e70236a8 | 4877 | struct drm_i915_private *dev_priv = dev->dev_private; |
7662c8bd | 4878 | |
d210246a CW |
4879 | if (dev_priv->display.update_wm) |
4880 | dev_priv->display.update_wm(dev); | |
7662c8bd SL |
4881 | } |
4882 | ||
b840d907 JB |
4883 | void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
4884 | uint32_t sprite_width, int pixel_size) | |
4885 | { | |
4886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4887 | ||
4888 | if (dev_priv->display.update_sprite_wm) | |
4889 | dev_priv->display.update_sprite_wm(dev, pipe, sprite_width, | |
4890 | pixel_size); | |
4891 | } | |
4892 | ||
a7615030 CW |
4893 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
4894 | { | |
72bbe58c KP |
4895 | if (i915_panel_use_ssc >= 0) |
4896 | return i915_panel_use_ssc != 0; | |
4897 | return dev_priv->lvds_use_ssc | |
435793df | 4898 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
4899 | } |
4900 | ||
5a354204 JB |
4901 | /** |
4902 | * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send | |
4903 | * @crtc: CRTC structure | |
3b5c78a3 | 4904 | * @mode: requested mode |
5a354204 JB |
4905 | * |
4906 | * A pipe may be connected to one or more outputs. Based on the depth of the | |
4907 | * attached framebuffer, choose a good color depth to use on the pipe. | |
4908 | * | |
4909 | * If possible, match the pipe depth to the fb depth. In some cases, this | |
4910 | * isn't ideal, because the connected output supports a lesser or restricted | |
4911 | * set of depths. Resolve that here: | |
4912 | * LVDS typically supports only 6bpc, so clamp down in that case | |
4913 | * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc | |
4914 | * Displays may support a restricted set as well, check EDID and clamp as | |
4915 | * appropriate. | |
3b5c78a3 | 4916 | * DP may want to dither down to 6bpc to fit larger modes |
5a354204 JB |
4917 | * |
4918 | * RETURNS: | |
4919 | * Dithering requirement (i.e. false if display bpc and pipe bpc match, | |
4920 | * true if they don't match). | |
4921 | */ | |
4922 | static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, | |
3b5c78a3 AJ |
4923 | unsigned int *pipe_bpp, |
4924 | struct drm_display_mode *mode) | |
5a354204 JB |
4925 | { |
4926 | struct drm_device *dev = crtc->dev; | |
4927 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4928 | struct drm_encoder *encoder; | |
4929 | struct drm_connector *connector; | |
4930 | unsigned int display_bpc = UINT_MAX, bpc; | |
4931 | ||
4932 | /* Walk the encoders & connectors on this crtc, get min bpc */ | |
4933 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
4934 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
4935 | ||
4936 | if (encoder->crtc != crtc) | |
4937 | continue; | |
4938 | ||
4939 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) { | |
4940 | unsigned int lvds_bpc; | |
4941 | ||
4942 | if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == | |
4943 | LVDS_A3_POWER_UP) | |
4944 | lvds_bpc = 8; | |
4945 | else | |
4946 | lvds_bpc = 6; | |
4947 | ||
4948 | if (lvds_bpc < display_bpc) { | |
82820490 | 4949 | DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); |
5a354204 JB |
4950 | display_bpc = lvds_bpc; |
4951 | } | |
4952 | continue; | |
4953 | } | |
4954 | ||
4955 | if (intel_encoder->type == INTEL_OUTPUT_EDP) { | |
4956 | /* Use VBT settings if we have an eDP panel */ | |
4957 | unsigned int edp_bpc = dev_priv->edp.bpp / 3; | |
4958 | ||
4959 | if (edp_bpc < display_bpc) { | |
82820490 | 4960 | DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); |
5a354204 JB |
4961 | display_bpc = edp_bpc; |
4962 | } | |
4963 | continue; | |
4964 | } | |
4965 | ||
4966 | /* Not one of the known troublemakers, check the EDID */ | |
4967 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
4968 | head) { | |
4969 | if (connector->encoder != encoder) | |
4970 | continue; | |
4971 | ||
62ac41a6 JB |
4972 | /* Don't use an invalid EDID bpc value */ |
4973 | if (connector->display_info.bpc && | |
4974 | connector->display_info.bpc < display_bpc) { | |
82820490 | 4975 | DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); |
5a354204 JB |
4976 | display_bpc = connector->display_info.bpc; |
4977 | } | |
4978 | } | |
4979 | ||
4980 | /* | |
4981 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
4982 | * through, clamp it down. (Note: >12bpc will be caught below.) | |
4983 | */ | |
4984 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { | |
4985 | if (display_bpc > 8 && display_bpc < 12) { | |
82820490 | 4986 | DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); |
5a354204 JB |
4987 | display_bpc = 12; |
4988 | } else { | |
82820490 | 4989 | DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); |
5a354204 JB |
4990 | display_bpc = 8; |
4991 | } | |
4992 | } | |
4993 | } | |
4994 | ||
3b5c78a3 AJ |
4995 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { |
4996 | DRM_DEBUG_KMS("Dithering DP to 6bpc\n"); | |
4997 | display_bpc = 6; | |
4998 | } | |
4999 | ||
5a354204 JB |
5000 | /* |
5001 | * We could just drive the pipe at the highest bpc all the time and | |
5002 | * enable dithering as needed, but that costs bandwidth. So choose | |
5003 | * the minimum value that expresses the full color range of the fb but | |
5004 | * also stays within the max display bpc discovered above. | |
5005 | */ | |
5006 | ||
5007 | switch (crtc->fb->depth) { | |
5008 | case 8: | |
5009 | bpc = 8; /* since we go through a colormap */ | |
5010 | break; | |
5011 | case 15: | |
5012 | case 16: | |
5013 | bpc = 6; /* min is 18bpp */ | |
5014 | break; | |
5015 | case 24: | |
578393cd | 5016 | bpc = 8; |
5a354204 JB |
5017 | break; |
5018 | case 30: | |
578393cd | 5019 | bpc = 10; |
5a354204 JB |
5020 | break; |
5021 | case 48: | |
578393cd | 5022 | bpc = 12; |
5a354204 JB |
5023 | break; |
5024 | default: | |
5025 | DRM_DEBUG("unsupported depth, assuming 24 bits\n"); | |
5026 | bpc = min((unsigned int)8, display_bpc); | |
5027 | break; | |
5028 | } | |
5029 | ||
578393cd KP |
5030 | display_bpc = min(display_bpc, bpc); |
5031 | ||
82820490 AJ |
5032 | DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n", |
5033 | bpc, display_bpc); | |
5a354204 | 5034 | |
578393cd | 5035 | *pipe_bpp = display_bpc * 3; |
5a354204 JB |
5036 | |
5037 | return display_bpc != bpc; | |
5038 | } | |
5039 | ||
c65d77d8 JB |
5040 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
5041 | { | |
5042 | struct drm_device *dev = crtc->dev; | |
5043 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5044 | int refclk; | |
5045 | ||
5046 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
5047 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
5048 | refclk = dev_priv->lvds_ssc_freq * 1000; | |
5049 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
5050 | refclk / 1000); | |
5051 | } else if (!IS_GEN2(dev)) { | |
5052 | refclk = 96000; | |
5053 | } else { | |
5054 | refclk = 48000; | |
5055 | } | |
5056 | ||
5057 | return refclk; | |
5058 | } | |
5059 | ||
5060 | static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, | |
5061 | intel_clock_t *clock) | |
5062 | { | |
5063 | /* SDVO TV has fixed PLL values depend on its clock range, | |
5064 | this mirrors vbios setting. */ | |
5065 | if (adjusted_mode->clock >= 100000 | |
5066 | && adjusted_mode->clock < 140500) { | |
5067 | clock->p1 = 2; | |
5068 | clock->p2 = 10; | |
5069 | clock->n = 3; | |
5070 | clock->m1 = 16; | |
5071 | clock->m2 = 8; | |
5072 | } else if (adjusted_mode->clock >= 140500 | |
5073 | && adjusted_mode->clock <= 200000) { | |
5074 | clock->p1 = 1; | |
5075 | clock->p2 = 10; | |
5076 | clock->n = 6; | |
5077 | clock->m1 = 12; | |
5078 | clock->m2 = 8; | |
5079 | } | |
5080 | } | |
5081 | ||
a7516a05 JB |
5082 | static void i9xx_update_pll_dividers(struct drm_crtc *crtc, |
5083 | intel_clock_t *clock, | |
5084 | intel_clock_t *reduced_clock) | |
5085 | { | |
5086 | struct drm_device *dev = crtc->dev; | |
5087 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5088 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5089 | int pipe = intel_crtc->pipe; | |
5090 | u32 fp, fp2 = 0; | |
5091 | ||
5092 | if (IS_PINEVIEW(dev)) { | |
5093 | fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; | |
5094 | if (reduced_clock) | |
5095 | fp2 = (1 << reduced_clock->n) << 16 | | |
5096 | reduced_clock->m1 << 8 | reduced_clock->m2; | |
5097 | } else { | |
5098 | fp = clock->n << 16 | clock->m1 << 8 | clock->m2; | |
5099 | if (reduced_clock) | |
5100 | fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | | |
5101 | reduced_clock->m2; | |
5102 | } | |
5103 | ||
5104 | I915_WRITE(FP0(pipe), fp); | |
5105 | ||
5106 | intel_crtc->lowfreq_avail = false; | |
5107 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && | |
5108 | reduced_clock && i915_powersave) { | |
5109 | I915_WRITE(FP1(pipe), fp2); | |
5110 | intel_crtc->lowfreq_avail = true; | |
5111 | } else { | |
5112 | I915_WRITE(FP1(pipe), fp); | |
5113 | } | |
5114 | } | |
5115 | ||
f564048e EA |
5116 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
5117 | struct drm_display_mode *mode, | |
5118 | struct drm_display_mode *adjusted_mode, | |
5119 | int x, int y, | |
5120 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
5121 | { |
5122 | struct drm_device *dev = crtc->dev; | |
5123 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5124 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5125 | int pipe = intel_crtc->pipe; | |
80824003 | 5126 | int plane = intel_crtc->plane; |
c751ce4f | 5127 | int refclk, num_connectors = 0; |
652c393a | 5128 | intel_clock_t clock, reduced_clock; |
0529a0d9 | 5129 | u32 dpll, dspcntr, pipeconf, vsyncshift; |
652c393a | 5130 | bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; |
a4fc5ed6 | 5131 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
79e53945 | 5132 | struct drm_mode_config *mode_config = &dev->mode_config; |
5eddb70b | 5133 | struct intel_encoder *encoder; |
d4906093 | 5134 | const intel_limit_t *limit; |
5c3b82e2 | 5135 | int ret; |
fae14981 | 5136 | u32 temp; |
aa9b500d | 5137 | u32 lvds_sync = 0; |
79e53945 | 5138 | |
5eddb70b CW |
5139 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
5140 | if (encoder->base.crtc != crtc) | |
79e53945 JB |
5141 | continue; |
5142 | ||
5eddb70b | 5143 | switch (encoder->type) { |
79e53945 JB |
5144 | case INTEL_OUTPUT_LVDS: |
5145 | is_lvds = true; | |
5146 | break; | |
5147 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5148 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5149 | is_sdvo = true; |
5eddb70b | 5150 | if (encoder->needs_tv_clock) |
e2f0ba97 | 5151 | is_tv = true; |
79e53945 JB |
5152 | break; |
5153 | case INTEL_OUTPUT_DVO: | |
5154 | is_dvo = true; | |
5155 | break; | |
5156 | case INTEL_OUTPUT_TVOUT: | |
5157 | is_tv = true; | |
5158 | break; | |
5159 | case INTEL_OUTPUT_ANALOG: | |
5160 | is_crt = true; | |
5161 | break; | |
a4fc5ed6 KP |
5162 | case INTEL_OUTPUT_DISPLAYPORT: |
5163 | is_dp = true; | |
5164 | break; | |
79e53945 | 5165 | } |
43565a06 | 5166 | |
c751ce4f | 5167 | num_connectors++; |
79e53945 JB |
5168 | } |
5169 | ||
c65d77d8 | 5170 | refclk = i9xx_get_refclk(crtc, num_connectors); |
79e53945 | 5171 | |
d4906093 ML |
5172 | /* |
5173 | * Returns a set of divisors for the desired target clock with the given | |
5174 | * refclk, or FALSE. The returned values represent the clock equation: | |
5175 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
5176 | */ | |
1b894b59 | 5177 | limit = intel_limit(crtc, refclk); |
cec2f356 SP |
5178 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
5179 | &clock); | |
79e53945 JB |
5180 | if (!ok) { |
5181 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 5182 | return -EINVAL; |
79e53945 JB |
5183 | } |
5184 | ||
cda4b7d3 | 5185 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 5186 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 5187 | |
ddc9003c | 5188 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
5189 | /* |
5190 | * Ensure we match the reduced clock's P to the target clock. | |
5191 | * If the clocks don't match, we can't switch the display clock | |
5192 | * by using the FP0/FP1. In such case we will disable the LVDS | |
5193 | * downclock feature. | |
5194 | */ | |
ddc9003c | 5195 | has_reduced_clock = limit->find_pll(limit, crtc, |
5eddb70b CW |
5196 | dev_priv->lvds_downclock, |
5197 | refclk, | |
cec2f356 | 5198 | &clock, |
5eddb70b | 5199 | &reduced_clock); |
7026d4ac ZW |
5200 | } |
5201 | ||
c65d77d8 JB |
5202 | if (is_sdvo && is_tv) |
5203 | i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); | |
7026d4ac | 5204 | |
a7516a05 JB |
5205 | i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ? |
5206 | &reduced_clock : NULL); | |
79e53945 | 5207 | |
929c77fb | 5208 | dpll = DPLL_VGA_MODE_DIS; |
2c07245f | 5209 | |
a6c45cf0 | 5210 | if (!IS_GEN2(dev)) { |
79e53945 JB |
5211 | if (is_lvds) |
5212 | dpll |= DPLLB_MODE_LVDS; | |
5213 | else | |
5214 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
5215 | if (is_sdvo) { | |
6c9547ff CW |
5216 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
5217 | if (pixel_multiplier > 1) { | |
5218 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
5219 | dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; | |
6c9547ff | 5220 | } |
79e53945 | 5221 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 | 5222 | } |
929c77fb | 5223 | if (is_dp) |
a4fc5ed6 | 5224 | dpll |= DPLL_DVO_HIGH_SPEED; |
79e53945 JB |
5225 | |
5226 | /* compute bitmask from p1 value */ | |
f2b115e6 AJ |
5227 | if (IS_PINEVIEW(dev)) |
5228 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
2c07245f | 5229 | else { |
2177832f | 5230 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
652c393a JB |
5231 | if (IS_G4X(dev) && has_reduced_clock) |
5232 | dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
2c07245f | 5233 | } |
79e53945 JB |
5234 | switch (clock.p2) { |
5235 | case 5: | |
5236 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5237 | break; | |
5238 | case 7: | |
5239 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5240 | break; | |
5241 | case 10: | |
5242 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5243 | break; | |
5244 | case 14: | |
5245 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5246 | break; | |
5247 | } | |
929c77fb | 5248 | if (INTEL_INFO(dev)->gen >= 4) |
79e53945 JB |
5249 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
5250 | } else { | |
5251 | if (is_lvds) { | |
5252 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5253 | } else { | |
5254 | if (clock.p1 == 2) | |
5255 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5256 | else | |
5257 | dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5258 | if (clock.p2 == 4) | |
5259 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5260 | } | |
5261 | } | |
5262 | ||
43565a06 KH |
5263 | if (is_sdvo && is_tv) |
5264 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
5265 | else if (is_tv) | |
79e53945 | 5266 | /* XXX: just matching BIOS for now */ |
43565a06 | 5267 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 5268 | dpll |= 3; |
a7615030 | 5269 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 5270 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
5271 | else |
5272 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5273 | ||
5274 | /* setup pipeconf */ | |
5eddb70b | 5275 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
5276 | |
5277 | /* Set up the display plane register */ | |
5278 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
5279 | ||
929c77fb EA |
5280 | if (pipe == 0) |
5281 | dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; | |
5282 | else | |
5283 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
79e53945 | 5284 | |
a6c45cf0 | 5285 | if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { |
79e53945 JB |
5286 | /* Enable pixel doubling when the dot clock is > 90% of the (display) |
5287 | * core speed. | |
5288 | * | |
5289 | * XXX: No double-wide on 915GM pipe B. Is that the only reason for the | |
5290 | * pipe == 0 check? | |
5291 | */ | |
e70236a8 JB |
5292 | if (mode->clock > |
5293 | dev_priv->display.get_display_clock_speed(dev) * 9 / 10) | |
5eddb70b | 5294 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
79e53945 | 5295 | else |
5eddb70b | 5296 | pipeconf &= ~PIPECONF_DOUBLE_WIDE; |
79e53945 JB |
5297 | } |
5298 | ||
3b5c78a3 AJ |
5299 | /* default to 8bpc */ |
5300 | pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN); | |
5301 | if (is_dp) { | |
5302 | if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { | |
5303 | pipeconf |= PIPECONF_BPP_6 | | |
5304 | PIPECONF_DITHER_EN | | |
5305 | PIPECONF_DITHER_TYPE_SP; | |
5306 | } | |
5307 | } | |
5308 | ||
929c77fb | 5309 | dpll |= DPLL_VCO_ENABLE; |
8d86dc6a | 5310 | |
28c97730 | 5311 | DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); |
79e53945 JB |
5312 | drm_mode_debug_printmodeline(mode); |
5313 | ||
fae14981 | 5314 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); |
5eddb70b | 5315 | |
fae14981 | 5316 | POSTING_READ(DPLL(pipe)); |
c713bb08 | 5317 | udelay(150); |
8db9d77b | 5318 | |
79e53945 JB |
5319 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
5320 | * This is an exception to the general rule that mode_set doesn't turn | |
5321 | * things on. | |
5322 | */ | |
5323 | if (is_lvds) { | |
fae14981 | 5324 | temp = I915_READ(LVDS); |
5eddb70b | 5325 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
b3b095b3 | 5326 | if (pipe == 1) { |
929c77fb | 5327 | temp |= LVDS_PIPEB_SELECT; |
b3b095b3 | 5328 | } else { |
929c77fb | 5329 | temp &= ~LVDS_PIPEB_SELECT; |
b3b095b3 | 5330 | } |
a3e17eb8 | 5331 | /* set the corresponsding LVDS_BORDER bit */ |
5eddb70b | 5332 | temp |= dev_priv->lvds_border_bits; |
79e53945 JB |
5333 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
5334 | * set the DPLLs for dual-channel mode or not. | |
5335 | */ | |
5336 | if (clock.p2 == 7) | |
5eddb70b | 5337 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
79e53945 | 5338 | else |
5eddb70b | 5339 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
79e53945 JB |
5340 | |
5341 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
5342 | * appropriately here, but we need to look more thoroughly into how | |
5343 | * panels behave in the two modes. | |
5344 | */ | |
929c77fb EA |
5345 | /* set the dithering flag on LVDS as needed */ |
5346 | if (INTEL_INFO(dev)->gen >= 4) { | |
434ed097 | 5347 | if (dev_priv->lvds_dither) |
5eddb70b | 5348 | temp |= LVDS_ENABLE_DITHER; |
434ed097 | 5349 | else |
5eddb70b | 5350 | temp &= ~LVDS_ENABLE_DITHER; |
898822ce | 5351 | } |
aa9b500d BF |
5352 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
5353 | lvds_sync |= LVDS_HSYNC_POLARITY; | |
5354 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) | |
5355 | lvds_sync |= LVDS_VSYNC_POLARITY; | |
5356 | if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) | |
5357 | != lvds_sync) { | |
5358 | char flags[2] = "-+"; | |
5359 | DRM_INFO("Changing LVDS panel from " | |
5360 | "(%chsync, %cvsync) to (%chsync, %cvsync)\n", | |
5361 | flags[!(temp & LVDS_HSYNC_POLARITY)], | |
5362 | flags[!(temp & LVDS_VSYNC_POLARITY)], | |
5363 | flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], | |
5364 | flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); | |
5365 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
5366 | temp |= lvds_sync; | |
5367 | } | |
fae14981 | 5368 | I915_WRITE(LVDS, temp); |
79e53945 | 5369 | } |
434ed097 | 5370 | |
929c77fb | 5371 | if (is_dp) { |
a4fc5ed6 | 5372 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
434ed097 JB |
5373 | } |
5374 | ||
fae14981 | 5375 | I915_WRITE(DPLL(pipe), dpll); |
5eddb70b | 5376 | |
c713bb08 | 5377 | /* Wait for the clocks to stabilize. */ |
fae14981 | 5378 | POSTING_READ(DPLL(pipe)); |
c713bb08 | 5379 | udelay(150); |
32f9d658 | 5380 | |
c713bb08 EA |
5381 | if (INTEL_INFO(dev)->gen >= 4) { |
5382 | temp = 0; | |
5383 | if (is_sdvo) { | |
5384 | temp = intel_mode_get_pixel_multiplier(adjusted_mode); | |
5385 | if (temp > 1) | |
5386 | temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
5387 | else | |
5388 | temp = 0; | |
32f9d658 | 5389 | } |
c713bb08 EA |
5390 | I915_WRITE(DPLL_MD(pipe), temp); |
5391 | } else { | |
5392 | /* The pixel multiplier can only be updated once the | |
5393 | * DPLL is enabled and the clocks are stable. | |
5394 | * | |
5395 | * So write it again. | |
5396 | */ | |
fae14981 | 5397 | I915_WRITE(DPLL(pipe), dpll); |
79e53945 | 5398 | } |
79e53945 | 5399 | |
a7516a05 JB |
5400 | if (HAS_PIPE_CXSR(dev)) { |
5401 | if (intel_crtc->lowfreq_avail) { | |
28c97730 | 5402 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); |
652c393a | 5403 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; |
a7516a05 | 5404 | } else { |
28c97730 | 5405 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); |
652c393a JB |
5406 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; |
5407 | } | |
5408 | } | |
5409 | ||
617cf884 | 5410 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
dbb02575 DV |
5411 | if (!IS_GEN2(dev) && |
5412 | adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
734b4157 KH |
5413 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
5414 | /* the chip adds 2 halflines automatically */ | |
734b4157 | 5415 | adjusted_mode->crtc_vtotal -= 1; |
734b4157 | 5416 | adjusted_mode->crtc_vblank_end -= 1; |
0529a0d9 DV |
5417 | vsyncshift = adjusted_mode->crtc_hsync_start |
5418 | - adjusted_mode->crtc_htotal/2; | |
5419 | } else { | |
617cf884 | 5420 | pipeconf |= PIPECONF_PROGRESSIVE; |
0529a0d9 DV |
5421 | vsyncshift = 0; |
5422 | } | |
5423 | ||
5424 | if (!IS_GEN3(dev)) | |
5425 | I915_WRITE(VSYNCSHIFT(pipe), vsyncshift); | |
734b4157 | 5426 | |
5eddb70b CW |
5427 | I915_WRITE(HTOTAL(pipe), |
5428 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 5429 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
5430 | I915_WRITE(HBLANK(pipe), |
5431 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 5432 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
5433 | I915_WRITE(HSYNC(pipe), |
5434 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 5435 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
5436 | |
5437 | I915_WRITE(VTOTAL(pipe), | |
5438 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 5439 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
5440 | I915_WRITE(VBLANK(pipe), |
5441 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 5442 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
5443 | I915_WRITE(VSYNC(pipe), |
5444 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 5445 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b CW |
5446 | |
5447 | /* pipesrc and dspsize control the size that is scaled from, | |
5448 | * which should always be the user's requested size. | |
79e53945 | 5449 | */ |
929c77fb EA |
5450 | I915_WRITE(DSPSIZE(plane), |
5451 | ((mode->vdisplay - 1) << 16) | | |
5452 | (mode->hdisplay - 1)); | |
5453 | I915_WRITE(DSPPOS(plane), 0); | |
5eddb70b CW |
5454 | I915_WRITE(PIPESRC(pipe), |
5455 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 5456 | |
f564048e EA |
5457 | I915_WRITE(PIPECONF(pipe), pipeconf); |
5458 | POSTING_READ(PIPECONF(pipe)); | |
929c77fb | 5459 | intel_enable_pipe(dev_priv, pipe, false); |
f564048e EA |
5460 | |
5461 | intel_wait_for_vblank(dev, pipe); | |
5462 | ||
f564048e EA |
5463 | I915_WRITE(DSPCNTR(plane), dspcntr); |
5464 | POSTING_READ(DSPCNTR(plane)); | |
284d9529 | 5465 | intel_enable_plane(dev_priv, plane, pipe); |
f564048e EA |
5466 | |
5467 | ret = intel_pipe_set_base(crtc, x, y, old_fb); | |
5468 | ||
5469 | intel_update_watermarks(dev); | |
5470 | ||
f564048e EA |
5471 | return ret; |
5472 | } | |
5473 | ||
9fb526db KP |
5474 | /* |
5475 | * Initialize reference clocks when the driver loads | |
5476 | */ | |
5477 | void ironlake_init_pch_refclk(struct drm_device *dev) | |
13d83a67 JB |
5478 | { |
5479 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5480 | struct drm_mode_config *mode_config = &dev->mode_config; | |
13d83a67 | 5481 | struct intel_encoder *encoder; |
13d83a67 JB |
5482 | u32 temp; |
5483 | bool has_lvds = false; | |
199e5d79 KP |
5484 | bool has_cpu_edp = false; |
5485 | bool has_pch_edp = false; | |
5486 | bool has_panel = false; | |
99eb6a01 KP |
5487 | bool has_ck505 = false; |
5488 | bool can_ssc = false; | |
13d83a67 JB |
5489 | |
5490 | /* We need to take the global config into account */ | |
199e5d79 KP |
5491 | list_for_each_entry(encoder, &mode_config->encoder_list, |
5492 | base.head) { | |
5493 | switch (encoder->type) { | |
5494 | case INTEL_OUTPUT_LVDS: | |
5495 | has_panel = true; | |
5496 | has_lvds = true; | |
5497 | break; | |
5498 | case INTEL_OUTPUT_EDP: | |
5499 | has_panel = true; | |
5500 | if (intel_encoder_is_pch_edp(&encoder->base)) | |
5501 | has_pch_edp = true; | |
5502 | else | |
5503 | has_cpu_edp = true; | |
5504 | break; | |
13d83a67 JB |
5505 | } |
5506 | } | |
5507 | ||
99eb6a01 KP |
5508 | if (HAS_PCH_IBX(dev)) { |
5509 | has_ck505 = dev_priv->display_clock_mode; | |
5510 | can_ssc = has_ck505; | |
5511 | } else { | |
5512 | has_ck505 = false; | |
5513 | can_ssc = true; | |
5514 | } | |
5515 | ||
5516 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", | |
5517 | has_panel, has_lvds, has_pch_edp, has_cpu_edp, | |
5518 | has_ck505); | |
13d83a67 JB |
5519 | |
5520 | /* Ironlake: try to setup display ref clock before DPLL | |
5521 | * enabling. This is only under driver's control after | |
5522 | * PCH B stepping, previous chipset stepping should be | |
5523 | * ignoring this setting. | |
5524 | */ | |
5525 | temp = I915_READ(PCH_DREF_CONTROL); | |
5526 | /* Always enable nonspread source */ | |
5527 | temp &= ~DREF_NONSPREAD_SOURCE_MASK; | |
13d83a67 | 5528 | |
99eb6a01 KP |
5529 | if (has_ck505) |
5530 | temp |= DREF_NONSPREAD_CK505_ENABLE; | |
5531 | else | |
5532 | temp |= DREF_NONSPREAD_SOURCE_ENABLE; | |
13d83a67 | 5533 | |
199e5d79 KP |
5534 | if (has_panel) { |
5535 | temp &= ~DREF_SSC_SOURCE_MASK; | |
5536 | temp |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 5537 | |
199e5d79 | 5538 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 5539 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5540 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
13d83a67 | 5541 | temp |= DREF_SSC1_ENABLE; |
13d83a67 | 5542 | } |
199e5d79 KP |
5543 | |
5544 | /* Get SSC going before enabling the outputs */ | |
5545 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5546 | POSTING_READ(PCH_DREF_CONTROL); | |
5547 | udelay(200); | |
5548 | ||
13d83a67 JB |
5549 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
5550 | ||
5551 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 5552 | if (has_cpu_edp) { |
99eb6a01 | 5553 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 5554 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
13d83a67 | 5555 | temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
199e5d79 | 5556 | } |
13d83a67 JB |
5557 | else |
5558 | temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
199e5d79 KP |
5559 | } else |
5560 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5561 | ||
5562 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5563 | POSTING_READ(PCH_DREF_CONTROL); | |
5564 | udelay(200); | |
5565 | } else { | |
5566 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
5567 | ||
5568 | temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
5569 | ||
5570 | /* Turn off CPU output */ | |
5571 | temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
5572 | ||
5573 | I915_WRITE(PCH_DREF_CONTROL, temp); | |
5574 | POSTING_READ(PCH_DREF_CONTROL); | |
5575 | udelay(200); | |
5576 | ||
5577 | /* Turn off the SSC source */ | |
5578 | temp &= ~DREF_SSC_SOURCE_MASK; | |
5579 | temp |= DREF_SSC_SOURCE_DISABLE; | |
5580 | ||
5581 | /* Turn off SSC1 */ | |
5582 | temp &= ~ DREF_SSC1_ENABLE; | |
5583 | ||
13d83a67 JB |
5584 | I915_WRITE(PCH_DREF_CONTROL, temp); |
5585 | POSTING_READ(PCH_DREF_CONTROL); | |
5586 | udelay(200); | |
5587 | } | |
5588 | } | |
5589 | ||
d9d444cb JB |
5590 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
5591 | { | |
5592 | struct drm_device *dev = crtc->dev; | |
5593 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5594 | struct intel_encoder *encoder; | |
5595 | struct drm_mode_config *mode_config = &dev->mode_config; | |
5596 | struct intel_encoder *edp_encoder = NULL; | |
5597 | int num_connectors = 0; | |
5598 | bool is_lvds = false; | |
5599 | ||
5600 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { | |
5601 | if (encoder->base.crtc != crtc) | |
5602 | continue; | |
5603 | ||
5604 | switch (encoder->type) { | |
5605 | case INTEL_OUTPUT_LVDS: | |
5606 | is_lvds = true; | |
5607 | break; | |
5608 | case INTEL_OUTPUT_EDP: | |
5609 | edp_encoder = encoder; | |
5610 | break; | |
5611 | } | |
5612 | num_connectors++; | |
5613 | } | |
5614 | ||
5615 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
5616 | DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", | |
5617 | dev_priv->lvds_ssc_freq); | |
5618 | return dev_priv->lvds_ssc_freq * 1000; | |
5619 | } | |
5620 | ||
5621 | return 120000; | |
5622 | } | |
5623 | ||
f564048e EA |
5624 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, |
5625 | struct drm_display_mode *mode, | |
5626 | struct drm_display_mode *adjusted_mode, | |
5627 | int x, int y, | |
5628 | struct drm_framebuffer *old_fb) | |
79e53945 JB |
5629 | { |
5630 | struct drm_device *dev = crtc->dev; | |
5631 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5632 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5633 | int pipe = intel_crtc->pipe; | |
80824003 | 5634 | int plane = intel_crtc->plane; |
c751ce4f | 5635 | int refclk, num_connectors = 0; |
652c393a | 5636 | intel_clock_t clock, reduced_clock; |
5eddb70b | 5637 | u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf; |
a07d6787 | 5638 | bool ok, has_reduced_clock = false, is_sdvo = false; |
a4fc5ed6 | 5639 | bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; |
8e647a27 | 5640 | struct intel_encoder *has_edp_encoder = NULL; |
79e53945 | 5641 | struct drm_mode_config *mode_config = &dev->mode_config; |
5eddb70b | 5642 | struct intel_encoder *encoder; |
d4906093 | 5643 | const intel_limit_t *limit; |
5c3b82e2 | 5644 | int ret; |
2c07245f | 5645 | struct fdi_m_n m_n = {0}; |
fae14981 | 5646 | u32 temp; |
aa9b500d | 5647 | u32 lvds_sync = 0; |
5a354204 JB |
5648 | int target_clock, pixel_multiplier, lane, link_bw, factor; |
5649 | unsigned int pipe_bpp; | |
5650 | bool dither; | |
79e53945 | 5651 | |
5eddb70b CW |
5652 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { |
5653 | if (encoder->base.crtc != crtc) | |
79e53945 JB |
5654 | continue; |
5655 | ||
5eddb70b | 5656 | switch (encoder->type) { |
79e53945 JB |
5657 | case INTEL_OUTPUT_LVDS: |
5658 | is_lvds = true; | |
5659 | break; | |
5660 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 5661 | case INTEL_OUTPUT_HDMI: |
79e53945 | 5662 | is_sdvo = true; |
5eddb70b | 5663 | if (encoder->needs_tv_clock) |
e2f0ba97 | 5664 | is_tv = true; |
79e53945 | 5665 | break; |
79e53945 JB |
5666 | case INTEL_OUTPUT_TVOUT: |
5667 | is_tv = true; | |
5668 | break; | |
5669 | case INTEL_OUTPUT_ANALOG: | |
5670 | is_crt = true; | |
5671 | break; | |
a4fc5ed6 KP |
5672 | case INTEL_OUTPUT_DISPLAYPORT: |
5673 | is_dp = true; | |
5674 | break; | |
32f9d658 | 5675 | case INTEL_OUTPUT_EDP: |
5eddb70b | 5676 | has_edp_encoder = encoder; |
32f9d658 | 5677 | break; |
79e53945 | 5678 | } |
43565a06 | 5679 | |
c751ce4f | 5680 | num_connectors++; |
79e53945 JB |
5681 | } |
5682 | ||
d9d444cb | 5683 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 5684 | |
d4906093 ML |
5685 | /* |
5686 | * Returns a set of divisors for the desired target clock with the given | |
5687 | * refclk, or FALSE. The returned values represent the clock equation: | |
5688 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
5689 | */ | |
1b894b59 | 5690 | limit = intel_limit(crtc, refclk); |
cec2f356 SP |
5691 | ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, |
5692 | &clock); | |
79e53945 JB |
5693 | if (!ok) { |
5694 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
5c3b82e2 | 5695 | return -EINVAL; |
79e53945 JB |
5696 | } |
5697 | ||
cda4b7d3 | 5698 | /* Ensure that the cursor is valid for the new mode before changing... */ |
6b383a7f | 5699 | intel_crtc_update_cursor(crtc, true); |
cda4b7d3 | 5700 | |
ddc9003c | 5701 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
5702 | /* |
5703 | * Ensure we match the reduced clock's P to the target clock. | |
5704 | * If the clocks don't match, we can't switch the display clock | |
5705 | * by using the FP0/FP1. In such case we will disable the LVDS | |
5706 | * downclock feature. | |
5707 | */ | |
ddc9003c | 5708 | has_reduced_clock = limit->find_pll(limit, crtc, |
5eddb70b CW |
5709 | dev_priv->lvds_downclock, |
5710 | refclk, | |
cec2f356 | 5711 | &clock, |
5eddb70b | 5712 | &reduced_clock); |
652c393a | 5713 | } |
7026d4ac ZW |
5714 | /* SDVO TV has fixed PLL values depend on its clock range, |
5715 | this mirrors vbios setting. */ | |
5716 | if (is_sdvo && is_tv) { | |
5717 | if (adjusted_mode->clock >= 100000 | |
5eddb70b | 5718 | && adjusted_mode->clock < 140500) { |
7026d4ac ZW |
5719 | clock.p1 = 2; |
5720 | clock.p2 = 10; | |
5721 | clock.n = 3; | |
5722 | clock.m1 = 16; | |
5723 | clock.m2 = 8; | |
5724 | } else if (adjusted_mode->clock >= 140500 | |
5eddb70b | 5725 | && adjusted_mode->clock <= 200000) { |
7026d4ac ZW |
5726 | clock.p1 = 1; |
5727 | clock.p2 = 10; | |
5728 | clock.n = 6; | |
5729 | clock.m1 = 12; | |
5730 | clock.m2 = 8; | |
5731 | } | |
5732 | } | |
5733 | ||
2c07245f | 5734 | /* FDI link */ |
8febb297 EA |
5735 | pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
5736 | lane = 0; | |
5737 | /* CPU eDP doesn't require FDI link, so just set DP M/N | |
5738 | according to current link config */ | |
5739 | if (has_edp_encoder && | |
5740 | !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
5741 | target_clock = mode->clock; | |
5742 | intel_edp_link_config(has_edp_encoder, | |
5743 | &lane, &link_bw); | |
5744 | } else { | |
5745 | /* [e]DP over FDI requires target mode clock | |
5746 | instead of link clock */ | |
5747 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) | |
5eb08b69 | 5748 | target_clock = mode->clock; |
8febb297 EA |
5749 | else |
5750 | target_clock = adjusted_mode->clock; | |
5751 | ||
5752 | /* FDI is a binary signal running at ~2.7GHz, encoding | |
5753 | * each output octet as 10 bits. The actual frequency | |
5754 | * is stored as a divider into a 100MHz clock, and the | |
5755 | * mode pixel clock is stored in units of 1KHz. | |
5756 | * Hence the bw of each lane in terms of the mode signal | |
5757 | * is: | |
5758 | */ | |
5759 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5760 | } | |
58a27471 | 5761 | |
8febb297 EA |
5762 | /* determine panel color depth */ |
5763 | temp = I915_READ(PIPECONF(pipe)); | |
5764 | temp &= ~PIPE_BPC_MASK; | |
3b5c78a3 | 5765 | dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode); |
5a354204 JB |
5766 | switch (pipe_bpp) { |
5767 | case 18: | |
5768 | temp |= PIPE_6BPC; | |
8febb297 | 5769 | break; |
5a354204 JB |
5770 | case 24: |
5771 | temp |= PIPE_8BPC; | |
8febb297 | 5772 | break; |
5a354204 JB |
5773 | case 30: |
5774 | temp |= PIPE_10BPC; | |
8febb297 | 5775 | break; |
5a354204 JB |
5776 | case 36: |
5777 | temp |= PIPE_12BPC; | |
8febb297 EA |
5778 | break; |
5779 | default: | |
62ac41a6 JB |
5780 | WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n", |
5781 | pipe_bpp); | |
5a354204 JB |
5782 | temp |= PIPE_8BPC; |
5783 | pipe_bpp = 24; | |
5784 | break; | |
8febb297 | 5785 | } |
77ffb597 | 5786 | |
5a354204 JB |
5787 | intel_crtc->bpp = pipe_bpp; |
5788 | I915_WRITE(PIPECONF(pipe), temp); | |
5789 | ||
8febb297 EA |
5790 | if (!lane) { |
5791 | /* | |
5792 | * Account for spread spectrum to avoid | |
5793 | * oversubscribing the link. Max center spread | |
5794 | * is 2.5%; use 5% for safety's sake. | |
5795 | */ | |
5a354204 | 5796 | u32 bps = target_clock * intel_crtc->bpp * 21 / 20; |
8febb297 | 5797 | lane = bps / (link_bw * 8) + 1; |
5eb08b69 | 5798 | } |
2c07245f | 5799 | |
8febb297 EA |
5800 | intel_crtc->fdi_lanes = lane; |
5801 | ||
5802 | if (pixel_multiplier > 1) | |
5803 | link_bw *= pixel_multiplier; | |
5a354204 JB |
5804 | ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, |
5805 | &m_n); | |
8febb297 | 5806 | |
a07d6787 EA |
5807 | fp = clock.n << 16 | clock.m1 << 8 | clock.m2; |
5808 | if (has_reduced_clock) | |
5809 | fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | | |
5810 | reduced_clock.m2; | |
79e53945 | 5811 | |
c1858123 | 5812 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
5813 | factor = 21; |
5814 | if (is_lvds) { | |
5815 | if ((intel_panel_use_ssc(dev_priv) && | |
5816 | dev_priv->lvds_ssc_freq == 100) || | |
5817 | (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP) | |
5818 | factor = 25; | |
5819 | } else if (is_sdvo && is_tv) | |
5820 | factor = 20; | |
c1858123 | 5821 | |
cb0e0931 | 5822 | if (clock.m < factor * clock.n) |
8febb297 | 5823 | fp |= FP_CB_TUNE; |
2c07245f | 5824 | |
5eddb70b | 5825 | dpll = 0; |
2c07245f | 5826 | |
a07d6787 EA |
5827 | if (is_lvds) |
5828 | dpll |= DPLLB_MODE_LVDS; | |
5829 | else | |
5830 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
5831 | if (is_sdvo) { | |
5832 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); | |
5833 | if (pixel_multiplier > 1) { | |
5834 | dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
79e53945 | 5835 | } |
a07d6787 EA |
5836 | dpll |= DPLL_DVO_HIGH_SPEED; |
5837 | } | |
5838 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) | |
5839 | dpll |= DPLL_DVO_HIGH_SPEED; | |
79e53945 | 5840 | |
a07d6787 EA |
5841 | /* compute bitmask from p1 value */ |
5842 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5843 | /* also FPA1 */ | |
5844 | dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5845 | ||
5846 | switch (clock.p2) { | |
5847 | case 5: | |
5848 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5849 | break; | |
5850 | case 7: | |
5851 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5852 | break; | |
5853 | case 10: | |
5854 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5855 | break; | |
5856 | case 14: | |
5857 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5858 | break; | |
79e53945 JB |
5859 | } |
5860 | ||
43565a06 KH |
5861 | if (is_sdvo && is_tv) |
5862 | dpll |= PLL_REF_INPUT_TVCLKINBC; | |
5863 | else if (is_tv) | |
79e53945 | 5864 | /* XXX: just matching BIOS for now */ |
43565a06 | 5865 | /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ |
79e53945 | 5866 | dpll |= 3; |
a7615030 | 5867 | else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 5868 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
5869 | else |
5870 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5871 | ||
5872 | /* setup pipeconf */ | |
5eddb70b | 5873 | pipeconf = I915_READ(PIPECONF(pipe)); |
79e53945 JB |
5874 | |
5875 | /* Set up the display plane register */ | |
5876 | dspcntr = DISPPLANE_GAMMA_ENABLE; | |
5877 | ||
f7cb34d4 | 5878 | DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); |
79e53945 JB |
5879 | drm_mode_debug_printmodeline(mode); |
5880 | ||
5c5313c8 | 5881 | /* PCH eDP needs FDI, but CPU eDP does not */ |
4b645f14 JB |
5882 | if (!intel_crtc->no_pll) { |
5883 | if (!has_edp_encoder || | |
5884 | intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
5885 | I915_WRITE(PCH_FP0(pipe), fp); | |
5886 | I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); | |
5887 | ||
5888 | POSTING_READ(PCH_DPLL(pipe)); | |
5889 | udelay(150); | |
5890 | } | |
5891 | } else { | |
5892 | if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) && | |
5893 | fp == I915_READ(PCH_FP0(0))) { | |
5894 | intel_crtc->use_pll_a = true; | |
5895 | DRM_DEBUG_KMS("using pipe a dpll\n"); | |
5896 | } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) && | |
5897 | fp == I915_READ(PCH_FP0(1))) { | |
5898 | intel_crtc->use_pll_a = false; | |
5899 | DRM_DEBUG_KMS("using pipe b dpll\n"); | |
5900 | } else { | |
5901 | DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n"); | |
5902 | return -EINVAL; | |
5903 | } | |
79e53945 JB |
5904 | } |
5905 | ||
5906 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. | |
5907 | * This is an exception to the general rule that mode_set doesn't turn | |
5908 | * things on. | |
5909 | */ | |
5910 | if (is_lvds) { | |
fae14981 | 5911 | temp = I915_READ(PCH_LVDS); |
5eddb70b | 5912 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
7885d205 JB |
5913 | if (HAS_PCH_CPT(dev)) { |
5914 | temp &= ~PORT_TRANS_SEL_MASK; | |
4b645f14 | 5915 | temp |= PORT_TRANS_SEL_CPT(pipe); |
7885d205 JB |
5916 | } else { |
5917 | if (pipe == 1) | |
5918 | temp |= LVDS_PIPEB_SELECT; | |
5919 | else | |
5920 | temp &= ~LVDS_PIPEB_SELECT; | |
5921 | } | |
4b645f14 | 5922 | |
a3e17eb8 | 5923 | /* set the corresponsding LVDS_BORDER bit */ |
5eddb70b | 5924 | temp |= dev_priv->lvds_border_bits; |
79e53945 JB |
5925 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
5926 | * set the DPLLs for dual-channel mode or not. | |
5927 | */ | |
5928 | if (clock.p2 == 7) | |
5eddb70b | 5929 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; |
79e53945 | 5930 | else |
5eddb70b | 5931 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); |
79e53945 JB |
5932 | |
5933 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
5934 | * appropriately here, but we need to look more thoroughly into how | |
5935 | * panels behave in the two modes. | |
5936 | */ | |
aa9b500d BF |
5937 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
5938 | lvds_sync |= LVDS_HSYNC_POLARITY; | |
5939 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) | |
5940 | lvds_sync |= LVDS_VSYNC_POLARITY; | |
5941 | if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY)) | |
5942 | != lvds_sync) { | |
5943 | char flags[2] = "-+"; | |
5944 | DRM_INFO("Changing LVDS panel from " | |
5945 | "(%chsync, %cvsync) to (%chsync, %cvsync)\n", | |
5946 | flags[!(temp & LVDS_HSYNC_POLARITY)], | |
5947 | flags[!(temp & LVDS_VSYNC_POLARITY)], | |
5948 | flags[!(lvds_sync & LVDS_HSYNC_POLARITY)], | |
5949 | flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]); | |
5950 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
5951 | temp |= lvds_sync; | |
5952 | } | |
fae14981 | 5953 | I915_WRITE(PCH_LVDS, temp); |
79e53945 | 5954 | } |
434ed097 | 5955 | |
8febb297 EA |
5956 | pipeconf &= ~PIPECONF_DITHER_EN; |
5957 | pipeconf &= ~PIPECONF_DITHER_TYPE_MASK; | |
5a354204 | 5958 | if ((is_lvds && dev_priv->lvds_dither) || dither) { |
8febb297 | 5959 | pipeconf |= PIPECONF_DITHER_EN; |
f74974c7 | 5960 | pipeconf |= PIPECONF_DITHER_TYPE_SP; |
434ed097 | 5961 | } |
5c5313c8 | 5962 | if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) { |
a4fc5ed6 | 5963 | intel_dp_set_m_n(crtc, mode, adjusted_mode); |
8febb297 | 5964 | } else { |
8db9d77b | 5965 | /* For non-DP output, clear any trans DP clock recovery setting.*/ |
9db4a9c7 JB |
5966 | I915_WRITE(TRANSDATA_M1(pipe), 0); |
5967 | I915_WRITE(TRANSDATA_N1(pipe), 0); | |
5968 | I915_WRITE(TRANSDPLINK_M1(pipe), 0); | |
5969 | I915_WRITE(TRANSDPLINK_N1(pipe), 0); | |
8db9d77b | 5970 | } |
79e53945 | 5971 | |
4b645f14 JB |
5972 | if (!intel_crtc->no_pll && |
5973 | (!has_edp_encoder || | |
5974 | intel_encoder_is_pch_edp(&has_edp_encoder->base))) { | |
fae14981 | 5975 | I915_WRITE(PCH_DPLL(pipe), dpll); |
5eddb70b | 5976 | |
32f9d658 | 5977 | /* Wait for the clocks to stabilize. */ |
fae14981 | 5978 | POSTING_READ(PCH_DPLL(pipe)); |
32f9d658 ZW |
5979 | udelay(150); |
5980 | ||
8febb297 EA |
5981 | /* The pixel multiplier can only be updated once the |
5982 | * DPLL is enabled and the clocks are stable. | |
5983 | * | |
5984 | * So write it again. | |
5985 | */ | |
fae14981 | 5986 | I915_WRITE(PCH_DPLL(pipe), dpll); |
79e53945 | 5987 | } |
79e53945 | 5988 | |
5eddb70b | 5989 | intel_crtc->lowfreq_avail = false; |
4b645f14 JB |
5990 | if (!intel_crtc->no_pll) { |
5991 | if (is_lvds && has_reduced_clock && i915_powersave) { | |
5992 | I915_WRITE(PCH_FP1(pipe), fp2); | |
5993 | intel_crtc->lowfreq_avail = true; | |
5994 | if (HAS_PIPE_CXSR(dev)) { | |
5995 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
5996 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
5997 | } | |
5998 | } else { | |
5999 | I915_WRITE(PCH_FP1(pipe), fp); | |
6000 | if (HAS_PIPE_CXSR(dev)) { | |
6001 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
6002 | pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; | |
6003 | } | |
652c393a JB |
6004 | } |
6005 | } | |
6006 | ||
617cf884 | 6007 | pipeconf &= ~PIPECONF_INTERLACE_MASK; |
734b4157 | 6008 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
5def474e | 6009 | pipeconf |= PIPECONF_INTERLACED_ILK; |
734b4157 | 6010 | /* the chip adds 2 halflines automatically */ |
734b4157 | 6011 | adjusted_mode->crtc_vtotal -= 1; |
734b4157 | 6012 | adjusted_mode->crtc_vblank_end -= 1; |
0529a0d9 DV |
6013 | I915_WRITE(VSYNCSHIFT(pipe), |
6014 | adjusted_mode->crtc_hsync_start | |
6015 | - adjusted_mode->crtc_htotal/2); | |
6016 | } else { | |
617cf884 | 6017 | pipeconf |= PIPECONF_PROGRESSIVE; |
0529a0d9 DV |
6018 | I915_WRITE(VSYNCSHIFT(pipe), 0); |
6019 | } | |
734b4157 | 6020 | |
5eddb70b CW |
6021 | I915_WRITE(HTOTAL(pipe), |
6022 | (adjusted_mode->crtc_hdisplay - 1) | | |
79e53945 | 6023 | ((adjusted_mode->crtc_htotal - 1) << 16)); |
5eddb70b CW |
6024 | I915_WRITE(HBLANK(pipe), |
6025 | (adjusted_mode->crtc_hblank_start - 1) | | |
79e53945 | 6026 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); |
5eddb70b CW |
6027 | I915_WRITE(HSYNC(pipe), |
6028 | (adjusted_mode->crtc_hsync_start - 1) | | |
79e53945 | 6029 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); |
5eddb70b CW |
6030 | |
6031 | I915_WRITE(VTOTAL(pipe), | |
6032 | (adjusted_mode->crtc_vdisplay - 1) | | |
79e53945 | 6033 | ((adjusted_mode->crtc_vtotal - 1) << 16)); |
5eddb70b CW |
6034 | I915_WRITE(VBLANK(pipe), |
6035 | (adjusted_mode->crtc_vblank_start - 1) | | |
79e53945 | 6036 | ((adjusted_mode->crtc_vblank_end - 1) << 16)); |
5eddb70b CW |
6037 | I915_WRITE(VSYNC(pipe), |
6038 | (adjusted_mode->crtc_vsync_start - 1) | | |
79e53945 | 6039 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |
5eddb70b | 6040 | |
8febb297 EA |
6041 | /* pipesrc controls the size that is scaled from, which should |
6042 | * always be the user's requested size. | |
79e53945 | 6043 | */ |
5eddb70b CW |
6044 | I915_WRITE(PIPESRC(pipe), |
6045 | ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); | |
2c07245f | 6046 | |
8febb297 EA |
6047 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
6048 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); | |
6049 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); | |
6050 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); | |
2c07245f | 6051 | |
8febb297 EA |
6052 | if (has_edp_encoder && |
6053 | !intel_encoder_is_pch_edp(&has_edp_encoder->base)) { | |
6054 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); | |
2c07245f ZW |
6055 | } |
6056 | ||
5eddb70b CW |
6057 | I915_WRITE(PIPECONF(pipe), pipeconf); |
6058 | POSTING_READ(PIPECONF(pipe)); | |
79e53945 | 6059 | |
9d0498a2 | 6060 | intel_wait_for_vblank(dev, pipe); |
79e53945 | 6061 | |
5eddb70b | 6062 | I915_WRITE(DSPCNTR(plane), dspcntr); |
b24e7179 | 6063 | POSTING_READ(DSPCNTR(plane)); |
79e53945 | 6064 | |
5c3b82e2 | 6065 | ret = intel_pipe_set_base(crtc, x, y, old_fb); |
7662c8bd SL |
6066 | |
6067 | intel_update_watermarks(dev); | |
6068 | ||
1f803ee5 | 6069 | return ret; |
79e53945 JB |
6070 | } |
6071 | ||
f564048e EA |
6072 | static int intel_crtc_mode_set(struct drm_crtc *crtc, |
6073 | struct drm_display_mode *mode, | |
6074 | struct drm_display_mode *adjusted_mode, | |
6075 | int x, int y, | |
6076 | struct drm_framebuffer *old_fb) | |
6077 | { | |
6078 | struct drm_device *dev = crtc->dev; | |
6079 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b701d27 EA |
6080 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6081 | int pipe = intel_crtc->pipe; | |
f564048e EA |
6082 | int ret; |
6083 | ||
0b701d27 | 6084 | drm_vblank_pre_modeset(dev, pipe); |
7662c8bd | 6085 | |
f564048e EA |
6086 | ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, |
6087 | x, y, old_fb); | |
79e53945 | 6088 | drm_vblank_post_modeset(dev, pipe); |
5c3b82e2 | 6089 | |
d8e70a25 JB |
6090 | if (ret) |
6091 | intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF; | |
6092 | else | |
6093 | intel_crtc->dpms_mode = DRM_MODE_DPMS_ON; | |
120eced9 | 6094 | |
1f803ee5 | 6095 | return ret; |
79e53945 JB |
6096 | } |
6097 | ||
3a9627f4 WF |
6098 | static bool intel_eld_uptodate(struct drm_connector *connector, |
6099 | int reg_eldv, uint32_t bits_eldv, | |
6100 | int reg_elda, uint32_t bits_elda, | |
6101 | int reg_edid) | |
6102 | { | |
6103 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6104 | uint8_t *eld = connector->eld; | |
6105 | uint32_t i; | |
6106 | ||
6107 | i = I915_READ(reg_eldv); | |
6108 | i &= bits_eldv; | |
6109 | ||
6110 | if (!eld[0]) | |
6111 | return !i; | |
6112 | ||
6113 | if (!i) | |
6114 | return false; | |
6115 | ||
6116 | i = I915_READ(reg_elda); | |
6117 | i &= ~bits_elda; | |
6118 | I915_WRITE(reg_elda, i); | |
6119 | ||
6120 | for (i = 0; i < eld[2]; i++) | |
6121 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
6122 | return false; | |
6123 | ||
6124 | return true; | |
6125 | } | |
6126 | ||
e0dac65e WF |
6127 | static void g4x_write_eld(struct drm_connector *connector, |
6128 | struct drm_crtc *crtc) | |
6129 | { | |
6130 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6131 | uint8_t *eld = connector->eld; | |
6132 | uint32_t eldv; | |
6133 | uint32_t len; | |
6134 | uint32_t i; | |
6135 | ||
6136 | i = I915_READ(G4X_AUD_VID_DID); | |
6137 | ||
6138 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
6139 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
6140 | else | |
6141 | eldv = G4X_ELDV_DEVCTG; | |
6142 | ||
3a9627f4 WF |
6143 | if (intel_eld_uptodate(connector, |
6144 | G4X_AUD_CNTL_ST, eldv, | |
6145 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
6146 | G4X_HDMIW_HDMIEDID)) | |
6147 | return; | |
6148 | ||
e0dac65e WF |
6149 | i = I915_READ(G4X_AUD_CNTL_ST); |
6150 | i &= ~(eldv | G4X_ELD_ADDR); | |
6151 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
6152 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
6153 | ||
6154 | if (!eld[0]) | |
6155 | return; | |
6156 | ||
6157 | len = min_t(uint8_t, eld[2], len); | |
6158 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6159 | for (i = 0; i < len; i++) | |
6160 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
6161 | ||
6162 | i = I915_READ(G4X_AUD_CNTL_ST); | |
6163 | i |= eldv; | |
6164 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
6165 | } | |
6166 | ||
6167 | static void ironlake_write_eld(struct drm_connector *connector, | |
6168 | struct drm_crtc *crtc) | |
6169 | { | |
6170 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
6171 | uint8_t *eld = connector->eld; | |
6172 | uint32_t eldv; | |
6173 | uint32_t i; | |
6174 | int len; | |
6175 | int hdmiw_hdmiedid; | |
b6daa025 | 6176 | int aud_config; |
e0dac65e WF |
6177 | int aud_cntl_st; |
6178 | int aud_cntrl_st2; | |
6179 | ||
b3f33cbf | 6180 | if (HAS_PCH_IBX(connector->dev)) { |
1202b4c6 | 6181 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A; |
b6daa025 | 6182 | aud_config = IBX_AUD_CONFIG_A; |
1202b4c6 WF |
6183 | aud_cntl_st = IBX_AUD_CNTL_ST_A; |
6184 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; | |
e0dac65e | 6185 | } else { |
1202b4c6 | 6186 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A; |
b6daa025 | 6187 | aud_config = CPT_AUD_CONFIG_A; |
1202b4c6 WF |
6188 | aud_cntl_st = CPT_AUD_CNTL_ST_A; |
6189 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; | |
e0dac65e WF |
6190 | } |
6191 | ||
6192 | i = to_intel_crtc(crtc)->pipe; | |
6193 | hdmiw_hdmiedid += i * 0x100; | |
6194 | aud_cntl_st += i * 0x100; | |
b6daa025 | 6195 | aud_config += i * 0x100; |
e0dac65e WF |
6196 | |
6197 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i)); | |
6198 | ||
6199 | i = I915_READ(aud_cntl_st); | |
6200 | i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */ | |
6201 | if (!i) { | |
6202 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
6203 | /* operate blindly on all ports */ | |
1202b4c6 WF |
6204 | eldv = IBX_ELD_VALIDB; |
6205 | eldv |= IBX_ELD_VALIDB << 4; | |
6206 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e WF |
6207 | } else { |
6208 | DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); | |
1202b4c6 | 6209 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
6210 | } |
6211 | ||
3a9627f4 WF |
6212 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
6213 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
6214 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 WF |
6215 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
6216 | } else | |
6217 | I915_WRITE(aud_config, 0); | |
e0dac65e | 6218 | |
3a9627f4 WF |
6219 | if (intel_eld_uptodate(connector, |
6220 | aud_cntrl_st2, eldv, | |
6221 | aud_cntl_st, IBX_ELD_ADDRESS, | |
6222 | hdmiw_hdmiedid)) | |
6223 | return; | |
6224 | ||
e0dac65e WF |
6225 | i = I915_READ(aud_cntrl_st2); |
6226 | i &= ~eldv; | |
6227 | I915_WRITE(aud_cntrl_st2, i); | |
6228 | ||
6229 | if (!eld[0]) | |
6230 | return; | |
6231 | ||
e0dac65e | 6232 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 6233 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
6234 | I915_WRITE(aud_cntl_st, i); |
6235 | ||
6236 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
6237 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
6238 | for (i = 0; i < len; i++) | |
6239 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
6240 | ||
6241 | i = I915_READ(aud_cntrl_st2); | |
6242 | i |= eldv; | |
6243 | I915_WRITE(aud_cntrl_st2, i); | |
6244 | } | |
6245 | ||
6246 | void intel_write_eld(struct drm_encoder *encoder, | |
6247 | struct drm_display_mode *mode) | |
6248 | { | |
6249 | struct drm_crtc *crtc = encoder->crtc; | |
6250 | struct drm_connector *connector; | |
6251 | struct drm_device *dev = encoder->dev; | |
6252 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6253 | ||
6254 | connector = drm_select_eld(encoder, mode); | |
6255 | if (!connector) | |
6256 | return; | |
6257 | ||
6258 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
6259 | connector->base.id, | |
6260 | drm_get_connector_name(connector), | |
6261 | connector->encoder->base.id, | |
6262 | drm_get_encoder_name(connector->encoder)); | |
6263 | ||
6264 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
6265 | ||
6266 | if (dev_priv->display.write_eld) | |
6267 | dev_priv->display.write_eld(connector, crtc); | |
6268 | } | |
6269 | ||
79e53945 JB |
6270 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ |
6271 | void intel_crtc_load_lut(struct drm_crtc *crtc) | |
6272 | { | |
6273 | struct drm_device *dev = crtc->dev; | |
6274 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6275 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9db4a9c7 | 6276 | int palreg = PALETTE(intel_crtc->pipe); |
79e53945 JB |
6277 | int i; |
6278 | ||
6279 | /* The clocks have to be on to load the palette. */ | |
aed3f09d | 6280 | if (!crtc->enabled || !intel_crtc->active) |
79e53945 JB |
6281 | return; |
6282 | ||
f2b115e6 | 6283 | /* use legacy palette for Ironlake */ |
bad720ff | 6284 | if (HAS_PCH_SPLIT(dev)) |
9db4a9c7 | 6285 | palreg = LGC_PALETTE(intel_crtc->pipe); |
2c07245f | 6286 | |
79e53945 JB |
6287 | for (i = 0; i < 256; i++) { |
6288 | I915_WRITE(palreg + 4 * i, | |
6289 | (intel_crtc->lut_r[i] << 16) | | |
6290 | (intel_crtc->lut_g[i] << 8) | | |
6291 | intel_crtc->lut_b[i]); | |
6292 | } | |
6293 | } | |
6294 | ||
560b85bb CW |
6295 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
6296 | { | |
6297 | struct drm_device *dev = crtc->dev; | |
6298 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6299 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6300 | bool visible = base != 0; | |
6301 | u32 cntl; | |
6302 | ||
6303 | if (intel_crtc->cursor_visible == visible) | |
6304 | return; | |
6305 | ||
9db4a9c7 | 6306 | cntl = I915_READ(_CURACNTR); |
560b85bb CW |
6307 | if (visible) { |
6308 | /* On these chipsets we can only modify the base whilst | |
6309 | * the cursor is disabled. | |
6310 | */ | |
9db4a9c7 | 6311 | I915_WRITE(_CURABASE, base); |
560b85bb CW |
6312 | |
6313 | cntl &= ~(CURSOR_FORMAT_MASK); | |
6314 | /* XXX width must be 64, stride 256 => 0x00 << 28 */ | |
6315 | cntl |= CURSOR_ENABLE | | |
6316 | CURSOR_GAMMA_ENABLE | | |
6317 | CURSOR_FORMAT_ARGB; | |
6318 | } else | |
6319 | cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); | |
9db4a9c7 | 6320 | I915_WRITE(_CURACNTR, cntl); |
560b85bb CW |
6321 | |
6322 | intel_crtc->cursor_visible = visible; | |
6323 | } | |
6324 | ||
6325 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) | |
6326 | { | |
6327 | struct drm_device *dev = crtc->dev; | |
6328 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6329 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6330 | int pipe = intel_crtc->pipe; | |
6331 | bool visible = base != 0; | |
6332 | ||
6333 | if (intel_crtc->cursor_visible != visible) { | |
548f245b | 6334 | uint32_t cntl = I915_READ(CURCNTR(pipe)); |
560b85bb CW |
6335 | if (base) { |
6336 | cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); | |
6337 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6338 | cntl |= pipe << 28; /* Connect to correct pipe */ | |
6339 | } else { | |
6340 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6341 | cntl |= CURSOR_MODE_DISABLE; | |
6342 | } | |
9db4a9c7 | 6343 | I915_WRITE(CURCNTR(pipe), cntl); |
560b85bb CW |
6344 | |
6345 | intel_crtc->cursor_visible = visible; | |
6346 | } | |
6347 | /* and commit changes on next vblank */ | |
9db4a9c7 | 6348 | I915_WRITE(CURBASE(pipe), base); |
560b85bb CW |
6349 | } |
6350 | ||
65a21cd6 JB |
6351 | static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) |
6352 | { | |
6353 | struct drm_device *dev = crtc->dev; | |
6354 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6355 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6356 | int pipe = intel_crtc->pipe; | |
6357 | bool visible = base != 0; | |
6358 | ||
6359 | if (intel_crtc->cursor_visible != visible) { | |
6360 | uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); | |
6361 | if (base) { | |
6362 | cntl &= ~CURSOR_MODE; | |
6363 | cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; | |
6364 | } else { | |
6365 | cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); | |
6366 | cntl |= CURSOR_MODE_DISABLE; | |
6367 | } | |
6368 | I915_WRITE(CURCNTR_IVB(pipe), cntl); | |
6369 | ||
6370 | intel_crtc->cursor_visible = visible; | |
6371 | } | |
6372 | /* and commit changes on next vblank */ | |
6373 | I915_WRITE(CURBASE_IVB(pipe), base); | |
6374 | } | |
6375 | ||
cda4b7d3 | 6376 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
6377 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
6378 | bool on) | |
cda4b7d3 CW |
6379 | { |
6380 | struct drm_device *dev = crtc->dev; | |
6381 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6382 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6383 | int pipe = intel_crtc->pipe; | |
6384 | int x = intel_crtc->cursor_x; | |
6385 | int y = intel_crtc->cursor_y; | |
560b85bb | 6386 | u32 base, pos; |
cda4b7d3 CW |
6387 | bool visible; |
6388 | ||
6389 | pos = 0; | |
6390 | ||
6b383a7f | 6391 | if (on && crtc->enabled && crtc->fb) { |
cda4b7d3 CW |
6392 | base = intel_crtc->cursor_addr; |
6393 | if (x > (int) crtc->fb->width) | |
6394 | base = 0; | |
6395 | ||
6396 | if (y > (int) crtc->fb->height) | |
6397 | base = 0; | |
6398 | } else | |
6399 | base = 0; | |
6400 | ||
6401 | if (x < 0) { | |
6402 | if (x + intel_crtc->cursor_width < 0) | |
6403 | base = 0; | |
6404 | ||
6405 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
6406 | x = -x; | |
6407 | } | |
6408 | pos |= x << CURSOR_X_SHIFT; | |
6409 | ||
6410 | if (y < 0) { | |
6411 | if (y + intel_crtc->cursor_height < 0) | |
6412 | base = 0; | |
6413 | ||
6414 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
6415 | y = -y; | |
6416 | } | |
6417 | pos |= y << CURSOR_Y_SHIFT; | |
6418 | ||
6419 | visible = base != 0; | |
560b85bb | 6420 | if (!visible && !intel_crtc->cursor_visible) |
cda4b7d3 CW |
6421 | return; |
6422 | ||
65a21cd6 JB |
6423 | if (IS_IVYBRIDGE(dev)) { |
6424 | I915_WRITE(CURPOS_IVB(pipe), pos); | |
6425 | ivb_update_cursor(crtc, base); | |
6426 | } else { | |
6427 | I915_WRITE(CURPOS(pipe), pos); | |
6428 | if (IS_845G(dev) || IS_I865G(dev)) | |
6429 | i845_update_cursor(crtc, base); | |
6430 | else | |
6431 | i9xx_update_cursor(crtc, base); | |
6432 | } | |
cda4b7d3 CW |
6433 | |
6434 | if (visible) | |
6435 | intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj); | |
6436 | } | |
6437 | ||
79e53945 | 6438 | static int intel_crtc_cursor_set(struct drm_crtc *crtc, |
05394f39 | 6439 | struct drm_file *file, |
79e53945 JB |
6440 | uint32_t handle, |
6441 | uint32_t width, uint32_t height) | |
6442 | { | |
6443 | struct drm_device *dev = crtc->dev; | |
6444 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6445 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 6446 | struct drm_i915_gem_object *obj; |
cda4b7d3 | 6447 | uint32_t addr; |
3f8bc370 | 6448 | int ret; |
79e53945 | 6449 | |
28c97730 | 6450 | DRM_DEBUG_KMS("\n"); |
79e53945 JB |
6451 | |
6452 | /* if we want to turn off the cursor ignore width and height */ | |
6453 | if (!handle) { | |
28c97730 | 6454 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 6455 | addr = 0; |
05394f39 | 6456 | obj = NULL; |
5004417d | 6457 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 6458 | goto finish; |
79e53945 JB |
6459 | } |
6460 | ||
6461 | /* Currently we only support 64x64 cursors */ | |
6462 | if (width != 64 || height != 64) { | |
6463 | DRM_ERROR("we currently only support 64x64 cursors\n"); | |
6464 | return -EINVAL; | |
6465 | } | |
6466 | ||
05394f39 | 6467 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 6468 | if (&obj->base == NULL) |
79e53945 JB |
6469 | return -ENOENT; |
6470 | ||
05394f39 | 6471 | if (obj->base.size < width * height * 4) { |
79e53945 | 6472 | DRM_ERROR("buffer is to small\n"); |
34b8686e DA |
6473 | ret = -ENOMEM; |
6474 | goto fail; | |
79e53945 JB |
6475 | } |
6476 | ||
71acb5eb | 6477 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 6478 | mutex_lock(&dev->struct_mutex); |
b295d1b6 | 6479 | if (!dev_priv->info->cursor_needs_physical) { |
d9e86c0e CW |
6480 | if (obj->tiling_mode) { |
6481 | DRM_ERROR("cursor cannot be tiled\n"); | |
6482 | ret = -EINVAL; | |
6483 | goto fail_locked; | |
6484 | } | |
6485 | ||
2da3b9b9 | 6486 | ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); |
e7b526bb CW |
6487 | if (ret) { |
6488 | DRM_ERROR("failed to move cursor bo into the GTT\n"); | |
2da3b9b9 | 6489 | goto fail_locked; |
e7b526bb CW |
6490 | } |
6491 | ||
d9e86c0e CW |
6492 | ret = i915_gem_object_put_fence(obj); |
6493 | if (ret) { | |
2da3b9b9 | 6494 | DRM_ERROR("failed to release fence for cursor"); |
d9e86c0e CW |
6495 | goto fail_unpin; |
6496 | } | |
6497 | ||
05394f39 | 6498 | addr = obj->gtt_offset; |
71acb5eb | 6499 | } else { |
6eeefaf3 | 6500 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
05394f39 | 6501 | ret = i915_gem_attach_phys_object(dev, obj, |
6eeefaf3 CW |
6502 | (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, |
6503 | align); | |
71acb5eb DA |
6504 | if (ret) { |
6505 | DRM_ERROR("failed to attach phys object\n"); | |
7f9872e0 | 6506 | goto fail_locked; |
71acb5eb | 6507 | } |
05394f39 | 6508 | addr = obj->phys_obj->handle->busaddr; |
3f8bc370 KH |
6509 | } |
6510 | ||
a6c45cf0 | 6511 | if (IS_GEN2(dev)) |
14b60391 JB |
6512 | I915_WRITE(CURSIZE, (height << 12) | width); |
6513 | ||
3f8bc370 | 6514 | finish: |
3f8bc370 | 6515 | if (intel_crtc->cursor_bo) { |
b295d1b6 | 6516 | if (dev_priv->info->cursor_needs_physical) { |
05394f39 | 6517 | if (intel_crtc->cursor_bo != obj) |
71acb5eb DA |
6518 | i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); |
6519 | } else | |
6520 | i915_gem_object_unpin(intel_crtc->cursor_bo); | |
05394f39 | 6521 | drm_gem_object_unreference(&intel_crtc->cursor_bo->base); |
3f8bc370 | 6522 | } |
80824003 | 6523 | |
7f9872e0 | 6524 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 KH |
6525 | |
6526 | intel_crtc->cursor_addr = addr; | |
05394f39 | 6527 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
6528 | intel_crtc->cursor_width = width; |
6529 | intel_crtc->cursor_height = height; | |
6530 | ||
6b383a7f | 6531 | intel_crtc_update_cursor(crtc, true); |
3f8bc370 | 6532 | |
79e53945 | 6533 | return 0; |
e7b526bb | 6534 | fail_unpin: |
05394f39 | 6535 | i915_gem_object_unpin(obj); |
7f9872e0 | 6536 | fail_locked: |
34b8686e | 6537 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 6538 | fail: |
05394f39 | 6539 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 6540 | return ret; |
79e53945 JB |
6541 | } |
6542 | ||
6543 | static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
6544 | { | |
79e53945 | 6545 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6546 | |
cda4b7d3 CW |
6547 | intel_crtc->cursor_x = x; |
6548 | intel_crtc->cursor_y = y; | |
652c393a | 6549 | |
6b383a7f | 6550 | intel_crtc_update_cursor(crtc, true); |
79e53945 JB |
6551 | |
6552 | return 0; | |
6553 | } | |
6554 | ||
6555 | /** Sets the color ramps on behalf of RandR */ | |
6556 | void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
6557 | u16 blue, int regno) | |
6558 | { | |
6559 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6560 | ||
6561 | intel_crtc->lut_r[regno] = red >> 8; | |
6562 | intel_crtc->lut_g[regno] = green >> 8; | |
6563 | intel_crtc->lut_b[regno] = blue >> 8; | |
6564 | } | |
6565 | ||
b8c00ac5 DA |
6566 | void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, |
6567 | u16 *blue, int regno) | |
6568 | { | |
6569 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6570 | ||
6571 | *red = intel_crtc->lut_r[regno] << 8; | |
6572 | *green = intel_crtc->lut_g[regno] << 8; | |
6573 | *blue = intel_crtc->lut_b[regno] << 8; | |
6574 | } | |
6575 | ||
79e53945 | 6576 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 6577 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 6578 | { |
7203425a | 6579 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 6580 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 6581 | |
7203425a | 6582 | for (i = start; i < end; i++) { |
79e53945 JB |
6583 | intel_crtc->lut_r[i] = red[i] >> 8; |
6584 | intel_crtc->lut_g[i] = green[i] >> 8; | |
6585 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
6586 | } | |
6587 | ||
6588 | intel_crtc_load_lut(crtc); | |
6589 | } | |
6590 | ||
6591 | /** | |
6592 | * Get a pipe with a simple mode set on it for doing load-based monitor | |
6593 | * detection. | |
6594 | * | |
6595 | * It will be up to the load-detect code to adjust the pipe as appropriate for | |
c751ce4f | 6596 | * its requirements. The pipe will be connected to no other encoders. |
79e53945 | 6597 | * |
c751ce4f | 6598 | * Currently this code will only succeed if there is a pipe with no encoders |
79e53945 JB |
6599 | * configured for it. In the future, it could choose to temporarily disable |
6600 | * some outputs to free up a pipe for its use. | |
6601 | * | |
6602 | * \return crtc, or NULL if no pipes are available. | |
6603 | */ | |
6604 | ||
6605 | /* VESA 640x480x72Hz mode to set on the pipe */ | |
6606 | static struct drm_display_mode load_detect_mode = { | |
6607 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
6608 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
6609 | }; | |
6610 | ||
d2dff872 CW |
6611 | static struct drm_framebuffer * |
6612 | intel_framebuffer_create(struct drm_device *dev, | |
308e5bcb | 6613 | struct drm_mode_fb_cmd2 *mode_cmd, |
d2dff872 CW |
6614 | struct drm_i915_gem_object *obj) |
6615 | { | |
6616 | struct intel_framebuffer *intel_fb; | |
6617 | int ret; | |
6618 | ||
6619 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
6620 | if (!intel_fb) { | |
6621 | drm_gem_object_unreference_unlocked(&obj->base); | |
6622 | return ERR_PTR(-ENOMEM); | |
6623 | } | |
6624 | ||
6625 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
6626 | if (ret) { | |
6627 | drm_gem_object_unreference_unlocked(&obj->base); | |
6628 | kfree(intel_fb); | |
6629 | return ERR_PTR(ret); | |
6630 | } | |
6631 | ||
6632 | return &intel_fb->base; | |
6633 | } | |
6634 | ||
6635 | static u32 | |
6636 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
6637 | { | |
6638 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
6639 | return ALIGN(pitch, 64); | |
6640 | } | |
6641 | ||
6642 | static u32 | |
6643 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
6644 | { | |
6645 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
6646 | return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); | |
6647 | } | |
6648 | ||
6649 | static struct drm_framebuffer * | |
6650 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
6651 | struct drm_display_mode *mode, | |
6652 | int depth, int bpp) | |
6653 | { | |
6654 | struct drm_i915_gem_object *obj; | |
308e5bcb | 6655 | struct drm_mode_fb_cmd2 mode_cmd; |
d2dff872 CW |
6656 | |
6657 | obj = i915_gem_alloc_object(dev, | |
6658 | intel_framebuffer_size_for_mode(mode, bpp)); | |
6659 | if (obj == NULL) | |
6660 | return ERR_PTR(-ENOMEM); | |
6661 | ||
6662 | mode_cmd.width = mode->hdisplay; | |
6663 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
6664 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
6665 | bpp); | |
5ca0c34a | 6666 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
6667 | |
6668 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
6669 | } | |
6670 | ||
6671 | static struct drm_framebuffer * | |
6672 | mode_fits_in_fbdev(struct drm_device *dev, | |
6673 | struct drm_display_mode *mode) | |
6674 | { | |
6675 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6676 | struct drm_i915_gem_object *obj; | |
6677 | struct drm_framebuffer *fb; | |
6678 | ||
6679 | if (dev_priv->fbdev == NULL) | |
6680 | return NULL; | |
6681 | ||
6682 | obj = dev_priv->fbdev->ifb.obj; | |
6683 | if (obj == NULL) | |
6684 | return NULL; | |
6685 | ||
6686 | fb = &dev_priv->fbdev->ifb.base; | |
01f2c773 VS |
6687 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
6688 | fb->bits_per_pixel)) | |
d2dff872 CW |
6689 | return NULL; |
6690 | ||
01f2c773 | 6691 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
6692 | return NULL; |
6693 | ||
6694 | return fb; | |
6695 | } | |
6696 | ||
7173188d CW |
6697 | bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, |
6698 | struct drm_connector *connector, | |
6699 | struct drm_display_mode *mode, | |
8261b191 | 6700 | struct intel_load_detect_pipe *old) |
79e53945 JB |
6701 | { |
6702 | struct intel_crtc *intel_crtc; | |
6703 | struct drm_crtc *possible_crtc; | |
4ef69c7a | 6704 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
6705 | struct drm_crtc *crtc = NULL; |
6706 | struct drm_device *dev = encoder->dev; | |
d2dff872 | 6707 | struct drm_framebuffer *old_fb; |
79e53945 JB |
6708 | int i = -1; |
6709 | ||
d2dff872 CW |
6710 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6711 | connector->base.id, drm_get_connector_name(connector), | |
6712 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6713 | ||
79e53945 JB |
6714 | /* |
6715 | * Algorithm gets a little messy: | |
7a5e4805 | 6716 | * |
79e53945 JB |
6717 | * - if the connector already has an assigned crtc, use it (but make |
6718 | * sure it's on first) | |
7a5e4805 | 6719 | * |
79e53945 JB |
6720 | * - try to find the first unused crtc that can drive this connector, |
6721 | * and use that if we find one | |
79e53945 JB |
6722 | */ |
6723 | ||
6724 | /* See if we already have a CRTC for this connector */ | |
6725 | if (encoder->crtc) { | |
6726 | crtc = encoder->crtc; | |
8261b191 | 6727 | |
79e53945 | 6728 | intel_crtc = to_intel_crtc(crtc); |
8261b191 CW |
6729 | old->dpms_mode = intel_crtc->dpms_mode; |
6730 | old->load_detect_temp = false; | |
6731 | ||
6732 | /* Make sure the crtc and connector are running */ | |
79e53945 | 6733 | if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) { |
6492711d CW |
6734 | struct drm_encoder_helper_funcs *encoder_funcs; |
6735 | struct drm_crtc_helper_funcs *crtc_funcs; | |
6736 | ||
79e53945 JB |
6737 | crtc_funcs = crtc->helper_private; |
6738 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
6492711d CW |
6739 | |
6740 | encoder_funcs = encoder->helper_private; | |
79e53945 JB |
6741 | encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON); |
6742 | } | |
8261b191 | 6743 | |
7173188d | 6744 | return true; |
79e53945 JB |
6745 | } |
6746 | ||
6747 | /* Find an unused one (if possible) */ | |
6748 | list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { | |
6749 | i++; | |
6750 | if (!(encoder->possible_crtcs & (1 << i))) | |
6751 | continue; | |
6752 | if (!possible_crtc->enabled) { | |
6753 | crtc = possible_crtc; | |
6754 | break; | |
6755 | } | |
79e53945 JB |
6756 | } |
6757 | ||
6758 | /* | |
6759 | * If we didn't find an unused CRTC, don't use any. | |
6760 | */ | |
6761 | if (!crtc) { | |
7173188d CW |
6762 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
6763 | return false; | |
79e53945 JB |
6764 | } |
6765 | ||
6766 | encoder->crtc = crtc; | |
c1c43977 | 6767 | connector->encoder = encoder; |
79e53945 JB |
6768 | |
6769 | intel_crtc = to_intel_crtc(crtc); | |
8261b191 CW |
6770 | old->dpms_mode = intel_crtc->dpms_mode; |
6771 | old->load_detect_temp = true; | |
d2dff872 | 6772 | old->release_fb = NULL; |
79e53945 | 6773 | |
6492711d CW |
6774 | if (!mode) |
6775 | mode = &load_detect_mode; | |
79e53945 | 6776 | |
d2dff872 CW |
6777 | old_fb = crtc->fb; |
6778 | ||
6779 | /* We need a framebuffer large enough to accommodate all accesses | |
6780 | * that the plane may generate whilst we perform load detection. | |
6781 | * We can not rely on the fbcon either being present (we get called | |
6782 | * during its initialisation to detect all boot displays, or it may | |
6783 | * not even exist) or that it is large enough to satisfy the | |
6784 | * requested mode. | |
6785 | */ | |
6786 | crtc->fb = mode_fits_in_fbdev(dev, mode); | |
6787 | if (crtc->fb == NULL) { | |
6788 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); | |
6789 | crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); | |
6790 | old->release_fb = crtc->fb; | |
6791 | } else | |
6792 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
6793 | if (IS_ERR(crtc->fb)) { | |
6794 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); | |
6795 | crtc->fb = old_fb; | |
6796 | return false; | |
79e53945 | 6797 | } |
79e53945 | 6798 | |
d2dff872 | 6799 | if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) { |
6492711d | 6800 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
6801 | if (old->release_fb) |
6802 | old->release_fb->funcs->destroy(old->release_fb); | |
6803 | crtc->fb = old_fb; | |
6492711d | 6804 | return false; |
79e53945 | 6805 | } |
7173188d | 6806 | |
79e53945 | 6807 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 6808 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
79e53945 | 6809 | |
7173188d | 6810 | return true; |
79e53945 JB |
6811 | } |
6812 | ||
c1c43977 | 6813 | void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, |
8261b191 CW |
6814 | struct drm_connector *connector, |
6815 | struct intel_load_detect_pipe *old) | |
79e53945 | 6816 | { |
4ef69c7a | 6817 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
6818 | struct drm_device *dev = encoder->dev; |
6819 | struct drm_crtc *crtc = encoder->crtc; | |
6820 | struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private; | |
6821 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
6822 | ||
d2dff872 CW |
6823 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
6824 | connector->base.id, drm_get_connector_name(connector), | |
6825 | encoder->base.id, drm_get_encoder_name(encoder)); | |
6826 | ||
8261b191 | 6827 | if (old->load_detect_temp) { |
c1c43977 | 6828 | connector->encoder = NULL; |
79e53945 | 6829 | drm_helper_disable_unused_functions(dev); |
d2dff872 CW |
6830 | |
6831 | if (old->release_fb) | |
6832 | old->release_fb->funcs->destroy(old->release_fb); | |
6833 | ||
0622a53c | 6834 | return; |
79e53945 JB |
6835 | } |
6836 | ||
c751ce4f | 6837 | /* Switch crtc and encoder back off if necessary */ |
0622a53c CW |
6838 | if (old->dpms_mode != DRM_MODE_DPMS_ON) { |
6839 | encoder_funcs->dpms(encoder, old->dpms_mode); | |
8261b191 | 6840 | crtc_funcs->dpms(crtc, old->dpms_mode); |
79e53945 JB |
6841 | } |
6842 | } | |
6843 | ||
6844 | /* Returns the clock of the currently programmed mode of the given pipe. */ | |
6845 | static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) | |
6846 | { | |
6847 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6848 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6849 | int pipe = intel_crtc->pipe; | |
548f245b | 6850 | u32 dpll = I915_READ(DPLL(pipe)); |
79e53945 JB |
6851 | u32 fp; |
6852 | intel_clock_t clock; | |
6853 | ||
6854 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
39adb7a5 | 6855 | fp = I915_READ(FP0(pipe)); |
79e53945 | 6856 | else |
39adb7a5 | 6857 | fp = I915_READ(FP1(pipe)); |
79e53945 JB |
6858 | |
6859 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
6860 | if (IS_PINEVIEW(dev)) { |
6861 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
6862 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
6863 | } else { |
6864 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
6865 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
6866 | } | |
6867 | ||
a6c45cf0 | 6868 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
6869 | if (IS_PINEVIEW(dev)) |
6870 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
6871 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
6872 | else |
6873 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
6874 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
6875 | ||
6876 | switch (dpll & DPLL_MODE_MASK) { | |
6877 | case DPLLB_MODE_DAC_SERIAL: | |
6878 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
6879 | 5 : 10; | |
6880 | break; | |
6881 | case DPLLB_MODE_LVDS: | |
6882 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
6883 | 7 : 14; | |
6884 | break; | |
6885 | default: | |
28c97730 | 6886 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 JB |
6887 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
6888 | return 0; | |
6889 | } | |
6890 | ||
6891 | /* XXX: Handle the 100Mhz refclk */ | |
2177832f | 6892 | intel_clock(dev, 96000, &clock); |
79e53945 JB |
6893 | } else { |
6894 | bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); | |
6895 | ||
6896 | if (is_lvds) { | |
6897 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
6898 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
6899 | clock.p2 = 14; | |
6900 | ||
6901 | if ((dpll & PLL_REF_INPUT_MASK) == | |
6902 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
6903 | /* XXX: might not be 66MHz */ | |
2177832f | 6904 | intel_clock(dev, 66000, &clock); |
79e53945 | 6905 | } else |
2177832f | 6906 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6907 | } else { |
6908 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
6909 | clock.p1 = 2; | |
6910 | else { | |
6911 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
6912 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
6913 | } | |
6914 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
6915 | clock.p2 = 4; | |
6916 | else | |
6917 | clock.p2 = 2; | |
6918 | ||
2177832f | 6919 | intel_clock(dev, 48000, &clock); |
79e53945 JB |
6920 | } |
6921 | } | |
6922 | ||
6923 | /* XXX: It would be nice to validate the clocks, but we can't reuse | |
6924 | * i830PllIsValid() because it relies on the xf86_config connector | |
6925 | * configuration being accurate, which it isn't necessarily. | |
6926 | */ | |
6927 | ||
6928 | return clock.dot; | |
6929 | } | |
6930 | ||
6931 | /** Returns the currently programmed mode of the given pipe. */ | |
6932 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
6933 | struct drm_crtc *crtc) | |
6934 | { | |
548f245b | 6935 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
6936 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6937 | int pipe = intel_crtc->pipe; | |
6938 | struct drm_display_mode *mode; | |
548f245b JB |
6939 | int htot = I915_READ(HTOTAL(pipe)); |
6940 | int hsync = I915_READ(HSYNC(pipe)); | |
6941 | int vtot = I915_READ(VTOTAL(pipe)); | |
6942 | int vsync = I915_READ(VSYNC(pipe)); | |
79e53945 JB |
6943 | |
6944 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
6945 | if (!mode) | |
6946 | return NULL; | |
6947 | ||
6948 | mode->clock = intel_crtc_clock_get(dev, crtc); | |
6949 | mode->hdisplay = (htot & 0xffff) + 1; | |
6950 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
6951 | mode->hsync_start = (hsync & 0xffff) + 1; | |
6952 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
6953 | mode->vdisplay = (vtot & 0xffff) + 1; | |
6954 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
6955 | mode->vsync_start = (vsync & 0xffff) + 1; | |
6956 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
6957 | ||
6958 | drm_mode_set_name(mode); | |
6959 | drm_mode_set_crtcinfo(mode, 0); | |
6960 | ||
6961 | return mode; | |
6962 | } | |
6963 | ||
652c393a JB |
6964 | #define GPU_IDLE_TIMEOUT 500 /* ms */ |
6965 | ||
6966 | /* When this timer fires, we've been idle for awhile */ | |
6967 | static void intel_gpu_idle_timer(unsigned long arg) | |
6968 | { | |
6969 | struct drm_device *dev = (struct drm_device *)arg; | |
6970 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6971 | ||
ff7ea4c0 CW |
6972 | if (!list_empty(&dev_priv->mm.active_list)) { |
6973 | /* Still processing requests, so just re-arm the timer. */ | |
6974 | mod_timer(&dev_priv->idle_timer, jiffies + | |
6975 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
6976 | return; | |
6977 | } | |
652c393a | 6978 | |
ff7ea4c0 | 6979 | dev_priv->busy = false; |
01dfba93 | 6980 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
6981 | } |
6982 | ||
652c393a JB |
6983 | #define CRTC_IDLE_TIMEOUT 1000 /* ms */ |
6984 | ||
6985 | static void intel_crtc_idle_timer(unsigned long arg) | |
6986 | { | |
6987 | struct intel_crtc *intel_crtc = (struct intel_crtc *)arg; | |
6988 | struct drm_crtc *crtc = &intel_crtc->base; | |
6989 | drm_i915_private_t *dev_priv = crtc->dev->dev_private; | |
ff7ea4c0 | 6990 | struct intel_framebuffer *intel_fb; |
652c393a | 6991 | |
ff7ea4c0 CW |
6992 | intel_fb = to_intel_framebuffer(crtc->fb); |
6993 | if (intel_fb && intel_fb->obj->active) { | |
6994 | /* The framebuffer is still being accessed by the GPU. */ | |
6995 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
6996 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
6997 | return; | |
6998 | } | |
652c393a | 6999 | |
ff7ea4c0 | 7000 | intel_crtc->busy = false; |
01dfba93 | 7001 | queue_work(dev_priv->wq, &dev_priv->idle_work); |
652c393a JB |
7002 | } |
7003 | ||
3dec0095 | 7004 | static void intel_increase_pllclock(struct drm_crtc *crtc) |
652c393a JB |
7005 | { |
7006 | struct drm_device *dev = crtc->dev; | |
7007 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7008 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7009 | int pipe = intel_crtc->pipe; | |
dbdc6479 JB |
7010 | int dpll_reg = DPLL(pipe); |
7011 | int dpll; | |
652c393a | 7012 | |
bad720ff | 7013 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
7014 | return; |
7015 | ||
7016 | if (!dev_priv->lvds_downclock_avail) | |
7017 | return; | |
7018 | ||
dbdc6479 | 7019 | dpll = I915_READ(dpll_reg); |
652c393a | 7020 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 7021 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 7022 | |
8ac5a6d5 | 7023 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
7024 | |
7025 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
7026 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 7027 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 7028 | |
652c393a JB |
7029 | dpll = I915_READ(dpll_reg); |
7030 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 7031 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a JB |
7032 | } |
7033 | ||
7034 | /* Schedule downclock */ | |
3dec0095 DV |
7035 | mod_timer(&intel_crtc->idle_timer, jiffies + |
7036 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
652c393a JB |
7037 | } |
7038 | ||
7039 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
7040 | { | |
7041 | struct drm_device *dev = crtc->dev; | |
7042 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7043 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7044 | int pipe = intel_crtc->pipe; | |
9db4a9c7 | 7045 | int dpll_reg = DPLL(pipe); |
652c393a JB |
7046 | int dpll = I915_READ(dpll_reg); |
7047 | ||
bad720ff | 7048 | if (HAS_PCH_SPLIT(dev)) |
652c393a JB |
7049 | return; |
7050 | ||
7051 | if (!dev_priv->lvds_downclock_avail) | |
7052 | return; | |
7053 | ||
7054 | /* | |
7055 | * Since this is called by a timer, we should never get here in | |
7056 | * the manual case. | |
7057 | */ | |
7058 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
44d98a61 | 7059 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 7060 | |
8ac5a6d5 | 7061 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
7062 | |
7063 | dpll |= DISPLAY_RATE_SELECT_FPA1; | |
7064 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 7065 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
7066 | dpll = I915_READ(dpll_reg); |
7067 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 7068 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
7069 | } |
7070 | ||
7071 | } | |
7072 | ||
7073 | /** | |
7074 | * intel_idle_update - adjust clocks for idleness | |
7075 | * @work: work struct | |
7076 | * | |
7077 | * Either the GPU or display (or both) went idle. Check the busy status | |
7078 | * here and adjust the CRTC and GPU clocks as necessary. | |
7079 | */ | |
7080 | static void intel_idle_update(struct work_struct *work) | |
7081 | { | |
7082 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
7083 | idle_work); | |
7084 | struct drm_device *dev = dev_priv->dev; | |
7085 | struct drm_crtc *crtc; | |
7086 | struct intel_crtc *intel_crtc; | |
7087 | ||
7088 | if (!i915_powersave) | |
7089 | return; | |
7090 | ||
7091 | mutex_lock(&dev->struct_mutex); | |
7092 | ||
7648fa99 JB |
7093 | i915_update_gfx_val(dev_priv); |
7094 | ||
652c393a JB |
7095 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
7096 | /* Skip inactive CRTCs */ | |
7097 | if (!crtc->fb) | |
7098 | continue; | |
7099 | ||
7100 | intel_crtc = to_intel_crtc(crtc); | |
7101 | if (!intel_crtc->busy) | |
7102 | intel_decrease_pllclock(crtc); | |
7103 | } | |
7104 | ||
45ac22c8 | 7105 | |
652c393a JB |
7106 | mutex_unlock(&dev->struct_mutex); |
7107 | } | |
7108 | ||
7109 | /** | |
7110 | * intel_mark_busy - mark the GPU and possibly the display busy | |
7111 | * @dev: drm device | |
7112 | * @obj: object we're operating on | |
7113 | * | |
7114 | * Callers can use this function to indicate that the GPU is busy processing | |
7115 | * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout | |
7116 | * buffer), we'll also mark the display as busy, so we know to increase its | |
7117 | * clock frequency. | |
7118 | */ | |
05394f39 | 7119 | void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj) |
652c393a JB |
7120 | { |
7121 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7122 | struct drm_crtc *crtc = NULL; | |
7123 | struct intel_framebuffer *intel_fb; | |
7124 | struct intel_crtc *intel_crtc; | |
7125 | ||
5e17ee74 ZW |
7126 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
7127 | return; | |
7128 | ||
18b2190c | 7129 | if (!dev_priv->busy) |
28cf798f | 7130 | dev_priv->busy = true; |
18b2190c | 7131 | else |
28cf798f CW |
7132 | mod_timer(&dev_priv->idle_timer, jiffies + |
7133 | msecs_to_jiffies(GPU_IDLE_TIMEOUT)); | |
652c393a JB |
7134 | |
7135 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
7136 | if (!crtc->fb) | |
7137 | continue; | |
7138 | ||
7139 | intel_crtc = to_intel_crtc(crtc); | |
7140 | intel_fb = to_intel_framebuffer(crtc->fb); | |
7141 | if (intel_fb->obj == obj) { | |
7142 | if (!intel_crtc->busy) { | |
7143 | /* Non-busy -> busy, upclock */ | |
3dec0095 | 7144 | intel_increase_pllclock(crtc); |
652c393a JB |
7145 | intel_crtc->busy = true; |
7146 | } else { | |
7147 | /* Busy -> busy, put off timer */ | |
7148 | mod_timer(&intel_crtc->idle_timer, jiffies + | |
7149 | msecs_to_jiffies(CRTC_IDLE_TIMEOUT)); | |
7150 | } | |
7151 | } | |
7152 | } | |
7153 | } | |
7154 | ||
79e53945 JB |
7155 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
7156 | { | |
7157 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
7158 | struct drm_device *dev = crtc->dev; |
7159 | struct intel_unpin_work *work; | |
7160 | unsigned long flags; | |
7161 | ||
7162 | spin_lock_irqsave(&dev->event_lock, flags); | |
7163 | work = intel_crtc->unpin_work; | |
7164 | intel_crtc->unpin_work = NULL; | |
7165 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7166 | ||
7167 | if (work) { | |
7168 | cancel_work_sync(&work->work); | |
7169 | kfree(work); | |
7170 | } | |
79e53945 JB |
7171 | |
7172 | drm_crtc_cleanup(crtc); | |
67e77c5a | 7173 | |
79e53945 JB |
7174 | kfree(intel_crtc); |
7175 | } | |
7176 | ||
6b95a207 KH |
7177 | static void intel_unpin_work_fn(struct work_struct *__work) |
7178 | { | |
7179 | struct intel_unpin_work *work = | |
7180 | container_of(__work, struct intel_unpin_work, work); | |
7181 | ||
7182 | mutex_lock(&work->dev->struct_mutex); | |
1690e1eb | 7183 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
7184 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
7185 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 7186 | |
7782de3b | 7187 | intel_update_fbc(work->dev); |
6b95a207 KH |
7188 | mutex_unlock(&work->dev->struct_mutex); |
7189 | kfree(work); | |
7190 | } | |
7191 | ||
1afe3e9d | 7192 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 7193 | struct drm_crtc *crtc) |
6b95a207 KH |
7194 | { |
7195 | drm_i915_private_t *dev_priv = dev->dev_private; | |
6b95a207 KH |
7196 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7197 | struct intel_unpin_work *work; | |
05394f39 | 7198 | struct drm_i915_gem_object *obj; |
6b95a207 | 7199 | struct drm_pending_vblank_event *e; |
49b14a5c | 7200 | struct timeval tnow, tvbl; |
6b95a207 KH |
7201 | unsigned long flags; |
7202 | ||
7203 | /* Ignore early vblank irqs */ | |
7204 | if (intel_crtc == NULL) | |
7205 | return; | |
7206 | ||
49b14a5c MK |
7207 | do_gettimeofday(&tnow); |
7208 | ||
6b95a207 KH |
7209 | spin_lock_irqsave(&dev->event_lock, flags); |
7210 | work = intel_crtc->unpin_work; | |
7211 | if (work == NULL || !work->pending) { | |
7212 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7213 | return; | |
7214 | } | |
7215 | ||
7216 | intel_crtc->unpin_work = NULL; | |
6b95a207 KH |
7217 | |
7218 | if (work->event) { | |
7219 | e = work->event; | |
49b14a5c | 7220 | e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl); |
0af7e4df MK |
7221 | |
7222 | /* Called before vblank count and timestamps have | |
7223 | * been updated for the vblank interval of flip | |
7224 | * completion? Need to increment vblank count and | |
7225 | * add one videorefresh duration to returned timestamp | |
49b14a5c MK |
7226 | * to account for this. We assume this happened if we |
7227 | * get called over 0.9 frame durations after the last | |
7228 | * timestamped vblank. | |
7229 | * | |
7230 | * This calculation can not be used with vrefresh rates | |
7231 | * below 5Hz (10Hz to be on the safe side) without | |
7232 | * promoting to 64 integers. | |
0af7e4df | 7233 | */ |
49b14a5c MK |
7234 | if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) > |
7235 | 9 * crtc->framedur_ns) { | |
0af7e4df | 7236 | e->event.sequence++; |
49b14a5c MK |
7237 | tvbl = ns_to_timeval(timeval_to_ns(&tvbl) + |
7238 | crtc->framedur_ns); | |
0af7e4df MK |
7239 | } |
7240 | ||
49b14a5c MK |
7241 | e->event.tv_sec = tvbl.tv_sec; |
7242 | e->event.tv_usec = tvbl.tv_usec; | |
0af7e4df | 7243 | |
6b95a207 KH |
7244 | list_add_tail(&e->base.link, |
7245 | &e->base.file_priv->event_list); | |
7246 | wake_up_interruptible(&e->base.file_priv->event_wait); | |
7247 | } | |
7248 | ||
0af7e4df MK |
7249 | drm_vblank_put(dev, intel_crtc->pipe); |
7250 | ||
6b95a207 KH |
7251 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7252 | ||
05394f39 | 7253 | obj = work->old_fb_obj; |
d9e86c0e | 7254 | |
e59f2bac | 7255 | atomic_clear_mask(1 << intel_crtc->plane, |
05394f39 CW |
7256 | &obj->pending_flip.counter); |
7257 | if (atomic_read(&obj->pending_flip) == 0) | |
f787a5f5 | 7258 | wake_up(&dev_priv->pending_flip_queue); |
d9e86c0e | 7259 | |
6b95a207 | 7260 | schedule_work(&work->work); |
e5510fac JB |
7261 | |
7262 | trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj); | |
6b95a207 KH |
7263 | } |
7264 | ||
1afe3e9d JB |
7265 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
7266 | { | |
7267 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7268 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
7269 | ||
49b14a5c | 7270 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
7271 | } |
7272 | ||
7273 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
7274 | { | |
7275 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7276 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; | |
7277 | ||
49b14a5c | 7278 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
7279 | } |
7280 | ||
6b95a207 KH |
7281 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
7282 | { | |
7283 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7284 | struct intel_crtc *intel_crtc = | |
7285 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
7286 | unsigned long flags; | |
7287 | ||
7288 | spin_lock_irqsave(&dev->event_lock, flags); | |
de3f440f | 7289 | if (intel_crtc->unpin_work) { |
4e5359cd SF |
7290 | if ((++intel_crtc->unpin_work->pending) > 1) |
7291 | DRM_ERROR("Prepared flip multiple times\n"); | |
de3f440f JB |
7292 | } else { |
7293 | DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n"); | |
7294 | } | |
6b95a207 KH |
7295 | spin_unlock_irqrestore(&dev->event_lock, flags); |
7296 | } | |
7297 | ||
8c9f3aaf JB |
7298 | static int intel_gen2_queue_flip(struct drm_device *dev, |
7299 | struct drm_crtc *crtc, | |
7300 | struct drm_framebuffer *fb, | |
7301 | struct drm_i915_gem_object *obj) | |
7302 | { | |
7303 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7304 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7305 | unsigned long offset; | |
7306 | u32 flip_mask; | |
7307 | int ret; | |
7308 | ||
7309 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
7310 | if (ret) | |
7311 | goto out; | |
7312 | ||
7313 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ | |
01f2c773 | 7314 | offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; |
8c9f3aaf JB |
7315 | |
7316 | ret = BEGIN_LP_RING(6); | |
7317 | if (ret) | |
7318 | goto out; | |
7319 | ||
7320 | /* Can't queue multiple flips, so wait for the previous | |
7321 | * one to finish before executing the next. | |
7322 | */ | |
7323 | if (intel_crtc->plane) | |
7324 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
7325 | else | |
7326 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
7327 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
7328 | OUT_RING(MI_NOOP); | |
7329 | OUT_RING(MI_DISPLAY_FLIP | | |
7330 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
01f2c773 | 7331 | OUT_RING(fb->pitches[0]); |
8c9f3aaf | 7332 | OUT_RING(obj->gtt_offset + offset); |
c6a32fcb | 7333 | OUT_RING(0); /* aux display base address, unused */ |
8c9f3aaf JB |
7334 | ADVANCE_LP_RING(); |
7335 | out: | |
7336 | return ret; | |
7337 | } | |
7338 | ||
7339 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
7340 | struct drm_crtc *crtc, | |
7341 | struct drm_framebuffer *fb, | |
7342 | struct drm_i915_gem_object *obj) | |
7343 | { | |
7344 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7345 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7346 | unsigned long offset; | |
7347 | u32 flip_mask; | |
7348 | int ret; | |
7349 | ||
7350 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
7351 | if (ret) | |
7352 | goto out; | |
7353 | ||
7354 | /* Offset into the new buffer for cases of shared fbs between CRTCs */ | |
01f2c773 | 7355 | offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8; |
8c9f3aaf JB |
7356 | |
7357 | ret = BEGIN_LP_RING(6); | |
7358 | if (ret) | |
7359 | goto out; | |
7360 | ||
7361 | if (intel_crtc->plane) | |
7362 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
7363 | else | |
7364 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
7365 | OUT_RING(MI_WAIT_FOR_EVENT | flip_mask); | |
7366 | OUT_RING(MI_NOOP); | |
7367 | OUT_RING(MI_DISPLAY_FLIP_I915 | | |
7368 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
01f2c773 | 7369 | OUT_RING(fb->pitches[0]); |
8c9f3aaf JB |
7370 | OUT_RING(obj->gtt_offset + offset); |
7371 | OUT_RING(MI_NOOP); | |
7372 | ||
7373 | ADVANCE_LP_RING(); | |
7374 | out: | |
7375 | return ret; | |
7376 | } | |
7377 | ||
7378 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
7379 | struct drm_crtc *crtc, | |
7380 | struct drm_framebuffer *fb, | |
7381 | struct drm_i915_gem_object *obj) | |
7382 | { | |
7383 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7384 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7385 | uint32_t pf, pipesrc; | |
7386 | int ret; | |
7387 | ||
7388 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
7389 | if (ret) | |
7390 | goto out; | |
7391 | ||
7392 | ret = BEGIN_LP_RING(4); | |
7393 | if (ret) | |
7394 | goto out; | |
7395 | ||
7396 | /* i965+ uses the linear or tiled offsets from the | |
7397 | * Display Registers (which do not change across a page-flip) | |
7398 | * so we need only reprogram the base address. | |
7399 | */ | |
7400 | OUT_RING(MI_DISPLAY_FLIP | | |
7401 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
01f2c773 | 7402 | OUT_RING(fb->pitches[0]); |
8c9f3aaf JB |
7403 | OUT_RING(obj->gtt_offset | obj->tiling_mode); |
7404 | ||
7405 | /* XXX Enabling the panel-fitter across page-flip is so far | |
7406 | * untested on non-native modes, so ignore it for now. | |
7407 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
7408 | */ | |
7409 | pf = 0; | |
7410 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
7411 | OUT_RING(pf | pipesrc); | |
7412 | ADVANCE_LP_RING(); | |
7413 | out: | |
7414 | return ret; | |
7415 | } | |
7416 | ||
7417 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
7418 | struct drm_crtc *crtc, | |
7419 | struct drm_framebuffer *fb, | |
7420 | struct drm_i915_gem_object *obj) | |
7421 | { | |
7422 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7423 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7424 | uint32_t pf, pipesrc; | |
7425 | int ret; | |
7426 | ||
7427 | ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv)); | |
7428 | if (ret) | |
7429 | goto out; | |
7430 | ||
7431 | ret = BEGIN_LP_RING(4); | |
7432 | if (ret) | |
7433 | goto out; | |
7434 | ||
7435 | OUT_RING(MI_DISPLAY_FLIP | | |
7436 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
01f2c773 | 7437 | OUT_RING(fb->pitches[0] | obj->tiling_mode); |
8c9f3aaf JB |
7438 | OUT_RING(obj->gtt_offset); |
7439 | ||
7440 | pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
7441 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
7442 | OUT_RING(pf | pipesrc); | |
7443 | ADVANCE_LP_RING(); | |
7444 | out: | |
7445 | return ret; | |
7446 | } | |
7447 | ||
7c9017e5 JB |
7448 | /* |
7449 | * On gen7 we currently use the blit ring because (in early silicon at least) | |
7450 | * the render ring doesn't give us interrpts for page flip completion, which | |
7451 | * means clients will hang after the first flip is queued. Fortunately the | |
7452 | * blit ring generates interrupts properly, so use it instead. | |
7453 | */ | |
7454 | static int intel_gen7_queue_flip(struct drm_device *dev, | |
7455 | struct drm_crtc *crtc, | |
7456 | struct drm_framebuffer *fb, | |
7457 | struct drm_i915_gem_object *obj) | |
7458 | { | |
7459 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7460 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7461 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; | |
7462 | int ret; | |
7463 | ||
7464 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
7465 | if (ret) | |
7466 | goto out; | |
7467 | ||
7468 | ret = intel_ring_begin(ring, 4); | |
7469 | if (ret) | |
7470 | goto out; | |
7471 | ||
7472 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19)); | |
01f2c773 | 7473 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
7c9017e5 JB |
7474 | intel_ring_emit(ring, (obj->gtt_offset)); |
7475 | intel_ring_emit(ring, (MI_NOOP)); | |
7476 | intel_ring_advance(ring); | |
7477 | out: | |
7478 | return ret; | |
7479 | } | |
7480 | ||
8c9f3aaf JB |
7481 | static int intel_default_queue_flip(struct drm_device *dev, |
7482 | struct drm_crtc *crtc, | |
7483 | struct drm_framebuffer *fb, | |
7484 | struct drm_i915_gem_object *obj) | |
7485 | { | |
7486 | return -ENODEV; | |
7487 | } | |
7488 | ||
6b95a207 KH |
7489 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
7490 | struct drm_framebuffer *fb, | |
7491 | struct drm_pending_vblank_event *event) | |
7492 | { | |
7493 | struct drm_device *dev = crtc->dev; | |
7494 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7495 | struct intel_framebuffer *intel_fb; | |
05394f39 | 7496 | struct drm_i915_gem_object *obj; |
6b95a207 KH |
7497 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7498 | struct intel_unpin_work *work; | |
8c9f3aaf | 7499 | unsigned long flags; |
52e68630 | 7500 | int ret; |
6b95a207 KH |
7501 | |
7502 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
7503 | if (work == NULL) | |
7504 | return -ENOMEM; | |
7505 | ||
6b95a207 KH |
7506 | work->event = event; |
7507 | work->dev = crtc->dev; | |
7508 | intel_fb = to_intel_framebuffer(crtc->fb); | |
b1b87f6b | 7509 | work->old_fb_obj = intel_fb->obj; |
6b95a207 KH |
7510 | INIT_WORK(&work->work, intel_unpin_work_fn); |
7511 | ||
7317c75e JB |
7512 | ret = drm_vblank_get(dev, intel_crtc->pipe); |
7513 | if (ret) | |
7514 | goto free_work; | |
7515 | ||
6b95a207 KH |
7516 | /* We borrow the event spin lock for protecting unpin_work */ |
7517 | spin_lock_irqsave(&dev->event_lock, flags); | |
7518 | if (intel_crtc->unpin_work) { | |
7519 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7520 | kfree(work); | |
7317c75e | 7521 | drm_vblank_put(dev, intel_crtc->pipe); |
468f0b44 CW |
7522 | |
7523 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
6b95a207 KH |
7524 | return -EBUSY; |
7525 | } | |
7526 | intel_crtc->unpin_work = work; | |
7527 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7528 | ||
7529 | intel_fb = to_intel_framebuffer(fb); | |
7530 | obj = intel_fb->obj; | |
7531 | ||
468f0b44 | 7532 | mutex_lock(&dev->struct_mutex); |
6b95a207 | 7533 | |
75dfca80 | 7534 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
7535 | drm_gem_object_reference(&work->old_fb_obj->base); |
7536 | drm_gem_object_reference(&obj->base); | |
6b95a207 KH |
7537 | |
7538 | crtc->fb = fb; | |
96b099fd | 7539 | |
e1f99ce6 | 7540 | work->pending_flip_obj = obj; |
e1f99ce6 | 7541 | |
4e5359cd SF |
7542 | work->enable_stall_check = true; |
7543 | ||
e1f99ce6 CW |
7544 | /* Block clients from rendering to the new back buffer until |
7545 | * the flip occurs and the object is no longer visible. | |
7546 | */ | |
05394f39 | 7547 | atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); |
e1f99ce6 | 7548 | |
8c9f3aaf JB |
7549 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); |
7550 | if (ret) | |
7551 | goto cleanup_pending; | |
6b95a207 | 7552 | |
7782de3b | 7553 | intel_disable_fbc(dev); |
6b95a207 KH |
7554 | mutex_unlock(&dev->struct_mutex); |
7555 | ||
e5510fac JB |
7556 | trace_i915_flip_request(intel_crtc->plane, obj); |
7557 | ||
6b95a207 | 7558 | return 0; |
96b099fd | 7559 | |
8c9f3aaf JB |
7560 | cleanup_pending: |
7561 | atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip); | |
05394f39 CW |
7562 | drm_gem_object_unreference(&work->old_fb_obj->base); |
7563 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
7564 | mutex_unlock(&dev->struct_mutex); |
7565 | ||
7566 | spin_lock_irqsave(&dev->event_lock, flags); | |
7567 | intel_crtc->unpin_work = NULL; | |
7568 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
7569 | ||
7317c75e JB |
7570 | drm_vblank_put(dev, intel_crtc->pipe); |
7571 | free_work: | |
96b099fd CW |
7572 | kfree(work); |
7573 | ||
7574 | return ret; | |
6b95a207 KH |
7575 | } |
7576 | ||
47f1c6c9 CW |
7577 | static void intel_sanitize_modesetting(struct drm_device *dev, |
7578 | int pipe, int plane) | |
7579 | { | |
7580 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7581 | u32 reg, val; | |
7582 | ||
7583 | if (HAS_PCH_SPLIT(dev)) | |
7584 | return; | |
7585 | ||
7586 | /* Who knows what state these registers were left in by the BIOS or | |
7587 | * grub? | |
7588 | * | |
7589 | * If we leave the registers in a conflicting state (e.g. with the | |
7590 | * display plane reading from the other pipe than the one we intend | |
7591 | * to use) then when we attempt to teardown the active mode, we will | |
7592 | * not disable the pipes and planes in the correct order -- leaving | |
7593 | * a plane reading from a disabled pipe and possibly leading to | |
7594 | * undefined behaviour. | |
7595 | */ | |
7596 | ||
7597 | reg = DSPCNTR(plane); | |
7598 | val = I915_READ(reg); | |
7599 | ||
7600 | if ((val & DISPLAY_PLANE_ENABLE) == 0) | |
7601 | return; | |
7602 | if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe) | |
7603 | return; | |
7604 | ||
7605 | /* This display plane is active and attached to the other CPU pipe. */ | |
7606 | pipe = !pipe; | |
7607 | ||
7608 | /* Disable the plane and wait for it to stop reading from the pipe. */ | |
b24e7179 JB |
7609 | intel_disable_plane(dev_priv, plane, pipe); |
7610 | intel_disable_pipe(dev_priv, pipe); | |
47f1c6c9 | 7611 | } |
79e53945 | 7612 | |
f6e5b160 CW |
7613 | static void intel_crtc_reset(struct drm_crtc *crtc) |
7614 | { | |
7615 | struct drm_device *dev = crtc->dev; | |
7616 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7617 | ||
7618 | /* Reset flags back to the 'unknown' status so that they | |
7619 | * will be correctly set on the initial modeset. | |
7620 | */ | |
7621 | intel_crtc->dpms_mode = -1; | |
7622 | ||
7623 | /* We need to fix up any BIOS configuration that conflicts with | |
7624 | * our expectations. | |
7625 | */ | |
7626 | intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane); | |
7627 | } | |
7628 | ||
7629 | static struct drm_crtc_helper_funcs intel_helper_funcs = { | |
7630 | .dpms = intel_crtc_dpms, | |
7631 | .mode_fixup = intel_crtc_mode_fixup, | |
7632 | .mode_set = intel_crtc_mode_set, | |
7633 | .mode_set_base = intel_pipe_set_base, | |
7634 | .mode_set_base_atomic = intel_pipe_set_base_atomic, | |
7635 | .load_lut = intel_crtc_load_lut, | |
7636 | .disable = intel_crtc_disable, | |
7637 | }; | |
7638 | ||
7639 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
7640 | .reset = intel_crtc_reset, | |
7641 | .cursor_set = intel_crtc_cursor_set, | |
7642 | .cursor_move = intel_crtc_cursor_move, | |
7643 | .gamma_set = intel_crtc_gamma_set, | |
7644 | .set_config = drm_crtc_helper_set_config, | |
7645 | .destroy = intel_crtc_destroy, | |
7646 | .page_flip = intel_crtc_page_flip, | |
7647 | }; | |
7648 | ||
b358d0a6 | 7649 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 7650 | { |
22fd0fab | 7651 | drm_i915_private_t *dev_priv = dev->dev_private; |
79e53945 JB |
7652 | struct intel_crtc *intel_crtc; |
7653 | int i; | |
7654 | ||
7655 | intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); | |
7656 | if (intel_crtc == NULL) | |
7657 | return; | |
7658 | ||
7659 | drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); | |
7660 | ||
7661 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
7662 | for (i = 0; i < 256; i++) { |
7663 | intel_crtc->lut_r[i] = i; | |
7664 | intel_crtc->lut_g[i] = i; | |
7665 | intel_crtc->lut_b[i] = i; | |
7666 | } | |
7667 | ||
80824003 JB |
7668 | /* Swap pipes & planes for FBC on pre-965 */ |
7669 | intel_crtc->pipe = pipe; | |
7670 | intel_crtc->plane = pipe; | |
e2e767ab | 7671 | if (IS_MOBILE(dev) && IS_GEN3(dev)) { |
28c97730 | 7672 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 7673 | intel_crtc->plane = !pipe; |
80824003 JB |
7674 | } |
7675 | ||
22fd0fab JB |
7676 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
7677 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
7678 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
7679 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
7680 | ||
5d1d0cc8 | 7681 | intel_crtc_reset(&intel_crtc->base); |
04dbff52 | 7682 | intel_crtc->active = true; /* force the pipe off on setup_init_config */ |
5a354204 | 7683 | intel_crtc->bpp = 24; /* default for pre-Ironlake */ |
7e7d76c3 JB |
7684 | |
7685 | if (HAS_PCH_SPLIT(dev)) { | |
4b645f14 JB |
7686 | if (pipe == 2 && IS_IVYBRIDGE(dev)) |
7687 | intel_crtc->no_pll = true; | |
7e7d76c3 JB |
7688 | intel_helper_funcs.prepare = ironlake_crtc_prepare; |
7689 | intel_helper_funcs.commit = ironlake_crtc_commit; | |
7690 | } else { | |
7691 | intel_helper_funcs.prepare = i9xx_crtc_prepare; | |
7692 | intel_helper_funcs.commit = i9xx_crtc_commit; | |
7693 | } | |
7694 | ||
79e53945 JB |
7695 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
7696 | ||
652c393a JB |
7697 | intel_crtc->busy = false; |
7698 | ||
7699 | setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer, | |
7700 | (unsigned long)intel_crtc); | |
79e53945 JB |
7701 | } |
7702 | ||
08d7b3d1 | 7703 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 7704 | struct drm_file *file) |
08d7b3d1 CW |
7705 | { |
7706 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7707 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; | |
c05422d5 DV |
7708 | struct drm_mode_object *drmmode_obj; |
7709 | struct intel_crtc *crtc; | |
08d7b3d1 CW |
7710 | |
7711 | if (!dev_priv) { | |
7712 | DRM_ERROR("called with no initialization\n"); | |
7713 | return -EINVAL; | |
7714 | } | |
7715 | ||
c05422d5 DV |
7716 | drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, |
7717 | DRM_MODE_OBJECT_CRTC); | |
08d7b3d1 | 7718 | |
c05422d5 | 7719 | if (!drmmode_obj) { |
08d7b3d1 CW |
7720 | DRM_ERROR("no such CRTC id\n"); |
7721 | return -EINVAL; | |
7722 | } | |
7723 | ||
c05422d5 DV |
7724 | crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); |
7725 | pipe_from_crtc_id->pipe = crtc->pipe; | |
08d7b3d1 | 7726 | |
c05422d5 | 7727 | return 0; |
08d7b3d1 CW |
7728 | } |
7729 | ||
c5e4df33 | 7730 | static int intel_encoder_clones(struct drm_device *dev, int type_mask) |
79e53945 | 7731 | { |
4ef69c7a | 7732 | struct intel_encoder *encoder; |
79e53945 | 7733 | int index_mask = 0; |
79e53945 JB |
7734 | int entry = 0; |
7735 | ||
4ef69c7a CW |
7736 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7737 | if (type_mask & encoder->clone_mask) | |
79e53945 JB |
7738 | index_mask |= (1 << entry); |
7739 | entry++; | |
7740 | } | |
4ef69c7a | 7741 | |
79e53945 JB |
7742 | return index_mask; |
7743 | } | |
7744 | ||
4d302442 CW |
7745 | static bool has_edp_a(struct drm_device *dev) |
7746 | { | |
7747 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7748 | ||
7749 | if (!IS_MOBILE(dev)) | |
7750 | return false; | |
7751 | ||
7752 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
7753 | return false; | |
7754 | ||
7755 | if (IS_GEN5(dev) && | |
7756 | (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) | |
7757 | return false; | |
7758 | ||
7759 | return true; | |
7760 | } | |
7761 | ||
79e53945 JB |
7762 | static void intel_setup_outputs(struct drm_device *dev) |
7763 | { | |
725e30ad | 7764 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 7765 | struct intel_encoder *encoder; |
cb0953d7 | 7766 | bool dpd_is_edp = false; |
f3cfcba6 | 7767 | bool has_lvds; |
79e53945 | 7768 | |
f3cfcba6 | 7769 | has_lvds = intel_lvds_init(dev); |
c5d1b51d CW |
7770 | if (!has_lvds && !HAS_PCH_SPLIT(dev)) { |
7771 | /* disable the panel fitter on everything but LVDS */ | |
7772 | I915_WRITE(PFIT_CONTROL, 0); | |
7773 | } | |
79e53945 | 7774 | |
bad720ff | 7775 | if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 7776 | dpd_is_edp = intel_dpd_is_edp(dev); |
30ad48b7 | 7777 | |
4d302442 | 7778 | if (has_edp_a(dev)) |
32f9d658 ZW |
7779 | intel_dp_init(dev, DP_A); |
7780 | ||
cb0953d7 AJ |
7781 | if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
7782 | intel_dp_init(dev, PCH_DP_D); | |
7783 | } | |
7784 | ||
7785 | intel_crt_init(dev); | |
7786 | ||
7787 | if (HAS_PCH_SPLIT(dev)) { | |
7788 | int found; | |
7789 | ||
30ad48b7 | 7790 | if (I915_READ(HDMIB) & PORT_DETECTED) { |
461ed3ca ZY |
7791 | /* PCH SDVOB multiplex with HDMIB */ |
7792 | found = intel_sdvo_init(dev, PCH_SDVOB); | |
30ad48b7 ZW |
7793 | if (!found) |
7794 | intel_hdmi_init(dev, HDMIB); | |
5eb08b69 ZW |
7795 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
7796 | intel_dp_init(dev, PCH_DP_B); | |
30ad48b7 ZW |
7797 | } |
7798 | ||
7799 | if (I915_READ(HDMIC) & PORT_DETECTED) | |
7800 | intel_hdmi_init(dev, HDMIC); | |
7801 | ||
7802 | if (I915_READ(HDMID) & PORT_DETECTED) | |
7803 | intel_hdmi_init(dev, HDMID); | |
7804 | ||
5eb08b69 ZW |
7805 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
7806 | intel_dp_init(dev, PCH_DP_C); | |
7807 | ||
cb0953d7 | 7808 | if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED)) |
5eb08b69 ZW |
7809 | intel_dp_init(dev, PCH_DP_D); |
7810 | ||
103a196f | 7811 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 7812 | bool found = false; |
7d57382e | 7813 | |
725e30ad | 7814 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 7815 | DRM_DEBUG_KMS("probing SDVOB\n"); |
725e30ad | 7816 | found = intel_sdvo_init(dev, SDVOB); |
b01f2c3a JB |
7817 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
7818 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
725e30ad | 7819 | intel_hdmi_init(dev, SDVOB); |
b01f2c3a | 7820 | } |
27185ae1 | 7821 | |
b01f2c3a JB |
7822 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) { |
7823 | DRM_DEBUG_KMS("probing DP_B\n"); | |
a4fc5ed6 | 7824 | intel_dp_init(dev, DP_B); |
b01f2c3a | 7825 | } |
725e30ad | 7826 | } |
13520b05 KH |
7827 | |
7828 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 7829 | |
b01f2c3a JB |
7830 | if (I915_READ(SDVOB) & SDVO_DETECTED) { |
7831 | DRM_DEBUG_KMS("probing SDVOC\n"); | |
725e30ad | 7832 | found = intel_sdvo_init(dev, SDVOC); |
b01f2c3a | 7833 | } |
27185ae1 ML |
7834 | |
7835 | if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { | |
7836 | ||
b01f2c3a JB |
7837 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
7838 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
725e30ad | 7839 | intel_hdmi_init(dev, SDVOC); |
b01f2c3a JB |
7840 | } |
7841 | if (SUPPORTS_INTEGRATED_DP(dev)) { | |
7842 | DRM_DEBUG_KMS("probing DP_C\n"); | |
a4fc5ed6 | 7843 | intel_dp_init(dev, DP_C); |
b01f2c3a | 7844 | } |
725e30ad | 7845 | } |
27185ae1 | 7846 | |
b01f2c3a JB |
7847 | if (SUPPORTS_INTEGRATED_DP(dev) && |
7848 | (I915_READ(DP_D) & DP_DETECTED)) { | |
7849 | DRM_DEBUG_KMS("probing DP_D\n"); | |
a4fc5ed6 | 7850 | intel_dp_init(dev, DP_D); |
b01f2c3a | 7851 | } |
bad720ff | 7852 | } else if (IS_GEN2(dev)) |
79e53945 JB |
7853 | intel_dvo_init(dev); |
7854 | ||
103a196f | 7855 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
7856 | intel_tv_init(dev); |
7857 | ||
4ef69c7a CW |
7858 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { |
7859 | encoder->base.possible_crtcs = encoder->crtc_mask; | |
7860 | encoder->base.possible_clones = | |
7861 | intel_encoder_clones(dev, encoder->clone_mask); | |
79e53945 | 7862 | } |
47356eb6 | 7863 | |
2c7111db CW |
7864 | /* disable all the possible outputs/crtcs before entering KMS mode */ |
7865 | drm_helper_disable_unused_functions(dev); | |
9fb526db KP |
7866 | |
7867 | if (HAS_PCH_SPLIT(dev)) | |
7868 | ironlake_init_pch_refclk(dev); | |
79e53945 JB |
7869 | } |
7870 | ||
7871 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
7872 | { | |
7873 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 JB |
7874 | |
7875 | drm_framebuffer_cleanup(fb); | |
05394f39 | 7876 | drm_gem_object_unreference_unlocked(&intel_fb->obj->base); |
79e53945 JB |
7877 | |
7878 | kfree(intel_fb); | |
7879 | } | |
7880 | ||
7881 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 7882 | struct drm_file *file, |
79e53945 JB |
7883 | unsigned int *handle) |
7884 | { | |
7885 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 7886 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 7887 | |
05394f39 | 7888 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
7889 | } |
7890 | ||
7891 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
7892 | .destroy = intel_user_framebuffer_destroy, | |
7893 | .create_handle = intel_user_framebuffer_create_handle, | |
7894 | }; | |
7895 | ||
38651674 DA |
7896 | int intel_framebuffer_init(struct drm_device *dev, |
7897 | struct intel_framebuffer *intel_fb, | |
308e5bcb | 7898 | struct drm_mode_fb_cmd2 *mode_cmd, |
05394f39 | 7899 | struct drm_i915_gem_object *obj) |
79e53945 | 7900 | { |
79e53945 JB |
7901 | int ret; |
7902 | ||
05394f39 | 7903 | if (obj->tiling_mode == I915_TILING_Y) |
57cd6508 CW |
7904 | return -EINVAL; |
7905 | ||
308e5bcb | 7906 | if (mode_cmd->pitches[0] & 63) |
57cd6508 CW |
7907 | return -EINVAL; |
7908 | ||
308e5bcb | 7909 | switch (mode_cmd->pixel_format) { |
04b3924d VS |
7910 | case DRM_FORMAT_RGB332: |
7911 | case DRM_FORMAT_RGB565: | |
7912 | case DRM_FORMAT_XRGB8888: | |
b250da79 | 7913 | case DRM_FORMAT_XBGR8888: |
04b3924d VS |
7914 | case DRM_FORMAT_ARGB8888: |
7915 | case DRM_FORMAT_XRGB2101010: | |
7916 | case DRM_FORMAT_ARGB2101010: | |
308e5bcb | 7917 | /* RGB formats are common across chipsets */ |
b5626747 | 7918 | break; |
04b3924d VS |
7919 | case DRM_FORMAT_YUYV: |
7920 | case DRM_FORMAT_UYVY: | |
7921 | case DRM_FORMAT_YVYU: | |
7922 | case DRM_FORMAT_VYUY: | |
57cd6508 CW |
7923 | break; |
7924 | default: | |
aca25848 ED |
7925 | DRM_DEBUG_KMS("unsupported pixel format %u\n", |
7926 | mode_cmd->pixel_format); | |
57cd6508 CW |
7927 | return -EINVAL; |
7928 | } | |
7929 | ||
79e53945 JB |
7930 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
7931 | if (ret) { | |
7932 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
7933 | return ret; | |
7934 | } | |
7935 | ||
7936 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); | |
79e53945 | 7937 | intel_fb->obj = obj; |
79e53945 JB |
7938 | return 0; |
7939 | } | |
7940 | ||
79e53945 JB |
7941 | static struct drm_framebuffer * |
7942 | intel_user_framebuffer_create(struct drm_device *dev, | |
7943 | struct drm_file *filp, | |
308e5bcb | 7944 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 7945 | { |
05394f39 | 7946 | struct drm_i915_gem_object *obj; |
79e53945 | 7947 | |
308e5bcb JB |
7948 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
7949 | mode_cmd->handles[0])); | |
c8725226 | 7950 | if (&obj->base == NULL) |
cce13ff7 | 7951 | return ERR_PTR(-ENOENT); |
79e53945 | 7952 | |
d2dff872 | 7953 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
7954 | } |
7955 | ||
79e53945 | 7956 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 7957 | .fb_create = intel_user_framebuffer_create, |
eb1f8e4f | 7958 | .output_poll_changed = intel_fb_output_poll_changed, |
79e53945 JB |
7959 | }; |
7960 | ||
05394f39 | 7961 | static struct drm_i915_gem_object * |
aa40d6bb | 7962 | intel_alloc_context_page(struct drm_device *dev) |
9ea8d059 | 7963 | { |
05394f39 | 7964 | struct drm_i915_gem_object *ctx; |
9ea8d059 CW |
7965 | int ret; |
7966 | ||
2c34b850 BW |
7967 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
7968 | ||
aa40d6bb ZN |
7969 | ctx = i915_gem_alloc_object(dev, 4096); |
7970 | if (!ctx) { | |
9ea8d059 CW |
7971 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
7972 | return NULL; | |
7973 | } | |
7974 | ||
75e9e915 | 7975 | ret = i915_gem_object_pin(ctx, 4096, true); |
9ea8d059 CW |
7976 | if (ret) { |
7977 | DRM_ERROR("failed to pin power context: %d\n", ret); | |
7978 | goto err_unref; | |
7979 | } | |
7980 | ||
aa40d6bb | 7981 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
9ea8d059 CW |
7982 | if (ret) { |
7983 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); | |
7984 | goto err_unpin; | |
7985 | } | |
9ea8d059 | 7986 | |
aa40d6bb | 7987 | return ctx; |
9ea8d059 CW |
7988 | |
7989 | err_unpin: | |
aa40d6bb | 7990 | i915_gem_object_unpin(ctx); |
9ea8d059 | 7991 | err_unref: |
05394f39 | 7992 | drm_gem_object_unreference(&ctx->base); |
9ea8d059 CW |
7993 | mutex_unlock(&dev->struct_mutex); |
7994 | return NULL; | |
7995 | } | |
7996 | ||
7648fa99 JB |
7997 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
7998 | { | |
7999 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8000 | u16 rgvswctl; | |
8001 | ||
8002 | rgvswctl = I915_READ16(MEMSWCTL); | |
8003 | if (rgvswctl & MEMCTL_CMD_STS) { | |
8004 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
8005 | return false; /* still busy with another command */ | |
8006 | } | |
8007 | ||
8008 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
8009 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
8010 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
8011 | POSTING_READ16(MEMSWCTL); | |
8012 | ||
8013 | rgvswctl |= MEMCTL_CMD_STS; | |
8014 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
8015 | ||
8016 | return true; | |
8017 | } | |
8018 | ||
f97108d1 JB |
8019 | void ironlake_enable_drps(struct drm_device *dev) |
8020 | { | |
8021 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 8022 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
f97108d1 | 8023 | u8 fmax, fmin, fstart, vstart; |
f97108d1 | 8024 | |
ea056c14 JB |
8025 | /* Enable temp reporting */ |
8026 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
8027 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
8028 | ||
f97108d1 JB |
8029 | /* 100ms RC evaluation intervals */ |
8030 | I915_WRITE(RCUPEI, 100000); | |
8031 | I915_WRITE(RCDNEI, 100000); | |
8032 | ||
8033 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
8034 | I915_WRITE(RCBMAXAVG, 90000); | |
8035 | I915_WRITE(RCBMINAVG, 80000); | |
8036 | ||
8037 | I915_WRITE(MEMIHYST, 1); | |
8038 | ||
8039 | /* Set up min, max, and cur for interrupt handling */ | |
8040 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
8041 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
8042 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
8043 | MEMMODE_FSTART_SHIFT; | |
7648fa99 | 8044 | |
f97108d1 JB |
8045 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
8046 | PXVFREQ_PX_SHIFT; | |
8047 | ||
80dbf4b7 | 8048 | dev_priv->fmax = fmax; /* IPS callback will increase this */ |
7648fa99 JB |
8049 | dev_priv->fstart = fstart; |
8050 | ||
80dbf4b7 | 8051 | dev_priv->max_delay = fstart; |
f97108d1 JB |
8052 | dev_priv->min_delay = fmin; |
8053 | dev_priv->cur_delay = fstart; | |
8054 | ||
80dbf4b7 JB |
8055 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
8056 | fmax, fmin, fstart); | |
7648fa99 | 8057 | |
f97108d1 JB |
8058 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
8059 | ||
8060 | /* | |
8061 | * Interrupts will be enabled in ironlake_irq_postinstall | |
8062 | */ | |
8063 | ||
8064 | I915_WRITE(VIDSTART, vstart); | |
8065 | POSTING_READ(VIDSTART); | |
8066 | ||
8067 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
8068 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
8069 | ||
481b6af3 | 8070 | if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
913d8d11 | 8071 | DRM_ERROR("stuck trying to change perf mode\n"); |
f97108d1 JB |
8072 | msleep(1); |
8073 | ||
7648fa99 | 8074 | ironlake_set_drps(dev, fstart); |
f97108d1 | 8075 | |
7648fa99 JB |
8076 | dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
8077 | I915_READ(0x112e0); | |
8078 | dev_priv->last_time1 = jiffies_to_msecs(jiffies); | |
8079 | dev_priv->last_count2 = I915_READ(0x112f4); | |
8080 | getrawmonotonic(&dev_priv->last_time2); | |
f97108d1 JB |
8081 | } |
8082 | ||
8083 | void ironlake_disable_drps(struct drm_device *dev) | |
8084 | { | |
8085 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7648fa99 | 8086 | u16 rgvswctl = I915_READ16(MEMSWCTL); |
f97108d1 JB |
8087 | |
8088 | /* Ack interrupts, disable EFC interrupt */ | |
8089 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
8090 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
8091 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
8092 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
8093 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
8094 | ||
8095 | /* Go back to the starting frequency */ | |
7648fa99 | 8096 | ironlake_set_drps(dev, dev_priv->fstart); |
f97108d1 JB |
8097 | msleep(1); |
8098 | rgvswctl |= MEMCTL_CMD_STS; | |
8099 | I915_WRITE(MEMSWCTL, rgvswctl); | |
8100 | msleep(1); | |
8101 | ||
8102 | } | |
8103 | ||
3b8d8d91 JB |
8104 | void gen6_set_rps(struct drm_device *dev, u8 val) |
8105 | { | |
8106 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8107 | u32 swreq; | |
8108 | ||
8109 | swreq = (val & 0x3ff) << 25; | |
8110 | I915_WRITE(GEN6_RPNSWREQ, swreq); | |
8111 | } | |
8112 | ||
8113 | void gen6_disable_rps(struct drm_device *dev) | |
8114 | { | |
8115 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8116 | ||
8117 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); | |
8118 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); | |
8119 | I915_WRITE(GEN6_PMIER, 0); | |
6fdd4d98 DV |
8120 | /* Complete PM interrupt masking here doesn't race with the rps work |
8121 | * item again unmasking PM interrupts because that is using a different | |
8122 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving | |
8123 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ | |
4912d041 BW |
8124 | |
8125 | spin_lock_irq(&dev_priv->rps_lock); | |
8126 | dev_priv->pm_iir = 0; | |
8127 | spin_unlock_irq(&dev_priv->rps_lock); | |
8128 | ||
3b8d8d91 JB |
8129 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); |
8130 | } | |
8131 | ||
7648fa99 JB |
8132 | static unsigned long intel_pxfreq(u32 vidfreq) |
8133 | { | |
8134 | unsigned long freq; | |
8135 | int div = (vidfreq & 0x3f0000) >> 16; | |
8136 | int post = (vidfreq & 0x3000) >> 12; | |
8137 | int pre = (vidfreq & 0x7); | |
8138 | ||
8139 | if (!pre) | |
8140 | return 0; | |
8141 | ||
8142 | freq = ((div * 133333) / ((1<<post) * pre)); | |
8143 | ||
8144 | return freq; | |
8145 | } | |
8146 | ||
8147 | void intel_init_emon(struct drm_device *dev) | |
8148 | { | |
8149 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8150 | u32 lcfuse; | |
8151 | u8 pxw[16]; | |
8152 | int i; | |
8153 | ||
8154 | /* Disable to program */ | |
8155 | I915_WRITE(ECR, 0); | |
8156 | POSTING_READ(ECR); | |
8157 | ||
8158 | /* Program energy weights for various events */ | |
8159 | I915_WRITE(SDEW, 0x15040d00); | |
8160 | I915_WRITE(CSIEW0, 0x007f0000); | |
8161 | I915_WRITE(CSIEW1, 0x1e220004); | |
8162 | I915_WRITE(CSIEW2, 0x04000004); | |
8163 | ||
8164 | for (i = 0; i < 5; i++) | |
8165 | I915_WRITE(PEW + (i * 4), 0); | |
8166 | for (i = 0; i < 3; i++) | |
8167 | I915_WRITE(DEW + (i * 4), 0); | |
8168 | ||
8169 | /* Program P-state weights to account for frequency power adjustment */ | |
8170 | for (i = 0; i < 16; i++) { | |
8171 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
8172 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
8173 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
8174 | PXVFREQ_PX_SHIFT; | |
8175 | unsigned long val; | |
8176 | ||
8177 | val = vid * vid; | |
8178 | val *= (freq / 1000); | |
8179 | val *= 255; | |
8180 | val /= (127*127*900); | |
8181 | if (val > 0xff) | |
8182 | DRM_ERROR("bad pxval: %ld\n", val); | |
8183 | pxw[i] = val; | |
8184 | } | |
8185 | /* Render standby states get 0 weight */ | |
8186 | pxw[14] = 0; | |
8187 | pxw[15] = 0; | |
8188 | ||
8189 | for (i = 0; i < 4; i++) { | |
8190 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
8191 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
8192 | I915_WRITE(PXW + (i * 4), val); | |
8193 | } | |
8194 | ||
8195 | /* Adjust magic regs to magic values (more experimental results) */ | |
8196 | I915_WRITE(OGW0, 0); | |
8197 | I915_WRITE(OGW1, 0); | |
8198 | I915_WRITE(EG0, 0x00007f00); | |
8199 | I915_WRITE(EG1, 0x0000000e); | |
8200 | I915_WRITE(EG2, 0x000e0000); | |
8201 | I915_WRITE(EG3, 0x68000300); | |
8202 | I915_WRITE(EG4, 0x42000000); | |
8203 | I915_WRITE(EG5, 0x00140031); | |
8204 | I915_WRITE(EG6, 0); | |
8205 | I915_WRITE(EG7, 0); | |
8206 | ||
8207 | for (i = 0; i < 8; i++) | |
8208 | I915_WRITE(PXWL + (i * 4), 0); | |
8209 | ||
8210 | /* Enable PMON + select events */ | |
8211 | I915_WRITE(ECR, 0x80000019); | |
8212 | ||
8213 | lcfuse = I915_READ(LCFUSE02); | |
8214 | ||
8215 | dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); | |
8216 | } | |
8217 | ||
c0f372b3 KP |
8218 | static bool intel_enable_rc6(struct drm_device *dev) |
8219 | { | |
8220 | /* | |
8221 | * Respect the kernel parameter if it is set | |
8222 | */ | |
8223 | if (i915_enable_rc6 >= 0) | |
8224 | return i915_enable_rc6; | |
8225 | ||
8226 | /* | |
8227 | * Disable RC6 on Ironlake | |
8228 | */ | |
8229 | if (INTEL_INFO(dev)->gen == 5) | |
8230 | return 0; | |
8231 | ||
8232 | /* | |
371de6e4 | 8233 | * Disable rc6 on Sandybridge |
c0f372b3 KP |
8234 | */ |
8235 | if (INTEL_INFO(dev)->gen == 6) { | |
371de6e4 KP |
8236 | DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n"); |
8237 | return 0; | |
c0f372b3 KP |
8238 | } |
8239 | DRM_DEBUG_DRIVER("RC6 enabled\n"); | |
8240 | return 1; | |
8241 | } | |
8242 | ||
3b8d8d91 | 8243 | void gen6_enable_rps(struct drm_i915_private *dev_priv) |
8fd26859 | 8244 | { |
a6044e23 JB |
8245 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
8246 | u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
7df8721b | 8247 | u32 pcu_mbox, rc6_mask = 0; |
dd202c6d | 8248 | u32 gtfifodbg; |
a6044e23 | 8249 | int cur_freq, min_freq, max_freq; |
8fd26859 CW |
8250 | int i; |
8251 | ||
8252 | /* Here begins a magic sequence of register writes to enable | |
8253 | * auto-downclocking. | |
8254 | * | |
8255 | * Perhaps there might be some value in exposing these to | |
8256 | * userspace... | |
8257 | */ | |
8258 | I915_WRITE(GEN6_RC_STATE, 0); | |
d1ebd816 | 8259 | mutex_lock(&dev_priv->dev->struct_mutex); |
dd202c6d BW |
8260 | |
8261 | /* Clear the DBG now so we don't confuse earlier errors */ | |
8262 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { | |
8263 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); | |
8264 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
8265 | } | |
8266 | ||
fcca7926 | 8267 | gen6_gt_force_wake_get(dev_priv); |
8fd26859 | 8268 | |
3b8d8d91 | 8269 | /* disable the counters and set deterministic thresholds */ |
8fd26859 CW |
8270 | I915_WRITE(GEN6_RC_CONTROL, 0); |
8271 | ||
8272 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
8273 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
8274 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
8275 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
8276 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
8277 | ||
8278 | for (i = 0; i < I915_NUM_RINGS; i++) | |
8279 | I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10); | |
8280 | ||
8281 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
8282 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
8283 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
8284 | I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); | |
8285 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ | |
8286 | ||
c0f372b3 | 8287 | if (intel_enable_rc6(dev_priv->dev)) |
1c8ecf80 | 8288 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE | |
c0e2ee1b | 8289 | ((IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0); |
7df8721b | 8290 | |
8fd26859 | 8291 | I915_WRITE(GEN6_RC_CONTROL, |
7df8721b | 8292 | rc6_mask | |
9c3d2f7f | 8293 | GEN6_RC_CTL_EI_MODE(1) | |
8fd26859 CW |
8294 | GEN6_RC_CTL_HW_ENABLE); |
8295 | ||
3b8d8d91 | 8296 | I915_WRITE(GEN6_RPNSWREQ, |
8fd26859 CW |
8297 | GEN6_FREQUENCY(10) | |
8298 | GEN6_OFFSET(0) | | |
8299 | GEN6_AGGRESSIVE_TURBO); | |
8300 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
8301 | GEN6_FREQUENCY(12)); | |
8302 | ||
8303 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); | |
8304 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
8305 | 18 << 24 | | |
8306 | 6 << 16); | |
ccab5c82 JB |
8307 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000); |
8308 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000); | |
8fd26859 | 8309 | I915_WRITE(GEN6_RP_UP_EI, 100000); |
ccab5c82 | 8310 | I915_WRITE(GEN6_RP_DOWN_EI, 5000000); |
8fd26859 CW |
8311 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
8312 | I915_WRITE(GEN6_RP_CONTROL, | |
8313 | GEN6_RP_MEDIA_TURBO | | |
6ed55ee7 | 8314 | GEN6_RP_MEDIA_HW_MODE | |
8fd26859 CW |
8315 | GEN6_RP_MEDIA_IS_GFX | |
8316 | GEN6_RP_ENABLE | | |
ccab5c82 JB |
8317 | GEN6_RP_UP_BUSY_AVG | |
8318 | GEN6_RP_DOWN_IDLE_CONT); | |
8fd26859 CW |
8319 | |
8320 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
8321 | 500)) | |
8322 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); | |
8323 | ||
8324 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
8325 | I915_WRITE(GEN6_PCODE_MAILBOX, | |
8326 | GEN6_PCODE_READY | | |
8327 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); | |
8328 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
8329 | 500)) | |
8330 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); | |
8331 | ||
a6044e23 JB |
8332 | min_freq = (rp_state_cap & 0xff0000) >> 16; |
8333 | max_freq = rp_state_cap & 0xff; | |
8334 | cur_freq = (gt_perf_status & 0xff00) >> 8; | |
8335 | ||
8336 | /* Check for overclock support */ | |
8337 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
8338 | 500)) | |
8339 | DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); | |
8340 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS); | |
8341 | pcu_mbox = I915_READ(GEN6_PCODE_DATA); | |
8342 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
8343 | 500)) | |
8344 | DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); | |
8345 | if (pcu_mbox & (1<<31)) { /* OC supported */ | |
8346 | max_freq = pcu_mbox & 0xff; | |
e281fcaa | 8347 | DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50); |
a6044e23 JB |
8348 | } |
8349 | ||
8350 | /* In units of 100MHz */ | |
8351 | dev_priv->max_delay = max_freq; | |
8352 | dev_priv->min_delay = min_freq; | |
8353 | dev_priv->cur_delay = cur_freq; | |
8354 | ||
8fd26859 CW |
8355 | /* requires MSI enabled */ |
8356 | I915_WRITE(GEN6_PMIER, | |
8357 | GEN6_PM_MBOX_EVENT | | |
8358 | GEN6_PM_THERMAL_EVENT | | |
8359 | GEN6_PM_RP_DOWN_TIMEOUT | | |
8360 | GEN6_PM_RP_UP_THRESHOLD | | |
8361 | GEN6_PM_RP_DOWN_THRESHOLD | | |
8362 | GEN6_PM_RP_UP_EI_EXPIRED | | |
8363 | GEN6_PM_RP_DOWN_EI_EXPIRED); | |
4912d041 BW |
8364 | spin_lock_irq(&dev_priv->rps_lock); |
8365 | WARN_ON(dev_priv->pm_iir != 0); | |
3b8d8d91 | 8366 | I915_WRITE(GEN6_PMIMR, 0); |
4912d041 | 8367 | spin_unlock_irq(&dev_priv->rps_lock); |
3b8d8d91 JB |
8368 | /* enable all PM interrupts */ |
8369 | I915_WRITE(GEN6_PMINTRMSK, 0); | |
8fd26859 | 8370 | |
fcca7926 | 8371 | gen6_gt_force_wake_put(dev_priv); |
d1ebd816 | 8372 | mutex_unlock(&dev_priv->dev->struct_mutex); |
8fd26859 CW |
8373 | } |
8374 | ||
23b2f8bb JB |
8375 | void gen6_update_ring_freq(struct drm_i915_private *dev_priv) |
8376 | { | |
8377 | int min_freq = 15; | |
8378 | int gpu_freq, ia_freq, max_ia_freq; | |
8379 | int scaling_factor = 180; | |
8380 | ||
8381 | max_ia_freq = cpufreq_quick_get_max(0); | |
8382 | /* | |
8383 | * Default to measured freq if none found, PCU will ensure we don't go | |
8384 | * over | |
8385 | */ | |
8386 | if (!max_ia_freq) | |
8387 | max_ia_freq = tsc_khz; | |
8388 | ||
8389 | /* Convert from kHz to MHz */ | |
8390 | max_ia_freq /= 1000; | |
8391 | ||
8392 | mutex_lock(&dev_priv->dev->struct_mutex); | |
8393 | ||
8394 | /* | |
8395 | * For each potential GPU frequency, load a ring frequency we'd like | |
8396 | * to use for memory access. We do this by specifying the IA frequency | |
8397 | * the PCU should use as a reference to determine the ring frequency. | |
8398 | */ | |
8399 | for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay; | |
8400 | gpu_freq--) { | |
8401 | int diff = dev_priv->max_delay - gpu_freq; | |
8402 | ||
8403 | /* | |
8404 | * For GPU frequencies less than 750MHz, just use the lowest | |
8405 | * ring freq. | |
8406 | */ | |
8407 | if (gpu_freq < min_freq) | |
8408 | ia_freq = 800; | |
8409 | else | |
8410 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
8411 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
8412 | ||
8413 | I915_WRITE(GEN6_PCODE_DATA, | |
8414 | (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) | | |
8415 | gpu_freq); | |
8416 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | | |
8417 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE); | |
8418 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & | |
8419 | GEN6_PCODE_READY) == 0, 10)) { | |
8420 | DRM_ERROR("pcode write of freq table timed out\n"); | |
8421 | continue; | |
8422 | } | |
8423 | } | |
8424 | ||
8425 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
8426 | } | |
8427 | ||
6067aaea JB |
8428 | static void ironlake_init_clock_gating(struct drm_device *dev) |
8429 | { | |
8430 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8431 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; | |
8432 | ||
8433 | /* Required for FBC */ | |
8434 | dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE | | |
8435 | DPFCRUNIT_CLOCK_GATE_DISABLE | | |
8436 | DPFDUNIT_CLOCK_GATE_DISABLE; | |
8437 | /* Required for CxSR */ | |
8438 | dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE; | |
8439 | ||
8440 | I915_WRITE(PCH_3DCGDIS0, | |
8441 | MARIUNIT_CLOCK_GATE_DISABLE | | |
8442 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
8443 | I915_WRITE(PCH_3DCGDIS1, | |
8444 | VFMUNIT_CLOCK_GATE_DISABLE); | |
8445 | ||
8446 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | |
8447 | ||
6067aaea JB |
8448 | /* |
8449 | * According to the spec the following bits should be set in | |
8450 | * order to enable memory self-refresh | |
8451 | * The bit 22/21 of 0x42004 | |
8452 | * The bit 5 of 0x42020 | |
8453 | * The bit 15 of 0x45000 | |
8454 | */ | |
8455 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8456 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8457 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
8458 | I915_WRITE(ILK_DSPCLK_GATE, | |
8459 | (I915_READ(ILK_DSPCLK_GATE) | | |
8460 | ILK_DPARB_CLK_GATE)); | |
8461 | I915_WRITE(DISP_ARB_CTL, | |
8462 | (I915_READ(DISP_ARB_CTL) | | |
8463 | DISP_FBC_WM_DIS)); | |
8464 | I915_WRITE(WM3_LP_ILK, 0); | |
8465 | I915_WRITE(WM2_LP_ILK, 0); | |
8466 | I915_WRITE(WM1_LP_ILK, 0); | |
8467 | ||
8468 | /* | |
8469 | * Based on the document from hardware guys the following bits | |
8470 | * should be set unconditionally in order to enable FBC. | |
8471 | * The bit 22 of 0x42000 | |
8472 | * The bit 22 of 0x42004 | |
8473 | * The bit 7,8,9 of 0x42020. | |
8474 | */ | |
8475 | if (IS_IRONLAKE_M(dev)) { | |
8476 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
8477 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
8478 | ILK_FBCQ_DIS); | |
8479 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8480 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8481 | ILK_DPARB_GATE); | |
8482 | I915_WRITE(ILK_DSPCLK_GATE, | |
8483 | I915_READ(ILK_DSPCLK_GATE) | | |
8484 | ILK_DPFC_DIS1 | | |
8485 | ILK_DPFC_DIS2 | | |
8486 | ILK_CLK_FBC); | |
8487 | } | |
8488 | ||
8489 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8490 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8491 | ILK_ELPIN_409_SELECT); | |
8492 | I915_WRITE(_3D_CHICKEN2, | |
8493 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
8494 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
8fd26859 CW |
8495 | } |
8496 | ||
6067aaea | 8497 | static void gen6_init_clock_gating(struct drm_device *dev) |
652c393a JB |
8498 | { |
8499 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9db4a9c7 | 8500 | int pipe; |
6067aaea JB |
8501 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; |
8502 | ||
8503 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); | |
652c393a | 8504 | |
6067aaea JB |
8505 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
8506 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8507 | ILK_ELPIN_409_SELECT); | |
8956c8bb | 8508 | |
6067aaea JB |
8509 | I915_WRITE(WM3_LP_ILK, 0); |
8510 | I915_WRITE(WM2_LP_ILK, 0); | |
8511 | I915_WRITE(WM1_LP_ILK, 0); | |
652c393a | 8512 | |
406478dc EA |
8513 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
8514 | * gating disable must be set. Failure to set it results in | |
8515 | * flickering pixels due to Z write ordering failures after | |
8516 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
8517 | * Sanctuary and Tropics, and apparently anything else with | |
8518 | * alpha test or pixel discard. | |
9ca1d10d EA |
8519 | * |
8520 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
8521 | * but we didn't debug actual testcases to find it out. | |
406478dc | 8522 | */ |
9ca1d10d EA |
8523 | I915_WRITE(GEN6_UCGCTL2, |
8524 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | | |
8525 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
406478dc | 8526 | |
652c393a | 8527 | /* |
6067aaea JB |
8528 | * According to the spec the following bits should be |
8529 | * set in order to enable memory self-refresh and fbc: | |
8530 | * The bit21 and bit22 of 0x42000 | |
8531 | * The bit21 and bit22 of 0x42004 | |
8532 | * The bit5 and bit7 of 0x42020 | |
8533 | * The bit14 of 0x70180 | |
8534 | * The bit14 of 0x71180 | |
652c393a | 8535 | */ |
6067aaea JB |
8536 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
8537 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
8538 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
8539 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8540 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8541 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
8542 | I915_WRITE(ILK_DSPCLK_GATE, | |
8543 | I915_READ(ILK_DSPCLK_GATE) | | |
8544 | ILK_DPARB_CLK_GATE | | |
8545 | ILK_DPFD_CLK_GATE); | |
8956c8bb | 8546 | |
d74362c9 | 8547 | for_each_pipe(pipe) { |
6067aaea JB |
8548 | I915_WRITE(DSPCNTR(pipe), |
8549 | I915_READ(DSPCNTR(pipe)) | | |
8550 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
d74362c9 KP |
8551 | intel_flush_display_plane(dev_priv, pipe); |
8552 | } | |
6067aaea | 8553 | } |
8956c8bb | 8554 | |
28963a3e JB |
8555 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
8556 | { | |
8557 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8558 | int pipe; | |
8559 | uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; | |
7f8a8569 | 8560 | |
28963a3e | 8561 | I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate); |
382b0936 | 8562 | |
28963a3e JB |
8563 | I915_WRITE(WM3_LP_ILK, 0); |
8564 | I915_WRITE(WM2_LP_ILK, 0); | |
8565 | I915_WRITE(WM1_LP_ILK, 0); | |
de6e2eaf | 8566 | |
eae66b50 ED |
8567 | /* According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
8568 | * This implements the WaDisableRCZUnitClockGating workaround. | |
8569 | */ | |
8570 | I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); | |
8571 | ||
28963a3e | 8572 | I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); |
67e92af0 | 8573 | |
116ac8d2 EA |
8574 | I915_WRITE(IVB_CHICKEN3, |
8575 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
8576 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
8577 | ||
d71de14d KG |
8578 | /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ |
8579 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, | |
8580 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); | |
8581 | ||
e4e0c058 ED |
8582 | /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ |
8583 | I915_WRITE(GEN7_L3CNTLREG1, | |
8584 | GEN7_WA_FOR_GEN7_L3_CONTROL); | |
8585 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, | |
8586 | GEN7_WA_L3_CHICKEN_MODE); | |
8587 | ||
db099c8f ED |
8588 | /* This is required by WaCatErrorRejectionIssue */ |
8589 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, | |
8590 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
8591 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
8592 | ||
d74362c9 | 8593 | for_each_pipe(pipe) { |
28963a3e JB |
8594 | I915_WRITE(DSPCNTR(pipe), |
8595 | I915_READ(DSPCNTR(pipe)) | | |
8596 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
d74362c9 KP |
8597 | intel_flush_display_plane(dev_priv, pipe); |
8598 | } | |
28963a3e JB |
8599 | } |
8600 | ||
6067aaea JB |
8601 | static void g4x_init_clock_gating(struct drm_device *dev) |
8602 | { | |
8603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8604 | uint32_t dspclk_gate; | |
8fd26859 | 8605 | |
6067aaea JB |
8606 | I915_WRITE(RENCLK_GATE_D1, 0); |
8607 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
8608 | GS_UNIT_CLOCK_GATE_DISABLE | | |
8609 | CL_UNIT_CLOCK_GATE_DISABLE); | |
8610 | I915_WRITE(RAMCLK_GATE_D, 0); | |
8611 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
8612 | OVRUNIT_CLOCK_GATE_DISABLE | | |
8613 | OVCUNIT_CLOCK_GATE_DISABLE; | |
8614 | if (IS_GM45(dev)) | |
8615 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
8616 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
8617 | } | |
1398261a | 8618 | |
6067aaea JB |
8619 | static void crestline_init_clock_gating(struct drm_device *dev) |
8620 | { | |
8621 | struct drm_i915_private *dev_priv = dev->dev_private; | |
652c393a | 8622 | |
6067aaea JB |
8623 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
8624 | I915_WRITE(RENCLK_GATE_D2, 0); | |
8625 | I915_WRITE(DSPCLK_GATE_D, 0); | |
8626 | I915_WRITE(RAMCLK_GATE_D, 0); | |
8627 | I915_WRITE16(DEUC, 0); | |
8628 | } | |
652c393a | 8629 | |
6067aaea JB |
8630 | static void broadwater_init_clock_gating(struct drm_device *dev) |
8631 | { | |
8632 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8633 | ||
8634 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | | |
8635 | I965_RCC_CLOCK_GATE_DISABLE | | |
8636 | I965_RCPB_CLOCK_GATE_DISABLE | | |
8637 | I965_ISC_CLOCK_GATE_DISABLE | | |
8638 | I965_FBC_CLOCK_GATE_DISABLE); | |
8639 | I915_WRITE(RENCLK_GATE_D2, 0); | |
8640 | } | |
8641 | ||
8642 | static void gen3_init_clock_gating(struct drm_device *dev) | |
8643 | { | |
8644 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8645 | u32 dstate = I915_READ(D_STATE); | |
8646 | ||
8647 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
8648 | DSTATE_DOT_CLOCK_GATING; | |
8649 | I915_WRITE(D_STATE, dstate); | |
8650 | } | |
8651 | ||
8652 | static void i85x_init_clock_gating(struct drm_device *dev) | |
8653 | { | |
8654 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8655 | ||
8656 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); | |
8657 | } | |
8658 | ||
8659 | static void i830_init_clock_gating(struct drm_device *dev) | |
8660 | { | |
8661 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8662 | ||
8663 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
652c393a JB |
8664 | } |
8665 | ||
645c62a5 JB |
8666 | static void ibx_init_clock_gating(struct drm_device *dev) |
8667 | { | |
8668 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8669 | ||
8670 | /* | |
8671 | * On Ibex Peak and Cougar Point, we need to disable clock | |
8672 | * gating for the panel power sequencer or it will fail to | |
8673 | * start up when no ports are active. | |
8674 | */ | |
8675 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
8676 | } | |
8677 | ||
8678 | static void cpt_init_clock_gating(struct drm_device *dev) | |
8679 | { | |
8680 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3bcf603f | 8681 | int pipe; |
645c62a5 JB |
8682 | |
8683 | /* | |
8684 | * On Ibex Peak and Cougar Point, we need to disable clock | |
8685 | * gating for the panel power sequencer or it will fail to | |
8686 | * start up when no ports are active. | |
8687 | */ | |
8688 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
8689 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | | |
8690 | DPLS_EDP_PPS_FIX_DIS); | |
3bcf603f JB |
8691 | /* Without this, mode sets may fail silently on FDI */ |
8692 | for_each_pipe(pipe) | |
8693 | I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS); | |
652c393a JB |
8694 | } |
8695 | ||
ac668088 | 8696 | static void ironlake_teardown_rc6(struct drm_device *dev) |
0cdab21f CW |
8697 | { |
8698 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8699 | ||
8700 | if (dev_priv->renderctx) { | |
ac668088 CW |
8701 | i915_gem_object_unpin(dev_priv->renderctx); |
8702 | drm_gem_object_unreference(&dev_priv->renderctx->base); | |
0cdab21f CW |
8703 | dev_priv->renderctx = NULL; |
8704 | } | |
8705 | ||
8706 | if (dev_priv->pwrctx) { | |
ac668088 CW |
8707 | i915_gem_object_unpin(dev_priv->pwrctx); |
8708 | drm_gem_object_unreference(&dev_priv->pwrctx->base); | |
8709 | dev_priv->pwrctx = NULL; | |
8710 | } | |
8711 | } | |
8712 | ||
8713 | static void ironlake_disable_rc6(struct drm_device *dev) | |
8714 | { | |
8715 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8716 | ||
8717 | if (I915_READ(PWRCTXA)) { | |
8718 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ | |
8719 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); | |
8720 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), | |
8721 | 50); | |
0cdab21f CW |
8722 | |
8723 | I915_WRITE(PWRCTXA, 0); | |
8724 | POSTING_READ(PWRCTXA); | |
8725 | ||
ac668088 CW |
8726 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
8727 | POSTING_READ(RSTDBYCTL); | |
0cdab21f | 8728 | } |
ac668088 | 8729 | |
99507307 | 8730 | ironlake_teardown_rc6(dev); |
0cdab21f CW |
8731 | } |
8732 | ||
ac668088 | 8733 | static int ironlake_setup_rc6(struct drm_device *dev) |
d5bb081b JB |
8734 | { |
8735 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8736 | ||
ac668088 CW |
8737 | if (dev_priv->renderctx == NULL) |
8738 | dev_priv->renderctx = intel_alloc_context_page(dev); | |
8739 | if (!dev_priv->renderctx) | |
8740 | return -ENOMEM; | |
8741 | ||
8742 | if (dev_priv->pwrctx == NULL) | |
8743 | dev_priv->pwrctx = intel_alloc_context_page(dev); | |
8744 | if (!dev_priv->pwrctx) { | |
8745 | ironlake_teardown_rc6(dev); | |
8746 | return -ENOMEM; | |
8747 | } | |
8748 | ||
8749 | return 0; | |
d5bb081b JB |
8750 | } |
8751 | ||
8752 | void ironlake_enable_rc6(struct drm_device *dev) | |
8753 | { | |
8754 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8755 | int ret; | |
8756 | ||
ac668088 CW |
8757 | /* rc6 disabled by default due to repeated reports of hanging during |
8758 | * boot and resume. | |
8759 | */ | |
c0f372b3 | 8760 | if (!intel_enable_rc6(dev)) |
ac668088 CW |
8761 | return; |
8762 | ||
2c34b850 | 8763 | mutex_lock(&dev->struct_mutex); |
ac668088 | 8764 | ret = ironlake_setup_rc6(dev); |
2c34b850 BW |
8765 | if (ret) { |
8766 | mutex_unlock(&dev->struct_mutex); | |
ac668088 | 8767 | return; |
2c34b850 | 8768 | } |
ac668088 | 8769 | |
d5bb081b JB |
8770 | /* |
8771 | * GPU can automatically power down the render unit if given a page | |
8772 | * to save state. | |
8773 | */ | |
8774 | ret = BEGIN_LP_RING(6); | |
8775 | if (ret) { | |
ac668088 | 8776 | ironlake_teardown_rc6(dev); |
2c34b850 | 8777 | mutex_unlock(&dev->struct_mutex); |
d5bb081b JB |
8778 | return; |
8779 | } | |
ac668088 | 8780 | |
d5bb081b JB |
8781 | OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
8782 | OUT_RING(MI_SET_CONTEXT); | |
8783 | OUT_RING(dev_priv->renderctx->gtt_offset | | |
8784 | MI_MM_SPACE_GTT | | |
8785 | MI_SAVE_EXT_STATE_EN | | |
8786 | MI_RESTORE_EXT_STATE_EN | | |
8787 | MI_RESTORE_INHIBIT); | |
8788 | OUT_RING(MI_SUSPEND_FLUSH); | |
8789 | OUT_RING(MI_NOOP); | |
8790 | OUT_RING(MI_FLUSH); | |
8791 | ADVANCE_LP_RING(); | |
8792 | ||
4a246cfc BW |
8793 | /* |
8794 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW | |
8795 | * does an implicit flush, combined with MI_FLUSH above, it should be | |
8796 | * safe to assume that renderctx is valid | |
8797 | */ | |
8798 | ret = intel_wait_ring_idle(LP_RING(dev_priv)); | |
8799 | if (ret) { | |
8800 | DRM_ERROR("failed to enable ironlake power power savings\n"); | |
8801 | ironlake_teardown_rc6(dev); | |
8802 | mutex_unlock(&dev->struct_mutex); | |
8803 | return; | |
8804 | } | |
8805 | ||
d5bb081b JB |
8806 | I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); |
8807 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | |
2c34b850 | 8808 | mutex_unlock(&dev->struct_mutex); |
d5bb081b JB |
8809 | } |
8810 | ||
645c62a5 JB |
8811 | void intel_init_clock_gating(struct drm_device *dev) |
8812 | { | |
8813 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8814 | ||
8815 | dev_priv->display.init_clock_gating(dev); | |
8816 | ||
8817 | if (dev_priv->display.init_pch_clock_gating) | |
8818 | dev_priv->display.init_pch_clock_gating(dev); | |
8819 | } | |
ac668088 | 8820 | |
e70236a8 JB |
8821 | /* Set up chip specific display functions */ |
8822 | static void intel_init_display(struct drm_device *dev) | |
8823 | { | |
8824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8825 | ||
8826 | /* We always want a DPMS function */ | |
f564048e | 8827 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 8828 | dev_priv->display.dpms = ironlake_crtc_dpms; |
f564048e | 8829 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
17638cd6 | 8830 | dev_priv->display.update_plane = ironlake_update_plane; |
f564048e | 8831 | } else { |
e70236a8 | 8832 | dev_priv->display.dpms = i9xx_crtc_dpms; |
f564048e | 8833 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
17638cd6 | 8834 | dev_priv->display.update_plane = i9xx_update_plane; |
f564048e | 8835 | } |
e70236a8 | 8836 | |
ee5382ae | 8837 | if (I915_HAS_FBC(dev)) { |
9c04f015 | 8838 | if (HAS_PCH_SPLIT(dev)) { |
b52eb4dc ZY |
8839 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
8840 | dev_priv->display.enable_fbc = ironlake_enable_fbc; | |
8841 | dev_priv->display.disable_fbc = ironlake_disable_fbc; | |
8842 | } else if (IS_GM45(dev)) { | |
74dff282 JB |
8843 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
8844 | dev_priv->display.enable_fbc = g4x_enable_fbc; | |
8845 | dev_priv->display.disable_fbc = g4x_disable_fbc; | |
a6c45cf0 | 8846 | } else if (IS_CRESTLINE(dev)) { |
e70236a8 JB |
8847 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
8848 | dev_priv->display.enable_fbc = i8xx_enable_fbc; | |
8849 | dev_priv->display.disable_fbc = i8xx_disable_fbc; | |
8850 | } | |
74dff282 | 8851 | /* 855GM needs testing */ |
e70236a8 JB |
8852 | } |
8853 | ||
8854 | /* Returns the core display clock speed */ | |
0206e353 | 8855 | if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) |
e70236a8 JB |
8856 | dev_priv->display.get_display_clock_speed = |
8857 | i945_get_display_clock_speed; | |
8858 | else if (IS_I915G(dev)) | |
8859 | dev_priv->display.get_display_clock_speed = | |
8860 | i915_get_display_clock_speed; | |
f2b115e6 | 8861 | else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) |
e70236a8 JB |
8862 | dev_priv->display.get_display_clock_speed = |
8863 | i9xx_misc_get_display_clock_speed; | |
8864 | else if (IS_I915GM(dev)) | |
8865 | dev_priv->display.get_display_clock_speed = | |
8866 | i915gm_get_display_clock_speed; | |
8867 | else if (IS_I865G(dev)) | |
8868 | dev_priv->display.get_display_clock_speed = | |
8869 | i865_get_display_clock_speed; | |
f0f8a9ce | 8870 | else if (IS_I85X(dev)) |
e70236a8 JB |
8871 | dev_priv->display.get_display_clock_speed = |
8872 | i855_get_display_clock_speed; | |
8873 | else /* 852, 830 */ | |
8874 | dev_priv->display.get_display_clock_speed = | |
8875 | i830_get_display_clock_speed; | |
8876 | ||
8877 | /* For FIFO watermark updates */ | |
7f8a8569 | 8878 | if (HAS_PCH_SPLIT(dev)) { |
8d715f00 KP |
8879 | dev_priv->display.force_wake_get = __gen6_gt_force_wake_get; |
8880 | dev_priv->display.force_wake_put = __gen6_gt_force_wake_put; | |
8881 | ||
8882 | /* IVB configs may use multi-threaded forcewake */ | |
8883 | if (IS_IVYBRIDGE(dev)) { | |
8884 | u32 ecobus; | |
8885 | ||
c7dffff7 KP |
8886 | /* A small trick here - if the bios hasn't configured MT forcewake, |
8887 | * and if the device is in RC6, then force_wake_mt_get will not wake | |
8888 | * the device and the ECOBUS read will return zero. Which will be | |
8889 | * (correctly) interpreted by the test below as MT forcewake being | |
8890 | * disabled. | |
8891 | */ | |
8d715f00 KP |
8892 | mutex_lock(&dev->struct_mutex); |
8893 | __gen6_gt_force_wake_mt_get(dev_priv); | |
c7dffff7 | 8894 | ecobus = I915_READ_NOTRACE(ECOBUS); |
8d715f00 KP |
8895 | __gen6_gt_force_wake_mt_put(dev_priv); |
8896 | mutex_unlock(&dev->struct_mutex); | |
8897 | ||
8898 | if (ecobus & FORCEWAKE_MT_ENABLE) { | |
8899 | DRM_DEBUG_KMS("Using MT version of forcewake\n"); | |
8900 | dev_priv->display.force_wake_get = | |
8901 | __gen6_gt_force_wake_mt_get; | |
8902 | dev_priv->display.force_wake_put = | |
8903 | __gen6_gt_force_wake_mt_put; | |
8904 | } | |
8905 | } | |
8906 | ||
645c62a5 JB |
8907 | if (HAS_PCH_IBX(dev)) |
8908 | dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating; | |
8909 | else if (HAS_PCH_CPT(dev)) | |
8910 | dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating; | |
8911 | ||
f00a3ddf | 8912 | if (IS_GEN5(dev)) { |
7f8a8569 ZW |
8913 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) |
8914 | dev_priv->display.update_wm = ironlake_update_wm; | |
8915 | else { | |
8916 | DRM_DEBUG_KMS("Failed to get proper latency. " | |
8917 | "Disable CxSR\n"); | |
8918 | dev_priv->display.update_wm = NULL; | |
1398261a | 8919 | } |
674cf967 | 8920 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
6067aaea | 8921 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
e0dac65e | 8922 | dev_priv->display.write_eld = ironlake_write_eld; |
1398261a YL |
8923 | } else if (IS_GEN6(dev)) { |
8924 | if (SNB_READ_WM0_LATENCY()) { | |
8925 | dev_priv->display.update_wm = sandybridge_update_wm; | |
b840d907 | 8926 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
1398261a YL |
8927 | } else { |
8928 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
8929 | "Disable CxSR\n"); | |
8930 | dev_priv->display.update_wm = NULL; | |
7f8a8569 | 8931 | } |
674cf967 | 8932 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
6067aaea | 8933 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
e0dac65e | 8934 | dev_priv->display.write_eld = ironlake_write_eld; |
357555c0 JB |
8935 | } else if (IS_IVYBRIDGE(dev)) { |
8936 | /* FIXME: detect B0+ stepping and use auto training */ | |
8937 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
fe100d4d JB |
8938 | if (SNB_READ_WM0_LATENCY()) { |
8939 | dev_priv->display.update_wm = sandybridge_update_wm; | |
b840d907 | 8940 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
fe100d4d JB |
8941 | } else { |
8942 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
8943 | "Disable CxSR\n"); | |
8944 | dev_priv->display.update_wm = NULL; | |
8945 | } | |
28963a3e | 8946 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
e0dac65e | 8947 | dev_priv->display.write_eld = ironlake_write_eld; |
7f8a8569 ZW |
8948 | } else |
8949 | dev_priv->display.update_wm = NULL; | |
8950 | } else if (IS_PINEVIEW(dev)) { | |
d4294342 | 8951 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
95534263 | 8952 | dev_priv->is_ddr3, |
d4294342 ZY |
8953 | dev_priv->fsb_freq, |
8954 | dev_priv->mem_freq)) { | |
8955 | DRM_INFO("failed to find known CxSR latency " | |
95534263 | 8956 | "(found ddr%s fsb freq %d, mem freq %d), " |
d4294342 | 8957 | "disabling CxSR\n", |
0206e353 | 8958 | (dev_priv->is_ddr3 == 1) ? "3" : "2", |
d4294342 ZY |
8959 | dev_priv->fsb_freq, dev_priv->mem_freq); |
8960 | /* Disable CxSR and never update its watermark again */ | |
8961 | pineview_disable_cxsr(dev); | |
8962 | dev_priv->display.update_wm = NULL; | |
8963 | } else | |
8964 | dev_priv->display.update_wm = pineview_update_wm; | |
95e0ee92 | 8965 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
6067aaea | 8966 | } else if (IS_G4X(dev)) { |
e0dac65e | 8967 | dev_priv->display.write_eld = g4x_write_eld; |
e70236a8 | 8968 | dev_priv->display.update_wm = g4x_update_wm; |
6067aaea JB |
8969 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; |
8970 | } else if (IS_GEN4(dev)) { | |
e70236a8 | 8971 | dev_priv->display.update_wm = i965_update_wm; |
6067aaea JB |
8972 | if (IS_CRESTLINE(dev)) |
8973 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; | |
8974 | else if (IS_BROADWATER(dev)) | |
8975 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; | |
8976 | } else if (IS_GEN3(dev)) { | |
e70236a8 JB |
8977 | dev_priv->display.update_wm = i9xx_update_wm; |
8978 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
6067aaea JB |
8979 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
8980 | } else if (IS_I865G(dev)) { | |
8981 | dev_priv->display.update_wm = i830_update_wm; | |
8982 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
8983 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
8f4695ed AJ |
8984 | } else if (IS_I85X(dev)) { |
8985 | dev_priv->display.update_wm = i9xx_update_wm; | |
8986 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; | |
6067aaea | 8987 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
e70236a8 | 8988 | } else { |
8f4695ed | 8989 | dev_priv->display.update_wm = i830_update_wm; |
6067aaea | 8990 | dev_priv->display.init_clock_gating = i830_init_clock_gating; |
8f4695ed | 8991 | if (IS_845G(dev)) |
e70236a8 JB |
8992 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
8993 | else | |
8994 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
e70236a8 | 8995 | } |
8c9f3aaf JB |
8996 | |
8997 | /* Default just returns -ENODEV to indicate unsupported */ | |
8998 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8999 | ||
9000 | switch (INTEL_INFO(dev)->gen) { | |
9001 | case 2: | |
9002 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
9003 | break; | |
9004 | ||
9005 | case 3: | |
9006 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
9007 | break; | |
9008 | ||
9009 | case 4: | |
9010 | case 5: | |
9011 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
9012 | break; | |
9013 | ||
9014 | case 6: | |
9015 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
9016 | break; | |
7c9017e5 JB |
9017 | case 7: |
9018 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
9019 | break; | |
8c9f3aaf | 9020 | } |
e70236a8 JB |
9021 | } |
9022 | ||
b690e96c JB |
9023 | /* |
9024 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
9025 | * resume, or other times. This quirk makes sure that's the case for | |
9026 | * affected systems. | |
9027 | */ | |
0206e353 | 9028 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
9029 | { |
9030 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9031 | ||
9032 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
9033 | DRM_DEBUG_DRIVER("applying pipe a force quirk\n"); | |
9034 | } | |
9035 | ||
435793df KP |
9036 | /* |
9037 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
9038 | */ | |
9039 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
9040 | { | |
9041 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9042 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
9043 | } | |
9044 | ||
b690e96c JB |
9045 | struct intel_quirk { |
9046 | int device; | |
9047 | int subsystem_vendor; | |
9048 | int subsystem_device; | |
9049 | void (*hook)(struct drm_device *dev); | |
9050 | }; | |
9051 | ||
9052 | struct intel_quirk intel_quirks[] = { | |
b690e96c | 9053 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 9054 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c JB |
9055 | |
9056 | /* Thinkpad R31 needs pipe A force quirk */ | |
9057 | { 0x3577, 0x1014, 0x0505, quirk_pipea_force }, | |
9058 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ | |
9059 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
9060 | ||
9061 | /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */ | |
9062 | { 0x3577, 0x1014, 0x0513, quirk_pipea_force }, | |
9063 | /* ThinkPad X40 needs pipe A force quirk */ | |
9064 | ||
9065 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ | |
9066 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
9067 | ||
9068 | /* 855 & before need to leave pipe A & dpll A up */ | |
9069 | { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
9070 | { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
435793df KP |
9071 | |
9072 | /* Lenovo U160 cannot use SSC on LVDS */ | |
9073 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
9074 | |
9075 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
9076 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
b690e96c JB |
9077 | }; |
9078 | ||
9079 | static void intel_init_quirks(struct drm_device *dev) | |
9080 | { | |
9081 | struct pci_dev *d = dev->pdev; | |
9082 | int i; | |
9083 | ||
9084 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
9085 | struct intel_quirk *q = &intel_quirks[i]; | |
9086 | ||
9087 | if (d->device == q->device && | |
9088 | (d->subsystem_vendor == q->subsystem_vendor || | |
9089 | q->subsystem_vendor == PCI_ANY_ID) && | |
9090 | (d->subsystem_device == q->subsystem_device || | |
9091 | q->subsystem_device == PCI_ANY_ID)) | |
9092 | q->hook(dev); | |
9093 | } | |
9094 | } | |
9095 | ||
9cce37f4 JB |
9096 | /* Disable the VGA plane that we never use */ |
9097 | static void i915_disable_vga(struct drm_device *dev) | |
9098 | { | |
9099 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9100 | u8 sr1; | |
9101 | u32 vga_reg; | |
9102 | ||
9103 | if (HAS_PCH_SPLIT(dev)) | |
9104 | vga_reg = CPU_VGACNTRL; | |
9105 | else | |
9106 | vga_reg = VGACNTRL; | |
9107 | ||
9108 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
9109 | outb(1, VGA_SR_INDEX); | |
9110 | sr1 = inb(VGA_SR_DATA); | |
9111 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
9112 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
9113 | udelay(300); | |
9114 | ||
9115 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); | |
9116 | POSTING_READ(vga_reg); | |
9117 | } | |
9118 | ||
79e53945 JB |
9119 | void intel_modeset_init(struct drm_device *dev) |
9120 | { | |
652c393a | 9121 | struct drm_i915_private *dev_priv = dev->dev_private; |
b840d907 | 9122 | int i, ret; |
79e53945 JB |
9123 | |
9124 | drm_mode_config_init(dev); | |
9125 | ||
9126 | dev->mode_config.min_width = 0; | |
9127 | dev->mode_config.min_height = 0; | |
9128 | ||
019d96cb DA |
9129 | dev->mode_config.preferred_depth = 24; |
9130 | dev->mode_config.prefer_shadow = 1; | |
9131 | ||
79e53945 JB |
9132 | dev->mode_config.funcs = (void *)&intel_mode_funcs; |
9133 | ||
b690e96c JB |
9134 | intel_init_quirks(dev); |
9135 | ||
e70236a8 JB |
9136 | intel_init_display(dev); |
9137 | ||
a6c45cf0 CW |
9138 | if (IS_GEN2(dev)) { |
9139 | dev->mode_config.max_width = 2048; | |
9140 | dev->mode_config.max_height = 2048; | |
9141 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
9142 | dev->mode_config.max_width = 4096; |
9143 | dev->mode_config.max_height = 4096; | |
79e53945 | 9144 | } else { |
a6c45cf0 CW |
9145 | dev->mode_config.max_width = 8192; |
9146 | dev->mode_config.max_height = 8192; | |
79e53945 | 9147 | } |
35c3047a | 9148 | dev->mode_config.fb_base = dev->agp->base; |
79e53945 | 9149 | |
28c97730 | 9150 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
a3524f1b | 9151 | dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); |
79e53945 | 9152 | |
a3524f1b | 9153 | for (i = 0; i < dev_priv->num_pipe; i++) { |
79e53945 | 9154 | intel_crtc_init(dev, i); |
00c2064b JB |
9155 | ret = intel_plane_init(dev, i); |
9156 | if (ret) | |
9157 | DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); | |
79e53945 JB |
9158 | } |
9159 | ||
9cce37f4 JB |
9160 | /* Just disable it once at startup */ |
9161 | i915_disable_vga(dev); | |
79e53945 | 9162 | intel_setup_outputs(dev); |
652c393a | 9163 | |
645c62a5 | 9164 | intel_init_clock_gating(dev); |
9cce37f4 | 9165 | |
7648fa99 | 9166 | if (IS_IRONLAKE_M(dev)) { |
f97108d1 | 9167 | ironlake_enable_drps(dev); |
7648fa99 JB |
9168 | intel_init_emon(dev); |
9169 | } | |
f97108d1 | 9170 | |
1c70c0ce | 9171 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
3b8d8d91 | 9172 | gen6_enable_rps(dev_priv); |
23b2f8bb JB |
9173 | gen6_update_ring_freq(dev_priv); |
9174 | } | |
3b8d8d91 | 9175 | |
652c393a JB |
9176 | INIT_WORK(&dev_priv->idle_work, intel_idle_update); |
9177 | setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer, | |
9178 | (unsigned long)dev); | |
2c7111db CW |
9179 | } |
9180 | ||
9181 | void intel_modeset_gem_init(struct drm_device *dev) | |
9182 | { | |
9183 | if (IS_IRONLAKE_M(dev)) | |
9184 | ironlake_enable_rc6(dev); | |
02e792fb DV |
9185 | |
9186 | intel_setup_overlay(dev); | |
79e53945 JB |
9187 | } |
9188 | ||
9189 | void intel_modeset_cleanup(struct drm_device *dev) | |
9190 | { | |
652c393a JB |
9191 | struct drm_i915_private *dev_priv = dev->dev_private; |
9192 | struct drm_crtc *crtc; | |
9193 | struct intel_crtc *intel_crtc; | |
9194 | ||
f87ea761 | 9195 | drm_kms_helper_poll_fini(dev); |
652c393a JB |
9196 | mutex_lock(&dev->struct_mutex); |
9197 | ||
723bfd70 JB |
9198 | intel_unregister_dsm_handler(); |
9199 | ||
9200 | ||
652c393a JB |
9201 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
9202 | /* Skip inactive CRTCs */ | |
9203 | if (!crtc->fb) | |
9204 | continue; | |
9205 | ||
9206 | intel_crtc = to_intel_crtc(crtc); | |
3dec0095 | 9207 | intel_increase_pllclock(crtc); |
652c393a JB |
9208 | } |
9209 | ||
973d04f9 | 9210 | intel_disable_fbc(dev); |
e70236a8 | 9211 | |
f97108d1 JB |
9212 | if (IS_IRONLAKE_M(dev)) |
9213 | ironlake_disable_drps(dev); | |
1c70c0ce | 9214 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
3b8d8d91 | 9215 | gen6_disable_rps(dev); |
f97108d1 | 9216 | |
d5bb081b JB |
9217 | if (IS_IRONLAKE_M(dev)) |
9218 | ironlake_disable_rc6(dev); | |
0cdab21f | 9219 | |
69341a5e KH |
9220 | mutex_unlock(&dev->struct_mutex); |
9221 | ||
6c0d9350 DV |
9222 | /* Disable the irq before mode object teardown, for the irq might |
9223 | * enqueue unpin/hotplug work. */ | |
9224 | drm_irq_uninstall(dev); | |
9225 | cancel_work_sync(&dev_priv->hotplug_work); | |
6fdd4d98 | 9226 | cancel_work_sync(&dev_priv->rps_work); |
6c0d9350 | 9227 | |
1630fe75 CW |
9228 | /* flush any delayed tasks or pending work */ |
9229 | flush_scheduled_work(); | |
9230 | ||
3dec0095 DV |
9231 | /* Shut off idle work before the crtcs get freed. */ |
9232 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
9233 | intel_crtc = to_intel_crtc(crtc); | |
9234 | del_timer_sync(&intel_crtc->idle_timer); | |
9235 | } | |
9236 | del_timer_sync(&dev_priv->idle_timer); | |
9237 | cancel_work_sync(&dev_priv->idle_work); | |
9238 | ||
79e53945 JB |
9239 | drm_mode_config_cleanup(dev); |
9240 | } | |
9241 | ||
f1c79df3 ZW |
9242 | /* |
9243 | * Return which encoder is currently attached for connector. | |
9244 | */ | |
df0e9248 | 9245 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 9246 | { |
df0e9248 CW |
9247 | return &intel_attached_encoder(connector)->base; |
9248 | } | |
f1c79df3 | 9249 | |
df0e9248 CW |
9250 | void intel_connector_attach_encoder(struct intel_connector *connector, |
9251 | struct intel_encoder *encoder) | |
9252 | { | |
9253 | connector->encoder = encoder; | |
9254 | drm_mode_connector_attach_encoder(&connector->base, | |
9255 | &encoder->base); | |
79e53945 | 9256 | } |
28d52043 DA |
9257 | |
9258 | /* | |
9259 | * set vga decode state - true == enable VGA decode | |
9260 | */ | |
9261 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
9262 | { | |
9263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9264 | u16 gmch_ctrl; | |
9265 | ||
9266 | pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); | |
9267 | if (state) | |
9268 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
9269 | else | |
9270 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
9271 | pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); | |
9272 | return 0; | |
9273 | } | |
c4a1d9e4 CW |
9274 | |
9275 | #ifdef CONFIG_DEBUG_FS | |
9276 | #include <linux/seq_file.h> | |
9277 | ||
9278 | struct intel_display_error_state { | |
9279 | struct intel_cursor_error_state { | |
9280 | u32 control; | |
9281 | u32 position; | |
9282 | u32 base; | |
9283 | u32 size; | |
9284 | } cursor[2]; | |
9285 | ||
9286 | struct intel_pipe_error_state { | |
9287 | u32 conf; | |
9288 | u32 source; | |
9289 | ||
9290 | u32 htotal; | |
9291 | u32 hblank; | |
9292 | u32 hsync; | |
9293 | u32 vtotal; | |
9294 | u32 vblank; | |
9295 | u32 vsync; | |
9296 | } pipe[2]; | |
9297 | ||
9298 | struct intel_plane_error_state { | |
9299 | u32 control; | |
9300 | u32 stride; | |
9301 | u32 size; | |
9302 | u32 pos; | |
9303 | u32 addr; | |
9304 | u32 surface; | |
9305 | u32 tile_offset; | |
9306 | } plane[2]; | |
9307 | }; | |
9308 | ||
9309 | struct intel_display_error_state * | |
9310 | intel_display_capture_error_state(struct drm_device *dev) | |
9311 | { | |
0206e353 | 9312 | drm_i915_private_t *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
9313 | struct intel_display_error_state *error; |
9314 | int i; | |
9315 | ||
9316 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
9317 | if (error == NULL) | |
9318 | return NULL; | |
9319 | ||
9320 | for (i = 0; i < 2; i++) { | |
9321 | error->cursor[i].control = I915_READ(CURCNTR(i)); | |
9322 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
9323 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
9324 | ||
9325 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
9326 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
9327 | error->plane[i].size = I915_READ(DSPSIZE(i)); | |
0206e353 | 9328 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
c4a1d9e4 CW |
9329 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
9330 | if (INTEL_INFO(dev)->gen >= 4) { | |
9331 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
9332 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
9333 | } | |
9334 | ||
9335 | error->pipe[i].conf = I915_READ(PIPECONF(i)); | |
9336 | error->pipe[i].source = I915_READ(PIPESRC(i)); | |
9337 | error->pipe[i].htotal = I915_READ(HTOTAL(i)); | |
9338 | error->pipe[i].hblank = I915_READ(HBLANK(i)); | |
9339 | error->pipe[i].hsync = I915_READ(HSYNC(i)); | |
9340 | error->pipe[i].vtotal = I915_READ(VTOTAL(i)); | |
9341 | error->pipe[i].vblank = I915_READ(VBLANK(i)); | |
9342 | error->pipe[i].vsync = I915_READ(VSYNC(i)); | |
9343 | } | |
9344 | ||
9345 | return error; | |
9346 | } | |
9347 | ||
9348 | void | |
9349 | intel_display_print_error_state(struct seq_file *m, | |
9350 | struct drm_device *dev, | |
9351 | struct intel_display_error_state *error) | |
9352 | { | |
9353 | int i; | |
9354 | ||
9355 | for (i = 0; i < 2; i++) { | |
9356 | seq_printf(m, "Pipe [%d]:\n", i); | |
9357 | seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); | |
9358 | seq_printf(m, " SRC: %08x\n", error->pipe[i].source); | |
9359 | seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); | |
9360 | seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); | |
9361 | seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); | |
9362 | seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); | |
9363 | seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); | |
9364 | seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); | |
9365 | ||
9366 | seq_printf(m, "Plane [%d]:\n", i); | |
9367 | seq_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
9368 | seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
9369 | seq_printf(m, " SIZE: %08x\n", error->plane[i].size); | |
9370 | seq_printf(m, " POS: %08x\n", error->plane[i].pos); | |
9371 | seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); | |
9372 | if (INTEL_INFO(dev)->gen >= 4) { | |
9373 | seq_printf(m, " SURF: %08x\n", error->plane[i].surface); | |
9374 | seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
9375 | } | |
9376 | ||
9377 | seq_printf(m, "Cursor [%d]:\n", i); | |
9378 | seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
9379 | seq_printf(m, " POS: %08x\n", error->cursor[i].position); | |
9380 | seq_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
9381 | } | |
9382 | } | |
9383 | #endif |