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drm/i915: don't set transcoder bpc on CougarPoint
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
23b2f8bb 27#include <linux/cpufreq.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
79e53945
JB		 34#include "drmP.h"
35#include "intel_drv.h"
36#include "i915_drm.h"
37#include "i915_drv.h"
e5510fac 38#include "i915_trace.h"
ab2c0672 39#include "drm_dp_helper.h"
79e53945
JB		 40
41#include "drm_crtc_helper.h"
42
32f9d658
ZW		 43#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44
79e53945 45bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
7662c8bd 46static void intel_update_watermarks(struct drm_device *dev);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60} intel_clock_t;
61
62typedef struct {
63 int min, max;
64} intel_range_t;
65
66typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
79e53945
JB		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
d4906093
ML		 76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *);
78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *best_clock);
86static bool
87intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
88 int target, int refclk, intel_clock_t *best_clock);
79e53945 89
a4fc5ed6
KP		 90static bool
91intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
92 int target, int refclk, intel_clock_t *best_clock);
5eb08b69 93static bool
f2b115e6
AJ		 94intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *best_clock);
a4fc5ed6 96
021357ac
CW		 97static inline u32 /* units of 100MHz */
98intel_fdi_link_freq(struct drm_device *dev)
99{
8b99e68c
CW		 100 if (IS_GEN5(dev)) {
101 struct drm_i915_private *dev_priv = dev->dev_private;
102 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
103 } else
104 return 27;
021357ac
CW		 105}
106
e4b36699 107static const intel_limit_t intel_limits_i8xx_dvo = {
273e27ca
EA		 108 .dot = { .min = 25000, .max = 350000 },
109 .vco = { .min = 930000, .max = 1400000 },
110 .n = { .min = 3, .max = 16 },
111 .m = { .min = 96, .max = 140 },
112 .m1 = { .min = 18, .max = 26 },
113 .m2 = { .min = 6, .max = 16 },
114 .p = { .min = 4, .max = 128 },
115 .p1 = { .min = 2, .max = 33 },
116 .p2 = { .dot_limit = 165000,
117 .p2_slow = 4, .p2_fast = 2 },
d4906093 118 .find_pll = intel_find_best_PLL,
e4b36699
KP		 119};
120
121static const intel_limit_t intel_limits_i8xx_lvds = {
273e27ca
EA		 122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
d4906093 132 .find_pll = intel_find_best_PLL,
e4b36699 133};
273e27ca 134
e4b36699 135static const intel_limit_t intel_limits_i9xx_sdvo = {
273e27ca
EA		 136 .dot = { .min = 20000, .max = 400000 },
137 .vco = { .min = 1400000, .max = 2800000 },
138 .n = { .min = 1, .max = 6 },
139 .m = { .min = 70, .max = 120 },
140 .m1 = { .min = 10, .max = 22 },
141 .m2 = { .min = 5, .max = 9 },
142 .p = { .min = 5, .max = 80 },
143 .p1 = { .min = 1, .max = 8 },
144 .p2 = { .dot_limit = 200000,
145 .p2_slow = 10, .p2_fast = 5 },
d4906093 146 .find_pll = intel_find_best_PLL,
e4b36699
KP		 147};
148
149static const intel_limit_t intel_limits_i9xx_lvds = {
273e27ca
EA		 150 .dot = { .min = 20000, .max = 400000 },
151 .vco = { .min = 1400000, .max = 2800000 },
152 .n = { .min = 1, .max = 6 },
153 .m = { .min = 70, .max = 120 },
154 .m1 = { .min = 10, .max = 22 },
155 .m2 = { .min = 5, .max = 9 },
156 .p = { .min = 7, .max = 98 },
157 .p1 = { .min = 1, .max = 8 },
158 .p2 = { .dot_limit = 112000,
159 .p2_slow = 14, .p2_fast = 7 },
d4906093 160 .find_pll = intel_find_best_PLL,
e4b36699
KP		 161};
162
273e27ca 163
e4b36699 164static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 165 .dot = { .min = 25000, .max = 270000 },
166 .vco = { .min = 1750000, .max = 3500000},
167 .n = { .min = 1, .max = 4 },
168 .m = { .min = 104, .max = 138 },
169 .m1 = { .min = 17, .max = 23 },
170 .m2 = { .min = 5, .max = 11 },
171 .p = { .min = 10, .max = 30 },
172 .p1 = { .min = 1, .max = 3},
173 .p2 = { .dot_limit = 270000,
174 .p2_slow = 10,
175 .p2_fast = 10
044c7c41 176 },
d4906093 177 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 178};
179
180static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 181 .dot = { .min = 22000, .max = 400000 },
182 .vco = { .min = 1750000, .max = 3500000},
183 .n = { .min = 1, .max = 4 },
184 .m = { .min = 104, .max = 138 },
185 .m1 = { .min = 16, .max = 23 },
186 .m2 = { .min = 5, .max = 11 },
187 .p = { .min = 5, .max = 80 },
188 .p1 = { .min = 1, .max = 8},
189 .p2 = { .dot_limit = 165000,
190 .p2_slow = 10, .p2_fast = 5 },
d4906093 191 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 192};
193
194static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 195 .dot = { .min = 20000, .max = 115000 },
196 .vco = { .min = 1750000, .max = 3500000 },
197 .n = { .min = 1, .max = 3 },
198 .m = { .min = 104, .max = 138 },
199 .m1 = { .min = 17, .max = 23 },
200 .m2 = { .min = 5, .max = 11 },
201 .p = { .min = 28, .max = 112 },
202 .p1 = { .min = 2, .max = 8 },
203 .p2 = { .dot_limit = 0,
204 .p2_slow = 14, .p2_fast = 14
044c7c41 205 },
d4906093 206 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 207};
208
209static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 210 .dot = { .min = 80000, .max = 224000 },
211 .vco = { .min = 1750000, .max = 3500000 },
212 .n = { .min = 1, .max = 3 },
213 .m = { .min = 104, .max = 138 },
214 .m1 = { .min = 17, .max = 23 },
215 .m2 = { .min = 5, .max = 11 },
216 .p = { .min = 14, .max = 42 },
217 .p1 = { .min = 2, .max = 6 },
218 .p2 = { .dot_limit = 0,
219 .p2_slow = 7, .p2_fast = 7
044c7c41 220 },
d4906093 221 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 222};
223
224static const intel_limit_t intel_limits_g4x_display_port = {
273e27ca
EA		 225 .dot = { .min = 161670, .max = 227000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 2 },
228 .m = { .min = 97, .max = 108 },
229 .m1 = { .min = 0x10, .max = 0x12 },
230 .m2 = { .min = 0x05, .max = 0x06 },
231 .p = { .min = 10, .max = 20 },
232 .p1 = { .min = 1, .max = 2},
233 .p2 = { .dot_limit = 0,
234 .p2_slow = 10, .p2_fast = 10 },
a4fc5ed6 235 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 236};
237
f2b115e6 238static const intel_limit_t intel_limits_pineview_sdvo = {
273e27ca
EA		 239 .dot = { .min = 20000, .max = 400000},
240 .vco = { .min = 1700000, .max = 3500000 },
241 /* Pineview's Ncounter is a ring counter */
242 .n = { .min = 3, .max = 6 },
243 .m = { .min = 2, .max = 256 },
244 /* Pineview only has one combined m divider, which we treat as m2. */
245 .m1 = { .min = 0, .max = 0 },
246 .m2 = { .min = 0, .max = 254 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8 },
249 .p2 = { .dot_limit = 200000,
250 .p2_slow = 10, .p2_fast = 5 },
6115707b 251 .find_pll = intel_find_best_PLL,
e4b36699
KP		 252};
253
f2b115e6 254static const intel_limit_t intel_limits_pineview_lvds = {
273e27ca
EA		 255 .dot = { .min = 20000, .max = 400000 },
256 .vco = { .min = 1700000, .max = 3500000 },
257 .n = { .min = 3, .max = 6 },
258 .m = { .min = 2, .max = 256 },
259 .m1 = { .min = 0, .max = 0 },
260 .m2 = { .min = 0, .max = 254 },
261 .p = { .min = 7, .max = 112 },
262 .p1 = { .min = 1, .max = 8 },
263 .p2 = { .dot_limit = 112000,
264 .p2_slow = 14, .p2_fast = 14 },
6115707b 265 .find_pll = intel_find_best_PLL,
e4b36699
KP		 266};
267
273e27ca
EA		 268/* Ironlake / Sandybridge
269 *
270 * We calculate clock using (register_value + 2) for N/M1/M2, so here
271 * the range value for them is (actual_value - 2).
272 */
b91ad0ec 273static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 5 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 10, .p2_fast = 5 },
4547668a 284 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 285};
286
b91ad0ec 287static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 118 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
295 .p1 = { .min = 2, .max = 8 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 298 .find_pll = intel_g4x_find_best_PLL,
299};
300
301static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 302 .dot = { .min = 25000, .max = 350000 },
303 .vco = { .min = 1760000, .max = 3510000 },
304 .n = { .min = 1, .max = 3 },
305 .m = { .min = 79, .max = 127 },
306 .m1 = { .min = 12, .max = 22 },
307 .m2 = { .min = 5, .max = 9 },
308 .p = { .min = 14, .max = 56 },
309 .p1 = { .min = 2, .max = 8 },
310 .p2 = { .dot_limit = 225000,
311 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 312 .find_pll = intel_g4x_find_best_PLL,
313};
314
273e27ca 315/* LVDS 100mhz refclk limits. */
b91ad0ec 316static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 2 },
320 .m = { .min = 79, .max = 126 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2,.max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 327 .find_pll = intel_g4x_find_best_PLL,
328};
329
330static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 126 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 42 },
338 .p1 = { .min = 2,.max = 6 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 341 .find_pll = intel_g4x_find_best_PLL,
342};
343
344static const intel_limit_t intel_limits_ironlake_display_port = {
273e27ca
EA		 345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000},
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 81, .max = 90 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 10, .max = 20 },
352 .p1 = { .min = 1, .max = 2},
353 .p2 = { .dot_limit = 0,
354 .p2_slow = 10, .p2_fast = 10 },
4547668a 355 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 356};
357
1b894b59
CW		 358static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
359 int refclk)
2c07245f 360{
b91ad0ec
ZW		 361 struct drm_device *dev = crtc->dev;
362 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 363 const intel_limit_t *limit;
b91ad0ec
ZW		 364
365 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 366 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
367 LVDS_CLKB_POWER_UP) {
368 /* LVDS dual channel */
1b894b59 369 if (refclk == 100000)
b91ad0ec
ZW		 370 limit = &intel_limits_ironlake_dual_lvds_100m;
371 else
372 limit = &intel_limits_ironlake_dual_lvds;
373 } else {
1b894b59 374 if (refclk == 100000)
b91ad0ec
ZW		 375 limit = &intel_limits_ironlake_single_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_single_lvds;
378 }
379 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 380 HAS_eDP)
381 limit = &intel_limits_ironlake_display_port;
2c07245f 382 else
b91ad0ec 383 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 384
385 return limit;
386}
387
044c7c41
ML		 388static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
389{
390 struct drm_device *dev = crtc->dev;
391 struct drm_i915_private *dev_priv = dev->dev_private;
392 const intel_limit_t *limit;
393
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
395 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
396 LVDS_CLKB_POWER_UP)
397 /* LVDS with dual channel */
e4b36699 398 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 399 else
400 /* LVDS with dual channel */
e4b36699 401 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 402 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
403 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 404 limit = &intel_limits_g4x_hdmi;
044c7c41 405 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 406 limit = &intel_limits_g4x_sdvo;
a4fc5ed6 407 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 408 limit = &intel_limits_g4x_display_port;
044c7c41 409 } else /* The option is for other outputs */
e4b36699 410 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 411
412 return limit;
413}
414
1b894b59 415static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 416{
417 struct drm_device *dev = crtc->dev;
418 const intel_limit_t *limit;
419
bad720ff 420 if (HAS_PCH_SPLIT(dev))
1b894b59 421 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 422 else if (IS_G4X(dev)) {
044c7c41 423 limit = intel_g4x_limit(crtc);
f2b115e6 424 } else if (IS_PINEVIEW(dev)) {
2177832f 425 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 426 limit = &intel_limits_pineview_lvds;
2177832f 427 else
f2b115e6 428 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 429 } else if (!IS_GEN2(dev)) {
430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431 limit = &intel_limits_i9xx_lvds;
432 else
433 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 434 } else {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 436 limit = &intel_limits_i8xx_lvds;
79e53945 437 else
e4b36699 438 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 439 }
440 return limit;
441}
442
f2b115e6
AJ		 443/* m1 is reserved as 0 in Pineview, n is a ring counter */
444static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 445{
2177832f
SL		 446 clock->m = clock->m2 + 2;
447 clock->p = clock->p1 * clock->p2;
448 clock->vco = refclk * clock->m / clock->n;
449 clock->dot = clock->vco / clock->p;
450}
451
452static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
453{
f2b115e6
AJ		 454 if (IS_PINEVIEW(dev)) {
455 pineview_clock(refclk, clock);
2177832f
SL		 456 return;
457 }
79e53945
JB		 458 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
459 clock->p = clock->p1 * clock->p2;
460 clock->vco = refclk * clock->m / (clock->n + 2);
461 clock->dot = clock->vco / clock->p;
462}
463
79e53945
JB		 464/**
465 * Returns whether any output on the specified pipe is of the specified type
466 */
4ef69c7a 467bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 468{
4ef69c7a
CW		 469 struct drm_device *dev = crtc->dev;
470 struct drm_mode_config *mode_config = &dev->mode_config;
471 struct intel_encoder *encoder;
472
473 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
474 if (encoder->base.crtc == crtc && encoder->type == type)
475 return true;
476
477 return false;
79e53945
JB		 478}
479
7c04d1d9 480#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 481/**
482 * Returns whether the given set of divisors are valid for a given refclk with
483 * the given connectors.
484 */
485
1b894b59
CW		 486static bool intel_PLL_is_valid(struct drm_device *dev,
487 const intel_limit_t *limit,
488 const intel_clock_t *clock)
79e53945 489{
79e53945
JB		 490 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
491 INTELPllInvalid ("p1 out of range\n");
492 if (clock->p < limit->p.min || limit->p.max < clock->p)
493 INTELPllInvalid ("p out of range\n");
494 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
495 INTELPllInvalid ("m2 out of range\n");
496 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
497 INTELPllInvalid ("m1 out of range\n");
f2b115e6 498 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
79e53945
JB		 499 INTELPllInvalid ("m1 <= m2\n");
500 if (clock->m < limit->m.min || limit->m.max < clock->m)
501 INTELPllInvalid ("m out of range\n");
502 if (clock->n < limit->n.min || limit->n.max < clock->n)
503 INTELPllInvalid ("n out of range\n");
504 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
505 INTELPllInvalid ("vco out of range\n");
506 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
507 * connector, etc., rather than just a single range.
508 */
509 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
510 INTELPllInvalid ("dot out of range\n");
511
512 return true;
513}
514
d4906093
ML		 515static bool
516intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
517 int target, int refclk, intel_clock_t *best_clock)
518
79e53945
JB		 519{
520 struct drm_device *dev = crtc->dev;
521 struct drm_i915_private *dev_priv = dev->dev_private;
522 intel_clock_t clock;
79e53945
JB		 523 int err = target;
524
bc5e5718 525 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 526 (I915_READ(LVDS)) != 0) {
79e53945
JB		 527 /*
528 * For LVDS, if the panel is on, just rely on its current
529 * settings for dual-channel. We haven't figured out how to
530 * reliably set up different single/dual channel state, if we
531 * even can.
532 */
533 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
534 LVDS_CLKB_POWER_UP)
535 clock.p2 = limit->p2.p2_fast;
536 else
537 clock.p2 = limit->p2.p2_slow;
538 } else {
539 if (target < limit->p2.dot_limit)
540 clock.p2 = limit->p2.p2_slow;
541 else
542 clock.p2 = limit->p2.p2_fast;
543 }
544
545 memset (best_clock, 0, sizeof (*best_clock));
546
42158660
ZY		 547 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
548 clock.m1++) {
549 for (clock.m2 = limit->m2.min;
550 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 551 /* m1 is always 0 in Pineview */
552 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 553 break;
554 for (clock.n = limit->n.min;
555 clock.n <= limit->n.max; clock.n++) {
556 for (clock.p1 = limit->p1.min;
557 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 558 int this_err;
559
2177832f 560 intel_clock(dev, refclk, &clock);
1b894b59
CW		 561 if (!intel_PLL_is_valid(dev, limit,
562 &clock))
79e53945
JB		 563 continue;
564
565 this_err = abs(clock.dot - target);
566 if (this_err < err) {
567 *best_clock = clock;
568 err = this_err;
569 }
570 }
571 }
572 }
573 }
574
575 return (err != target);
576}
577
d4906093
ML		 578static bool
579intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
580 int target, int refclk, intel_clock_t *best_clock)
581{
582 struct drm_device *dev = crtc->dev;
583 struct drm_i915_private *dev_priv = dev->dev_private;
584 intel_clock_t clock;
585 int max_n;
586 bool found;
6ba770dc
AJ		 587 /* approximately equals target * 0.00585 */
588 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 589 found = false;
590
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 592 int lvds_reg;
593
c619eed4 594 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 595 lvds_reg = PCH_LVDS;
596 else
597 lvds_reg = LVDS;
598 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 599 LVDS_CLKB_POWER_UP)
600 clock.p2 = limit->p2.p2_fast;
601 else
602 clock.p2 = limit->p2.p2_slow;
603 } else {
604 if (target < limit->p2.dot_limit)
605 clock.p2 = limit->p2.p2_slow;
606 else
607 clock.p2 = limit->p2.p2_fast;
608 }
609
610 memset(best_clock, 0, sizeof(*best_clock));
611 max_n = limit->n.max;
f77f13e2 612 /* based on hardware requirement, prefer smaller n to precision */
d4906093 613 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 614 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 615 for (clock.m1 = limit->m1.max;
616 clock.m1 >= limit->m1.min; clock.m1--) {
617 for (clock.m2 = limit->m2.max;
618 clock.m2 >= limit->m2.min; clock.m2--) {
619 for (clock.p1 = limit->p1.max;
620 clock.p1 >= limit->p1.min; clock.p1--) {
621 int this_err;
622
2177832f 623 intel_clock(dev, refclk, &clock);
1b894b59
CW		 624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
d4906093 626 continue;
1b894b59
CW		 627
628 this_err = abs(clock.dot - target);
d4906093
ML		 629 if (this_err < err_most) {
630 *best_clock = clock;
631 err_most = this_err;
632 max_n = clock.n;
633 found = true;
634 }
635 }
636 }
637 }
638 }
2c07245f
ZW		 639 return found;
640}
641
5eb08b69 642static bool
f2b115e6
AJ		 643intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
644 int target, int refclk, intel_clock_t *best_clock)
5eb08b69
ZW		 645{
646 struct drm_device *dev = crtc->dev;
647 intel_clock_t clock;
4547668a 648
5eb08b69
ZW		 649 if (target < 200000) {
650 clock.n = 1;
651 clock.p1 = 2;
652 clock.p2 = 10;
653 clock.m1 = 12;
654 clock.m2 = 9;
655 } else {
656 clock.n = 2;
657 clock.p1 = 1;
658 clock.p2 = 10;
659 clock.m1 = 14;
660 clock.m2 = 8;
661 }
662 intel_clock(dev, refclk, &clock);
663 memcpy(best_clock, &clock, sizeof(intel_clock_t));
664 return true;
665}
666
a4fc5ed6
KP		 667/* DisplayPort has only two frequencies, 162MHz and 270MHz */
668static bool
669intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *best_clock)
671{
5eddb70b
CW		 672 intel_clock_t clock;
673 if (target < 200000) {
674 clock.p1 = 2;
675 clock.p2 = 10;
676 clock.n = 2;
677 clock.m1 = 23;
678 clock.m2 = 8;
679 } else {
680 clock.p1 = 1;
681 clock.p2 = 10;
682 clock.n = 1;
683 clock.m1 = 14;
684 clock.m2 = 2;
685 }
686 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
687 clock.p = (clock.p1 * clock.p2);
688 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
689 clock.vco = 0;
690 memcpy(best_clock, &clock, sizeof(intel_clock_t));
691 return true;
a4fc5ed6
KP		 692}
693
9d0498a2
JB		 694/**
695 * intel_wait_for_vblank - wait for vblank on a given pipe
696 * @dev: drm device
697 * @pipe: pipe to wait for
698 *
699 * Wait for vblank to occur on a given pipe. Needed for various bits of
700 * mode setting code.
701 */
702void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 703{
9d0498a2 704 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 705 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 706
300387c0
CW		 707 /* Clear existing vblank status. Note this will clear any other
708 * sticky status fields as well.
709 *
710 * This races with i915_driver_irq_handler() with the result
711 * that either function could miss a vblank event. Here it is not
712 * fatal, as we will either wait upon the next vblank interrupt or
713 * timeout. Generally speaking intel_wait_for_vblank() is only
714 * called during modeset at which time the GPU should be idle and
715 * should *not* be performing page flips and thus not waiting on
716 * vblanks...
717 * Currently, the result of us stealing a vblank from the irq
718 * handler is that a single frame will be skipped during swapbuffers.
719 */
720 I915_WRITE(pipestat_reg,
721 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
722
9d0498a2 723 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 724 if (wait_for(I915_READ(pipestat_reg) &
725 PIPE_VBLANK_INTERRUPT_STATUS,
726 50))
9d0498a2
JB		 727 DRM_DEBUG_KMS("vblank wait timed out\n");
728}
729
ab7ad7f6
KP		 730/*
731 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 732 * @dev: drm device
733 * @pipe: pipe to wait for
734 *
735 * After disabling a pipe, we can't wait for vblank in the usual way,
736 * spinning on the vblank interrupt status bit, since we won't actually
737 * see an interrupt when the pipe is disabled.
738 *
ab7ad7f6
KP		 739 * On Gen4 and above:
740 * wait for the pipe register state bit to turn off
741 *
742 * Otherwise:
743 * wait for the display line value to settle (it usually
744 * ends up stopping at the start of the next frame).
58e10eb9 745 *
9d0498a2 746 */
58e10eb9 747void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 748{
749 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 750
751 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 752 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 753
754 /* Wait for the Pipe State to go off */
58e10eb9
CW		 755 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
756 100))
ab7ad7f6
KP		 757 DRM_DEBUG_KMS("pipe_off wait timed out\n");
758 } else {
759 u32 last_line;
58e10eb9 760 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 761 unsigned long timeout = jiffies + msecs_to_jiffies(100);
762
763 /* Wait for the display line to settle */
764 do {
58e10eb9 765 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 766 mdelay(5);
58e10eb9 767 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 768 time_after(timeout, jiffies));
769 if (time_after(jiffies, timeout))
770 DRM_DEBUG_KMS("pipe_off wait timed out\n");
771 }
79e53945
JB		 772}
773
b24e7179
JB		 774static const char *state_string(bool enabled)
775{
776 return enabled ? "on" : "off";
777}
778
779/* Only for pre-ILK configs */
780static void assert_pll(struct drm_i915_private *dev_priv,
781 enum pipe pipe, bool state)
782{
783 int reg;
784 u32 val;
785 bool cur_state;
786
787 reg = DPLL(pipe);
788 val = I915_READ(reg);
789 cur_state = !!(val & DPLL_VCO_ENABLE);
790 WARN(cur_state != state,
791 "PLL state assertion failure (expected %s, current %s)\n",
792 state_string(state), state_string(cur_state));
793}
794#define assert_pll_enabled(d, p) assert_pll(d, p, true)
795#define assert_pll_disabled(d, p) assert_pll(d, p, false)
796
040484af
JB		 797/* For ILK+ */
798static void assert_pch_pll(struct drm_i915_private *dev_priv,
799 enum pipe pipe, bool state)
800{
801 int reg;
802 u32 val;
803 bool cur_state;
804
805 reg = PCH_DPLL(pipe);
806 val = I915_READ(reg);
807 cur_state = !!(val & DPLL_VCO_ENABLE);
808 WARN(cur_state != state,
809 "PCH PLL state assertion failure (expected %s, current %s)\n",
810 state_string(state), state_string(cur_state));
811}
812#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
813#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
814
815static void assert_fdi_tx(struct drm_i915_private *dev_priv,
816 enum pipe pipe, bool state)
817{
818 int reg;
819 u32 val;
820 bool cur_state;
821
822 reg = FDI_TX_CTL(pipe);
823 val = I915_READ(reg);
824 cur_state = !!(val & FDI_TX_ENABLE);
825 WARN(cur_state != state,
826 "FDI TX state assertion failure (expected %s, current %s)\n",
827 state_string(state), state_string(cur_state));
828}
829#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
830#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
831
832static void assert_fdi_rx(struct drm_i915_private *dev_priv,
833 enum pipe pipe, bool state)
834{
835 int reg;
836 u32 val;
837 bool cur_state;
838
839 reg = FDI_RX_CTL(pipe);
840 val = I915_READ(reg);
841 cur_state = !!(val & FDI_RX_ENABLE);
842 WARN(cur_state != state,
843 "FDI RX state assertion failure (expected %s, current %s)\n",
844 state_string(state), state_string(cur_state));
845}
846#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
847#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
848
849static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
850 enum pipe pipe)
851{
852 int reg;
853 u32 val;
854
855 /* ILK FDI PLL is always enabled */
856 if (dev_priv->info->gen == 5)
857 return;
858
859 reg = FDI_TX_CTL(pipe);
860 val = I915_READ(reg);
861 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
862}
863
864static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
865 enum pipe pipe)
866{
867 int reg;
868 u32 val;
869
870 reg = FDI_RX_CTL(pipe);
871 val = I915_READ(reg);
872 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
873}
874
ea0760cf
JB		 875static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
876 enum pipe pipe)
877{
878 int pp_reg, lvds_reg;
879 u32 val;
880 enum pipe panel_pipe = PIPE_A;
881 bool locked = locked;
882
883 if (HAS_PCH_SPLIT(dev_priv->dev)) {
884 pp_reg = PCH_PP_CONTROL;
885 lvds_reg = PCH_LVDS;
886 } else {
887 pp_reg = PP_CONTROL;
888 lvds_reg = LVDS;
889 }
890
891 val = I915_READ(pp_reg);
892 if (!(val & PANEL_POWER_ON) ||
893 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
894 locked = false;
895
896 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
897 panel_pipe = PIPE_B;
898
899 WARN(panel_pipe == pipe && locked,
900 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 901 pipe_name(pipe));
ea0760cf
JB		 902}
903
63d7bbe9
JB		 904static void assert_pipe(struct drm_i915_private *dev_priv,
905 enum pipe pipe, bool state)
b24e7179
JB		 906{
907 int reg;
908 u32 val;
63d7bbe9 909 bool cur_state;
b24e7179
JB		 910
911 reg = PIPECONF(pipe);
912 val = I915_READ(reg);
63d7bbe9
JB		 913 cur_state = !!(val & PIPECONF_ENABLE);
914 WARN(cur_state != state,
915 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 916 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179 917}
63d7bbe9
JB		 918#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
919#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
b24e7179
JB		 920
921static void assert_plane_enabled(struct drm_i915_private *dev_priv,
922 enum plane plane)
923{
924 int reg;
925 u32 val;
926
927 reg = DSPCNTR(plane);
928 val = I915_READ(reg);
929 WARN(!(val & DISPLAY_PLANE_ENABLE),
930 "plane %c assertion failure, should be active but is disabled\n",
9db4a9c7 931 plane_name(plane));
b24e7179
JB		 932}
933
934static void assert_planes_disabled(struct drm_i915_private *dev_priv,
935 enum pipe pipe)
936{
937 int reg, i;
938 u32 val;
939 int cur_pipe;
940
19ec1358
JB		 941 /* Planes are fixed to pipes on ILK+ */
942 if (HAS_PCH_SPLIT(dev_priv->dev))
943 return;
944
b24e7179
JB		 945 /* Need to check both planes against the pipe */
946 for (i = 0; i < 2; i++) {
947 reg = DSPCNTR(i);
948 val = I915_READ(reg);
949 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
950 DISPPLANE_SEL_PIPE_SHIFT;
951 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 952 "plane %c assertion failure, should be off on pipe %c but is still active\n",
953 plane_name(i), pipe_name(pipe));
b24e7179
JB		 954 }
955}
956
92f2584a
JB		 957static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
958{
959 u32 val;
960 bool enabled;
961
962 val = I915_READ(PCH_DREF_CONTROL);
963 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
964 DREF_SUPERSPREAD_SOURCE_MASK));
965 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
966}
967
968static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
969 enum pipe pipe)
970{
971 int reg;
972 u32 val;
973 bool enabled;
974
975 reg = TRANSCONF(pipe);
976 val = I915_READ(reg);
977 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 978 WARN(enabled,
979 "transcoder assertion failed, should be off on pipe %c but is still active\n",
980 pipe_name(pipe));
92f2584a
JB		 981}
982
291906f1
JB		 983static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
984 enum pipe pipe, int reg)
985{
47a05eca
JB		 986 u32 val = I915_READ(reg);
987 WARN(DP_PIPE_ENABLED(val, pipe),
291906f1 988 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 989 reg, pipe_name(pipe));
291906f1
JB		 990}
991
992static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
993 enum pipe pipe, int reg)
994{
47a05eca
JB		 995 u32 val = I915_READ(reg);
996 WARN(HDMI_PIPE_ENABLED(val, pipe),
291906f1 997 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 998 reg, pipe_name(pipe));
291906f1
JB		 999}
1000
1001static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe)
1003{
1004 int reg;
1005 u32 val;
291906f1
JB		 1006
1007 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1008 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1009 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1010
1011 reg = PCH_ADPA;
1012 val = I915_READ(reg);
47a05eca 1013 WARN(ADPA_PIPE_ENABLED(val, pipe),
291906f1 1014 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1015 pipe_name(pipe));
291906f1
JB		 1016
1017 reg = PCH_LVDS;
1018 val = I915_READ(reg);
47a05eca 1019 WARN(LVDS_PIPE_ENABLED(val, pipe),
291906f1 1020 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1021 pipe_name(pipe));
291906f1
JB		 1022
1023 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1024 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1025 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1026}
1027
63d7bbe9
JB		 1028/**
1029 * intel_enable_pll - enable a PLL
1030 * @dev_priv: i915 private structure
1031 * @pipe: pipe PLL to enable
1032 *
1033 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1034 * make sure the PLL reg is writable first though, since the panel write
1035 * protect mechanism may be enabled.
1036 *
1037 * Note! This is for pre-ILK only.
1038 */
1039static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1040{
1041 int reg;
1042 u32 val;
1043
1044 /* No really, not for ILK+ */
1045 BUG_ON(dev_priv->info->gen >= 5);
1046
1047 /* PLL is protected by panel, make sure we can write it */
1048 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1049 assert_panel_unlocked(dev_priv, pipe);
1050
1051 reg = DPLL(pipe);
1052 val = I915_READ(reg);
1053 val |= DPLL_VCO_ENABLE;
1054
1055 /* We do this three times for luck */
1056 I915_WRITE(reg, val);
1057 POSTING_READ(reg);
1058 udelay(150); /* wait for warmup */
1059 I915_WRITE(reg, val);
1060 POSTING_READ(reg);
1061 udelay(150); /* wait for warmup */
1062 I915_WRITE(reg, val);
1063 POSTING_READ(reg);
1064 udelay(150); /* wait for warmup */
1065}
1066
1067/**
1068 * intel_disable_pll - disable a PLL
1069 * @dev_priv: i915 private structure
1070 * @pipe: pipe PLL to disable
1071 *
1072 * Disable the PLL for @pipe, making sure the pipe is off first.
1073 *
1074 * Note! This is for pre-ILK only.
1075 */
1076static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1077{
1078 int reg;
1079 u32 val;
1080
1081 /* Don't disable pipe A or pipe A PLLs if needed */
1082 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1083 return;
1084
1085 /* Make sure the pipe isn't still relying on us */
1086 assert_pipe_disabled(dev_priv, pipe);
1087
1088 reg = DPLL(pipe);
1089 val = I915_READ(reg);
1090 val &= ~DPLL_VCO_ENABLE;
1091 I915_WRITE(reg, val);
1092 POSTING_READ(reg);
1093}
1094
92f2584a
JB		 1095/**
1096 * intel_enable_pch_pll - enable PCH PLL
1097 * @dev_priv: i915 private structure
1098 * @pipe: pipe PLL to enable
1099 *
1100 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1101 * drives the transcoder clock.
1102 */
1103static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1104 enum pipe pipe)
1105{
1106 int reg;
1107 u32 val;
1108
1109 /* PCH only available on ILK+ */
1110 BUG_ON(dev_priv->info->gen < 5);
1111
1112 /* PCH refclock must be enabled first */
1113 assert_pch_refclk_enabled(dev_priv);
1114
1115 reg = PCH_DPLL(pipe);
1116 val = I915_READ(reg);
1117 val |= DPLL_VCO_ENABLE;
1118 I915_WRITE(reg, val);
1119 POSTING_READ(reg);
1120 udelay(200);
1121}
1122
1123static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1124 enum pipe pipe)
1125{
1126 int reg;
1127 u32 val;
1128
1129 /* PCH only available on ILK+ */
1130 BUG_ON(dev_priv->info->gen < 5);
1131
1132 /* Make sure transcoder isn't still depending on us */
1133 assert_transcoder_disabled(dev_priv, pipe);
1134
1135 reg = PCH_DPLL(pipe);
1136 val = I915_READ(reg);
1137 val &= ~DPLL_VCO_ENABLE;
1138 I915_WRITE(reg, val);
1139 POSTING_READ(reg);
1140 udelay(200);
1141}
1142
040484af
JB		 1143static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1144 enum pipe pipe)
1145{
1146 int reg;
1147 u32 val;
1148
1149 /* PCH only available on ILK+ */
1150 BUG_ON(dev_priv->info->gen < 5);
1151
1152 /* Make sure PCH DPLL is enabled */
1153 assert_pch_pll_enabled(dev_priv, pipe);
1154
1155 /* FDI must be feeding us bits for PCH ports */
1156 assert_fdi_tx_enabled(dev_priv, pipe);
1157 assert_fdi_rx_enabled(dev_priv, pipe);
1158
1159 reg = TRANSCONF(pipe);
1160 val = I915_READ(reg);
e9bcff5c
JB		 1161
1162 if (HAS_PCH_IBX(dev_priv->dev)) {
1163 /*
1164 * make the BPC in transcoder be consistent with
1165 * that in pipeconf reg.
1166 */
1167 val &= ~PIPE_BPC_MASK;
1168 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1169 }
040484af
JB		 1170 I915_WRITE(reg, val | TRANS_ENABLE);
1171 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1172 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1173}
1174
1175static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1176 enum pipe pipe)
1177{
1178 int reg;
1179 u32 val;
1180
1181 /* FDI relies on the transcoder */
1182 assert_fdi_tx_disabled(dev_priv, pipe);
1183 assert_fdi_rx_disabled(dev_priv, pipe);
1184
291906f1
JB		 1185 /* Ports must be off as well */
1186 assert_pch_ports_disabled(dev_priv, pipe);
1187
040484af
JB		 1188 reg = TRANSCONF(pipe);
1189 val = I915_READ(reg);
1190 val &= ~TRANS_ENABLE;
1191 I915_WRITE(reg, val);
1192 /* wait for PCH transcoder off, transcoder state */
1193 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1194 DRM_ERROR("failed to disable transcoder\n");
1195}
1196
b24e7179 1197/**
309cfea8 1198 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1199 * @dev_priv: i915 private structure
1200 * @pipe: pipe to enable
040484af 1201 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1202 *
1203 * Enable @pipe, making sure that various hardware specific requirements
1204 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1205 *
1206 * @pipe should be %PIPE_A or %PIPE_B.
1207 *
1208 * Will wait until the pipe is actually running (i.e. first vblank) before
1209 * returning.
1210 */
040484af
JB		 1211static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1212 bool pch_port)
b24e7179
JB		 1213{
1214 int reg;
1215 u32 val;
1216
1217 /*
1218 * A pipe without a PLL won't actually be able to drive bits from
1219 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1220 * need the check.
1221 */
1222 if (!HAS_PCH_SPLIT(dev_priv->dev))
1223 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1224 else {
1225 if (pch_port) {
1226 /* if driving the PCH, we need FDI enabled */
1227 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1228 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1229 }
1230 /* FIXME: assert CPU port conditions for SNB+ */
1231 }
b24e7179
JB		 1232
1233 reg = PIPECONF(pipe);
1234 val = I915_READ(reg);
00d70b15
CW		 1235 if (val & PIPECONF_ENABLE)
1236 return;
1237
1238 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1239 intel_wait_for_vblank(dev_priv->dev, pipe);
1240}
1241
1242/**
309cfea8 1243 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1244 * @dev_priv: i915 private structure
1245 * @pipe: pipe to disable
1246 *
1247 * Disable @pipe, making sure that various hardware specific requirements
1248 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1249 *
1250 * @pipe should be %PIPE_A or %PIPE_B.
1251 *
1252 * Will wait until the pipe has shut down before returning.
1253 */
1254static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
1256{
1257 int reg;
1258 u32 val;
1259
1260 /*
1261 * Make sure planes won't keep trying to pump pixels to us,
1262 * or we might hang the display.
1263 */
1264 assert_planes_disabled(dev_priv, pipe);
1265
1266 /* Don't disable pipe A or pipe A PLLs if needed */
1267 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1268 return;
1269
1270 reg = PIPECONF(pipe);
1271 val = I915_READ(reg);
00d70b15
CW		 1272 if ((val & PIPECONF_ENABLE) == 0)
1273 return;
1274
1275 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1276 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1277}
1278
1279/**
1280 * intel_enable_plane - enable a display plane on a given pipe
1281 * @dev_priv: i915 private structure
1282 * @plane: plane to enable
1283 * @pipe: pipe being fed
1284 *
1285 * Enable @plane on @pipe, making sure that @pipe is running first.
1286 */
1287static void intel_enable_plane(struct drm_i915_private *dev_priv,
1288 enum plane plane, enum pipe pipe)
1289{
1290 int reg;
1291 u32 val;
1292
1293 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1294 assert_pipe_enabled(dev_priv, pipe);
1295
1296 reg = DSPCNTR(plane);
1297 val = I915_READ(reg);
00d70b15
CW		 1298 if (val & DISPLAY_PLANE_ENABLE)
1299 return;
1300
1301 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1302 intel_wait_for_vblank(dev_priv->dev, pipe);
1303}
1304
1305/*
1306 * Plane regs are double buffered, going from enabled->disabled needs a
1307 * trigger in order to latch. The display address reg provides this.
1308 */
1309static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1310 enum plane plane)
1311{
1312 u32 reg = DSPADDR(plane);
1313 I915_WRITE(reg, I915_READ(reg));
1314}
1315
1316/**
1317 * intel_disable_plane - disable a display plane
1318 * @dev_priv: i915 private structure
1319 * @plane: plane to disable
1320 * @pipe: pipe consuming the data
1321 *
1322 * Disable @plane; should be an independent operation.
1323 */
1324static void intel_disable_plane(struct drm_i915_private *dev_priv,
1325 enum plane plane, enum pipe pipe)
1326{
1327 int reg;
1328 u32 val;
1329
1330 reg = DSPCNTR(plane);
1331 val = I915_READ(reg);
00d70b15
CW		 1332 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1333 return;
1334
1335 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1336 intel_flush_display_plane(dev_priv, plane);
1337 intel_wait_for_vblank(dev_priv->dev, pipe);
1338}
1339
47a05eca
JB		 1340static void disable_pch_dp(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, int reg)
1342{
1343 u32 val = I915_READ(reg);
1344 if (DP_PIPE_ENABLED(val, pipe))
1345 I915_WRITE(reg, val & ~DP_PORT_EN);
1346}
1347
1348static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1349 enum pipe pipe, int reg)
1350{
1351 u32 val = I915_READ(reg);
1352 if (HDMI_PIPE_ENABLED(val, pipe))
1353 I915_WRITE(reg, val & ~PORT_ENABLE);
1354}
1355
1356/* Disable any ports connected to this transcoder */
1357static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1358 enum pipe pipe)
1359{
1360 u32 reg, val;
1361
1362 val = I915_READ(PCH_PP_CONTROL);
1363 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1364
1365 disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1366 disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1367 disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1368
1369 reg = PCH_ADPA;
1370 val = I915_READ(reg);
1371 if (ADPA_PIPE_ENABLED(val, pipe))
1372 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1373
1374 reg = PCH_LVDS;
1375 val = I915_READ(reg);
1376 if (LVDS_PIPE_ENABLED(val, pipe)) {
1377 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1378 POSTING_READ(reg);
1379 udelay(100);
1380 }
1381
1382 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1383 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1384 disable_pch_hdmi(dev_priv, pipe, HDMID);
1385}
1386
80824003
JB		 1387static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1388{
1389 struct drm_device *dev = crtc->dev;
1390 struct drm_i915_private *dev_priv = dev->dev_private;
1391 struct drm_framebuffer *fb = crtc->fb;
1392 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1393 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003
JB		 1394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1395 int plane, i;
1396 u32 fbc_ctl, fbc_ctl2;
1397
bed4a673 1398 if (fb->pitch == dev_priv->cfb_pitch &&
05394f39 1399 obj->fence_reg == dev_priv->cfb_fence &&
bed4a673
CW		 1400 intel_crtc->plane == dev_priv->cfb_plane &&
1401 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1402 return;
1403
1404 i8xx_disable_fbc(dev);
1405
80824003
JB		 1406 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1407
1408 if (fb->pitch < dev_priv->cfb_pitch)
1409 dev_priv->cfb_pitch = fb->pitch;
1410
1411 /* FBC_CTL wants 64B units */
1412 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1413 dev_priv->cfb_fence = obj->fence_reg;
80824003
JB		 1414 dev_priv->cfb_plane = intel_crtc->plane;
1415 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1416
1417 /* Clear old tags */
1418 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1419 I915_WRITE(FBC_TAG + (i * 4), 0);
1420
1421 /* Set it up... */
1422 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
05394f39 1423 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB		 1424 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1425 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1426 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1427
1428 /* enable it... */
1429 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1430 if (IS_I945GM(dev))
49677901 1431 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
80824003
JB		 1432 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1433 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
05394f39 1434 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB		 1435 fbc_ctl |= dev_priv->cfb_fence;
1436 I915_WRITE(FBC_CONTROL, fbc_ctl);
1437
28c97730 1438 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
5eddb70b 1439 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
80824003
JB		 1440}
1441
1442void i8xx_disable_fbc(struct drm_device *dev)
1443{
1444 struct drm_i915_private *dev_priv = dev->dev_private;
1445 u32 fbc_ctl;
1446
1447 /* Disable compression */
1448 fbc_ctl = I915_READ(FBC_CONTROL);
a5cad620
CW		 1449 if ((fbc_ctl & FBC_CTL_EN) == 0)
1450 return;
1451
80824003
JB		 1452 fbc_ctl &= ~FBC_CTL_EN;
1453 I915_WRITE(FBC_CONTROL, fbc_ctl);
1454
1455 /* Wait for compressing bit to clear */
481b6af3 1456 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
913d8d11
CW		 1457 DRM_DEBUG_KMS("FBC idle timed out\n");
1458 return;
9517a92f 1459 }
80824003 1460
28c97730 1461 DRM_DEBUG_KMS("disabled FBC\n");
80824003
JB		 1462}
1463
ee5382ae 1464static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1465{
80824003
JB		 1466 struct drm_i915_private *dev_priv = dev->dev_private;
1467
1468 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1469}
1470
74dff282
JB		 1471static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1472{
1473 struct drm_device *dev = crtc->dev;
1474 struct drm_i915_private *dev_priv = dev->dev_private;
1475 struct drm_framebuffer *fb = crtc->fb;
1476 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1477 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1479 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1480 unsigned long stall_watermark = 200;
1481 u32 dpfc_ctl;
1482
bed4a673
CW		 1483 dpfc_ctl = I915_READ(DPFC_CONTROL);
1484 if (dpfc_ctl & DPFC_CTL_EN) {
1485 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
05394f39 1486 dev_priv->cfb_fence == obj->fence_reg &&
bed4a673
CW		 1487 dev_priv->cfb_plane == intel_crtc->plane &&
1488 dev_priv->cfb_y == crtc->y)
1489 return;
1490
1491 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1492 intel_wait_for_vblank(dev, intel_crtc->pipe);
1493 }
1494
74dff282 1495 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1496 dev_priv->cfb_fence = obj->fence_reg;
74dff282 1497 dev_priv->cfb_plane = intel_crtc->plane;
bed4a673 1498 dev_priv->cfb_y = crtc->y;
74dff282
JB		 1499
1500 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
05394f39 1501 if (obj->tiling_mode != I915_TILING_NONE) {
74dff282
JB		 1502 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1503 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1504 } else {
1505 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1506 }
1507
74dff282
JB		 1508 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1509 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1510 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1511 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1512
1513 /* enable it... */
1514 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1515
28c97730 1516 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1517}
1518
1519void g4x_disable_fbc(struct drm_device *dev)
1520{
1521 struct drm_i915_private *dev_priv = dev->dev_private;
1522 u32 dpfc_ctl;
1523
1524 /* Disable compression */
1525 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1526 if (dpfc_ctl & DPFC_CTL_EN) {
1527 dpfc_ctl &= ~DPFC_CTL_EN;
1528 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1529
bed4a673
CW		 1530 DRM_DEBUG_KMS("disabled FBC\n");
1531 }
74dff282
JB		 1532}
1533
ee5382ae 1534static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1535{
74dff282
JB		 1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537
1538 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1539}
1540
4efe0708
JB		 1541static void sandybridge_blit_fbc_update(struct drm_device *dev)
1542{
1543 struct drm_i915_private *dev_priv = dev->dev_private;
1544 u32 blt_ecoskpd;
1545
1546 /* Make sure blitter notifies FBC of writes */
fcca7926 1547 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1548 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1549 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1550 GEN6_BLITTER_LOCK_SHIFT;
1551 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1552 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1553 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1554 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1555 GEN6_BLITTER_LOCK_SHIFT);
1556 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1557 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1558 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1559}
1560
b52eb4dc
ZY		 1561static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1562{
1563 struct drm_device *dev = crtc->dev;
1564 struct drm_i915_private *dev_priv = dev->dev_private;
1565 struct drm_framebuffer *fb = crtc->fb;
1566 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1567 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1569 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1570 unsigned long stall_watermark = 200;
1571 u32 dpfc_ctl;
1572
bed4a673
CW		 1573 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1574 if (dpfc_ctl & DPFC_CTL_EN) {
1575 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
05394f39 1576 dev_priv->cfb_fence == obj->fence_reg &&
bed4a673 1577 dev_priv->cfb_plane == intel_crtc->plane &&
05394f39 1578 dev_priv->cfb_offset == obj->gtt_offset &&
bed4a673
CW		 1579 dev_priv->cfb_y == crtc->y)
1580 return;
1581
1582 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1583 intel_wait_for_vblank(dev, intel_crtc->pipe);
1584 }
1585
b52eb4dc 1586 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1587 dev_priv->cfb_fence = obj->fence_reg;
b52eb4dc 1588 dev_priv->cfb_plane = intel_crtc->plane;
05394f39 1589 dev_priv->cfb_offset = obj->gtt_offset;
bed4a673 1590 dev_priv->cfb_y = crtc->y;
b52eb4dc 1591
b52eb4dc
ZY		 1592 dpfc_ctl &= DPFC_RESERVED;
1593 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
05394f39 1594 if (obj->tiling_mode != I915_TILING_NONE) {
b52eb4dc
ZY		 1595 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1596 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1597 } else {
1598 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1599 }
1600
b52eb4dc
ZY		 1601 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1602 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1603 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1604 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1605 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1606 /* enable it... */
bed4a673 1607 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1608
9c04f015
YL		 1609 if (IS_GEN6(dev)) {
1610 I915_WRITE(SNB_DPFC_CTL_SA,
1611 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1612 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1613 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1614 }
1615
b52eb4dc
ZY		 1616 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1617}
1618
1619void ironlake_disable_fbc(struct drm_device *dev)
1620{
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 u32 dpfc_ctl;
1623
1624 /* Disable compression */
1625 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1626 if (dpfc_ctl & DPFC_CTL_EN) {
1627 dpfc_ctl &= ~DPFC_CTL_EN;
1628 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1629
bed4a673
CW		 1630 DRM_DEBUG_KMS("disabled FBC\n");
1631 }
b52eb4dc
ZY		 1632}
1633
1634static bool ironlake_fbc_enabled(struct drm_device *dev)
1635{
1636 struct drm_i915_private *dev_priv = dev->dev_private;
1637
1638 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1639}
1640
ee5382ae
AJ		 1641bool intel_fbc_enabled(struct drm_device *dev)
1642{
1643 struct drm_i915_private *dev_priv = dev->dev_private;
1644
1645 if (!dev_priv->display.fbc_enabled)
1646 return false;
1647
1648 return dev_priv->display.fbc_enabled(dev);
1649}
1650
1651void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1652{
1653 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1654
1655 if (!dev_priv->display.enable_fbc)
1656 return;
1657
1658 dev_priv->display.enable_fbc(crtc, interval);
1659}
1660
1661void intel_disable_fbc(struct drm_device *dev)
1662{
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664
1665 if (!dev_priv->display.disable_fbc)
1666 return;
1667
1668 dev_priv->display.disable_fbc(dev);
1669}
1670
80824003
JB		 1671/**
1672 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1673 * @dev: the drm_device
80824003
JB		 1674 *
1675 * Set up the framebuffer compression hardware at mode set time. We
1676 * enable it if possible:
1677 * - plane A only (on pre-965)
1678 * - no pixel mulitply/line duplication
1679 * - no alpha buffer discard
1680 * - no dual wide
1681 * - framebuffer <= 2048 in width, 1536 in height
1682 *
1683 * We can't assume that any compression will take place (worst case),
1684 * so the compressed buffer has to be the same size as the uncompressed
1685 * one. It also must reside (along with the line length buffer) in
1686 * stolen memory.
1687 *
1688 * We need to enable/disable FBC on a global basis.
1689 */
bed4a673 1690static void intel_update_fbc(struct drm_device *dev)
80824003 1691{
80824003 1692 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1693 struct drm_crtc *crtc = NULL, *tmp_crtc;
1694 struct intel_crtc *intel_crtc;
1695 struct drm_framebuffer *fb;
80824003 1696 struct intel_framebuffer *intel_fb;
05394f39 1697 struct drm_i915_gem_object *obj;
9c928d16
JB		 1698
1699 DRM_DEBUG_KMS("\n");
80824003
JB		 1700
1701 if (!i915_powersave)
1702 return;
1703
ee5382ae 1704 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1705 return;
1706
80824003
JB		 1707 /*
1708 * If FBC is already on, we just have to verify that we can
1709 * keep it that way...
1710 * Need to disable if:
9c928d16 1711 * - more than one pipe is active
80824003
JB		 1712 * - changing FBC params (stride, fence, mode)
1713 * - new fb is too large to fit in compressed buffer
1714 * - going to an unsupported config (interlace, pixel multiply, etc.)
1715 */
9c928d16 1716 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1717 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1718 if (crtc) {
1719 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1720 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1721 goto out_disable;
1722 }
1723 crtc = tmp_crtc;
1724 }
9c928d16 1725 }
bed4a673
CW		 1726
1727 if (!crtc || crtc->fb == NULL) {
1728 DRM_DEBUG_KMS("no output, disabling\n");
1729 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1730 goto out_disable;
1731 }
bed4a673
CW		 1732
1733 intel_crtc = to_intel_crtc(crtc);
1734 fb = crtc->fb;
1735 intel_fb = to_intel_framebuffer(fb);
05394f39 1736 obj = intel_fb->obj;
bed4a673 1737
c1a9f047
JB		 1738 if (!i915_enable_fbc) {
1739 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1740 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1741 goto out_disable;
1742 }
05394f39 1743 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1744 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1745 "compression\n");
b5e50c3f 1746 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1747 goto out_disable;
1748 }
bed4a673
CW		 1749 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1750 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1751 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1752 "disabling\n");
b5e50c3f 1753 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1754 goto out_disable;
1755 }
bed4a673
CW		 1756 if ((crtc->mode.hdisplay > 2048) ||
1757 (crtc->mode.vdisplay > 1536)) {
28c97730 1758 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1759 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1760 goto out_disable;
1761 }
bed4a673 1762 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1763 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1764 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1765 goto out_disable;
1766 }
05394f39 1767 if (obj->tiling_mode != I915_TILING_X) {
28c97730 1768 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
b5e50c3f 1769 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1770 goto out_disable;
1771 }
1772
c924b934
JW		 1773 /* If the kernel debugger is active, always disable compression */
1774 if (in_dbg_master())
1775 goto out_disable;
1776
bed4a673 1777 intel_enable_fbc(crtc, 500);
80824003
JB		 1778 return;
1779
1780out_disable:
80824003 1781 /* Multiple disables should be harmless */
a939406f
CW		 1782 if (intel_fbc_enabled(dev)) {
1783 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1784 intel_disable_fbc(dev);
a939406f 1785 }
80824003
JB		 1786}
1787
127bd2ac 1788int
48b956c5 1789intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1790 struct drm_i915_gem_object *obj,
919926ae 1791 struct intel_ring_buffer *pipelined)
6b95a207 1792{
ce453d81 1793 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1794 u32 alignment;
1795 int ret;
1796
05394f39 1797 switch (obj->tiling_mode) {
6b95a207 1798 case I915_TILING_NONE:
534843da
CW		 1799 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1800 alignment = 128 * 1024;
a6c45cf0 1801 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1802 alignment = 4 * 1024;
1803 else
1804 alignment = 64 * 1024;
6b95a207
KH		 1805 break;
1806 case I915_TILING_X:
1807 /* pin() will align the object as required by fence */
1808 alignment = 0;
1809 break;
1810 case I915_TILING_Y:
1811 /* FIXME: Is this true? */
1812 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1813 return -EINVAL;
1814 default:
1815 BUG();
1816 }
1817
ce453d81 1818 dev_priv->mm.interruptible = false;
2da3b9b9 1819 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1820 if (ret)
ce453d81 1821 goto err_interruptible;
6b95a207
KH		 1822
1823 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1824 * fence, whereas 965+ only requires a fence if using
1825 * framebuffer compression. For simplicity, we always install
1826 * a fence as the cost is not that onerous.
1827 */
05394f39 1828 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 1829 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 1830 if (ret)
1831 goto err_unpin;
6b95a207
KH		 1832 }
1833
ce453d81 1834 dev_priv->mm.interruptible = true;
6b95a207 1835 return 0;
48b956c5
CW		 1836
1837err_unpin:
1838 i915_gem_object_unpin(obj);
ce453d81
CW		 1839err_interruptible:
1840 dev_priv->mm.interruptible = true;
48b956c5 1841 return ret;
6b95a207
KH		 1842}
1843
81255565
JB		 1844/* Assume fb object is pinned & idle & fenced and just update base pointers */
1845static int
1846intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
21c74a8e 1847 int x, int y, enum mode_set_atomic state)
81255565
JB		 1848{
1849 struct drm_device *dev = crtc->dev;
1850 struct drm_i915_private *dev_priv = dev->dev_private;
1851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1852 struct intel_framebuffer *intel_fb;
05394f39 1853 struct drm_i915_gem_object *obj;
81255565
JB		 1854 int plane = intel_crtc->plane;
1855 unsigned long Start, Offset;
81255565 1856 u32 dspcntr;
5eddb70b 1857 u32 reg;
81255565
JB		 1858
1859 switch (plane) {
1860 case 0:
1861 case 1:
1862 break;
1863 default:
1864 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1865 return -EINVAL;
1866 }
1867
1868 intel_fb = to_intel_framebuffer(fb);
1869 obj = intel_fb->obj;
81255565 1870
5eddb70b
CW		 1871 reg = DSPCNTR(plane);
1872 dspcntr = I915_READ(reg);
81255565
JB		 1873 /* Mask out pixel format bits in case we change it */
1874 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1875 switch (fb->bits_per_pixel) {
1876 case 8:
1877 dspcntr |= DISPPLANE_8BPP;
1878 break;
1879 case 16:
1880 if (fb->depth == 15)
1881 dspcntr |= DISPPLANE_15_16BPP;
1882 else
1883 dspcntr |= DISPPLANE_16BPP;
1884 break;
1885 case 24:
1886 case 32:
1887 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1888 break;
1889 default:
1890 DRM_ERROR("Unknown color depth\n");
1891 return -EINVAL;
1892 }
a6c45cf0 1893 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1894 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1895 dspcntr |= DISPPLANE_TILED;
1896 else
1897 dspcntr &= ~DISPPLANE_TILED;
1898 }
1899
4e6cfefc 1900 if (HAS_PCH_SPLIT(dev))
81255565
JB		 1901 /* must disable */
1902 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1903
5eddb70b 1904 I915_WRITE(reg, dspcntr);
81255565 1905
05394f39 1906 Start = obj->gtt_offset;
81255565
JB		 1907 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1908
4e6cfefc
CW		 1909 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1910 Start, Offset, x, y, fb->pitch);
5eddb70b 1911 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
a6c45cf0 1912 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 1913 I915_WRITE(DSPSURF(plane), Start);
1914 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1915 I915_WRITE(DSPADDR(plane), Offset);
1916 } else
1917 I915_WRITE(DSPADDR(plane), Start + Offset);
1918 POSTING_READ(reg);
81255565 1919
bed4a673 1920 intel_update_fbc(dev);
3dec0095 1921 intel_increase_pllclock(crtc);
81255565
JB		 1922
1923 return 0;
1924}
1925
5c3b82e2 1926static int
3c4fdcfb
KH		 1927intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1928 struct drm_framebuffer *old_fb)
79e53945
JB		 1929{
1930 struct drm_device *dev = crtc->dev;
79e53945
JB		 1931 struct drm_i915_master_private *master_priv;
1932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 1933 int ret;
79e53945
JB		 1934
1935 /* no fb bound */
1936 if (!crtc->fb) {
28c97730 1937 DRM_DEBUG_KMS("No FB bound\n");
5c3b82e2
CW		 1938 return 0;
1939 }
1940
265db958 1941 switch (intel_crtc->plane) {
5c3b82e2
CW		 1942 case 0:
1943 case 1:
1944 break;
1945 default:
5c3b82e2 1946 return -EINVAL;
79e53945
JB		 1947 }
1948
5c3b82e2 1949 mutex_lock(&dev->struct_mutex);
265db958
CW		 1950 ret = intel_pin_and_fence_fb_obj(dev,
1951 to_intel_framebuffer(crtc->fb)->obj,
919926ae 1952 NULL);
5c3b82e2
CW		 1953 if (ret != 0) {
1954 mutex_unlock(&dev->struct_mutex);
1955 return ret;
1956 }
79e53945 1957
265db958 1958 if (old_fb) {
e6c3a2a6 1959 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1960 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 1961
e6c3a2a6 1962 wait_event(dev_priv->pending_flip_queue,
01eec727 1963 atomic_read(&dev_priv->mm.wedged) ||
05394f39 1964 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 1965
1966 /* Big Hammer, we also need to ensure that any pending
1967 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1968 * current scanout is retired before unpinning the old
1969 * framebuffer.
01eec727
CW		 1970 *
1971 * This should only fail upon a hung GPU, in which case we
1972 * can safely continue.
85345517 1973 */
a8198eea 1974 ret = i915_gem_object_finish_gpu(obj);
01eec727 1975 (void) ret;
265db958
CW		 1976 }
1977
21c74a8e
JW		 1978 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1979 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 1980 if (ret) {
265db958 1981 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 1982 mutex_unlock(&dev->struct_mutex);
4e6cfefc 1983 return ret;
79e53945 1984 }
3c4fdcfb 1985
b7f1de28
CW		 1986 if (old_fb) {
1987 intel_wait_for_vblank(dev, intel_crtc->pipe);
265db958 1988 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
b7f1de28 1989 }
652c393a 1990
5c3b82e2 1991 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 1992
1993 if (!dev->primary->master)
5c3b82e2 1994 return 0;
79e53945
JB		 1995
1996 master_priv = dev->primary->master->driver_priv;
1997 if (!master_priv->sarea_priv)
5c3b82e2 1998 return 0;
79e53945 1999
265db958 2000 if (intel_crtc->pipe) {
79e53945
JB		 2001 master_priv->sarea_priv->pipeB_x = x;
2002 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2003 } else {
2004 master_priv->sarea_priv->pipeA_x = x;
2005 master_priv->sarea_priv->pipeA_y = y;
79e53945 2006 }
5c3b82e2
CW		 2007
2008 return 0;
79e53945
JB		 2009}
2010
5eddb70b 2011static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2012{
2013 struct drm_device *dev = crtc->dev;
2014 struct drm_i915_private *dev_priv = dev->dev_private;
2015 u32 dpa_ctl;
2016
28c97730 2017 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2018 dpa_ctl = I915_READ(DP_A);
2019 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2020
2021 if (clock < 200000) {
2022 u32 temp;
2023 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2024 /* workaround for 160Mhz:
2025 1) program 0x4600c bits 15:0 = 0x8124
2026 2) program 0x46010 bit 0 = 1
2027 3) program 0x46034 bit 24 = 1
2028 4) program 0x64000 bit 14 = 1
2029 */
2030 temp = I915_READ(0x4600c);
2031 temp &= 0xffff0000;
2032 I915_WRITE(0x4600c, temp | 0x8124);
2033
2034 temp = I915_READ(0x46010);
2035 I915_WRITE(0x46010, temp | 1);
2036
2037 temp = I915_READ(0x46034);
2038 I915_WRITE(0x46034, temp | (1 << 24));
2039 } else {
2040 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2041 }
2042 I915_WRITE(DP_A, dpa_ctl);
2043
5eddb70b 2044 POSTING_READ(DP_A);
32f9d658
ZW		 2045 udelay(500);
2046}
2047
5e84e1a4
ZW		 2048static void intel_fdi_normal_train(struct drm_crtc *crtc)
2049{
2050 struct drm_device *dev = crtc->dev;
2051 struct drm_i915_private *dev_priv = dev->dev_private;
2052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2053 int pipe = intel_crtc->pipe;
2054 u32 reg, temp;
2055
2056 /* enable normal train */
2057 reg = FDI_TX_CTL(pipe);
2058 temp = I915_READ(reg);
61e499bf 2059 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2060 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2061 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2062 } else {
2063 temp &= ~FDI_LINK_TRAIN_NONE;
2064 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2065 }
5e84e1a4
ZW		 2066 I915_WRITE(reg, temp);
2067
2068 reg = FDI_RX_CTL(pipe);
2069 temp = I915_READ(reg);
2070 if (HAS_PCH_CPT(dev)) {
2071 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2072 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2073 } else {
2074 temp &= ~FDI_LINK_TRAIN_NONE;
2075 temp |= FDI_LINK_TRAIN_NONE;
2076 }
2077 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2078
2079 /* wait one idle pattern time */
2080 POSTING_READ(reg);
2081 udelay(1000);
357555c0
JB		 2082
2083 /* IVB wants error correction enabled */
2084 if (IS_IVYBRIDGE(dev))
2085 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2086 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2087}
2088
8db9d77b
ZW		 2089/* The FDI link training functions for ILK/Ibexpeak. */
2090static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2091{
2092 struct drm_device *dev = crtc->dev;
2093 struct drm_i915_private *dev_priv = dev->dev_private;
2094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2095 int pipe = intel_crtc->pipe;
0fc932b8 2096 int plane = intel_crtc->plane;
5eddb70b 2097 u32 reg, temp, tries;
8db9d77b 2098
0fc932b8
JB		 2099 /* FDI needs bits from pipe & plane first */
2100 assert_pipe_enabled(dev_priv, pipe);
2101 assert_plane_enabled(dev_priv, plane);
2102
e1a44743
AJ		 2103 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2104 for train result */
5eddb70b
CW		 2105 reg = FDI_RX_IMR(pipe);
2106 temp = I915_READ(reg);
e1a44743
AJ		 2107 temp &= ~FDI_RX_SYMBOL_LOCK;
2108 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2109 I915_WRITE(reg, temp);
2110 I915_READ(reg);
e1a44743
AJ		 2111 udelay(150);
2112
8db9d77b 2113 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2114 reg = FDI_TX_CTL(pipe);
2115 temp = I915_READ(reg);
77ffb597
AJ		 2116 temp &= ~(7 << 19);
2117 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2118 temp &= ~FDI_LINK_TRAIN_NONE;
2119 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2120 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2121
5eddb70b
CW		 2122 reg = FDI_RX_CTL(pipe);
2123 temp = I915_READ(reg);
8db9d77b
ZW		 2124 temp &= ~FDI_LINK_TRAIN_NONE;
2125 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2126 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2127
2128 POSTING_READ(reg);
8db9d77b
ZW		 2129 udelay(150);
2130
5b2adf89 2131 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2132 if (HAS_PCH_IBX(dev)) {
2133 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2134 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2135 FDI_RX_PHASE_SYNC_POINTER_EN);
2136 }
5b2adf89 2137
5eddb70b 2138 reg = FDI_RX_IIR(pipe);
e1a44743 2139 for (tries = 0; tries < 5; tries++) {
5eddb70b 2140 temp = I915_READ(reg);
8db9d77b
ZW		 2141 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2142
2143 if ((temp & FDI_RX_BIT_LOCK)) {
2144 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2145 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2146 break;
2147 }
8db9d77b 2148 }
e1a44743 2149 if (tries == 5)
5eddb70b 2150 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2151
2152 /* Train 2 */
5eddb70b
CW		 2153 reg = FDI_TX_CTL(pipe);
2154 temp = I915_READ(reg);
8db9d77b
ZW		 2155 temp &= ~FDI_LINK_TRAIN_NONE;
2156 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2157 I915_WRITE(reg, temp);
8db9d77b 2158
5eddb70b
CW		 2159 reg = FDI_RX_CTL(pipe);
2160 temp = I915_READ(reg);
8db9d77b
ZW		 2161 temp &= ~FDI_LINK_TRAIN_NONE;
2162 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2163 I915_WRITE(reg, temp);
8db9d77b 2164
5eddb70b
CW		 2165 POSTING_READ(reg);
2166 udelay(150);
8db9d77b 2167
5eddb70b 2168 reg = FDI_RX_IIR(pipe);
e1a44743 2169 for (tries = 0; tries < 5; tries++) {
5eddb70b 2170 temp = I915_READ(reg);
8db9d77b
ZW		 2171 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2172
2173 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2174 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2175 DRM_DEBUG_KMS("FDI train 2 done.\n");
2176 break;
2177 }
8db9d77b 2178 }
e1a44743 2179 if (tries == 5)
5eddb70b 2180 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2181
2182 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2183
8db9d77b
ZW		 2184}
2185
311bd68e 2186static const int snb_b_fdi_train_param [] = {
8db9d77b
ZW		 2187 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2188 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2189 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2190 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2191};
2192
2193/* The FDI link training functions for SNB/Cougarpoint. */
2194static void gen6_fdi_link_train(struct drm_crtc *crtc)
2195{
2196 struct drm_device *dev = crtc->dev;
2197 struct drm_i915_private *dev_priv = dev->dev_private;
2198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2199 int pipe = intel_crtc->pipe;
5eddb70b 2200 u32 reg, temp, i;
8db9d77b 2201
e1a44743
AJ		 2202 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2203 for train result */
5eddb70b
CW		 2204 reg = FDI_RX_IMR(pipe);
2205 temp = I915_READ(reg);
e1a44743
AJ		 2206 temp &= ~FDI_RX_SYMBOL_LOCK;
2207 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2208 I915_WRITE(reg, temp);
2209
2210 POSTING_READ(reg);
e1a44743
AJ		 2211 udelay(150);
2212
8db9d77b 2213 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2214 reg = FDI_TX_CTL(pipe);
2215 temp = I915_READ(reg);
77ffb597
AJ		 2216 temp &= ~(7 << 19);
2217 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2218 temp &= ~FDI_LINK_TRAIN_NONE;
2219 temp |= FDI_LINK_TRAIN_PATTERN_1;
2220 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2221 /* SNB-B */
2222 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2223 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2224
5eddb70b
CW		 2225 reg = FDI_RX_CTL(pipe);
2226 temp = I915_READ(reg);
8db9d77b
ZW		 2227 if (HAS_PCH_CPT(dev)) {
2228 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2229 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2230 } else {
2231 temp &= ~FDI_LINK_TRAIN_NONE;
2232 temp |= FDI_LINK_TRAIN_PATTERN_1;
2233 }
5eddb70b
CW		 2234 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2235
2236 POSTING_READ(reg);
8db9d77b
ZW		 2237 udelay(150);
2238
8db9d77b 2239 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2240 reg = FDI_TX_CTL(pipe);
2241 temp = I915_READ(reg);
8db9d77b
ZW		 2242 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2243 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2244 I915_WRITE(reg, temp);
2245
2246 POSTING_READ(reg);
8db9d77b
ZW		 2247 udelay(500);
2248
5eddb70b
CW		 2249 reg = FDI_RX_IIR(pipe);
2250 temp = I915_READ(reg);
8db9d77b
ZW		 2251 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2252
2253 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2254 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2255 DRM_DEBUG_KMS("FDI train 1 done.\n");
2256 break;
2257 }
2258 }
2259 if (i == 4)
5eddb70b 2260 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2261
2262 /* Train 2 */
5eddb70b
CW		 2263 reg = FDI_TX_CTL(pipe);
2264 temp = I915_READ(reg);
8db9d77b
ZW		 2265 temp &= ~FDI_LINK_TRAIN_NONE;
2266 temp |= FDI_LINK_TRAIN_PATTERN_2;
2267 if (IS_GEN6(dev)) {
2268 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2269 /* SNB-B */
2270 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2271 }
5eddb70b 2272 I915_WRITE(reg, temp);
8db9d77b 2273
5eddb70b
CW		 2274 reg = FDI_RX_CTL(pipe);
2275 temp = I915_READ(reg);
8db9d77b
ZW		 2276 if (HAS_PCH_CPT(dev)) {
2277 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2278 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2279 } else {
2280 temp &= ~FDI_LINK_TRAIN_NONE;
2281 temp |= FDI_LINK_TRAIN_PATTERN_2;
2282 }
5eddb70b
CW		 2283 I915_WRITE(reg, temp);
2284
2285 POSTING_READ(reg);
8db9d77b
ZW		 2286 udelay(150);
2287
2288 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2289 reg = FDI_TX_CTL(pipe);
2290 temp = I915_READ(reg);
8db9d77b
ZW		 2291 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2292 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2293 I915_WRITE(reg, temp);
2294
2295 POSTING_READ(reg);
8db9d77b
ZW		 2296 udelay(500);
2297
5eddb70b
CW		 2298 reg = FDI_RX_IIR(pipe);
2299 temp = I915_READ(reg);
8db9d77b
ZW		 2300 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2301
2302 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2303 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2304 DRM_DEBUG_KMS("FDI train 2 done.\n");
2305 break;
2306 }
2307 }
2308 if (i == 4)
5eddb70b 2309 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2310
2311 DRM_DEBUG_KMS("FDI train done.\n");
2312}
2313
357555c0
JB		 2314/* Manual link training for Ivy Bridge A0 parts */
2315static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2316{
2317 struct drm_device *dev = crtc->dev;
2318 struct drm_i915_private *dev_priv = dev->dev_private;
2319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2320 int pipe = intel_crtc->pipe;
2321 u32 reg, temp, i;
2322
2323 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2324 for train result */
2325 reg = FDI_RX_IMR(pipe);
2326 temp = I915_READ(reg);
2327 temp &= ~FDI_RX_SYMBOL_LOCK;
2328 temp &= ~FDI_RX_BIT_LOCK;
2329 I915_WRITE(reg, temp);
2330
2331 POSTING_READ(reg);
2332 udelay(150);
2333
2334 /* enable CPU FDI TX and PCH FDI RX */
2335 reg = FDI_TX_CTL(pipe);
2336 temp = I915_READ(reg);
2337 temp &= ~(7 << 19);
2338 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2339 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2340 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2341 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2342 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2343 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2344
2345 reg = FDI_RX_CTL(pipe);
2346 temp = I915_READ(reg);
2347 temp &= ~FDI_LINK_TRAIN_AUTO;
2348 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2349 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2350 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2351
2352 POSTING_READ(reg);
2353 udelay(150);
2354
2355 for (i = 0; i < 4; i++ ) {
2356 reg = FDI_TX_CTL(pipe);
2357 temp = I915_READ(reg);
2358 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2359 temp |= snb_b_fdi_train_param[i];
2360 I915_WRITE(reg, temp);
2361
2362 POSTING_READ(reg);
2363 udelay(500);
2364
2365 reg = FDI_RX_IIR(pipe);
2366 temp = I915_READ(reg);
2367 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2368
2369 if (temp & FDI_RX_BIT_LOCK ||
2370 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2371 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2372 DRM_DEBUG_KMS("FDI train 1 done.\n");
2373 break;
2374 }
2375 }
2376 if (i == 4)
2377 DRM_ERROR("FDI train 1 fail!\n");
2378
2379 /* Train 2 */
2380 reg = FDI_TX_CTL(pipe);
2381 temp = I915_READ(reg);
2382 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2383 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2384 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2385 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2386 I915_WRITE(reg, temp);
2387
2388 reg = FDI_RX_CTL(pipe);
2389 temp = I915_READ(reg);
2390 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2391 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2392 I915_WRITE(reg, temp);
2393
2394 POSTING_READ(reg);
2395 udelay(150);
2396
2397 for (i = 0; i < 4; i++ ) {
2398 reg = FDI_TX_CTL(pipe);
2399 temp = I915_READ(reg);
2400 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2401 temp |= snb_b_fdi_train_param[i];
2402 I915_WRITE(reg, temp);
2403
2404 POSTING_READ(reg);
2405 udelay(500);
2406
2407 reg = FDI_RX_IIR(pipe);
2408 temp = I915_READ(reg);
2409 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2410
2411 if (temp & FDI_RX_SYMBOL_LOCK) {
2412 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2413 DRM_DEBUG_KMS("FDI train 2 done.\n");
2414 break;
2415 }
2416 }
2417 if (i == 4)
2418 DRM_ERROR("FDI train 2 fail!\n");
2419
2420 DRM_DEBUG_KMS("FDI train done.\n");
2421}
2422
2423static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2424{
2425 struct drm_device *dev = crtc->dev;
2426 struct drm_i915_private *dev_priv = dev->dev_private;
2427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2428 int pipe = intel_crtc->pipe;
5eddb70b 2429 u32 reg, temp;
79e53945 2430
c64e311e 2431 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2432 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2433 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2434
c98e9dcf 2435 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
2438 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2439 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2440 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2441 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2442
2443 POSTING_READ(reg);
c98e9dcf
JB		 2444 udelay(200);
2445
2446 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2447 temp = I915_READ(reg);
2448 I915_WRITE(reg, temp | FDI_PCDCLK);
2449
2450 POSTING_READ(reg);
c98e9dcf
JB		 2451 udelay(200);
2452
2453 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2454 reg = FDI_TX_CTL(pipe);
2455 temp = I915_READ(reg);
c98e9dcf 2456 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2457 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2458
2459 POSTING_READ(reg);
c98e9dcf 2460 udelay(100);
6be4a607 2461 }
0e23b99d
JB		 2462}
2463
0fc932b8
JB		 2464static void ironlake_fdi_disable(struct drm_crtc *crtc)
2465{
2466 struct drm_device *dev = crtc->dev;
2467 struct drm_i915_private *dev_priv = dev->dev_private;
2468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2469 int pipe = intel_crtc->pipe;
2470 u32 reg, temp;
2471
2472 /* disable CPU FDI tx and PCH FDI rx */
2473 reg = FDI_TX_CTL(pipe);
2474 temp = I915_READ(reg);
2475 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2476 POSTING_READ(reg);
2477
2478 reg = FDI_RX_CTL(pipe);
2479 temp = I915_READ(reg);
2480 temp &= ~(0x7 << 16);
2481 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2482 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2483
2484 POSTING_READ(reg);
2485 udelay(100);
2486
2487 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2488 if (HAS_PCH_IBX(dev)) {
2489 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2490 I915_WRITE(FDI_RX_CHICKEN(pipe),
2491 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18
JB		 2492 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2493 }
0fc932b8
JB		 2494
2495 /* still set train pattern 1 */
2496 reg = FDI_TX_CTL(pipe);
2497 temp = I915_READ(reg);
2498 temp &= ~FDI_LINK_TRAIN_NONE;
2499 temp |= FDI_LINK_TRAIN_PATTERN_1;
2500 I915_WRITE(reg, temp);
2501
2502 reg = FDI_RX_CTL(pipe);
2503 temp = I915_READ(reg);
2504 if (HAS_PCH_CPT(dev)) {
2505 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2506 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2507 } else {
2508 temp &= ~FDI_LINK_TRAIN_NONE;
2509 temp |= FDI_LINK_TRAIN_PATTERN_1;
2510 }
2511 /* BPC in FDI rx is consistent with that in PIPECONF */
2512 temp &= ~(0x07 << 16);
2513 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2514 I915_WRITE(reg, temp);
2515
2516 POSTING_READ(reg);
2517 udelay(100);
2518}
2519
6b383a7f
CW		 2520/*
2521 * When we disable a pipe, we need to clear any pending scanline wait events
2522 * to avoid hanging the ring, which we assume we are waiting on.
2523 */
2524static void intel_clear_scanline_wait(struct drm_device *dev)
2525{
2526 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2527 struct intel_ring_buffer *ring;
6b383a7f
CW		 2528 u32 tmp;
2529
2530 if (IS_GEN2(dev))
2531 /* Can't break the hang on i8xx */
2532 return;
2533
1ec14ad3 2534 ring = LP_RING(dev_priv);
8168bd48
CW		 2535 tmp = I915_READ_CTL(ring);
2536 if (tmp & RING_WAIT)
2537 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2538}
2539
e6c3a2a6
CW		 2540static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2541{
05394f39 2542 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2543 struct drm_i915_private *dev_priv;
2544
2545 if (crtc->fb == NULL)
2546 return;
2547
05394f39 2548 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2549 dev_priv = crtc->dev->dev_private;
2550 wait_event(dev_priv->pending_flip_queue,
05394f39 2551 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2552}
2553
040484af
JB		 2554static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2555{
2556 struct drm_device *dev = crtc->dev;
2557 struct drm_mode_config *mode_config = &dev->mode_config;
2558 struct intel_encoder *encoder;
2559
2560 /*
2561 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2562 * must be driven by its own crtc; no sharing is possible.
2563 */
2564 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2565 if (encoder->base.crtc != crtc)
2566 continue;
2567
2568 switch (encoder->type) {
2569 case INTEL_OUTPUT_EDP:
2570 if (!intel_encoder_is_pch_edp(&encoder->base))
2571 return false;
2572 continue;
2573 }
2574 }
2575
2576 return true;
2577}
2578
f67a559d
JB		 2579/*
2580 * Enable PCH resources required for PCH ports:
2581 * - PCH PLLs
2582 * - FDI training & RX/TX
2583 * - update transcoder timings
2584 * - DP transcoding bits
2585 * - transcoder
2586 */
2587static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2588{
2589 struct drm_device *dev = crtc->dev;
2590 struct drm_i915_private *dev_priv = dev->dev_private;
2591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2592 int pipe = intel_crtc->pipe;
5eddb70b 2593 u32 reg, temp;
2c07245f 2594
c98e9dcf 2595 /* For PCH output, training FDI link */
674cf967 2596 dev_priv->display.fdi_link_train(crtc);
2c07245f 2597
92f2584a 2598 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2599
c98e9dcf
JB		 2600 if (HAS_PCH_CPT(dev)) {
2601 /* Be sure PCH DPLL SEL is set */
2602 temp = I915_READ(PCH_DPLL_SEL);
5eddb70b 2603 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
c98e9dcf 2604 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
5eddb70b 2605 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
c98e9dcf
JB		 2606 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2607 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2608 }
5eddb70b 2609
d9b6cb56
JB		 2610 /* set transcoder timing, panel must allow it */
2611 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2612 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2613 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2614 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2615
5eddb70b
CW		 2616 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2617 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2618 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2619
5e84e1a4
ZW		 2620 intel_fdi_normal_train(crtc);
2621
c98e9dcf
JB		 2622 /* For PCH DP, enable TRANS_DP_CTL */
2623 if (HAS_PCH_CPT(dev) &&
2624 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5eddb70b
CW		 2625 reg = TRANS_DP_CTL(pipe);
2626 temp = I915_READ(reg);
2627 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2628 TRANS_DP_SYNC_MASK |
2629 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2630 temp |= (TRANS_DP_OUTPUT_ENABLE |
2631 TRANS_DP_ENH_FRAMING);
220cad3c 2632 temp |= TRANS_DP_8BPC;
c98e9dcf
JB		 2633
2634 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2635 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2636 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2637 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2638
2639 switch (intel_trans_dp_port_sel(crtc)) {
2640 case PCH_DP_B:
5eddb70b 2641 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2642 break;
2643 case PCH_DP_C:
5eddb70b 2644 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2645 break;
2646 case PCH_DP_D:
5eddb70b 2647 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2648 break;
2649 default:
2650 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2651 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2652 break;
32f9d658 2653 }
2c07245f 2654
5eddb70b 2655 I915_WRITE(reg, temp);
6be4a607 2656 }
b52eb4dc 2657
040484af 2658 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2659}
2660
2661static void ironlake_crtc_enable(struct drm_crtc *crtc)
2662{
2663 struct drm_device *dev = crtc->dev;
2664 struct drm_i915_private *dev_priv = dev->dev_private;
2665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2666 int pipe = intel_crtc->pipe;
2667 int plane = intel_crtc->plane;
2668 u32 temp;
2669 bool is_pch_port;
2670
2671 if (intel_crtc->active)
2672 return;
2673
2674 intel_crtc->active = true;
2675 intel_update_watermarks(dev);
2676
2677 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2678 temp = I915_READ(PCH_LVDS);
2679 if ((temp & LVDS_PORT_EN) == 0)
2680 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2681 }
2682
2683 is_pch_port = intel_crtc_driving_pch(crtc);
2684
2685 if (is_pch_port)
357555c0 2686 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 2687 else
2688 ironlake_fdi_disable(crtc);
2689
2690 /* Enable panel fitting for LVDS */
2691 if (dev_priv->pch_pf_size &&
2692 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2693 /* Force use of hard-coded filter coefficients
2694 * as some pre-programmed values are broken,
2695 * e.g. x201.
2696 */
9db4a9c7
JB		 2697 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2698 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2699 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 2700 }
2701
2702 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2703 intel_enable_plane(dev_priv, plane, pipe);
2704
2705 if (is_pch_port)
2706 ironlake_pch_enable(crtc);
c98e9dcf 2707
6be4a607 2708 intel_crtc_load_lut(crtc);
d1ebd816
BW		 2709
2710 mutex_lock(&dev->struct_mutex);
bed4a673 2711 intel_update_fbc(dev);
d1ebd816
BW		 2712 mutex_unlock(&dev->struct_mutex);
2713
6b383a7f 2714 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 2715}
2716
2717static void ironlake_crtc_disable(struct drm_crtc *crtc)
2718{
2719 struct drm_device *dev = crtc->dev;
2720 struct drm_i915_private *dev_priv = dev->dev_private;
2721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2722 int pipe = intel_crtc->pipe;
2723 int plane = intel_crtc->plane;
5eddb70b 2724 u32 reg, temp;
b52eb4dc 2725
f7abfe8b
CW		 2726 if (!intel_crtc->active)
2727 return;
2728
e6c3a2a6 2729 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 2730 drm_vblank_off(dev, pipe);
6b383a7f 2731 intel_crtc_update_cursor(crtc, false);
5eddb70b 2732
b24e7179 2733 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 2734
6be4a607
JB		 2735 if (dev_priv->cfb_plane == plane &&
2736 dev_priv->display.disable_fbc)
2737 dev_priv->display.disable_fbc(dev);
2c07245f 2738
b24e7179 2739 intel_disable_pipe(dev_priv, pipe);
32f9d658 2740
6be4a607 2741 /* Disable PF */
9db4a9c7
JB		 2742 I915_WRITE(PF_CTL(pipe), 0);
2743 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 2744
0fc932b8 2745 ironlake_fdi_disable(crtc);
2c07245f 2746
47a05eca
JB		 2747 /* This is a horrible layering violation; we should be doing this in
2748 * the connector/encoder ->prepare instead, but we don't always have
2749 * enough information there about the config to know whether it will
2750 * actually be necessary or just cause undesired flicker.
2751 */
2752 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 2753
040484af 2754 intel_disable_transcoder(dev_priv, pipe);
913d8d11 2755
6be4a607
JB		 2756 if (HAS_PCH_CPT(dev)) {
2757 /* disable TRANS_DP_CTL */
5eddb70b
CW		 2758 reg = TRANS_DP_CTL(pipe);
2759 temp = I915_READ(reg);
2760 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 2761 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 2762 I915_WRITE(reg, temp);
6be4a607
JB		 2763
2764 /* disable DPLL_SEL */
2765 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 2766 switch (pipe) {
2767 case 0:
2768 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2769 break;
2770 case 1:
6be4a607 2771 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 2772 break;
2773 case 2:
2774 /* FIXME: manage transcoder PLLs? */
2775 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2776 break;
2777 default:
2778 BUG(); /* wtf */
2779 }
6be4a607 2780 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 2781 }
e3421a18 2782
6be4a607 2783 /* disable PCH DPLL */
92f2584a 2784 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 2785
6be4a607 2786 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 2787 reg = FDI_RX_CTL(pipe);
2788 temp = I915_READ(reg);
2789 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 2790
6be4a607 2791 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 2792 reg = FDI_TX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2795
2796 POSTING_READ(reg);
6be4a607 2797 udelay(100);
8db9d77b 2798
5eddb70b
CW		 2799 reg = FDI_RX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 2802
6be4a607 2803 /* Wait for the clocks to turn off. */
5eddb70b 2804 POSTING_READ(reg);
6be4a607 2805 udelay(100);
6b383a7f 2806
f7abfe8b 2807 intel_crtc->active = false;
6b383a7f 2808 intel_update_watermarks(dev);
d1ebd816
BW		 2809
2810 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 2811 intel_update_fbc(dev);
2812 intel_clear_scanline_wait(dev);
d1ebd816 2813 mutex_unlock(&dev->struct_mutex);
6be4a607 2814}
1b3c7a47 2815
6be4a607
JB		 2816static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2817{
2818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2819 int pipe = intel_crtc->pipe;
2820 int plane = intel_crtc->plane;
8db9d77b 2821
6be4a607
JB		 2822 /* XXX: When our outputs are all unaware of DPMS modes other than off
2823 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2824 */
2825 switch (mode) {
2826 case DRM_MODE_DPMS_ON:
2827 case DRM_MODE_DPMS_STANDBY:
2828 case DRM_MODE_DPMS_SUSPEND:
2829 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2830 ironlake_crtc_enable(crtc);
2831 break;
1b3c7a47 2832
6be4a607
JB		 2833 case DRM_MODE_DPMS_OFF:
2834 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2835 ironlake_crtc_disable(crtc);
2c07245f
ZW		 2836 break;
2837 }
2838}
2839
02e792fb
DV		 2840static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2841{
02e792fb 2842 if (!enable && intel_crtc->overlay) {
23f09ce3 2843 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 2844 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 2845
23f09ce3 2846 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 2847 dev_priv->mm.interruptible = false;
2848 (void) intel_overlay_switch_off(intel_crtc->overlay);
2849 dev_priv->mm.interruptible = true;
23f09ce3 2850 mutex_unlock(&dev->struct_mutex);
02e792fb 2851 }
02e792fb 2852
5dcdbcb0
CW		 2853 /* Let userspace switch the overlay on again. In most cases userspace
2854 * has to recompute where to put it anyway.
2855 */
02e792fb
DV		 2856}
2857
0b8765c6 2858static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 2859{
2860 struct drm_device *dev = crtc->dev;
79e53945
JB		 2861 struct drm_i915_private *dev_priv = dev->dev_private;
2862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2863 int pipe = intel_crtc->pipe;
80824003 2864 int plane = intel_crtc->plane;
79e53945 2865
f7abfe8b
CW		 2866 if (intel_crtc->active)
2867 return;
2868
2869 intel_crtc->active = true;
6b383a7f
CW		 2870 intel_update_watermarks(dev);
2871
63d7bbe9 2872 intel_enable_pll(dev_priv, pipe);
040484af 2873 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 2874 intel_enable_plane(dev_priv, plane, pipe);
79e53945 2875
0b8765c6 2876 intel_crtc_load_lut(crtc);
bed4a673 2877 intel_update_fbc(dev);
79e53945 2878
0b8765c6
JB		 2879 /* Give the overlay scaler a chance to enable if it's on this pipe */
2880 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 2881 intel_crtc_update_cursor(crtc, true);
0b8765c6 2882}
79e53945 2883
0b8765c6
JB		 2884static void i9xx_crtc_disable(struct drm_crtc *crtc)
2885{
2886 struct drm_device *dev = crtc->dev;
2887 struct drm_i915_private *dev_priv = dev->dev_private;
2888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2889 int pipe = intel_crtc->pipe;
2890 int plane = intel_crtc->plane;
b690e96c 2891
f7abfe8b
CW		 2892 if (!intel_crtc->active)
2893 return;
2894
0b8765c6 2895 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 2896 intel_crtc_wait_for_pending_flips(crtc);
2897 drm_vblank_off(dev, pipe);
0b8765c6 2898 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 2899 intel_crtc_update_cursor(crtc, false);
0b8765c6
JB		 2900
2901 if (dev_priv->cfb_plane == plane &&
2902 dev_priv->display.disable_fbc)
2903 dev_priv->display.disable_fbc(dev);
79e53945 2904
b24e7179 2905 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 2906 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 2907 intel_disable_pll(dev_priv, pipe);
0b8765c6 2908
f7abfe8b 2909 intel_crtc->active = false;
6b383a7f
CW		 2910 intel_update_fbc(dev);
2911 intel_update_watermarks(dev);
2912 intel_clear_scanline_wait(dev);
0b8765c6
JB		 2913}
2914
2915static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2916{
2917 /* XXX: When our outputs are all unaware of DPMS modes other than off
2918 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2919 */
2920 switch (mode) {
2921 case DRM_MODE_DPMS_ON:
2922 case DRM_MODE_DPMS_STANDBY:
2923 case DRM_MODE_DPMS_SUSPEND:
2924 i9xx_crtc_enable(crtc);
2925 break;
2926 case DRM_MODE_DPMS_OFF:
2927 i9xx_crtc_disable(crtc);
79e53945
JB		 2928 break;
2929 }
2c07245f
ZW		 2930}
2931
2932/**
2933 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 2934 */
2935static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2936{
2937 struct drm_device *dev = crtc->dev;
e70236a8 2938 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 2939 struct drm_i915_master_private *master_priv;
2940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2941 int pipe = intel_crtc->pipe;
2942 bool enabled;
2943
032d2a0d
CW		 2944 if (intel_crtc->dpms_mode == mode)
2945 return;
2946
65655d4a 2947 intel_crtc->dpms_mode = mode;
debcaddc 2948
e70236a8 2949 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 2950
2951 if (!dev->primary->master)
2952 return;
2953
2954 master_priv = dev->primary->master->driver_priv;
2955 if (!master_priv->sarea_priv)
2956 return;
2957
2958 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2959
2960 switch (pipe) {
2961 case 0:
2962 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2963 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2964 break;
2965 case 1:
2966 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2967 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2968 break;
2969 default:
9db4a9c7 2970 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 2971 break;
2972 }
79e53945
JB		 2973}
2974
cdd59983
CW		 2975static void intel_crtc_disable(struct drm_crtc *crtc)
2976{
2977 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2978 struct drm_device *dev = crtc->dev;
2979
2980 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2981
2982 if (crtc->fb) {
2983 mutex_lock(&dev->struct_mutex);
2984 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2985 mutex_unlock(&dev->struct_mutex);
2986 }
2987}
2988
7e7d76c3
JB		 2989/* Prepare for a mode set.
2990 *
2991 * Note we could be a lot smarter here. We need to figure out which outputs
2992 * will be enabled, which disabled (in short, how the config will changes)
2993 * and perform the minimum necessary steps to accomplish that, e.g. updating
2994 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2995 * panel fitting is in the proper state, etc.
2996 */
2997static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 2998{
7e7d76c3 2999 i9xx_crtc_disable(crtc);
79e53945
JB		 3000}
3001
7e7d76c3 3002static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3003{
7e7d76c3 3004 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3005}
3006
3007static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3008{
7e7d76c3 3009 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3010}
3011
3012static void ironlake_crtc_commit(struct drm_crtc *crtc)
3013{
7e7d76c3 3014 ironlake_crtc_enable(crtc);
79e53945
JB		 3015}
3016
3017void intel_encoder_prepare (struct drm_encoder *encoder)
3018{
3019 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3020 /* lvds has its own version of prepare see intel_lvds_prepare */
3021 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3022}
3023
3024void intel_encoder_commit (struct drm_encoder *encoder)
3025{
3026 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3027 /* lvds has its own version of commit see intel_lvds_commit */
3028 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3029}
3030
ea5b213a
CW		 3031void intel_encoder_destroy(struct drm_encoder *encoder)
3032{
4ef69c7a 3033 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3034
ea5b213a
CW		 3035 drm_encoder_cleanup(encoder);
3036 kfree(intel_encoder);
3037}
3038
79e53945
JB		 3039static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3040 struct drm_display_mode *mode,
3041 struct drm_display_mode *adjusted_mode)
3042{
2c07245f 3043 struct drm_device *dev = crtc->dev;
89749350 3044
bad720ff 3045 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3046 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3047 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3048 return false;
2c07245f 3049 }
89749350
CW		 3050
3051 /* XXX some encoders set the crtcinfo, others don't.
3052 * Obviously we need some form of conflict resolution here...
3053 */
3054 if (adjusted_mode->crtc_htotal == 0)
3055 drm_mode_set_crtcinfo(adjusted_mode, 0);
3056
79e53945
JB		 3057 return true;
3058}
3059
e70236a8
JB		 3060static int i945_get_display_clock_speed(struct drm_device *dev)
3061{
3062 return 400000;
3063}
79e53945 3064
e70236a8 3065static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3066{
e70236a8
JB		 3067 return 333000;
3068}
79e53945 3069
e70236a8
JB		 3070static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3071{
3072 return 200000;
3073}
79e53945 3074
e70236a8
JB		 3075static int i915gm_get_display_clock_speed(struct drm_device *dev)
3076{
3077 u16 gcfgc = 0;
79e53945 3078
e70236a8
JB		 3079 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3080
3081 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3082 return 133000;
3083 else {
3084 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3085 case GC_DISPLAY_CLOCK_333_MHZ:
3086 return 333000;
3087 default:
3088 case GC_DISPLAY_CLOCK_190_200_MHZ:
3089 return 190000;
79e53945 3090 }
e70236a8
JB		 3091 }
3092}
3093
3094static int i865_get_display_clock_speed(struct drm_device *dev)
3095{
3096 return 266000;
3097}
3098
3099static int i855_get_display_clock_speed(struct drm_device *dev)
3100{
3101 u16 hpllcc = 0;
3102 /* Assume that the hardware is in the high speed state. This
3103 * should be the default.
3104 */
3105 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3106 case GC_CLOCK_133_200:
3107 case GC_CLOCK_100_200:
3108 return 200000;
3109 case GC_CLOCK_166_250:
3110 return 250000;
3111 case GC_CLOCK_100_133:
79e53945 3112 return 133000;
e70236a8 3113 }
79e53945 3114
e70236a8
JB		 3115 /* Shouldn't happen */
3116 return 0;
3117}
79e53945 3118
e70236a8
JB		 3119static int i830_get_display_clock_speed(struct drm_device *dev)
3120{
3121 return 133000;
79e53945
JB		 3122}
3123
2c07245f
ZW		 3124struct fdi_m_n {
3125 u32 tu;
3126 u32 gmch_m;
3127 u32 gmch_n;
3128 u32 link_m;
3129 u32 link_n;
3130};
3131
3132static void
3133fdi_reduce_ratio(u32 *num, u32 *den)
3134{
3135 while (*num > 0xffffff || *den > 0xffffff) {
3136 *num >>= 1;
3137 *den >>= 1;
3138 }
3139}
3140
2c07245f 3141static void
f2b115e6
AJ		 3142ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3143 int link_clock, struct fdi_m_n *m_n)
2c07245f 3144{
2c07245f
ZW		 3145 m_n->tu = 64; /* default size */
3146
22ed1113
CW		 3147 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3148 m_n->gmch_m = bits_per_pixel * pixel_clock;
3149 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3150 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3151
22ed1113
CW		 3152 m_n->link_m = pixel_clock;
3153 m_n->link_n = link_clock;
2c07245f
ZW		 3154 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3155}
3156
3157
7662c8bd
SL		 3158struct intel_watermark_params {
3159 unsigned long fifo_size;
3160 unsigned long max_wm;
3161 unsigned long default_wm;
3162 unsigned long guard_size;
3163 unsigned long cacheline_size;
3164};
3165
f2b115e6 3166/* Pineview has different values for various configs */
d210246a 3167static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3168 PINEVIEW_DISPLAY_FIFO,
3169 PINEVIEW_MAX_WM,
3170 PINEVIEW_DFT_WM,
3171 PINEVIEW_GUARD_WM,
3172 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3173};
d210246a 3174static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3175 PINEVIEW_DISPLAY_FIFO,
3176 PINEVIEW_MAX_WM,
3177 PINEVIEW_DFT_HPLLOFF_WM,
3178 PINEVIEW_GUARD_WM,
3179 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3180};
d210246a 3181static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3182 PINEVIEW_CURSOR_FIFO,
3183 PINEVIEW_CURSOR_MAX_WM,
3184 PINEVIEW_CURSOR_DFT_WM,
3185 PINEVIEW_CURSOR_GUARD_WM,
3186 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3187};
d210246a 3188static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3189 PINEVIEW_CURSOR_FIFO,
3190 PINEVIEW_CURSOR_MAX_WM,
3191 PINEVIEW_CURSOR_DFT_WM,
3192 PINEVIEW_CURSOR_GUARD_WM,
3193 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3194};
d210246a 3195static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3196 G4X_FIFO_SIZE,
3197 G4X_MAX_WM,
3198 G4X_MAX_WM,
3199 2,
3200 G4X_FIFO_LINE_SIZE,
3201};
d210246a 3202static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3203 I965_CURSOR_FIFO,
3204 I965_CURSOR_MAX_WM,
3205 I965_CURSOR_DFT_WM,
3206 2,
3207 G4X_FIFO_LINE_SIZE,
3208};
d210246a 3209static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3210 I965_CURSOR_FIFO,
3211 I965_CURSOR_MAX_WM,
3212 I965_CURSOR_DFT_WM,
3213 2,
3214 I915_FIFO_LINE_SIZE,
3215};
d210246a 3216static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3217 I945_FIFO_SIZE,
7662c8bd
SL		 3218 I915_MAX_WM,
3219 1,
dff33cfc
JB		 3220 2,
3221 I915_FIFO_LINE_SIZE
7662c8bd 3222};
d210246a 3223static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3224 I915_FIFO_SIZE,
7662c8bd
SL		 3225 I915_MAX_WM,
3226 1,
dff33cfc 3227 2,
7662c8bd
SL		 3228 I915_FIFO_LINE_SIZE
3229};
d210246a 3230static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3231 I855GM_FIFO_SIZE,
3232 I915_MAX_WM,
3233 1,
dff33cfc 3234 2,
7662c8bd
SL		 3235 I830_FIFO_LINE_SIZE
3236};
d210246a 3237static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3238 I830_FIFO_SIZE,
3239 I915_MAX_WM,
3240 1,
dff33cfc 3241 2,
7662c8bd
SL		 3242 I830_FIFO_LINE_SIZE
3243};
3244
d210246a 3245static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3246 ILK_DISPLAY_FIFO,
3247 ILK_DISPLAY_MAXWM,
3248 ILK_DISPLAY_DFTWM,
3249 2,
3250 ILK_FIFO_LINE_SIZE
3251};
d210246a 3252static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3253 ILK_CURSOR_FIFO,
3254 ILK_CURSOR_MAXWM,
3255 ILK_CURSOR_DFTWM,
3256 2,
3257 ILK_FIFO_LINE_SIZE
3258};
d210246a 3259static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3260 ILK_DISPLAY_SR_FIFO,
3261 ILK_DISPLAY_MAX_SRWM,
3262 ILK_DISPLAY_DFT_SRWM,
3263 2,
3264 ILK_FIFO_LINE_SIZE
3265};
d210246a 3266static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3267 ILK_CURSOR_SR_FIFO,
3268 ILK_CURSOR_MAX_SRWM,
3269 ILK_CURSOR_DFT_SRWM,
3270 2,
3271 ILK_FIFO_LINE_SIZE
3272};
3273
d210246a 3274static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3275 SNB_DISPLAY_FIFO,
3276 SNB_DISPLAY_MAXWM,
3277 SNB_DISPLAY_DFTWM,
3278 2,
3279 SNB_FIFO_LINE_SIZE
3280};
d210246a 3281static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3282 SNB_CURSOR_FIFO,
3283 SNB_CURSOR_MAXWM,
3284 SNB_CURSOR_DFTWM,
3285 2,
3286 SNB_FIFO_LINE_SIZE
3287};
d210246a 3288static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3289 SNB_DISPLAY_SR_FIFO,
3290 SNB_DISPLAY_MAX_SRWM,
3291 SNB_DISPLAY_DFT_SRWM,
3292 2,
3293 SNB_FIFO_LINE_SIZE
3294};
d210246a 3295static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3296 SNB_CURSOR_SR_FIFO,
3297 SNB_CURSOR_MAX_SRWM,
3298 SNB_CURSOR_DFT_SRWM,
3299 2,
3300 SNB_FIFO_LINE_SIZE
3301};
3302
3303
dff33cfc
JB		 3304/**
3305 * intel_calculate_wm - calculate watermark level
3306 * @clock_in_khz: pixel clock
3307 * @wm: chip FIFO params
3308 * @pixel_size: display pixel size
3309 * @latency_ns: memory latency for the platform
3310 *
3311 * Calculate the watermark level (the level at which the display plane will
3312 * start fetching from memory again). Each chip has a different display
3313 * FIFO size and allocation, so the caller needs to figure that out and pass
3314 * in the correct intel_watermark_params structure.
3315 *
3316 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3317 * on the pixel size. When it reaches the watermark level, it'll start
3318 * fetching FIFO line sized based chunks from memory until the FIFO fills
3319 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3320 * will occur, and a display engine hang could result.
3321 */
7662c8bd 3322static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3323 const struct intel_watermark_params *wm,
3324 int fifo_size,
7662c8bd
SL		 3325 int pixel_size,
3326 unsigned long latency_ns)
3327{
390c4dd4 3328 long entries_required, wm_size;
dff33cfc 3329
d660467c
JB		 3330 /*
3331 * Note: we need to make sure we don't overflow for various clock &
3332 * latency values.
3333 * clocks go from a few thousand to several hundred thousand.
3334 * latency is usually a few thousand
3335 */
3336 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3337 1000;
8de9b311 3338 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3339
bbb0aef5 3340 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3341
d210246a 3342 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3343
bbb0aef5 3344 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3345
390c4dd4
JB		 3346 /* Don't promote wm_size to unsigned... */
3347 if (wm_size > (long)wm->max_wm)
7662c8bd 3348 wm_size = wm->max_wm;
c3add4b6 3349 if (wm_size <= 0)
7662c8bd
SL		 3350 wm_size = wm->default_wm;
3351 return wm_size;
3352}
3353
3354struct cxsr_latency {
3355 int is_desktop;
95534263 3356 int is_ddr3;
7662c8bd
SL		 3357 unsigned long fsb_freq;
3358 unsigned long mem_freq;
3359 unsigned long display_sr;
3360 unsigned long display_hpll_disable;
3361 unsigned long cursor_sr;
3362 unsigned long cursor_hpll_disable;
3363};
3364
403c89ff 3365static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3366 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3367 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3368 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3369 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3370 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3371
3372 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3373 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3374 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3375 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3376 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3377
3378 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3379 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3380 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3381 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3382 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3383
3384 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3385 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3386 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3387 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3388 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3389
3390 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3391 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3392 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3393 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3394 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3395
3396 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3397 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3398 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3399 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3400 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3401};
3402
403c89ff
CW		 3403static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3404 int is_ddr3,
3405 int fsb,
3406 int mem)
7662c8bd 3407{
403c89ff 3408 const struct cxsr_latency *latency;
7662c8bd 3409 int i;
7662c8bd
SL		 3410
3411 if (fsb == 0 || mem == 0)
3412 return NULL;
3413
3414 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3415 latency = &cxsr_latency_table[i];
3416 if (is_desktop == latency->is_desktop &&
95534263 3417 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3418 fsb == latency->fsb_freq && mem == latency->mem_freq)
3419 return latency;
7662c8bd 3420 }
decbbcda 3421
28c97730 3422 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3423
3424 return NULL;
7662c8bd
SL		 3425}
3426
f2b115e6 3427static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3428{
3429 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3430
3431 /* deactivate cxsr */
3e33d94d 3432 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3433}
3434
bcc24fb4
JB		 3435/*
3436 * Latency for FIFO fetches is dependent on several factors:
3437 * - memory configuration (speed, channels)
3438 * - chipset
3439 * - current MCH state
3440 * It can be fairly high in some situations, so here we assume a fairly
3441 * pessimal value. It's a tradeoff between extra memory fetches (if we
3442 * set this value too high, the FIFO will fetch frequently to stay full)
3443 * and power consumption (set it too low to save power and we might see
3444 * FIFO underruns and display "flicker").
3445 *
3446 * A value of 5us seems to be a good balance; safe for very low end
3447 * platforms but not overly aggressive on lower latency configs.
3448 */
69e302a9 3449static const int latency_ns = 5000;
7662c8bd 3450
e70236a8 3451static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3452{
3453 struct drm_i915_private *dev_priv = dev->dev_private;
3454 uint32_t dsparb = I915_READ(DSPARB);
3455 int size;
3456
8de9b311
CW		 3457 size = dsparb & 0x7f;
3458 if (plane)
3459 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3460
28c97730 3461 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3462 plane ? "B" : "A", size);
dff33cfc
JB		 3463
3464 return size;
3465}
7662c8bd 3466
e70236a8
JB		 3467static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3468{
3469 struct drm_i915_private *dev_priv = dev->dev_private;
3470 uint32_t dsparb = I915_READ(DSPARB);
3471 int size;
3472
8de9b311
CW		 3473 size = dsparb & 0x1ff;
3474 if (plane)
3475 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3476 size >>= 1; /* Convert to cachelines */
dff33cfc 3477
28c97730 3478 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3479 plane ? "B" : "A", size);
dff33cfc
JB		 3480
3481 return size;
3482}
7662c8bd 3483
e70236a8
JB		 3484static int i845_get_fifo_size(struct drm_device *dev, int plane)
3485{
3486 struct drm_i915_private *dev_priv = dev->dev_private;
3487 uint32_t dsparb = I915_READ(DSPARB);
3488 int size;
3489
3490 size = dsparb & 0x7f;
3491 size >>= 2; /* Convert to cachelines */
3492
28c97730 3493 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3494 plane ? "B" : "A",
3495 size);
e70236a8
JB		 3496
3497 return size;
3498}
3499
3500static int i830_get_fifo_size(struct drm_device *dev, int plane)
3501{
3502 struct drm_i915_private *dev_priv = dev->dev_private;
3503 uint32_t dsparb = I915_READ(DSPARB);
3504 int size;
3505
3506 size = dsparb & 0x7f;
3507 size >>= 1; /* Convert to cachelines */
3508
28c97730 3509 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3510 plane ? "B" : "A", size);
e70236a8
JB		 3511
3512 return size;
3513}
3514
d210246a
CW		 3515static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3516{
3517 struct drm_crtc *crtc, *enabled = NULL;
3518
3519 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3520 if (crtc->enabled && crtc->fb) {
3521 if (enabled)
3522 return NULL;
3523 enabled = crtc;
3524 }
3525 }
3526
3527 return enabled;
3528}
3529
3530static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3531{
3532 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3533 struct drm_crtc *crtc;
403c89ff 3534 const struct cxsr_latency *latency;
d4294342
ZY		 3535 u32 reg;
3536 unsigned long wm;
d4294342 3537
403c89ff 3538 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3539 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3540 if (!latency) {
3541 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3542 pineview_disable_cxsr(dev);
3543 return;
3544 }
3545
d210246a
CW		 3546 crtc = single_enabled_crtc(dev);
3547 if (crtc) {
3548 int clock = crtc->mode.clock;
3549 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3550
3551 /* Display SR */
d210246a
CW		 3552 wm = intel_calculate_wm(clock, &pineview_display_wm,
3553 pineview_display_wm.fifo_size,
d4294342
ZY		 3554 pixel_size, latency->display_sr);
3555 reg = I915_READ(DSPFW1);
3556 reg &= ~DSPFW_SR_MASK;
3557 reg |= wm << DSPFW_SR_SHIFT;
3558 I915_WRITE(DSPFW1, reg);
3559 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3560
3561 /* cursor SR */
d210246a
CW		 3562 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3563 pineview_display_wm.fifo_size,
d4294342
ZY		 3564 pixel_size, latency->cursor_sr);
3565 reg = I915_READ(DSPFW3);
3566 reg &= ~DSPFW_CURSOR_SR_MASK;
3567 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3568 I915_WRITE(DSPFW3, reg);
3569
3570 /* Display HPLL off SR */
d210246a
CW		 3571 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3572 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3573 pixel_size, latency->display_hpll_disable);
3574 reg = I915_READ(DSPFW3);
3575 reg &= ~DSPFW_HPLL_SR_MASK;
3576 reg |= wm & DSPFW_HPLL_SR_MASK;
3577 I915_WRITE(DSPFW3, reg);
3578
3579 /* cursor HPLL off SR */
d210246a
CW		 3580 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3581 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3582 pixel_size, latency->cursor_hpll_disable);
3583 reg = I915_READ(DSPFW3);
3584 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3585 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3586 I915_WRITE(DSPFW3, reg);
3587 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3588
3589 /* activate cxsr */
3e33d94d
CW		 3590 I915_WRITE(DSPFW3,
3591 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3592 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3593 } else {
3594 pineview_disable_cxsr(dev);
3595 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3596 }
3597}
3598
417ae147
CW		 3599static bool g4x_compute_wm0(struct drm_device *dev,
3600 int plane,
3601 const struct intel_watermark_params *display,
3602 int display_latency_ns,
3603 const struct intel_watermark_params *cursor,
3604 int cursor_latency_ns,
3605 int *plane_wm,
3606 int *cursor_wm)
3607{
3608 struct drm_crtc *crtc;
3609 int htotal, hdisplay, clock, pixel_size;
3610 int line_time_us, line_count;
3611 int entries, tlb_miss;
3612
3613 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 3614 if (crtc->fb == NULL || !crtc->enabled) {
3615 *cursor_wm = cursor->guard_size;
3616 *plane_wm = display->guard_size;
417ae147 3617 return false;
5c72d064 3618 }
417ae147
CW		 3619
3620 htotal = crtc->mode.htotal;
3621 hdisplay = crtc->mode.hdisplay;
3622 clock = crtc->mode.clock;
3623 pixel_size = crtc->fb->bits_per_pixel / 8;
3624
3625 /* Use the small buffer method to calculate plane watermark */
3626 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3627 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3628 if (tlb_miss > 0)
3629 entries += tlb_miss;
3630 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3631 *plane_wm = entries + display->guard_size;
3632 if (*plane_wm > (int)display->max_wm)
3633 *plane_wm = display->max_wm;
3634
3635 /* Use the large buffer method to calculate cursor watermark */
3636 line_time_us = ((htotal * 1000) / clock);
3637 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3638 entries = line_count * 64 * pixel_size;
3639 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3640 if (tlb_miss > 0)
3641 entries += tlb_miss;
3642 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3643 *cursor_wm = entries + cursor->guard_size;
3644 if (*cursor_wm > (int)cursor->max_wm)
3645 *cursor_wm = (int)cursor->max_wm;
3646
3647 return true;
3648}
3649
3650/*
3651 * Check the wm result.
3652 *
3653 * If any calculated watermark values is larger than the maximum value that
3654 * can be programmed into the associated watermark register, that watermark
3655 * must be disabled.
3656 */
3657static bool g4x_check_srwm(struct drm_device *dev,
3658 int display_wm, int cursor_wm,
3659 const struct intel_watermark_params *display,
3660 const struct intel_watermark_params *cursor)
652c393a 3661{
417ae147
CW		 3662 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3663 display_wm, cursor_wm);
652c393a 3664
417ae147 3665 if (display_wm > display->max_wm) {
bbb0aef5 3666 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3667 display_wm, display->max_wm);
3668 return false;
3669 }
0e442c60 3670
417ae147 3671 if (cursor_wm > cursor->max_wm) {
bbb0aef5 3672 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3673 cursor_wm, cursor->max_wm);
3674 return false;
3675 }
0e442c60 3676
417ae147
CW		 3677 if (!(display_wm || cursor_wm)) {
3678 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3679 return false;
3680 }
0e442c60 3681
417ae147
CW		 3682 return true;
3683}
0e442c60 3684
417ae147 3685static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 3686 int plane,
3687 int latency_ns,
417ae147
CW		 3688 const struct intel_watermark_params *display,
3689 const struct intel_watermark_params *cursor,
3690 int *display_wm, int *cursor_wm)
3691{
d210246a
CW		 3692 struct drm_crtc *crtc;
3693 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 3694 unsigned long line_time_us;
3695 int line_count, line_size;
3696 int small, large;
3697 int entries;
0e442c60 3698
417ae147
CW		 3699 if (!latency_ns) {
3700 *display_wm = *cursor_wm = 0;
3701 return false;
3702 }
0e442c60 3703
d210246a
CW		 3704 crtc = intel_get_crtc_for_plane(dev, plane);
3705 hdisplay = crtc->mode.hdisplay;
3706 htotal = crtc->mode.htotal;
3707 clock = crtc->mode.clock;
3708 pixel_size = crtc->fb->bits_per_pixel / 8;
3709
417ae147
CW		 3710 line_time_us = (htotal * 1000) / clock;
3711 line_count = (latency_ns / line_time_us + 1000) / 1000;
3712 line_size = hdisplay * pixel_size;
0e442c60 3713
417ae147
CW		 3714 /* Use the minimum of the small and large buffer method for primary */
3715 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3716 large = line_count * line_size;
0e442c60 3717
417ae147
CW		 3718 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3719 *display_wm = entries + display->guard_size;
4fe5e611 3720
417ae147
CW		 3721 /* calculate the self-refresh watermark for display cursor */
3722 entries = line_count * pixel_size * 64;
3723 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3724 *cursor_wm = entries + cursor->guard_size;
4fe5e611 3725
417ae147
CW		 3726 return g4x_check_srwm(dev,
3727 *display_wm, *cursor_wm,
3728 display, cursor);
3729}
4fe5e611 3730
7ccb4a53 3731#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 3732
3733static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 3734{
3735 static const int sr_latency_ns = 12000;
3736 struct drm_i915_private *dev_priv = dev->dev_private;
3737 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 3738 int plane_sr, cursor_sr;
3739 unsigned int enabled = 0;
417ae147
CW		 3740
3741 if (g4x_compute_wm0(dev, 0,
3742 &g4x_wm_info, latency_ns,
3743 &g4x_cursor_wm_info, latency_ns,
3744 &planea_wm, &cursora_wm))
d210246a 3745 enabled |= 1;
417ae147
CW		 3746
3747 if (g4x_compute_wm0(dev, 1,
3748 &g4x_wm_info, latency_ns,
3749 &g4x_cursor_wm_info, latency_ns,
3750 &planeb_wm, &cursorb_wm))
d210246a 3751 enabled |= 2;
417ae147
CW		 3752
3753 plane_sr = cursor_sr = 0;
d210246a
CW		 3754 if (single_plane_enabled(enabled) &&
3755 g4x_compute_srwm(dev, ffs(enabled) - 1,
3756 sr_latency_ns,
417ae147
CW		 3757 &g4x_wm_info,
3758 &g4x_cursor_wm_info,
3759 &plane_sr, &cursor_sr))
0e442c60 3760 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 3761 else
3762 I915_WRITE(FW_BLC_SELF,
3763 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 3764
308977ac
CW		 3765 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3766 planea_wm, cursora_wm,
3767 planeb_wm, cursorb_wm,
3768 plane_sr, cursor_sr);
0e442c60 3769
417ae147
CW		 3770 I915_WRITE(DSPFW1,
3771 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 3772 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 3773 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3774 planea_wm);
3775 I915_WRITE(DSPFW2,
3776 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 3777 (cursora_wm << DSPFW_CURSORA_SHIFT));
3778 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 3779 I915_WRITE(DSPFW3,
3780 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 3781 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 3782}
3783
d210246a 3784static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 3785{
3786 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 3787 struct drm_crtc *crtc;
3788 int srwm = 1;
4fe5e611 3789 int cursor_sr = 16;
1dc7546d
JB		 3790
3791 /* Calc sr entries for one plane configs */
d210246a
CW		 3792 crtc = single_enabled_crtc(dev);
3793 if (crtc) {
1dc7546d 3794 /* self-refresh has much higher latency */
69e302a9 3795 static const int sr_latency_ns = 12000;
d210246a
CW		 3796 int clock = crtc->mode.clock;
3797 int htotal = crtc->mode.htotal;
3798 int hdisplay = crtc->mode.hdisplay;
3799 int pixel_size = crtc->fb->bits_per_pixel / 8;
3800 unsigned long line_time_us;
3801 int entries;
1dc7546d 3802
d210246a 3803 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 3804
3805 /* Use ns/us then divide to preserve precision */
d210246a
CW		 3806 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3807 pixel_size * hdisplay;
3808 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 3809 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 3810 if (srwm < 0)
3811 srwm = 1;
1b07e04e 3812 srwm &= 0x1ff;
308977ac
CW		 3813 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3814 entries, srwm);
4fe5e611 3815
d210246a 3816 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 3817 pixel_size * 64;
d210246a 3818 entries = DIV_ROUND_UP(entries,
8de9b311 3819 i965_cursor_wm_info.cacheline_size);
4fe5e611 3820 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 3821 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 3822
3823 if (cursor_sr > i965_cursor_wm_info.max_wm)
3824 cursor_sr = i965_cursor_wm_info.max_wm;
3825
3826 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3827 "cursor %d\n", srwm, cursor_sr);
3828
a6c45cf0 3829 if (IS_CRESTLINE(dev))
adcdbc66 3830 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 3831 } else {
3832 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 3833 if (IS_CRESTLINE(dev))
adcdbc66
JB		 3834 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3835 & ~FW_BLC_SELF_EN);
1dc7546d 3836 }
7662c8bd 3837
1dc7546d
JB		 3838 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3839 srwm);
7662c8bd
SL		 3840
3841 /* 965 has limitations... */
417ae147
CW		 3842 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3843 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 3844 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 3845 /* update cursor SR watermark */
3846 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 3847}
3848
d210246a 3849static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 3850{
3851 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3852 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 3853 uint32_t fwater_lo;
3854 uint32_t fwater_hi;
d210246a
CW		 3855 int cwm, srwm = 1;
3856 int fifo_size;
dff33cfc 3857 int planea_wm, planeb_wm;
d210246a 3858 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 3859
72557b4f 3860 if (IS_I945GM(dev))
d210246a 3861 wm_info = &i945_wm_info;
a6c45cf0 3862 else if (!IS_GEN2(dev))
d210246a 3863 wm_info = &i915_wm_info;
7662c8bd 3864 else
d210246a
CW		 3865 wm_info = &i855_wm_info;
3866
3867 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3868 crtc = intel_get_crtc_for_plane(dev, 0);
3869 if (crtc->enabled && crtc->fb) {
3870 planea_wm = intel_calculate_wm(crtc->mode.clock,
3871 wm_info, fifo_size,
3872 crtc->fb->bits_per_pixel / 8,
3873 latency_ns);
3874 enabled = crtc;
3875 } else
3876 planea_wm = fifo_size - wm_info->guard_size;
3877
3878 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3879 crtc = intel_get_crtc_for_plane(dev, 1);
3880 if (crtc->enabled && crtc->fb) {
3881 planeb_wm = intel_calculate_wm(crtc->mode.clock,
3882 wm_info, fifo_size,
3883 crtc->fb->bits_per_pixel / 8,
3884 latency_ns);
3885 if (enabled == NULL)
3886 enabled = crtc;
3887 else
3888 enabled = NULL;
3889 } else
3890 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 3891
28c97730 3892 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 3893
3894 /*
3895 * Overlay gets an aggressive default since video jitter is bad.
3896 */
3897 cwm = 2;
3898
18b2190c
AL		 3899 /* Play safe and disable self-refresh before adjusting watermarks. */
3900 if (IS_I945G(dev) || IS_I945GM(dev))
3901 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3902 else if (IS_I915GM(dev))
3903 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3904
dff33cfc 3905 /* Calc sr entries for one plane configs */
d210246a 3906 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 3907 /* self-refresh has much higher latency */
69e302a9 3908 static const int sr_latency_ns = 6000;
d210246a
CW		 3909 int clock = enabled->mode.clock;
3910 int htotal = enabled->mode.htotal;
3911 int hdisplay = enabled->mode.hdisplay;
3912 int pixel_size = enabled->fb->bits_per_pixel / 8;
3913 unsigned long line_time_us;
3914 int entries;
dff33cfc 3915
d210246a 3916 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 3917
3918 /* Use ns/us then divide to preserve precision */
d210246a
CW		 3919 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3920 pixel_size * hdisplay;
3921 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
3922 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
3923 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 3924 if (srwm < 0)
3925 srwm = 1;
ee980b80
LP		 3926
3927 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 3928 I915_WRITE(FW_BLC_SELF,
3929 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3930 else if (IS_I915GM(dev))
ee980b80 3931 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 3932 }
3933
28c97730 3934 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 3935 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 3936
dff33cfc
JB		 3937 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3938 fwater_hi = (cwm & 0x1f);
3939
3940 /* Set request length to 8 cachelines per fetch */
3941 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3942 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 3943
3944 I915_WRITE(FW_BLC, fwater_lo);
3945 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 3946
d210246a
CW		 3947 if (HAS_FW_BLC(dev)) {
3948 if (enabled) {
3949 if (IS_I945G(dev) || IS_I945GM(dev))
3950 I915_WRITE(FW_BLC_SELF,
3951 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
3952 else if (IS_I915GM(dev))
3953 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3954 DRM_DEBUG_KMS("memory self refresh enabled\n");
3955 } else
3956 DRM_DEBUG_KMS("memory self refresh disabled\n");
3957 }
7662c8bd
SL		 3958}
3959
d210246a 3960static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 3961{
3962 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 3963 struct drm_crtc *crtc;
3964 uint32_t fwater_lo;
dff33cfc 3965 int planea_wm;
7662c8bd 3966
d210246a
CW		 3967 crtc = single_enabled_crtc(dev);
3968 if (crtc == NULL)
3969 return;
7662c8bd 3970
d210246a
CW		 3971 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
3972 dev_priv->display.get_fifo_size(dev, 0),
3973 crtc->fb->bits_per_pixel / 8,
3974 latency_ns);
3975 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 3976 fwater_lo |= (3<<8) | planea_wm;
3977
28c97730 3978 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 3979
3980 I915_WRITE(FW_BLC, fwater_lo);
3981}
3982
7f8a8569 3983#define ILK_LP0_PLANE_LATENCY 700
c936f44d 3984#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 3985
1398261a
YL		 3986/*
3987 * Check the wm result.
3988 *
3989 * If any calculated watermark values is larger than the maximum value that
3990 * can be programmed into the associated watermark register, that watermark
3991 * must be disabled.
1398261a 3992 */
b79d4990
JB		 3993static bool ironlake_check_srwm(struct drm_device *dev, int level,
3994 int fbc_wm, int display_wm, int cursor_wm,
3995 const struct intel_watermark_params *display,
3996 const struct intel_watermark_params *cursor)
1398261a
YL		 3997{
3998 struct drm_i915_private *dev_priv = dev->dev_private;
3999
4000 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4001 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4002
4003 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4004 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4005 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4006
4007 /* fbc has it's own way to disable FBC WM */
4008 I915_WRITE(DISP_ARB_CTL,
4009 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4010 return false;
4011 }
4012
b79d4990 4013 if (display_wm > display->max_wm) {
1398261a 4014 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4015 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4016 return false;
4017 }
4018
b79d4990 4019 if (cursor_wm > cursor->max_wm) {
1398261a 4020 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4021 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4022 return false;
4023 }
4024
4025 if (!(fbc_wm || display_wm || cursor_wm)) {
4026 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4027 return false;
4028 }
4029
4030 return true;
4031}
4032
4033/*
4034 * Compute watermark values of WM[1-3],
4035 */
d210246a
CW		 4036static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4037 int latency_ns,
b79d4990
JB		 4038 const struct intel_watermark_params *display,
4039 const struct intel_watermark_params *cursor,
4040 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4041{
d210246a 4042 struct drm_crtc *crtc;
1398261a 4043 unsigned long line_time_us;
d210246a 4044 int hdisplay, htotal, pixel_size, clock;
b79d4990 4045 int line_count, line_size;
1398261a
YL		 4046 int small, large;
4047 int entries;
1398261a
YL		 4048
4049 if (!latency_ns) {
4050 *fbc_wm = *display_wm = *cursor_wm = 0;
4051 return false;
4052 }
4053
d210246a
CW		 4054 crtc = intel_get_crtc_for_plane(dev, plane);
4055 hdisplay = crtc->mode.hdisplay;
4056 htotal = crtc->mode.htotal;
4057 clock = crtc->mode.clock;
4058 pixel_size = crtc->fb->bits_per_pixel / 8;
4059
1398261a
YL		 4060 line_time_us = (htotal * 1000) / clock;
4061 line_count = (latency_ns / line_time_us + 1000) / 1000;
4062 line_size = hdisplay * pixel_size;
4063
4064 /* Use the minimum of the small and large buffer method for primary */
4065 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4066 large = line_count * line_size;
4067
b79d4990
JB		 4068 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4069 *display_wm = entries + display->guard_size;
1398261a
YL		 4070
4071 /*
b79d4990 4072 * Spec says:
1398261a
YL		 4073 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4074 */
4075 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4076
4077 /* calculate the self-refresh watermark for display cursor */
4078 entries = line_count * pixel_size * 64;
b79d4990
JB		 4079 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4080 *cursor_wm = entries + cursor->guard_size;
1398261a 4081
b79d4990
JB		 4082 return ironlake_check_srwm(dev, level,
4083 *fbc_wm, *display_wm, *cursor_wm,
4084 display, cursor);
4085}
4086
d210246a 4087static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4088{
4089 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4090 int fbc_wm, plane_wm, cursor_wm;
4091 unsigned int enabled;
b79d4990
JB		 4092
4093 enabled = 0;
9f405100
CW		 4094 if (g4x_compute_wm0(dev, 0,
4095 &ironlake_display_wm_info,
4096 ILK_LP0_PLANE_LATENCY,
4097 &ironlake_cursor_wm_info,
4098 ILK_LP0_CURSOR_LATENCY,
4099 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4100 I915_WRITE(WM0_PIPEA_ILK,
4101 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4102 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4103 " plane %d, " "cursor: %d\n",
4104 plane_wm, cursor_wm);
d210246a 4105 enabled |= 1;
b79d4990
JB		 4106 }
4107
9f405100
CW		 4108 if (g4x_compute_wm0(dev, 1,
4109 &ironlake_display_wm_info,
4110 ILK_LP0_PLANE_LATENCY,
4111 &ironlake_cursor_wm_info,
4112 ILK_LP0_CURSOR_LATENCY,
4113 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4114 I915_WRITE(WM0_PIPEB_ILK,
4115 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4116 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4117 " plane %d, cursor: %d\n",
4118 plane_wm, cursor_wm);
d210246a 4119 enabled |= 2;
b79d4990
JB		 4120 }
4121
4122 /*
4123 * Calculate and update the self-refresh watermark only when one
4124 * display plane is used.
4125 */
4126 I915_WRITE(WM3_LP_ILK, 0);
4127 I915_WRITE(WM2_LP_ILK, 0);
4128 I915_WRITE(WM1_LP_ILK, 0);
4129
d210246a 4130 if (!single_plane_enabled(enabled))
b79d4990 4131 return;
d210246a 4132 enabled = ffs(enabled) - 1;
b79d4990
JB		 4133
4134 /* WM1 */
d210246a
CW		 4135 if (!ironlake_compute_srwm(dev, 1, enabled,
4136 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4137 &ironlake_display_srwm_info,
4138 &ironlake_cursor_srwm_info,
4139 &fbc_wm, &plane_wm, &cursor_wm))
4140 return;
4141
4142 I915_WRITE(WM1_LP_ILK,
4143 WM1_LP_SR_EN |
4144 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4145 (fbc_wm << WM1_LP_FBC_SHIFT) |
4146 (plane_wm << WM1_LP_SR_SHIFT) |
4147 cursor_wm);
4148
4149 /* WM2 */
d210246a
CW		 4150 if (!ironlake_compute_srwm(dev, 2, enabled,
4151 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4152 &ironlake_display_srwm_info,
4153 &ironlake_cursor_srwm_info,
4154 &fbc_wm, &plane_wm, &cursor_wm))
4155 return;
4156
4157 I915_WRITE(WM2_LP_ILK,
4158 WM2_LP_EN |
4159 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4160 (fbc_wm << WM1_LP_FBC_SHIFT) |
4161 (plane_wm << WM1_LP_SR_SHIFT) |
4162 cursor_wm);
4163
4164 /*
4165 * WM3 is unsupported on ILK, probably because we don't have latency
4166 * data for that power state
4167 */
1398261a
YL		 4168}
4169
d210246a 4170static void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4171{
4172 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4173 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
d210246a
CW		 4174 int fbc_wm, plane_wm, cursor_wm;
4175 unsigned int enabled;
1398261a
YL		 4176
4177 enabled = 0;
9f405100
CW		 4178 if (g4x_compute_wm0(dev, 0,
4179 &sandybridge_display_wm_info, latency,
4180 &sandybridge_cursor_wm_info, latency,
4181 &plane_wm, &cursor_wm)) {
1398261a
YL		 4182 I915_WRITE(WM0_PIPEA_ILK,
4183 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4184 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4185 " plane %d, " "cursor: %d\n",
4186 plane_wm, cursor_wm);
d210246a 4187 enabled |= 1;
1398261a
YL		 4188 }
4189
9f405100
CW		 4190 if (g4x_compute_wm0(dev, 1,
4191 &sandybridge_display_wm_info, latency,
4192 &sandybridge_cursor_wm_info, latency,
4193 &plane_wm, &cursor_wm)) {
1398261a
YL		 4194 I915_WRITE(WM0_PIPEB_ILK,
4195 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4196 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4197 " plane %d, cursor: %d\n",
4198 plane_wm, cursor_wm);
d210246a 4199 enabled |= 2;
1398261a
YL		 4200 }
4201
4202 /*
4203 * Calculate and update the self-refresh watermark only when one
4204 * display plane is used.
4205 *
4206 * SNB support 3 levels of watermark.
4207 *
4208 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4209 * and disabled in the descending order
4210 *
4211 */
4212 I915_WRITE(WM3_LP_ILK, 0);
4213 I915_WRITE(WM2_LP_ILK, 0);
4214 I915_WRITE(WM1_LP_ILK, 0);
4215
d210246a 4216 if (!single_plane_enabled(enabled))
1398261a 4217 return;
d210246a 4218 enabled = ffs(enabled) - 1;
1398261a
YL		 4219
4220 /* WM1 */
d210246a
CW		 4221 if (!ironlake_compute_srwm(dev, 1, enabled,
4222 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4223 &sandybridge_display_srwm_info,
4224 &sandybridge_cursor_srwm_info,
4225 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4226 return;
4227
4228 I915_WRITE(WM1_LP_ILK,
4229 WM1_LP_SR_EN |
4230 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4231 (fbc_wm << WM1_LP_FBC_SHIFT) |
4232 (plane_wm << WM1_LP_SR_SHIFT) |
4233 cursor_wm);
4234
4235 /* WM2 */
d210246a
CW		 4236 if (!ironlake_compute_srwm(dev, 2, enabled,
4237 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4238 &sandybridge_display_srwm_info,
4239 &sandybridge_cursor_srwm_info,
4240 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4241 return;
4242
4243 I915_WRITE(WM2_LP_ILK,
4244 WM2_LP_EN |
4245 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4246 (fbc_wm << WM1_LP_FBC_SHIFT) |
4247 (plane_wm << WM1_LP_SR_SHIFT) |
4248 cursor_wm);
4249
4250 /* WM3 */
d210246a
CW		 4251 if (!ironlake_compute_srwm(dev, 3, enabled,
4252 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4253 &sandybridge_display_srwm_info,
4254 &sandybridge_cursor_srwm_info,
4255 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4256 return;
4257
4258 I915_WRITE(WM3_LP_ILK,
4259 WM3_LP_EN |
4260 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4261 (fbc_wm << WM1_LP_FBC_SHIFT) |
4262 (plane_wm << WM1_LP_SR_SHIFT) |
4263 cursor_wm);
4264}
4265
7662c8bd
SL		 4266/**
4267 * intel_update_watermarks - update FIFO watermark values based on current modes
4268 *
4269 * Calculate watermark values for the various WM regs based on current mode
4270 * and plane configuration.
4271 *
4272 * There are several cases to deal with here:
4273 * - normal (i.e. non-self-refresh)
4274 * - self-refresh (SR) mode
4275 * - lines are large relative to FIFO size (buffer can hold up to 2)
4276 * - lines are small relative to FIFO size (buffer can hold more than 2
4277 * lines), so need to account for TLB latency
4278 *
4279 * The normal calculation is:
4280 * watermark = dotclock * bytes per pixel * latency
4281 * where latency is platform & configuration dependent (we assume pessimal
4282 * values here).
4283 *
4284 * The SR calculation is:
4285 * watermark = (trunc(latency/line time)+1) * surface width *
4286 * bytes per pixel
4287 * where
4288 * line time = htotal / dotclock
fa143215 4289 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4290 * and latency is assumed to be high, as above.
4291 *
4292 * The final value programmed to the register should always be rounded up,
4293 * and include an extra 2 entries to account for clock crossings.
4294 *
4295 * We don't use the sprite, so we can ignore that. And on Crestline we have
4296 * to set the non-SR watermarks to 8.
5eddb70b 4297 */
7662c8bd
SL		 4298static void intel_update_watermarks(struct drm_device *dev)
4299{
e70236a8 4300 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4301
d210246a
CW		 4302 if (dev_priv->display.update_wm)
4303 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4304}
4305
a7615030
CW		 4306static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4307{
4308 return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4309}
4310
f564048e
EA		 4311static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4312 struct drm_display_mode *mode,
4313 struct drm_display_mode *adjusted_mode,
4314 int x, int y,
4315 struct drm_framebuffer *old_fb)
79e53945
JB		 4316{
4317 struct drm_device *dev = crtc->dev;
4318 struct drm_i915_private *dev_priv = dev->dev_private;
4319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4320 int pipe = intel_crtc->pipe;
80824003 4321 int plane = intel_crtc->plane;
c751ce4f 4322 int refclk, num_connectors = 0;
652c393a 4323 intel_clock_t clock, reduced_clock;
5eddb70b 4324 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
652c393a 4325 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 4326 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4327 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4328 struct intel_encoder *encoder;
d4906093 4329 const intel_limit_t *limit;
5c3b82e2 4330 int ret;
fae14981 4331 u32 temp;
aa9b500d 4332 u32 lvds_sync = 0;
79e53945 4333
5eddb70b
CW		 4334 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4335 if (encoder->base.crtc != crtc)
79e53945
JB		 4336 continue;
4337
5eddb70b 4338 switch (encoder->type) {
79e53945
JB		 4339 case INTEL_OUTPUT_LVDS:
4340 is_lvds = true;
4341 break;
4342 case INTEL_OUTPUT_SDVO:
7d57382e 4343 case INTEL_OUTPUT_HDMI:
79e53945 4344 is_sdvo = true;
5eddb70b 4345 if (encoder->needs_tv_clock)
e2f0ba97 4346 is_tv = true;
79e53945
JB		 4347 break;
4348 case INTEL_OUTPUT_DVO:
4349 is_dvo = true;
4350 break;
4351 case INTEL_OUTPUT_TVOUT:
4352 is_tv = true;
4353 break;
4354 case INTEL_OUTPUT_ANALOG:
4355 is_crt = true;
4356 break;
a4fc5ed6
KP		 4357 case INTEL_OUTPUT_DISPLAYPORT:
4358 is_dp = true;
4359 break;
79e53945 4360 }
43565a06 4361
c751ce4f 4362 num_connectors++;
79e53945
JB		 4363 }
4364
a7615030 4365 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4366 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4367 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4368 refclk / 1000);
a6c45cf0 4369 } else if (!IS_GEN2(dev)) {
79e53945
JB		 4370 refclk = 96000;
4371 } else {
4372 refclk = 48000;
4373 }
4374
d4906093
ML		 4375 /*
4376 * Returns a set of divisors for the desired target clock with the given
4377 * refclk, or FALSE. The returned values represent the clock equation:
4378 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4379 */
1b894b59 4380 limit = intel_limit(crtc, refclk);
d4906093 4381 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4382 if (!ok) {
4383 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4384 return -EINVAL;
79e53945
JB		 4385 }
4386
cda4b7d3 4387 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4388 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4389
ddc9003c
ZY		 4390 if (is_lvds && dev_priv->lvds_downclock_avail) {
4391 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4392 dev_priv->lvds_downclock,
4393 refclk,
4394 &reduced_clock);
18f9ed12
ZY		 4395 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4396 /*
4397 * If the different P is found, it means that we can't
4398 * switch the display clock by using the FP0/FP1.
4399 * In such case we will disable the LVDS downclock
4400 * feature.
4401 */
4402 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4403 "LVDS clock/downclock\n");
18f9ed12
ZY		 4404 has_reduced_clock = 0;
4405 }
652c393a 4406 }
7026d4ac
ZW		 4407 /* SDVO TV has fixed PLL values depend on its clock range,
4408 this mirrors vbios setting. */
4409 if (is_sdvo && is_tv) {
4410 if (adjusted_mode->clock >= 100000
5eddb70b 4411 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4412 clock.p1 = 2;
4413 clock.p2 = 10;
4414 clock.n = 3;
4415 clock.m1 = 16;
4416 clock.m2 = 8;
4417 } else if (adjusted_mode->clock >= 140500
5eddb70b 4418 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4419 clock.p1 = 1;
4420 clock.p2 = 10;
4421 clock.n = 6;
4422 clock.m1 = 12;
4423 clock.m2 = 8;
4424 }
4425 }
4426
f2b115e6 4427 if (IS_PINEVIEW(dev)) {
2177832f 4428 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4429 if (has_reduced_clock)
4430 fp2 = (1 << reduced_clock.n) << 16 |
4431 reduced_clock.m1 << 8 | reduced_clock.m2;
4432 } else {
2177832f 4433 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4434 if (has_reduced_clock)
4435 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4436 reduced_clock.m2;
4437 }
79e53945 4438
929c77fb 4439 dpll = DPLL_VGA_MODE_DIS;
2c07245f 4440
a6c45cf0 4441 if (!IS_GEN2(dev)) {
79e53945
JB		 4442 if (is_lvds)
4443 dpll |= DPLLB_MODE_LVDS;
4444 else
4445 dpll |= DPLLB_MODE_DAC_SERIAL;
4446 if (is_sdvo) {
6c9547ff
CW		 4447 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4448 if (pixel_multiplier > 1) {
4449 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4450 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 4451 }
79e53945 4452 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4453 }
929c77fb 4454 if (is_dp)
a4fc5ed6 4455 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 4456
4457 /* compute bitmask from p1 value */
f2b115e6
AJ		 4458 if (IS_PINEVIEW(dev))
4459 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 4460 else {
2177832f 4461 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 4462 if (IS_G4X(dev) && has_reduced_clock)
4463 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 4464 }
79e53945
JB		 4465 switch (clock.p2) {
4466 case 5:
4467 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4468 break;
4469 case 7:
4470 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4471 break;
4472 case 10:
4473 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4474 break;
4475 case 14:
4476 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4477 break;
4478 }
929c77fb 4479 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 4480 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4481 } else {
4482 if (is_lvds) {
4483 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4484 } else {
4485 if (clock.p1 == 2)
4486 dpll |= PLL_P1_DIVIDE_BY_TWO;
4487 else
4488 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4489 if (clock.p2 == 4)
4490 dpll |= PLL_P2_DIVIDE_BY_4;
4491 }
4492 }
4493
43565a06
KH		 4494 if (is_sdvo && is_tv)
4495 dpll |= PLL_REF_INPUT_TVCLKINBC;
4496 else if (is_tv)
79e53945 4497 /* XXX: just matching BIOS for now */
43565a06 4498 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4499 dpll |= 3;
a7615030 4500 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4501 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4502 else
4503 dpll |= PLL_REF_INPUT_DREFCLK;
4504
4505 /* setup pipeconf */
5eddb70b 4506 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4507
4508 /* Set up the display plane register */
4509 dspcntr = DISPPLANE_GAMMA_ENABLE;
4510
f2b115e6 4511 /* Ironlake's plane is forced to pipe, bit 24 is to
2c07245f 4512 enable color space conversion */
929c77fb
EA		 4513 if (pipe == 0)
4514 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4515 else
4516 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4517
a6c45cf0 4518 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4519 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4520 * core speed.
4521 *
4522 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4523 * pipe == 0 check?
4524 */
e70236a8
JB		 4525 if (mode->clock >
4526 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4527 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4528 else
5eddb70b 4529 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4530 }
4531
929c77fb 4532 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 4533
28c97730 4534 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4535 drm_mode_debug_printmodeline(mode);
4536
fae14981
EA		 4537 I915_WRITE(FP0(pipe), fp);
4538 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 4539
fae14981 4540 POSTING_READ(DPLL(pipe));
c713bb08 4541 udelay(150);
8db9d77b 4542
79e53945
JB		 4543 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4544 * This is an exception to the general rule that mode_set doesn't turn
4545 * things on.
4546 */
4547 if (is_lvds) {
fae14981 4548 temp = I915_READ(LVDS);
5eddb70b 4549 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 4550 if (pipe == 1) {
929c77fb 4551 temp |= LVDS_PIPEB_SELECT;
b3b095b3 4552 } else {
929c77fb 4553 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 4554 }
a3e17eb8 4555 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4556 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4557 /* Set the B0-B3 data pairs corresponding to whether we're going to
4558 * set the DPLLs for dual-channel mode or not.
4559 */
4560 if (clock.p2 == 7)
5eddb70b 4561 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4562 else
5eddb70b 4563 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4564
4565 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4566 * appropriately here, but we need to look more thoroughly into how
4567 * panels behave in the two modes.
4568 */
929c77fb
EA		 4569 /* set the dithering flag on LVDS as needed */
4570 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 4571 if (dev_priv->lvds_dither)
5eddb70b 4572 temp |= LVDS_ENABLE_DITHER;
434ed097 4573 else
5eddb70b 4574 temp &= ~LVDS_ENABLE_DITHER;
898822ce 4575 }
aa9b500d
BF		 4576 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4577 lvds_sync |= LVDS_HSYNC_POLARITY;
4578 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4579 lvds_sync |= LVDS_VSYNC_POLARITY;
4580 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4581 != lvds_sync) {
4582 char flags[2] = "-+";
4583 DRM_INFO("Changing LVDS panel from "
4584 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4585 flags[!(temp & LVDS_HSYNC_POLARITY)],
4586 flags[!(temp & LVDS_VSYNC_POLARITY)],
4587 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4588 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4589 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4590 temp |= lvds_sync;
4591 }
fae14981 4592 I915_WRITE(LVDS, temp);
79e53945 4593 }
434ed097 4594
929c77fb 4595 if (is_dp) {
a4fc5ed6 4596 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 4597 }
4598
fae14981 4599 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 4600
c713bb08 4601 /* Wait for the clocks to stabilize. */
fae14981 4602 POSTING_READ(DPLL(pipe));
c713bb08 4603 udelay(150);
32f9d658 4604
c713bb08
EA		 4605 if (INTEL_INFO(dev)->gen >= 4) {
4606 temp = 0;
4607 if (is_sdvo) {
4608 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4609 if (temp > 1)
4610 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4611 else
4612 temp = 0;
32f9d658 4613 }
c713bb08
EA		 4614 I915_WRITE(DPLL_MD(pipe), temp);
4615 } else {
4616 /* The pixel multiplier can only be updated once the
4617 * DPLL is enabled and the clocks are stable.
4618 *
4619 * So write it again.
4620 */
fae14981 4621 I915_WRITE(DPLL(pipe), dpll);
79e53945 4622 }
79e53945 4623
5eddb70b 4624 intel_crtc->lowfreq_avail = false;
652c393a 4625 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 4626 I915_WRITE(FP1(pipe), fp2);
652c393a
JB		 4627 intel_crtc->lowfreq_avail = true;
4628 if (HAS_PIPE_CXSR(dev)) {
28c97730 4629 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 4630 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4631 }
4632 } else {
fae14981 4633 I915_WRITE(FP1(pipe), fp);
652c393a 4634 if (HAS_PIPE_CXSR(dev)) {
28c97730 4635 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4636 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4637 }
4638 }
4639
734b4157
KH		 4640 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4641 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4642 /* the chip adds 2 halflines automatically */
4643 adjusted_mode->crtc_vdisplay -= 1;
4644 adjusted_mode->crtc_vtotal -= 1;
4645 adjusted_mode->crtc_vblank_start -= 1;
4646 adjusted_mode->crtc_vblank_end -= 1;
4647 adjusted_mode->crtc_vsync_end -= 1;
4648 adjusted_mode->crtc_vsync_start -= 1;
4649 } else
4650 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4651
5eddb70b
CW		 4652 I915_WRITE(HTOTAL(pipe),
4653 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4654 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4655 I915_WRITE(HBLANK(pipe),
4656 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4657 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4658 I915_WRITE(HSYNC(pipe),
4659 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4660 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4661
4662 I915_WRITE(VTOTAL(pipe),
4663 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4664 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4665 I915_WRITE(VBLANK(pipe),
4666 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4667 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4668 I915_WRITE(VSYNC(pipe),
4669 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4670 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4671
4672 /* pipesrc and dspsize control the size that is scaled from,
4673 * which should always be the user's requested size.
79e53945 4674 */
929c77fb
EA		 4675 I915_WRITE(DSPSIZE(plane),
4676 ((mode->vdisplay - 1) << 16) |
4677 (mode->hdisplay - 1));
4678 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4679 I915_WRITE(PIPESRC(pipe),
4680 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4681
f564048e
EA		 4682 I915_WRITE(PIPECONF(pipe), pipeconf);
4683 POSTING_READ(PIPECONF(pipe));
929c77fb 4684 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4685
4686 intel_wait_for_vblank(dev, pipe);
4687
f564048e
EA		 4688 I915_WRITE(DSPCNTR(plane), dspcntr);
4689 POSTING_READ(DSPCNTR(plane));
284d9529 4690 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 4691
4692 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4693
4694 intel_update_watermarks(dev);
4695
f564048e
EA		 4696 return ret;
4697}
4698
4699static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4700 struct drm_display_mode *mode,
4701 struct drm_display_mode *adjusted_mode,
4702 int x, int y,
4703 struct drm_framebuffer *old_fb)
79e53945
JB		 4704{
4705 struct drm_device *dev = crtc->dev;
4706 struct drm_i915_private *dev_priv = dev->dev_private;
4707 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4708 int pipe = intel_crtc->pipe;
80824003 4709 int plane = intel_crtc->plane;
c751ce4f 4710 int refclk, num_connectors = 0;
652c393a 4711 intel_clock_t clock, reduced_clock;
5eddb70b 4712 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4713 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4714 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 4715 struct intel_encoder *has_edp_encoder = NULL;
79e53945 4716 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4717 struct intel_encoder *encoder;
d4906093 4718 const intel_limit_t *limit;
5c3b82e2 4719 int ret;
2c07245f 4720 struct fdi_m_n m_n = {0};
fae14981 4721 u32 temp;
aa9b500d 4722 u32 lvds_sync = 0;
8febb297 4723 int target_clock, pixel_multiplier, lane, link_bw, bpp, factor;
79e53945 4724
5eddb70b
CW		 4725 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4726 if (encoder->base.crtc != crtc)
79e53945
JB		 4727 continue;
4728
5eddb70b 4729 switch (encoder->type) {
79e53945
JB		 4730 case INTEL_OUTPUT_LVDS:
4731 is_lvds = true;
4732 break;
4733 case INTEL_OUTPUT_SDVO:
7d57382e 4734 case INTEL_OUTPUT_HDMI:
79e53945 4735 is_sdvo = true;
5eddb70b 4736 if (encoder->needs_tv_clock)
e2f0ba97 4737 is_tv = true;
79e53945 4738 break;
79e53945
JB		 4739 case INTEL_OUTPUT_TVOUT:
4740 is_tv = true;
4741 break;
4742 case INTEL_OUTPUT_ANALOG:
4743 is_crt = true;
4744 break;
a4fc5ed6
KP		 4745 case INTEL_OUTPUT_DISPLAYPORT:
4746 is_dp = true;
4747 break;
32f9d658 4748 case INTEL_OUTPUT_EDP:
5eddb70b 4749 has_edp_encoder = encoder;
32f9d658 4750 break;
79e53945 4751 }
43565a06 4752
c751ce4f 4753 num_connectors++;
79e53945
JB		 4754 }
4755
a7615030 4756 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4757 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4758 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4759 refclk / 1000);
a07d6787 4760 } else {
79e53945 4761 refclk = 96000;
8febb297
EA		 4762 if (!has_edp_encoder ||
4763 intel_encoder_is_pch_edp(&has_edp_encoder->base))
2c07245f 4764 refclk = 120000; /* 120Mhz refclk */
79e53945
JB		 4765 }
4766
d4906093
ML		 4767 /*
4768 * Returns a set of divisors for the desired target clock with the given
4769 * refclk, or FALSE. The returned values represent the clock equation:
4770 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4771 */
1b894b59 4772 limit = intel_limit(crtc, refclk);
d4906093 4773 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4774 if (!ok) {
4775 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4776 return -EINVAL;
79e53945
JB		 4777 }
4778
cda4b7d3 4779 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4780 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4781
ddc9003c
ZY		 4782 if (is_lvds && dev_priv->lvds_downclock_avail) {
4783 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4784 dev_priv->lvds_downclock,
4785 refclk,
4786 &reduced_clock);
18f9ed12
ZY		 4787 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4788 /*
4789 * If the different P is found, it means that we can't
4790 * switch the display clock by using the FP0/FP1.
4791 * In such case we will disable the LVDS downclock
4792 * feature.
4793 */
4794 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4795 "LVDS clock/downclock\n");
18f9ed12
ZY		 4796 has_reduced_clock = 0;
4797 }
652c393a 4798 }
7026d4ac
ZW		 4799 /* SDVO TV has fixed PLL values depend on its clock range,
4800 this mirrors vbios setting. */
4801 if (is_sdvo && is_tv) {
4802 if (adjusted_mode->clock >= 100000
5eddb70b 4803 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4804 clock.p1 = 2;
4805 clock.p2 = 10;
4806 clock.n = 3;
4807 clock.m1 = 16;
4808 clock.m2 = 8;
4809 } else if (adjusted_mode->clock >= 140500
5eddb70b 4810 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4811 clock.p1 = 1;
4812 clock.p2 = 10;
4813 clock.n = 6;
4814 clock.m1 = 12;
4815 clock.m2 = 8;
4816 }
4817 }
4818
2c07245f 4819 /* FDI link */
8febb297
EA		 4820 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4821 lane = 0;
4822 /* CPU eDP doesn't require FDI link, so just set DP M/N
4823 according to current link config */
4824 if (has_edp_encoder &&
4825 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4826 target_clock = mode->clock;
4827 intel_edp_link_config(has_edp_encoder,
4828 &lane, &link_bw);
4829 } else {
4830 /* [e]DP over FDI requires target mode clock
4831 instead of link clock */
4832 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 4833 target_clock = mode->clock;
8febb297
EA		 4834 else
4835 target_clock = adjusted_mode->clock;
4836
4837 /* FDI is a binary signal running at ~2.7GHz, encoding
4838 * each output octet as 10 bits. The actual frequency
4839 * is stored as a divider into a 100MHz clock, and the
4840 * mode pixel clock is stored in units of 1KHz.
4841 * Hence the bw of each lane in terms of the mode signal
4842 * is:
4843 */
4844 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4845 }
58a27471 4846
8febb297
EA		 4847 /* determine panel color depth */
4848 temp = I915_READ(PIPECONF(pipe));
4849 temp &= ~PIPE_BPC_MASK;
4850 if (is_lvds) {
4851 /* the BPC will be 6 if it is 18-bit LVDS panel */
4852 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4853 temp |= PIPE_8BPC;
4854 else
4855 temp |= PIPE_6BPC;
4856 } else if (has_edp_encoder) {
4857 switch (dev_priv->edp.bpp/3) {
4858 case 8:
e5a95eb7 4859 temp |= PIPE_8BPC;
58a27471 4860 break;
8febb297
EA		 4861 case 10:
4862 temp |= PIPE_10BPC;
58a27471 4863 break;
8febb297
EA		 4864 case 6:
4865 temp |= PIPE_6BPC;
58a27471 4866 break;
8febb297
EA		 4867 case 12:
4868 temp |= PIPE_12BPC;
58a27471 4869 break;
77ffb597 4870 }
8febb297
EA		 4871 } else
4872 temp |= PIPE_8BPC;
4873 I915_WRITE(PIPECONF(pipe), temp);
77ffb597 4874
8febb297
EA		 4875 switch (temp & PIPE_BPC_MASK) {
4876 case PIPE_8BPC:
4877 bpp = 24;
4878 break;
4879 case PIPE_10BPC:
4880 bpp = 30;
4881 break;
4882 case PIPE_6BPC:
4883 bpp = 18;
4884 break;
4885 case PIPE_12BPC:
4886 bpp = 36;
4887 break;
4888 default:
4889 DRM_ERROR("unknown pipe bpc value\n");
4890 bpp = 24;
4891 }
77ffb597 4892
8febb297
EA		 4893 if (!lane) {
4894 /*
4895 * Account for spread spectrum to avoid
4896 * oversubscribing the link. Max center spread
4897 * is 2.5%; use 5% for safety's sake.
4898 */
4899 u32 bps = target_clock * bpp * 21 / 20;
4900 lane = bps / (link_bw * 8) + 1;
5eb08b69 4901 }
2c07245f 4902
8febb297
EA		 4903 intel_crtc->fdi_lanes = lane;
4904
4905 if (pixel_multiplier > 1)
4906 link_bw *= pixel_multiplier;
4907 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4908
c038e51e
ZW		 4909 /* Ironlake: try to setup display ref clock before DPLL
4910 * enabling. This is only under driver's control after
4911 * PCH B stepping, previous chipset stepping should be
4912 * ignoring this setting.
4913 */
8febb297
EA		 4914 temp = I915_READ(PCH_DREF_CONTROL);
4915 /* Always enable nonspread source */
4916 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4917 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4918 temp &= ~DREF_SSC_SOURCE_MASK;
4919 temp |= DREF_SSC_SOURCE_ENABLE;
4920 I915_WRITE(PCH_DREF_CONTROL, temp);
4921
4922 POSTING_READ(PCH_DREF_CONTROL);
4923 udelay(200);
fc9a2228 4924
8febb297
EA		 4925 if (has_edp_encoder) {
4926 if (intel_panel_use_ssc(dev_priv)) {
4927 temp |= DREF_SSC1_ENABLE;
fc9a2228 4928 I915_WRITE(PCH_DREF_CONTROL, temp);
8febb297 4929
fc9a2228
CW		 4930 POSTING_READ(PCH_DREF_CONTROL);
4931 udelay(200);
4932 }
8febb297
EA		 4933 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4934
4935 /* Enable CPU source on CPU attached eDP */
4936 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4937 if (intel_panel_use_ssc(dev_priv))
4938 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4939 else
4940 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4941 } else {
4942 /* Enable SSC on PCH eDP if needed */
4943 if (intel_panel_use_ssc(dev_priv)) {
4944 DRM_ERROR("enabling SSC on PCH\n");
4945 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4946 }
4947 }
4948 I915_WRITE(PCH_DREF_CONTROL, temp);
4949 POSTING_READ(PCH_DREF_CONTROL);
4950 udelay(200);
fc9a2228 4951 }
c038e51e 4952
a07d6787
EA		 4953 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4954 if (has_reduced_clock)
4955 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4956 reduced_clock.m2;
79e53945 4957
c1858123 4958 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4959 factor = 21;
4960 if (is_lvds) {
4961 if ((intel_panel_use_ssc(dev_priv) &&
4962 dev_priv->lvds_ssc_freq == 100) ||
4963 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4964 factor = 25;
4965 } else if (is_sdvo && is_tv)
4966 factor = 20;
c1858123 4967
8febb297
EA		 4968 if (clock.m1 < factor * clock.n)
4969 fp |= FP_CB_TUNE;
2c07245f 4970
5eddb70b 4971 dpll = 0;
2c07245f 4972
a07d6787
EA		 4973 if (is_lvds)
4974 dpll |= DPLLB_MODE_LVDS;
4975 else
4976 dpll |= DPLLB_MODE_DAC_SERIAL;
4977 if (is_sdvo) {
4978 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4979 if (pixel_multiplier > 1) {
4980 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4981 }
a07d6787
EA		 4982 dpll |= DPLL_DVO_HIGH_SPEED;
4983 }
4984 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4985 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4986
a07d6787
EA		 4987 /* compute bitmask from p1 value */
4988 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4989 /* also FPA1 */
4990 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4991
4992 switch (clock.p2) {
4993 case 5:
4994 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4995 break;
4996 case 7:
4997 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4998 break;
4999 case 10:
5000 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5001 break;
5002 case 14:
5003 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5004 break;
79e53945
JB		 5005 }
5006
43565a06
KH		 5007 if (is_sdvo && is_tv)
5008 dpll |= PLL_REF_INPUT_TVCLKINBC;
5009 else if (is_tv)
79e53945 5010 /* XXX: just matching BIOS for now */
43565a06 5011 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5012 dpll |= 3;
a7615030 5013 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5014 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5015 else
5016 dpll |= PLL_REF_INPUT_DREFCLK;
5017
5018 /* setup pipeconf */
5eddb70b 5019 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5020
5021 /* Set up the display plane register */
5022 dspcntr = DISPPLANE_GAMMA_ENABLE;
5023
28c97730 5024 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5025 drm_mode_debug_printmodeline(mode);
5026
5c5313c8
JB		 5027 /* PCH eDP needs FDI, but CPU eDP does not */
5028 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981
EA		 5029 I915_WRITE(PCH_FP0(pipe), fp);
5030 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5031
fae14981 5032 POSTING_READ(PCH_DPLL(pipe));
79e53945
JB		 5033 udelay(150);
5034 }
5035
8db9d77b
ZW		 5036 /* enable transcoder DPLL */
5037 if (HAS_PCH_CPT(dev)) {
5038 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 5039 switch (pipe) {
5040 case 0:
5eddb70b 5041 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
9db4a9c7
JB		 5042 break;
5043 case 1:
5eddb70b 5044 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
9db4a9c7
JB		 5045 break;
5046 case 2:
5047 /* FIXME: manage transcoder PLLs? */
5048 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5049 break;
5050 default:
5051 BUG();
32f9d658 5052 }
8db9d77b 5053 I915_WRITE(PCH_DPLL_SEL, temp);
5eddb70b
CW		 5054
5055 POSTING_READ(PCH_DPLL_SEL);
8db9d77b
ZW		 5056 udelay(150);
5057 }
5058
79e53945
JB		 5059 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5060 * This is an exception to the general rule that mode_set doesn't turn
5061 * things on.
5062 */
5063 if (is_lvds) {
fae14981 5064 temp = I915_READ(PCH_LVDS);
5eddb70b 5065 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3
ZW		 5066 if (pipe == 1) {
5067 if (HAS_PCH_CPT(dev))
5eddb70b 5068 temp |= PORT_TRANS_B_SEL_CPT;
b3b095b3 5069 else
5eddb70b 5070 temp |= LVDS_PIPEB_SELECT;
b3b095b3
ZW		 5071 } else {
5072 if (HAS_PCH_CPT(dev))
5eddb70b 5073 temp &= ~PORT_TRANS_SEL_MASK;
b3b095b3 5074 else
5eddb70b 5075 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5076 }
a3e17eb8 5077 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5078 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5079 /* Set the B0-B3 data pairs corresponding to whether we're going to
5080 * set the DPLLs for dual-channel mode or not.
5081 */
5082 if (clock.p2 == 7)
5eddb70b 5083 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5084 else
5eddb70b 5085 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5086
5087 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5088 * appropriately here, but we need to look more thoroughly into how
5089 * panels behave in the two modes.
5090 */
aa9b500d
BF		 5091 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5092 lvds_sync |= LVDS_HSYNC_POLARITY;
5093 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5094 lvds_sync |= LVDS_VSYNC_POLARITY;
5095 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5096 != lvds_sync) {
5097 char flags[2] = "-+";
5098 DRM_INFO("Changing LVDS panel from "
5099 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5100 flags[!(temp & LVDS_HSYNC_POLARITY)],
5101 flags[!(temp & LVDS_VSYNC_POLARITY)],
5102 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5103 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5104 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5105 temp |= lvds_sync;
5106 }
fae14981 5107 I915_WRITE(PCH_LVDS, temp);
79e53945 5108 }
434ed097
JB		 5109
5110 /* set the dithering flag and clear for anything other than a panel. */
8febb297
EA		 5111 pipeconf &= ~PIPECONF_DITHER_EN;
5112 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5113 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5114 pipeconf |= PIPECONF_DITHER_EN;
5115 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
434ed097
JB		 5116 }
5117
5c5313c8 5118 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5119 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5120 } else {
8db9d77b 5121 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5122 I915_WRITE(TRANSDATA_M1(pipe), 0);
5123 I915_WRITE(TRANSDATA_N1(pipe), 0);
5124 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5125 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5126 }
79e53945 5127
8febb297
EA		 5128 if (!has_edp_encoder ||
5129 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981 5130 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5131
32f9d658 5132 /* Wait for the clocks to stabilize. */
fae14981 5133 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5134 udelay(150);
5135
8febb297
EA		 5136 /* The pixel multiplier can only be updated once the
5137 * DPLL is enabled and the clocks are stable.
5138 *
5139 * So write it again.
5140 */
fae14981 5141 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5142 }
79e53945 5143
5eddb70b 5144 intel_crtc->lowfreq_avail = false;
652c393a 5145 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 5146 I915_WRITE(PCH_FP1(pipe), fp2);
652c393a
JB		 5147 intel_crtc->lowfreq_avail = true;
5148 if (HAS_PIPE_CXSR(dev)) {
28c97730 5149 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 5150 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5151 }
5152 } else {
fae14981 5153 I915_WRITE(PCH_FP1(pipe), fp);
652c393a 5154 if (HAS_PIPE_CXSR(dev)) {
28c97730 5155 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5156 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5157 }
5158 }
5159
734b4157
KH		 5160 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5161 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5162 /* the chip adds 2 halflines automatically */
5163 adjusted_mode->crtc_vdisplay -= 1;
5164 adjusted_mode->crtc_vtotal -= 1;
5165 adjusted_mode->crtc_vblank_start -= 1;
5166 adjusted_mode->crtc_vblank_end -= 1;
5167 adjusted_mode->crtc_vsync_end -= 1;
5168 adjusted_mode->crtc_vsync_start -= 1;
5169 } else
5170 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5171
5eddb70b
CW		 5172 I915_WRITE(HTOTAL(pipe),
5173 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5174 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5175 I915_WRITE(HBLANK(pipe),
5176 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5177 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5178 I915_WRITE(HSYNC(pipe),
5179 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5180 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5181
5182 I915_WRITE(VTOTAL(pipe),
5183 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5184 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5185 I915_WRITE(VBLANK(pipe),
5186 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5187 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5188 I915_WRITE(VSYNC(pipe),
5189 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5190 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5191
8febb297
EA		 5192 /* pipesrc controls the size that is scaled from, which should
5193 * always be the user's requested size.
79e53945 5194 */
5eddb70b
CW		 5195 I915_WRITE(PIPESRC(pipe),
5196 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5197
8febb297
EA		 5198 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5199 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5200 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5201 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5202
8febb297
EA		 5203 if (has_edp_encoder &&
5204 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5205 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 5206 }
5207
5eddb70b
CW		 5208 I915_WRITE(PIPECONF(pipe), pipeconf);
5209 POSTING_READ(PIPECONF(pipe));
79e53945 5210
9d0498a2 5211 intel_wait_for_vblank(dev, pipe);
79e53945 5212
f00a3ddf 5213 if (IS_GEN5(dev)) {
553bd149
ZW		 5214 /* enable address swizzle for tiling buffer */
5215 temp = I915_READ(DISP_ARB_CTL);
5216 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5217 }
5218
5eddb70b 5219 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 5220 POSTING_READ(DSPCNTR(plane));
79e53945 5221
5c3b82e2 5222 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 5223
5224 intel_update_watermarks(dev);
5225
1f803ee5 5226 return ret;
79e53945
JB		 5227}
5228
f564048e
EA		 5229static int intel_crtc_mode_set(struct drm_crtc *crtc,
5230 struct drm_display_mode *mode,
5231 struct drm_display_mode *adjusted_mode,
5232 int x, int y,
5233 struct drm_framebuffer *old_fb)
5234{
5235 struct drm_device *dev = crtc->dev;
5236 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5238 int pipe = intel_crtc->pipe;
f564048e
EA		 5239 int ret;
5240
0b701d27 5241 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5242
f564048e
EA		 5243 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5244 x, y, old_fb);
7662c8bd 5245
79e53945 5246 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5247
1f803ee5 5248 return ret;
79e53945
JB		 5249}
5250
5251/** Loads the palette/gamma unit for the CRTC with the prepared values */
5252void intel_crtc_load_lut(struct drm_crtc *crtc)
5253{
5254 struct drm_device *dev = crtc->dev;
5255 struct drm_i915_private *dev_priv = dev->dev_private;
5256 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5257 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5258 int i;
5259
5260 /* The clocks have to be on to load the palette. */
5261 if (!crtc->enabled)
5262 return;
5263
f2b115e6 5264 /* use legacy palette for Ironlake */
bad720ff 5265 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5266 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5267
79e53945
JB		 5268 for (i = 0; i < 256; i++) {
5269 I915_WRITE(palreg + 4 * i,
5270 (intel_crtc->lut_r[i] << 16) |
5271 (intel_crtc->lut_g[i] << 8) |
5272 intel_crtc->lut_b[i]);
5273 }
5274}
5275
560b85bb
CW		 5276static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5277{
5278 struct drm_device *dev = crtc->dev;
5279 struct drm_i915_private *dev_priv = dev->dev_private;
5280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5281 bool visible = base != 0;
5282 u32 cntl;
5283
5284 if (intel_crtc->cursor_visible == visible)
5285 return;
5286
9db4a9c7 5287 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5288 if (visible) {
5289 /* On these chipsets we can only modify the base whilst
5290 * the cursor is disabled.
5291 */
9db4a9c7 5292 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5293
5294 cntl &= ~(CURSOR_FORMAT_MASK);
5295 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5296 cntl |= CURSOR_ENABLE |
5297 CURSOR_GAMMA_ENABLE |
5298 CURSOR_FORMAT_ARGB;
5299 } else
5300 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5301 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5302
5303 intel_crtc->cursor_visible = visible;
5304}
5305
5306static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5307{
5308 struct drm_device *dev = crtc->dev;
5309 struct drm_i915_private *dev_priv = dev->dev_private;
5310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5311 int pipe = intel_crtc->pipe;
5312 bool visible = base != 0;
5313
5314 if (intel_crtc->cursor_visible != visible) {
548f245b 5315 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5316 if (base) {
5317 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5318 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5319 cntl |= pipe << 28; /* Connect to correct pipe */
5320 } else {
5321 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5322 cntl |= CURSOR_MODE_DISABLE;
5323 }
9db4a9c7 5324 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5325
5326 intel_crtc->cursor_visible = visible;
5327 }
5328 /* and commit changes on next vblank */
9db4a9c7 5329 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5330}
5331
cda4b7d3 5332/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5333static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5334 bool on)
cda4b7d3
CW		 5335{
5336 struct drm_device *dev = crtc->dev;
5337 struct drm_i915_private *dev_priv = dev->dev_private;
5338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5339 int pipe = intel_crtc->pipe;
5340 int x = intel_crtc->cursor_x;
5341 int y = intel_crtc->cursor_y;
560b85bb 5342 u32 base, pos;
cda4b7d3
CW		 5343 bool visible;
5344
5345 pos = 0;
5346
6b383a7f 5347 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5348 base = intel_crtc->cursor_addr;
5349 if (x > (int) crtc->fb->width)
5350 base = 0;
5351
5352 if (y > (int) crtc->fb->height)
5353 base = 0;
5354 } else
5355 base = 0;
5356
5357 if (x < 0) {
5358 if (x + intel_crtc->cursor_width < 0)
5359 base = 0;
5360
5361 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5362 x = -x;
5363 }
5364 pos |= x << CURSOR_X_SHIFT;
5365
5366 if (y < 0) {
5367 if (y + intel_crtc->cursor_height < 0)
5368 base = 0;
5369
5370 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5371 y = -y;
5372 }
5373 pos |= y << CURSOR_Y_SHIFT;
5374
5375 visible = base != 0;
560b85bb 5376 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5377 return;
5378
9db4a9c7 5379 I915_WRITE(CURPOS(pipe), pos);
560b85bb
CW		 5380 if (IS_845G(dev) || IS_I865G(dev))
5381 i845_update_cursor(crtc, base);
5382 else
5383 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 5384
5385 if (visible)
5386 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5387}
5388
79e53945 5389static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5390 struct drm_file *file,
79e53945
JB		 5391 uint32_t handle,
5392 uint32_t width, uint32_t height)
5393{
5394 struct drm_device *dev = crtc->dev;
5395 struct drm_i915_private *dev_priv = dev->dev_private;
5396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5397 struct drm_i915_gem_object *obj;
cda4b7d3 5398 uint32_t addr;
3f8bc370 5399 int ret;
79e53945 5400
28c97730 5401 DRM_DEBUG_KMS("\n");
79e53945
JB		 5402
5403 /* if we want to turn off the cursor ignore width and height */
5404 if (!handle) {
28c97730 5405 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5406 addr = 0;
05394f39 5407 obj = NULL;
5004417d 5408 mutex_lock(&dev->struct_mutex);
3f8bc370 5409 goto finish;
79e53945
JB		 5410 }
5411
5412 /* Currently we only support 64x64 cursors */
5413 if (width != 64 || height != 64) {
5414 DRM_ERROR("we currently only support 64x64 cursors\n");
5415 return -EINVAL;
5416 }
5417
05394f39 5418 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5419 if (&obj->base == NULL)
79e53945
JB		 5420 return -ENOENT;
5421
05394f39 5422 if (obj->base.size < width * height * 4) {
79e53945 5423 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5424 ret = -ENOMEM;
5425 goto fail;
79e53945
JB		 5426 }
5427
71acb5eb 5428 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5429 mutex_lock(&dev->struct_mutex);
b295d1b6 5430 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5431 if (obj->tiling_mode) {
5432 DRM_ERROR("cursor cannot be tiled\n");
5433 ret = -EINVAL;
5434 goto fail_locked;
5435 }
5436
2da3b9b9 5437 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5438 if (ret) {
5439 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5440 goto fail_locked;
e7b526bb
CW		 5441 }
5442
d9e86c0e
CW		 5443 ret = i915_gem_object_put_fence(obj);
5444 if (ret) {
2da3b9b9 5445 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5446 goto fail_unpin;
5447 }
5448
05394f39 5449 addr = obj->gtt_offset;
71acb5eb 5450 } else {
6eeefaf3 5451 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5452 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5453 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5454 align);
71acb5eb
DA		 5455 if (ret) {
5456 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5457 goto fail_locked;
71acb5eb 5458 }
05394f39 5459 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5460 }
5461
a6c45cf0 5462 if (IS_GEN2(dev))
14b60391
JB		 5463 I915_WRITE(CURSIZE, (height << 12) | width);
5464
3f8bc370 5465 finish:
3f8bc370 5466 if (intel_crtc->cursor_bo) {
b295d1b6 5467 if (dev_priv->info->cursor_needs_physical) {
05394f39 5468 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5469 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5470 } else
5471 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5472 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5473 }
80824003 5474
7f9872e0 5475 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5476
5477 intel_crtc->cursor_addr = addr;
05394f39 5478 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5479 intel_crtc->cursor_width = width;
5480 intel_crtc->cursor_height = height;
5481
6b383a7f 5482 intel_crtc_update_cursor(crtc, true);
3f8bc370 5483
79e53945 5484 return 0;
e7b526bb 5485fail_unpin:
05394f39 5486 i915_gem_object_unpin(obj);
7f9872e0 5487fail_locked:
34b8686e 5488 mutex_unlock(&dev->struct_mutex);
bc9025bd 5489fail:
05394f39 5490 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5491 return ret;
79e53945
JB		 5492}
5493
5494static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5495{
79e53945 5496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5497
cda4b7d3
CW		 5498 intel_crtc->cursor_x = x;
5499 intel_crtc->cursor_y = y;
652c393a 5500
6b383a7f 5501 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5502
5503 return 0;
5504}
5505
5506/** Sets the color ramps on behalf of RandR */
5507void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5508 u16 blue, int regno)
5509{
5510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5511
5512 intel_crtc->lut_r[regno] = red >> 8;
5513 intel_crtc->lut_g[regno] = green >> 8;
5514 intel_crtc->lut_b[regno] = blue >> 8;
5515}
5516
b8c00ac5
DA		 5517void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5518 u16 *blue, int regno)
5519{
5520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5521
5522 *red = intel_crtc->lut_r[regno] << 8;
5523 *green = intel_crtc->lut_g[regno] << 8;
5524 *blue = intel_crtc->lut_b[regno] << 8;
5525}
5526
79e53945 5527static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5528 u16 *blue, uint32_t start, uint32_t size)
79e53945 5529{
7203425a 5530 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5532
7203425a 5533 for (i = start; i < end; i++) {
79e53945
JB		 5534 intel_crtc->lut_r[i] = red[i] >> 8;
5535 intel_crtc->lut_g[i] = green[i] >> 8;
5536 intel_crtc->lut_b[i] = blue[i] >> 8;
5537 }
5538
5539 intel_crtc_load_lut(crtc);
5540}
5541
5542/**
5543 * Get a pipe with a simple mode set on it for doing load-based monitor
5544 * detection.
5545 *
5546 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5547 * its requirements. The pipe will be connected to no other encoders.
79e53945 5548 *
c751ce4f 5549 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5550 * configured for it. In the future, it could choose to temporarily disable
5551 * some outputs to free up a pipe for its use.
5552 *
5553 * \return crtc, or NULL if no pipes are available.
5554 */
5555
5556/* VESA 640x480x72Hz mode to set on the pipe */
5557static struct drm_display_mode load_detect_mode = {
5558 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5559 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5560};
5561
d2dff872
CW		 5562static struct drm_framebuffer *
5563intel_framebuffer_create(struct drm_device *dev,
5564 struct drm_mode_fb_cmd *mode_cmd,
5565 struct drm_i915_gem_object *obj)
5566{
5567 struct intel_framebuffer *intel_fb;
5568 int ret;
5569
5570 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5571 if (!intel_fb) {
5572 drm_gem_object_unreference_unlocked(&obj->base);
5573 return ERR_PTR(-ENOMEM);
5574 }
5575
5576 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5577 if (ret) {
5578 drm_gem_object_unreference_unlocked(&obj->base);
5579 kfree(intel_fb);
5580 return ERR_PTR(ret);
5581 }
5582
5583 return &intel_fb->base;
5584}
5585
5586static u32
5587intel_framebuffer_pitch_for_width(int width, int bpp)
5588{
5589 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5590 return ALIGN(pitch, 64);
5591}
5592
5593static u32
5594intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5595{
5596 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5597 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5598}
5599
5600static struct drm_framebuffer *
5601intel_framebuffer_create_for_mode(struct drm_device *dev,
5602 struct drm_display_mode *mode,
5603 int depth, int bpp)
5604{
5605 struct drm_i915_gem_object *obj;
5606 struct drm_mode_fb_cmd mode_cmd;
5607
5608 obj = i915_gem_alloc_object(dev,
5609 intel_framebuffer_size_for_mode(mode, bpp));
5610 if (obj == NULL)
5611 return ERR_PTR(-ENOMEM);
5612
5613 mode_cmd.width = mode->hdisplay;
5614 mode_cmd.height = mode->vdisplay;
5615 mode_cmd.depth = depth;
5616 mode_cmd.bpp = bpp;
5617 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5618
5619 return intel_framebuffer_create(dev, &mode_cmd, obj);
5620}
5621
5622static struct drm_framebuffer *
5623mode_fits_in_fbdev(struct drm_device *dev,
5624 struct drm_display_mode *mode)
5625{
5626 struct drm_i915_private *dev_priv = dev->dev_private;
5627 struct drm_i915_gem_object *obj;
5628 struct drm_framebuffer *fb;
5629
5630 if (dev_priv->fbdev == NULL)
5631 return NULL;
5632
5633 obj = dev_priv->fbdev->ifb.obj;
5634 if (obj == NULL)
5635 return NULL;
5636
5637 fb = &dev_priv->fbdev->ifb.base;
5638 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5639 fb->bits_per_pixel))
5640 return NULL;
5641
5642 if (obj->base.size < mode->vdisplay * fb->pitch)
5643 return NULL;
5644
5645 return fb;
5646}
5647
7173188d
CW		 5648bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5649 struct drm_connector *connector,
5650 struct drm_display_mode *mode,
8261b191 5651 struct intel_load_detect_pipe *old)
79e53945
JB		 5652{
5653 struct intel_crtc *intel_crtc;
5654 struct drm_crtc *possible_crtc;
4ef69c7a 5655 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5656 struct drm_crtc *crtc = NULL;
5657 struct drm_device *dev = encoder->dev;
d2dff872 5658 struct drm_framebuffer *old_fb;
79e53945
JB		 5659 int i = -1;
5660
d2dff872
CW		 5661 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5662 connector->base.id, drm_get_connector_name(connector),
5663 encoder->base.id, drm_get_encoder_name(encoder));
5664
79e53945
JB		 5665 /*
5666 * Algorithm gets a little messy:
7a5e4805 5667 *
79e53945
JB		 5668 * - if the connector already has an assigned crtc, use it (but make
5669 * sure it's on first)
7a5e4805 5670 *
79e53945
JB		 5671 * - try to find the first unused crtc that can drive this connector,
5672 * and use that if we find one
79e53945
JB		 5673 */
5674
5675 /* See if we already have a CRTC for this connector */
5676 if (encoder->crtc) {
5677 crtc = encoder->crtc;
8261b191 5678
79e53945 5679 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5680 old->dpms_mode = intel_crtc->dpms_mode;
5681 old->load_detect_temp = false;
5682
5683 /* Make sure the crtc and connector are running */
79e53945 5684 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5685 struct drm_encoder_helper_funcs *encoder_funcs;
5686 struct drm_crtc_helper_funcs *crtc_funcs;
5687
79e53945
JB		 5688 crtc_funcs = crtc->helper_private;
5689 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5690
5691 encoder_funcs = encoder->helper_private;
79e53945
JB		 5692 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5693 }
8261b191 5694
7173188d 5695 return true;
79e53945
JB		 5696 }
5697
5698 /* Find an unused one (if possible) */
5699 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5700 i++;
5701 if (!(encoder->possible_crtcs & (1 << i)))
5702 continue;
5703 if (!possible_crtc->enabled) {
5704 crtc = possible_crtc;
5705 break;
5706 }
79e53945
JB		 5707 }
5708
5709 /*
5710 * If we didn't find an unused CRTC, don't use any.
5711 */
5712 if (!crtc) {
7173188d
CW		 5713 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5714 return false;
79e53945
JB		 5715 }
5716
5717 encoder->crtc = crtc;
c1c43977 5718 connector->encoder = encoder;
79e53945
JB		 5719
5720 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5721 old->dpms_mode = intel_crtc->dpms_mode;
5722 old->load_detect_temp = true;
d2dff872 5723 old->release_fb = NULL;
79e53945 5724
6492711d
CW		 5725 if (!mode)
5726 mode = &load_detect_mode;
79e53945 5727
d2dff872
CW		 5728 old_fb = crtc->fb;
5729
5730 /* We need a framebuffer large enough to accommodate all accesses
5731 * that the plane may generate whilst we perform load detection.
5732 * We can not rely on the fbcon either being present (we get called
5733 * during its initialisation to detect all boot displays, or it may
5734 * not even exist) or that it is large enough to satisfy the
5735 * requested mode.
5736 */
5737 crtc->fb = mode_fits_in_fbdev(dev, mode);
5738 if (crtc->fb == NULL) {
5739 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5740 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5741 old->release_fb = crtc->fb;
5742 } else
5743 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5744 if (IS_ERR(crtc->fb)) {
5745 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5746 crtc->fb = old_fb;
5747 return false;
79e53945 5748 }
79e53945 5749
d2dff872 5750 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5751 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5752 if (old->release_fb)
5753 old->release_fb->funcs->destroy(old->release_fb);
5754 crtc->fb = old_fb;
6492711d 5755 return false;
79e53945 5756 }
7173188d 5757
79e53945 5758 /* let the connector get through one full cycle before testing */
9d0498a2 5759 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5760
7173188d 5761 return true;
79e53945
JB		 5762}
5763
c1c43977 5764void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5765 struct drm_connector *connector,
5766 struct intel_load_detect_pipe *old)
79e53945 5767{
4ef69c7a 5768 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5769 struct drm_device *dev = encoder->dev;
5770 struct drm_crtc *crtc = encoder->crtc;
5771 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5772 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5773
d2dff872
CW		 5774 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5775 connector->base.id, drm_get_connector_name(connector),
5776 encoder->base.id, drm_get_encoder_name(encoder));
5777
8261b191 5778 if (old->load_detect_temp) {
c1c43977 5779 connector->encoder = NULL;
79e53945 5780 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5781
5782 if (old->release_fb)
5783 old->release_fb->funcs->destroy(old->release_fb);
5784
0622a53c 5785 return;
79e53945
JB		 5786 }
5787
c751ce4f 5788 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5789 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5790 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5791 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5792 }
5793}
5794
5795/* Returns the clock of the currently programmed mode of the given pipe. */
5796static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5797{
5798 struct drm_i915_private *dev_priv = dev->dev_private;
5799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5800 int pipe = intel_crtc->pipe;
548f245b 5801 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5802 u32 fp;
5803 intel_clock_t clock;
5804
5805 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5806 fp = I915_READ(FP0(pipe));
79e53945 5807 else
39adb7a5 5808 fp = I915_READ(FP1(pipe));
79e53945
JB		 5809
5810 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5811 if (IS_PINEVIEW(dev)) {
5812 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5813 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5814 } else {
5815 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5816 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5817 }
5818
a6c45cf0 5819 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5820 if (IS_PINEVIEW(dev))
5821 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5822 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5823 else
5824 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5825 DPLL_FPA01_P1_POST_DIV_SHIFT);
5826
5827 switch (dpll & DPLL_MODE_MASK) {
5828 case DPLLB_MODE_DAC_SERIAL:
5829 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5830 5 : 10;
5831 break;
5832 case DPLLB_MODE_LVDS:
5833 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5834 7 : 14;
5835 break;
5836 default:
28c97730 5837 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5838 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5839 return 0;
5840 }
5841
5842 /* XXX: Handle the 100Mhz refclk */
2177832f 5843 intel_clock(dev, 96000, &clock);
79e53945
JB		 5844 } else {
5845 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5846
5847 if (is_lvds) {
5848 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5849 DPLL_FPA01_P1_POST_DIV_SHIFT);
5850 clock.p2 = 14;
5851
5852 if ((dpll & PLL_REF_INPUT_MASK) ==
5853 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5854 /* XXX: might not be 66MHz */
2177832f 5855 intel_clock(dev, 66000, &clock);
79e53945 5856 } else
2177832f 5857 intel_clock(dev, 48000, &clock);
79e53945
JB		 5858 } else {
5859 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5860 clock.p1 = 2;
5861 else {
5862 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5863 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5864 }
5865 if (dpll & PLL_P2_DIVIDE_BY_4)
5866 clock.p2 = 4;
5867 else
5868 clock.p2 = 2;
5869
2177832f 5870 intel_clock(dev, 48000, &clock);
79e53945
JB		 5871 }
5872 }
5873
5874 /* XXX: It would be nice to validate the clocks, but we can't reuse
5875 * i830PllIsValid() because it relies on the xf86_config connector
5876 * configuration being accurate, which it isn't necessarily.
5877 */
5878
5879 return clock.dot;
5880}
5881
5882/** Returns the currently programmed mode of the given pipe. */
5883struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5884 struct drm_crtc *crtc)
5885{
548f245b 5886 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5888 int pipe = intel_crtc->pipe;
5889 struct drm_display_mode *mode;
548f245b
JB		 5890 int htot = I915_READ(HTOTAL(pipe));
5891 int hsync = I915_READ(HSYNC(pipe));
5892 int vtot = I915_READ(VTOTAL(pipe));
5893 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5894
5895 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5896 if (!mode)
5897 return NULL;
5898
5899 mode->clock = intel_crtc_clock_get(dev, crtc);
5900 mode->hdisplay = (htot & 0xffff) + 1;
5901 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5902 mode->hsync_start = (hsync & 0xffff) + 1;
5903 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5904 mode->vdisplay = (vtot & 0xffff) + 1;
5905 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5906 mode->vsync_start = (vsync & 0xffff) + 1;
5907 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5908
5909 drm_mode_set_name(mode);
5910 drm_mode_set_crtcinfo(mode, 0);
5911
5912 return mode;
5913}
5914
652c393a
JB		 5915#define GPU_IDLE_TIMEOUT 500 /* ms */
5916
5917/* When this timer fires, we've been idle for awhile */
5918static void intel_gpu_idle_timer(unsigned long arg)
5919{
5920 struct drm_device *dev = (struct drm_device *)arg;
5921 drm_i915_private_t *dev_priv = dev->dev_private;
5922
ff7ea4c0
CW		 5923 if (!list_empty(&dev_priv->mm.active_list)) {
5924 /* Still processing requests, so just re-arm the timer. */
5925 mod_timer(&dev_priv->idle_timer, jiffies +
5926 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5927 return;
5928 }
652c393a 5929
ff7ea4c0 5930 dev_priv->busy = false;
01dfba93 5931 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5932}
5933
652c393a
JB		 5934#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5935
5936static void intel_crtc_idle_timer(unsigned long arg)
5937{
5938 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5939 struct drm_crtc *crtc = &intel_crtc->base;
5940 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 5941 struct intel_framebuffer *intel_fb;
652c393a 5942
ff7ea4c0
CW		 5943 intel_fb = to_intel_framebuffer(crtc->fb);
5944 if (intel_fb && intel_fb->obj->active) {
5945 /* The framebuffer is still being accessed by the GPU. */
5946 mod_timer(&intel_crtc->idle_timer, jiffies +
5947 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5948 return;
5949 }
652c393a 5950
ff7ea4c0 5951 intel_crtc->busy = false;
01dfba93 5952 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5953}
5954
3dec0095 5955static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5956{
5957 struct drm_device *dev = crtc->dev;
5958 drm_i915_private_t *dev_priv = dev->dev_private;
5959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5960 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5961 int dpll_reg = DPLL(pipe);
5962 int dpll;
652c393a 5963
bad720ff 5964 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5965 return;
5966
5967 if (!dev_priv->lvds_downclock_avail)
5968 return;
5969
dbdc6479 5970 dpll = I915_READ(dpll_reg);
652c393a 5971 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 5972 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 5973
5974 /* Unlock panel regs */
dbdc6479
JB		 5975 I915_WRITE(PP_CONTROL,
5976 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 5977
5978 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5979 I915_WRITE(dpll_reg, dpll);
9d0498a2 5980 intel_wait_for_vblank(dev, pipe);
dbdc6479 5981
652c393a
JB		 5982 dpll = I915_READ(dpll_reg);
5983 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 5984 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 5985
5986 /* ...and lock them again */
5987 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5988 }
5989
5990 /* Schedule downclock */
3dec0095
DV		 5991 mod_timer(&intel_crtc->idle_timer, jiffies +
5992 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 5993}
5994
5995static void intel_decrease_pllclock(struct drm_crtc *crtc)
5996{
5997 struct drm_device *dev = crtc->dev;
5998 drm_i915_private_t *dev_priv = dev->dev_private;
5999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6000 int pipe = intel_crtc->pipe;
9db4a9c7 6001 int dpll_reg = DPLL(pipe);
652c393a
JB		 6002 int dpll = I915_READ(dpll_reg);
6003
bad720ff 6004 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6005 return;
6006
6007 if (!dev_priv->lvds_downclock_avail)
6008 return;
6009
6010 /*
6011 * Since this is called by a timer, we should never get here in
6012 * the manual case.
6013 */
6014 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 6015 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 6016
6017 /* Unlock panel regs */
4a655f04
JB		 6018 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6019 PANEL_UNLOCK_REGS);
652c393a
JB		 6020
6021 dpll |= DISPLAY_RATE_SELECT_FPA1;
6022 I915_WRITE(dpll_reg, dpll);
9d0498a2 6023 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6024 dpll = I915_READ(dpll_reg);
6025 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6026 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6027
6028 /* ...and lock them again */
6029 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6030 }
6031
6032}
6033
6034/**
6035 * intel_idle_update - adjust clocks for idleness
6036 * @work: work struct
6037 *
6038 * Either the GPU or display (or both) went idle. Check the busy status
6039 * here and adjust the CRTC and GPU clocks as necessary.
6040 */
6041static void intel_idle_update(struct work_struct *work)
6042{
6043 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6044 idle_work);
6045 struct drm_device *dev = dev_priv->dev;
6046 struct drm_crtc *crtc;
6047 struct intel_crtc *intel_crtc;
6048
6049 if (!i915_powersave)
6050 return;
6051
6052 mutex_lock(&dev->struct_mutex);
6053
7648fa99
JB		 6054 i915_update_gfx_val(dev_priv);
6055
652c393a
JB		 6056 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6057 /* Skip inactive CRTCs */
6058 if (!crtc->fb)
6059 continue;
6060
6061 intel_crtc = to_intel_crtc(crtc);
6062 if (!intel_crtc->busy)
6063 intel_decrease_pllclock(crtc);
6064 }
6065
45ac22c8 6066
652c393a
JB		 6067 mutex_unlock(&dev->struct_mutex);
6068}
6069
6070/**
6071 * intel_mark_busy - mark the GPU and possibly the display busy
6072 * @dev: drm device
6073 * @obj: object we're operating on
6074 *
6075 * Callers can use this function to indicate that the GPU is busy processing
6076 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6077 * buffer), we'll also mark the display as busy, so we know to increase its
6078 * clock frequency.
6079 */
05394f39 6080void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 6081{
6082 drm_i915_private_t *dev_priv = dev->dev_private;
6083 struct drm_crtc *crtc = NULL;
6084 struct intel_framebuffer *intel_fb;
6085 struct intel_crtc *intel_crtc;
6086
5e17ee74
ZW		 6087 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6088 return;
6089
18b2190c 6090 if (!dev_priv->busy)
28cf798f 6091 dev_priv->busy = true;
18b2190c 6092 else
28cf798f
CW		 6093 mod_timer(&dev_priv->idle_timer, jiffies +
6094 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 6095
6096 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6097 if (!crtc->fb)
6098 continue;
6099
6100 intel_crtc = to_intel_crtc(crtc);
6101 intel_fb = to_intel_framebuffer(crtc->fb);
6102 if (intel_fb->obj == obj) {
6103 if (!intel_crtc->busy) {
6104 /* Non-busy -> busy, upclock */
3dec0095 6105 intel_increase_pllclock(crtc);
652c393a
JB		 6106 intel_crtc->busy = true;
6107 } else {
6108 /* Busy -> busy, put off timer */
6109 mod_timer(&intel_crtc->idle_timer, jiffies +
6110 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6111 }
6112 }
6113 }
6114}
6115
79e53945
JB		 6116static void intel_crtc_destroy(struct drm_crtc *crtc)
6117{
6118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6119 struct drm_device *dev = crtc->dev;
6120 struct intel_unpin_work *work;
6121 unsigned long flags;
6122
6123 spin_lock_irqsave(&dev->event_lock, flags);
6124 work = intel_crtc->unpin_work;
6125 intel_crtc->unpin_work = NULL;
6126 spin_unlock_irqrestore(&dev->event_lock, flags);
6127
6128 if (work) {
6129 cancel_work_sync(&work->work);
6130 kfree(work);
6131 }
79e53945
JB		 6132
6133 drm_crtc_cleanup(crtc);
67e77c5a 6134
79e53945
JB		 6135 kfree(intel_crtc);
6136}
6137
6b95a207
KH		 6138static void intel_unpin_work_fn(struct work_struct *__work)
6139{
6140 struct intel_unpin_work *work =
6141 container_of(__work, struct intel_unpin_work, work);
6142
6143 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 6144 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW		 6145 drm_gem_object_unreference(&work->pending_flip_obj->base);
6146 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6147
6b95a207
KH		 6148 mutex_unlock(&work->dev->struct_mutex);
6149 kfree(work);
6150}
6151
1afe3e9d 6152static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6153 struct drm_crtc *crtc)
6b95a207
KH		 6154{
6155 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6157 struct intel_unpin_work *work;
05394f39 6158 struct drm_i915_gem_object *obj;
6b95a207 6159 struct drm_pending_vblank_event *e;
49b14a5c 6160 struct timeval tnow, tvbl;
6b95a207
KH		 6161 unsigned long flags;
6162
6163 /* Ignore early vblank irqs */
6164 if (intel_crtc == NULL)
6165 return;
6166
49b14a5c
MK		 6167 do_gettimeofday(&tnow);
6168
6b95a207
KH		 6169 spin_lock_irqsave(&dev->event_lock, flags);
6170 work = intel_crtc->unpin_work;
6171 if (work == NULL || !work->pending) {
6172 spin_unlock_irqrestore(&dev->event_lock, flags);
6173 return;
6174 }
6175
6176 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6177
6178 if (work->event) {
6179 e = work->event;
49b14a5c 6180 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6181
6182 /* Called before vblank count and timestamps have
6183 * been updated for the vblank interval of flip
6184 * completion? Need to increment vblank count and
6185 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6186 * to account for this. We assume this happened if we
6187 * get called over 0.9 frame durations after the last
6188 * timestamped vblank.
6189 *
6190 * This calculation can not be used with vrefresh rates
6191 * below 5Hz (10Hz to be on the safe side) without
6192 * promoting to 64 integers.
0af7e4df 6193 */
49b14a5c
MK		 6194 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6195 9 * crtc->framedur_ns) {
0af7e4df 6196 e->event.sequence++;
49b14a5c
MK		 6197 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6198 crtc->framedur_ns);
0af7e4df
MK		 6199 }
6200
49b14a5c
MK		 6201 e->event.tv_sec = tvbl.tv_sec;
6202 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6203
6b95a207
KH		 6204 list_add_tail(&e->base.link,
6205 &e->base.file_priv->event_list);
6206 wake_up_interruptible(&e->base.file_priv->event_wait);
6207 }
6208
0af7e4df
MK		 6209 drm_vblank_put(dev, intel_crtc->pipe);
6210
6b95a207
KH		 6211 spin_unlock_irqrestore(&dev->event_lock, flags);
6212
05394f39 6213 obj = work->old_fb_obj;
d9e86c0e 6214
e59f2bac 6215 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6216 &obj->pending_flip.counter);
6217 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6218 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6219
6b95a207 6220 schedule_work(&work->work);
e5510fac
JB		 6221
6222 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6223}
6224
1afe3e9d
JB		 6225void intel_finish_page_flip(struct drm_device *dev, int pipe)
6226{
6227 drm_i915_private_t *dev_priv = dev->dev_private;
6228 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6229
49b14a5c 6230 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6231}
6232
6233void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6234{
6235 drm_i915_private_t *dev_priv = dev->dev_private;
6236 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6237
49b14a5c 6238 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6239}
6240
6b95a207
KH		 6241void intel_prepare_page_flip(struct drm_device *dev, int plane)
6242{
6243 drm_i915_private_t *dev_priv = dev->dev_private;
6244 struct intel_crtc *intel_crtc =
6245 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6246 unsigned long flags;
6247
6248 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6249 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6250 if ((++intel_crtc->unpin_work->pending) > 1)
6251 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6252 } else {
6253 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6254 }
6b95a207
KH		 6255 spin_unlock_irqrestore(&dev->event_lock, flags);
6256}
6257
8c9f3aaf
JB		 6258static int intel_gen2_queue_flip(struct drm_device *dev,
6259 struct drm_crtc *crtc,
6260 struct drm_framebuffer *fb,
6261 struct drm_i915_gem_object *obj)
6262{
6263 struct drm_i915_private *dev_priv = dev->dev_private;
6264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6265 unsigned long offset;
6266 u32 flip_mask;
6267 int ret;
6268
6269 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6270 if (ret)
6271 goto out;
6272
6273 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6274 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6275
6276 ret = BEGIN_LP_RING(6);
6277 if (ret)
6278 goto out;
6279
6280 /* Can't queue multiple flips, so wait for the previous
6281 * one to finish before executing the next.
6282 */
6283 if (intel_crtc->plane)
6284 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6285 else
6286 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6287 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6288 OUT_RING(MI_NOOP);
6289 OUT_RING(MI_DISPLAY_FLIP |
6290 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6291 OUT_RING(fb->pitch);
6292 OUT_RING(obj->gtt_offset + offset);
6293 OUT_RING(MI_NOOP);
6294 ADVANCE_LP_RING();
6295out:
6296 return ret;
6297}
6298
6299static int intel_gen3_queue_flip(struct drm_device *dev,
6300 struct drm_crtc *crtc,
6301 struct drm_framebuffer *fb,
6302 struct drm_i915_gem_object *obj)
6303{
6304 struct drm_i915_private *dev_priv = dev->dev_private;
6305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6306 unsigned long offset;
6307 u32 flip_mask;
6308 int ret;
6309
6310 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6311 if (ret)
6312 goto out;
6313
6314 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6315 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6316
6317 ret = BEGIN_LP_RING(6);
6318 if (ret)
6319 goto out;
6320
6321 if (intel_crtc->plane)
6322 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6323 else
6324 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6325 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6326 OUT_RING(MI_NOOP);
6327 OUT_RING(MI_DISPLAY_FLIP_I915 |
6328 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6329 OUT_RING(fb->pitch);
6330 OUT_RING(obj->gtt_offset + offset);
6331 OUT_RING(MI_NOOP);
6332
6333 ADVANCE_LP_RING();
6334out:
6335 return ret;
6336}
6337
6338static int intel_gen4_queue_flip(struct drm_device *dev,
6339 struct drm_crtc *crtc,
6340 struct drm_framebuffer *fb,
6341 struct drm_i915_gem_object *obj)
6342{
6343 struct drm_i915_private *dev_priv = dev->dev_private;
6344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6345 uint32_t pf, pipesrc;
6346 int ret;
6347
6348 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6349 if (ret)
6350 goto out;
6351
6352 ret = BEGIN_LP_RING(4);
6353 if (ret)
6354 goto out;
6355
6356 /* i965+ uses the linear or tiled offsets from the
6357 * Display Registers (which do not change across a page-flip)
6358 * so we need only reprogram the base address.
6359 */
6360 OUT_RING(MI_DISPLAY_FLIP |
6361 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6362 OUT_RING(fb->pitch);
6363 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6364
6365 /* XXX Enabling the panel-fitter across page-flip is so far
6366 * untested on non-native modes, so ignore it for now.
6367 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6368 */
6369 pf = 0;
6370 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6371 OUT_RING(pf | pipesrc);
6372 ADVANCE_LP_RING();
6373out:
6374 return ret;
6375}
6376
6377static int intel_gen6_queue_flip(struct drm_device *dev,
6378 struct drm_crtc *crtc,
6379 struct drm_framebuffer *fb,
6380 struct drm_i915_gem_object *obj)
6381{
6382 struct drm_i915_private *dev_priv = dev->dev_private;
6383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6384 uint32_t pf, pipesrc;
6385 int ret;
6386
6387 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6388 if (ret)
6389 goto out;
6390
6391 ret = BEGIN_LP_RING(4);
6392 if (ret)
6393 goto out;
6394
6395 OUT_RING(MI_DISPLAY_FLIP |
6396 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6397 OUT_RING(fb->pitch | obj->tiling_mode);
6398 OUT_RING(obj->gtt_offset);
6399
6400 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6401 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6402 OUT_RING(pf | pipesrc);
6403 ADVANCE_LP_RING();
6404out:
6405 return ret;
6406}
6407
7c9017e5
JB		 6408/*
6409 * On gen7 we currently use the blit ring because (in early silicon at least)
6410 * the render ring doesn't give us interrpts for page flip completion, which
6411 * means clients will hang after the first flip is queued. Fortunately the
6412 * blit ring generates interrupts properly, so use it instead.
6413 */
6414static int intel_gen7_queue_flip(struct drm_device *dev,
6415 struct drm_crtc *crtc,
6416 struct drm_framebuffer *fb,
6417 struct drm_i915_gem_object *obj)
6418{
6419 struct drm_i915_private *dev_priv = dev->dev_private;
6420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6421 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6422 int ret;
6423
6424 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6425 if (ret)
6426 goto out;
6427
6428 ret = intel_ring_begin(ring, 4);
6429 if (ret)
6430 goto out;
6431
6432 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6433 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6434 intel_ring_emit(ring, (obj->gtt_offset));
6435 intel_ring_emit(ring, (MI_NOOP));
6436 intel_ring_advance(ring);
6437out:
6438 return ret;
6439}
6440
8c9f3aaf
JB		 6441static int intel_default_queue_flip(struct drm_device *dev,
6442 struct drm_crtc *crtc,
6443 struct drm_framebuffer *fb,
6444 struct drm_i915_gem_object *obj)
6445{
6446 return -ENODEV;
6447}
6448
6b95a207
KH		 6449static int intel_crtc_page_flip(struct drm_crtc *crtc,
6450 struct drm_framebuffer *fb,
6451 struct drm_pending_vblank_event *event)
6452{
6453 struct drm_device *dev = crtc->dev;
6454 struct drm_i915_private *dev_priv = dev->dev_private;
6455 struct intel_framebuffer *intel_fb;
05394f39 6456 struct drm_i915_gem_object *obj;
6b95a207
KH		 6457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6458 struct intel_unpin_work *work;
8c9f3aaf 6459 unsigned long flags;
52e68630 6460 int ret;
6b95a207
KH		 6461
6462 work = kzalloc(sizeof *work, GFP_KERNEL);
6463 if (work == NULL)
6464 return -ENOMEM;
6465
6b95a207
KH		 6466 work->event = event;
6467 work->dev = crtc->dev;
6468 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6469 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6470 INIT_WORK(&work->work, intel_unpin_work_fn);
6471
6472 /* We borrow the event spin lock for protecting unpin_work */
6473 spin_lock_irqsave(&dev->event_lock, flags);
6474 if (intel_crtc->unpin_work) {
6475 spin_unlock_irqrestore(&dev->event_lock, flags);
6476 kfree(work);
468f0b44
CW		 6477
6478 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6479 return -EBUSY;
6480 }
6481 intel_crtc->unpin_work = work;
6482 spin_unlock_irqrestore(&dev->event_lock, flags);
6483
6484 intel_fb = to_intel_framebuffer(fb);
6485 obj = intel_fb->obj;
6486
468f0b44 6487 mutex_lock(&dev->struct_mutex);
6b95a207 6488
75dfca80 6489 /* Reference the objects for the scheduled work. */
05394f39
CW		 6490 drm_gem_object_reference(&work->old_fb_obj->base);
6491 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6492
6493 crtc->fb = fb;
96b099fd
CW		 6494
6495 ret = drm_vblank_get(dev, intel_crtc->pipe);
6496 if (ret)
6497 goto cleanup_objs;
6498
e1f99ce6 6499 work->pending_flip_obj = obj;
e1f99ce6 6500
4e5359cd
SF		 6501 work->enable_stall_check = true;
6502
e1f99ce6
CW		 6503 /* Block clients from rendering to the new back buffer until
6504 * the flip occurs and the object is no longer visible.
6505 */
05394f39 6506 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6507
8c9f3aaf
JB		 6508 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6509 if (ret)
6510 goto cleanup_pending;
6b95a207
KH		 6511
6512 mutex_unlock(&dev->struct_mutex);
6513
e5510fac
JB		 6514 trace_i915_flip_request(intel_crtc->plane, obj);
6515
6b95a207 6516 return 0;
96b099fd 6517
8c9f3aaf
JB		 6518cleanup_pending:
6519 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
96b099fd 6520cleanup_objs:
05394f39
CW		 6521 drm_gem_object_unreference(&work->old_fb_obj->base);
6522 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6523 mutex_unlock(&dev->struct_mutex);
6524
6525 spin_lock_irqsave(&dev->event_lock, flags);
6526 intel_crtc->unpin_work = NULL;
6527 spin_unlock_irqrestore(&dev->event_lock, flags);
6528
6529 kfree(work);
6530
6531 return ret;
6b95a207
KH		 6532}
6533
47f1c6c9
CW		 6534static void intel_sanitize_modesetting(struct drm_device *dev,
6535 int pipe, int plane)
6536{
6537 struct drm_i915_private *dev_priv = dev->dev_private;
6538 u32 reg, val;
6539
6540 if (HAS_PCH_SPLIT(dev))
6541 return;
6542
6543 /* Who knows what state these registers were left in by the BIOS or
6544 * grub?
6545 *
6546 * If we leave the registers in a conflicting state (e.g. with the
6547 * display plane reading from the other pipe than the one we intend
6548 * to use) then when we attempt to teardown the active mode, we will
6549 * not disable the pipes and planes in the correct order -- leaving
6550 * a plane reading from a disabled pipe and possibly leading to
6551 * undefined behaviour.
6552 */
6553
6554 reg = DSPCNTR(plane);
6555 val = I915_READ(reg);
6556
6557 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6558 return;
6559 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6560 return;
6561
6562 /* This display plane is active and attached to the other CPU pipe. */
6563 pipe = !pipe;
6564
6565 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6566 intel_disable_plane(dev_priv, plane, pipe);
6567 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6568}
79e53945 6569
f6e5b160
CW		 6570static void intel_crtc_reset(struct drm_crtc *crtc)
6571{
6572 struct drm_device *dev = crtc->dev;
6573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6574
6575 /* Reset flags back to the 'unknown' status so that they
6576 * will be correctly set on the initial modeset.
6577 */
6578 intel_crtc->dpms_mode = -1;
6579
6580 /* We need to fix up any BIOS configuration that conflicts with
6581 * our expectations.
6582 */
6583 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6584}
6585
6586static struct drm_crtc_helper_funcs intel_helper_funcs = {
6587 .dpms = intel_crtc_dpms,
6588 .mode_fixup = intel_crtc_mode_fixup,
6589 .mode_set = intel_crtc_mode_set,
6590 .mode_set_base = intel_pipe_set_base,
6591 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6592 .load_lut = intel_crtc_load_lut,
6593 .disable = intel_crtc_disable,
6594};
6595
6596static const struct drm_crtc_funcs intel_crtc_funcs = {
6597 .reset = intel_crtc_reset,
6598 .cursor_set = intel_crtc_cursor_set,
6599 .cursor_move = intel_crtc_cursor_move,
6600 .gamma_set = intel_crtc_gamma_set,
6601 .set_config = drm_crtc_helper_set_config,
6602 .destroy = intel_crtc_destroy,
6603 .page_flip = intel_crtc_page_flip,
6604};
6605
b358d0a6 6606static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6607{
22fd0fab 6608 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6609 struct intel_crtc *intel_crtc;
6610 int i;
6611
6612 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6613 if (intel_crtc == NULL)
6614 return;
6615
6616 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6617
6618 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6619 for (i = 0; i < 256; i++) {
6620 intel_crtc->lut_r[i] = i;
6621 intel_crtc->lut_g[i] = i;
6622 intel_crtc->lut_b[i] = i;
6623 }
6624
80824003
JB		 6625 /* Swap pipes & planes for FBC on pre-965 */
6626 intel_crtc->pipe = pipe;
6627 intel_crtc->plane = pipe;
e2e767ab 6628 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6629 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6630 intel_crtc->plane = !pipe;
80824003
JB		 6631 }
6632
22fd0fab
JB		 6633 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6634 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6635 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6636 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6637
5d1d0cc8 6638 intel_crtc_reset(&intel_crtc->base);
04dbff52 6639 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7e7d76c3
JB		 6640
6641 if (HAS_PCH_SPLIT(dev)) {
6642 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6643 intel_helper_funcs.commit = ironlake_crtc_commit;
6644 } else {
6645 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6646 intel_helper_funcs.commit = i9xx_crtc_commit;
6647 }
6648
79e53945
JB		 6649 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6650
652c393a
JB		 6651 intel_crtc->busy = false;
6652
6653 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6654 (unsigned long)intel_crtc);
79e53945
JB		 6655}
6656
08d7b3d1 6657int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6658 struct drm_file *file)
08d7b3d1
CW		 6659{
6660 drm_i915_private_t *dev_priv = dev->dev_private;
6661 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6662 struct drm_mode_object *drmmode_obj;
6663 struct intel_crtc *crtc;
08d7b3d1
CW		 6664
6665 if (!dev_priv) {
6666 DRM_ERROR("called with no initialization\n");
6667 return -EINVAL;
6668 }
6669
c05422d5
DV		 6670 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6671 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6672
c05422d5 6673 if (!drmmode_obj) {
08d7b3d1
CW		 6674 DRM_ERROR("no such CRTC id\n");
6675 return -EINVAL;
6676 }
6677
c05422d5
DV		 6678 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6679 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6680
c05422d5 6681 return 0;
08d7b3d1
CW		 6682}
6683
c5e4df33 6684static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6685{
4ef69c7a 6686 struct intel_encoder *encoder;
79e53945 6687 int index_mask = 0;
79e53945
JB		 6688 int entry = 0;
6689
4ef69c7a
CW		 6690 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6691 if (type_mask & encoder->clone_mask)
79e53945
JB		 6692 index_mask |= (1 << entry);
6693 entry++;
6694 }
4ef69c7a 6695
79e53945
JB		 6696 return index_mask;
6697}
6698
4d302442
CW		 6699static bool has_edp_a(struct drm_device *dev)
6700{
6701 struct drm_i915_private *dev_priv = dev->dev_private;
6702
6703 if (!IS_MOBILE(dev))
6704 return false;
6705
6706 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6707 return false;
6708
6709 if (IS_GEN5(dev) &&
6710 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6711 return false;
6712
6713 return true;
6714}
6715
79e53945
JB		 6716static void intel_setup_outputs(struct drm_device *dev)
6717{
725e30ad 6718 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6719 struct intel_encoder *encoder;
cb0953d7 6720 bool dpd_is_edp = false;
c5d1b51d 6721 bool has_lvds = false;
79e53945 6722
541998a1 6723 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 6724 has_lvds = intel_lvds_init(dev);
6725 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6726 /* disable the panel fitter on everything but LVDS */
6727 I915_WRITE(PFIT_CONTROL, 0);
6728 }
79e53945 6729
bad720ff 6730 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6731 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6732
4d302442 6733 if (has_edp_a(dev))
32f9d658
ZW		 6734 intel_dp_init(dev, DP_A);
6735
cb0953d7
AJ		 6736 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6737 intel_dp_init(dev, PCH_DP_D);
6738 }
6739
6740 intel_crt_init(dev);
6741
6742 if (HAS_PCH_SPLIT(dev)) {
6743 int found;
6744
30ad48b7 6745 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 6746 /* PCH SDVOB multiplex with HDMIB */
6747 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 6748 if (!found)
6749 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6750 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6751 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6752 }
6753
6754 if (I915_READ(HDMIC) & PORT_DETECTED)
6755 intel_hdmi_init(dev, HDMIC);
6756
6757 if (I915_READ(HDMID) & PORT_DETECTED)
6758 intel_hdmi_init(dev, HDMID);
6759
5eb08b69
ZW		 6760 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6761 intel_dp_init(dev, PCH_DP_C);
6762
cb0953d7 6763 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 6764 intel_dp_init(dev, PCH_DP_D);
6765
103a196f 6766 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6767 bool found = false;
7d57382e 6768
725e30ad 6769 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6770 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 6771 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 6772 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6773 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6774 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6775 }
27185ae1 6776
b01f2c3a
JB		 6777 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6778 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6779 intel_dp_init(dev, DP_B);
b01f2c3a 6780 }
725e30ad 6781 }
13520b05
KH		 6782
6783 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6784
b01f2c3a
JB		 6785 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6786 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 6787 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 6788 }
27185ae1
ML		 6789
6790 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6791
b01f2c3a
JB		 6792 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6793 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6794 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6795 }
6796 if (SUPPORTS_INTEGRATED_DP(dev)) {
6797 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6798 intel_dp_init(dev, DP_C);
b01f2c3a 6799 }
725e30ad 6800 }
27185ae1 6801
b01f2c3a
JB		 6802 if (SUPPORTS_INTEGRATED_DP(dev) &&
6803 (I915_READ(DP_D) & DP_DETECTED)) {
6804 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 6805 intel_dp_init(dev, DP_D);
b01f2c3a 6806 }
bad720ff 6807 } else if (IS_GEN2(dev))
79e53945
JB		 6808 intel_dvo_init(dev);
6809
103a196f 6810 if (SUPPORTS_TV(dev))
79e53945
JB		 6811 intel_tv_init(dev);
6812
4ef69c7a
CW		 6813 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6814 encoder->base.possible_crtcs = encoder->crtc_mask;
6815 encoder->base.possible_clones =
6816 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 6817 }
47356eb6
CW		 6818
6819 intel_panel_setup_backlight(dev);
2c7111db
CW		 6820
6821 /* disable all the possible outputs/crtcs before entering KMS mode */
6822 drm_helper_disable_unused_functions(dev);
79e53945
JB		 6823}
6824
6825static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6826{
6827 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6828
6829 drm_framebuffer_cleanup(fb);
05394f39 6830 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6831
6832 kfree(intel_fb);
6833}
6834
6835static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6836 struct drm_file *file,
79e53945
JB		 6837 unsigned int *handle)
6838{
6839 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6840 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6841
05394f39 6842 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6843}
6844
6845static const struct drm_framebuffer_funcs intel_fb_funcs = {
6846 .destroy = intel_user_framebuffer_destroy,
6847 .create_handle = intel_user_framebuffer_create_handle,
6848};
6849
38651674
DA		 6850int intel_framebuffer_init(struct drm_device *dev,
6851 struct intel_framebuffer *intel_fb,
6852 struct drm_mode_fb_cmd *mode_cmd,
05394f39 6853 struct drm_i915_gem_object *obj)
79e53945 6854{
79e53945
JB		 6855 int ret;
6856
05394f39 6857 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6858 return -EINVAL;
6859
6860 if (mode_cmd->pitch & 63)
6861 return -EINVAL;
6862
6863 switch (mode_cmd->bpp) {
6864 case 8:
6865 case 16:
6866 case 24:
6867 case 32:
6868 break;
6869 default:
6870 return -EINVAL;
6871 }
6872
79e53945
JB		 6873 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6874 if (ret) {
6875 DRM_ERROR("framebuffer init failed %d\n", ret);
6876 return ret;
6877 }
6878
6879 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6880 intel_fb->obj = obj;
79e53945
JB		 6881 return 0;
6882}
6883
79e53945
JB		 6884static struct drm_framebuffer *
6885intel_user_framebuffer_create(struct drm_device *dev,
6886 struct drm_file *filp,
6887 struct drm_mode_fb_cmd *mode_cmd)
6888{
05394f39 6889 struct drm_i915_gem_object *obj;
79e53945 6890
05394f39 6891 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
c8725226 6892 if (&obj->base == NULL)
cce13ff7 6893 return ERR_PTR(-ENOENT);
79e53945 6894
d2dff872 6895 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6896}
6897
79e53945 6898static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6899 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6900 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6901};
6902
05394f39 6903static struct drm_i915_gem_object *
aa40d6bb 6904intel_alloc_context_page(struct drm_device *dev)
9ea8d059 6905{
05394f39 6906 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 6907 int ret;
6908
2c34b850
BW		 6909 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
6910
aa40d6bb
ZN		 6911 ctx = i915_gem_alloc_object(dev, 4096);
6912 if (!ctx) {
9ea8d059
CW		 6913 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6914 return NULL;
6915 }
6916
75e9e915 6917 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 6918 if (ret) {
6919 DRM_ERROR("failed to pin power context: %d\n", ret);
6920 goto err_unref;
6921 }
6922
aa40d6bb 6923 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 6924 if (ret) {
6925 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6926 goto err_unpin;
6927 }
9ea8d059 6928
aa40d6bb 6929 return ctx;
9ea8d059
CW		 6930
6931err_unpin:
aa40d6bb 6932 i915_gem_object_unpin(ctx);
9ea8d059 6933err_unref:
05394f39 6934 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 6935 mutex_unlock(&dev->struct_mutex);
6936 return NULL;
6937}
6938
7648fa99
JB		 6939bool ironlake_set_drps(struct drm_device *dev, u8 val)
6940{
6941 struct drm_i915_private *dev_priv = dev->dev_private;
6942 u16 rgvswctl;
6943
6944 rgvswctl = I915_READ16(MEMSWCTL);
6945 if (rgvswctl & MEMCTL_CMD_STS) {
6946 DRM_DEBUG("gpu busy, RCS change rejected\n");
6947 return false; /* still busy with another command */
6948 }
6949
6950 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6951 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6952 I915_WRITE16(MEMSWCTL, rgvswctl);
6953 POSTING_READ16(MEMSWCTL);
6954
6955 rgvswctl |= MEMCTL_CMD_STS;
6956 I915_WRITE16(MEMSWCTL, rgvswctl);
6957
6958 return true;
6959}
6960
f97108d1
JB		 6961void ironlake_enable_drps(struct drm_device *dev)
6962{
6963 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 6964 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 6965 u8 fmax, fmin, fstart, vstart;
f97108d1 6966
ea056c14
JB		 6967 /* Enable temp reporting */
6968 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6969 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6970
f97108d1
JB		 6971 /* 100ms RC evaluation intervals */
6972 I915_WRITE(RCUPEI, 100000);
6973 I915_WRITE(RCDNEI, 100000);
6974
6975 /* Set max/min thresholds to 90ms and 80ms respectively */
6976 I915_WRITE(RCBMAXAVG, 90000);
6977 I915_WRITE(RCBMINAVG, 80000);
6978
6979 I915_WRITE(MEMIHYST, 1);
6980
6981 /* Set up min, max, and cur for interrupt handling */
6982 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6983 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6984 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6985 MEMMODE_FSTART_SHIFT;
7648fa99 6986
f97108d1
JB		 6987 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6988 PXVFREQ_PX_SHIFT;
6989
80dbf4b7 6990 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 6991 dev_priv->fstart = fstart;
6992
80dbf4b7 6993 dev_priv->max_delay = fstart;
f97108d1
JB		 6994 dev_priv->min_delay = fmin;
6995 dev_priv->cur_delay = fstart;
6996
80dbf4b7
JB		 6997 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6998 fmax, fmin, fstart);
7648fa99 6999
f97108d1
JB		 7000 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7001
7002 /*
7003 * Interrupts will be enabled in ironlake_irq_postinstall
7004 */
7005
7006 I915_WRITE(VIDSTART, vstart);
7007 POSTING_READ(VIDSTART);
7008
7009 rgvmodectl |= MEMMODE_SWMODE_EN;
7010 I915_WRITE(MEMMODECTL, rgvmodectl);
7011
481b6af3 7012 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 7013 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 7014 msleep(1);
7015
7648fa99 7016 ironlake_set_drps(dev, fstart);
f97108d1 7017
7648fa99
JB		 7018 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7019 I915_READ(0x112e0);
7020 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7021 dev_priv->last_count2 = I915_READ(0x112f4);
7022 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 7023}
7024
7025void ironlake_disable_drps(struct drm_device *dev)
7026{
7027 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7028 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 7029
7030 /* Ack interrupts, disable EFC interrupt */
7031 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7032 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7033 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7034 I915_WRITE(DEIIR, DE_PCU_EVENT);
7035 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7036
7037 /* Go back to the starting frequency */
7648fa99 7038 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 7039 msleep(1);
7040 rgvswctl |= MEMCTL_CMD_STS;
7041 I915_WRITE(MEMSWCTL, rgvswctl);
7042 msleep(1);
7043
7044}
7045
3b8d8d91
JB		 7046void gen6_set_rps(struct drm_device *dev, u8 val)
7047{
7048 struct drm_i915_private *dev_priv = dev->dev_private;
7049 u32 swreq;
7050
7051 swreq = (val & 0x3ff) << 25;
7052 I915_WRITE(GEN6_RPNSWREQ, swreq);
7053}
7054
7055void gen6_disable_rps(struct drm_device *dev)
7056{
7057 struct drm_i915_private *dev_priv = dev->dev_private;
7058
7059 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7060 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7061 I915_WRITE(GEN6_PMIER, 0);
4912d041
BW		 7062
7063 spin_lock_irq(&dev_priv->rps_lock);
7064 dev_priv->pm_iir = 0;
7065 spin_unlock_irq(&dev_priv->rps_lock);
7066
3b8d8d91
JB		 7067 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7068}
7069
7648fa99
JB		 7070static unsigned long intel_pxfreq(u32 vidfreq)
7071{
7072 unsigned long freq;
7073 int div = (vidfreq & 0x3f0000) >> 16;
7074 int post = (vidfreq & 0x3000) >> 12;
7075 int pre = (vidfreq & 0x7);
7076
7077 if (!pre)
7078 return 0;
7079
7080 freq = ((div * 133333) / ((1<<post) * pre));
7081
7082 return freq;
7083}
7084
7085void intel_init_emon(struct drm_device *dev)
7086{
7087 struct drm_i915_private *dev_priv = dev->dev_private;
7088 u32 lcfuse;
7089 u8 pxw[16];
7090 int i;
7091
7092 /* Disable to program */
7093 I915_WRITE(ECR, 0);
7094 POSTING_READ(ECR);
7095
7096 /* Program energy weights for various events */
7097 I915_WRITE(SDEW, 0x15040d00);
7098 I915_WRITE(CSIEW0, 0x007f0000);
7099 I915_WRITE(CSIEW1, 0x1e220004);
7100 I915_WRITE(CSIEW2, 0x04000004);
7101
7102 for (i = 0; i < 5; i++)
7103 I915_WRITE(PEW + (i * 4), 0);
7104 for (i = 0; i < 3; i++)
7105 I915_WRITE(DEW + (i * 4), 0);
7106
7107 /* Program P-state weights to account for frequency power adjustment */
7108 for (i = 0; i < 16; i++) {
7109 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7110 unsigned long freq = intel_pxfreq(pxvidfreq);
7111 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7112 PXVFREQ_PX_SHIFT;
7113 unsigned long val;
7114
7115 val = vid * vid;
7116 val *= (freq / 1000);
7117 val *= 255;
7118 val /= (127*127*900);
7119 if (val > 0xff)
7120 DRM_ERROR("bad pxval: %ld\n", val);
7121 pxw[i] = val;
7122 }
7123 /* Render standby states get 0 weight */
7124 pxw[14] = 0;
7125 pxw[15] = 0;
7126
7127 for (i = 0; i < 4; i++) {
7128 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7129 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7130 I915_WRITE(PXW + (i * 4), val);
7131 }
7132
7133 /* Adjust magic regs to magic values (more experimental results) */
7134 I915_WRITE(OGW0, 0);
7135 I915_WRITE(OGW1, 0);
7136 I915_WRITE(EG0, 0x00007f00);
7137 I915_WRITE(EG1, 0x0000000e);
7138 I915_WRITE(EG2, 0x000e0000);
7139 I915_WRITE(EG3, 0x68000300);
7140 I915_WRITE(EG4, 0x42000000);
7141 I915_WRITE(EG5, 0x00140031);
7142 I915_WRITE(EG6, 0);
7143 I915_WRITE(EG7, 0);
7144
7145 for (i = 0; i < 8; i++)
7146 I915_WRITE(PXWL + (i * 4), 0);
7147
7148 /* Enable PMON + select events */
7149 I915_WRITE(ECR, 0x80000019);
7150
7151 lcfuse = I915_READ(LCFUSE02);
7152
7153 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7154}
7155
3b8d8d91 7156void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 7157{
a6044e23
JB		 7158 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7159 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 7160 u32 pcu_mbox, rc6_mask = 0;
a6044e23 7161 int cur_freq, min_freq, max_freq;
8fd26859
CW		 7162 int i;
7163
7164 /* Here begins a magic sequence of register writes to enable
7165 * auto-downclocking.
7166 *
7167 * Perhaps there might be some value in exposing these to
7168 * userspace...
7169 */
7170 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 7171 mutex_lock(&dev_priv->dev->struct_mutex);
fcca7926 7172 gen6_gt_force_wake_get(dev_priv);
8fd26859 7173
3b8d8d91 7174 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 7175 I915_WRITE(GEN6_RC_CONTROL, 0);
7176
7177 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7178 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7179 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7180 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7181 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7182
7183 for (i = 0; i < I915_NUM_RINGS; i++)
7184 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7185
7186 I915_WRITE(GEN6_RC_SLEEP, 0);
7187 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7188 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7189 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7190 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7191
7df8721b
JB		 7192 if (i915_enable_rc6)
7193 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7194 GEN6_RC_CTL_RC6_ENABLE;
7195
8fd26859 7196 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 7197 rc6_mask |
9c3d2f7f 7198 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 7199 GEN6_RC_CTL_HW_ENABLE);
7200
3b8d8d91 7201 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 7202 GEN6_FREQUENCY(10) |
7203 GEN6_OFFSET(0) |
7204 GEN6_AGGRESSIVE_TURBO);
7205 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7206 GEN6_FREQUENCY(12));
7207
7208 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7209 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7210 18 << 24 |
7211 6 << 16);
ccab5c82
JB		 7212 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7213 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 7214 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 7215 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 7216 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7217 I915_WRITE(GEN6_RP_CONTROL,
7218 GEN6_RP_MEDIA_TURBO |
7219 GEN6_RP_USE_NORMAL_FREQ |
7220 GEN6_RP_MEDIA_IS_GFX |
7221 GEN6_RP_ENABLE |
ccab5c82
JB		 7222 GEN6_RP_UP_BUSY_AVG |
7223 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 7224
7225 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7226 500))
7227 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7228
7229 I915_WRITE(GEN6_PCODE_DATA, 0);
7230 I915_WRITE(GEN6_PCODE_MAILBOX,
7231 GEN6_PCODE_READY |
7232 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7233 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7234 500))
7235 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7236
a6044e23
JB		 7237 min_freq = (rp_state_cap & 0xff0000) >> 16;
7238 max_freq = rp_state_cap & 0xff;
7239 cur_freq = (gt_perf_status & 0xff00) >> 8;
7240
7241 /* Check for overclock support */
7242 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7243 500))
7244 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7245 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7246 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7247 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7248 500))
7249 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7250 if (pcu_mbox & (1<<31)) { /* OC supported */
7251 max_freq = pcu_mbox & 0xff;
e281fcaa 7252 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 7253 }
7254
7255 /* In units of 100MHz */
7256 dev_priv->max_delay = max_freq;
7257 dev_priv->min_delay = min_freq;
7258 dev_priv->cur_delay = cur_freq;
7259
8fd26859
CW		 7260 /* requires MSI enabled */
7261 I915_WRITE(GEN6_PMIER,
7262 GEN6_PM_MBOX_EVENT |
7263 GEN6_PM_THERMAL_EVENT |
7264 GEN6_PM_RP_DOWN_TIMEOUT |
7265 GEN6_PM_RP_UP_THRESHOLD |
7266 GEN6_PM_RP_DOWN_THRESHOLD |
7267 GEN6_PM_RP_UP_EI_EXPIRED |
7268 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 7269 spin_lock_irq(&dev_priv->rps_lock);
7270 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 7271 I915_WRITE(GEN6_PMIMR, 0);
4912d041 7272 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 7273 /* enable all PM interrupts */
7274 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 7275
fcca7926 7276 gen6_gt_force_wake_put(dev_priv);
d1ebd816 7277 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 7278}
7279
23b2f8bb
JB		 7280void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7281{
7282 int min_freq = 15;
7283 int gpu_freq, ia_freq, max_ia_freq;
7284 int scaling_factor = 180;
7285
7286 max_ia_freq = cpufreq_quick_get_max(0);
7287 /*
7288 * Default to measured freq if none found, PCU will ensure we don't go
7289 * over
7290 */
7291 if (!max_ia_freq)
7292 max_ia_freq = tsc_khz;
7293
7294 /* Convert from kHz to MHz */
7295 max_ia_freq /= 1000;
7296
7297 mutex_lock(&dev_priv->dev->struct_mutex);
7298
7299 /*
7300 * For each potential GPU frequency, load a ring frequency we'd like
7301 * to use for memory access. We do this by specifying the IA frequency
7302 * the PCU should use as a reference to determine the ring frequency.
7303 */
7304 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7305 gpu_freq--) {
7306 int diff = dev_priv->max_delay - gpu_freq;
7307
7308 /*
7309 * For GPU frequencies less than 750MHz, just use the lowest
7310 * ring freq.
7311 */
7312 if (gpu_freq < min_freq)
7313 ia_freq = 800;
7314 else
7315 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7316 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7317
7318 I915_WRITE(GEN6_PCODE_DATA,
7319 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7320 gpu_freq);
7321 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7322 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7323 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7324 GEN6_PCODE_READY) == 0, 10)) {
7325 DRM_ERROR("pcode write of freq table timed out\n");
7326 continue;
7327 }
7328 }
7329
7330 mutex_unlock(&dev_priv->dev->struct_mutex);
7331}
7332
6067aaea
JB		 7333static void ironlake_init_clock_gating(struct drm_device *dev)
7334{
7335 struct drm_i915_private *dev_priv = dev->dev_private;
7336 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7337
7338 /* Required for FBC */
7339 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7340 DPFCRUNIT_CLOCK_GATE_DISABLE |
7341 DPFDUNIT_CLOCK_GATE_DISABLE;
7342 /* Required for CxSR */
7343 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7344
7345 I915_WRITE(PCH_3DCGDIS0,
7346 MARIUNIT_CLOCK_GATE_DISABLE |
7347 SVSMUNIT_CLOCK_GATE_DISABLE);
7348 I915_WRITE(PCH_3DCGDIS1,
7349 VFMUNIT_CLOCK_GATE_DISABLE);
7350
7351 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7352
6067aaea
JB		 7353 /*
7354 * According to the spec the following bits should be set in
7355 * order to enable memory self-refresh
7356 * The bit 22/21 of 0x42004
7357 * The bit 5 of 0x42020
7358 * The bit 15 of 0x45000
7359 */
7360 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7361 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7362 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7363 I915_WRITE(ILK_DSPCLK_GATE,
7364 (I915_READ(ILK_DSPCLK_GATE) |
7365 ILK_DPARB_CLK_GATE));
7366 I915_WRITE(DISP_ARB_CTL,
7367 (I915_READ(DISP_ARB_CTL) |
7368 DISP_FBC_WM_DIS));
7369 I915_WRITE(WM3_LP_ILK, 0);
7370 I915_WRITE(WM2_LP_ILK, 0);
7371 I915_WRITE(WM1_LP_ILK, 0);
7372
7373 /*
7374 * Based on the document from hardware guys the following bits
7375 * should be set unconditionally in order to enable FBC.
7376 * The bit 22 of 0x42000
7377 * The bit 22 of 0x42004
7378 * The bit 7,8,9 of 0x42020.
7379 */
7380 if (IS_IRONLAKE_M(dev)) {
7381 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7382 I915_READ(ILK_DISPLAY_CHICKEN1) |
7383 ILK_FBCQ_DIS);
7384 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7385 I915_READ(ILK_DISPLAY_CHICKEN2) |
7386 ILK_DPARB_GATE);
7387 I915_WRITE(ILK_DSPCLK_GATE,
7388 I915_READ(ILK_DSPCLK_GATE) |
7389 ILK_DPFC_DIS1 |
7390 ILK_DPFC_DIS2 |
7391 ILK_CLK_FBC);
7392 }
7393
7394 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7395 I915_READ(ILK_DISPLAY_CHICKEN2) |
7396 ILK_ELPIN_409_SELECT);
7397 I915_WRITE(_3D_CHICKEN2,
7398 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7399 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 7400}
7401
6067aaea 7402static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 7403{
7404 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 7405 int pipe;
6067aaea
JB		 7406 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7407
7408 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 7409
6067aaea
JB		 7410 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7411 I915_READ(ILK_DISPLAY_CHICKEN2) |
7412 ILK_ELPIN_409_SELECT);
8956c8bb 7413
6067aaea
JB		 7414 I915_WRITE(WM3_LP_ILK, 0);
7415 I915_WRITE(WM2_LP_ILK, 0);
7416 I915_WRITE(WM1_LP_ILK, 0);
652c393a
JB		 7417
7418 /*
6067aaea
JB		 7419 * According to the spec the following bits should be
7420 * set in order to enable memory self-refresh and fbc:
7421 * The bit21 and bit22 of 0x42000
7422 * The bit21 and bit22 of 0x42004
7423 * The bit5 and bit7 of 0x42020
7424 * The bit14 of 0x70180
7425 * The bit14 of 0x71180
652c393a 7426 */
6067aaea
JB		 7427 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7428 I915_READ(ILK_DISPLAY_CHICKEN1) |
7429 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7430 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7431 I915_READ(ILK_DISPLAY_CHICKEN2) |
7432 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7433 I915_WRITE(ILK_DSPCLK_GATE,
7434 I915_READ(ILK_DSPCLK_GATE) |
7435 ILK_DPARB_CLK_GATE |
7436 ILK_DPFD_CLK_GATE);
8956c8bb 7437
6067aaea
JB		 7438 for_each_pipe(pipe)
7439 I915_WRITE(DSPCNTR(pipe),
7440 I915_READ(DSPCNTR(pipe)) |
7441 DISPPLANE_TRICKLE_FEED_DISABLE);
7442}
8956c8bb 7443
28963a3e
JB		 7444static void ivybridge_init_clock_gating(struct drm_device *dev)
7445{
7446 struct drm_i915_private *dev_priv = dev->dev_private;
7447 int pipe;
7448 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 7449
28963a3e 7450 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 7451
28963a3e
JB		 7452 I915_WRITE(WM3_LP_ILK, 0);
7453 I915_WRITE(WM2_LP_ILK, 0);
7454 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 7455
28963a3e 7456 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 7457
28963a3e
JB		 7458 for_each_pipe(pipe)
7459 I915_WRITE(DSPCNTR(pipe),
7460 I915_READ(DSPCNTR(pipe)) |
7461 DISPPLANE_TRICKLE_FEED_DISABLE);
7462}
7463
6067aaea
JB		 7464static void g4x_init_clock_gating(struct drm_device *dev)
7465{
7466 struct drm_i915_private *dev_priv = dev->dev_private;
7467 uint32_t dspclk_gate;
8fd26859 7468
6067aaea
JB		 7469 I915_WRITE(RENCLK_GATE_D1, 0);
7470 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7471 GS_UNIT_CLOCK_GATE_DISABLE |
7472 CL_UNIT_CLOCK_GATE_DISABLE);
7473 I915_WRITE(RAMCLK_GATE_D, 0);
7474 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7475 OVRUNIT_CLOCK_GATE_DISABLE |
7476 OVCUNIT_CLOCK_GATE_DISABLE;
7477 if (IS_GM45(dev))
7478 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7479 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7480}
1398261a 7481
6067aaea
JB		 7482static void crestline_init_clock_gating(struct drm_device *dev)
7483{
7484 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7485
6067aaea
JB		 7486 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7487 I915_WRITE(RENCLK_GATE_D2, 0);
7488 I915_WRITE(DSPCLK_GATE_D, 0);
7489 I915_WRITE(RAMCLK_GATE_D, 0);
7490 I915_WRITE16(DEUC, 0);
7491}
652c393a 7492
6067aaea
JB		 7493static void broadwater_init_clock_gating(struct drm_device *dev)
7494{
7495 struct drm_i915_private *dev_priv = dev->dev_private;
7496
7497 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7498 I965_RCC_CLOCK_GATE_DISABLE |
7499 I965_RCPB_CLOCK_GATE_DISABLE |
7500 I965_ISC_CLOCK_GATE_DISABLE |
7501 I965_FBC_CLOCK_GATE_DISABLE);
7502 I915_WRITE(RENCLK_GATE_D2, 0);
7503}
7504
7505static void gen3_init_clock_gating(struct drm_device *dev)
7506{
7507 struct drm_i915_private *dev_priv = dev->dev_private;
7508 u32 dstate = I915_READ(D_STATE);
7509
7510 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7511 DSTATE_DOT_CLOCK_GATING;
7512 I915_WRITE(D_STATE, dstate);
7513}
7514
7515static void i85x_init_clock_gating(struct drm_device *dev)
7516{
7517 struct drm_i915_private *dev_priv = dev->dev_private;
7518
7519 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7520}
7521
7522static void i830_init_clock_gating(struct drm_device *dev)
7523{
7524 struct drm_i915_private *dev_priv = dev->dev_private;
7525
7526 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 7527}
7528
645c62a5
JB		 7529static void ibx_init_clock_gating(struct drm_device *dev)
7530{
7531 struct drm_i915_private *dev_priv = dev->dev_private;
7532
7533 /*
7534 * On Ibex Peak and Cougar Point, we need to disable clock
7535 * gating for the panel power sequencer or it will fail to
7536 * start up when no ports are active.
7537 */
7538 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7539}
7540
7541static void cpt_init_clock_gating(struct drm_device *dev)
7542{
7543 struct drm_i915_private *dev_priv = dev->dev_private;
7544
7545 /*
7546 * On Ibex Peak and Cougar Point, we need to disable clock
7547 * gating for the panel power sequencer or it will fail to
7548 * start up when no ports are active.
7549 */
7550 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7551 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7552 DPLS_EDP_PPS_FIX_DIS);
652c393a
JB		 7553}
7554
ac668088 7555static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 7556{
7557 struct drm_i915_private *dev_priv = dev->dev_private;
7558
7559 if (dev_priv->renderctx) {
ac668088
CW		 7560 i915_gem_object_unpin(dev_priv->renderctx);
7561 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 7562 dev_priv->renderctx = NULL;
7563 }
7564
7565 if (dev_priv->pwrctx) {
ac668088
CW		 7566 i915_gem_object_unpin(dev_priv->pwrctx);
7567 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7568 dev_priv->pwrctx = NULL;
7569 }
7570}
7571
7572static void ironlake_disable_rc6(struct drm_device *dev)
7573{
7574 struct drm_i915_private *dev_priv = dev->dev_private;
7575
7576 if (I915_READ(PWRCTXA)) {
7577 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7578 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7579 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7580 50);
0cdab21f
CW		 7581
7582 I915_WRITE(PWRCTXA, 0);
7583 POSTING_READ(PWRCTXA);
7584
ac668088
CW		 7585 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7586 POSTING_READ(RSTDBYCTL);
0cdab21f 7587 }
ac668088 7588
99507307 7589 ironlake_teardown_rc6(dev);
0cdab21f
CW		 7590}
7591
ac668088 7592static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 7593{
7594 struct drm_i915_private *dev_priv = dev->dev_private;
7595
ac668088
CW		 7596 if (dev_priv->renderctx == NULL)
7597 dev_priv->renderctx = intel_alloc_context_page(dev);
7598 if (!dev_priv->renderctx)
7599 return -ENOMEM;
7600
7601 if (dev_priv->pwrctx == NULL)
7602 dev_priv->pwrctx = intel_alloc_context_page(dev);
7603 if (!dev_priv->pwrctx) {
7604 ironlake_teardown_rc6(dev);
7605 return -ENOMEM;
7606 }
7607
7608 return 0;
d5bb081b
JB		 7609}
7610
7611void ironlake_enable_rc6(struct drm_device *dev)
7612{
7613 struct drm_i915_private *dev_priv = dev->dev_private;
7614 int ret;
7615
ac668088
CW		 7616 /* rc6 disabled by default due to repeated reports of hanging during
7617 * boot and resume.
7618 */
7619 if (!i915_enable_rc6)
7620 return;
7621
2c34b850 7622 mutex_lock(&dev->struct_mutex);
ac668088 7623 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 7624 if (ret) {
7625 mutex_unlock(&dev->struct_mutex);
ac668088 7626 return;
2c34b850 7627 }
ac668088 7628
d5bb081b
JB		 7629 /*
7630 * GPU can automatically power down the render unit if given a page
7631 * to save state.
7632 */
7633 ret = BEGIN_LP_RING(6);
7634 if (ret) {
ac668088 7635 ironlake_teardown_rc6(dev);
2c34b850 7636 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7637 return;
7638 }
ac668088 7639
d5bb081b
JB		 7640 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7641 OUT_RING(MI_SET_CONTEXT);
7642 OUT_RING(dev_priv->renderctx->gtt_offset |
7643 MI_MM_SPACE_GTT |
7644 MI_SAVE_EXT_STATE_EN |
7645 MI_RESTORE_EXT_STATE_EN |
7646 MI_RESTORE_INHIBIT);
7647 OUT_RING(MI_SUSPEND_FLUSH);
7648 OUT_RING(MI_NOOP);
7649 OUT_RING(MI_FLUSH);
7650 ADVANCE_LP_RING();
7651
4a246cfc
BW		 7652 /*
7653 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7654 * does an implicit flush, combined with MI_FLUSH above, it should be
7655 * safe to assume that renderctx is valid
7656 */
7657 ret = intel_wait_ring_idle(LP_RING(dev_priv));
7658 if (ret) {
7659 DRM_ERROR("failed to enable ironlake power power savings\n");
7660 ironlake_teardown_rc6(dev);
7661 mutex_unlock(&dev->struct_mutex);
7662 return;
7663 }
7664
d5bb081b
JB		 7665 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7666 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 7667 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7668}
7669
645c62a5
JB		 7670void intel_init_clock_gating(struct drm_device *dev)
7671{
7672 struct drm_i915_private *dev_priv = dev->dev_private;
7673
7674 dev_priv->display.init_clock_gating(dev);
7675
7676 if (dev_priv->display.init_pch_clock_gating)
7677 dev_priv->display.init_pch_clock_gating(dev);
7678}
ac668088 7679
e70236a8
JB		 7680/* Set up chip specific display functions */
7681static void intel_init_display(struct drm_device *dev)
7682{
7683 struct drm_i915_private *dev_priv = dev->dev_private;
7684
7685 /* We always want a DPMS function */
f564048e 7686 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 7687 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e
EA		 7688 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7689 } else {
e70236a8 7690 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e
EA		 7691 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7692 }
e70236a8 7693
ee5382ae 7694 if (I915_HAS_FBC(dev)) {
9c04f015 7695 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 7696 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7697 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7698 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7699 } else if (IS_GM45(dev)) {
74dff282
JB		 7700 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7701 dev_priv->display.enable_fbc = g4x_enable_fbc;
7702 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 7703 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 7704 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7705 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7706 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7707 }
74dff282 7708 /* 855GM needs testing */
e70236a8
JB		 7709 }
7710
7711 /* Returns the core display clock speed */
f2b115e6 7712 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
e70236a8
JB		 7713 dev_priv->display.get_display_clock_speed =
7714 i945_get_display_clock_speed;
7715 else if (IS_I915G(dev))
7716 dev_priv->display.get_display_clock_speed =
7717 i915_get_display_clock_speed;
f2b115e6 7718 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7719 dev_priv->display.get_display_clock_speed =
7720 i9xx_misc_get_display_clock_speed;
7721 else if (IS_I915GM(dev))
7722 dev_priv->display.get_display_clock_speed =
7723 i915gm_get_display_clock_speed;
7724 else if (IS_I865G(dev))
7725 dev_priv->display.get_display_clock_speed =
7726 i865_get_display_clock_speed;
f0f8a9ce 7727 else if (IS_I85X(dev))
e70236a8
JB		 7728 dev_priv->display.get_display_clock_speed =
7729 i855_get_display_clock_speed;
7730 else /* 852, 830 */
7731 dev_priv->display.get_display_clock_speed =
7732 i830_get_display_clock_speed;
7733
7734 /* For FIFO watermark updates */
7f8a8569 7735 if (HAS_PCH_SPLIT(dev)) {
645c62a5
JB		 7736 if (HAS_PCH_IBX(dev))
7737 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
7738 else if (HAS_PCH_CPT(dev))
7739 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
7740
f00a3ddf 7741 if (IS_GEN5(dev)) {
7f8a8569
ZW		 7742 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7743 dev_priv->display.update_wm = ironlake_update_wm;
7744 else {
7745 DRM_DEBUG_KMS("Failed to get proper latency. "
7746 "Disable CxSR\n");
7747 dev_priv->display.update_wm = NULL;
1398261a 7748 }
674cf967 7749 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 7750 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
1398261a
YL		 7751 } else if (IS_GEN6(dev)) {
7752 if (SNB_READ_WM0_LATENCY()) {
7753 dev_priv->display.update_wm = sandybridge_update_wm;
7754 } else {
7755 DRM_DEBUG_KMS("Failed to read display plane latency. "
7756 "Disable CxSR\n");
7757 dev_priv->display.update_wm = NULL;
7f8a8569 7758 }
674cf967 7759 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 7760 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
357555c0
JB		 7761 } else if (IS_IVYBRIDGE(dev)) {
7762 /* FIXME: detect B0+ stepping and use auto training */
7763 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 7764 if (SNB_READ_WM0_LATENCY()) {
7765 dev_priv->display.update_wm = sandybridge_update_wm;
7766 } else {
7767 DRM_DEBUG_KMS("Failed to read display plane latency. "
7768 "Disable CxSR\n");
7769 dev_priv->display.update_wm = NULL;
7770 }
28963a3e 7771 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6067aaea 7772
7f8a8569
ZW		 7773 } else
7774 dev_priv->display.update_wm = NULL;
7775 } else if (IS_PINEVIEW(dev)) {
d4294342 7776 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 7777 dev_priv->is_ddr3,
d4294342
ZY		 7778 dev_priv->fsb_freq,
7779 dev_priv->mem_freq)) {
7780 DRM_INFO("failed to find known CxSR latency "
95534263 7781 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 7782 "disabling CxSR\n",
95534263 7783 (dev_priv->is_ddr3 == 1) ? "3": "2",
d4294342
ZY		 7784 dev_priv->fsb_freq, dev_priv->mem_freq);
7785 /* Disable CxSR and never update its watermark again */
7786 pineview_disable_cxsr(dev);
7787 dev_priv->display.update_wm = NULL;
7788 } else
7789 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 7790 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 7791 } else if (IS_G4X(dev)) {
e70236a8 7792 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 7793 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7794 } else if (IS_GEN4(dev)) {
e70236a8 7795 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 7796 if (IS_CRESTLINE(dev))
7797 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7798 else if (IS_BROADWATER(dev))
7799 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7800 } else if (IS_GEN3(dev)) {
e70236a8
JB		 7801 dev_priv->display.update_wm = i9xx_update_wm;
7802 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 7803 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7804 } else if (IS_I865G(dev)) {
7805 dev_priv->display.update_wm = i830_update_wm;
7806 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7807 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 7808 } else if (IS_I85X(dev)) {
7809 dev_priv->display.update_wm = i9xx_update_wm;
7810 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 7811 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 7812 } else {
8f4695ed 7813 dev_priv->display.update_wm = i830_update_wm;
6067aaea 7814 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 7815 if (IS_845G(dev))
e70236a8
JB		 7816 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7817 else
7818 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 7819 }
8c9f3aaf
JB		 7820
7821 /* Default just returns -ENODEV to indicate unsupported */
7822 dev_priv->display.queue_flip = intel_default_queue_flip;
7823
7824 switch (INTEL_INFO(dev)->gen) {
7825 case 2:
7826 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7827 break;
7828
7829 case 3:
7830 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7831 break;
7832
7833 case 4:
7834 case 5:
7835 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7836 break;
7837
7838 case 6:
7839 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7840 break;
7c9017e5
JB		 7841 case 7:
7842 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7843 break;
8c9f3aaf 7844 }
e70236a8
JB		 7845}
7846
b690e96c
JB		 7847/*
7848 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7849 * resume, or other times. This quirk makes sure that's the case for
7850 * affected systems.
7851 */
7852static void quirk_pipea_force (struct drm_device *dev)
7853{
7854 struct drm_i915_private *dev_priv = dev->dev_private;
7855
7856 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7857 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7858}
7859
7860struct intel_quirk {
7861 int device;
7862 int subsystem_vendor;
7863 int subsystem_device;
7864 void (*hook)(struct drm_device *dev);
7865};
7866
7867struct intel_quirk intel_quirks[] = {
7868 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7869 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7870 /* HP Mini needs pipe A force quirk (LP: #322104) */
7871 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7872
7873 /* Thinkpad R31 needs pipe A force quirk */
7874 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7875 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7876 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7877
7878 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7879 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7880 /* ThinkPad X40 needs pipe A force quirk */
7881
7882 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7883 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7884
7885 /* 855 & before need to leave pipe A & dpll A up */
7886 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7887 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7888};
7889
7890static void intel_init_quirks(struct drm_device *dev)
7891{
7892 struct pci_dev *d = dev->pdev;
7893 int i;
7894
7895 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7896 struct intel_quirk *q = &intel_quirks[i];
7897
7898 if (d->device == q->device &&
7899 (d->subsystem_vendor == q->subsystem_vendor ||
7900 q->subsystem_vendor == PCI_ANY_ID) &&
7901 (d->subsystem_device == q->subsystem_device ||
7902 q->subsystem_device == PCI_ANY_ID))
7903 q->hook(dev);
7904 }
7905}
7906
9cce37f4
JB		 7907/* Disable the VGA plane that we never use */
7908static void i915_disable_vga(struct drm_device *dev)
7909{
7910 struct drm_i915_private *dev_priv = dev->dev_private;
7911 u8 sr1;
7912 u32 vga_reg;
7913
7914 if (HAS_PCH_SPLIT(dev))
7915 vga_reg = CPU_VGACNTRL;
7916 else
7917 vga_reg = VGACNTRL;
7918
7919 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7920 outb(1, VGA_SR_INDEX);
7921 sr1 = inb(VGA_SR_DATA);
7922 outb(sr1 | 1<<5, VGA_SR_DATA);
7923 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7924 udelay(300);
7925
7926 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7927 POSTING_READ(vga_reg);
7928}
7929
79e53945
JB		 7930void intel_modeset_init(struct drm_device *dev)
7931{
652c393a 7932 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 7933 int i;
7934
7935 drm_mode_config_init(dev);
7936
7937 dev->mode_config.min_width = 0;
7938 dev->mode_config.min_height = 0;
7939
7940 dev->mode_config.funcs = (void *)&intel_mode_funcs;
7941
b690e96c
JB		 7942 intel_init_quirks(dev);
7943
e70236a8
JB		 7944 intel_init_display(dev);
7945
a6c45cf0
CW		 7946 if (IS_GEN2(dev)) {
7947 dev->mode_config.max_width = 2048;
7948 dev->mode_config.max_height = 2048;
7949 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 7950 dev->mode_config.max_width = 4096;
7951 dev->mode_config.max_height = 4096;
79e53945 7952 } else {
a6c45cf0
CW		 7953 dev->mode_config.max_width = 8192;
7954 dev->mode_config.max_height = 8192;
79e53945 7955 }
35c3047a 7956 dev->mode_config.fb_base = dev->agp->base;
79e53945 7957
28c97730 7958 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 7959 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 7960
a3524f1b 7961 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945
JB		 7962 intel_crtc_init(dev, i);
7963 }
7964
9cce37f4
JB		 7965 /* Just disable it once at startup */
7966 i915_disable_vga(dev);
79e53945 7967 intel_setup_outputs(dev);
652c393a 7968
645c62a5 7969 intel_init_clock_gating(dev);
9cce37f4 7970
7648fa99 7971 if (IS_IRONLAKE_M(dev)) {
f97108d1 7972 ironlake_enable_drps(dev);
7648fa99
JB		 7973 intel_init_emon(dev);
7974 }
f97108d1 7975
1c70c0ce 7976 if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91 7977 gen6_enable_rps(dev_priv);
23b2f8bb
JB		 7978 gen6_update_ring_freq(dev_priv);
7979 }
3b8d8d91 7980
652c393a
JB		 7981 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7982 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7983 (unsigned long)dev);
2c7111db
CW		 7984}
7985
7986void intel_modeset_gem_init(struct drm_device *dev)
7987{
7988 if (IS_IRONLAKE_M(dev))
7989 ironlake_enable_rc6(dev);
02e792fb
DV		 7990
7991 intel_setup_overlay(dev);
79e53945
JB		 7992}
7993
7994void intel_modeset_cleanup(struct drm_device *dev)
7995{
652c393a
JB		 7996 struct drm_i915_private *dev_priv = dev->dev_private;
7997 struct drm_crtc *crtc;
7998 struct intel_crtc *intel_crtc;
7999
f87ea761 8000 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8001 mutex_lock(&dev->struct_mutex);
8002
723bfd70
JB		 8003 intel_unregister_dsm_handler();
8004
8005
652c393a
JB		 8006 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8007 /* Skip inactive CRTCs */
8008 if (!crtc->fb)
8009 continue;
8010
8011 intel_crtc = to_intel_crtc(crtc);
3dec0095 8012 intel_increase_pllclock(crtc);
652c393a
JB		 8013 }
8014
e70236a8
JB		 8015 if (dev_priv->display.disable_fbc)
8016 dev_priv->display.disable_fbc(dev);
8017
f97108d1
JB		 8018 if (IS_IRONLAKE_M(dev))
8019 ironlake_disable_drps(dev);
1c70c0ce 8020 if (IS_GEN6(dev) || IS_GEN7(dev))
3b8d8d91 8021 gen6_disable_rps(dev);
f97108d1 8022
d5bb081b
JB		 8023 if (IS_IRONLAKE_M(dev))
8024 ironlake_disable_rc6(dev);
0cdab21f 8025
69341a5e
KH		 8026 mutex_unlock(&dev->struct_mutex);
8027
6c0d9350
DV		 8028 /* Disable the irq before mode object teardown, for the irq might
8029 * enqueue unpin/hotplug work. */
8030 drm_irq_uninstall(dev);
8031 cancel_work_sync(&dev_priv->hotplug_work);
8032
3dec0095
DV		 8033 /* Shut off idle work before the crtcs get freed. */
8034 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8035 intel_crtc = to_intel_crtc(crtc);
8036 del_timer_sync(&intel_crtc->idle_timer);
8037 }
8038 del_timer_sync(&dev_priv->idle_timer);
8039 cancel_work_sync(&dev_priv->idle_work);
8040
79e53945
JB		 8041 drm_mode_config_cleanup(dev);
8042}
8043
f1c79df3
ZW		 8044/*
8045 * Return which encoder is currently attached for connector.
8046 */
df0e9248 8047struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8048{
df0e9248
CW		 8049 return &intel_attached_encoder(connector)->base;
8050}
f1c79df3 8051
df0e9248
CW		 8052void intel_connector_attach_encoder(struct intel_connector *connector,
8053 struct intel_encoder *encoder)
8054{
8055 connector->encoder = encoder;
8056 drm_mode_connector_attach_encoder(&connector->base,
8057 &encoder->base);
79e53945 8058}
28d52043
DA		 8059
8060/*
8061 * set vga decode state - true == enable VGA decode
8062 */
8063int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8064{
8065 struct drm_i915_private *dev_priv = dev->dev_private;
8066 u16 gmch_ctrl;
8067
8068 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8069 if (state)
8070 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8071 else
8072 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8073 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8074 return 0;
8075}
c4a1d9e4
CW		 8076
8077#ifdef CONFIG_DEBUG_FS
8078#include <linux/seq_file.h>
8079
8080struct intel_display_error_state {
8081 struct intel_cursor_error_state {
8082 u32 control;
8083 u32 position;
8084 u32 base;
8085 u32 size;
8086 } cursor[2];
8087
8088 struct intel_pipe_error_state {
8089 u32 conf;
8090 u32 source;
8091
8092 u32 htotal;
8093 u32 hblank;
8094 u32 hsync;
8095 u32 vtotal;
8096 u32 vblank;
8097 u32 vsync;
8098 } pipe[2];
8099
8100 struct intel_plane_error_state {
8101 u32 control;
8102 u32 stride;
8103 u32 size;
8104 u32 pos;
8105 u32 addr;
8106 u32 surface;
8107 u32 tile_offset;
8108 } plane[2];
8109};
8110
8111struct intel_display_error_state *
8112intel_display_capture_error_state(struct drm_device *dev)
8113{
8114 drm_i915_private_t *dev_priv = dev->dev_private;
8115 struct intel_display_error_state *error;
8116 int i;
8117
8118 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8119 if (error == NULL)
8120 return NULL;
8121
8122 for (i = 0; i < 2; i++) {
8123 error->cursor[i].control = I915_READ(CURCNTR(i));
8124 error->cursor[i].position = I915_READ(CURPOS(i));
8125 error->cursor[i].base = I915_READ(CURBASE(i));
8126
8127 error->plane[i].control = I915_READ(DSPCNTR(i));
8128 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8129 error->plane[i].size = I915_READ(DSPSIZE(i));
8130 error->plane[i].pos= I915_READ(DSPPOS(i));
8131 error->plane[i].addr = I915_READ(DSPADDR(i));
8132 if (INTEL_INFO(dev)->gen >= 4) {
8133 error->plane[i].surface = I915_READ(DSPSURF(i));
8134 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8135 }
8136
8137 error->pipe[i].conf = I915_READ(PIPECONF(i));
8138 error->pipe[i].source = I915_READ(PIPESRC(i));
8139 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8140 error->pipe[i].hblank = I915_READ(HBLANK(i));
8141 error->pipe[i].hsync = I915_READ(HSYNC(i));
8142 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8143 error->pipe[i].vblank = I915_READ(VBLANK(i));
8144 error->pipe[i].vsync = I915_READ(VSYNC(i));
8145 }
8146
8147 return error;
8148}
8149
8150void
8151intel_display_print_error_state(struct seq_file *m,
8152 struct drm_device *dev,
8153 struct intel_display_error_state *error)
8154{
8155 int i;
8156
8157 for (i = 0; i < 2; i++) {
8158 seq_printf(m, "Pipe [%d]:\n", i);
8159 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8160 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8161 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8162 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8163 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8164 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8165 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8166 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8167
8168 seq_printf(m, "Plane [%d]:\n", i);
8169 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8170 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8171 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8172 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8173 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8174 if (INTEL_INFO(dev)->gen >= 4) {
8175 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8176 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8177 }
8178
8179 seq_printf(m, "Cursor [%d]:\n", i);
8180 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8181 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8182 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8183 }
8184}
8185#endif
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