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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
5d723d7a | 37 | #include "intel_frontbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
db18b6a6 | 40 | #include "intel_dsi.h" |
e5510fac | 41 | #include "i915_trace.h" |
319c1d42 | 42 | #include <drm/drm_atomic.h> |
c196e1d6 | 43 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
44 | #include <drm/drm_dp_helper.h> |
45 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
46 | #include <drm/drm_plane_helper.h> |
47 | #include <drm/drm_rect.h> | |
c0f372b3 | 48 | #include <linux/dma_remapping.h> |
fd8e058a | 49 | #include <linux/reservation.h> |
79e53945 | 50 | |
5a21b665 DV |
51 | static bool is_mmio_work(struct intel_flip_work *work) |
52 | { | |
53 | return work->mmio_work.func; | |
54 | } | |
55 | ||
465c120c | 56 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 57 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
58 | DRM_FORMAT_C8, |
59 | DRM_FORMAT_RGB565, | |
465c120c | 60 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 61 | DRM_FORMAT_XRGB8888, |
465c120c MR |
62 | }; |
63 | ||
64 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 65 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
66 | DRM_FORMAT_C8, |
67 | DRM_FORMAT_RGB565, | |
68 | DRM_FORMAT_XRGB8888, | |
69 | DRM_FORMAT_XBGR8888, | |
70 | DRM_FORMAT_XRGB2101010, | |
71 | DRM_FORMAT_XBGR2101010, | |
72 | }; | |
73 | ||
74 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
75 | DRM_FORMAT_C8, |
76 | DRM_FORMAT_RGB565, | |
77 | DRM_FORMAT_XRGB8888, | |
465c120c | 78 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 79 | DRM_FORMAT_ARGB8888, |
465c120c MR |
80 | DRM_FORMAT_ABGR8888, |
81 | DRM_FORMAT_XRGB2101010, | |
465c120c | 82 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
83 | DRM_FORMAT_YUYV, |
84 | DRM_FORMAT_YVYU, | |
85 | DRM_FORMAT_UYVY, | |
86 | DRM_FORMAT_VYUY, | |
465c120c MR |
87 | }; |
88 | ||
3d7d6510 MR |
89 | /* Cursor formats */ |
90 | static const uint32_t intel_cursor_formats[] = { | |
91 | DRM_FORMAT_ARGB8888, | |
92 | }; | |
93 | ||
f1f644dc | 94 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 95 | struct intel_crtc_state *pipe_config); |
18442d08 | 96 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 97 | struct intel_crtc_state *pipe_config); |
f1f644dc | 98 | |
eb1bfe80 JB |
99 | static int intel_framebuffer_init(struct drm_device *dev, |
100 | struct intel_framebuffer *ifb, | |
101 | struct drm_mode_fb_cmd2 *mode_cmd, | |
102 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
103 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
104 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 105 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 106 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
107 | struct intel_link_m_n *m_n, |
108 | struct intel_link_m_n *m2_n2); | |
29407aab | 109 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 110 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 111 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 112 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 113 | const struct intel_crtc_state *pipe_config); |
d288f65f | 114 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 115 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
116 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
117 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
65edccce VS |
118 | static void skl_init_scalers(struct drm_i915_private *dev_priv, |
119 | struct intel_crtc *crtc, | |
120 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
121 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
122 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
123 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 124 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 125 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
4e5ca60f | 126 | static int ilk_max_pixel_rate(struct drm_atomic_state *state); |
324513c0 | 127 | static int bxt_calc_cdclk(int max_pixclk); |
e7457a9a | 128 | |
d4906093 | 129 | struct intel_limit { |
4c5def93 ACO |
130 | struct { |
131 | int min, max; | |
132 | } dot, vco, n, m, m1, m2, p, p1; | |
133 | ||
134 | struct { | |
135 | int dot_limit; | |
136 | int p2_slow, p2_fast; | |
137 | } p2; | |
d4906093 | 138 | }; |
79e53945 | 139 | |
bfa7df01 VS |
140 | /* returns HPLL frequency in kHz */ |
141 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
142 | { | |
143 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
144 | ||
145 | /* Obtain SKU information */ | |
146 | mutex_lock(&dev_priv->sb_lock); | |
147 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
148 | CCK_FUSE_HPLL_FREQ_MASK; | |
149 | mutex_unlock(&dev_priv->sb_lock); | |
150 | ||
151 | return vco_freq[hpll_freq] * 1000; | |
152 | } | |
153 | ||
c30fec65 VS |
154 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
155 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
156 | { |
157 | u32 val; | |
158 | int divider; | |
159 | ||
bfa7df01 VS |
160 | mutex_lock(&dev_priv->sb_lock); |
161 | val = vlv_cck_read(dev_priv, reg); | |
162 | mutex_unlock(&dev_priv->sb_lock); | |
163 | ||
164 | divider = val & CCK_FREQUENCY_VALUES; | |
165 | ||
166 | WARN((val & CCK_FREQUENCY_STATUS) != | |
167 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
168 | "%s change in progress\n", name); | |
169 | ||
c30fec65 VS |
170 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
171 | } | |
172 | ||
173 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
174 | const char *name, u32 reg) | |
175 | { | |
176 | if (dev_priv->hpll_freq == 0) | |
177 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
178 | ||
179 | return vlv_get_cck_clock(dev_priv, name, reg, | |
180 | dev_priv->hpll_freq); | |
bfa7df01 VS |
181 | } |
182 | ||
e7dc33f3 VS |
183 | static int |
184 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
d2acd215 | 185 | { |
e7dc33f3 VS |
186 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
187 | } | |
d2acd215 | 188 | |
e7dc33f3 VS |
189 | static int |
190 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
191 | { | |
19ab4ed3 | 192 | /* RAWCLK_FREQ_VLV register updated from power well code */ |
35d38d1f VS |
193 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
194 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
d2acd215 DV |
195 | } |
196 | ||
e7dc33f3 VS |
197 | static int |
198 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
79e50a4f | 199 | { |
79e50a4f JN |
200 | uint32_t clkcfg; |
201 | ||
e7dc33f3 | 202 | /* hrawclock is 1/4 the FSB frequency */ |
79e50a4f JN |
203 | clkcfg = I915_READ(CLKCFG); |
204 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
205 | case CLKCFG_FSB_400: | |
e7dc33f3 | 206 | return 100000; |
79e50a4f | 207 | case CLKCFG_FSB_533: |
e7dc33f3 | 208 | return 133333; |
79e50a4f | 209 | case CLKCFG_FSB_667: |
e7dc33f3 | 210 | return 166667; |
79e50a4f | 211 | case CLKCFG_FSB_800: |
e7dc33f3 | 212 | return 200000; |
79e50a4f | 213 | case CLKCFG_FSB_1067: |
e7dc33f3 | 214 | return 266667; |
79e50a4f | 215 | case CLKCFG_FSB_1333: |
e7dc33f3 | 216 | return 333333; |
79e50a4f JN |
217 | /* these two are just a guess; one of them might be right */ |
218 | case CLKCFG_FSB_1600: | |
219 | case CLKCFG_FSB_1600_ALT: | |
e7dc33f3 | 220 | return 400000; |
79e50a4f | 221 | default: |
e7dc33f3 | 222 | return 133333; |
79e50a4f JN |
223 | } |
224 | } | |
225 | ||
19ab4ed3 | 226 | void intel_update_rawclk(struct drm_i915_private *dev_priv) |
e7dc33f3 VS |
227 | { |
228 | if (HAS_PCH_SPLIT(dev_priv)) | |
229 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
230 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
231 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
232 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
233 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
234 | else | |
235 | return; /* no rawclk on other platforms, or no need to know it */ | |
236 | ||
237 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
238 | } | |
239 | ||
bfa7df01 VS |
240 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
241 | { | |
666a4537 | 242 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
243 | return; |
244 | ||
245 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
246 | CCK_CZ_CLOCK_CONTROL); | |
247 | ||
248 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
249 | } | |
250 | ||
021357ac | 251 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
252 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
253 | const struct intel_crtc_state *pipe_config) | |
021357ac | 254 | { |
21a727b3 VS |
255 | if (HAS_DDI(dev_priv)) |
256 | return pipe_config->port_clock; /* SPLL */ | |
257 | else if (IS_GEN5(dev_priv)) | |
258 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 259 | else |
21a727b3 | 260 | return 270000; |
021357ac CW |
261 | } |
262 | ||
1b6f4958 | 263 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 264 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 265 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 266 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
267 | .m = { .min = 96, .max = 140 }, |
268 | .m1 = { .min = 18, .max = 26 }, | |
269 | .m2 = { .min = 6, .max = 16 }, | |
270 | .p = { .min = 4, .max = 128 }, | |
271 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
272 | .p2 = { .dot_limit = 165000, |
273 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
274 | }; |
275 | ||
1b6f4958 | 276 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 277 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 278 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 279 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
280 | .m = { .min = 96, .max = 140 }, |
281 | .m1 = { .min = 18, .max = 26 }, | |
282 | .m2 = { .min = 6, .max = 16 }, | |
283 | .p = { .min = 4, .max = 128 }, | |
284 | .p1 = { .min = 2, .max = 33 }, | |
285 | .p2 = { .dot_limit = 165000, | |
286 | .p2_slow = 4, .p2_fast = 4 }, | |
287 | }; | |
288 | ||
1b6f4958 | 289 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 290 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 291 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 292 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
293 | .m = { .min = 96, .max = 140 }, |
294 | .m1 = { .min = 18, .max = 26 }, | |
295 | .m2 = { .min = 6, .max = 16 }, | |
296 | .p = { .min = 4, .max = 128 }, | |
297 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
298 | .p2 = { .dot_limit = 165000, |
299 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 300 | }; |
273e27ca | 301 | |
1b6f4958 | 302 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
303 | .dot = { .min = 20000, .max = 400000 }, |
304 | .vco = { .min = 1400000, .max = 2800000 }, | |
305 | .n = { .min = 1, .max = 6 }, | |
306 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
307 | .m1 = { .min = 8, .max = 18 }, |
308 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
309 | .p = { .min = 5, .max = 80 }, |
310 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
311 | .p2 = { .dot_limit = 200000, |
312 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
313 | }; |
314 | ||
1b6f4958 | 315 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
316 | .dot = { .min = 20000, .max = 400000 }, |
317 | .vco = { .min = 1400000, .max = 2800000 }, | |
318 | .n = { .min = 1, .max = 6 }, | |
319 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
320 | .m1 = { .min = 8, .max = 18 }, |
321 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
322 | .p = { .min = 7, .max = 98 }, |
323 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
324 | .p2 = { .dot_limit = 112000, |
325 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
326 | }; |
327 | ||
273e27ca | 328 | |
1b6f4958 | 329 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
330 | .dot = { .min = 25000, .max = 270000 }, |
331 | .vco = { .min = 1750000, .max = 3500000}, | |
332 | .n = { .min = 1, .max = 4 }, | |
333 | .m = { .min = 104, .max = 138 }, | |
334 | .m1 = { .min = 17, .max = 23 }, | |
335 | .m2 = { .min = 5, .max = 11 }, | |
336 | .p = { .min = 10, .max = 30 }, | |
337 | .p1 = { .min = 1, .max = 3}, | |
338 | .p2 = { .dot_limit = 270000, | |
339 | .p2_slow = 10, | |
340 | .p2_fast = 10 | |
044c7c41 | 341 | }, |
e4b36699 KP |
342 | }; |
343 | ||
1b6f4958 | 344 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
345 | .dot = { .min = 22000, .max = 400000 }, |
346 | .vco = { .min = 1750000, .max = 3500000}, | |
347 | .n = { .min = 1, .max = 4 }, | |
348 | .m = { .min = 104, .max = 138 }, | |
349 | .m1 = { .min = 16, .max = 23 }, | |
350 | .m2 = { .min = 5, .max = 11 }, | |
351 | .p = { .min = 5, .max = 80 }, | |
352 | .p1 = { .min = 1, .max = 8}, | |
353 | .p2 = { .dot_limit = 165000, | |
354 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
355 | }; |
356 | ||
1b6f4958 | 357 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
358 | .dot = { .min = 20000, .max = 115000 }, |
359 | .vco = { .min = 1750000, .max = 3500000 }, | |
360 | .n = { .min = 1, .max = 3 }, | |
361 | .m = { .min = 104, .max = 138 }, | |
362 | .m1 = { .min = 17, .max = 23 }, | |
363 | .m2 = { .min = 5, .max = 11 }, | |
364 | .p = { .min = 28, .max = 112 }, | |
365 | .p1 = { .min = 2, .max = 8 }, | |
366 | .p2 = { .dot_limit = 0, | |
367 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 368 | }, |
e4b36699 KP |
369 | }; |
370 | ||
1b6f4958 | 371 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
372 | .dot = { .min = 80000, .max = 224000 }, |
373 | .vco = { .min = 1750000, .max = 3500000 }, | |
374 | .n = { .min = 1, .max = 3 }, | |
375 | .m = { .min = 104, .max = 138 }, | |
376 | .m1 = { .min = 17, .max = 23 }, | |
377 | .m2 = { .min = 5, .max = 11 }, | |
378 | .p = { .min = 14, .max = 42 }, | |
379 | .p1 = { .min = 2, .max = 6 }, | |
380 | .p2 = { .dot_limit = 0, | |
381 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 382 | }, |
e4b36699 KP |
383 | }; |
384 | ||
1b6f4958 | 385 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
386 | .dot = { .min = 20000, .max = 400000}, |
387 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 388 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
389 | .n = { .min = 3, .max = 6 }, |
390 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 391 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
392 | .m1 = { .min = 0, .max = 0 }, |
393 | .m2 = { .min = 0, .max = 254 }, | |
394 | .p = { .min = 5, .max = 80 }, | |
395 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
396 | .p2 = { .dot_limit = 200000, |
397 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
398 | }; |
399 | ||
1b6f4958 | 400 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
401 | .dot = { .min = 20000, .max = 400000 }, |
402 | .vco = { .min = 1700000, .max = 3500000 }, | |
403 | .n = { .min = 3, .max = 6 }, | |
404 | .m = { .min = 2, .max = 256 }, | |
405 | .m1 = { .min = 0, .max = 0 }, | |
406 | .m2 = { .min = 0, .max = 254 }, | |
407 | .p = { .min = 7, .max = 112 }, | |
408 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
409 | .p2 = { .dot_limit = 112000, |
410 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
411 | }; |
412 | ||
273e27ca EA |
413 | /* Ironlake / Sandybridge |
414 | * | |
415 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
416 | * the range value for them is (actual_value - 2). | |
417 | */ | |
1b6f4958 | 418 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
419 | .dot = { .min = 25000, .max = 350000 }, |
420 | .vco = { .min = 1760000, .max = 3510000 }, | |
421 | .n = { .min = 1, .max = 5 }, | |
422 | .m = { .min = 79, .max = 127 }, | |
423 | .m1 = { .min = 12, .max = 22 }, | |
424 | .m2 = { .min = 5, .max = 9 }, | |
425 | .p = { .min = 5, .max = 80 }, | |
426 | .p1 = { .min = 1, .max = 8 }, | |
427 | .p2 = { .dot_limit = 225000, | |
428 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
429 | }; |
430 | ||
1b6f4958 | 431 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
432 | .dot = { .min = 25000, .max = 350000 }, |
433 | .vco = { .min = 1760000, .max = 3510000 }, | |
434 | .n = { .min = 1, .max = 3 }, | |
435 | .m = { .min = 79, .max = 118 }, | |
436 | .m1 = { .min = 12, .max = 22 }, | |
437 | .m2 = { .min = 5, .max = 9 }, | |
438 | .p = { .min = 28, .max = 112 }, | |
439 | .p1 = { .min = 2, .max = 8 }, | |
440 | .p2 = { .dot_limit = 225000, | |
441 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
442 | }; |
443 | ||
1b6f4958 | 444 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
445 | .dot = { .min = 25000, .max = 350000 }, |
446 | .vco = { .min = 1760000, .max = 3510000 }, | |
447 | .n = { .min = 1, .max = 3 }, | |
448 | .m = { .min = 79, .max = 127 }, | |
449 | .m1 = { .min = 12, .max = 22 }, | |
450 | .m2 = { .min = 5, .max = 9 }, | |
451 | .p = { .min = 14, .max = 56 }, | |
452 | .p1 = { .min = 2, .max = 8 }, | |
453 | .p2 = { .dot_limit = 225000, | |
454 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
455 | }; |
456 | ||
273e27ca | 457 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 458 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
459 | .dot = { .min = 25000, .max = 350000 }, |
460 | .vco = { .min = 1760000, .max = 3510000 }, | |
461 | .n = { .min = 1, .max = 2 }, | |
462 | .m = { .min = 79, .max = 126 }, | |
463 | .m1 = { .min = 12, .max = 22 }, | |
464 | .m2 = { .min = 5, .max = 9 }, | |
465 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 466 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
467 | .p2 = { .dot_limit = 225000, |
468 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
469 | }; |
470 | ||
1b6f4958 | 471 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
472 | .dot = { .min = 25000, .max = 350000 }, |
473 | .vco = { .min = 1760000, .max = 3510000 }, | |
474 | .n = { .min = 1, .max = 3 }, | |
475 | .m = { .min = 79, .max = 126 }, | |
476 | .m1 = { .min = 12, .max = 22 }, | |
477 | .m2 = { .min = 5, .max = 9 }, | |
478 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 479 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
480 | .p2 = { .dot_limit = 225000, |
481 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
482 | }; |
483 | ||
1b6f4958 | 484 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
485 | /* |
486 | * These are the data rate limits (measured in fast clocks) | |
487 | * since those are the strictest limits we have. The fast | |
488 | * clock and actual rate limits are more relaxed, so checking | |
489 | * them would make no difference. | |
490 | */ | |
491 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 492 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 493 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
494 | .m1 = { .min = 2, .max = 3 }, |
495 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 496 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 497 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
498 | }; |
499 | ||
1b6f4958 | 500 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
501 | /* |
502 | * These are the data rate limits (measured in fast clocks) | |
503 | * since those are the strictest limits we have. The fast | |
504 | * clock and actual rate limits are more relaxed, so checking | |
505 | * them would make no difference. | |
506 | */ | |
507 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 508 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
509 | .n = { .min = 1, .max = 1 }, |
510 | .m1 = { .min = 2, .max = 2 }, | |
511 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
512 | .p1 = { .min = 2, .max = 4 }, | |
513 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
514 | }; | |
515 | ||
1b6f4958 | 516 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
517 | /* FIXME: find real dot limits */ |
518 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 519 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
520 | .n = { .min = 1, .max = 1 }, |
521 | .m1 = { .min = 2, .max = 2 }, | |
522 | /* FIXME: find real m2 limits */ | |
523 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
524 | .p1 = { .min = 2, .max = 4 }, | |
525 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
526 | }; | |
527 | ||
cdba954e ACO |
528 | static bool |
529 | needs_modeset(struct drm_crtc_state *state) | |
530 | { | |
fc596660 | 531 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
532 | } |
533 | ||
dccbea3b ID |
534 | /* |
535 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
536 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
537 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
538 | * The helpers' return value is the rate of the clock that is fed to the | |
539 | * display engine's pipe which can be the above fast dot clock rate or a | |
540 | * divided-down version of it. | |
541 | */ | |
f2b115e6 | 542 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 543 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 544 | { |
2177832f SL |
545 | clock->m = clock->m2 + 2; |
546 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 547 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 548 | return 0; |
fb03ac01 VS |
549 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
550 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
551 | |
552 | return clock->dot; | |
2177832f SL |
553 | } |
554 | ||
7429e9d4 DV |
555 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
556 | { | |
557 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
558 | } | |
559 | ||
9e2c8475 | 560 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 561 | { |
7429e9d4 | 562 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 563 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 564 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 565 | return 0; |
fb03ac01 VS |
566 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
567 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
568 | |
569 | return clock->dot; | |
79e53945 JB |
570 | } |
571 | ||
9e2c8475 | 572 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
573 | { |
574 | clock->m = clock->m1 * clock->m2; | |
575 | clock->p = clock->p1 * clock->p2; | |
576 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 577 | return 0; |
589eca67 ID |
578 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
579 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
580 | |
581 | return clock->dot / 5; | |
589eca67 ID |
582 | } |
583 | ||
9e2c8475 | 584 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
585 | { |
586 | clock->m = clock->m1 * clock->m2; | |
587 | clock->p = clock->p1 * clock->p2; | |
588 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 589 | return 0; |
ef9348c8 CML |
590 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
591 | clock->n << 22); | |
592 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
593 | |
594 | return clock->dot / 5; | |
ef9348c8 CML |
595 | } |
596 | ||
7c04d1d9 | 597 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
598 | /** |
599 | * Returns whether the given set of divisors are valid for a given refclk with | |
600 | * the given connectors. | |
601 | */ | |
602 | ||
e2d214ae | 603 | static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv, |
1b6f4958 | 604 | const struct intel_limit *limit, |
9e2c8475 | 605 | const struct dpll *clock) |
79e53945 | 606 | { |
f01b7962 VS |
607 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
608 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 609 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 610 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 611 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 612 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 613 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 614 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 615 | |
e2d214ae TU |
616 | if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && |
617 | !IS_CHERRYVIEW(dev_priv) && !IS_BROXTON(dev_priv)) | |
f01b7962 VS |
618 | if (clock->m1 <= clock->m2) |
619 | INTELPllInvalid("m1 <= m2\n"); | |
620 | ||
e2d214ae TU |
621 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
622 | !IS_BROXTON(dev_priv)) { | |
f01b7962 VS |
623 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
624 | INTELPllInvalid("p out of range\n"); | |
625 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
626 | INTELPllInvalid("m out of range\n"); | |
627 | } | |
628 | ||
79e53945 | 629 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 630 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
631 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
632 | * connector, etc., rather than just a single range. | |
633 | */ | |
634 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 635 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
636 | |
637 | return true; | |
638 | } | |
639 | ||
3b1429d9 | 640 | static int |
1b6f4958 | 641 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
642 | const struct intel_crtc_state *crtc_state, |
643 | int target) | |
79e53945 | 644 | { |
3b1429d9 | 645 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 646 | |
2d84d2b3 | 647 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 648 | /* |
a210b028 DV |
649 | * For LVDS just rely on its current settings for dual-channel. |
650 | * We haven't figured out how to reliably set up different | |
651 | * single/dual channel state, if we even can. | |
79e53945 | 652 | */ |
1974cad0 | 653 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 654 | return limit->p2.p2_fast; |
79e53945 | 655 | else |
3b1429d9 | 656 | return limit->p2.p2_slow; |
79e53945 JB |
657 | } else { |
658 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 659 | return limit->p2.p2_slow; |
79e53945 | 660 | else |
3b1429d9 | 661 | return limit->p2.p2_fast; |
79e53945 | 662 | } |
3b1429d9 VS |
663 | } |
664 | ||
70e8aa21 ACO |
665 | /* |
666 | * Returns a set of divisors for the desired target clock with the given | |
667 | * refclk, or FALSE. The returned values represent the clock equation: | |
668 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
669 | * | |
670 | * Target and reference clocks are specified in kHz. | |
671 | * | |
672 | * If match_clock is provided, then best_clock P divider must match the P | |
673 | * divider from @match_clock used for LVDS downclocking. | |
674 | */ | |
3b1429d9 | 675 | static bool |
1b6f4958 | 676 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 677 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
678 | int target, int refclk, struct dpll *match_clock, |
679 | struct dpll *best_clock) | |
3b1429d9 VS |
680 | { |
681 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 682 | struct dpll clock; |
3b1429d9 | 683 | int err = target; |
79e53945 | 684 | |
0206e353 | 685 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 686 | |
3b1429d9 VS |
687 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
688 | ||
42158660 ZY |
689 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
690 | clock.m1++) { | |
691 | for (clock.m2 = limit->m2.min; | |
692 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 693 | if (clock.m2 >= clock.m1) |
42158660 ZY |
694 | break; |
695 | for (clock.n = limit->n.min; | |
696 | clock.n <= limit->n.max; clock.n++) { | |
697 | for (clock.p1 = limit->p1.min; | |
698 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
699 | int this_err; |
700 | ||
dccbea3b | 701 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
702 | if (!intel_PLL_is_valid(to_i915(dev), |
703 | limit, | |
ac58c3f0 DV |
704 | &clock)) |
705 | continue; | |
706 | if (match_clock && | |
707 | clock.p != match_clock->p) | |
708 | continue; | |
709 | ||
710 | this_err = abs(clock.dot - target); | |
711 | if (this_err < err) { | |
712 | *best_clock = clock; | |
713 | err = this_err; | |
714 | } | |
715 | } | |
716 | } | |
717 | } | |
718 | } | |
719 | ||
720 | return (err != target); | |
721 | } | |
722 | ||
70e8aa21 ACO |
723 | /* |
724 | * Returns a set of divisors for the desired target clock with the given | |
725 | * refclk, or FALSE. The returned values represent the clock equation: | |
726 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
727 | * | |
728 | * Target and reference clocks are specified in kHz. | |
729 | * | |
730 | * If match_clock is provided, then best_clock P divider must match the P | |
731 | * divider from @match_clock used for LVDS downclocking. | |
732 | */ | |
ac58c3f0 | 733 | static bool |
1b6f4958 | 734 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 735 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
736 | int target, int refclk, struct dpll *match_clock, |
737 | struct dpll *best_clock) | |
79e53945 | 738 | { |
3b1429d9 | 739 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 740 | struct dpll clock; |
79e53945 JB |
741 | int err = target; |
742 | ||
0206e353 | 743 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 744 | |
3b1429d9 VS |
745 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
746 | ||
42158660 ZY |
747 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
748 | clock.m1++) { | |
749 | for (clock.m2 = limit->m2.min; | |
750 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
751 | for (clock.n = limit->n.min; |
752 | clock.n <= limit->n.max; clock.n++) { | |
753 | for (clock.p1 = limit->p1.min; | |
754 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
755 | int this_err; |
756 | ||
dccbea3b | 757 | pnv_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
758 | if (!intel_PLL_is_valid(to_i915(dev), |
759 | limit, | |
1b894b59 | 760 | &clock)) |
79e53945 | 761 | continue; |
cec2f356 SP |
762 | if (match_clock && |
763 | clock.p != match_clock->p) | |
764 | continue; | |
79e53945 JB |
765 | |
766 | this_err = abs(clock.dot - target); | |
767 | if (this_err < err) { | |
768 | *best_clock = clock; | |
769 | err = this_err; | |
770 | } | |
771 | } | |
772 | } | |
773 | } | |
774 | } | |
775 | ||
776 | return (err != target); | |
777 | } | |
778 | ||
997c030c ACO |
779 | /* |
780 | * Returns a set of divisors for the desired target clock with the given | |
781 | * refclk, or FALSE. The returned values represent the clock equation: | |
782 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
783 | * |
784 | * Target and reference clocks are specified in kHz. | |
785 | * | |
786 | * If match_clock is provided, then best_clock P divider must match the P | |
787 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 788 | */ |
d4906093 | 789 | static bool |
1b6f4958 | 790 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 791 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
792 | int target, int refclk, struct dpll *match_clock, |
793 | struct dpll *best_clock) | |
d4906093 | 794 | { |
3b1429d9 | 795 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 796 | struct dpll clock; |
d4906093 | 797 | int max_n; |
3b1429d9 | 798 | bool found = false; |
6ba770dc AJ |
799 | /* approximately equals target * 0.00585 */ |
800 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
801 | |
802 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
803 | |
804 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
805 | ||
d4906093 | 806 | max_n = limit->n.max; |
f77f13e2 | 807 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 808 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 809 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
810 | for (clock.m1 = limit->m1.max; |
811 | clock.m1 >= limit->m1.min; clock.m1--) { | |
812 | for (clock.m2 = limit->m2.max; | |
813 | clock.m2 >= limit->m2.min; clock.m2--) { | |
814 | for (clock.p1 = limit->p1.max; | |
815 | clock.p1 >= limit->p1.min; clock.p1--) { | |
816 | int this_err; | |
817 | ||
dccbea3b | 818 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
819 | if (!intel_PLL_is_valid(to_i915(dev), |
820 | limit, | |
1b894b59 | 821 | &clock)) |
d4906093 | 822 | continue; |
1b894b59 CW |
823 | |
824 | this_err = abs(clock.dot - target); | |
d4906093 ML |
825 | if (this_err < err_most) { |
826 | *best_clock = clock; | |
827 | err_most = this_err; | |
828 | max_n = clock.n; | |
829 | found = true; | |
830 | } | |
831 | } | |
832 | } | |
833 | } | |
834 | } | |
2c07245f ZW |
835 | return found; |
836 | } | |
837 | ||
d5dd62bd ID |
838 | /* |
839 | * Check if the calculated PLL configuration is more optimal compared to the | |
840 | * best configuration and error found so far. Return the calculated error. | |
841 | */ | |
842 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
843 | const struct dpll *calculated_clock, |
844 | const struct dpll *best_clock, | |
d5dd62bd ID |
845 | unsigned int best_error_ppm, |
846 | unsigned int *error_ppm) | |
847 | { | |
9ca3ba01 ID |
848 | /* |
849 | * For CHV ignore the error and consider only the P value. | |
850 | * Prefer a bigger P value based on HW requirements. | |
851 | */ | |
920a14b2 | 852 | if (IS_CHERRYVIEW(to_i915(dev))) { |
9ca3ba01 ID |
853 | *error_ppm = 0; |
854 | ||
855 | return calculated_clock->p > best_clock->p; | |
856 | } | |
857 | ||
24be4e46 ID |
858 | if (WARN_ON_ONCE(!target_freq)) |
859 | return false; | |
860 | ||
d5dd62bd ID |
861 | *error_ppm = div_u64(1000000ULL * |
862 | abs(target_freq - calculated_clock->dot), | |
863 | target_freq); | |
864 | /* | |
865 | * Prefer a better P value over a better (smaller) error if the error | |
866 | * is small. Ensure this preference for future configurations too by | |
867 | * setting the error to 0. | |
868 | */ | |
869 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
870 | *error_ppm = 0; | |
871 | ||
872 | return true; | |
873 | } | |
874 | ||
875 | return *error_ppm + 10 < best_error_ppm; | |
876 | } | |
877 | ||
65b3d6a9 ACO |
878 | /* |
879 | * Returns a set of divisors for the desired target clock with the given | |
880 | * refclk, or FALSE. The returned values represent the clock equation: | |
881 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
882 | */ | |
a0c4da24 | 883 | static bool |
1b6f4958 | 884 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 885 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
886 | int target, int refclk, struct dpll *match_clock, |
887 | struct dpll *best_clock) | |
a0c4da24 | 888 | { |
a93e255f | 889 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 890 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 891 | struct dpll clock; |
69e4f900 | 892 | unsigned int bestppm = 1000000; |
27e639bf VS |
893 | /* min update 19.2 MHz */ |
894 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 895 | bool found = false; |
a0c4da24 | 896 | |
6b4bf1c4 VS |
897 | target *= 5; /* fast clock */ |
898 | ||
899 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
900 | |
901 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 902 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 903 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 904 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 905 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 906 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 907 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 908 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 909 | unsigned int ppm; |
69e4f900 | 910 | |
6b4bf1c4 VS |
911 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
912 | refclk * clock.m1); | |
913 | ||
dccbea3b | 914 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 915 | |
e2d214ae TU |
916 | if (!intel_PLL_is_valid(to_i915(dev), |
917 | limit, | |
f01b7962 | 918 | &clock)) |
43b0ac53 VS |
919 | continue; |
920 | ||
d5dd62bd ID |
921 | if (!vlv_PLL_is_optimal(dev, target, |
922 | &clock, | |
923 | best_clock, | |
924 | bestppm, &ppm)) | |
925 | continue; | |
6b4bf1c4 | 926 | |
d5dd62bd ID |
927 | *best_clock = clock; |
928 | bestppm = ppm; | |
929 | found = true; | |
a0c4da24 JB |
930 | } |
931 | } | |
932 | } | |
933 | } | |
a0c4da24 | 934 | |
49e497ef | 935 | return found; |
a0c4da24 | 936 | } |
a4fc5ed6 | 937 | |
65b3d6a9 ACO |
938 | /* |
939 | * Returns a set of divisors for the desired target clock with the given | |
940 | * refclk, or FALSE. The returned values represent the clock equation: | |
941 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
942 | */ | |
ef9348c8 | 943 | static bool |
1b6f4958 | 944 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 945 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
946 | int target, int refclk, struct dpll *match_clock, |
947 | struct dpll *best_clock) | |
ef9348c8 | 948 | { |
a93e255f | 949 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 950 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 951 | unsigned int best_error_ppm; |
9e2c8475 | 952 | struct dpll clock; |
ef9348c8 CML |
953 | uint64_t m2; |
954 | int found = false; | |
955 | ||
956 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 957 | best_error_ppm = 1000000; |
ef9348c8 CML |
958 | |
959 | /* | |
960 | * Based on hardware doc, the n always set to 1, and m1 always | |
961 | * set to 2. If requires to support 200Mhz refclk, we need to | |
962 | * revisit this because n may not 1 anymore. | |
963 | */ | |
964 | clock.n = 1, clock.m1 = 2; | |
965 | target *= 5; /* fast clock */ | |
966 | ||
967 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
968 | for (clock.p2 = limit->p2.p2_fast; | |
969 | clock.p2 >= limit->p2.p2_slow; | |
970 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 971 | unsigned int error_ppm; |
ef9348c8 CML |
972 | |
973 | clock.p = clock.p1 * clock.p2; | |
974 | ||
975 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
976 | clock.n) << 22, refclk * clock.m1); | |
977 | ||
978 | if (m2 > INT_MAX/clock.m1) | |
979 | continue; | |
980 | ||
981 | clock.m2 = m2; | |
982 | ||
dccbea3b | 983 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 | 984 | |
e2d214ae | 985 | if (!intel_PLL_is_valid(to_i915(dev), limit, &clock)) |
ef9348c8 CML |
986 | continue; |
987 | ||
9ca3ba01 ID |
988 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
989 | best_error_ppm, &error_ppm)) | |
990 | continue; | |
991 | ||
992 | *best_clock = clock; | |
993 | best_error_ppm = error_ppm; | |
994 | found = true; | |
ef9348c8 CML |
995 | } |
996 | } | |
997 | ||
998 | return found; | |
999 | } | |
1000 | ||
5ab7b0b7 | 1001 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 1002 | struct dpll *best_clock) |
5ab7b0b7 | 1003 | { |
65b3d6a9 | 1004 | int refclk = 100000; |
1b6f4958 | 1005 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 1006 | |
65b3d6a9 | 1007 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
1008 | target_clock, refclk, NULL, best_clock); |
1009 | } | |
1010 | ||
525b9311 | 1011 | bool intel_crtc_active(struct intel_crtc *crtc) |
20ddf665 | 1012 | { |
20ddf665 VS |
1013 | /* Be paranoid as we can arrive here with only partial |
1014 | * state retrieved from the hardware during setup. | |
1015 | * | |
241bfc38 | 1016 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1017 | * as Haswell has gained clock readout/fastboot support. |
1018 | * | |
66e514c1 | 1019 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1020 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1021 | * |
1022 | * FIXME: The intel_crtc->active here should be switched to | |
1023 | * crtc->state->active once we have proper CRTC states wired up | |
1024 | * for atomic. | |
20ddf665 | 1025 | */ |
525b9311 VS |
1026 | return crtc->active && crtc->base.primary->state->fb && |
1027 | crtc->config->base.adjusted_mode.crtc_clock; | |
20ddf665 VS |
1028 | } |
1029 | ||
a5c961d1 PZ |
1030 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1031 | enum pipe pipe) | |
1032 | { | |
98187836 | 1033 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a5c961d1 | 1034 | |
e2af48c6 | 1035 | return crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1036 | } |
1037 | ||
fbf49ea2 VS |
1038 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1039 | { | |
fac5e23e | 1040 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1041 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1042 | u32 line1, line2; |
1043 | u32 line_mask; | |
1044 | ||
5db94019 | 1045 | if (IS_GEN2(dev_priv)) |
fbf49ea2 VS |
1046 | line_mask = DSL_LINEMASK_GEN2; |
1047 | else | |
1048 | line_mask = DSL_LINEMASK_GEN3; | |
1049 | ||
1050 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1051 | msleep(5); |
fbf49ea2 VS |
1052 | line2 = I915_READ(reg) & line_mask; |
1053 | ||
1054 | return line1 == line2; | |
1055 | } | |
1056 | ||
ab7ad7f6 KP |
1057 | /* |
1058 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1059 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1060 | * |
1061 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1062 | * spinning on the vblank interrupt status bit, since we won't actually | |
1063 | * see an interrupt when the pipe is disabled. | |
1064 | * | |
ab7ad7f6 KP |
1065 | * On Gen4 and above: |
1066 | * wait for the pipe register state bit to turn off | |
1067 | * | |
1068 | * Otherwise: | |
1069 | * wait for the display line value to settle (it usually | |
1070 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1071 | * |
9d0498a2 | 1072 | */ |
575f7ab7 | 1073 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1074 | { |
575f7ab7 | 1075 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1076 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 1077 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1078 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1079 | |
1080 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1081 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1082 | |
1083 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1084 | if (intel_wait_for_register(dev_priv, |
1085 | reg, I965_PIPECONF_ACTIVE, 0, | |
1086 | 100)) | |
284637d9 | 1087 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1088 | } else { |
ab7ad7f6 | 1089 | /* Wait for the display line to settle */ |
fbf49ea2 | 1090 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1091 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1092 | } |
79e53945 JB |
1093 | } |
1094 | ||
b24e7179 | 1095 | /* Only for pre-ILK configs */ |
55607e8a DV |
1096 | void assert_pll(struct drm_i915_private *dev_priv, |
1097 | enum pipe pipe, bool state) | |
b24e7179 | 1098 | { |
b24e7179 JB |
1099 | u32 val; |
1100 | bool cur_state; | |
1101 | ||
649636ef | 1102 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1103 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1104 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1105 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1106 | onoff(state), onoff(cur_state)); |
b24e7179 | 1107 | } |
b24e7179 | 1108 | |
23538ef1 | 1109 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1110 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1111 | { |
1112 | u32 val; | |
1113 | bool cur_state; | |
1114 | ||
a580516d | 1115 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1116 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1117 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1118 | |
1119 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1120 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1121 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1122 | onoff(state), onoff(cur_state)); |
23538ef1 | 1123 | } |
23538ef1 | 1124 | |
040484af JB |
1125 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1126 | enum pipe pipe, bool state) | |
1127 | { | |
040484af | 1128 | bool cur_state; |
ad80a810 PZ |
1129 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1130 | pipe); | |
040484af | 1131 | |
2d1fe073 | 1132 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1133 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1134 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1135 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1136 | } else { |
649636ef | 1137 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1138 | cur_state = !!(val & FDI_TX_ENABLE); |
1139 | } | |
e2c719b7 | 1140 | I915_STATE_WARN(cur_state != state, |
040484af | 1141 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1142 | onoff(state), onoff(cur_state)); |
040484af JB |
1143 | } |
1144 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1145 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1146 | ||
1147 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1148 | enum pipe pipe, bool state) | |
1149 | { | |
040484af JB |
1150 | u32 val; |
1151 | bool cur_state; | |
1152 | ||
649636ef | 1153 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1154 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1155 | I915_STATE_WARN(cur_state != state, |
040484af | 1156 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1157 | onoff(state), onoff(cur_state)); |
040484af JB |
1158 | } |
1159 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1160 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1161 | ||
1162 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1163 | enum pipe pipe) | |
1164 | { | |
040484af JB |
1165 | u32 val; |
1166 | ||
1167 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1168 | if (IS_GEN5(dev_priv)) |
040484af JB |
1169 | return; |
1170 | ||
bf507ef7 | 1171 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1172 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1173 | return; |
1174 | ||
649636ef | 1175 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1176 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1177 | } |
1178 | ||
55607e8a DV |
1179 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1180 | enum pipe pipe, bool state) | |
040484af | 1181 | { |
040484af | 1182 | u32 val; |
55607e8a | 1183 | bool cur_state; |
040484af | 1184 | |
649636ef | 1185 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1186 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1187 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1188 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1189 | onoff(state), onoff(cur_state)); |
040484af JB |
1190 | } |
1191 | ||
4f8036a2 | 1192 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) |
ea0760cf | 1193 | { |
f0f59a00 | 1194 | i915_reg_t pp_reg; |
ea0760cf JB |
1195 | u32 val; |
1196 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1197 | bool locked = true; |
ea0760cf | 1198 | |
4f8036a2 | 1199 | if (WARN_ON(HAS_DDI(dev_priv))) |
bedd4dba JN |
1200 | return; |
1201 | ||
4f8036a2 | 1202 | if (HAS_PCH_SPLIT(dev_priv)) { |
bedd4dba JN |
1203 | u32 port_sel; |
1204 | ||
44cb734c ID |
1205 | pp_reg = PP_CONTROL(0); |
1206 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; | |
bedd4dba JN |
1207 | |
1208 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1209 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1210 | panel_pipe = PIPE_B; | |
1211 | /* XXX: else fix for eDP */ | |
4f8036a2 | 1212 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bedd4dba | 1213 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1214 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1215 | panel_pipe = pipe; |
ea0760cf | 1216 | } else { |
44cb734c | 1217 | pp_reg = PP_CONTROL(0); |
bedd4dba JN |
1218 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1219 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1220 | } |
1221 | ||
1222 | val = I915_READ(pp_reg); | |
1223 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1224 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1225 | locked = false; |
1226 | ||
e2c719b7 | 1227 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1228 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1229 | pipe_name(pipe)); |
ea0760cf JB |
1230 | } |
1231 | ||
93ce0ba6 JN |
1232 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1233 | enum pipe pipe, bool state) | |
1234 | { | |
93ce0ba6 JN |
1235 | bool cur_state; |
1236 | ||
50a0bc90 | 1237 | if (IS_845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 1238 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1239 | else |
5efb3e28 | 1240 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1241 | |
e2c719b7 | 1242 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1243 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1244 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1245 | } |
1246 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1247 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1248 | ||
b840d907 JB |
1249 | void assert_pipe(struct drm_i915_private *dev_priv, |
1250 | enum pipe pipe, bool state) | |
b24e7179 | 1251 | { |
63d7bbe9 | 1252 | bool cur_state; |
702e7a56 PZ |
1253 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1254 | pipe); | |
4feed0eb | 1255 | enum intel_display_power_domain power_domain; |
b24e7179 | 1256 | |
b6b5d049 VS |
1257 | /* if we need the pipe quirk it must be always on */ |
1258 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1259 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1260 | state = true; |
1261 | ||
4feed0eb ID |
1262 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1263 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1264 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1265 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1266 | |
1267 | intel_display_power_put(dev_priv, power_domain); | |
1268 | } else { | |
1269 | cur_state = false; | |
69310161 PZ |
1270 | } |
1271 | ||
e2c719b7 | 1272 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1273 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1274 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1275 | } |
1276 | ||
931872fc CW |
1277 | static void assert_plane(struct drm_i915_private *dev_priv, |
1278 | enum plane plane, bool state) | |
b24e7179 | 1279 | { |
b24e7179 | 1280 | u32 val; |
931872fc | 1281 | bool cur_state; |
b24e7179 | 1282 | |
649636ef | 1283 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1284 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1285 | I915_STATE_WARN(cur_state != state, |
931872fc | 1286 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1287 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1288 | } |
1289 | ||
931872fc CW |
1290 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1291 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1292 | ||
b24e7179 JB |
1293 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1294 | enum pipe pipe) | |
1295 | { | |
91c8a326 | 1296 | struct drm_device *dev = &dev_priv->drm; |
649636ef | 1297 | int i; |
b24e7179 | 1298 | |
653e1026 VS |
1299 | /* Primary planes are fixed to pipes on gen4+ */ |
1300 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1301 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1302 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1303 | "plane %c assertion failure, should be disabled but not\n", |
1304 | plane_name(pipe)); | |
19ec1358 | 1305 | return; |
28c05794 | 1306 | } |
19ec1358 | 1307 | |
b24e7179 | 1308 | /* Need to check both planes against the pipe */ |
055e393f | 1309 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1310 | u32 val = I915_READ(DSPCNTR(i)); |
1311 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1312 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1313 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1314 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1315 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1316 | } |
1317 | } | |
1318 | ||
19332d7a JB |
1319 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1320 | enum pipe pipe) | |
1321 | { | |
91c8a326 | 1322 | struct drm_device *dev = &dev_priv->drm; |
649636ef | 1323 | int sprite; |
19332d7a | 1324 | |
7feb8b88 | 1325 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1326 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1327 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1328 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1329 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1330 | sprite, pipe_name(pipe)); | |
1331 | } | |
920a14b2 | 1332 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3bdcfc0c | 1333 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1334 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1335 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1336 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1337 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1338 | } |
1339 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1340 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1341 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1342 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1343 | plane_name(pipe), pipe_name(pipe)); |
1344 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1345 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1346 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1347 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1348 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1349 | } |
1350 | } | |
1351 | ||
08c71e5e VS |
1352 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1353 | { | |
e2c719b7 | 1354 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1355 | drm_crtc_vblank_put(crtc); |
1356 | } | |
1357 | ||
7abd4b35 ACO |
1358 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1359 | enum pipe pipe) | |
92f2584a | 1360 | { |
92f2584a JB |
1361 | u32 val; |
1362 | bool enabled; | |
1363 | ||
649636ef | 1364 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1365 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1366 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1367 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1368 | pipe_name(pipe)); | |
92f2584a JB |
1369 | } |
1370 | ||
4e634389 KP |
1371 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1372 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1373 | { |
1374 | if ((val & DP_PORT_EN) == 0) | |
1375 | return false; | |
1376 | ||
2d1fe073 | 1377 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1378 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1379 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1380 | return false; | |
2d1fe073 | 1381 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1382 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1383 | return false; | |
f0575e92 KP |
1384 | } else { |
1385 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1386 | return false; | |
1387 | } | |
1388 | return true; | |
1389 | } | |
1390 | ||
1519b995 KP |
1391 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1392 | enum pipe pipe, u32 val) | |
1393 | { | |
dc0fa718 | 1394 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1395 | return false; |
1396 | ||
2d1fe073 | 1397 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1398 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1399 | return false; |
2d1fe073 | 1400 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1401 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1402 | return false; | |
1519b995 | 1403 | } else { |
dc0fa718 | 1404 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1405 | return false; |
1406 | } | |
1407 | return true; | |
1408 | } | |
1409 | ||
1410 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1411 | enum pipe pipe, u32 val) | |
1412 | { | |
1413 | if ((val & LVDS_PORT_EN) == 0) | |
1414 | return false; | |
1415 | ||
2d1fe073 | 1416 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1417 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1418 | return false; | |
1419 | } else { | |
1420 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1421 | return false; | |
1422 | } | |
1423 | return true; | |
1424 | } | |
1425 | ||
1426 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1427 | enum pipe pipe, u32 val) | |
1428 | { | |
1429 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1430 | return false; | |
2d1fe073 | 1431 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1432 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1433 | return false; | |
1434 | } else { | |
1435 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1436 | return false; | |
1437 | } | |
1438 | return true; | |
1439 | } | |
1440 | ||
291906f1 | 1441 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1442 | enum pipe pipe, i915_reg_t reg, |
1443 | u32 port_sel) | |
291906f1 | 1444 | { |
47a05eca | 1445 | u32 val = I915_READ(reg); |
e2c719b7 | 1446 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1447 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1448 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1449 | |
2d1fe073 | 1450 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1451 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1452 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1453 | } |
1454 | ||
1455 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1456 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1457 | { |
47a05eca | 1458 | u32 val = I915_READ(reg); |
e2c719b7 | 1459 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1460 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1461 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1462 | |
2d1fe073 | 1463 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1464 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1465 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1466 | } |
1467 | ||
1468 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1469 | enum pipe pipe) | |
1470 | { | |
291906f1 | 1471 | u32 val; |
291906f1 | 1472 | |
f0575e92 KP |
1473 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1474 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1475 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1476 | |
649636ef | 1477 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1478 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1479 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1480 | pipe_name(pipe)); |
291906f1 | 1481 | |
649636ef | 1482 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1483 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1484 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1485 | pipe_name(pipe)); |
291906f1 | 1486 | |
e2debe91 PZ |
1487 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1488 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1489 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1490 | } |
1491 | ||
cd2d34d9 VS |
1492 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1493 | const struct intel_crtc_state *pipe_config) | |
1494 | { | |
1495 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1496 | enum pipe pipe = crtc->pipe; | |
1497 | ||
1498 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1499 | POSTING_READ(DPLL(pipe)); | |
1500 | udelay(150); | |
1501 | ||
2c30b43b CW |
1502 | if (intel_wait_for_register(dev_priv, |
1503 | DPLL(pipe), | |
1504 | DPLL_LOCK_VLV, | |
1505 | DPLL_LOCK_VLV, | |
1506 | 1)) | |
cd2d34d9 VS |
1507 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1508 | } | |
1509 | ||
d288f65f | 1510 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1511 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1512 | { |
cd2d34d9 | 1513 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1514 | enum pipe pipe = crtc->pipe; |
87442f73 | 1515 | |
8bd3f301 | 1516 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1517 | |
87442f73 | 1518 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1519 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1520 | |
cd2d34d9 VS |
1521 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1522 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1523 | |
8bd3f301 VS |
1524 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1525 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1526 | } |
1527 | ||
cd2d34d9 VS |
1528 | |
1529 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1530 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1531 | { |
cd2d34d9 | 1532 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1533 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1534 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1535 | u32 tmp; |
1536 | ||
a580516d | 1537 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1538 | |
1539 | /* Enable back the 10bit clock to display controller */ | |
1540 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1541 | tmp |= DPIO_DCLKP_EN; | |
1542 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1543 | ||
54433e91 VS |
1544 | mutex_unlock(&dev_priv->sb_lock); |
1545 | ||
9d556c99 CML |
1546 | /* |
1547 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1548 | */ | |
1549 | udelay(1); | |
1550 | ||
1551 | /* Enable PLL */ | |
d288f65f | 1552 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1553 | |
1554 | /* Check PLL is locked */ | |
6b18826a CW |
1555 | if (intel_wait_for_register(dev_priv, |
1556 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1557 | 1)) | |
9d556c99 | 1558 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1559 | } |
1560 | ||
1561 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1562 | const struct intel_crtc_state *pipe_config) | |
1563 | { | |
1564 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1565 | enum pipe pipe = crtc->pipe; | |
1566 | ||
1567 | assert_pipe_disabled(dev_priv, pipe); | |
1568 | ||
1569 | /* PLL is protected by panel, make sure we can write it */ | |
1570 | assert_panel_unlocked(dev_priv, pipe); | |
1571 | ||
1572 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1573 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1574 | |
c231775c VS |
1575 | if (pipe != PIPE_A) { |
1576 | /* | |
1577 | * WaPixelRepeatModeFixForC0:chv | |
1578 | * | |
1579 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1580 | * the value from DPLLBMD to either pipe B or C. | |
1581 | */ | |
1582 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1583 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1584 | I915_WRITE(CBR4_VLV, 0); | |
1585 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1586 | ||
1587 | /* | |
1588 | * DPLLB VGA mode also seems to cause problems. | |
1589 | * We should always have it disabled. | |
1590 | */ | |
1591 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1592 | } else { | |
1593 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1594 | POSTING_READ(DPLL_MD(pipe)); | |
1595 | } | |
9d556c99 CML |
1596 | } |
1597 | ||
1c4e0274 VS |
1598 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1599 | { | |
1600 | struct intel_crtc *crtc; | |
1601 | int count = 0; | |
1602 | ||
2d84d2b3 | 1603 | for_each_intel_crtc(dev, crtc) { |
3538b9df | 1604 | count += crtc->base.state->active && |
2d84d2b3 VS |
1605 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1606 | } | |
1c4e0274 VS |
1607 | |
1608 | return count; | |
1609 | } | |
1610 | ||
66e3d5c0 | 1611 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1612 | { |
66e3d5c0 | 1613 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1614 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1615 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1616 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1617 | |
66e3d5c0 | 1618 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1619 | |
63d7bbe9 | 1620 | /* PLL is protected by panel, make sure we can write it */ |
50a0bc90 | 1621 | if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) |
66e3d5c0 | 1622 | assert_panel_unlocked(dev_priv, crtc->pipe); |
63d7bbe9 | 1623 | |
1c4e0274 | 1624 | /* Enable DVO 2x clock on both PLLs if necessary */ |
50a0bc90 | 1625 | if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev) > 0) { |
1c4e0274 VS |
1626 | /* |
1627 | * It appears to be important that we don't enable this | |
1628 | * for the current pipe before otherwise configuring the | |
1629 | * PLL. No idea how this should be handled if multiple | |
1630 | * DVO outputs are enabled simultaneosly. | |
1631 | */ | |
1632 | dpll |= DPLL_DVO_2X_MODE; | |
1633 | I915_WRITE(DPLL(!crtc->pipe), | |
1634 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1635 | } | |
66e3d5c0 | 1636 | |
c2b63374 VS |
1637 | /* |
1638 | * Apparently we need to have VGA mode enabled prior to changing | |
1639 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1640 | * dividers, even though the register value does change. | |
1641 | */ | |
1642 | I915_WRITE(reg, 0); | |
1643 | ||
8e7a65aa VS |
1644 | I915_WRITE(reg, dpll); |
1645 | ||
66e3d5c0 DV |
1646 | /* Wait for the clocks to stabilize. */ |
1647 | POSTING_READ(reg); | |
1648 | udelay(150); | |
1649 | ||
1650 | if (INTEL_INFO(dev)->gen >= 4) { | |
1651 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1652 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1653 | } else { |
1654 | /* The pixel multiplier can only be updated once the | |
1655 | * DPLL is enabled and the clocks are stable. | |
1656 | * | |
1657 | * So write it again. | |
1658 | */ | |
1659 | I915_WRITE(reg, dpll); | |
1660 | } | |
63d7bbe9 JB |
1661 | |
1662 | /* We do this three times for luck */ | |
66e3d5c0 | 1663 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1664 | POSTING_READ(reg); |
1665 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1666 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1667 | POSTING_READ(reg); |
1668 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1669 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1670 | POSTING_READ(reg); |
1671 | udelay(150); /* wait for warmup */ | |
1672 | } | |
1673 | ||
1674 | /** | |
50b44a44 | 1675 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1676 | * @dev_priv: i915 private structure |
1677 | * @pipe: pipe PLL to disable | |
1678 | * | |
1679 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1680 | * | |
1681 | * Note! This is for pre-ILK only. | |
1682 | */ | |
1c4e0274 | 1683 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1684 | { |
1c4e0274 | 1685 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1686 | struct drm_i915_private *dev_priv = to_i915(dev); |
1c4e0274 VS |
1687 | enum pipe pipe = crtc->pipe; |
1688 | ||
1689 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
50a0bc90 | 1690 | if (IS_I830(dev_priv) && |
2d84d2b3 | 1691 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
3538b9df | 1692 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1693 | I915_WRITE(DPLL(PIPE_B), |
1694 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1695 | I915_WRITE(DPLL(PIPE_A), | |
1696 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1697 | } | |
1698 | ||
b6b5d049 VS |
1699 | /* Don't disable pipe or pipe PLLs if needed */ |
1700 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1701 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1702 | return; |
1703 | ||
1704 | /* Make sure the pipe isn't still relying on us */ | |
1705 | assert_pipe_disabled(dev_priv, pipe); | |
1706 | ||
b8afb911 | 1707 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1708 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1709 | } |
1710 | ||
f6071166 JB |
1711 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1712 | { | |
b8afb911 | 1713 | u32 val; |
f6071166 JB |
1714 | |
1715 | /* Make sure the pipe isn't still relying on us */ | |
1716 | assert_pipe_disabled(dev_priv, pipe); | |
1717 | ||
03ed5cbf VS |
1718 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1719 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1720 | if (pipe != PIPE_A) | |
1721 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1722 | ||
f6071166 JB |
1723 | I915_WRITE(DPLL(pipe), val); |
1724 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1725 | } |
1726 | ||
1727 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1728 | { | |
d752048d | 1729 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1730 | u32 val; |
1731 | ||
a11b0703 VS |
1732 | /* Make sure the pipe isn't still relying on us */ |
1733 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1734 | |
60bfe44f VS |
1735 | val = DPLL_SSC_REF_CLK_CHV | |
1736 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1737 | if (pipe != PIPE_A) |
1738 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1739 | |
a11b0703 VS |
1740 | I915_WRITE(DPLL(pipe), val); |
1741 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1742 | |
a580516d | 1743 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1744 | |
1745 | /* Disable 10bit clock to display controller */ | |
1746 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1747 | val &= ~DPIO_DCLKP_EN; | |
1748 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1749 | ||
a580516d | 1750 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1751 | } |
1752 | ||
e4607fcf | 1753 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1754 | struct intel_digital_port *dport, |
1755 | unsigned int expected_mask) | |
89b667f8 JB |
1756 | { |
1757 | u32 port_mask; | |
f0f59a00 | 1758 | i915_reg_t dpll_reg; |
89b667f8 | 1759 | |
e4607fcf CML |
1760 | switch (dport->port) { |
1761 | case PORT_B: | |
89b667f8 | 1762 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1763 | dpll_reg = DPLL(0); |
e4607fcf CML |
1764 | break; |
1765 | case PORT_C: | |
89b667f8 | 1766 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1767 | dpll_reg = DPLL(0); |
9b6de0a1 | 1768 | expected_mask <<= 4; |
00fc31b7 CML |
1769 | break; |
1770 | case PORT_D: | |
1771 | port_mask = DPLL_PORTD_READY_MASK; | |
1772 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1773 | break; |
1774 | default: | |
1775 | BUG(); | |
1776 | } | |
89b667f8 | 1777 | |
370004d3 CW |
1778 | if (intel_wait_for_register(dev_priv, |
1779 | dpll_reg, port_mask, expected_mask, | |
1780 | 1000)) | |
9b6de0a1 VS |
1781 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1782 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1783 | } |
1784 | ||
b8a4f404 PZ |
1785 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1786 | enum pipe pipe) | |
040484af | 1787 | { |
98187836 VS |
1788 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
1789 | pipe); | |
f0f59a00 VS |
1790 | i915_reg_t reg; |
1791 | uint32_t val, pipeconf_val; | |
040484af | 1792 | |
040484af | 1793 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1794 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1795 | |
1796 | /* FDI must be feeding us bits for PCH ports */ | |
1797 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1798 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1799 | ||
6e266956 | 1800 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1801 | /* Workaround: Set the timing override bit before enabling the |
1802 | * pch transcoder. */ | |
1803 | reg = TRANS_CHICKEN2(pipe); | |
1804 | val = I915_READ(reg); | |
1805 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1806 | I915_WRITE(reg, val); | |
59c859d6 | 1807 | } |
23670b32 | 1808 | |
ab9412ba | 1809 | reg = PCH_TRANSCONF(pipe); |
040484af | 1810 | val = I915_READ(reg); |
5f7f726d | 1811 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1812 | |
2d1fe073 | 1813 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1814 | /* |
c5de7c6f VS |
1815 | * Make the BPC in transcoder be consistent with |
1816 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1817 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1818 | */ |
dfd07d72 | 1819 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1820 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1821 | val |= PIPECONF_8BPC; |
1822 | else | |
1823 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1824 | } |
5f7f726d PZ |
1825 | |
1826 | val &= ~TRANS_INTERLACE_MASK; | |
1827 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1828 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1829 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1830 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1831 | else | |
1832 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1833 | else |
1834 | val |= TRANS_PROGRESSIVE; | |
1835 | ||
040484af | 1836 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1837 | if (intel_wait_for_register(dev_priv, |
1838 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1839 | 100)) | |
4bb6f1f3 | 1840 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1841 | } |
1842 | ||
8fb033d7 | 1843 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1844 | enum transcoder cpu_transcoder) |
040484af | 1845 | { |
8fb033d7 | 1846 | u32 val, pipeconf_val; |
8fb033d7 | 1847 | |
8fb033d7 | 1848 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1849 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1850 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1851 | |
223a6fdf | 1852 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1853 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1854 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1855 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1856 | |
25f3ef11 | 1857 | val = TRANS_ENABLE; |
937bb610 | 1858 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1859 | |
9a76b1c6 PZ |
1860 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1861 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1862 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1863 | else |
1864 | val |= TRANS_PROGRESSIVE; | |
1865 | ||
ab9412ba | 1866 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1867 | if (intel_wait_for_register(dev_priv, |
1868 | LPT_TRANSCONF, | |
1869 | TRANS_STATE_ENABLE, | |
1870 | TRANS_STATE_ENABLE, | |
1871 | 100)) | |
937bb610 | 1872 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1873 | } |
1874 | ||
b8a4f404 PZ |
1875 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1876 | enum pipe pipe) | |
040484af | 1877 | { |
f0f59a00 VS |
1878 | i915_reg_t reg; |
1879 | uint32_t val; | |
040484af JB |
1880 | |
1881 | /* FDI relies on the transcoder */ | |
1882 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1883 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1884 | ||
291906f1 JB |
1885 | /* Ports must be off as well */ |
1886 | assert_pch_ports_disabled(dev_priv, pipe); | |
1887 | ||
ab9412ba | 1888 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1889 | val = I915_READ(reg); |
1890 | val &= ~TRANS_ENABLE; | |
1891 | I915_WRITE(reg, val); | |
1892 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1893 | if (intel_wait_for_register(dev_priv, |
1894 | reg, TRANS_STATE_ENABLE, 0, | |
1895 | 50)) | |
4bb6f1f3 | 1896 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1897 | |
6e266956 | 1898 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1899 | /* Workaround: Clear the timing override chicken bit again. */ |
1900 | reg = TRANS_CHICKEN2(pipe); | |
1901 | val = I915_READ(reg); | |
1902 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1903 | I915_WRITE(reg, val); | |
1904 | } | |
040484af JB |
1905 | } |
1906 | ||
b7076546 | 1907 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1908 | { |
8fb033d7 PZ |
1909 | u32 val; |
1910 | ||
ab9412ba | 1911 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1912 | val &= ~TRANS_ENABLE; |
ab9412ba | 1913 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1914 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1915 | if (intel_wait_for_register(dev_priv, |
1916 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1917 | 50)) | |
8a52fd9f | 1918 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1919 | |
1920 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1921 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1922 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1923 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1924 | } |
1925 | ||
65f2130c VS |
1926 | enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc) |
1927 | { | |
1928 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1929 | ||
1930 | WARN_ON(!crtc->config->has_pch_encoder); | |
1931 | ||
1932 | if (HAS_PCH_LPT(dev_priv)) | |
1933 | return TRANSCODER_A; | |
1934 | else | |
1935 | return (enum transcoder) crtc->pipe; | |
1936 | } | |
1937 | ||
b24e7179 | 1938 | /** |
309cfea8 | 1939 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1940 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1941 | * |
0372264a | 1942 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1943 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1944 | */ |
e1fdc473 | 1945 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1946 | { |
0372264a | 1947 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1948 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1949 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1950 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
f0f59a00 | 1951 | i915_reg_t reg; |
b24e7179 JB |
1952 | u32 val; |
1953 | ||
9e2ee2dd VS |
1954 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1955 | ||
58c6eaa2 | 1956 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1957 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1958 | assert_sprites_disabled(dev_priv, pipe); |
1959 | ||
b24e7179 JB |
1960 | /* |
1961 | * A pipe without a PLL won't actually be able to drive bits from | |
1962 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1963 | * need the check. | |
1964 | */ | |
09fa8bb9 | 1965 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
d7edc4e5 | 1966 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1967 | assert_dsi_pll_enabled(dev_priv); |
1968 | else | |
1969 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1970 | } else { |
6e3c9717 | 1971 | if (crtc->config->has_pch_encoder) { |
040484af | 1972 | /* if driving the PCH, we need FDI enabled */ |
65f2130c VS |
1973 | assert_fdi_rx_pll_enabled(dev_priv, |
1974 | (enum pipe) intel_crtc_pch_transcoder(crtc)); | |
1a240d4d DV |
1975 | assert_fdi_tx_pll_enabled(dev_priv, |
1976 | (enum pipe) cpu_transcoder); | |
040484af JB |
1977 | } |
1978 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1979 | } | |
b24e7179 | 1980 | |
702e7a56 | 1981 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1982 | val = I915_READ(reg); |
7ad25d48 | 1983 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
1984 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1985 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 1986 | return; |
7ad25d48 | 1987 | } |
00d70b15 CW |
1988 | |
1989 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1990 | POSTING_READ(reg); |
b7792d8b VS |
1991 | |
1992 | /* | |
1993 | * Until the pipe starts DSL will read as 0, which would cause | |
1994 | * an apparent vblank timestamp jump, which messes up also the | |
1995 | * frame count when it's derived from the timestamps. So let's | |
1996 | * wait for the pipe to start properly before we call | |
1997 | * drm_crtc_vblank_on() | |
1998 | */ | |
1999 | if (dev->max_vblank_count == 0 && | |
2000 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
2001 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
2002 | } |
2003 | ||
2004 | /** | |
309cfea8 | 2005 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2006 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2007 | * |
575f7ab7 VS |
2008 | * Disable the pipe of @crtc, making sure that various hardware |
2009 | * specific requirements are met, if applicable, e.g. plane | |
2010 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2011 | * |
2012 | * Will wait until the pipe has shut down before returning. | |
2013 | */ | |
575f7ab7 | 2014 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2015 | { |
fac5e23e | 2016 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 2017 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2018 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2019 | i915_reg_t reg; |
b24e7179 JB |
2020 | u32 val; |
2021 | ||
9e2ee2dd VS |
2022 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2023 | ||
b24e7179 JB |
2024 | /* |
2025 | * Make sure planes won't keep trying to pump pixels to us, | |
2026 | * or we might hang the display. | |
2027 | */ | |
2028 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2029 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2030 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2031 | |
702e7a56 | 2032 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2033 | val = I915_READ(reg); |
00d70b15 CW |
2034 | if ((val & PIPECONF_ENABLE) == 0) |
2035 | return; | |
2036 | ||
67adc644 VS |
2037 | /* |
2038 | * Double wide has implications for planes | |
2039 | * so best keep it disabled when not needed. | |
2040 | */ | |
6e3c9717 | 2041 | if (crtc->config->double_wide) |
67adc644 VS |
2042 | val &= ~PIPECONF_DOUBLE_WIDE; |
2043 | ||
2044 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2045 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2046 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2047 | val &= ~PIPECONF_ENABLE; |
2048 | ||
2049 | I915_WRITE(reg, val); | |
2050 | if ((val & PIPECONF_ENABLE) == 0) | |
2051 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2052 | } |
2053 | ||
832be82f VS |
2054 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2055 | { | |
2056 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2057 | } | |
2058 | ||
27ba3910 VS |
2059 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2060 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2061 | { |
2062 | switch (fb_modifier) { | |
2063 | case DRM_FORMAT_MOD_NONE: | |
2064 | return cpp; | |
2065 | case I915_FORMAT_MOD_X_TILED: | |
2066 | if (IS_GEN2(dev_priv)) | |
2067 | return 128; | |
2068 | else | |
2069 | return 512; | |
2070 | case I915_FORMAT_MOD_Y_TILED: | |
2071 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2072 | return 128; | |
2073 | else | |
2074 | return 512; | |
2075 | case I915_FORMAT_MOD_Yf_TILED: | |
2076 | switch (cpp) { | |
2077 | case 1: | |
2078 | return 64; | |
2079 | case 2: | |
2080 | case 4: | |
2081 | return 128; | |
2082 | case 8: | |
2083 | case 16: | |
2084 | return 256; | |
2085 | default: | |
2086 | MISSING_CASE(cpp); | |
2087 | return cpp; | |
2088 | } | |
2089 | break; | |
2090 | default: | |
2091 | MISSING_CASE(fb_modifier); | |
2092 | return cpp; | |
2093 | } | |
2094 | } | |
2095 | ||
832be82f VS |
2096 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2097 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2098 | { |
832be82f VS |
2099 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2100 | return 1; | |
2101 | else | |
2102 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2103 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2104 | } |
2105 | ||
8d0deca8 VS |
2106 | /* Return the tile dimensions in pixel units */ |
2107 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2108 | unsigned int *tile_width, | |
2109 | unsigned int *tile_height, | |
2110 | uint64_t fb_modifier, | |
2111 | unsigned int cpp) | |
2112 | { | |
2113 | unsigned int tile_width_bytes = | |
2114 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2115 | ||
2116 | *tile_width = tile_width_bytes / cpp; | |
2117 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2118 | } | |
2119 | ||
6761dd31 TU |
2120 | unsigned int |
2121 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2122 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2123 | { |
832be82f VS |
2124 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2125 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2126 | ||
2127 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2128 | } |
2129 | ||
1663b9d6 VS |
2130 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2131 | { | |
2132 | unsigned int size = 0; | |
2133 | int i; | |
2134 | ||
2135 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2136 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2137 | ||
2138 | return size; | |
2139 | } | |
2140 | ||
75c82a53 | 2141 | static void |
3465c580 VS |
2142 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2143 | const struct drm_framebuffer *fb, | |
2144 | unsigned int rotation) | |
f64b98cd | 2145 | { |
bd2ef25d | 2146 | if (drm_rotation_90_or_270(rotation)) { |
2d7a215f VS |
2147 | *view = i915_ggtt_view_rotated; |
2148 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2149 | } else { | |
2150 | *view = i915_ggtt_view_normal; | |
2151 | } | |
2152 | } | |
50470bb0 | 2153 | |
603525d7 | 2154 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2155 | { |
2156 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2157 | return 256 * 1024; | |
985b8bb4 | 2158 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2159 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2160 | return 128 * 1024; |
2161 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2162 | return 4 * 1024; | |
2163 | else | |
44c5905e | 2164 | return 0; |
4e9a86b6 VS |
2165 | } |
2166 | ||
603525d7 VS |
2167 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2168 | uint64_t fb_modifier) | |
2169 | { | |
2170 | switch (fb_modifier) { | |
2171 | case DRM_FORMAT_MOD_NONE: | |
2172 | return intel_linear_alignment(dev_priv); | |
2173 | case I915_FORMAT_MOD_X_TILED: | |
2174 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2175 | return 256 * 1024; | |
2176 | return 0; | |
2177 | case I915_FORMAT_MOD_Y_TILED: | |
2178 | case I915_FORMAT_MOD_Yf_TILED: | |
2179 | return 1 * 1024 * 1024; | |
2180 | default: | |
2181 | MISSING_CASE(fb_modifier); | |
2182 | return 0; | |
2183 | } | |
2184 | } | |
2185 | ||
058d88c4 CW |
2186 | struct i915_vma * |
2187 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) | |
6b95a207 | 2188 | { |
850c4cdc | 2189 | struct drm_device *dev = fb->dev; |
fac5e23e | 2190 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2191 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2192 | struct i915_ggtt_view view; |
058d88c4 | 2193 | struct i915_vma *vma; |
6b95a207 | 2194 | u32 alignment; |
6b95a207 | 2195 | |
ebcdd39e MR |
2196 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2197 | ||
603525d7 | 2198 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2199 | |
3465c580 | 2200 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2201 | |
693db184 CW |
2202 | /* Note that the w/a also requires 64 PTE of padding following the |
2203 | * bo. We currently fill all unused PTE with the shadow page and so | |
2204 | * we should always have valid PTE following the scanout preventing | |
2205 | * the VT-d warning. | |
2206 | */ | |
48f112fe | 2207 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2208 | alignment = 256 * 1024; |
2209 | ||
d6dd6843 PZ |
2210 | /* |
2211 | * Global gtt pte registers are special registers which actually forward | |
2212 | * writes to a chunk of system memory. Which means that there is no risk | |
2213 | * that the register values disappear as soon as we call | |
2214 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2215 | * pin/unpin/fence and not more. | |
2216 | */ | |
2217 | intel_runtime_pm_get(dev_priv); | |
2218 | ||
058d88c4 | 2219 | vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); |
49ef5294 CW |
2220 | if (IS_ERR(vma)) |
2221 | goto err; | |
6b95a207 | 2222 | |
05a20d09 | 2223 | if (i915_vma_is_map_and_fenceable(vma)) { |
49ef5294 CW |
2224 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2225 | * fence, whereas 965+ only requires a fence if using | |
2226 | * framebuffer compression. For simplicity, we always, when | |
2227 | * possible, install a fence as the cost is not that onerous. | |
2228 | * | |
2229 | * If we fail to fence the tiled scanout, then either the | |
2230 | * modeset will reject the change (which is highly unlikely as | |
2231 | * the affected systems, all but one, do not have unmappable | |
2232 | * space) or we will not be able to enable full powersaving | |
2233 | * techniques (also likely not to apply due to various limits | |
2234 | * FBC and the like impose on the size of the buffer, which | |
2235 | * presumably we violated anyway with this unmappable buffer). | |
2236 | * Anyway, it is presumably better to stumble onwards with | |
2237 | * something and try to run the system in a "less than optimal" | |
2238 | * mode that matches the user configuration. | |
2239 | */ | |
2240 | if (i915_vma_get_fence(vma) == 0) | |
2241 | i915_vma_pin_fence(vma); | |
9807216f | 2242 | } |
6b95a207 | 2243 | |
49ef5294 | 2244 | err: |
d6dd6843 | 2245 | intel_runtime_pm_put(dev_priv); |
058d88c4 | 2246 | return vma; |
6b95a207 KH |
2247 | } |
2248 | ||
fb4b8ce1 | 2249 | void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2250 | { |
82bc3b2d | 2251 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2252 | struct i915_ggtt_view view; |
058d88c4 | 2253 | struct i915_vma *vma; |
82bc3b2d | 2254 | |
ebcdd39e MR |
2255 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2256 | ||
3465c580 | 2257 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
05a20d09 | 2258 | vma = i915_gem_object_to_ggtt(obj, &view); |
f64b98cd | 2259 | |
49ef5294 | 2260 | i915_vma_unpin_fence(vma); |
058d88c4 | 2261 | i915_gem_object_unpin_from_display_plane(vma); |
1690e1eb CW |
2262 | } |
2263 | ||
ef78ec94 VS |
2264 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, |
2265 | unsigned int rotation) | |
2266 | { | |
bd2ef25d | 2267 | if (drm_rotation_90_or_270(rotation)) |
ef78ec94 VS |
2268 | return to_intel_framebuffer(fb)->rotated[plane].pitch; |
2269 | else | |
2270 | return fb->pitches[plane]; | |
2271 | } | |
2272 | ||
6687c906 VS |
2273 | /* |
2274 | * Convert the x/y offsets into a linear offset. | |
2275 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2276 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2277 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2278 | */ | |
2279 | u32 intel_fb_xy_to_linear(int x, int y, | |
2949056c VS |
2280 | const struct intel_plane_state *state, |
2281 | int plane) | |
6687c906 | 2282 | { |
2949056c | 2283 | const struct drm_framebuffer *fb = state->base.fb; |
6687c906 VS |
2284 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); |
2285 | unsigned int pitch = fb->pitches[plane]; | |
2286 | ||
2287 | return y * pitch + x * cpp; | |
2288 | } | |
2289 | ||
2290 | /* | |
2291 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2292 | * specified plane src x/y offsets. The resulting x/y offsets | |
2293 | * specify the start of scanout from the beginning of the gtt mapping. | |
2294 | */ | |
2295 | void intel_add_fb_offsets(int *x, int *y, | |
2949056c VS |
2296 | const struct intel_plane_state *state, |
2297 | int plane) | |
6687c906 VS |
2298 | |
2299 | { | |
2949056c VS |
2300 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb); |
2301 | unsigned int rotation = state->base.rotation; | |
6687c906 | 2302 | |
bd2ef25d | 2303 | if (drm_rotation_90_or_270(rotation)) { |
6687c906 VS |
2304 | *x += intel_fb->rotated[plane].x; |
2305 | *y += intel_fb->rotated[plane].y; | |
2306 | } else { | |
2307 | *x += intel_fb->normal[plane].x; | |
2308 | *y += intel_fb->normal[plane].y; | |
2309 | } | |
2310 | } | |
2311 | ||
29cf9491 | 2312 | /* |
29cf9491 VS |
2313 | * Input tile dimensions and pitch must already be |
2314 | * rotated to match x and y, and in pixel units. | |
2315 | */ | |
66a2d927 VS |
2316 | static u32 _intel_adjust_tile_offset(int *x, int *y, |
2317 | unsigned int tile_width, | |
2318 | unsigned int tile_height, | |
2319 | unsigned int tile_size, | |
2320 | unsigned int pitch_tiles, | |
2321 | u32 old_offset, | |
2322 | u32 new_offset) | |
29cf9491 | 2323 | { |
b9b24038 | 2324 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
29cf9491 VS |
2325 | unsigned int tiles; |
2326 | ||
2327 | WARN_ON(old_offset & (tile_size - 1)); | |
2328 | WARN_ON(new_offset & (tile_size - 1)); | |
2329 | WARN_ON(new_offset > old_offset); | |
2330 | ||
2331 | tiles = (old_offset - new_offset) / tile_size; | |
2332 | ||
2333 | *y += tiles / pitch_tiles * tile_height; | |
2334 | *x += tiles % pitch_tiles * tile_width; | |
2335 | ||
b9b24038 VS |
2336 | /* minimize x in case it got needlessly big */ |
2337 | *y += *x / pitch_pixels * tile_height; | |
2338 | *x %= pitch_pixels; | |
2339 | ||
29cf9491 VS |
2340 | return new_offset; |
2341 | } | |
2342 | ||
66a2d927 VS |
2343 | /* |
2344 | * Adjust the tile offset by moving the difference into | |
2345 | * the x/y offsets. | |
2346 | */ | |
2347 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2348 | const struct intel_plane_state *state, int plane, | |
2349 | u32 old_offset, u32 new_offset) | |
2350 | { | |
2351 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); | |
2352 | const struct drm_framebuffer *fb = state->base.fb; | |
2353 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2354 | unsigned int rotation = state->base.rotation; | |
2355 | unsigned int pitch = intel_fb_pitch(fb, plane, rotation); | |
2356 | ||
2357 | WARN_ON(new_offset > old_offset); | |
2358 | ||
2359 | if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) { | |
2360 | unsigned int tile_size, tile_width, tile_height; | |
2361 | unsigned int pitch_tiles; | |
2362 | ||
2363 | tile_size = intel_tile_size(dev_priv); | |
2364 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
2365 | fb->modifier[plane], cpp); | |
2366 | ||
bd2ef25d | 2367 | if (drm_rotation_90_or_270(rotation)) { |
66a2d927 VS |
2368 | pitch_tiles = pitch / tile_height; |
2369 | swap(tile_width, tile_height); | |
2370 | } else { | |
2371 | pitch_tiles = pitch / (tile_width * cpp); | |
2372 | } | |
2373 | ||
2374 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, | |
2375 | tile_size, pitch_tiles, | |
2376 | old_offset, new_offset); | |
2377 | } else { | |
2378 | old_offset += *y * pitch + *x * cpp; | |
2379 | ||
2380 | *y = (old_offset - new_offset) / pitch; | |
2381 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; | |
2382 | } | |
2383 | ||
2384 | return new_offset; | |
2385 | } | |
2386 | ||
8d0deca8 VS |
2387 | /* |
2388 | * Computes the linear offset to the base tile and adjusts | |
2389 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2390 | * | |
2391 | * In the 90/270 rotated case, x and y are assumed | |
2392 | * to be already rotated to match the rotated GTT view, and | |
2393 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2394 | * |
2395 | * This function is used when computing the derived information | |
2396 | * under intel_framebuffer, so using any of that information | |
2397 | * here is not allowed. Anything under drm_framebuffer can be | |
2398 | * used. This is why the user has to pass in the pitch since it | |
2399 | * is specified in the rotated orientation. | |
8d0deca8 | 2400 | */ |
6687c906 VS |
2401 | static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, |
2402 | int *x, int *y, | |
2403 | const struct drm_framebuffer *fb, int plane, | |
2404 | unsigned int pitch, | |
2405 | unsigned int rotation, | |
2406 | u32 alignment) | |
c2c75131 | 2407 | { |
4f2d9934 VS |
2408 | uint64_t fb_modifier = fb->modifier[plane]; |
2409 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
6687c906 | 2410 | u32 offset, offset_aligned; |
29cf9491 | 2411 | |
29cf9491 VS |
2412 | if (alignment) |
2413 | alignment--; | |
2414 | ||
b5c65338 | 2415 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2416 | unsigned int tile_size, tile_width, tile_height; |
2417 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2418 | |
d843310d | 2419 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2420 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2421 | fb_modifier, cpp); | |
2422 | ||
bd2ef25d | 2423 | if (drm_rotation_90_or_270(rotation)) { |
8d0deca8 VS |
2424 | pitch_tiles = pitch / tile_height; |
2425 | swap(tile_width, tile_height); | |
2426 | } else { | |
2427 | pitch_tiles = pitch / (tile_width * cpp); | |
2428 | } | |
d843310d VS |
2429 | |
2430 | tile_rows = *y / tile_height; | |
2431 | *y %= tile_height; | |
c2c75131 | 2432 | |
8d0deca8 VS |
2433 | tiles = *x / tile_width; |
2434 | *x %= tile_width; | |
bc752862 | 2435 | |
29cf9491 VS |
2436 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2437 | offset_aligned = offset & ~alignment; | |
bc752862 | 2438 | |
66a2d927 VS |
2439 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2440 | tile_size, pitch_tiles, | |
2441 | offset, offset_aligned); | |
29cf9491 | 2442 | } else { |
bc752862 | 2443 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2444 | offset_aligned = offset & ~alignment; |
2445 | ||
4e9a86b6 VS |
2446 | *y = (offset & alignment) / pitch; |
2447 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2448 | } |
29cf9491 VS |
2449 | |
2450 | return offset_aligned; | |
c2c75131 DV |
2451 | } |
2452 | ||
6687c906 | 2453 | u32 intel_compute_tile_offset(int *x, int *y, |
2949056c VS |
2454 | const struct intel_plane_state *state, |
2455 | int plane) | |
6687c906 | 2456 | { |
2949056c VS |
2457 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); |
2458 | const struct drm_framebuffer *fb = state->base.fb; | |
2459 | unsigned int rotation = state->base.rotation; | |
ef78ec94 | 2460 | int pitch = intel_fb_pitch(fb, plane, rotation); |
8d970654 VS |
2461 | u32 alignment; |
2462 | ||
2463 | /* AUX_DIST needs only 4K alignment */ | |
2464 | if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1) | |
2465 | alignment = 4096; | |
2466 | else | |
2467 | alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]); | |
6687c906 VS |
2468 | |
2469 | return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, | |
2470 | rotation, alignment); | |
2471 | } | |
2472 | ||
2473 | /* Convert the fb->offset[] linear offset into x/y offsets */ | |
2474 | static void intel_fb_offset_to_xy(int *x, int *y, | |
2475 | const struct drm_framebuffer *fb, int plane) | |
2476 | { | |
2477 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2478 | unsigned int pitch = fb->pitches[plane]; | |
2479 | u32 linear_offset = fb->offsets[plane]; | |
2480 | ||
2481 | *y = linear_offset / pitch; | |
2482 | *x = linear_offset % pitch / cpp; | |
2483 | } | |
2484 | ||
72618ebf VS |
2485 | static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) |
2486 | { | |
2487 | switch (fb_modifier) { | |
2488 | case I915_FORMAT_MOD_X_TILED: | |
2489 | return I915_TILING_X; | |
2490 | case I915_FORMAT_MOD_Y_TILED: | |
2491 | return I915_TILING_Y; | |
2492 | default: | |
2493 | return I915_TILING_NONE; | |
2494 | } | |
2495 | } | |
2496 | ||
6687c906 VS |
2497 | static int |
2498 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2499 | struct drm_framebuffer *fb) | |
2500 | { | |
2501 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2502 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
2503 | u32 gtt_offset_rotated = 0; | |
2504 | unsigned int max_size = 0; | |
2505 | uint32_t format = fb->pixel_format; | |
2506 | int i, num_planes = drm_format_num_planes(format); | |
2507 | unsigned int tile_size = intel_tile_size(dev_priv); | |
2508 | ||
2509 | for (i = 0; i < num_planes; i++) { | |
2510 | unsigned int width, height; | |
2511 | unsigned int cpp, size; | |
2512 | u32 offset; | |
2513 | int x, y; | |
2514 | ||
2515 | cpp = drm_format_plane_cpp(format, i); | |
2516 | width = drm_format_plane_width(fb->width, format, i); | |
2517 | height = drm_format_plane_height(fb->height, format, i); | |
2518 | ||
2519 | intel_fb_offset_to_xy(&x, &y, fb, i); | |
2520 | ||
60d5f2a4 VS |
2521 | /* |
2522 | * The fence (if used) is aligned to the start of the object | |
2523 | * so having the framebuffer wrap around across the edge of the | |
2524 | * fenced region doesn't really work. We have no API to configure | |
2525 | * the fence start offset within the object (nor could we probably | |
2526 | * on gen2/3). So it's just easier if we just require that the | |
2527 | * fb layout agrees with the fence layout. We already check that the | |
2528 | * fb stride matches the fence stride elsewhere. | |
2529 | */ | |
2530 | if (i915_gem_object_is_tiled(intel_fb->obj) && | |
2531 | (x + width) * cpp > fb->pitches[i]) { | |
2532 | DRM_DEBUG("bad fb plane %d offset: 0x%x\n", | |
2533 | i, fb->offsets[i]); | |
2534 | return -EINVAL; | |
2535 | } | |
2536 | ||
6687c906 VS |
2537 | /* |
2538 | * First pixel of the framebuffer from | |
2539 | * the start of the normal gtt mapping. | |
2540 | */ | |
2541 | intel_fb->normal[i].x = x; | |
2542 | intel_fb->normal[i].y = y; | |
2543 | ||
2544 | offset = _intel_compute_tile_offset(dev_priv, &x, &y, | |
2545 | fb, 0, fb->pitches[i], | |
cc926387 | 2546 | DRM_ROTATE_0, tile_size); |
6687c906 VS |
2547 | offset /= tile_size; |
2548 | ||
2549 | if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) { | |
2550 | unsigned int tile_width, tile_height; | |
2551 | unsigned int pitch_tiles; | |
2552 | struct drm_rect r; | |
2553 | ||
2554 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
2555 | fb->modifier[i], cpp); | |
2556 | ||
2557 | rot_info->plane[i].offset = offset; | |
2558 | rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); | |
2559 | rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
2560 | rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
2561 | ||
2562 | intel_fb->rotated[i].pitch = | |
2563 | rot_info->plane[i].height * tile_height; | |
2564 | ||
2565 | /* how many tiles does this plane need */ | |
2566 | size = rot_info->plane[i].stride * rot_info->plane[i].height; | |
2567 | /* | |
2568 | * If the plane isn't horizontally tile aligned, | |
2569 | * we need one more tile. | |
2570 | */ | |
2571 | if (x != 0) | |
2572 | size++; | |
2573 | ||
2574 | /* rotate the x/y offsets to match the GTT view */ | |
2575 | r.x1 = x; | |
2576 | r.y1 = y; | |
2577 | r.x2 = x + width; | |
2578 | r.y2 = y + height; | |
2579 | drm_rect_rotate(&r, | |
2580 | rot_info->plane[i].width * tile_width, | |
2581 | rot_info->plane[i].height * tile_height, | |
cc926387 | 2582 | DRM_ROTATE_270); |
6687c906 VS |
2583 | x = r.x1; |
2584 | y = r.y1; | |
2585 | ||
2586 | /* rotate the tile dimensions to match the GTT view */ | |
2587 | pitch_tiles = intel_fb->rotated[i].pitch / tile_height; | |
2588 | swap(tile_width, tile_height); | |
2589 | ||
2590 | /* | |
2591 | * We only keep the x/y offsets, so push all of the | |
2592 | * gtt offset into the x/y offsets. | |
2593 | */ | |
66a2d927 VS |
2594 | _intel_adjust_tile_offset(&x, &y, tile_size, |
2595 | tile_width, tile_height, pitch_tiles, | |
2596 | gtt_offset_rotated * tile_size, 0); | |
6687c906 VS |
2597 | |
2598 | gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; | |
2599 | ||
2600 | /* | |
2601 | * First pixel of the framebuffer from | |
2602 | * the start of the rotated gtt mapping. | |
2603 | */ | |
2604 | intel_fb->rotated[i].x = x; | |
2605 | intel_fb->rotated[i].y = y; | |
2606 | } else { | |
2607 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
2608 | x * cpp, tile_size); | |
2609 | } | |
2610 | ||
2611 | /* how many tiles in total needed in the bo */ | |
2612 | max_size = max(max_size, offset + size); | |
2613 | } | |
2614 | ||
2615 | if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) { | |
2616 | DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n", | |
2617 | max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size); | |
2618 | return -EINVAL; | |
2619 | } | |
2620 | ||
2621 | return 0; | |
2622 | } | |
2623 | ||
b35d63fa | 2624 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2625 | { |
2626 | switch (format) { | |
2627 | case DISPPLANE_8BPP: | |
2628 | return DRM_FORMAT_C8; | |
2629 | case DISPPLANE_BGRX555: | |
2630 | return DRM_FORMAT_XRGB1555; | |
2631 | case DISPPLANE_BGRX565: | |
2632 | return DRM_FORMAT_RGB565; | |
2633 | default: | |
2634 | case DISPPLANE_BGRX888: | |
2635 | return DRM_FORMAT_XRGB8888; | |
2636 | case DISPPLANE_RGBX888: | |
2637 | return DRM_FORMAT_XBGR8888; | |
2638 | case DISPPLANE_BGRX101010: | |
2639 | return DRM_FORMAT_XRGB2101010; | |
2640 | case DISPPLANE_RGBX101010: | |
2641 | return DRM_FORMAT_XBGR2101010; | |
2642 | } | |
2643 | } | |
2644 | ||
bc8d7dff DL |
2645 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2646 | { | |
2647 | switch (format) { | |
2648 | case PLANE_CTL_FORMAT_RGB_565: | |
2649 | return DRM_FORMAT_RGB565; | |
2650 | default: | |
2651 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2652 | if (rgb_order) { | |
2653 | if (alpha) | |
2654 | return DRM_FORMAT_ABGR8888; | |
2655 | else | |
2656 | return DRM_FORMAT_XBGR8888; | |
2657 | } else { | |
2658 | if (alpha) | |
2659 | return DRM_FORMAT_ARGB8888; | |
2660 | else | |
2661 | return DRM_FORMAT_XRGB8888; | |
2662 | } | |
2663 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2664 | if (rgb_order) | |
2665 | return DRM_FORMAT_XBGR2101010; | |
2666 | else | |
2667 | return DRM_FORMAT_XRGB2101010; | |
2668 | } | |
2669 | } | |
2670 | ||
5724dbd1 | 2671 | static bool |
f6936e29 DV |
2672 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2673 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2674 | { |
2675 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2676 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2677 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2678 | struct drm_i915_gem_object *obj = NULL; |
2679 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2680 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2681 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2682 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2683 | PAGE_SIZE); | |
2684 | ||
2685 | size_aligned -= base_aligned; | |
46f297fb | 2686 | |
ff2652ea CW |
2687 | if (plane_config->size == 0) |
2688 | return false; | |
2689 | ||
3badb49f PZ |
2690 | /* If the FB is too big, just don't use it since fbdev is not very |
2691 | * important and we should probably use that space with FBC or other | |
2692 | * features. */ | |
72e96d64 | 2693 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2694 | return false; |
2695 | ||
12c83d99 TU |
2696 | mutex_lock(&dev->struct_mutex); |
2697 | ||
f37b5c2b DV |
2698 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2699 | base_aligned, | |
2700 | base_aligned, | |
2701 | size_aligned); | |
12c83d99 TU |
2702 | if (!obj) { |
2703 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2704 | return false; |
12c83d99 | 2705 | } |
46f297fb | 2706 | |
3e510a8e CW |
2707 | if (plane_config->tiling == I915_TILING_X) |
2708 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; | |
46f297fb | 2709 | |
6bf129df DL |
2710 | mode_cmd.pixel_format = fb->pixel_format; |
2711 | mode_cmd.width = fb->width; | |
2712 | mode_cmd.height = fb->height; | |
2713 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2714 | mode_cmd.modifier[0] = fb->modifier[0]; |
2715 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2716 | |
6bf129df | 2717 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2718 | &mode_cmd, obj)) { |
46f297fb JB |
2719 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2720 | goto out_unref_obj; | |
2721 | } | |
12c83d99 | 2722 | |
46f297fb | 2723 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2724 | |
f6936e29 | 2725 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2726 | return true; |
46f297fb JB |
2727 | |
2728 | out_unref_obj: | |
f8c417cd | 2729 | i915_gem_object_put(obj); |
46f297fb | 2730 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2731 | return false; |
2732 | } | |
2733 | ||
5a21b665 DV |
2734 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2735 | static void | |
2736 | update_state_fb(struct drm_plane *plane) | |
2737 | { | |
2738 | if (plane->fb == plane->state->fb) | |
2739 | return; | |
2740 | ||
2741 | if (plane->state->fb) | |
2742 | drm_framebuffer_unreference(plane->state->fb); | |
2743 | plane->state->fb = plane->fb; | |
2744 | if (plane->state->fb) | |
2745 | drm_framebuffer_reference(plane->state->fb); | |
2746 | } | |
2747 | ||
5724dbd1 | 2748 | static void |
f6936e29 DV |
2749 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2750 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2751 | { |
2752 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2753 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd JB |
2754 | struct drm_crtc *c; |
2755 | struct intel_crtc *i; | |
2ff8fde1 | 2756 | struct drm_i915_gem_object *obj; |
88595ac9 | 2757 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2758 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2759 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2760 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2761 | struct intel_plane_state *intel_state = |
2762 | to_intel_plane_state(plane_state); | |
88595ac9 | 2763 | struct drm_framebuffer *fb; |
484b41dd | 2764 | |
2d14030b | 2765 | if (!plane_config->fb) |
484b41dd JB |
2766 | return; |
2767 | ||
f6936e29 | 2768 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2769 | fb = &plane_config->fb->base; |
2770 | goto valid_fb; | |
f55548b5 | 2771 | } |
484b41dd | 2772 | |
2d14030b | 2773 | kfree(plane_config->fb); |
484b41dd JB |
2774 | |
2775 | /* | |
2776 | * Failed to alloc the obj, check to see if we should share | |
2777 | * an fb with another CRTC instead | |
2778 | */ | |
70e1e0ec | 2779 | for_each_crtc(dev, c) { |
484b41dd JB |
2780 | i = to_intel_crtc(c); |
2781 | ||
2782 | if (c == &intel_crtc->base) | |
2783 | continue; | |
2784 | ||
2ff8fde1 MR |
2785 | if (!i->active) |
2786 | continue; | |
2787 | ||
88595ac9 DV |
2788 | fb = c->primary->fb; |
2789 | if (!fb) | |
484b41dd JB |
2790 | continue; |
2791 | ||
88595ac9 | 2792 | obj = intel_fb_obj(fb); |
058d88c4 | 2793 | if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) { |
88595ac9 DV |
2794 | drm_framebuffer_reference(fb); |
2795 | goto valid_fb; | |
484b41dd JB |
2796 | } |
2797 | } | |
88595ac9 | 2798 | |
200757f5 MR |
2799 | /* |
2800 | * We've failed to reconstruct the BIOS FB. Current display state | |
2801 | * indicates that the primary plane is visible, but has a NULL FB, | |
2802 | * which will lead to problems later if we don't fix it up. The | |
2803 | * simplest solution is to just disable the primary plane now and | |
2804 | * pretend the BIOS never had it enabled. | |
2805 | */ | |
936e71e3 | 2806 | to_intel_plane_state(plane_state)->base.visible = false; |
200757f5 | 2807 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); |
2622a081 | 2808 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2809 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2810 | ||
88595ac9 DV |
2811 | return; |
2812 | ||
2813 | valid_fb: | |
f44e2659 VS |
2814 | plane_state->src_x = 0; |
2815 | plane_state->src_y = 0; | |
be5651f2 ML |
2816 | plane_state->src_w = fb->width << 16; |
2817 | plane_state->src_h = fb->height << 16; | |
2818 | ||
f44e2659 VS |
2819 | plane_state->crtc_x = 0; |
2820 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2821 | plane_state->crtc_w = fb->width; |
2822 | plane_state->crtc_h = fb->height; | |
2823 | ||
1638d30c RC |
2824 | intel_state->base.src = drm_plane_state_src(plane_state); |
2825 | intel_state->base.dst = drm_plane_state_dest(plane_state); | |
0a8d8a86 | 2826 | |
88595ac9 | 2827 | obj = intel_fb_obj(fb); |
3e510a8e | 2828 | if (i915_gem_object_is_tiled(obj)) |
88595ac9 DV |
2829 | dev_priv->preserve_bios_swizzle = true; |
2830 | ||
be5651f2 ML |
2831 | drm_framebuffer_reference(fb); |
2832 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2833 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2834 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
faf5bf0a CW |
2835 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
2836 | &obj->frontbuffer_bits); | |
46f297fb JB |
2837 | } |
2838 | ||
b63a16f6 VS |
2839 | static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, |
2840 | unsigned int rotation) | |
2841 | { | |
2842 | int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
2843 | ||
2844 | switch (fb->modifier[plane]) { | |
2845 | case DRM_FORMAT_MOD_NONE: | |
2846 | case I915_FORMAT_MOD_X_TILED: | |
2847 | switch (cpp) { | |
2848 | case 8: | |
2849 | return 4096; | |
2850 | case 4: | |
2851 | case 2: | |
2852 | case 1: | |
2853 | return 8192; | |
2854 | default: | |
2855 | MISSING_CASE(cpp); | |
2856 | break; | |
2857 | } | |
2858 | break; | |
2859 | case I915_FORMAT_MOD_Y_TILED: | |
2860 | case I915_FORMAT_MOD_Yf_TILED: | |
2861 | switch (cpp) { | |
2862 | case 8: | |
2863 | return 2048; | |
2864 | case 4: | |
2865 | return 4096; | |
2866 | case 2: | |
2867 | case 1: | |
2868 | return 8192; | |
2869 | default: | |
2870 | MISSING_CASE(cpp); | |
2871 | break; | |
2872 | } | |
2873 | break; | |
2874 | default: | |
2875 | MISSING_CASE(fb->modifier[plane]); | |
2876 | } | |
2877 | ||
2878 | return 2048; | |
2879 | } | |
2880 | ||
2881 | static int skl_check_main_surface(struct intel_plane_state *plane_state) | |
2882 | { | |
2883 | const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev); | |
2884 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2885 | unsigned int rotation = plane_state->base.rotation; | |
cc926387 DV |
2886 | int x = plane_state->base.src.x1 >> 16; |
2887 | int y = plane_state->base.src.y1 >> 16; | |
2888 | int w = drm_rect_width(&plane_state->base.src) >> 16; | |
2889 | int h = drm_rect_height(&plane_state->base.src) >> 16; | |
b63a16f6 VS |
2890 | int max_width = skl_max_plane_width(fb, 0, rotation); |
2891 | int max_height = 4096; | |
8d970654 | 2892 | u32 alignment, offset, aux_offset = plane_state->aux.offset; |
b63a16f6 VS |
2893 | |
2894 | if (w > max_width || h > max_height) { | |
2895 | DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n", | |
2896 | w, h, max_width, max_height); | |
2897 | return -EINVAL; | |
2898 | } | |
2899 | ||
2900 | intel_add_fb_offsets(&x, &y, plane_state, 0); | |
2901 | offset = intel_compute_tile_offset(&x, &y, plane_state, 0); | |
2902 | ||
2903 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); | |
2904 | ||
8d970654 VS |
2905 | /* |
2906 | * AUX surface offset is specified as the distance from the | |
2907 | * main surface offset, and it must be non-negative. Make | |
2908 | * sure that is what we will get. | |
2909 | */ | |
2910 | if (offset > aux_offset) | |
2911 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2912 | offset, aux_offset & ~(alignment - 1)); | |
2913 | ||
b63a16f6 VS |
2914 | /* |
2915 | * When using an X-tiled surface, the plane blows up | |
2916 | * if the x offset + width exceed the stride. | |
2917 | * | |
2918 | * TODO: linear and Y-tiled seem fine, Yf untested, | |
2919 | */ | |
2920 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) { | |
2921 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
2922 | ||
2923 | while ((x + w) * cpp > fb->pitches[0]) { | |
2924 | if (offset == 0) { | |
2925 | DRM_DEBUG_KMS("Unable to find suitable display surface offset\n"); | |
2926 | return -EINVAL; | |
2927 | } | |
2928 | ||
2929 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2930 | offset, offset - alignment); | |
2931 | } | |
2932 | } | |
2933 | ||
2934 | plane_state->main.offset = offset; | |
2935 | plane_state->main.x = x; | |
2936 | plane_state->main.y = y; | |
2937 | ||
2938 | return 0; | |
2939 | } | |
2940 | ||
8d970654 VS |
2941 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
2942 | { | |
2943 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2944 | unsigned int rotation = plane_state->base.rotation; | |
2945 | int max_width = skl_max_plane_width(fb, 1, rotation); | |
2946 | int max_height = 4096; | |
cc926387 DV |
2947 | int x = plane_state->base.src.x1 >> 17; |
2948 | int y = plane_state->base.src.y1 >> 17; | |
2949 | int w = drm_rect_width(&plane_state->base.src) >> 17; | |
2950 | int h = drm_rect_height(&plane_state->base.src) >> 17; | |
8d970654 VS |
2951 | u32 offset; |
2952 | ||
2953 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
2954 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
2955 | ||
2956 | /* FIXME not quite sure how/if these apply to the chroma plane */ | |
2957 | if (w > max_width || h > max_height) { | |
2958 | DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n", | |
2959 | w, h, max_width, max_height); | |
2960 | return -EINVAL; | |
2961 | } | |
2962 | ||
2963 | plane_state->aux.offset = offset; | |
2964 | plane_state->aux.x = x; | |
2965 | plane_state->aux.y = y; | |
2966 | ||
2967 | return 0; | |
2968 | } | |
2969 | ||
b63a16f6 VS |
2970 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
2971 | { | |
2972 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2973 | unsigned int rotation = plane_state->base.rotation; | |
2974 | int ret; | |
2975 | ||
2976 | /* Rotate src coordinates to match rotated GTT view */ | |
bd2ef25d | 2977 | if (drm_rotation_90_or_270(rotation)) |
cc926387 | 2978 | drm_rect_rotate(&plane_state->base.src, |
da064b47 VS |
2979 | fb->width << 16, fb->height << 16, |
2980 | DRM_ROTATE_270); | |
b63a16f6 | 2981 | |
8d970654 VS |
2982 | /* |
2983 | * Handle the AUX surface first since | |
2984 | * the main surface setup depends on it. | |
2985 | */ | |
2986 | if (fb->pixel_format == DRM_FORMAT_NV12) { | |
2987 | ret = skl_check_nv12_aux_surface(plane_state); | |
2988 | if (ret) | |
2989 | return ret; | |
2990 | } else { | |
2991 | plane_state->aux.offset = ~0xfff; | |
2992 | plane_state->aux.x = 0; | |
2993 | plane_state->aux.y = 0; | |
2994 | } | |
2995 | ||
b63a16f6 VS |
2996 | ret = skl_check_main_surface(plane_state); |
2997 | if (ret) | |
2998 | return ret; | |
2999 | ||
3000 | return 0; | |
3001 | } | |
3002 | ||
a8d201af ML |
3003 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
3004 | const struct intel_crtc_state *crtc_state, | |
3005 | const struct intel_plane_state *plane_state) | |
81255565 | 3006 | { |
a8d201af | 3007 | struct drm_device *dev = primary->dev; |
fac5e23e | 3008 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3009 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3010 | struct drm_framebuffer *fb = plane_state->base.fb; | |
3011 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 3012 | int plane = intel_crtc->plane; |
54ea9da8 | 3013 | u32 linear_offset; |
81255565 | 3014 | u32 dspcntr; |
f0f59a00 | 3015 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 3016 | unsigned int rotation = plane_state->base.rotation; |
936e71e3 VS |
3017 | int x = plane_state->base.src.x1 >> 16; |
3018 | int y = plane_state->base.src.y1 >> 16; | |
c9ba6fad | 3019 | |
f45651ba VS |
3020 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
3021 | ||
fdd508a6 | 3022 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
3023 | |
3024 | if (INTEL_INFO(dev)->gen < 4) { | |
3025 | if (intel_crtc->pipe == PIPE_B) | |
3026 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
3027 | ||
3028 | /* pipesrc and dspsize control the size that is scaled from, | |
3029 | * which should always be the user's requested size. | |
3030 | */ | |
3031 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
3032 | ((crtc_state->pipe_src_h - 1) << 16) | |
3033 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 3034 | I915_WRITE(DSPPOS(plane), 0); |
920a14b2 | 3035 | } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) { |
c14b0485 | 3036 | I915_WRITE(PRIMSIZE(plane), |
a8d201af ML |
3037 | ((crtc_state->pipe_src_h - 1) << 16) | |
3038 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
3039 | I915_WRITE(PRIMPOS(plane), 0); |
3040 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 3041 | } |
81255565 | 3042 | |
57779d06 VS |
3043 | switch (fb->pixel_format) { |
3044 | case DRM_FORMAT_C8: | |
81255565 JB |
3045 | dspcntr |= DISPPLANE_8BPP; |
3046 | break; | |
57779d06 | 3047 | case DRM_FORMAT_XRGB1555: |
57779d06 | 3048 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 3049 | break; |
57779d06 VS |
3050 | case DRM_FORMAT_RGB565: |
3051 | dspcntr |= DISPPLANE_BGRX565; | |
3052 | break; | |
3053 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
3054 | dspcntr |= DISPPLANE_BGRX888; |
3055 | break; | |
3056 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3057 | dspcntr |= DISPPLANE_RGBX888; |
3058 | break; | |
3059 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3060 | dspcntr |= DISPPLANE_BGRX101010; |
3061 | break; | |
3062 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3063 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
3064 | break; |
3065 | default: | |
baba133a | 3066 | BUG(); |
81255565 | 3067 | } |
57779d06 | 3068 | |
72618ebf VS |
3069 | if (INTEL_GEN(dev_priv) >= 4 && |
3070 | fb->modifier[0] == I915_FORMAT_MOD_X_TILED) | |
f45651ba | 3071 | dspcntr |= DISPPLANE_TILED; |
81255565 | 3072 | |
9beb5fea | 3073 | if (IS_G4X(dev_priv)) |
de1aa629 VS |
3074 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
3075 | ||
2949056c | 3076 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
81255565 | 3077 | |
6687c906 | 3078 | if (INTEL_INFO(dev)->gen >= 4) |
c2c75131 | 3079 | intel_crtc->dspaddr_offset = |
2949056c | 3080 | intel_compute_tile_offset(&x, &y, plane_state, 0); |
e506a0c6 | 3081 | |
31ad61e4 | 3082 | if (rotation == DRM_ROTATE_180) { |
48404c1e SJ |
3083 | dspcntr |= DISPPLANE_ROTATE_180; |
3084 | ||
a8d201af ML |
3085 | x += (crtc_state->pipe_src_w - 1); |
3086 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
3087 | } |
3088 | ||
2949056c | 3089 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 VS |
3090 | |
3091 | if (INTEL_INFO(dev)->gen < 4) | |
3092 | intel_crtc->dspaddr_offset = linear_offset; | |
3093 | ||
2db3366b PZ |
3094 | intel_crtc->adjusted_x = x; |
3095 | intel_crtc->adjusted_y = y; | |
3096 | ||
48404c1e SJ |
3097 | I915_WRITE(reg, dspcntr); |
3098 | ||
01f2c773 | 3099 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 3100 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d | 3101 | I915_WRITE(DSPSURF(plane), |
6687c906 VS |
3102 | intel_fb_gtt_offset(fb, rotation) + |
3103 | intel_crtc->dspaddr_offset); | |
5eddb70b | 3104 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 3105 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 3106 | } else |
058d88c4 | 3107 | I915_WRITE(DSPADDR(plane), i915_gem_object_ggtt_offset(obj, NULL) + linear_offset); |
5eddb70b | 3108 | POSTING_READ(reg); |
17638cd6 JB |
3109 | } |
3110 | ||
a8d201af ML |
3111 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
3112 | struct drm_crtc *crtc) | |
17638cd6 JB |
3113 | { |
3114 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3115 | struct drm_i915_private *dev_priv = to_i915(dev); |
17638cd6 | 3116 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
17638cd6 | 3117 | int plane = intel_crtc->plane; |
f45651ba | 3118 | |
a8d201af ML |
3119 | I915_WRITE(DSPCNTR(plane), 0); |
3120 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 3121 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
3122 | else |
3123 | I915_WRITE(DSPADDR(plane), 0); | |
3124 | POSTING_READ(DSPCNTR(plane)); | |
3125 | } | |
c9ba6fad | 3126 | |
a8d201af ML |
3127 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
3128 | const struct intel_crtc_state *crtc_state, | |
3129 | const struct intel_plane_state *plane_state) | |
3130 | { | |
3131 | struct drm_device *dev = primary->dev; | |
fac5e23e | 3132 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3133 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3134 | struct drm_framebuffer *fb = plane_state->base.fb; | |
a8d201af | 3135 | int plane = intel_crtc->plane; |
54ea9da8 | 3136 | u32 linear_offset; |
a8d201af ML |
3137 | u32 dspcntr; |
3138 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 3139 | unsigned int rotation = plane_state->base.rotation; |
936e71e3 VS |
3140 | int x = plane_state->base.src.x1 >> 16; |
3141 | int y = plane_state->base.src.y1 >> 16; | |
c9ba6fad | 3142 | |
f45651ba | 3143 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 3144 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba | 3145 | |
8652744b | 3146 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f45651ba | 3147 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; |
17638cd6 | 3148 | |
57779d06 VS |
3149 | switch (fb->pixel_format) { |
3150 | case DRM_FORMAT_C8: | |
17638cd6 JB |
3151 | dspcntr |= DISPPLANE_8BPP; |
3152 | break; | |
57779d06 VS |
3153 | case DRM_FORMAT_RGB565: |
3154 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 3155 | break; |
57779d06 | 3156 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
3157 | dspcntr |= DISPPLANE_BGRX888; |
3158 | break; | |
3159 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3160 | dspcntr |= DISPPLANE_RGBX888; |
3161 | break; | |
3162 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3163 | dspcntr |= DISPPLANE_BGRX101010; |
3164 | break; | |
3165 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3166 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
3167 | break; |
3168 | default: | |
baba133a | 3169 | BUG(); |
17638cd6 JB |
3170 | } |
3171 | ||
72618ebf | 3172 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) |
17638cd6 | 3173 | dspcntr |= DISPPLANE_TILED; |
17638cd6 | 3174 | |
8652744b | 3175 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) |
1f5d76db | 3176 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 3177 | |
2949056c | 3178 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
6687c906 | 3179 | |
c2c75131 | 3180 | intel_crtc->dspaddr_offset = |
2949056c | 3181 | intel_compute_tile_offset(&x, &y, plane_state, 0); |
6687c906 | 3182 | |
31ad61e4 | 3183 | if (rotation == DRM_ROTATE_180) { |
48404c1e SJ |
3184 | dspcntr |= DISPPLANE_ROTATE_180; |
3185 | ||
8652744b | 3186 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { |
a8d201af ML |
3187 | x += (crtc_state->pipe_src_w - 1); |
3188 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
3189 | } |
3190 | } | |
3191 | ||
2949056c | 3192 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3193 | |
2db3366b PZ |
3194 | intel_crtc->adjusted_x = x; |
3195 | intel_crtc->adjusted_y = y; | |
3196 | ||
48404c1e | 3197 | I915_WRITE(reg, dspcntr); |
17638cd6 | 3198 | |
01f2c773 | 3199 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d | 3200 | I915_WRITE(DSPSURF(plane), |
6687c906 VS |
3201 | intel_fb_gtt_offset(fb, rotation) + |
3202 | intel_crtc->dspaddr_offset); | |
8652744b | 3203 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
bc1c91eb DL |
3204 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
3205 | } else { | |
3206 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
3207 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
3208 | } | |
17638cd6 | 3209 | POSTING_READ(reg); |
17638cd6 JB |
3210 | } |
3211 | ||
7b49f948 VS |
3212 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
3213 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 3214 | { |
7b49f948 | 3215 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 3216 | return 64; |
7b49f948 VS |
3217 | } else { |
3218 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
3219 | ||
27ba3910 | 3220 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
3221 | } |
3222 | } | |
3223 | ||
6687c906 VS |
3224 | u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, |
3225 | unsigned int rotation) | |
121920fa | 3226 | { |
6687c906 | 3227 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ce7f1728 | 3228 | struct i915_ggtt_view view; |
058d88c4 | 3229 | struct i915_vma *vma; |
121920fa | 3230 | |
6687c906 | 3231 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
dedf278c | 3232 | |
058d88c4 CW |
3233 | vma = i915_gem_object_to_ggtt(obj, &view); |
3234 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", | |
3235 | view.type)) | |
3236 | return -1; | |
3237 | ||
bde13ebd | 3238 | return i915_ggtt_offset(vma); |
121920fa TU |
3239 | } |
3240 | ||
e435d6e5 ML |
3241 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
3242 | { | |
3243 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3244 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
3245 | |
3246 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3247 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3248 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3249 | } |
3250 | ||
a1b2278e CK |
3251 | /* |
3252 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3253 | */ | |
0583236e | 3254 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3255 | { |
a1b2278e CK |
3256 | struct intel_crtc_scaler_state *scaler_state; |
3257 | int i; | |
3258 | ||
a1b2278e CK |
3259 | scaler_state = &intel_crtc->config->scaler_state; |
3260 | ||
3261 | /* loop through and disable scalers that aren't in use */ | |
3262 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3263 | if (!scaler_state->scalers[i].in_use) |
3264 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3265 | } |
3266 | } | |
3267 | ||
d2196774 VS |
3268 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
3269 | unsigned int rotation) | |
3270 | { | |
3271 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); | |
3272 | u32 stride = intel_fb_pitch(fb, plane, rotation); | |
3273 | ||
3274 | /* | |
3275 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
3276 | * linear buffers or in number of tiles for tiled buffers. | |
3277 | */ | |
bd2ef25d | 3278 | if (drm_rotation_90_or_270(rotation)) { |
d2196774 VS |
3279 | int cpp = drm_format_plane_cpp(fb->pixel_format, plane); |
3280 | ||
3281 | stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp); | |
3282 | } else { | |
3283 | stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0], | |
3284 | fb->pixel_format); | |
3285 | } | |
3286 | ||
3287 | return stride; | |
3288 | } | |
3289 | ||
6156a456 | 3290 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3291 | { |
6156a456 | 3292 | switch (pixel_format) { |
d161cf7a | 3293 | case DRM_FORMAT_C8: |
c34ce3d1 | 3294 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3295 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3296 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3297 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3298 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3299 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3300 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3301 | /* |
3302 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3303 | * to be already pre-multiplied. We need to add a knob (or a different | |
3304 | * DRM_FORMAT) for user-space to configure that. | |
3305 | */ | |
f75fb42a | 3306 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3307 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3308 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3309 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3310 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3311 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3312 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3313 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3314 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3315 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3316 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3317 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3318 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3319 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3320 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3321 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3322 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3323 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3324 | default: |
4249eeef | 3325 | MISSING_CASE(pixel_format); |
70d21f0e | 3326 | } |
8cfcba41 | 3327 | |
c34ce3d1 | 3328 | return 0; |
6156a456 | 3329 | } |
70d21f0e | 3330 | |
6156a456 CK |
3331 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3332 | { | |
6156a456 | 3333 | switch (fb_modifier) { |
30af77c4 | 3334 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3335 | break; |
30af77c4 | 3336 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3337 | return PLANE_CTL_TILED_X; |
b321803d | 3338 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3339 | return PLANE_CTL_TILED_Y; |
b321803d | 3340 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3341 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3342 | default: |
6156a456 | 3343 | MISSING_CASE(fb_modifier); |
70d21f0e | 3344 | } |
8cfcba41 | 3345 | |
c34ce3d1 | 3346 | return 0; |
6156a456 | 3347 | } |
70d21f0e | 3348 | |
6156a456 CK |
3349 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3350 | { | |
3b7a5119 | 3351 | switch (rotation) { |
31ad61e4 | 3352 | case DRM_ROTATE_0: |
6156a456 | 3353 | break; |
1e8df167 SJ |
3354 | /* |
3355 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3356 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3357 | */ | |
31ad61e4 | 3358 | case DRM_ROTATE_90: |
1e8df167 | 3359 | return PLANE_CTL_ROTATE_270; |
31ad61e4 | 3360 | case DRM_ROTATE_180: |
c34ce3d1 | 3361 | return PLANE_CTL_ROTATE_180; |
31ad61e4 | 3362 | case DRM_ROTATE_270: |
1e8df167 | 3363 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3364 | default: |
3365 | MISSING_CASE(rotation); | |
3366 | } | |
3367 | ||
c34ce3d1 | 3368 | return 0; |
6156a456 CK |
3369 | } |
3370 | ||
a8d201af ML |
3371 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3372 | const struct intel_crtc_state *crtc_state, | |
3373 | const struct intel_plane_state *plane_state) | |
6156a456 | 3374 | { |
a8d201af | 3375 | struct drm_device *dev = plane->dev; |
fac5e23e | 3376 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3377 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3378 | struct drm_framebuffer *fb = plane_state->base.fb; | |
62e0fb88 | 3379 | const struct skl_wm_values *wm = &dev_priv->wm.skl_results; |
d8c0fafc | 3380 | const struct skl_plane_wm *p_wm = |
3381 | &crtc_state->wm.skl.optimal.planes[0]; | |
6156a456 | 3382 | int pipe = intel_crtc->pipe; |
d2196774 | 3383 | u32 plane_ctl; |
a8d201af | 3384 | unsigned int rotation = plane_state->base.rotation; |
d2196774 | 3385 | u32 stride = skl_plane_stride(fb, 0, rotation); |
b63a16f6 | 3386 | u32 surf_addr = plane_state->main.offset; |
a8d201af | 3387 | int scaler_id = plane_state->scaler_id; |
b63a16f6 VS |
3388 | int src_x = plane_state->main.x; |
3389 | int src_y = plane_state->main.y; | |
936e71e3 VS |
3390 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; |
3391 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3392 | int dst_x = plane_state->base.dst.x1; | |
3393 | int dst_y = plane_state->base.dst.y1; | |
3394 | int dst_w = drm_rect_width(&plane_state->base.dst); | |
3395 | int dst_h = drm_rect_height(&plane_state->base.dst); | |
70d21f0e | 3396 | |
6156a456 CK |
3397 | plane_ctl = PLANE_CTL_ENABLE | |
3398 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3399 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3400 | ||
3401 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3402 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3403 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3404 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3405 | ||
6687c906 VS |
3406 | /* Sizes are 0 based */ |
3407 | src_w--; | |
3408 | src_h--; | |
3409 | dst_w--; | |
3410 | dst_h--; | |
3411 | ||
4c0b8a8b PZ |
3412 | intel_crtc->dspaddr_offset = surf_addr; |
3413 | ||
6687c906 VS |
3414 | intel_crtc->adjusted_x = src_x; |
3415 | intel_crtc->adjusted_y = src_y; | |
2db3366b | 3416 | |
62e0fb88 | 3417 | if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) |
d8c0fafc | 3418 | skl_write_plane_wm(intel_crtc, p_wm, &wm->ddb, 0); |
62e0fb88 | 3419 | |
70d21f0e | 3420 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
6687c906 | 3421 | I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x); |
ef78ec94 | 3422 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); |
6687c906 | 3423 | I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w); |
6156a456 CK |
3424 | |
3425 | if (scaler_id >= 0) { | |
3426 | uint32_t ps_ctrl = 0; | |
3427 | ||
3428 | WARN_ON(!dst_w || !dst_h); | |
3429 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3430 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3431 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3432 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3433 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3434 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3435 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3436 | } else { | |
3437 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3438 | } | |
3439 | ||
6687c906 VS |
3440 | I915_WRITE(PLANE_SURF(pipe, 0), |
3441 | intel_fb_gtt_offset(fb, rotation) + surf_addr); | |
70d21f0e DL |
3442 | |
3443 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3444 | } | |
3445 | ||
a8d201af ML |
3446 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3447 | struct drm_crtc *crtc) | |
17638cd6 JB |
3448 | { |
3449 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3450 | struct drm_i915_private *dev_priv = to_i915(dev); |
62e0fb88 | 3451 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
d8c0fafc | 3452 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
3453 | const struct skl_plane_wm *p_wm = &cstate->wm.skl.optimal.planes[0]; | |
62e0fb88 L |
3454 | int pipe = intel_crtc->pipe; |
3455 | ||
ccebc23b L |
3456 | /* |
3457 | * We only populate skl_results on watermark updates, and if the | |
3458 | * plane's visiblity isn't actually changing neither is its watermarks. | |
3459 | */ | |
3460 | if (!crtc->primary->state->visible) | |
d8c0fafc | 3461 | skl_write_plane_wm(intel_crtc, p_wm, |
3462 | &dev_priv->wm.skl_results.ddb, 0); | |
17638cd6 | 3463 | |
a8d201af ML |
3464 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3465 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3466 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3467 | } | |
29b9bde6 | 3468 | |
a8d201af ML |
3469 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3470 | static int | |
3471 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3472 | int x, int y, enum mode_set_atomic state) | |
3473 | { | |
3474 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3475 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3476 | ||
3477 | return -ENODEV; | |
81255565 JB |
3478 | } |
3479 | ||
5a21b665 DV |
3480 | static void intel_complete_page_flips(struct drm_i915_private *dev_priv) |
3481 | { | |
3482 | struct intel_crtc *crtc; | |
3483 | ||
91c8a326 | 3484 | for_each_intel_crtc(&dev_priv->drm, crtc) |
5a21b665 DV |
3485 | intel_finish_page_flip_cs(dev_priv, crtc->pipe); |
3486 | } | |
3487 | ||
7514747d VS |
3488 | static void intel_update_primary_planes(struct drm_device *dev) |
3489 | { | |
7514747d | 3490 | struct drm_crtc *crtc; |
96a02917 | 3491 | |
70e1e0ec | 3492 | for_each_crtc(dev, crtc) { |
11c22da6 | 3493 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
73974893 ML |
3494 | struct intel_plane_state *plane_state = |
3495 | to_intel_plane_state(plane->base.state); | |
11c22da6 | 3496 | |
936e71e3 | 3497 | if (plane_state->base.visible) |
a8d201af ML |
3498 | plane->update_plane(&plane->base, |
3499 | to_intel_crtc_state(crtc->state), | |
3500 | plane_state); | |
73974893 ML |
3501 | } |
3502 | } | |
3503 | ||
3504 | static int | |
3505 | __intel_display_resume(struct drm_device *dev, | |
3506 | struct drm_atomic_state *state) | |
3507 | { | |
3508 | struct drm_crtc_state *crtc_state; | |
3509 | struct drm_crtc *crtc; | |
3510 | int i, ret; | |
11c22da6 | 3511 | |
73974893 ML |
3512 | intel_modeset_setup_hw_state(dev); |
3513 | i915_redisable_vga(dev); | |
3514 | ||
3515 | if (!state) | |
3516 | return 0; | |
3517 | ||
3518 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
3519 | /* | |
3520 | * Force recalculation even if we restore | |
3521 | * current state. With fast modeset this may not result | |
3522 | * in a modeset when the state is compatible. | |
3523 | */ | |
3524 | crtc_state->mode_changed = true; | |
96a02917 | 3525 | } |
73974893 ML |
3526 | |
3527 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
3528 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
3529 | ||
3530 | ret = drm_atomic_commit(state); | |
3531 | ||
3532 | WARN_ON(ret == -EDEADLK); | |
3533 | return ret; | |
96a02917 VS |
3534 | } |
3535 | ||
4ac2ba2f VS |
3536 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
3537 | { | |
ae98104b VS |
3538 | return intel_has_gpu_reset(dev_priv) && |
3539 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); | |
4ac2ba2f VS |
3540 | } |
3541 | ||
c033666a | 3542 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 3543 | { |
73974893 ML |
3544 | struct drm_device *dev = &dev_priv->drm; |
3545 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3546 | struct drm_atomic_state *state; | |
3547 | int ret; | |
3548 | ||
73974893 ML |
3549 | /* |
3550 | * Need mode_config.mutex so that we don't | |
3551 | * trample ongoing ->detect() and whatnot. | |
3552 | */ | |
3553 | mutex_lock(&dev->mode_config.mutex); | |
3554 | drm_modeset_acquire_init(ctx, 0); | |
3555 | while (1) { | |
3556 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
3557 | if (ret != -EDEADLK) | |
3558 | break; | |
3559 | ||
3560 | drm_modeset_backoff(ctx); | |
3561 | } | |
3562 | ||
3563 | /* reset doesn't touch the display, but flips might get nuked anyway, */ | |
522a63de | 3564 | if (!i915.force_reset_modeset_test && |
4ac2ba2f | 3565 | !gpu_reset_clobbers_display(dev_priv)) |
7514747d VS |
3566 | return; |
3567 | ||
f98ce92f VS |
3568 | /* |
3569 | * Disabling the crtcs gracefully seems nicer. Also the | |
3570 | * g33 docs say we should at least disable all the planes. | |
3571 | */ | |
73974893 ML |
3572 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
3573 | if (IS_ERR(state)) { | |
3574 | ret = PTR_ERR(state); | |
3575 | state = NULL; | |
3576 | DRM_ERROR("Duplicating state failed with %i\n", ret); | |
3577 | goto err; | |
3578 | } | |
3579 | ||
3580 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
3581 | if (ret) { | |
3582 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
3583 | goto err; | |
3584 | } | |
3585 | ||
3586 | dev_priv->modeset_restore_state = state; | |
3587 | state->acquire_ctx = ctx; | |
3588 | return; | |
3589 | ||
3590 | err: | |
0853695c | 3591 | drm_atomic_state_put(state); |
7514747d VS |
3592 | } |
3593 | ||
c033666a | 3594 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3595 | { |
73974893 ML |
3596 | struct drm_device *dev = &dev_priv->drm; |
3597 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3598 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
3599 | int ret; | |
3600 | ||
5a21b665 DV |
3601 | /* |
3602 | * Flips in the rings will be nuked by the reset, | |
3603 | * so complete all pending flips so that user space | |
3604 | * will get its events and not get stuck. | |
3605 | */ | |
3606 | intel_complete_page_flips(dev_priv); | |
3607 | ||
73974893 ML |
3608 | dev_priv->modeset_restore_state = NULL; |
3609 | ||
7514747d | 3610 | /* reset doesn't touch the display */ |
4ac2ba2f | 3611 | if (!gpu_reset_clobbers_display(dev_priv)) { |
522a63de ML |
3612 | if (!state) { |
3613 | /* | |
3614 | * Flips in the rings have been nuked by the reset, | |
3615 | * so update the base address of all primary | |
3616 | * planes to the the last fb to make sure we're | |
3617 | * showing the correct fb after a reset. | |
3618 | * | |
3619 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3620 | * CS-based flips (which might get lost in gpu resets) any more. | |
3621 | */ | |
3622 | intel_update_primary_planes(dev); | |
3623 | } else { | |
3624 | ret = __intel_display_resume(dev, state); | |
3625 | if (ret) | |
3626 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
3627 | } | |
73974893 ML |
3628 | } else { |
3629 | /* | |
3630 | * The display has been reset as well, | |
3631 | * so need a full re-initialization. | |
3632 | */ | |
3633 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3634 | intel_runtime_pm_enable_interrupts(dev_priv); | |
7514747d | 3635 | |
51f59205 | 3636 | intel_pps_unlock_regs_wa(dev_priv); |
73974893 | 3637 | intel_modeset_init_hw(dev); |
7514747d | 3638 | |
73974893 ML |
3639 | spin_lock_irq(&dev_priv->irq_lock); |
3640 | if (dev_priv->display.hpd_irq_setup) | |
3641 | dev_priv->display.hpd_irq_setup(dev_priv); | |
3642 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 3643 | |
73974893 ML |
3644 | ret = __intel_display_resume(dev, state); |
3645 | if (ret) | |
3646 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
7514747d | 3647 | |
73974893 ML |
3648 | intel_hpd_init(dev_priv); |
3649 | } | |
7514747d | 3650 | |
0853695c CW |
3651 | if (state) |
3652 | drm_atomic_state_put(state); | |
73974893 ML |
3653 | drm_modeset_drop_locks(ctx); |
3654 | drm_modeset_acquire_fini(ctx); | |
3655 | mutex_unlock(&dev->mode_config.mutex); | |
7514747d VS |
3656 | } |
3657 | ||
8af29b0c CW |
3658 | static bool abort_flip_on_reset(struct intel_crtc *crtc) |
3659 | { | |
3660 | struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error; | |
3661 | ||
3662 | if (i915_reset_in_progress(error)) | |
3663 | return true; | |
3664 | ||
3665 | if (crtc->reset_count != i915_reset_count(error)) | |
3666 | return true; | |
3667 | ||
3668 | return false; | |
3669 | } | |
3670 | ||
7d5e3799 CW |
3671 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3672 | { | |
5a21b665 DV |
3673 | struct drm_device *dev = crtc->dev; |
3674 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5a21b665 DV |
3675 | bool pending; |
3676 | ||
8af29b0c | 3677 | if (abort_flip_on_reset(intel_crtc)) |
5a21b665 DV |
3678 | return false; |
3679 | ||
3680 | spin_lock_irq(&dev->event_lock); | |
3681 | pending = to_intel_crtc(crtc)->flip_work != NULL; | |
3682 | spin_unlock_irq(&dev->event_lock); | |
3683 | ||
3684 | return pending; | |
7d5e3799 CW |
3685 | } |
3686 | ||
bfd16b2a ML |
3687 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3688 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3689 | { |
3690 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 3691 | struct drm_i915_private *dev_priv = to_i915(dev); |
bfd16b2a ML |
3692 | struct intel_crtc_state *pipe_config = |
3693 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3694 | |
bfd16b2a ML |
3695 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3696 | crtc->base.mode = crtc->base.state->mode; | |
3697 | ||
3698 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3699 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3700 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 GP |
3701 | |
3702 | /* | |
3703 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3704 | * that in compute_mode_changes we check the native mode (not the pfit | |
3705 | * mode) to see if we can flip rather than do a full mode set. In the | |
3706 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3707 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3708 | * sized surface. | |
e30e8f75 GP |
3709 | */ |
3710 | ||
e30e8f75 | 3711 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3712 | ((pipe_config->pipe_src_w - 1) << 16) | |
3713 | (pipe_config->pipe_src_h - 1)); | |
3714 | ||
3715 | /* on skylake this is done by detaching scalers */ | |
3716 | if (INTEL_INFO(dev)->gen >= 9) { | |
3717 | skl_detach_scalers(crtc); | |
3718 | ||
3719 | if (pipe_config->pch_pfit.enabled) | |
3720 | skylake_pfit_enable(crtc); | |
6e266956 | 3721 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
bfd16b2a ML |
3722 | if (pipe_config->pch_pfit.enabled) |
3723 | ironlake_pfit_enable(crtc); | |
3724 | else if (old_crtc_state->pch_pfit.enabled) | |
3725 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3726 | } |
e30e8f75 GP |
3727 | } |
3728 | ||
5e84e1a4 ZW |
3729 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3730 | { | |
3731 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3732 | struct drm_i915_private *dev_priv = to_i915(dev); |
5e84e1a4 ZW |
3733 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3734 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3735 | i915_reg_t reg; |
3736 | u32 temp; | |
5e84e1a4 ZW |
3737 | |
3738 | /* enable normal train */ | |
3739 | reg = FDI_TX_CTL(pipe); | |
3740 | temp = I915_READ(reg); | |
fd6b8f43 | 3741 | if (IS_IVYBRIDGE(dev_priv)) { |
357555c0 JB |
3742 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3743 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3744 | } else { |
3745 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3746 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3747 | } |
5e84e1a4 ZW |
3748 | I915_WRITE(reg, temp); |
3749 | ||
3750 | reg = FDI_RX_CTL(pipe); | |
3751 | temp = I915_READ(reg); | |
6e266956 | 3752 | if (HAS_PCH_CPT(dev_priv)) { |
5e84e1a4 ZW |
3753 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3754 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3755 | } else { | |
3756 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3757 | temp |= FDI_LINK_TRAIN_NONE; | |
3758 | } | |
3759 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3760 | ||
3761 | /* wait one idle pattern time */ | |
3762 | POSTING_READ(reg); | |
3763 | udelay(1000); | |
357555c0 JB |
3764 | |
3765 | /* IVB wants error correction enabled */ | |
fd6b8f43 | 3766 | if (IS_IVYBRIDGE(dev_priv)) |
357555c0 JB |
3767 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
3768 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3769 | } |
3770 | ||
8db9d77b ZW |
3771 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3772 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3773 | { | |
3774 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3775 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3776 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3777 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3778 | i915_reg_t reg; |
3779 | u32 temp, tries; | |
8db9d77b | 3780 | |
1c8562f6 | 3781 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3782 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3783 | |
e1a44743 AJ |
3784 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3785 | for train result */ | |
5eddb70b CW |
3786 | reg = FDI_RX_IMR(pipe); |
3787 | temp = I915_READ(reg); | |
e1a44743 AJ |
3788 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3789 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3790 | I915_WRITE(reg, temp); |
3791 | I915_READ(reg); | |
e1a44743 AJ |
3792 | udelay(150); |
3793 | ||
8db9d77b | 3794 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3795 | reg = FDI_TX_CTL(pipe); |
3796 | temp = I915_READ(reg); | |
627eb5a3 | 3797 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3798 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3799 | temp &= ~FDI_LINK_TRAIN_NONE; |
3800 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3801 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3802 | |
5eddb70b CW |
3803 | reg = FDI_RX_CTL(pipe); |
3804 | temp = I915_READ(reg); | |
8db9d77b ZW |
3805 | temp &= ~FDI_LINK_TRAIN_NONE; |
3806 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3807 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3808 | ||
3809 | POSTING_READ(reg); | |
8db9d77b ZW |
3810 | udelay(150); |
3811 | ||
5b2adf89 | 3812 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3813 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3814 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3815 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3816 | |
5eddb70b | 3817 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3818 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3819 | temp = I915_READ(reg); |
8db9d77b ZW |
3820 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3821 | ||
3822 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3823 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3824 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3825 | break; |
3826 | } | |
8db9d77b | 3827 | } |
e1a44743 | 3828 | if (tries == 5) |
5eddb70b | 3829 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3830 | |
3831 | /* Train 2 */ | |
5eddb70b CW |
3832 | reg = FDI_TX_CTL(pipe); |
3833 | temp = I915_READ(reg); | |
8db9d77b ZW |
3834 | temp &= ~FDI_LINK_TRAIN_NONE; |
3835 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3836 | I915_WRITE(reg, temp); |
8db9d77b | 3837 | |
5eddb70b CW |
3838 | reg = FDI_RX_CTL(pipe); |
3839 | temp = I915_READ(reg); | |
8db9d77b ZW |
3840 | temp &= ~FDI_LINK_TRAIN_NONE; |
3841 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3842 | I915_WRITE(reg, temp); |
8db9d77b | 3843 | |
5eddb70b CW |
3844 | POSTING_READ(reg); |
3845 | udelay(150); | |
8db9d77b | 3846 | |
5eddb70b | 3847 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3848 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3849 | temp = I915_READ(reg); |
8db9d77b ZW |
3850 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3851 | ||
3852 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3853 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3854 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3855 | break; | |
3856 | } | |
8db9d77b | 3857 | } |
e1a44743 | 3858 | if (tries == 5) |
5eddb70b | 3859 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3860 | |
3861 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3862 | |
8db9d77b ZW |
3863 | } |
3864 | ||
0206e353 | 3865 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3866 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3867 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3868 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3869 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3870 | }; | |
3871 | ||
3872 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3873 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3874 | { | |
3875 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3876 | struct drm_i915_private *dev_priv = to_i915(dev); |
8db9d77b ZW |
3877 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3878 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3879 | i915_reg_t reg; |
3880 | u32 temp, i, retry; | |
8db9d77b | 3881 | |
e1a44743 AJ |
3882 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3883 | for train result */ | |
5eddb70b CW |
3884 | reg = FDI_RX_IMR(pipe); |
3885 | temp = I915_READ(reg); | |
e1a44743 AJ |
3886 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3887 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3888 | I915_WRITE(reg, temp); |
3889 | ||
3890 | POSTING_READ(reg); | |
e1a44743 AJ |
3891 | udelay(150); |
3892 | ||
8db9d77b | 3893 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3894 | reg = FDI_TX_CTL(pipe); |
3895 | temp = I915_READ(reg); | |
627eb5a3 | 3896 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3897 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3898 | temp &= ~FDI_LINK_TRAIN_NONE; |
3899 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3900 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3901 | /* SNB-B */ | |
3902 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3903 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3904 | |
d74cf324 DV |
3905 | I915_WRITE(FDI_RX_MISC(pipe), |
3906 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3907 | ||
5eddb70b CW |
3908 | reg = FDI_RX_CTL(pipe); |
3909 | temp = I915_READ(reg); | |
6e266956 | 3910 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3911 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3912 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3913 | } else { | |
3914 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3915 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3916 | } | |
5eddb70b CW |
3917 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3918 | ||
3919 | POSTING_READ(reg); | |
8db9d77b ZW |
3920 | udelay(150); |
3921 | ||
0206e353 | 3922 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3923 | reg = FDI_TX_CTL(pipe); |
3924 | temp = I915_READ(reg); | |
8db9d77b ZW |
3925 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3926 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3927 | I915_WRITE(reg, temp); |
3928 | ||
3929 | POSTING_READ(reg); | |
8db9d77b ZW |
3930 | udelay(500); |
3931 | ||
fa37d39e SP |
3932 | for (retry = 0; retry < 5; retry++) { |
3933 | reg = FDI_RX_IIR(pipe); | |
3934 | temp = I915_READ(reg); | |
3935 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3936 | if (temp & FDI_RX_BIT_LOCK) { | |
3937 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3938 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3939 | break; | |
3940 | } | |
3941 | udelay(50); | |
8db9d77b | 3942 | } |
fa37d39e SP |
3943 | if (retry < 5) |
3944 | break; | |
8db9d77b ZW |
3945 | } |
3946 | if (i == 4) | |
5eddb70b | 3947 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3948 | |
3949 | /* Train 2 */ | |
5eddb70b CW |
3950 | reg = FDI_TX_CTL(pipe); |
3951 | temp = I915_READ(reg); | |
8db9d77b ZW |
3952 | temp &= ~FDI_LINK_TRAIN_NONE; |
3953 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5db94019 | 3954 | if (IS_GEN6(dev_priv)) { |
8db9d77b ZW |
3955 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3956 | /* SNB-B */ | |
3957 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3958 | } | |
5eddb70b | 3959 | I915_WRITE(reg, temp); |
8db9d77b | 3960 | |
5eddb70b CW |
3961 | reg = FDI_RX_CTL(pipe); |
3962 | temp = I915_READ(reg); | |
6e266956 | 3963 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3964 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3965 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3966 | } else { | |
3967 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3968 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3969 | } | |
5eddb70b CW |
3970 | I915_WRITE(reg, temp); |
3971 | ||
3972 | POSTING_READ(reg); | |
8db9d77b ZW |
3973 | udelay(150); |
3974 | ||
0206e353 | 3975 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3976 | reg = FDI_TX_CTL(pipe); |
3977 | temp = I915_READ(reg); | |
8db9d77b ZW |
3978 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3979 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3980 | I915_WRITE(reg, temp); |
3981 | ||
3982 | POSTING_READ(reg); | |
8db9d77b ZW |
3983 | udelay(500); |
3984 | ||
fa37d39e SP |
3985 | for (retry = 0; retry < 5; retry++) { |
3986 | reg = FDI_RX_IIR(pipe); | |
3987 | temp = I915_READ(reg); | |
3988 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3989 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3990 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3991 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3992 | break; | |
3993 | } | |
3994 | udelay(50); | |
8db9d77b | 3995 | } |
fa37d39e SP |
3996 | if (retry < 5) |
3997 | break; | |
8db9d77b ZW |
3998 | } |
3999 | if (i == 4) | |
5eddb70b | 4000 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
4001 | |
4002 | DRM_DEBUG_KMS("FDI train done.\n"); | |
4003 | } | |
4004 | ||
357555c0 JB |
4005 | /* Manual link training for Ivy Bridge A0 parts */ |
4006 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
4007 | { | |
4008 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4009 | struct drm_i915_private *dev_priv = to_i915(dev); |
357555c0 JB |
4010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4011 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
4012 | i915_reg_t reg; |
4013 | u32 temp, i, j; | |
357555c0 JB |
4014 | |
4015 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
4016 | for train result */ | |
4017 | reg = FDI_RX_IMR(pipe); | |
4018 | temp = I915_READ(reg); | |
4019 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
4020 | temp &= ~FDI_RX_BIT_LOCK; | |
4021 | I915_WRITE(reg, temp); | |
4022 | ||
4023 | POSTING_READ(reg); | |
4024 | udelay(150); | |
4025 | ||
01a415fd DV |
4026 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
4027 | I915_READ(FDI_RX_IIR(pipe))); | |
4028 | ||
139ccd3f JB |
4029 | /* Try each vswing and preemphasis setting twice before moving on */ |
4030 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
4031 | /* disable first in case we need to retry */ | |
4032 | reg = FDI_TX_CTL(pipe); | |
4033 | temp = I915_READ(reg); | |
4034 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
4035 | temp &= ~FDI_TX_ENABLE; | |
4036 | I915_WRITE(reg, temp); | |
357555c0 | 4037 | |
139ccd3f JB |
4038 | reg = FDI_RX_CTL(pipe); |
4039 | temp = I915_READ(reg); | |
4040 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
4041 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4042 | temp &= ~FDI_RX_ENABLE; | |
4043 | I915_WRITE(reg, temp); | |
357555c0 | 4044 | |
139ccd3f | 4045 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
4046 | reg = FDI_TX_CTL(pipe); |
4047 | temp = I915_READ(reg); | |
139ccd3f | 4048 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 4049 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 4050 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 4051 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
4052 | temp |= snb_b_fdi_train_param[j/2]; |
4053 | temp |= FDI_COMPOSITE_SYNC; | |
4054 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 4055 | |
139ccd3f JB |
4056 | I915_WRITE(FDI_RX_MISC(pipe), |
4057 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 4058 | |
139ccd3f | 4059 | reg = FDI_RX_CTL(pipe); |
357555c0 | 4060 | temp = I915_READ(reg); |
139ccd3f JB |
4061 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
4062 | temp |= FDI_COMPOSITE_SYNC; | |
4063 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 4064 | |
139ccd3f JB |
4065 | POSTING_READ(reg); |
4066 | udelay(1); /* should be 0.5us */ | |
357555c0 | 4067 | |
139ccd3f JB |
4068 | for (i = 0; i < 4; i++) { |
4069 | reg = FDI_RX_IIR(pipe); | |
4070 | temp = I915_READ(reg); | |
4071 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4072 | |
139ccd3f JB |
4073 | if (temp & FDI_RX_BIT_LOCK || |
4074 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
4075 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
4076 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
4077 | i); | |
4078 | break; | |
4079 | } | |
4080 | udelay(1); /* should be 0.5us */ | |
4081 | } | |
4082 | if (i == 4) { | |
4083 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
4084 | continue; | |
4085 | } | |
357555c0 | 4086 | |
139ccd3f | 4087 | /* Train 2 */ |
357555c0 JB |
4088 | reg = FDI_TX_CTL(pipe); |
4089 | temp = I915_READ(reg); | |
139ccd3f JB |
4090 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
4091 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
4092 | I915_WRITE(reg, temp); | |
4093 | ||
4094 | reg = FDI_RX_CTL(pipe); | |
4095 | temp = I915_READ(reg); | |
4096 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4097 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
4098 | I915_WRITE(reg, temp); |
4099 | ||
4100 | POSTING_READ(reg); | |
139ccd3f | 4101 | udelay(2); /* should be 1.5us */ |
357555c0 | 4102 | |
139ccd3f JB |
4103 | for (i = 0; i < 4; i++) { |
4104 | reg = FDI_RX_IIR(pipe); | |
4105 | temp = I915_READ(reg); | |
4106 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4107 | |
139ccd3f JB |
4108 | if (temp & FDI_RX_SYMBOL_LOCK || |
4109 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
4110 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
4111 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
4112 | i); | |
4113 | goto train_done; | |
4114 | } | |
4115 | udelay(2); /* should be 1.5us */ | |
357555c0 | 4116 | } |
139ccd3f JB |
4117 | if (i == 4) |
4118 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 4119 | } |
357555c0 | 4120 | |
139ccd3f | 4121 | train_done: |
357555c0 JB |
4122 | DRM_DEBUG_KMS("FDI train done.\n"); |
4123 | } | |
4124 | ||
88cefb6c | 4125 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 4126 | { |
88cefb6c | 4127 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4128 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 4129 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4130 | i915_reg_t reg; |
4131 | u32 temp; | |
c64e311e | 4132 | |
c98e9dcf | 4133 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
4134 | reg = FDI_RX_CTL(pipe); |
4135 | temp = I915_READ(reg); | |
627eb5a3 | 4136 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 4137 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 4138 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
4139 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
4140 | ||
4141 | POSTING_READ(reg); | |
c98e9dcf JB |
4142 | udelay(200); |
4143 | ||
4144 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
4145 | temp = I915_READ(reg); |
4146 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
4147 | ||
4148 | POSTING_READ(reg); | |
c98e9dcf JB |
4149 | udelay(200); |
4150 | ||
20749730 PZ |
4151 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
4152 | reg = FDI_TX_CTL(pipe); | |
4153 | temp = I915_READ(reg); | |
4154 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
4155 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 4156 | |
20749730 PZ |
4157 | POSTING_READ(reg); |
4158 | udelay(100); | |
6be4a607 | 4159 | } |
0e23b99d JB |
4160 | } |
4161 | ||
88cefb6c DV |
4162 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
4163 | { | |
4164 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 4165 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 4166 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4167 | i915_reg_t reg; |
4168 | u32 temp; | |
88cefb6c DV |
4169 | |
4170 | /* Switch from PCDclk to Rawclk */ | |
4171 | reg = FDI_RX_CTL(pipe); | |
4172 | temp = I915_READ(reg); | |
4173 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
4174 | ||
4175 | /* Disable CPU FDI TX PLL */ | |
4176 | reg = FDI_TX_CTL(pipe); | |
4177 | temp = I915_READ(reg); | |
4178 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
4179 | ||
4180 | POSTING_READ(reg); | |
4181 | udelay(100); | |
4182 | ||
4183 | reg = FDI_RX_CTL(pipe); | |
4184 | temp = I915_READ(reg); | |
4185 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
4186 | ||
4187 | /* Wait for the clocks to turn off. */ | |
4188 | POSTING_READ(reg); | |
4189 | udelay(100); | |
4190 | } | |
4191 | ||
0fc932b8 JB |
4192 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
4193 | { | |
4194 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4195 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
4196 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4197 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
4198 | i915_reg_t reg; |
4199 | u32 temp; | |
0fc932b8 JB |
4200 | |
4201 | /* disable CPU FDI tx and PCH FDI rx */ | |
4202 | reg = FDI_TX_CTL(pipe); | |
4203 | temp = I915_READ(reg); | |
4204 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
4205 | POSTING_READ(reg); | |
4206 | ||
4207 | reg = FDI_RX_CTL(pipe); | |
4208 | temp = I915_READ(reg); | |
4209 | temp &= ~(0x7 << 16); | |
dfd07d72 | 4210 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4211 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
4212 | ||
4213 | POSTING_READ(reg); | |
4214 | udelay(100); | |
4215 | ||
4216 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6e266956 | 4217 | if (HAS_PCH_IBX(dev_priv)) |
6f06ce18 | 4218 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
4219 | |
4220 | /* still set train pattern 1 */ | |
4221 | reg = FDI_TX_CTL(pipe); | |
4222 | temp = I915_READ(reg); | |
4223 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4224 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4225 | I915_WRITE(reg, temp); | |
4226 | ||
4227 | reg = FDI_RX_CTL(pipe); | |
4228 | temp = I915_READ(reg); | |
6e266956 | 4229 | if (HAS_PCH_CPT(dev_priv)) { |
0fc932b8 JB |
4230 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4231 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
4232 | } else { | |
4233 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4234 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4235 | } | |
4236 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
4237 | temp &= ~(0x07 << 16); | |
dfd07d72 | 4238 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4239 | I915_WRITE(reg, temp); |
4240 | ||
4241 | POSTING_READ(reg); | |
4242 | udelay(100); | |
4243 | } | |
4244 | ||
5dce5b93 CW |
4245 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
4246 | { | |
0f0f74bc | 4247 | struct drm_i915_private *dev_priv = to_i915(dev); |
5dce5b93 CW |
4248 | struct intel_crtc *crtc; |
4249 | ||
4250 | /* Note that we don't need to be called with mode_config.lock here | |
4251 | * as our list of CRTC objects is static for the lifetime of the | |
4252 | * device and so cannot disappear as we iterate. Similarly, we can | |
4253 | * happily treat the predicates as racy, atomic checks as userspace | |
4254 | * cannot claim and pin a new fb without at least acquring the | |
4255 | * struct_mutex and so serialising with us. | |
4256 | */ | |
d3fcc808 | 4257 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
4258 | if (atomic_read(&crtc->unpin_work_count) == 0) |
4259 | continue; | |
4260 | ||
5a21b665 | 4261 | if (crtc->flip_work) |
0f0f74bc | 4262 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
5dce5b93 CW |
4263 | |
4264 | return true; | |
4265 | } | |
4266 | ||
4267 | return false; | |
4268 | } | |
4269 | ||
5a21b665 | 4270 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
d6bbafa1 CW |
4271 | { |
4272 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
5a21b665 DV |
4273 | struct intel_flip_work *work = intel_crtc->flip_work; |
4274 | ||
4275 | intel_crtc->flip_work = NULL; | |
d6bbafa1 CW |
4276 | |
4277 | if (work->event) | |
560ce1dc | 4278 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
d6bbafa1 CW |
4279 | |
4280 | drm_crtc_vblank_put(&intel_crtc->base); | |
4281 | ||
5a21b665 | 4282 | wake_up_all(&dev_priv->pending_flip_queue); |
143f73b3 | 4283 | queue_work(dev_priv->wq, &work->unpin_work); |
5a21b665 DV |
4284 | |
4285 | trace_i915_flip_complete(intel_crtc->plane, | |
4286 | work->pending_flip_obj); | |
d6bbafa1 CW |
4287 | } |
4288 | ||
5008e874 | 4289 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 4290 | { |
0f91128d | 4291 | struct drm_device *dev = crtc->dev; |
fac5e23e | 4292 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 | 4293 | long ret; |
e6c3a2a6 | 4294 | |
2c10d571 | 4295 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
4296 | |
4297 | ret = wait_event_interruptible_timeout( | |
4298 | dev_priv->pending_flip_queue, | |
4299 | !intel_crtc_has_pending_flip(crtc), | |
4300 | 60*HZ); | |
4301 | ||
4302 | if (ret < 0) | |
4303 | return ret; | |
4304 | ||
5a21b665 DV |
4305 | if (ret == 0) { |
4306 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4307 | struct intel_flip_work *work; | |
4308 | ||
4309 | spin_lock_irq(&dev->event_lock); | |
4310 | work = intel_crtc->flip_work; | |
4311 | if (work && !is_mmio_work(work)) { | |
4312 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
4313 | page_flip_completed(intel_crtc); | |
4314 | } | |
4315 | spin_unlock_irq(&dev->event_lock); | |
4316 | } | |
5bb61643 | 4317 | |
5008e874 | 4318 | return 0; |
e6c3a2a6 CW |
4319 | } |
4320 | ||
b7076546 | 4321 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
060f02d8 VS |
4322 | { |
4323 | u32 temp; | |
4324 | ||
4325 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4326 | ||
4327 | mutex_lock(&dev_priv->sb_lock); | |
4328 | ||
4329 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4330 | temp |= SBI_SSCCTL_DISABLE; | |
4331 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4332 | ||
4333 | mutex_unlock(&dev_priv->sb_lock); | |
4334 | } | |
4335 | ||
e615efe4 ED |
4336 | /* Program iCLKIP clock to the desired frequency */ |
4337 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
4338 | { | |
64b46a06 | 4339 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 4340 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
4341 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4342 | u32 temp; | |
4343 | ||
060f02d8 | 4344 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4345 | |
64b46a06 VS |
4346 | /* The iCLK virtual clock root frequency is in MHz, |
4347 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4348 | * divisors, it is necessary to divide one by another, so we | |
4349 | * convert the virtual clock precision to KHz here for higher | |
4350 | * precision. | |
4351 | */ | |
4352 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4353 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4354 | u32 iclk_pi_range = 64; | |
64b46a06 | 4355 | u32 desired_divisor; |
e615efe4 | 4356 | |
64b46a06 VS |
4357 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4358 | clock << auxdiv); | |
4359 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4360 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4361 | |
64b46a06 VS |
4362 | /* |
4363 | * Near 20MHz is a corner case which is | |
4364 | * out of range for the 7-bit divisor | |
4365 | */ | |
4366 | if (divsel <= 0x7f) | |
4367 | break; | |
e615efe4 ED |
4368 | } |
4369 | ||
4370 | /* This should not happen with any sane values */ | |
4371 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4372 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4373 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4374 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4375 | ||
4376 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4377 | clock, |
e615efe4 ED |
4378 | auxdiv, |
4379 | divsel, | |
4380 | phasedir, | |
4381 | phaseinc); | |
4382 | ||
060f02d8 VS |
4383 | mutex_lock(&dev_priv->sb_lock); |
4384 | ||
e615efe4 | 4385 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4386 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4387 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4388 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4389 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4390 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4391 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4392 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4393 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4394 | |
4395 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4396 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4397 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4398 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4399 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4400 | |
4401 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4402 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4403 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4404 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4405 | |
060f02d8 VS |
4406 | mutex_unlock(&dev_priv->sb_lock); |
4407 | ||
e615efe4 ED |
4408 | /* Wait for initialization time */ |
4409 | udelay(24); | |
4410 | ||
4411 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4412 | } | |
4413 | ||
8802e5b6 VS |
4414 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4415 | { | |
4416 | u32 divsel, phaseinc, auxdiv; | |
4417 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4418 | u32 iclk_pi_range = 64; | |
4419 | u32 desired_divisor; | |
4420 | u32 temp; | |
4421 | ||
4422 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4423 | return 0; | |
4424 | ||
4425 | mutex_lock(&dev_priv->sb_lock); | |
4426 | ||
4427 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4428 | if (temp & SBI_SSCCTL_DISABLE) { | |
4429 | mutex_unlock(&dev_priv->sb_lock); | |
4430 | return 0; | |
4431 | } | |
4432 | ||
4433 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4434 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4435 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4436 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4437 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4438 | ||
4439 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4440 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4441 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4442 | ||
4443 | mutex_unlock(&dev_priv->sb_lock); | |
4444 | ||
4445 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4446 | ||
4447 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4448 | desired_divisor << auxdiv); | |
4449 | } | |
4450 | ||
275f01b2 DV |
4451 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4452 | enum pipe pch_transcoder) | |
4453 | { | |
4454 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4455 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 4456 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4457 | |
4458 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4459 | I915_READ(HTOTAL(cpu_transcoder))); | |
4460 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4461 | I915_READ(HBLANK(cpu_transcoder))); | |
4462 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4463 | I915_READ(HSYNC(cpu_transcoder))); | |
4464 | ||
4465 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4466 | I915_READ(VTOTAL(cpu_transcoder))); | |
4467 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4468 | I915_READ(VBLANK(cpu_transcoder))); | |
4469 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4470 | I915_READ(VSYNC(cpu_transcoder))); | |
4471 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4472 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4473 | } | |
4474 | ||
003632d9 | 4475 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 4476 | { |
fac5e23e | 4477 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
4478 | uint32_t temp; |
4479 | ||
4480 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4481 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4482 | return; |
4483 | ||
4484 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4485 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4486 | ||
003632d9 ACO |
4487 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4488 | if (enable) | |
4489 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4490 | ||
4491 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4492 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4493 | POSTING_READ(SOUTH_CHICKEN1); | |
4494 | } | |
4495 | ||
4496 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4497 | { | |
4498 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4499 | |
4500 | switch (intel_crtc->pipe) { | |
4501 | case PIPE_A: | |
4502 | break; | |
4503 | case PIPE_B: | |
6e3c9717 | 4504 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4505 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4506 | else |
003632d9 | 4507 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4508 | |
4509 | break; | |
4510 | case PIPE_C: | |
003632d9 | 4511 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4512 | |
4513 | break; | |
4514 | default: | |
4515 | BUG(); | |
4516 | } | |
4517 | } | |
4518 | ||
c48b5305 VS |
4519 | /* Return which DP Port should be selected for Transcoder DP control */ |
4520 | static enum port | |
4521 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4522 | { | |
4523 | struct drm_device *dev = crtc->dev; | |
4524 | struct intel_encoder *encoder; | |
4525 | ||
4526 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
cca0502b | 4527 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4528 | encoder->type == INTEL_OUTPUT_EDP) |
4529 | return enc_to_dig_port(&encoder->base)->port; | |
4530 | } | |
4531 | ||
4532 | return -1; | |
4533 | } | |
4534 | ||
f67a559d JB |
4535 | /* |
4536 | * Enable PCH resources required for PCH ports: | |
4537 | * - PCH PLLs | |
4538 | * - FDI training & RX/TX | |
4539 | * - update transcoder timings | |
4540 | * - DP transcoding bits | |
4541 | * - transcoder | |
4542 | */ | |
4543 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4544 | { |
4545 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4546 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e23b99d JB |
4547 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4548 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4549 | u32 temp; |
2c07245f | 4550 | |
ab9412ba | 4551 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4552 | |
fd6b8f43 | 4553 | if (IS_IVYBRIDGE(dev_priv)) |
1fbc0d78 DV |
4554 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); |
4555 | ||
cd986abb DV |
4556 | /* Write the TU size bits before fdi link training, so that error |
4557 | * detection works. */ | |
4558 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4559 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4560 | ||
c98e9dcf | 4561 | /* For PCH output, training FDI link */ |
674cf967 | 4562 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4563 | |
3ad8a208 DV |
4564 | /* We need to program the right clock selection before writing the pixel |
4565 | * mutliplier into the DPLL. */ | |
6e266956 | 4566 | if (HAS_PCH_CPT(dev_priv)) { |
ee7b9f93 | 4567 | u32 sel; |
4b645f14 | 4568 | |
c98e9dcf | 4569 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4570 | temp |= TRANS_DPLL_ENABLE(pipe); |
4571 | sel = TRANS_DPLLB_SEL(pipe); | |
8106ddbd ACO |
4572 | if (intel_crtc->config->shared_dpll == |
4573 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) | |
ee7b9f93 JB |
4574 | temp |= sel; |
4575 | else | |
4576 | temp &= ~sel; | |
c98e9dcf | 4577 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4578 | } |
5eddb70b | 4579 | |
3ad8a208 DV |
4580 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4581 | * transcoder, and we actually should do this to not upset any PCH | |
4582 | * transcoder that already use the clock when we share it. | |
4583 | * | |
4584 | * Note that enable_shared_dpll tries to do the right thing, but | |
4585 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4586 | * the right LVDS enable sequence. */ | |
85b3894f | 4587 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4588 | |
d9b6cb56 JB |
4589 | /* set transcoder timing, panel must allow it */ |
4590 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4591 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4592 | |
303b81e0 | 4593 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4594 | |
c98e9dcf | 4595 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e266956 TU |
4596 | if (HAS_PCH_CPT(dev_priv) && |
4597 | intel_crtc_has_dp_encoder(intel_crtc->config)) { | |
9c4edaee VS |
4598 | const struct drm_display_mode *adjusted_mode = |
4599 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4600 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4601 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4602 | temp = I915_READ(reg); |
4603 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4604 | TRANS_DP_SYNC_MASK | |
4605 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4606 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4607 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4608 | |
9c4edaee | 4609 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4610 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4611 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4612 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4613 | |
4614 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4615 | case PORT_B: |
5eddb70b | 4616 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4617 | break; |
c48b5305 | 4618 | case PORT_C: |
5eddb70b | 4619 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4620 | break; |
c48b5305 | 4621 | case PORT_D: |
5eddb70b | 4622 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4623 | break; |
4624 | default: | |
e95d41e1 | 4625 | BUG(); |
32f9d658 | 4626 | } |
2c07245f | 4627 | |
5eddb70b | 4628 | I915_WRITE(reg, temp); |
6be4a607 | 4629 | } |
b52eb4dc | 4630 | |
b8a4f404 | 4631 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4632 | } |
4633 | ||
1507e5bd PZ |
4634 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4635 | { | |
4636 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4637 | struct drm_i915_private *dev_priv = to_i915(dev); |
1507e5bd | 4638 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 4639 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4640 | |
ab9412ba | 4641 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4642 | |
8c52b5e8 | 4643 | lpt_program_iclkip(crtc); |
1507e5bd | 4644 | |
0540e488 | 4645 | /* Set transcoder timing. */ |
275f01b2 | 4646 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4647 | |
937bb610 | 4648 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4649 | } |
4650 | ||
a1520318 | 4651 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4652 | { |
fac5e23e | 4653 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4654 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4655 | u32 temp; |
4656 | ||
4657 | temp = I915_READ(dslreg); | |
4658 | udelay(500); | |
4659 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4660 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4661 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4662 | } |
4663 | } | |
4664 | ||
86adf9d7 ML |
4665 | static int |
4666 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4667 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4668 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4669 | { |
86adf9d7 ML |
4670 | struct intel_crtc_scaler_state *scaler_state = |
4671 | &crtc_state->scaler_state; | |
4672 | struct intel_crtc *intel_crtc = | |
4673 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4674 | int need_scaling; |
6156a456 | 4675 | |
bd2ef25d | 4676 | need_scaling = drm_rotation_90_or_270(rotation) ? |
6156a456 CK |
4677 | (src_h != dst_w || src_w != dst_h): |
4678 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4679 | |
4680 | /* | |
4681 | * if plane is being disabled or scaler is no more required or force detach | |
4682 | * - free scaler binded to this plane/crtc | |
4683 | * - in order to do this, update crtc->scaler_usage | |
4684 | * | |
4685 | * Here scaler state in crtc_state is set free so that | |
4686 | * scaler can be assigned to other user. Actual register | |
4687 | * update to free the scaler is done in plane/panel-fit programming. | |
4688 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4689 | */ | |
86adf9d7 | 4690 | if (force_detach || !need_scaling) { |
a1b2278e | 4691 | if (*scaler_id >= 0) { |
86adf9d7 | 4692 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4693 | scaler_state->scalers[*scaler_id].in_use = 0; |
4694 | ||
86adf9d7 ML |
4695 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4696 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4697 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4698 | scaler_state->scaler_users); |
4699 | *scaler_id = -1; | |
4700 | } | |
4701 | return 0; | |
4702 | } | |
4703 | ||
4704 | /* range checks */ | |
4705 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4706 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4707 | ||
4708 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4709 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4710 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4711 | "size is out of scaler range\n", |
86adf9d7 | 4712 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4713 | return -EINVAL; |
4714 | } | |
4715 | ||
86adf9d7 ML |
4716 | /* mark this plane as a scaler user in crtc_state */ |
4717 | scaler_state->scaler_users |= (1 << scaler_user); | |
4718 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4719 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4720 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4721 | scaler_state->scaler_users); | |
4722 | ||
4723 | return 0; | |
4724 | } | |
4725 | ||
4726 | /** | |
4727 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4728 | * | |
4729 | * @state: crtc's scaler state | |
86adf9d7 ML |
4730 | * |
4731 | * Return | |
4732 | * 0 - scaler_usage updated successfully | |
4733 | * error - requested scaling cannot be supported or other error condition | |
4734 | */ | |
e435d6e5 | 4735 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4736 | { |
4737 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4738 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4739 | |
78108b7c VS |
4740 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n", |
4741 | intel_crtc->base.base.id, intel_crtc->base.name, | |
4742 | intel_crtc->pipe, SKL_CRTC_INDEX); | |
86adf9d7 | 4743 | |
e435d6e5 | 4744 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
31ad61e4 | 4745 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
86adf9d7 | 4746 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4747 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4748 | } |
4749 | ||
4750 | /** | |
4751 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4752 | * | |
4753 | * @state: crtc's scaler state | |
86adf9d7 ML |
4754 | * @plane_state: atomic plane state to update |
4755 | * | |
4756 | * Return | |
4757 | * 0 - scaler_usage updated successfully | |
4758 | * error - requested scaling cannot be supported or other error condition | |
4759 | */ | |
da20eabd ML |
4760 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4761 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4762 | { |
4763 | ||
4764 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4765 | struct intel_plane *intel_plane = |
4766 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4767 | struct drm_framebuffer *fb = plane_state->base.fb; |
4768 | int ret; | |
4769 | ||
936e71e3 | 4770 | bool force_detach = !fb || !plane_state->base.visible; |
86adf9d7 | 4771 | |
72660ce0 VS |
4772 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n", |
4773 | intel_plane->base.base.id, intel_plane->base.name, | |
4774 | intel_crtc->pipe, drm_plane_index(&intel_plane->base)); | |
86adf9d7 ML |
4775 | |
4776 | ret = skl_update_scaler(crtc_state, force_detach, | |
4777 | drm_plane_index(&intel_plane->base), | |
4778 | &plane_state->scaler_id, | |
4779 | plane_state->base.rotation, | |
936e71e3 VS |
4780 | drm_rect_width(&plane_state->base.src) >> 16, |
4781 | drm_rect_height(&plane_state->base.src) >> 16, | |
4782 | drm_rect_width(&plane_state->base.dst), | |
4783 | drm_rect_height(&plane_state->base.dst)); | |
86adf9d7 ML |
4784 | |
4785 | if (ret || plane_state->scaler_id < 0) | |
4786 | return ret; | |
4787 | ||
a1b2278e | 4788 | /* check colorkey */ |
818ed961 | 4789 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4790 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4791 | intel_plane->base.base.id, | |
4792 | intel_plane->base.name); | |
a1b2278e CK |
4793 | return -EINVAL; |
4794 | } | |
4795 | ||
4796 | /* Check src format */ | |
86adf9d7 ML |
4797 | switch (fb->pixel_format) { |
4798 | case DRM_FORMAT_RGB565: | |
4799 | case DRM_FORMAT_XBGR8888: | |
4800 | case DRM_FORMAT_XRGB8888: | |
4801 | case DRM_FORMAT_ABGR8888: | |
4802 | case DRM_FORMAT_ARGB8888: | |
4803 | case DRM_FORMAT_XRGB2101010: | |
4804 | case DRM_FORMAT_XBGR2101010: | |
4805 | case DRM_FORMAT_YUYV: | |
4806 | case DRM_FORMAT_YVYU: | |
4807 | case DRM_FORMAT_UYVY: | |
4808 | case DRM_FORMAT_VYUY: | |
4809 | break; | |
4810 | default: | |
72660ce0 VS |
4811 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4812 | intel_plane->base.base.id, intel_plane->base.name, | |
4813 | fb->base.id, fb->pixel_format); | |
86adf9d7 | 4814 | return -EINVAL; |
a1b2278e CK |
4815 | } |
4816 | ||
a1b2278e CK |
4817 | return 0; |
4818 | } | |
4819 | ||
e435d6e5 ML |
4820 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4821 | { | |
4822 | int i; | |
4823 | ||
4824 | for (i = 0; i < crtc->num_scalers; i++) | |
4825 | skl_detach_scaler(crtc, i); | |
4826 | } | |
4827 | ||
4828 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4829 | { |
4830 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4831 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4832 | int pipe = crtc->pipe; |
a1b2278e CK |
4833 | struct intel_crtc_scaler_state *scaler_state = |
4834 | &crtc->config->scaler_state; | |
4835 | ||
4836 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4837 | ||
6e3c9717 | 4838 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4839 | int id; |
4840 | ||
4841 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4842 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4843 | return; | |
4844 | } | |
4845 | ||
4846 | id = scaler_state->scaler_id; | |
4847 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4848 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4849 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4850 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4851 | ||
4852 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4853 | } |
4854 | } | |
4855 | ||
b074cec8 JB |
4856 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4857 | { | |
4858 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4859 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4860 | int pipe = crtc->pipe; |
4861 | ||
6e3c9717 | 4862 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4863 | /* Force use of hard-coded filter coefficients |
4864 | * as some pre-programmed values are broken, | |
4865 | * e.g. x201. | |
4866 | */ | |
fd6b8f43 | 4867 | if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) |
b074cec8 JB |
4868 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
4869 | PF_PIPE_SEL_IVB(pipe)); | |
4870 | else | |
4871 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4872 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4873 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4874 | } |
4875 | } | |
4876 | ||
20bc8673 | 4877 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4878 | { |
cea165c3 | 4879 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4880 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4881 | |
6e3c9717 | 4882 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4883 | return; |
4884 | ||
307e4498 ML |
4885 | /* |
4886 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4887 | * This function is called from post_plane_update, which is run after | |
4888 | * a vblank wait. | |
4889 | */ | |
cea165c3 | 4890 | |
d77e4531 | 4891 | assert_plane_enabled(dev_priv, crtc->plane); |
8652744b | 4892 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4893 | mutex_lock(&dev_priv->rps.hw_lock); |
4894 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4895 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4896 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4897 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4898 | * mailbox." Moreover, the mailbox may return a bogus state, |
4899 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4900 | */ |
4901 | } else { | |
4902 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4903 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4904 | * is essentially intel_wait_for_vblank. If we don't have this | |
4905 | * and don't wait for vblanks until the end of crtc_enable, then | |
4906 | * the HW state readout code will complain that the expected | |
4907 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4908 | if (intel_wait_for_register(dev_priv, |
4909 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4910 | 50)) | |
2a114cc1 BW |
4911 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4912 | } | |
d77e4531 PZ |
4913 | } |
4914 | ||
20bc8673 | 4915 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4916 | { |
4917 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4918 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4919 | |
6e3c9717 | 4920 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4921 | return; |
4922 | ||
4923 | assert_plane_enabled(dev_priv, crtc->plane); | |
8652744b | 4924 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4925 | mutex_lock(&dev_priv->rps.hw_lock); |
4926 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4927 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4928 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4929 | if (intel_wait_for_register(dev_priv, |
4930 | IPS_CTL, IPS_ENABLE, 0, | |
4931 | 42)) | |
23d0b130 | 4932 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4933 | } else { |
2a114cc1 | 4934 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4935 | POSTING_READ(IPS_CTL); |
4936 | } | |
d77e4531 PZ |
4937 | |
4938 | /* We need to wait for a vblank before we can disable the plane. */ | |
0f0f74bc | 4939 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
d77e4531 PZ |
4940 | } |
4941 | ||
7cac945f | 4942 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4943 | { |
7cac945f | 4944 | if (intel_crtc->overlay) { |
d3eedb1a | 4945 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4946 | struct drm_i915_private *dev_priv = to_i915(dev); |
d3eedb1a VS |
4947 | |
4948 | mutex_lock(&dev->struct_mutex); | |
4949 | dev_priv->mm.interruptible = false; | |
4950 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4951 | dev_priv->mm.interruptible = true; | |
4952 | mutex_unlock(&dev->struct_mutex); | |
4953 | } | |
4954 | ||
4955 | /* Let userspace switch the overlay on again. In most cases userspace | |
4956 | * has to recompute where to put it anyway. | |
4957 | */ | |
4958 | } | |
4959 | ||
87d4300a ML |
4960 | /** |
4961 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4962 | * @crtc: the CRTC whose primary plane was just enabled | |
4963 | * | |
4964 | * Performs potentially sleeping operations that must be done after the primary | |
4965 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4966 | * called due to an explicit primary plane update, or due to an implicit | |
4967 | * re-enable that is caused when a sprite plane is updated to no longer | |
4968 | * completely hide the primary plane. | |
4969 | */ | |
4970 | static void | |
4971 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4972 | { |
4973 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4974 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4975 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4976 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4977 | |
87d4300a ML |
4978 | /* |
4979 | * FIXME IPS should be fine as long as one plane is | |
4980 | * enabled, but in practice it seems to have problems | |
4981 | * when going from primary only to sprite only and vice | |
4982 | * versa. | |
4983 | */ | |
a5c4d7bc VS |
4984 | hsw_enable_ips(intel_crtc); |
4985 | ||
f99d7069 | 4986 | /* |
87d4300a ML |
4987 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4988 | * So don't enable underrun reporting before at least some planes | |
4989 | * are enabled. | |
4990 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4991 | * but leave the pipe running. | |
f99d7069 | 4992 | */ |
5db94019 | 4993 | if (IS_GEN2(dev_priv)) |
87d4300a ML |
4994 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4995 | ||
aca7b684 VS |
4996 | /* Underruns don't always raise interrupts, so check manually. */ |
4997 | intel_check_cpu_fifo_underruns(dev_priv); | |
4998 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4999 | } |
5000 | ||
2622a081 | 5001 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
5002 | static void |
5003 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
5004 | { |
5005 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5006 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
5007 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5008 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 5009 | |
87d4300a ML |
5010 | /* |
5011 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5012 | * So diasble underrun reporting before all the planes get disabled. | |
5013 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5014 | * but leave the pipe running. | |
5015 | */ | |
5db94019 | 5016 | if (IS_GEN2(dev_priv)) |
87d4300a | 5017 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
a5c4d7bc | 5018 | |
2622a081 VS |
5019 | /* |
5020 | * FIXME IPS should be fine as long as one plane is | |
5021 | * enabled, but in practice it seems to have problems | |
5022 | * when going from primary only to sprite only and vice | |
5023 | * versa. | |
5024 | */ | |
5025 | hsw_disable_ips(intel_crtc); | |
5026 | } | |
5027 | ||
5028 | /* FIXME get rid of this and use pre_plane_update */ | |
5029 | static void | |
5030 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
5031 | { | |
5032 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5033 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
5034 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5035 | int pipe = intel_crtc->pipe; | |
5036 | ||
5037 | intel_pre_disable_primary(crtc); | |
5038 | ||
87d4300a ML |
5039 | /* |
5040 | * Vblank time updates from the shadow to live plane control register | |
5041 | * are blocked if the memory self-refresh mode is active at that | |
5042 | * moment. So to make sure the plane gets truly disabled, disable | |
5043 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5044 | * will be checked/applied by the HW only at the next frame start | |
5045 | * event which is after the vblank start event, so we need to have a | |
5046 | * wait-for-vblank between disabling the plane and the pipe. | |
5047 | */ | |
49cff963 | 5048 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
87d4300a | 5049 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 | 5050 | dev_priv->wm.vlv.cxsr = false; |
0f0f74bc | 5051 | intel_wait_for_vblank(dev_priv, pipe); |
262cd2e1 | 5052 | } |
87d4300a ML |
5053 | } |
5054 | ||
5a21b665 DV |
5055 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
5056 | { | |
5057 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
5058 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
5059 | struct intel_crtc_state *pipe_config = | |
5060 | to_intel_crtc_state(crtc->base.state); | |
5a21b665 DV |
5061 | struct drm_plane *primary = crtc->base.primary; |
5062 | struct drm_plane_state *old_pri_state = | |
5063 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5064 | ||
5748b6a1 | 5065 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
5a21b665 DV |
5066 | |
5067 | crtc->wm.cxsr_allowed = true; | |
5068 | ||
5069 | if (pipe_config->update_wm_post && pipe_config->base.active) | |
432081bc | 5070 | intel_update_watermarks(crtc); |
5a21b665 DV |
5071 | |
5072 | if (old_pri_state) { | |
5073 | struct intel_plane_state *primary_state = | |
5074 | to_intel_plane_state(primary->state); | |
5075 | struct intel_plane_state *old_primary_state = | |
5076 | to_intel_plane_state(old_pri_state); | |
5077 | ||
5078 | intel_fbc_post_update(crtc); | |
5079 | ||
936e71e3 | 5080 | if (primary_state->base.visible && |
5a21b665 | 5081 | (needs_modeset(&pipe_config->base) || |
936e71e3 | 5082 | !old_primary_state->base.visible)) |
5a21b665 DV |
5083 | intel_post_enable_primary(&crtc->base); |
5084 | } | |
5085 | } | |
5086 | ||
5c74cd73 | 5087 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 5088 | { |
5c74cd73 | 5089 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 5090 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5091 | struct drm_i915_private *dev_priv = to_i915(dev); |
ab1d3a0e ML |
5092 | struct intel_crtc_state *pipe_config = |
5093 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
5094 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
5095 | struct drm_plane *primary = crtc->base.primary; | |
5096 | struct drm_plane_state *old_pri_state = | |
5097 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5098 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 5099 | |
5c74cd73 ML |
5100 | if (old_pri_state) { |
5101 | struct intel_plane_state *primary_state = | |
5102 | to_intel_plane_state(primary->state); | |
5103 | struct intel_plane_state *old_primary_state = | |
5104 | to_intel_plane_state(old_pri_state); | |
5105 | ||
faf68d92 | 5106 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 5107 | |
936e71e3 VS |
5108 | if (old_primary_state->base.visible && |
5109 | (modeset || !primary_state->base.visible)) | |
5c74cd73 ML |
5110 | intel_pre_disable_primary(&crtc->base); |
5111 | } | |
852eb00d | 5112 | |
49cff963 | 5113 | if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) { |
852eb00d | 5114 | crtc->wm.cxsr_allowed = false; |
2dfd178d | 5115 | |
2622a081 VS |
5116 | /* |
5117 | * Vblank time updates from the shadow to live plane control register | |
5118 | * are blocked if the memory self-refresh mode is active at that | |
5119 | * moment. So to make sure the plane gets truly disabled, disable | |
5120 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5121 | * will be checked/applied by the HW only at the next frame start | |
5122 | * event which is after the vblank start event, so we need to have a | |
5123 | * wait-for-vblank between disabling the plane and the pipe. | |
5124 | */ | |
5125 | if (old_crtc_state->base.active) { | |
2dfd178d | 5126 | intel_set_memory_cxsr(dev_priv, false); |
2622a081 | 5127 | dev_priv->wm.vlv.cxsr = false; |
0f0f74bc | 5128 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
2622a081 | 5129 | } |
852eb00d | 5130 | } |
92826fcd | 5131 | |
ed4a6a7c MR |
5132 | /* |
5133 | * IVB workaround: must disable low power watermarks for at least | |
5134 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
5135 | * when scaling is disabled. | |
5136 | * | |
5137 | * WaCxSRDisabledForSpriteScaling:ivb | |
5138 | */ | |
5139 | if (pipe_config->disable_lp_wm) { | |
5140 | ilk_disable_lp_wm(dev); | |
0f0f74bc | 5141 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
ed4a6a7c MR |
5142 | } |
5143 | ||
5144 | /* | |
5145 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
5146 | * watermark programming here. | |
5147 | */ | |
5148 | if (needs_modeset(&pipe_config->base)) | |
5149 | return; | |
5150 | ||
5151 | /* | |
5152 | * For platforms that support atomic watermarks, program the | |
5153 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
5154 | * will be the intermediate values that are safe for both pre- and | |
5155 | * post- vblank; when vblank happens, the 'active' values will be set | |
5156 | * to the final 'target' values and we'll do this again to get the | |
5157 | * optimal watermarks. For gen9+ platforms, the values we program here | |
5158 | * will be the final target values which will get automatically latched | |
5159 | * at vblank time; no further programming will be necessary. | |
5160 | * | |
5161 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
5162 | * we'll continue to update watermarks the old way, if flags tell | |
5163 | * us to. | |
5164 | */ | |
5165 | if (dev_priv->display.initial_watermarks != NULL) | |
5166 | dev_priv->display.initial_watermarks(pipe_config); | |
caed361d | 5167 | else if (pipe_config->update_wm_pre) |
432081bc | 5168 | intel_update_watermarks(crtc); |
ac21b225 ML |
5169 | } |
5170 | ||
d032ffa0 | 5171 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
5172 | { |
5173 | struct drm_device *dev = crtc->dev; | |
5174 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 5175 | struct drm_plane *p; |
87d4300a ML |
5176 | int pipe = intel_crtc->pipe; |
5177 | ||
7cac945f | 5178 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 5179 | |
d032ffa0 ML |
5180 | drm_for_each_plane_mask(p, dev, plane_mask) |
5181 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 5182 | |
f99d7069 DV |
5183 | /* |
5184 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
5185 | * to compute the mask of flip planes precisely. For the time being | |
5186 | * consider this a flip to a NULL plane. | |
5187 | */ | |
5748b6a1 | 5188 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
a5c4d7bc VS |
5189 | } |
5190 | ||
fb1c98b1 | 5191 | static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc, |
fd6bbda9 | 5192 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5193 | struct drm_atomic_state *old_state) |
5194 | { | |
5195 | struct drm_connector_state *old_conn_state; | |
5196 | struct drm_connector *conn; | |
5197 | int i; | |
5198 | ||
5199 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5200 | struct drm_connector_state *conn_state = conn->state; | |
5201 | struct intel_encoder *encoder = | |
5202 | to_intel_encoder(conn_state->best_encoder); | |
5203 | ||
5204 | if (conn_state->crtc != crtc) | |
5205 | continue; | |
5206 | ||
5207 | if (encoder->pre_pll_enable) | |
fd6bbda9 | 5208 | encoder->pre_pll_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5209 | } |
5210 | } | |
5211 | ||
5212 | static void intel_encoders_pre_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5213 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5214 | struct drm_atomic_state *old_state) |
5215 | { | |
5216 | struct drm_connector_state *old_conn_state; | |
5217 | struct drm_connector *conn; | |
5218 | int i; | |
5219 | ||
5220 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5221 | struct drm_connector_state *conn_state = conn->state; | |
5222 | struct intel_encoder *encoder = | |
5223 | to_intel_encoder(conn_state->best_encoder); | |
5224 | ||
5225 | if (conn_state->crtc != crtc) | |
5226 | continue; | |
5227 | ||
5228 | if (encoder->pre_enable) | |
fd6bbda9 | 5229 | encoder->pre_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5230 | } |
5231 | } | |
5232 | ||
5233 | static void intel_encoders_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5234 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5235 | struct drm_atomic_state *old_state) |
5236 | { | |
5237 | struct drm_connector_state *old_conn_state; | |
5238 | struct drm_connector *conn; | |
5239 | int i; | |
5240 | ||
5241 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5242 | struct drm_connector_state *conn_state = conn->state; | |
5243 | struct intel_encoder *encoder = | |
5244 | to_intel_encoder(conn_state->best_encoder); | |
5245 | ||
5246 | if (conn_state->crtc != crtc) | |
5247 | continue; | |
5248 | ||
fd6bbda9 | 5249 | encoder->enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5250 | intel_opregion_notify_encoder(encoder, true); |
5251 | } | |
5252 | } | |
5253 | ||
5254 | static void intel_encoders_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5255 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5256 | struct drm_atomic_state *old_state) |
5257 | { | |
5258 | struct drm_connector_state *old_conn_state; | |
5259 | struct drm_connector *conn; | |
5260 | int i; | |
5261 | ||
5262 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5263 | struct intel_encoder *encoder = | |
5264 | to_intel_encoder(old_conn_state->best_encoder); | |
5265 | ||
5266 | if (old_conn_state->crtc != crtc) | |
5267 | continue; | |
5268 | ||
5269 | intel_opregion_notify_encoder(encoder, false); | |
fd6bbda9 | 5270 | encoder->disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5271 | } |
5272 | } | |
5273 | ||
5274 | static void intel_encoders_post_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5275 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5276 | struct drm_atomic_state *old_state) |
5277 | { | |
5278 | struct drm_connector_state *old_conn_state; | |
5279 | struct drm_connector *conn; | |
5280 | int i; | |
5281 | ||
5282 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5283 | struct intel_encoder *encoder = | |
5284 | to_intel_encoder(old_conn_state->best_encoder); | |
5285 | ||
5286 | if (old_conn_state->crtc != crtc) | |
5287 | continue; | |
5288 | ||
5289 | if (encoder->post_disable) | |
fd6bbda9 | 5290 | encoder->post_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5291 | } |
5292 | } | |
5293 | ||
5294 | static void intel_encoders_post_pll_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5295 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5296 | struct drm_atomic_state *old_state) |
5297 | { | |
5298 | struct drm_connector_state *old_conn_state; | |
5299 | struct drm_connector *conn; | |
5300 | int i; | |
5301 | ||
5302 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5303 | struct intel_encoder *encoder = | |
5304 | to_intel_encoder(old_conn_state->best_encoder); | |
5305 | ||
5306 | if (old_conn_state->crtc != crtc) | |
5307 | continue; | |
5308 | ||
5309 | if (encoder->post_pll_disable) | |
fd6bbda9 | 5310 | encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5311 | } |
5312 | } | |
5313 | ||
4a806558 ML |
5314 | static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, |
5315 | struct drm_atomic_state *old_state) | |
f67a559d | 5316 | { |
4a806558 | 5317 | struct drm_crtc *crtc = pipe_config->base.crtc; |
f67a559d | 5318 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5319 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d JB |
5320 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5321 | int pipe = intel_crtc->pipe; | |
f67a559d | 5322 | |
53d9f4e9 | 5323 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
5324 | return; |
5325 | ||
b2c0593a VS |
5326 | /* |
5327 | * Sometimes spurious CPU pipe underruns happen during FDI | |
5328 | * training, at least with VGA+HDMI cloning. Suppress them. | |
5329 | * | |
5330 | * On ILK we get an occasional spurious CPU pipe underruns | |
5331 | * between eDP port A enable and vdd enable. Also PCH port | |
5332 | * enable seems to result in the occasional CPU pipe underrun. | |
5333 | * | |
5334 | * Spurious PCH underruns also occur during PCH enabling. | |
5335 | */ | |
5336 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
5337 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
5338 | if (intel_crtc->config->has_pch_encoder) |
5339 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5340 | ||
6e3c9717 | 5341 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
5342 | intel_prepare_shared_dpll(intel_crtc); |
5343 | ||
37a5650b | 5344 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5345 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
5346 | |
5347 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 5348 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 5349 | |
6e3c9717 | 5350 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 5351 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5352 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
5353 | } |
5354 | ||
5355 | ironlake_set_pipeconf(crtc); | |
5356 | ||
f67a559d | 5357 | intel_crtc->active = true; |
8664281b | 5358 | |
fd6bbda9 | 5359 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f67a559d | 5360 | |
6e3c9717 | 5361 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
5362 | /* Note: FDI PLL enabling _must_ be done before we enable the |
5363 | * cpu pipes, hence this is separate from all the other fdi/pch | |
5364 | * enabling. */ | |
88cefb6c | 5365 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
5366 | } else { |
5367 | assert_fdi_tx_disabled(dev_priv, pipe); | |
5368 | assert_fdi_rx_disabled(dev_priv, pipe); | |
5369 | } | |
f67a559d | 5370 | |
b074cec8 | 5371 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 5372 | |
9c54c0dd JB |
5373 | /* |
5374 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5375 | * clocks enabled | |
5376 | */ | |
b95c5321 | 5377 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 5378 | |
1d5bf5d9 ID |
5379 | if (dev_priv->display.initial_watermarks != NULL) |
5380 | dev_priv->display.initial_watermarks(intel_crtc->config); | |
e1fdc473 | 5381 | intel_enable_pipe(intel_crtc); |
f67a559d | 5382 | |
6e3c9717 | 5383 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 5384 | ironlake_pch_enable(crtc); |
c98e9dcf | 5385 | |
f9b61ff6 DV |
5386 | assert_vblank_disabled(crtc); |
5387 | drm_crtc_vblank_on(crtc); | |
5388 | ||
fd6bbda9 | 5389 | intel_encoders_enable(crtc, pipe_config, old_state); |
61b77ddd | 5390 | |
6e266956 | 5391 | if (HAS_PCH_CPT(dev_priv)) |
a1520318 | 5392 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5393 | |
5394 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5395 | if (intel_crtc->config->has_pch_encoder) | |
0f0f74bc | 5396 | intel_wait_for_vblank(dev_priv, pipe); |
b2c0593a | 5397 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 5398 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
5399 | } |
5400 | ||
42db64ef PZ |
5401 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5402 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5403 | { | |
50a0bc90 | 5404 | return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5405 | } |
5406 | ||
4a806558 ML |
5407 | static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, |
5408 | struct drm_atomic_state *old_state) | |
4f771f10 | 5409 | { |
4a806558 | 5410 | struct drm_crtc *crtc = pipe_config->base.crtc; |
4f771f10 | 5411 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5412 | struct drm_i915_private *dev_priv = to_i915(dev); |
4f771f10 | 5413 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
99d736a2 | 5414 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 5415 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
4f771f10 | 5416 | |
53d9f4e9 | 5417 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5418 | return; |
5419 | ||
81b088ca VS |
5420 | if (intel_crtc->config->has_pch_encoder) |
5421 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5422 | false); | |
5423 | ||
fd6bbda9 | 5424 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
95a7a2ae | 5425 | |
8106ddbd | 5426 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
5427 | intel_enable_shared_dpll(intel_crtc); |
5428 | ||
37a5650b | 5429 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5430 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 5431 | |
d7edc4e5 | 5432 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5433 | intel_set_pipe_timings(intel_crtc); |
5434 | ||
bc58be60 | 5435 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 5436 | |
4d1de975 JN |
5437 | if (cpu_transcoder != TRANSCODER_EDP && |
5438 | !transcoder_is_dsi(cpu_transcoder)) { | |
5439 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 5440 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
5441 | } |
5442 | ||
6e3c9717 | 5443 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5444 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5445 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5446 | } |
5447 | ||
d7edc4e5 | 5448 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5449 | haswell_set_pipeconf(crtc); |
5450 | ||
391bf048 | 5451 | haswell_set_pipemisc(crtc); |
229fca97 | 5452 | |
b95c5321 | 5453 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 5454 | |
4f771f10 | 5455 | intel_crtc->active = true; |
8664281b | 5456 | |
6b698516 DV |
5457 | if (intel_crtc->config->has_pch_encoder) |
5458 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5459 | else | |
5460 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5461 | ||
fd6bbda9 | 5462 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
4f771f10 | 5463 | |
d2d65408 | 5464 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 5465 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 5466 | |
d7edc4e5 | 5467 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5468 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5469 | |
1c132b44 | 5470 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5471 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5472 | else |
1c132b44 | 5473 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5474 | |
5475 | /* | |
5476 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5477 | * clocks enabled | |
5478 | */ | |
b95c5321 | 5479 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 5480 | |
1f544388 | 5481 | intel_ddi_set_pipe_settings(crtc); |
d7edc4e5 | 5482 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5483 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5484 | |
1d5bf5d9 ID |
5485 | if (dev_priv->display.initial_watermarks != NULL) |
5486 | dev_priv->display.initial_watermarks(pipe_config); | |
5487 | else | |
432081bc | 5488 | intel_update_watermarks(intel_crtc); |
4d1de975 JN |
5489 | |
5490 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 5491 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5492 | intel_enable_pipe(intel_crtc); |
42db64ef | 5493 | |
6e3c9717 | 5494 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5495 | lpt_pch_enable(crtc); |
4f771f10 | 5496 | |
a65347ba | 5497 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5498 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5499 | ||
f9b61ff6 DV |
5500 | assert_vblank_disabled(crtc); |
5501 | drm_crtc_vblank_on(crtc); | |
5502 | ||
fd6bbda9 | 5503 | intel_encoders_enable(crtc, pipe_config, old_state); |
4f771f10 | 5504 | |
6b698516 | 5505 | if (intel_crtc->config->has_pch_encoder) { |
0f0f74bc VS |
5506 | intel_wait_for_vblank(dev_priv, pipe); |
5507 | intel_wait_for_vblank(dev_priv, pipe); | |
6b698516 | 5508 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
d2d65408 VS |
5509 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5510 | true); | |
6b698516 | 5511 | } |
d2d65408 | 5512 | |
e4916946 PZ |
5513 | /* If we change the relative order between pipe/planes enabling, we need |
5514 | * to change the workaround. */ | |
99d736a2 | 5515 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
772c2a51 | 5516 | if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { |
0f0f74bc VS |
5517 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); |
5518 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); | |
99d736a2 | 5519 | } |
4f771f10 PZ |
5520 | } |
5521 | ||
bfd16b2a | 5522 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5523 | { |
5524 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5525 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
5526 | int pipe = crtc->pipe; |
5527 | ||
5528 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5529 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5530 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5531 | I915_WRITE(PF_CTL(pipe), 0); |
5532 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5533 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5534 | } | |
5535 | } | |
5536 | ||
4a806558 ML |
5537 | static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5538 | struct drm_atomic_state *old_state) | |
6be4a607 | 5539 | { |
4a806558 | 5540 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6be4a607 | 5541 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5542 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 JB |
5543 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5544 | int pipe = intel_crtc->pipe; | |
b52eb4dc | 5545 | |
b2c0593a VS |
5546 | /* |
5547 | * Sometimes spurious CPU pipe underruns happen when the | |
5548 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5549 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5550 | */ | |
5551 | if (intel_crtc->config->has_pch_encoder) { | |
5552 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 5553 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 5554 | } |
37ca8d4c | 5555 | |
fd6bbda9 | 5556 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
ea9d758d | 5557 | |
f9b61ff6 DV |
5558 | drm_crtc_vblank_off(crtc); |
5559 | assert_vblank_disabled(crtc); | |
5560 | ||
575f7ab7 | 5561 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5562 | |
bfd16b2a | 5563 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5564 | |
b2c0593a | 5565 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5566 | ironlake_fdi_disable(crtc); |
5567 | ||
fd6bbda9 | 5568 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
2c07245f | 5569 | |
6e3c9717 | 5570 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5571 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5572 | |
6e266956 | 5573 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 VS |
5574 | i915_reg_t reg; |
5575 | u32 temp; | |
5576 | ||
d925c59a DV |
5577 | /* disable TRANS_DP_CTL */ |
5578 | reg = TRANS_DP_CTL(pipe); | |
5579 | temp = I915_READ(reg); | |
5580 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5581 | TRANS_DP_PORT_SEL_MASK); | |
5582 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5583 | I915_WRITE(reg, temp); | |
5584 | ||
5585 | /* disable DPLL_SEL */ | |
5586 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5587 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5588 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5589 | } |
e3421a18 | 5590 | |
d925c59a DV |
5591 | ironlake_fdi_pll_disable(intel_crtc); |
5592 | } | |
81b088ca | 5593 | |
b2c0593a | 5594 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5595 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5596 | } |
1b3c7a47 | 5597 | |
4a806558 ML |
5598 | static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5599 | struct drm_atomic_state *old_state) | |
ee7b9f93 | 5600 | { |
4a806558 | 5601 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
4f771f10 | 5602 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5603 | struct drm_i915_private *dev_priv = to_i915(dev); |
ee7b9f93 | 5604 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 5605 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5606 | |
d2d65408 VS |
5607 | if (intel_crtc->config->has_pch_encoder) |
5608 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5609 | false); | |
5610 | ||
fd6bbda9 | 5611 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4f771f10 | 5612 | |
f9b61ff6 DV |
5613 | drm_crtc_vblank_off(crtc); |
5614 | assert_vblank_disabled(crtc); | |
5615 | ||
4d1de975 | 5616 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5617 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5618 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5619 | |
6e3c9717 | 5620 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5621 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5622 | ||
d7edc4e5 | 5623 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5624 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5625 | |
1c132b44 | 5626 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5627 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5628 | else |
bfd16b2a | 5629 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5630 | |
d7edc4e5 | 5631 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5632 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5633 | |
fd6bbda9 | 5634 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
81b088ca | 5635 | |
b7076546 | 5636 | if (old_crtc_state->has_pch_encoder) |
81b088ca VS |
5637 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5638 | true); | |
4f771f10 PZ |
5639 | } |
5640 | ||
2dd24552 JB |
5641 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5642 | { | |
5643 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5644 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5645 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5646 | |
681a8504 | 5647 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5648 | return; |
5649 | ||
2dd24552 | 5650 | /* |
c0b03411 DV |
5651 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5652 | * according to register description and PRM. | |
2dd24552 | 5653 | */ |
c0b03411 DV |
5654 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5655 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5656 | |
b074cec8 JB |
5657 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5658 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5659 | |
5660 | /* Border color in case we don't scale up to the full screen. Black by | |
5661 | * default, change to something else for debugging. */ | |
5662 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5663 | } |
5664 | ||
d05410f9 DA |
5665 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5666 | { | |
5667 | switch (port) { | |
5668 | case PORT_A: | |
6331a704 | 5669 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5670 | case PORT_B: |
6331a704 | 5671 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5672 | case PORT_C: |
6331a704 | 5673 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5674 | case PORT_D: |
6331a704 | 5675 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5676 | case PORT_E: |
6331a704 | 5677 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5678 | default: |
b9fec167 | 5679 | MISSING_CASE(port); |
d05410f9 DA |
5680 | return POWER_DOMAIN_PORT_OTHER; |
5681 | } | |
5682 | } | |
5683 | ||
25f78f58 VS |
5684 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5685 | { | |
5686 | switch (port) { | |
5687 | case PORT_A: | |
5688 | return POWER_DOMAIN_AUX_A; | |
5689 | case PORT_B: | |
5690 | return POWER_DOMAIN_AUX_B; | |
5691 | case PORT_C: | |
5692 | return POWER_DOMAIN_AUX_C; | |
5693 | case PORT_D: | |
5694 | return POWER_DOMAIN_AUX_D; | |
5695 | case PORT_E: | |
5696 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5697 | return POWER_DOMAIN_AUX_D; | |
5698 | default: | |
b9fec167 | 5699 | MISSING_CASE(port); |
25f78f58 VS |
5700 | return POWER_DOMAIN_AUX_A; |
5701 | } | |
5702 | } | |
5703 | ||
319be8ae ID |
5704 | enum intel_display_power_domain |
5705 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5706 | { | |
4f8036a2 | 5707 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
319be8ae ID |
5708 | struct intel_digital_port *intel_dig_port; |
5709 | ||
5710 | switch (intel_encoder->type) { | |
5711 | case INTEL_OUTPUT_UNKNOWN: | |
5712 | /* Only DDI platforms should ever use this output type */ | |
4f8036a2 | 5713 | WARN_ON_ONCE(!HAS_DDI(dev_priv)); |
cca0502b | 5714 | case INTEL_OUTPUT_DP: |
319be8ae ID |
5715 | case INTEL_OUTPUT_HDMI: |
5716 | case INTEL_OUTPUT_EDP: | |
5717 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5718 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5719 | case INTEL_OUTPUT_DP_MST: |
5720 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5721 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5722 | case INTEL_OUTPUT_ANALOG: |
5723 | return POWER_DOMAIN_PORT_CRT; | |
5724 | case INTEL_OUTPUT_DSI: | |
5725 | return POWER_DOMAIN_PORT_DSI; | |
5726 | default: | |
5727 | return POWER_DOMAIN_PORT_OTHER; | |
5728 | } | |
5729 | } | |
5730 | ||
25f78f58 VS |
5731 | enum intel_display_power_domain |
5732 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5733 | { | |
4f8036a2 | 5734 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
25f78f58 VS |
5735 | struct intel_digital_port *intel_dig_port; |
5736 | ||
5737 | switch (intel_encoder->type) { | |
5738 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5739 | case INTEL_OUTPUT_HDMI: |
5740 | /* | |
5741 | * Only DDI platforms should ever use these output types. | |
5742 | * We can get here after the HDMI detect code has already set | |
5743 | * the type of the shared encoder. Since we can't be sure | |
5744 | * what's the status of the given connectors, play safe and | |
5745 | * run the DP detection too. | |
5746 | */ | |
4f8036a2 | 5747 | WARN_ON_ONCE(!HAS_DDI(dev_priv)); |
cca0502b | 5748 | case INTEL_OUTPUT_DP: |
25f78f58 VS |
5749 | case INTEL_OUTPUT_EDP: |
5750 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5751 | return port_to_aux_power_domain(intel_dig_port->port); | |
5752 | case INTEL_OUTPUT_DP_MST: | |
5753 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5754 | return port_to_aux_power_domain(intel_dig_port->port); | |
5755 | default: | |
b9fec167 | 5756 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5757 | return POWER_DOMAIN_AUX_A; |
5758 | } | |
5759 | } | |
5760 | ||
74bff5f9 ML |
5761 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5762 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5763 | { |
319be8ae | 5764 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5765 | struct drm_encoder *encoder; |
319be8ae ID |
5766 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5767 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5768 | unsigned long mask; |
74bff5f9 | 5769 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5770 | |
74bff5f9 | 5771 | if (!crtc_state->base.active) |
292b990e ML |
5772 | return 0; |
5773 | ||
77d22dca ID |
5774 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5775 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5776 | if (crtc_state->pch_pfit.enabled || |
5777 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5778 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5779 | ||
74bff5f9 ML |
5780 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5781 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5782 | ||
319be8ae | 5783 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5784 | } |
319be8ae | 5785 | |
15e7ec29 ML |
5786 | if (crtc_state->shared_dpll) |
5787 | mask |= BIT(POWER_DOMAIN_PLLS); | |
5788 | ||
77d22dca ID |
5789 | return mask; |
5790 | } | |
5791 | ||
74bff5f9 ML |
5792 | static unsigned long |
5793 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5794 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5795 | { |
fac5e23e | 5796 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5797 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5798 | enum intel_display_power_domain domain; | |
5a21b665 | 5799 | unsigned long domains, new_domains, old_domains; |
77d22dca | 5800 | |
292b990e | 5801 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5802 | intel_crtc->enabled_power_domains = new_domains = |
5803 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5804 | |
5a21b665 | 5805 | domains = new_domains & ~old_domains; |
292b990e ML |
5806 | |
5807 | for_each_power_domain(domain, domains) | |
5808 | intel_display_power_get(dev_priv, domain); | |
5809 | ||
5a21b665 | 5810 | return old_domains & ~new_domains; |
292b990e ML |
5811 | } |
5812 | ||
5813 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5814 | unsigned long domains) | |
5815 | { | |
5816 | enum intel_display_power_domain domain; | |
5817 | ||
5818 | for_each_power_domain(domain, domains) | |
5819 | intel_display_power_put(dev_priv, domain); | |
5820 | } | |
77d22dca | 5821 | |
adafdc6f MK |
5822 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5823 | { | |
5824 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5825 | ||
5826 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5827 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5828 | return max_cdclk_freq; | |
5829 | else if (IS_CHERRYVIEW(dev_priv)) | |
5830 | return max_cdclk_freq*95/100; | |
5831 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5832 | return 2*max_cdclk_freq*90/100; | |
5833 | else | |
5834 | return max_cdclk_freq*90/100; | |
5835 | } | |
5836 | ||
b2045352 VS |
5837 | static int skl_calc_cdclk(int max_pixclk, int vco); |
5838 | ||
4c75b940 | 5839 | static void intel_update_max_cdclk(struct drm_i915_private *dev_priv) |
560a7ae4 | 5840 | { |
0853723b | 5841 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
560a7ae4 | 5842 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
b2045352 VS |
5843 | int max_cdclk, vco; |
5844 | ||
5845 | vco = dev_priv->skl_preferred_vco_freq; | |
63911d72 | 5846 | WARN_ON(vco != 8100000 && vco != 8640000); |
560a7ae4 | 5847 | |
b2045352 VS |
5848 | /* |
5849 | * Use the lower (vco 8640) cdclk values as a | |
5850 | * first guess. skl_calc_cdclk() will correct it | |
5851 | * if the preferred vco is 8100 instead. | |
5852 | */ | |
560a7ae4 | 5853 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) |
487ed2e4 | 5854 | max_cdclk = 617143; |
560a7ae4 | 5855 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) |
b2045352 | 5856 | max_cdclk = 540000; |
560a7ae4 | 5857 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) |
b2045352 | 5858 | max_cdclk = 432000; |
560a7ae4 | 5859 | else |
487ed2e4 | 5860 | max_cdclk = 308571; |
b2045352 VS |
5861 | |
5862 | dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); | |
e2d214ae | 5863 | } else if (IS_BROXTON(dev_priv)) { |
281c114f | 5864 | dev_priv->max_cdclk_freq = 624000; |
8652744b | 5865 | } else if (IS_BROADWELL(dev_priv)) { |
560a7ae4 DL |
5866 | /* |
5867 | * FIXME with extra cooling we can allow | |
5868 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5869 | * How can we know if extra cooling is | |
5870 | * available? PCI ID, VTB, something else? | |
5871 | */ | |
5872 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5873 | dev_priv->max_cdclk_freq = 450000; | |
50a0bc90 | 5874 | else if (IS_BDW_ULX(dev_priv)) |
560a7ae4 | 5875 | dev_priv->max_cdclk_freq = 450000; |
50a0bc90 | 5876 | else if (IS_BDW_ULT(dev_priv)) |
560a7ae4 DL |
5877 | dev_priv->max_cdclk_freq = 540000; |
5878 | else | |
5879 | dev_priv->max_cdclk_freq = 675000; | |
920a14b2 | 5880 | } else if (IS_CHERRYVIEW(dev_priv)) { |
0904deaf | 5881 | dev_priv->max_cdclk_freq = 320000; |
11a914c2 | 5882 | } else if (IS_VALLEYVIEW(dev_priv)) { |
560a7ae4 DL |
5883 | dev_priv->max_cdclk_freq = 400000; |
5884 | } else { | |
5885 | /* otherwise assume cdclk is fixed */ | |
5886 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5887 | } | |
5888 | ||
adafdc6f MK |
5889 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5890 | ||
560a7ae4 DL |
5891 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5892 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5893 | |
5894 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5895 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5896 | } |
5897 | ||
4c75b940 | 5898 | static void intel_update_cdclk(struct drm_i915_private *dev_priv) |
560a7ae4 | 5899 | { |
1353c4fb | 5900 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev_priv); |
2f2a121a | 5901 | |
83d7c81f | 5902 | if (INTEL_GEN(dev_priv) >= 9) |
709e05c3 VS |
5903 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n", |
5904 | dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco, | |
5905 | dev_priv->cdclk_pll.ref); | |
2f2a121a VS |
5906 | else |
5907 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5908 | dev_priv->cdclk_freq); | |
560a7ae4 DL |
5909 | |
5910 | /* | |
b5d99ff9 VS |
5911 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): |
5912 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
5913 | * of cdclk that generates 4MHz reference clock freq which is used to | |
5914 | * generate GMBus clock. This will vary with the cdclk freq. | |
560a7ae4 | 5915 | */ |
b5d99ff9 | 5916 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
560a7ae4 | 5917 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
560a7ae4 DL |
5918 | } |
5919 | ||
92891e45 VS |
5920 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ |
5921 | static int skl_cdclk_decimal(int cdclk) | |
5922 | { | |
5923 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); | |
5924 | } | |
5925 | ||
5f199dfa VS |
5926 | static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk) |
5927 | { | |
5928 | int ratio; | |
5929 | ||
5930 | if (cdclk == dev_priv->cdclk_pll.ref) | |
5931 | return 0; | |
5932 | ||
5933 | switch (cdclk) { | |
5934 | default: | |
5935 | MISSING_CASE(cdclk); | |
5936 | case 144000: | |
5937 | case 288000: | |
5938 | case 384000: | |
5939 | case 576000: | |
5940 | ratio = 60; | |
5941 | break; | |
5942 | case 624000: | |
5943 | ratio = 65; | |
5944 | break; | |
5945 | } | |
5946 | ||
5947 | return dev_priv->cdclk_pll.ref * ratio; | |
5948 | } | |
5949 | ||
2b73001e VS |
5950 | static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) |
5951 | { | |
5952 | I915_WRITE(BXT_DE_PLL_ENABLE, 0); | |
5953 | ||
5954 | /* Timeout 200us */ | |
95cac283 CW |
5955 | if (intel_wait_for_register(dev_priv, |
5956 | BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0, | |
5957 | 1)) | |
2b73001e | 5958 | DRM_ERROR("timeout waiting for DE PLL unlock\n"); |
83d7c81f VS |
5959 | |
5960 | dev_priv->cdclk_pll.vco = 0; | |
2b73001e VS |
5961 | } |
5962 | ||
5f199dfa | 5963 | static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) |
2b73001e | 5964 | { |
5f199dfa | 5965 | int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref); |
2b73001e VS |
5966 | u32 val; |
5967 | ||
5968 | val = I915_READ(BXT_DE_PLL_CTL); | |
5969 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5f199dfa | 5970 | val |= BXT_DE_PLL_RATIO(ratio); |
2b73001e VS |
5971 | I915_WRITE(BXT_DE_PLL_CTL, val); |
5972 | ||
5973 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5974 | ||
5975 | /* Timeout 200us */ | |
e084e1b9 CW |
5976 | if (intel_wait_for_register(dev_priv, |
5977 | BXT_DE_PLL_ENABLE, | |
5978 | BXT_DE_PLL_LOCK, | |
5979 | BXT_DE_PLL_LOCK, | |
5980 | 1)) | |
2b73001e | 5981 | DRM_ERROR("timeout waiting for DE PLL lock\n"); |
83d7c81f | 5982 | |
5f199dfa | 5983 | dev_priv->cdclk_pll.vco = vco; |
2b73001e VS |
5984 | } |
5985 | ||
324513c0 | 5986 | static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk) |
f8437dd1 | 5987 | { |
5f199dfa VS |
5988 | u32 val, divider; |
5989 | int vco, ret; | |
f8437dd1 | 5990 | |
5f199dfa VS |
5991 | vco = bxt_de_pll_vco(dev_priv, cdclk); |
5992 | ||
5993 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); | |
5994 | ||
5995 | /* cdclk = vco / 2 / div{1,1.5,2,4} */ | |
5996 | switch (DIV_ROUND_CLOSEST(vco, cdclk)) { | |
5997 | case 8: | |
f8437dd1 | 5998 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; |
f8437dd1 | 5999 | break; |
5f199dfa | 6000 | case 4: |
f8437dd1 | 6001 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; |
f8437dd1 | 6002 | break; |
5f199dfa | 6003 | case 3: |
f8437dd1 | 6004 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; |
f8437dd1 | 6005 | break; |
5f199dfa | 6006 | case 2: |
f8437dd1 | 6007 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
f8437dd1 VK |
6008 | break; |
6009 | default: | |
5f199dfa VS |
6010 | WARN_ON(cdclk != dev_priv->cdclk_pll.ref); |
6011 | WARN_ON(vco != 0); | |
f8437dd1 | 6012 | |
5f199dfa VS |
6013 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; |
6014 | break; | |
f8437dd1 VK |
6015 | } |
6016 | ||
f8437dd1 | 6017 | /* Inform power controller of upcoming frequency change */ |
5f199dfa | 6018 | mutex_lock(&dev_priv->rps.hw_lock); |
f8437dd1 VK |
6019 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, |
6020 | 0x80000000); | |
6021 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6022 | ||
6023 | if (ret) { | |
6024 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
9ef56154 | 6025 | ret, cdclk); |
f8437dd1 VK |
6026 | return; |
6027 | } | |
6028 | ||
5f199dfa VS |
6029 | if (dev_priv->cdclk_pll.vco != 0 && |
6030 | dev_priv->cdclk_pll.vco != vco) | |
2b73001e | 6031 | bxt_de_pll_disable(dev_priv); |
f8437dd1 | 6032 | |
5f199dfa VS |
6033 | if (dev_priv->cdclk_pll.vco != vco) |
6034 | bxt_de_pll_enable(dev_priv, vco); | |
f8437dd1 | 6035 | |
5f199dfa VS |
6036 | val = divider | skl_cdclk_decimal(cdclk); |
6037 | /* | |
6038 | * FIXME if only the cd2x divider needs changing, it could be done | |
6039 | * without shutting off the pipe (if only one pipe is active). | |
6040 | */ | |
6041 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
6042 | /* | |
6043 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
6044 | * enable otherwise. | |
6045 | */ | |
6046 | if (cdclk >= 500000) | |
6047 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
6048 | I915_WRITE(CDCLK_CTL, val); | |
f8437dd1 VK |
6049 | |
6050 | mutex_lock(&dev_priv->rps.hw_lock); | |
6051 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
9ef56154 | 6052 | DIV_ROUND_UP(cdclk, 25000)); |
f8437dd1 VK |
6053 | mutex_unlock(&dev_priv->rps.hw_lock); |
6054 | ||
6055 | if (ret) { | |
6056 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
9ef56154 | 6057 | ret, cdclk); |
f8437dd1 VK |
6058 | return; |
6059 | } | |
6060 | ||
4c75b940 | 6061 | intel_update_cdclk(dev_priv); |
f8437dd1 VK |
6062 | } |
6063 | ||
d66a2194 | 6064 | static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 6065 | { |
d66a2194 ID |
6066 | u32 cdctl, expected; |
6067 | ||
4c75b940 | 6068 | intel_update_cdclk(dev_priv); |
f8437dd1 | 6069 | |
d66a2194 ID |
6070 | if (dev_priv->cdclk_pll.vco == 0 || |
6071 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
6072 | goto sanitize; | |
6073 | ||
6074 | /* DPLL okay; verify the cdclock | |
6075 | * | |
6076 | * Some BIOS versions leave an incorrect decimal frequency value and | |
6077 | * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4, | |
6078 | * so sanitize this register. | |
6079 | */ | |
6080 | cdctl = I915_READ(CDCLK_CTL); | |
6081 | /* | |
6082 | * Let's ignore the pipe field, since BIOS could have configured the | |
6083 | * dividers both synching to an active pipe, or asynchronously | |
6084 | * (PIPE_NONE). | |
6085 | */ | |
6086 | cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE; | |
6087 | ||
6088 | expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) | | |
6089 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
6090 | /* | |
6091 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
6092 | * enable otherwise. | |
6093 | */ | |
6094 | if (dev_priv->cdclk_freq >= 500000) | |
6095 | expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
6096 | ||
6097 | if (cdctl == expected) | |
6098 | /* All well; nothing to sanitize */ | |
6099 | return; | |
6100 | ||
6101 | sanitize: | |
6102 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
6103 | ||
6104 | /* force cdclk programming */ | |
6105 | dev_priv->cdclk_freq = 0; | |
6106 | ||
6107 | /* force full PLL disable + enable */ | |
6108 | dev_priv->cdclk_pll.vco = -1; | |
6109 | } | |
6110 | ||
324513c0 | 6111 | void bxt_init_cdclk(struct drm_i915_private *dev_priv) |
d66a2194 ID |
6112 | { |
6113 | bxt_sanitize_cdclk(dev_priv); | |
6114 | ||
6115 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) | |
089c6fd5 | 6116 | return; |
c2e001ef | 6117 | |
f8437dd1 VK |
6118 | /* |
6119 | * FIXME: | |
6120 | * - The initial CDCLK needs to be read from VBT. | |
6121 | * Need to make this change after VBT has changes for BXT. | |
f8437dd1 | 6122 | */ |
324513c0 | 6123 | bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0)); |
f8437dd1 VK |
6124 | } |
6125 | ||
324513c0 | 6126 | void bxt_uninit_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 6127 | { |
324513c0 | 6128 | bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref); |
f8437dd1 VK |
6129 | } |
6130 | ||
a8ca4934 VS |
6131 | static int skl_calc_cdclk(int max_pixclk, int vco) |
6132 | { | |
63911d72 | 6133 | if (vco == 8640000) { |
a8ca4934 | 6134 | if (max_pixclk > 540000) |
487ed2e4 | 6135 | return 617143; |
a8ca4934 VS |
6136 | else if (max_pixclk > 432000) |
6137 | return 540000; | |
487ed2e4 | 6138 | else if (max_pixclk > 308571) |
a8ca4934 VS |
6139 | return 432000; |
6140 | else | |
487ed2e4 | 6141 | return 308571; |
a8ca4934 | 6142 | } else { |
a8ca4934 VS |
6143 | if (max_pixclk > 540000) |
6144 | return 675000; | |
6145 | else if (max_pixclk > 450000) | |
6146 | return 540000; | |
6147 | else if (max_pixclk > 337500) | |
6148 | return 450000; | |
6149 | else | |
6150 | return 337500; | |
6151 | } | |
6152 | } | |
6153 | ||
ea61791e VS |
6154 | static void |
6155 | skl_dpll0_update(struct drm_i915_private *dev_priv) | |
5d96d8af | 6156 | { |
ea61791e | 6157 | u32 val; |
5d96d8af | 6158 | |
709e05c3 | 6159 | dev_priv->cdclk_pll.ref = 24000; |
1c3f7700 | 6160 | dev_priv->cdclk_pll.vco = 0; |
709e05c3 | 6161 | |
ea61791e | 6162 | val = I915_READ(LCPLL1_CTL); |
1c3f7700 | 6163 | if ((val & LCPLL_PLL_ENABLE) == 0) |
ea61791e | 6164 | return; |
5d96d8af | 6165 | |
1c3f7700 ID |
6166 | if (WARN_ON((val & LCPLL_PLL_LOCK) == 0)) |
6167 | return; | |
9f7eb31a | 6168 | |
ea61791e VS |
6169 | val = I915_READ(DPLL_CTRL1); |
6170 | ||
1c3f7700 ID |
6171 | if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | |
6172 | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
6173 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != | |
6174 | DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) | |
6175 | return; | |
9f7eb31a | 6176 | |
ea61791e VS |
6177 | switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { |
6178 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): | |
6179 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): | |
6180 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): | |
6181 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): | |
63911d72 | 6182 | dev_priv->cdclk_pll.vco = 8100000; |
ea61791e VS |
6183 | break; |
6184 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): | |
6185 | case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): | |
63911d72 | 6186 | dev_priv->cdclk_pll.vco = 8640000; |
ea61791e VS |
6187 | break; |
6188 | default: | |
6189 | MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
ea61791e VS |
6190 | break; |
6191 | } | |
5d96d8af DL |
6192 | } |
6193 | ||
b2045352 VS |
6194 | void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco) |
6195 | { | |
6196 | bool changed = dev_priv->skl_preferred_vco_freq != vco; | |
6197 | ||
6198 | dev_priv->skl_preferred_vco_freq = vco; | |
6199 | ||
6200 | if (changed) | |
4c75b940 | 6201 | intel_update_max_cdclk(dev_priv); |
b2045352 VS |
6202 | } |
6203 | ||
5d96d8af | 6204 | static void |
3861fc60 | 6205 | skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) |
5d96d8af | 6206 | { |
a8ca4934 | 6207 | int min_cdclk = skl_calc_cdclk(0, vco); |
5d96d8af DL |
6208 | u32 val; |
6209 | ||
63911d72 | 6210 | WARN_ON(vco != 8100000 && vco != 8640000); |
b2045352 | 6211 | |
5d96d8af | 6212 | /* select the minimum CDCLK before enabling DPLL 0 */ |
9ef56154 | 6213 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); |
5d96d8af DL |
6214 | I915_WRITE(CDCLK_CTL, val); |
6215 | POSTING_READ(CDCLK_CTL); | |
6216 | ||
6217 | /* | |
6218 | * We always enable DPLL0 with the lowest link rate possible, but still | |
6219 | * taking into account the VCO required to operate the eDP panel at the | |
6220 | * desired frequency. The usual DP link rates operate with a VCO of | |
6221 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
6222 | * The modeset code is responsible for the selection of the exact link | |
6223 | * rate later on, with the constraint of choosing a frequency that | |
a8ca4934 | 6224 | * works with vco. |
5d96d8af DL |
6225 | */ |
6226 | val = I915_READ(DPLL_CTRL1); | |
6227 | ||
6228 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
6229 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
6230 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
63911d72 | 6231 | if (vco == 8640000) |
5d96d8af DL |
6232 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
6233 | SKL_DPLL0); | |
6234 | else | |
6235 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
6236 | SKL_DPLL0); | |
6237 | ||
6238 | I915_WRITE(DPLL_CTRL1, val); | |
6239 | POSTING_READ(DPLL_CTRL1); | |
6240 | ||
6241 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
6242 | ||
e24ca054 CW |
6243 | if (intel_wait_for_register(dev_priv, |
6244 | LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
6245 | 5)) | |
5d96d8af | 6246 | DRM_ERROR("DPLL0 not locked\n"); |
1cd593e0 | 6247 | |
63911d72 | 6248 | dev_priv->cdclk_pll.vco = vco; |
b2045352 VS |
6249 | |
6250 | /* We'll want to keep using the current vco from now on. */ | |
6251 | skl_set_preferred_cdclk_vco(dev_priv, vco); | |
5d96d8af DL |
6252 | } |
6253 | ||
430e05de VS |
6254 | static void |
6255 | skl_dpll0_disable(struct drm_i915_private *dev_priv) | |
6256 | { | |
6257 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
8ad32a05 CW |
6258 | if (intel_wait_for_register(dev_priv, |
6259 | LCPLL1_CTL, LCPLL_PLL_LOCK, 0, | |
6260 | 1)) | |
430e05de | 6261 | DRM_ERROR("Couldn't disable DPLL0\n"); |
1cd593e0 | 6262 | |
63911d72 | 6263 | dev_priv->cdclk_pll.vco = 0; |
430e05de VS |
6264 | } |
6265 | ||
5d96d8af DL |
6266 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) |
6267 | { | |
6268 | int ret; | |
6269 | u32 val; | |
6270 | ||
6271 | /* inform PCU we want to change CDCLK */ | |
6272 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
6273 | mutex_lock(&dev_priv->rps.hw_lock); | |
6274 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
6275 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6276 | ||
6277 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
6278 | } | |
6279 | ||
6280 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
6281 | { | |
848496e5 | 6282 | return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0; |
5d96d8af DL |
6283 | } |
6284 | ||
1cd593e0 | 6285 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco) |
5d96d8af DL |
6286 | { |
6287 | u32 freq_select, pcu_ack; | |
6288 | ||
1cd593e0 VS |
6289 | WARN_ON((cdclk == 24000) != (vco == 0)); |
6290 | ||
63911d72 | 6291 | DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco); |
5d96d8af DL |
6292 | |
6293 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
6294 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
6295 | return; | |
6296 | } | |
6297 | ||
6298 | /* set CDCLK_CTL */ | |
9ef56154 | 6299 | switch (cdclk) { |
5d96d8af DL |
6300 | case 450000: |
6301 | case 432000: | |
6302 | freq_select = CDCLK_FREQ_450_432; | |
6303 | pcu_ack = 1; | |
6304 | break; | |
6305 | case 540000: | |
6306 | freq_select = CDCLK_FREQ_540; | |
6307 | pcu_ack = 2; | |
6308 | break; | |
487ed2e4 | 6309 | case 308571: |
5d96d8af DL |
6310 | case 337500: |
6311 | default: | |
6312 | freq_select = CDCLK_FREQ_337_308; | |
6313 | pcu_ack = 0; | |
6314 | break; | |
487ed2e4 | 6315 | case 617143: |
5d96d8af DL |
6316 | case 675000: |
6317 | freq_select = CDCLK_FREQ_675_617; | |
6318 | pcu_ack = 3; | |
6319 | break; | |
6320 | } | |
6321 | ||
63911d72 VS |
6322 | if (dev_priv->cdclk_pll.vco != 0 && |
6323 | dev_priv->cdclk_pll.vco != vco) | |
1cd593e0 VS |
6324 | skl_dpll0_disable(dev_priv); |
6325 | ||
63911d72 | 6326 | if (dev_priv->cdclk_pll.vco != vco) |
1cd593e0 VS |
6327 | skl_dpll0_enable(dev_priv, vco); |
6328 | ||
9ef56154 | 6329 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); |
5d96d8af DL |
6330 | POSTING_READ(CDCLK_CTL); |
6331 | ||
6332 | /* inform PCU of the change */ | |
6333 | mutex_lock(&dev_priv->rps.hw_lock); | |
6334 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
6335 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 | 6336 | |
4c75b940 | 6337 | intel_update_cdclk(dev_priv); |
5d96d8af DL |
6338 | } |
6339 | ||
9f7eb31a VS |
6340 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv); |
6341 | ||
5d96d8af DL |
6342 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) |
6343 | { | |
709e05c3 | 6344 | skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0); |
5d96d8af DL |
6345 | } |
6346 | ||
6347 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
6348 | { | |
9f7eb31a VS |
6349 | int cdclk, vco; |
6350 | ||
6351 | skl_sanitize_cdclk(dev_priv); | |
5d96d8af | 6352 | |
63911d72 | 6353 | if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) { |
9f7eb31a VS |
6354 | /* |
6355 | * Use the current vco as our initial | |
6356 | * guess as to what the preferred vco is. | |
6357 | */ | |
6358 | if (dev_priv->skl_preferred_vco_freq == 0) | |
6359 | skl_set_preferred_cdclk_vco(dev_priv, | |
63911d72 | 6360 | dev_priv->cdclk_pll.vco); |
70c2c184 | 6361 | return; |
1cd593e0 | 6362 | } |
5d96d8af | 6363 | |
70c2c184 VS |
6364 | vco = dev_priv->skl_preferred_vco_freq; |
6365 | if (vco == 0) | |
63911d72 | 6366 | vco = 8100000; |
70c2c184 | 6367 | cdclk = skl_calc_cdclk(0, vco); |
5d96d8af | 6368 | |
70c2c184 | 6369 | skl_set_cdclk(dev_priv, cdclk, vco); |
5d96d8af DL |
6370 | } |
6371 | ||
9f7eb31a | 6372 | static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
c73666f3 | 6373 | { |
09492498 | 6374 | uint32_t cdctl, expected; |
c73666f3 | 6375 | |
f1b391a5 SK |
6376 | /* |
6377 | * check if the pre-os intialized the display | |
6378 | * There is SWF18 scratchpad register defined which is set by the | |
6379 | * pre-os which can be used by the OS drivers to check the status | |
6380 | */ | |
6381 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
6382 | goto sanitize; | |
6383 | ||
4c75b940 | 6384 | intel_update_cdclk(dev_priv); |
c73666f3 | 6385 | /* Is PLL enabled and locked ? */ |
1c3f7700 ID |
6386 | if (dev_priv->cdclk_pll.vco == 0 || |
6387 | dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref) | |
c73666f3 SK |
6388 | goto sanitize; |
6389 | ||
6390 | /* DPLL okay; verify the cdclock | |
6391 | * | |
6392 | * Noticed in some instances that the freq selection is correct but | |
6393 | * decimal part is programmed wrong from BIOS where pre-os does not | |
6394 | * enable display. Verify the same as well. | |
6395 | */ | |
09492498 VS |
6396 | cdctl = I915_READ(CDCLK_CTL); |
6397 | expected = (cdctl & CDCLK_FREQ_SEL_MASK) | | |
6398 | skl_cdclk_decimal(dev_priv->cdclk_freq); | |
6399 | if (cdctl == expected) | |
c73666f3 | 6400 | /* All well; nothing to sanitize */ |
9f7eb31a | 6401 | return; |
c89e39f3 | 6402 | |
9f7eb31a VS |
6403 | sanitize: |
6404 | DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n"); | |
c73666f3 | 6405 | |
9f7eb31a VS |
6406 | /* force cdclk programming */ |
6407 | dev_priv->cdclk_freq = 0; | |
6408 | /* force full PLL disable + enable */ | |
63911d72 | 6409 | dev_priv->cdclk_pll.vco = -1; |
c73666f3 SK |
6410 | } |
6411 | ||
30a970c6 JB |
6412 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
6413 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
6414 | { | |
fac5e23e | 6415 | struct drm_i915_private *dev_priv = to_i915(dev); |
30a970c6 JB |
6416 | u32 val, cmd; |
6417 | ||
1353c4fb | 6418 | WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv) |
164dfd28 | 6419 | != dev_priv->cdclk_freq); |
d60c4473 | 6420 | |
dfcab17e | 6421 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 6422 | cmd = 2; |
dfcab17e | 6423 | else if (cdclk == 266667) |
30a970c6 JB |
6424 | cmd = 1; |
6425 | else | |
6426 | cmd = 0; | |
6427 | ||
6428 | mutex_lock(&dev_priv->rps.hw_lock); | |
6429 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6430 | val &= ~DSPFREQGUAR_MASK; | |
6431 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
6432 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6433 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6434 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
6435 | 50)) { | |
6436 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6437 | } | |
6438 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6439 | ||
54433e91 VS |
6440 | mutex_lock(&dev_priv->sb_lock); |
6441 | ||
dfcab17e | 6442 | if (cdclk == 400000) { |
6bcda4f0 | 6443 | u32 divider; |
30a970c6 | 6444 | |
6bcda4f0 | 6445 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 6446 | |
30a970c6 JB |
6447 | /* adjust cdclk divider */ |
6448 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 6449 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
6450 | val |= divider; |
6451 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
6452 | |
6453 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 6454 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
6455 | 50)) |
6456 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
6457 | } |
6458 | ||
30a970c6 JB |
6459 | /* adjust self-refresh exit latency value */ |
6460 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
6461 | val &= ~0x7f; | |
6462 | ||
6463 | /* | |
6464 | * For high bandwidth configs, we set a higher latency in the bunit | |
6465 | * so that the core display fetch happens in time to avoid underruns. | |
6466 | */ | |
dfcab17e | 6467 | if (cdclk == 400000) |
30a970c6 JB |
6468 | val |= 4500 / 250; /* 4.5 usec */ |
6469 | else | |
6470 | val |= 3000 / 250; /* 3.0 usec */ | |
6471 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 6472 | |
a580516d | 6473 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 6474 | |
4c75b940 | 6475 | intel_update_cdclk(dev_priv); |
30a970c6 JB |
6476 | } |
6477 | ||
383c5a6a VS |
6478 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
6479 | { | |
fac5e23e | 6480 | struct drm_i915_private *dev_priv = to_i915(dev); |
383c5a6a VS |
6481 | u32 val, cmd; |
6482 | ||
1353c4fb | 6483 | WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv) |
164dfd28 | 6484 | != dev_priv->cdclk_freq); |
383c5a6a VS |
6485 | |
6486 | switch (cdclk) { | |
383c5a6a VS |
6487 | case 333333: |
6488 | case 320000: | |
383c5a6a | 6489 | case 266667: |
383c5a6a | 6490 | case 200000: |
383c5a6a VS |
6491 | break; |
6492 | default: | |
5f77eeb0 | 6493 | MISSING_CASE(cdclk); |
383c5a6a VS |
6494 | return; |
6495 | } | |
6496 | ||
9d0d3fda VS |
6497 | /* |
6498 | * Specs are full of misinformation, but testing on actual | |
6499 | * hardware has shown that we just need to write the desired | |
6500 | * CCK divider into the Punit register. | |
6501 | */ | |
6502 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
6503 | ||
383c5a6a VS |
6504 | mutex_lock(&dev_priv->rps.hw_lock); |
6505 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6506 | val &= ~DSPFREQGUAR_MASK_CHV; | |
6507 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
6508 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6509 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6510 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
6511 | 50)) { | |
6512 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6513 | } | |
6514 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6515 | ||
4c75b940 | 6516 | intel_update_cdclk(dev_priv); |
383c5a6a VS |
6517 | } |
6518 | ||
30a970c6 JB |
6519 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
6520 | int max_pixclk) | |
6521 | { | |
6bcda4f0 | 6522 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 6523 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 6524 | |
30a970c6 JB |
6525 | /* |
6526 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
6527 | * 200MHz | |
6528 | * 267MHz | |
29dc7ef3 | 6529 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
6530 | * 400MHz (VLV only) |
6531 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
6532 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
6533 | * |
6534 | * We seem to get an unstable or solid color picture at 200MHz. | |
6535 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
6536 | * are off. | |
30a970c6 | 6537 | */ |
6cca3195 VS |
6538 | if (!IS_CHERRYVIEW(dev_priv) && |
6539 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6540 | return 400000; |
6cca3195 | 6541 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6542 | return freq_320; |
e37c67a1 | 6543 | else if (max_pixclk > 0) |
dfcab17e | 6544 | return 266667; |
e37c67a1 VS |
6545 | else |
6546 | return 200000; | |
30a970c6 JB |
6547 | } |
6548 | ||
324513c0 | 6549 | static int bxt_calc_cdclk(int max_pixclk) |
f8437dd1 | 6550 | { |
760e1477 | 6551 | if (max_pixclk > 576000) |
f8437dd1 | 6552 | return 624000; |
760e1477 | 6553 | else if (max_pixclk > 384000) |
f8437dd1 | 6554 | return 576000; |
760e1477 | 6555 | else if (max_pixclk > 288000) |
f8437dd1 | 6556 | return 384000; |
760e1477 | 6557 | else if (max_pixclk > 144000) |
f8437dd1 VK |
6558 | return 288000; |
6559 | else | |
6560 | return 144000; | |
6561 | } | |
6562 | ||
e8788cbc | 6563 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
6564 | static int intel_mode_max_pixclk(struct drm_device *dev, |
6565 | struct drm_atomic_state *state) | |
30a970c6 | 6566 | { |
565602d7 | 6567 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 6568 | struct drm_i915_private *dev_priv = to_i915(dev); |
565602d7 ML |
6569 | struct drm_crtc *crtc; |
6570 | struct drm_crtc_state *crtc_state; | |
6571 | unsigned max_pixclk = 0, i; | |
6572 | enum pipe pipe; | |
30a970c6 | 6573 | |
565602d7 ML |
6574 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6575 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6576 | |
565602d7 ML |
6577 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6578 | int pixclk = 0; | |
6579 | ||
6580 | if (crtc_state->enable) | |
6581 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6582 | |
565602d7 | 6583 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6584 | } |
6585 | ||
565602d7 ML |
6586 | for_each_pipe(dev_priv, pipe) |
6587 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6588 | ||
30a970c6 JB |
6589 | return max_pixclk; |
6590 | } | |
6591 | ||
27c329ed | 6592 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6593 | { |
27c329ed | 6594 | struct drm_device *dev = state->dev; |
fac5e23e | 6595 | struct drm_i915_private *dev_priv = to_i915(dev); |
27c329ed | 6596 | int max_pixclk = intel_mode_max_pixclk(dev, state); |
1a617b77 ML |
6597 | struct intel_atomic_state *intel_state = |
6598 | to_intel_atomic_state(state); | |
30a970c6 | 6599 | |
1a617b77 | 6600 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6601 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6602 | |
1a617b77 ML |
6603 | if (!intel_state->active_crtcs) |
6604 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6605 | ||
27c329ed ML |
6606 | return 0; |
6607 | } | |
304603f4 | 6608 | |
324513c0 | 6609 | static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state) |
27c329ed | 6610 | { |
4e5ca60f | 6611 | int max_pixclk = ilk_max_pixel_rate(state); |
1a617b77 ML |
6612 | struct intel_atomic_state *intel_state = |
6613 | to_intel_atomic_state(state); | |
85a96e7a | 6614 | |
1a617b77 | 6615 | intel_state->cdclk = intel_state->dev_cdclk = |
324513c0 | 6616 | bxt_calc_cdclk(max_pixclk); |
85a96e7a | 6617 | |
1a617b77 | 6618 | if (!intel_state->active_crtcs) |
324513c0 | 6619 | intel_state->dev_cdclk = bxt_calc_cdclk(0); |
1a617b77 | 6620 | |
27c329ed | 6621 | return 0; |
30a970c6 JB |
6622 | } |
6623 | ||
1e69cd74 VS |
6624 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6625 | { | |
6626 | unsigned int credits, default_credits; | |
6627 | ||
6628 | if (IS_CHERRYVIEW(dev_priv)) | |
6629 | default_credits = PFI_CREDIT(12); | |
6630 | else | |
6631 | default_credits = PFI_CREDIT(8); | |
6632 | ||
bfa7df01 | 6633 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6634 | /* CHV suggested value is 31 or 63 */ |
6635 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6636 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6637 | else |
6638 | credits = PFI_CREDIT(15); | |
6639 | } else { | |
6640 | credits = default_credits; | |
6641 | } | |
6642 | ||
6643 | /* | |
6644 | * WA - write default credits before re-programming | |
6645 | * FIXME: should we also set the resend bit here? | |
6646 | */ | |
6647 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6648 | default_credits); | |
6649 | ||
6650 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6651 | credits | PFI_CREDIT_RESEND); | |
6652 | ||
6653 | /* | |
6654 | * FIXME is this guaranteed to clear | |
6655 | * immediately or should we poll for it? | |
6656 | */ | |
6657 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6658 | } | |
6659 | ||
27c329ed | 6660 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6661 | { |
a821fc46 | 6662 | struct drm_device *dev = old_state->dev; |
fac5e23e | 6663 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 ML |
6664 | struct intel_atomic_state *old_intel_state = |
6665 | to_intel_atomic_state(old_state); | |
6666 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6667 | |
27c329ed ML |
6668 | /* |
6669 | * FIXME: We can end up here with all power domains off, yet | |
6670 | * with a CDCLK frequency other than the minimum. To account | |
6671 | * for this take the PIPE-A power domain, which covers the HW | |
6672 | * blocks needed for the following programming. This can be | |
6673 | * removed once it's guaranteed that we get here either with | |
6674 | * the minimum CDCLK set, or the required power domains | |
6675 | * enabled. | |
6676 | */ | |
6677 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6678 | |
920a14b2 | 6679 | if (IS_CHERRYVIEW(dev_priv)) |
27c329ed ML |
6680 | cherryview_set_cdclk(dev, req_cdclk); |
6681 | else | |
6682 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6683 | |
27c329ed | 6684 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6685 | |
27c329ed | 6686 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6687 | } |
6688 | ||
4a806558 ML |
6689 | static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, |
6690 | struct drm_atomic_state *old_state) | |
89b667f8 | 6691 | { |
4a806558 | 6692 | struct drm_crtc *crtc = pipe_config->base.crtc; |
89b667f8 | 6693 | struct drm_device *dev = crtc->dev; |
a72e4c9f | 6694 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 | 6695 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
89b667f8 | 6696 | int pipe = intel_crtc->pipe; |
89b667f8 | 6697 | |
53d9f4e9 | 6698 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6699 | return; |
6700 | ||
37a5650b | 6701 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6702 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6703 | |
6704 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6705 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6706 | |
920a14b2 | 6707 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
fac5e23e | 6708 | struct drm_i915_private *dev_priv = to_i915(dev); |
c14b0485 VS |
6709 | |
6710 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6711 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6712 | } | |
6713 | ||
5b18e57c DV |
6714 | i9xx_set_pipeconf(intel_crtc); |
6715 | ||
89b667f8 | 6716 | intel_crtc->active = true; |
89b667f8 | 6717 | |
a72e4c9f | 6718 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6719 | |
fd6bbda9 | 6720 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
89b667f8 | 6721 | |
920a14b2 | 6722 | if (IS_CHERRYVIEW(dev_priv)) { |
cd2d34d9 VS |
6723 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
6724 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
6725 | } else { | |
6726 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6727 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
9d556c99 | 6728 | } |
89b667f8 | 6729 | |
fd6bbda9 | 6730 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
89b667f8 | 6731 | |
2dd24552 JB |
6732 | i9xx_pfit_enable(intel_crtc); |
6733 | ||
b95c5321 | 6734 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6735 | |
432081bc | 6736 | intel_update_watermarks(intel_crtc); |
e1fdc473 | 6737 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6738 | |
4b3a9526 VS |
6739 | assert_vblank_disabled(crtc); |
6740 | drm_crtc_vblank_on(crtc); | |
6741 | ||
fd6bbda9 | 6742 | intel_encoders_enable(crtc, pipe_config, old_state); |
89b667f8 JB |
6743 | } |
6744 | ||
f13c2ef3 DV |
6745 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6746 | { | |
6747 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6748 | struct drm_i915_private *dev_priv = to_i915(dev); |
f13c2ef3 | 6749 | |
6e3c9717 ACO |
6750 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6751 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6752 | } |
6753 | ||
4a806558 ML |
6754 | static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, |
6755 | struct drm_atomic_state *old_state) | |
79e53945 | 6756 | { |
4a806558 | 6757 | struct drm_crtc *crtc = pipe_config->base.crtc; |
79e53945 | 6758 | struct drm_device *dev = crtc->dev; |
a72e4c9f | 6759 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6760 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cd2d34d9 | 6761 | enum pipe pipe = intel_crtc->pipe; |
79e53945 | 6762 | |
53d9f4e9 | 6763 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6764 | return; |
6765 | ||
f13c2ef3 DV |
6766 | i9xx_set_pll_dividers(intel_crtc); |
6767 | ||
37a5650b | 6768 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 6769 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6770 | |
6771 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6772 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6773 | |
5b18e57c DV |
6774 | i9xx_set_pipeconf(intel_crtc); |
6775 | ||
f7abfe8b | 6776 | intel_crtc->active = true; |
6b383a7f | 6777 | |
5db94019 | 6778 | if (!IS_GEN2(dev_priv)) |
a72e4c9f | 6779 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6780 | |
fd6bbda9 | 6781 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
9d6d9f19 | 6782 | |
f6736a1a DV |
6783 | i9xx_enable_pll(intel_crtc); |
6784 | ||
2dd24552 JB |
6785 | i9xx_pfit_enable(intel_crtc); |
6786 | ||
b95c5321 | 6787 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6788 | |
432081bc | 6789 | intel_update_watermarks(intel_crtc); |
e1fdc473 | 6790 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6791 | |
4b3a9526 VS |
6792 | assert_vblank_disabled(crtc); |
6793 | drm_crtc_vblank_on(crtc); | |
6794 | ||
fd6bbda9 | 6795 | intel_encoders_enable(crtc, pipe_config, old_state); |
0b8765c6 | 6796 | } |
79e53945 | 6797 | |
87476d63 DV |
6798 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6799 | { | |
6800 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6801 | struct drm_i915_private *dev_priv = to_i915(dev); |
87476d63 | 6802 | |
6e3c9717 | 6803 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6804 | return; |
87476d63 | 6805 | |
328d8e82 | 6806 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6807 | |
328d8e82 DV |
6808 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6809 | I915_READ(PFIT_CONTROL)); | |
6810 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6811 | } |
6812 | ||
4a806558 ML |
6813 | static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, |
6814 | struct drm_atomic_state *old_state) | |
0b8765c6 | 6815 | { |
4a806558 | 6816 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
0b8765c6 | 6817 | struct drm_device *dev = crtc->dev; |
fac5e23e | 6818 | struct drm_i915_private *dev_priv = to_i915(dev); |
0b8765c6 JB |
6819 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6820 | int pipe = intel_crtc->pipe; | |
ef9c3aee | 6821 | |
6304cd91 VS |
6822 | /* |
6823 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6824 | * wait for planes to fully turn off before disabling the pipe. | |
6825 | */ | |
5db94019 | 6826 | if (IS_GEN2(dev_priv)) |
0f0f74bc | 6827 | intel_wait_for_vblank(dev_priv, pipe); |
6304cd91 | 6828 | |
fd6bbda9 | 6829 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4b3a9526 | 6830 | |
f9b61ff6 DV |
6831 | drm_crtc_vblank_off(crtc); |
6832 | assert_vblank_disabled(crtc); | |
6833 | ||
575f7ab7 | 6834 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6835 | |
87476d63 | 6836 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6837 | |
fd6bbda9 | 6838 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
89b667f8 | 6839 | |
d7edc4e5 | 6840 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
920a14b2 | 6841 | if (IS_CHERRYVIEW(dev_priv)) |
076ed3b2 | 6842 | chv_disable_pll(dev_priv, pipe); |
11a914c2 | 6843 | else if (IS_VALLEYVIEW(dev_priv)) |
076ed3b2 CML |
6844 | vlv_disable_pll(dev_priv, pipe); |
6845 | else | |
1c4e0274 | 6846 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6847 | } |
0b8765c6 | 6848 | |
fd6bbda9 | 6849 | intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); |
d6db995f | 6850 | |
5db94019 | 6851 | if (!IS_GEN2(dev_priv)) |
a72e4c9f | 6852 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6853 | } |
6854 | ||
b17d48e2 ML |
6855 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6856 | { | |
842e0307 | 6857 | struct intel_encoder *encoder; |
b17d48e2 ML |
6858 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6859 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6860 | enum intel_display_power_domain domain; | |
6861 | unsigned long domains; | |
4a806558 ML |
6862 | struct drm_atomic_state *state; |
6863 | struct intel_crtc_state *crtc_state; | |
6864 | int ret; | |
b17d48e2 ML |
6865 | |
6866 | if (!intel_crtc->active) | |
6867 | return; | |
6868 | ||
936e71e3 | 6869 | if (to_intel_plane_state(crtc->primary->state)->base.visible) { |
5a21b665 | 6870 | WARN_ON(intel_crtc->flip_work); |
fc32b1fd | 6871 | |
2622a081 | 6872 | intel_pre_disable_primary_noatomic(crtc); |
54a41961 ML |
6873 | |
6874 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
936e71e3 | 6875 | to_intel_plane_state(crtc->primary->state)->base.visible = false; |
a539205a ML |
6876 | } |
6877 | ||
4a806558 ML |
6878 | state = drm_atomic_state_alloc(crtc->dev); |
6879 | state->acquire_ctx = crtc->dev->mode_config.acquire_ctx; | |
6880 | ||
6881 | /* Everything's already locked, -EDEADLK can't happen. */ | |
6882 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
6883 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
6884 | ||
6885 | WARN_ON(IS_ERR(crtc_state) || ret); | |
6886 | ||
6887 | dev_priv->display.crtc_disable(crtc_state, state); | |
6888 | ||
0853695c | 6889 | drm_atomic_state_put(state); |
842e0307 | 6890 | |
78108b7c VS |
6891 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
6892 | crtc->base.id, crtc->name); | |
842e0307 ML |
6893 | |
6894 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6895 | crtc->state->active = false; | |
37d9078b | 6896 | intel_crtc->active = false; |
842e0307 ML |
6897 | crtc->enabled = false; |
6898 | crtc->state->connector_mask = 0; | |
6899 | crtc->state->encoder_mask = 0; | |
6900 | ||
6901 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6902 | encoder->base.crtc = NULL; | |
6903 | ||
58f9c0bc | 6904 | intel_fbc_disable(intel_crtc); |
432081bc | 6905 | intel_update_watermarks(intel_crtc); |
1f7457b1 | 6906 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6907 | |
6908 | domains = intel_crtc->enabled_power_domains; | |
6909 | for_each_power_domain(domain, domains) | |
6910 | intel_display_power_put(dev_priv, domain); | |
6911 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6912 | |
6913 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6914 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6915 | } |
6916 | ||
6b72d486 ML |
6917 | /* |
6918 | * turn all crtc's off, but do not adjust state | |
6919 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6920 | */ | |
70e0bd74 | 6921 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6922 | { |
e2c8b870 | 6923 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6924 | struct drm_atomic_state *state; |
e2c8b870 | 6925 | int ret; |
70e0bd74 | 6926 | |
e2c8b870 ML |
6927 | state = drm_atomic_helper_suspend(dev); |
6928 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6929 | if (ret) |
6930 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6931 | else |
6932 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6933 | return ret; |
ee7b9f93 JB |
6934 | } |
6935 | ||
ea5b213a | 6936 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6937 | { |
4ef69c7a | 6938 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6939 | |
ea5b213a CW |
6940 | drm_encoder_cleanup(encoder); |
6941 | kfree(intel_encoder); | |
7e7d76c3 JB |
6942 | } |
6943 | ||
0a91ca29 DV |
6944 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6945 | * internal consistency). */ | |
5a21b665 | 6946 | static void intel_connector_verify_state(struct intel_connector *connector) |
79e53945 | 6947 | { |
5a21b665 | 6948 | struct drm_crtc *crtc = connector->base.state->crtc; |
35dd3c64 ML |
6949 | |
6950 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6951 | connector->base.base.id, | |
6952 | connector->base.name); | |
6953 | ||
0a91ca29 | 6954 | if (connector->get_hw_state(connector)) { |
e85376cb | 6955 | struct intel_encoder *encoder = connector->encoder; |
5a21b665 | 6956 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6957 | |
35dd3c64 ML |
6958 | I915_STATE_WARN(!crtc, |
6959 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6960 | |
35dd3c64 ML |
6961 | if (!crtc) |
6962 | return; | |
6963 | ||
6964 | I915_STATE_WARN(!crtc->state->active, | |
6965 | "connector is active, but attached crtc isn't\n"); | |
6966 | ||
e85376cb | 6967 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6968 | return; |
6969 | ||
e85376cb | 6970 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6971 | "atomic encoder doesn't match attached encoder\n"); |
6972 | ||
e85376cb | 6973 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6974 | "attached encoder crtc differs from connector crtc\n"); |
6975 | } else { | |
4d688a2a ML |
6976 | I915_STATE_WARN(crtc && crtc->state->active, |
6977 | "attached crtc is active, but connector isn't\n"); | |
5a21b665 | 6978 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
35dd3c64 | 6979 | "best encoder set without crtc!\n"); |
0a91ca29 | 6980 | } |
79e53945 JB |
6981 | } |
6982 | ||
08d9bc92 ACO |
6983 | int intel_connector_init(struct intel_connector *connector) |
6984 | { | |
5350a031 | 6985 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6986 | |
5350a031 | 6987 | if (!connector->base.state) |
08d9bc92 ACO |
6988 | return -ENOMEM; |
6989 | ||
08d9bc92 ACO |
6990 | return 0; |
6991 | } | |
6992 | ||
6993 | struct intel_connector *intel_connector_alloc(void) | |
6994 | { | |
6995 | struct intel_connector *connector; | |
6996 | ||
6997 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6998 | if (!connector) | |
6999 | return NULL; | |
7000 | ||
7001 | if (intel_connector_init(connector) < 0) { | |
7002 | kfree(connector); | |
7003 | return NULL; | |
7004 | } | |
7005 | ||
7006 | return connector; | |
7007 | } | |
7008 | ||
f0947c37 DV |
7009 | /* Simple connector->get_hw_state implementation for encoders that support only |
7010 | * one connector and no cloning and hence the encoder state determines the state | |
7011 | * of the connector. */ | |
7012 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 7013 | { |
24929352 | 7014 | enum pipe pipe = 0; |
f0947c37 | 7015 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 7016 | |
f0947c37 | 7017 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
7018 | } |
7019 | ||
6d293983 | 7020 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 7021 | { |
6d293983 ACO |
7022 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
7023 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
7024 | |
7025 | return 0; | |
7026 | } | |
7027 | ||
6d293983 | 7028 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 7029 | struct intel_crtc_state *pipe_config) |
1857e1da | 7030 | { |
8652744b | 7031 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d293983 ACO |
7032 | struct drm_atomic_state *state = pipe_config->base.state; |
7033 | struct intel_crtc *other_crtc; | |
7034 | struct intel_crtc_state *other_crtc_state; | |
7035 | ||
1857e1da DV |
7036 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
7037 | pipe_name(pipe), pipe_config->fdi_lanes); | |
7038 | if (pipe_config->fdi_lanes > 4) { | |
7039 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
7040 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7041 | return -EINVAL; |
1857e1da DV |
7042 | } |
7043 | ||
8652744b | 7044 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1857e1da DV |
7045 | if (pipe_config->fdi_lanes > 2) { |
7046 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
7047 | pipe_config->fdi_lanes); | |
6d293983 | 7048 | return -EINVAL; |
1857e1da | 7049 | } else { |
6d293983 | 7050 | return 0; |
1857e1da DV |
7051 | } |
7052 | } | |
7053 | ||
7054 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 7055 | return 0; |
1857e1da DV |
7056 | |
7057 | /* Ivybridge 3 pipe is really complicated */ | |
7058 | switch (pipe) { | |
7059 | case PIPE_A: | |
6d293983 | 7060 | return 0; |
1857e1da | 7061 | case PIPE_B: |
6d293983 ACO |
7062 | if (pipe_config->fdi_lanes <= 2) |
7063 | return 0; | |
7064 | ||
b91eb5cc | 7065 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); |
6d293983 ACO |
7066 | other_crtc_state = |
7067 | intel_atomic_get_crtc_state(state, other_crtc); | |
7068 | if (IS_ERR(other_crtc_state)) | |
7069 | return PTR_ERR(other_crtc_state); | |
7070 | ||
7071 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
7072 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
7073 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7074 | return -EINVAL; |
1857e1da | 7075 | } |
6d293983 | 7076 | return 0; |
1857e1da | 7077 | case PIPE_C: |
251cc67c VS |
7078 | if (pipe_config->fdi_lanes > 2) { |
7079 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
7080 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 7081 | return -EINVAL; |
251cc67c | 7082 | } |
6d293983 | 7083 | |
b91eb5cc | 7084 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); |
6d293983 ACO |
7085 | other_crtc_state = |
7086 | intel_atomic_get_crtc_state(state, other_crtc); | |
7087 | if (IS_ERR(other_crtc_state)) | |
7088 | return PTR_ERR(other_crtc_state); | |
7089 | ||
7090 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 7091 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 7092 | return -EINVAL; |
1857e1da | 7093 | } |
6d293983 | 7094 | return 0; |
1857e1da DV |
7095 | default: |
7096 | BUG(); | |
7097 | } | |
7098 | } | |
7099 | ||
e29c22c0 DV |
7100 | #define RETRY 1 |
7101 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 7102 | struct intel_crtc_state *pipe_config) |
877d48d5 | 7103 | { |
1857e1da | 7104 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 7105 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
7106 | int lane, link_bw, fdi_dotclock, ret; |
7107 | bool needs_recompute = false; | |
877d48d5 | 7108 | |
e29c22c0 | 7109 | retry: |
877d48d5 DV |
7110 | /* FDI is a binary signal running at ~2.7GHz, encoding |
7111 | * each output octet as 10 bits. The actual frequency | |
7112 | * is stored as a divider into a 100MHz clock, and the | |
7113 | * mode pixel clock is stored in units of 1KHz. | |
7114 | * Hence the bw of each lane in terms of the mode signal | |
7115 | * is: | |
7116 | */ | |
21a727b3 | 7117 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 7118 | |
241bfc38 | 7119 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 7120 | |
2bd89a07 | 7121 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
7122 | pipe_config->pipe_bpp); |
7123 | ||
7124 | pipe_config->fdi_lanes = lane; | |
7125 | ||
2bd89a07 | 7126 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 7127 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 7128 | |
e3b247da | 7129 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 7130 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
7131 | pipe_config->pipe_bpp -= 2*3; |
7132 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
7133 | pipe_config->pipe_bpp); | |
7134 | needs_recompute = true; | |
7135 | pipe_config->bw_constrained = true; | |
7136 | ||
7137 | goto retry; | |
7138 | } | |
7139 | ||
7140 | if (needs_recompute) | |
7141 | return RETRY; | |
7142 | ||
6d293983 | 7143 | return ret; |
877d48d5 DV |
7144 | } |
7145 | ||
8cfb3407 VS |
7146 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
7147 | struct intel_crtc_state *pipe_config) | |
7148 | { | |
7149 | if (pipe_config->pipe_bpp > 24) | |
7150 | return false; | |
7151 | ||
7152 | /* HSW can handle pixel rate up to cdclk? */ | |
2d1fe073 | 7153 | if (IS_HASWELL(dev_priv)) |
8cfb3407 VS |
7154 | return true; |
7155 | ||
7156 | /* | |
b432e5cf VS |
7157 | * We compare against max which means we must take |
7158 | * the increased cdclk requirement into account when | |
7159 | * calculating the new cdclk. | |
7160 | * | |
7161 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
7162 | */ |
7163 | return ilk_pipe_pixel_rate(pipe_config) <= | |
7164 | dev_priv->max_cdclk_freq * 95 / 100; | |
7165 | } | |
7166 | ||
42db64ef | 7167 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 7168 | struct intel_crtc_state *pipe_config) |
42db64ef | 7169 | { |
8cfb3407 | 7170 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7171 | struct drm_i915_private *dev_priv = to_i915(dev); |
8cfb3407 | 7172 | |
d330a953 | 7173 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
7174 | hsw_crtc_supports_ips(crtc) && |
7175 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
7176 | } |
7177 | ||
39acb4aa VS |
7178 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
7179 | { | |
7180 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
7181 | ||
7182 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
7183 | return INTEL_INFO(dev_priv)->gen < 4 && | |
7184 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
7185 | } | |
7186 | ||
a43f6e0f | 7187 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 7188 | struct intel_crtc_state *pipe_config) |
79e53945 | 7189 | { |
a43f6e0f | 7190 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7191 | struct drm_i915_private *dev_priv = to_i915(dev); |
7c5f93b0 | 7192 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
f3261156 | 7193 | int clock_limit = dev_priv->max_dotclk_freq; |
89749350 | 7194 | |
cf532bb2 | 7195 | if (INTEL_INFO(dev)->gen < 4) { |
f3261156 | 7196 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
7197 | |
7198 | /* | |
39acb4aa | 7199 | * Enable double wide mode when the dot clock |
cf532bb2 | 7200 | * is > 90% of the (display) core speed. |
cf532bb2 | 7201 | */ |
39acb4aa VS |
7202 | if (intel_crtc_supports_double_wide(crtc) && |
7203 | adjusted_mode->crtc_clock > clock_limit) { | |
f3261156 | 7204 | clock_limit = dev_priv->max_dotclk_freq; |
cf532bb2 | 7205 | pipe_config->double_wide = true; |
ad3a4479 | 7206 | } |
f3261156 | 7207 | } |
ad3a4479 | 7208 | |
f3261156 VS |
7209 | if (adjusted_mode->crtc_clock > clock_limit) { |
7210 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
7211 | adjusted_mode->crtc_clock, clock_limit, | |
7212 | yesno(pipe_config->double_wide)); | |
7213 | return -EINVAL; | |
2c07245f | 7214 | } |
89749350 | 7215 | |
1d1d0e27 VS |
7216 | /* |
7217 | * Pipe horizontal size must be even in: | |
7218 | * - DVO ganged mode | |
7219 | * - LVDS dual channel mode | |
7220 | * - Double wide pipe | |
7221 | */ | |
2d84d2b3 | 7222 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
7223 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
7224 | pipe_config->pipe_src_w &= ~1; | |
7225 | ||
8693a824 DL |
7226 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
7227 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 | 7228 | */ |
9beb5fea | 7229 | if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && |
aad941d5 | 7230 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 7231 | return -EINVAL; |
44f46b42 | 7232 | |
50a0bc90 | 7233 | if (HAS_IPS(dev_priv)) |
a43f6e0f DV |
7234 | hsw_compute_ips_config(crtc, pipe_config); |
7235 | ||
877d48d5 | 7236 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 7237 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 7238 | |
cf5a15be | 7239 | return 0; |
79e53945 JB |
7240 | } |
7241 | ||
1353c4fb | 7242 | static int skylake_get_display_clock_speed(struct drm_i915_private *dev_priv) |
1652d19e | 7243 | { |
1353c4fb | 7244 | u32 cdctl; |
1652d19e | 7245 | |
ea61791e | 7246 | skl_dpll0_update(dev_priv); |
1652d19e | 7247 | |
63911d72 | 7248 | if (dev_priv->cdclk_pll.vco == 0) |
709e05c3 | 7249 | return dev_priv->cdclk_pll.ref; |
1652d19e | 7250 | |
ea61791e | 7251 | cdctl = I915_READ(CDCLK_CTL); |
1652d19e | 7252 | |
63911d72 | 7253 | if (dev_priv->cdclk_pll.vco == 8640000) { |
1652d19e VS |
7254 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
7255 | case CDCLK_FREQ_450_432: | |
7256 | return 432000; | |
7257 | case CDCLK_FREQ_337_308: | |
487ed2e4 | 7258 | return 308571; |
ea61791e VS |
7259 | case CDCLK_FREQ_540: |
7260 | return 540000; | |
1652d19e | 7261 | case CDCLK_FREQ_675_617: |
487ed2e4 | 7262 | return 617143; |
1652d19e | 7263 | default: |
ea61791e | 7264 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
7265 | } |
7266 | } else { | |
1652d19e VS |
7267 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { |
7268 | case CDCLK_FREQ_450_432: | |
7269 | return 450000; | |
7270 | case CDCLK_FREQ_337_308: | |
7271 | return 337500; | |
ea61791e VS |
7272 | case CDCLK_FREQ_540: |
7273 | return 540000; | |
1652d19e VS |
7274 | case CDCLK_FREQ_675_617: |
7275 | return 675000; | |
7276 | default: | |
ea61791e | 7277 | MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); |
1652d19e VS |
7278 | } |
7279 | } | |
7280 | ||
709e05c3 | 7281 | return dev_priv->cdclk_pll.ref; |
1652d19e VS |
7282 | } |
7283 | ||
83d7c81f VS |
7284 | static void bxt_de_pll_update(struct drm_i915_private *dev_priv) |
7285 | { | |
7286 | u32 val; | |
7287 | ||
7288 | dev_priv->cdclk_pll.ref = 19200; | |
1c3f7700 | 7289 | dev_priv->cdclk_pll.vco = 0; |
83d7c81f VS |
7290 | |
7291 | val = I915_READ(BXT_DE_PLL_ENABLE); | |
1c3f7700 | 7292 | if ((val & BXT_DE_PLL_PLL_ENABLE) == 0) |
83d7c81f | 7293 | return; |
83d7c81f | 7294 | |
1c3f7700 ID |
7295 | if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0)) |
7296 | return; | |
83d7c81f VS |
7297 | |
7298 | val = I915_READ(BXT_DE_PLL_CTL); | |
7299 | dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) * | |
7300 | dev_priv->cdclk_pll.ref; | |
7301 | } | |
7302 | ||
1353c4fb | 7303 | static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv) |
acd3f3d3 | 7304 | { |
f5986242 VS |
7305 | u32 divider; |
7306 | int div, vco; | |
acd3f3d3 | 7307 | |
83d7c81f VS |
7308 | bxt_de_pll_update(dev_priv); |
7309 | ||
f5986242 VS |
7310 | vco = dev_priv->cdclk_pll.vco; |
7311 | if (vco == 0) | |
7312 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 | 7313 | |
f5986242 | 7314 | divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; |
acd3f3d3 | 7315 | |
f5986242 | 7316 | switch (divider) { |
acd3f3d3 | 7317 | case BXT_CDCLK_CD2X_DIV_SEL_1: |
f5986242 VS |
7318 | div = 2; |
7319 | break; | |
acd3f3d3 | 7320 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: |
f5986242 VS |
7321 | div = 3; |
7322 | break; | |
acd3f3d3 | 7323 | case BXT_CDCLK_CD2X_DIV_SEL_2: |
f5986242 VS |
7324 | div = 4; |
7325 | break; | |
acd3f3d3 | 7326 | case BXT_CDCLK_CD2X_DIV_SEL_4: |
f5986242 VS |
7327 | div = 8; |
7328 | break; | |
7329 | default: | |
7330 | MISSING_CASE(divider); | |
7331 | return dev_priv->cdclk_pll.ref; | |
acd3f3d3 BP |
7332 | } |
7333 | ||
f5986242 | 7334 | return DIV_ROUND_CLOSEST(vco, div); |
acd3f3d3 BP |
7335 | } |
7336 | ||
1353c4fb | 7337 | static int broadwell_get_display_clock_speed(struct drm_i915_private *dev_priv) |
1652d19e | 7338 | { |
1652d19e VS |
7339 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
7340 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
7341 | ||
7342 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
7343 | return 800000; | |
7344 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
7345 | return 450000; | |
7346 | else if (freq == LCPLL_CLK_FREQ_450) | |
7347 | return 450000; | |
7348 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
7349 | return 540000; | |
7350 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
7351 | return 337500; | |
7352 | else | |
7353 | return 675000; | |
7354 | } | |
7355 | ||
1353c4fb | 7356 | static int haswell_get_display_clock_speed(struct drm_i915_private *dev_priv) |
1652d19e | 7357 | { |
1652d19e VS |
7358 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
7359 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
7360 | ||
7361 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
7362 | return 800000; | |
7363 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
7364 | return 450000; | |
7365 | else if (freq == LCPLL_CLK_FREQ_450) | |
7366 | return 450000; | |
50a0bc90 | 7367 | else if (IS_HSW_ULT(dev_priv)) |
1652d19e VS |
7368 | return 337500; |
7369 | else | |
7370 | return 540000; | |
79e53945 JB |
7371 | } |
7372 | ||
1353c4fb | 7373 | static int valleyview_get_display_clock_speed(struct drm_i915_private *dev_priv) |
25eb05fc | 7374 | { |
1353c4fb | 7375 | return vlv_get_cck_clock_hpll(dev_priv, "cdclk", |
bfa7df01 | 7376 | CCK_DISPLAY_CLOCK_CONTROL); |
25eb05fc JB |
7377 | } |
7378 | ||
1353c4fb | 7379 | static int ilk_get_display_clock_speed(struct drm_i915_private *dev_priv) |
b37a6434 VS |
7380 | { |
7381 | return 450000; | |
7382 | } | |
7383 | ||
1353c4fb | 7384 | static int i945_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 JB |
7385 | { |
7386 | return 400000; | |
7387 | } | |
79e53945 | 7388 | |
1353c4fb | 7389 | static int i915_get_display_clock_speed(struct drm_i915_private *dev_priv) |
79e53945 | 7390 | { |
e907f170 | 7391 | return 333333; |
e70236a8 | 7392 | } |
79e53945 | 7393 | |
1353c4fb | 7394 | static int i9xx_misc_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 JB |
7395 | { |
7396 | return 200000; | |
7397 | } | |
79e53945 | 7398 | |
1353c4fb | 7399 | static int pnv_get_display_clock_speed(struct drm_i915_private *dev_priv) |
257a7ffc | 7400 | { |
1353c4fb | 7401 | struct pci_dev *pdev = dev_priv->drm.pdev; |
257a7ffc DV |
7402 | u16 gcfgc = 0; |
7403 | ||
52a05c30 | 7404 | pci_read_config_word(pdev, GCFGC, &gcfgc); |
257a7ffc DV |
7405 | |
7406 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
7407 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 7408 | return 266667; |
257a7ffc | 7409 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 7410 | return 333333; |
257a7ffc | 7411 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 7412 | return 444444; |
257a7ffc DV |
7413 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
7414 | return 200000; | |
7415 | default: | |
7416 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
7417 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 7418 | return 133333; |
257a7ffc | 7419 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 7420 | return 166667; |
257a7ffc DV |
7421 | } |
7422 | } | |
7423 | ||
1353c4fb | 7424 | static int i915gm_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 | 7425 | { |
1353c4fb | 7426 | struct pci_dev *pdev = dev_priv->drm.pdev; |
e70236a8 | 7427 | u16 gcfgc = 0; |
79e53945 | 7428 | |
52a05c30 | 7429 | pci_read_config_word(pdev, GCFGC, &gcfgc); |
e70236a8 JB |
7430 | |
7431 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 7432 | return 133333; |
e70236a8 JB |
7433 | else { |
7434 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
7435 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 7436 | return 333333; |
e70236a8 JB |
7437 | default: |
7438 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
7439 | return 190000; | |
79e53945 | 7440 | } |
e70236a8 JB |
7441 | } |
7442 | } | |
7443 | ||
1353c4fb | 7444 | static int i865_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 | 7445 | { |
e907f170 | 7446 | return 266667; |
e70236a8 JB |
7447 | } |
7448 | ||
1353c4fb | 7449 | static int i85x_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 | 7450 | { |
1353c4fb | 7451 | struct pci_dev *pdev = dev_priv->drm.pdev; |
e70236a8 | 7452 | u16 hpllcc = 0; |
1b1d2716 | 7453 | |
65cd2b3f VS |
7454 | /* |
7455 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
7456 | * encoding is different :( | |
7457 | * FIXME is this the right way to detect 852GM/852GMV? | |
7458 | */ | |
52a05c30 | 7459 | if (pdev->revision == 0x1) |
65cd2b3f VS |
7460 | return 133333; |
7461 | ||
52a05c30 | 7462 | pci_bus_read_config_word(pdev->bus, |
1b1d2716 VS |
7463 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); |
7464 | ||
e70236a8 JB |
7465 | /* Assume that the hardware is in the high speed state. This |
7466 | * should be the default. | |
7467 | */ | |
7468 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
7469 | case GC_CLOCK_133_200: | |
1b1d2716 | 7470 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
7471 | case GC_CLOCK_100_200: |
7472 | return 200000; | |
7473 | case GC_CLOCK_166_250: | |
7474 | return 250000; | |
7475 | case GC_CLOCK_100_133: | |
e907f170 | 7476 | return 133333; |
1b1d2716 VS |
7477 | case GC_CLOCK_133_266: |
7478 | case GC_CLOCK_133_266_2: | |
7479 | case GC_CLOCK_166_266: | |
7480 | return 266667; | |
e70236a8 | 7481 | } |
79e53945 | 7482 | |
e70236a8 JB |
7483 | /* Shouldn't happen */ |
7484 | return 0; | |
7485 | } | |
79e53945 | 7486 | |
1353c4fb | 7487 | static int i830_get_display_clock_speed(struct drm_i915_private *dev_priv) |
e70236a8 | 7488 | { |
e907f170 | 7489 | return 133333; |
79e53945 JB |
7490 | } |
7491 | ||
1353c4fb | 7492 | static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) |
34edce2f | 7493 | { |
34edce2f VS |
7494 | static const unsigned int blb_vco[8] = { |
7495 | [0] = 3200000, | |
7496 | [1] = 4000000, | |
7497 | [2] = 5333333, | |
7498 | [3] = 4800000, | |
7499 | [4] = 6400000, | |
7500 | }; | |
7501 | static const unsigned int pnv_vco[8] = { | |
7502 | [0] = 3200000, | |
7503 | [1] = 4000000, | |
7504 | [2] = 5333333, | |
7505 | [3] = 4800000, | |
7506 | [4] = 2666667, | |
7507 | }; | |
7508 | static const unsigned int cl_vco[8] = { | |
7509 | [0] = 3200000, | |
7510 | [1] = 4000000, | |
7511 | [2] = 5333333, | |
7512 | [3] = 6400000, | |
7513 | [4] = 3333333, | |
7514 | [5] = 3566667, | |
7515 | [6] = 4266667, | |
7516 | }; | |
7517 | static const unsigned int elk_vco[8] = { | |
7518 | [0] = 3200000, | |
7519 | [1] = 4000000, | |
7520 | [2] = 5333333, | |
7521 | [3] = 4800000, | |
7522 | }; | |
7523 | static const unsigned int ctg_vco[8] = { | |
7524 | [0] = 3200000, | |
7525 | [1] = 4000000, | |
7526 | [2] = 5333333, | |
7527 | [3] = 6400000, | |
7528 | [4] = 2666667, | |
7529 | [5] = 4266667, | |
7530 | }; | |
7531 | const unsigned int *vco_table; | |
7532 | unsigned int vco; | |
7533 | uint8_t tmp = 0; | |
7534 | ||
7535 | /* FIXME other chipsets? */ | |
50a0bc90 | 7536 | if (IS_GM45(dev_priv)) |
34edce2f | 7537 | vco_table = ctg_vco; |
9beb5fea | 7538 | else if (IS_G4X(dev_priv)) |
34edce2f | 7539 | vco_table = elk_vco; |
1353c4fb | 7540 | else if (IS_CRESTLINE(dev_priv)) |
34edce2f | 7541 | vco_table = cl_vco; |
1353c4fb | 7542 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f | 7543 | vco_table = pnv_vco; |
1353c4fb | 7544 | else if (IS_G33(dev_priv)) |
34edce2f VS |
7545 | vco_table = blb_vco; |
7546 | else | |
7547 | return 0; | |
7548 | ||
1353c4fb | 7549 | tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); |
34edce2f VS |
7550 | |
7551 | vco = vco_table[tmp & 0x7]; | |
7552 | if (vco == 0) | |
7553 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7554 | else | |
7555 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7556 | ||
7557 | return vco; | |
7558 | } | |
7559 | ||
1353c4fb | 7560 | static int gm45_get_display_clock_speed(struct drm_i915_private *dev_priv) |
34edce2f | 7561 | { |
1353c4fb VS |
7562 | struct pci_dev *pdev = dev_priv->drm.pdev; |
7563 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv); | |
34edce2f VS |
7564 | uint16_t tmp = 0; |
7565 | ||
52a05c30 | 7566 | pci_read_config_word(pdev, GCFGC, &tmp); |
34edce2f VS |
7567 | |
7568 | cdclk_sel = (tmp >> 12) & 0x1; | |
7569 | ||
7570 | switch (vco) { | |
7571 | case 2666667: | |
7572 | case 4000000: | |
7573 | case 5333333: | |
7574 | return cdclk_sel ? 333333 : 222222; | |
7575 | case 3200000: | |
7576 | return cdclk_sel ? 320000 : 228571; | |
7577 | default: | |
7578 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7579 | return 222222; | |
7580 | } | |
7581 | } | |
7582 | ||
1353c4fb | 7583 | static int i965gm_get_display_clock_speed(struct drm_i915_private *dev_priv) |
34edce2f | 7584 | { |
1353c4fb | 7585 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34edce2f VS |
7586 | static const uint8_t div_3200[] = { 16, 10, 8 }; |
7587 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7588 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7589 | const uint8_t *div_table; | |
1353c4fb | 7590 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv); |
34edce2f VS |
7591 | uint16_t tmp = 0; |
7592 | ||
52a05c30 | 7593 | pci_read_config_word(pdev, GCFGC, &tmp); |
34edce2f VS |
7594 | |
7595 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7596 | ||
7597 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7598 | goto fail; | |
7599 | ||
7600 | switch (vco) { | |
7601 | case 3200000: | |
7602 | div_table = div_3200; | |
7603 | break; | |
7604 | case 4000000: | |
7605 | div_table = div_4000; | |
7606 | break; | |
7607 | case 5333333: | |
7608 | div_table = div_5333; | |
7609 | break; | |
7610 | default: | |
7611 | goto fail; | |
7612 | } | |
7613 | ||
7614 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7615 | ||
caf4e252 | 7616 | fail: |
34edce2f VS |
7617 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7618 | return 200000; | |
7619 | } | |
7620 | ||
1353c4fb | 7621 | static int g33_get_display_clock_speed(struct drm_i915_private *dev_priv) |
34edce2f | 7622 | { |
1353c4fb | 7623 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34edce2f VS |
7624 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; |
7625 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7626 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7627 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7628 | const uint8_t *div_table; | |
1353c4fb | 7629 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv); |
34edce2f VS |
7630 | uint16_t tmp = 0; |
7631 | ||
52a05c30 | 7632 | pci_read_config_word(pdev, GCFGC, &tmp); |
34edce2f VS |
7633 | |
7634 | cdclk_sel = (tmp >> 4) & 0x7; | |
7635 | ||
7636 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7637 | goto fail; | |
7638 | ||
7639 | switch (vco) { | |
7640 | case 3200000: | |
7641 | div_table = div_3200; | |
7642 | break; | |
7643 | case 4000000: | |
7644 | div_table = div_4000; | |
7645 | break; | |
7646 | case 4800000: | |
7647 | div_table = div_4800; | |
7648 | break; | |
7649 | case 5333333: | |
7650 | div_table = div_5333; | |
7651 | break; | |
7652 | default: | |
7653 | goto fail; | |
7654 | } | |
7655 | ||
7656 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7657 | ||
caf4e252 | 7658 | fail: |
34edce2f VS |
7659 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7660 | return 190476; | |
7661 | } | |
7662 | ||
2c07245f | 7663 | static void |
a65851af | 7664 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7665 | { |
a65851af VS |
7666 | while (*num > DATA_LINK_M_N_MASK || |
7667 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7668 | *num >>= 1; |
7669 | *den >>= 1; | |
7670 | } | |
7671 | } | |
7672 | ||
a65851af VS |
7673 | static void compute_m_n(unsigned int m, unsigned int n, |
7674 | uint32_t *ret_m, uint32_t *ret_n) | |
7675 | { | |
7676 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7677 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7678 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7679 | } | |
7680 | ||
e69d0bc1 DV |
7681 | void |
7682 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7683 | int pixel_clock, int link_clock, | |
7684 | struct intel_link_m_n *m_n) | |
2c07245f | 7685 | { |
e69d0bc1 | 7686 | m_n->tu = 64; |
a65851af VS |
7687 | |
7688 | compute_m_n(bits_per_pixel * pixel_clock, | |
7689 | link_clock * nlanes * 8, | |
7690 | &m_n->gmch_m, &m_n->gmch_n); | |
7691 | ||
7692 | compute_m_n(pixel_clock, link_clock, | |
7693 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7694 | } |
7695 | ||
a7615030 CW |
7696 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7697 | { | |
d330a953 JN |
7698 | if (i915.panel_use_ssc >= 0) |
7699 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7700 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7701 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7702 | } |
7703 | ||
7429e9d4 | 7704 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7705 | { |
7df00d7a | 7706 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7707 | } |
f47709a9 | 7708 | |
7429e9d4 DV |
7709 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7710 | { | |
7711 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7712 | } |
7713 | ||
f47709a9 | 7714 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7715 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 7716 | struct dpll *reduced_clock) |
a7516a05 | 7717 | { |
9b1e14f4 | 7718 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
a7516a05 JB |
7719 | u32 fp, fp2 = 0; |
7720 | ||
9b1e14f4 | 7721 | if (IS_PINEVIEW(dev_priv)) { |
190f68c5 | 7722 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7723 | if (reduced_clock) |
7429e9d4 | 7724 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7725 | } else { |
190f68c5 | 7726 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7727 | if (reduced_clock) |
7429e9d4 | 7728 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7729 | } |
7730 | ||
190f68c5 | 7731 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7732 | |
f47709a9 | 7733 | crtc->lowfreq_avail = false; |
2d84d2b3 | 7734 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7735 | reduced_clock) { |
190f68c5 | 7736 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7737 | crtc->lowfreq_avail = true; |
a7516a05 | 7738 | } else { |
190f68c5 | 7739 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7740 | } |
7741 | } | |
7742 | ||
5e69f97f CML |
7743 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7744 | pipe) | |
89b667f8 JB |
7745 | { |
7746 | u32 reg_val; | |
7747 | ||
7748 | /* | |
7749 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7750 | * and set it to a reasonable value instead. | |
7751 | */ | |
ab3c759a | 7752 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7753 | reg_val &= 0xffffff00; |
7754 | reg_val |= 0x00000030; | |
ab3c759a | 7755 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7756 | |
ab3c759a | 7757 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7758 | reg_val &= 0x8cffffff; |
7759 | reg_val = 0x8c000000; | |
ab3c759a | 7760 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7761 | |
ab3c759a | 7762 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7763 | reg_val &= 0xffffff00; |
ab3c759a | 7764 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7765 | |
ab3c759a | 7766 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7767 | reg_val &= 0x00ffffff; |
7768 | reg_val |= 0xb0000000; | |
ab3c759a | 7769 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7770 | } |
7771 | ||
b551842d DV |
7772 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7773 | struct intel_link_m_n *m_n) | |
7774 | { | |
7775 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7776 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
7777 | int pipe = crtc->pipe; |
7778 | ||
e3b95f1e DV |
7779 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7780 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7781 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7782 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7783 | } |
7784 | ||
7785 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7786 | struct intel_link_m_n *m_n, |
7787 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7788 | { |
7789 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7790 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d | 7791 | int pipe = crtc->pipe; |
6e3c9717 | 7792 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7793 | |
7794 | if (INTEL_INFO(dev)->gen >= 5) { | |
7795 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7796 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7797 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7798 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7799 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7800 | * for gen < 8) and if DRRS is supported (to make sure the | |
7801 | * registers are not unnecessarily accessed). | |
7802 | */ | |
920a14b2 TU |
7803 | if (m2_n2 && (IS_CHERRYVIEW(dev_priv) || |
7804 | INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) { | |
f769cd24 VK |
7805 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7806 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7807 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7808 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7809 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7810 | } | |
b551842d | 7811 | } else { |
e3b95f1e DV |
7812 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7813 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7814 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7815 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7816 | } |
7817 | } | |
7818 | ||
fe3cd48d | 7819 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7820 | { |
fe3cd48d R |
7821 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7822 | ||
7823 | if (m_n == M1_N1) { | |
7824 | dp_m_n = &crtc->config->dp_m_n; | |
7825 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7826 | } else if (m_n == M2_N2) { | |
7827 | ||
7828 | /* | |
7829 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7830 | * needs to be programmed into M1_N1. | |
7831 | */ | |
7832 | dp_m_n = &crtc->config->dp_m2_n2; | |
7833 | } else { | |
7834 | DRM_ERROR("Unsupported divider value\n"); | |
7835 | return; | |
7836 | } | |
7837 | ||
6e3c9717 ACO |
7838 | if (crtc->config->has_pch_encoder) |
7839 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7840 | else |
fe3cd48d | 7841 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7842 | } |
7843 | ||
251ac862 DV |
7844 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7845 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 7846 | { |
03ed5cbf | 7847 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 7848 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7849 | if (crtc->pipe != PIPE_A) |
7850 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 7851 | |
cd2d34d9 | 7852 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 7853 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
7854 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
7855 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
7856 | ||
03ed5cbf VS |
7857 | pipe_config->dpll_hw_state.dpll_md = |
7858 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
7859 | } | |
bdd4b6a6 | 7860 | |
03ed5cbf VS |
7861 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7862 | struct intel_crtc_state *pipe_config) | |
7863 | { | |
7864 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 7865 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7866 | if (crtc->pipe != PIPE_A) |
7867 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7868 | ||
cd2d34d9 | 7869 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 7870 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
7871 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
7872 | ||
03ed5cbf VS |
7873 | pipe_config->dpll_hw_state.dpll_md = |
7874 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
7875 | } |
7876 | ||
d288f65f | 7877 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7878 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7879 | { |
f47709a9 | 7880 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7881 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 7882 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 7883 | u32 mdiv; |
a0c4da24 | 7884 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7885 | u32 coreclk, reg_val; |
a0c4da24 | 7886 | |
cd2d34d9 VS |
7887 | /* Enable Refclk */ |
7888 | I915_WRITE(DPLL(pipe), | |
7889 | pipe_config->dpll_hw_state.dpll & | |
7890 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
7891 | ||
7892 | /* No need to actually set up the DPLL with DSI */ | |
7893 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7894 | return; | |
7895 | ||
a580516d | 7896 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7897 | |
d288f65f VS |
7898 | bestn = pipe_config->dpll.n; |
7899 | bestm1 = pipe_config->dpll.m1; | |
7900 | bestm2 = pipe_config->dpll.m2; | |
7901 | bestp1 = pipe_config->dpll.p1; | |
7902 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7903 | |
89b667f8 JB |
7904 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7905 | ||
7906 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7907 | if (pipe == PIPE_B) |
5e69f97f | 7908 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7909 | |
7910 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7911 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7912 | |
7913 | /* Disable target IRef on PLL */ | |
ab3c759a | 7914 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7915 | reg_val &= 0x00ffffff; |
ab3c759a | 7916 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7917 | |
7918 | /* Disable fast lock */ | |
ab3c759a | 7919 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7920 | |
7921 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7922 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7923 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7924 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7925 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7926 | |
7927 | /* | |
7928 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7929 | * but we don't support that). | |
7930 | * Note: don't use the DAC post divider as it seems unstable. | |
7931 | */ | |
7932 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7933 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7934 | |
a0c4da24 | 7935 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7936 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7937 | |
89b667f8 | 7938 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7939 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
7940 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
7941 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7942 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7943 | 0x009f0003); |
89b667f8 | 7944 | else |
ab3c759a | 7945 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7946 | 0x00d0000f); |
7947 | ||
37a5650b | 7948 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 7949 | /* Use SSC source */ |
bdd4b6a6 | 7950 | if (pipe == PIPE_A) |
ab3c759a | 7951 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7952 | 0x0df40000); |
7953 | else | |
ab3c759a | 7954 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7955 | 0x0df70000); |
7956 | } else { /* HDMI or VGA */ | |
7957 | /* Use bend source */ | |
bdd4b6a6 | 7958 | if (pipe == PIPE_A) |
ab3c759a | 7959 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7960 | 0x0df70000); |
7961 | else | |
ab3c759a | 7962 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7963 | 0x0df40000); |
7964 | } | |
a0c4da24 | 7965 | |
ab3c759a | 7966 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7967 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 7968 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 7969 | coreclk |= 0x01000000; |
ab3c759a | 7970 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7971 | |
ab3c759a | 7972 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7973 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7974 | } |
7975 | ||
d288f65f | 7976 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7977 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7978 | { |
7979 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7980 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 7981 | enum pipe pipe = crtc->pipe; |
9d556c99 | 7982 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7983 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7984 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7985 | u32 dpio_val; |
9cbe40c1 | 7986 | int vco; |
9d556c99 | 7987 | |
cd2d34d9 VS |
7988 | /* Enable Refclk and SSC */ |
7989 | I915_WRITE(DPLL(pipe), | |
7990 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
7991 | ||
7992 | /* No need to actually set up the DPLL with DSI */ | |
7993 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7994 | return; | |
7995 | ||
d288f65f VS |
7996 | bestn = pipe_config->dpll.n; |
7997 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7998 | bestm1 = pipe_config->dpll.m1; | |
7999 | bestm2 = pipe_config->dpll.m2 >> 22; | |
8000 | bestp1 = pipe_config->dpll.p1; | |
8001 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 8002 | vco = pipe_config->dpll.vco; |
a945ce7e | 8003 | dpio_val = 0; |
9cbe40c1 | 8004 | loopfilter = 0; |
9d556c99 | 8005 | |
a580516d | 8006 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 8007 | |
9d556c99 CML |
8008 | /* p1 and p2 divider */ |
8009 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
8010 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
8011 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
8012 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
8013 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
8014 | ||
8015 | /* Feedback post-divider - m2 */ | |
8016 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
8017 | ||
8018 | /* Feedback refclk divider - n and m1 */ | |
8019 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
8020 | DPIO_CHV_M1_DIV_BY_2 | | |
8021 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
8022 | ||
8023 | /* M2 fraction division */ | |
25a25dfc | 8024 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
8025 | |
8026 | /* M2 fraction division enable */ | |
a945ce7e VP |
8027 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
8028 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
8029 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
8030 | if (bestm2_frac) | |
8031 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
8032 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 8033 | |
de3a0fde VP |
8034 | /* Program digital lock detect threshold */ |
8035 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
8036 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
8037 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
8038 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
8039 | if (!bestm2_frac) | |
8040 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
8041 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
8042 | ||
9d556c99 | 8043 | /* Loop filter */ |
9cbe40c1 VP |
8044 | if (vco == 5400000) { |
8045 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8046 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
8047 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8048 | tribuf_calcntr = 0x9; | |
8049 | } else if (vco <= 6200000) { | |
8050 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8051 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
8052 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8053 | tribuf_calcntr = 0x9; | |
8054 | } else if (vco <= 6480000) { | |
8055 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8056 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
8057 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8058 | tribuf_calcntr = 0x8; | |
8059 | } else { | |
8060 | /* Not supported. Apply the same limits as in the max case */ | |
8061 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
8062 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
8063 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
8064 | tribuf_calcntr = 0; | |
8065 | } | |
9d556c99 CML |
8066 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
8067 | ||
968040b2 | 8068 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
8069 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
8070 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
8071 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
8072 | ||
9d556c99 CML |
8073 | /* AFC Recal */ |
8074 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
8075 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
8076 | DPIO_AFC_RECAL); | |
8077 | ||
a580516d | 8078 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
8079 | } |
8080 | ||
d288f65f VS |
8081 | /** |
8082 | * vlv_force_pll_on - forcibly enable just the PLL | |
8083 | * @dev_priv: i915 private structure | |
8084 | * @pipe: pipe PLL to enable | |
8085 | * @dpll: PLL configuration | |
8086 | * | |
8087 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
8088 | * in cases where we need the PLL enabled even when @pipe is not going to | |
8089 | * be enabled. | |
8090 | */ | |
30ad9814 | 8091 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 8092 | const struct dpll *dpll) |
d288f65f | 8093 | { |
b91eb5cc | 8094 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
3f36b937 TU |
8095 | struct intel_crtc_state *pipe_config; |
8096 | ||
8097 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
8098 | if (!pipe_config) | |
8099 | return -ENOMEM; | |
8100 | ||
8101 | pipe_config->base.crtc = &crtc->base; | |
8102 | pipe_config->pixel_multiplier = 1; | |
8103 | pipe_config->dpll = *dpll; | |
d288f65f | 8104 | |
30ad9814 | 8105 | if (IS_CHERRYVIEW(dev_priv)) { |
3f36b937 TU |
8106 | chv_compute_dpll(crtc, pipe_config); |
8107 | chv_prepare_pll(crtc, pipe_config); | |
8108 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 8109 | } else { |
3f36b937 TU |
8110 | vlv_compute_dpll(crtc, pipe_config); |
8111 | vlv_prepare_pll(crtc, pipe_config); | |
8112 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 8113 | } |
3f36b937 TU |
8114 | |
8115 | kfree(pipe_config); | |
8116 | ||
8117 | return 0; | |
d288f65f VS |
8118 | } |
8119 | ||
8120 | /** | |
8121 | * vlv_force_pll_off - forcibly disable just the PLL | |
8122 | * @dev_priv: i915 private structure | |
8123 | * @pipe: pipe PLL to disable | |
8124 | * | |
8125 | * Disable the PLL for @pipe. To be used in cases where we need | |
8126 | * the PLL enabled even when @pipe is not going to be enabled. | |
8127 | */ | |
30ad9814 | 8128 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) |
d288f65f | 8129 | { |
30ad9814 VS |
8130 | if (IS_CHERRYVIEW(dev_priv)) |
8131 | chv_disable_pll(dev_priv, pipe); | |
d288f65f | 8132 | else |
30ad9814 | 8133 | vlv_disable_pll(dev_priv, pipe); |
d288f65f VS |
8134 | } |
8135 | ||
251ac862 DV |
8136 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
8137 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8138 | struct dpll *reduced_clock) |
eb1cbe48 | 8139 | { |
9b1e14f4 | 8140 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb1cbe48 | 8141 | u32 dpll; |
190f68c5 | 8142 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 8143 | |
190f68c5 | 8144 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 8145 | |
eb1cbe48 DV |
8146 | dpll = DPLL_VGA_MODE_DIS; |
8147 | ||
2d84d2b3 | 8148 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
8149 | dpll |= DPLLB_MODE_LVDS; |
8150 | else | |
8151 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 8152 | |
50a0bc90 | 8153 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv)) { |
190f68c5 | 8154 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 8155 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 8156 | } |
198a037f | 8157 | |
3d6e9ee0 VS |
8158 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8159 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8160 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 8161 | |
37a5650b | 8162 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8163 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
8164 | |
8165 | /* compute bitmask from p1 value */ | |
9b1e14f4 | 8166 | if (IS_PINEVIEW(dev_priv)) |
eb1cbe48 DV |
8167 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
8168 | else { | |
8169 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
9beb5fea | 8170 | if (IS_G4X(dev_priv) && reduced_clock) |
eb1cbe48 DV |
8171 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
8172 | } | |
8173 | switch (clock->p2) { | |
8174 | case 5: | |
8175 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8176 | break; | |
8177 | case 7: | |
8178 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8179 | break; | |
8180 | case 10: | |
8181 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8182 | break; | |
8183 | case 14: | |
8184 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8185 | break; | |
8186 | } | |
9b1e14f4 | 8187 | if (INTEL_GEN(dev_priv) >= 4) |
eb1cbe48 DV |
8188 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
8189 | ||
190f68c5 | 8190 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 8191 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 8192 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 8193 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
8194 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
8195 | else | |
8196 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8197 | ||
8198 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 8199 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 8200 | |
9b1e14f4 | 8201 | if (INTEL_GEN(dev_priv) >= 4) { |
190f68c5 | 8202 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8203 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 8204 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
8205 | } |
8206 | } | |
8207 | ||
251ac862 DV |
8208 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
8209 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8210 | struct dpll *reduced_clock) |
eb1cbe48 | 8211 | { |
f47709a9 | 8212 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8213 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 8214 | u32 dpll; |
190f68c5 | 8215 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 8216 | |
190f68c5 | 8217 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 8218 | |
eb1cbe48 DV |
8219 | dpll = DPLL_VGA_MODE_DIS; |
8220 | ||
2d84d2b3 | 8221 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
8222 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
8223 | } else { | |
8224 | if (clock->p1 == 2) | |
8225 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
8226 | else | |
8227 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
8228 | if (clock->p2 == 4) | |
8229 | dpll |= PLL_P2_DIVIDE_BY_4; | |
8230 | } | |
8231 | ||
50a0bc90 TU |
8232 | if (!IS_I830(dev_priv) && |
8233 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) | |
4a33e48d DV |
8234 | dpll |= DPLL_DVO_2X_MODE; |
8235 | ||
2d84d2b3 | 8236 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 8237 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
8238 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
8239 | else | |
8240 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8241 | ||
8242 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 8243 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
8244 | } |
8245 | ||
8a654f3b | 8246 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
8247 | { |
8248 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 8249 | struct drm_i915_private *dev_priv = to_i915(dev); |
b0e77b9c | 8250 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8251 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 8252 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
8253 | uint32_t crtc_vtotal, crtc_vblank_end; |
8254 | int vsyncshift = 0; | |
4d8a62ea DV |
8255 | |
8256 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
8257 | * the hw state checker will get angry at the mismatch. */ | |
8258 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
8259 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 8260 | |
609aeaca | 8261 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 8262 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
8263 | crtc_vtotal -= 1; |
8264 | crtc_vblank_end -= 1; | |
609aeaca | 8265 | |
2d84d2b3 | 8266 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
8267 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
8268 | else | |
8269 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
8270 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
8271 | if (vsyncshift < 0) |
8272 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
8273 | } |
8274 | ||
8275 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 8276 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 8277 | |
fe2b8f9d | 8278 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
8279 | (adjusted_mode->crtc_hdisplay - 1) | |
8280 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 8281 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
8282 | (adjusted_mode->crtc_hblank_start - 1) | |
8283 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 8284 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
8285 | (adjusted_mode->crtc_hsync_start - 1) | |
8286 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
8287 | ||
fe2b8f9d | 8288 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 8289 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 8290 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 8291 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 8292 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 8293 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 8294 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
8295 | (adjusted_mode->crtc_vsync_start - 1) | |
8296 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
8297 | ||
b5e508d4 PZ |
8298 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
8299 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
8300 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
8301 | * bits. */ | |
772c2a51 | 8302 | if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && |
b5e508d4 PZ |
8303 | (pipe == PIPE_B || pipe == PIPE_C)) |
8304 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
8305 | ||
bc58be60 JN |
8306 | } |
8307 | ||
8308 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
8309 | { | |
8310 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 8311 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
8312 | enum pipe pipe = intel_crtc->pipe; |
8313 | ||
b0e77b9c PZ |
8314 | /* pipesrc controls the size that is scaled from, which should |
8315 | * always be the user's requested size. | |
8316 | */ | |
8317 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
8318 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
8319 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
8320 | } |
8321 | ||
1bd1bd80 | 8322 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 8323 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
8324 | { |
8325 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8326 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
8327 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
8328 | uint32_t tmp; | |
8329 | ||
8330 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
8331 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
8332 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8333 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
8334 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
8335 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8336 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
8337 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
8338 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
8339 | |
8340 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
8341 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
8342 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8343 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
8344 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
8345 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 8346 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
8347 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
8348 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
8349 | |
8350 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
8351 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
8352 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
8353 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 8354 | } |
bc58be60 JN |
8355 | } |
8356 | ||
8357 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
8358 | struct intel_crtc_state *pipe_config) | |
8359 | { | |
8360 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8361 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 8362 | u32 tmp; |
1bd1bd80 DV |
8363 | |
8364 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
8365 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
8366 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
8367 | ||
2d112de7 ACO |
8368 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
8369 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
8370 | } |
8371 | ||
f6a83288 | 8372 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 8373 | struct intel_crtc_state *pipe_config) |
babea61d | 8374 | { |
2d112de7 ACO |
8375 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
8376 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
8377 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
8378 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 8379 | |
2d112de7 ACO |
8380 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
8381 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
8382 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
8383 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 8384 | |
2d112de7 | 8385 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 8386 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 8387 | |
2d112de7 ACO |
8388 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
8389 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
8390 | |
8391 | mode->hsync = drm_mode_hsync(mode); | |
8392 | mode->vrefresh = drm_mode_vrefresh(mode); | |
8393 | drm_mode_set_name(mode); | |
babea61d JB |
8394 | } |
8395 | ||
84b046f3 DV |
8396 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
8397 | { | |
8398 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 8399 | struct drm_i915_private *dev_priv = to_i915(dev); |
84b046f3 DV |
8400 | uint32_t pipeconf; |
8401 | ||
9f11a9e4 | 8402 | pipeconf = 0; |
84b046f3 | 8403 | |
b6b5d049 VS |
8404 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
8405 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8406 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 8407 | |
6e3c9717 | 8408 | if (intel_crtc->config->double_wide) |
cf532bb2 | 8409 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 8410 | |
ff9ce46e | 8411 | /* only g4x and later have fancy bpc/dither controls */ |
9beb5fea TU |
8412 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
8413 | IS_CHERRYVIEW(dev_priv)) { | |
ff9ce46e | 8414 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 8415 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 8416 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 8417 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 8418 | |
6e3c9717 | 8419 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
8420 | case 18: |
8421 | pipeconf |= PIPECONF_6BPC; | |
8422 | break; | |
8423 | case 24: | |
8424 | pipeconf |= PIPECONF_8BPC; | |
8425 | break; | |
8426 | case 30: | |
8427 | pipeconf |= PIPECONF_10BPC; | |
8428 | break; | |
8429 | default: | |
8430 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
8431 | BUG(); | |
84b046f3 DV |
8432 | } |
8433 | } | |
8434 | ||
8435 | if (HAS_PIPE_CXSR(dev)) { | |
8436 | if (intel_crtc->lowfreq_avail) { | |
8437 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
8438 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
8439 | } else { | |
8440 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
8441 | } |
8442 | } | |
8443 | ||
6e3c9717 | 8444 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 8445 | if (INTEL_INFO(dev)->gen < 4 || |
2d84d2b3 | 8446 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
8447 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
8448 | else | |
8449 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
8450 | } else | |
84b046f3 DV |
8451 | pipeconf |= PIPECONF_PROGRESSIVE; |
8452 | ||
920a14b2 | 8453 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 8454 | intel_crtc->config->limited_color_range) |
9f11a9e4 | 8455 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 8456 | |
84b046f3 DV |
8457 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
8458 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
8459 | } | |
8460 | ||
81c97f52 ACO |
8461 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
8462 | struct intel_crtc_state *crtc_state) | |
8463 | { | |
8464 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8465 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8466 | const struct intel_limit *limit; |
81c97f52 ACO |
8467 | int refclk = 48000; |
8468 | ||
8469 | memset(&crtc_state->dpll_hw_state, 0, | |
8470 | sizeof(crtc_state->dpll_hw_state)); | |
8471 | ||
2d84d2b3 | 8472 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
8473 | if (intel_panel_use_ssc(dev_priv)) { |
8474 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8475 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8476 | } | |
8477 | ||
8478 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 8479 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
8480 | limit = &intel_limits_i8xx_dvo; |
8481 | } else { | |
8482 | limit = &intel_limits_i8xx_dac; | |
8483 | } | |
8484 | ||
8485 | if (!crtc_state->clock_set && | |
8486 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8487 | refclk, NULL, &crtc_state->dpll)) { | |
8488 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8489 | return -EINVAL; | |
8490 | } | |
8491 | ||
8492 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
8493 | ||
8494 | return 0; | |
8495 | } | |
8496 | ||
19ec6693 ACO |
8497 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
8498 | struct intel_crtc_state *crtc_state) | |
8499 | { | |
8500 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8501 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8502 | const struct intel_limit *limit; |
19ec6693 ACO |
8503 | int refclk = 96000; |
8504 | ||
8505 | memset(&crtc_state->dpll_hw_state, 0, | |
8506 | sizeof(crtc_state->dpll_hw_state)); | |
8507 | ||
2d84d2b3 | 8508 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
8509 | if (intel_panel_use_ssc(dev_priv)) { |
8510 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8511 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8512 | } | |
8513 | ||
8514 | if (intel_is_dual_link_lvds(dev)) | |
8515 | limit = &intel_limits_g4x_dual_channel_lvds; | |
8516 | else | |
8517 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
8518 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
8519 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 8520 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 8521 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
8522 | limit = &intel_limits_g4x_sdvo; |
8523 | } else { | |
8524 | /* The option is for other outputs */ | |
8525 | limit = &intel_limits_i9xx_sdvo; | |
8526 | } | |
8527 | ||
8528 | if (!crtc_state->clock_set && | |
8529 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8530 | refclk, NULL, &crtc_state->dpll)) { | |
8531 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8532 | return -EINVAL; | |
8533 | } | |
8534 | ||
8535 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
8536 | ||
8537 | return 0; | |
8538 | } | |
8539 | ||
70e8aa21 ACO |
8540 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
8541 | struct intel_crtc_state *crtc_state) | |
8542 | { | |
8543 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8544 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8545 | const struct intel_limit *limit; |
70e8aa21 ACO |
8546 | int refclk = 96000; |
8547 | ||
8548 | memset(&crtc_state->dpll_hw_state, 0, | |
8549 | sizeof(crtc_state->dpll_hw_state)); | |
8550 | ||
2d84d2b3 | 8551 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
8552 | if (intel_panel_use_ssc(dev_priv)) { |
8553 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8554 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8555 | } | |
8556 | ||
8557 | limit = &intel_limits_pineview_lvds; | |
8558 | } else { | |
8559 | limit = &intel_limits_pineview_sdvo; | |
8560 | } | |
8561 | ||
8562 | if (!crtc_state->clock_set && | |
8563 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8564 | refclk, NULL, &crtc_state->dpll)) { | |
8565 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8566 | return -EINVAL; | |
8567 | } | |
8568 | ||
8569 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
8570 | ||
8571 | return 0; | |
8572 | } | |
8573 | ||
190f68c5 ACO |
8574 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
8575 | struct intel_crtc_state *crtc_state) | |
79e53945 | 8576 | { |
c7653199 | 8577 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8578 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8579 | const struct intel_limit *limit; |
81c97f52 | 8580 | int refclk = 96000; |
79e53945 | 8581 | |
dd3cd74a ACO |
8582 | memset(&crtc_state->dpll_hw_state, 0, |
8583 | sizeof(crtc_state->dpll_hw_state)); | |
8584 | ||
2d84d2b3 | 8585 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
8586 | if (intel_panel_use_ssc(dev_priv)) { |
8587 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8588 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
8589 | } | |
43565a06 | 8590 | |
70e8aa21 ACO |
8591 | limit = &intel_limits_i9xx_lvds; |
8592 | } else { | |
8593 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 8594 | } |
79e53945 | 8595 | |
70e8aa21 ACO |
8596 | if (!crtc_state->clock_set && |
8597 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8598 | refclk, NULL, &crtc_state->dpll)) { | |
8599 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8600 | return -EINVAL; | |
f47709a9 | 8601 | } |
7026d4ac | 8602 | |
81c97f52 | 8603 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 8604 | |
c8f7a0db | 8605 | return 0; |
f564048e EA |
8606 | } |
8607 | ||
65b3d6a9 ACO |
8608 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
8609 | struct intel_crtc_state *crtc_state) | |
8610 | { | |
8611 | int refclk = 100000; | |
1b6f4958 | 8612 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
8613 | |
8614 | memset(&crtc_state->dpll_hw_state, 0, | |
8615 | sizeof(crtc_state->dpll_hw_state)); | |
8616 | ||
65b3d6a9 ACO |
8617 | if (!crtc_state->clock_set && |
8618 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8619 | refclk, NULL, &crtc_state->dpll)) { | |
8620 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8621 | return -EINVAL; | |
8622 | } | |
8623 | ||
8624 | chv_compute_dpll(crtc, crtc_state); | |
8625 | ||
8626 | return 0; | |
8627 | } | |
8628 | ||
8629 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
8630 | struct intel_crtc_state *crtc_state) | |
8631 | { | |
8632 | int refclk = 100000; | |
1b6f4958 | 8633 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
8634 | |
8635 | memset(&crtc_state->dpll_hw_state, 0, | |
8636 | sizeof(crtc_state->dpll_hw_state)); | |
8637 | ||
65b3d6a9 ACO |
8638 | if (!crtc_state->clock_set && |
8639 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
8640 | refclk, NULL, &crtc_state->dpll)) { | |
8641 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
8642 | return -EINVAL; | |
8643 | } | |
8644 | ||
8645 | vlv_compute_dpll(crtc, crtc_state); | |
8646 | ||
8647 | return 0; | |
8648 | } | |
8649 | ||
2fa2fe9a | 8650 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8651 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8652 | { |
8653 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8654 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
8655 | uint32_t tmp; |
8656 | ||
50a0bc90 TU |
8657 | if (INTEL_GEN(dev_priv) <= 3 && |
8658 | (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) | |
dc9e7dec VS |
8659 | return; |
8660 | ||
2fa2fe9a | 8661 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8662 | if (!(tmp & PFIT_ENABLE)) |
8663 | return; | |
2fa2fe9a | 8664 | |
06922821 | 8665 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8666 | if (INTEL_INFO(dev)->gen < 4) { |
8667 | if (crtc->pipe != PIPE_B) | |
8668 | return; | |
2fa2fe9a DV |
8669 | } else { |
8670 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8671 | return; | |
8672 | } | |
8673 | ||
06922821 | 8674 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 8675 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
8676 | } |
8677 | ||
acbec814 | 8678 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8679 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8680 | { |
8681 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8682 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 8683 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 8684 | struct dpll clock; |
acbec814 | 8685 | u32 mdiv; |
662c6ecb | 8686 | int refclk = 100000; |
acbec814 | 8687 | |
b521973b VS |
8688 | /* In case of DSI, DPLL will not be used */ |
8689 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
8690 | return; |
8691 | ||
a580516d | 8692 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8693 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8694 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8695 | |
8696 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8697 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8698 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8699 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8700 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8701 | ||
dccbea3b | 8702 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8703 | } |
8704 | ||
5724dbd1 DL |
8705 | static void |
8706 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8707 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8708 | { |
8709 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8710 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
8711 | u32 val, base, offset; |
8712 | int pipe = crtc->pipe, plane = crtc->plane; | |
8713 | int fourcc, pixel_format; | |
6761dd31 | 8714 | unsigned int aligned_height; |
b113d5ee | 8715 | struct drm_framebuffer *fb; |
1b842c89 | 8716 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8717 | |
42a7b088 DL |
8718 | val = I915_READ(DSPCNTR(plane)); |
8719 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8720 | return; | |
8721 | ||
d9806c9f | 8722 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8723 | if (!intel_fb) { |
1ad292b5 JB |
8724 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8725 | return; | |
8726 | } | |
8727 | ||
1b842c89 DL |
8728 | fb = &intel_fb->base; |
8729 | ||
18c5247e DV |
8730 | if (INTEL_INFO(dev)->gen >= 4) { |
8731 | if (val & DISPPLANE_TILED) { | |
49af449b | 8732 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8733 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8734 | } | |
8735 | } | |
1ad292b5 JB |
8736 | |
8737 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8738 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8739 | fb->pixel_format = fourcc; |
8740 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8741 | |
8742 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8743 | if (plane_config->tiling) |
1ad292b5 JB |
8744 | offset = I915_READ(DSPTILEOFF(plane)); |
8745 | else | |
8746 | offset = I915_READ(DSPLINOFF(plane)); | |
8747 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8748 | } else { | |
8749 | base = I915_READ(DSPADDR(plane)); | |
8750 | } | |
8751 | plane_config->base = base; | |
8752 | ||
8753 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8754 | fb->width = ((val >> 16) & 0xfff) + 1; |
8755 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8756 | |
8757 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8758 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8759 | |
b113d5ee | 8760 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8761 | fb->pixel_format, |
8762 | fb->modifier[0]); | |
1ad292b5 | 8763 | |
f37b5c2b | 8764 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8765 | |
2844a921 DL |
8766 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8767 | pipe_name(pipe), plane, fb->width, fb->height, | |
8768 | fb->bits_per_pixel, base, fb->pitches[0], | |
8769 | plane_config->size); | |
1ad292b5 | 8770 | |
2d14030b | 8771 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8772 | } |
8773 | ||
70b23a98 | 8774 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8775 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8776 | { |
8777 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8778 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
8779 | int pipe = pipe_config->cpu_transcoder; |
8780 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 8781 | struct dpll clock; |
0d7b6b11 | 8782 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8783 | int refclk = 100000; |
8784 | ||
b521973b VS |
8785 | /* In case of DSI, DPLL will not be used */ |
8786 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8787 | return; | |
8788 | ||
a580516d | 8789 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8790 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8791 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8792 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8793 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8794 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8795 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8796 | |
8797 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8798 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8799 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8800 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8801 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8802 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8803 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8804 | ||
dccbea3b | 8805 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8806 | } |
8807 | ||
0e8ffe1b | 8808 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8809 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8810 | { |
8811 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8812 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 8813 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8814 | uint32_t tmp; |
1729050e | 8815 | bool ret; |
0e8ffe1b | 8816 | |
1729050e ID |
8817 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8818 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8819 | return false; |
8820 | ||
e143a21c | 8821 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8822 | pipe_config->shared_dpll = NULL; |
eccb140b | 8823 | |
1729050e ID |
8824 | ret = false; |
8825 | ||
0e8ffe1b DV |
8826 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8827 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8828 | goto out; |
0e8ffe1b | 8829 | |
9beb5fea TU |
8830 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
8831 | IS_CHERRYVIEW(dev_priv)) { | |
42571aef VS |
8832 | switch (tmp & PIPECONF_BPC_MASK) { |
8833 | case PIPECONF_6BPC: | |
8834 | pipe_config->pipe_bpp = 18; | |
8835 | break; | |
8836 | case PIPECONF_8BPC: | |
8837 | pipe_config->pipe_bpp = 24; | |
8838 | break; | |
8839 | case PIPECONF_10BPC: | |
8840 | pipe_config->pipe_bpp = 30; | |
8841 | break; | |
8842 | default: | |
8843 | break; | |
8844 | } | |
8845 | } | |
8846 | ||
920a14b2 | 8847 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 8848 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
b5a9fa09 DV |
8849 | pipe_config->limited_color_range = true; |
8850 | ||
282740f7 VS |
8851 | if (INTEL_INFO(dev)->gen < 4) |
8852 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8853 | ||
1bd1bd80 | 8854 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8855 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8856 | |
2fa2fe9a DV |
8857 | i9xx_get_pfit_config(crtc, pipe_config); |
8858 | ||
6c49f241 | 8859 | if (INTEL_INFO(dev)->gen >= 4) { |
c231775c | 8860 | /* No way to read it out on pipes B and C */ |
920a14b2 | 8861 | if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) |
c231775c VS |
8862 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; |
8863 | else | |
8864 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
8865 | pipe_config->pixel_multiplier = |
8866 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8867 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8868 | pipe_config->dpll_hw_state.dpll_md = tmp; |
50a0bc90 TU |
8869 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
8870 | IS_G33(dev_priv)) { | |
6c49f241 DV |
8871 | tmp = I915_READ(DPLL(crtc->pipe)); |
8872 | pipe_config->pixel_multiplier = | |
8873 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8874 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8875 | } else { | |
8876 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8877 | * port and will be fixed up in the encoder->get_config | |
8878 | * function. */ | |
8879 | pipe_config->pixel_multiplier = 1; | |
8880 | } | |
8bcc2795 | 8881 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
920a14b2 | 8882 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
1c4e0274 VS |
8883 | /* |
8884 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8885 | * on 830. Filter it out here so that we don't | |
8886 | * report errors due to that. | |
8887 | */ | |
50a0bc90 | 8888 | if (IS_I830(dev_priv)) |
1c4e0274 VS |
8889 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; |
8890 | ||
8bcc2795 DV |
8891 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8892 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8893 | } else { |
8894 | /* Mask out read-only status bits. */ | |
8895 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8896 | DPLL_PORTC_READY_MASK | | |
8897 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8898 | } |
6c49f241 | 8899 | |
920a14b2 | 8900 | if (IS_CHERRYVIEW(dev_priv)) |
70b23a98 | 8901 | chv_crtc_clock_get(crtc, pipe_config); |
11a914c2 | 8902 | else if (IS_VALLEYVIEW(dev_priv)) |
acbec814 JB |
8903 | vlv_crtc_clock_get(crtc, pipe_config); |
8904 | else | |
8905 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8906 | |
0f64614d VS |
8907 | /* |
8908 | * Normally the dotclock is filled in by the encoder .get_config() | |
8909 | * but in case the pipe is enabled w/o any ports we need a sane | |
8910 | * default. | |
8911 | */ | |
8912 | pipe_config->base.adjusted_mode.crtc_clock = | |
8913 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8914 | ||
1729050e ID |
8915 | ret = true; |
8916 | ||
8917 | out: | |
8918 | intel_display_power_put(dev_priv, power_domain); | |
8919 | ||
8920 | return ret; | |
0e8ffe1b DV |
8921 | } |
8922 | ||
dde86e2d | 8923 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 | 8924 | { |
fac5e23e | 8925 | struct drm_i915_private *dev_priv = to_i915(dev); |
13d83a67 | 8926 | struct intel_encoder *encoder; |
1c1a24d2 | 8927 | int i; |
74cfd7ac | 8928 | u32 val, final; |
13d83a67 | 8929 | bool has_lvds = false; |
199e5d79 | 8930 | bool has_cpu_edp = false; |
199e5d79 | 8931 | bool has_panel = false; |
99eb6a01 KP |
8932 | bool has_ck505 = false; |
8933 | bool can_ssc = false; | |
1c1a24d2 | 8934 | bool using_ssc_source = false; |
13d83a67 JB |
8935 | |
8936 | /* We need to take the global config into account */ | |
b2784e15 | 8937 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8938 | switch (encoder->type) { |
8939 | case INTEL_OUTPUT_LVDS: | |
8940 | has_panel = true; | |
8941 | has_lvds = true; | |
8942 | break; | |
8943 | case INTEL_OUTPUT_EDP: | |
8944 | has_panel = true; | |
2de6905f | 8945 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8946 | has_cpu_edp = true; |
8947 | break; | |
6847d71b PZ |
8948 | default: |
8949 | break; | |
13d83a67 JB |
8950 | } |
8951 | } | |
8952 | ||
6e266956 | 8953 | if (HAS_PCH_IBX(dev_priv)) { |
41aa3448 | 8954 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8955 | can_ssc = has_ck505; |
8956 | } else { | |
8957 | has_ck505 = false; | |
8958 | can_ssc = true; | |
8959 | } | |
8960 | ||
1c1a24d2 L |
8961 | /* Check if any DPLLs are using the SSC source */ |
8962 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
8963 | u32 temp = I915_READ(PCH_DPLL(i)); | |
8964 | ||
8965 | if (!(temp & DPLL_VCO_ENABLE)) | |
8966 | continue; | |
8967 | ||
8968 | if ((temp & PLL_REF_INPUT_MASK) == | |
8969 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
8970 | using_ssc_source = true; | |
8971 | break; | |
8972 | } | |
8973 | } | |
8974 | ||
8975 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
8976 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
8977 | |
8978 | /* Ironlake: try to setup display ref clock before DPLL | |
8979 | * enabling. This is only under driver's control after | |
8980 | * PCH B stepping, previous chipset stepping should be | |
8981 | * ignoring this setting. | |
8982 | */ | |
74cfd7ac CW |
8983 | val = I915_READ(PCH_DREF_CONTROL); |
8984 | ||
8985 | /* As we must carefully and slowly disable/enable each source in turn, | |
8986 | * compute the final state we want first and check if we need to | |
8987 | * make any changes at all. | |
8988 | */ | |
8989 | final = val; | |
8990 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8991 | if (has_ck505) | |
8992 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8993 | else | |
8994 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8995 | ||
8c07eb68 | 8996 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 8997 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 8998 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
8999 | |
9000 | if (has_panel) { | |
9001 | final |= DREF_SSC_SOURCE_ENABLE; | |
9002 | ||
9003 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
9004 | final |= DREF_SSC1_ENABLE; | |
9005 | ||
9006 | if (has_cpu_edp) { | |
9007 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
9008 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
9009 | else | |
9010 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
9011 | } else | |
9012 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
9013 | } else if (using_ssc_source) { |
9014 | final |= DREF_SSC_SOURCE_ENABLE; | |
9015 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
9016 | } |
9017 | ||
9018 | if (final == val) | |
9019 | return; | |
9020 | ||
13d83a67 | 9021 | /* Always enable nonspread source */ |
74cfd7ac | 9022 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 9023 | |
99eb6a01 | 9024 | if (has_ck505) |
74cfd7ac | 9025 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 9026 | else |
74cfd7ac | 9027 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 9028 | |
199e5d79 | 9029 | if (has_panel) { |
74cfd7ac CW |
9030 | val &= ~DREF_SSC_SOURCE_MASK; |
9031 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 9032 | |
199e5d79 | 9033 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 9034 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 9035 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 9036 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 9037 | } else |
74cfd7ac | 9038 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
9039 | |
9040 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 9041 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
9042 | POSTING_READ(PCH_DREF_CONTROL); |
9043 | udelay(200); | |
9044 | ||
74cfd7ac | 9045 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
9046 | |
9047 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 9048 | if (has_cpu_edp) { |
99eb6a01 | 9049 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 9050 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 9051 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 9052 | } else |
74cfd7ac | 9053 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 9054 | } else |
74cfd7ac | 9055 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 9056 | |
74cfd7ac | 9057 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
9058 | POSTING_READ(PCH_DREF_CONTROL); |
9059 | udelay(200); | |
9060 | } else { | |
1c1a24d2 | 9061 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 9062 | |
74cfd7ac | 9063 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
9064 | |
9065 | /* Turn off CPU output */ | |
74cfd7ac | 9066 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 9067 | |
74cfd7ac | 9068 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
9069 | POSTING_READ(PCH_DREF_CONTROL); |
9070 | udelay(200); | |
9071 | ||
1c1a24d2 L |
9072 | if (!using_ssc_source) { |
9073 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 9074 | |
1c1a24d2 L |
9075 | /* Turn off the SSC source */ |
9076 | val &= ~DREF_SSC_SOURCE_MASK; | |
9077 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 9078 | |
1c1a24d2 L |
9079 | /* Turn off SSC1 */ |
9080 | val &= ~DREF_SSC1_ENABLE; | |
9081 | ||
9082 | I915_WRITE(PCH_DREF_CONTROL, val); | |
9083 | POSTING_READ(PCH_DREF_CONTROL); | |
9084 | udelay(200); | |
9085 | } | |
13d83a67 | 9086 | } |
74cfd7ac CW |
9087 | |
9088 | BUG_ON(val != final); | |
13d83a67 JB |
9089 | } |
9090 | ||
f31f2d55 | 9091 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 9092 | { |
f31f2d55 | 9093 | uint32_t tmp; |
dde86e2d | 9094 | |
0ff066a9 PZ |
9095 | tmp = I915_READ(SOUTH_CHICKEN2); |
9096 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
9097 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 9098 | |
cf3598c2 ID |
9099 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
9100 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 9101 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 9102 | |
0ff066a9 PZ |
9103 | tmp = I915_READ(SOUTH_CHICKEN2); |
9104 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
9105 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 9106 | |
cf3598c2 ID |
9107 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
9108 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 9109 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
9110 | } |
9111 | ||
9112 | /* WaMPhyProgramming:hsw */ | |
9113 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
9114 | { | |
9115 | uint32_t tmp; | |
dde86e2d PZ |
9116 | |
9117 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
9118 | tmp &= ~(0xFF << 24); | |
9119 | tmp |= (0x12 << 24); | |
9120 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
9121 | ||
dde86e2d PZ |
9122 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
9123 | tmp |= (1 << 11); | |
9124 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
9125 | ||
9126 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
9127 | tmp |= (1 << 11); | |
9128 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
9129 | ||
dde86e2d PZ |
9130 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
9131 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
9132 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
9133 | ||
9134 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
9135 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
9136 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
9137 | ||
0ff066a9 PZ |
9138 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
9139 | tmp &= ~(7 << 13); | |
9140 | tmp |= (5 << 13); | |
9141 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 9142 | |
0ff066a9 PZ |
9143 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
9144 | tmp &= ~(7 << 13); | |
9145 | tmp |= (5 << 13); | |
9146 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
9147 | |
9148 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
9149 | tmp &= ~0xFF; | |
9150 | tmp |= 0x1C; | |
9151 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
9152 | ||
9153 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
9154 | tmp &= ~0xFF; | |
9155 | tmp |= 0x1C; | |
9156 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
9157 | ||
9158 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
9159 | tmp &= ~(0xFF << 16); | |
9160 | tmp |= (0x1C << 16); | |
9161 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
9162 | ||
9163 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
9164 | tmp &= ~(0xFF << 16); | |
9165 | tmp |= (0x1C << 16); | |
9166 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
9167 | ||
0ff066a9 PZ |
9168 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
9169 | tmp |= (1 << 27); | |
9170 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 9171 | |
0ff066a9 PZ |
9172 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
9173 | tmp |= (1 << 27); | |
9174 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 9175 | |
0ff066a9 PZ |
9176 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
9177 | tmp &= ~(0xF << 28); | |
9178 | tmp |= (4 << 28); | |
9179 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 9180 | |
0ff066a9 PZ |
9181 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
9182 | tmp &= ~(0xF << 28); | |
9183 | tmp |= (4 << 28); | |
9184 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
9185 | } |
9186 | ||
2fa86a1f PZ |
9187 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
9188 | * Programming" based on the parameters passed: | |
9189 | * - Sequence to enable CLKOUT_DP | |
9190 | * - Sequence to enable CLKOUT_DP without spread | |
9191 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
9192 | */ | |
9193 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
9194 | bool with_fdi) | |
f31f2d55 | 9195 | { |
fac5e23e | 9196 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa86a1f PZ |
9197 | uint32_t reg, tmp; |
9198 | ||
9199 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
9200 | with_spread = true; | |
4f8036a2 TU |
9201 | if (WARN(HAS_PCH_LPT_LP(dev_priv) && |
9202 | with_fdi, "LP PCH doesn't have FDI\n")) | |
2fa86a1f | 9203 | with_fdi = false; |
f31f2d55 | 9204 | |
a580516d | 9205 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
9206 | |
9207 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9208 | tmp &= ~SBI_SSCCTL_DISABLE; | |
9209 | tmp |= SBI_SSCCTL_PATHALT; | |
9210 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9211 | ||
9212 | udelay(24); | |
9213 | ||
2fa86a1f PZ |
9214 | if (with_spread) { |
9215 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9216 | tmp &= ~SBI_SSCCTL_PATHALT; | |
9217 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 9218 | |
2fa86a1f PZ |
9219 | if (with_fdi) { |
9220 | lpt_reset_fdi_mphy(dev_priv); | |
9221 | lpt_program_fdi_mphy(dev_priv); | |
9222 | } | |
9223 | } | |
dde86e2d | 9224 | |
4f8036a2 | 9225 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
9226 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
9227 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
9228 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 9229 | |
a580516d | 9230 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
9231 | } |
9232 | ||
47701c3b PZ |
9233 | /* Sequence to disable CLKOUT_DP */ |
9234 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
9235 | { | |
fac5e23e | 9236 | struct drm_i915_private *dev_priv = to_i915(dev); |
47701c3b PZ |
9237 | uint32_t reg, tmp; |
9238 | ||
a580516d | 9239 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 9240 | |
4f8036a2 | 9241 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
9242 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
9243 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
9244 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
9245 | ||
9246 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
9247 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
9248 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
9249 | tmp |= SBI_SSCCTL_PATHALT; | |
9250 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9251 | udelay(32); | |
9252 | } | |
9253 | tmp |= SBI_SSCCTL_DISABLE; | |
9254 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
9255 | } | |
9256 | ||
a580516d | 9257 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
9258 | } |
9259 | ||
f7be2c21 VS |
9260 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
9261 | ||
9262 | static const uint16_t sscdivintphase[] = { | |
9263 | [BEND_IDX( 50)] = 0x3B23, | |
9264 | [BEND_IDX( 45)] = 0x3B23, | |
9265 | [BEND_IDX( 40)] = 0x3C23, | |
9266 | [BEND_IDX( 35)] = 0x3C23, | |
9267 | [BEND_IDX( 30)] = 0x3D23, | |
9268 | [BEND_IDX( 25)] = 0x3D23, | |
9269 | [BEND_IDX( 20)] = 0x3E23, | |
9270 | [BEND_IDX( 15)] = 0x3E23, | |
9271 | [BEND_IDX( 10)] = 0x3F23, | |
9272 | [BEND_IDX( 5)] = 0x3F23, | |
9273 | [BEND_IDX( 0)] = 0x0025, | |
9274 | [BEND_IDX( -5)] = 0x0025, | |
9275 | [BEND_IDX(-10)] = 0x0125, | |
9276 | [BEND_IDX(-15)] = 0x0125, | |
9277 | [BEND_IDX(-20)] = 0x0225, | |
9278 | [BEND_IDX(-25)] = 0x0225, | |
9279 | [BEND_IDX(-30)] = 0x0325, | |
9280 | [BEND_IDX(-35)] = 0x0325, | |
9281 | [BEND_IDX(-40)] = 0x0425, | |
9282 | [BEND_IDX(-45)] = 0x0425, | |
9283 | [BEND_IDX(-50)] = 0x0525, | |
9284 | }; | |
9285 | ||
9286 | /* | |
9287 | * Bend CLKOUT_DP | |
9288 | * steps -50 to 50 inclusive, in steps of 5 | |
9289 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
9290 | * change in clock period = -(steps / 10) * 5.787 ps | |
9291 | */ | |
9292 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
9293 | { | |
9294 | uint32_t tmp; | |
9295 | int idx = BEND_IDX(steps); | |
9296 | ||
9297 | if (WARN_ON(steps % 5 != 0)) | |
9298 | return; | |
9299 | ||
9300 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
9301 | return; | |
9302 | ||
9303 | mutex_lock(&dev_priv->sb_lock); | |
9304 | ||
9305 | if (steps % 10 != 0) | |
9306 | tmp = 0xAAAAAAAB; | |
9307 | else | |
9308 | tmp = 0x00000000; | |
9309 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
9310 | ||
9311 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
9312 | tmp &= 0xffff0000; | |
9313 | tmp |= sscdivintphase[idx]; | |
9314 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
9315 | ||
9316 | mutex_unlock(&dev_priv->sb_lock); | |
9317 | } | |
9318 | ||
9319 | #undef BEND_IDX | |
9320 | ||
bf8fa3d3 PZ |
9321 | static void lpt_init_pch_refclk(struct drm_device *dev) |
9322 | { | |
bf8fa3d3 PZ |
9323 | struct intel_encoder *encoder; |
9324 | bool has_vga = false; | |
9325 | ||
b2784e15 | 9326 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
9327 | switch (encoder->type) { |
9328 | case INTEL_OUTPUT_ANALOG: | |
9329 | has_vga = true; | |
9330 | break; | |
6847d71b PZ |
9331 | default: |
9332 | break; | |
bf8fa3d3 PZ |
9333 | } |
9334 | } | |
9335 | ||
f7be2c21 VS |
9336 | if (has_vga) { |
9337 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 9338 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 9339 | } else { |
47701c3b | 9340 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 9341 | } |
bf8fa3d3 PZ |
9342 | } |
9343 | ||
dde86e2d PZ |
9344 | /* |
9345 | * Initialize reference clocks when the driver loads | |
9346 | */ | |
9347 | void intel_init_pch_refclk(struct drm_device *dev) | |
9348 | { | |
6e266956 TU |
9349 | struct drm_i915_private *dev_priv = to_i915(dev); |
9350 | ||
9351 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) | |
dde86e2d | 9352 | ironlake_init_pch_refclk(dev); |
6e266956 | 9353 | else if (HAS_PCH_LPT(dev_priv)) |
dde86e2d PZ |
9354 | lpt_init_pch_refclk(dev); |
9355 | } | |
9356 | ||
6ff93609 | 9357 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 9358 | { |
fac5e23e | 9359 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
9360 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9361 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
9362 | uint32_t val; |
9363 | ||
78114071 | 9364 | val = 0; |
c8203565 | 9365 | |
6e3c9717 | 9366 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 9367 | case 18: |
dfd07d72 | 9368 | val |= PIPECONF_6BPC; |
c8203565 PZ |
9369 | break; |
9370 | case 24: | |
dfd07d72 | 9371 | val |= PIPECONF_8BPC; |
c8203565 PZ |
9372 | break; |
9373 | case 30: | |
dfd07d72 | 9374 | val |= PIPECONF_10BPC; |
c8203565 PZ |
9375 | break; |
9376 | case 36: | |
dfd07d72 | 9377 | val |= PIPECONF_12BPC; |
c8203565 PZ |
9378 | break; |
9379 | default: | |
cc769b62 PZ |
9380 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
9381 | BUG(); | |
c8203565 PZ |
9382 | } |
9383 | ||
6e3c9717 | 9384 | if (intel_crtc->config->dither) |
c8203565 PZ |
9385 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
9386 | ||
6e3c9717 | 9387 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
9388 | val |= PIPECONF_INTERLACED_ILK; |
9389 | else | |
9390 | val |= PIPECONF_PROGRESSIVE; | |
9391 | ||
6e3c9717 | 9392 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 9393 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 9394 | |
c8203565 PZ |
9395 | I915_WRITE(PIPECONF(pipe), val); |
9396 | POSTING_READ(PIPECONF(pipe)); | |
9397 | } | |
9398 | ||
6ff93609 | 9399 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 9400 | { |
fac5e23e | 9401 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 9402 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9403 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 9404 | u32 val = 0; |
ee2b0b38 | 9405 | |
391bf048 | 9406 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
9407 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
9408 | ||
6e3c9717 | 9409 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
9410 | val |= PIPECONF_INTERLACED_ILK; |
9411 | else | |
9412 | val |= PIPECONF_PROGRESSIVE; | |
9413 | ||
702e7a56 PZ |
9414 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
9415 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
9416 | } |
9417 | ||
391bf048 JN |
9418 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
9419 | { | |
fac5e23e | 9420 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 9421 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 9422 | |
391bf048 JN |
9423 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
9424 | u32 val = 0; | |
756f85cf | 9425 | |
6e3c9717 | 9426 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
9427 | case 18: |
9428 | val |= PIPEMISC_DITHER_6_BPC; | |
9429 | break; | |
9430 | case 24: | |
9431 | val |= PIPEMISC_DITHER_8_BPC; | |
9432 | break; | |
9433 | case 30: | |
9434 | val |= PIPEMISC_DITHER_10_BPC; | |
9435 | break; | |
9436 | case 36: | |
9437 | val |= PIPEMISC_DITHER_12_BPC; | |
9438 | break; | |
9439 | default: | |
9440 | /* Case prevented by pipe_config_set_bpp. */ | |
9441 | BUG(); | |
9442 | } | |
9443 | ||
6e3c9717 | 9444 | if (intel_crtc->config->dither) |
756f85cf PZ |
9445 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
9446 | ||
391bf048 | 9447 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 9448 | } |
ee2b0b38 PZ |
9449 | } |
9450 | ||
d4b1931c PZ |
9451 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
9452 | { | |
9453 | /* | |
9454 | * Account for spread spectrum to avoid | |
9455 | * oversubscribing the link. Max center spread | |
9456 | * is 2.5%; use 5% for safety's sake. | |
9457 | */ | |
9458 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 9459 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
9460 | } |
9461 | ||
7429e9d4 | 9462 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 9463 | { |
7429e9d4 | 9464 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
9465 | } |
9466 | ||
b75ca6f6 ACO |
9467 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
9468 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 9469 | struct dpll *reduced_clock) |
79e53945 | 9470 | { |
de13a2e3 | 9471 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 9472 | struct drm_device *dev = crtc->dev; |
fac5e23e | 9473 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 9474 | u32 dpll, fp, fp2; |
3d6e9ee0 | 9475 | int factor; |
79e53945 | 9476 | |
c1858123 | 9477 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 9478 | factor = 21; |
3d6e9ee0 | 9479 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 9480 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 9481 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
6e266956 | 9482 | (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev))) |
8febb297 | 9483 | factor = 25; |
190f68c5 | 9484 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 9485 | factor = 20; |
c1858123 | 9486 | |
b75ca6f6 ACO |
9487 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
9488 | ||
190f68c5 | 9489 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
9490 | fp |= FP_CB_TUNE; |
9491 | ||
9492 | if (reduced_clock) { | |
9493 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 9494 | |
b75ca6f6 ACO |
9495 | if (reduced_clock->m < factor * reduced_clock->n) |
9496 | fp2 |= FP_CB_TUNE; | |
9497 | } else { | |
9498 | fp2 = fp; | |
9499 | } | |
9a7c7890 | 9500 | |
5eddb70b | 9501 | dpll = 0; |
2c07245f | 9502 | |
3d6e9ee0 | 9503 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
9504 | dpll |= DPLLB_MODE_LVDS; |
9505 | else | |
9506 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 9507 | |
190f68c5 | 9508 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 9509 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 9510 | |
3d6e9ee0 VS |
9511 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
9512 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 9513 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 9514 | |
37a5650b | 9515 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 9516 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 9517 | |
7d7f8633 VS |
9518 | /* |
9519 | * The high speed IO clock is only really required for | |
9520 | * SDVO/HDMI/DP, but we also enable it for CRT to make it | |
9521 | * possible to share the DPLL between CRT and HDMI. Enabling | |
9522 | * the clock needlessly does no real harm, except use up a | |
9523 | * bit of power potentially. | |
9524 | * | |
9525 | * We'll limit this to IVB with 3 pipes, since it has only two | |
9526 | * DPLLs and so DPLL sharing is the only way to get three pipes | |
9527 | * driving PCH ports at the same time. On SNB we could do this, | |
9528 | * and potentially avoid enabling the second DPLL, but it's not | |
9529 | * clear if it''s a win or loss power wise. No point in doing | |
9530 | * this on ILK at all since it has a fixed DPLL<->pipe mapping. | |
9531 | */ | |
9532 | if (INTEL_INFO(dev_priv)->num_pipes == 3 && | |
9533 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) | |
9534 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
9535 | ||
a07d6787 | 9536 | /* compute bitmask from p1 value */ |
190f68c5 | 9537 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 9538 | /* also FPA1 */ |
190f68c5 | 9539 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 9540 | |
190f68c5 | 9541 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
9542 | case 5: |
9543 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
9544 | break; | |
9545 | case 7: | |
9546 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
9547 | break; | |
9548 | case 10: | |
9549 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
9550 | break; | |
9551 | case 14: | |
9552 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
9553 | break; | |
79e53945 JB |
9554 | } |
9555 | ||
3d6e9ee0 VS |
9556 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
9557 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 9558 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
9559 | else |
9560 | dpll |= PLL_REF_INPUT_DREFCLK; | |
9561 | ||
b75ca6f6 ACO |
9562 | dpll |= DPLL_VCO_ENABLE; |
9563 | ||
9564 | crtc_state->dpll_hw_state.dpll = dpll; | |
9565 | crtc_state->dpll_hw_state.fp0 = fp; | |
9566 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
9567 | } |
9568 | ||
190f68c5 ACO |
9569 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
9570 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 9571 | { |
997c030c | 9572 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 9573 | struct drm_i915_private *dev_priv = to_i915(dev); |
9e2c8475 | 9574 | struct dpll reduced_clock; |
7ed9f894 | 9575 | bool has_reduced_clock = false; |
e2b78267 | 9576 | struct intel_shared_dpll *pll; |
1b6f4958 | 9577 | const struct intel_limit *limit; |
997c030c | 9578 | int refclk = 120000; |
de13a2e3 | 9579 | |
dd3cd74a ACO |
9580 | memset(&crtc_state->dpll_hw_state, 0, |
9581 | sizeof(crtc_state->dpll_hw_state)); | |
9582 | ||
ded220e2 ACO |
9583 | crtc->lowfreq_avail = false; |
9584 | ||
9585 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
9586 | if (!crtc_state->has_pch_encoder) | |
9587 | return 0; | |
79e53945 | 9588 | |
2d84d2b3 | 9589 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
9590 | if (intel_panel_use_ssc(dev_priv)) { |
9591 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
9592 | dev_priv->vbt.lvds_ssc_freq); | |
9593 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
9594 | } | |
9595 | ||
9596 | if (intel_is_dual_link_lvds(dev)) { | |
9597 | if (refclk == 100000) | |
9598 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
9599 | else | |
9600 | limit = &intel_limits_ironlake_dual_lvds; | |
9601 | } else { | |
9602 | if (refclk == 100000) | |
9603 | limit = &intel_limits_ironlake_single_lvds_100m; | |
9604 | else | |
9605 | limit = &intel_limits_ironlake_single_lvds; | |
9606 | } | |
9607 | } else { | |
9608 | limit = &intel_limits_ironlake_dac; | |
9609 | } | |
9610 | ||
364ee29d | 9611 | if (!crtc_state->clock_set && |
997c030c ACO |
9612 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
9613 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
9614 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9615 | return -EINVAL; | |
f47709a9 | 9616 | } |
79e53945 | 9617 | |
b75ca6f6 ACO |
9618 | ironlake_compute_dpll(crtc, crtc_state, |
9619 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 9620 | |
ded220e2 ACO |
9621 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
9622 | if (pll == NULL) { | |
9623 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
9624 | pipe_name(crtc->pipe)); | |
9625 | return -EINVAL; | |
3fb37703 | 9626 | } |
79e53945 | 9627 | |
2d84d2b3 | 9628 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ded220e2 | 9629 | has_reduced_clock) |
c7653199 | 9630 | crtc->lowfreq_avail = true; |
e2b78267 | 9631 | |
c8f7a0db | 9632 | return 0; |
79e53945 JB |
9633 | } |
9634 | ||
eb14cb74 VS |
9635 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9636 | struct intel_link_m_n *m_n) | |
9637 | { | |
9638 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9639 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
9640 | enum pipe pipe = crtc->pipe; |
9641 | ||
9642 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9643 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9644 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9645 | & ~TU_SIZE_MASK; | |
9646 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9647 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9648 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9649 | } | |
9650 | ||
9651 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9652 | enum transcoder transcoder, | |
b95af8be VK |
9653 | struct intel_link_m_n *m_n, |
9654 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9655 | { |
9656 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9657 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 | 9658 | enum pipe pipe = crtc->pipe; |
72419203 | 9659 | |
eb14cb74 VS |
9660 | if (INTEL_INFO(dev)->gen >= 5) { |
9661 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9662 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9663 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9664 | & ~TU_SIZE_MASK; | |
9665 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9666 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9667 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9668 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9669 | * gen < 8) and if DRRS is supported (to make sure the | |
9670 | * registers are not unnecessarily read). | |
9671 | */ | |
9672 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9673 | crtc->config->has_drrs) { |
b95af8be VK |
9674 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9675 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9676 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9677 | & ~TU_SIZE_MASK; | |
9678 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9679 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9680 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9681 | } | |
eb14cb74 VS |
9682 | } else { |
9683 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9684 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9685 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9686 | & ~TU_SIZE_MASK; | |
9687 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9688 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9689 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9690 | } | |
9691 | } | |
9692 | ||
9693 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9694 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9695 | { |
681a8504 | 9696 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9697 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9698 | else | |
9699 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9700 | &pipe_config->dp_m_n, |
9701 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9702 | } |
72419203 | 9703 | |
eb14cb74 | 9704 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9705 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9706 | { |
9707 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9708 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9709 | } |
9710 | ||
bd2e244f | 9711 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9712 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9713 | { |
9714 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9715 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
9716 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9717 | uint32_t ps_ctrl = 0; | |
9718 | int id = -1; | |
9719 | int i; | |
bd2e244f | 9720 | |
a1b2278e CK |
9721 | /* find scaler attached to this pipe */ |
9722 | for (i = 0; i < crtc->num_scalers; i++) { | |
9723 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9724 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9725 | id = i; | |
9726 | pipe_config->pch_pfit.enabled = true; | |
9727 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9728 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9729 | break; | |
9730 | } | |
9731 | } | |
bd2e244f | 9732 | |
a1b2278e CK |
9733 | scaler_state->scaler_id = id; |
9734 | if (id >= 0) { | |
9735 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9736 | } else { | |
9737 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9738 | } |
9739 | } | |
9740 | ||
5724dbd1 DL |
9741 | static void |
9742 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9743 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9744 | { |
9745 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9746 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 9747 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9748 | int pipe = crtc->pipe; |
9749 | int fourcc, pixel_format; | |
6761dd31 | 9750 | unsigned int aligned_height; |
bc8d7dff | 9751 | struct drm_framebuffer *fb; |
1b842c89 | 9752 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9753 | |
d9806c9f | 9754 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9755 | if (!intel_fb) { |
bc8d7dff DL |
9756 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9757 | return; | |
9758 | } | |
9759 | ||
1b842c89 DL |
9760 | fb = &intel_fb->base; |
9761 | ||
bc8d7dff | 9762 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9763 | if (!(val & PLANE_CTL_ENABLE)) |
9764 | goto error; | |
9765 | ||
bc8d7dff DL |
9766 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9767 | fourcc = skl_format_to_fourcc(pixel_format, | |
9768 | val & PLANE_CTL_ORDER_RGBX, | |
9769 | val & PLANE_CTL_ALPHA_MASK); | |
9770 | fb->pixel_format = fourcc; | |
9771 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9772 | ||
40f46283 DL |
9773 | tiling = val & PLANE_CTL_TILED_MASK; |
9774 | switch (tiling) { | |
9775 | case PLANE_CTL_TILED_LINEAR: | |
9776 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9777 | break; | |
9778 | case PLANE_CTL_TILED_X: | |
9779 | plane_config->tiling = I915_TILING_X; | |
9780 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9781 | break; | |
9782 | case PLANE_CTL_TILED_Y: | |
9783 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9784 | break; | |
9785 | case PLANE_CTL_TILED_YF: | |
9786 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9787 | break; | |
9788 | default: | |
9789 | MISSING_CASE(tiling); | |
9790 | goto error; | |
9791 | } | |
9792 | ||
bc8d7dff DL |
9793 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9794 | plane_config->base = base; | |
9795 | ||
9796 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9797 | ||
9798 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9799 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9800 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9801 | ||
9802 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9803 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9804 | fb->pixel_format); |
bc8d7dff DL |
9805 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9806 | ||
9807 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9808 | fb->pixel_format, |
9809 | fb->modifier[0]); | |
bc8d7dff | 9810 | |
f37b5c2b | 9811 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9812 | |
9813 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9814 | pipe_name(pipe), fb->width, fb->height, | |
9815 | fb->bits_per_pixel, base, fb->pitches[0], | |
9816 | plane_config->size); | |
9817 | ||
2d14030b | 9818 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9819 | return; |
9820 | ||
9821 | error: | |
d1a3a036 | 9822 | kfree(intel_fb); |
bc8d7dff DL |
9823 | } |
9824 | ||
2fa2fe9a | 9825 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9826 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9827 | { |
9828 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9829 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
9830 | uint32_t tmp; |
9831 | ||
9832 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9833 | ||
9834 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9835 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9836 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9837 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9838 | |
9839 | /* We currently do not free assignements of panel fitters on | |
9840 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9841 | * differentiates them) so just WARN about this case for now. */ | |
5db94019 | 9842 | if (IS_GEN7(dev_priv)) { |
cb8b2a30 DV |
9843 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
9844 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9845 | } | |
2fa2fe9a | 9846 | } |
79e53945 JB |
9847 | } |
9848 | ||
5724dbd1 DL |
9849 | static void |
9850 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9851 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9852 | { |
9853 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9854 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 9855 | u32 val, base, offset; |
aeee5a49 | 9856 | int pipe = crtc->pipe; |
4c6baa59 | 9857 | int fourcc, pixel_format; |
6761dd31 | 9858 | unsigned int aligned_height; |
b113d5ee | 9859 | struct drm_framebuffer *fb; |
1b842c89 | 9860 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9861 | |
42a7b088 DL |
9862 | val = I915_READ(DSPCNTR(pipe)); |
9863 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9864 | return; | |
9865 | ||
d9806c9f | 9866 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9867 | if (!intel_fb) { |
4c6baa59 JB |
9868 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9869 | return; | |
9870 | } | |
9871 | ||
1b842c89 DL |
9872 | fb = &intel_fb->base; |
9873 | ||
18c5247e DV |
9874 | if (INTEL_INFO(dev)->gen >= 4) { |
9875 | if (val & DISPPLANE_TILED) { | |
49af449b | 9876 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9877 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9878 | } | |
9879 | } | |
4c6baa59 JB |
9880 | |
9881 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9882 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9883 | fb->pixel_format = fourcc; |
9884 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9885 | |
aeee5a49 | 9886 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
8652744b | 9887 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
aeee5a49 | 9888 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9889 | } else { |
49af449b | 9890 | if (plane_config->tiling) |
aeee5a49 | 9891 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9892 | else |
aeee5a49 | 9893 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9894 | } |
9895 | plane_config->base = base; | |
9896 | ||
9897 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9898 | fb->width = ((val >> 16) & 0xfff) + 1; |
9899 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9900 | |
9901 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9902 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9903 | |
b113d5ee | 9904 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9905 | fb->pixel_format, |
9906 | fb->modifier[0]); | |
4c6baa59 | 9907 | |
f37b5c2b | 9908 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9909 | |
2844a921 DL |
9910 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9911 | pipe_name(pipe), fb->width, fb->height, | |
9912 | fb->bits_per_pixel, base, fb->pitches[0], | |
9913 | plane_config->size); | |
b113d5ee | 9914 | |
2d14030b | 9915 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9916 | } |
9917 | ||
0e8ffe1b | 9918 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9919 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9920 | { |
9921 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9922 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 9923 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9924 | uint32_t tmp; |
1729050e | 9925 | bool ret; |
0e8ffe1b | 9926 | |
1729050e ID |
9927 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9928 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9929 | return false; |
9930 | ||
e143a21c | 9931 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9932 | pipe_config->shared_dpll = NULL; |
eccb140b | 9933 | |
1729050e | 9934 | ret = false; |
0e8ffe1b DV |
9935 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9936 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9937 | goto out; |
0e8ffe1b | 9938 | |
42571aef VS |
9939 | switch (tmp & PIPECONF_BPC_MASK) { |
9940 | case PIPECONF_6BPC: | |
9941 | pipe_config->pipe_bpp = 18; | |
9942 | break; | |
9943 | case PIPECONF_8BPC: | |
9944 | pipe_config->pipe_bpp = 24; | |
9945 | break; | |
9946 | case PIPECONF_10BPC: | |
9947 | pipe_config->pipe_bpp = 30; | |
9948 | break; | |
9949 | case PIPECONF_12BPC: | |
9950 | pipe_config->pipe_bpp = 36; | |
9951 | break; | |
9952 | default: | |
9953 | break; | |
9954 | } | |
9955 | ||
b5a9fa09 DV |
9956 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9957 | pipe_config->limited_color_range = true; | |
9958 | ||
ab9412ba | 9959 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 9960 | struct intel_shared_dpll *pll; |
8106ddbd | 9961 | enum intel_dpll_id pll_id; |
66e985c0 | 9962 | |
88adfff1 DV |
9963 | pipe_config->has_pch_encoder = true; |
9964 | ||
627eb5a3 DV |
9965 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9966 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9967 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9968 | |
9969 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9970 | |
2d1fe073 | 9971 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
9972 | /* |
9973 | * The pipe->pch transcoder and pch transcoder->pll | |
9974 | * mapping is fixed. | |
9975 | */ | |
8106ddbd | 9976 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
9977 | } else { |
9978 | tmp = I915_READ(PCH_DPLL_SEL); | |
9979 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 9980 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 9981 | else |
8106ddbd | 9982 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 9983 | } |
66e985c0 | 9984 | |
8106ddbd ACO |
9985 | pipe_config->shared_dpll = |
9986 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
9987 | pll = pipe_config->shared_dpll; | |
66e985c0 | 9988 | |
2edd6443 ACO |
9989 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9990 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9991 | |
9992 | tmp = pipe_config->dpll_hw_state.dpll; | |
9993 | pipe_config->pixel_multiplier = | |
9994 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9995 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9996 | |
9997 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9998 | } else { |
9999 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
10000 | } |
10001 | ||
1bd1bd80 | 10002 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 10003 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10004 | |
2fa2fe9a DV |
10005 | ironlake_get_pfit_config(crtc, pipe_config); |
10006 | ||
1729050e ID |
10007 | ret = true; |
10008 | ||
10009 | out: | |
10010 | intel_display_power_put(dev_priv, power_domain); | |
10011 | ||
10012 | return ret; | |
0e8ffe1b DV |
10013 | } |
10014 | ||
be256dc7 PZ |
10015 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
10016 | { | |
91c8a326 | 10017 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 10018 | struct intel_crtc *crtc; |
be256dc7 | 10019 | |
d3fcc808 | 10020 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 10021 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
10022 | pipe_name(crtc->pipe)); |
10023 | ||
e2c719b7 RC |
10024 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
10025 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
10026 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
10027 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
44cb734c | 10028 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
e2c719b7 | 10029 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
be256dc7 | 10030 | "CPU PWM1 enabled\n"); |
772c2a51 | 10031 | if (IS_HASWELL(dev_priv)) |
e2c719b7 | 10032 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 10033 | "CPU PWM2 enabled\n"); |
e2c719b7 | 10034 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 10035 | "PCH PWM1 enabled\n"); |
e2c719b7 | 10036 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 10037 | "Utility pin enabled\n"); |
e2c719b7 | 10038 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 10039 | |
9926ada1 PZ |
10040 | /* |
10041 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
10042 | * interrupts remain enabled. We used to check for that, but since it's | |
10043 | * gen-specific and since we only disable LCPLL after we fully disable | |
10044 | * the interrupts, the check below should be enough. | |
10045 | */ | |
e2c719b7 | 10046 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
10047 | } |
10048 | ||
9ccd5aeb PZ |
10049 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
10050 | { | |
772c2a51 | 10051 | if (IS_HASWELL(dev_priv)) |
9ccd5aeb PZ |
10052 | return I915_READ(D_COMP_HSW); |
10053 | else | |
10054 | return I915_READ(D_COMP_BDW); | |
10055 | } | |
10056 | ||
3c4c9b81 PZ |
10057 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
10058 | { | |
772c2a51 | 10059 | if (IS_HASWELL(dev_priv)) { |
3c4c9b81 PZ |
10060 | mutex_lock(&dev_priv->rps.hw_lock); |
10061 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
10062 | val)) | |
79cf219a | 10063 | DRM_DEBUG_KMS("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
10064 | mutex_unlock(&dev_priv->rps.hw_lock); |
10065 | } else { | |
9ccd5aeb PZ |
10066 | I915_WRITE(D_COMP_BDW, val); |
10067 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 10068 | } |
be256dc7 PZ |
10069 | } |
10070 | ||
10071 | /* | |
10072 | * This function implements pieces of two sequences from BSpec: | |
10073 | * - Sequence for display software to disable LCPLL | |
10074 | * - Sequence for display software to allow package C8+ | |
10075 | * The steps implemented here are just the steps that actually touch the LCPLL | |
10076 | * register. Callers should take care of disabling all the display engine | |
10077 | * functions, doing the mode unset, fixing interrupts, etc. | |
10078 | */ | |
6ff58d53 PZ |
10079 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
10080 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
10081 | { |
10082 | uint32_t val; | |
10083 | ||
10084 | assert_can_disable_lcpll(dev_priv); | |
10085 | ||
10086 | val = I915_READ(LCPLL_CTL); | |
10087 | ||
10088 | if (switch_to_fclk) { | |
10089 | val |= LCPLL_CD_SOURCE_FCLK; | |
10090 | I915_WRITE(LCPLL_CTL, val); | |
10091 | ||
f53dd63f ID |
10092 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
10093 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
10094 | DRM_ERROR("Switching to FCLK failed\n"); |
10095 | ||
10096 | val = I915_READ(LCPLL_CTL); | |
10097 | } | |
10098 | ||
10099 | val |= LCPLL_PLL_DISABLE; | |
10100 | I915_WRITE(LCPLL_CTL, val); | |
10101 | POSTING_READ(LCPLL_CTL); | |
10102 | ||
24d8441d | 10103 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
10104 | DRM_ERROR("LCPLL still locked\n"); |
10105 | ||
9ccd5aeb | 10106 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 10107 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 10108 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
10109 | ndelay(100); |
10110 | ||
9ccd5aeb PZ |
10111 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
10112 | 1)) | |
be256dc7 PZ |
10113 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
10114 | ||
10115 | if (allow_power_down) { | |
10116 | val = I915_READ(LCPLL_CTL); | |
10117 | val |= LCPLL_POWER_DOWN_ALLOW; | |
10118 | I915_WRITE(LCPLL_CTL, val); | |
10119 | POSTING_READ(LCPLL_CTL); | |
10120 | } | |
10121 | } | |
10122 | ||
10123 | /* | |
10124 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
10125 | * source. | |
10126 | */ | |
6ff58d53 | 10127 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
10128 | { |
10129 | uint32_t val; | |
10130 | ||
10131 | val = I915_READ(LCPLL_CTL); | |
10132 | ||
10133 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
10134 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
10135 | return; | |
10136 | ||
a8a8bd54 PZ |
10137 | /* |
10138 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
10139 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 10140 | */ |
59bad947 | 10141 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 10142 | |
be256dc7 PZ |
10143 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
10144 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
10145 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 10146 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
10147 | } |
10148 | ||
9ccd5aeb | 10149 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
10150 | val |= D_COMP_COMP_FORCE; |
10151 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 10152 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
10153 | |
10154 | val = I915_READ(LCPLL_CTL); | |
10155 | val &= ~LCPLL_PLL_DISABLE; | |
10156 | I915_WRITE(LCPLL_CTL, val); | |
10157 | ||
93220c08 CW |
10158 | if (intel_wait_for_register(dev_priv, |
10159 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
10160 | 5)) | |
be256dc7 PZ |
10161 | DRM_ERROR("LCPLL not locked yet\n"); |
10162 | ||
10163 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
10164 | val = I915_READ(LCPLL_CTL); | |
10165 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
10166 | I915_WRITE(LCPLL_CTL, val); | |
10167 | ||
f53dd63f ID |
10168 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
10169 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
10170 | DRM_ERROR("Switching back to LCPLL failed\n"); |
10171 | } | |
215733fa | 10172 | |
59bad947 | 10173 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4c75b940 | 10174 | intel_update_cdclk(dev_priv); |
be256dc7 PZ |
10175 | } |
10176 | ||
765dab67 PZ |
10177 | /* |
10178 | * Package states C8 and deeper are really deep PC states that can only be | |
10179 | * reached when all the devices on the system allow it, so even if the graphics | |
10180 | * device allows PC8+, it doesn't mean the system will actually get to these | |
10181 | * states. Our driver only allows PC8+ when going into runtime PM. | |
10182 | * | |
10183 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
10184 | * well is disabled and most interrupts are disabled, and these are also | |
10185 | * requirements for runtime PM. When these conditions are met, we manually do | |
10186 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
10187 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
10188 | * hang the machine. | |
10189 | * | |
10190 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
10191 | * the state of some registers, so when we come back from PC8+ we need to | |
10192 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
10193 | * need to take care of the registers kept by RC6. Notice that this happens even | |
10194 | * if we don't put the device in PCI D3 state (which is what currently happens | |
10195 | * because of the runtime PM support). | |
10196 | * | |
10197 | * For more, read "Display Sequences for Package C8" on the hardware | |
10198 | * documentation. | |
10199 | */ | |
a14cb6fc | 10200 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 10201 | { |
91c8a326 | 10202 | struct drm_device *dev = &dev_priv->drm; |
c67a470b PZ |
10203 | uint32_t val; |
10204 | ||
c67a470b PZ |
10205 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
10206 | ||
4f8036a2 | 10207 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
10208 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
10209 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
10210 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
10211 | } | |
10212 | ||
10213 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
10214 | hsw_disable_lcpll(dev_priv, true, true); |
10215 | } | |
10216 | ||
a14cb6fc | 10217 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 10218 | { |
91c8a326 | 10219 | struct drm_device *dev = &dev_priv->drm; |
c67a470b PZ |
10220 | uint32_t val; |
10221 | ||
c67a470b PZ |
10222 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
10223 | ||
10224 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
10225 | lpt_init_pch_refclk(dev); |
10226 | ||
4f8036a2 | 10227 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
10228 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
10229 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
10230 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
10231 | } | |
c67a470b PZ |
10232 | } |
10233 | ||
324513c0 | 10234 | static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 10235 | { |
a821fc46 | 10236 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
10237 | struct intel_atomic_state *old_intel_state = |
10238 | to_intel_atomic_state(old_state); | |
10239 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 10240 | |
324513c0 | 10241 | bxt_set_cdclk(to_i915(dev), req_cdclk); |
f8437dd1 VK |
10242 | } |
10243 | ||
b30ce9e0 DP |
10244 | static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, |
10245 | int pixel_rate) | |
10246 | { | |
9c754024 DP |
10247 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
10248 | ||
b30ce9e0 | 10249 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ |
9c754024 | 10250 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b30ce9e0 DP |
10251 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
10252 | ||
10253 | /* BSpec says "Do not use DisplayPort with CDCLK less than | |
10254 | * 432 MHz, audio enabled, port width x4, and link rate | |
10255 | * HBR2 (5.4 GHz), or else there may be audio corruption or | |
10256 | * screen corruption." | |
10257 | */ | |
10258 | if (intel_crtc_has_dp_encoder(crtc_state) && | |
10259 | crtc_state->has_audio && | |
10260 | crtc_state->port_clock >= 540000 && | |
10261 | crtc_state->lane_count == 4) | |
10262 | pixel_rate = max(432000, pixel_rate); | |
10263 | ||
10264 | return pixel_rate; | |
10265 | } | |
10266 | ||
b432e5cf | 10267 | /* compute the max rate for new configuration */ |
27c329ed | 10268 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 10269 | { |
565602d7 | 10270 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 10271 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
10272 | struct drm_crtc *crtc; |
10273 | struct drm_crtc_state *cstate; | |
27c329ed | 10274 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
10275 | unsigned max_pixel_rate = 0, i; |
10276 | enum pipe pipe; | |
b432e5cf | 10277 | |
565602d7 ML |
10278 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
10279 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 10280 | |
565602d7 ML |
10281 | for_each_crtc_in_state(state, crtc, cstate, i) { |
10282 | int pixel_rate; | |
27c329ed | 10283 | |
565602d7 ML |
10284 | crtc_state = to_intel_crtc_state(cstate); |
10285 | if (!crtc_state->base.enable) { | |
10286 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 10287 | continue; |
565602d7 | 10288 | } |
b432e5cf | 10289 | |
27c329ed | 10290 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf | 10291 | |
9c754024 | 10292 | if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv)) |
b30ce9e0 DP |
10293 | pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state, |
10294 | pixel_rate); | |
b432e5cf | 10295 | |
565602d7 | 10296 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
10297 | } |
10298 | ||
565602d7 ML |
10299 | for_each_pipe(dev_priv, pipe) |
10300 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
10301 | ||
b432e5cf VS |
10302 | return max_pixel_rate; |
10303 | } | |
10304 | ||
10305 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
10306 | { | |
fac5e23e | 10307 | struct drm_i915_private *dev_priv = to_i915(dev); |
b432e5cf VS |
10308 | uint32_t val, data; |
10309 | int ret; | |
10310 | ||
10311 | if (WARN((I915_READ(LCPLL_CTL) & | |
10312 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
10313 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
10314 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
10315 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
10316 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
10317 | return; | |
10318 | ||
10319 | mutex_lock(&dev_priv->rps.hw_lock); | |
10320 | ret = sandybridge_pcode_write(dev_priv, | |
10321 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
10322 | mutex_unlock(&dev_priv->rps.hw_lock); | |
10323 | if (ret) { | |
10324 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
10325 | return; | |
10326 | } | |
10327 | ||
10328 | val = I915_READ(LCPLL_CTL); | |
10329 | val |= LCPLL_CD_SOURCE_FCLK; | |
10330 | I915_WRITE(LCPLL_CTL, val); | |
10331 | ||
5ba00178 TU |
10332 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
10333 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
b432e5cf VS |
10334 | DRM_ERROR("Switching to FCLK failed\n"); |
10335 | ||
10336 | val = I915_READ(LCPLL_CTL); | |
10337 | val &= ~LCPLL_CLK_FREQ_MASK; | |
10338 | ||
10339 | switch (cdclk) { | |
10340 | case 450000: | |
10341 | val |= LCPLL_CLK_FREQ_450; | |
10342 | data = 0; | |
10343 | break; | |
10344 | case 540000: | |
10345 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
10346 | data = 1; | |
10347 | break; | |
10348 | case 337500: | |
10349 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
10350 | data = 2; | |
10351 | break; | |
10352 | case 675000: | |
10353 | val |= LCPLL_CLK_FREQ_675_BDW; | |
10354 | data = 3; | |
10355 | break; | |
10356 | default: | |
10357 | WARN(1, "invalid cdclk frequency\n"); | |
10358 | return; | |
10359 | } | |
10360 | ||
10361 | I915_WRITE(LCPLL_CTL, val); | |
10362 | ||
10363 | val = I915_READ(LCPLL_CTL); | |
10364 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
10365 | I915_WRITE(LCPLL_CTL, val); | |
10366 | ||
5ba00178 TU |
10367 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
10368 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
b432e5cf VS |
10369 | DRM_ERROR("Switching back to LCPLL failed\n"); |
10370 | ||
10371 | mutex_lock(&dev_priv->rps.hw_lock); | |
10372 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
10373 | mutex_unlock(&dev_priv->rps.hw_lock); | |
10374 | ||
7f1052a8 VS |
10375 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); |
10376 | ||
4c75b940 | 10377 | intel_update_cdclk(dev_priv); |
b432e5cf VS |
10378 | |
10379 | WARN(cdclk != dev_priv->cdclk_freq, | |
10380 | "cdclk requested %d kHz but got %d kHz\n", | |
10381 | cdclk, dev_priv->cdclk_freq); | |
10382 | } | |
10383 | ||
587c7914 VS |
10384 | static int broadwell_calc_cdclk(int max_pixclk) |
10385 | { | |
10386 | if (max_pixclk > 540000) | |
10387 | return 675000; | |
10388 | else if (max_pixclk > 450000) | |
10389 | return 540000; | |
10390 | else if (max_pixclk > 337500) | |
10391 | return 450000; | |
10392 | else | |
10393 | return 337500; | |
10394 | } | |
10395 | ||
27c329ed | 10396 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 10397 | { |
27c329ed | 10398 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 10399 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 10400 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
10401 | int cdclk; |
10402 | ||
10403 | /* | |
10404 | * FIXME should also account for plane ratio | |
10405 | * once 64bpp pixel formats are supported. | |
10406 | */ | |
587c7914 | 10407 | cdclk = broadwell_calc_cdclk(max_pixclk); |
b432e5cf | 10408 | |
b432e5cf | 10409 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
10410 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
10411 | cdclk, dev_priv->max_cdclk_freq); | |
10412 | return -EINVAL; | |
b432e5cf VS |
10413 | } |
10414 | ||
1a617b77 ML |
10415 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
10416 | if (!intel_state->active_crtcs) | |
587c7914 | 10417 | intel_state->dev_cdclk = broadwell_calc_cdclk(0); |
b432e5cf VS |
10418 | |
10419 | return 0; | |
10420 | } | |
10421 | ||
27c329ed | 10422 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 10423 | { |
27c329ed | 10424 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
10425 | struct intel_atomic_state *old_intel_state = |
10426 | to_intel_atomic_state(old_state); | |
10427 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 10428 | |
27c329ed | 10429 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
10430 | } |
10431 | ||
c89e39f3 CT |
10432 | static int skl_modeset_calc_cdclk(struct drm_atomic_state *state) |
10433 | { | |
10434 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
10435 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
10436 | const int max_pixclk = ilk_max_pixel_rate(state); | |
a8ca4934 | 10437 | int vco = intel_state->cdclk_pll_vco; |
c89e39f3 CT |
10438 | int cdclk; |
10439 | ||
10440 | /* | |
10441 | * FIXME should also account for plane ratio | |
10442 | * once 64bpp pixel formats are supported. | |
10443 | */ | |
a8ca4934 | 10444 | cdclk = skl_calc_cdclk(max_pixclk, vco); |
c89e39f3 CT |
10445 | |
10446 | /* | |
10447 | * FIXME move the cdclk caclulation to | |
10448 | * compute_config() so we can fail gracegully. | |
10449 | */ | |
10450 | if (cdclk > dev_priv->max_cdclk_freq) { | |
10451 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
10452 | cdclk, dev_priv->max_cdclk_freq); | |
10453 | cdclk = dev_priv->max_cdclk_freq; | |
10454 | } | |
10455 | ||
10456 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; | |
10457 | if (!intel_state->active_crtcs) | |
a8ca4934 | 10458 | intel_state->dev_cdclk = skl_calc_cdclk(0, vco); |
c89e39f3 CT |
10459 | |
10460 | return 0; | |
10461 | } | |
10462 | ||
10463 | static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |
10464 | { | |
1cd593e0 VS |
10465 | struct drm_i915_private *dev_priv = to_i915(old_state->dev); |
10466 | struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state); | |
10467 | unsigned int req_cdclk = intel_state->dev_cdclk; | |
10468 | unsigned int req_vco = intel_state->cdclk_pll_vco; | |
c89e39f3 | 10469 | |
1cd593e0 | 10470 | skl_set_cdclk(dev_priv, req_cdclk, req_vco); |
c89e39f3 CT |
10471 | } |
10472 | ||
190f68c5 ACO |
10473 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
10474 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 10475 | { |
d7edc4e5 | 10476 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
af3997b5 MK |
10477 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
10478 | return -EINVAL; | |
10479 | } | |
716c2e55 | 10480 | |
c7653199 | 10481 | crtc->lowfreq_avail = false; |
644cef34 | 10482 | |
c8f7a0db | 10483 | return 0; |
79e53945 JB |
10484 | } |
10485 | ||
3760b59c S |
10486 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
10487 | enum port port, | |
10488 | struct intel_crtc_state *pipe_config) | |
10489 | { | |
8106ddbd ACO |
10490 | enum intel_dpll_id id; |
10491 | ||
3760b59c S |
10492 | switch (port) { |
10493 | case PORT_A: | |
08250c4b | 10494 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
10495 | break; |
10496 | case PORT_B: | |
08250c4b | 10497 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
10498 | break; |
10499 | case PORT_C: | |
08250c4b | 10500 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
10501 | break; |
10502 | default: | |
10503 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 10504 | return; |
3760b59c | 10505 | } |
8106ddbd ACO |
10506 | |
10507 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
10508 | } |
10509 | ||
96b7dfb7 S |
10510 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
10511 | enum port port, | |
5cec258b | 10512 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 10513 | { |
8106ddbd | 10514 | enum intel_dpll_id id; |
a3c988ea | 10515 | u32 temp; |
96b7dfb7 S |
10516 | |
10517 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
c856052a | 10518 | id = temp >> (port * 3 + 1); |
96b7dfb7 | 10519 | |
c856052a | 10520 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) |
8106ddbd | 10521 | return; |
8106ddbd ACO |
10522 | |
10523 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
10524 | } |
10525 | ||
7d2c8175 DL |
10526 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
10527 | enum port port, | |
5cec258b | 10528 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 10529 | { |
8106ddbd | 10530 | enum intel_dpll_id id; |
c856052a | 10531 | uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
8106ddbd | 10532 | |
c856052a | 10533 | switch (ddi_pll_sel) { |
7d2c8175 | 10534 | case PORT_CLK_SEL_WRPLL1: |
8106ddbd | 10535 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
10536 | break; |
10537 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 10538 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 10539 | break; |
00490c22 | 10540 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 10541 | id = DPLL_ID_SPLL; |
79bd23da | 10542 | break; |
9d16da65 ACO |
10543 | case PORT_CLK_SEL_LCPLL_810: |
10544 | id = DPLL_ID_LCPLL_810; | |
10545 | break; | |
10546 | case PORT_CLK_SEL_LCPLL_1350: | |
10547 | id = DPLL_ID_LCPLL_1350; | |
10548 | break; | |
10549 | case PORT_CLK_SEL_LCPLL_2700: | |
10550 | id = DPLL_ID_LCPLL_2700; | |
10551 | break; | |
8106ddbd | 10552 | default: |
c856052a | 10553 | MISSING_CASE(ddi_pll_sel); |
8106ddbd ACO |
10554 | /* fall through */ |
10555 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 10556 | return; |
7d2c8175 | 10557 | } |
8106ddbd ACO |
10558 | |
10559 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
10560 | } |
10561 | ||
cf30429e JN |
10562 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
10563 | struct intel_crtc_state *pipe_config, | |
10564 | unsigned long *power_domain_mask) | |
10565 | { | |
10566 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10567 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
10568 | enum intel_display_power_domain power_domain; |
10569 | u32 tmp; | |
10570 | ||
d9a7bc67 ID |
10571 | /* |
10572 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
10573 | * transcoder handled below. | |
10574 | */ | |
cf30429e JN |
10575 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
10576 | ||
10577 | /* | |
10578 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
10579 | * consistency and less surprising code; it's in always on power). | |
10580 | */ | |
10581 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
10582 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
10583 | enum pipe trans_edp_pipe; | |
10584 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
10585 | default: | |
10586 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
10587 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
10588 | case TRANS_DDI_EDP_INPUT_A_ON: | |
10589 | trans_edp_pipe = PIPE_A; | |
10590 | break; | |
10591 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
10592 | trans_edp_pipe = PIPE_B; | |
10593 | break; | |
10594 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
10595 | trans_edp_pipe = PIPE_C; | |
10596 | break; | |
10597 | } | |
10598 | ||
10599 | if (trans_edp_pipe == crtc->pipe) | |
10600 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
10601 | } | |
10602 | ||
10603 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
10604 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10605 | return false; | |
10606 | *power_domain_mask |= BIT(power_domain); | |
10607 | ||
10608 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
10609 | ||
10610 | return tmp & PIPECONF_ENABLE; | |
10611 | } | |
10612 | ||
4d1de975 JN |
10613 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
10614 | struct intel_crtc_state *pipe_config, | |
10615 | unsigned long *power_domain_mask) | |
10616 | { | |
10617 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10618 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
10619 | enum intel_display_power_domain power_domain; |
10620 | enum port port; | |
10621 | enum transcoder cpu_transcoder; | |
10622 | u32 tmp; | |
10623 | ||
4d1de975 JN |
10624 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
10625 | if (port == PORT_A) | |
10626 | cpu_transcoder = TRANSCODER_DSI_A; | |
10627 | else | |
10628 | cpu_transcoder = TRANSCODER_DSI_C; | |
10629 | ||
10630 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
10631 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
10632 | continue; | |
10633 | *power_domain_mask |= BIT(power_domain); | |
10634 | ||
db18b6a6 ID |
10635 | /* |
10636 | * The PLL needs to be enabled with a valid divider | |
10637 | * configuration, otherwise accessing DSI registers will hang | |
10638 | * the machine. See BSpec North Display Engine | |
10639 | * registers/MIPI[BXT]. We can break out here early, since we | |
10640 | * need the same DSI PLL to be enabled for both DSI ports. | |
10641 | */ | |
10642 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
10643 | break; | |
10644 | ||
4d1de975 JN |
10645 | /* XXX: this works for video mode only */ |
10646 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
10647 | if (!(tmp & DPI_ENABLE)) | |
10648 | continue; | |
10649 | ||
10650 | tmp = I915_READ(MIPI_CTRL(port)); | |
10651 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
10652 | continue; | |
10653 | ||
10654 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
10655 | break; |
10656 | } | |
10657 | ||
d7edc4e5 | 10658 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
10659 | } |
10660 | ||
26804afd | 10661 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 10662 | struct intel_crtc_state *pipe_config) |
26804afd DV |
10663 | { |
10664 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10665 | struct drm_i915_private *dev_priv = to_i915(dev); |
d452c5b6 | 10666 | struct intel_shared_dpll *pll; |
26804afd DV |
10667 | enum port port; |
10668 | uint32_t tmp; | |
10669 | ||
10670 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
10671 | ||
10672 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
10673 | ||
0853723b | 10674 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
96b7dfb7 | 10675 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
e2d214ae | 10676 | else if (IS_BROXTON(dev_priv)) |
3760b59c | 10677 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
96b7dfb7 S |
10678 | else |
10679 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 10680 | |
8106ddbd ACO |
10681 | pll = pipe_config->shared_dpll; |
10682 | if (pll) { | |
2edd6443 ACO |
10683 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
10684 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
10685 | } |
10686 | ||
26804afd DV |
10687 | /* |
10688 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
10689 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
10690 | * the PCH transcoder is on. | |
10691 | */ | |
ca370455 DL |
10692 | if (INTEL_INFO(dev)->gen < 9 && |
10693 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
10694 | pipe_config->has_pch_encoder = true; |
10695 | ||
10696 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
10697 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
10698 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
10699 | ||
10700 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
10701 | } | |
10702 | } | |
10703 | ||
0e8ffe1b | 10704 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10705 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
10706 | { |
10707 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 10708 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e ID |
10709 | enum intel_display_power_domain power_domain; |
10710 | unsigned long power_domain_mask; | |
cf30429e | 10711 | bool active; |
0e8ffe1b | 10712 | |
1729050e ID |
10713 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
10714 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 10715 | return false; |
1729050e ID |
10716 | power_domain_mask = BIT(power_domain); |
10717 | ||
8106ddbd | 10718 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 10719 | |
cf30429e | 10720 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 10721 | |
d7edc4e5 VS |
10722 | if (IS_BROXTON(dev_priv) && |
10723 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { | |
10724 | WARN_ON(active); | |
10725 | active = true; | |
4d1de975 JN |
10726 | } |
10727 | ||
cf30429e | 10728 | if (!active) |
1729050e | 10729 | goto out; |
0e8ffe1b | 10730 | |
d7edc4e5 | 10731 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
10732 | haswell_get_ddi_port_state(crtc, pipe_config); |
10733 | intel_get_pipe_timings(crtc, pipe_config); | |
10734 | } | |
627eb5a3 | 10735 | |
bc58be60 | 10736 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10737 | |
05dc698c LL |
10738 | pipe_config->gamma_mode = |
10739 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
10740 | ||
a1b2278e | 10741 | if (INTEL_INFO(dev)->gen >= 9) { |
65edccce | 10742 | skl_init_scalers(dev_priv, crtc, pipe_config); |
a1b2278e | 10743 | |
af99ceda CK |
10744 | pipe_config->scaler_state.scaler_id = -1; |
10745 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10746 | } | |
10747 | ||
1729050e ID |
10748 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
10749 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10750 | power_domain_mask |= BIT(power_domain); | |
1c132b44 | 10751 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10752 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10753 | else |
1c132b44 | 10754 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10755 | } |
88adfff1 | 10756 | |
772c2a51 | 10757 | if (IS_HASWELL(dev_priv)) |
e59150dc JB |
10758 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
10759 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10760 | |
4d1de975 JN |
10761 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
10762 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
10763 | pipe_config->pixel_multiplier = |
10764 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10765 | } else { | |
10766 | pipe_config->pixel_multiplier = 1; | |
10767 | } | |
6c49f241 | 10768 | |
1729050e ID |
10769 | out: |
10770 | for_each_power_domain(power_domain, power_domain_mask) | |
10771 | intel_display_power_put(dev_priv, power_domain); | |
10772 | ||
cf30429e | 10773 | return active; |
0e8ffe1b DV |
10774 | } |
10775 | ||
55a08b3f ML |
10776 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10777 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10778 | { |
10779 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10780 | struct drm_i915_private *dev_priv = to_i915(dev); |
560b85bb | 10781 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
dc41c154 | 10782 | uint32_t cntl = 0, size = 0; |
560b85bb | 10783 | |
936e71e3 | 10784 | if (plane_state && plane_state->base.visible) { |
55a08b3f ML |
10785 | unsigned int width = plane_state->base.crtc_w; |
10786 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10787 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10788 | ||
10789 | switch (stride) { | |
10790 | default: | |
10791 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10792 | width, stride); | |
10793 | stride = 256; | |
10794 | /* fallthrough */ | |
10795 | case 256: | |
10796 | case 512: | |
10797 | case 1024: | |
10798 | case 2048: | |
10799 | break; | |
4b0e333e CW |
10800 | } |
10801 | ||
dc41c154 VS |
10802 | cntl |= CURSOR_ENABLE | |
10803 | CURSOR_GAMMA_ENABLE | | |
10804 | CURSOR_FORMAT_ARGB | | |
10805 | CURSOR_STRIDE(stride); | |
10806 | ||
10807 | size = (height << 12) | width; | |
4b0e333e | 10808 | } |
560b85bb | 10809 | |
dc41c154 VS |
10810 | if (intel_crtc->cursor_cntl != 0 && |
10811 | (intel_crtc->cursor_base != base || | |
10812 | intel_crtc->cursor_size != size || | |
10813 | intel_crtc->cursor_cntl != cntl)) { | |
10814 | /* On these chipsets we can only modify the base/size/stride | |
10815 | * whilst the cursor is disabled. | |
10816 | */ | |
0b87c24e VS |
10817 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10818 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10819 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10820 | } |
560b85bb | 10821 | |
99d1f387 | 10822 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10823 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10824 | intel_crtc->cursor_base = base; |
10825 | } | |
4726e0b0 | 10826 | |
dc41c154 VS |
10827 | if (intel_crtc->cursor_size != size) { |
10828 | I915_WRITE(CURSIZE, size); | |
10829 | intel_crtc->cursor_size = size; | |
4b0e333e | 10830 | } |
560b85bb | 10831 | |
4b0e333e | 10832 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10833 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10834 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10835 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10836 | } |
560b85bb CW |
10837 | } |
10838 | ||
55a08b3f ML |
10839 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10840 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10841 | { |
10842 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10843 | struct drm_i915_private *dev_priv = to_i915(dev); |
65a21cd6 | 10844 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
d8c0fafc | 10845 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
62e0fb88 | 10846 | const struct skl_wm_values *wm = &dev_priv->wm.skl_results; |
d8c0fafc | 10847 | const struct skl_plane_wm *p_wm = |
10848 | &cstate->wm.skl.optimal.planes[PLANE_CURSOR]; | |
65a21cd6 | 10849 | int pipe = intel_crtc->pipe; |
663f3122 | 10850 | uint32_t cntl = 0; |
4b0e333e | 10851 | |
62e0fb88 | 10852 | if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes & drm_crtc_mask(crtc)) |
d8c0fafc | 10853 | skl_write_cursor_wm(intel_crtc, p_wm, &wm->ddb); |
62e0fb88 | 10854 | |
936e71e3 | 10855 | if (plane_state && plane_state->base.visible) { |
4b0e333e | 10856 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10857 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10858 | case 64: |
10859 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10860 | break; | |
10861 | case 128: | |
10862 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10863 | break; | |
10864 | case 256: | |
10865 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10866 | break; | |
10867 | default: | |
55a08b3f | 10868 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10869 | return; |
65a21cd6 | 10870 | } |
4b0e333e | 10871 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10872 | |
4f8036a2 | 10873 | if (HAS_DDI(dev_priv)) |
47bf17a7 | 10874 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10875 | |
31ad61e4 | 10876 | if (plane_state->base.rotation == DRM_ROTATE_180) |
55a08b3f ML |
10877 | cntl |= CURSOR_ROTATE_180; |
10878 | } | |
4398ad45 | 10879 | |
4b0e333e CW |
10880 | if (intel_crtc->cursor_cntl != cntl) { |
10881 | I915_WRITE(CURCNTR(pipe), cntl); | |
10882 | POSTING_READ(CURCNTR(pipe)); | |
10883 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10884 | } |
4b0e333e | 10885 | |
65a21cd6 | 10886 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10887 | I915_WRITE(CURBASE(pipe), base); |
10888 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10889 | |
10890 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10891 | } |
10892 | ||
cda4b7d3 | 10893 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10894 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10895 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10896 | { |
10897 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10898 | struct drm_i915_private *dev_priv = to_i915(dev); |
cda4b7d3 CW |
10899 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10900 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10901 | u32 base = intel_crtc->cursor_addr; |
10902 | u32 pos = 0; | |
cda4b7d3 | 10903 | |
55a08b3f ML |
10904 | if (plane_state) { |
10905 | int x = plane_state->base.crtc_x; | |
10906 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10907 | |
55a08b3f ML |
10908 | if (x < 0) { |
10909 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10910 | x = -x; | |
10911 | } | |
10912 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10913 | |
55a08b3f ML |
10914 | if (y < 0) { |
10915 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10916 | y = -y; | |
10917 | } | |
10918 | pos |= y << CURSOR_Y_SHIFT; | |
10919 | ||
10920 | /* ILK+ do this automagically */ | |
49cff963 | 10921 | if (HAS_GMCH_DISPLAY(dev_priv) && |
31ad61e4 | 10922 | plane_state->base.rotation == DRM_ROTATE_180) { |
55a08b3f ML |
10923 | base += (plane_state->base.crtc_h * |
10924 | plane_state->base.crtc_w - 1) * 4; | |
10925 | } | |
cda4b7d3 | 10926 | } |
cda4b7d3 | 10927 | |
5efb3e28 VS |
10928 | I915_WRITE(CURPOS(pipe), pos); |
10929 | ||
50a0bc90 | 10930 | if (IS_845G(dev_priv) || IS_I865G(dev_priv)) |
55a08b3f | 10931 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10932 | else |
55a08b3f | 10933 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10934 | } |
10935 | ||
50a0bc90 | 10936 | static bool cursor_size_ok(struct drm_i915_private *dev_priv, |
dc41c154 VS |
10937 | uint32_t width, uint32_t height) |
10938 | { | |
10939 | if (width == 0 || height == 0) | |
10940 | return false; | |
10941 | ||
10942 | /* | |
10943 | * 845g/865g are special in that they are only limited by | |
10944 | * the width of their cursors, the height is arbitrary up to | |
10945 | * the precision of the register. Everything else requires | |
10946 | * square cursors, limited to a few power-of-two sizes. | |
10947 | */ | |
50a0bc90 | 10948 | if (IS_845G(dev_priv) || IS_I865G(dev_priv)) { |
dc41c154 VS |
10949 | if ((width & 63) != 0) |
10950 | return false; | |
10951 | ||
50a0bc90 | 10952 | if (width > (IS_845G(dev_priv) ? 64 : 512)) |
dc41c154 VS |
10953 | return false; |
10954 | ||
10955 | if (height > 1023) | |
10956 | return false; | |
10957 | } else { | |
10958 | switch (width | height) { | |
10959 | case 256: | |
10960 | case 128: | |
50a0bc90 | 10961 | if (IS_GEN2(dev_priv)) |
dc41c154 VS |
10962 | return false; |
10963 | case 64: | |
10964 | break; | |
10965 | default: | |
10966 | return false; | |
10967 | } | |
10968 | } | |
10969 | ||
10970 | return true; | |
10971 | } | |
10972 | ||
79e53945 JB |
10973 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10974 | static struct drm_display_mode load_detect_mode = { | |
10975 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10976 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10977 | }; | |
10978 | ||
a8bb6818 DV |
10979 | struct drm_framebuffer * |
10980 | __intel_framebuffer_create(struct drm_device *dev, | |
10981 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10982 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10983 | { |
10984 | struct intel_framebuffer *intel_fb; | |
10985 | int ret; | |
10986 | ||
10987 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10988 | if (!intel_fb) |
d2dff872 | 10989 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10990 | |
10991 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10992 | if (ret) |
10993 | goto err; | |
d2dff872 CW |
10994 | |
10995 | return &intel_fb->base; | |
dcb1394e | 10996 | |
dd4916c5 | 10997 | err: |
dd4916c5 | 10998 | kfree(intel_fb); |
dd4916c5 | 10999 | return ERR_PTR(ret); |
d2dff872 CW |
11000 | } |
11001 | ||
b5ea642a | 11002 | static struct drm_framebuffer * |
a8bb6818 DV |
11003 | intel_framebuffer_create(struct drm_device *dev, |
11004 | struct drm_mode_fb_cmd2 *mode_cmd, | |
11005 | struct drm_i915_gem_object *obj) | |
11006 | { | |
11007 | struct drm_framebuffer *fb; | |
11008 | int ret; | |
11009 | ||
11010 | ret = i915_mutex_lock_interruptible(dev); | |
11011 | if (ret) | |
11012 | return ERR_PTR(ret); | |
11013 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
11014 | mutex_unlock(&dev->struct_mutex); | |
11015 | ||
11016 | return fb; | |
11017 | } | |
11018 | ||
d2dff872 CW |
11019 | static u32 |
11020 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
11021 | { | |
11022 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
11023 | return ALIGN(pitch, 64); | |
11024 | } | |
11025 | ||
11026 | static u32 | |
11027 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
11028 | { | |
11029 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 11030 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
11031 | } |
11032 | ||
11033 | static struct drm_framebuffer * | |
11034 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
11035 | struct drm_display_mode *mode, | |
11036 | int depth, int bpp) | |
11037 | { | |
dcb1394e | 11038 | struct drm_framebuffer *fb; |
d2dff872 | 11039 | struct drm_i915_gem_object *obj; |
0fed39bd | 11040 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 11041 | |
d37cd8a8 | 11042 | obj = i915_gem_object_create(dev, |
d2dff872 | 11043 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
11044 | if (IS_ERR(obj)) |
11045 | return ERR_CAST(obj); | |
d2dff872 CW |
11046 | |
11047 | mode_cmd.width = mode->hdisplay; | |
11048 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
11049 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
11050 | bpp); | |
5ca0c34a | 11051 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 11052 | |
dcb1394e LW |
11053 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
11054 | if (IS_ERR(fb)) | |
f0cd5182 | 11055 | i915_gem_object_put(obj); |
dcb1394e LW |
11056 | |
11057 | return fb; | |
d2dff872 CW |
11058 | } |
11059 | ||
11060 | static struct drm_framebuffer * | |
11061 | mode_fits_in_fbdev(struct drm_device *dev, | |
11062 | struct drm_display_mode *mode) | |
11063 | { | |
0695726e | 11064 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 11065 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
11066 | struct drm_i915_gem_object *obj; |
11067 | struct drm_framebuffer *fb; | |
11068 | ||
4c0e5528 | 11069 | if (!dev_priv->fbdev) |
d2dff872 CW |
11070 | return NULL; |
11071 | ||
4c0e5528 | 11072 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
11073 | return NULL; |
11074 | ||
4c0e5528 DV |
11075 | obj = dev_priv->fbdev->fb->obj; |
11076 | BUG_ON(!obj); | |
11077 | ||
8bcd4553 | 11078 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
11079 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
11080 | fb->bits_per_pixel)) | |
d2dff872 CW |
11081 | return NULL; |
11082 | ||
01f2c773 | 11083 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
11084 | return NULL; |
11085 | ||
edde3617 | 11086 | drm_framebuffer_reference(fb); |
d2dff872 | 11087 | return fb; |
4520f53a DV |
11088 | #else |
11089 | return NULL; | |
11090 | #endif | |
d2dff872 CW |
11091 | } |
11092 | ||
d3a40d1b ACO |
11093 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
11094 | struct drm_crtc *crtc, | |
11095 | struct drm_display_mode *mode, | |
11096 | struct drm_framebuffer *fb, | |
11097 | int x, int y) | |
11098 | { | |
11099 | struct drm_plane_state *plane_state; | |
11100 | int hdisplay, vdisplay; | |
11101 | int ret; | |
11102 | ||
11103 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
11104 | if (IS_ERR(plane_state)) | |
11105 | return PTR_ERR(plane_state); | |
11106 | ||
11107 | if (mode) | |
11108 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
11109 | else | |
11110 | hdisplay = vdisplay = 0; | |
11111 | ||
11112 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
11113 | if (ret) | |
11114 | return ret; | |
11115 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11116 | plane_state->crtc_x = 0; | |
11117 | plane_state->crtc_y = 0; | |
11118 | plane_state->crtc_w = hdisplay; | |
11119 | plane_state->crtc_h = vdisplay; | |
11120 | plane_state->src_x = x << 16; | |
11121 | plane_state->src_y = y << 16; | |
11122 | plane_state->src_w = hdisplay << 16; | |
11123 | plane_state->src_h = vdisplay << 16; | |
11124 | ||
11125 | return 0; | |
11126 | } | |
11127 | ||
d2434ab7 | 11128 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 11129 | struct drm_display_mode *mode, |
51fd371b RC |
11130 | struct intel_load_detect_pipe *old, |
11131 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
11132 | { |
11133 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
11134 | struct intel_encoder *intel_encoder = |
11135 | intel_attached_encoder(connector); | |
79e53945 | 11136 | struct drm_crtc *possible_crtc; |
4ef69c7a | 11137 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
11138 | struct drm_crtc *crtc = NULL; |
11139 | struct drm_device *dev = encoder->dev; | |
0f0f74bc | 11140 | struct drm_i915_private *dev_priv = to_i915(dev); |
94352cf9 | 11141 | struct drm_framebuffer *fb; |
51fd371b | 11142 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 11143 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 11144 | struct drm_connector_state *connector_state; |
4be07317 | 11145 | struct intel_crtc_state *crtc_state; |
51fd371b | 11146 | int ret, i = -1; |
79e53945 | 11147 | |
d2dff872 | 11148 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 11149 | connector->base.id, connector->name, |
8e329a03 | 11150 | encoder->base.id, encoder->name); |
d2dff872 | 11151 | |
edde3617 ML |
11152 | old->restore_state = NULL; |
11153 | ||
51fd371b RC |
11154 | retry: |
11155 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
11156 | if (ret) | |
ad3c558f | 11157 | goto fail; |
6e9f798d | 11158 | |
79e53945 JB |
11159 | /* |
11160 | * Algorithm gets a little messy: | |
7a5e4805 | 11161 | * |
79e53945 JB |
11162 | * - if the connector already has an assigned crtc, use it (but make |
11163 | * sure it's on first) | |
7a5e4805 | 11164 | * |
79e53945 JB |
11165 | * - try to find the first unused crtc that can drive this connector, |
11166 | * and use that if we find one | |
79e53945 JB |
11167 | */ |
11168 | ||
11169 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
11170 | if (connector->state->crtc) { |
11171 | crtc = connector->state->crtc; | |
8261b191 | 11172 | |
51fd371b | 11173 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 11174 | if (ret) |
ad3c558f | 11175 | goto fail; |
8261b191 CW |
11176 | |
11177 | /* Make sure the crtc and connector are running */ | |
edde3617 | 11178 | goto found; |
79e53945 JB |
11179 | } |
11180 | ||
11181 | /* Find an unused one (if possible) */ | |
70e1e0ec | 11182 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
11183 | i++; |
11184 | if (!(encoder->possible_crtcs & (1 << i))) | |
11185 | continue; | |
edde3617 ML |
11186 | |
11187 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
11188 | if (ret) | |
11189 | goto fail; | |
11190 | ||
11191 | if (possible_crtc->state->enable) { | |
11192 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 11193 | continue; |
edde3617 | 11194 | } |
a459249c VS |
11195 | |
11196 | crtc = possible_crtc; | |
11197 | break; | |
79e53945 JB |
11198 | } |
11199 | ||
11200 | /* | |
11201 | * If we didn't find an unused CRTC, don't use any. | |
11202 | */ | |
11203 | if (!crtc) { | |
7173188d | 11204 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 11205 | goto fail; |
79e53945 JB |
11206 | } |
11207 | ||
edde3617 ML |
11208 | found: |
11209 | intel_crtc = to_intel_crtc(crtc); | |
11210 | ||
4d02e2de DV |
11211 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
11212 | if (ret) | |
ad3c558f | 11213 | goto fail; |
79e53945 | 11214 | |
83a57153 | 11215 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
11216 | restore_state = drm_atomic_state_alloc(dev); |
11217 | if (!state || !restore_state) { | |
11218 | ret = -ENOMEM; | |
11219 | goto fail; | |
11220 | } | |
83a57153 ACO |
11221 | |
11222 | state->acquire_ctx = ctx; | |
edde3617 | 11223 | restore_state->acquire_ctx = ctx; |
83a57153 | 11224 | |
944b0c76 ACO |
11225 | connector_state = drm_atomic_get_connector_state(state, connector); |
11226 | if (IS_ERR(connector_state)) { | |
11227 | ret = PTR_ERR(connector_state); | |
11228 | goto fail; | |
11229 | } | |
11230 | ||
edde3617 ML |
11231 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
11232 | if (ret) | |
11233 | goto fail; | |
944b0c76 | 11234 | |
4be07317 ACO |
11235 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
11236 | if (IS_ERR(crtc_state)) { | |
11237 | ret = PTR_ERR(crtc_state); | |
11238 | goto fail; | |
11239 | } | |
11240 | ||
49d6fa21 | 11241 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 11242 | |
6492711d CW |
11243 | if (!mode) |
11244 | mode = &load_detect_mode; | |
79e53945 | 11245 | |
d2dff872 CW |
11246 | /* We need a framebuffer large enough to accommodate all accesses |
11247 | * that the plane may generate whilst we perform load detection. | |
11248 | * We can not rely on the fbcon either being present (we get called | |
11249 | * during its initialisation to detect all boot displays, or it may | |
11250 | * not even exist) or that it is large enough to satisfy the | |
11251 | * requested mode. | |
11252 | */ | |
94352cf9 DV |
11253 | fb = mode_fits_in_fbdev(dev, mode); |
11254 | if (fb == NULL) { | |
d2dff872 | 11255 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 11256 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
11257 | } else |
11258 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 11259 | if (IS_ERR(fb)) { |
d2dff872 | 11260 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 11261 | goto fail; |
79e53945 | 11262 | } |
79e53945 | 11263 | |
d3a40d1b ACO |
11264 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
11265 | if (ret) | |
11266 | goto fail; | |
11267 | ||
edde3617 ML |
11268 | drm_framebuffer_unreference(fb); |
11269 | ||
11270 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
11271 | if (ret) | |
11272 | goto fail; | |
11273 | ||
11274 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
11275 | if (!ret) | |
11276 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
11277 | if (!ret) | |
11278 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
11279 | if (ret) { | |
11280 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
11281 | goto fail; | |
11282 | } | |
8c7b5ccb | 11283 | |
3ba86073 ML |
11284 | ret = drm_atomic_commit(state); |
11285 | if (ret) { | |
6492711d | 11286 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 11287 | goto fail; |
79e53945 | 11288 | } |
edde3617 ML |
11289 | |
11290 | old->restore_state = restore_state; | |
7173188d | 11291 | |
79e53945 | 11292 | /* let the connector get through one full cycle before testing */ |
0f0f74bc | 11293 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
7173188d | 11294 | return true; |
412b61d8 | 11295 | |
ad3c558f | 11296 | fail: |
7fb71c8f CW |
11297 | if (state) { |
11298 | drm_atomic_state_put(state); | |
11299 | state = NULL; | |
11300 | } | |
11301 | if (restore_state) { | |
11302 | drm_atomic_state_put(restore_state); | |
11303 | restore_state = NULL; | |
11304 | } | |
83a57153 | 11305 | |
51fd371b RC |
11306 | if (ret == -EDEADLK) { |
11307 | drm_modeset_backoff(ctx); | |
11308 | goto retry; | |
11309 | } | |
11310 | ||
412b61d8 | 11311 | return false; |
79e53945 JB |
11312 | } |
11313 | ||
d2434ab7 | 11314 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
11315 | struct intel_load_detect_pipe *old, |
11316 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 11317 | { |
d2434ab7 DV |
11318 | struct intel_encoder *intel_encoder = |
11319 | intel_attached_encoder(connector); | |
4ef69c7a | 11320 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 11321 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 11322 | int ret; |
79e53945 | 11323 | |
d2dff872 | 11324 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 11325 | connector->base.id, connector->name, |
8e329a03 | 11326 | encoder->base.id, encoder->name); |
d2dff872 | 11327 | |
edde3617 | 11328 | if (!state) |
0622a53c | 11329 | return; |
79e53945 | 11330 | |
edde3617 | 11331 | ret = drm_atomic_commit(state); |
0853695c | 11332 | if (ret) |
edde3617 | 11333 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); |
0853695c | 11334 | drm_atomic_state_put(state); |
79e53945 JB |
11335 | } |
11336 | ||
da4a1efa | 11337 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 11338 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 11339 | { |
fac5e23e | 11340 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
11341 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
11342 | ||
11343 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 11344 | return dev_priv->vbt.lvds_ssc_freq; |
6e266956 | 11345 | else if (HAS_PCH_SPLIT(dev_priv)) |
da4a1efa | 11346 | return 120000; |
5db94019 | 11347 | else if (!IS_GEN2(dev_priv)) |
da4a1efa VS |
11348 | return 96000; |
11349 | else | |
11350 | return 48000; | |
11351 | } | |
11352 | ||
79e53945 | 11353 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 11354 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 11355 | struct intel_crtc_state *pipe_config) |
79e53945 | 11356 | { |
f1f644dc | 11357 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 11358 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 11359 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 11360 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 11361 | u32 fp; |
9e2c8475 | 11362 | struct dpll clock; |
dccbea3b | 11363 | int port_clock; |
da4a1efa | 11364 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
11365 | |
11366 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 11367 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 11368 | else |
293623f7 | 11369 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
11370 | |
11371 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
9b1e14f4 | 11372 | if (IS_PINEVIEW(dev_priv)) { |
f2b115e6 AJ |
11373 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
11374 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
11375 | } else { |
11376 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
11377 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
11378 | } | |
11379 | ||
5db94019 | 11380 | if (!IS_GEN2(dev_priv)) { |
9b1e14f4 | 11381 | if (IS_PINEVIEW(dev_priv)) |
f2b115e6 AJ |
11382 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
11383 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
11384 | else |
11385 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
11386 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
11387 | ||
11388 | switch (dpll & DPLL_MODE_MASK) { | |
11389 | case DPLLB_MODE_DAC_SERIAL: | |
11390 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
11391 | 5 : 10; | |
11392 | break; | |
11393 | case DPLLB_MODE_LVDS: | |
11394 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
11395 | 7 : 14; | |
11396 | break; | |
11397 | default: | |
28c97730 | 11398 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 11399 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 11400 | return; |
79e53945 JB |
11401 | } |
11402 | ||
9b1e14f4 | 11403 | if (IS_PINEVIEW(dev_priv)) |
dccbea3b | 11404 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 11405 | else |
dccbea3b | 11406 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 11407 | } else { |
50a0bc90 | 11408 | u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); |
b1c560d1 | 11409 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
11410 | |
11411 | if (is_lvds) { | |
11412 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
11413 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
11414 | |
11415 | if (lvds & LVDS_CLKB_POWER_UP) | |
11416 | clock.p2 = 7; | |
11417 | else | |
11418 | clock.p2 = 14; | |
79e53945 JB |
11419 | } else { |
11420 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
11421 | clock.p1 = 2; | |
11422 | else { | |
11423 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
11424 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
11425 | } | |
11426 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
11427 | clock.p2 = 4; | |
11428 | else | |
11429 | clock.p2 = 2; | |
79e53945 | 11430 | } |
da4a1efa | 11431 | |
dccbea3b | 11432 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
11433 | } |
11434 | ||
18442d08 VS |
11435 | /* |
11436 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 11437 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
11438 | * encoder's get_config() function. |
11439 | */ | |
dccbea3b | 11440 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
11441 | } |
11442 | ||
6878da05 VS |
11443 | int intel_dotclock_calculate(int link_freq, |
11444 | const struct intel_link_m_n *m_n) | |
f1f644dc | 11445 | { |
f1f644dc JB |
11446 | /* |
11447 | * The calculation for the data clock is: | |
1041a02f | 11448 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 11449 | * But we want to avoid losing precison if possible, so: |
1041a02f | 11450 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
11451 | * |
11452 | * and the link clock is simpler: | |
1041a02f | 11453 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
11454 | */ |
11455 | ||
6878da05 VS |
11456 | if (!m_n->link_n) |
11457 | return 0; | |
f1f644dc | 11458 | |
6878da05 VS |
11459 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
11460 | } | |
f1f644dc | 11461 | |
18442d08 | 11462 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 11463 | struct intel_crtc_state *pipe_config) |
6878da05 | 11464 | { |
e3b247da | 11465 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 11466 | |
18442d08 VS |
11467 | /* read out port_clock from the DPLL */ |
11468 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 11469 | |
f1f644dc | 11470 | /* |
e3b247da VS |
11471 | * In case there is an active pipe without active ports, |
11472 | * we may need some idea for the dotclock anyway. | |
11473 | * Calculate one based on the FDI configuration. | |
79e53945 | 11474 | */ |
2d112de7 | 11475 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 11476 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 11477 | &pipe_config->fdi_m_n); |
79e53945 JB |
11478 | } |
11479 | ||
11480 | /** Returns the currently programmed mode of the given pipe. */ | |
11481 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
11482 | struct drm_crtc *crtc) | |
11483 | { | |
fac5e23e | 11484 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 11485 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 11486 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 11487 | struct drm_display_mode *mode; |
3f36b937 | 11488 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
11489 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
11490 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
11491 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
11492 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 11493 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
11494 | |
11495 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
11496 | if (!mode) | |
11497 | return NULL; | |
11498 | ||
3f36b937 TU |
11499 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
11500 | if (!pipe_config) { | |
11501 | kfree(mode); | |
11502 | return NULL; | |
11503 | } | |
11504 | ||
f1f644dc JB |
11505 | /* |
11506 | * Construct a pipe_config sufficient for getting the clock info | |
11507 | * back out of crtc_clock_get. | |
11508 | * | |
11509 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
11510 | * to use a real value here instead. | |
11511 | */ | |
3f36b937 TU |
11512 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
11513 | pipe_config->pixel_multiplier = 1; | |
11514 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
11515 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
11516 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
11517 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
11518 | ||
11519 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
11520 | mode->hdisplay = (htot & 0xffff) + 1; |
11521 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
11522 | mode->hsync_start = (hsync & 0xffff) + 1; | |
11523 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
11524 | mode->vdisplay = (vtot & 0xffff) + 1; | |
11525 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
11526 | mode->vsync_start = (vsync & 0xffff) + 1; | |
11527 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
11528 | ||
11529 | drm_mode_set_name(mode); | |
79e53945 | 11530 | |
3f36b937 TU |
11531 | kfree(pipe_config); |
11532 | ||
79e53945 JB |
11533 | return mode; |
11534 | } | |
11535 | ||
11536 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
11537 | { | |
11538 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a | 11539 | struct drm_device *dev = crtc->dev; |
51cbaf01 | 11540 | struct intel_flip_work *work; |
67e77c5a | 11541 | |
5e2d7afc | 11542 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
11543 | work = intel_crtc->flip_work; |
11544 | intel_crtc->flip_work = NULL; | |
11545 | spin_unlock_irq(&dev->event_lock); | |
67e77c5a | 11546 | |
5a21b665 | 11547 | if (work) { |
51cbaf01 ML |
11548 | cancel_work_sync(&work->mmio_work); |
11549 | cancel_work_sync(&work->unpin_work); | |
5a21b665 | 11550 | kfree(work); |
67e77c5a | 11551 | } |
79e53945 JB |
11552 | |
11553 | drm_crtc_cleanup(crtc); | |
67e77c5a | 11554 | |
79e53945 JB |
11555 | kfree(intel_crtc); |
11556 | } | |
11557 | ||
6b95a207 KH |
11558 | static void intel_unpin_work_fn(struct work_struct *__work) |
11559 | { | |
51cbaf01 ML |
11560 | struct intel_flip_work *work = |
11561 | container_of(__work, struct intel_flip_work, unpin_work); | |
5a21b665 DV |
11562 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
11563 | struct drm_device *dev = crtc->base.dev; | |
11564 | struct drm_plane *primary = crtc->base.primary; | |
03f476e1 | 11565 | |
5a21b665 DV |
11566 | if (is_mmio_work(work)) |
11567 | flush_work(&work->mmio_work); | |
03f476e1 | 11568 | |
5a21b665 DV |
11569 | mutex_lock(&dev->struct_mutex); |
11570 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); | |
f8c417cd | 11571 | i915_gem_object_put(work->pending_flip_obj); |
5a21b665 | 11572 | mutex_unlock(&dev->struct_mutex); |
143f73b3 | 11573 | |
e8a261ea CW |
11574 | i915_gem_request_put(work->flip_queued_req); |
11575 | ||
5748b6a1 CW |
11576 | intel_frontbuffer_flip_complete(to_i915(dev), |
11577 | to_intel_plane(primary)->frontbuffer_bit); | |
5a21b665 DV |
11578 | intel_fbc_post_update(crtc); |
11579 | drm_framebuffer_unreference(work->old_fb); | |
143f73b3 | 11580 | |
5a21b665 DV |
11581 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
11582 | atomic_dec(&crtc->unpin_work_count); | |
a6747b73 | 11583 | |
5a21b665 DV |
11584 | kfree(work); |
11585 | } | |
d9e86c0e | 11586 | |
5a21b665 DV |
11587 | /* Is 'a' after or equal to 'b'? */ |
11588 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
11589 | { | |
11590 | return !((a - b) & 0x80000000); | |
11591 | } | |
143f73b3 | 11592 | |
5a21b665 DV |
11593 | static bool __pageflip_finished_cs(struct intel_crtc *crtc, |
11594 | struct intel_flip_work *work) | |
11595 | { | |
11596 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 11597 | struct drm_i915_private *dev_priv = to_i915(dev); |
143f73b3 | 11598 | |
8af29b0c | 11599 | if (abort_flip_on_reset(crtc)) |
5a21b665 | 11600 | return true; |
143f73b3 | 11601 | |
5a21b665 DV |
11602 | /* |
11603 | * The relevant registers doen't exist on pre-ctg. | |
11604 | * As the flip done interrupt doesn't trigger for mmio | |
11605 | * flips on gmch platforms, a flip count check isn't | |
11606 | * really needed there. But since ctg has the registers, | |
11607 | * include it in the check anyway. | |
11608 | */ | |
9beb5fea | 11609 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
5a21b665 | 11610 | return true; |
b4a98e57 | 11611 | |
5a21b665 DV |
11612 | /* |
11613 | * BDW signals flip done immediately if the plane | |
11614 | * is disabled, even if the plane enable is already | |
11615 | * armed to occur at the next vblank :( | |
11616 | */ | |
f99d7069 | 11617 | |
5a21b665 DV |
11618 | /* |
11619 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
11620 | * used the same base address. In that case the mmio flip might | |
11621 | * have completed, but the CS hasn't even executed the flip yet. | |
11622 | * | |
11623 | * A flip count check isn't enough as the CS might have updated | |
11624 | * the base address just after start of vblank, but before we | |
11625 | * managed to process the interrupt. This means we'd complete the | |
11626 | * CS flip too soon. | |
11627 | * | |
11628 | * Combining both checks should get us a good enough result. It may | |
11629 | * still happen that the CS flip has been executed, but has not | |
11630 | * yet actually completed. But in case the base address is the same | |
11631 | * anyway, we don't really care. | |
11632 | */ | |
11633 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
11634 | crtc->flip_work->gtt_offset && | |
11635 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), | |
11636 | crtc->flip_work->flip_count); | |
11637 | } | |
b4a98e57 | 11638 | |
5a21b665 DV |
11639 | static bool |
11640 | __pageflip_finished_mmio(struct intel_crtc *crtc, | |
11641 | struct intel_flip_work *work) | |
11642 | { | |
11643 | /* | |
11644 | * MMIO work completes when vblank is different from | |
11645 | * flip_queued_vblank. | |
11646 | * | |
11647 | * Reset counter value doesn't matter, this is handled by | |
11648 | * i915_wait_request finishing early, so no need to handle | |
11649 | * reset here. | |
11650 | */ | |
11651 | return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; | |
6b95a207 KH |
11652 | } |
11653 | ||
51cbaf01 ML |
11654 | |
11655 | static bool pageflip_finished(struct intel_crtc *crtc, | |
11656 | struct intel_flip_work *work) | |
11657 | { | |
11658 | if (!atomic_read(&work->pending)) | |
11659 | return false; | |
11660 | ||
11661 | smp_rmb(); | |
11662 | ||
5a21b665 DV |
11663 | if (is_mmio_work(work)) |
11664 | return __pageflip_finished_mmio(crtc, work); | |
11665 | else | |
11666 | return __pageflip_finished_cs(crtc, work); | |
11667 | } | |
11668 | ||
11669 | void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) | |
11670 | { | |
91c8a326 | 11671 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 11672 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
5a21b665 DV |
11673 | struct intel_flip_work *work; |
11674 | unsigned long flags; | |
11675 | ||
11676 | /* Ignore early vblank irqs */ | |
11677 | if (!crtc) | |
11678 | return; | |
11679 | ||
51cbaf01 | 11680 | /* |
5a21b665 DV |
11681 | * This is called both by irq handlers and the reset code (to complete |
11682 | * lost pageflips) so needs the full irqsave spinlocks. | |
51cbaf01 | 11683 | */ |
5a21b665 | 11684 | spin_lock_irqsave(&dev->event_lock, flags); |
e2af48c6 | 11685 | work = crtc->flip_work; |
5a21b665 DV |
11686 | |
11687 | if (work != NULL && | |
11688 | !is_mmio_work(work) && | |
e2af48c6 VS |
11689 | pageflip_finished(crtc, work)) |
11690 | page_flip_completed(crtc); | |
5a21b665 DV |
11691 | |
11692 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
75f7f3ec VS |
11693 | } |
11694 | ||
51cbaf01 | 11695 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) |
6b95a207 | 11696 | { |
91c8a326 | 11697 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 11698 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
51cbaf01 | 11699 | struct intel_flip_work *work; |
6b95a207 KH |
11700 | unsigned long flags; |
11701 | ||
5251f04e ML |
11702 | /* Ignore early vblank irqs */ |
11703 | if (!crtc) | |
11704 | return; | |
f326038a DV |
11705 | |
11706 | /* | |
11707 | * This is called both by irq handlers and the reset code (to complete | |
11708 | * lost pageflips) so needs the full irqsave spinlocks. | |
e7d841ca | 11709 | */ |
6b95a207 | 11710 | spin_lock_irqsave(&dev->event_lock, flags); |
e2af48c6 | 11711 | work = crtc->flip_work; |
5251f04e | 11712 | |
5a21b665 DV |
11713 | if (work != NULL && |
11714 | is_mmio_work(work) && | |
e2af48c6 VS |
11715 | pageflip_finished(crtc, work)) |
11716 | page_flip_completed(crtc); | |
5251f04e | 11717 | |
6b95a207 KH |
11718 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11719 | } | |
11720 | ||
5a21b665 DV |
11721 | static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, |
11722 | struct intel_flip_work *work) | |
84c33a64 | 11723 | { |
5a21b665 | 11724 | work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); |
84c33a64 | 11725 | |
5a21b665 DV |
11726 | /* Ensure that the work item is consistent when activating it ... */ |
11727 | smp_mb__before_atomic(); | |
11728 | atomic_set(&work->pending, 1); | |
11729 | } | |
a6747b73 | 11730 | |
5a21b665 DV |
11731 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11732 | struct drm_crtc *crtc, | |
11733 | struct drm_framebuffer *fb, | |
11734 | struct drm_i915_gem_object *obj, | |
11735 | struct drm_i915_gem_request *req, | |
11736 | uint32_t flags) | |
11737 | { | |
7e37f889 | 11738 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11739 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11740 | u32 flip_mask; | |
11741 | int ret; | |
143f73b3 | 11742 | |
5a21b665 DV |
11743 | ret = intel_ring_begin(req, 6); |
11744 | if (ret) | |
11745 | return ret; | |
143f73b3 | 11746 | |
5a21b665 DV |
11747 | /* Can't queue multiple flips, so wait for the previous |
11748 | * one to finish before executing the next. | |
11749 | */ | |
11750 | if (intel_crtc->plane) | |
11751 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11752 | else | |
11753 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
b5321f30 CW |
11754 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11755 | intel_ring_emit(ring, MI_NOOP); | |
11756 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
5a21b665 | 11757 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11758 | intel_ring_emit(ring, fb->pitches[0]); |
11759 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); | |
11760 | intel_ring_emit(ring, 0); /* aux display base address, unused */ | |
143f73b3 | 11761 | |
5a21b665 DV |
11762 | return 0; |
11763 | } | |
84c33a64 | 11764 | |
5a21b665 DV |
11765 | static int intel_gen3_queue_flip(struct drm_device *dev, |
11766 | struct drm_crtc *crtc, | |
11767 | struct drm_framebuffer *fb, | |
11768 | struct drm_i915_gem_object *obj, | |
11769 | struct drm_i915_gem_request *req, | |
11770 | uint32_t flags) | |
11771 | { | |
7e37f889 | 11772 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11773 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11774 | u32 flip_mask; | |
11775 | int ret; | |
d55dbd06 | 11776 | |
5a21b665 DV |
11777 | ret = intel_ring_begin(req, 6); |
11778 | if (ret) | |
11779 | return ret; | |
d55dbd06 | 11780 | |
5a21b665 DV |
11781 | if (intel_crtc->plane) |
11782 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11783 | else | |
11784 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
b5321f30 CW |
11785 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11786 | intel_ring_emit(ring, MI_NOOP); | |
11787 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
5a21b665 | 11788 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11789 | intel_ring_emit(ring, fb->pitches[0]); |
11790 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); | |
11791 | intel_ring_emit(ring, MI_NOOP); | |
fd8e058a | 11792 | |
5a21b665 DV |
11793 | return 0; |
11794 | } | |
84c33a64 | 11795 | |
5a21b665 DV |
11796 | static int intel_gen4_queue_flip(struct drm_device *dev, |
11797 | struct drm_crtc *crtc, | |
11798 | struct drm_framebuffer *fb, | |
11799 | struct drm_i915_gem_object *obj, | |
11800 | struct drm_i915_gem_request *req, | |
11801 | uint32_t flags) | |
11802 | { | |
7e37f889 | 11803 | struct intel_ring *ring = req->ring; |
fac5e23e | 11804 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11805 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11806 | uint32_t pf, pipesrc; | |
11807 | int ret; | |
143f73b3 | 11808 | |
5a21b665 DV |
11809 | ret = intel_ring_begin(req, 4); |
11810 | if (ret) | |
11811 | return ret; | |
143f73b3 | 11812 | |
5a21b665 DV |
11813 | /* i965+ uses the linear or tiled offsets from the |
11814 | * Display Registers (which do not change across a page-flip) | |
11815 | * so we need only reprogram the base address. | |
11816 | */ | |
b5321f30 | 11817 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
5a21b665 | 11818 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
b5321f30 CW |
11819 | intel_ring_emit(ring, fb->pitches[0]); |
11820 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset | | |
72618ebf | 11821 | intel_fb_modifier_to_tiling(fb->modifier[0])); |
5a21b665 DV |
11822 | |
11823 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11824 | * untested on non-native modes, so ignore it for now. | |
11825 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11826 | */ | |
11827 | pf = 0; | |
11828 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
b5321f30 | 11829 | intel_ring_emit(ring, pf | pipesrc); |
143f73b3 | 11830 | |
5a21b665 | 11831 | return 0; |
8c9f3aaf JB |
11832 | } |
11833 | ||
5a21b665 DV |
11834 | static int intel_gen6_queue_flip(struct drm_device *dev, |
11835 | struct drm_crtc *crtc, | |
11836 | struct drm_framebuffer *fb, | |
11837 | struct drm_i915_gem_object *obj, | |
11838 | struct drm_i915_gem_request *req, | |
11839 | uint32_t flags) | |
da20eabd | 11840 | { |
7e37f889 | 11841 | struct intel_ring *ring = req->ring; |
fac5e23e | 11842 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
11843 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11844 | uint32_t pf, pipesrc; | |
11845 | int ret; | |
d21fbe87 | 11846 | |
5a21b665 DV |
11847 | ret = intel_ring_begin(req, 4); |
11848 | if (ret) | |
11849 | return ret; | |
92826fcd | 11850 | |
b5321f30 | 11851 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
5a21b665 | 11852 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
72618ebf VS |
11853 | intel_ring_emit(ring, fb->pitches[0] | |
11854 | intel_fb_modifier_to_tiling(fb->modifier[0])); | |
b5321f30 | 11855 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
92826fcd | 11856 | |
5a21b665 DV |
11857 | /* Contrary to the suggestions in the documentation, |
11858 | * "Enable Panel Fitter" does not seem to be required when page | |
11859 | * flipping with a non-native mode, and worse causes a normal | |
11860 | * modeset to fail. | |
11861 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11862 | */ | |
11863 | pf = 0; | |
11864 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
b5321f30 | 11865 | intel_ring_emit(ring, pf | pipesrc); |
7809e5ae | 11866 | |
5a21b665 | 11867 | return 0; |
7809e5ae MR |
11868 | } |
11869 | ||
5a21b665 DV |
11870 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11871 | struct drm_crtc *crtc, | |
11872 | struct drm_framebuffer *fb, | |
11873 | struct drm_i915_gem_object *obj, | |
11874 | struct drm_i915_gem_request *req, | |
11875 | uint32_t flags) | |
d21fbe87 | 11876 | { |
5db94019 | 11877 | struct drm_i915_private *dev_priv = to_i915(dev); |
7e37f889 | 11878 | struct intel_ring *ring = req->ring; |
5a21b665 DV |
11879 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11880 | uint32_t plane_bit = 0; | |
11881 | int len, ret; | |
d21fbe87 | 11882 | |
5a21b665 DV |
11883 | switch (intel_crtc->plane) { |
11884 | case PLANE_A: | |
11885 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11886 | break; | |
11887 | case PLANE_B: | |
11888 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11889 | break; | |
11890 | case PLANE_C: | |
11891 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11892 | break; | |
11893 | default: | |
11894 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
11895 | return -ENODEV; | |
11896 | } | |
11897 | ||
11898 | len = 4; | |
b5321f30 | 11899 | if (req->engine->id == RCS) { |
5a21b665 DV |
11900 | len += 6; |
11901 | /* | |
11902 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11903 | * 48bits addresses, and we need a NOOP for the batch size to | |
11904 | * stay even. | |
11905 | */ | |
5db94019 | 11906 | if (IS_GEN8(dev_priv)) |
5a21b665 DV |
11907 | len += 2; |
11908 | } | |
11909 | ||
11910 | /* | |
11911 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11912 | * "The full packet must be contained within the same cache line." | |
11913 | * | |
11914 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11915 | * cacheline, if we ever start emitting more commands before | |
11916 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11917 | * then do the cacheline alignment, and finally emit the | |
11918 | * MI_DISPLAY_FLIP. | |
11919 | */ | |
11920 | ret = intel_ring_cacheline_align(req); | |
11921 | if (ret) | |
11922 | return ret; | |
11923 | ||
11924 | ret = intel_ring_begin(req, len); | |
11925 | if (ret) | |
11926 | return ret; | |
11927 | ||
11928 | /* Unmask the flip-done completion message. Note that the bspec says that | |
11929 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11930 | * more than one flip event at any time (or ensure that one flip message | |
11931 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11932 | * Experimentation says that BCS works despite DERRMR masking all | |
11933 | * flip-done completion events and that unmasking all planes at once | |
11934 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11935 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11936 | */ | |
b5321f30 CW |
11937 | if (req->engine->id == RCS) { |
11938 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
11939 | intel_ring_emit_reg(ring, DERRMR); | |
11940 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
5a21b665 DV |
11941 | DERRMR_PIPEB_PRI_FLIP_DONE | |
11942 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
5db94019 | 11943 | if (IS_GEN8(dev_priv)) |
b5321f30 | 11944 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
5a21b665 DV |
11945 | MI_SRM_LRM_GLOBAL_GTT); |
11946 | else | |
b5321f30 | 11947 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
5a21b665 | 11948 | MI_SRM_LRM_GLOBAL_GTT); |
b5321f30 | 11949 | intel_ring_emit_reg(ring, DERRMR); |
bde13ebd CW |
11950 | intel_ring_emit(ring, |
11951 | i915_ggtt_offset(req->engine->scratch) + 256); | |
5db94019 | 11952 | if (IS_GEN8(dev_priv)) { |
b5321f30 CW |
11953 | intel_ring_emit(ring, 0); |
11954 | intel_ring_emit(ring, MI_NOOP); | |
5a21b665 DV |
11955 | } |
11956 | } | |
11957 | ||
b5321f30 | 11958 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
72618ebf VS |
11959 | intel_ring_emit(ring, fb->pitches[0] | |
11960 | intel_fb_modifier_to_tiling(fb->modifier[0])); | |
b5321f30 CW |
11961 | intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset); |
11962 | intel_ring_emit(ring, (MI_NOOP)); | |
5a21b665 DV |
11963 | |
11964 | return 0; | |
11965 | } | |
11966 | ||
11967 | static bool use_mmio_flip(struct intel_engine_cs *engine, | |
11968 | struct drm_i915_gem_object *obj) | |
11969 | { | |
11970 | /* | |
11971 | * This is not being used for older platforms, because | |
11972 | * non-availability of flip done interrupt forces us to use | |
11973 | * CS flips. Older platforms derive flip done using some clever | |
11974 | * tricks involving the flip_pending status bits and vblank irqs. | |
11975 | * So using MMIO flips there would disrupt this mechanism. | |
11976 | */ | |
11977 | ||
11978 | if (engine == NULL) | |
11979 | return true; | |
11980 | ||
11981 | if (INTEL_GEN(engine->i915) < 5) | |
11982 | return false; | |
11983 | ||
11984 | if (i915.use_mmio_flip < 0) | |
11985 | return false; | |
11986 | else if (i915.use_mmio_flip > 0) | |
11987 | return true; | |
11988 | else if (i915.enable_execlists) | |
11989 | return true; | |
c37efb99 | 11990 | |
d07f0e59 | 11991 | return engine != i915_gem_object_last_write_engine(obj); |
5a21b665 DV |
11992 | } |
11993 | ||
11994 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, | |
11995 | unsigned int rotation, | |
11996 | struct intel_flip_work *work) | |
11997 | { | |
11998 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 11999 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
12000 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
12001 | const enum pipe pipe = intel_crtc->pipe; | |
d2196774 | 12002 | u32 ctl, stride = skl_plane_stride(fb, 0, rotation); |
5a21b665 DV |
12003 | |
12004 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
12005 | ctl &= ~PLANE_CTL_TILED_MASK; | |
12006 | switch (fb->modifier[0]) { | |
12007 | case DRM_FORMAT_MOD_NONE: | |
12008 | break; | |
12009 | case I915_FORMAT_MOD_X_TILED: | |
12010 | ctl |= PLANE_CTL_TILED_X; | |
12011 | break; | |
12012 | case I915_FORMAT_MOD_Y_TILED: | |
12013 | ctl |= PLANE_CTL_TILED_Y; | |
12014 | break; | |
12015 | case I915_FORMAT_MOD_Yf_TILED: | |
12016 | ctl |= PLANE_CTL_TILED_YF; | |
12017 | break; | |
12018 | default: | |
12019 | MISSING_CASE(fb->modifier[0]); | |
12020 | } | |
12021 | ||
5a21b665 DV |
12022 | /* |
12023 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
12024 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
12025 | */ | |
12026 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
12027 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
12028 | ||
12029 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); | |
12030 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
12031 | } | |
12032 | ||
12033 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, | |
12034 | struct intel_flip_work *work) | |
12035 | { | |
12036 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 12037 | struct drm_i915_private *dev_priv = to_i915(dev); |
72618ebf | 12038 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
5a21b665 DV |
12039 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
12040 | u32 dspcntr; | |
12041 | ||
12042 | dspcntr = I915_READ(reg); | |
12043 | ||
72618ebf | 12044 | if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) |
5a21b665 DV |
12045 | dspcntr |= DISPPLANE_TILED; |
12046 | else | |
12047 | dspcntr &= ~DISPPLANE_TILED; | |
12048 | ||
12049 | I915_WRITE(reg, dspcntr); | |
12050 | ||
12051 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); | |
12052 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
12053 | } | |
12054 | ||
12055 | static void intel_mmio_flip_work_func(struct work_struct *w) | |
12056 | { | |
12057 | struct intel_flip_work *work = | |
12058 | container_of(w, struct intel_flip_work, mmio_work); | |
12059 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); | |
12060 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
12061 | struct intel_framebuffer *intel_fb = | |
12062 | to_intel_framebuffer(crtc->base.primary->fb); | |
12063 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
12064 | ||
d07f0e59 | 12065 | WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0); |
5a21b665 DV |
12066 | |
12067 | intel_pipe_update_start(crtc); | |
12068 | ||
12069 | if (INTEL_GEN(dev_priv) >= 9) | |
12070 | skl_do_mmio_flip(crtc, work->rotation, work); | |
12071 | else | |
12072 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
12073 | ilk_do_mmio_flip(crtc, work); | |
12074 | ||
12075 | intel_pipe_update_end(crtc, work); | |
12076 | } | |
12077 | ||
12078 | static int intel_default_queue_flip(struct drm_device *dev, | |
12079 | struct drm_crtc *crtc, | |
12080 | struct drm_framebuffer *fb, | |
12081 | struct drm_i915_gem_object *obj, | |
12082 | struct drm_i915_gem_request *req, | |
12083 | uint32_t flags) | |
12084 | { | |
12085 | return -ENODEV; | |
12086 | } | |
12087 | ||
12088 | static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, | |
12089 | struct intel_crtc *intel_crtc, | |
12090 | struct intel_flip_work *work) | |
12091 | { | |
12092 | u32 addr, vblank; | |
12093 | ||
12094 | if (!atomic_read(&work->pending)) | |
12095 | return false; | |
12096 | ||
12097 | smp_rmb(); | |
12098 | ||
12099 | vblank = intel_crtc_get_vblank_counter(intel_crtc); | |
12100 | if (work->flip_ready_vblank == 0) { | |
12101 | if (work->flip_queued_req && | |
f69a02c9 | 12102 | !i915_gem_request_completed(work->flip_queued_req)) |
5a21b665 DV |
12103 | return false; |
12104 | ||
12105 | work->flip_ready_vblank = vblank; | |
12106 | } | |
12107 | ||
12108 | if (vblank - work->flip_ready_vblank < 3) | |
12109 | return false; | |
12110 | ||
12111 | /* Potential stall - if we see that the flip has happened, | |
12112 | * assume a missed interrupt. */ | |
12113 | if (INTEL_GEN(dev_priv) >= 4) | |
12114 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
12115 | else | |
12116 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
12117 | ||
12118 | /* There is a potential issue here with a false positive after a flip | |
12119 | * to the same address. We could address this by checking for a | |
12120 | * non-incrementing frame counter. | |
12121 | */ | |
12122 | return addr == work->gtt_offset; | |
12123 | } | |
12124 | ||
12125 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) | |
12126 | { | |
91c8a326 | 12127 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 12128 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
5a21b665 DV |
12129 | struct intel_flip_work *work; |
12130 | ||
12131 | WARN_ON(!in_interrupt()); | |
12132 | ||
12133 | if (crtc == NULL) | |
12134 | return; | |
12135 | ||
12136 | spin_lock(&dev->event_lock); | |
e2af48c6 | 12137 | work = crtc->flip_work; |
5a21b665 DV |
12138 | |
12139 | if (work != NULL && !is_mmio_work(work) && | |
e2af48c6 | 12140 | __pageflip_stall_check_cs(dev_priv, crtc, work)) { |
5a21b665 DV |
12141 | WARN_ONCE(1, |
12142 | "Kicking stuck page flip: queued at %d, now %d\n", | |
e2af48c6 VS |
12143 | work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc)); |
12144 | page_flip_completed(crtc); | |
5a21b665 DV |
12145 | work = NULL; |
12146 | } | |
12147 | ||
12148 | if (work != NULL && !is_mmio_work(work) && | |
e2af48c6 | 12149 | intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1) |
5a21b665 DV |
12150 | intel_queue_rps_boost_for_request(work->flip_queued_req); |
12151 | spin_unlock(&dev->event_lock); | |
12152 | } | |
12153 | ||
12154 | static int intel_crtc_page_flip(struct drm_crtc *crtc, | |
12155 | struct drm_framebuffer *fb, | |
12156 | struct drm_pending_vblank_event *event, | |
12157 | uint32_t page_flip_flags) | |
12158 | { | |
12159 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 12160 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
12161 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
12162 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
12163 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12164 | struct drm_plane *primary = crtc->primary; | |
12165 | enum pipe pipe = intel_crtc->pipe; | |
12166 | struct intel_flip_work *work; | |
12167 | struct intel_engine_cs *engine; | |
12168 | bool mmio_flip; | |
8e637178 | 12169 | struct drm_i915_gem_request *request; |
058d88c4 | 12170 | struct i915_vma *vma; |
5a21b665 DV |
12171 | int ret; |
12172 | ||
12173 | /* | |
12174 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
12175 | * check to be safe. In the future we may enable pageflipping from | |
12176 | * a disabled primary plane. | |
12177 | */ | |
12178 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
12179 | return -EBUSY; | |
12180 | ||
12181 | /* Can't change pixel format via MI display flips. */ | |
12182 | if (fb->pixel_format != crtc->primary->fb->pixel_format) | |
12183 | return -EINVAL; | |
12184 | ||
12185 | /* | |
12186 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
12187 | * Note that pitch changes could also affect these register. | |
12188 | */ | |
12189 | if (INTEL_INFO(dev)->gen > 3 && | |
12190 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || | |
12191 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
12192 | return -EINVAL; | |
12193 | ||
12194 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
12195 | goto out_hang; | |
12196 | ||
12197 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
12198 | if (work == NULL) | |
12199 | return -ENOMEM; | |
12200 | ||
12201 | work->event = event; | |
12202 | work->crtc = crtc; | |
12203 | work->old_fb = old_fb; | |
12204 | INIT_WORK(&work->unpin_work, intel_unpin_work_fn); | |
12205 | ||
12206 | ret = drm_crtc_vblank_get(crtc); | |
12207 | if (ret) | |
12208 | goto free_work; | |
12209 | ||
12210 | /* We borrow the event spin lock for protecting flip_work */ | |
12211 | spin_lock_irq(&dev->event_lock); | |
12212 | if (intel_crtc->flip_work) { | |
12213 | /* Before declaring the flip queue wedged, check if | |
12214 | * the hardware completed the operation behind our backs. | |
12215 | */ | |
12216 | if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { | |
12217 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
12218 | page_flip_completed(intel_crtc); | |
12219 | } else { | |
12220 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
12221 | spin_unlock_irq(&dev->event_lock); | |
12222 | ||
12223 | drm_crtc_vblank_put(crtc); | |
12224 | kfree(work); | |
12225 | return -EBUSY; | |
12226 | } | |
12227 | } | |
12228 | intel_crtc->flip_work = work; | |
12229 | spin_unlock_irq(&dev->event_lock); | |
12230 | ||
12231 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) | |
12232 | flush_workqueue(dev_priv->wq); | |
12233 | ||
12234 | /* Reference the objects for the scheduled work. */ | |
12235 | drm_framebuffer_reference(work->old_fb); | |
5a21b665 DV |
12236 | |
12237 | crtc->primary->fb = fb; | |
12238 | update_state_fb(crtc->primary); | |
faf68d92 | 12239 | |
25dc556a | 12240 | work->pending_flip_obj = i915_gem_object_get(obj); |
5a21b665 DV |
12241 | |
12242 | ret = i915_mutex_lock_interruptible(dev); | |
12243 | if (ret) | |
12244 | goto cleanup; | |
12245 | ||
8af29b0c CW |
12246 | intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error); |
12247 | if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) { | |
5a21b665 DV |
12248 | ret = -EIO; |
12249 | goto cleanup; | |
12250 | } | |
12251 | ||
12252 | atomic_inc(&intel_crtc->unpin_work_count); | |
12253 | ||
9beb5fea | 12254 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
5a21b665 DV |
12255 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
12256 | ||
920a14b2 | 12257 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3b3f1650 | 12258 | engine = dev_priv->engine[BCS]; |
72618ebf | 12259 | if (fb->modifier[0] != old_fb->modifier[0]) |
5a21b665 DV |
12260 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
12261 | engine = NULL; | |
fd6b8f43 | 12262 | } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { |
3b3f1650 | 12263 | engine = dev_priv->engine[BCS]; |
5a21b665 | 12264 | } else if (INTEL_INFO(dev)->gen >= 7) { |
d07f0e59 | 12265 | engine = i915_gem_object_last_write_engine(obj); |
5a21b665 | 12266 | if (engine == NULL || engine->id != RCS) |
3b3f1650 | 12267 | engine = dev_priv->engine[BCS]; |
5a21b665 | 12268 | } else { |
3b3f1650 | 12269 | engine = dev_priv->engine[RCS]; |
5a21b665 DV |
12270 | } |
12271 | ||
12272 | mmio_flip = use_mmio_flip(engine, obj); | |
12273 | ||
058d88c4 CW |
12274 | vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
12275 | if (IS_ERR(vma)) { | |
12276 | ret = PTR_ERR(vma); | |
5a21b665 | 12277 | goto cleanup_pending; |
058d88c4 | 12278 | } |
5a21b665 | 12279 | |
6687c906 | 12280 | work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation); |
5a21b665 DV |
12281 | work->gtt_offset += intel_crtc->dspaddr_offset; |
12282 | work->rotation = crtc->primary->state->rotation; | |
12283 | ||
1f061316 PZ |
12284 | /* |
12285 | * There's the potential that the next frame will not be compatible with | |
12286 | * FBC, so we want to call pre_update() before the actual page flip. | |
12287 | * The problem is that pre_update() caches some information about the fb | |
12288 | * object, so we want to do this only after the object is pinned. Let's | |
12289 | * be on the safe side and do this immediately before scheduling the | |
12290 | * flip. | |
12291 | */ | |
12292 | intel_fbc_pre_update(intel_crtc, intel_crtc->config, | |
12293 | to_intel_plane_state(primary->state)); | |
12294 | ||
5a21b665 DV |
12295 | if (mmio_flip) { |
12296 | INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); | |
6277c8d0 | 12297 | queue_work(system_unbound_wq, &work->mmio_work); |
5a21b665 | 12298 | } else { |
8e637178 CW |
12299 | request = i915_gem_request_alloc(engine, engine->last_context); |
12300 | if (IS_ERR(request)) { | |
12301 | ret = PTR_ERR(request); | |
12302 | goto cleanup_unpin; | |
12303 | } | |
12304 | ||
a2bc4695 | 12305 | ret = i915_gem_request_await_object(request, obj, false); |
8e637178 CW |
12306 | if (ret) |
12307 | goto cleanup_request; | |
12308 | ||
5a21b665 DV |
12309 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
12310 | page_flip_flags); | |
12311 | if (ret) | |
8e637178 | 12312 | goto cleanup_request; |
5a21b665 DV |
12313 | |
12314 | intel_mark_page_flip_active(intel_crtc, work); | |
12315 | ||
8e637178 | 12316 | work->flip_queued_req = i915_gem_request_get(request); |
5a21b665 DV |
12317 | i915_add_request_no_flush(request); |
12318 | } | |
12319 | ||
12320 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, | |
12321 | to_intel_plane(primary)->frontbuffer_bit); | |
12322 | mutex_unlock(&dev->struct_mutex); | |
12323 | ||
5748b6a1 | 12324 | intel_frontbuffer_flip_prepare(to_i915(dev), |
5a21b665 DV |
12325 | to_intel_plane(primary)->frontbuffer_bit); |
12326 | ||
12327 | trace_i915_flip_request(intel_crtc->plane, obj); | |
12328 | ||
12329 | return 0; | |
12330 | ||
8e637178 CW |
12331 | cleanup_request: |
12332 | i915_add_request_no_flush(request); | |
5a21b665 DV |
12333 | cleanup_unpin: |
12334 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); | |
12335 | cleanup_pending: | |
5a21b665 DV |
12336 | atomic_dec(&intel_crtc->unpin_work_count); |
12337 | mutex_unlock(&dev->struct_mutex); | |
12338 | cleanup: | |
12339 | crtc->primary->fb = old_fb; | |
12340 | update_state_fb(crtc->primary); | |
12341 | ||
f0cd5182 | 12342 | i915_gem_object_put(obj); |
5a21b665 DV |
12343 | drm_framebuffer_unreference(work->old_fb); |
12344 | ||
12345 | spin_lock_irq(&dev->event_lock); | |
12346 | intel_crtc->flip_work = NULL; | |
12347 | spin_unlock_irq(&dev->event_lock); | |
12348 | ||
12349 | drm_crtc_vblank_put(crtc); | |
12350 | free_work: | |
12351 | kfree(work); | |
12352 | ||
12353 | if (ret == -EIO) { | |
12354 | struct drm_atomic_state *state; | |
12355 | struct drm_plane_state *plane_state; | |
12356 | ||
12357 | out_hang: | |
12358 | state = drm_atomic_state_alloc(dev); | |
12359 | if (!state) | |
12360 | return -ENOMEM; | |
12361 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
12362 | ||
12363 | retry: | |
12364 | plane_state = drm_atomic_get_plane_state(state, primary); | |
12365 | ret = PTR_ERR_OR_ZERO(plane_state); | |
12366 | if (!ret) { | |
12367 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
12368 | ||
12369 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
12370 | if (!ret) | |
12371 | ret = drm_atomic_commit(state); | |
12372 | } | |
12373 | ||
12374 | if (ret == -EDEADLK) { | |
12375 | drm_modeset_backoff(state->acquire_ctx); | |
12376 | drm_atomic_state_clear(state); | |
12377 | goto retry; | |
12378 | } | |
12379 | ||
0853695c | 12380 | drm_atomic_state_put(state); |
5a21b665 DV |
12381 | |
12382 | if (ret == 0 && event) { | |
12383 | spin_lock_irq(&dev->event_lock); | |
12384 | drm_crtc_send_vblank_event(crtc, event); | |
12385 | spin_unlock_irq(&dev->event_lock); | |
12386 | } | |
12387 | } | |
12388 | return ret; | |
12389 | } | |
12390 | ||
12391 | ||
12392 | /** | |
12393 | * intel_wm_need_update - Check whether watermarks need updating | |
12394 | * @plane: drm plane | |
12395 | * @state: new plane state | |
12396 | * | |
12397 | * Check current plane state versus the new one to determine whether | |
12398 | * watermarks need to be recalculated. | |
12399 | * | |
12400 | * Returns true or false. | |
12401 | */ | |
12402 | static bool intel_wm_need_update(struct drm_plane *plane, | |
12403 | struct drm_plane_state *state) | |
12404 | { | |
12405 | struct intel_plane_state *new = to_intel_plane_state(state); | |
12406 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
12407 | ||
12408 | /* Update watermarks on tiling or size changes. */ | |
936e71e3 | 12409 | if (new->base.visible != cur->base.visible) |
5a21b665 DV |
12410 | return true; |
12411 | ||
12412 | if (!cur->base.fb || !new->base.fb) | |
12413 | return false; | |
12414 | ||
12415 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
12416 | cur->base.rotation != new->base.rotation || | |
936e71e3 VS |
12417 | drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) || |
12418 | drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) || | |
12419 | drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) || | |
12420 | drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst)) | |
5a21b665 DV |
12421 | return true; |
12422 | ||
12423 | return false; | |
12424 | } | |
12425 | ||
12426 | static bool needs_scaling(struct intel_plane_state *state) | |
12427 | { | |
936e71e3 VS |
12428 | int src_w = drm_rect_width(&state->base.src) >> 16; |
12429 | int src_h = drm_rect_height(&state->base.src) >> 16; | |
12430 | int dst_w = drm_rect_width(&state->base.dst); | |
12431 | int dst_h = drm_rect_height(&state->base.dst); | |
5a21b665 DV |
12432 | |
12433 | return (src_w != dst_w || src_h != dst_h); | |
12434 | } | |
d21fbe87 | 12435 | |
da20eabd ML |
12436 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
12437 | struct drm_plane_state *plane_state) | |
12438 | { | |
ab1d3a0e | 12439 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
12440 | struct drm_crtc *crtc = crtc_state->crtc; |
12441 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12442 | struct drm_plane *plane = plane_state->plane; | |
12443 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 12444 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
12445 | struct intel_plane_state *old_plane_state = |
12446 | to_intel_plane_state(plane->state); | |
da20eabd ML |
12447 | bool mode_changed = needs_modeset(crtc_state); |
12448 | bool was_crtc_enabled = crtc->state->active; | |
12449 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
12450 | bool turn_off, turn_on, visible, was_visible; |
12451 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 12452 | int ret; |
da20eabd | 12453 | |
55b8f2a7 | 12454 | if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) { |
da20eabd ML |
12455 | ret = skl_update_scaler_plane( |
12456 | to_intel_crtc_state(crtc_state), | |
12457 | to_intel_plane_state(plane_state)); | |
12458 | if (ret) | |
12459 | return ret; | |
12460 | } | |
12461 | ||
936e71e3 VS |
12462 | was_visible = old_plane_state->base.visible; |
12463 | visible = to_intel_plane_state(plane_state)->base.visible; | |
da20eabd ML |
12464 | |
12465 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
12466 | was_visible = false; | |
12467 | ||
35c08f43 ML |
12468 | /* |
12469 | * Visibility is calculated as if the crtc was on, but | |
12470 | * after scaler setup everything depends on it being off | |
12471 | * when the crtc isn't active. | |
f818ffea VS |
12472 | * |
12473 | * FIXME this is wrong for watermarks. Watermarks should also | |
12474 | * be computed as if the pipe would be active. Perhaps move | |
12475 | * per-plane wm computation to the .check_plane() hook, and | |
12476 | * only combine the results from all planes in the current place? | |
35c08f43 ML |
12477 | */ |
12478 | if (!is_crtc_enabled) | |
936e71e3 | 12479 | to_intel_plane_state(plane_state)->base.visible = visible = false; |
da20eabd ML |
12480 | |
12481 | if (!was_visible && !visible) | |
12482 | return 0; | |
12483 | ||
e8861675 ML |
12484 | if (fb != old_plane_state->base.fb) |
12485 | pipe_config->fb_changed = true; | |
12486 | ||
da20eabd ML |
12487 | turn_off = was_visible && (!visible || mode_changed); |
12488 | turn_on = visible && (!was_visible || mode_changed); | |
12489 | ||
72660ce0 | 12490 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
78108b7c VS |
12491 | intel_crtc->base.base.id, |
12492 | intel_crtc->base.name, | |
72660ce0 VS |
12493 | plane->base.id, plane->name, |
12494 | fb ? fb->base.id : -1); | |
da20eabd | 12495 | |
72660ce0 VS |
12496 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
12497 | plane->base.id, plane->name, | |
12498 | was_visible, visible, | |
da20eabd ML |
12499 | turn_off, turn_on, mode_changed); |
12500 | ||
caed361d VS |
12501 | if (turn_on) { |
12502 | pipe_config->update_wm_pre = true; | |
12503 | ||
12504 | /* must disable cxsr around plane enable/disable */ | |
12505 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
12506 | pipe_config->disable_cxsr = true; | |
12507 | } else if (turn_off) { | |
12508 | pipe_config->update_wm_post = true; | |
92826fcd | 12509 | |
852eb00d | 12510 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 12511 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 12512 | pipe_config->disable_cxsr = true; |
852eb00d | 12513 | } else if (intel_wm_need_update(plane, plane_state)) { |
caed361d VS |
12514 | /* FIXME bollocks */ |
12515 | pipe_config->update_wm_pre = true; | |
12516 | pipe_config->update_wm_post = true; | |
852eb00d | 12517 | } |
da20eabd | 12518 | |
ed4a6a7c | 12519 | /* Pre-gen9 platforms need two-step watermark updates */ |
caed361d VS |
12520 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
12521 | INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) | |
ed4a6a7c MR |
12522 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
12523 | ||
8be6ca85 | 12524 | if (visible || was_visible) |
cd202f69 | 12525 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
a9ff8714 | 12526 | |
31ae71fc ML |
12527 | /* |
12528 | * WaCxSRDisabledForSpriteScaling:ivb | |
12529 | * | |
12530 | * cstate->update_wm was already set above, so this flag will | |
12531 | * take effect when we commit and program watermarks. | |
12532 | */ | |
fd6b8f43 | 12533 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) && |
31ae71fc ML |
12534 | needs_scaling(to_intel_plane_state(plane_state)) && |
12535 | !needs_scaling(old_plane_state)) | |
12536 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 12537 | |
da20eabd ML |
12538 | return 0; |
12539 | } | |
12540 | ||
6d3a1ce7 ML |
12541 | static bool encoders_cloneable(const struct intel_encoder *a, |
12542 | const struct intel_encoder *b) | |
12543 | { | |
12544 | /* masks could be asymmetric, so check both ways */ | |
12545 | return a == b || (a->cloneable & (1 << b->type) && | |
12546 | b->cloneable & (1 << a->type)); | |
12547 | } | |
12548 | ||
12549 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
12550 | struct intel_crtc *crtc, | |
12551 | struct intel_encoder *encoder) | |
12552 | { | |
12553 | struct intel_encoder *source_encoder; | |
12554 | struct drm_connector *connector; | |
12555 | struct drm_connector_state *connector_state; | |
12556 | int i; | |
12557 | ||
12558 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12559 | if (connector_state->crtc != &crtc->base) | |
12560 | continue; | |
12561 | ||
12562 | source_encoder = | |
12563 | to_intel_encoder(connector_state->best_encoder); | |
12564 | if (!encoders_cloneable(encoder, source_encoder)) | |
12565 | return false; | |
12566 | } | |
12567 | ||
12568 | return true; | |
12569 | } | |
12570 | ||
6d3a1ce7 ML |
12571 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
12572 | struct drm_crtc_state *crtc_state) | |
12573 | { | |
cf5a15be | 12574 | struct drm_device *dev = crtc->dev; |
fac5e23e | 12575 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 12576 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
12577 | struct intel_crtc_state *pipe_config = |
12578 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 12579 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 12580 | int ret; |
6d3a1ce7 ML |
12581 | bool mode_changed = needs_modeset(crtc_state); |
12582 | ||
852eb00d | 12583 | if (mode_changed && !crtc_state->active) |
caed361d | 12584 | pipe_config->update_wm_post = true; |
eddfcbcd | 12585 | |
ad421372 ML |
12586 | if (mode_changed && crtc_state->enable && |
12587 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 12588 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
12589 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
12590 | pipe_config); | |
12591 | if (ret) | |
12592 | return ret; | |
12593 | } | |
12594 | ||
82cf435b LL |
12595 | if (crtc_state->color_mgmt_changed) { |
12596 | ret = intel_color_check(crtc, crtc_state); | |
12597 | if (ret) | |
12598 | return ret; | |
e7852a4b LL |
12599 | |
12600 | /* | |
12601 | * Changing color management on Intel hardware is | |
12602 | * handled as part of planes update. | |
12603 | */ | |
12604 | crtc_state->planes_changed = true; | |
82cf435b LL |
12605 | } |
12606 | ||
e435d6e5 | 12607 | ret = 0; |
86c8bbbe | 12608 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 12609 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
12610 | if (ret) { |
12611 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
12612 | return ret; | |
12613 | } | |
12614 | } | |
12615 | ||
12616 | if (dev_priv->display.compute_intermediate_wm && | |
12617 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
12618 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
12619 | return 0; | |
12620 | ||
12621 | /* | |
12622 | * Calculate 'intermediate' watermarks that satisfy both the | |
12623 | * old state and the new state. We can program these | |
12624 | * immediately. | |
12625 | */ | |
12626 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
12627 | intel_crtc, | |
12628 | pipe_config); | |
12629 | if (ret) { | |
12630 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 12631 | return ret; |
ed4a6a7c | 12632 | } |
e3d5457c VS |
12633 | } else if (dev_priv->display.compute_intermediate_wm) { |
12634 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
12635 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
12636 | } |
12637 | ||
e435d6e5 ML |
12638 | if (INTEL_INFO(dev)->gen >= 9) { |
12639 | if (mode_changed) | |
12640 | ret = skl_update_scaler_crtc(pipe_config); | |
12641 | ||
12642 | if (!ret) | |
12643 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12644 | pipe_config); | |
12645 | } | |
12646 | ||
12647 | return ret; | |
6d3a1ce7 ML |
12648 | } |
12649 | ||
65b38e0d | 12650 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 12651 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
5a21b665 DV |
12652 | .atomic_begin = intel_begin_crtc_commit, |
12653 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12654 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12655 | }; |
12656 | ||
d29b2f9d ACO |
12657 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12658 | { | |
12659 | struct intel_connector *connector; | |
12660 | ||
12661 | for_each_intel_connector(dev, connector) { | |
8863dc7f DV |
12662 | if (connector->base.state->crtc) |
12663 | drm_connector_unreference(&connector->base); | |
12664 | ||
d29b2f9d ACO |
12665 | if (connector->base.encoder) { |
12666 | connector->base.state->best_encoder = | |
12667 | connector->base.encoder; | |
12668 | connector->base.state->crtc = | |
12669 | connector->base.encoder->crtc; | |
8863dc7f DV |
12670 | |
12671 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
12672 | } else { |
12673 | connector->base.state->best_encoder = NULL; | |
12674 | connector->base.state->crtc = NULL; | |
12675 | } | |
12676 | } | |
12677 | } | |
12678 | ||
050f7aeb | 12679 | static void |
eba905b2 | 12680 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12681 | struct intel_crtc_state *pipe_config) |
050f7aeb | 12682 | { |
6a2a5c5d | 12683 | const struct drm_display_info *info = &connector->base.display_info; |
050f7aeb DV |
12684 | int bpp = pipe_config->pipe_bpp; |
12685 | ||
12686 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
6a2a5c5d VS |
12687 | connector->base.base.id, |
12688 | connector->base.name); | |
050f7aeb DV |
12689 | |
12690 | /* Don't use an invalid EDID bpc value */ | |
6a2a5c5d | 12691 | if (info->bpc != 0 && info->bpc * 3 < bpp) { |
050f7aeb | 12692 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
6a2a5c5d VS |
12693 | bpp, info->bpc * 3); |
12694 | pipe_config->pipe_bpp = info->bpc * 3; | |
050f7aeb DV |
12695 | } |
12696 | ||
196f954e | 12697 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
6a2a5c5d | 12698 | if (info->bpc == 0 && bpp > 24) { |
196f954e MK |
12699 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
12700 | bpp); | |
12701 | pipe_config->pipe_bpp = 24; | |
050f7aeb DV |
12702 | } |
12703 | } | |
12704 | ||
4e53c2e0 | 12705 | static int |
050f7aeb | 12706 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12707 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12708 | { |
9beb5fea | 12709 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1486017f | 12710 | struct drm_atomic_state *state; |
da3ced29 ACO |
12711 | struct drm_connector *connector; |
12712 | struct drm_connector_state *connector_state; | |
1486017f | 12713 | int bpp, i; |
4e53c2e0 | 12714 | |
9beb5fea TU |
12715 | if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
12716 | IS_CHERRYVIEW(dev_priv))) | |
4e53c2e0 | 12717 | bpp = 10*3; |
9beb5fea | 12718 | else if (INTEL_GEN(dev_priv) >= 5) |
d328c9d7 DV |
12719 | bpp = 12*3; |
12720 | else | |
12721 | bpp = 8*3; | |
12722 | ||
4e53c2e0 | 12723 | |
4e53c2e0 DV |
12724 | pipe_config->pipe_bpp = bpp; |
12725 | ||
1486017f ACO |
12726 | state = pipe_config->base.state; |
12727 | ||
4e53c2e0 | 12728 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12729 | for_each_connector_in_state(state, connector, connector_state, i) { |
12730 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12731 | continue; |
12732 | ||
da3ced29 ACO |
12733 | connected_sink_compute_bpp(to_intel_connector(connector), |
12734 | pipe_config); | |
4e53c2e0 DV |
12735 | } |
12736 | ||
12737 | return bpp; | |
12738 | } | |
12739 | ||
644db711 DV |
12740 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12741 | { | |
12742 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12743 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12744 | mode->crtc_clock, |
644db711 DV |
12745 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12746 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12747 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12748 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12749 | } | |
12750 | ||
c0b03411 | 12751 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12752 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12753 | const char *context) |
12754 | { | |
6a60cd87 | 12755 | struct drm_device *dev = crtc->base.dev; |
4f8036a2 | 12756 | struct drm_i915_private *dev_priv = to_i915(dev); |
6a60cd87 CK |
12757 | struct drm_plane *plane; |
12758 | struct intel_plane *intel_plane; | |
12759 | struct intel_plane_state *state; | |
12760 | struct drm_framebuffer *fb; | |
12761 | ||
78108b7c VS |
12762 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n", |
12763 | crtc->base.base.id, crtc->base.name, | |
6a60cd87 | 12764 | context, pipe_config, pipe_name(crtc->pipe)); |
c0b03411 | 12765 | |
da205630 | 12766 | DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder)); |
c0b03411 DV |
12767 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
12768 | pipe_config->pipe_bpp, pipe_config->dither); | |
12769 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12770 | pipe_config->has_pch_encoder, | |
12771 | pipe_config->fdi_lanes, | |
12772 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12773 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12774 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12775 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
37a5650b | 12776 | intel_crtc_has_dp_encoder(pipe_config), |
90a6b7b0 | 12777 | pipe_config->lane_count, |
eb14cb74 VS |
12778 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12779 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12780 | pipe_config->dp_m_n.tu); | |
b95af8be | 12781 | |
90a6b7b0 | 12782 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
37a5650b | 12783 | intel_crtc_has_dp_encoder(pipe_config), |
90a6b7b0 | 12784 | pipe_config->lane_count, |
b95af8be VK |
12785 | pipe_config->dp_m2_n2.gmch_m, |
12786 | pipe_config->dp_m2_n2.gmch_n, | |
12787 | pipe_config->dp_m2_n2.link_m, | |
12788 | pipe_config->dp_m2_n2.link_n, | |
12789 | pipe_config->dp_m2_n2.tu); | |
12790 | ||
55072d19 DV |
12791 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12792 | pipe_config->has_audio, | |
12793 | pipe_config->has_infoframe); | |
12794 | ||
c0b03411 | 12795 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12796 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12797 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12798 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12799 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12800 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12801 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12802 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12803 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12804 | crtc->num_scalers, | |
12805 | pipe_config->scaler_state.scaler_users, | |
12806 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12807 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12808 | pipe_config->gmch_pfit.control, | |
12809 | pipe_config->gmch_pfit.pgm_ratios, | |
12810 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12811 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12812 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12813 | pipe_config->pch_pfit.size, |
12814 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12815 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12816 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12817 | |
e2d214ae | 12818 | if (IS_BROXTON(dev_priv)) { |
c856052a | 12819 | DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12820 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12821 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 | 12822 | pipe_config->dpll_hw_state.ebb0, |
05712c15 | 12823 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12824 | pipe_config->dpll_hw_state.pll0, |
12825 | pipe_config->dpll_hw_state.pll1, | |
12826 | pipe_config->dpll_hw_state.pll2, | |
12827 | pipe_config->dpll_hw_state.pll3, | |
12828 | pipe_config->dpll_hw_state.pll6, | |
12829 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12830 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12831 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12832 | pipe_config->dpll_hw_state.pcsdw12); |
0853723b | 12833 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
c856052a | 12834 | DRM_DEBUG_KMS("dpll_hw_state: " |
415ff0f6 | 12835 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", |
415ff0f6 TU |
12836 | pipe_config->dpll_hw_state.ctrl1, |
12837 | pipe_config->dpll_hw_state.cfgcr1, | |
12838 | pipe_config->dpll_hw_state.cfgcr2); | |
4f8036a2 | 12839 | } else if (HAS_DDI(dev_priv)) { |
c856052a | 12840 | DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
00490c22 ML |
12841 | pipe_config->dpll_hw_state.wrpll, |
12842 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12843 | } else { |
12844 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12845 | "fp0: 0x%x, fp1: 0x%x\n", | |
12846 | pipe_config->dpll_hw_state.dpll, | |
12847 | pipe_config->dpll_hw_state.dpll_md, | |
12848 | pipe_config->dpll_hw_state.fp0, | |
12849 | pipe_config->dpll_hw_state.fp1); | |
12850 | } | |
12851 | ||
6a60cd87 CK |
12852 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12853 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
d3828147 | 12854 | char *format_name; |
6a60cd87 CK |
12855 | intel_plane = to_intel_plane(plane); |
12856 | if (intel_plane->pipe != crtc->pipe) | |
12857 | continue; | |
12858 | ||
12859 | state = to_intel_plane_state(plane->state); | |
12860 | fb = state->base.fb; | |
12861 | if (!fb) { | |
1d577e02 VS |
12862 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
12863 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
12864 | continue; |
12865 | } | |
12866 | ||
90844f00 EE |
12867 | format_name = drm_get_format_name(fb->pixel_format); |
12868 | ||
1d577e02 VS |
12869 | DRM_DEBUG_KMS("[PLANE:%d:%s] enabled", |
12870 | plane->base.id, plane->name); | |
12871 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s", | |
90844f00 | 12872 | fb->base.id, fb->width, fb->height, format_name); |
1d577e02 VS |
12873 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", |
12874 | state->scaler_id, | |
936e71e3 VS |
12875 | state->base.src.x1 >> 16, |
12876 | state->base.src.y1 >> 16, | |
12877 | drm_rect_width(&state->base.src) >> 16, | |
12878 | drm_rect_height(&state->base.src) >> 16, | |
12879 | state->base.dst.x1, state->base.dst.y1, | |
12880 | drm_rect_width(&state->base.dst), | |
12881 | drm_rect_height(&state->base.dst)); | |
90844f00 EE |
12882 | |
12883 | kfree(format_name); | |
6a60cd87 | 12884 | } |
c0b03411 DV |
12885 | } |
12886 | ||
5448a00d | 12887 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12888 | { |
5448a00d | 12889 | struct drm_device *dev = state->dev; |
da3ced29 | 12890 | struct drm_connector *connector; |
00f0b378 | 12891 | unsigned int used_ports = 0; |
477321e0 | 12892 | unsigned int used_mst_ports = 0; |
00f0b378 VS |
12893 | |
12894 | /* | |
12895 | * Walk the connector list instead of the encoder | |
12896 | * list to detect the problem on ddi platforms | |
12897 | * where there's just one encoder per digital port. | |
12898 | */ | |
0bff4858 VS |
12899 | drm_for_each_connector(connector, dev) { |
12900 | struct drm_connector_state *connector_state; | |
12901 | struct intel_encoder *encoder; | |
12902 | ||
12903 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12904 | if (!connector_state) | |
12905 | connector_state = connector->state; | |
12906 | ||
5448a00d | 12907 | if (!connector_state->best_encoder) |
00f0b378 VS |
12908 | continue; |
12909 | ||
5448a00d ACO |
12910 | encoder = to_intel_encoder(connector_state->best_encoder); |
12911 | ||
12912 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12913 | |
12914 | switch (encoder->type) { | |
12915 | unsigned int port_mask; | |
12916 | case INTEL_OUTPUT_UNKNOWN: | |
4f8036a2 | 12917 | if (WARN_ON(!HAS_DDI(to_i915(dev)))) |
00f0b378 | 12918 | break; |
cca0502b | 12919 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
12920 | case INTEL_OUTPUT_HDMI: |
12921 | case INTEL_OUTPUT_EDP: | |
12922 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12923 | ||
12924 | /* the same port mustn't appear more than once */ | |
12925 | if (used_ports & port_mask) | |
12926 | return false; | |
12927 | ||
12928 | used_ports |= port_mask; | |
477321e0 VS |
12929 | break; |
12930 | case INTEL_OUTPUT_DP_MST: | |
12931 | used_mst_ports |= | |
12932 | 1 << enc_to_mst(&encoder->base)->primary->port; | |
12933 | break; | |
00f0b378 VS |
12934 | default: |
12935 | break; | |
12936 | } | |
12937 | } | |
12938 | ||
477321e0 VS |
12939 | /* can't mix MST and SST/HDMI on the same port */ |
12940 | if (used_ports & used_mst_ports) | |
12941 | return false; | |
12942 | ||
00f0b378 VS |
12943 | return true; |
12944 | } | |
12945 | ||
83a57153 ACO |
12946 | static void |
12947 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12948 | { | |
12949 | struct drm_crtc_state tmp_state; | |
663a3640 | 12950 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 12951 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 12952 | struct intel_shared_dpll *shared_dpll; |
c4e2d043 | 12953 | bool force_thru; |
83a57153 | 12954 | |
7546a384 ACO |
12955 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12956 | * kzalloc'd. Code that depends on any field being zero should be | |
12957 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12958 | * only fields that are know to not cause problems are preserved. */ | |
12959 | ||
83a57153 | 12960 | tmp_state = crtc_state->base; |
663a3640 | 12961 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12962 | shared_dpll = crtc_state->shared_dpll; |
12963 | dpll_hw_state = crtc_state->dpll_hw_state; | |
c4e2d043 | 12964 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12965 | |
83a57153 | 12966 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12967 | |
83a57153 | 12968 | crtc_state->base = tmp_state; |
663a3640 | 12969 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12970 | crtc_state->shared_dpll = shared_dpll; |
12971 | crtc_state->dpll_hw_state = dpll_hw_state; | |
c4e2d043 | 12972 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12973 | } |
12974 | ||
548ee15b | 12975 | static int |
b8cecdf5 | 12976 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12977 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12978 | { |
b359283a | 12979 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12980 | struct intel_encoder *encoder; |
da3ced29 | 12981 | struct drm_connector *connector; |
0b901879 | 12982 | struct drm_connector_state *connector_state; |
d328c9d7 | 12983 | int base_bpp, ret = -EINVAL; |
0b901879 | 12984 | int i; |
e29c22c0 | 12985 | bool retry = true; |
ee7b9f93 | 12986 | |
83a57153 | 12987 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12988 | |
e143a21c DV |
12989 | pipe_config->cpu_transcoder = |
12990 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12991 | |
2960bc9c ID |
12992 | /* |
12993 | * Sanitize sync polarity flags based on requested ones. If neither | |
12994 | * positive or negative polarity is requested, treat this as meaning | |
12995 | * negative polarity. | |
12996 | */ | |
2d112de7 | 12997 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12998 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12999 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 13000 | |
2d112de7 | 13001 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 13002 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 13003 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 13004 | |
d328c9d7 DV |
13005 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
13006 | pipe_config); | |
13007 | if (base_bpp < 0) | |
4e53c2e0 DV |
13008 | goto fail; |
13009 | ||
e41a56be VS |
13010 | /* |
13011 | * Determine the real pipe dimensions. Note that stereo modes can | |
13012 | * increase the actual pipe size due to the frame doubling and | |
13013 | * insertion of additional space for blanks between the frame. This | |
13014 | * is stored in the crtc timings. We use the requested mode to do this | |
13015 | * computation to clearly distinguish it from the adjusted mode, which | |
13016 | * can be changed by the connectors in the below retry loop. | |
13017 | */ | |
2d112de7 | 13018 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
13019 | &pipe_config->pipe_src_w, |
13020 | &pipe_config->pipe_src_h); | |
e41a56be | 13021 | |
253c84c8 VS |
13022 | for_each_connector_in_state(state, connector, connector_state, i) { |
13023 | if (connector_state->crtc != crtc) | |
13024 | continue; | |
13025 | ||
13026 | encoder = to_intel_encoder(connector_state->best_encoder); | |
13027 | ||
e25148d0 VS |
13028 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
13029 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
13030 | goto fail; | |
13031 | } | |
13032 | ||
253c84c8 VS |
13033 | /* |
13034 | * Determine output_types before calling the .compute_config() | |
13035 | * hooks so that the hooks can use this information safely. | |
13036 | */ | |
13037 | pipe_config->output_types |= 1 << encoder->type; | |
13038 | } | |
13039 | ||
e29c22c0 | 13040 | encoder_retry: |
ef1b460d | 13041 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 13042 | pipe_config->port_clock = 0; |
ef1b460d | 13043 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 13044 | |
135c81b8 | 13045 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
13046 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
13047 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 13048 | |
7758a113 DV |
13049 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
13050 | * adjust it according to limitations or connector properties, and also | |
13051 | * a chance to reject the mode entirely. | |
47f1c6c9 | 13052 | */ |
da3ced29 | 13053 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 13054 | if (connector_state->crtc != crtc) |
7758a113 | 13055 | continue; |
7ae89233 | 13056 | |
0b901879 ACO |
13057 | encoder = to_intel_encoder(connector_state->best_encoder); |
13058 | ||
0a478c27 | 13059 | if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { |
efea6e8e | 13060 | DRM_DEBUG_KMS("Encoder config failure\n"); |
7758a113 DV |
13061 | goto fail; |
13062 | } | |
ee7b9f93 | 13063 | } |
47f1c6c9 | 13064 | |
ff9a6750 DV |
13065 | /* Set default port clock if not overwritten by the encoder. Needs to be |
13066 | * done afterwards in case the encoder adjusts the mode. */ | |
13067 | if (!pipe_config->port_clock) | |
2d112de7 | 13068 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 13069 | * pipe_config->pixel_multiplier; |
ff9a6750 | 13070 | |
a43f6e0f | 13071 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 13072 | if (ret < 0) { |
7758a113 DV |
13073 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
13074 | goto fail; | |
ee7b9f93 | 13075 | } |
e29c22c0 DV |
13076 | |
13077 | if (ret == RETRY) { | |
13078 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
13079 | ret = -EINVAL; | |
13080 | goto fail; | |
13081 | } | |
13082 | ||
13083 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
13084 | retry = false; | |
13085 | goto encoder_retry; | |
13086 | } | |
13087 | ||
e8fa4270 DV |
13088 | /* Dithering seems to not pass-through bits correctly when it should, so |
13089 | * only enable it on 6bpc panels. */ | |
13090 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 13091 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 13092 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 13093 | |
7758a113 | 13094 | fail: |
548ee15b | 13095 | return ret; |
ee7b9f93 | 13096 | } |
47f1c6c9 | 13097 | |
ea9d758d | 13098 | static void |
4740b0f2 | 13099 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 13100 | { |
0a9ab303 ACO |
13101 | struct drm_crtc *crtc; |
13102 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 13103 | int i; |
ea9d758d | 13104 | |
7668851f | 13105 | /* Double check state. */ |
8a75d157 | 13106 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 13107 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
13108 | |
13109 | /* Update hwmode for vblank functions */ | |
13110 | if (crtc->state->active) | |
13111 | crtc->hwmode = crtc->state->adjusted_mode; | |
13112 | else | |
13113 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
13114 | |
13115 | /* | |
13116 | * Update legacy state to satisfy fbc code. This can | |
13117 | * be removed when fbc uses the atomic state. | |
13118 | */ | |
13119 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
13120 | struct drm_plane_state *plane_state = crtc->primary->state; | |
13121 | ||
13122 | crtc->primary->fb = plane_state->fb; | |
13123 | crtc->x = plane_state->src_x >> 16; | |
13124 | crtc->y = plane_state->src_y >> 16; | |
13125 | } | |
ea9d758d | 13126 | } |
ea9d758d DV |
13127 | } |
13128 | ||
3bd26263 | 13129 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 13130 | { |
3bd26263 | 13131 | int diff; |
f1f644dc JB |
13132 | |
13133 | if (clock1 == clock2) | |
13134 | return true; | |
13135 | ||
13136 | if (!clock1 || !clock2) | |
13137 | return false; | |
13138 | ||
13139 | diff = abs(clock1 - clock2); | |
13140 | ||
13141 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
13142 | return true; | |
13143 | ||
13144 | return false; | |
13145 | } | |
13146 | ||
cfb23ed6 ML |
13147 | static bool |
13148 | intel_compare_m_n(unsigned int m, unsigned int n, | |
13149 | unsigned int m2, unsigned int n2, | |
13150 | bool exact) | |
13151 | { | |
13152 | if (m == m2 && n == n2) | |
13153 | return true; | |
13154 | ||
13155 | if (exact || !m || !n || !m2 || !n2) | |
13156 | return false; | |
13157 | ||
13158 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
13159 | ||
31d10b57 ML |
13160 | if (n > n2) { |
13161 | while (n > n2) { | |
cfb23ed6 ML |
13162 | m2 <<= 1; |
13163 | n2 <<= 1; | |
13164 | } | |
31d10b57 ML |
13165 | } else if (n < n2) { |
13166 | while (n < n2) { | |
cfb23ed6 ML |
13167 | m <<= 1; |
13168 | n <<= 1; | |
13169 | } | |
13170 | } | |
13171 | ||
31d10b57 ML |
13172 | if (n != n2) |
13173 | return false; | |
13174 | ||
13175 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
13176 | } |
13177 | ||
13178 | static bool | |
13179 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
13180 | struct intel_link_m_n *m2_n2, | |
13181 | bool adjust) | |
13182 | { | |
13183 | if (m_n->tu == m2_n2->tu && | |
13184 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
13185 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
13186 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
13187 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
13188 | if (adjust) | |
13189 | *m2_n2 = *m_n; | |
13190 | ||
13191 | return true; | |
13192 | } | |
13193 | ||
13194 | return false; | |
13195 | } | |
13196 | ||
0e8ffe1b | 13197 | static bool |
2fa2fe9a | 13198 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 13199 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
13200 | struct intel_crtc_state *pipe_config, |
13201 | bool adjust) | |
0e8ffe1b | 13202 | { |
772c2a51 | 13203 | struct drm_i915_private *dev_priv = to_i915(dev); |
cfb23ed6 ML |
13204 | bool ret = true; |
13205 | ||
13206 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
13207 | do { \ | |
13208 | if (!adjust) \ | |
13209 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
13210 | else \ | |
13211 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
13212 | } while (0) | |
13213 | ||
66e985c0 DV |
13214 | #define PIPE_CONF_CHECK_X(name) \ |
13215 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 13216 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
13217 | "(expected 0x%08x, found 0x%08x)\n", \ |
13218 | current_config->name, \ | |
13219 | pipe_config->name); \ | |
cfb23ed6 | 13220 | ret = false; \ |
66e985c0 DV |
13221 | } |
13222 | ||
08a24034 DV |
13223 | #define PIPE_CONF_CHECK_I(name) \ |
13224 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 13225 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
13226 | "(expected %i, found %i)\n", \ |
13227 | current_config->name, \ | |
13228 | pipe_config->name); \ | |
cfb23ed6 ML |
13229 | ret = false; \ |
13230 | } | |
13231 | ||
8106ddbd ACO |
13232 | #define PIPE_CONF_CHECK_P(name) \ |
13233 | if (current_config->name != pipe_config->name) { \ | |
13234 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
13235 | "(expected %p, found %p)\n", \ | |
13236 | current_config->name, \ | |
13237 | pipe_config->name); \ | |
13238 | ret = false; \ | |
13239 | } | |
13240 | ||
cfb23ed6 ML |
13241 | #define PIPE_CONF_CHECK_M_N(name) \ |
13242 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
13243 | &pipe_config->name,\ | |
13244 | adjust)) { \ | |
13245 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
13246 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
13247 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
13248 | current_config->name.tu, \ | |
13249 | current_config->name.gmch_m, \ | |
13250 | current_config->name.gmch_n, \ | |
13251 | current_config->name.link_m, \ | |
13252 | current_config->name.link_n, \ | |
13253 | pipe_config->name.tu, \ | |
13254 | pipe_config->name.gmch_m, \ | |
13255 | pipe_config->name.gmch_n, \ | |
13256 | pipe_config->name.link_m, \ | |
13257 | pipe_config->name.link_n); \ | |
13258 | ret = false; \ | |
13259 | } | |
13260 | ||
55c561a7 DV |
13261 | /* This is required for BDW+ where there is only one set of registers for |
13262 | * switching between high and low RR. | |
13263 | * This macro can be used whenever a comparison has to be made between one | |
13264 | * hw state and multiple sw state variables. | |
13265 | */ | |
cfb23ed6 ML |
13266 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
13267 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
13268 | &pipe_config->name, adjust) && \ | |
13269 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
13270 | &pipe_config->name, adjust)) { \ | |
13271 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
13272 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
13273 | "or tu %i gmch %i/%i link %i/%i, " \ | |
13274 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
13275 | current_config->name.tu, \ | |
13276 | current_config->name.gmch_m, \ | |
13277 | current_config->name.gmch_n, \ | |
13278 | current_config->name.link_m, \ | |
13279 | current_config->name.link_n, \ | |
13280 | current_config->alt_name.tu, \ | |
13281 | current_config->alt_name.gmch_m, \ | |
13282 | current_config->alt_name.gmch_n, \ | |
13283 | current_config->alt_name.link_m, \ | |
13284 | current_config->alt_name.link_n, \ | |
13285 | pipe_config->name.tu, \ | |
13286 | pipe_config->name.gmch_m, \ | |
13287 | pipe_config->name.gmch_n, \ | |
13288 | pipe_config->name.link_m, \ | |
13289 | pipe_config->name.link_n); \ | |
13290 | ret = false; \ | |
88adfff1 DV |
13291 | } |
13292 | ||
1bd1bd80 DV |
13293 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
13294 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 13295 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
13296 | "(expected %i, found %i)\n", \ |
13297 | current_config->name & (mask), \ | |
13298 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 13299 | ret = false; \ |
1bd1bd80 DV |
13300 | } |
13301 | ||
5e550656 VS |
13302 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
13303 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 13304 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
13305 | "(expected %i, found %i)\n", \ |
13306 | current_config->name, \ | |
13307 | pipe_config->name); \ | |
cfb23ed6 | 13308 | ret = false; \ |
5e550656 VS |
13309 | } |
13310 | ||
bb760063 DV |
13311 | #define PIPE_CONF_QUIRK(quirk) \ |
13312 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
13313 | ||
eccb140b DV |
13314 | PIPE_CONF_CHECK_I(cpu_transcoder); |
13315 | ||
08a24034 DV |
13316 | PIPE_CONF_CHECK_I(has_pch_encoder); |
13317 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 13318 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 13319 | |
90a6b7b0 | 13320 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 13321 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be VK |
13322 | |
13323 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
13324 | PIPE_CONF_CHECK_M_N(dp_m_n); |
13325 | ||
cfb23ed6 ML |
13326 | if (current_config->has_drrs) |
13327 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
13328 | } else | |
13329 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 13330 | |
253c84c8 | 13331 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 13332 | |
2d112de7 ACO |
13333 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
13334 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
13335 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
13336 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
13337 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
13338 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 13339 | |
2d112de7 ACO |
13340 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
13341 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
13342 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
13343 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
13344 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
13345 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 13346 | |
c93f54cf | 13347 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 13348 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
772c2a51 | 13349 | if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || |
920a14b2 | 13350 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
b5a9fa09 | 13351 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 13352 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 13353 | |
9ed109a7 DV |
13354 | PIPE_CONF_CHECK_I(has_audio); |
13355 | ||
2d112de7 | 13356 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
13357 | DRM_MODE_FLAG_INTERLACE); |
13358 | ||
bb760063 | 13359 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 13360 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13361 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 13362 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13363 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 13364 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 13365 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 13366 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
13367 | DRM_MODE_FLAG_NVSYNC); |
13368 | } | |
045ac3b5 | 13369 | |
333b8ca8 | 13370 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
13371 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
13372 | if (INTEL_INFO(dev)->gen < 4) | |
7f7d8dd6 | 13373 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 13374 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 13375 | |
bfd16b2a ML |
13376 | if (!adjust) { |
13377 | PIPE_CONF_CHECK_I(pipe_src_w); | |
13378 | PIPE_CONF_CHECK_I(pipe_src_h); | |
13379 | ||
13380 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
13381 | if (current_config->pch_pfit.enabled) { | |
13382 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
13383 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
13384 | } | |
2fa2fe9a | 13385 | |
7aefe2b5 ML |
13386 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
13387 | } | |
a1b2278e | 13388 | |
e59150dc | 13389 | /* BDW+ don't expose a synchronous way to read the state */ |
772c2a51 | 13390 | if (IS_HASWELL(dev_priv)) |
e59150dc | 13391 | PIPE_CONF_CHECK_I(ips_enabled); |
42db64ef | 13392 | |
282740f7 VS |
13393 | PIPE_CONF_CHECK_I(double_wide); |
13394 | ||
8106ddbd | 13395 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 13396 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 13397 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
13398 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
13399 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 13400 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 13401 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
13402 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
13403 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
13404 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 13405 | |
47eacbab VS |
13406 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
13407 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
13408 | ||
9beb5fea | 13409 | if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) |
42571aef VS |
13410 | PIPE_CONF_CHECK_I(pipe_bpp); |
13411 | ||
2d112de7 | 13412 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 13413 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 13414 | |
66e985c0 | 13415 | #undef PIPE_CONF_CHECK_X |
08a24034 | 13416 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 13417 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 13418 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 13419 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 13420 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 13421 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 13422 | |
cfb23ed6 | 13423 | return ret; |
0e8ffe1b DV |
13424 | } |
13425 | ||
e3b247da VS |
13426 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
13427 | const struct intel_crtc_state *pipe_config) | |
13428 | { | |
13429 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 13430 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
13431 | &pipe_config->fdi_m_n); |
13432 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
13433 | ||
13434 | /* | |
13435 | * FDI already provided one idea for the dotclock. | |
13436 | * Yell if the encoder disagrees. | |
13437 | */ | |
13438 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
13439 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
13440 | fdi_dotclock, dotclock); | |
13441 | } | |
13442 | } | |
13443 | ||
c0ead703 ML |
13444 | static void verify_wm_state(struct drm_crtc *crtc, |
13445 | struct drm_crtc_state *new_state) | |
08db6652 | 13446 | { |
e7c84544 | 13447 | struct drm_device *dev = crtc->dev; |
fac5e23e | 13448 | struct drm_i915_private *dev_priv = to_i915(dev); |
08db6652 | 13449 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
3de8a14c | 13450 | struct skl_pipe_wm hw_wm, *sw_wm; |
13451 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; | |
13452 | struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; | |
e7c84544 ML |
13453 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13454 | const enum pipe pipe = intel_crtc->pipe; | |
3de8a14c | 13455 | int plane, level, max_level = ilk_wm_max_level(dev_priv); |
08db6652 | 13456 | |
e7c84544 | 13457 | if (INTEL_INFO(dev)->gen < 9 || !new_state->active) |
08db6652 DL |
13458 | return; |
13459 | ||
3de8a14c | 13460 | skl_pipe_wm_get_hw_state(crtc, &hw_wm); |
03af79e0 | 13461 | sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal; |
3de8a14c | 13462 | |
08db6652 DL |
13463 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); |
13464 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
13465 | ||
e7c84544 | 13466 | /* planes */ |
8b364b41 | 13467 | for_each_universal_plane(dev_priv, pipe, plane) { |
3de8a14c | 13468 | hw_plane_wm = &hw_wm.planes[plane]; |
13469 | sw_plane_wm = &sw_wm->planes[plane]; | |
08db6652 | 13470 | |
3de8a14c | 13471 | /* Watermarks */ |
13472 | for (level = 0; level <= max_level; level++) { | |
13473 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
13474 | &sw_plane_wm->wm[level])) | |
13475 | continue; | |
13476 | ||
13477 | DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
13478 | pipe_name(pipe), plane + 1, level, | |
13479 | sw_plane_wm->wm[level].plane_en, | |
13480 | sw_plane_wm->wm[level].plane_res_b, | |
13481 | sw_plane_wm->wm[level].plane_res_l, | |
13482 | hw_plane_wm->wm[level].plane_en, | |
13483 | hw_plane_wm->wm[level].plane_res_b, | |
13484 | hw_plane_wm->wm[level].plane_res_l); | |
13485 | } | |
08db6652 | 13486 | |
3de8a14c | 13487 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, |
13488 | &sw_plane_wm->trans_wm)) { | |
13489 | DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
13490 | pipe_name(pipe), plane + 1, | |
13491 | sw_plane_wm->trans_wm.plane_en, | |
13492 | sw_plane_wm->trans_wm.plane_res_b, | |
13493 | sw_plane_wm->trans_wm.plane_res_l, | |
13494 | hw_plane_wm->trans_wm.plane_en, | |
13495 | hw_plane_wm->trans_wm.plane_res_b, | |
13496 | hw_plane_wm->trans_wm.plane_res_l); | |
13497 | } | |
13498 | ||
13499 | /* DDB */ | |
13500 | hw_ddb_entry = &hw_ddb.plane[pipe][plane]; | |
13501 | sw_ddb_entry = &sw_ddb->plane[pipe][plane]; | |
13502 | ||
13503 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { | |
faccd994 | 13504 | DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", |
3de8a14c | 13505 | pipe_name(pipe), plane + 1, |
13506 | sw_ddb_entry->start, sw_ddb_entry->end, | |
13507 | hw_ddb_entry->start, hw_ddb_entry->end); | |
13508 | } | |
e7c84544 | 13509 | } |
08db6652 | 13510 | |
27082493 L |
13511 | /* |
13512 | * cursor | |
13513 | * If the cursor plane isn't active, we may not have updated it's ddb | |
13514 | * allocation. In that case since the ddb allocation will be updated | |
13515 | * once the plane becomes visible, we can skip this check | |
13516 | */ | |
13517 | if (intel_crtc->cursor_addr) { | |
3de8a14c | 13518 | hw_plane_wm = &hw_wm.planes[PLANE_CURSOR]; |
13519 | sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; | |
13520 | ||
13521 | /* Watermarks */ | |
13522 | for (level = 0; level <= max_level; level++) { | |
13523 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
13524 | &sw_plane_wm->wm[level])) | |
13525 | continue; | |
13526 | ||
13527 | DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
13528 | pipe_name(pipe), level, | |
13529 | sw_plane_wm->wm[level].plane_en, | |
13530 | sw_plane_wm->wm[level].plane_res_b, | |
13531 | sw_plane_wm->wm[level].plane_res_l, | |
13532 | hw_plane_wm->wm[level].plane_en, | |
13533 | hw_plane_wm->wm[level].plane_res_b, | |
13534 | hw_plane_wm->wm[level].plane_res_l); | |
13535 | } | |
13536 | ||
13537 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, | |
13538 | &sw_plane_wm->trans_wm)) { | |
13539 | DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
13540 | pipe_name(pipe), | |
13541 | sw_plane_wm->trans_wm.plane_en, | |
13542 | sw_plane_wm->trans_wm.plane_res_b, | |
13543 | sw_plane_wm->trans_wm.plane_res_l, | |
13544 | hw_plane_wm->trans_wm.plane_en, | |
13545 | hw_plane_wm->trans_wm.plane_res_b, | |
13546 | hw_plane_wm->trans_wm.plane_res_l); | |
13547 | } | |
13548 | ||
13549 | /* DDB */ | |
13550 | hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
13551 | sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
27082493 | 13552 | |
3de8a14c | 13553 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { |
faccd994 | 13554 | DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", |
27082493 | 13555 | pipe_name(pipe), |
3de8a14c | 13556 | sw_ddb_entry->start, sw_ddb_entry->end, |
13557 | hw_ddb_entry->start, hw_ddb_entry->end); | |
27082493 | 13558 | } |
08db6652 DL |
13559 | } |
13560 | } | |
13561 | ||
91d1b4bd | 13562 | static void |
c0ead703 | 13563 | verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc) |
8af6cf88 | 13564 | { |
35dd3c64 | 13565 | struct drm_connector *connector; |
8af6cf88 | 13566 | |
e7c84544 | 13567 | drm_for_each_connector(connector, dev) { |
35dd3c64 ML |
13568 | struct drm_encoder *encoder = connector->encoder; |
13569 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 13570 | |
e7c84544 ML |
13571 | if (state->crtc != crtc) |
13572 | continue; | |
13573 | ||
5a21b665 | 13574 | intel_connector_verify_state(to_intel_connector(connector)); |
8af6cf88 | 13575 | |
ad3c558f | 13576 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 13577 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 13578 | } |
91d1b4bd DV |
13579 | } |
13580 | ||
13581 | static void | |
c0ead703 | 13582 | verify_encoder_state(struct drm_device *dev) |
91d1b4bd DV |
13583 | { |
13584 | struct intel_encoder *encoder; | |
13585 | struct intel_connector *connector; | |
8af6cf88 | 13586 | |
b2784e15 | 13587 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 13588 | bool enabled = false; |
4d20cd86 | 13589 | enum pipe pipe; |
8af6cf88 DV |
13590 | |
13591 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
13592 | encoder->base.base.id, | |
8e329a03 | 13593 | encoder->base.name); |
8af6cf88 | 13594 | |
3a3371ff | 13595 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 13596 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
13597 | continue; |
13598 | enabled = true; | |
ad3c558f ML |
13599 | |
13600 | I915_STATE_WARN(connector->base.state->crtc != | |
13601 | encoder->base.crtc, | |
13602 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 13603 | } |
0e32b39c | 13604 | |
e2c719b7 | 13605 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
13606 | "encoder's enabled state mismatch " |
13607 | "(expected %i, found %i)\n", | |
13608 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
13609 | |
13610 | if (!encoder->base.crtc) { | |
4d20cd86 | 13611 | bool active; |
7c60d198 | 13612 | |
4d20cd86 ML |
13613 | active = encoder->get_hw_state(encoder, &pipe); |
13614 | I915_STATE_WARN(active, | |
13615 | "encoder detached but still enabled on pipe %c.\n", | |
13616 | pipe_name(pipe)); | |
7c60d198 | 13617 | } |
8af6cf88 | 13618 | } |
91d1b4bd DV |
13619 | } |
13620 | ||
13621 | static void | |
c0ead703 ML |
13622 | verify_crtc_state(struct drm_crtc *crtc, |
13623 | struct drm_crtc_state *old_crtc_state, | |
13624 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 13625 | { |
e7c84544 | 13626 | struct drm_device *dev = crtc->dev; |
fac5e23e | 13627 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 13628 | struct intel_encoder *encoder; |
e7c84544 ML |
13629 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13630 | struct intel_crtc_state *pipe_config, *sw_config; | |
13631 | struct drm_atomic_state *old_state; | |
13632 | bool active; | |
045ac3b5 | 13633 | |
e7c84544 | 13634 | old_state = old_crtc_state->state; |
ec2dc6a0 | 13635 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
13636 | pipe_config = to_intel_crtc_state(old_crtc_state); |
13637 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
13638 | pipe_config->base.crtc = crtc; | |
13639 | pipe_config->base.state = old_state; | |
8af6cf88 | 13640 | |
78108b7c | 13641 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 13642 | |
e7c84544 | 13643 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 13644 | |
e7c84544 ML |
13645 | /* hw state is inconsistent with the pipe quirk */ |
13646 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
13647 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
13648 | active = new_crtc_state->active; | |
6c49f241 | 13649 | |
e7c84544 ML |
13650 | I915_STATE_WARN(new_crtc_state->active != active, |
13651 | "crtc active state doesn't match with hw state " | |
13652 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 13653 | |
e7c84544 ML |
13654 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
13655 | "transitional active state does not match atomic hw state " | |
13656 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 13657 | |
e7c84544 ML |
13658 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
13659 | enum pipe pipe; | |
4d20cd86 | 13660 | |
e7c84544 ML |
13661 | active = encoder->get_hw_state(encoder, &pipe); |
13662 | I915_STATE_WARN(active != new_crtc_state->active, | |
13663 | "[ENCODER:%i] active %i with crtc active %i\n", | |
13664 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 13665 | |
e7c84544 ML |
13666 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
13667 | "Encoder connected to wrong pipe %c\n", | |
13668 | pipe_name(pipe)); | |
4d20cd86 | 13669 | |
253c84c8 VS |
13670 | if (active) { |
13671 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 13672 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 13673 | } |
e7c84544 | 13674 | } |
53d9f4e9 | 13675 | |
e7c84544 ML |
13676 | if (!new_crtc_state->active) |
13677 | return; | |
cfb23ed6 | 13678 | |
e7c84544 | 13679 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 13680 | |
e7c84544 ML |
13681 | sw_config = to_intel_crtc_state(crtc->state); |
13682 | if (!intel_pipe_config_compare(dev, sw_config, | |
13683 | pipe_config, false)) { | |
13684 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
13685 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
13686 | "[hw state]"); | |
13687 | intel_dump_pipe_config(intel_crtc, sw_config, | |
13688 | "[sw state]"); | |
8af6cf88 DV |
13689 | } |
13690 | } | |
13691 | ||
91d1b4bd | 13692 | static void |
c0ead703 ML |
13693 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
13694 | struct intel_shared_dpll *pll, | |
13695 | struct drm_crtc *crtc, | |
13696 | struct drm_crtc_state *new_state) | |
91d1b4bd | 13697 | { |
91d1b4bd | 13698 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
13699 | unsigned crtc_mask; |
13700 | bool active; | |
5358901f | 13701 | |
e7c84544 | 13702 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 13703 | |
e7c84544 | 13704 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 13705 | |
e7c84544 | 13706 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 13707 | |
e7c84544 ML |
13708 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
13709 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
13710 | "pll in active use but not on in sw tracking\n"); | |
13711 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
13712 | "pll is on but not used by any active crtc\n"); | |
13713 | I915_STATE_WARN(pll->on != active, | |
13714 | "pll on state mismatch (expected %i, found %i)\n", | |
13715 | pll->on, active); | |
13716 | } | |
5358901f | 13717 | |
e7c84544 | 13718 | if (!crtc) { |
2dd66ebd | 13719 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, |
e7c84544 ML |
13720 | "more active pll users than references: %x vs %x\n", |
13721 | pll->active_mask, pll->config.crtc_mask); | |
5358901f | 13722 | |
e7c84544 ML |
13723 | return; |
13724 | } | |
13725 | ||
13726 | crtc_mask = 1 << drm_crtc_index(crtc); | |
13727 | ||
13728 | if (new_state->active) | |
13729 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
13730 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
13731 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
13732 | else | |
13733 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13734 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
13735 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 13736 | |
e7c84544 ML |
13737 | I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask), |
13738 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", | |
13739 | crtc_mask, pll->config.crtc_mask); | |
66e985c0 | 13740 | |
e7c84544 ML |
13741 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, |
13742 | &dpll_hw_state, | |
13743 | sizeof(dpll_hw_state)), | |
13744 | "pll hw state mismatch\n"); | |
13745 | } | |
13746 | ||
13747 | static void | |
c0ead703 ML |
13748 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
13749 | struct drm_crtc_state *old_crtc_state, | |
13750 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 13751 | { |
fac5e23e | 13752 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13753 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
13754 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
13755 | ||
13756 | if (new_state->shared_dpll) | |
c0ead703 | 13757 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
13758 | |
13759 | if (old_state->shared_dpll && | |
13760 | old_state->shared_dpll != new_state->shared_dpll) { | |
13761 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
13762 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
13763 | ||
13764 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
13765 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
13766 | pipe_name(drm_crtc_index(crtc))); | |
13767 | I915_STATE_WARN(pll->config.crtc_mask & crtc_mask, | |
13768 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", | |
13769 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 13770 | } |
8af6cf88 DV |
13771 | } |
13772 | ||
e7c84544 | 13773 | static void |
c0ead703 | 13774 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
e7c84544 ML |
13775 | struct drm_crtc_state *old_state, |
13776 | struct drm_crtc_state *new_state) | |
13777 | { | |
5a21b665 DV |
13778 | if (!needs_modeset(new_state) && |
13779 | !to_intel_crtc_state(new_state)->update_pipe) | |
13780 | return; | |
13781 | ||
c0ead703 | 13782 | verify_wm_state(crtc, new_state); |
5a21b665 | 13783 | verify_connector_state(crtc->dev, crtc); |
c0ead703 ML |
13784 | verify_crtc_state(crtc, old_state, new_state); |
13785 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
13786 | } |
13787 | ||
13788 | static void | |
c0ead703 | 13789 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 13790 | { |
fac5e23e | 13791 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
13792 | int i; |
13793 | ||
13794 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 13795 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
13796 | } |
13797 | ||
13798 | static void | |
c0ead703 | 13799 | intel_modeset_verify_disabled(struct drm_device *dev) |
e7c84544 | 13800 | { |
c0ead703 ML |
13801 | verify_encoder_state(dev); |
13802 | verify_connector_state(dev, NULL); | |
13803 | verify_disabled_dpll_state(dev); | |
e7c84544 ML |
13804 | } |
13805 | ||
80715b2f VS |
13806 | static void update_scanline_offset(struct intel_crtc *crtc) |
13807 | { | |
4f8036a2 | 13808 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
80715b2f VS |
13809 | |
13810 | /* | |
13811 | * The scanline counter increments at the leading edge of hsync. | |
13812 | * | |
13813 | * On most platforms it starts counting from vtotal-1 on the | |
13814 | * first active line. That means the scanline counter value is | |
13815 | * always one less than what we would expect. Ie. just after | |
13816 | * start of vblank, which also occurs at start of hsync (on the | |
13817 | * last active line), the scanline counter will read vblank_start-1. | |
13818 | * | |
13819 | * On gen2 the scanline counter starts counting from 1 instead | |
13820 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13821 | * to keep the value positive), instead of adding one. | |
13822 | * | |
13823 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13824 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13825 | * there's an extra 1 line difference. So we need to add two instead of | |
13826 | * one to the value. | |
13827 | */ | |
4f8036a2 | 13828 | if (IS_GEN2(dev_priv)) { |
124abe07 | 13829 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13830 | int vtotal; |
13831 | ||
124abe07 VS |
13832 | vtotal = adjusted_mode->crtc_vtotal; |
13833 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13834 | vtotal /= 2; |
13835 | ||
13836 | crtc->scanline_offset = vtotal - 1; | |
4f8036a2 | 13837 | } else if (HAS_DDI(dev_priv) && |
2d84d2b3 | 13838 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13839 | crtc->scanline_offset = 2; |
13840 | } else | |
13841 | crtc->scanline_offset = 1; | |
13842 | } | |
13843 | ||
ad421372 | 13844 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13845 | { |
225da59b | 13846 | struct drm_device *dev = state->dev; |
ed6739ef | 13847 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13848 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13849 | struct drm_crtc *crtc; |
13850 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13851 | int i; |
ed6739ef ACO |
13852 | |
13853 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13854 | return; |
ed6739ef | 13855 | |
0a9ab303 | 13856 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 13857 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
13858 | struct intel_shared_dpll *old_dpll = |
13859 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13860 | |
fb1a38a9 | 13861 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13862 | continue; |
13863 | ||
8106ddbd | 13864 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 13865 | |
8106ddbd | 13866 | if (!old_dpll) |
fb1a38a9 | 13867 | continue; |
0a9ab303 | 13868 | |
ad421372 ML |
13869 | if (!shared_dpll) |
13870 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13871 | |
8106ddbd | 13872 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); |
ad421372 | 13873 | } |
ed6739ef ACO |
13874 | } |
13875 | ||
99d736a2 ML |
13876 | /* |
13877 | * This implements the workaround described in the "notes" section of the mode | |
13878 | * set sequence documentation. When going from no pipes or single pipe to | |
13879 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13880 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13881 | */ | |
13882 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13883 | { | |
13884 | struct drm_crtc_state *crtc_state; | |
13885 | struct intel_crtc *intel_crtc; | |
13886 | struct drm_crtc *crtc; | |
13887 | struct intel_crtc_state *first_crtc_state = NULL; | |
13888 | struct intel_crtc_state *other_crtc_state = NULL; | |
13889 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13890 | int i; | |
13891 | ||
13892 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13893 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13894 | intel_crtc = to_intel_crtc(crtc); | |
13895 | ||
13896 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13897 | continue; | |
13898 | ||
13899 | if (first_crtc_state) { | |
13900 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13901 | break; | |
13902 | } else { | |
13903 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13904 | first_pipe = intel_crtc->pipe; | |
13905 | } | |
13906 | } | |
13907 | ||
13908 | /* No workaround needed? */ | |
13909 | if (!first_crtc_state) | |
13910 | return 0; | |
13911 | ||
13912 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13913 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13914 | struct intel_crtc_state *pipe_config; | |
13915 | ||
13916 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13917 | if (IS_ERR(pipe_config)) | |
13918 | return PTR_ERR(pipe_config); | |
13919 | ||
13920 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13921 | ||
13922 | if (!pipe_config->base.active || | |
13923 | needs_modeset(&pipe_config->base)) | |
13924 | continue; | |
13925 | ||
13926 | /* 2 or more enabled crtcs means no need for w/a */ | |
13927 | if (enabled_pipe != INVALID_PIPE) | |
13928 | return 0; | |
13929 | ||
13930 | enabled_pipe = intel_crtc->pipe; | |
13931 | } | |
13932 | ||
13933 | if (enabled_pipe != INVALID_PIPE) | |
13934 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13935 | else if (other_crtc_state) | |
13936 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13937 | ||
13938 | return 0; | |
13939 | } | |
13940 | ||
27c329ed ML |
13941 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13942 | { | |
13943 | struct drm_crtc *crtc; | |
13944 | struct drm_crtc_state *crtc_state; | |
13945 | int ret = 0; | |
13946 | ||
13947 | /* add all active pipes to the state */ | |
13948 | for_each_crtc(state->dev, crtc) { | |
13949 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13950 | if (IS_ERR(crtc_state)) | |
13951 | return PTR_ERR(crtc_state); | |
13952 | ||
13953 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13954 | continue; | |
13955 | ||
13956 | crtc_state->mode_changed = true; | |
13957 | ||
13958 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13959 | if (ret) | |
13960 | break; | |
13961 | ||
13962 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13963 | if (ret) | |
13964 | break; | |
13965 | } | |
13966 | ||
13967 | return ret; | |
13968 | } | |
13969 | ||
c347a676 | 13970 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13971 | { |
565602d7 | 13972 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 13973 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
13974 | struct drm_crtc *crtc; |
13975 | struct drm_crtc_state *crtc_state; | |
13976 | int ret = 0, i; | |
054518dd | 13977 | |
b359283a ML |
13978 | if (!check_digital_port_conflicts(state)) { |
13979 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13980 | return -EINVAL; | |
13981 | } | |
13982 | ||
565602d7 ML |
13983 | intel_state->modeset = true; |
13984 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13985 | ||
13986 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13987 | if (crtc_state->active) | |
13988 | intel_state->active_crtcs |= 1 << i; | |
13989 | else | |
13990 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 MR |
13991 | |
13992 | if (crtc_state->active != crtc->state->active) | |
13993 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); | |
565602d7 ML |
13994 | } |
13995 | ||
054518dd ACO |
13996 | /* |
13997 | * See if the config requires any additional preparation, e.g. | |
13998 | * to adjust global state with pipes off. We need to do this | |
13999 | * here so we can get the modeset_pipe updated config for the new | |
14000 | * mode set on this crtc. For other crtcs we need to use the | |
14001 | * adjusted_mode bits in the crtc directly. | |
14002 | */ | |
27c329ed | 14003 | if (dev_priv->display.modeset_calc_cdclk) { |
c89e39f3 | 14004 | if (!intel_state->cdclk_pll_vco) |
63911d72 | 14005 | intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco; |
b2045352 VS |
14006 | if (!intel_state->cdclk_pll_vco) |
14007 | intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq; | |
c89e39f3 | 14008 | |
27c329ed | 14009 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
14010 | if (ret < 0) |
14011 | return ret; | |
27c329ed | 14012 | |
c89e39f3 | 14013 | if (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 14014 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco) |
27c329ed ML |
14015 | ret = intel_modeset_all_pipes(state); |
14016 | ||
14017 | if (ret < 0) | |
054518dd | 14018 | return ret; |
e8788cbc ML |
14019 | |
14020 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
14021 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 14022 | } else |
1a617b77 | 14023 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 14024 | |
ad421372 | 14025 | intel_modeset_clear_plls(state); |
054518dd | 14026 | |
565602d7 | 14027 | if (IS_HASWELL(dev_priv)) |
ad421372 | 14028 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 14029 | |
ad421372 | 14030 | return 0; |
c347a676 ACO |
14031 | } |
14032 | ||
aa363136 MR |
14033 | /* |
14034 | * Handle calculation of various watermark data at the end of the atomic check | |
14035 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
14036 | * handlers to ensure that all derived state has been updated. | |
14037 | */ | |
55994c2c | 14038 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
14039 | { |
14040 | struct drm_device *dev = state->dev; | |
98d39494 | 14041 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
14042 | |
14043 | /* Is there platform-specific watermark information to calculate? */ | |
14044 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
14045 | return dev_priv->display.compute_global_watermarks(state); |
14046 | ||
14047 | return 0; | |
aa363136 MR |
14048 | } |
14049 | ||
74c090b1 ML |
14050 | /** |
14051 | * intel_atomic_check - validate state object | |
14052 | * @dev: drm device | |
14053 | * @state: state to validate | |
14054 | */ | |
14055 | static int intel_atomic_check(struct drm_device *dev, | |
14056 | struct drm_atomic_state *state) | |
c347a676 | 14057 | { |
dd8b3bdb | 14058 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 14059 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
14060 | struct drm_crtc *crtc; |
14061 | struct drm_crtc_state *crtc_state; | |
14062 | int ret, i; | |
61333b60 | 14063 | bool any_ms = false; |
c347a676 | 14064 | |
74c090b1 | 14065 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
14066 | if (ret) |
14067 | return ret; | |
14068 | ||
c347a676 | 14069 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
14070 | struct intel_crtc_state *pipe_config = |
14071 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
14072 | |
14073 | /* Catch I915_MODE_FLAG_INHERITED */ | |
14074 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
14075 | crtc_state->mode_changed = true; | |
cfb23ed6 | 14076 | |
af4a879e | 14077 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
14078 | continue; |
14079 | ||
af4a879e DV |
14080 | if (!crtc_state->enable) { |
14081 | any_ms = true; | |
cfb23ed6 | 14082 | continue; |
af4a879e | 14083 | } |
cfb23ed6 | 14084 | |
26495481 DV |
14085 | /* FIXME: For only active_changed we shouldn't need to do any |
14086 | * state recomputation at all. */ | |
14087 | ||
1ed51de9 DV |
14088 | ret = drm_atomic_add_affected_connectors(state, crtc); |
14089 | if (ret) | |
14090 | return ret; | |
b359283a | 14091 | |
cfb23ed6 | 14092 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
14093 | if (ret) { |
14094 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
14095 | pipe_config, "[failed]"); | |
c347a676 | 14096 | return ret; |
25aa1c39 | 14097 | } |
c347a676 | 14098 | |
73831236 | 14099 | if (i915.fastboot && |
dd8b3bdb | 14100 | intel_pipe_config_compare(dev, |
cfb23ed6 | 14101 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 14102 | pipe_config, true)) { |
26495481 | 14103 | crtc_state->mode_changed = false; |
bfd16b2a | 14104 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
14105 | } |
14106 | ||
af4a879e | 14107 | if (needs_modeset(crtc_state)) |
26495481 | 14108 | any_ms = true; |
cfb23ed6 | 14109 | |
af4a879e DV |
14110 | ret = drm_atomic_add_affected_planes(state, crtc); |
14111 | if (ret) | |
14112 | return ret; | |
61333b60 | 14113 | |
26495481 DV |
14114 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
14115 | needs_modeset(crtc_state) ? | |
14116 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
14117 | } |
14118 | ||
61333b60 ML |
14119 | if (any_ms) { |
14120 | ret = intel_modeset_checks(state); | |
14121 | ||
14122 | if (ret) | |
14123 | return ret; | |
27c329ed | 14124 | } else |
dd8b3bdb | 14125 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 14126 | |
dd8b3bdb | 14127 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
14128 | if (ret) |
14129 | return ret; | |
14130 | ||
f51be2e0 | 14131 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 14132 | return calc_watermark_data(state); |
054518dd ACO |
14133 | } |
14134 | ||
5008e874 | 14135 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
d07f0e59 | 14136 | struct drm_atomic_state *state) |
5008e874 | 14137 | { |
fac5e23e | 14138 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 ML |
14139 | struct drm_crtc_state *crtc_state; |
14140 | struct drm_crtc *crtc; | |
14141 | int i, ret; | |
14142 | ||
5a21b665 DV |
14143 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
14144 | if (state->legacy_cursor_update) | |
a6747b73 ML |
14145 | continue; |
14146 | ||
5a21b665 DV |
14147 | ret = intel_crtc_wait_for_pending_flips(crtc); |
14148 | if (ret) | |
14149 | return ret; | |
5008e874 | 14150 | |
5a21b665 DV |
14151 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
14152 | flush_workqueue(dev_priv->wq); | |
d55dbd06 ML |
14153 | } |
14154 | ||
f935675f ML |
14155 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
14156 | if (ret) | |
14157 | return ret; | |
14158 | ||
5008e874 | 14159 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 14160 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 14161 | |
5008e874 ML |
14162 | return ret; |
14163 | } | |
14164 | ||
a2991414 ML |
14165 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
14166 | { | |
14167 | struct drm_device *dev = crtc->base.dev; | |
14168 | ||
14169 | if (!dev->max_vblank_count) | |
14170 | return drm_accurate_vblank_count(&crtc->base); | |
14171 | ||
14172 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
14173 | } | |
14174 | ||
5a21b665 DV |
14175 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
14176 | struct drm_i915_private *dev_priv, | |
14177 | unsigned crtc_mask) | |
e8861675 | 14178 | { |
5a21b665 DV |
14179 | unsigned last_vblank_count[I915_MAX_PIPES]; |
14180 | enum pipe pipe; | |
14181 | int ret; | |
e8861675 | 14182 | |
5a21b665 DV |
14183 | if (!crtc_mask) |
14184 | return; | |
e8861675 | 14185 | |
5a21b665 | 14186 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
14187 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
14188 | pipe); | |
e8861675 | 14189 | |
5a21b665 | 14190 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
14191 | continue; |
14192 | ||
e2af48c6 | 14193 | ret = drm_crtc_vblank_get(&crtc->base); |
5a21b665 DV |
14194 | if (WARN_ON(ret != 0)) { |
14195 | crtc_mask &= ~(1 << pipe); | |
14196 | continue; | |
e8861675 ML |
14197 | } |
14198 | ||
e2af48c6 | 14199 | last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base); |
e8861675 ML |
14200 | } |
14201 | ||
5a21b665 | 14202 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
14203 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
14204 | pipe); | |
5a21b665 | 14205 | long lret; |
e8861675 | 14206 | |
5a21b665 DV |
14207 | if (!((1 << pipe) & crtc_mask)) |
14208 | continue; | |
d55dbd06 | 14209 | |
5a21b665 DV |
14210 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
14211 | last_vblank_count[pipe] != | |
e2af48c6 | 14212 | drm_crtc_vblank_count(&crtc->base), |
5a21b665 | 14213 | msecs_to_jiffies(50)); |
d55dbd06 | 14214 | |
5a21b665 | 14215 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 14216 | |
e2af48c6 | 14217 | drm_crtc_vblank_put(&crtc->base); |
d55dbd06 ML |
14218 | } |
14219 | } | |
14220 | ||
5a21b665 | 14221 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 14222 | { |
5a21b665 DV |
14223 | /* fb updated, need to unpin old fb */ |
14224 | if (crtc_state->fb_changed) | |
14225 | return true; | |
a6747b73 | 14226 | |
5a21b665 DV |
14227 | /* wm changes, need vblank before final wm's */ |
14228 | if (crtc_state->update_wm_post) | |
14229 | return true; | |
a6747b73 | 14230 | |
5a21b665 DV |
14231 | /* |
14232 | * cxsr is re-enabled after vblank. | |
14233 | * This is already handled by crtc_state->update_wm_post, | |
14234 | * but added for clarity. | |
14235 | */ | |
14236 | if (crtc_state->disable_cxsr) | |
14237 | return true; | |
a6747b73 | 14238 | |
5a21b665 | 14239 | return false; |
e8861675 ML |
14240 | } |
14241 | ||
896e5bb0 L |
14242 | static void intel_update_crtc(struct drm_crtc *crtc, |
14243 | struct drm_atomic_state *state, | |
14244 | struct drm_crtc_state *old_crtc_state, | |
14245 | unsigned int *crtc_vblank_mask) | |
14246 | { | |
14247 | struct drm_device *dev = crtc->dev; | |
14248 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14249 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14250 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state); | |
14251 | bool modeset = needs_modeset(crtc->state); | |
14252 | ||
14253 | if (modeset) { | |
14254 | update_scanline_offset(intel_crtc); | |
14255 | dev_priv->display.crtc_enable(pipe_config, state); | |
14256 | } else { | |
14257 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); | |
14258 | } | |
14259 | ||
14260 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
14261 | intel_fbc_enable( | |
14262 | intel_crtc, pipe_config, | |
14263 | to_intel_plane_state(crtc->primary->state)); | |
14264 | } | |
14265 | ||
14266 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); | |
14267 | ||
14268 | if (needs_vblank_wait(pipe_config)) | |
14269 | *crtc_vblank_mask |= drm_crtc_mask(crtc); | |
14270 | } | |
14271 | ||
14272 | static void intel_update_crtcs(struct drm_atomic_state *state, | |
14273 | unsigned int *crtc_vblank_mask) | |
14274 | { | |
14275 | struct drm_crtc *crtc; | |
14276 | struct drm_crtc_state *old_crtc_state; | |
14277 | int i; | |
14278 | ||
14279 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14280 | if (!crtc->state->active) | |
14281 | continue; | |
14282 | ||
14283 | intel_update_crtc(crtc, state, old_crtc_state, | |
14284 | crtc_vblank_mask); | |
14285 | } | |
14286 | } | |
14287 | ||
27082493 L |
14288 | static void skl_update_crtcs(struct drm_atomic_state *state, |
14289 | unsigned int *crtc_vblank_mask) | |
14290 | { | |
0f0f74bc | 14291 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
27082493 L |
14292 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
14293 | struct drm_crtc *crtc; | |
ce0ba283 | 14294 | struct intel_crtc *intel_crtc; |
27082493 | 14295 | struct drm_crtc_state *old_crtc_state; |
ce0ba283 | 14296 | struct intel_crtc_state *cstate; |
27082493 L |
14297 | unsigned int updated = 0; |
14298 | bool progress; | |
14299 | enum pipe pipe; | |
14300 | ||
14301 | /* | |
14302 | * Whenever the number of active pipes changes, we need to make sure we | |
14303 | * update the pipes in the right order so that their ddb allocations | |
14304 | * never overlap with eachother inbetween CRTC updates. Otherwise we'll | |
14305 | * cause pipe underruns and other bad stuff. | |
14306 | */ | |
14307 | do { | |
14308 | int i; | |
14309 | progress = false; | |
14310 | ||
14311 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14312 | bool vbl_wait = false; | |
14313 | unsigned int cmask = drm_crtc_mask(crtc); | |
ce0ba283 L |
14314 | |
14315 | intel_crtc = to_intel_crtc(crtc); | |
14316 | cstate = to_intel_crtc_state(crtc->state); | |
14317 | pipe = intel_crtc->pipe; | |
27082493 L |
14318 | |
14319 | if (updated & cmask || !crtc->state->active) | |
14320 | continue; | |
ce0ba283 | 14321 | if (skl_ddb_allocation_overlaps(state, intel_crtc)) |
27082493 L |
14322 | continue; |
14323 | ||
14324 | updated |= cmask; | |
14325 | ||
14326 | /* | |
14327 | * If this is an already active pipe, it's DDB changed, | |
14328 | * and this isn't the last pipe that needs updating | |
14329 | * then we need to wait for a vblank to pass for the | |
14330 | * new ddb allocation to take effect. | |
14331 | */ | |
ce0ba283 L |
14332 | if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb, |
14333 | &intel_crtc->hw_ddb) && | |
27082493 L |
14334 | !crtc->state->active_changed && |
14335 | intel_state->wm_results.dirty_pipes != updated) | |
14336 | vbl_wait = true; | |
14337 | ||
14338 | intel_update_crtc(crtc, state, old_crtc_state, | |
14339 | crtc_vblank_mask); | |
14340 | ||
14341 | if (vbl_wait) | |
0f0f74bc | 14342 | intel_wait_for_vblank(dev_priv, pipe); |
27082493 L |
14343 | |
14344 | progress = true; | |
14345 | } | |
14346 | } while (progress); | |
14347 | } | |
14348 | ||
94f05024 | 14349 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 14350 | { |
94f05024 | 14351 | struct drm_device *dev = state->dev; |
565602d7 | 14352 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 14353 | struct drm_i915_private *dev_priv = to_i915(dev); |
29ceb0e6 | 14354 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 14355 | struct drm_crtc *crtc; |
5a21b665 | 14356 | struct intel_crtc_state *intel_cstate; |
5a21b665 DV |
14357 | bool hw_check = intel_state->modeset; |
14358 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
14359 | unsigned crtc_vblank_mask = 0; | |
e95433c7 | 14360 | int i; |
a6778b3c | 14361 | |
ea0000f0 DV |
14362 | drm_atomic_helper_wait_for_dependencies(state); |
14363 | ||
565602d7 ML |
14364 | if (intel_state->modeset) { |
14365 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
14366 | sizeof(intel_state->min_pixclk)); | |
14367 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 14368 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
5a21b665 DV |
14369 | |
14370 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
565602d7 ML |
14371 | } |
14372 | ||
29ceb0e6 | 14373 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
14374 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14375 | ||
5a21b665 DV |
14376 | if (needs_modeset(crtc->state) || |
14377 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
14378 | hw_check = true; | |
14379 | ||
14380 | put_domains[to_intel_crtc(crtc)->pipe] = | |
14381 | modeset_get_crtc_power_domains(crtc, | |
14382 | to_intel_crtc_state(crtc->state)); | |
14383 | } | |
14384 | ||
61333b60 ML |
14385 | if (!needs_modeset(crtc->state)) |
14386 | continue; | |
14387 | ||
29ceb0e6 | 14388 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 14389 | |
29ceb0e6 VS |
14390 | if (old_crtc_state->active) { |
14391 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
4a806558 | 14392 | dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state); |
eddfcbcd | 14393 | intel_crtc->active = false; |
58f9c0bc | 14394 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 14395 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
14396 | |
14397 | /* | |
14398 | * Underruns don't always raise | |
14399 | * interrupts, so check manually. | |
14400 | */ | |
14401 | intel_check_cpu_fifo_underruns(dev_priv); | |
14402 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
14403 | |
14404 | if (!crtc->state->active) | |
432081bc | 14405 | intel_update_watermarks(intel_crtc); |
a539205a | 14406 | } |
b8cecdf5 | 14407 | } |
7758a113 | 14408 | |
ea9d758d DV |
14409 | /* Only after disabling all output pipelines that will be changed can we |
14410 | * update the the output configuration. */ | |
4740b0f2 | 14411 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 14412 | |
565602d7 | 14413 | if (intel_state->modeset) { |
4740b0f2 | 14414 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 ML |
14415 | |
14416 | if (dev_priv->display.modeset_commit_cdclk && | |
c89e39f3 | 14417 | (intel_state->dev_cdclk != dev_priv->cdclk_freq || |
63911d72 | 14418 | intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)) |
33c8df89 | 14419 | dev_priv->display.modeset_commit_cdclk(state); |
f6d1973d | 14420 | |
656d1b89 L |
14421 | /* |
14422 | * SKL workaround: bspec recommends we disable the SAGV when we | |
14423 | * have more then one pipe enabled | |
14424 | */ | |
56feca91 | 14425 | if (!intel_can_enable_sagv(state)) |
16dcdc4e | 14426 | intel_disable_sagv(dev_priv); |
656d1b89 | 14427 | |
c0ead703 | 14428 | intel_modeset_verify_disabled(dev); |
4740b0f2 | 14429 | } |
47fab737 | 14430 | |
896e5bb0 | 14431 | /* Complete the events for pipes that have now been disabled */ |
29ceb0e6 | 14432 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a | 14433 | bool modeset = needs_modeset(crtc->state); |
80715b2f | 14434 | |
1f7528c4 DV |
14435 | /* Complete events for now disable pipes here. */ |
14436 | if (modeset && !crtc->state->active && crtc->state->event) { | |
14437 | spin_lock_irq(&dev->event_lock); | |
14438 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
14439 | spin_unlock_irq(&dev->event_lock); | |
14440 | ||
14441 | crtc->state->event = NULL; | |
14442 | } | |
177246a8 MR |
14443 | } |
14444 | ||
896e5bb0 L |
14445 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
14446 | dev_priv->display.update_crtcs(state, &crtc_vblank_mask); | |
14447 | ||
94f05024 DV |
14448 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
14449 | * already, but still need the state for the delayed optimization. To | |
14450 | * fix this: | |
14451 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
14452 | * - schedule that vblank worker _before_ calling hw_done | |
14453 | * - at the start of commit_tail, cancel it _synchrously | |
14454 | * - switch over to the vblank wait helper in the core after that since | |
14455 | * we don't need out special handling any more. | |
14456 | */ | |
5a21b665 DV |
14457 | if (!state->legacy_cursor_update) |
14458 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
14459 | ||
14460 | /* | |
14461 | * Now that the vblank has passed, we can go ahead and program the | |
14462 | * optimal watermarks on platforms that need two-step watermark | |
14463 | * programming. | |
14464 | * | |
14465 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
14466 | */ | |
14467 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14468 | intel_cstate = to_intel_crtc_state(crtc->state); | |
14469 | ||
14470 | if (dev_priv->display.optimize_watermarks) | |
14471 | dev_priv->display.optimize_watermarks(intel_cstate); | |
14472 | } | |
14473 | ||
14474 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
14475 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
14476 | ||
14477 | if (put_domains[i]) | |
14478 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
14479 | ||
14480 | intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state); | |
14481 | } | |
14482 | ||
56feca91 | 14483 | if (intel_state->modeset && intel_can_enable_sagv(state)) |
16dcdc4e | 14484 | intel_enable_sagv(dev_priv); |
656d1b89 | 14485 | |
94f05024 DV |
14486 | drm_atomic_helper_commit_hw_done(state); |
14487 | ||
5a21b665 DV |
14488 | if (intel_state->modeset) |
14489 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
14490 | ||
14491 | mutex_lock(&dev->struct_mutex); | |
14492 | drm_atomic_helper_cleanup_planes(dev, state); | |
14493 | mutex_unlock(&dev->struct_mutex); | |
14494 | ||
ea0000f0 DV |
14495 | drm_atomic_helper_commit_cleanup_done(state); |
14496 | ||
0853695c | 14497 | drm_atomic_state_put(state); |
f30da187 | 14498 | |
75714940 MK |
14499 | /* As one of the primary mmio accessors, KMS has a high likelihood |
14500 | * of triggering bugs in unclaimed access. After we finish | |
14501 | * modesetting, see if an error has been flagged, and if so | |
14502 | * enable debugging for the next modeset - and hope we catch | |
14503 | * the culprit. | |
14504 | * | |
14505 | * XXX note that we assume display power is on at this point. | |
14506 | * This might hold true now but we need to add pm helper to check | |
14507 | * unclaimed only when the hardware is on, as atomic commits | |
14508 | * can happen also when the device is completely off. | |
14509 | */ | |
14510 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
94f05024 DV |
14511 | } |
14512 | ||
14513 | static void intel_atomic_commit_work(struct work_struct *work) | |
14514 | { | |
c004a90b CW |
14515 | struct drm_atomic_state *state = |
14516 | container_of(work, struct drm_atomic_state, commit_work); | |
14517 | ||
94f05024 DV |
14518 | intel_atomic_commit_tail(state); |
14519 | } | |
14520 | ||
c004a90b CW |
14521 | static int __i915_sw_fence_call |
14522 | intel_atomic_commit_ready(struct i915_sw_fence *fence, | |
14523 | enum i915_sw_fence_notify notify) | |
14524 | { | |
14525 | struct intel_atomic_state *state = | |
14526 | container_of(fence, struct intel_atomic_state, commit_ready); | |
14527 | ||
14528 | switch (notify) { | |
14529 | case FENCE_COMPLETE: | |
14530 | if (state->base.commit_work.func) | |
14531 | queue_work(system_unbound_wq, &state->base.commit_work); | |
14532 | break; | |
14533 | ||
14534 | case FENCE_FREE: | |
14535 | drm_atomic_state_put(&state->base); | |
14536 | break; | |
14537 | } | |
14538 | ||
14539 | return NOTIFY_DONE; | |
14540 | } | |
14541 | ||
6c9c1b38 DV |
14542 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
14543 | { | |
14544 | struct drm_plane_state *old_plane_state; | |
14545 | struct drm_plane *plane; | |
6c9c1b38 DV |
14546 | int i; |
14547 | ||
faf5bf0a CW |
14548 | for_each_plane_in_state(state, plane, old_plane_state, i) |
14549 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), | |
14550 | intel_fb_obj(plane->state->fb), | |
14551 | to_intel_plane(plane)->frontbuffer_bit); | |
6c9c1b38 DV |
14552 | } |
14553 | ||
94f05024 DV |
14554 | /** |
14555 | * intel_atomic_commit - commit validated state object | |
14556 | * @dev: DRM device | |
14557 | * @state: the top-level driver state object | |
14558 | * @nonblock: nonblocking commit | |
14559 | * | |
14560 | * This function commits a top-level state object that has been validated | |
14561 | * with drm_atomic_helper_check(). | |
14562 | * | |
14563 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
14564 | * nonblocking commits are only safe for pure plane updates. Everything else | |
14565 | * should work though. | |
14566 | * | |
14567 | * RETURNS | |
14568 | * Zero for success or -errno. | |
14569 | */ | |
14570 | static int intel_atomic_commit(struct drm_device *dev, | |
14571 | struct drm_atomic_state *state, | |
14572 | bool nonblock) | |
14573 | { | |
14574 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 14575 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
14576 | int ret = 0; |
14577 | ||
14578 | if (intel_state->modeset && nonblock) { | |
14579 | DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n"); | |
14580 | return -EINVAL; | |
14581 | } | |
14582 | ||
14583 | ret = drm_atomic_helper_setup_commit(state, nonblock); | |
14584 | if (ret) | |
14585 | return ret; | |
14586 | ||
c004a90b CW |
14587 | drm_atomic_state_get(state); |
14588 | i915_sw_fence_init(&intel_state->commit_ready, | |
14589 | intel_atomic_commit_ready); | |
94f05024 | 14590 | |
d07f0e59 | 14591 | ret = intel_atomic_prepare_commit(dev, state); |
94f05024 DV |
14592 | if (ret) { |
14593 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
c004a90b | 14594 | i915_sw_fence_commit(&intel_state->commit_ready); |
94f05024 DV |
14595 | return ret; |
14596 | } | |
14597 | ||
14598 | drm_atomic_helper_swap_state(state, true); | |
14599 | dev_priv->wm.distrust_bios_wm = false; | |
14600 | dev_priv->wm.skl_results = intel_state->wm_results; | |
14601 | intel_shared_dpll_commit(state); | |
6c9c1b38 | 14602 | intel_atomic_track_fbs(state); |
94f05024 | 14603 | |
0853695c | 14604 | drm_atomic_state_get(state); |
c004a90b CW |
14605 | INIT_WORK(&state->commit_work, |
14606 | nonblock ? intel_atomic_commit_work : NULL); | |
14607 | ||
14608 | i915_sw_fence_commit(&intel_state->commit_ready); | |
14609 | if (!nonblock) { | |
14610 | i915_sw_fence_wait(&intel_state->commit_ready); | |
94f05024 | 14611 | intel_atomic_commit_tail(state); |
c004a90b | 14612 | } |
75714940 | 14613 | |
74c090b1 | 14614 | return 0; |
7f27126e JB |
14615 | } |
14616 | ||
c0c36b94 CW |
14617 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
14618 | { | |
83a57153 ACO |
14619 | struct drm_device *dev = crtc->dev; |
14620 | struct drm_atomic_state *state; | |
e694eb02 | 14621 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 14622 | int ret; |
83a57153 ACO |
14623 | |
14624 | state = drm_atomic_state_alloc(dev); | |
14625 | if (!state) { | |
78108b7c VS |
14626 | DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory", |
14627 | crtc->base.id, crtc->name); | |
83a57153 ACO |
14628 | return; |
14629 | } | |
14630 | ||
e694eb02 | 14631 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 14632 | |
e694eb02 ML |
14633 | retry: |
14634 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
14635 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
14636 | if (!ret) { | |
14637 | if (!crtc_state->active) | |
14638 | goto out; | |
83a57153 | 14639 | |
e694eb02 | 14640 | crtc_state->mode_changed = true; |
74c090b1 | 14641 | ret = drm_atomic_commit(state); |
83a57153 ACO |
14642 | } |
14643 | ||
e694eb02 ML |
14644 | if (ret == -EDEADLK) { |
14645 | drm_atomic_state_clear(state); | |
14646 | drm_modeset_backoff(state->acquire_ctx); | |
14647 | goto retry; | |
4ed9fb37 | 14648 | } |
4be07317 | 14649 | |
e694eb02 | 14650 | out: |
0853695c | 14651 | drm_atomic_state_put(state); |
c0c36b94 CW |
14652 | } |
14653 | ||
a8784875 BP |
14654 | /* |
14655 | * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling | |
14656 | * drm_atomic_helper_legacy_gamma_set() directly. | |
14657 | */ | |
14658 | static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc, | |
14659 | u16 *red, u16 *green, u16 *blue, | |
14660 | uint32_t size) | |
14661 | { | |
14662 | struct drm_device *dev = crtc->dev; | |
14663 | struct drm_mode_config *config = &dev->mode_config; | |
14664 | struct drm_crtc_state *state; | |
14665 | int ret; | |
14666 | ||
14667 | ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size); | |
14668 | if (ret) | |
14669 | return ret; | |
14670 | ||
14671 | /* | |
14672 | * Make sure we update the legacy properties so this works when | |
14673 | * atomic is not enabled. | |
14674 | */ | |
14675 | ||
14676 | state = crtc->state; | |
14677 | ||
14678 | drm_object_property_set_value(&crtc->base, | |
14679 | config->degamma_lut_property, | |
14680 | (state->degamma_lut) ? | |
14681 | state->degamma_lut->base.id : 0); | |
14682 | ||
14683 | drm_object_property_set_value(&crtc->base, | |
14684 | config->ctm_property, | |
14685 | (state->ctm) ? | |
14686 | state->ctm->base.id : 0); | |
14687 | ||
14688 | drm_object_property_set_value(&crtc->base, | |
14689 | config->gamma_lut_property, | |
14690 | (state->gamma_lut) ? | |
14691 | state->gamma_lut->base.id : 0); | |
14692 | ||
14693 | return 0; | |
14694 | } | |
14695 | ||
f6e5b160 | 14696 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
a8784875 | 14697 | .gamma_set = intel_atomic_legacy_gamma_set, |
74c090b1 | 14698 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 14699 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 | 14700 | .destroy = intel_crtc_destroy, |
527b6abe | 14701 | .page_flip = intel_crtc_page_flip, |
1356837e MR |
14702 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
14703 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
14704 | }; |
14705 | ||
6beb8c23 MR |
14706 | /** |
14707 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
14708 | * @plane: drm plane to prepare for | |
14709 | * @fb: framebuffer to prepare for presentation | |
14710 | * | |
14711 | * Prepares a framebuffer for usage on a display plane. Generally this | |
14712 | * involves pinning the underlying object and updating the frontbuffer tracking | |
14713 | * bits. Some older platforms need special physical address handling for | |
14714 | * cursor planes. | |
14715 | * | |
f935675f ML |
14716 | * Must be called with struct_mutex held. |
14717 | * | |
6beb8c23 MR |
14718 | * Returns 0 on success, negative error code on failure. |
14719 | */ | |
14720 | int | |
14721 | intel_prepare_plane_fb(struct drm_plane *plane, | |
1832040d | 14722 | struct drm_plane_state *new_state) |
465c120c | 14723 | { |
c004a90b CW |
14724 | struct intel_atomic_state *intel_state = |
14725 | to_intel_atomic_state(new_state->state); | |
465c120c | 14726 | struct drm_device *dev = plane->dev; |
50a0bc90 | 14727 | struct drm_i915_private *dev_priv = to_i915(dev); |
844f9111 | 14728 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 14729 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 14730 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c004a90b | 14731 | int ret; |
465c120c | 14732 | |
1ee49399 | 14733 | if (!obj && !old_obj) |
465c120c MR |
14734 | return 0; |
14735 | ||
5008e874 ML |
14736 | if (old_obj) { |
14737 | struct drm_crtc_state *crtc_state = | |
c004a90b CW |
14738 | drm_atomic_get_existing_crtc_state(new_state->state, |
14739 | plane->state->crtc); | |
5008e874 ML |
14740 | |
14741 | /* Big Hammer, we also need to ensure that any pending | |
14742 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
14743 | * current scanout is retired before unpinning the old | |
14744 | * framebuffer. Note that we rely on userspace rendering | |
14745 | * into the buffer attached to the pipe they are waiting | |
14746 | * on. If not, userspace generates a GPU hang with IPEHR | |
14747 | * point to the MI_WAIT_FOR_EVENT. | |
14748 | * | |
14749 | * This should only fail upon a hung GPU, in which case we | |
14750 | * can safely continue. | |
14751 | */ | |
c004a90b CW |
14752 | if (needs_modeset(crtc_state)) { |
14753 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
14754 | old_obj->resv, NULL, | |
14755 | false, 0, | |
14756 | GFP_KERNEL); | |
14757 | if (ret < 0) | |
14758 | return ret; | |
f4457ae7 | 14759 | } |
5008e874 ML |
14760 | } |
14761 | ||
c004a90b CW |
14762 | if (new_state->fence) { /* explicit fencing */ |
14763 | ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready, | |
14764 | new_state->fence, | |
14765 | I915_FENCE_TIMEOUT, | |
14766 | GFP_KERNEL); | |
14767 | if (ret < 0) | |
14768 | return ret; | |
14769 | } | |
14770 | ||
c37efb99 CW |
14771 | if (!obj) |
14772 | return 0; | |
14773 | ||
c004a90b CW |
14774 | if (!new_state->fence) { /* implicit fencing */ |
14775 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
14776 | obj->resv, NULL, | |
14777 | false, I915_FENCE_TIMEOUT, | |
14778 | GFP_KERNEL); | |
14779 | if (ret < 0) | |
14780 | return ret; | |
14781 | } | |
5a21b665 | 14782 | |
c37efb99 | 14783 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
6beb8c23 | 14784 | INTEL_INFO(dev)->cursor_needs_physical) { |
50a0bc90 | 14785 | int align = IS_I830(dev_priv) ? 16 * 1024 : 256; |
6beb8c23 | 14786 | ret = i915_gem_object_attach_phys(obj, align); |
d07f0e59 | 14787 | if (ret) { |
6beb8c23 | 14788 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
d07f0e59 CW |
14789 | return ret; |
14790 | } | |
6beb8c23 | 14791 | } else { |
058d88c4 CW |
14792 | struct i915_vma *vma; |
14793 | ||
14794 | vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); | |
d07f0e59 CW |
14795 | if (IS_ERR(vma)) { |
14796 | DRM_DEBUG_KMS("failed to pin object\n"); | |
14797 | return PTR_ERR(vma); | |
14798 | } | |
7580d774 | 14799 | } |
fdd508a6 | 14800 | |
d07f0e59 | 14801 | return 0; |
6beb8c23 MR |
14802 | } |
14803 | ||
38f3ce3a MR |
14804 | /** |
14805 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
14806 | * @plane: drm plane to clean up for | |
14807 | * @fb: old framebuffer that was on plane | |
14808 | * | |
14809 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
14810 | * |
14811 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
14812 | */ |
14813 | void | |
14814 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
1832040d | 14815 | struct drm_plane_state *old_state) |
38f3ce3a MR |
14816 | { |
14817 | struct drm_device *dev = plane->dev; | |
7580d774 | 14818 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
14819 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
14820 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 14821 | |
7580d774 ML |
14822 | old_intel_state = to_intel_plane_state(old_state); |
14823 | ||
1ee49399 | 14824 | if (!obj && !old_obj) |
38f3ce3a MR |
14825 | return; |
14826 | ||
1ee49399 ML |
14827 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
14828 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
3465c580 | 14829 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
465c120c MR |
14830 | } |
14831 | ||
6156a456 CK |
14832 | int |
14833 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
14834 | { | |
14835 | int max_scale; | |
6156a456 CK |
14836 | int crtc_clock, cdclk; |
14837 | ||
bf8a0af0 | 14838 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
14839 | return DRM_PLANE_HELPER_NO_SCALING; |
14840 | ||
6156a456 | 14841 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
27c329ed | 14842 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 14843 | |
54bf1ce6 | 14844 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
14845 | return DRM_PLANE_HELPER_NO_SCALING; |
14846 | ||
14847 | /* | |
14848 | * skl max scale is lower of: | |
14849 | * close to 3 but not 3, -1 is for that purpose | |
14850 | * or | |
14851 | * cdclk/crtc_clock | |
14852 | */ | |
14853 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
14854 | ||
14855 | return max_scale; | |
14856 | } | |
14857 | ||
465c120c | 14858 | static int |
3c692a41 | 14859 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 14860 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
14861 | struct intel_plane_state *state) |
14862 | { | |
b63a16f6 | 14863 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
2b875c22 | 14864 | struct drm_crtc *crtc = state->base.crtc; |
6156a456 | 14865 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
14866 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
14867 | bool can_position = false; | |
b63a16f6 | 14868 | int ret; |
465c120c | 14869 | |
b63a16f6 | 14870 | if (INTEL_GEN(dev_priv) >= 9) { |
693bdc28 VS |
14871 | /* use scaler when colorkey is not required */ |
14872 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
14873 | min_scale = 1; | |
14874 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
14875 | } | |
d8106366 | 14876 | can_position = true; |
6156a456 | 14877 | } |
d8106366 | 14878 | |
cc926387 DV |
14879 | ret = drm_plane_helper_check_state(&state->base, |
14880 | &state->clip, | |
14881 | min_scale, max_scale, | |
14882 | can_position, true); | |
b63a16f6 VS |
14883 | if (ret) |
14884 | return ret; | |
14885 | ||
cc926387 | 14886 | if (!state->base.fb) |
b63a16f6 VS |
14887 | return 0; |
14888 | ||
14889 | if (INTEL_GEN(dev_priv) >= 9) { | |
14890 | ret = skl_check_plane_surface(state); | |
14891 | if (ret) | |
14892 | return ret; | |
14893 | } | |
14894 | ||
14895 | return 0; | |
14af293f GP |
14896 | } |
14897 | ||
5a21b665 DV |
14898 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
14899 | struct drm_crtc_state *old_crtc_state) | |
14900 | { | |
14901 | struct drm_device *dev = crtc->dev; | |
62e0fb88 | 14902 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 14903 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b707aa50 L |
14904 | struct intel_crtc_state *intel_cstate = |
14905 | to_intel_crtc_state(crtc->state); | |
5a21b665 DV |
14906 | struct intel_crtc_state *old_intel_state = |
14907 | to_intel_crtc_state(old_crtc_state); | |
14908 | bool modeset = needs_modeset(crtc->state); | |
62e0fb88 | 14909 | enum pipe pipe = intel_crtc->pipe; |
5a21b665 DV |
14910 | |
14911 | /* Perform vblank evasion around commit operation */ | |
14912 | intel_pipe_update_start(intel_crtc); | |
14913 | ||
14914 | if (modeset) | |
14915 | return; | |
14916 | ||
14917 | if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) { | |
14918 | intel_color_set_csc(crtc->state); | |
14919 | intel_color_load_luts(crtc->state); | |
14920 | } | |
14921 | ||
b707aa50 | 14922 | if (intel_cstate->update_pipe) { |
5a21b665 | 14923 | intel_update_pipe_config(intel_crtc, old_intel_state); |
b707aa50 | 14924 | } else if (INTEL_GEN(dev_priv) >= 9) { |
5a21b665 | 14925 | skl_detach_scalers(intel_crtc); |
62e0fb88 L |
14926 | |
14927 | I915_WRITE(PIPE_WM_LINETIME(pipe), | |
b707aa50 | 14928 | intel_cstate->wm.skl.optimal.linetime); |
62e0fb88 | 14929 | } |
5a21b665 DV |
14930 | } |
14931 | ||
14932 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
14933 | struct drm_crtc_state *old_crtc_state) | |
14934 | { | |
14935 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
14936 | ||
14937 | intel_pipe_update_end(intel_crtc, NULL); | |
14938 | } | |
14939 | ||
cf4c7c12 | 14940 | /** |
4a3b8769 MR |
14941 | * intel_plane_destroy - destroy a plane |
14942 | * @plane: plane to destroy | |
cf4c7c12 | 14943 | * |
4a3b8769 MR |
14944 | * Common destruction function for all types of planes (primary, cursor, |
14945 | * sprite). | |
cf4c7c12 | 14946 | */ |
4a3b8769 | 14947 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 14948 | { |
465c120c | 14949 | drm_plane_cleanup(plane); |
69ae561f | 14950 | kfree(to_intel_plane(plane)); |
465c120c MR |
14951 | } |
14952 | ||
65a3fea0 | 14953 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
14954 | .update_plane = drm_atomic_helper_update_plane, |
14955 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 14956 | .destroy = intel_plane_destroy, |
c196e1d6 | 14957 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
14958 | .atomic_get_property = intel_plane_atomic_get_property, |
14959 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
14960 | .atomic_duplicate_state = intel_plane_duplicate_state, |
14961 | .atomic_destroy_state = intel_plane_destroy_state, | |
465c120c MR |
14962 | }; |
14963 | ||
b079bd17 | 14964 | static struct intel_plane * |
580503c7 | 14965 | intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
465c120c | 14966 | { |
fca0ce2a VS |
14967 | struct intel_plane *primary = NULL; |
14968 | struct intel_plane_state *state = NULL; | |
465c120c | 14969 | const uint32_t *intel_primary_formats; |
93ca7e00 | 14970 | unsigned int supported_rotations; |
45e3743a | 14971 | unsigned int num_formats; |
fca0ce2a | 14972 | int ret; |
465c120c MR |
14973 | |
14974 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
b079bd17 VS |
14975 | if (!primary) { |
14976 | ret = -ENOMEM; | |
fca0ce2a | 14977 | goto fail; |
b079bd17 | 14978 | } |
465c120c | 14979 | |
8e7d688b | 14980 | state = intel_create_plane_state(&primary->base); |
b079bd17 VS |
14981 | if (!state) { |
14982 | ret = -ENOMEM; | |
fca0ce2a | 14983 | goto fail; |
b079bd17 VS |
14984 | } |
14985 | ||
8e7d688b | 14986 | primary->base.state = &state->base; |
ea2c67bb | 14987 | |
465c120c MR |
14988 | primary->can_scale = false; |
14989 | primary->max_downscale = 1; | |
580503c7 | 14990 | if (INTEL_GEN(dev_priv) >= 9) { |
6156a456 | 14991 | primary->can_scale = true; |
af99ceda | 14992 | state->scaler_id = -1; |
6156a456 | 14993 | } |
465c120c MR |
14994 | primary->pipe = pipe; |
14995 | primary->plane = pipe; | |
a9ff8714 | 14996 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 14997 | primary->check_plane = intel_check_primary_plane; |
580503c7 | 14998 | if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) |
465c120c MR |
14999 | primary->plane = !pipe; |
15000 | ||
580503c7 | 15001 | if (INTEL_GEN(dev_priv) >= 9) { |
6c0fd451 DL |
15002 | intel_primary_formats = skl_primary_formats; |
15003 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
15004 | |
15005 | primary->update_plane = skylake_update_primary_plane; | |
15006 | primary->disable_plane = skylake_disable_primary_plane; | |
6e266956 | 15007 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
a8d201af ML |
15008 | intel_primary_formats = i965_primary_formats; |
15009 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
15010 | ||
15011 | primary->update_plane = ironlake_update_primary_plane; | |
15012 | primary->disable_plane = i9xx_disable_primary_plane; | |
580503c7 | 15013 | } else if (INTEL_GEN(dev_priv) >= 4) { |
568db4f2 DL |
15014 | intel_primary_formats = i965_primary_formats; |
15015 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
15016 | |
15017 | primary->update_plane = i9xx_update_primary_plane; | |
15018 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
15019 | } else { |
15020 | intel_primary_formats = i8xx_primary_formats; | |
15021 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
15022 | |
15023 | primary->update_plane = i9xx_update_primary_plane; | |
15024 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
15025 | } |
15026 | ||
580503c7 VS |
15027 | if (INTEL_GEN(dev_priv) >= 9) |
15028 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, | |
15029 | 0, &intel_plane_funcs, | |
38573dc1 VS |
15030 | intel_primary_formats, num_formats, |
15031 | DRM_PLANE_TYPE_PRIMARY, | |
15032 | "plane 1%c", pipe_name(pipe)); | |
9beb5fea | 15033 | else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
580503c7 VS |
15034 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
15035 | 0, &intel_plane_funcs, | |
38573dc1 VS |
15036 | intel_primary_formats, num_formats, |
15037 | DRM_PLANE_TYPE_PRIMARY, | |
15038 | "primary %c", pipe_name(pipe)); | |
15039 | else | |
580503c7 VS |
15040 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
15041 | 0, &intel_plane_funcs, | |
38573dc1 VS |
15042 | intel_primary_formats, num_formats, |
15043 | DRM_PLANE_TYPE_PRIMARY, | |
15044 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
15045 | if (ret) |
15046 | goto fail; | |
48404c1e | 15047 | |
5481e27f | 15048 | if (INTEL_GEN(dev_priv) >= 9) { |
93ca7e00 VS |
15049 | supported_rotations = |
15050 | DRM_ROTATE_0 | DRM_ROTATE_90 | | |
15051 | DRM_ROTATE_180 | DRM_ROTATE_270; | |
5481e27f | 15052 | } else if (INTEL_GEN(dev_priv) >= 4) { |
93ca7e00 VS |
15053 | supported_rotations = |
15054 | DRM_ROTATE_0 | DRM_ROTATE_180; | |
15055 | } else { | |
15056 | supported_rotations = DRM_ROTATE_0; | |
15057 | } | |
15058 | ||
5481e27f | 15059 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 VS |
15060 | drm_plane_create_rotation_property(&primary->base, |
15061 | DRM_ROTATE_0, | |
15062 | supported_rotations); | |
48404c1e | 15063 | |
ea2c67bb MR |
15064 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
15065 | ||
b079bd17 | 15066 | return primary; |
fca0ce2a VS |
15067 | |
15068 | fail: | |
15069 | kfree(state); | |
15070 | kfree(primary); | |
15071 | ||
b079bd17 | 15072 | return ERR_PTR(ret); |
465c120c MR |
15073 | } |
15074 | ||
3d7d6510 | 15075 | static int |
852e787c | 15076 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 15077 | struct intel_crtc_state *crtc_state, |
852e787c | 15078 | struct intel_plane_state *state) |
3d7d6510 | 15079 | { |
2b875c22 | 15080 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 15081 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 15082 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
15083 | unsigned stride; |
15084 | int ret; | |
3d7d6510 | 15085 | |
f8856a44 VS |
15086 | ret = drm_plane_helper_check_state(&state->base, |
15087 | &state->clip, | |
15088 | DRM_PLANE_HELPER_NO_SCALING, | |
15089 | DRM_PLANE_HELPER_NO_SCALING, | |
15090 | true, true); | |
757f9a3e GP |
15091 | if (ret) |
15092 | return ret; | |
15093 | ||
757f9a3e GP |
15094 | /* if we want to turn off the cursor ignore width and height */ |
15095 | if (!obj) | |
da20eabd | 15096 | return 0; |
757f9a3e | 15097 | |
757f9a3e | 15098 | /* Check for which cursor types we support */ |
50a0bc90 TU |
15099 | if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w, |
15100 | state->base.crtc_h)) { | |
ea2c67bb MR |
15101 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
15102 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
15103 | return -EINVAL; |
15104 | } | |
15105 | ||
ea2c67bb MR |
15106 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
15107 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
15108 | DRM_DEBUG_KMS("buffer is too small\n"); |
15109 | return -ENOMEM; | |
15110 | } | |
15111 | ||
3a656b54 | 15112 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 15113 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 15114 | return -EINVAL; |
32b7eeec MR |
15115 | } |
15116 | ||
b29ec92c VS |
15117 | /* |
15118 | * There's something wrong with the cursor on CHV pipe C. | |
15119 | * If it straddles the left edge of the screen then | |
15120 | * moving it away from the edge or disabling it often | |
15121 | * results in a pipe underrun, and often that can lead to | |
15122 | * dead pipe (constant underrun reported, and it scans | |
15123 | * out just a solid color). To recover from that, the | |
15124 | * display power well must be turned off and on again. | |
15125 | * Refuse the put the cursor into that compromised position. | |
15126 | */ | |
920a14b2 | 15127 | if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C && |
936e71e3 | 15128 | state->base.visible && state->base.crtc_x < 0) { |
b29ec92c VS |
15129 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); |
15130 | return -EINVAL; | |
15131 | } | |
15132 | ||
da20eabd | 15133 | return 0; |
852e787c | 15134 | } |
3d7d6510 | 15135 | |
a8ad0d8e ML |
15136 | static void |
15137 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 15138 | struct drm_crtc *crtc) |
a8ad0d8e | 15139 | { |
f2858021 ML |
15140 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
15141 | ||
15142 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 15143 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
15144 | } |
15145 | ||
f4a2cf29 | 15146 | static void |
55a08b3f ML |
15147 | intel_update_cursor_plane(struct drm_plane *plane, |
15148 | const struct intel_crtc_state *crtc_state, | |
15149 | const struct intel_plane_state *state) | |
852e787c | 15150 | { |
55a08b3f ML |
15151 | struct drm_crtc *crtc = crtc_state->base.crtc; |
15152 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 15153 | struct drm_device *dev = plane->dev; |
2b875c22 | 15154 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 15155 | uint32_t addr; |
852e787c | 15156 | |
f4a2cf29 | 15157 | if (!obj) |
a912f12f | 15158 | addr = 0; |
f4a2cf29 | 15159 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
058d88c4 | 15160 | addr = i915_gem_object_ggtt_offset(obj, NULL); |
f4a2cf29 | 15161 | else |
a912f12f | 15162 | addr = obj->phys_handle->busaddr; |
852e787c | 15163 | |
a912f12f | 15164 | intel_crtc->cursor_addr = addr; |
55a08b3f | 15165 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
15166 | } |
15167 | ||
b079bd17 | 15168 | static struct intel_plane * |
580503c7 | 15169 | intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
3d7d6510 | 15170 | { |
fca0ce2a VS |
15171 | struct intel_plane *cursor = NULL; |
15172 | struct intel_plane_state *state = NULL; | |
15173 | int ret; | |
3d7d6510 MR |
15174 | |
15175 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
b079bd17 VS |
15176 | if (!cursor) { |
15177 | ret = -ENOMEM; | |
fca0ce2a | 15178 | goto fail; |
b079bd17 | 15179 | } |
3d7d6510 | 15180 | |
8e7d688b | 15181 | state = intel_create_plane_state(&cursor->base); |
b079bd17 VS |
15182 | if (!state) { |
15183 | ret = -ENOMEM; | |
fca0ce2a | 15184 | goto fail; |
b079bd17 VS |
15185 | } |
15186 | ||
8e7d688b | 15187 | cursor->base.state = &state->base; |
ea2c67bb | 15188 | |
3d7d6510 MR |
15189 | cursor->can_scale = false; |
15190 | cursor->max_downscale = 1; | |
15191 | cursor->pipe = pipe; | |
15192 | cursor->plane = pipe; | |
a9ff8714 | 15193 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 15194 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 15195 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 15196 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 | 15197 | |
580503c7 VS |
15198 | ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, |
15199 | 0, &intel_plane_funcs, | |
fca0ce2a VS |
15200 | intel_cursor_formats, |
15201 | ARRAY_SIZE(intel_cursor_formats), | |
38573dc1 VS |
15202 | DRM_PLANE_TYPE_CURSOR, |
15203 | "cursor %c", pipe_name(pipe)); | |
fca0ce2a VS |
15204 | if (ret) |
15205 | goto fail; | |
4398ad45 | 15206 | |
5481e27f | 15207 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 VS |
15208 | drm_plane_create_rotation_property(&cursor->base, |
15209 | DRM_ROTATE_0, | |
15210 | DRM_ROTATE_0 | | |
15211 | DRM_ROTATE_180); | |
4398ad45 | 15212 | |
580503c7 | 15213 | if (INTEL_GEN(dev_priv) >= 9) |
af99ceda CK |
15214 | state->scaler_id = -1; |
15215 | ||
ea2c67bb MR |
15216 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
15217 | ||
b079bd17 | 15218 | return cursor; |
fca0ce2a VS |
15219 | |
15220 | fail: | |
15221 | kfree(state); | |
15222 | kfree(cursor); | |
15223 | ||
b079bd17 | 15224 | return ERR_PTR(ret); |
3d7d6510 MR |
15225 | } |
15226 | ||
65edccce VS |
15227 | static void skl_init_scalers(struct drm_i915_private *dev_priv, |
15228 | struct intel_crtc *crtc, | |
15229 | struct intel_crtc_state *crtc_state) | |
549e2bfb | 15230 | { |
65edccce VS |
15231 | struct intel_crtc_scaler_state *scaler_state = |
15232 | &crtc_state->scaler_state; | |
549e2bfb | 15233 | int i; |
549e2bfb | 15234 | |
65edccce VS |
15235 | for (i = 0; i < crtc->num_scalers; i++) { |
15236 | struct intel_scaler *scaler = &scaler_state->scalers[i]; | |
15237 | ||
15238 | scaler->in_use = 0; | |
15239 | scaler->mode = PS_SCALER_MODE_DYN; | |
549e2bfb CK |
15240 | } |
15241 | ||
15242 | scaler_state->scaler_id = -1; | |
15243 | } | |
15244 | ||
5ab0d85b | 15245 | static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) |
79e53945 JB |
15246 | { |
15247 | struct intel_crtc *intel_crtc; | |
f5de6e07 | 15248 | struct intel_crtc_state *crtc_state = NULL; |
b079bd17 VS |
15249 | struct intel_plane *primary = NULL; |
15250 | struct intel_plane *cursor = NULL; | |
a81d6fa0 | 15251 | int sprite, ret; |
79e53945 | 15252 | |
955382f3 | 15253 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
b079bd17 VS |
15254 | if (!intel_crtc) |
15255 | return -ENOMEM; | |
79e53945 | 15256 | |
f5de6e07 | 15257 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
b079bd17 VS |
15258 | if (!crtc_state) { |
15259 | ret = -ENOMEM; | |
f5de6e07 | 15260 | goto fail; |
b079bd17 | 15261 | } |
550acefd ACO |
15262 | intel_crtc->config = crtc_state; |
15263 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 15264 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 15265 | |
549e2bfb | 15266 | /* initialize shared scalers */ |
5ab0d85b | 15267 | if (INTEL_GEN(dev_priv) >= 9) { |
549e2bfb CK |
15268 | if (pipe == PIPE_C) |
15269 | intel_crtc->num_scalers = 1; | |
15270 | else | |
15271 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
15272 | ||
65edccce | 15273 | skl_init_scalers(dev_priv, intel_crtc, crtc_state); |
549e2bfb CK |
15274 | } |
15275 | ||
580503c7 | 15276 | primary = intel_primary_plane_create(dev_priv, pipe); |
b079bd17 VS |
15277 | if (IS_ERR(primary)) { |
15278 | ret = PTR_ERR(primary); | |
3d7d6510 | 15279 | goto fail; |
b079bd17 | 15280 | } |
3d7d6510 | 15281 | |
a81d6fa0 | 15282 | for_each_sprite(dev_priv, pipe, sprite) { |
b079bd17 VS |
15283 | struct intel_plane *plane; |
15284 | ||
580503c7 | 15285 | plane = intel_sprite_plane_create(dev_priv, pipe, sprite); |
b079bd17 VS |
15286 | if (!plane) { |
15287 | ret = PTR_ERR(plane); | |
15288 | goto fail; | |
15289 | } | |
a81d6fa0 VS |
15290 | } |
15291 | ||
580503c7 | 15292 | cursor = intel_cursor_plane_create(dev_priv, pipe); |
b079bd17 VS |
15293 | if (!cursor) { |
15294 | ret = PTR_ERR(cursor); | |
3d7d6510 | 15295 | goto fail; |
b079bd17 | 15296 | } |
3d7d6510 | 15297 | |
5ab0d85b | 15298 | ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base, |
b079bd17 VS |
15299 | &primary->base, &cursor->base, |
15300 | &intel_crtc_funcs, | |
4d5d72b7 | 15301 | "pipe %c", pipe_name(pipe)); |
3d7d6510 MR |
15302 | if (ret) |
15303 | goto fail; | |
79e53945 | 15304 | |
1f1c2e24 VS |
15305 | /* |
15306 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 15307 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 15308 | */ |
80824003 | 15309 | intel_crtc->pipe = pipe; |
b079bd17 | 15310 | intel_crtc->plane = (enum plane) pipe; |
5ab0d85b | 15311 | if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) { |
28c97730 | 15312 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 15313 | intel_crtc->plane = !pipe; |
80824003 JB |
15314 | } |
15315 | ||
4b0e333e CW |
15316 | intel_crtc->cursor_base = ~0; |
15317 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 15318 | intel_crtc->cursor_size = ~0; |
8d7849db | 15319 | |
852eb00d VS |
15320 | intel_crtc->wm.cxsr_allowed = true; |
15321 | ||
22fd0fab JB |
15322 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
15323 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
e2af48c6 VS |
15324 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc; |
15325 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc; | |
22fd0fab | 15326 | |
79e53945 | 15327 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 15328 | |
8563b1e8 LL |
15329 | intel_color_init(&intel_crtc->base); |
15330 | ||
87b6b101 | 15331 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
b079bd17 VS |
15332 | |
15333 | return 0; | |
3d7d6510 MR |
15334 | |
15335 | fail: | |
b079bd17 VS |
15336 | /* |
15337 | * drm_mode_config_cleanup() will free up any | |
15338 | * crtcs/planes already initialized. | |
15339 | */ | |
f5de6e07 | 15340 | kfree(crtc_state); |
3d7d6510 | 15341 | kfree(intel_crtc); |
b079bd17 VS |
15342 | |
15343 | return ret; | |
79e53945 JB |
15344 | } |
15345 | ||
752aa88a JB |
15346 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
15347 | { | |
15348 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 15349 | struct drm_device *dev = connector->base.dev; |
752aa88a | 15350 | |
51fd371b | 15351 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 15352 | |
d3babd3f | 15353 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
15354 | return INVALID_PIPE; |
15355 | ||
15356 | return to_intel_crtc(encoder->crtc)->pipe; | |
15357 | } | |
15358 | ||
08d7b3d1 | 15359 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 15360 | struct drm_file *file) |
08d7b3d1 | 15361 | { |
08d7b3d1 | 15362 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 15363 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 15364 | struct intel_crtc *crtc; |
08d7b3d1 | 15365 | |
7707e653 | 15366 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 15367 | if (!drmmode_crtc) |
3f2c2057 | 15368 | return -ENOENT; |
08d7b3d1 | 15369 | |
7707e653 | 15370 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 15371 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 15372 | |
c05422d5 | 15373 | return 0; |
08d7b3d1 CW |
15374 | } |
15375 | ||
66a9278e | 15376 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 15377 | { |
66a9278e DV |
15378 | struct drm_device *dev = encoder->base.dev; |
15379 | struct intel_encoder *source_encoder; | |
79e53945 | 15380 | int index_mask = 0; |
79e53945 JB |
15381 | int entry = 0; |
15382 | ||
b2784e15 | 15383 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 15384 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
15385 | index_mask |= (1 << entry); |
15386 | ||
79e53945 JB |
15387 | entry++; |
15388 | } | |
4ef69c7a | 15389 | |
79e53945 JB |
15390 | return index_mask; |
15391 | } | |
15392 | ||
646d5772 | 15393 | static bool has_edp_a(struct drm_i915_private *dev_priv) |
4d302442 | 15394 | { |
646d5772 | 15395 | if (!IS_MOBILE(dev_priv)) |
4d302442 CW |
15396 | return false; |
15397 | ||
15398 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
15399 | return false; | |
15400 | ||
5db94019 | 15401 | if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
15402 | return false; |
15403 | ||
15404 | return true; | |
15405 | } | |
15406 | ||
84b4e042 JB |
15407 | static bool intel_crt_present(struct drm_device *dev) |
15408 | { | |
fac5e23e | 15409 | struct drm_i915_private *dev_priv = to_i915(dev); |
84b4e042 | 15410 | |
884497ed DL |
15411 | if (INTEL_INFO(dev)->gen >= 9) |
15412 | return false; | |
15413 | ||
50a0bc90 | 15414 | if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) |
84b4e042 JB |
15415 | return false; |
15416 | ||
920a14b2 | 15417 | if (IS_CHERRYVIEW(dev_priv)) |
84b4e042 JB |
15418 | return false; |
15419 | ||
4f8036a2 TU |
15420 | if (HAS_PCH_LPT_H(dev_priv) && |
15421 | I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) | |
65e472e4 VS |
15422 | return false; |
15423 | ||
70ac54d0 | 15424 | /* DDI E can't be used if DDI A requires 4 lanes */ |
4f8036a2 | 15425 | if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
70ac54d0 VS |
15426 | return false; |
15427 | ||
e4abb733 | 15428 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
15429 | return false; |
15430 | ||
15431 | return true; | |
15432 | } | |
15433 | ||
8090ba8c ID |
15434 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
15435 | { | |
15436 | int pps_num; | |
15437 | int pps_idx; | |
15438 | ||
15439 | if (HAS_DDI(dev_priv)) | |
15440 | return; | |
15441 | /* | |
15442 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
15443 | * everywhere where registers can be write protected. | |
15444 | */ | |
15445 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
15446 | pps_num = 2; | |
15447 | else | |
15448 | pps_num = 1; | |
15449 | ||
15450 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
15451 | u32 val = I915_READ(PP_CONTROL(pps_idx)); | |
15452 | ||
15453 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
15454 | I915_WRITE(PP_CONTROL(pps_idx), val); | |
15455 | } | |
15456 | } | |
15457 | ||
44cb734c ID |
15458 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
15459 | { | |
15460 | if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv)) | |
15461 | dev_priv->pps_mmio_base = PCH_PPS_BASE; | |
15462 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
15463 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
15464 | else | |
15465 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
15466 | |
15467 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
15468 | } |
15469 | ||
79e53945 JB |
15470 | static void intel_setup_outputs(struct drm_device *dev) |
15471 | { | |
fac5e23e | 15472 | struct drm_i915_private *dev_priv = to_i915(dev); |
4ef69c7a | 15473 | struct intel_encoder *encoder; |
cb0953d7 | 15474 | bool dpd_is_edp = false; |
79e53945 | 15475 | |
44cb734c ID |
15476 | intel_pps_init(dev_priv); |
15477 | ||
97a824e1 ID |
15478 | /* |
15479 | * intel_edp_init_connector() depends on this completing first, to | |
15480 | * prevent the registeration of both eDP and LVDS and the incorrect | |
15481 | * sharing of the PPS. | |
15482 | */ | |
c9093354 | 15483 | intel_lvds_init(dev); |
79e53945 | 15484 | |
84b4e042 | 15485 | if (intel_crt_present(dev)) |
79935fca | 15486 | intel_crt_init(dev); |
cb0953d7 | 15487 | |
e2d214ae | 15488 | if (IS_BROXTON(dev_priv)) { |
c776eb2e VK |
15489 | /* |
15490 | * FIXME: Broxton doesn't support port detection via the | |
15491 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
15492 | * detect the ports. | |
15493 | */ | |
15494 | intel_ddi_init(dev, PORT_A); | |
15495 | intel_ddi_init(dev, PORT_B); | |
15496 | intel_ddi_init(dev, PORT_C); | |
c6c794a2 SS |
15497 | |
15498 | intel_dsi_init(dev); | |
4f8036a2 | 15499 | } else if (HAS_DDI(dev_priv)) { |
0e72a5b5 ED |
15500 | int found; |
15501 | ||
de31facd JB |
15502 | /* |
15503 | * Haswell uses DDI functions to detect digital outputs. | |
15504 | * On SKL pre-D0 the strap isn't connected, so we assume | |
15505 | * it's there. | |
15506 | */ | |
77179400 | 15507 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 15508 | /* WaIgnoreDDIAStrap: skl */ |
0853723b | 15509 | if (found || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
0e72a5b5 ED |
15510 | intel_ddi_init(dev, PORT_A); |
15511 | ||
15512 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
15513 | * register */ | |
15514 | found = I915_READ(SFUSE_STRAP); | |
15515 | ||
15516 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
15517 | intel_ddi_init(dev, PORT_B); | |
15518 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
15519 | intel_ddi_init(dev, PORT_C); | |
15520 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
15521 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
15522 | /* |
15523 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
15524 | */ | |
0853723b | 15525 | if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && |
2800e4c2 RV |
15526 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
15527 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
15528 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
15529 | intel_ddi_init(dev, PORT_E); | |
15530 | ||
6e266956 | 15531 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
cb0953d7 | 15532 | int found; |
5d8a7752 | 15533 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 | 15534 | |
646d5772 | 15535 | if (has_edp_a(dev_priv)) |
270b3042 | 15536 | intel_dp_init(dev, DP_A, PORT_A); |
cb0953d7 | 15537 | |
dc0fa718 | 15538 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 15539 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 15540 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 15541 | if (!found) |
e2debe91 | 15542 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 15543 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 15544 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
15545 | } |
15546 | ||
dc0fa718 | 15547 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 15548 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 15549 | |
dc0fa718 | 15550 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 15551 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 15552 | |
5eb08b69 | 15553 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 15554 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 15555 | |
270b3042 | 15556 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 15557 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
920a14b2 | 15558 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
22f35042 | 15559 | bool has_edp, has_port; |
457c52d8 | 15560 | |
e17ac6db VS |
15561 | /* |
15562 | * The DP_DETECTED bit is the latched state of the DDC | |
15563 | * SDA pin at boot. However since eDP doesn't require DDC | |
15564 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
15565 | * eDP ports may have been muxed to an alternate function. | |
15566 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
15567 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
15568 | * detect eDP ports. | |
22f35042 VS |
15569 | * |
15570 | * Sadly the straps seem to be missing sometimes even for HDMI | |
15571 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
15572 | * and VBT for the presence of the port. Additionally we can't | |
15573 | * trust the port type the VBT declares as we've seen at least | |
15574 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 15575 | */ |
457c52d8 | 15576 | has_edp = intel_dp_is_edp(dev, PORT_B); |
22f35042 VS |
15577 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
15578 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
457c52d8 | 15579 | has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B); |
22f35042 | 15580 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
e66eb81d | 15581 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
585a94b8 | 15582 | |
457c52d8 | 15583 | has_edp = intel_dp_is_edp(dev, PORT_C); |
22f35042 VS |
15584 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
15585 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
457c52d8 | 15586 | has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C); |
22f35042 | 15587 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
e66eb81d | 15588 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
19c03924 | 15589 | |
920a14b2 | 15590 | if (IS_CHERRYVIEW(dev_priv)) { |
22f35042 VS |
15591 | /* |
15592 | * eDP not supported on port D, | |
15593 | * so no need to worry about it | |
15594 | */ | |
15595 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
15596 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
e66eb81d | 15597 | intel_dp_init(dev, CHV_DP_D, PORT_D); |
22f35042 VS |
15598 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
15599 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
9418c1f1 VS |
15600 | } |
15601 | ||
3cfca973 | 15602 | intel_dsi_init(dev); |
5db94019 | 15603 | } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { |
27185ae1 | 15604 | bool found = false; |
7d57382e | 15605 | |
e2debe91 | 15606 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 15607 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 15608 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
9beb5fea | 15609 | if (!found && IS_G4X(dev_priv)) { |
b01f2c3a | 15610 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 15611 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 15612 | } |
27185ae1 | 15613 | |
9beb5fea | 15614 | if (!found && IS_G4X(dev_priv)) |
ab9d7c30 | 15615 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 15616 | } |
13520b05 KH |
15617 | |
15618 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 15619 | |
e2debe91 | 15620 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 15621 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 15622 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 15623 | } |
27185ae1 | 15624 | |
e2debe91 | 15625 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 15626 | |
9beb5fea | 15627 | if (IS_G4X(dev_priv)) { |
b01f2c3a | 15628 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 15629 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 15630 | } |
9beb5fea | 15631 | if (IS_G4X(dev_priv)) |
ab9d7c30 | 15632 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 15633 | } |
27185ae1 | 15634 | |
9beb5fea | 15635 | if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 15636 | intel_dp_init(dev, DP_D, PORT_D); |
5db94019 | 15637 | } else if (IS_GEN2(dev_priv)) |
79e53945 JB |
15638 | intel_dvo_init(dev); |
15639 | ||
103a196f | 15640 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
15641 | intel_tv_init(dev); |
15642 | ||
0bc12bcb | 15643 | intel_psr_init(dev); |
7c8f8a70 | 15644 | |
b2784e15 | 15645 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
15646 | encoder->base.possible_crtcs = encoder->crtc_mask; |
15647 | encoder->base.possible_clones = | |
66a9278e | 15648 | intel_encoder_clones(encoder); |
79e53945 | 15649 | } |
47356eb6 | 15650 | |
dde86e2d | 15651 | intel_init_pch_refclk(dev); |
270b3042 DV |
15652 | |
15653 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
15654 | } |
15655 | ||
15656 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
15657 | { | |
60a5ca01 | 15658 | struct drm_device *dev = fb->dev; |
79e53945 | 15659 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 15660 | |
ef2d633e | 15661 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 15662 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 15663 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
f8c417cd | 15664 | i915_gem_object_put(intel_fb->obj); |
60a5ca01 | 15665 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
15666 | kfree(intel_fb); |
15667 | } | |
15668 | ||
15669 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 15670 | struct drm_file *file, |
79e53945 JB |
15671 | unsigned int *handle) |
15672 | { | |
15673 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 15674 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 15675 | |
cc917ab4 CW |
15676 | if (obj->userptr.mm) { |
15677 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
15678 | return -EINVAL; | |
15679 | } | |
15680 | ||
05394f39 | 15681 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
15682 | } |
15683 | ||
86c98588 RV |
15684 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
15685 | struct drm_file *file, | |
15686 | unsigned flags, unsigned color, | |
15687 | struct drm_clip_rect *clips, | |
15688 | unsigned num_clips) | |
15689 | { | |
15690 | struct drm_device *dev = fb->dev; | |
15691 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
15692 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
15693 | ||
15694 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 15695 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
15696 | mutex_unlock(&dev->struct_mutex); |
15697 | ||
15698 | return 0; | |
15699 | } | |
15700 | ||
79e53945 JB |
15701 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
15702 | .destroy = intel_user_framebuffer_destroy, | |
15703 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 15704 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
15705 | }; |
15706 | ||
b321803d | 15707 | static |
920a14b2 TU |
15708 | u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv, |
15709 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 15710 | { |
920a14b2 | 15711 | u32 gen = INTEL_INFO(dev_priv)->gen; |
b321803d DL |
15712 | |
15713 | if (gen >= 9) { | |
ac484963 VS |
15714 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
15715 | ||
b321803d DL |
15716 | /* "The stride in bytes must not exceed the of the size of 8K |
15717 | * pixels and 32K bytes." | |
15718 | */ | |
ac484963 | 15719 | return min(8192 * cpp, 32768); |
920a14b2 TU |
15720 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev_priv) && |
15721 | !IS_CHERRYVIEW(dev_priv)) { | |
b321803d DL |
15722 | return 32*1024; |
15723 | } else if (gen >= 4) { | |
15724 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
15725 | return 16*1024; | |
15726 | else | |
15727 | return 32*1024; | |
15728 | } else if (gen >= 3) { | |
15729 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
15730 | return 8*1024; | |
15731 | else | |
15732 | return 16*1024; | |
15733 | } else { | |
15734 | /* XXX DSPC is limited to 4k tiled */ | |
15735 | return 8*1024; | |
15736 | } | |
15737 | } | |
15738 | ||
b5ea642a DV |
15739 | static int intel_framebuffer_init(struct drm_device *dev, |
15740 | struct intel_framebuffer *intel_fb, | |
15741 | struct drm_mode_fb_cmd2 *mode_cmd, | |
15742 | struct drm_i915_gem_object *obj) | |
79e53945 | 15743 | { |
7b49f948 | 15744 | struct drm_i915_private *dev_priv = to_i915(dev); |
c2ff7370 | 15745 | unsigned int tiling = i915_gem_object_get_tiling(obj); |
79e53945 | 15746 | int ret; |
b321803d | 15747 | u32 pitch_limit, stride_alignment; |
d3828147 | 15748 | char *format_name; |
79e53945 | 15749 | |
dd4916c5 DV |
15750 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
15751 | ||
2a80eada | 15752 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
c2ff7370 VS |
15753 | /* |
15754 | * If there's a fence, enforce that | |
15755 | * the fb modifier and tiling mode match. | |
15756 | */ | |
15757 | if (tiling != I915_TILING_NONE && | |
15758 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
2a80eada DV |
15759 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); |
15760 | return -EINVAL; | |
15761 | } | |
15762 | } else { | |
c2ff7370 | 15763 | if (tiling == I915_TILING_X) { |
2a80eada | 15764 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
c2ff7370 | 15765 | } else if (tiling == I915_TILING_Y) { |
2a80eada DV |
15766 | DRM_DEBUG("No Y tiling for legacy addfb\n"); |
15767 | return -EINVAL; | |
15768 | } | |
15769 | } | |
15770 | ||
9a8f0a12 TU |
15771 | /* Passed in modifier sanity checking. */ |
15772 | switch (mode_cmd->modifier[0]) { | |
15773 | case I915_FORMAT_MOD_Y_TILED: | |
15774 | case I915_FORMAT_MOD_Yf_TILED: | |
15775 | if (INTEL_INFO(dev)->gen < 9) { | |
15776 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
15777 | mode_cmd->modifier[0]); | |
15778 | return -EINVAL; | |
15779 | } | |
15780 | case DRM_FORMAT_MOD_NONE: | |
15781 | case I915_FORMAT_MOD_X_TILED: | |
15782 | break; | |
15783 | default: | |
c0f40428 JB |
15784 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
15785 | mode_cmd->modifier[0]); | |
57cd6508 | 15786 | return -EINVAL; |
c16ed4be | 15787 | } |
57cd6508 | 15788 | |
c2ff7370 VS |
15789 | /* |
15790 | * gen2/3 display engine uses the fence if present, | |
15791 | * so the tiling mode must match the fb modifier exactly. | |
15792 | */ | |
15793 | if (INTEL_INFO(dev_priv)->gen < 4 && | |
15794 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
15795 | DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n"); | |
15796 | return -EINVAL; | |
15797 | } | |
15798 | ||
7b49f948 VS |
15799 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
15800 | mode_cmd->modifier[0], | |
b321803d DL |
15801 | mode_cmd->pixel_format); |
15802 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
15803 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
15804 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 15805 | return -EINVAL; |
c16ed4be | 15806 | } |
57cd6508 | 15807 | |
920a14b2 | 15808 | pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0], |
b321803d | 15809 | mode_cmd->pixel_format); |
a35cdaa0 | 15810 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
15811 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
15812 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 15813 | "tiled" : "linear", |
a35cdaa0 | 15814 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 15815 | return -EINVAL; |
c16ed4be | 15816 | } |
5d7bd705 | 15817 | |
c2ff7370 VS |
15818 | /* |
15819 | * If there's a fence, enforce that | |
15820 | * the fb pitch and fence stride match. | |
15821 | */ | |
15822 | if (tiling != I915_TILING_NONE && | |
3e510a8e | 15823 | mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) { |
c16ed4be | 15824 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
3e510a8e CW |
15825 | mode_cmd->pitches[0], |
15826 | i915_gem_object_get_stride(obj)); | |
5d7bd705 | 15827 | return -EINVAL; |
c16ed4be | 15828 | } |
5d7bd705 | 15829 | |
57779d06 | 15830 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 15831 | switch (mode_cmd->pixel_format) { |
57779d06 | 15832 | case DRM_FORMAT_C8: |
04b3924d VS |
15833 | case DRM_FORMAT_RGB565: |
15834 | case DRM_FORMAT_XRGB8888: | |
15835 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
15836 | break; |
15837 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 15838 | if (INTEL_INFO(dev)->gen > 3) { |
90844f00 EE |
15839 | format_name = drm_get_format_name(mode_cmd->pixel_format); |
15840 | DRM_DEBUG("unsupported pixel format: %s\n", format_name); | |
15841 | kfree(format_name); | |
57779d06 | 15842 | return -EINVAL; |
c16ed4be | 15843 | } |
57779d06 | 15844 | break; |
57779d06 | 15845 | case DRM_FORMAT_ABGR8888: |
920a14b2 | 15846 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
666a4537 | 15847 | INTEL_INFO(dev)->gen < 9) { |
90844f00 EE |
15848 | format_name = drm_get_format_name(mode_cmd->pixel_format); |
15849 | DRM_DEBUG("unsupported pixel format: %s\n", format_name); | |
15850 | kfree(format_name); | |
6c0fd451 DL |
15851 | return -EINVAL; |
15852 | } | |
15853 | break; | |
15854 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 15855 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 15856 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 15857 | if (INTEL_INFO(dev)->gen < 4) { |
90844f00 EE |
15858 | format_name = drm_get_format_name(mode_cmd->pixel_format); |
15859 | DRM_DEBUG("unsupported pixel format: %s\n", format_name); | |
15860 | kfree(format_name); | |
57779d06 | 15861 | return -EINVAL; |
c16ed4be | 15862 | } |
b5626747 | 15863 | break; |
7531208b | 15864 | case DRM_FORMAT_ABGR2101010: |
920a14b2 | 15865 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
90844f00 EE |
15866 | format_name = drm_get_format_name(mode_cmd->pixel_format); |
15867 | DRM_DEBUG("unsupported pixel format: %s\n", format_name); | |
15868 | kfree(format_name); | |
7531208b DL |
15869 | return -EINVAL; |
15870 | } | |
15871 | break; | |
04b3924d VS |
15872 | case DRM_FORMAT_YUYV: |
15873 | case DRM_FORMAT_UYVY: | |
15874 | case DRM_FORMAT_YVYU: | |
15875 | case DRM_FORMAT_VYUY: | |
c16ed4be | 15876 | if (INTEL_INFO(dev)->gen < 5) { |
90844f00 EE |
15877 | format_name = drm_get_format_name(mode_cmd->pixel_format); |
15878 | DRM_DEBUG("unsupported pixel format: %s\n", format_name); | |
15879 | kfree(format_name); | |
57779d06 | 15880 | return -EINVAL; |
c16ed4be | 15881 | } |
57cd6508 CW |
15882 | break; |
15883 | default: | |
90844f00 EE |
15884 | format_name = drm_get_format_name(mode_cmd->pixel_format); |
15885 | DRM_DEBUG("unsupported pixel format: %s\n", format_name); | |
15886 | kfree(format_name); | |
57cd6508 CW |
15887 | return -EINVAL; |
15888 | } | |
15889 | ||
90f9a336 VS |
15890 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
15891 | if (mode_cmd->offsets[0] != 0) | |
15892 | return -EINVAL; | |
15893 | ||
c7d73f6a DV |
15894 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
15895 | intel_fb->obj = obj; | |
15896 | ||
6687c906 VS |
15897 | ret = intel_fill_fb_info(dev_priv, &intel_fb->base); |
15898 | if (ret) | |
15899 | return ret; | |
2d7a215f | 15900 | |
79e53945 JB |
15901 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
15902 | if (ret) { | |
15903 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
15904 | return ret; | |
15905 | } | |
15906 | ||
0b05e1e0 VS |
15907 | intel_fb->obj->framebuffer_references++; |
15908 | ||
79e53945 JB |
15909 | return 0; |
15910 | } | |
15911 | ||
79e53945 JB |
15912 | static struct drm_framebuffer * |
15913 | intel_user_framebuffer_create(struct drm_device *dev, | |
15914 | struct drm_file *filp, | |
1eb83451 | 15915 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 15916 | { |
dcb1394e | 15917 | struct drm_framebuffer *fb; |
05394f39 | 15918 | struct drm_i915_gem_object *obj; |
76dc3769 | 15919 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 15920 | |
03ac0642 CW |
15921 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
15922 | if (!obj) | |
cce13ff7 | 15923 | return ERR_PTR(-ENOENT); |
79e53945 | 15924 | |
92907cbb | 15925 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e | 15926 | if (IS_ERR(fb)) |
f0cd5182 | 15927 | i915_gem_object_put(obj); |
dcb1394e LW |
15928 | |
15929 | return fb; | |
79e53945 JB |
15930 | } |
15931 | ||
79e53945 | 15932 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 15933 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 15934 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
15935 | .atomic_check = intel_atomic_check, |
15936 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
15937 | .atomic_state_alloc = intel_atomic_state_alloc, |
15938 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
15939 | }; |
15940 | ||
88212941 ID |
15941 | /** |
15942 | * intel_init_display_hooks - initialize the display modesetting hooks | |
15943 | * @dev_priv: device private | |
15944 | */ | |
15945 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 15946 | { |
88212941 | 15947 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 15948 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15949 | dev_priv->display.get_initial_plane_config = |
15950 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
15951 | dev_priv->display.crtc_compute_clock = |
15952 | haswell_crtc_compute_clock; | |
15953 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
15954 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 15955 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 15956 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
15957 | dev_priv->display.get_initial_plane_config = |
15958 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
15959 | dev_priv->display.crtc_compute_clock = |
15960 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
15961 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
15962 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 15963 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 15964 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
15965 | dev_priv->display.get_initial_plane_config = |
15966 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
15967 | dev_priv->display.crtc_compute_clock = |
15968 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
15969 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
15970 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 15971 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 15972 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15973 | dev_priv->display.get_initial_plane_config = |
15974 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
15975 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
15976 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
15977 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
15978 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
15979 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15980 | dev_priv->display.get_initial_plane_config = | |
15981 | i9xx_get_initial_plane_config; | |
15982 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
15983 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
15984 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
15985 | } else if (IS_G4X(dev_priv)) { |
15986 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15987 | dev_priv->display.get_initial_plane_config = | |
15988 | i9xx_get_initial_plane_config; | |
15989 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
15990 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15991 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
15992 | } else if (IS_PINEVIEW(dev_priv)) { |
15993 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
15994 | dev_priv->display.get_initial_plane_config = | |
15995 | i9xx_get_initial_plane_config; | |
15996 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
15997 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
15998 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 15999 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 16000 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
16001 | dev_priv->display.get_initial_plane_config = |
16002 | i9xx_get_initial_plane_config; | |
d6dfee7a | 16003 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
16004 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
16005 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
16006 | } else { |
16007 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
16008 | dev_priv->display.get_initial_plane_config = | |
16009 | i9xx_get_initial_plane_config; | |
16010 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
16011 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
16012 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 16013 | } |
e70236a8 | 16014 | |
e70236a8 | 16015 | /* Returns the core display clock speed */ |
88212941 | 16016 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
1652d19e VS |
16017 | dev_priv->display.get_display_clock_speed = |
16018 | skylake_get_display_clock_speed; | |
88212941 | 16019 | else if (IS_BROXTON(dev_priv)) |
acd3f3d3 BP |
16020 | dev_priv->display.get_display_clock_speed = |
16021 | broxton_get_display_clock_speed; | |
88212941 | 16022 | else if (IS_BROADWELL(dev_priv)) |
1652d19e VS |
16023 | dev_priv->display.get_display_clock_speed = |
16024 | broadwell_get_display_clock_speed; | |
88212941 | 16025 | else if (IS_HASWELL(dev_priv)) |
1652d19e VS |
16026 | dev_priv->display.get_display_clock_speed = |
16027 | haswell_get_display_clock_speed; | |
88212941 | 16028 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
25eb05fc JB |
16029 | dev_priv->display.get_display_clock_speed = |
16030 | valleyview_get_display_clock_speed; | |
88212941 | 16031 | else if (IS_GEN5(dev_priv)) |
b37a6434 VS |
16032 | dev_priv->display.get_display_clock_speed = |
16033 | ilk_get_display_clock_speed; | |
88212941 ID |
16034 | else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) || |
16035 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
e70236a8 JB |
16036 | dev_priv->display.get_display_clock_speed = |
16037 | i945_get_display_clock_speed; | |
88212941 | 16038 | else if (IS_GM45(dev_priv)) |
34edce2f VS |
16039 | dev_priv->display.get_display_clock_speed = |
16040 | gm45_get_display_clock_speed; | |
88212941 | 16041 | else if (IS_CRESTLINE(dev_priv)) |
34edce2f VS |
16042 | dev_priv->display.get_display_clock_speed = |
16043 | i965gm_get_display_clock_speed; | |
88212941 | 16044 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f VS |
16045 | dev_priv->display.get_display_clock_speed = |
16046 | pnv_get_display_clock_speed; | |
88212941 | 16047 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) |
34edce2f VS |
16048 | dev_priv->display.get_display_clock_speed = |
16049 | g33_get_display_clock_speed; | |
88212941 | 16050 | else if (IS_I915G(dev_priv)) |
e70236a8 JB |
16051 | dev_priv->display.get_display_clock_speed = |
16052 | i915_get_display_clock_speed; | |
88212941 | 16053 | else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) |
e70236a8 JB |
16054 | dev_priv->display.get_display_clock_speed = |
16055 | i9xx_misc_get_display_clock_speed; | |
88212941 | 16056 | else if (IS_I915GM(dev_priv)) |
e70236a8 JB |
16057 | dev_priv->display.get_display_clock_speed = |
16058 | i915gm_get_display_clock_speed; | |
88212941 | 16059 | else if (IS_I865G(dev_priv)) |
e70236a8 JB |
16060 | dev_priv->display.get_display_clock_speed = |
16061 | i865_get_display_clock_speed; | |
88212941 | 16062 | else if (IS_I85X(dev_priv)) |
e70236a8 | 16063 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 16064 | i85x_get_display_clock_speed; |
623e01e5 | 16065 | else { /* 830 */ |
88212941 | 16066 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
e70236a8 JB |
16067 | dev_priv->display.get_display_clock_speed = |
16068 | i830_get_display_clock_speed; | |
623e01e5 | 16069 | } |
e70236a8 | 16070 | |
88212941 | 16071 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 16072 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 16073 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 16074 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 16075 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
16076 | /* FIXME: detect B0+ stepping and use auto training */ |
16077 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 16078 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 16079 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
16080 | } |
16081 | ||
16082 | if (IS_BROADWELL(dev_priv)) { | |
16083 | dev_priv->display.modeset_commit_cdclk = | |
16084 | broadwell_modeset_commit_cdclk; | |
16085 | dev_priv->display.modeset_calc_cdclk = | |
16086 | broadwell_modeset_calc_cdclk; | |
88212941 | 16087 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
27c329ed ML |
16088 | dev_priv->display.modeset_commit_cdclk = |
16089 | valleyview_modeset_commit_cdclk; | |
16090 | dev_priv->display.modeset_calc_cdclk = | |
16091 | valleyview_modeset_calc_cdclk; | |
88212941 | 16092 | } else if (IS_BROXTON(dev_priv)) { |
27c329ed | 16093 | dev_priv->display.modeset_commit_cdclk = |
324513c0 | 16094 | bxt_modeset_commit_cdclk; |
27c329ed | 16095 | dev_priv->display.modeset_calc_cdclk = |
324513c0 | 16096 | bxt_modeset_calc_cdclk; |
c89e39f3 CT |
16097 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
16098 | dev_priv->display.modeset_commit_cdclk = | |
16099 | skl_modeset_commit_cdclk; | |
16100 | dev_priv->display.modeset_calc_cdclk = | |
16101 | skl_modeset_calc_cdclk; | |
e70236a8 | 16102 | } |
5a21b665 | 16103 | |
27082493 L |
16104 | if (dev_priv->info.gen >= 9) |
16105 | dev_priv->display.update_crtcs = skl_update_crtcs; | |
16106 | else | |
16107 | dev_priv->display.update_crtcs = intel_update_crtcs; | |
16108 | ||
5a21b665 DV |
16109 | switch (INTEL_INFO(dev_priv)->gen) { |
16110 | case 2: | |
16111 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
16112 | break; | |
16113 | ||
16114 | case 3: | |
16115 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
16116 | break; | |
16117 | ||
16118 | case 4: | |
16119 | case 5: | |
16120 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
16121 | break; | |
16122 | ||
16123 | case 6: | |
16124 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
16125 | break; | |
16126 | case 7: | |
16127 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ | |
16128 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
16129 | break; | |
16130 | case 9: | |
16131 | /* Drop through - unsupported since execlist only. */ | |
16132 | default: | |
16133 | /* Default just returns -ENODEV to indicate unsupported */ | |
16134 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
16135 | } | |
e70236a8 JB |
16136 | } |
16137 | ||
b690e96c JB |
16138 | /* |
16139 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
16140 | * resume, or other times. This quirk makes sure that's the case for | |
16141 | * affected systems. | |
16142 | */ | |
0206e353 | 16143 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c | 16144 | { |
fac5e23e | 16145 | struct drm_i915_private *dev_priv = to_i915(dev); |
b690e96c JB |
16146 | |
16147 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 16148 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
16149 | } |
16150 | ||
b6b5d049 VS |
16151 | static void quirk_pipeb_force(struct drm_device *dev) |
16152 | { | |
fac5e23e | 16153 | struct drm_i915_private *dev_priv = to_i915(dev); |
b6b5d049 VS |
16154 | |
16155 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
16156 | DRM_INFO("applying pipe b force quirk\n"); | |
16157 | } | |
16158 | ||
435793df KP |
16159 | /* |
16160 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
16161 | */ | |
16162 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
16163 | { | |
fac5e23e | 16164 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 16165 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 16166 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
16167 | } |
16168 | ||
4dca20ef | 16169 | /* |
5a15ab5b CE |
16170 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
16171 | * brightness value | |
4dca20ef CE |
16172 | */ |
16173 | static void quirk_invert_brightness(struct drm_device *dev) | |
16174 | { | |
fac5e23e | 16175 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 16176 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 16177 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
16178 | } |
16179 | ||
9c72cc6f SD |
16180 | /* Some VBT's incorrectly indicate no backlight is present */ |
16181 | static void quirk_backlight_present(struct drm_device *dev) | |
16182 | { | |
fac5e23e | 16183 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
16184 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
16185 | DRM_INFO("applying backlight present quirk\n"); | |
16186 | } | |
16187 | ||
b690e96c JB |
16188 | struct intel_quirk { |
16189 | int device; | |
16190 | int subsystem_vendor; | |
16191 | int subsystem_device; | |
16192 | void (*hook)(struct drm_device *dev); | |
16193 | }; | |
16194 | ||
5f85f176 EE |
16195 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
16196 | struct intel_dmi_quirk { | |
16197 | void (*hook)(struct drm_device *dev); | |
16198 | const struct dmi_system_id (*dmi_id_list)[]; | |
16199 | }; | |
16200 | ||
16201 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
16202 | { | |
16203 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
16204 | return 1; | |
16205 | } | |
16206 | ||
16207 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
16208 | { | |
16209 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
16210 | { | |
16211 | .callback = intel_dmi_reverse_brightness, | |
16212 | .ident = "NCR Corporation", | |
16213 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
16214 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
16215 | }, | |
16216 | }, | |
16217 | { } /* terminating entry */ | |
16218 | }, | |
16219 | .hook = quirk_invert_brightness, | |
16220 | }, | |
16221 | }; | |
16222 | ||
c43b5634 | 16223 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
16224 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
16225 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
16226 | ||
b690e96c JB |
16227 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
16228 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
16229 | ||
5f080c0f VS |
16230 | /* 830 needs to leave pipe A & dpll A up */ |
16231 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
16232 | ||
b6b5d049 VS |
16233 | /* 830 needs to leave pipe B & dpll B up */ |
16234 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
16235 | ||
435793df KP |
16236 | /* Lenovo U160 cannot use SSC on LVDS */ |
16237 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
16238 | |
16239 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
16240 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 16241 | |
be505f64 AH |
16242 | /* Acer Aspire 5734Z must invert backlight brightness */ |
16243 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
16244 | ||
16245 | /* Acer/eMachines G725 */ | |
16246 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
16247 | ||
16248 | /* Acer/eMachines e725 */ | |
16249 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
16250 | ||
16251 | /* Acer/Packard Bell NCL20 */ | |
16252 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
16253 | ||
16254 | /* Acer Aspire 4736Z */ | |
16255 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
16256 | |
16257 | /* Acer Aspire 5336 */ | |
16258 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
16259 | |
16260 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
16261 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 16262 | |
dfb3d47b SD |
16263 | /* Acer C720 Chromebook (Core i3 4005U) */ |
16264 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
16265 | ||
b2a9601c | 16266 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
16267 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
16268 | ||
1b9448b0 JN |
16269 | /* Apple Macbook 4,1 */ |
16270 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
16271 | ||
d4967d8c SD |
16272 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
16273 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
16274 | |
16275 | /* HP Chromebook 14 (Celeron 2955U) */ | |
16276 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
16277 | |
16278 | /* Dell Chromebook 11 */ | |
16279 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
16280 | |
16281 | /* Dell Chromebook 11 (2015 version) */ | |
16282 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
16283 | }; |
16284 | ||
16285 | static void intel_init_quirks(struct drm_device *dev) | |
16286 | { | |
16287 | struct pci_dev *d = dev->pdev; | |
16288 | int i; | |
16289 | ||
16290 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
16291 | struct intel_quirk *q = &intel_quirks[i]; | |
16292 | ||
16293 | if (d->device == q->device && | |
16294 | (d->subsystem_vendor == q->subsystem_vendor || | |
16295 | q->subsystem_vendor == PCI_ANY_ID) && | |
16296 | (d->subsystem_device == q->subsystem_device || | |
16297 | q->subsystem_device == PCI_ANY_ID)) | |
16298 | q->hook(dev); | |
16299 | } | |
5f85f176 EE |
16300 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
16301 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
16302 | intel_dmi_quirks[i].hook(dev); | |
16303 | } | |
b690e96c JB |
16304 | } |
16305 | ||
9cce37f4 JB |
16306 | /* Disable the VGA plane that we never use */ |
16307 | static void i915_disable_vga(struct drm_device *dev) | |
16308 | { | |
fac5e23e | 16309 | struct drm_i915_private *dev_priv = to_i915(dev); |
52a05c30 | 16310 | struct pci_dev *pdev = dev_priv->drm.pdev; |
9cce37f4 | 16311 | u8 sr1; |
920a14b2 | 16312 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
9cce37f4 | 16313 | |
2b37c616 | 16314 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
52a05c30 | 16315 | vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 16316 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
16317 | sr1 = inb(VGA_SR_DATA); |
16318 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
52a05c30 | 16319 | vga_put(pdev, VGA_RSRC_LEGACY_IO); |
9cce37f4 JB |
16320 | udelay(300); |
16321 | ||
01f5a626 | 16322 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
16323 | POSTING_READ(vga_reg); |
16324 | } | |
16325 | ||
f817586c DV |
16326 | void intel_modeset_init_hw(struct drm_device *dev) |
16327 | { | |
fac5e23e | 16328 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 16329 | |
4c75b940 | 16330 | intel_update_cdclk(dev_priv); |
1a617b77 ML |
16331 | |
16332 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
16333 | ||
46f16e63 | 16334 | intel_init_clock_gating(dev_priv); |
f817586c DV |
16335 | } |
16336 | ||
d93c0372 MR |
16337 | /* |
16338 | * Calculate what we think the watermarks should be for the state we've read | |
16339 | * out of the hardware and then immediately program those watermarks so that | |
16340 | * we ensure the hardware settings match our internal state. | |
16341 | * | |
16342 | * We can calculate what we think WM's should be by creating a duplicate of the | |
16343 | * current state (which was constructed during hardware readout) and running it | |
16344 | * through the atomic check code to calculate new watermark values in the | |
16345 | * state object. | |
16346 | */ | |
16347 | static void sanitize_watermarks(struct drm_device *dev) | |
16348 | { | |
16349 | struct drm_i915_private *dev_priv = to_i915(dev); | |
16350 | struct drm_atomic_state *state; | |
16351 | struct drm_crtc *crtc; | |
16352 | struct drm_crtc_state *cstate; | |
16353 | struct drm_modeset_acquire_ctx ctx; | |
16354 | int ret; | |
16355 | int i; | |
16356 | ||
16357 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 16358 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
16359 | return; |
16360 | ||
16361 | /* | |
16362 | * We need to hold connection_mutex before calling duplicate_state so | |
16363 | * that the connector loop is protected. | |
16364 | */ | |
16365 | drm_modeset_acquire_init(&ctx, 0); | |
16366 | retry: | |
0cd1262d | 16367 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
16368 | if (ret == -EDEADLK) { |
16369 | drm_modeset_backoff(&ctx); | |
16370 | goto retry; | |
16371 | } else if (WARN_ON(ret)) { | |
0cd1262d | 16372 | goto fail; |
d93c0372 MR |
16373 | } |
16374 | ||
16375 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
16376 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 16377 | goto fail; |
d93c0372 | 16378 | |
ed4a6a7c MR |
16379 | /* |
16380 | * Hardware readout is the only time we don't want to calculate | |
16381 | * intermediate watermarks (since we don't trust the current | |
16382 | * watermarks). | |
16383 | */ | |
16384 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
16385 | ||
d93c0372 MR |
16386 | ret = intel_atomic_check(dev, state); |
16387 | if (ret) { | |
16388 | /* | |
16389 | * If we fail here, it means that the hardware appears to be | |
16390 | * programmed in a way that shouldn't be possible, given our | |
16391 | * understanding of watermark requirements. This might mean a | |
16392 | * mistake in the hardware readout code or a mistake in the | |
16393 | * watermark calculations for a given platform. Raise a WARN | |
16394 | * so that this is noticeable. | |
16395 | * | |
16396 | * If this actually happens, we'll have to just leave the | |
16397 | * BIOS-programmed watermarks untouched and hope for the best. | |
16398 | */ | |
16399 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
b9a1b717 | 16400 | goto put_state; |
d93c0372 MR |
16401 | } |
16402 | ||
16403 | /* Write calculated watermark values back */ | |
d93c0372 MR |
16404 | for_each_crtc_in_state(state, crtc, cstate, i) { |
16405 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
16406 | ||
ed4a6a7c MR |
16407 | cs->wm.need_postvbl_update = true; |
16408 | dev_priv->display.optimize_watermarks(cs); | |
d93c0372 MR |
16409 | } |
16410 | ||
b9a1b717 | 16411 | put_state: |
0853695c | 16412 | drm_atomic_state_put(state); |
0cd1262d | 16413 | fail: |
d93c0372 MR |
16414 | drm_modeset_drop_locks(&ctx); |
16415 | drm_modeset_acquire_fini(&ctx); | |
16416 | } | |
16417 | ||
b079bd17 | 16418 | int intel_modeset_init(struct drm_device *dev) |
79e53945 | 16419 | { |
72e96d64 JL |
16420 | struct drm_i915_private *dev_priv = to_i915(dev); |
16421 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
8cc87b75 | 16422 | enum pipe pipe; |
46f297fb | 16423 | struct intel_crtc *crtc; |
79e53945 JB |
16424 | |
16425 | drm_mode_config_init(dev); | |
16426 | ||
16427 | dev->mode_config.min_width = 0; | |
16428 | dev->mode_config.min_height = 0; | |
16429 | ||
019d96cb DA |
16430 | dev->mode_config.preferred_depth = 24; |
16431 | dev->mode_config.prefer_shadow = 1; | |
16432 | ||
25bab385 TU |
16433 | dev->mode_config.allow_fb_modifiers = true; |
16434 | ||
e6ecefaa | 16435 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 16436 | |
b690e96c JB |
16437 | intel_init_quirks(dev); |
16438 | ||
62d75df7 | 16439 | intel_init_pm(dev_priv); |
1fa61106 | 16440 | |
e3c74757 | 16441 | if (INTEL_INFO(dev)->num_pipes == 0) |
b079bd17 | 16442 | return 0; |
e3c74757 | 16443 | |
69f92f67 LW |
16444 | /* |
16445 | * There may be no VBT; and if the BIOS enabled SSC we can | |
16446 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
16447 | * BIOS isn't using it, don't assume it will work even if the VBT | |
16448 | * indicates as much. | |
16449 | */ | |
6e266956 | 16450 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
69f92f67 LW |
16451 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
16452 | DREF_SSC1_ENABLE); | |
16453 | ||
16454 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
16455 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
16456 | bios_lvds_use_ssc ? "en" : "dis", | |
16457 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
16458 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
16459 | } | |
16460 | } | |
16461 | ||
5db94019 | 16462 | if (IS_GEN2(dev_priv)) { |
a6c45cf0 CW |
16463 | dev->mode_config.max_width = 2048; |
16464 | dev->mode_config.max_height = 2048; | |
5db94019 | 16465 | } else if (IS_GEN3(dev_priv)) { |
5e4d6fa7 KP |
16466 | dev->mode_config.max_width = 4096; |
16467 | dev->mode_config.max_height = 4096; | |
79e53945 | 16468 | } else { |
a6c45cf0 CW |
16469 | dev->mode_config.max_width = 8192; |
16470 | dev->mode_config.max_height = 8192; | |
79e53945 | 16471 | } |
068be561 | 16472 | |
50a0bc90 TU |
16473 | if (IS_845G(dev_priv) || IS_I865G(dev_priv)) { |
16474 | dev->mode_config.cursor_width = IS_845G(dev_priv) ? 64 : 512; | |
dc41c154 | 16475 | dev->mode_config.cursor_height = 1023; |
5db94019 | 16476 | } else if (IS_GEN2(dev_priv)) { |
068be561 DL |
16477 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
16478 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
16479 | } else { | |
16480 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
16481 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
16482 | } | |
16483 | ||
72e96d64 | 16484 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 16485 | |
28c97730 | 16486 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
16487 | INTEL_INFO(dev)->num_pipes, |
16488 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 16489 | |
055e393f | 16490 | for_each_pipe(dev_priv, pipe) { |
b079bd17 VS |
16491 | int ret; |
16492 | ||
5ab0d85b | 16493 | ret = intel_crtc_init(dev_priv, pipe); |
b079bd17 VS |
16494 | if (ret) { |
16495 | drm_mode_config_cleanup(dev); | |
16496 | return ret; | |
16497 | } | |
79e53945 JB |
16498 | } |
16499 | ||
bfa7df01 | 16500 | intel_update_czclk(dev_priv); |
4c75b940 | 16501 | intel_update_cdclk(dev_priv); |
bfa7df01 | 16502 | |
e72f9fbf | 16503 | intel_shared_dpll_init(dev); |
ee7b9f93 | 16504 | |
b2045352 | 16505 | if (dev_priv->max_cdclk_freq == 0) |
4c75b940 | 16506 | intel_update_max_cdclk(dev_priv); |
b2045352 | 16507 | |
9cce37f4 JB |
16508 | /* Just disable it once at startup */ |
16509 | i915_disable_vga(dev); | |
79e53945 | 16510 | intel_setup_outputs(dev); |
11be49eb | 16511 | |
6e9f798d | 16512 | drm_modeset_lock_all(dev); |
043e9bda | 16513 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 16514 | drm_modeset_unlock_all(dev); |
46f297fb | 16515 | |
d3fcc808 | 16516 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
16517 | struct intel_initial_plane_config plane_config = {}; |
16518 | ||
46f297fb JB |
16519 | if (!crtc->active) |
16520 | continue; | |
16521 | ||
46f297fb | 16522 | /* |
46f297fb JB |
16523 | * Note that reserving the BIOS fb up front prevents us |
16524 | * from stuffing other stolen allocations like the ring | |
16525 | * on top. This prevents some ugliness at boot time, and | |
16526 | * can even allow for smooth boot transitions if the BIOS | |
16527 | * fb is large enough for the active pipe configuration. | |
16528 | */ | |
eeebeac5 ML |
16529 | dev_priv->display.get_initial_plane_config(crtc, |
16530 | &plane_config); | |
16531 | ||
16532 | /* | |
16533 | * If the fb is shared between multiple heads, we'll | |
16534 | * just get the first one. | |
16535 | */ | |
16536 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 16537 | } |
d93c0372 MR |
16538 | |
16539 | /* | |
16540 | * Make sure hardware watermarks really match the state we read out. | |
16541 | * Note that we need to do this after reconstructing the BIOS fb's | |
16542 | * since the watermark calculation done here will use pstate->fb. | |
16543 | */ | |
16544 | sanitize_watermarks(dev); | |
b079bd17 VS |
16545 | |
16546 | return 0; | |
2c7111db CW |
16547 | } |
16548 | ||
7fad798e DV |
16549 | static void intel_enable_pipe_a(struct drm_device *dev) |
16550 | { | |
16551 | struct intel_connector *connector; | |
16552 | struct drm_connector *crt = NULL; | |
16553 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 16554 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
16555 | |
16556 | /* We can't just switch on the pipe A, we need to set things up with a | |
16557 | * proper mode and output configuration. As a gross hack, enable pipe A | |
16558 | * by enabling the load detect pipe once. */ | |
3a3371ff | 16559 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
16560 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
16561 | crt = &connector->base; | |
16562 | break; | |
16563 | } | |
16564 | } | |
16565 | ||
16566 | if (!crt) | |
16567 | return; | |
16568 | ||
208bf9fd | 16569 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 16570 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
16571 | } |
16572 | ||
fa555837 DV |
16573 | static bool |
16574 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
16575 | { | |
7eb552ae | 16576 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 16577 | struct drm_i915_private *dev_priv = to_i915(dev); |
649636ef | 16578 | u32 val; |
fa555837 | 16579 | |
7eb552ae | 16580 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
16581 | return true; |
16582 | ||
649636ef | 16583 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
16584 | |
16585 | if ((val & DISPLAY_PLANE_ENABLE) && | |
16586 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
16587 | return false; | |
16588 | ||
16589 | return true; | |
16590 | } | |
16591 | ||
02e93c35 VS |
16592 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
16593 | { | |
16594 | struct drm_device *dev = crtc->base.dev; | |
16595 | struct intel_encoder *encoder; | |
16596 | ||
16597 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
16598 | return true; | |
16599 | ||
16600 | return false; | |
16601 | } | |
16602 | ||
496b0fc3 ML |
16603 | static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) |
16604 | { | |
16605 | struct drm_device *dev = encoder->base.dev; | |
16606 | struct intel_connector *connector; | |
16607 | ||
16608 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
16609 | return connector; | |
16610 | ||
16611 | return NULL; | |
16612 | } | |
16613 | ||
a168f5b3 VS |
16614 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
16615 | enum transcoder pch_transcoder) | |
16616 | { | |
16617 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
16618 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); | |
16619 | } | |
16620 | ||
24929352 DV |
16621 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
16622 | { | |
16623 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 16624 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 16625 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 16626 | |
24929352 | 16627 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
16628 | if (!transcoder_is_dsi(cpu_transcoder)) { |
16629 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
16630 | ||
16631 | I915_WRITE(reg, | |
16632 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
16633 | } | |
24929352 | 16634 | |
d3eaf884 | 16635 | /* restore vblank interrupts to correct state */ |
9625604c | 16636 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 16637 | if (crtc->active) { |
f9cd7b88 VS |
16638 | struct intel_plane *plane; |
16639 | ||
9625604c | 16640 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
16641 | |
16642 | /* Disable everything but the primary plane */ | |
16643 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
16644 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
16645 | continue; | |
16646 | ||
16647 | plane->disable_plane(&plane->base, &crtc->base); | |
16648 | } | |
9625604c | 16649 | } |
d3eaf884 | 16650 | |
24929352 | 16651 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
16652 | * disable the crtc (and hence change the state) if it is wrong. Note |
16653 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
16654 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
16655 | bool plane; |
16656 | ||
78108b7c VS |
16657 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
16658 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
16659 | |
16660 | /* Pipe has the wrong plane attached and the plane is active. | |
16661 | * Temporarily change the plane mapping and disable everything | |
16662 | * ... */ | |
16663 | plane = crtc->plane; | |
936e71e3 | 16664 | to_intel_plane_state(crtc->base.primary->state)->base.visible = true; |
24929352 | 16665 | crtc->plane = !plane; |
b17d48e2 | 16666 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 16667 | crtc->plane = plane; |
24929352 | 16668 | } |
24929352 | 16669 | |
7fad798e DV |
16670 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
16671 | crtc->pipe == PIPE_A && !crtc->active) { | |
16672 | /* BIOS forgot to enable pipe A, this mostly happens after | |
16673 | * resume. Force-enable the pipe to fix this, the update_dpms | |
16674 | * call below we restore the pipe to the right state, but leave | |
16675 | * the required bits on. */ | |
16676 | intel_enable_pipe_a(dev); | |
16677 | } | |
16678 | ||
24929352 DV |
16679 | /* Adjust the state of the output pipe according to whether we |
16680 | * have active connectors/encoders. */ | |
842e0307 | 16681 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 16682 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 16683 | |
49cff963 | 16684 | if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) { |
4cc31489 DV |
16685 | /* |
16686 | * We start out with underrun reporting disabled to avoid races. | |
16687 | * For correct bookkeeping mark this on active crtcs. | |
16688 | * | |
c5ab3bc0 DV |
16689 | * Also on gmch platforms we dont have any hardware bits to |
16690 | * disable the underrun reporting. Which means we need to start | |
16691 | * out with underrun reporting disabled also on inactive pipes, | |
16692 | * since otherwise we'll complain about the garbage we read when | |
16693 | * e.g. coming up after runtime pm. | |
16694 | * | |
4cc31489 DV |
16695 | * No protection against concurrent access is required - at |
16696 | * worst a fifo underrun happens which also sets this to false. | |
16697 | */ | |
16698 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
16699 | /* |
16700 | * We track the PCH trancoder underrun reporting state | |
16701 | * within the crtc. With crtc for pipe A housing the underrun | |
16702 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
16703 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
16704 | * and marking underrun reporting as disabled for the non-existing | |
16705 | * PCH transcoders B and C would prevent enabling the south | |
16706 | * error interrupt (see cpt_can_enable_serr_int()). | |
16707 | */ | |
16708 | if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) | |
16709 | crtc->pch_fifo_underrun_disabled = true; | |
4cc31489 | 16710 | } |
24929352 DV |
16711 | } |
16712 | ||
16713 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
16714 | { | |
16715 | struct intel_connector *connector; | |
24929352 DV |
16716 | |
16717 | /* We need to check both for a crtc link (meaning that the | |
16718 | * encoder is active and trying to read from a pipe) and the | |
16719 | * pipe itself being active. */ | |
16720 | bool has_active_crtc = encoder->base.crtc && | |
16721 | to_intel_crtc(encoder->base.crtc)->active; | |
16722 | ||
496b0fc3 ML |
16723 | connector = intel_encoder_find_connector(encoder); |
16724 | if (connector && !has_active_crtc) { | |
24929352 DV |
16725 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
16726 | encoder->base.base.id, | |
8e329a03 | 16727 | encoder->base.name); |
24929352 DV |
16728 | |
16729 | /* Connector is active, but has no active pipe. This is | |
16730 | * fallout from our resume register restoring. Disable | |
16731 | * the encoder manually again. */ | |
16732 | if (encoder->base.crtc) { | |
fd6bbda9 ML |
16733 | struct drm_crtc_state *crtc_state = encoder->base.crtc->state; |
16734 | ||
24929352 DV |
16735 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
16736 | encoder->base.base.id, | |
8e329a03 | 16737 | encoder->base.name); |
fd6bbda9 | 16738 | encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
a62d1497 | 16739 | if (encoder->post_disable) |
fd6bbda9 | 16740 | encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
24929352 | 16741 | } |
7f1950fb | 16742 | encoder->base.crtc = NULL; |
24929352 DV |
16743 | |
16744 | /* Inconsistent output/port/pipe state happens presumably due to | |
16745 | * a bug in one of the get_hw_state functions. Or someplace else | |
16746 | * in our code, like the register restore mess on resume. Clamp | |
16747 | * things to off as a safer default. */ | |
fd6bbda9 ML |
16748 | |
16749 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
16750 | connector->base.encoder = NULL; | |
24929352 DV |
16751 | } |
16752 | /* Enabled encoders without active connectors will be fixed in | |
16753 | * the crtc fixup. */ | |
16754 | } | |
16755 | ||
04098753 | 16756 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f | 16757 | { |
fac5e23e | 16758 | struct drm_i915_private *dev_priv = to_i915(dev); |
920a14b2 | 16759 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
0fde901f | 16760 | |
04098753 ID |
16761 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
16762 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
16763 | i915_disable_vga(dev); | |
16764 | } | |
16765 | } | |
16766 | ||
16767 | void i915_redisable_vga(struct drm_device *dev) | |
16768 | { | |
fac5e23e | 16769 | struct drm_i915_private *dev_priv = to_i915(dev); |
04098753 | 16770 | |
8dc8a27c PZ |
16771 | /* This function can be called both from intel_modeset_setup_hw_state or |
16772 | * at a very early point in our resume sequence, where the power well | |
16773 | * structures are not yet restored. Since this function is at a very | |
16774 | * paranoid "someone might have enabled VGA while we were not looking" | |
16775 | * level, just check if the power well is enabled instead of trying to | |
16776 | * follow the "don't touch the power well if we don't need it" policy | |
16777 | * the rest of the driver uses. */ | |
6392f847 | 16778 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
16779 | return; |
16780 | ||
04098753 | 16781 | i915_redisable_vga_power_on(dev); |
6392f847 ID |
16782 | |
16783 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
16784 | } |
16785 | ||
f9cd7b88 | 16786 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 16787 | { |
f9cd7b88 | 16788 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 16789 | |
f9cd7b88 | 16790 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
16791 | } |
16792 | ||
f9cd7b88 VS |
16793 | /* FIXME read out full plane state for all planes */ |
16794 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 16795 | { |
b26d3ea3 | 16796 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 16797 | struct intel_plane_state *plane_state = |
b26d3ea3 | 16798 | to_intel_plane_state(primary->state); |
d032ffa0 | 16799 | |
936e71e3 | 16800 | plane_state->base.visible = crtc->active && |
b26d3ea3 ML |
16801 | primary_get_hw_state(to_intel_plane(primary)); |
16802 | ||
936e71e3 | 16803 | if (plane_state->base.visible) |
b26d3ea3 | 16804 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); |
98ec7739 VS |
16805 | } |
16806 | ||
30e984df | 16807 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 16808 | { |
fac5e23e | 16809 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 16810 | enum pipe pipe; |
24929352 DV |
16811 | struct intel_crtc *crtc; |
16812 | struct intel_encoder *encoder; | |
16813 | struct intel_connector *connector; | |
5358901f | 16814 | int i; |
24929352 | 16815 | |
565602d7 ML |
16816 | dev_priv->active_crtcs = 0; |
16817 | ||
d3fcc808 | 16818 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
16819 | struct intel_crtc_state *crtc_state = crtc->config; |
16820 | int pixclk = 0; | |
3b117c8f | 16821 | |
ec2dc6a0 | 16822 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
16823 | memset(crtc_state, 0, sizeof(*crtc_state)); |
16824 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 16825 | |
565602d7 ML |
16826 | crtc_state->base.active = crtc_state->base.enable = |
16827 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
16828 | ||
16829 | crtc->base.enabled = crtc_state->base.enable; | |
16830 | crtc->active = crtc_state->base.active; | |
16831 | ||
16832 | if (crtc_state->base.active) { | |
16833 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
16834 | ||
c89e39f3 | 16835 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) |
565602d7 | 16836 | pixclk = ilk_pipe_pixel_rate(crtc_state); |
9558d15d | 16837 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
565602d7 ML |
16838 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; |
16839 | else | |
16840 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
9558d15d VS |
16841 | |
16842 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
16843 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) | |
16844 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
565602d7 ML |
16845 | } |
16846 | ||
16847 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 16848 | |
f9cd7b88 | 16849 | readout_plane_state(crtc); |
24929352 | 16850 | |
78108b7c VS |
16851 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
16852 | crtc->base.base.id, crtc->base.name, | |
24929352 DV |
16853 | crtc->active ? "enabled" : "disabled"); |
16854 | } | |
16855 | ||
5358901f DV |
16856 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16857 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16858 | ||
2edd6443 ACO |
16859 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
16860 | &pll->config.hw_state); | |
3e369b76 | 16861 | pll->config.crtc_mask = 0; |
d3fcc808 | 16862 | for_each_intel_crtc(dev, crtc) { |
2dd66ebd | 16863 | if (crtc->active && crtc->config->shared_dpll == pll) |
3e369b76 | 16864 | pll->config.crtc_mask |= 1 << crtc->pipe; |
5358901f | 16865 | } |
2dd66ebd | 16866 | pll->active_mask = pll->config.crtc_mask; |
5358901f | 16867 | |
1e6f2ddc | 16868 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 16869 | pll->name, pll->config.crtc_mask, pll->on); |
5358901f DV |
16870 | } |
16871 | ||
b2784e15 | 16872 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16873 | pipe = 0; |
16874 | ||
16875 | if (encoder->get_hw_state(encoder, &pipe)) { | |
98187836 | 16876 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
e2af48c6 | 16877 | |
045ac3b5 | 16878 | encoder->base.crtc = &crtc->base; |
253c84c8 | 16879 | crtc->config->output_types |= 1 << encoder->type; |
6e3c9717 | 16880 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
16881 | } else { |
16882 | encoder->base.crtc = NULL; | |
16883 | } | |
16884 | ||
6f2bcceb | 16885 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 16886 | encoder->base.base.id, |
8e329a03 | 16887 | encoder->base.name, |
24929352 | 16888 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 16889 | pipe_name(pipe)); |
24929352 DV |
16890 | } |
16891 | ||
3a3371ff | 16892 | for_each_intel_connector(dev, connector) { |
24929352 DV |
16893 | if (connector->get_hw_state(connector)) { |
16894 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
16895 | |
16896 | encoder = connector->encoder; | |
16897 | connector->base.encoder = &encoder->base; | |
16898 | ||
16899 | if (encoder->base.crtc && | |
16900 | encoder->base.crtc->state->active) { | |
16901 | /* | |
16902 | * This has to be done during hardware readout | |
16903 | * because anything calling .crtc_disable may | |
16904 | * rely on the connector_mask being accurate. | |
16905 | */ | |
16906 | encoder->base.crtc->state->connector_mask |= | |
16907 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
16908 | encoder->base.crtc->state->encoder_mask |= |
16909 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
16910 | } |
16911 | ||
24929352 DV |
16912 | } else { |
16913 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
16914 | connector->base.encoder = NULL; | |
16915 | } | |
16916 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
16917 | connector->base.base.id, | |
c23cc417 | 16918 | connector->base.name, |
24929352 DV |
16919 | connector->base.encoder ? "enabled" : "disabled"); |
16920 | } | |
7f4c6284 VS |
16921 | |
16922 | for_each_intel_crtc(dev, crtc) { | |
16923 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
16924 | ||
16925 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
16926 | if (crtc->base.state->active) { | |
16927 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
16928 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
16929 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
16930 | ||
16931 | /* | |
16932 | * The initial mode needs to be set in order to keep | |
16933 | * the atomic core happy. It wants a valid mode if the | |
16934 | * crtc's enabled, so we do the above call. | |
16935 | * | |
16936 | * At this point some state updated by the connectors | |
16937 | * in their ->detect() callback has not run yet, so | |
16938 | * no recalculation can be done yet. | |
16939 | * | |
16940 | * Even if we could do a recalculation and modeset | |
16941 | * right now it would cause a double modeset if | |
16942 | * fbdev or userspace chooses a different initial mode. | |
16943 | * | |
16944 | * If that happens, someone indicated they wanted a | |
16945 | * mode change, which means it's safe to do a full | |
16946 | * recalculation. | |
16947 | */ | |
16948 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
16949 | |
16950 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
16951 | update_scanline_offset(crtc); | |
7f4c6284 | 16952 | } |
e3b247da VS |
16953 | |
16954 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 16955 | } |
30e984df DV |
16956 | } |
16957 | ||
043e9bda ML |
16958 | /* Scan out the current hw modeset state, |
16959 | * and sanitizes it to the current state | |
16960 | */ | |
16961 | static void | |
16962 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df | 16963 | { |
fac5e23e | 16964 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 16965 | enum pipe pipe; |
30e984df DV |
16966 | struct intel_crtc *crtc; |
16967 | struct intel_encoder *encoder; | |
35c95375 | 16968 | int i; |
30e984df DV |
16969 | |
16970 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
16971 | |
16972 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 16973 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
16974 | intel_sanitize_encoder(encoder); |
16975 | } | |
16976 | ||
055e393f | 16977 | for_each_pipe(dev_priv, pipe) { |
98187836 | 16978 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
e2af48c6 | 16979 | |
24929352 | 16980 | intel_sanitize_crtc(crtc); |
6e3c9717 ACO |
16981 | intel_dump_pipe_config(crtc, crtc->config, |
16982 | "[setup_hw_state]"); | |
24929352 | 16983 | } |
9a935856 | 16984 | |
d29b2f9d ACO |
16985 | intel_modeset_update_connector_atomic_state(dev); |
16986 | ||
35c95375 DV |
16987 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
16988 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
16989 | ||
2dd66ebd | 16990 | if (!pll->on || pll->active_mask) |
35c95375 DV |
16991 | continue; |
16992 | ||
16993 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
16994 | ||
2edd6443 | 16995 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
16996 | pll->on = false; |
16997 | } | |
16998 | ||
920a14b2 | 16999 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6eb1a681 | 17000 | vlv_wm_get_hw_state(dev); |
5db94019 | 17001 | else if (IS_GEN9(dev_priv)) |
3078999f | 17002 | skl_wm_get_hw_state(dev); |
6e266956 | 17003 | else if (HAS_PCH_SPLIT(dev_priv)) |
243e6a44 | 17004 | ilk_wm_get_hw_state(dev); |
292b990e ML |
17005 | |
17006 | for_each_intel_crtc(dev, crtc) { | |
17007 | unsigned long put_domains; | |
17008 | ||
74bff5f9 | 17009 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
17010 | if (WARN_ON(put_domains)) |
17011 | modeset_put_power_domains(dev_priv, put_domains); | |
17012 | } | |
17013 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
17014 | |
17015 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 17016 | } |
7d0bc1ea | 17017 | |
043e9bda ML |
17018 | void intel_display_resume(struct drm_device *dev) |
17019 | { | |
e2c8b870 ML |
17020 | struct drm_i915_private *dev_priv = to_i915(dev); |
17021 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
17022 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 17023 | int ret; |
f30da187 | 17024 | |
e2c8b870 | 17025 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
17026 | if (state) |
17027 | state->acquire_ctx = &ctx; | |
043e9bda | 17028 | |
ea49c9ac ML |
17029 | /* |
17030 | * This is a cludge because with real atomic modeset mode_config.mutex | |
17031 | * won't be taken. Unfortunately some probed state like | |
17032 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
17033 | * it here for now. | |
17034 | */ | |
17035 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 17036 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 17037 | |
73974893 ML |
17038 | while (1) { |
17039 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
17040 | if (ret != -EDEADLK) | |
17041 | break; | |
043e9bda | 17042 | |
e2c8b870 | 17043 | drm_modeset_backoff(&ctx); |
e2c8b870 | 17044 | } |
043e9bda | 17045 | |
73974893 ML |
17046 | if (!ret) |
17047 | ret = __intel_display_resume(dev, state); | |
17048 | ||
e2c8b870 ML |
17049 | drm_modeset_drop_locks(&ctx); |
17050 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 17051 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 17052 | |
0853695c | 17053 | if (ret) |
e2c8b870 | 17054 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
0853695c | 17055 | drm_atomic_state_put(state); |
2c7111db CW |
17056 | } |
17057 | ||
17058 | void intel_modeset_gem_init(struct drm_device *dev) | |
17059 | { | |
dc97997a | 17060 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 17061 | struct drm_crtc *c; |
2ff8fde1 | 17062 | struct drm_i915_gem_object *obj; |
484b41dd | 17063 | |
dc97997a | 17064 | intel_init_gt_powersave(dev_priv); |
ae48434c | 17065 | |
1833b134 | 17066 | intel_modeset_init_hw(dev); |
02e792fb | 17067 | |
1ee8da6d | 17068 | intel_setup_overlay(dev_priv); |
484b41dd JB |
17069 | |
17070 | /* | |
17071 | * Make sure any fbs we allocated at startup are properly | |
17072 | * pinned & fenced. When we do the allocation it's too early | |
17073 | * for this. | |
17074 | */ | |
70e1e0ec | 17075 | for_each_crtc(dev, c) { |
058d88c4 CW |
17076 | struct i915_vma *vma; |
17077 | ||
2ff8fde1 MR |
17078 | obj = intel_fb_obj(c->primary->fb); |
17079 | if (obj == NULL) | |
484b41dd JB |
17080 | continue; |
17081 | ||
e0d6149b | 17082 | mutex_lock(&dev->struct_mutex); |
058d88c4 | 17083 | vma = intel_pin_and_fence_fb_obj(c->primary->fb, |
3465c580 | 17084 | c->primary->state->rotation); |
e0d6149b | 17085 | mutex_unlock(&dev->struct_mutex); |
058d88c4 | 17086 | if (IS_ERR(vma)) { |
484b41dd JB |
17087 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
17088 | to_intel_crtc(c)->pipe); | |
66e514c1 | 17089 | drm_framebuffer_unreference(c->primary->fb); |
5a21b665 | 17090 | c->primary->fb = NULL; |
36750f28 | 17091 | c->primary->crtc = c->primary->state->crtc = NULL; |
5a21b665 | 17092 | update_state_fb(c->primary); |
36750f28 | 17093 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
17094 | } |
17095 | } | |
1ebaa0b9 CW |
17096 | } |
17097 | ||
17098 | int intel_connector_register(struct drm_connector *connector) | |
17099 | { | |
17100 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
17101 | int ret; | |
17102 | ||
17103 | ret = intel_backlight_device_register(intel_connector); | |
17104 | if (ret) | |
17105 | goto err; | |
17106 | ||
17107 | return 0; | |
0962c3c9 | 17108 | |
1ebaa0b9 CW |
17109 | err: |
17110 | return ret; | |
79e53945 JB |
17111 | } |
17112 | ||
c191eca1 | 17113 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 17114 | { |
e63d87c0 | 17115 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 17116 | |
e63d87c0 | 17117 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 17118 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
17119 | } |
17120 | ||
79e53945 JB |
17121 | void intel_modeset_cleanup(struct drm_device *dev) |
17122 | { | |
fac5e23e | 17123 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 17124 | |
dc97997a | 17125 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 17126 | |
fd0c0642 DV |
17127 | /* |
17128 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 17129 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
17130 | * experience fancy races otherwise. |
17131 | */ | |
2aeb7d3a | 17132 | intel_irq_uninstall(dev_priv); |
eb21b92b | 17133 | |
fd0c0642 DV |
17134 | /* |
17135 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
17136 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
17137 | */ | |
f87ea761 | 17138 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 17139 | |
723bfd70 JB |
17140 | intel_unregister_dsm_handler(); |
17141 | ||
c937ab3e | 17142 | intel_fbc_global_disable(dev_priv); |
69341a5e | 17143 | |
1630fe75 CW |
17144 | /* flush any delayed tasks or pending work */ |
17145 | flush_scheduled_work(); | |
17146 | ||
79e53945 | 17147 | drm_mode_config_cleanup(dev); |
4d7bb011 | 17148 | |
1ee8da6d | 17149 | intel_cleanup_overlay(dev_priv); |
ae48434c | 17150 | |
dc97997a | 17151 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 DV |
17152 | |
17153 | intel_teardown_gmbus(dev); | |
79e53945 JB |
17154 | } |
17155 | ||
df0e9248 CW |
17156 | void intel_connector_attach_encoder(struct intel_connector *connector, |
17157 | struct intel_encoder *encoder) | |
17158 | { | |
17159 | connector->encoder = encoder; | |
17160 | drm_mode_connector_attach_encoder(&connector->base, | |
17161 | &encoder->base); | |
79e53945 | 17162 | } |
28d52043 DA |
17163 | |
17164 | /* | |
17165 | * set vga decode state - true == enable VGA decode | |
17166 | */ | |
17167 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
17168 | { | |
fac5e23e | 17169 | struct drm_i915_private *dev_priv = to_i915(dev); |
a885b3cc | 17170 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
17171 | u16 gmch_ctrl; |
17172 | ||
75fa041d CW |
17173 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
17174 | DRM_ERROR("failed to read control word\n"); | |
17175 | return -EIO; | |
17176 | } | |
17177 | ||
c0cc8a55 CW |
17178 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
17179 | return 0; | |
17180 | ||
28d52043 DA |
17181 | if (state) |
17182 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
17183 | else | |
17184 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
17185 | |
17186 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
17187 | DRM_ERROR("failed to write control word\n"); | |
17188 | return -EIO; | |
17189 | } | |
17190 | ||
28d52043 DA |
17191 | return 0; |
17192 | } | |
c4a1d9e4 | 17193 | |
98a2f411 CW |
17194 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
17195 | ||
c4a1d9e4 | 17196 | struct intel_display_error_state { |
ff57f1b0 PZ |
17197 | |
17198 | u32 power_well_driver; | |
17199 | ||
63b66e5b CW |
17200 | int num_transcoders; |
17201 | ||
c4a1d9e4 CW |
17202 | struct intel_cursor_error_state { |
17203 | u32 control; | |
17204 | u32 position; | |
17205 | u32 base; | |
17206 | u32 size; | |
52331309 | 17207 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
17208 | |
17209 | struct intel_pipe_error_state { | |
ddf9c536 | 17210 | bool power_domain_on; |
c4a1d9e4 | 17211 | u32 source; |
f301b1e1 | 17212 | u32 stat; |
52331309 | 17213 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
17214 | |
17215 | struct intel_plane_error_state { | |
17216 | u32 control; | |
17217 | u32 stride; | |
17218 | u32 size; | |
17219 | u32 pos; | |
17220 | u32 addr; | |
17221 | u32 surface; | |
17222 | u32 tile_offset; | |
52331309 | 17223 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
17224 | |
17225 | struct intel_transcoder_error_state { | |
ddf9c536 | 17226 | bool power_domain_on; |
63b66e5b CW |
17227 | enum transcoder cpu_transcoder; |
17228 | ||
17229 | u32 conf; | |
17230 | ||
17231 | u32 htotal; | |
17232 | u32 hblank; | |
17233 | u32 hsync; | |
17234 | u32 vtotal; | |
17235 | u32 vblank; | |
17236 | u32 vsync; | |
17237 | } transcoder[4]; | |
c4a1d9e4 CW |
17238 | }; |
17239 | ||
17240 | struct intel_display_error_state * | |
c033666a | 17241 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 17242 | { |
c4a1d9e4 | 17243 | struct intel_display_error_state *error; |
63b66e5b CW |
17244 | int transcoders[] = { |
17245 | TRANSCODER_A, | |
17246 | TRANSCODER_B, | |
17247 | TRANSCODER_C, | |
17248 | TRANSCODER_EDP, | |
17249 | }; | |
c4a1d9e4 CW |
17250 | int i; |
17251 | ||
c033666a | 17252 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
17253 | return NULL; |
17254 | ||
9d1cb914 | 17255 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
17256 | if (error == NULL) |
17257 | return NULL; | |
17258 | ||
c033666a | 17259 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
17260 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
17261 | ||
055e393f | 17262 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 17263 | error->pipe[i].power_domain_on = |
f458ebbc DV |
17264 | __intel_display_power_is_enabled(dev_priv, |
17265 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 17266 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
17267 | continue; |
17268 | ||
5efb3e28 VS |
17269 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
17270 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
17271 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
17272 | |
17273 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
17274 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 17275 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 17276 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
17277 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
17278 | } | |
c033666a | 17279 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 17280 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 17281 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
17282 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
17283 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
17284 | } | |
17285 | ||
c4a1d9e4 | 17286 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 17287 | |
c033666a | 17288 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 17289 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
17290 | } |
17291 | ||
4d1de975 | 17292 | /* Note: this does not include DSI transcoders. */ |
c033666a | 17293 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 17294 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
17295 | error->num_transcoders++; /* Account for eDP. */ |
17296 | ||
17297 | for (i = 0; i < error->num_transcoders; i++) { | |
17298 | enum transcoder cpu_transcoder = transcoders[i]; | |
17299 | ||
ddf9c536 | 17300 | error->transcoder[i].power_domain_on = |
f458ebbc | 17301 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 17302 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 17303 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
17304 | continue; |
17305 | ||
63b66e5b CW |
17306 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
17307 | ||
17308 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
17309 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
17310 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
17311 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
17312 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
17313 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
17314 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
17315 | } |
17316 | ||
17317 | return error; | |
17318 | } | |
17319 | ||
edc3d884 MK |
17320 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
17321 | ||
c4a1d9e4 | 17322 | void |
edc3d884 | 17323 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
17324 | struct drm_device *dev, |
17325 | struct intel_display_error_state *error) | |
17326 | { | |
fac5e23e | 17327 | struct drm_i915_private *dev_priv = to_i915(dev); |
c4a1d9e4 CW |
17328 | int i; |
17329 | ||
63b66e5b CW |
17330 | if (!error) |
17331 | return; | |
17332 | ||
edc3d884 | 17333 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
8652744b | 17334 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
edc3d884 | 17335 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 17336 | error->power_well_driver); |
055e393f | 17337 | for_each_pipe(dev_priv, i) { |
edc3d884 | 17338 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 17339 | err_printf(m, " Power: %s\n", |
87ad3212 | 17340 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 17341 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 17342 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
17343 | |
17344 | err_printf(m, "Plane [%d]:\n", i); | |
17345 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
17346 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 17347 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
17348 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
17349 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 17350 | } |
772c2a51 | 17351 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
edc3d884 | 17352 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 17353 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
17354 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
17355 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
17356 | } |
17357 | ||
edc3d884 MK |
17358 | err_printf(m, "Cursor [%d]:\n", i); |
17359 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
17360 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
17361 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 17362 | } |
63b66e5b CW |
17363 | |
17364 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 17365 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 17366 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 17367 | err_printf(m, " Power: %s\n", |
87ad3212 | 17368 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
17369 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
17370 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
17371 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
17372 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
17373 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
17374 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
17375 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
17376 | } | |
c4a1d9e4 | 17377 | } |
98a2f411 CW |
17378 | |
17379 | #endif |