[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_display.h

/*
 * Copyright © 2006-2017 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#ifndef _INTEL_DISPLAY_H_
#define _INTEL_DISPLAY_H_

enum pipe {
	INVALID_PIPE = -1,

	PIPE_A = 0,
	PIPE_B,
	PIPE_C,
	_PIPE_EDP,

	I915_MAX_PIPES = _PIPE_EDP
};

#define pipe_name(p) ((p) + 'A')

enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
	TRANSCODER_EDP,
	TRANSCODER_DSI_A,
	TRANSCODER_DSI_C,

	I915_MAX_TRANSCODERS
};

static inline const char *transcoder_name(enum transcoder transcoder)
{
	switch (transcoder) {
	case TRANSCODER_A:
		return "A";
	case TRANSCODER_B:
		return "B";
	case TRANSCODER_C:
		return "C";
	case TRANSCODER_EDP:
		return "EDP";
	case TRANSCODER_DSI_A:
		return "DSI A";
	case TRANSCODER_DSI_C:
		return "DSI C";
	default:
		return "<invalid>";
	}
}

static inline bool transcoder_is_dsi(enum transcoder transcoder)
{
	return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
}

/*
 * Global legacy plane identifier. Valid only for primary/sprite
 * planes on pre-g4x, and only for primary planes on g4x-bdw.
 */
enum i9xx_plane_id {
	PLANE_A,
	PLANE_B,
	PLANE_C,
};

#define plane_name(p) ((p) + 'A')
#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')

/*
 * Per-pipe plane identifier.
 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 * number of planes per CRTC.  Not all platforms really have this many planes,
 * which means some arrays of size I915_MAX_PLANES may have unused entries
 * between the topmost sprite plane and the cursor plane.
 *
 * This is expected to be passed to various register macros
 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 */
enum plane_id {
	PLANE_PRIMARY,
	PLANE_SPRITE0,
	PLANE_SPRITE1,
	PLANE_SPRITE2,
	PLANE_CURSOR,

	I915_MAX_PLANES,
};

#define for_each_plane_id_on_crtc(__crtc, __p) \
	for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
		for_each_if((__crtc)->plane_ids_mask & BIT(__p))

enum port {
	PORT_NONE = -1,

	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,

	I915_MAX_PORTS
};

#define port_name(p) ((p) + 'A')

enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
	DPIO_PHY1,
	DPIO_PHY2,
};

#define I915_NUM_PHYS_VLV 2

enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
	POWER_DOMAIN_TRANSCODER_EDP,
	POWER_DOMAIN_TRANSCODER_DSI_A,
	POWER_DOMAIN_TRANSCODER_DSI_C,
	POWER_DOMAIN_PORT_DDI_A_LANES,
	POWER_DOMAIN_PORT_DDI_B_LANES,
	POWER_DOMAIN_PORT_DDI_C_LANES,
	POWER_DOMAIN_PORT_DDI_D_LANES,
	POWER_DOMAIN_PORT_DDI_E_LANES,
	POWER_DOMAIN_PORT_DDI_A_IO,
	POWER_DOMAIN_PORT_DDI_B_IO,
	POWER_DOMAIN_PORT_DDI_C_IO,
	POWER_DOMAIN_PORT_DDI_D_IO,
	POWER_DOMAIN_PORT_DDI_E_IO,
	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
	POWER_DOMAIN_VGA,
	POWER_DOMAIN_AUDIO,
	POWER_DOMAIN_PLLS,
	POWER_DOMAIN_AUX_A,
	POWER_DOMAIN_AUX_B,
	POWER_DOMAIN_AUX_C,
	POWER_DOMAIN_AUX_D,
	POWER_DOMAIN_GMBUS,
	POWER_DOMAIN_MODESET,
	POWER_DOMAIN_GT_IRQ,
	POWER_DOMAIN_INIT,

	POWER_DOMAIN_NUM,
};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)

/* Used by dp and fdi links */
struct intel_link_m_n {
	u32 tu;
	u32 gmch_m;
	u32 gmch_n;
	u32 link_m;
	u32 link_n;
};

#define for_each_pipe(__dev_priv, __p) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)

#define for_each_pipe_masked(__dev_priv, __p, __mask) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
		for_each_if((__mask) & BIT(__p))

#define for_each_universal_plane(__dev_priv, __pipe, __p)		\
	for ((__p) = 0;							\
	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
	     (__p)++)

#define for_each_sprite(__dev_priv, __p, __s)				\
	for ((__s) = 0;							\
	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
	     (__s)++)

#define for_each_port_masked(__port, __ports_mask) \
	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
		for_each_if((__ports_mask) & BIT(__port))

#define for_each_crtc(dev, crtc) \
	list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)

#define for_each_intel_plane(dev, intel_plane) \
	list_for_each_entry(intel_plane,			\
			    &(dev)->mode_config.plane_list,	\
			    base.head)

#define for_each_intel_plane_mask(dev, intel_plane, plane_mask)		\
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
			    base.head)					\
		for_each_if((plane_mask) &				\
			    BIT(drm_plane_index(&intel_plane->base)))

#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
			    base.head)					\
		for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)

#define for_each_intel_crtc(dev, intel_crtc)				\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)

#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)		\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)					\
		for_each_if((crtc_mask) & BIT(drm_crtc_index(&intel_crtc->base)))

#define for_each_intel_encoder(dev, intel_encoder)		\
	list_for_each_entry(intel_encoder,			\
			    &(dev)->mode_config.encoder_list,	\
			    base.head)

#define for_each_intel_connector_iter(intel_connector, iter) \
	while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))

#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
		for_each_if((intel_encoder)->base.crtc == (__crtc))

#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
		for_each_if((intel_connector)->base.encoder == (__encoder))

#define for_each_power_domain(domain, mask)				\
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
		for_each_if(BIT_ULL(domain) & (mask))

#define for_each_power_well(__dev_priv, __power_well)				\
	for ((__power_well) = (__dev_priv)->power_domains.power_wells;	\
	     (__power_well) - (__dev_priv)->power_domains.power_wells <	\
		(__dev_priv)->power_domains.power_well_count;		\
	     (__power_well)++)

#define for_each_power_well_rev(__dev_priv, __power_well)			\
	for ((__power_well) = (__dev_priv)->power_domains.power_wells +		\
			      (__dev_priv)->power_domains.power_well_count - 1;	\
	     (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;	\
	     (__power_well)--)

#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)	\
	for_each_power_well(__dev_priv, __power_well)				\
		for_each_if((__power_well)->domains & (__domain_mask))

#define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
	for_each_power_well_rev(__dev_priv, __power_well)		        \
		for_each_if((__power_well)->domains & (__domain_mask))

#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
	for ((__i) = 0; \
	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
		      (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
	     (__i)++) \
		for_each_if(plane)

#define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
	for ((__i) = 0; \
	     (__i) < (__state)->base.dev->mode_config.num_crtc && \
		     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
		      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
	     (__i)++) \
		for_each_if(crtc)

#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
	for ((__i) = 0; \
	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
		      (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
		      (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
	     (__i)++) \
		for_each_if(plane)

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
			    struct intel_link_m_n *m_n,
			    bool reduce_m_n);

#endif
Commit	Line	Data
09a28bd9 MW	1	/*
	2	* Copyright © 2006-2017 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
	25	#ifndef _INTEL_DISPLAY_H_
	26	#define _INTEL_DISPLAY_H_
	27
	28	enum pipe {
	29	INVALID_PIPE = -1,
	30
	31	PIPE_A = 0,
	32	PIPE_B,
	33	PIPE_C,
	34	_PIPE_EDP,
	35
	36	I915_MAX_PIPES = _PIPE_EDP
	37	};
	38
	39	#define pipe_name(p) ((p) + 'A')
	40
	41	enum transcoder {
	42	TRANSCODER_A = 0,
	43	TRANSCODER_B,
	44	TRANSCODER_C,
	45	TRANSCODER_EDP,
	46	TRANSCODER_DSI_A,
	47	TRANSCODER_DSI_C,
	48
	49	I915_MAX_TRANSCODERS
	50	};
	51
	52	static inline const char *transcoder_name(enum transcoder transcoder)
	53	{
	54	switch (transcoder) {
	55	case TRANSCODER_A:
	56	return "A";
	57	case TRANSCODER_B:
	58	return "B";
	59	case TRANSCODER_C:
	60	return "C";
	61	case TRANSCODER_EDP:
	62	return "EDP";
	63	case TRANSCODER_DSI_A:
	64	return "DSI A";
65	case TRANSCODER_DSI_C:
66	return "DSI C";
67	default:
68	return "<invalid>";
69	}
70	}
71
72	static inline bool transcoder_is_dsi(enum transcoder transcoder)
73	{
74	return transcoder == TRANSCODER_DSI_A \|\| transcoder == TRANSCODER_DSI_C;
75	}
76
77	/*
78	* Global legacy plane identifier. Valid only for primary/sprite
79	* planes on pre-g4x, and only for primary planes on g4x-bdw.
80	*/
81	enum i9xx_plane_id {
82	PLANE_A,
83	PLANE_B,
84	PLANE_C,
85	};
86
87	#define plane_name(p) ((p) + 'A')
88	#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
89
90	/*
91	* Per-pipe plane identifier.
92	* I915_MAX_PLANES in the enum below is the maximum (across all platforms)
93	* number of planes per CRTC. Not all platforms really have this many planes,
94	* which means some arrays of size I915_MAX_PLANES may have unused entries
95	* between the topmost sprite plane and the cursor plane.
96	*
97	* This is expected to be passed to various register macros
98	* (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
99	*/
100	enum plane_id {
101	PLANE_PRIMARY,
102	PLANE_SPRITE0,
103	PLANE_SPRITE1,
104	PLANE_SPRITE2,
105	PLANE_CURSOR,
106
107	I915_MAX_PLANES,
108	};
109
110	#define for_each_plane_id_on_crtc(__crtc, __p) \
111	for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
112	for_each_if((__crtc)->plane_ids_mask & BIT(__p))
113
114	enum port {
115	PORT_NONE = -1,
116
117	PORT_A = 0,
118	PORT_B,
119	PORT_C,
120	PORT_D,
121	PORT_E,
122
123	I915_MAX_PORTS
124	};
125
126	#define port_name(p) ((p) + 'A')
127
128	enum dpio_channel {
129	DPIO_CH0,
130	DPIO_CH1
131	};
132
133	enum dpio_phy {
134	DPIO_PHY0,
135	DPIO_PHY1,
136	DPIO_PHY2,
137	};
138
139	#define I915_NUM_PHYS_VLV 2
140
141	enum intel_display_power_domain {
142	POWER_DOMAIN_PIPE_A,
143	POWER_DOMAIN_PIPE_B,
144	POWER_DOMAIN_PIPE_C,
145	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
146	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
147	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
148	POWER_DOMAIN_TRANSCODER_A,
149	POWER_DOMAIN_TRANSCODER_B,
150	POWER_DOMAIN_TRANSCODER_C,
151	POWER_DOMAIN_TRANSCODER_EDP,
152	POWER_DOMAIN_TRANSCODER_DSI_A,
153	POWER_DOMAIN_TRANSCODER_DSI_C,
154	POWER_DOMAIN_PORT_DDI_A_LANES,
155	POWER_DOMAIN_PORT_DDI_B_LANES,
156	POWER_DOMAIN_PORT_DDI_C_LANES,
157	POWER_DOMAIN_PORT_DDI_D_LANES,
158	POWER_DOMAIN_PORT_DDI_E_LANES,
159	POWER_DOMAIN_PORT_DDI_A_IO,
160	POWER_DOMAIN_PORT_DDI_B_IO,
161	POWER_DOMAIN_PORT_DDI_C_IO,
162	POWER_DOMAIN_PORT_DDI_D_IO,
163	POWER_DOMAIN_PORT_DDI_E_IO,
164	POWER_DOMAIN_PORT_DSI,
165	POWER_DOMAIN_PORT_CRT,
166	POWER_DOMAIN_PORT_OTHER,
167	POWER_DOMAIN_VGA,
168	POWER_DOMAIN_AUDIO,
169	POWER_DOMAIN_PLLS,
170	POWER_DOMAIN_AUX_A,
171	POWER_DOMAIN_AUX_B,
172	POWER_DOMAIN_AUX_C,
173	POWER_DOMAIN_AUX_D,
174	POWER_DOMAIN_GMBUS,
175	POWER_DOMAIN_MODESET,
176	POWER_DOMAIN_GT_IRQ,
177	POWER_DOMAIN_INIT,
178
179	POWER_DOMAIN_NUM,
180	};
181
182	#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
183	#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
184	((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
185	#define POWER_DOMAIN_TRANSCODER(tran) \
186	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
187	(tran) + POWER_DOMAIN_TRANSCODER_A)
188
189	/* Used by dp and fdi links */
190	struct intel_link_m_n {
191	u32 tu;
192	u32 gmch_m;
193	u32 gmch_n;
194	u32 link_m;
195	u32 link_n;
196	};
197
198	#define for_each_pipe(__dev_priv, __p) \
199	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
200
201	#define for_each_pipe_masked(__dev_priv, __p, __mask) \
202	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
203	for_each_if((__mask) & BIT(__p))
204
205	#define for_each_universal_plane(__dev_priv, __pipe, __p) \
206	for ((__p) = 0; \
207	(__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
208	(__p)++)
209
210	#define for_each_sprite(__dev_priv, __p, __s) \
211	for ((__s) = 0; \
212	(__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
213	(__s)++)
214
215	#define for_each_port_masked(__port, __ports_mask) \
216	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
217	for_each_if((__ports_mask) & BIT(__port))
218
219	#define for_each_crtc(dev, crtc) \
220	list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
221
222	#define for_each_intel_plane(dev, intel_plane) \
223	list_for_each_entry(intel_plane, \
224	&(dev)->mode_config.plane_list, \
225	base.head)
226
227	#define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
228	list_for_each_entry(intel_plane, \
229	&(dev)->mode_config.plane_list, \
230	base.head) \
231	for_each_if((plane_mask) & \
232	BIT(drm_plane_index(&intel_plane->base)))
233
234	#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
235	list_for_each_entry(intel_plane, \
236	&(dev)->mode_config.plane_list, \
237	base.head) \
238	for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
239
240	#define for_each_intel_crtc(dev, intel_crtc) \
241	list_for_each_entry(intel_crtc, \
242	&(dev)->mode_config.crtc_list, \
243	base.head)
244
245	#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
246	list_for_each_entry(intel_crtc, \
247	&(dev)->mode_config.crtc_list, \
248	base.head) \
249	for_each_if((crtc_mask) & BIT(drm_crtc_index(&intel_crtc->base)))
250
251	#define for_each_intel_encoder(dev, intel_encoder) \
252	list_for_each_entry(intel_encoder, \
253	&(dev)->mode_config.encoder_list, \
254	base.head)
255
256	#define for_each_intel_connector_iter(intel_connector, iter) \
257	while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
258
259	#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
260	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
261	for_each_if((intel_encoder)->base.crtc == (__crtc))
262
263	#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
264	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
265	for_each_if((intel_connector)->base.encoder == (__encoder))
266
267	#define for_each_power_domain(domain, mask) \
268	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
269	for_each_if(BIT_ULL(domain) & (mask))
270
271	#define for_each_power_well(__dev_priv, __power_well) \
272	for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
273	(__power_well) - (__dev_priv)->power_domains.power_wells < \
274	(__dev_priv)->power_domains.power_well_count; \
275	(__power_well)++)
276
277	#define for_each_power_well_rev(__dev_priv, __power_well) \
278	for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
279	(__dev_priv)->power_domains.power_well_count - 1; \
280	(__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
281	(__power_well)--)
282
283	#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
284	for_each_power_well(__dev_priv, __power_well) \
285	for_each_if((__power_well)->domains & (__domain_mask))
286
287	#define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
288	for_each_power_well_rev(__dev_priv, __power_well) \
289	for_each_if((__power_well)->domains & (__domain_mask))
290
291	#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
292	for ((__i) = 0; \
293	(__i) < (__state)->base.dev->mode_config.num_total_plane && \
294	((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
295	(new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
296	(__i)++) \
297	for_each_if(plane)
298
299	#define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
300	for ((__i) = 0; \
301	(__i) < (__state)->base.dev->mode_config.num_crtc && \
302	((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
303	(new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
304	(__i)++) \
305	for_each_if(crtc)
306
307	#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
308	for ((__i) = 0; \
309	(__i) < (__state)->base.dev->mode_config.num_total_plane && \
310	((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
311	(old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
312	(new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
313	(__i)++) \
314	for_each_if(plane)
315
316	void intel_link_compute_m_n(int bpp, int nlanes,
317	int pixel_clock, int link_clock,
318	struct intel_link_m_n *m_n,
319	bool reduce_m_n);
320
321	#endif