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drm/i915/vlv: reset VLV media force wake request register
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 94static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 95static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 96
a4fc5ed6 97static int
ea5b213a 98intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 99{
7183dc29 100 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 101 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 102
103 switch (max_link_bw) {
104 case DP_LINK_BW_1_62:
105 case DP_LINK_BW_2_7:
106 break;
d4eead50 107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 108 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
109 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 110 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
111 max_link_bw = DP_LINK_BW_5_4;
112 else
113 max_link_bw = DP_LINK_BW_2_7;
d4eead50 114 break;
a4fc5ed6 115 default:
d4eead50
ID		 116 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
117 max_link_bw);
a4fc5ed6
KP		 118 max_link_bw = DP_LINK_BW_1_62;
119 break;
120 }
121 return max_link_bw;
122}
123
eeb6324d
PZ		 124static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
125{
126 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
127 struct drm_device *dev = intel_dig_port->base.base.dev;
128 u8 source_max, sink_max;
129
130 source_max = 4;
131 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
132 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
133 source_max = 2;
134
135 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
136
137 return min(source_max, sink_max);
138}
139
cd9dde44
AJ		 140/*
141 * The units on the numbers in the next two are... bizarre. Examples will
142 * make it clearer; this one parallels an example in the eDP spec.
143 *
144 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
145 *
146 * 270000 * 1 * 8 / 10 == 216000
147 *
148 * The actual data capacity of that configuration is 2.16Gbit/s, so the
149 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
150 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
151 * 119000. At 18bpp that's 2142000 kilobits per second.
152 *
153 * Thus the strange-looking division by 10 in intel_dp_link_required, to
154 * get the result in decakilobits instead of kilobits.
155 */
156
a4fc5ed6 157static int
c898261c 158intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 159{
cd9dde44 160 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 161}
162
fe27d53e
DA		 163static int
164intel_dp_max_data_rate(int max_link_clock, int max_lanes)
165{
166 return (max_link_clock * max_lanes * 8) / 10;
167}
168
c19de8eb 169static enum drm_mode_status
a4fc5ed6
KP		 170intel_dp_mode_valid(struct drm_connector *connector,
171 struct drm_display_mode *mode)
172{
df0e9248 173 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 174 struct intel_connector *intel_connector = to_intel_connector(connector);
175 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 176 int target_clock = mode->clock;
177 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 178
dd06f90e
JN		 179 if (is_edp(intel_dp) && fixed_mode) {
180 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 181 return MODE_PANEL;
182
dd06f90e 183 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 184 return MODE_PANEL;
03afc4a2
DV		 185
186 target_clock = fixed_mode->clock;
7de56f43
ZY		 187 }
188
36008365 189 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 190 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 191
192 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
193 mode_rate = intel_dp_link_required(target_clock, 18);
194
195 if (mode_rate > max_rate)
c4867936 196 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 197
198 if (mode->clock < 10000)
199 return MODE_CLOCK_LOW;
200
0af78a2b
DV		 201 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
202 return MODE_H_ILLEGAL;
203
a4fc5ed6
KP		 204 return MODE_OK;
205}
206
207static uint32_t
208pack_aux(uint8_t *src, int src_bytes)
209{
210 int i;
211 uint32_t v = 0;
212
213 if (src_bytes > 4)
214 src_bytes = 4;
215 for (i = 0; i < src_bytes; i++)
216 v |= ((uint32_t) src[i]) << ((3-i) * 8);
217 return v;
218}
219
220static void
221unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
222{
223 int i;
224 if (dst_bytes > 4)
225 dst_bytes = 4;
226 for (i = 0; i < dst_bytes; i++)
227 dst[i] = src >> ((3-i) * 8);
228}
229
fb0f8fbf
KP		 230/* hrawclock is 1/4 the FSB frequency */
231static int
232intel_hrawclk(struct drm_device *dev)
233{
234 struct drm_i915_private *dev_priv = dev->dev_private;
235 uint32_t clkcfg;
236
9473c8f4
VP		 237 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
238 if (IS_VALLEYVIEW(dev))
239 return 200;
240
fb0f8fbf
KP		 241 clkcfg = I915_READ(CLKCFG);
242 switch (clkcfg & CLKCFG_FSB_MASK) {
243 case CLKCFG_FSB_400:
244 return 100;
245 case CLKCFG_FSB_533:
246 return 133;
247 case CLKCFG_FSB_667:
248 return 166;
249 case CLKCFG_FSB_800:
250 return 200;
251 case CLKCFG_FSB_1067:
252 return 266;
253 case CLKCFG_FSB_1333:
254 return 333;
255 /* these two are just a guess; one of them might be right */
256 case CLKCFG_FSB_1600:
257 case CLKCFG_FSB_1600_ALT:
258 return 400;
259 default:
260 return 133;
261 }
262}
263
bf13e81b
JN		 264static void
265intel_dp_init_panel_power_sequencer(struct drm_device *dev,
266 struct intel_dp *intel_dp,
267 struct edp_power_seq *out);
268static void
269intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
270 struct intel_dp *intel_dp,
271 struct edp_power_seq *out);
272
273static enum pipe
274vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
275{
276 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
277 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
278 struct drm_device *dev = intel_dig_port->base.base.dev;
279 struct drm_i915_private *dev_priv = dev->dev_private;
280 enum port port = intel_dig_port->port;
281 enum pipe pipe;
282
283 /* modeset should have pipe */
284 if (crtc)
285 return to_intel_crtc(crtc)->pipe;
286
287 /* init time, try to find a pipe with this port selected */
288 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
289 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
290 PANEL_PORT_SELECT_MASK;
291 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
292 return pipe;
293 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
294 return pipe;
295 }
296
297 /* shrug */
298 return PIPE_A;
299}
300
301static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
302{
303 struct drm_device *dev = intel_dp_to_dev(intel_dp);
304
305 if (HAS_PCH_SPLIT(dev))
306 return PCH_PP_CONTROL;
307 else
308 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
309}
310
311static u32 _pp_stat_reg(struct intel_dp *intel_dp)
312{
313 struct drm_device *dev = intel_dp_to_dev(intel_dp);
314
315 if (HAS_PCH_SPLIT(dev))
316 return PCH_PP_STATUS;
317 else
318 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
319}
320
4be73780 321static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 322{
30add22d 323 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 324 struct drm_i915_private *dev_priv = dev->dev_private;
325
bf13e81b 326 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 327}
328
4be73780 329static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 330{
30add22d 331 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 332 struct drm_i915_private *dev_priv = dev->dev_private;
333
efbc20ab
PZ		 334 return !dev_priv->pm.suspended &&
335 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 336}
337
9b984dae
KP		 338static void
339intel_dp_check_edp(struct intel_dp *intel_dp)
340{
30add22d 341 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 342 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 343
9b984dae
KP		 344 if (!is_edp(intel_dp))
345 return;
453c5420 346
4be73780 347 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 348 WARN(1, "eDP powered off while attempting aux channel communication.\n");
349 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 350 I915_READ(_pp_stat_reg(intel_dp)),
351 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 352 }
353}
354
9ee32fea
DV		 355static uint32_t
356intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
357{
358 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
359 struct drm_device *dev = intel_dig_port->base.base.dev;
360 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 361 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 362 uint32_t status;
363 bool done;
364
ef04f00d 365#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 366 if (has_aux_irq)
b18ac466 367 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 368 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 369 else
370 done = wait_for_atomic(C, 10) == 0;
371 if (!done)
372 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
373 has_aux_irq);
374#undef C
375
376 return status;
377}
378
ec5b01dd 379static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 380{
174edf1f
PZ		 381 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
382 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 383
ec5b01dd
DL		 384 /*
385 * The clock divider is based off the hrawclk, and would like to run at
386 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 387 */
ec5b01dd
DL		 388 return index ? 0 : intel_hrawclk(dev) / 2;
389}
390
391static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
392{
393 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
394 struct drm_device *dev = intel_dig_port->base.base.dev;
395
396 if (index)
397 return 0;
398
399 if (intel_dig_port->port == PORT_A) {
400 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 401 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 402 else
b84a1cf8 403 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 404 } else {
405 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
406 }
407}
408
409static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
410{
411 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
412 struct drm_device *dev = intel_dig_port->base.base.dev;
413 struct drm_i915_private *dev_priv = dev->dev_private;
414
415 if (intel_dig_port->port == PORT_A) {
416 if (index)
417 return 0;
418 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 419 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
420 /* Workaround for non-ULT HSW */
bc86625a
CW		 421 switch (index) {
422 case 0: return 63;
423 case 1: return 72;
424 default: return 0;
425 }
ec5b01dd 426 } else {
bc86625a 427 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 428 }
b84a1cf8
RV		 429}
430
ec5b01dd
DL		 431static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
432{
433 return index ? 0 : 100;
434}
435
5ed12a19
DL		 436static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
437 bool has_aux_irq,
438 int send_bytes,
439 uint32_t aux_clock_divider)
440{
441 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
442 struct drm_device *dev = intel_dig_port->base.base.dev;
443 uint32_t precharge, timeout;
444
445 if (IS_GEN6(dev))
446 precharge = 3;
447 else
448 precharge = 5;
449
450 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
451 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
452 else
453 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
454
455 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 456 DP_AUX_CH_CTL_DONE |
5ed12a19 457 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 458 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 459 timeout |
788d4433 460 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 461 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
462 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 463 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 464}
465
b84a1cf8
RV		 466static int
467intel_dp_aux_ch(struct intel_dp *intel_dp,
468 uint8_t *send, int send_bytes,
469 uint8_t *recv, int recv_size)
470{
471 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
472 struct drm_device *dev = intel_dig_port->base.base.dev;
473 struct drm_i915_private *dev_priv = dev->dev_private;
474 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
475 uint32_t ch_data = ch_ctl + 4;
bc86625a 476 uint32_t aux_clock_divider;
b84a1cf8
RV		 477 int i, ret, recv_bytes;
478 uint32_t status;
5ed12a19 479 int try, clock = 0;
4e6b788c 480 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 481 bool vdd;
482
483 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 484
485 /* dp aux is extremely sensitive to irq latency, hence request the
486 * lowest possible wakeup latency and so prevent the cpu from going into
487 * deep sleep states.
488 */
489 pm_qos_update_request(&dev_priv->pm_qos, 0);
490
491 intel_dp_check_edp(intel_dp);
5eb08b69 492
c67a470b
PZ		 493 intel_aux_display_runtime_get(dev_priv);
494
11bee43e
JB		 495 /* Try to wait for any previous AUX channel activity */
496 for (try = 0; try < 3; try++) {
ef04f00d 497 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 498 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
499 break;
500 msleep(1);
501 }
502
503 if (try == 3) {
504 WARN(1, "dp_aux_ch not started status 0x%08x\n",
505 I915_READ(ch_ctl));
9ee32fea
DV		 506 ret = -EBUSY;
507 goto out;
4f7f7b7e
CW		 508 }
509
46a5ae9f
PZ		 510 /* Only 5 data registers! */
511 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
512 ret = -E2BIG;
513 goto out;
514 }
515
ec5b01dd 516 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 517 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
518 has_aux_irq,
519 send_bytes,
520 aux_clock_divider);
5ed12a19 521
bc86625a
CW		 522 /* Must try at least 3 times according to DP spec */
523 for (try = 0; try < 5; try++) {
524 /* Load the send data into the aux channel data registers */
525 for (i = 0; i < send_bytes; i += 4)
526 I915_WRITE(ch_data + i,
527 pack_aux(send + i, send_bytes - i));
528
529 /* Send the command and wait for it to complete */
5ed12a19 530 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 531
532 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
533
534 /* Clear done status and any errors */
535 I915_WRITE(ch_ctl,
536 status |
537 DP_AUX_CH_CTL_DONE |
538 DP_AUX_CH_CTL_TIME_OUT_ERROR |
539 DP_AUX_CH_CTL_RECEIVE_ERROR);
540
541 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
542 DP_AUX_CH_CTL_RECEIVE_ERROR))
543 continue;
544 if (status & DP_AUX_CH_CTL_DONE)
545 break;
546 }
4f7f7b7e 547 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 548 break;
549 }
550
a4fc5ed6 551 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 552 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 553 ret = -EBUSY;
554 goto out;
a4fc5ed6
KP		 555 }
556
557 /* Check for timeout or receive error.
558 * Timeouts occur when the sink is not connected
559 */
a5b3da54 560 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 561 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 562 ret = -EIO;
563 goto out;
a5b3da54 564 }
1ae8c0a5
KP		 565
566 /* Timeouts occur when the device isn't connected, so they're
567 * "normal" -- don't fill the kernel log with these */
a5b3da54 568 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 569 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 570 ret = -ETIMEDOUT;
571 goto out;
a4fc5ed6
KP		 572 }
573
574 /* Unload any bytes sent back from the other side */
575 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
576 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 577 if (recv_bytes > recv_size)
578 recv_bytes = recv_size;
0206e353 579
4f7f7b7e
CW		 580 for (i = 0; i < recv_bytes; i += 4)
581 unpack_aux(I915_READ(ch_data + i),
582 recv + i, recv_bytes - i);
a4fc5ed6 583
9ee32fea
DV		 584 ret = recv_bytes;
585out:
586 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 587 intel_aux_display_runtime_put(dev_priv);
9ee32fea 588
884f19e9
JN		 589 if (vdd)
590 edp_panel_vdd_off(intel_dp, false);
591
9ee32fea 592 return ret;
a4fc5ed6
KP		 593}
594
a6c8aff0
JN		 595#define BARE_ADDRESS_SIZE 3
596#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 597static ssize_t
598intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 599{
9d1a1031
JN		 600 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
601 uint8_t txbuf[20], rxbuf[20];
602 size_t txsize, rxsize;
a4fc5ed6 603 int ret;
a4fc5ed6 604
9d1a1031
JN		 605 txbuf[0] = msg->request << 4;
606 txbuf[1] = msg->address >> 8;
607 txbuf[2] = msg->address & 0xff;
608 txbuf[3] = msg->size - 1;
46a5ae9f 609
9d1a1031
JN		 610 switch (msg->request & ~DP_AUX_I2C_MOT) {
611 case DP_AUX_NATIVE_WRITE:
612 case DP_AUX_I2C_WRITE:
a6c8aff0 613 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 614 rxsize = 1;
f51a44b9 615
9d1a1031
JN		 616 if (WARN_ON(txsize > 20))
617 return -E2BIG;
a4fc5ed6 618
9d1a1031 619 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 620
9d1a1031
JN		 621 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
622 if (ret > 0) {
623 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 624
9d1a1031
JN		 625 /* Return payload size. */
626 ret = msg->size;
627 }
628 break;
46a5ae9f 629
9d1a1031
JN		 630 case DP_AUX_NATIVE_READ:
631 case DP_AUX_I2C_READ:
a6c8aff0 632 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 633 rxsize = msg->size + 1;
a4fc5ed6 634
9d1a1031
JN		 635 if (WARN_ON(rxsize > 20))
636 return -E2BIG;
a4fc5ed6 637
9d1a1031
JN		 638 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
639 if (ret > 0) {
640 msg->reply = rxbuf[0] >> 4;
641 /*
642 * Assume happy day, and copy the data. The caller is
643 * expected to check msg->reply before touching it.
644 *
645 * Return payload size.
646 */
647 ret--;
648 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 649 }
9d1a1031
JN		 650 break;
651
652 default:
653 ret = -EINVAL;
654 break;
a4fc5ed6 655 }
f51a44b9 656
9d1a1031 657 return ret;
a4fc5ed6
KP		 658}
659
9d1a1031
JN		 660static void
661intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
662{
663 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 664 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
665 enum port port = intel_dig_port->port;
0b99836f 666 const char *name = NULL;
ab2c0672
DA		 667 int ret;
668
33ad6626
JN		 669 switch (port) {
670 case PORT_A:
671 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 672 name = "DPDDC-A";
ab2c0672 673 break;
33ad6626
JN		 674 case PORT_B:
675 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 676 name = "DPDDC-B";
ab2c0672 677 break;
33ad6626
JN		 678 case PORT_C:
679 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 680 name = "DPDDC-C";
ab2c0672 681 break;
33ad6626
JN		 682 case PORT_D:
683 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 684 name = "DPDDC-D";
33ad6626
JN		 685 break;
686 default:
687 BUG();
ab2c0672
DA		 688 }
689
33ad6626
JN		 690 if (!HAS_DDI(dev))
691 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 692
0b99836f 693 intel_dp->aux.name = name;
9d1a1031
JN		 694 intel_dp->aux.dev = dev->dev;
695 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 696
0b99836f
JN		 697 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
698 connector->base.kdev->kobj.name);
8316f337 699
0b99836f
JN		 700 ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
701 if (ret < 0) {
702 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
703 name, ret);
704 return;
ab2c0672 705 }
8a5e6aeb 706
0b99836f
JN		 707 ret = sysfs_create_link(&connector->base.kdev->kobj,
708 &intel_dp->aux.ddc.dev.kobj,
709 intel_dp->aux.ddc.dev.kobj.name);
710 if (ret < 0) {
711 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
712 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
ab2c0672 713 }
a4fc5ed6
KP		 714}
715
80f65de3
ID		 716static void
717intel_dp_connector_unregister(struct intel_connector *intel_connector)
718{
719 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
720
721 sysfs_remove_link(&intel_connector->base.kdev->kobj,
0b99836f 722 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 723 intel_connector_unregister(intel_connector);
724}
725
c6bb3538
DV		 726static void
727intel_dp_set_clock(struct intel_encoder *encoder,
728 struct intel_crtc_config *pipe_config, int link_bw)
729{
730 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 731 const struct dp_link_dpll *divisor = NULL;
732 int i, count = 0;
c6bb3538
DV		 733
734 if (IS_G4X(dev)) {
9dd4ffdf
CML		 735 divisor = gen4_dpll;
736 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 737 } else if (IS_HASWELL(dev)) {
738 /* Haswell has special-purpose DP DDI clocks. */
739 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 740 divisor = pch_dpll;
741 count = ARRAY_SIZE(pch_dpll);
c6bb3538 742 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 743 divisor = vlv_dpll;
744 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 745 }
9dd4ffdf
CML		 746
747 if (divisor && count) {
748 for (i = 0; i < count; i++) {
749 if (link_bw == divisor[i].link_bw) {
750 pipe_config->dpll = divisor[i].dpll;
751 pipe_config->clock_set = true;
752 break;
753 }
754 }
c6bb3538
DV		 755 }
756}
757
00c09d70 758bool
5bfe2ac0
DV		 759intel_dp_compute_config(struct intel_encoder *encoder,
760 struct intel_crtc_config *pipe_config)
a4fc5ed6 761{
5bfe2ac0 762 struct drm_device *dev = encoder->base.dev;
36008365 763 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 764 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 765 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 766 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 767 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 768 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 769 int lane_count, clock;
56071a20 770 int min_lane_count = 1;
eeb6324d 771 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 772 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 773 int min_clock = 0;
06ea66b6 774 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 775 int bpp, mode_rate;
06ea66b6 776 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 777 int link_avail, link_clock;
a4fc5ed6 778
bc7d38a4 779 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 780 pipe_config->has_pch_encoder = true;
781
03afc4a2 782 pipe_config->has_dp_encoder = true;
a4fc5ed6 783
dd06f90e
JN		 784 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
785 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
786 adjusted_mode);
2dd24552
JB		 787 if (!HAS_PCH_SPLIT(dev))
788 intel_gmch_panel_fitting(intel_crtc, pipe_config,
789 intel_connector->panel.fitting_mode);
790 else
b074cec8
JB		 791 intel_pch_panel_fitting(intel_crtc, pipe_config,
792 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 793 }
794
cb1793ce 795 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 796 return false;
797
083f9560
DV		 798 DRM_DEBUG_KMS("DP link computation with max lane count %i "
799 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 800 max_lane_count, bws[max_clock],
801 adjusted_mode->crtc_clock);
083f9560 802
36008365
DV		 803 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
804 * bpc in between. */
3e7ca985 805 bpp = pipe_config->pipe_bpp;
56071a20
JN		 806 if (is_edp(intel_dp)) {
807 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
808 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
809 dev_priv->vbt.edp_bpp);
810 bpp = dev_priv->vbt.edp_bpp;
811 }
812
813 if (dev_priv->vbt.edp_lanes) {
814 min_lane_count = min(dev_priv->vbt.edp_lanes,
815 max_lane_count);
816 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
817 min_lane_count);
818 }
819
820 if (dev_priv->vbt.edp_rate) {
821 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
822 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
823 bws[min_clock]);
824 }
7984211e 825 }
657445fe 826
36008365 827 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 828 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
829 bpp);
36008365 830
56071a20
JN		 831 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
832 for (clock = min_clock; clock <= max_clock; clock++) {
36008365
DV		 833 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
834 link_avail = intel_dp_max_data_rate(link_clock,
835 lane_count);
836
837 if (mode_rate <= link_avail) {
838 goto found;
839 }
840 }
841 }
842 }
c4867936 843
36008365 844 return false;
3685a8f3 845
36008365 846found:
55bc60db
VS		 847 if (intel_dp->color_range_auto) {
848 /*
849 * See:
850 * CEA-861-E - 5.1 Default Encoding Parameters
851 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
852 */
18316c8c 853 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 854 intel_dp->color_range = DP_COLOR_RANGE_16_235;
855 else
856 intel_dp->color_range = 0;
857 }
858
3685a8f3 859 if (intel_dp->color_range)
50f3b016 860 pipe_config->limited_color_range = true;
a4fc5ed6 861
36008365
DV		 862 intel_dp->link_bw = bws[clock];
863 intel_dp->lane_count = lane_count;
657445fe 864 pipe_config->pipe_bpp = bpp;
ff9a6750 865 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 866
36008365
DV		 867 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
868 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 869 pipe_config->port_clock, bpp);
36008365
DV		 870 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
871 mode_rate, link_avail);
a4fc5ed6 872
03afc4a2 873 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 874 adjusted_mode->crtc_clock,
875 pipe_config->port_clock,
03afc4a2 876 &pipe_config->dp_m_n);
9d1a455b 877
c6bb3538
DV		 878 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
879
03afc4a2 880 return true;
a4fc5ed6
KP		 881}
882
7c62a164 883static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 884{
7c62a164
DV		 885 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
886 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
887 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 888 struct drm_i915_private *dev_priv = dev->dev_private;
889 u32 dpa_ctl;
890
ff9a6750 891 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 892 dpa_ctl = I915_READ(DP_A);
893 dpa_ctl &= ~DP_PLL_FREQ_MASK;
894
ff9a6750 895 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 896 /* For a long time we've carried around a ILK-DevA w/a for the
897 * 160MHz clock. If we're really unlucky, it's still required.
898 */
899 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 900 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 901 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 902 } else {
903 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 904 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 905 }
1ce17038 906
ea9b6006
DV		 907 I915_WRITE(DP_A, dpa_ctl);
908
909 POSTING_READ(DP_A);
910 udelay(500);
911}
912
b934223d 913static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 914{
b934223d 915 struct drm_device *dev = encoder->base.dev;
417e822d 916 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 917 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 918 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 919 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
920 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 921
417e822d 922 /*
1a2eb460 923 * There are four kinds of DP registers:
417e822d
KP		 924 *
925 * IBX PCH
1a2eb460
KP		 926 * SNB CPU
927 * IVB CPU
417e822d
KP		 928 * CPT PCH
929 *
930 * IBX PCH and CPU are the same for almost everything,
931 * except that the CPU DP PLL is configured in this
932 * register
933 *
934 * CPT PCH is quite different, having many bits moved
935 * to the TRANS_DP_CTL register instead. That
936 * configuration happens (oddly) in ironlake_pch_enable
937 */
9c9e7927 938
417e822d
KP		 939 /* Preserve the BIOS-computed detected bit. This is
940 * supposed to be read-only.
941 */
942 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 943
417e822d 944 /* Handle DP bits in common between all three register formats */
417e822d 945 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 946 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 947
e0dac65e
WF		 948 if (intel_dp->has_audio) {
949 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 950 pipe_name(crtc->pipe));
ea5b213a 951 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 952 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 953 }
247d89f6 954
417e822d 955 /* Split out the IBX/CPU vs CPT settings */
32f9d658 956
bc7d38a4 957 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 958 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
959 intel_dp->DP |= DP_SYNC_HS_HIGH;
960 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
961 intel_dp->DP |= DP_SYNC_VS_HIGH;
962 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
963
6aba5b6c 964 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 965 intel_dp->DP |= DP_ENHANCED_FRAMING;
966
7c62a164 967 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 968 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 969 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 970 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 971
972 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
973 intel_dp->DP |= DP_SYNC_HS_HIGH;
974 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
975 intel_dp->DP |= DP_SYNC_VS_HIGH;
976 intel_dp->DP |= DP_LINK_TRAIN_OFF;
977
6aba5b6c 978 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 979 intel_dp->DP |= DP_ENHANCED_FRAMING;
980
7c62a164 981 if (crtc->pipe == 1)
417e822d 982 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 983 } else {
984 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 985 }
ea9b6006 986
bc7d38a4 987 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 988 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 989}
990
ffd6749d
PZ		 991#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
992#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 993
1a5ef5b7
PZ		 994#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
995#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 996
ffd6749d
PZ		 997#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
998#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 999
4be73780 1000static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1001 u32 mask,
1002 u32 value)
bd943159 1003{
30add22d 1004 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1005 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1006 u32 pp_stat_reg, pp_ctrl_reg;
1007
bf13e81b
JN		 1008 pp_stat_reg = _pp_stat_reg(intel_dp);
1009 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1010
99ea7127 1011 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1012 mask, value,
1013 I915_READ(pp_stat_reg),
1014 I915_READ(pp_ctrl_reg));
32ce697c 1015
453c5420 1016 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1017 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1018 I915_READ(pp_stat_reg),
1019 I915_READ(pp_ctrl_reg));
32ce697c 1020 }
54c136d4
CW		 1021
1022 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1023}
32ce697c 1024
4be73780 1025static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1026{
1027 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1028 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1029}
1030
4be73780 1031static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1032{
1033 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1034 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1035}
1036
4be73780 1037static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1038{
1039 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1040
1041 /* When we disable the VDD override bit last we have to do the manual
1042 * wait. */
1043 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1044 intel_dp->panel_power_cycle_delay);
1045
4be73780 1046 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1047}
1048
4be73780 1049static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1050{
1051 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1052 intel_dp->backlight_on_delay);
1053}
1054
4be73780 1055static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1056{
1057 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1058 intel_dp->backlight_off_delay);
1059}
99ea7127 1060
832dd3c1
KP		 1061/* Read the current pp_control value, unlocking the register if it
1062 * is locked
1063 */
1064
453c5420 1065static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1066{
453c5420
JB		 1067 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1068 struct drm_i915_private *dev_priv = dev->dev_private;
1069 u32 control;
832dd3c1 1070
bf13e81b 1071 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1072 control &= ~PANEL_UNLOCK_MASK;
1073 control |= PANEL_UNLOCK_REGS;
1074 return control;
bd943159
KP		 1075}
1076
adddaaf4 1077static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1078{
30add22d 1079 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1080 struct drm_i915_private *dev_priv = dev->dev_private;
1081 u32 pp;
453c5420 1082 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1083 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1084
97af61f5 1085 if (!is_edp(intel_dp))
adddaaf4 1086 return false;
bd943159
KP		 1087
1088 intel_dp->want_panel_vdd = true;
99ea7127 1089
4be73780 1090 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1091 return need_to_disable;
b0665d57 1092
e9cb81a2
PZ		 1093 intel_runtime_pm_get(dev_priv);
1094
b0665d57 1095 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1096
4be73780
DV		 1097 if (!edp_have_panel_power(intel_dp))
1098 wait_panel_power_cycle(intel_dp);
99ea7127 1099
453c5420 1100 pp = ironlake_get_pp_control(intel_dp);
5d613501 1101 pp |= EDP_FORCE_VDD;
ebf33b18 1102
bf13e81b
JN		 1103 pp_stat_reg = _pp_stat_reg(intel_dp);
1104 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1105
1106 I915_WRITE(pp_ctrl_reg, pp);
1107 POSTING_READ(pp_ctrl_reg);
1108 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1109 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1110 /*
1111 * If the panel wasn't on, delay before accessing aux channel
1112 */
4be73780 1113 if (!edp_have_panel_power(intel_dp)) {
bd943159 1114 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1115 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1116 }
adddaaf4
JN		 1117
1118 return need_to_disable;
1119}
1120
b80d6c78 1121void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1122{
1123 if (is_edp(intel_dp)) {
1124 bool vdd = _edp_panel_vdd_on(intel_dp);
1125
1126 WARN(!vdd, "eDP VDD already requested on\n");
1127 }
5d613501
JB		 1128}
1129
4be73780 1130static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1131{
30add22d 1132 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1133 struct drm_i915_private *dev_priv = dev->dev_private;
1134 u32 pp;
453c5420 1135 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1136
a0e99e68
DV		 1137 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1138
4be73780 1139 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
b0665d57
PZ		 1140 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1141
453c5420 1142 pp = ironlake_get_pp_control(intel_dp);
bd943159 1143 pp &= ~EDP_FORCE_VDD;
bd943159 1144
9f08ef59
PZ		 1145 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1146 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1147
1148 I915_WRITE(pp_ctrl_reg, pp);
1149 POSTING_READ(pp_ctrl_reg);
99ea7127 1150
453c5420
JB		 1151 /* Make sure sequencer is idle before allowing subsequent activity */
1152 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1153 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1154
1155 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1156 intel_dp->last_power_cycle = jiffies;
e9cb81a2
PZ		 1157
1158 intel_runtime_pm_put(dev_priv);
bd943159
KP		 1159 }
1160}
5d613501 1161
4be73780 1162static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1163{
1164 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1165 struct intel_dp, panel_vdd_work);
30add22d 1166 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1167
627f7675 1168 mutex_lock(&dev->mode_config.mutex);
4be73780 1169 edp_panel_vdd_off_sync(intel_dp);
627f7675 1170 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1171}
1172
4be73780 1173static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1174{
97af61f5
KP		 1175 if (!is_edp(intel_dp))
1176 return;
5d613501 1177
bd943159 1178 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1179
bd943159
KP		 1180 intel_dp->want_panel_vdd = false;
1181
1182 if (sync) {
4be73780 1183 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1184 } else {
1185 /*
1186 * Queue the timer to fire a long
1187 * time from now (relative to the power down delay)
1188 * to keep the panel power up across a sequence of operations
1189 */
1190 schedule_delayed_work(&intel_dp->panel_vdd_work,
1191 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1192 }
5d613501
JB		 1193}
1194
4be73780 1195void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1196{
30add22d 1197 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1198 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1199 u32 pp;
453c5420 1200 u32 pp_ctrl_reg;
9934c132 1201
97af61f5 1202 if (!is_edp(intel_dp))
bd943159 1203 return;
99ea7127
KP		 1204
1205 DRM_DEBUG_KMS("Turn eDP power on\n");
1206
4be73780 1207 if (edp_have_panel_power(intel_dp)) {
99ea7127 1208 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1209 return;
99ea7127 1210 }
9934c132 1211
4be73780 1212 wait_panel_power_cycle(intel_dp);
37c6c9b0 1213
bf13e81b 1214 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1215 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1216 if (IS_GEN5(dev)) {
1217 /* ILK workaround: disable reset around power sequence */
1218 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1219 I915_WRITE(pp_ctrl_reg, pp);
1220 POSTING_READ(pp_ctrl_reg);
05ce1a49 1221 }
37c6c9b0 1222
1c0ae80a 1223 pp |= POWER_TARGET_ON;
99ea7127
KP		 1224 if (!IS_GEN5(dev))
1225 pp |= PANEL_POWER_RESET;
1226
453c5420
JB		 1227 I915_WRITE(pp_ctrl_reg, pp);
1228 POSTING_READ(pp_ctrl_reg);
9934c132 1229
4be73780 1230 wait_panel_on(intel_dp);
dce56b3c 1231 intel_dp->last_power_on = jiffies;
9934c132 1232
05ce1a49
KP		 1233 if (IS_GEN5(dev)) {
1234 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1235 I915_WRITE(pp_ctrl_reg, pp);
1236 POSTING_READ(pp_ctrl_reg);
05ce1a49 1237 }
9934c132
JB		 1238}
1239
4be73780 1240void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1241{
30add22d 1242 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1243 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1244 u32 pp;
453c5420 1245 u32 pp_ctrl_reg;
9934c132 1246
97af61f5
KP		 1247 if (!is_edp(intel_dp))
1248 return;
37c6c9b0 1249
99ea7127 1250 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1251
4be73780 1252 edp_wait_backlight_off(intel_dp);
dce56b3c 1253
24f3e092
JN		 1254 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1255
453c5420 1256 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1257 /* We need to switch off panel power _and_ force vdd, for otherwise some
1258 * panels get very unhappy and cease to work. */
b3064154
PJ		 1259 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1260 EDP_BLC_ENABLE);
453c5420 1261
bf13e81b 1262 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1263
849e39f5
PZ		 1264 intel_dp->want_panel_vdd = false;
1265
453c5420
JB		 1266 I915_WRITE(pp_ctrl_reg, pp);
1267 POSTING_READ(pp_ctrl_reg);
9934c132 1268
dce56b3c 1269 intel_dp->last_power_cycle = jiffies;
4be73780 1270 wait_panel_off(intel_dp);
849e39f5
PZ		 1271
1272 /* We got a reference when we enabled the VDD. */
1273 intel_runtime_pm_put(dev_priv);
9934c132
JB		 1274}
1275
4be73780 1276void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1277{
da63a9f2
PZ		 1278 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1279 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1280 struct drm_i915_private *dev_priv = dev->dev_private;
1281 u32 pp;
453c5420 1282 u32 pp_ctrl_reg;
32f9d658 1283
f01eca2e
KP		 1284 if (!is_edp(intel_dp))
1285 return;
1286
28c97730 1287 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1288 /*
1289 * If we enable the backlight right away following a panel power
1290 * on, we may see slight flicker as the panel syncs with the eDP
1291 * link. So delay a bit to make sure the image is solid before
1292 * allowing it to appear.
1293 */
4be73780 1294 wait_backlight_on(intel_dp);
453c5420 1295 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1296 pp |= EDP_BLC_ENABLE;
453c5420 1297
bf13e81b 1298 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1299
1300 I915_WRITE(pp_ctrl_reg, pp);
1301 POSTING_READ(pp_ctrl_reg);
035aa3de 1302
752aa88a 1303 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1304}
1305
4be73780 1306void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1307{
30add22d 1308 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1309 struct drm_i915_private *dev_priv = dev->dev_private;
1310 u32 pp;
453c5420 1311 u32 pp_ctrl_reg;
32f9d658 1312
f01eca2e
KP		 1313 if (!is_edp(intel_dp))
1314 return;
1315
752aa88a 1316 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1317
28c97730 1318 DRM_DEBUG_KMS("\n");
453c5420 1319 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1320 pp &= ~EDP_BLC_ENABLE;
453c5420 1321
bf13e81b 1322 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1323
1324 I915_WRITE(pp_ctrl_reg, pp);
1325 POSTING_READ(pp_ctrl_reg);
dce56b3c 1326 intel_dp->last_backlight_off = jiffies;
32f9d658 1327}
a4fc5ed6 1328
2bd2ad64 1329static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1330{
da63a9f2
PZ		 1331 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1332 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1333 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1334 struct drm_i915_private *dev_priv = dev->dev_private;
1335 u32 dpa_ctl;
1336
2bd2ad64
DV		 1337 assert_pipe_disabled(dev_priv,
1338 to_intel_crtc(crtc)->pipe);
1339
d240f20f
JB		 1340 DRM_DEBUG_KMS("\n");
1341 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1342 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1343 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1344
1345 /* We don't adjust intel_dp->DP while tearing down the link, to
1346 * facilitate link retraining (e.g. after hotplug). Hence clear all
1347 * enable bits here to ensure that we don't enable too much. */
1348 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1349 intel_dp->DP |= DP_PLL_ENABLE;
1350 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1351 POSTING_READ(DP_A);
1352 udelay(200);
d240f20f
JB		 1353}
1354
2bd2ad64 1355static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1356{
da63a9f2
PZ		 1357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1358 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1359 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1360 struct drm_i915_private *dev_priv = dev->dev_private;
1361 u32 dpa_ctl;
1362
2bd2ad64
DV		 1363 assert_pipe_disabled(dev_priv,
1364 to_intel_crtc(crtc)->pipe);
1365
d240f20f 1366 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1367 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1368 "dp pll off, should be on\n");
1369 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1370
1371 /* We can't rely on the value tracked for the DP register in
1372 * intel_dp->DP because link_down must not change that (otherwise link
1373 * re-training will fail. */
298b0b39 1374 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1375 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1376 POSTING_READ(DP_A);
d240f20f
JB		 1377 udelay(200);
1378}
1379
c7ad3810 1380/* If the sink supports it, try to set the power state appropriately */
c19b0669 1381void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1382{
1383 int ret, i;
1384
1385 /* Should have a valid DPCD by this point */
1386 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1387 return;
1388
1389 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1390 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1391 DP_SET_POWER_D3);
c7ad3810
JB		 1392 if (ret != 1)
1393 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1394 } else {
1395 /*
1396 * When turning on, we need to retry for 1ms to give the sink
1397 * time to wake up.
1398 */
1399 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1400 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1401 DP_SET_POWER_D0);
c7ad3810
JB		 1402 if (ret == 1)
1403 break;
1404 msleep(1);
1405 }
1406 }
1407}
1408
19d8fe15
DV		 1409static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1410 enum pipe *pipe)
d240f20f 1411{
19d8fe15 1412 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1413 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1414 struct drm_device *dev = encoder->base.dev;
1415 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1416 enum intel_display_power_domain power_domain;
1417 u32 tmp;
1418
1419 power_domain = intel_display_port_power_domain(encoder);
1420 if (!intel_display_power_enabled(dev_priv, power_domain))
1421 return false;
1422
1423 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1424
1425 if (!(tmp & DP_PORT_EN))
1426 return false;
1427
bc7d38a4 1428 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1429 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1430 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1431 *pipe = PORT_TO_PIPE(tmp);
1432 } else {
1433 u32 trans_sel;
1434 u32 trans_dp;
1435 int i;
1436
1437 switch (intel_dp->output_reg) {
1438 case PCH_DP_B:
1439 trans_sel = TRANS_DP_PORT_SEL_B;
1440 break;
1441 case PCH_DP_C:
1442 trans_sel = TRANS_DP_PORT_SEL_C;
1443 break;
1444 case PCH_DP_D:
1445 trans_sel = TRANS_DP_PORT_SEL_D;
1446 break;
1447 default:
1448 return true;
1449 }
1450
1451 for_each_pipe(i) {
1452 trans_dp = I915_READ(TRANS_DP_CTL(i));
1453 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1454 *pipe = i;
1455 return true;
1456 }
1457 }
19d8fe15 1458
4a0833ec
DV		 1459 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1460 intel_dp->output_reg);
1461 }
d240f20f 1462
19d8fe15
DV		 1463 return true;
1464}
d240f20f 1465
045ac3b5
JB		 1466static void intel_dp_get_config(struct intel_encoder *encoder,
1467 struct intel_crtc_config *pipe_config)
1468{
1469 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1470 u32 tmp, flags = 0;
63000ef6
XZ		 1471 struct drm_device *dev = encoder->base.dev;
1472 struct drm_i915_private *dev_priv = dev->dev_private;
1473 enum port port = dp_to_dig_port(intel_dp)->port;
1474 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1475 int dotclock;
045ac3b5 1476
63000ef6
XZ		 1477 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1478 tmp = I915_READ(intel_dp->output_reg);
1479 if (tmp & DP_SYNC_HS_HIGH)
1480 flags |= DRM_MODE_FLAG_PHSYNC;
1481 else
1482 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1483
63000ef6
XZ		 1484 if (tmp & DP_SYNC_VS_HIGH)
1485 flags |= DRM_MODE_FLAG_PVSYNC;
1486 else
1487 flags |= DRM_MODE_FLAG_NVSYNC;
1488 } else {
1489 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1490 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1491 flags |= DRM_MODE_FLAG_PHSYNC;
1492 else
1493 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1494
63000ef6
XZ		 1495 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1496 flags |= DRM_MODE_FLAG_PVSYNC;
1497 else
1498 flags |= DRM_MODE_FLAG_NVSYNC;
1499 }
045ac3b5
JB		 1500
1501 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1502
eb14cb74
VS		 1503 pipe_config->has_dp_encoder = true;
1504
1505 intel_dp_get_m_n(crtc, pipe_config);
1506
18442d08 1507 if (port == PORT_A) {
f1f644dc
JB		 1508 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1509 pipe_config->port_clock = 162000;
1510 else
1511 pipe_config->port_clock = 270000;
1512 }
18442d08
VS		 1513
1514 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1515 &pipe_config->dp_m_n);
1516
1517 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1518 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1519
241bfc38 1520 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1521
c6cd2ee2
JN		 1522 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1523 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1524 /*
1525 * This is a big fat ugly hack.
1526 *
1527 * Some machines in UEFI boot mode provide us a VBT that has 18
1528 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1529 * unknown we fail to light up. Yet the same BIOS boots up with
1530 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1531 * max, not what it tells us to use.
1532 *
1533 * Note: This will still be broken if the eDP panel is not lit
1534 * up by the BIOS, and thus we can't get the mode at module
1535 * load.
1536 */
1537 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1538 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1539 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1540 }
045ac3b5
JB		 1541}
1542
a031d709 1543static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1544{
a031d709
RV		 1545 struct drm_i915_private *dev_priv = dev->dev_private;
1546
1547 return dev_priv->psr.sink_support;
2293bb5c
SK		 1548}
1549
2b28bb1b
RV		 1550static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1551{
1552 struct drm_i915_private *dev_priv = dev->dev_private;
1553
18b5992c 1554 if (!HAS_PSR(dev))
2b28bb1b
RV		 1555 return false;
1556
18b5992c 1557 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1558}
1559
1560static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1561 struct edp_vsc_psr *vsc_psr)
1562{
1563 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1564 struct drm_device *dev = dig_port->base.base.dev;
1565 struct drm_i915_private *dev_priv = dev->dev_private;
1566 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1567 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1568 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1569 uint32_t *data = (uint32_t *) vsc_psr;
1570 unsigned int i;
1571
1572 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1573 the video DIP being updated before program video DIP data buffer
1574 registers for DIP being updated. */
1575 I915_WRITE(ctl_reg, 0);
1576 POSTING_READ(ctl_reg);
1577
1578 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1579 if (i < sizeof(struct edp_vsc_psr))
1580 I915_WRITE(data_reg + i, *data++);
1581 else
1582 I915_WRITE(data_reg + i, 0);
1583 }
1584
1585 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1586 POSTING_READ(ctl_reg);
1587}
1588
1589static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1590{
1591 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1592 struct drm_i915_private *dev_priv = dev->dev_private;
1593 struct edp_vsc_psr psr_vsc;
1594
1595 if (intel_dp->psr_setup_done)
1596 return;
1597
1598 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1599 memset(&psr_vsc, 0, sizeof(psr_vsc));
1600 psr_vsc.sdp_header.HB0 = 0;
1601 psr_vsc.sdp_header.HB1 = 0x7;
1602 psr_vsc.sdp_header.HB2 = 0x2;
1603 psr_vsc.sdp_header.HB3 = 0x8;
1604 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1605
1606 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1607 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1608 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1609
1610 intel_dp->psr_setup_done = true;
1611}
1612
1613static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1614{
1615 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1616 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1617 uint32_t aux_clock_divider;
2b28bb1b
RV		 1618 int precharge = 0x3;
1619 int msg_size = 5; /* Header(4) + Message(1) */
1620
ec5b01dd
DL		 1621 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1622
2b28bb1b
RV		 1623 /* Enable PSR in sink */
1624 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
9d1a1031
JN		 1625 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1626 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1627 else
9d1a1031
JN		 1628 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1629 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1630
1631 /* Setup AUX registers */
18b5992c
BW		 1632 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1633 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1634 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1635 DP_AUX_CH_CTL_TIME_OUT_400us |
1636 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1637 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1638 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1639}
1640
1641static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1642{
1643 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1644 struct drm_i915_private *dev_priv = dev->dev_private;
1645 uint32_t max_sleep_time = 0x1f;
1646 uint32_t idle_frames = 1;
1647 uint32_t val = 0x0;
ed8546ac 1648 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1649
1650 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1651 val |= EDP_PSR_LINK_STANDBY;
1652 val |= EDP_PSR_TP2_TP3_TIME_0us;
1653 val |= EDP_PSR_TP1_TIME_0us;
1654 val |= EDP_PSR_SKIP_AUX_EXIT;
1655 } else
1656 val |= EDP_PSR_LINK_DISABLE;
1657
18b5992c 1658 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1659 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1660 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1661 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1662 EDP_PSR_ENABLE);
1663}
1664
3f51e471
RV		 1665static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1666{
1667 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1668 struct drm_device *dev = dig_port->base.base.dev;
1669 struct drm_i915_private *dev_priv = dev->dev_private;
1670 struct drm_crtc *crtc = dig_port->base.base.crtc;
1671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f4510a27 1672 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1673 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1674
a031d709
RV		 1675 dev_priv->psr.source_ok = false;
1676
18b5992c 1677 if (!HAS_PSR(dev)) {
3f51e471 1678 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1679 return false;
1680 }
1681
1682 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1683 (dig_port->port != PORT_A)) {
1684 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1685 return false;
1686 }
1687
d330a953 1688 if (!i915.enable_psr) {
105b7c11 1689 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1690 return false;
1691 }
1692
cd234b0b
CW		 1693 crtc = dig_port->base.base.crtc;
1694 if (crtc == NULL) {
1695 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1696 return false;
1697 }
1698
1699 intel_crtc = to_intel_crtc(crtc);
20ddf665 1700 if (!intel_crtc_active(crtc)) {
3f51e471 1701 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1702 return false;
1703 }
1704
f4510a27 1705 obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1706 if (obj->tiling_mode != I915_TILING_X ||
1707 obj->fence_reg == I915_FENCE_REG_NONE) {
1708 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1709 return false;
1710 }
1711
1712 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1713 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1714 return false;
1715 }
1716
1717 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1718 S3D_ENABLE) {
1719 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1720 return false;
1721 }
1722
ca73b4f0 1723 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1724 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1725 return false;
1726 }
1727
a031d709 1728 dev_priv->psr.source_ok = true;
3f51e471
RV		 1729 return true;
1730}
1731
3d739d92 1732static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1733{
1734 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1735
3f51e471
RV		 1736 if (!intel_edp_psr_match_conditions(intel_dp) ||
1737 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1738 return;
1739
1740 /* Setup PSR once */
1741 intel_edp_psr_setup(intel_dp);
1742
1743 /* Enable PSR on the panel */
1744 intel_edp_psr_enable_sink(intel_dp);
1745
1746 /* Enable PSR on the host */
1747 intel_edp_psr_enable_source(intel_dp);
1748}
1749
3d739d92
RV		 1750void intel_edp_psr_enable(struct intel_dp *intel_dp)
1751{
1752 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1753
1754 if (intel_edp_psr_match_conditions(intel_dp) &&
1755 !intel_edp_is_psr_enabled(dev))
1756 intel_edp_psr_do_enable(intel_dp);
1757}
1758
2b28bb1b
RV		 1759void intel_edp_psr_disable(struct intel_dp *intel_dp)
1760{
1761 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1762 struct drm_i915_private *dev_priv = dev->dev_private;
1763
1764 if (!intel_edp_is_psr_enabled(dev))
1765 return;
1766
18b5992c
BW		 1767 I915_WRITE(EDP_PSR_CTL(dev),
1768 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1769
1770 /* Wait till PSR is idle */
18b5992c 1771 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1772 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1773 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1774}
1775
3d739d92
RV		 1776void intel_edp_psr_update(struct drm_device *dev)
1777{
1778 struct intel_encoder *encoder;
1779 struct intel_dp *intel_dp = NULL;
1780
1781 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1782 if (encoder->type == INTEL_OUTPUT_EDP) {
1783 intel_dp = enc_to_intel_dp(&encoder->base);
1784
a031d709 1785 if (!is_edp_psr(dev))
3d739d92
RV		 1786 return;
1787
1788 if (!intel_edp_psr_match_conditions(intel_dp))
1789 intel_edp_psr_disable(intel_dp);
1790 else
1791 if (!intel_edp_is_psr_enabled(dev))
1792 intel_edp_psr_do_enable(intel_dp);
1793 }
1794}
1795
e8cb4558 1796static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1797{
e8cb4558 1798 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1799 enum port port = dp_to_dig_port(intel_dp)->port;
1800 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1801
1802 /* Make sure the panel is off before trying to change the mode. But also
1803 * ensure that we have vdd while we switch off the panel. */
24f3e092 1804 intel_edp_panel_vdd_on(intel_dp);
4be73780 1805 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1806 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1807 intel_edp_panel_off(intel_dp);
3739850b
DV		 1808
1809 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1810 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1811 intel_dp_link_down(intel_dp);
d240f20f
JB		 1812}
1813
2bd2ad64 1814static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1815{
2bd2ad64 1816 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1817 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1818 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1819
982a3866 1820 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1821 intel_dp_link_down(intel_dp);
b2634017
JB		 1822 if (!IS_VALLEYVIEW(dev))
1823 ironlake_edp_pll_off(intel_dp);
3739850b 1824 }
2bd2ad64
DV		 1825}
1826
e8cb4558 1827static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1828{
e8cb4558
DV		 1829 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1830 struct drm_device *dev = encoder->base.dev;
1831 struct drm_i915_private *dev_priv = dev->dev_private;
1832 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1833
0c33d8d7
DV		 1834 if (WARN_ON(dp_reg & DP_PORT_EN))
1835 return;
5d613501 1836
24f3e092 1837 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 1838 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1839 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1840 intel_edp_panel_on(intel_dp);
1841 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1842 intel_dp_complete_link_train(intel_dp);
3ab9c637 1843 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1844}
89b667f8 1845
ecff4f3b
JN		 1846static void g4x_enable_dp(struct intel_encoder *encoder)
1847{
828f5c6e
JN		 1848 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1849
ecff4f3b 1850 intel_enable_dp(encoder);
4be73780 1851 intel_edp_backlight_on(intel_dp);
ab1f90f9 1852}
89b667f8 1853
ab1f90f9
JN		 1854static void vlv_enable_dp(struct intel_encoder *encoder)
1855{
828f5c6e
JN		 1856 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1857
4be73780 1858 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1859}
1860
ecff4f3b 1861static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1862{
1863 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1864 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1865
1866 if (dport->port == PORT_A)
1867 ironlake_edp_pll_on(intel_dp);
1868}
1869
1870static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1871{
2bd2ad64 1872 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1873 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1874 struct drm_device *dev = encoder->base.dev;
89b667f8 1875 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1876 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1877 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1878 int pipe = intel_crtc->pipe;
bf13e81b 1879 struct edp_power_seq power_seq;
ab1f90f9 1880 u32 val;
a4fc5ed6 1881
ab1f90f9 1882 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1883
ab3c759a 1884 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1885 val = 0;
1886 if (pipe)
1887 val |= (1<<21);
1888 else
1889 val &= ~(1<<21);
1890 val |= 0x001000c4;
ab3c759a
CML		 1891 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1892 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1893 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1894
ab1f90f9
JN		 1895 mutex_unlock(&dev_priv->dpio_lock);
1896
2cac613b
ID		 1897 if (is_edp(intel_dp)) {
1898 /* init power sequencer on this pipe and port */
1899 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1900 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1901 &power_seq);
1902 }
bf13e81b 1903
ab1f90f9
JN		 1904 intel_enable_dp(encoder);
1905
e4607fcf 1906 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1907}
1908
ecff4f3b 1909static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1910{
1911 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1912 struct drm_device *dev = encoder->base.dev;
1913 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1914 struct intel_crtc *intel_crtc =
1915 to_intel_crtc(encoder->base.crtc);
e4607fcf 1916 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1917 int pipe = intel_crtc->pipe;
89b667f8 1918
89b667f8 1919 /* Program Tx lane resets to default */
0980a60f 1920 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 1921 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 1922 DPIO_PCS_TX_LANE2_RESET |
1923 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 1924 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 1925 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1926 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1927 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1928 DPIO_PCS_CLK_SOFT_RESET);
1929
1930 /* Fix up inter-pair skew failure */
ab3c759a
CML		 1931 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1932 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1933 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 1934 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1935}
1936
1937/*
df0c237d
JB		 1938 * Native read with retry for link status and receiver capability reads for
1939 * cases where the sink may still be asleep.
9d1a1031
JN		 1940 *
1941 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
1942 * supposed to retry 3 times per the spec.
a4fc5ed6 1943 */
9d1a1031
JN		 1944static ssize_t
1945intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
1946 void *buffer, size_t size)
a4fc5ed6 1947{
9d1a1031
JN		 1948 ssize_t ret;
1949 int i;
61da5fab 1950
61da5fab 1951 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1952 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
1953 if (ret == size)
1954 return ret;
61da5fab
JB		 1955 msleep(1);
1956 }
a4fc5ed6 1957
9d1a1031 1958 return ret;
a4fc5ed6
KP		 1959}
1960
1961/*
1962 * Fetch AUX CH registers 0x202 - 0x207 which contain
1963 * link status information
1964 */
1965static bool
93f62dad 1966intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1967{
9d1a1031
JN		 1968 return intel_dp_dpcd_read_wake(&intel_dp->aux,
1969 DP_LANE0_1_STATUS,
1970 link_status,
1971 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 1972}
1973
a4fc5ed6
KP		 1974/*
1975 * These are source-specific values; current Intel hardware supports
1976 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1977 */
a4fc5ed6
KP		 1978
1979static uint8_t
1a2eb460 1980intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1981{
30add22d 1982 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1983 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1984
8f93f4f1 1985 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 1986 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1987 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1988 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1989 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1990 return DP_TRAIN_VOLTAGE_SWING_1200;
1991 else
1992 return DP_TRAIN_VOLTAGE_SWING_800;
1993}
1994
1995static uint8_t
1996intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1997{
30add22d 1998 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1999 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2000
8f93f4f1
PZ		 2001 if (IS_BROADWELL(dev)) {
2002 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2003 case DP_TRAIN_VOLTAGE_SWING_400:
2004 case DP_TRAIN_VOLTAGE_SWING_600:
2005 return DP_TRAIN_PRE_EMPHASIS_6;
2006 case DP_TRAIN_VOLTAGE_SWING_800:
2007 return DP_TRAIN_PRE_EMPHASIS_3_5;
2008 case DP_TRAIN_VOLTAGE_SWING_1200:
2009 default:
2010 return DP_TRAIN_PRE_EMPHASIS_0;
2011 }
2012 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 2013 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2014 case DP_TRAIN_VOLTAGE_SWING_400:
2015 return DP_TRAIN_PRE_EMPHASIS_9_5;
2016 case DP_TRAIN_VOLTAGE_SWING_600:
2017 return DP_TRAIN_PRE_EMPHASIS_6;
2018 case DP_TRAIN_VOLTAGE_SWING_800:
2019 return DP_TRAIN_PRE_EMPHASIS_3_5;
2020 case DP_TRAIN_VOLTAGE_SWING_1200:
2021 default:
2022 return DP_TRAIN_PRE_EMPHASIS_0;
2023 }
e2fa6fba
P		 2024 } else if (IS_VALLEYVIEW(dev)) {
2025 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2026 case DP_TRAIN_VOLTAGE_SWING_400:
2027 return DP_TRAIN_PRE_EMPHASIS_9_5;
2028 case DP_TRAIN_VOLTAGE_SWING_600:
2029 return DP_TRAIN_PRE_EMPHASIS_6;
2030 case DP_TRAIN_VOLTAGE_SWING_800:
2031 return DP_TRAIN_PRE_EMPHASIS_3_5;
2032 case DP_TRAIN_VOLTAGE_SWING_1200:
2033 default:
2034 return DP_TRAIN_PRE_EMPHASIS_0;
2035 }
bc7d38a4 2036 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2037 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2038 case DP_TRAIN_VOLTAGE_SWING_400:
2039 return DP_TRAIN_PRE_EMPHASIS_6;
2040 case DP_TRAIN_VOLTAGE_SWING_600:
2041 case DP_TRAIN_VOLTAGE_SWING_800:
2042 return DP_TRAIN_PRE_EMPHASIS_3_5;
2043 default:
2044 return DP_TRAIN_PRE_EMPHASIS_0;
2045 }
2046 } else {
2047 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2048 case DP_TRAIN_VOLTAGE_SWING_400:
2049 return DP_TRAIN_PRE_EMPHASIS_6;
2050 case DP_TRAIN_VOLTAGE_SWING_600:
2051 return DP_TRAIN_PRE_EMPHASIS_6;
2052 case DP_TRAIN_VOLTAGE_SWING_800:
2053 return DP_TRAIN_PRE_EMPHASIS_3_5;
2054 case DP_TRAIN_VOLTAGE_SWING_1200:
2055 default:
2056 return DP_TRAIN_PRE_EMPHASIS_0;
2057 }
a4fc5ed6
KP		 2058 }
2059}
2060
e2fa6fba
P		 2061static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2062{
2063 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2064 struct drm_i915_private *dev_priv = dev->dev_private;
2065 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2066 struct intel_crtc *intel_crtc =
2067 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2068 unsigned long demph_reg_value, preemph_reg_value,
2069 uniqtranscale_reg_value;
2070 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2071 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2072 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2073
2074 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2075 case DP_TRAIN_PRE_EMPHASIS_0:
2076 preemph_reg_value = 0x0004000;
2077 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2078 case DP_TRAIN_VOLTAGE_SWING_400:
2079 demph_reg_value = 0x2B405555;
2080 uniqtranscale_reg_value = 0x552AB83A;
2081 break;
2082 case DP_TRAIN_VOLTAGE_SWING_600:
2083 demph_reg_value = 0x2B404040;
2084 uniqtranscale_reg_value = 0x5548B83A;
2085 break;
2086 case DP_TRAIN_VOLTAGE_SWING_800:
2087 demph_reg_value = 0x2B245555;
2088 uniqtranscale_reg_value = 0x5560B83A;
2089 break;
2090 case DP_TRAIN_VOLTAGE_SWING_1200:
2091 demph_reg_value = 0x2B405555;
2092 uniqtranscale_reg_value = 0x5598DA3A;
2093 break;
2094 default:
2095 return 0;
2096 }
2097 break;
2098 case DP_TRAIN_PRE_EMPHASIS_3_5:
2099 preemph_reg_value = 0x0002000;
2100 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2101 case DP_TRAIN_VOLTAGE_SWING_400:
2102 demph_reg_value = 0x2B404040;
2103 uniqtranscale_reg_value = 0x5552B83A;
2104 break;
2105 case DP_TRAIN_VOLTAGE_SWING_600:
2106 demph_reg_value = 0x2B404848;
2107 uniqtranscale_reg_value = 0x5580B83A;
2108 break;
2109 case DP_TRAIN_VOLTAGE_SWING_800:
2110 demph_reg_value = 0x2B404040;
2111 uniqtranscale_reg_value = 0x55ADDA3A;
2112 break;
2113 default:
2114 return 0;
2115 }
2116 break;
2117 case DP_TRAIN_PRE_EMPHASIS_6:
2118 preemph_reg_value = 0x0000000;
2119 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2120 case DP_TRAIN_VOLTAGE_SWING_400:
2121 demph_reg_value = 0x2B305555;
2122 uniqtranscale_reg_value = 0x5570B83A;
2123 break;
2124 case DP_TRAIN_VOLTAGE_SWING_600:
2125 demph_reg_value = 0x2B2B4040;
2126 uniqtranscale_reg_value = 0x55ADDA3A;
2127 break;
2128 default:
2129 return 0;
2130 }
2131 break;
2132 case DP_TRAIN_PRE_EMPHASIS_9_5:
2133 preemph_reg_value = 0x0006000;
2134 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2135 case DP_TRAIN_VOLTAGE_SWING_400:
2136 demph_reg_value = 0x1B405555;
2137 uniqtranscale_reg_value = 0x55ADDA3A;
2138 break;
2139 default:
2140 return 0;
2141 }
2142 break;
2143 default:
2144 return 0;
2145 }
2146
0980a60f 2147 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2148 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2149 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2150 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2151 uniqtranscale_reg_value);
ab3c759a
CML		 2152 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2153 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2154 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2155 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2156 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2157
2158 return 0;
2159}
2160
a4fc5ed6 2161static void
0301b3ac
JN		 2162intel_get_adjust_train(struct intel_dp *intel_dp,
2163 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2164{
2165 uint8_t v = 0;
2166 uint8_t p = 0;
2167 int lane;
1a2eb460
KP		 2168 uint8_t voltage_max;
2169 uint8_t preemph_max;
a4fc5ed6 2170
33a34e4e 2171 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2172 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2173 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2174
2175 if (this_v > v)
2176 v = this_v;
2177 if (this_p > p)
2178 p = this_p;
2179 }
2180
1a2eb460 2181 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2182 if (v >= voltage_max)
2183 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2184
1a2eb460
KP		 2185 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2186 if (p >= preemph_max)
2187 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2188
2189 for (lane = 0; lane < 4; lane++)
33a34e4e 2190 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2191}
2192
2193static uint32_t
f0a3424e 2194intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2195{
3cf2efb1 2196 uint32_t signal_levels = 0;
a4fc5ed6 2197
3cf2efb1 2198 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2199 case DP_TRAIN_VOLTAGE_SWING_400:
2200 default:
2201 signal_levels |= DP_VOLTAGE_0_4;
2202 break;
2203 case DP_TRAIN_VOLTAGE_SWING_600:
2204 signal_levels |= DP_VOLTAGE_0_6;
2205 break;
2206 case DP_TRAIN_VOLTAGE_SWING_800:
2207 signal_levels |= DP_VOLTAGE_0_8;
2208 break;
2209 case DP_TRAIN_VOLTAGE_SWING_1200:
2210 signal_levels |= DP_VOLTAGE_1_2;
2211 break;
2212 }
3cf2efb1 2213 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2214 case DP_TRAIN_PRE_EMPHASIS_0:
2215 default:
2216 signal_levels |= DP_PRE_EMPHASIS_0;
2217 break;
2218 case DP_TRAIN_PRE_EMPHASIS_3_5:
2219 signal_levels |= DP_PRE_EMPHASIS_3_5;
2220 break;
2221 case DP_TRAIN_PRE_EMPHASIS_6:
2222 signal_levels |= DP_PRE_EMPHASIS_6;
2223 break;
2224 case DP_TRAIN_PRE_EMPHASIS_9_5:
2225 signal_levels |= DP_PRE_EMPHASIS_9_5;
2226 break;
2227 }
2228 return signal_levels;
2229}
2230
e3421a18
ZW		 2231/* Gen6's DP voltage swing and pre-emphasis control */
2232static uint32_t
2233intel_gen6_edp_signal_levels(uint8_t train_set)
2234{
3c5a62b5
YL		 2235 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2236 DP_TRAIN_PRE_EMPHASIS_MASK);
2237 switch (signal_levels) {
e3421a18 2238 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2239 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2240 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2241 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2242 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2243 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2244 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2245 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2246 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2247 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2248 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2249 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2250 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2251 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2252 default:
3c5a62b5
YL		 2253 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2254 "0x%x\n", signal_levels);
2255 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2256 }
2257}
2258
1a2eb460
KP		 2259/* Gen7's DP voltage swing and pre-emphasis control */
2260static uint32_t
2261intel_gen7_edp_signal_levels(uint8_t train_set)
2262{
2263 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2264 DP_TRAIN_PRE_EMPHASIS_MASK);
2265 switch (signal_levels) {
2266 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2267 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2268 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2269 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2270 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2271 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2272
2273 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2274 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2275 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2276 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2277
2278 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2279 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2280 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2281 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2282
2283 default:
2284 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2285 "0x%x\n", signal_levels);
2286 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2287 }
2288}
2289
d6c0d722
PZ		 2290/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2291static uint32_t
f0a3424e 2292intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2293{
d6c0d722
PZ		 2294 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2295 DP_TRAIN_PRE_EMPHASIS_MASK);
2296 switch (signal_levels) {
2297 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2298 return DDI_BUF_EMP_400MV_0DB_HSW;
2299 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2300 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2301 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2302 return DDI_BUF_EMP_400MV_6DB_HSW;
2303 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2304 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2305
d6c0d722
PZ		 2306 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2307 return DDI_BUF_EMP_600MV_0DB_HSW;
2308 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2309 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2310 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2311 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2312
d6c0d722
PZ		 2313 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2314 return DDI_BUF_EMP_800MV_0DB_HSW;
2315 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2316 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2317 default:
2318 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2319 "0x%x\n", signal_levels);
2320 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2321 }
a4fc5ed6
KP		 2322}
2323
8f93f4f1
PZ		 2324static uint32_t
2325intel_bdw_signal_levels(uint8_t train_set)
2326{
2327 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2328 DP_TRAIN_PRE_EMPHASIS_MASK);
2329 switch (signal_levels) {
2330 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2331 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2332 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2333 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2334 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2335 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2336
2337 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2338 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2339 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2340 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2341 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2342 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2343
2344 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2345 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2346 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2347 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2348
2349 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2350 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2351
2352 default:
2353 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2354 "0x%x\n", signal_levels);
2355 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2356 }
2357}
2358
f0a3424e
PZ		 2359/* Properly updates "DP" with the correct signal levels. */
2360static void
2361intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2362{
2363 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2364 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2365 struct drm_device *dev = intel_dig_port->base.base.dev;
2366 uint32_t signal_levels, mask;
2367 uint8_t train_set = intel_dp->train_set[0];
2368
8f93f4f1
PZ		 2369 if (IS_BROADWELL(dev)) {
2370 signal_levels = intel_bdw_signal_levels(train_set);
2371 mask = DDI_BUF_EMP_MASK;
2372 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2373 signal_levels = intel_hsw_signal_levels(train_set);
2374 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2375 } else if (IS_VALLEYVIEW(dev)) {
2376 signal_levels = intel_vlv_signal_levels(intel_dp);
2377 mask = 0;
bc7d38a4 2378 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2379 signal_levels = intel_gen7_edp_signal_levels(train_set);
2380 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2381 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2382 signal_levels = intel_gen6_edp_signal_levels(train_set);
2383 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2384 } else {
2385 signal_levels = intel_gen4_signal_levels(train_set);
2386 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2387 }
2388
2389 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2390
2391 *DP = (*DP & ~mask) | signal_levels;
2392}
2393
a4fc5ed6 2394static bool
ea5b213a 2395intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2396 uint32_t *DP,
58e10eb9 2397 uint8_t dp_train_pat)
a4fc5ed6 2398{
174edf1f
PZ		 2399 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2400 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2401 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2402 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2403 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2404 int ret, len;
a4fc5ed6 2405
22b8bf17 2406 if (HAS_DDI(dev)) {
3ab9c637 2407 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2408
2409 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2410 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2411 else
2412 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2413
2414 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2415 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2416 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2417 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2418
2419 break;
2420 case DP_TRAINING_PATTERN_1:
2421 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2422 break;
2423 case DP_TRAINING_PATTERN_2:
2424 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2425 break;
2426 case DP_TRAINING_PATTERN_3:
2427 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2428 break;
2429 }
174edf1f 2430 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2431
bc7d38a4 2432 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2433 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2434
2435 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2436 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2437 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2438 break;
2439 case DP_TRAINING_PATTERN_1:
70aff66c 2440 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2441 break;
2442 case DP_TRAINING_PATTERN_2:
70aff66c 2443 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2444 break;
2445 case DP_TRAINING_PATTERN_3:
2446 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2447 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2448 break;
2449 }
2450
2451 } else {
70aff66c 2452 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2453
2454 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2455 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2456 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2457 break;
2458 case DP_TRAINING_PATTERN_1:
70aff66c 2459 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2460 break;
2461 case DP_TRAINING_PATTERN_2:
70aff66c 2462 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2463 break;
2464 case DP_TRAINING_PATTERN_3:
2465 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2466 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2467 break;
2468 }
2469 }
2470
70aff66c 2471 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2472 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2473
2cdfe6c8
JN		 2474 buf[0] = dp_train_pat;
2475 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2476 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2477 /* don't write DP_TRAINING_LANEx_SET on disable */
2478 len = 1;
2479 } else {
2480 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2481 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2482 len = intel_dp->lane_count + 1;
47ea7542 2483 }
a4fc5ed6 2484
9d1a1031
JN		 2485 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2486 buf, len);
2cdfe6c8
JN		 2487
2488 return ret == len;
a4fc5ed6
KP		 2489}
2490
70aff66c
JN		 2491static bool
2492intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2493 uint8_t dp_train_pat)
2494{
953d22e8 2495 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2496 intel_dp_set_signal_levels(intel_dp, DP);
2497 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2498}
2499
2500static bool
2501intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2502 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2503{
2504 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2505 struct drm_device *dev = intel_dig_port->base.base.dev;
2506 struct drm_i915_private *dev_priv = dev->dev_private;
2507 int ret;
2508
2509 intel_get_adjust_train(intel_dp, link_status);
2510 intel_dp_set_signal_levels(intel_dp, DP);
2511
2512 I915_WRITE(intel_dp->output_reg, *DP);
2513 POSTING_READ(intel_dp->output_reg);
2514
9d1a1031
JN		 2515 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2516 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 2517
2518 return ret == intel_dp->lane_count;
2519}
2520
3ab9c637
ID		 2521static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2522{
2523 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2524 struct drm_device *dev = intel_dig_port->base.base.dev;
2525 struct drm_i915_private *dev_priv = dev->dev_private;
2526 enum port port = intel_dig_port->port;
2527 uint32_t val;
2528
2529 if (!HAS_DDI(dev))
2530 return;
2531
2532 val = I915_READ(DP_TP_CTL(port));
2533 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2534 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2535 I915_WRITE(DP_TP_CTL(port), val);
2536
2537 /*
2538 * On PORT_A we can have only eDP in SST mode. There the only reason
2539 * we need to set idle transmission mode is to work around a HW issue
2540 * where we enable the pipe while not in idle link-training mode.
2541 * In this case there is requirement to wait for a minimum number of
2542 * idle patterns to be sent.
2543 */
2544 if (port == PORT_A)
2545 return;
2546
2547 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2548 1))
2549 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2550}
2551
33a34e4e 2552/* Enable corresponding port and start training pattern 1 */
c19b0669 2553void
33a34e4e 2554intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2555{
da63a9f2 2556 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2557 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2558 int i;
2559 uint8_t voltage;
cdb0e95b 2560 int voltage_tries, loop_tries;
ea5b213a 2561 uint32_t DP = intel_dp->DP;
6aba5b6c 2562 uint8_t link_config[2];
a4fc5ed6 2563
affa9354 2564 if (HAS_DDI(dev))
c19b0669
PZ		 2565 intel_ddi_prepare_link_retrain(encoder);
2566
3cf2efb1 2567 /* Write the link configuration data */
6aba5b6c
JN		 2568 link_config[0] = intel_dp->link_bw;
2569 link_config[1] = intel_dp->lane_count;
2570 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2571 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 2572 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 2573
2574 link_config[0] = 0;
2575 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 2576 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2577
2578 DP |= DP_PORT_EN;
1a2eb460 2579
70aff66c
JN		 2580 /* clock recovery */
2581 if (!intel_dp_reset_link_train(intel_dp, &DP,
2582 DP_TRAINING_PATTERN_1 |
2583 DP_LINK_SCRAMBLING_DISABLE)) {
2584 DRM_ERROR("failed to enable link training\n");
2585 return;
2586 }
2587
a4fc5ed6 2588 voltage = 0xff;
cdb0e95b
KP		 2589 voltage_tries = 0;
2590 loop_tries = 0;
a4fc5ed6 2591 for (;;) {
70aff66c 2592 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2593
a7c9655f 2594 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2595 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2596 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2597 break;
93f62dad 2598 }
a4fc5ed6 2599
01916270 2600 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2601 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2602 break;
2603 }
2604
2605 /* Check to see if we've tried the max voltage */
2606 for (i = 0; i < intel_dp->lane_count; i++)
2607 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2608 break;
3b4f819d 2609 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2610 ++loop_tries;
2611 if (loop_tries == 5) {
3def84b3 2612 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2613 break;
2614 }
70aff66c
JN		 2615 intel_dp_reset_link_train(intel_dp, &DP,
2616 DP_TRAINING_PATTERN_1 |
2617 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2618 voltage_tries = 0;
2619 continue;
2620 }
a4fc5ed6 2621
3cf2efb1 2622 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2623 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2624 ++voltage_tries;
b06fbda3 2625 if (voltage_tries == 5) {
3def84b3 2626 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2627 break;
2628 }
2629 } else
2630 voltage_tries = 0;
2631 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2632
70aff66c
JN		 2633 /* Update training set as requested by target */
2634 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2635 DRM_ERROR("failed to update link training\n");
2636 break;
2637 }
a4fc5ed6
KP		 2638 }
2639
33a34e4e
JB		 2640 intel_dp->DP = DP;
2641}
2642
c19b0669 2643void
33a34e4e
JB		 2644intel_dp_complete_link_train(struct intel_dp *intel_dp)
2645{
33a34e4e 2646 bool channel_eq = false;
37f80975 2647 int tries, cr_tries;
33a34e4e 2648 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 2649 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2650
2651 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2652 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2653 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 2654
a4fc5ed6 2655 /* channel equalization */
70aff66c 2656 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2657 training_pattern |
70aff66c
JN		 2658 DP_LINK_SCRAMBLING_DISABLE)) {
2659 DRM_ERROR("failed to start channel equalization\n");
2660 return;
2661 }
2662
a4fc5ed6 2663 tries = 0;
37f80975 2664 cr_tries = 0;
a4fc5ed6
KP		 2665 channel_eq = false;
2666 for (;;) {
70aff66c 2667 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2668
37f80975
JB		 2669 if (cr_tries > 5) {
2670 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2671 break;
2672 }
2673
a7c9655f 2674 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2675 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2676 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2677 break;
70aff66c 2678 }
a4fc5ed6 2679
37f80975 2680 /* Make sure clock is still ok */
01916270 2681 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2682 intel_dp_start_link_train(intel_dp);
70aff66c 2683 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2684 training_pattern |
70aff66c 2685 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2686 cr_tries++;
2687 continue;
2688 }
2689
1ffdff13 2690 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2691 channel_eq = true;
2692 break;
2693 }
a4fc5ed6 2694
37f80975
JB		 2695 /* Try 5 times, then try clock recovery if that fails */
2696 if (tries > 5) {
2697 intel_dp_link_down(intel_dp);
2698 intel_dp_start_link_train(intel_dp);
70aff66c 2699 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2700 training_pattern |
70aff66c 2701 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2702 tries = 0;
2703 cr_tries++;
2704 continue;
2705 }
a4fc5ed6 2706
70aff66c
JN		 2707 /* Update training set as requested by target */
2708 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2709 DRM_ERROR("failed to update link training\n");
2710 break;
2711 }
3cf2efb1 2712 ++tries;
869184a6 2713 }
3cf2efb1 2714
3ab9c637
ID		 2715 intel_dp_set_idle_link_train(intel_dp);
2716
2717 intel_dp->DP = DP;
2718
d6c0d722 2719 if (channel_eq)
07f42258 2720 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2721
3ab9c637
ID		 2722}
2723
2724void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2725{
70aff66c 2726 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2727 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2728}
2729
2730static void
ea5b213a 2731intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2732{
da63a9f2 2733 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2734 enum port port = intel_dig_port->port;
da63a9f2 2735 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2736 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2737 struct intel_crtc *intel_crtc =
2738 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2739 uint32_t DP = intel_dp->DP;
a4fc5ed6 2740
c19b0669
PZ		 2741 /*
2742 * DDI code has a strict mode set sequence and we should try to respect
2743 * it, otherwise we might hang the machine in many different ways. So we
2744 * really should be disabling the port only on a complete crtc_disable
2745 * sequence. This function is just called under two conditions on DDI
2746 * code:
2747 * - Link train failed while doing crtc_enable, and on this case we
2748 * really should respect the mode set sequence and wait for a
2749 * crtc_disable.
2750 * - Someone turned the monitor off and intel_dp_check_link_status
2751 * called us. We don't need to disable the whole port on this case, so
2752 * when someone turns the monitor on again,
2753 * intel_ddi_prepare_link_retrain will take care of redoing the link
2754 * train.
2755 */
affa9354 2756 if (HAS_DDI(dev))
c19b0669
PZ		 2757 return;
2758
0c33d8d7 2759 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2760 return;
2761
28c97730 2762 DRM_DEBUG_KMS("\n");
32f9d658 2763
bc7d38a4 2764 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2765 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2766 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2767 } else {
2768 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2769 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2770 }
fe255d00 2771 POSTING_READ(intel_dp->output_reg);
5eb08b69 2772
ab527efc
DV		 2773 /* We don't really know why we're doing this */
2774 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2775
493a7081 2776 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2777 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2778 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2779
5bddd17f
EA		 2780 /* Hardware workaround: leaving our transcoder select
2781 * set to transcoder B while it's off will prevent the
2782 * corresponding HDMI output on transcoder A.
2783 *
2784 * Combine this with another hardware workaround:
2785 * transcoder select bit can only be cleared while the
2786 * port is enabled.
2787 */
2788 DP &= ~DP_PIPEB_SELECT;
2789 I915_WRITE(intel_dp->output_reg, DP);
2790
2791 /* Changes to enable or select take place the vblank
2792 * after being written.
2793 */
ff50afe9
DV		 2794 if (WARN_ON(crtc == NULL)) {
2795 /* We should never try to disable a port without a crtc
2796 * attached. For paranoia keep the code around for a
2797 * bit. */
31acbcc4
CW		 2798 POSTING_READ(intel_dp->output_reg);
2799 msleep(50);
2800 } else
ab527efc 2801 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2802 }
2803
832afda6 2804 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2805 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2806 POSTING_READ(intel_dp->output_reg);
f01eca2e 2807 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2808}
2809
26d61aad
KP		 2810static bool
2811intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2812{
a031d709
RV		 2813 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2814 struct drm_device *dev = dig_port->base.base.dev;
2815 struct drm_i915_private *dev_priv = dev->dev_private;
2816
577c7a50
DL		 2817 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2818
9d1a1031
JN		 2819 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
2820 sizeof(intel_dp->dpcd)) < 0)
edb39244 2821 return false; /* aux transfer failed */
92fd8fd1 2822
577c7a50
DL		 2823 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2824 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2825 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2826
edb39244
AJ		 2827 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2828 return false; /* DPCD not present */
2829
2293bb5c
SK		 2830 /* Check if the panel supports PSR */
2831 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 2832 if (is_edp(intel_dp)) {
9d1a1031
JN		 2833 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
2834 intel_dp->psr_dpcd,
2835 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2836 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2837 dev_priv->psr.sink_support = true;
50003939 2838 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2839 }
50003939
JN		 2840 }
2841
06ea66b6
TP		 2842 /* Training Pattern 3 support */
2843 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2844 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2845 intel_dp->use_tps3 = true;
2846 DRM_DEBUG_KMS("Displayport TPS3 supported");
2847 } else
2848 intel_dp->use_tps3 = false;
2849
edb39244
AJ		 2850 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2851 DP_DWN_STRM_PORT_PRESENT))
2852 return true; /* native DP sink */
2853
2854 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2855 return true; /* no per-port downstream info */
2856
9d1a1031
JN		 2857 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
2858 intel_dp->downstream_ports,
2859 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 2860 return false; /* downstream port status fetch failed */
2861
2862 return true;
92fd8fd1
KP		 2863}
2864
0d198328
AJ		 2865static void
2866intel_dp_probe_oui(struct intel_dp *intel_dp)
2867{
2868 u8 buf[3];
2869
2870 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2871 return;
2872
24f3e092 2873 intel_edp_panel_vdd_on(intel_dp);
351cfc34 2874
9d1a1031 2875 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 2876 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2877 buf[0], buf[1], buf[2]);
2878
9d1a1031 2879 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 2880 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2881 buf[0], buf[1], buf[2]);
351cfc34 2882
4be73780 2883 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2884}
2885
d2e216d0
RV		 2886int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2887{
2888 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2889 struct drm_device *dev = intel_dig_port->base.base.dev;
2890 struct intel_crtc *intel_crtc =
2891 to_intel_crtc(intel_dig_port->base.base.crtc);
2892 u8 buf[1];
2893
9d1a1031 2894 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 2895 return -EAGAIN;
2896
2897 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2898 return -ENOTTY;
2899
9d1a1031
JN		 2900 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
2901 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 2902 return -EAGAIN;
2903
2904 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2905 intel_wait_for_vblank(dev, intel_crtc->pipe);
2906 intel_wait_for_vblank(dev, intel_crtc->pipe);
2907
9d1a1031 2908 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 2909 return -EAGAIN;
2910
9d1a1031 2911 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 2912 return 0;
2913}
2914
a60f0e38
JB		 2915static bool
2916intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2917{
9d1a1031
JN		 2918 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2919 DP_DEVICE_SERVICE_IRQ_VECTOR,
2920 sink_irq_vector, 1) == 1;
a60f0e38
JB		 2921}
2922
2923static void
2924intel_dp_handle_test_request(struct intel_dp *intel_dp)
2925{
2926 /* NAK by default */
9d1a1031 2927 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2928}
2929
a4fc5ed6
KP		 2930/*
2931 * According to DP spec
2932 * 5.1.2:
2933 * 1. Read DPCD
2934 * 2. Configure link according to Receiver Capabilities
2935 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2936 * 4. Check link status on receipt of hot-plug interrupt
2937 */
2938
00c09d70 2939void
ea5b213a 2940intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2941{
da63a9f2 2942 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2943 u8 sink_irq_vector;
93f62dad 2944 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2945
da63a9f2 2946 if (!intel_encoder->connectors_active)
d2b996ac 2947 return;
59cd09e1 2948
da63a9f2 2949 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2950 return;
2951
92fd8fd1 2952 /* Try to read receiver status if the link appears to be up */
93f62dad 2953 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 2954 return;
2955 }
2956
92fd8fd1 2957 /* Now read the DPCD to see if it's actually running */
26d61aad 2958 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2959 return;
2960 }
2961
a60f0e38
JB		 2962 /* Try to read the source of the interrupt */
2963 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2964 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2965 /* Clear interrupt source */
9d1a1031
JN		 2966 drm_dp_dpcd_writeb(&intel_dp->aux,
2967 DP_DEVICE_SERVICE_IRQ_VECTOR,
2968 sink_irq_vector);
a60f0e38
JB		 2969
2970 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2971 intel_dp_handle_test_request(intel_dp);
2972 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2973 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2974 }
2975
1ffdff13 2976 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2977 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2978 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2979 intel_dp_start_link_train(intel_dp);
2980 intel_dp_complete_link_train(intel_dp);
3ab9c637 2981 intel_dp_stop_link_train(intel_dp);
33a34e4e 2982 }
a4fc5ed6 2983}
a4fc5ed6 2984
caf9ab24 2985/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2986static enum drm_connector_status
26d61aad 2987intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2988{
caf9ab24 2989 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 2990 uint8_t type;
2991
2992 if (!intel_dp_get_dpcd(intel_dp))
2993 return connector_status_disconnected;
2994
2995 /* if there's no downstream port, we're done */
2996 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2997 return connector_status_connected;
caf9ab24
AJ		 2998
2999 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3000 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3001 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3002 uint8_t reg;
9d1a1031
JN		 3003
3004 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3005 &reg, 1) < 0)
caf9ab24 3006 return connector_status_unknown;
9d1a1031 3007
23235177
AJ		 3008 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3009 : connector_status_disconnected;
caf9ab24
AJ		 3010 }
3011
3012 /* If no HPD, poke DDC gently */
0b99836f 3013 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3014 return connector_status_connected;
caf9ab24
AJ		 3015
3016 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3017 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3018 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3019 if (type == DP_DS_PORT_TYPE_VGA ||
3020 type == DP_DS_PORT_TYPE_NON_EDID)
3021 return connector_status_unknown;
3022 } else {
3023 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3024 DP_DWN_STRM_PORT_TYPE_MASK;
3025 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3026 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3027 return connector_status_unknown;
3028 }
caf9ab24
AJ		 3029
3030 /* Anything else is out of spec, warn and ignore */
3031 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3032 return connector_status_disconnected;
71ba9000
AJ		 3033}
3034
5eb08b69 3035static enum drm_connector_status
a9756bb5 3036ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3037{
30add22d 3038 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3039 struct drm_i915_private *dev_priv = dev->dev_private;
3040 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3041 enum drm_connector_status status;
3042
fe16d949
CW		 3043 /* Can't disconnect eDP, but you can close the lid... */
3044 if (is_edp(intel_dp)) {
30add22d 3045 status = intel_panel_detect(dev);
fe16d949
CW		 3046 if (status == connector_status_unknown)
3047 status = connector_status_connected;
3048 return status;
3049 }
01cb9ea6 3050
1b469639
DL		 3051 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3052 return connector_status_disconnected;
3053
26d61aad 3054 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3055}
3056
a4fc5ed6 3057static enum drm_connector_status
a9756bb5 3058g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3059{
30add22d 3060 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3061 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3062 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3063 uint32_t bit;
5eb08b69 3064
35aad75f
JB		 3065 /* Can't disconnect eDP, but you can close the lid... */
3066 if (is_edp(intel_dp)) {
3067 enum drm_connector_status status;
3068
3069 status = intel_panel_detect(dev);
3070 if (status == connector_status_unknown)
3071 status = connector_status_connected;
3072 return status;
3073 }
3074
232a6ee9
TP		 3075 if (IS_VALLEYVIEW(dev)) {
3076 switch (intel_dig_port->port) {
3077 case PORT_B:
3078 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3079 break;
3080 case PORT_C:
3081 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3082 break;
3083 case PORT_D:
3084 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3085 break;
3086 default:
3087 return connector_status_unknown;
3088 }
3089 } else {
3090 switch (intel_dig_port->port) {
3091 case PORT_B:
3092 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3093 break;
3094 case PORT_C:
3095 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3096 break;
3097 case PORT_D:
3098 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3099 break;
3100 default:
3101 return connector_status_unknown;
3102 }
a4fc5ed6
KP		 3103 }
3104
10f76a38 3105 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3106 return connector_status_disconnected;
3107
26d61aad 3108 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3109}
3110
8c241fef
KP		 3111static struct edid *
3112intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3113{
9cd300e0 3114 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3115
9cd300e0
JN		 3116 /* use cached edid if we have one */
3117 if (intel_connector->edid) {
9cd300e0
JN		 3118 /* invalid edid */
3119 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3120 return NULL;
3121
55e9edeb 3122 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3123 }
8c241fef 3124
9cd300e0 3125 return drm_get_edid(connector, adapter);
8c241fef
KP		 3126}
3127
3128static int
3129intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3130{
9cd300e0 3131 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3132
9cd300e0
JN		 3133 /* use cached edid if we have one */
3134 if (intel_connector->edid) {
3135 /* invalid edid */
3136 if (IS_ERR(intel_connector->edid))
3137 return 0;
3138
3139 return intel_connector_update_modes(connector,
3140 intel_connector->edid);
d6f24d0f
JB		 3141 }
3142
9cd300e0 3143 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3144}
3145
a9756bb5
ZW		 3146static enum drm_connector_status
3147intel_dp_detect(struct drm_connector *connector, bool force)
3148{
3149 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3150 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3151 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3152 struct drm_device *dev = connector->dev;
c8c8fb33 3153 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3154 enum drm_connector_status status;
671dedd2 3155 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3156 struct edid *edid = NULL;
3157
c8c8fb33
PZ		 3158 intel_runtime_pm_get(dev_priv);
3159
671dedd2
ID		 3160 power_domain = intel_display_port_power_domain(intel_encoder);
3161 intel_display_power_get(dev_priv, power_domain);
3162
164c8598
CW		 3163 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3164 connector->base.id, drm_get_connector_name(connector));
3165
a9756bb5
ZW		 3166 intel_dp->has_audio = false;
3167
3168 if (HAS_PCH_SPLIT(dev))
3169 status = ironlake_dp_detect(intel_dp);
3170 else
3171 status = g4x_dp_detect(intel_dp);
1b9be9d0 3172
a9756bb5 3173 if (status != connector_status_connected)
c8c8fb33 3174 goto out;
a9756bb5 3175
0d198328
AJ		 3176 intel_dp_probe_oui(intel_dp);
3177
c3e5f67b
DV		 3178 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3179 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3180 } else {
0b99836f 3181 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3182 if (edid) {
3183 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3184 kfree(edid);
3185 }
a9756bb5
ZW		 3186 }
3187
d63885da
PZ		 3188 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3189 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3190 status = connector_status_connected;
3191
3192out:
671dedd2
ID		 3193 intel_display_power_put(dev_priv, power_domain);
3194
c8c8fb33 3195 intel_runtime_pm_put(dev_priv);
671dedd2 3196
c8c8fb33 3197 return status;
a4fc5ed6
KP		 3198}
3199
3200static int intel_dp_get_modes(struct drm_connector *connector)
3201{
df0e9248 3202 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3203 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3204 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3205 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3206 struct drm_device *dev = connector->dev;
671dedd2
ID		 3207 struct drm_i915_private *dev_priv = dev->dev_private;
3208 enum intel_display_power_domain power_domain;
32f9d658 3209 int ret;
a4fc5ed6
KP		 3210
3211 /* We should parse the EDID data and find out if it has an audio sink
3212 */
3213
671dedd2
ID		 3214 power_domain = intel_display_port_power_domain(intel_encoder);
3215 intel_display_power_get(dev_priv, power_domain);
3216
0b99836f 3217 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3218 intel_display_power_put(dev_priv, power_domain);
f8779fda 3219 if (ret)
32f9d658
ZW		 3220 return ret;
3221
f8779fda 3222 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3223 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3224 struct drm_display_mode *mode;
dd06f90e
JN		 3225 mode = drm_mode_duplicate(dev,
3226 intel_connector->panel.fixed_mode);
f8779fda 3227 if (mode) {
32f9d658
ZW		 3228 drm_mode_probed_add(connector, mode);
3229 return 1;
3230 }
3231 }
3232 return 0;
a4fc5ed6
KP		 3233}
3234
1aad7ac0
CW		 3235static bool
3236intel_dp_detect_audio(struct drm_connector *connector)
3237{
3238 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3239 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3240 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3241 struct drm_device *dev = connector->dev;
3242 struct drm_i915_private *dev_priv = dev->dev_private;
3243 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3244 struct edid *edid;
3245 bool has_audio = false;
3246
671dedd2
ID		 3247 power_domain = intel_display_port_power_domain(intel_encoder);
3248 intel_display_power_get(dev_priv, power_domain);
3249
0b99836f 3250 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3251 if (edid) {
3252 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3253 kfree(edid);
3254 }
3255
671dedd2
ID		 3256 intel_display_power_put(dev_priv, power_domain);
3257
1aad7ac0
CW		 3258 return has_audio;
3259}
3260
f684960e
CW		 3261static int
3262intel_dp_set_property(struct drm_connector *connector,
3263 struct drm_property *property,
3264 uint64_t val)
3265{
e953fd7b 3266 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3267 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3268 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3269 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3270 int ret;
3271
662595df 3272 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3273 if (ret)
3274 return ret;
3275
3f43c48d 3276 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3277 int i = val;
3278 bool has_audio;
3279
3280 if (i == intel_dp->force_audio)
f684960e
CW		 3281 return 0;
3282
1aad7ac0 3283 intel_dp->force_audio = i;
f684960e 3284
c3e5f67b 3285 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3286 has_audio = intel_dp_detect_audio(connector);
3287 else
c3e5f67b 3288 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3289
3290 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3291 return 0;
3292
1aad7ac0 3293 intel_dp->has_audio = has_audio;
f684960e
CW		 3294 goto done;
3295 }
3296
e953fd7b 3297 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3298 bool old_auto = intel_dp->color_range_auto;
3299 uint32_t old_range = intel_dp->color_range;
3300
55bc60db
VS		 3301 switch (val) {
3302 case INTEL_BROADCAST_RGB_AUTO:
3303 intel_dp->color_range_auto = true;
3304 break;
3305 case INTEL_BROADCAST_RGB_FULL:
3306 intel_dp->color_range_auto = false;
3307 intel_dp->color_range = 0;
3308 break;
3309 case INTEL_BROADCAST_RGB_LIMITED:
3310 intel_dp->color_range_auto = false;
3311 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3312 break;
3313 default:
3314 return -EINVAL;
3315 }
ae4edb80
DV		 3316
3317 if (old_auto == intel_dp->color_range_auto &&
3318 old_range == intel_dp->color_range)
3319 return 0;
3320
e953fd7b
CW		 3321 goto done;
3322 }
3323
53b41837
YN		 3324 if (is_edp(intel_dp) &&
3325 property == connector->dev->mode_config.scaling_mode_property) {
3326 if (val == DRM_MODE_SCALE_NONE) {
3327 DRM_DEBUG_KMS("no scaling not supported\n");
3328 return -EINVAL;
3329 }
3330
3331 if (intel_connector->panel.fitting_mode == val) {
3332 /* the eDP scaling property is not changed */
3333 return 0;
3334 }
3335 intel_connector->panel.fitting_mode = val;
3336
3337 goto done;
3338 }
3339
f684960e
CW		 3340 return -EINVAL;
3341
3342done:
c0c36b94
CW		 3343 if (intel_encoder->base.crtc)
3344 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3345
3346 return 0;
3347}
3348
a4fc5ed6 3349static void
73845adf 3350intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3351{
1d508706 3352 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3353
9cd300e0
JN		 3354 if (!IS_ERR_OR_NULL(intel_connector->edid))
3355 kfree(intel_connector->edid);
3356
acd8db10
PZ		 3357 /* Can't call is_edp() since the encoder may have been destroyed
3358 * already. */
3359 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3360 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3361
a4fc5ed6 3362 drm_connector_cleanup(connector);
55f78c43 3363 kfree(connector);
a4fc5ed6
KP		 3364}
3365
00c09d70 3366void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3367{
da63a9f2
PZ		 3368 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3369 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3370 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 3371
0b99836f 3372 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
24d05927 3373 drm_encoder_cleanup(encoder);
bd943159
KP		 3374 if (is_edp(intel_dp)) {
3375 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3376 mutex_lock(&dev->mode_config.mutex);
4be73780 3377 edp_panel_vdd_off_sync(intel_dp);
bd173813 3378 mutex_unlock(&dev->mode_config.mutex);
bd943159 3379 }
da63a9f2 3380 kfree(intel_dig_port);
24d05927
DV		 3381}
3382
a4fc5ed6 3383static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3384 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3385 .detect = intel_dp_detect,
3386 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3387 .set_property = intel_dp_set_property,
73845adf 3388 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3389};
3390
3391static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3392 .get_modes = intel_dp_get_modes,
3393 .mode_valid = intel_dp_mode_valid,
df0e9248 3394 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3395};
3396
a4fc5ed6 3397static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3398 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3399};
3400
995b6762 3401static void
21d40d37 3402intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3403{
fa90ecef 3404 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3405
885a5014 3406 intel_dp_check_link_status(intel_dp);
c8110e52 3407}
6207937d 3408
e3421a18
ZW		 3409/* Return which DP Port should be selected for Transcoder DP control */
3410int
0206e353 3411intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3412{
3413 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3414 struct intel_encoder *intel_encoder;
3415 struct intel_dp *intel_dp;
e3421a18 3416
fa90ecef
PZ		 3417 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3418 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3419
fa90ecef
PZ		 3420 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3421 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3422 return intel_dp->output_reg;
e3421a18 3423 }
ea5b213a 3424
e3421a18
ZW		 3425 return -1;
3426}
3427
36e83a18 3428/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3429bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3430{
3431 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3432 union child_device_config *p_child;
36e83a18 3433 int i;
5d8a7752
VS		 3434 static const short port_mapping[] = {
3435 [PORT_B] = PORT_IDPB,
3436 [PORT_C] = PORT_IDPC,
3437 [PORT_D] = PORT_IDPD,
3438 };
36e83a18 3439
3b32a35b
VS		 3440 if (port == PORT_A)
3441 return true;
3442
41aa3448 3443 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3444 return false;
3445
41aa3448
RV		 3446 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3447 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3448
5d8a7752 3449 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3450 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3451 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3452 return true;
3453 }
3454 return false;
3455}
3456
f684960e
CW		 3457static void
3458intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3459{
53b41837
YN		 3460 struct intel_connector *intel_connector = to_intel_connector(connector);
3461
3f43c48d 3462 intel_attach_force_audio_property(connector);
e953fd7b 3463 intel_attach_broadcast_rgb_property(connector);
55bc60db 3464 intel_dp->color_range_auto = true;
53b41837
YN		 3465
3466 if (is_edp(intel_dp)) {
3467 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3468 drm_object_attach_property(
3469 &connector->base,
53b41837 3470 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3471 DRM_MODE_SCALE_ASPECT);
3472 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3473 }
f684960e
CW		 3474}
3475
dada1a9f
ID		 3476static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3477{
3478 intel_dp->last_power_cycle = jiffies;
3479 intel_dp->last_power_on = jiffies;
3480 intel_dp->last_backlight_off = jiffies;
3481}
3482
67a54566
DV		 3483static void
3484intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3485 struct intel_dp *intel_dp,
3486 struct edp_power_seq *out)
67a54566
DV		 3487{
3488 struct drm_i915_private *dev_priv = dev->dev_private;
3489 struct edp_power_seq cur, vbt, spec, final;
3490 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3491 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3492
3493 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3494 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3495 pp_on_reg = PCH_PP_ON_DELAYS;
3496 pp_off_reg = PCH_PP_OFF_DELAYS;
3497 pp_div_reg = PCH_PP_DIVISOR;
3498 } else {
bf13e81b
JN		 3499 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3500
3501 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3502 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3503 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3504 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3505 }
67a54566
DV		 3506
3507 /* Workaround: Need to write PP_CONTROL with the unlock key as
3508 * the very first thing. */
453c5420 3509 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3510 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3511
453c5420
JB		 3512 pp_on = I915_READ(pp_on_reg);
3513 pp_off = I915_READ(pp_off_reg);
3514 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3515
3516 /* Pull timing values out of registers */
3517 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3518 PANEL_POWER_UP_DELAY_SHIFT;
3519
3520 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3521 PANEL_LIGHT_ON_DELAY_SHIFT;
3522
3523 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3524 PANEL_LIGHT_OFF_DELAY_SHIFT;
3525
3526 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3527 PANEL_POWER_DOWN_DELAY_SHIFT;
3528
3529 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3530 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3531
3532 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3533 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3534
41aa3448 3535 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3536
3537 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3538 * our hw here, which are all in 100usec. */
3539 spec.t1_t3 = 210 * 10;
3540 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3541 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3542 spec.t10 = 500 * 10;
3543 /* This one is special and actually in units of 100ms, but zero
3544 * based in the hw (so we need to add 100 ms). But the sw vbt
3545 * table multiplies it with 1000 to make it in units of 100usec,
3546 * too. */
3547 spec.t11_t12 = (510 + 100) * 10;
3548
3549 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3550 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3551
3552 /* Use the max of the register settings and vbt. If both are
3553 * unset, fall back to the spec limits. */
3554#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3555 spec.field : \
3556 max(cur.field, vbt.field))
3557 assign_final(t1_t3);
3558 assign_final(t8);
3559 assign_final(t9);
3560 assign_final(t10);
3561 assign_final(t11_t12);
3562#undef assign_final
3563
3564#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3565 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3566 intel_dp->backlight_on_delay = get_delay(t8);
3567 intel_dp->backlight_off_delay = get_delay(t9);
3568 intel_dp->panel_power_down_delay = get_delay(t10);
3569 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3570#undef get_delay
3571
f30d26e4
JN		 3572 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3573 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3574 intel_dp->panel_power_cycle_delay);
3575
3576 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3577 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3578
3579 if (out)
3580 *out = final;
3581}
3582
3583static void
3584intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3585 struct intel_dp *intel_dp,
3586 struct edp_power_seq *seq)
3587{
3588 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3589 u32 pp_on, pp_off, pp_div, port_sel = 0;
3590 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3591 int pp_on_reg, pp_off_reg, pp_div_reg;
3592
3593 if (HAS_PCH_SPLIT(dev)) {
3594 pp_on_reg = PCH_PP_ON_DELAYS;
3595 pp_off_reg = PCH_PP_OFF_DELAYS;
3596 pp_div_reg = PCH_PP_DIVISOR;
3597 } else {
bf13e81b
JN		 3598 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3599
3600 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3601 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3602 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3603 }
3604
b2f19d1a
PZ		 3605 /*
3606 * And finally store the new values in the power sequencer. The
3607 * backlight delays are set to 1 because we do manual waits on them. For
3608 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3609 * we'll end up waiting for the backlight off delay twice: once when we
3610 * do the manual sleep, and once when we disable the panel and wait for
3611 * the PP_STATUS bit to become zero.
3612 */
f30d26e4 3613 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 3614 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3615 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 3616 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3617 /* Compute the divisor for the pp clock, simply match the Bspec
3618 * formula. */
453c5420 3619 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3620 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3621 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3622
3623 /* Haswell doesn't have any port selection bits for the panel
3624 * power sequencer any more. */
bc7d38a4 3625 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3626 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3627 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3628 else
3629 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3630 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3631 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3632 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3633 else
a24c144c 3634 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3635 }
3636
453c5420
JB		 3637 pp_on |= port_sel;
3638
3639 I915_WRITE(pp_on_reg, pp_on);
3640 I915_WRITE(pp_off_reg, pp_off);
3641 I915_WRITE(pp_div_reg, pp_div);
67a54566 3642
67a54566 3643 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3644 I915_READ(pp_on_reg),
3645 I915_READ(pp_off_reg),
3646 I915_READ(pp_div_reg));
f684960e
CW		 3647}
3648
ed92f0b2 3649static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 3650 struct intel_connector *intel_connector,
3651 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 3652{
3653 struct drm_connector *connector = &intel_connector->base;
3654 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 3655 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3656 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 3657 struct drm_i915_private *dev_priv = dev->dev_private;
3658 struct drm_display_mode *fixed_mode = NULL;
ed92f0b2
PZ		 3659 bool has_dpcd;
3660 struct drm_display_mode *scan;
3661 struct edid *edid;
3662
3663 if (!is_edp(intel_dp))
3664 return true;
3665
63635217
PZ		 3666 /* The VDD bit needs a power domain reference, so if the bit is already
3667 * enabled when we boot, grab this reference. */
3668 if (edp_have_panel_vdd(intel_dp)) {
3669 enum intel_display_power_domain power_domain;
3670 power_domain = intel_display_port_power_domain(intel_encoder);
3671 intel_display_power_get(dev_priv, power_domain);
3672 }
3673
ed92f0b2 3674 /* Cache DPCD and EDID for edp. */
24f3e092 3675 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 3676 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 3677 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 3678
3679 if (has_dpcd) {
3680 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3681 dev_priv->no_aux_handshake =
3682 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3683 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3684 } else {
3685 /* if this fails, presume the device is a ghost */
3686 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3687 return false;
3688 }
3689
3690 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 3691 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 3692
060c8778 3693 mutex_lock(&dev->mode_config.mutex);
0b99836f 3694 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 3695 if (edid) {
3696 if (drm_add_edid_modes(connector, edid)) {
3697 drm_mode_connector_update_edid_property(connector,
3698 edid);
3699 drm_edid_to_eld(connector, edid);
3700 } else {
3701 kfree(edid);
3702 edid = ERR_PTR(-EINVAL);
3703 }
3704 } else {
3705 edid = ERR_PTR(-ENOENT);
3706 }
3707 intel_connector->edid = edid;
3708
3709 /* prefer fixed mode from EDID if available */
3710 list_for_each_entry(scan, &connector->probed_modes, head) {
3711 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3712 fixed_mode = drm_mode_duplicate(dev, scan);
3713 break;
3714 }
3715 }
3716
3717 /* fallback to VBT if available for eDP */
3718 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3719 fixed_mode = drm_mode_duplicate(dev,
3720 dev_priv->vbt.lfp_lvds_vbt_mode);
3721 if (fixed_mode)
3722 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3723 }
060c8778 3724 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 3725
4b6ed685 3726 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
ed92f0b2
PZ		 3727 intel_panel_setup_backlight(connector);
3728
3729 return true;
3730}
3731
16c25533 3732bool
f0fec3f2
PZ		 3733intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3734 struct intel_connector *intel_connector)
a4fc5ed6 3735{
f0fec3f2
PZ		 3736 struct drm_connector *connector = &intel_connector->base;
3737 struct intel_dp *intel_dp = &intel_dig_port->dp;
3738 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3739 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3740 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3741 enum port port = intel_dig_port->port;
0095e6dc 3742 struct edp_power_seq power_seq = { 0 };
0b99836f 3743 int type;
a4fc5ed6 3744
ec5b01dd
DL		 3745 /* intel_dp vfuncs */
3746 if (IS_VALLEYVIEW(dev))
3747 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3748 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3749 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3750 else if (HAS_PCH_SPLIT(dev))
3751 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3752 else
3753 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3754
153b1100
DL		 3755 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3756
0767935e
DV		 3757 /* Preserve the current hw state. */
3758 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3759 intel_dp->attached_connector = intel_connector;
3d3dc149 3760
3b32a35b 3761 if (intel_dp_is_edp(dev, port))
b329530c 3762 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 3763 else
3764 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 3765
f7d24902
ID		 3766 /*
3767 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3768 * for DP the encoder type can be set by the caller to
3769 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3770 */
3771 if (type == DRM_MODE_CONNECTOR_eDP)
3772 intel_encoder->type = INTEL_OUTPUT_EDP;
3773
e7281eab
ID		 3774 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3775 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3776 port_name(port));
3777
b329530c 3778 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3779 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3780
a4fc5ed6
KP		 3781 connector->interlace_allowed = true;
3782 connector->doublescan_allowed = 0;
3783
f0fec3f2 3784 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 3785 edp_panel_vdd_work);
a4fc5ed6 3786
df0e9248 3787 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3788 drm_sysfs_connector_add(connector);
3789
affa9354 3790 if (HAS_DDI(dev))
bcbc889b
PZ		 3791 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3792 else
3793 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 3794 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 3795
0b99836f 3796 /* Set up the hotplug pin. */
ab9d7c30
PZ		 3797 switch (port) {
3798 case PORT_A:
1d843f9d 3799 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3800 break;
3801 case PORT_B:
1d843f9d 3802 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3803 break;
3804 case PORT_C:
1d843f9d 3805 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3806 break;
3807 case PORT_D:
1d843f9d 3808 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3809 break;
3810 default:
ad1c0b19 3811 BUG();
5eb08b69
ZW		 3812 }
3813
dada1a9f
ID		 3814 if (is_edp(intel_dp)) {
3815 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 3816 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 3817 }
0095e6dc 3818
9d1a1031 3819 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 3820
2b28bb1b
RV		 3821 intel_dp->psr_setup_done = false;
3822
0095e6dc 3823 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
0b99836f 3824 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
15b1d171
PZ		 3825 if (is_edp(intel_dp)) {
3826 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3827 mutex_lock(&dev->mode_config.mutex);
4be73780 3828 edp_panel_vdd_off_sync(intel_dp);
15b1d171
PZ		 3829 mutex_unlock(&dev->mode_config.mutex);
3830 }
b2f246a8
PZ		 3831 drm_sysfs_connector_remove(connector);
3832 drm_connector_cleanup(connector);
16c25533 3833 return false;
b2f246a8 3834 }
32f9d658 3835
f684960e
CW		 3836 intel_dp_add_properties(intel_dp, connector);
3837
a4fc5ed6
KP		 3838 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3839 * 0xd. Failure to do so will result in spurious interrupts being
3840 * generated on the port when a cable is not attached.
3841 */
3842 if (IS_G4X(dev) && !IS_GM45(dev)) {
3843 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3844 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3845 }
16c25533
PZ		 3846
3847 return true;
a4fc5ed6 3848}
f0fec3f2
PZ		 3849
3850void
3851intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3852{
3853 struct intel_digital_port *intel_dig_port;
3854 struct intel_encoder *intel_encoder;
3855 struct drm_encoder *encoder;
3856 struct intel_connector *intel_connector;
3857
b14c5679 3858 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3859 if (!intel_dig_port)
3860 return;
3861
b14c5679 3862 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3863 if (!intel_connector) {
3864 kfree(intel_dig_port);
3865 return;
3866 }
3867
3868 intel_encoder = &intel_dig_port->base;
3869 encoder = &intel_encoder->base;
3870
3871 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3872 DRM_MODE_ENCODER_TMDS);
3873
5bfe2ac0 3874 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3875 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3876 intel_encoder->disable = intel_disable_dp;
3877 intel_encoder->post_disable = intel_post_disable_dp;
3878 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3879 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3880 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3881 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3882 intel_encoder->pre_enable = vlv_pre_enable_dp;
3883 intel_encoder->enable = vlv_enable_dp;
3884 } else {
ecff4f3b
JN		 3885 intel_encoder->pre_enable = g4x_pre_enable_dp;
3886 intel_encoder->enable = g4x_enable_dp;
ab1f90f9 3887 }
f0fec3f2 3888
174edf1f 3889 intel_dig_port->port = port;
f0fec3f2
PZ		 3890 intel_dig_port->dp.output_reg = output_reg;
3891
00c09d70 3892 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2 3893 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 3894 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 3895 intel_encoder->hot_plug = intel_dp_hot_plug;
3896
15b1d171
PZ		 3897 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3898 drm_encoder_cleanup(encoder);
3899 kfree(intel_dig_port);
b2f246a8 3900 kfree(intel_connector);
15b1d171 3901 }
f0fec3f2 3902}
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