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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
a4fc5ed6 KP |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "drm_crtc.h" | |
33 | #include "drm_crtc_helper.h" | |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
ab2c0672 | 37 | #include "drm_dp_helper.h" |
a4fc5ed6 | 38 | |
ae266c98 | 39 | |
a4fc5ed6 KP |
40 | #define DP_LINK_STATUS_SIZE 6 |
41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) | |
42 | ||
43 | #define DP_LINK_CONFIGURATION_SIZE 9 | |
44 | ||
ea5b213a CW |
45 | struct intel_dp { |
46 | struct intel_encoder base; | |
a4fc5ed6 KP |
47 | uint32_t output_reg; |
48 | uint32_t DP; | |
49 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
a4fc5ed6 | 50 | bool has_audio; |
f684960e | 51 | int force_audio; |
e953fd7b | 52 | uint32_t color_range; |
d2b996ac | 53 | int dpms_mode; |
a4fc5ed6 KP |
54 | uint8_t link_bw; |
55 | uint8_t lane_count; | |
9de88e6e | 56 | uint8_t dpcd[8]; |
a4fc5ed6 KP |
57 | struct i2c_adapter adapter; |
58 | struct i2c_algo_dp_aux_data algo; | |
f0917379 | 59 | bool is_pch_edp; |
33a34e4e JB |
60 | uint8_t train_set[4]; |
61 | uint8_t link_status[DP_LINK_STATUS_SIZE]; | |
f01eca2e KP |
62 | int panel_power_up_delay; |
63 | int panel_power_down_delay; | |
64 | int panel_power_cycle_delay; | |
65 | int backlight_on_delay; | |
66 | int backlight_off_delay; | |
d15456de | 67 | struct drm_display_mode *panel_fixed_mode; /* for eDP */ |
bd943159 KP |
68 | struct delayed_work panel_vdd_work; |
69 | bool want_panel_vdd; | |
70 | unsigned long panel_off_jiffies; | |
a4fc5ed6 KP |
71 | }; |
72 | ||
cfcb0fc9 JB |
73 | /** |
74 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
75 | * @intel_dp: DP struct | |
76 | * | |
77 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
78 | * will return true, and false otherwise. | |
79 | */ | |
80 | static bool is_edp(struct intel_dp *intel_dp) | |
81 | { | |
82 | return intel_dp->base.type == INTEL_OUTPUT_EDP; | |
83 | } | |
84 | ||
85 | /** | |
86 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? | |
87 | * @intel_dp: DP struct | |
88 | * | |
89 | * Returns true if the given DP struct corresponds to a PCH DP port attached | |
90 | * to an eDP panel, false otherwise. Helpful for determining whether we | |
91 | * may need FDI resources for a given DP output or not. | |
92 | */ | |
93 | static bool is_pch_edp(struct intel_dp *intel_dp) | |
94 | { | |
95 | return intel_dp->is_pch_edp; | |
96 | } | |
97 | ||
ea5b213a CW |
98 | static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
99 | { | |
4ef69c7a | 100 | return container_of(encoder, struct intel_dp, base.base); |
ea5b213a | 101 | } |
a4fc5ed6 | 102 | |
df0e9248 CW |
103 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
104 | { | |
105 | return container_of(intel_attached_encoder(connector), | |
106 | struct intel_dp, base); | |
107 | } | |
108 | ||
814948ad JB |
109 | /** |
110 | * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? | |
111 | * @encoder: DRM encoder | |
112 | * | |
113 | * Return true if @encoder corresponds to a PCH attached eDP panel. Needed | |
114 | * by intel_display.c. | |
115 | */ | |
116 | bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) | |
117 | { | |
118 | struct intel_dp *intel_dp; | |
119 | ||
120 | if (!encoder) | |
121 | return false; | |
122 | ||
123 | intel_dp = enc_to_intel_dp(encoder); | |
124 | ||
125 | return is_pch_edp(intel_dp); | |
126 | } | |
127 | ||
33a34e4e JB |
128 | static void intel_dp_start_link_train(struct intel_dp *intel_dp); |
129 | static void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
ea5b213a | 130 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
a4fc5ed6 | 131 | |
32f9d658 | 132 | void |
21d40d37 | 133 | intel_edp_link_config (struct intel_encoder *intel_encoder, |
ea5b213a | 134 | int *lane_num, int *link_bw) |
32f9d658 | 135 | { |
ea5b213a | 136 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
32f9d658 | 137 | |
ea5b213a CW |
138 | *lane_num = intel_dp->lane_count; |
139 | if (intel_dp->link_bw == DP_LINK_BW_1_62) | |
32f9d658 | 140 | *link_bw = 162000; |
ea5b213a | 141 | else if (intel_dp->link_bw == DP_LINK_BW_2_7) |
32f9d658 ZW |
142 | *link_bw = 270000; |
143 | } | |
144 | ||
a4fc5ed6 | 145 | static int |
ea5b213a | 146 | intel_dp_max_lane_count(struct intel_dp *intel_dp) |
a4fc5ed6 | 147 | { |
a4fc5ed6 KP |
148 | int max_lane_count = 4; |
149 | ||
7183dc29 JB |
150 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
151 | max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; | |
a4fc5ed6 KP |
152 | switch (max_lane_count) { |
153 | case 1: case 2: case 4: | |
154 | break; | |
155 | default: | |
156 | max_lane_count = 4; | |
157 | } | |
158 | } | |
159 | return max_lane_count; | |
160 | } | |
161 | ||
162 | static int | |
ea5b213a | 163 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 164 | { |
7183dc29 | 165 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
166 | |
167 | switch (max_link_bw) { | |
168 | case DP_LINK_BW_1_62: | |
169 | case DP_LINK_BW_2_7: | |
170 | break; | |
171 | default: | |
172 | max_link_bw = DP_LINK_BW_1_62; | |
173 | break; | |
174 | } | |
175 | return max_link_bw; | |
176 | } | |
177 | ||
178 | static int | |
179 | intel_dp_link_clock(uint8_t link_bw) | |
180 | { | |
181 | if (link_bw == DP_LINK_BW_2_7) | |
182 | return 270000; | |
183 | else | |
184 | return 162000; | |
185 | } | |
186 | ||
187 | /* I think this is a fiction */ | |
188 | static int | |
ea5b213a | 189 | intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock) |
a4fc5ed6 | 190 | { |
89c61432 JB |
191 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
192 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
193 | int bpp = 24; | |
885a5fb5 | 194 | |
89c61432 JB |
195 | if (intel_crtc) |
196 | bpp = intel_crtc->bpp; | |
197 | ||
198 | return (pixel_clock * bpp + 7) / 8; | |
a4fc5ed6 KP |
199 | } |
200 | ||
fe27d53e DA |
201 | static int |
202 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
203 | { | |
204 | return (max_link_clock * max_lanes * 8) / 10; | |
205 | } | |
206 | ||
a4fc5ed6 KP |
207 | static int |
208 | intel_dp_mode_valid(struct drm_connector *connector, | |
209 | struct drm_display_mode *mode) | |
210 | { | |
df0e9248 | 211 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
ea5b213a CW |
212 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
213 | int max_lanes = intel_dp_max_lane_count(intel_dp); | |
a4fc5ed6 | 214 | |
d15456de KP |
215 | if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
216 | if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay) | |
7de56f43 ZY |
217 | return MODE_PANEL; |
218 | ||
d15456de | 219 | if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay) |
7de56f43 ZY |
220 | return MODE_PANEL; |
221 | } | |
222 | ||
25985edc | 223 | /* only refuse the mode on non eDP since we have seen some weird eDP panels |
fe27d53e | 224 | which are outside spec tolerances but somehow work by magic */ |
cfcb0fc9 | 225 | if (!is_edp(intel_dp) && |
ea5b213a | 226 | (intel_dp_link_required(connector->dev, intel_dp, mode->clock) |
fe27d53e | 227 | > intel_dp_max_data_rate(max_link_clock, max_lanes))) |
a4fc5ed6 KP |
228 | return MODE_CLOCK_HIGH; |
229 | ||
230 | if (mode->clock < 10000) | |
231 | return MODE_CLOCK_LOW; | |
232 | ||
233 | return MODE_OK; | |
234 | } | |
235 | ||
236 | static uint32_t | |
237 | pack_aux(uint8_t *src, int src_bytes) | |
238 | { | |
239 | int i; | |
240 | uint32_t v = 0; | |
241 | ||
242 | if (src_bytes > 4) | |
243 | src_bytes = 4; | |
244 | for (i = 0; i < src_bytes; i++) | |
245 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
246 | return v; | |
247 | } | |
248 | ||
249 | static void | |
250 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
251 | { | |
252 | int i; | |
253 | if (dst_bytes > 4) | |
254 | dst_bytes = 4; | |
255 | for (i = 0; i < dst_bytes; i++) | |
256 | dst[i] = src >> ((3-i) * 8); | |
257 | } | |
258 | ||
fb0f8fbf KP |
259 | /* hrawclock is 1/4 the FSB frequency */ |
260 | static int | |
261 | intel_hrawclk(struct drm_device *dev) | |
262 | { | |
263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
264 | uint32_t clkcfg; | |
265 | ||
266 | clkcfg = I915_READ(CLKCFG); | |
267 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
268 | case CLKCFG_FSB_400: | |
269 | return 100; | |
270 | case CLKCFG_FSB_533: | |
271 | return 133; | |
272 | case CLKCFG_FSB_667: | |
273 | return 166; | |
274 | case CLKCFG_FSB_800: | |
275 | return 200; | |
276 | case CLKCFG_FSB_1067: | |
277 | return 266; | |
278 | case CLKCFG_FSB_1333: | |
279 | return 333; | |
280 | /* these two are just a guess; one of them might be right */ | |
281 | case CLKCFG_FSB_1600: | |
282 | case CLKCFG_FSB_1600_ALT: | |
283 | return 400; | |
284 | default: | |
285 | return 133; | |
286 | } | |
287 | } | |
288 | ||
ebf33b18 KP |
289 | static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) |
290 | { | |
291 | struct drm_device *dev = intel_dp->base.base.dev; | |
292 | struct drm_i915_private *dev_priv = dev->dev_private; | |
293 | ||
294 | return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; | |
295 | } | |
296 | ||
297 | static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) | |
298 | { | |
299 | struct drm_device *dev = intel_dp->base.base.dev; | |
300 | struct drm_i915_private *dev_priv = dev->dev_private; | |
301 | ||
302 | return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0; | |
303 | } | |
304 | ||
9b984dae KP |
305 | static void |
306 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
307 | { | |
308 | struct drm_device *dev = intel_dp->base.base.dev; | |
309 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ebf33b18 | 310 | |
9b984dae KP |
311 | if (!is_edp(intel_dp)) |
312 | return; | |
ebf33b18 | 313 | if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
314 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
315 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
ebf33b18 | 316 | I915_READ(PCH_PP_STATUS), |
9b984dae KP |
317 | I915_READ(PCH_PP_CONTROL)); |
318 | } | |
319 | } | |
320 | ||
a4fc5ed6 | 321 | static int |
ea5b213a | 322 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
323 | uint8_t *send, int send_bytes, |
324 | uint8_t *recv, int recv_size) | |
325 | { | |
ea5b213a | 326 | uint32_t output_reg = intel_dp->output_reg; |
4ef69c7a | 327 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 KP |
328 | struct drm_i915_private *dev_priv = dev->dev_private; |
329 | uint32_t ch_ctl = output_reg + 0x10; | |
330 | uint32_t ch_data = ch_ctl + 4; | |
331 | int i; | |
332 | int recv_bytes; | |
a4fc5ed6 | 333 | uint32_t status; |
fb0f8fbf | 334 | uint32_t aux_clock_divider; |
e3421a18 | 335 | int try, precharge; |
a4fc5ed6 | 336 | |
9b984dae | 337 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 | 338 | /* The clock divider is based off the hrawclk, |
fb0f8fbf KP |
339 | * and would like to run at 2MHz. So, take the |
340 | * hrawclk value and divide by 2 and use that | |
6176b8f9 JB |
341 | * |
342 | * Note that PCH attached eDP panels should use a 125MHz input | |
343 | * clock divider. | |
a4fc5ed6 | 344 | */ |
cfcb0fc9 | 345 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { |
e3421a18 ZW |
346 | if (IS_GEN6(dev)) |
347 | aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ | |
348 | else | |
349 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ | |
350 | } else if (HAS_PCH_SPLIT(dev)) | |
f2b115e6 | 351 | aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ |
5eb08b69 ZW |
352 | else |
353 | aux_clock_divider = intel_hrawclk(dev) / 2; | |
354 | ||
e3421a18 ZW |
355 | if (IS_GEN6(dev)) |
356 | precharge = 3; | |
357 | else | |
358 | precharge = 5; | |
359 | ||
11bee43e JB |
360 | /* Try to wait for any previous AUX channel activity */ |
361 | for (try = 0; try < 3; try++) { | |
362 | status = I915_READ(ch_ctl); | |
363 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
364 | break; | |
365 | msleep(1); | |
366 | } | |
367 | ||
368 | if (try == 3) { | |
369 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
370 | I915_READ(ch_ctl)); | |
4f7f7b7e CW |
371 | return -EBUSY; |
372 | } | |
373 | ||
fb0f8fbf KP |
374 | /* Must try at least 3 times according to DP spec */ |
375 | for (try = 0; try < 5; try++) { | |
376 | /* Load the send data into the aux channel data registers */ | |
4f7f7b7e CW |
377 | for (i = 0; i < send_bytes; i += 4) |
378 | I915_WRITE(ch_data + i, | |
379 | pack_aux(send + i, send_bytes - i)); | |
fb0f8fbf KP |
380 | |
381 | /* Send the command and wait for it to complete */ | |
4f7f7b7e CW |
382 | I915_WRITE(ch_ctl, |
383 | DP_AUX_CH_CTL_SEND_BUSY | | |
384 | DP_AUX_CH_CTL_TIME_OUT_400us | | |
385 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
386 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
387 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | | |
388 | DP_AUX_CH_CTL_DONE | | |
389 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
390 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
fb0f8fbf | 391 | for (;;) { |
fb0f8fbf KP |
392 | status = I915_READ(ch_ctl); |
393 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
394 | break; | |
4f7f7b7e | 395 | udelay(100); |
fb0f8fbf KP |
396 | } |
397 | ||
398 | /* Clear done status and any errors */ | |
4f7f7b7e CW |
399 | I915_WRITE(ch_ctl, |
400 | status | | |
401 | DP_AUX_CH_CTL_DONE | | |
402 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
403 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
404 | if (status & DP_AUX_CH_CTL_DONE) | |
a4fc5ed6 KP |
405 | break; |
406 | } | |
407 | ||
a4fc5ed6 | 408 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 409 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
a5b3da54 | 410 | return -EBUSY; |
a4fc5ed6 KP |
411 | } |
412 | ||
413 | /* Check for timeout or receive error. | |
414 | * Timeouts occur when the sink is not connected | |
415 | */ | |
a5b3da54 | 416 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 417 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
a5b3da54 KP |
418 | return -EIO; |
419 | } | |
1ae8c0a5 KP |
420 | |
421 | /* Timeouts occur when the device isn't connected, so they're | |
422 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 423 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 424 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
a5b3da54 | 425 | return -ETIMEDOUT; |
a4fc5ed6 KP |
426 | } |
427 | ||
428 | /* Unload any bytes sent back from the other side */ | |
429 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
430 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
431 | if (recv_bytes > recv_size) |
432 | recv_bytes = recv_size; | |
433 | ||
4f7f7b7e CW |
434 | for (i = 0; i < recv_bytes; i += 4) |
435 | unpack_aux(I915_READ(ch_data + i), | |
436 | recv + i, recv_bytes - i); | |
a4fc5ed6 KP |
437 | |
438 | return recv_bytes; | |
439 | } | |
440 | ||
441 | /* Write data to the aux channel in native mode */ | |
442 | static int | |
ea5b213a | 443 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
444 | uint16_t address, uint8_t *send, int send_bytes) |
445 | { | |
446 | int ret; | |
447 | uint8_t msg[20]; | |
448 | int msg_bytes; | |
449 | uint8_t ack; | |
450 | ||
9b984dae | 451 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
452 | if (send_bytes > 16) |
453 | return -1; | |
454 | msg[0] = AUX_NATIVE_WRITE << 4; | |
455 | msg[1] = address >> 8; | |
eebc863e | 456 | msg[2] = address & 0xff; |
a4fc5ed6 KP |
457 | msg[3] = send_bytes - 1; |
458 | memcpy(&msg[4], send, send_bytes); | |
459 | msg_bytes = send_bytes + 4; | |
460 | for (;;) { | |
ea5b213a | 461 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
a4fc5ed6 KP |
462 | if (ret < 0) |
463 | return ret; | |
464 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
465 | break; | |
466 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
467 | udelay(100); | |
468 | else | |
a5b3da54 | 469 | return -EIO; |
a4fc5ed6 KP |
470 | } |
471 | return send_bytes; | |
472 | } | |
473 | ||
474 | /* Write a single byte to the aux channel in native mode */ | |
475 | static int | |
ea5b213a | 476 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
477 | uint16_t address, uint8_t byte) |
478 | { | |
ea5b213a | 479 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
a4fc5ed6 KP |
480 | } |
481 | ||
482 | /* read bytes from a native aux channel */ | |
483 | static int | |
ea5b213a | 484 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
485 | uint16_t address, uint8_t *recv, int recv_bytes) |
486 | { | |
487 | uint8_t msg[4]; | |
488 | int msg_bytes; | |
489 | uint8_t reply[20]; | |
490 | int reply_bytes; | |
491 | uint8_t ack; | |
492 | int ret; | |
493 | ||
9b984dae | 494 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
495 | msg[0] = AUX_NATIVE_READ << 4; |
496 | msg[1] = address >> 8; | |
497 | msg[2] = address & 0xff; | |
498 | msg[3] = recv_bytes - 1; | |
499 | ||
500 | msg_bytes = 4; | |
501 | reply_bytes = recv_bytes + 1; | |
502 | ||
503 | for (;;) { | |
ea5b213a | 504 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
a4fc5ed6 | 505 | reply, reply_bytes); |
a5b3da54 KP |
506 | if (ret == 0) |
507 | return -EPROTO; | |
508 | if (ret < 0) | |
a4fc5ed6 KP |
509 | return ret; |
510 | ack = reply[0]; | |
511 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { | |
512 | memcpy(recv, reply + 1, ret - 1); | |
513 | return ret - 1; | |
514 | } | |
515 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
516 | udelay(100); | |
517 | else | |
a5b3da54 | 518 | return -EIO; |
a4fc5ed6 KP |
519 | } |
520 | } | |
521 | ||
522 | static int | |
ab2c0672 DA |
523 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
524 | uint8_t write_byte, uint8_t *read_byte) | |
a4fc5ed6 | 525 | { |
ab2c0672 | 526 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
ea5b213a CW |
527 | struct intel_dp *intel_dp = container_of(adapter, |
528 | struct intel_dp, | |
529 | adapter); | |
ab2c0672 DA |
530 | uint16_t address = algo_data->address; |
531 | uint8_t msg[5]; | |
532 | uint8_t reply[2]; | |
8316f337 | 533 | unsigned retry; |
ab2c0672 DA |
534 | int msg_bytes; |
535 | int reply_bytes; | |
536 | int ret; | |
537 | ||
9b984dae | 538 | intel_dp_check_edp(intel_dp); |
ab2c0672 DA |
539 | /* Set up the command byte */ |
540 | if (mode & MODE_I2C_READ) | |
541 | msg[0] = AUX_I2C_READ << 4; | |
542 | else | |
543 | msg[0] = AUX_I2C_WRITE << 4; | |
544 | ||
545 | if (!(mode & MODE_I2C_STOP)) | |
546 | msg[0] |= AUX_I2C_MOT << 4; | |
a4fc5ed6 | 547 | |
ab2c0672 DA |
548 | msg[1] = address >> 8; |
549 | msg[2] = address; | |
550 | ||
551 | switch (mode) { | |
552 | case MODE_I2C_WRITE: | |
553 | msg[3] = 0; | |
554 | msg[4] = write_byte; | |
555 | msg_bytes = 5; | |
556 | reply_bytes = 1; | |
557 | break; | |
558 | case MODE_I2C_READ: | |
559 | msg[3] = 0; | |
560 | msg_bytes = 4; | |
561 | reply_bytes = 2; | |
562 | break; | |
563 | default: | |
564 | msg_bytes = 3; | |
565 | reply_bytes = 1; | |
566 | break; | |
567 | } | |
568 | ||
8316f337 DF |
569 | for (retry = 0; retry < 5; retry++) { |
570 | ret = intel_dp_aux_ch(intel_dp, | |
571 | msg, msg_bytes, | |
572 | reply, reply_bytes); | |
ab2c0672 | 573 | if (ret < 0) { |
3ff99164 | 574 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
ab2c0672 DA |
575 | return ret; |
576 | } | |
8316f337 DF |
577 | |
578 | switch (reply[0] & AUX_NATIVE_REPLY_MASK) { | |
579 | case AUX_NATIVE_REPLY_ACK: | |
580 | /* I2C-over-AUX Reply field is only valid | |
581 | * when paired with AUX ACK. | |
582 | */ | |
583 | break; | |
584 | case AUX_NATIVE_REPLY_NACK: | |
585 | DRM_DEBUG_KMS("aux_ch native nack\n"); | |
586 | return -EREMOTEIO; | |
587 | case AUX_NATIVE_REPLY_DEFER: | |
588 | udelay(100); | |
589 | continue; | |
590 | default: | |
591 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", | |
592 | reply[0]); | |
593 | return -EREMOTEIO; | |
594 | } | |
595 | ||
ab2c0672 DA |
596 | switch (reply[0] & AUX_I2C_REPLY_MASK) { |
597 | case AUX_I2C_REPLY_ACK: | |
598 | if (mode == MODE_I2C_READ) { | |
599 | *read_byte = reply[1]; | |
600 | } | |
601 | return reply_bytes - 1; | |
602 | case AUX_I2C_REPLY_NACK: | |
8316f337 | 603 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
ab2c0672 DA |
604 | return -EREMOTEIO; |
605 | case AUX_I2C_REPLY_DEFER: | |
8316f337 | 606 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
ab2c0672 DA |
607 | udelay(100); |
608 | break; | |
609 | default: | |
8316f337 | 610 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
ab2c0672 DA |
611 | return -EREMOTEIO; |
612 | } | |
613 | } | |
8316f337 DF |
614 | |
615 | DRM_ERROR("too many retries, giving up\n"); | |
616 | return -EREMOTEIO; | |
a4fc5ed6 KP |
617 | } |
618 | ||
0b5c541b | 619 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
bd943159 | 620 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
0b5c541b | 621 | |
a4fc5ed6 | 622 | static int |
ea5b213a | 623 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
55f78c43 | 624 | struct intel_connector *intel_connector, const char *name) |
a4fc5ed6 | 625 | { |
0b5c541b KP |
626 | int ret; |
627 | ||
d54e9d28 | 628 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
ea5b213a CW |
629 | intel_dp->algo.running = false; |
630 | intel_dp->algo.address = 0; | |
631 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | |
632 | ||
633 | memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter)); | |
634 | intel_dp->adapter.owner = THIS_MODULE; | |
635 | intel_dp->adapter.class = I2C_CLASS_DDC; | |
636 | strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); | |
637 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; | |
638 | intel_dp->adapter.algo_data = &intel_dp->algo; | |
639 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; | |
640 | ||
0b5c541b KP |
641 | ironlake_edp_panel_vdd_on(intel_dp); |
642 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); | |
bd943159 | 643 | ironlake_edp_panel_vdd_off(intel_dp, false); |
0b5c541b | 644 | return ret; |
a4fc5ed6 KP |
645 | } |
646 | ||
647 | static bool | |
648 | intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
649 | struct drm_display_mode *adjusted_mode) | |
650 | { | |
0d3a1bee | 651 | struct drm_device *dev = encoder->dev; |
ea5b213a | 652 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
a4fc5ed6 | 653 | int lane_count, clock; |
ea5b213a CW |
654 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
655 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; | |
a4fc5ed6 KP |
656 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
657 | ||
d15456de KP |
658 | if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
659 | intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode); | |
1d8e1c75 CW |
660 | intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, |
661 | mode, adjusted_mode); | |
0d3a1bee ZY |
662 | /* |
663 | * the mode->clock is used to calculate the Data&Link M/N | |
664 | * of the pipe. For the eDP the fixed clock should be used. | |
665 | */ | |
d15456de | 666 | mode->clock = intel_dp->panel_fixed_mode->clock; |
0d3a1bee ZY |
667 | } |
668 | ||
a4fc5ed6 KP |
669 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
670 | for (clock = 0; clock <= max_clock; clock++) { | |
fe27d53e | 671 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
a4fc5ed6 | 672 | |
ea5b213a | 673 | if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock) |
885a5fb5 | 674 | <= link_avail) { |
ea5b213a CW |
675 | intel_dp->link_bw = bws[clock]; |
676 | intel_dp->lane_count = lane_count; | |
677 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
28c97730 ZY |
678 | DRM_DEBUG_KMS("Display port link bw %02x lane " |
679 | "count %d clock %d\n", | |
ea5b213a | 680 | intel_dp->link_bw, intel_dp->lane_count, |
a4fc5ed6 KP |
681 | adjusted_mode->clock); |
682 | return true; | |
683 | } | |
684 | } | |
685 | } | |
fe27d53e | 686 | |
3cf2efb1 CW |
687 | if (is_edp(intel_dp)) { |
688 | /* okay we failed just pick the highest */ | |
689 | intel_dp->lane_count = max_lane_count; | |
690 | intel_dp->link_bw = bws[max_clock]; | |
691 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
692 | DRM_DEBUG_KMS("Force picking display port link bw %02x lane " | |
693 | "count %d clock %d\n", | |
694 | intel_dp->link_bw, intel_dp->lane_count, | |
695 | adjusted_mode->clock); | |
696 | ||
697 | return true; | |
698 | } | |
699 | ||
a4fc5ed6 KP |
700 | return false; |
701 | } | |
702 | ||
703 | struct intel_dp_m_n { | |
704 | uint32_t tu; | |
705 | uint32_t gmch_m; | |
706 | uint32_t gmch_n; | |
707 | uint32_t link_m; | |
708 | uint32_t link_n; | |
709 | }; | |
710 | ||
711 | static void | |
712 | intel_reduce_ratio(uint32_t *num, uint32_t *den) | |
713 | { | |
714 | while (*num > 0xffffff || *den > 0xffffff) { | |
715 | *num >>= 1; | |
716 | *den >>= 1; | |
717 | } | |
718 | } | |
719 | ||
720 | static void | |
36e83a18 | 721 | intel_dp_compute_m_n(int bpp, |
a4fc5ed6 KP |
722 | int nlanes, |
723 | int pixel_clock, | |
724 | int link_clock, | |
725 | struct intel_dp_m_n *m_n) | |
726 | { | |
727 | m_n->tu = 64; | |
36e83a18 | 728 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
a4fc5ed6 KP |
729 | m_n->gmch_n = link_clock * nlanes; |
730 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
731 | m_n->link_m = pixel_clock; | |
732 | m_n->link_n = link_clock; | |
733 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
734 | } | |
735 | ||
736 | void | |
737 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
738 | struct drm_display_mode *adjusted_mode) | |
739 | { | |
740 | struct drm_device *dev = crtc->dev; | |
741 | struct drm_mode_config *mode_config = &dev->mode_config; | |
55f78c43 | 742 | struct drm_encoder *encoder; |
a4fc5ed6 KP |
743 | struct drm_i915_private *dev_priv = dev->dev_private; |
744 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
858fa035 | 745 | int lane_count = 4; |
a4fc5ed6 | 746 | struct intel_dp_m_n m_n; |
9db4a9c7 | 747 | int pipe = intel_crtc->pipe; |
a4fc5ed6 KP |
748 | |
749 | /* | |
21d40d37 | 750 | * Find the lane count in the intel_encoder private |
a4fc5ed6 | 751 | */ |
55f78c43 | 752 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
ea5b213a | 753 | struct intel_dp *intel_dp; |
a4fc5ed6 | 754 | |
d8201ab6 | 755 | if (encoder->crtc != crtc) |
a4fc5ed6 KP |
756 | continue; |
757 | ||
ea5b213a CW |
758 | intel_dp = enc_to_intel_dp(encoder); |
759 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) { | |
760 | lane_count = intel_dp->lane_count; | |
51190667 JB |
761 | break; |
762 | } else if (is_edp(intel_dp)) { | |
763 | lane_count = dev_priv->edp.lanes; | |
a4fc5ed6 KP |
764 | break; |
765 | } | |
766 | } | |
767 | ||
768 | /* | |
769 | * Compute the GMCH and Link ratios. The '3' here is | |
770 | * the number of bytes_per_pixel post-LUT, which we always | |
771 | * set up for 8-bits of R/G/B, or 3 bytes total. | |
772 | */ | |
858fa035 | 773 | intel_dp_compute_m_n(intel_crtc->bpp, lane_count, |
a4fc5ed6 KP |
774 | mode->clock, adjusted_mode->clock, &m_n); |
775 | ||
c619eed4 | 776 | if (HAS_PCH_SPLIT(dev)) { |
9db4a9c7 JB |
777 | I915_WRITE(TRANSDATA_M1(pipe), |
778 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
779 | m_n.gmch_m); | |
780 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); | |
781 | I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); | |
782 | I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); | |
a4fc5ed6 | 783 | } else { |
9db4a9c7 JB |
784 | I915_WRITE(PIPE_GMCH_DATA_M(pipe), |
785 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
786 | m_n.gmch_m); | |
787 | I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); | |
788 | I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); | |
789 | I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); | |
a4fc5ed6 KP |
790 | } |
791 | } | |
792 | ||
f01eca2e KP |
793 | static void ironlake_edp_pll_on(struct drm_encoder *encoder); |
794 | static void ironlake_edp_pll_off(struct drm_encoder *encoder); | |
795 | ||
a4fc5ed6 KP |
796 | static void |
797 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
798 | struct drm_display_mode *adjusted_mode) | |
799 | { | |
e3421a18 | 800 | struct drm_device *dev = encoder->dev; |
ea5b213a | 801 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
4ef69c7a | 802 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
a4fc5ed6 KP |
803 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
804 | ||
f01eca2e KP |
805 | /* Turn on the eDP PLL if needed */ |
806 | if (is_edp(intel_dp)) { | |
807 | if (!is_pch_edp(intel_dp)) | |
808 | ironlake_edp_pll_on(encoder); | |
809 | else | |
810 | ironlake_edp_pll_off(encoder); | |
811 | } | |
812 | ||
e953fd7b CW |
813 | intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
814 | intel_dp->DP |= intel_dp->color_range; | |
9c9e7927 AJ |
815 | |
816 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
ea5b213a | 817 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
9c9e7927 | 818 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
ea5b213a | 819 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
a4fc5ed6 | 820 | |
cfcb0fc9 | 821 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
ea5b213a | 822 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3421a18 | 823 | else |
ea5b213a | 824 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
a4fc5ed6 | 825 | |
ea5b213a | 826 | switch (intel_dp->lane_count) { |
a4fc5ed6 | 827 | case 1: |
ea5b213a | 828 | intel_dp->DP |= DP_PORT_WIDTH_1; |
a4fc5ed6 KP |
829 | break; |
830 | case 2: | |
ea5b213a | 831 | intel_dp->DP |= DP_PORT_WIDTH_2; |
a4fc5ed6 KP |
832 | break; |
833 | case 4: | |
ea5b213a | 834 | intel_dp->DP |= DP_PORT_WIDTH_4; |
a4fc5ed6 KP |
835 | break; |
836 | } | |
ea5b213a CW |
837 | if (intel_dp->has_audio) |
838 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; | |
a4fc5ed6 | 839 | |
ea5b213a CW |
840 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
841 | intel_dp->link_configuration[0] = intel_dp->link_bw; | |
842 | intel_dp->link_configuration[1] = intel_dp->lane_count; | |
a2cab1b2 | 843 | intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; |
a4fc5ed6 KP |
844 | |
845 | /* | |
9962c925 | 846 | * Check for DPCD version > 1.1 and enhanced framing support |
a4fc5ed6 | 847 | */ |
7183dc29 JB |
848 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
849 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { | |
ea5b213a CW |
850 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
851 | intel_dp->DP |= DP_ENHANCED_FRAMING; | |
a4fc5ed6 KP |
852 | } |
853 | ||
e3421a18 ZW |
854 | /* CPT DP's pipe select is decided in TRANS_DP_CTL */ |
855 | if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev)) | |
ea5b213a | 856 | intel_dp->DP |= DP_PIPEB_SELECT; |
32f9d658 | 857 | |
895692be | 858 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) { |
32f9d658 | 859 | /* don't miss out required setting for eDP */ |
ea5b213a | 860 | intel_dp->DP |= DP_PLL_ENABLE; |
32f9d658 | 861 | if (adjusted_mode->clock < 200000) |
ea5b213a | 862 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
32f9d658 | 863 | else |
ea5b213a | 864 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
32f9d658 | 865 | } |
a4fc5ed6 KP |
866 | } |
867 | ||
bd943159 KP |
868 | static void ironlake_wait_panel_off(struct intel_dp *intel_dp) |
869 | { | |
870 | unsigned long off_time; | |
871 | unsigned long delay; | |
872 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
873 | off_time = intel_dp->panel_off_jiffies + msecs_to_jiffies(intel_dp->panel_power_down_delay); | |
874 | if (time_after(jiffies, off_time)) { | |
875 | DRM_DEBUG_KMS("Time already passed"); | |
876 | return; | |
877 | } | |
878 | delay = jiffies_to_msecs(off_time - jiffies); | |
879 | if (delay > intel_dp->panel_power_down_delay) | |
880 | delay = intel_dp->panel_power_down_delay; | |
881 | DRM_DEBUG_KMS("Waiting an additional %ld ms\n", delay); | |
882 | msleep(delay); | |
883 | } | |
884 | ||
5d613501 JB |
885 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
886 | { | |
887 | struct drm_device *dev = intel_dp->base.base.dev; | |
888 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ebf33b18 | 889 | u32 pp; |
5d613501 | 890 | |
97af61f5 KP |
891 | if (!is_edp(intel_dp)) |
892 | return; | |
f01eca2e | 893 | DRM_DEBUG_KMS("Turn eDP VDD on\n"); |
5d613501 | 894 | |
bd943159 KP |
895 | WARN(intel_dp->want_panel_vdd, |
896 | "eDP VDD already requested on\n"); | |
897 | ||
898 | intel_dp->want_panel_vdd = true; | |
899 | if (ironlake_edp_have_panel_vdd(intel_dp)) { | |
900 | DRM_DEBUG_KMS("eDP VDD already on\n"); | |
901 | return; | |
902 | } | |
903 | ||
904 | ironlake_wait_panel_off(intel_dp); | |
5d613501 | 905 | pp = I915_READ(PCH_PP_CONTROL); |
1c0ae80a KP |
906 | pp &= ~PANEL_UNLOCK_MASK; |
907 | pp |= PANEL_UNLOCK_REGS; | |
5d613501 JB |
908 | pp |= EDP_FORCE_VDD; |
909 | I915_WRITE(PCH_PP_CONTROL, pp); | |
910 | POSTING_READ(PCH_PP_CONTROL); | |
f01eca2e KP |
911 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", |
912 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); | |
ebf33b18 KP |
913 | |
914 | /* | |
915 | * If the panel wasn't on, delay before accessing aux channel | |
916 | */ | |
917 | if (!ironlake_edp_have_panel_power(intel_dp)) { | |
bd943159 | 918 | DRM_DEBUG_KMS("eDP was not running\n"); |
f01eca2e | 919 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 920 | } |
5d613501 JB |
921 | } |
922 | ||
bd943159 | 923 | static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 JB |
924 | { |
925 | struct drm_device *dev = intel_dp->base.base.dev; | |
926 | struct drm_i915_private *dev_priv = dev->dev_private; | |
927 | u32 pp; | |
928 | ||
bd943159 KP |
929 | if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { |
930 | pp = I915_READ(PCH_PP_CONTROL); | |
931 | pp &= ~PANEL_UNLOCK_MASK; | |
932 | pp |= PANEL_UNLOCK_REGS; | |
933 | pp &= ~EDP_FORCE_VDD; | |
934 | I915_WRITE(PCH_PP_CONTROL, pp); | |
935 | POSTING_READ(PCH_PP_CONTROL); | |
936 | ||
937 | /* Make sure sequencer is idle before allowing subsequent activity */ | |
938 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", | |
939 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); | |
940 | intel_dp->panel_off_jiffies = jiffies; | |
941 | } | |
942 | } | |
943 | ||
944 | static void ironlake_panel_vdd_work(struct work_struct *__work) | |
945 | { | |
946 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
947 | struct intel_dp, panel_vdd_work); | |
948 | struct drm_device *dev = intel_dp->base.base.dev; | |
949 | ||
950 | mutex_lock(&dev->struct_mutex); | |
951 | ironlake_panel_vdd_off_sync(intel_dp); | |
952 | mutex_unlock(&dev->struct_mutex); | |
953 | } | |
954 | ||
955 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) | |
956 | { | |
97af61f5 KP |
957 | if (!is_edp(intel_dp)) |
958 | return; | |
5d613501 | 959 | |
bd943159 KP |
960 | DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd); |
961 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); | |
962 | ||
963 | intel_dp->want_panel_vdd = false; | |
964 | ||
965 | if (sync) { | |
966 | ironlake_panel_vdd_off_sync(intel_dp); | |
967 | } else { | |
968 | /* | |
969 | * Queue the timer to fire a long | |
970 | * time from now (relative to the power down delay) | |
971 | * to keep the panel power up across a sequence of operations | |
972 | */ | |
973 | schedule_delayed_work(&intel_dp->panel_vdd_work, | |
974 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); | |
975 | } | |
5d613501 JB |
976 | } |
977 | ||
7eaf5547 | 978 | /* Returns true if the panel was already on when called */ |
7d639f35 | 979 | static void ironlake_edp_panel_on (struct intel_dp *intel_dp) |
9934c132 | 980 | { |
01cb9ea6 | 981 | struct drm_device *dev = intel_dp->base.base.dev; |
9934c132 | 982 | struct drm_i915_private *dev_priv = dev->dev_private; |
01cb9ea6 | 983 | u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE; |
9934c132 | 984 | |
97af61f5 | 985 | if (!is_edp(intel_dp)) |
bd943159 | 986 | return; |
ebf33b18 | 987 | if (ironlake_edp_have_panel_power(intel_dp)) |
7d639f35 | 988 | return; |
9934c132 | 989 | |
bd943159 | 990 | ironlake_wait_panel_off(intel_dp); |
9934c132 | 991 | pp = I915_READ(PCH_PP_CONTROL); |
1c0ae80a KP |
992 | pp &= ~PANEL_UNLOCK_MASK; |
993 | pp |= PANEL_UNLOCK_REGS; | |
37c6c9b0 | 994 | |
05ce1a49 KP |
995 | if (IS_GEN5(dev)) { |
996 | /* ILK workaround: disable reset around power sequence */ | |
997 | pp &= ~PANEL_POWER_RESET; | |
998 | I915_WRITE(PCH_PP_CONTROL, pp); | |
999 | POSTING_READ(PCH_PP_CONTROL); | |
1000 | } | |
37c6c9b0 | 1001 | |
1c0ae80a | 1002 | pp |= POWER_TARGET_ON; |
9934c132 | 1003 | I915_WRITE(PCH_PP_CONTROL, pp); |
01cb9ea6 | 1004 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 | 1005 | |
01cb9ea6 JB |
1006 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask, |
1007 | 5000)) | |
913d8d11 CW |
1008 | DRM_ERROR("panel on wait timed out: 0x%08x\n", |
1009 | I915_READ(PCH_PP_STATUS)); | |
9934c132 | 1010 | |
05ce1a49 KP |
1011 | if (IS_GEN5(dev)) { |
1012 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ | |
1013 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1014 | POSTING_READ(PCH_PP_CONTROL); | |
1015 | } | |
9934c132 JB |
1016 | } |
1017 | ||
f01eca2e | 1018 | static void ironlake_edp_panel_off(struct drm_encoder *encoder) |
9934c132 | 1019 | { |
f01eca2e KP |
1020 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
1021 | struct drm_device *dev = encoder->dev; | |
9934c132 | 1022 | struct drm_i915_private *dev_priv = dev->dev_private; |
01cb9ea6 JB |
1023 | u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK | |
1024 | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK; | |
9934c132 | 1025 | |
97af61f5 KP |
1026 | if (!is_edp(intel_dp)) |
1027 | return; | |
9934c132 | 1028 | pp = I915_READ(PCH_PP_CONTROL); |
1c0ae80a KP |
1029 | pp &= ~PANEL_UNLOCK_MASK; |
1030 | pp |= PANEL_UNLOCK_REGS; | |
37c6c9b0 | 1031 | |
05ce1a49 KP |
1032 | if (IS_GEN5(dev)) { |
1033 | /* ILK workaround: disable reset around power sequence */ | |
1034 | pp &= ~PANEL_POWER_RESET; | |
1035 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1036 | POSTING_READ(PCH_PP_CONTROL); | |
1037 | } | |
37c6c9b0 | 1038 | |
05ce1a49 | 1039 | intel_dp->panel_off_jiffies = jiffies; |
9934c132 | 1040 | |
05ce1a49 KP |
1041 | if (IS_GEN5(dev)) { |
1042 | pp &= ~POWER_TARGET_ON; | |
1043 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1044 | POSTING_READ(PCH_PP_CONTROL); | |
1045 | pp &= ~POWER_TARGET_ON; | |
1046 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1047 | POSTING_READ(PCH_PP_CONTROL); | |
1048 | msleep(intel_dp->panel_power_cycle_delay); | |
9934c132 | 1049 | |
05ce1a49 KP |
1050 | if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000)) |
1051 | DRM_ERROR("panel off wait timed out: 0x%08x\n", | |
1052 | I915_READ(PCH_PP_STATUS)); | |
1053 | ||
1054 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ | |
1055 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1056 | POSTING_READ(PCH_PP_CONTROL); | |
1057 | } | |
9934c132 JB |
1058 | } |
1059 | ||
f01eca2e | 1060 | static void ironlake_edp_backlight_on (struct intel_dp *intel_dp) |
32f9d658 | 1061 | { |
f01eca2e | 1062 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1063 | struct drm_i915_private *dev_priv = dev->dev_private; |
1064 | u32 pp; | |
1065 | ||
f01eca2e KP |
1066 | if (!is_edp(intel_dp)) |
1067 | return; | |
1068 | ||
28c97730 | 1069 | DRM_DEBUG_KMS("\n"); |
01cb9ea6 JB |
1070 | /* |
1071 | * If we enable the backlight right away following a panel power | |
1072 | * on, we may see slight flicker as the panel syncs with the eDP | |
1073 | * link. So delay a bit to make sure the image is solid before | |
1074 | * allowing it to appear. | |
1075 | */ | |
f01eca2e | 1076 | msleep(intel_dp->backlight_on_delay); |
32f9d658 | 1077 | pp = I915_READ(PCH_PP_CONTROL); |
1c0ae80a KP |
1078 | pp &= ~PANEL_UNLOCK_MASK; |
1079 | pp |= PANEL_UNLOCK_REGS; | |
32f9d658 ZW |
1080 | pp |= EDP_BLC_ENABLE; |
1081 | I915_WRITE(PCH_PP_CONTROL, pp); | |
f01eca2e | 1082 | POSTING_READ(PCH_PP_CONTROL); |
32f9d658 ZW |
1083 | } |
1084 | ||
f01eca2e | 1085 | static void ironlake_edp_backlight_off (struct intel_dp *intel_dp) |
32f9d658 | 1086 | { |
f01eca2e | 1087 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1088 | struct drm_i915_private *dev_priv = dev->dev_private; |
1089 | u32 pp; | |
1090 | ||
f01eca2e KP |
1091 | if (!is_edp(intel_dp)) |
1092 | return; | |
1093 | ||
28c97730 | 1094 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 1095 | pp = I915_READ(PCH_PP_CONTROL); |
1c0ae80a KP |
1096 | pp &= ~PANEL_UNLOCK_MASK; |
1097 | pp |= PANEL_UNLOCK_REGS; | |
32f9d658 ZW |
1098 | pp &= ~EDP_BLC_ENABLE; |
1099 | I915_WRITE(PCH_PP_CONTROL, pp); | |
f01eca2e KP |
1100 | POSTING_READ(PCH_PP_CONTROL); |
1101 | msleep(intel_dp->backlight_off_delay); | |
32f9d658 | 1102 | } |
a4fc5ed6 | 1103 | |
d240f20f JB |
1104 | static void ironlake_edp_pll_on(struct drm_encoder *encoder) |
1105 | { | |
1106 | struct drm_device *dev = encoder->dev; | |
1107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1108 | u32 dpa_ctl; | |
1109 | ||
1110 | DRM_DEBUG_KMS("\n"); | |
1111 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 1112 | dpa_ctl |= DP_PLL_ENABLE; |
d240f20f | 1113 | I915_WRITE(DP_A, dpa_ctl); |
298b0b39 JB |
1114 | POSTING_READ(DP_A); |
1115 | udelay(200); | |
d240f20f JB |
1116 | } |
1117 | ||
1118 | static void ironlake_edp_pll_off(struct drm_encoder *encoder) | |
1119 | { | |
1120 | struct drm_device *dev = encoder->dev; | |
1121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1122 | u32 dpa_ctl; | |
1123 | ||
1124 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 1125 | dpa_ctl &= ~DP_PLL_ENABLE; |
d240f20f | 1126 | I915_WRITE(DP_A, dpa_ctl); |
1af5fa1b | 1127 | POSTING_READ(DP_A); |
d240f20f JB |
1128 | udelay(200); |
1129 | } | |
1130 | ||
c7ad3810 JB |
1131 | /* If the sink supports it, try to set the power state appropriately */ |
1132 | static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) | |
1133 | { | |
1134 | int ret, i; | |
1135 | ||
1136 | /* Should have a valid DPCD by this point */ | |
1137 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
1138 | return; | |
1139 | ||
1140 | if (mode != DRM_MODE_DPMS_ON) { | |
1141 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, | |
1142 | DP_SET_POWER_D3); | |
1143 | if (ret != 1) | |
1144 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); | |
1145 | } else { | |
1146 | /* | |
1147 | * When turning on, we need to retry for 1ms to give the sink | |
1148 | * time to wake up. | |
1149 | */ | |
1150 | for (i = 0; i < 3; i++) { | |
1151 | ret = intel_dp_aux_native_write_1(intel_dp, | |
1152 | DP_SET_POWER, | |
1153 | DP_SET_POWER_D0); | |
1154 | if (ret == 1) | |
1155 | break; | |
1156 | msleep(1); | |
1157 | } | |
1158 | } | |
1159 | } | |
1160 | ||
d240f20f JB |
1161 | static void intel_dp_prepare(struct drm_encoder *encoder) |
1162 | { | |
1163 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
d240f20f | 1164 | |
c7ad3810 | 1165 | /* Wake up the sink first */ |
f58ff854 | 1166 | ironlake_edp_panel_vdd_on(intel_dp); |
c7ad3810 | 1167 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
bd943159 | 1168 | ironlake_edp_panel_vdd_off(intel_dp, false); |
c7ad3810 | 1169 | |
f01eca2e KP |
1170 | /* Make sure the panel is off before trying to |
1171 | * change the mode | |
1172 | */ | |
1173 | ironlake_edp_backlight_off(intel_dp); | |
736085bc | 1174 | intel_dp_link_down(intel_dp); |
f01eca2e | 1175 | ironlake_edp_panel_off(encoder); |
d240f20f JB |
1176 | } |
1177 | ||
1178 | static void intel_dp_commit(struct drm_encoder *encoder) | |
1179 | { | |
1180 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
d240f20f | 1181 | |
97af61f5 | 1182 | ironlake_edp_panel_vdd_on(intel_dp); |
f01eca2e | 1183 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 1184 | intel_dp_start_link_train(intel_dp); |
97af61f5 | 1185 | ironlake_edp_panel_on(intel_dp); |
bd943159 KP |
1186 | ironlake_edp_panel_vdd_off(intel_dp, true); |
1187 | ||
33a34e4e | 1188 | intel_dp_complete_link_train(intel_dp); |
f01eca2e | 1189 | ironlake_edp_backlight_on(intel_dp); |
d2b996ac KP |
1190 | |
1191 | intel_dp->dpms_mode = DRM_MODE_DPMS_ON; | |
d240f20f JB |
1192 | } |
1193 | ||
a4fc5ed6 KP |
1194 | static void |
1195 | intel_dp_dpms(struct drm_encoder *encoder, int mode) | |
1196 | { | |
ea5b213a | 1197 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
55f78c43 | 1198 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 | 1199 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1200 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
a4fc5ed6 KP |
1201 | |
1202 | if (mode != DRM_MODE_DPMS_ON) { | |
245e2708 | 1203 | ironlake_edp_panel_vdd_on(intel_dp); |
01cb9ea6 | 1204 | if (is_edp(intel_dp)) |
f01eca2e | 1205 | ironlake_edp_backlight_off(intel_dp); |
c7ad3810 | 1206 | intel_dp_sink_dpms(intel_dp, mode); |
736085bc | 1207 | intel_dp_link_down(intel_dp); |
f01eca2e | 1208 | ironlake_edp_panel_off(encoder); |
01cb9ea6 | 1209 | if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) |
d240f20f | 1210 | ironlake_edp_pll_off(encoder); |
bd943159 | 1211 | ironlake_edp_panel_vdd_off(intel_dp, false); |
a4fc5ed6 | 1212 | } else { |
97af61f5 | 1213 | ironlake_edp_panel_vdd_on(intel_dp); |
c7ad3810 | 1214 | intel_dp_sink_dpms(intel_dp, mode); |
32f9d658 | 1215 | if (!(dp_reg & DP_PORT_EN)) { |
01cb9ea6 | 1216 | intel_dp_start_link_train(intel_dp); |
97af61f5 | 1217 | ironlake_edp_panel_on(intel_dp); |
bd943159 | 1218 | ironlake_edp_panel_vdd_off(intel_dp, true); |
33a34e4e | 1219 | intel_dp_complete_link_train(intel_dp); |
f01eca2e | 1220 | ironlake_edp_backlight_on(intel_dp); |
bee7eb2d | 1221 | } else |
bd943159 KP |
1222 | ironlake_edp_panel_vdd_off(intel_dp, false); |
1223 | ironlake_edp_backlight_on(intel_dp); | |
a4fc5ed6 | 1224 | } |
d2b996ac | 1225 | intel_dp->dpms_mode = mode; |
a4fc5ed6 KP |
1226 | } |
1227 | ||
1228 | /* | |
df0c237d JB |
1229 | * Native read with retry for link status and receiver capability reads for |
1230 | * cases where the sink may still be asleep. | |
a4fc5ed6 KP |
1231 | */ |
1232 | static bool | |
df0c237d JB |
1233 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
1234 | uint8_t *recv, int recv_bytes) | |
a4fc5ed6 | 1235 | { |
61da5fab JB |
1236 | int ret, i; |
1237 | ||
df0c237d JB |
1238 | /* |
1239 | * Sinks are *supposed* to come up within 1ms from an off state, | |
1240 | * but we're also supposed to retry 3 times per the spec. | |
1241 | */ | |
61da5fab | 1242 | for (i = 0; i < 3; i++) { |
df0c237d JB |
1243 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
1244 | recv_bytes); | |
1245 | if (ret == recv_bytes) | |
61da5fab JB |
1246 | return true; |
1247 | msleep(1); | |
1248 | } | |
a4fc5ed6 | 1249 | |
61da5fab | 1250 | return false; |
a4fc5ed6 KP |
1251 | } |
1252 | ||
1253 | /* | |
1254 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
1255 | * link status information | |
1256 | */ | |
1257 | static bool | |
33a34e4e | 1258 | intel_dp_get_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 1259 | { |
df0c237d JB |
1260 | return intel_dp_aux_native_read_retry(intel_dp, |
1261 | DP_LANE0_1_STATUS, | |
1262 | intel_dp->link_status, | |
1263 | DP_LINK_STATUS_SIZE); | |
a4fc5ed6 KP |
1264 | } |
1265 | ||
1266 | static uint8_t | |
1267 | intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1268 | int r) | |
1269 | { | |
1270 | return link_status[r - DP_LANE0_1_STATUS]; | |
1271 | } | |
1272 | ||
a4fc5ed6 KP |
1273 | static uint8_t |
1274 | intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1275 | int lane) | |
1276 | { | |
1277 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
1278 | int s = ((lane & 1) ? | |
1279 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : | |
1280 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); | |
1281 | uint8_t l = intel_dp_link_status(link_status, i); | |
1282 | ||
1283 | return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; | |
1284 | } | |
1285 | ||
1286 | static uint8_t | |
1287 | intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1288 | int lane) | |
1289 | { | |
1290 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
1291 | int s = ((lane & 1) ? | |
1292 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : | |
1293 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); | |
1294 | uint8_t l = intel_dp_link_status(link_status, i); | |
1295 | ||
1296 | return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; | |
1297 | } | |
1298 | ||
1299 | ||
1300 | #if 0 | |
1301 | static char *voltage_names[] = { | |
1302 | "0.4V", "0.6V", "0.8V", "1.2V" | |
1303 | }; | |
1304 | static char *pre_emph_names[] = { | |
1305 | "0dB", "3.5dB", "6dB", "9.5dB" | |
1306 | }; | |
1307 | static char *link_train_names[] = { | |
1308 | "pattern 1", "pattern 2", "idle", "off" | |
1309 | }; | |
1310 | #endif | |
1311 | ||
1312 | /* | |
1313 | * These are source-specific values; current Intel hardware supports | |
1314 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
1315 | */ | |
1316 | #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 | |
1317 | ||
1318 | static uint8_t | |
1319 | intel_dp_pre_emphasis_max(uint8_t voltage_swing) | |
1320 | { | |
1321 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1322 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1323 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1324 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1325 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1326 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1327 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1328 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1329 | default: | |
1330 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1331 | } | |
1332 | } | |
1333 | ||
1334 | static void | |
33a34e4e | 1335 | intel_get_adjust_train(struct intel_dp *intel_dp) |
a4fc5ed6 KP |
1336 | { |
1337 | uint8_t v = 0; | |
1338 | uint8_t p = 0; | |
1339 | int lane; | |
1340 | ||
33a34e4e JB |
1341 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1342 | uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane); | |
1343 | uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane); | |
a4fc5ed6 KP |
1344 | |
1345 | if (this_v > v) | |
1346 | v = this_v; | |
1347 | if (this_p > p) | |
1348 | p = this_p; | |
1349 | } | |
1350 | ||
1351 | if (v >= I830_DP_VOLTAGE_MAX) | |
1352 | v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED; | |
1353 | ||
1354 | if (p >= intel_dp_pre_emphasis_max(v)) | |
1355 | p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
1356 | ||
1357 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 1358 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
1359 | } |
1360 | ||
1361 | static uint32_t | |
3cf2efb1 | 1362 | intel_dp_signal_levels(uint8_t train_set, int lane_count) |
a4fc5ed6 | 1363 | { |
3cf2efb1 | 1364 | uint32_t signal_levels = 0; |
a4fc5ed6 | 1365 | |
3cf2efb1 | 1366 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
a4fc5ed6 KP |
1367 | case DP_TRAIN_VOLTAGE_SWING_400: |
1368 | default: | |
1369 | signal_levels |= DP_VOLTAGE_0_4; | |
1370 | break; | |
1371 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1372 | signal_levels |= DP_VOLTAGE_0_6; | |
1373 | break; | |
1374 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1375 | signal_levels |= DP_VOLTAGE_0_8; | |
1376 | break; | |
1377 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1378 | signal_levels |= DP_VOLTAGE_1_2; | |
1379 | break; | |
1380 | } | |
3cf2efb1 | 1381 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
a4fc5ed6 KP |
1382 | case DP_TRAIN_PRE_EMPHASIS_0: |
1383 | default: | |
1384 | signal_levels |= DP_PRE_EMPHASIS_0; | |
1385 | break; | |
1386 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
1387 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
1388 | break; | |
1389 | case DP_TRAIN_PRE_EMPHASIS_6: | |
1390 | signal_levels |= DP_PRE_EMPHASIS_6; | |
1391 | break; | |
1392 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
1393 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
1394 | break; | |
1395 | } | |
1396 | return signal_levels; | |
1397 | } | |
1398 | ||
e3421a18 ZW |
1399 | /* Gen6's DP voltage swing and pre-emphasis control */ |
1400 | static uint32_t | |
1401 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
1402 | { | |
3c5a62b5 YL |
1403 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
1404 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
1405 | switch (signal_levels) { | |
e3421a18 | 1406 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1407 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
1408 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
1409 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1410 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; | |
e3421a18 | 1411 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
3c5a62b5 YL |
1412 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
1413 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; | |
e3421a18 | 1414 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3c5a62b5 YL |
1415 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
1416 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; | |
e3421a18 | 1417 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1418 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
1419 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; | |
e3421a18 | 1420 | default: |
3c5a62b5 YL |
1421 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
1422 | "0x%x\n", signal_levels); | |
1423 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
1424 | } |
1425 | } | |
1426 | ||
a4fc5ed6 KP |
1427 | static uint8_t |
1428 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1429 | int lane) | |
1430 | { | |
1431 | int i = DP_LANE0_1_STATUS + (lane >> 1); | |
1432 | int s = (lane & 1) * 4; | |
1433 | uint8_t l = intel_dp_link_status(link_status, i); | |
1434 | ||
1435 | return (l >> s) & 0xf; | |
1436 | } | |
1437 | ||
1438 | /* Check for clock recovery is done on all channels */ | |
1439 | static bool | |
1440 | intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) | |
1441 | { | |
1442 | int lane; | |
1443 | uint8_t lane_status; | |
1444 | ||
1445 | for (lane = 0; lane < lane_count; lane++) { | |
1446 | lane_status = intel_get_lane_status(link_status, lane); | |
1447 | if ((lane_status & DP_LANE_CR_DONE) == 0) | |
1448 | return false; | |
1449 | } | |
1450 | return true; | |
1451 | } | |
1452 | ||
1453 | /* Check to see if channel eq is done on all channels */ | |
1454 | #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ | |
1455 | DP_LANE_CHANNEL_EQ_DONE|\ | |
1456 | DP_LANE_SYMBOL_LOCKED) | |
1457 | static bool | |
33a34e4e | 1458 | intel_channel_eq_ok(struct intel_dp *intel_dp) |
a4fc5ed6 KP |
1459 | { |
1460 | uint8_t lane_align; | |
1461 | uint8_t lane_status; | |
1462 | int lane; | |
1463 | ||
33a34e4e | 1464 | lane_align = intel_dp_link_status(intel_dp->link_status, |
a4fc5ed6 KP |
1465 | DP_LANE_ALIGN_STATUS_UPDATED); |
1466 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) | |
1467 | return false; | |
33a34e4e JB |
1468 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
1469 | lane_status = intel_get_lane_status(intel_dp->link_status, lane); | |
a4fc5ed6 KP |
1470 | if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) |
1471 | return false; | |
1472 | } | |
1473 | return true; | |
1474 | } | |
1475 | ||
1476 | static bool | |
ea5b213a | 1477 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
a4fc5ed6 | 1478 | uint32_t dp_reg_value, |
58e10eb9 | 1479 | uint8_t dp_train_pat) |
a4fc5ed6 | 1480 | { |
4ef69c7a | 1481 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1482 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 KP |
1483 | int ret; |
1484 | ||
ea5b213a CW |
1485 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
1486 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 | 1487 | |
ea5b213a | 1488 | intel_dp_aux_native_write_1(intel_dp, |
a4fc5ed6 KP |
1489 | DP_TRAINING_PATTERN_SET, |
1490 | dp_train_pat); | |
1491 | ||
ea5b213a | 1492 | ret = intel_dp_aux_native_write(intel_dp, |
58e10eb9 CW |
1493 | DP_TRAINING_LANE0_SET, |
1494 | intel_dp->train_set, 4); | |
a4fc5ed6 KP |
1495 | if (ret != 4) |
1496 | return false; | |
1497 | ||
1498 | return true; | |
1499 | } | |
1500 | ||
33a34e4e | 1501 | /* Enable corresponding port and start training pattern 1 */ |
a4fc5ed6 | 1502 | static void |
33a34e4e | 1503 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 1504 | { |
4ef69c7a | 1505 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1506 | struct drm_i915_private *dev_priv = dev->dev_private; |
58e10eb9 | 1507 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); |
a4fc5ed6 KP |
1508 | int i; |
1509 | uint8_t voltage; | |
1510 | bool clock_recovery = false; | |
a4fc5ed6 | 1511 | int tries; |
e3421a18 | 1512 | u32 reg; |
ea5b213a | 1513 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1514 | |
e8519464 AJ |
1515 | /* |
1516 | * On CPT we have to enable the port in training pattern 1, which | |
1517 | * will happen below in intel_dp_set_link_train. Otherwise, enable | |
1518 | * the port and wait for it to become active. | |
1519 | */ | |
1520 | if (!HAS_PCH_CPT(dev)) { | |
1521 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
1522 | POSTING_READ(intel_dp->output_reg); | |
1523 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1524 | } | |
a4fc5ed6 | 1525 | |
3cf2efb1 CW |
1526 | /* Write the link configuration data */ |
1527 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, | |
1528 | intel_dp->link_configuration, | |
1529 | DP_LINK_CONFIGURATION_SIZE); | |
a4fc5ed6 KP |
1530 | |
1531 | DP |= DP_PORT_EN; | |
cfcb0fc9 | 1532 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1533 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1534 | else | |
1535 | DP &= ~DP_LINK_TRAIN_MASK; | |
33a34e4e | 1536 | memset(intel_dp->train_set, 0, 4); |
a4fc5ed6 KP |
1537 | voltage = 0xff; |
1538 | tries = 0; | |
1539 | clock_recovery = false; | |
1540 | for (;;) { | |
33a34e4e | 1541 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 | 1542 | uint32_t signal_levels; |
cfcb0fc9 | 1543 | if (IS_GEN6(dev) && is_edp(intel_dp)) { |
33a34e4e | 1544 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1545 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1546 | } else { | |
3cf2efb1 | 1547 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1548 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1549 | } | |
a4fc5ed6 | 1550 | |
cfcb0fc9 | 1551 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1552 | reg = DP | DP_LINK_TRAIN_PAT_1_CPT; |
1553 | else | |
1554 | reg = DP | DP_LINK_TRAIN_PAT_1; | |
1555 | ||
ea5b213a | 1556 | if (!intel_dp_set_link_train(intel_dp, reg, |
81055854 AJ |
1557 | DP_TRAINING_PATTERN_1 | |
1558 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 | 1559 | break; |
a4fc5ed6 KP |
1560 | /* Set training pattern 1 */ |
1561 | ||
3cf2efb1 CW |
1562 | udelay(100); |
1563 | if (!intel_dp_get_link_status(intel_dp)) | |
a4fc5ed6 | 1564 | break; |
a4fc5ed6 | 1565 | |
3cf2efb1 CW |
1566 | if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { |
1567 | clock_recovery = true; | |
1568 | break; | |
1569 | } | |
1570 | ||
1571 | /* Check to see if we've tried the max voltage */ | |
1572 | for (i = 0; i < intel_dp->lane_count; i++) | |
1573 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
a4fc5ed6 | 1574 | break; |
3cf2efb1 CW |
1575 | if (i == intel_dp->lane_count) |
1576 | break; | |
a4fc5ed6 | 1577 | |
3cf2efb1 CW |
1578 | /* Check to see if we've tried the same voltage 5 times */ |
1579 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { | |
1580 | ++tries; | |
1581 | if (tries == 5) | |
a4fc5ed6 | 1582 | break; |
3cf2efb1 CW |
1583 | } else |
1584 | tries = 0; | |
1585 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
a4fc5ed6 | 1586 | |
3cf2efb1 CW |
1587 | /* Compute new intel_dp->train_set as requested by target */ |
1588 | intel_get_adjust_train(intel_dp); | |
a4fc5ed6 KP |
1589 | } |
1590 | ||
33a34e4e JB |
1591 | intel_dp->DP = DP; |
1592 | } | |
1593 | ||
1594 | static void | |
1595 | intel_dp_complete_link_train(struct intel_dp *intel_dp) | |
1596 | { | |
4ef69c7a | 1597 | struct drm_device *dev = intel_dp->base.base.dev; |
33a34e4e JB |
1598 | struct drm_i915_private *dev_priv = dev->dev_private; |
1599 | bool channel_eq = false; | |
37f80975 | 1600 | int tries, cr_tries; |
33a34e4e JB |
1601 | u32 reg; |
1602 | uint32_t DP = intel_dp->DP; | |
1603 | ||
a4fc5ed6 KP |
1604 | /* channel equalization */ |
1605 | tries = 0; | |
37f80975 | 1606 | cr_tries = 0; |
a4fc5ed6 KP |
1607 | channel_eq = false; |
1608 | for (;;) { | |
33a34e4e | 1609 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 ZW |
1610 | uint32_t signal_levels; |
1611 | ||
37f80975 JB |
1612 | if (cr_tries > 5) { |
1613 | DRM_ERROR("failed to train DP, aborting\n"); | |
1614 | intel_dp_link_down(intel_dp); | |
1615 | break; | |
1616 | } | |
1617 | ||
cfcb0fc9 | 1618 | if (IS_GEN6(dev) && is_edp(intel_dp)) { |
33a34e4e | 1619 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1620 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1621 | } else { | |
3cf2efb1 | 1622 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count); |
e3421a18 ZW |
1623 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1624 | } | |
1625 | ||
cfcb0fc9 | 1626 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1627 | reg = DP | DP_LINK_TRAIN_PAT_2_CPT; |
1628 | else | |
1629 | reg = DP | DP_LINK_TRAIN_PAT_2; | |
a4fc5ed6 KP |
1630 | |
1631 | /* channel eq pattern */ | |
ea5b213a | 1632 | if (!intel_dp_set_link_train(intel_dp, reg, |
81055854 AJ |
1633 | DP_TRAINING_PATTERN_2 | |
1634 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 KP |
1635 | break; |
1636 | ||
3cf2efb1 CW |
1637 | udelay(400); |
1638 | if (!intel_dp_get_link_status(intel_dp)) | |
a4fc5ed6 | 1639 | break; |
a4fc5ed6 | 1640 | |
37f80975 JB |
1641 | /* Make sure clock is still ok */ |
1642 | if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) { | |
1643 | intel_dp_start_link_train(intel_dp); | |
1644 | cr_tries++; | |
1645 | continue; | |
1646 | } | |
1647 | ||
3cf2efb1 CW |
1648 | if (intel_channel_eq_ok(intel_dp)) { |
1649 | channel_eq = true; | |
1650 | break; | |
1651 | } | |
a4fc5ed6 | 1652 | |
37f80975 JB |
1653 | /* Try 5 times, then try clock recovery if that fails */ |
1654 | if (tries > 5) { | |
1655 | intel_dp_link_down(intel_dp); | |
1656 | intel_dp_start_link_train(intel_dp); | |
1657 | tries = 0; | |
1658 | cr_tries++; | |
1659 | continue; | |
1660 | } | |
a4fc5ed6 | 1661 | |
3cf2efb1 CW |
1662 | /* Compute new intel_dp->train_set as requested by target */ |
1663 | intel_get_adjust_train(intel_dp); | |
1664 | ++tries; | |
869184a6 | 1665 | } |
3cf2efb1 | 1666 | |
cfcb0fc9 | 1667 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) |
e3421a18 ZW |
1668 | reg = DP | DP_LINK_TRAIN_OFF_CPT; |
1669 | else | |
1670 | reg = DP | DP_LINK_TRAIN_OFF; | |
1671 | ||
ea5b213a CW |
1672 | I915_WRITE(intel_dp->output_reg, reg); |
1673 | POSTING_READ(intel_dp->output_reg); | |
1674 | intel_dp_aux_native_write_1(intel_dp, | |
a4fc5ed6 KP |
1675 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); |
1676 | } | |
1677 | ||
1678 | static void | |
ea5b213a | 1679 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 1680 | { |
4ef69c7a | 1681 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1682 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1683 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1684 | |
1b39d6f3 CW |
1685 | if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) |
1686 | return; | |
1687 | ||
28c97730 | 1688 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 1689 | |
cfcb0fc9 | 1690 | if (is_edp(intel_dp)) { |
32f9d658 | 1691 | DP &= ~DP_PLL_ENABLE; |
ea5b213a CW |
1692 | I915_WRITE(intel_dp->output_reg, DP); |
1693 | POSTING_READ(intel_dp->output_reg); | |
32f9d658 ZW |
1694 | udelay(100); |
1695 | } | |
1696 | ||
cfcb0fc9 | 1697 | if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) { |
e3421a18 | 1698 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a | 1699 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
e3421a18 ZW |
1700 | } else { |
1701 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a | 1702 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
e3421a18 | 1703 | } |
fe255d00 | 1704 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 1705 | |
fe255d00 | 1706 | msleep(17); |
5eb08b69 | 1707 | |
cfcb0fc9 | 1708 | if (is_edp(intel_dp)) |
32f9d658 | 1709 | DP |= DP_LINK_TRAIN_OFF; |
5bddd17f | 1710 | |
1b39d6f3 CW |
1711 | if (!HAS_PCH_CPT(dev) && |
1712 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { | |
31acbcc4 CW |
1713 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
1714 | ||
5bddd17f EA |
1715 | /* Hardware workaround: leaving our transcoder select |
1716 | * set to transcoder B while it's off will prevent the | |
1717 | * corresponding HDMI output on transcoder A. | |
1718 | * | |
1719 | * Combine this with another hardware workaround: | |
1720 | * transcoder select bit can only be cleared while the | |
1721 | * port is enabled. | |
1722 | */ | |
1723 | DP &= ~DP_PIPEB_SELECT; | |
1724 | I915_WRITE(intel_dp->output_reg, DP); | |
1725 | ||
1726 | /* Changes to enable or select take place the vblank | |
1727 | * after being written. | |
1728 | */ | |
31acbcc4 CW |
1729 | if (crtc == NULL) { |
1730 | /* We can arrive here never having been attached | |
1731 | * to a CRTC, for instance, due to inheriting | |
1732 | * random state from the BIOS. | |
1733 | * | |
1734 | * If the pipe is not running, play safe and | |
1735 | * wait for the clocks to stabilise before | |
1736 | * continuing. | |
1737 | */ | |
1738 | POSTING_READ(intel_dp->output_reg); | |
1739 | msleep(50); | |
1740 | } else | |
1741 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); | |
5bddd17f EA |
1742 | } |
1743 | ||
ea5b213a CW |
1744 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
1745 | POSTING_READ(intel_dp->output_reg); | |
f01eca2e | 1746 | msleep(intel_dp->panel_power_down_delay); |
a4fc5ed6 KP |
1747 | } |
1748 | ||
26d61aad KP |
1749 | static bool |
1750 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
92fd8fd1 | 1751 | { |
92fd8fd1 KP |
1752 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
1753 | sizeof (intel_dp->dpcd)) && | |
1754 | (intel_dp->dpcd[DP_DPCD_REV] != 0)) { | |
26d61aad | 1755 | return true; |
92fd8fd1 KP |
1756 | } |
1757 | ||
26d61aad | 1758 | return false; |
92fd8fd1 KP |
1759 | } |
1760 | ||
a4fc5ed6 KP |
1761 | /* |
1762 | * According to DP spec | |
1763 | * 5.1.2: | |
1764 | * 1. Read DPCD | |
1765 | * 2. Configure link according to Receiver Capabilities | |
1766 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
1767 | * 4. Check link status on receipt of hot-plug interrupt | |
1768 | */ | |
1769 | ||
1770 | static void | |
ea5b213a | 1771 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 1772 | { |
d2b996ac KP |
1773 | if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON) |
1774 | return; | |
59cd09e1 | 1775 | |
4ef69c7a | 1776 | if (!intel_dp->base.base.crtc) |
a4fc5ed6 KP |
1777 | return; |
1778 | ||
92fd8fd1 | 1779 | /* Try to read receiver status if the link appears to be up */ |
33a34e4e | 1780 | if (!intel_dp_get_link_status(intel_dp)) { |
ea5b213a | 1781 | intel_dp_link_down(intel_dp); |
a4fc5ed6 KP |
1782 | return; |
1783 | } | |
1784 | ||
92fd8fd1 | 1785 | /* Now read the DPCD to see if it's actually running */ |
26d61aad | 1786 | if (!intel_dp_get_dpcd(intel_dp)) { |
59cd09e1 JB |
1787 | intel_dp_link_down(intel_dp); |
1788 | return; | |
1789 | } | |
1790 | ||
33a34e4e | 1791 | if (!intel_channel_eq_ok(intel_dp)) { |
92fd8fd1 KP |
1792 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
1793 | drm_get_encoder_name(&intel_dp->base.base)); | |
33a34e4e JB |
1794 | intel_dp_start_link_train(intel_dp); |
1795 | intel_dp_complete_link_train(intel_dp); | |
1796 | } | |
a4fc5ed6 | 1797 | } |
a4fc5ed6 | 1798 | |
71ba9000 | 1799 | static enum drm_connector_status |
26d61aad | 1800 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 1801 | { |
26d61aad KP |
1802 | if (intel_dp_get_dpcd(intel_dp)) |
1803 | return connector_status_connected; | |
1804 | return connector_status_disconnected; | |
71ba9000 AJ |
1805 | } |
1806 | ||
5eb08b69 | 1807 | static enum drm_connector_status |
a9756bb5 | 1808 | ironlake_dp_detect(struct intel_dp *intel_dp) |
5eb08b69 | 1809 | { |
5eb08b69 ZW |
1810 | enum drm_connector_status status; |
1811 | ||
fe16d949 CW |
1812 | /* Can't disconnect eDP, but you can close the lid... */ |
1813 | if (is_edp(intel_dp)) { | |
1814 | status = intel_panel_detect(intel_dp->base.base.dev); | |
1815 | if (status == connector_status_unknown) | |
1816 | status = connector_status_connected; | |
1817 | return status; | |
1818 | } | |
01cb9ea6 | 1819 | |
26d61aad | 1820 | return intel_dp_detect_dpcd(intel_dp); |
5eb08b69 ZW |
1821 | } |
1822 | ||
a4fc5ed6 | 1823 | static enum drm_connector_status |
a9756bb5 | 1824 | g4x_dp_detect(struct intel_dp *intel_dp) |
a4fc5ed6 | 1825 | { |
4ef69c7a | 1826 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1827 | struct drm_i915_private *dev_priv = dev->dev_private; |
a9756bb5 | 1828 | uint32_t temp, bit; |
5eb08b69 | 1829 | |
ea5b213a | 1830 | switch (intel_dp->output_reg) { |
a4fc5ed6 KP |
1831 | case DP_B: |
1832 | bit = DPB_HOTPLUG_INT_STATUS; | |
1833 | break; | |
1834 | case DP_C: | |
1835 | bit = DPC_HOTPLUG_INT_STATUS; | |
1836 | break; | |
1837 | case DP_D: | |
1838 | bit = DPD_HOTPLUG_INT_STATUS; | |
1839 | break; | |
1840 | default: | |
1841 | return connector_status_unknown; | |
1842 | } | |
1843 | ||
1844 | temp = I915_READ(PORT_HOTPLUG_STAT); | |
1845 | ||
1846 | if ((temp & bit) == 0) | |
1847 | return connector_status_disconnected; | |
1848 | ||
26d61aad | 1849 | return intel_dp_detect_dpcd(intel_dp); |
a9756bb5 ZW |
1850 | } |
1851 | ||
8c241fef KP |
1852 | static struct edid * |
1853 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) | |
1854 | { | |
1855 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1856 | struct edid *edid; | |
1857 | ||
1858 | ironlake_edp_panel_vdd_on(intel_dp); | |
1859 | edid = drm_get_edid(connector, adapter); | |
bd943159 | 1860 | ironlake_edp_panel_vdd_off(intel_dp, false); |
8c241fef KP |
1861 | return edid; |
1862 | } | |
1863 | ||
1864 | static int | |
1865 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) | |
1866 | { | |
1867 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1868 | int ret; | |
1869 | ||
1870 | ironlake_edp_panel_vdd_on(intel_dp); | |
1871 | ret = intel_ddc_get_modes(connector, adapter); | |
bd943159 | 1872 | ironlake_edp_panel_vdd_off(intel_dp, false); |
8c241fef KP |
1873 | return ret; |
1874 | } | |
1875 | ||
1876 | ||
a9756bb5 ZW |
1877 | /** |
1878 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. | |
1879 | * | |
1880 | * \return true if DP port is connected. | |
1881 | * \return false if DP port is disconnected. | |
1882 | */ | |
1883 | static enum drm_connector_status | |
1884 | intel_dp_detect(struct drm_connector *connector, bool force) | |
1885 | { | |
1886 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1887 | struct drm_device *dev = intel_dp->base.base.dev; | |
1888 | enum drm_connector_status status; | |
1889 | struct edid *edid = NULL; | |
1890 | ||
1891 | intel_dp->has_audio = false; | |
1892 | ||
1893 | if (HAS_PCH_SPLIT(dev)) | |
1894 | status = ironlake_dp_detect(intel_dp); | |
1895 | else | |
1896 | status = g4x_dp_detect(intel_dp); | |
1b9be9d0 | 1897 | |
ac66ae83 AJ |
1898 | DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n", |
1899 | intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2], | |
1900 | intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5], | |
1901 | intel_dp->dpcd[6], intel_dp->dpcd[7]); | |
1b9be9d0 | 1902 | |
a9756bb5 ZW |
1903 | if (status != connector_status_connected) |
1904 | return status; | |
1905 | ||
f684960e CW |
1906 | if (intel_dp->force_audio) { |
1907 | intel_dp->has_audio = intel_dp->force_audio > 0; | |
1908 | } else { | |
8c241fef | 1909 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
f684960e CW |
1910 | if (edid) { |
1911 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
1912 | connector->display_info.raw_edid = NULL; | |
1913 | kfree(edid); | |
1914 | } | |
a9756bb5 ZW |
1915 | } |
1916 | ||
1917 | return connector_status_connected; | |
a4fc5ed6 KP |
1918 | } |
1919 | ||
1920 | static int intel_dp_get_modes(struct drm_connector *connector) | |
1921 | { | |
df0e9248 | 1922 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4ef69c7a | 1923 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1924 | struct drm_i915_private *dev_priv = dev->dev_private; |
1925 | int ret; | |
a4fc5ed6 KP |
1926 | |
1927 | /* We should parse the EDID data and find out if it has an audio sink | |
1928 | */ | |
1929 | ||
8c241fef | 1930 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
b9efc480 | 1931 | if (ret) { |
d15456de | 1932 | if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) { |
b9efc480 ZY |
1933 | struct drm_display_mode *newmode; |
1934 | list_for_each_entry(newmode, &connector->probed_modes, | |
1935 | head) { | |
d15456de KP |
1936 | if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) { |
1937 | intel_dp->panel_fixed_mode = | |
b9efc480 ZY |
1938 | drm_mode_duplicate(dev, newmode); |
1939 | break; | |
1940 | } | |
1941 | } | |
1942 | } | |
32f9d658 | 1943 | return ret; |
b9efc480 | 1944 | } |
32f9d658 ZW |
1945 | |
1946 | /* if eDP has no EDID, try to use fixed panel mode from VBT */ | |
4d926461 | 1947 | if (is_edp(intel_dp)) { |
47f0eb22 | 1948 | /* initialize panel mode from VBT if available for eDP */ |
d15456de KP |
1949 | if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) { |
1950 | intel_dp->panel_fixed_mode = | |
47f0eb22 | 1951 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
d15456de KP |
1952 | if (intel_dp->panel_fixed_mode) { |
1953 | intel_dp->panel_fixed_mode->type |= | |
47f0eb22 KP |
1954 | DRM_MODE_TYPE_PREFERRED; |
1955 | } | |
1956 | } | |
d15456de | 1957 | if (intel_dp->panel_fixed_mode) { |
32f9d658 | 1958 | struct drm_display_mode *mode; |
d15456de | 1959 | mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode); |
32f9d658 ZW |
1960 | drm_mode_probed_add(connector, mode); |
1961 | return 1; | |
1962 | } | |
1963 | } | |
1964 | return 0; | |
a4fc5ed6 KP |
1965 | } |
1966 | ||
1aad7ac0 CW |
1967 | static bool |
1968 | intel_dp_detect_audio(struct drm_connector *connector) | |
1969 | { | |
1970 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1971 | struct edid *edid; | |
1972 | bool has_audio = false; | |
1973 | ||
8c241fef | 1974 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
1aad7ac0 CW |
1975 | if (edid) { |
1976 | has_audio = drm_detect_monitor_audio(edid); | |
1977 | ||
1978 | connector->display_info.raw_edid = NULL; | |
1979 | kfree(edid); | |
1980 | } | |
1981 | ||
1982 | return has_audio; | |
1983 | } | |
1984 | ||
f684960e CW |
1985 | static int |
1986 | intel_dp_set_property(struct drm_connector *connector, | |
1987 | struct drm_property *property, | |
1988 | uint64_t val) | |
1989 | { | |
e953fd7b | 1990 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
f684960e CW |
1991 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
1992 | int ret; | |
1993 | ||
1994 | ret = drm_connector_property_set_value(connector, property, val); | |
1995 | if (ret) | |
1996 | return ret; | |
1997 | ||
3f43c48d | 1998 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
1999 | int i = val; |
2000 | bool has_audio; | |
2001 | ||
2002 | if (i == intel_dp->force_audio) | |
f684960e CW |
2003 | return 0; |
2004 | ||
1aad7ac0 | 2005 | intel_dp->force_audio = i; |
f684960e | 2006 | |
1aad7ac0 CW |
2007 | if (i == 0) |
2008 | has_audio = intel_dp_detect_audio(connector); | |
2009 | else | |
2010 | has_audio = i > 0; | |
2011 | ||
2012 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
2013 | return 0; |
2014 | ||
1aad7ac0 | 2015 | intel_dp->has_audio = has_audio; |
f684960e CW |
2016 | goto done; |
2017 | } | |
2018 | ||
e953fd7b CW |
2019 | if (property == dev_priv->broadcast_rgb_property) { |
2020 | if (val == !!intel_dp->color_range) | |
2021 | return 0; | |
2022 | ||
2023 | intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; | |
2024 | goto done; | |
2025 | } | |
2026 | ||
f684960e CW |
2027 | return -EINVAL; |
2028 | ||
2029 | done: | |
2030 | if (intel_dp->base.base.crtc) { | |
2031 | struct drm_crtc *crtc = intel_dp->base.base.crtc; | |
2032 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
2033 | crtc->x, crtc->y, | |
2034 | crtc->fb); | |
2035 | } | |
2036 | ||
2037 | return 0; | |
2038 | } | |
2039 | ||
a4fc5ed6 KP |
2040 | static void |
2041 | intel_dp_destroy (struct drm_connector *connector) | |
2042 | { | |
aaa6fd2a MG |
2043 | struct drm_device *dev = connector->dev; |
2044 | ||
2045 | if (intel_dpd_is_edp(dev)) | |
2046 | intel_panel_destroy_backlight(dev); | |
2047 | ||
a4fc5ed6 KP |
2048 | drm_sysfs_connector_remove(connector); |
2049 | drm_connector_cleanup(connector); | |
55f78c43 | 2050 | kfree(connector); |
a4fc5ed6 KP |
2051 | } |
2052 | ||
24d05927 DV |
2053 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
2054 | { | |
2055 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
2056 | ||
2057 | i2c_del_adapter(&intel_dp->adapter); | |
2058 | drm_encoder_cleanup(encoder); | |
bd943159 KP |
2059 | if (is_edp(intel_dp)) { |
2060 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
2061 | ironlake_panel_vdd_off_sync(intel_dp); | |
2062 | } | |
24d05927 DV |
2063 | kfree(intel_dp); |
2064 | } | |
2065 | ||
a4fc5ed6 KP |
2066 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
2067 | .dpms = intel_dp_dpms, | |
2068 | .mode_fixup = intel_dp_mode_fixup, | |
d240f20f | 2069 | .prepare = intel_dp_prepare, |
a4fc5ed6 | 2070 | .mode_set = intel_dp_mode_set, |
d240f20f | 2071 | .commit = intel_dp_commit, |
a4fc5ed6 KP |
2072 | }; |
2073 | ||
2074 | static const struct drm_connector_funcs intel_dp_connector_funcs = { | |
2075 | .dpms = drm_helper_connector_dpms, | |
a4fc5ed6 KP |
2076 | .detect = intel_dp_detect, |
2077 | .fill_modes = drm_helper_probe_single_connector_modes, | |
f684960e | 2078 | .set_property = intel_dp_set_property, |
a4fc5ed6 KP |
2079 | .destroy = intel_dp_destroy, |
2080 | }; | |
2081 | ||
2082 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
2083 | .get_modes = intel_dp_get_modes, | |
2084 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 2085 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
2086 | }; |
2087 | ||
a4fc5ed6 | 2088 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
24d05927 | 2089 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
2090 | }; |
2091 | ||
995b6762 | 2092 | static void |
21d40d37 | 2093 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 2094 | { |
ea5b213a | 2095 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
c8110e52 | 2096 | |
885a5014 | 2097 | intel_dp_check_link_status(intel_dp); |
c8110e52 | 2098 | } |
6207937d | 2099 | |
e3421a18 ZW |
2100 | /* Return which DP Port should be selected for Transcoder DP control */ |
2101 | int | |
2102 | intel_trans_dp_port_sel (struct drm_crtc *crtc) | |
2103 | { | |
2104 | struct drm_device *dev = crtc->dev; | |
2105 | struct drm_mode_config *mode_config = &dev->mode_config; | |
2106 | struct drm_encoder *encoder; | |
e3421a18 ZW |
2107 | |
2108 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
ea5b213a CW |
2109 | struct intel_dp *intel_dp; |
2110 | ||
d8201ab6 | 2111 | if (encoder->crtc != crtc) |
e3421a18 ZW |
2112 | continue; |
2113 | ||
ea5b213a CW |
2114 | intel_dp = enc_to_intel_dp(encoder); |
2115 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) | |
2116 | return intel_dp->output_reg; | |
e3421a18 | 2117 | } |
ea5b213a | 2118 | |
e3421a18 ZW |
2119 | return -1; |
2120 | } | |
2121 | ||
36e83a18 | 2122 | /* check the VBT to see whether the eDP is on DP-D port */ |
cb0953d7 | 2123 | bool intel_dpd_is_edp(struct drm_device *dev) |
36e83a18 ZY |
2124 | { |
2125 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2126 | struct child_device_config *p_child; | |
2127 | int i; | |
2128 | ||
2129 | if (!dev_priv->child_dev_num) | |
2130 | return false; | |
2131 | ||
2132 | for (i = 0; i < dev_priv->child_dev_num; i++) { | |
2133 | p_child = dev_priv->child_dev + i; | |
2134 | ||
2135 | if (p_child->dvo_port == PORT_IDPD && | |
2136 | p_child->device_type == DEVICE_TYPE_eDP) | |
2137 | return true; | |
2138 | } | |
2139 | return false; | |
2140 | } | |
2141 | ||
f684960e CW |
2142 | static void |
2143 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) | |
2144 | { | |
3f43c48d | 2145 | intel_attach_force_audio_property(connector); |
e953fd7b | 2146 | intel_attach_broadcast_rgb_property(connector); |
f684960e CW |
2147 | } |
2148 | ||
a4fc5ed6 KP |
2149 | void |
2150 | intel_dp_init(struct drm_device *dev, int output_reg) | |
2151 | { | |
2152 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2153 | struct drm_connector *connector; | |
ea5b213a | 2154 | struct intel_dp *intel_dp; |
21d40d37 | 2155 | struct intel_encoder *intel_encoder; |
55f78c43 | 2156 | struct intel_connector *intel_connector; |
5eb08b69 | 2157 | const char *name = NULL; |
b329530c | 2158 | int type; |
a4fc5ed6 | 2159 | |
ea5b213a CW |
2160 | intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); |
2161 | if (!intel_dp) | |
a4fc5ed6 KP |
2162 | return; |
2163 | ||
3d3dc149 | 2164 | intel_dp->output_reg = output_reg; |
d2b996ac | 2165 | intel_dp->dpms_mode = -1; |
3d3dc149 | 2166 | |
55f78c43 ZW |
2167 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
2168 | if (!intel_connector) { | |
ea5b213a | 2169 | kfree(intel_dp); |
55f78c43 ZW |
2170 | return; |
2171 | } | |
ea5b213a | 2172 | intel_encoder = &intel_dp->base; |
55f78c43 | 2173 | |
ea5b213a | 2174 | if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) |
b329530c | 2175 | if (intel_dpd_is_edp(dev)) |
ea5b213a | 2176 | intel_dp->is_pch_edp = true; |
b329530c | 2177 | |
cfcb0fc9 | 2178 | if (output_reg == DP_A || is_pch_edp(intel_dp)) { |
b329530c AJ |
2179 | type = DRM_MODE_CONNECTOR_eDP; |
2180 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
2181 | } else { | |
2182 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
2183 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
2184 | } | |
2185 | ||
55f78c43 | 2186 | connector = &intel_connector->base; |
b329530c | 2187 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
2188 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
2189 | ||
eb1f8e4f DA |
2190 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
2191 | ||
652af9d7 | 2192 | if (output_reg == DP_B || output_reg == PCH_DP_B) |
21d40d37 | 2193 | intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); |
652af9d7 | 2194 | else if (output_reg == DP_C || output_reg == PCH_DP_C) |
21d40d37 | 2195 | intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); |
652af9d7 | 2196 | else if (output_reg == DP_D || output_reg == PCH_DP_D) |
21d40d37 | 2197 | intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); |
f8aed700 | 2198 | |
bd943159 | 2199 | if (is_edp(intel_dp)) { |
21d40d37 | 2200 | intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); |
bd943159 KP |
2201 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
2202 | ironlake_panel_vdd_work); | |
2203 | } | |
6251ec0a | 2204 | |
21d40d37 | 2205 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
a4fc5ed6 KP |
2206 | connector->interlace_allowed = true; |
2207 | connector->doublescan_allowed = 0; | |
2208 | ||
4ef69c7a | 2209 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
a4fc5ed6 | 2210 | DRM_MODE_ENCODER_TMDS); |
4ef69c7a | 2211 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
a4fc5ed6 | 2212 | |
df0e9248 | 2213 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 KP |
2214 | drm_sysfs_connector_add(connector); |
2215 | ||
2216 | /* Set up the DDC bus. */ | |
5eb08b69 | 2217 | switch (output_reg) { |
32f9d658 ZW |
2218 | case DP_A: |
2219 | name = "DPDDC-A"; | |
2220 | break; | |
5eb08b69 ZW |
2221 | case DP_B: |
2222 | case PCH_DP_B: | |
b01f2c3a JB |
2223 | dev_priv->hotplug_supported_mask |= |
2224 | HDMIB_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2225 | name = "DPDDC-B"; |
2226 | break; | |
2227 | case DP_C: | |
2228 | case PCH_DP_C: | |
b01f2c3a JB |
2229 | dev_priv->hotplug_supported_mask |= |
2230 | HDMIC_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2231 | name = "DPDDC-C"; |
2232 | break; | |
2233 | case DP_D: | |
2234 | case PCH_DP_D: | |
b01f2c3a JB |
2235 | dev_priv->hotplug_supported_mask |= |
2236 | HDMID_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2237 | name = "DPDDC-D"; |
2238 | break; | |
2239 | } | |
2240 | ||
89667383 JB |
2241 | /* Cache some DPCD data in the eDP case */ |
2242 | if (is_edp(intel_dp)) { | |
59f3e272 | 2243 | bool ret; |
f01eca2e KP |
2244 | struct edp_power_seq cur, vbt; |
2245 | u32 pp_on, pp_off, pp_div; | |
5d613501 JB |
2246 | |
2247 | pp_on = I915_READ(PCH_PP_ON_DELAYS); | |
f01eca2e | 2248 | pp_off = I915_READ(PCH_PP_OFF_DELAYS); |
5d613501 | 2249 | pp_div = I915_READ(PCH_PP_DIVISOR); |
89667383 | 2250 | |
f01eca2e KP |
2251 | /* Pull timing values out of registers */ |
2252 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> | |
2253 | PANEL_POWER_UP_DELAY_SHIFT; | |
2254 | ||
2255 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> | |
2256 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
2257 | ||
2258 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> | |
2259 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
2260 | ||
2261 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> | |
2262 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
2263 | ||
2264 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
2265 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; | |
2266 | ||
2267 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
2268 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); | |
2269 | ||
2270 | vbt = dev_priv->edp.pps; | |
2271 | ||
2272 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
2273 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); | |
2274 | ||
2275 | #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10) | |
2276 | ||
2277 | intel_dp->panel_power_up_delay = get_delay(t1_t3); | |
2278 | intel_dp->backlight_on_delay = get_delay(t8); | |
2279 | intel_dp->backlight_off_delay = get_delay(t9); | |
2280 | intel_dp->panel_power_down_delay = get_delay(t10); | |
2281 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
2282 | ||
2283 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", | |
2284 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
2285 | intel_dp->panel_power_cycle_delay); | |
2286 | ||
2287 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
2288 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
5d613501 | 2289 | |
bd943159 KP |
2290 | intel_dp->panel_off_jiffies = jiffies - intel_dp->panel_power_down_delay; |
2291 | ||
5d613501 | 2292 | ironlake_edp_panel_vdd_on(intel_dp); |
59f3e272 | 2293 | ret = intel_dp_get_dpcd(intel_dp); |
bd943159 | 2294 | ironlake_edp_panel_vdd_off(intel_dp, false); |
59f3e272 | 2295 | if (ret) { |
7183dc29 JB |
2296 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
2297 | dev_priv->no_aux_handshake = | |
2298 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
89667383 JB |
2299 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
2300 | } else { | |
3d3dc149 | 2301 | /* if this fails, presume the device is a ghost */ |
48898b03 | 2302 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
3d3dc149 | 2303 | intel_dp_encoder_destroy(&intel_dp->base.base); |
48898b03 | 2304 | intel_dp_destroy(&intel_connector->base); |
3d3dc149 | 2305 | return; |
89667383 | 2306 | } |
89667383 JB |
2307 | } |
2308 | ||
552fb0b7 KP |
2309 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
2310 | ||
21d40d37 | 2311 | intel_encoder->hot_plug = intel_dp_hot_plug; |
a4fc5ed6 | 2312 | |
4d926461 | 2313 | if (is_edp(intel_dp)) { |
aaa6fd2a MG |
2314 | dev_priv->int_edp_connector = connector; |
2315 | intel_panel_setup_backlight(dev); | |
32f9d658 ZW |
2316 | } |
2317 | ||
f684960e CW |
2318 | intel_dp_add_properties(intel_dp, connector); |
2319 | ||
a4fc5ed6 KP |
2320 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
2321 | * 0xd. Failure to do so will result in spurious interrupts being | |
2322 | * generated on the port when a cable is not attached. | |
2323 | */ | |
2324 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
2325 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
2326 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
2327 | } | |
2328 | } |