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drm/i915/chv: Trigger phy common lane reset
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 94static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 95static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 96
a4fc5ed6 97static int
ea5b213a 98intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 99{
7183dc29 100 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 101 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 102
103 switch (max_link_bw) {
104 case DP_LINK_BW_1_62:
105 case DP_LINK_BW_2_7:
106 break;
d4eead50 107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
06ea66b6
TP		 108 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
109 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
110 max_link_bw = DP_LINK_BW_5_4;
111 else
112 max_link_bw = DP_LINK_BW_2_7;
d4eead50 113 break;
a4fc5ed6 114 default:
d4eead50
ID		 115 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
116 max_link_bw);
a4fc5ed6
KP		 117 max_link_bw = DP_LINK_BW_1_62;
118 break;
119 }
120 return max_link_bw;
121}
122
cd9dde44
AJ		 123/*
124 * The units on the numbers in the next two are... bizarre. Examples will
125 * make it clearer; this one parallels an example in the eDP spec.
126 *
127 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
128 *
129 * 270000 * 1 * 8 / 10 == 216000
130 *
131 * The actual data capacity of that configuration is 2.16Gbit/s, so the
132 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
133 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
134 * 119000. At 18bpp that's 2142000 kilobits per second.
135 *
136 * Thus the strange-looking division by 10 in intel_dp_link_required, to
137 * get the result in decakilobits instead of kilobits.
138 */
139
a4fc5ed6 140static int
c898261c 141intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 142{
cd9dde44 143 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 144}
145
fe27d53e
DA		 146static int
147intel_dp_max_data_rate(int max_link_clock, int max_lanes)
148{
149 return (max_link_clock * max_lanes * 8) / 10;
150}
151
c19de8eb 152static enum drm_mode_status
a4fc5ed6
KP		 153intel_dp_mode_valid(struct drm_connector *connector,
154 struct drm_display_mode *mode)
155{
df0e9248 156 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 157 struct intel_connector *intel_connector = to_intel_connector(connector);
158 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 159 int target_clock = mode->clock;
160 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 161
dd06f90e
JN		 162 if (is_edp(intel_dp) && fixed_mode) {
163 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 164 return MODE_PANEL;
165
dd06f90e 166 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 167 return MODE_PANEL;
03afc4a2
DV		 168
169 target_clock = fixed_mode->clock;
7de56f43
ZY		 170 }
171
36008365
DV		 172 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
173 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
174
175 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
176 mode_rate = intel_dp_link_required(target_clock, 18);
177
178 if (mode_rate > max_rate)
c4867936 179 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 180
181 if (mode->clock < 10000)
182 return MODE_CLOCK_LOW;
183
0af78a2b
DV		 184 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
185 return MODE_H_ILLEGAL;
186
a4fc5ed6
KP		 187 return MODE_OK;
188}
189
190static uint32_t
191pack_aux(uint8_t *src, int src_bytes)
192{
193 int i;
194 uint32_t v = 0;
195
196 if (src_bytes > 4)
197 src_bytes = 4;
198 for (i = 0; i < src_bytes; i++)
199 v |= ((uint32_t) src[i]) << ((3-i) * 8);
200 return v;
201}
202
203static void
204unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
205{
206 int i;
207 if (dst_bytes > 4)
208 dst_bytes = 4;
209 for (i = 0; i < dst_bytes; i++)
210 dst[i] = src >> ((3-i) * 8);
211}
212
fb0f8fbf
KP		 213/* hrawclock is 1/4 the FSB frequency */
214static int
215intel_hrawclk(struct drm_device *dev)
216{
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 uint32_t clkcfg;
219
9473c8f4
VP		 220 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
221 if (IS_VALLEYVIEW(dev))
222 return 200;
223
fb0f8fbf
KP		 224 clkcfg = I915_READ(CLKCFG);
225 switch (clkcfg & CLKCFG_FSB_MASK) {
226 case CLKCFG_FSB_400:
227 return 100;
228 case CLKCFG_FSB_533:
229 return 133;
230 case CLKCFG_FSB_667:
231 return 166;
232 case CLKCFG_FSB_800:
233 return 200;
234 case CLKCFG_FSB_1067:
235 return 266;
236 case CLKCFG_FSB_1333:
237 return 333;
238 /* these two are just a guess; one of them might be right */
239 case CLKCFG_FSB_1600:
240 case CLKCFG_FSB_1600_ALT:
241 return 400;
242 default:
243 return 133;
244 }
245}
246
bf13e81b
JN		 247static void
248intel_dp_init_panel_power_sequencer(struct drm_device *dev,
249 struct intel_dp *intel_dp,
250 struct edp_power_seq *out);
251static void
252intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
253 struct intel_dp *intel_dp,
254 struct edp_power_seq *out);
255
256static enum pipe
257vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
258{
259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
260 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
261 struct drm_device *dev = intel_dig_port->base.base.dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 enum port port = intel_dig_port->port;
264 enum pipe pipe;
265
266 /* modeset should have pipe */
267 if (crtc)
268 return to_intel_crtc(crtc)->pipe;
269
270 /* init time, try to find a pipe with this port selected */
271 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
272 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
273 PANEL_PORT_SELECT_MASK;
274 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
275 return pipe;
276 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
277 return pipe;
278 }
279
280 /* shrug */
281 return PIPE_A;
282}
283
284static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
285{
286 struct drm_device *dev = intel_dp_to_dev(intel_dp);
287
288 if (HAS_PCH_SPLIT(dev))
289 return PCH_PP_CONTROL;
290 else
291 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
292}
293
294static u32 _pp_stat_reg(struct intel_dp *intel_dp)
295{
296 struct drm_device *dev = intel_dp_to_dev(intel_dp);
297
298 if (HAS_PCH_SPLIT(dev))
299 return PCH_PP_STATUS;
300 else
301 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
302}
303
4be73780 304static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 305{
30add22d 306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 307 struct drm_i915_private *dev_priv = dev->dev_private;
308
bf13e81b 309 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 310}
311
4be73780 312static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 313{
30add22d 314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 315 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 316 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
317 struct intel_encoder *intel_encoder = &intel_dig_port->base;
318 enum intel_display_power_domain power_domain;
ebf33b18 319
bb4932c4
ID		 320 power_domain = intel_display_port_power_domain(intel_encoder);
321 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 322 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 323}
324
9b984dae
KP		 325static void
326intel_dp_check_edp(struct intel_dp *intel_dp)
327{
30add22d 328 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 329 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 330
9b984dae
KP		 331 if (!is_edp(intel_dp))
332 return;
453c5420 333
4be73780 334 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 335 WARN(1, "eDP powered off while attempting aux channel communication.\n");
336 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 337 I915_READ(_pp_stat_reg(intel_dp)),
338 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 339 }
340}
341
9ee32fea
DV		 342static uint32_t
343intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
344{
345 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
346 struct drm_device *dev = intel_dig_port->base.base.dev;
347 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 348 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 349 uint32_t status;
350 bool done;
351
ef04f00d 352#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 353 if (has_aux_irq)
b18ac466 354 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 355 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 356 else
357 done = wait_for_atomic(C, 10) == 0;
358 if (!done)
359 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
360 has_aux_irq);
361#undef C
362
363 return status;
364}
365
ec5b01dd 366static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 367{
174edf1f
PZ		 368 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
369 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 370
ec5b01dd
DL		 371 /*
372 * The clock divider is based off the hrawclk, and would like to run at
373 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 374 */
ec5b01dd
DL		 375 return index ? 0 : intel_hrawclk(dev) / 2;
376}
377
378static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
379{
380 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
381 struct drm_device *dev = intel_dig_port->base.base.dev;
382
383 if (index)
384 return 0;
385
386 if (intel_dig_port->port == PORT_A) {
387 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 388 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 389 else
b84a1cf8 390 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 391 } else {
392 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
393 }
394}
395
396static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
397{
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
400 struct drm_i915_private *dev_priv = dev->dev_private;
401
402 if (intel_dig_port->port == PORT_A) {
403 if (index)
404 return 0;
405 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 406 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
407 /* Workaround for non-ULT HSW */
bc86625a
CW		 408 switch (index) {
409 case 0: return 63;
410 case 1: return 72;
411 default: return 0;
412 }
ec5b01dd 413 } else {
bc86625a 414 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 415 }
b84a1cf8
RV		 416}
417
ec5b01dd
DL		 418static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
419{
420 return index ? 0 : 100;
421}
422
5ed12a19
DL		 423static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
424 bool has_aux_irq,
425 int send_bytes,
426 uint32_t aux_clock_divider)
427{
428 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
429 struct drm_device *dev = intel_dig_port->base.base.dev;
430 uint32_t precharge, timeout;
431
432 if (IS_GEN6(dev))
433 precharge = 3;
434 else
435 precharge = 5;
436
437 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
438 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
439 else
440 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
441
442 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 443 DP_AUX_CH_CTL_DONE |
5ed12a19 444 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 445 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 446 timeout |
788d4433 447 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 448 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
449 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 450 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 451}
452
b84a1cf8
RV		 453static int
454intel_dp_aux_ch(struct intel_dp *intel_dp,
455 uint8_t *send, int send_bytes,
456 uint8_t *recv, int recv_size)
457{
458 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
459 struct drm_device *dev = intel_dig_port->base.base.dev;
460 struct drm_i915_private *dev_priv = dev->dev_private;
461 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
462 uint32_t ch_data = ch_ctl + 4;
bc86625a 463 uint32_t aux_clock_divider;
b84a1cf8
RV		 464 int i, ret, recv_bytes;
465 uint32_t status;
5ed12a19 466 int try, clock = 0;
4e6b788c 467 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 468 bool vdd;
469
470 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 471
472 /* dp aux is extremely sensitive to irq latency, hence request the
473 * lowest possible wakeup latency and so prevent the cpu from going into
474 * deep sleep states.
475 */
476 pm_qos_update_request(&dev_priv->pm_qos, 0);
477
478 intel_dp_check_edp(intel_dp);
5eb08b69 479
c67a470b
PZ		 480 intel_aux_display_runtime_get(dev_priv);
481
11bee43e
JB		 482 /* Try to wait for any previous AUX channel activity */
483 for (try = 0; try < 3; try++) {
ef04f00d 484 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 485 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
486 break;
487 msleep(1);
488 }
489
490 if (try == 3) {
491 WARN(1, "dp_aux_ch not started status 0x%08x\n",
492 I915_READ(ch_ctl));
9ee32fea
DV		 493 ret = -EBUSY;
494 goto out;
4f7f7b7e
CW		 495 }
496
46a5ae9f
PZ		 497 /* Only 5 data registers! */
498 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
499 ret = -E2BIG;
500 goto out;
501 }
502
ec5b01dd 503 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 504 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
505 has_aux_irq,
506 send_bytes,
507 aux_clock_divider);
5ed12a19 508
bc86625a
CW		 509 /* Must try at least 3 times according to DP spec */
510 for (try = 0; try < 5; try++) {
511 /* Load the send data into the aux channel data registers */
512 for (i = 0; i < send_bytes; i += 4)
513 I915_WRITE(ch_data + i,
514 pack_aux(send + i, send_bytes - i));
515
516 /* Send the command and wait for it to complete */
5ed12a19 517 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 518
519 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
520
521 /* Clear done status and any errors */
522 I915_WRITE(ch_ctl,
523 status |
524 DP_AUX_CH_CTL_DONE |
525 DP_AUX_CH_CTL_TIME_OUT_ERROR |
526 DP_AUX_CH_CTL_RECEIVE_ERROR);
527
528 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
529 DP_AUX_CH_CTL_RECEIVE_ERROR))
530 continue;
531 if (status & DP_AUX_CH_CTL_DONE)
532 break;
533 }
4f7f7b7e 534 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 535 break;
536 }
537
a4fc5ed6 538 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 539 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 540 ret = -EBUSY;
541 goto out;
a4fc5ed6
KP		 542 }
543
544 /* Check for timeout or receive error.
545 * Timeouts occur when the sink is not connected
546 */
a5b3da54 547 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 548 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 549 ret = -EIO;
550 goto out;
a5b3da54 551 }
1ae8c0a5
KP		 552
553 /* Timeouts occur when the device isn't connected, so they're
554 * "normal" -- don't fill the kernel log with these */
a5b3da54 555 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 556 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 557 ret = -ETIMEDOUT;
558 goto out;
a4fc5ed6
KP		 559 }
560
561 /* Unload any bytes sent back from the other side */
562 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
563 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 564 if (recv_bytes > recv_size)
565 recv_bytes = recv_size;
0206e353 566
4f7f7b7e
CW		 567 for (i = 0; i < recv_bytes; i += 4)
568 unpack_aux(I915_READ(ch_data + i),
569 recv + i, recv_bytes - i);
a4fc5ed6 570
9ee32fea
DV		 571 ret = recv_bytes;
572out:
573 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 574 intel_aux_display_runtime_put(dev_priv);
9ee32fea 575
884f19e9
JN		 576 if (vdd)
577 edp_panel_vdd_off(intel_dp, false);
578
9ee32fea 579 return ret;
a4fc5ed6
KP		 580}
581
a6c8aff0
JN		 582#define BARE_ADDRESS_SIZE 3
583#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 584static ssize_t
585intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 586{
9d1a1031
JN		 587 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
588 uint8_t txbuf[20], rxbuf[20];
589 size_t txsize, rxsize;
a4fc5ed6 590 int ret;
a4fc5ed6 591
9d1a1031
JN		 592 txbuf[0] = msg->request << 4;
593 txbuf[1] = msg->address >> 8;
594 txbuf[2] = msg->address & 0xff;
595 txbuf[3] = msg->size - 1;
46a5ae9f 596
9d1a1031
JN		 597 switch (msg->request & ~DP_AUX_I2C_MOT) {
598 case DP_AUX_NATIVE_WRITE:
599 case DP_AUX_I2C_WRITE:
a6c8aff0 600 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 601 rxsize = 1;
f51a44b9 602
9d1a1031
JN		 603 if (WARN_ON(txsize > 20))
604 return -E2BIG;
a4fc5ed6 605
9d1a1031 606 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 607
9d1a1031
JN		 608 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
609 if (ret > 0) {
610 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 611
9d1a1031
JN		 612 /* Return payload size. */
613 ret = msg->size;
614 }
615 break;
46a5ae9f 616
9d1a1031
JN		 617 case DP_AUX_NATIVE_READ:
618 case DP_AUX_I2C_READ:
a6c8aff0 619 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 620 rxsize = msg->size + 1;
a4fc5ed6 621
9d1a1031
JN		 622 if (WARN_ON(rxsize > 20))
623 return -E2BIG;
a4fc5ed6 624
9d1a1031
JN		 625 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
626 if (ret > 0) {
627 msg->reply = rxbuf[0] >> 4;
628 /*
629 * Assume happy day, and copy the data. The caller is
630 * expected to check msg->reply before touching it.
631 *
632 * Return payload size.
633 */
634 ret--;
635 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 636 }
9d1a1031
JN		 637 break;
638
639 default:
640 ret = -EINVAL;
641 break;
a4fc5ed6 642 }
f51a44b9 643
9d1a1031 644 return ret;
a4fc5ed6
KP		 645}
646
9d1a1031
JN		 647static void
648intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
649{
650 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 651 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
652 enum port port = intel_dig_port->port;
0b99836f 653 const char *name = NULL;
ab2c0672
DA		 654 int ret;
655
33ad6626
JN		 656 switch (port) {
657 case PORT_A:
658 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 659 name = "DPDDC-A";
ab2c0672 660 break;
33ad6626
JN		 661 case PORT_B:
662 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 663 name = "DPDDC-B";
ab2c0672 664 break;
33ad6626
JN		 665 case PORT_C:
666 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 667 name = "DPDDC-C";
ab2c0672 668 break;
33ad6626
JN		 669 case PORT_D:
670 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 671 name = "DPDDC-D";
33ad6626
JN		 672 break;
673 default:
674 BUG();
ab2c0672
DA		 675 }
676
33ad6626
JN		 677 if (!HAS_DDI(dev))
678 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 679
0b99836f 680 intel_dp->aux.name = name;
9d1a1031
JN		 681 intel_dp->aux.dev = dev->dev;
682 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 683
0b99836f
JN		 684 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
685 connector->base.kdev->kobj.name);
8316f337 686
0b99836f
JN		 687 ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
688 if (ret < 0) {
689 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
690 name, ret);
691 return;
ab2c0672 692 }
8a5e6aeb 693
0b99836f
JN		 694 ret = sysfs_create_link(&connector->base.kdev->kobj,
695 &intel_dp->aux.ddc.dev.kobj,
696 intel_dp->aux.ddc.dev.kobj.name);
697 if (ret < 0) {
698 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
699 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
ab2c0672 700 }
a4fc5ed6
KP		 701}
702
80f65de3
ID		 703static void
704intel_dp_connector_unregister(struct intel_connector *intel_connector)
705{
706 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
707
708 sysfs_remove_link(&intel_connector->base.kdev->kobj,
0b99836f 709 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 710 intel_connector_unregister(intel_connector);
711}
712
c6bb3538
DV		 713static void
714intel_dp_set_clock(struct intel_encoder *encoder,
715 struct intel_crtc_config *pipe_config, int link_bw)
716{
717 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 718 const struct dp_link_dpll *divisor = NULL;
719 int i, count = 0;
c6bb3538
DV		 720
721 if (IS_G4X(dev)) {
9dd4ffdf
CML		 722 divisor = gen4_dpll;
723 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 724 } else if (IS_HASWELL(dev)) {
725 /* Haswell has special-purpose DP DDI clocks. */
726 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 727 divisor = pch_dpll;
728 count = ARRAY_SIZE(pch_dpll);
c6bb3538 729 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 730 divisor = vlv_dpll;
731 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 732 }
9dd4ffdf
CML		 733
734 if (divisor && count) {
735 for (i = 0; i < count; i++) {
736 if (link_bw == divisor[i].link_bw) {
737 pipe_config->dpll = divisor[i].dpll;
738 pipe_config->clock_set = true;
739 break;
740 }
741 }
c6bb3538
DV		 742 }
743}
744
439d7ac0
PB		 745static void
746intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
747{
748 struct drm_device *dev = crtc->base.dev;
749 struct drm_i915_private *dev_priv = dev->dev_private;
750 enum transcoder transcoder = crtc->config.cpu_transcoder;
751
752 I915_WRITE(PIPE_DATA_M2(transcoder),
753 TU_SIZE(m_n->tu) | m_n->gmch_m);
754 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
755 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
756 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
757}
758
00c09d70 759bool
5bfe2ac0
DV		 760intel_dp_compute_config(struct intel_encoder *encoder,
761 struct intel_crtc_config *pipe_config)
a4fc5ed6 762{
5bfe2ac0 763 struct drm_device *dev = encoder->base.dev;
36008365 764 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 765 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 766 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 767 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 768 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 769 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 770 int lane_count, clock;
397fe157 771 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
06ea66b6
TP		 772 /* Conveniently, the link BW constants become indices with a shift...*/
773 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 774 int bpp, mode_rate;
06ea66b6 775 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 776 int link_avail, link_clock;
a4fc5ed6 777
bc7d38a4 778 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 779 pipe_config->has_pch_encoder = true;
780
03afc4a2 781 pipe_config->has_dp_encoder = true;
a4fc5ed6 782
dd06f90e
JN		 783 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
784 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
785 adjusted_mode);
2dd24552
JB		 786 if (!HAS_PCH_SPLIT(dev))
787 intel_gmch_panel_fitting(intel_crtc, pipe_config,
788 intel_connector->panel.fitting_mode);
789 else
b074cec8
JB		 790 intel_pch_panel_fitting(intel_crtc, pipe_config,
791 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 792 }
793
cb1793ce 794 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 795 return false;
796
083f9560
DV		 797 DRM_DEBUG_KMS("DP link computation with max lane count %i "
798 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 799 max_lane_count, bws[max_clock],
800 adjusted_mode->crtc_clock);
083f9560 801
36008365
DV		 802 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
803 * bpc in between. */
3e7ca985 804 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 805 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
806 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 807 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
808 dev_priv->vbt.edp_bpp);
6da7f10d 809 bpp = dev_priv->vbt.edp_bpp;
7984211e 810 }
657445fe 811
36008365 812 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 813 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
814 bpp);
36008365 815
38aecea0
DV		 816 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
817 for (clock = 0; clock <= max_clock; clock++) {
36008365
DV		 818 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
819 link_avail = intel_dp_max_data_rate(link_clock,
820 lane_count);
821
822 if (mode_rate <= link_avail) {
823 goto found;
824 }
825 }
826 }
827 }
c4867936 828
36008365 829 return false;
3685a8f3 830
36008365 831found:
55bc60db
VS		 832 if (intel_dp->color_range_auto) {
833 /*
834 * See:
835 * CEA-861-E - 5.1 Default Encoding Parameters
836 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
837 */
18316c8c 838 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 839 intel_dp->color_range = DP_COLOR_RANGE_16_235;
840 else
841 intel_dp->color_range = 0;
842 }
843
3685a8f3 844 if (intel_dp->color_range)
50f3b016 845 pipe_config->limited_color_range = true;
a4fc5ed6 846
36008365
DV		 847 intel_dp->link_bw = bws[clock];
848 intel_dp->lane_count = lane_count;
657445fe 849 pipe_config->pipe_bpp = bpp;
ff9a6750 850 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 851
36008365
DV		 852 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
853 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 854 pipe_config->port_clock, bpp);
36008365
DV		 855 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
856 mode_rate, link_avail);
a4fc5ed6 857
03afc4a2 858 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 859 adjusted_mode->crtc_clock,
860 pipe_config->port_clock,
03afc4a2 861 &pipe_config->dp_m_n);
9d1a455b 862
439d7ac0
PB		 863 if (intel_connector->panel.downclock_mode != NULL &&
864 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
865 intel_link_compute_m_n(bpp, lane_count,
866 intel_connector->panel.downclock_mode->clock,
867 pipe_config->port_clock,
868 &pipe_config->dp_m2_n2);
869 }
870
c6bb3538
DV		 871 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
872
03afc4a2 873 return true;
a4fc5ed6
KP		 874}
875
7c62a164 876static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 877{
7c62a164
DV		 878 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
879 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
880 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 881 struct drm_i915_private *dev_priv = dev->dev_private;
882 u32 dpa_ctl;
883
ff9a6750 884 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 885 dpa_ctl = I915_READ(DP_A);
886 dpa_ctl &= ~DP_PLL_FREQ_MASK;
887
ff9a6750 888 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 889 /* For a long time we've carried around a ILK-DevA w/a for the
890 * 160MHz clock. If we're really unlucky, it's still required.
891 */
892 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 893 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 894 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 895 } else {
896 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 897 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 898 }
1ce17038 899
ea9b6006
DV		 900 I915_WRITE(DP_A, dpa_ctl);
901
902 POSTING_READ(DP_A);
903 udelay(500);
904}
905
b934223d 906static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 907{
b934223d 908 struct drm_device *dev = encoder->base.dev;
417e822d 909 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 910 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 911 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 912 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
913 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 914
417e822d 915 /*
1a2eb460 916 * There are four kinds of DP registers:
417e822d
KP		 917 *
918 * IBX PCH
1a2eb460
KP		 919 * SNB CPU
920 * IVB CPU
417e822d
KP		 921 * CPT PCH
922 *
923 * IBX PCH and CPU are the same for almost everything,
924 * except that the CPU DP PLL is configured in this
925 * register
926 *
927 * CPT PCH is quite different, having many bits moved
928 * to the TRANS_DP_CTL register instead. That
929 * configuration happens (oddly) in ironlake_pch_enable
930 */
9c9e7927 931
417e822d
KP		 932 /* Preserve the BIOS-computed detected bit. This is
933 * supposed to be read-only.
934 */
935 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 936
417e822d 937 /* Handle DP bits in common between all three register formats */
417e822d 938 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 939 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 940
e0dac65e
WF		 941 if (intel_dp->has_audio) {
942 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 943 pipe_name(crtc->pipe));
ea5b213a 944 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 945 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 946 }
247d89f6 947
417e822d 948 /* Split out the IBX/CPU vs CPT settings */
32f9d658 949
bc7d38a4 950 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 951 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
952 intel_dp->DP |= DP_SYNC_HS_HIGH;
953 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
954 intel_dp->DP |= DP_SYNC_VS_HIGH;
955 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
956
6aba5b6c 957 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 958 intel_dp->DP |= DP_ENHANCED_FRAMING;
959
7c62a164 960 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 961 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 962 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 963 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 964
965 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
966 intel_dp->DP |= DP_SYNC_HS_HIGH;
967 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
968 intel_dp->DP |= DP_SYNC_VS_HIGH;
969 intel_dp->DP |= DP_LINK_TRAIN_OFF;
970
6aba5b6c 971 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 972 intel_dp->DP |= DP_ENHANCED_FRAMING;
973
7c62a164 974 if (crtc->pipe == 1)
417e822d 975 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 976 } else {
977 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 978 }
ea9b6006 979
bc7d38a4 980 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 981 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 982}
983
ffd6749d
PZ		 984#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
985#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 986
1a5ef5b7
PZ		 987#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
988#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 989
ffd6749d
PZ		 990#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
991#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 992
4be73780 993static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 994 u32 mask,
995 u32 value)
bd943159 996{
30add22d 997 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 998 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 999 u32 pp_stat_reg, pp_ctrl_reg;
1000
bf13e81b
JN		 1001 pp_stat_reg = _pp_stat_reg(intel_dp);
1002 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1003
99ea7127 1004 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1005 mask, value,
1006 I915_READ(pp_stat_reg),
1007 I915_READ(pp_ctrl_reg));
32ce697c 1008
453c5420 1009 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1010 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1011 I915_READ(pp_stat_reg),
1012 I915_READ(pp_ctrl_reg));
32ce697c 1013 }
54c136d4
CW		 1014
1015 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1016}
32ce697c 1017
4be73780 1018static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1019{
1020 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1021 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1022}
1023
4be73780 1024static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1025{
1026 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1027 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1028}
1029
4be73780 1030static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1031{
1032 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1033
1034 /* When we disable the VDD override bit last we have to do the manual
1035 * wait. */
1036 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1037 intel_dp->panel_power_cycle_delay);
1038
4be73780 1039 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1040}
1041
4be73780 1042static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1043{
1044 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1045 intel_dp->backlight_on_delay);
1046}
1047
4be73780 1048static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1049{
1050 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1051 intel_dp->backlight_off_delay);
1052}
99ea7127 1053
832dd3c1
KP		 1054/* Read the current pp_control value, unlocking the register if it
1055 * is locked
1056 */
1057
453c5420 1058static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1059{
453c5420
JB		 1060 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1061 struct drm_i915_private *dev_priv = dev->dev_private;
1062 u32 control;
832dd3c1 1063
bf13e81b 1064 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1065 control &= ~PANEL_UNLOCK_MASK;
1066 control |= PANEL_UNLOCK_REGS;
1067 return control;
bd943159
KP		 1068}
1069
adddaaf4 1070static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1071{
30add22d 1072 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1073 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1074 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1075 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1076 enum intel_display_power_domain power_domain;
5d613501 1077 u32 pp;
453c5420 1078 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1079 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1080
97af61f5 1081 if (!is_edp(intel_dp))
adddaaf4 1082 return false;
bd943159
KP		 1083
1084 intel_dp->want_panel_vdd = true;
99ea7127 1085
4be73780 1086 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1087 return need_to_disable;
b0665d57 1088
4e6e1a54
ID		 1089 power_domain = intel_display_port_power_domain(intel_encoder);
1090 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1091
b0665d57 1092 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1093
4be73780
DV		 1094 if (!edp_have_panel_power(intel_dp))
1095 wait_panel_power_cycle(intel_dp);
99ea7127 1096
453c5420 1097 pp = ironlake_get_pp_control(intel_dp);
5d613501 1098 pp |= EDP_FORCE_VDD;
ebf33b18 1099
bf13e81b
JN		 1100 pp_stat_reg = _pp_stat_reg(intel_dp);
1101 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1102
1103 I915_WRITE(pp_ctrl_reg, pp);
1104 POSTING_READ(pp_ctrl_reg);
1105 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1106 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1107 /*
1108 * If the panel wasn't on, delay before accessing aux channel
1109 */
4be73780 1110 if (!edp_have_panel_power(intel_dp)) {
bd943159 1111 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1112 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1113 }
adddaaf4
JN		 1114
1115 return need_to_disable;
1116}
1117
b80d6c78 1118void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1119{
1120 if (is_edp(intel_dp)) {
1121 bool vdd = _edp_panel_vdd_on(intel_dp);
1122
1123 WARN(!vdd, "eDP VDD already requested on\n");
1124 }
5d613501
JB		 1125}
1126
4be73780 1127static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1128{
30add22d 1129 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1130 struct drm_i915_private *dev_priv = dev->dev_private;
1131 u32 pp;
453c5420 1132 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1133
a0e99e68
DV		 1134 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1135
4be73780 1136 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
4e6e1a54
ID		 1137 struct intel_digital_port *intel_dig_port =
1138 dp_to_dig_port(intel_dp);
1139 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1140 enum intel_display_power_domain power_domain;
1141
b0665d57
PZ		 1142 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1143
453c5420 1144 pp = ironlake_get_pp_control(intel_dp);
bd943159 1145 pp &= ~EDP_FORCE_VDD;
bd943159 1146
9f08ef59
PZ		 1147 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1148 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1149
1150 I915_WRITE(pp_ctrl_reg, pp);
1151 POSTING_READ(pp_ctrl_reg);
99ea7127 1152
453c5420
JB		 1153 /* Make sure sequencer is idle before allowing subsequent activity */
1154 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1155 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1156
1157 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1158 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1159
4e6e1a54
ID		 1160 power_domain = intel_display_port_power_domain(intel_encoder);
1161 intel_display_power_put(dev_priv, power_domain);
bd943159
KP		 1162 }
1163}
5d613501 1164
4be73780 1165static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1166{
1167 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1168 struct intel_dp, panel_vdd_work);
30add22d 1169 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1170
627f7675 1171 mutex_lock(&dev->mode_config.mutex);
4be73780 1172 edp_panel_vdd_off_sync(intel_dp);
627f7675 1173 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1174}
1175
4be73780 1176static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1177{
97af61f5
KP		 1178 if (!is_edp(intel_dp))
1179 return;
5d613501 1180
bd943159 1181 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1182
bd943159
KP		 1183 intel_dp->want_panel_vdd = false;
1184
1185 if (sync) {
4be73780 1186 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1187 } else {
1188 /*
1189 * Queue the timer to fire a long
1190 * time from now (relative to the power down delay)
1191 * to keep the panel power up across a sequence of operations
1192 */
1193 schedule_delayed_work(&intel_dp->panel_vdd_work,
1194 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1195 }
5d613501
JB		 1196}
1197
4be73780 1198void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1199{
30add22d 1200 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1201 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1202 u32 pp;
453c5420 1203 u32 pp_ctrl_reg;
9934c132 1204
97af61f5 1205 if (!is_edp(intel_dp))
bd943159 1206 return;
99ea7127
KP		 1207
1208 DRM_DEBUG_KMS("Turn eDP power on\n");
1209
4be73780 1210 if (edp_have_panel_power(intel_dp)) {
99ea7127 1211 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1212 return;
99ea7127 1213 }
9934c132 1214
4be73780 1215 wait_panel_power_cycle(intel_dp);
37c6c9b0 1216
bf13e81b 1217 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1218 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1219 if (IS_GEN5(dev)) {
1220 /* ILK workaround: disable reset around power sequence */
1221 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1222 I915_WRITE(pp_ctrl_reg, pp);
1223 POSTING_READ(pp_ctrl_reg);
05ce1a49 1224 }
37c6c9b0 1225
1c0ae80a 1226 pp |= POWER_TARGET_ON;
99ea7127
KP		 1227 if (!IS_GEN5(dev))
1228 pp |= PANEL_POWER_RESET;
1229
453c5420
JB		 1230 I915_WRITE(pp_ctrl_reg, pp);
1231 POSTING_READ(pp_ctrl_reg);
9934c132 1232
4be73780 1233 wait_panel_on(intel_dp);
dce56b3c 1234 intel_dp->last_power_on = jiffies;
9934c132 1235
05ce1a49
KP		 1236 if (IS_GEN5(dev)) {
1237 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1238 I915_WRITE(pp_ctrl_reg, pp);
1239 POSTING_READ(pp_ctrl_reg);
05ce1a49 1240 }
9934c132
JB		 1241}
1242
4be73780 1243void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1244{
4e6e1a54
ID		 1245 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1246 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1247 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1248 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1249 enum intel_display_power_domain power_domain;
99ea7127 1250 u32 pp;
453c5420 1251 u32 pp_ctrl_reg;
9934c132 1252
97af61f5
KP		 1253 if (!is_edp(intel_dp))
1254 return;
37c6c9b0 1255
99ea7127 1256 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1257
4be73780 1258 edp_wait_backlight_off(intel_dp);
dce56b3c 1259
24f3e092
JN		 1260 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1261
453c5420 1262 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1263 /* We need to switch off panel power _and_ force vdd, for otherwise some
1264 * panels get very unhappy and cease to work. */
b3064154
PJ		 1265 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1266 EDP_BLC_ENABLE);
453c5420 1267
bf13e81b 1268 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1269
849e39f5
PZ		 1270 intel_dp->want_panel_vdd = false;
1271
453c5420
JB		 1272 I915_WRITE(pp_ctrl_reg, pp);
1273 POSTING_READ(pp_ctrl_reg);
9934c132 1274
dce56b3c 1275 intel_dp->last_power_cycle = jiffies;
4be73780 1276 wait_panel_off(intel_dp);
849e39f5
PZ		 1277
1278 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1279 power_domain = intel_display_port_power_domain(intel_encoder);
1280 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1281}
1282
4be73780 1283void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1284{
da63a9f2
PZ		 1285 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1286 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1287 struct drm_i915_private *dev_priv = dev->dev_private;
1288 u32 pp;
453c5420 1289 u32 pp_ctrl_reg;
32f9d658 1290
f01eca2e
KP		 1291 if (!is_edp(intel_dp))
1292 return;
1293
28c97730 1294 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1295 /*
1296 * If we enable the backlight right away following a panel power
1297 * on, we may see slight flicker as the panel syncs with the eDP
1298 * link. So delay a bit to make sure the image is solid before
1299 * allowing it to appear.
1300 */
4be73780 1301 wait_backlight_on(intel_dp);
453c5420 1302 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1303 pp |= EDP_BLC_ENABLE;
453c5420 1304
bf13e81b 1305 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1306
1307 I915_WRITE(pp_ctrl_reg, pp);
1308 POSTING_READ(pp_ctrl_reg);
035aa3de 1309
752aa88a 1310 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1311}
1312
4be73780 1313void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1314{
30add22d 1315 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1316 struct drm_i915_private *dev_priv = dev->dev_private;
1317 u32 pp;
453c5420 1318 u32 pp_ctrl_reg;
32f9d658 1319
f01eca2e
KP		 1320 if (!is_edp(intel_dp))
1321 return;
1322
752aa88a 1323 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1324
28c97730 1325 DRM_DEBUG_KMS("\n");
453c5420 1326 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1327 pp &= ~EDP_BLC_ENABLE;
453c5420 1328
bf13e81b 1329 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1330
1331 I915_WRITE(pp_ctrl_reg, pp);
1332 POSTING_READ(pp_ctrl_reg);
dce56b3c 1333 intel_dp->last_backlight_off = jiffies;
32f9d658 1334}
a4fc5ed6 1335
2bd2ad64 1336static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1337{
da63a9f2
PZ		 1338 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1339 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1340 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1341 struct drm_i915_private *dev_priv = dev->dev_private;
1342 u32 dpa_ctl;
1343
2bd2ad64
DV		 1344 assert_pipe_disabled(dev_priv,
1345 to_intel_crtc(crtc)->pipe);
1346
d240f20f
JB		 1347 DRM_DEBUG_KMS("\n");
1348 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1349 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1350 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1351
1352 /* We don't adjust intel_dp->DP while tearing down the link, to
1353 * facilitate link retraining (e.g. after hotplug). Hence clear all
1354 * enable bits here to ensure that we don't enable too much. */
1355 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1356 intel_dp->DP |= DP_PLL_ENABLE;
1357 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1358 POSTING_READ(DP_A);
1359 udelay(200);
d240f20f
JB		 1360}
1361
2bd2ad64 1362static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1363{
da63a9f2
PZ		 1364 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1365 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1366 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 u32 dpa_ctl;
1369
2bd2ad64
DV		 1370 assert_pipe_disabled(dev_priv,
1371 to_intel_crtc(crtc)->pipe);
1372
d240f20f 1373 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1374 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1375 "dp pll off, should be on\n");
1376 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1377
1378 /* We can't rely on the value tracked for the DP register in
1379 * intel_dp->DP because link_down must not change that (otherwise link
1380 * re-training will fail. */
298b0b39 1381 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1382 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1383 POSTING_READ(DP_A);
d240f20f
JB		 1384 udelay(200);
1385}
1386
c7ad3810 1387/* If the sink supports it, try to set the power state appropriately */
c19b0669 1388void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1389{
1390 int ret, i;
1391
1392 /* Should have a valid DPCD by this point */
1393 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1394 return;
1395
1396 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1397 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1398 DP_SET_POWER_D3);
c7ad3810
JB		 1399 if (ret != 1)
1400 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1401 } else {
1402 /*
1403 * When turning on, we need to retry for 1ms to give the sink
1404 * time to wake up.
1405 */
1406 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1407 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1408 DP_SET_POWER_D0);
c7ad3810
JB		 1409 if (ret == 1)
1410 break;
1411 msleep(1);
1412 }
1413 }
1414}
1415
19d8fe15
DV		 1416static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1417 enum pipe *pipe)
d240f20f 1418{
19d8fe15 1419 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1420 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1421 struct drm_device *dev = encoder->base.dev;
1422 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1423 enum intel_display_power_domain power_domain;
1424 u32 tmp;
1425
1426 power_domain = intel_display_port_power_domain(encoder);
1427 if (!intel_display_power_enabled(dev_priv, power_domain))
1428 return false;
1429
1430 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1431
1432 if (!(tmp & DP_PORT_EN))
1433 return false;
1434
bc7d38a4 1435 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1436 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1437 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1438 *pipe = PORT_TO_PIPE(tmp);
1439 } else {
1440 u32 trans_sel;
1441 u32 trans_dp;
1442 int i;
1443
1444 switch (intel_dp->output_reg) {
1445 case PCH_DP_B:
1446 trans_sel = TRANS_DP_PORT_SEL_B;
1447 break;
1448 case PCH_DP_C:
1449 trans_sel = TRANS_DP_PORT_SEL_C;
1450 break;
1451 case PCH_DP_D:
1452 trans_sel = TRANS_DP_PORT_SEL_D;
1453 break;
1454 default:
1455 return true;
1456 }
1457
1458 for_each_pipe(i) {
1459 trans_dp = I915_READ(TRANS_DP_CTL(i));
1460 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1461 *pipe = i;
1462 return true;
1463 }
1464 }
19d8fe15 1465
4a0833ec
DV		 1466 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1467 intel_dp->output_reg);
1468 }
d240f20f 1469
19d8fe15
DV		 1470 return true;
1471}
d240f20f 1472
045ac3b5
JB		 1473static void intel_dp_get_config(struct intel_encoder *encoder,
1474 struct intel_crtc_config *pipe_config)
1475{
1476 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1477 u32 tmp, flags = 0;
63000ef6
XZ		 1478 struct drm_device *dev = encoder->base.dev;
1479 struct drm_i915_private *dev_priv = dev->dev_private;
1480 enum port port = dp_to_dig_port(intel_dp)->port;
1481 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1482 int dotclock;
045ac3b5 1483
63000ef6
XZ		 1484 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1485 tmp = I915_READ(intel_dp->output_reg);
1486 if (tmp & DP_SYNC_HS_HIGH)
1487 flags |= DRM_MODE_FLAG_PHSYNC;
1488 else
1489 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1490
63000ef6
XZ		 1491 if (tmp & DP_SYNC_VS_HIGH)
1492 flags |= DRM_MODE_FLAG_PVSYNC;
1493 else
1494 flags |= DRM_MODE_FLAG_NVSYNC;
1495 } else {
1496 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1497 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1498 flags |= DRM_MODE_FLAG_PHSYNC;
1499 else
1500 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1501
63000ef6
XZ		 1502 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1503 flags |= DRM_MODE_FLAG_PVSYNC;
1504 else
1505 flags |= DRM_MODE_FLAG_NVSYNC;
1506 }
045ac3b5
JB		 1507
1508 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1509
eb14cb74
VS		 1510 pipe_config->has_dp_encoder = true;
1511
1512 intel_dp_get_m_n(crtc, pipe_config);
1513
18442d08 1514 if (port == PORT_A) {
f1f644dc
JB		 1515 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1516 pipe_config->port_clock = 162000;
1517 else
1518 pipe_config->port_clock = 270000;
1519 }
18442d08
VS		 1520
1521 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1522 &pipe_config->dp_m_n);
1523
1524 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1525 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1526
241bfc38 1527 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1528
c6cd2ee2
JN		 1529 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1530 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1531 /*
1532 * This is a big fat ugly hack.
1533 *
1534 * Some machines in UEFI boot mode provide us a VBT that has 18
1535 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1536 * unknown we fail to light up. Yet the same BIOS boots up with
1537 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1538 * max, not what it tells us to use.
1539 *
1540 * Note: This will still be broken if the eDP panel is not lit
1541 * up by the BIOS, and thus we can't get the mode at module
1542 * load.
1543 */
1544 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1545 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1546 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1547 }
045ac3b5
JB		 1548}
1549
a031d709 1550static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1551{
a031d709
RV		 1552 struct drm_i915_private *dev_priv = dev->dev_private;
1553
1554 return dev_priv->psr.sink_support;
2293bb5c
SK		 1555}
1556
2b28bb1b
RV		 1557static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1558{
1559 struct drm_i915_private *dev_priv = dev->dev_private;
1560
18b5992c 1561 if (!HAS_PSR(dev))
2b28bb1b
RV		 1562 return false;
1563
18b5992c 1564 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1565}
1566
1567static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1568 struct edp_vsc_psr *vsc_psr)
1569{
1570 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1571 struct drm_device *dev = dig_port->base.base.dev;
1572 struct drm_i915_private *dev_priv = dev->dev_private;
1573 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1574 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1575 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1576 uint32_t *data = (uint32_t *) vsc_psr;
1577 unsigned int i;
1578
1579 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1580 the video DIP being updated before program video DIP data buffer
1581 registers for DIP being updated. */
1582 I915_WRITE(ctl_reg, 0);
1583 POSTING_READ(ctl_reg);
1584
1585 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1586 if (i < sizeof(struct edp_vsc_psr))
1587 I915_WRITE(data_reg + i, *data++);
1588 else
1589 I915_WRITE(data_reg + i, 0);
1590 }
1591
1592 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1593 POSTING_READ(ctl_reg);
1594}
1595
1596static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1597{
1598 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1599 struct drm_i915_private *dev_priv = dev->dev_private;
1600 struct edp_vsc_psr psr_vsc;
1601
1602 if (intel_dp->psr_setup_done)
1603 return;
1604
1605 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1606 memset(&psr_vsc, 0, sizeof(psr_vsc));
1607 psr_vsc.sdp_header.HB0 = 0;
1608 psr_vsc.sdp_header.HB1 = 0x7;
1609 psr_vsc.sdp_header.HB2 = 0x2;
1610 psr_vsc.sdp_header.HB3 = 0x8;
1611 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1612
1613 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1614 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1615 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1616
1617 intel_dp->psr_setup_done = true;
1618}
1619
1620static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1621{
1622 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1623 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1624 uint32_t aux_clock_divider;
2b28bb1b
RV		 1625 int precharge = 0x3;
1626 int msg_size = 5; /* Header(4) + Message(1) */
1627
ec5b01dd
DL		 1628 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1629
2b28bb1b
RV		 1630 /* Enable PSR in sink */
1631 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
9d1a1031
JN		 1632 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1633 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1634 else
9d1a1031
JN		 1635 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1636 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1637
1638 /* Setup AUX registers */
18b5992c
BW		 1639 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1640 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1641 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1642 DP_AUX_CH_CTL_TIME_OUT_400us |
1643 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1644 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1645 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1646}
1647
1648static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1649{
1650 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1651 struct drm_i915_private *dev_priv = dev->dev_private;
1652 uint32_t max_sleep_time = 0x1f;
1653 uint32_t idle_frames = 1;
1654 uint32_t val = 0x0;
ed8546ac 1655 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1656
1657 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1658 val |= EDP_PSR_LINK_STANDBY;
1659 val |= EDP_PSR_TP2_TP3_TIME_0us;
1660 val |= EDP_PSR_TP1_TIME_0us;
1661 val |= EDP_PSR_SKIP_AUX_EXIT;
1662 } else
1663 val |= EDP_PSR_LINK_DISABLE;
1664
18b5992c 1665 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1666 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1667 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1668 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1669 EDP_PSR_ENABLE);
1670}
1671
3f51e471
RV		 1672static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1673{
1674 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1675 struct drm_device *dev = dig_port->base.base.dev;
1676 struct drm_i915_private *dev_priv = dev->dev_private;
1677 struct drm_crtc *crtc = dig_port->base.base.crtc;
1678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f4510a27 1679 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1680 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1681
a031d709
RV		 1682 dev_priv->psr.source_ok = false;
1683
18b5992c 1684 if (!HAS_PSR(dev)) {
3f51e471 1685 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1686 return false;
1687 }
1688
1689 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1690 (dig_port->port != PORT_A)) {
1691 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1692 return false;
1693 }
1694
d330a953 1695 if (!i915.enable_psr) {
105b7c11 1696 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1697 return false;
1698 }
1699
cd234b0b
CW		 1700 crtc = dig_port->base.base.crtc;
1701 if (crtc == NULL) {
1702 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1703 return false;
1704 }
1705
1706 intel_crtc = to_intel_crtc(crtc);
20ddf665 1707 if (!intel_crtc_active(crtc)) {
3f51e471 1708 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1709 return false;
1710 }
1711
f4510a27 1712 obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1713 if (obj->tiling_mode != I915_TILING_X ||
1714 obj->fence_reg == I915_FENCE_REG_NONE) {
1715 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1716 return false;
1717 }
1718
1719 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1720 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1721 return false;
1722 }
1723
1724 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1725 S3D_ENABLE) {
1726 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1727 return false;
1728 }
1729
ca73b4f0 1730 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1731 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1732 return false;
1733 }
1734
a031d709 1735 dev_priv->psr.source_ok = true;
3f51e471
RV		 1736 return true;
1737}
1738
3d739d92 1739static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1740{
1741 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1742
3f51e471
RV		 1743 if (!intel_edp_psr_match_conditions(intel_dp) ||
1744 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1745 return;
1746
1747 /* Setup PSR once */
1748 intel_edp_psr_setup(intel_dp);
1749
1750 /* Enable PSR on the panel */
1751 intel_edp_psr_enable_sink(intel_dp);
1752
1753 /* Enable PSR on the host */
1754 intel_edp_psr_enable_source(intel_dp);
1755}
1756
3d739d92
RV		 1757void intel_edp_psr_enable(struct intel_dp *intel_dp)
1758{
1759 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1760
1761 if (intel_edp_psr_match_conditions(intel_dp) &&
1762 !intel_edp_is_psr_enabled(dev))
1763 intel_edp_psr_do_enable(intel_dp);
1764}
1765
2b28bb1b
RV		 1766void intel_edp_psr_disable(struct intel_dp *intel_dp)
1767{
1768 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1769 struct drm_i915_private *dev_priv = dev->dev_private;
1770
1771 if (!intel_edp_is_psr_enabled(dev))
1772 return;
1773
18b5992c
BW		 1774 I915_WRITE(EDP_PSR_CTL(dev),
1775 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1776
1777 /* Wait till PSR is idle */
18b5992c 1778 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1779 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1780 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1781}
1782
3d739d92
RV		 1783void intel_edp_psr_update(struct drm_device *dev)
1784{
1785 struct intel_encoder *encoder;
1786 struct intel_dp *intel_dp = NULL;
1787
1788 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1789 if (encoder->type == INTEL_OUTPUT_EDP) {
1790 intel_dp = enc_to_intel_dp(&encoder->base);
1791
a031d709 1792 if (!is_edp_psr(dev))
3d739d92
RV		 1793 return;
1794
1795 if (!intel_edp_psr_match_conditions(intel_dp))
1796 intel_edp_psr_disable(intel_dp);
1797 else
1798 if (!intel_edp_is_psr_enabled(dev))
1799 intel_edp_psr_do_enable(intel_dp);
1800 }
1801}
1802
e8cb4558 1803static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1804{
e8cb4558 1805 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1806 enum port port = dp_to_dig_port(intel_dp)->port;
1807 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1808
1809 /* Make sure the panel is off before trying to change the mode. But also
1810 * ensure that we have vdd while we switch off the panel. */
24f3e092 1811 intel_edp_panel_vdd_on(intel_dp);
4be73780 1812 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1813 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1814 intel_edp_panel_off(intel_dp);
3739850b
DV		 1815
1816 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1817 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1818 intel_dp_link_down(intel_dp);
d240f20f
JB		 1819}
1820
49277c31 1821static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1822{
2bd2ad64 1823 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1824 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 1825
49277c31
VS		 1826 if (port != PORT_A)
1827 return;
1828
1829 intel_dp_link_down(intel_dp);
1830 ironlake_edp_pll_off(intel_dp);
1831}
1832
1833static void vlv_post_disable_dp(struct intel_encoder *encoder)
1834{
1835 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1836
1837 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 1838}
1839
e8cb4558 1840static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1841{
e8cb4558
DV		 1842 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1843 struct drm_device *dev = encoder->base.dev;
1844 struct drm_i915_private *dev_priv = dev->dev_private;
1845 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1846
0c33d8d7
DV		 1847 if (WARN_ON(dp_reg & DP_PORT_EN))
1848 return;
5d613501 1849
24f3e092 1850 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 1851 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1852 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1853 intel_edp_panel_on(intel_dp);
1854 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1855 intel_dp_complete_link_train(intel_dp);
3ab9c637 1856 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1857}
89b667f8 1858
ecff4f3b
JN		 1859static void g4x_enable_dp(struct intel_encoder *encoder)
1860{
828f5c6e
JN		 1861 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1862
ecff4f3b 1863 intel_enable_dp(encoder);
4be73780 1864 intel_edp_backlight_on(intel_dp);
ab1f90f9 1865}
89b667f8 1866
ab1f90f9
JN		 1867static void vlv_enable_dp(struct intel_encoder *encoder)
1868{
828f5c6e
JN		 1869 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1870
4be73780 1871 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1872}
1873
ecff4f3b 1874static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1875{
1876 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1877 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1878
1879 if (dport->port == PORT_A)
1880 ironlake_edp_pll_on(intel_dp);
1881}
1882
1883static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1884{
2bd2ad64 1885 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1886 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1887 struct drm_device *dev = encoder->base.dev;
89b667f8 1888 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1889 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1890 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1891 int pipe = intel_crtc->pipe;
bf13e81b 1892 struct edp_power_seq power_seq;
ab1f90f9 1893 u32 val;
a4fc5ed6 1894
ab1f90f9 1895 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1896
ab3c759a 1897 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1898 val = 0;
1899 if (pipe)
1900 val |= (1<<21);
1901 else
1902 val &= ~(1<<21);
1903 val |= 0x001000c4;
ab3c759a
CML		 1904 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1905 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1906 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1907
ab1f90f9
JN		 1908 mutex_unlock(&dev_priv->dpio_lock);
1909
2cac613b
ID		 1910 if (is_edp(intel_dp)) {
1911 /* init power sequencer on this pipe and port */
1912 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1913 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1914 &power_seq);
1915 }
bf13e81b 1916
ab1f90f9
JN		 1917 intel_enable_dp(encoder);
1918
e4607fcf 1919 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1920}
1921
ecff4f3b 1922static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1923{
1924 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1925 struct drm_device *dev = encoder->base.dev;
1926 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1927 struct intel_crtc *intel_crtc =
1928 to_intel_crtc(encoder->base.crtc);
e4607fcf 1929 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1930 int pipe = intel_crtc->pipe;
89b667f8 1931
89b667f8 1932 /* Program Tx lane resets to default */
0980a60f 1933 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 1934 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 1935 DPIO_PCS_TX_LANE2_RESET |
1936 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 1937 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 1938 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1939 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1940 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1941 DPIO_PCS_CLK_SOFT_RESET);
1942
1943 /* Fix up inter-pair skew failure */
ab3c759a
CML		 1944 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1945 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1946 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 1947 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1948}
1949
1950/*
df0c237d
JB		 1951 * Native read with retry for link status and receiver capability reads for
1952 * cases where the sink may still be asleep.
9d1a1031
JN		 1953 *
1954 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
1955 * supposed to retry 3 times per the spec.
a4fc5ed6 1956 */
9d1a1031
JN		 1957static ssize_t
1958intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
1959 void *buffer, size_t size)
a4fc5ed6 1960{
9d1a1031
JN		 1961 ssize_t ret;
1962 int i;
61da5fab 1963
61da5fab 1964 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1965 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
1966 if (ret == size)
1967 return ret;
61da5fab
JB		 1968 msleep(1);
1969 }
a4fc5ed6 1970
9d1a1031 1971 return ret;
a4fc5ed6
KP		 1972}
1973
1974/*
1975 * Fetch AUX CH registers 0x202 - 0x207 which contain
1976 * link status information
1977 */
1978static bool
93f62dad 1979intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1980{
9d1a1031
JN		 1981 return intel_dp_dpcd_read_wake(&intel_dp->aux,
1982 DP_LANE0_1_STATUS,
1983 link_status,
1984 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 1985}
1986
a4fc5ed6
KP		 1987/*
1988 * These are source-specific values; current Intel hardware supports
1989 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1990 */
a4fc5ed6
KP		 1991
1992static uint8_t
1a2eb460 1993intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1994{
30add22d 1995 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1996 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1997
8f93f4f1 1998 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 1999 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2000 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2001 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2002 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2003 return DP_TRAIN_VOLTAGE_SWING_1200;
2004 else
2005 return DP_TRAIN_VOLTAGE_SWING_800;
2006}
2007
2008static uint8_t
2009intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2010{
30add22d 2011 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2012 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2013
8f93f4f1
PZ		 2014 if (IS_BROADWELL(dev)) {
2015 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2016 case DP_TRAIN_VOLTAGE_SWING_400:
2017 case DP_TRAIN_VOLTAGE_SWING_600:
2018 return DP_TRAIN_PRE_EMPHASIS_6;
2019 case DP_TRAIN_VOLTAGE_SWING_800:
2020 return DP_TRAIN_PRE_EMPHASIS_3_5;
2021 case DP_TRAIN_VOLTAGE_SWING_1200:
2022 default:
2023 return DP_TRAIN_PRE_EMPHASIS_0;
2024 }
2025 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 2026 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2027 case DP_TRAIN_VOLTAGE_SWING_400:
2028 return DP_TRAIN_PRE_EMPHASIS_9_5;
2029 case DP_TRAIN_VOLTAGE_SWING_600:
2030 return DP_TRAIN_PRE_EMPHASIS_6;
2031 case DP_TRAIN_VOLTAGE_SWING_800:
2032 return DP_TRAIN_PRE_EMPHASIS_3_5;
2033 case DP_TRAIN_VOLTAGE_SWING_1200:
2034 default:
2035 return DP_TRAIN_PRE_EMPHASIS_0;
2036 }
e2fa6fba
P		 2037 } else if (IS_VALLEYVIEW(dev)) {
2038 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2039 case DP_TRAIN_VOLTAGE_SWING_400:
2040 return DP_TRAIN_PRE_EMPHASIS_9_5;
2041 case DP_TRAIN_VOLTAGE_SWING_600:
2042 return DP_TRAIN_PRE_EMPHASIS_6;
2043 case DP_TRAIN_VOLTAGE_SWING_800:
2044 return DP_TRAIN_PRE_EMPHASIS_3_5;
2045 case DP_TRAIN_VOLTAGE_SWING_1200:
2046 default:
2047 return DP_TRAIN_PRE_EMPHASIS_0;
2048 }
bc7d38a4 2049 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2050 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2051 case DP_TRAIN_VOLTAGE_SWING_400:
2052 return DP_TRAIN_PRE_EMPHASIS_6;
2053 case DP_TRAIN_VOLTAGE_SWING_600:
2054 case DP_TRAIN_VOLTAGE_SWING_800:
2055 return DP_TRAIN_PRE_EMPHASIS_3_5;
2056 default:
2057 return DP_TRAIN_PRE_EMPHASIS_0;
2058 }
2059 } else {
2060 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2061 case DP_TRAIN_VOLTAGE_SWING_400:
2062 return DP_TRAIN_PRE_EMPHASIS_6;
2063 case DP_TRAIN_VOLTAGE_SWING_600:
2064 return DP_TRAIN_PRE_EMPHASIS_6;
2065 case DP_TRAIN_VOLTAGE_SWING_800:
2066 return DP_TRAIN_PRE_EMPHASIS_3_5;
2067 case DP_TRAIN_VOLTAGE_SWING_1200:
2068 default:
2069 return DP_TRAIN_PRE_EMPHASIS_0;
2070 }
a4fc5ed6
KP		 2071 }
2072}
2073
e2fa6fba
P		 2074static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2075{
2076 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2077 struct drm_i915_private *dev_priv = dev->dev_private;
2078 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2079 struct intel_crtc *intel_crtc =
2080 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2081 unsigned long demph_reg_value, preemph_reg_value,
2082 uniqtranscale_reg_value;
2083 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2084 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2085 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2086
2087 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2088 case DP_TRAIN_PRE_EMPHASIS_0:
2089 preemph_reg_value = 0x0004000;
2090 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2091 case DP_TRAIN_VOLTAGE_SWING_400:
2092 demph_reg_value = 0x2B405555;
2093 uniqtranscale_reg_value = 0x552AB83A;
2094 break;
2095 case DP_TRAIN_VOLTAGE_SWING_600:
2096 demph_reg_value = 0x2B404040;
2097 uniqtranscale_reg_value = 0x5548B83A;
2098 break;
2099 case DP_TRAIN_VOLTAGE_SWING_800:
2100 demph_reg_value = 0x2B245555;
2101 uniqtranscale_reg_value = 0x5560B83A;
2102 break;
2103 case DP_TRAIN_VOLTAGE_SWING_1200:
2104 demph_reg_value = 0x2B405555;
2105 uniqtranscale_reg_value = 0x5598DA3A;
2106 break;
2107 default:
2108 return 0;
2109 }
2110 break;
2111 case DP_TRAIN_PRE_EMPHASIS_3_5:
2112 preemph_reg_value = 0x0002000;
2113 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2114 case DP_TRAIN_VOLTAGE_SWING_400:
2115 demph_reg_value = 0x2B404040;
2116 uniqtranscale_reg_value = 0x5552B83A;
2117 break;
2118 case DP_TRAIN_VOLTAGE_SWING_600:
2119 demph_reg_value = 0x2B404848;
2120 uniqtranscale_reg_value = 0x5580B83A;
2121 break;
2122 case DP_TRAIN_VOLTAGE_SWING_800:
2123 demph_reg_value = 0x2B404040;
2124 uniqtranscale_reg_value = 0x55ADDA3A;
2125 break;
2126 default:
2127 return 0;
2128 }
2129 break;
2130 case DP_TRAIN_PRE_EMPHASIS_6:
2131 preemph_reg_value = 0x0000000;
2132 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2133 case DP_TRAIN_VOLTAGE_SWING_400:
2134 demph_reg_value = 0x2B305555;
2135 uniqtranscale_reg_value = 0x5570B83A;
2136 break;
2137 case DP_TRAIN_VOLTAGE_SWING_600:
2138 demph_reg_value = 0x2B2B4040;
2139 uniqtranscale_reg_value = 0x55ADDA3A;
2140 break;
2141 default:
2142 return 0;
2143 }
2144 break;
2145 case DP_TRAIN_PRE_EMPHASIS_9_5:
2146 preemph_reg_value = 0x0006000;
2147 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2148 case DP_TRAIN_VOLTAGE_SWING_400:
2149 demph_reg_value = 0x1B405555;
2150 uniqtranscale_reg_value = 0x55ADDA3A;
2151 break;
2152 default:
2153 return 0;
2154 }
2155 break;
2156 default:
2157 return 0;
2158 }
2159
0980a60f 2160 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2161 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2162 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2163 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2164 uniqtranscale_reg_value);
ab3c759a
CML		 2165 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2166 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2167 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2168 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2169 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2170
2171 return 0;
2172}
2173
a4fc5ed6 2174static void
0301b3ac
JN		 2175intel_get_adjust_train(struct intel_dp *intel_dp,
2176 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2177{
2178 uint8_t v = 0;
2179 uint8_t p = 0;
2180 int lane;
1a2eb460
KP		 2181 uint8_t voltage_max;
2182 uint8_t preemph_max;
a4fc5ed6 2183
33a34e4e 2184 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2185 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2186 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2187
2188 if (this_v > v)
2189 v = this_v;
2190 if (this_p > p)
2191 p = this_p;
2192 }
2193
1a2eb460 2194 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2195 if (v >= voltage_max)
2196 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2197
1a2eb460
KP		 2198 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2199 if (p >= preemph_max)
2200 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2201
2202 for (lane = 0; lane < 4; lane++)
33a34e4e 2203 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2204}
2205
2206static uint32_t
f0a3424e 2207intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2208{
3cf2efb1 2209 uint32_t signal_levels = 0;
a4fc5ed6 2210
3cf2efb1 2211 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2212 case DP_TRAIN_VOLTAGE_SWING_400:
2213 default:
2214 signal_levels |= DP_VOLTAGE_0_4;
2215 break;
2216 case DP_TRAIN_VOLTAGE_SWING_600:
2217 signal_levels |= DP_VOLTAGE_0_6;
2218 break;
2219 case DP_TRAIN_VOLTAGE_SWING_800:
2220 signal_levels |= DP_VOLTAGE_0_8;
2221 break;
2222 case DP_TRAIN_VOLTAGE_SWING_1200:
2223 signal_levels |= DP_VOLTAGE_1_2;
2224 break;
2225 }
3cf2efb1 2226 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2227 case DP_TRAIN_PRE_EMPHASIS_0:
2228 default:
2229 signal_levels |= DP_PRE_EMPHASIS_0;
2230 break;
2231 case DP_TRAIN_PRE_EMPHASIS_3_5:
2232 signal_levels |= DP_PRE_EMPHASIS_3_5;
2233 break;
2234 case DP_TRAIN_PRE_EMPHASIS_6:
2235 signal_levels |= DP_PRE_EMPHASIS_6;
2236 break;
2237 case DP_TRAIN_PRE_EMPHASIS_9_5:
2238 signal_levels |= DP_PRE_EMPHASIS_9_5;
2239 break;
2240 }
2241 return signal_levels;
2242}
2243
e3421a18
ZW		 2244/* Gen6's DP voltage swing and pre-emphasis control */
2245static uint32_t
2246intel_gen6_edp_signal_levels(uint8_t train_set)
2247{
3c5a62b5
YL		 2248 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2249 DP_TRAIN_PRE_EMPHASIS_MASK);
2250 switch (signal_levels) {
e3421a18 2251 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2252 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2253 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2254 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2255 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2256 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2257 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2258 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2259 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2260 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2261 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2262 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2263 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2264 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2265 default:
3c5a62b5
YL		 2266 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2267 "0x%x\n", signal_levels);
2268 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2269 }
2270}
2271
1a2eb460
KP		 2272/* Gen7's DP voltage swing and pre-emphasis control */
2273static uint32_t
2274intel_gen7_edp_signal_levels(uint8_t train_set)
2275{
2276 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2277 DP_TRAIN_PRE_EMPHASIS_MASK);
2278 switch (signal_levels) {
2279 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2280 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2281 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2282 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2283 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2284 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2285
2286 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2287 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2288 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2289 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2290
2291 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2292 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2293 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2294 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2295
2296 default:
2297 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2298 "0x%x\n", signal_levels);
2299 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2300 }
2301}
2302
d6c0d722
PZ		 2303/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2304static uint32_t
f0a3424e 2305intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2306{
d6c0d722
PZ		 2307 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2308 DP_TRAIN_PRE_EMPHASIS_MASK);
2309 switch (signal_levels) {
2310 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2311 return DDI_BUF_EMP_400MV_0DB_HSW;
2312 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2313 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2314 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2315 return DDI_BUF_EMP_400MV_6DB_HSW;
2316 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2317 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2318
d6c0d722
PZ		 2319 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2320 return DDI_BUF_EMP_600MV_0DB_HSW;
2321 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2322 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2323 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2324 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2325
d6c0d722
PZ		 2326 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2327 return DDI_BUF_EMP_800MV_0DB_HSW;
2328 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2329 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2330 default:
2331 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2332 "0x%x\n", signal_levels);
2333 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2334 }
a4fc5ed6
KP		 2335}
2336
8f93f4f1
PZ		 2337static uint32_t
2338intel_bdw_signal_levels(uint8_t train_set)
2339{
2340 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2341 DP_TRAIN_PRE_EMPHASIS_MASK);
2342 switch (signal_levels) {
2343 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2344 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2345 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2346 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2347 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2348 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2349
2350 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2351 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2352 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2353 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2354 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2355 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2356
2357 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2358 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2359 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2360 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2361
2362 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2363 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2364
2365 default:
2366 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2367 "0x%x\n", signal_levels);
2368 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2369 }
2370}
2371
f0a3424e
PZ		 2372/* Properly updates "DP" with the correct signal levels. */
2373static void
2374intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2375{
2376 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2377 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2378 struct drm_device *dev = intel_dig_port->base.base.dev;
2379 uint32_t signal_levels, mask;
2380 uint8_t train_set = intel_dp->train_set[0];
2381
8f93f4f1
PZ		 2382 if (IS_BROADWELL(dev)) {
2383 signal_levels = intel_bdw_signal_levels(train_set);
2384 mask = DDI_BUF_EMP_MASK;
2385 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2386 signal_levels = intel_hsw_signal_levels(train_set);
2387 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2388 } else if (IS_VALLEYVIEW(dev)) {
2389 signal_levels = intel_vlv_signal_levels(intel_dp);
2390 mask = 0;
bc7d38a4 2391 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2392 signal_levels = intel_gen7_edp_signal_levels(train_set);
2393 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2394 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2395 signal_levels = intel_gen6_edp_signal_levels(train_set);
2396 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2397 } else {
2398 signal_levels = intel_gen4_signal_levels(train_set);
2399 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2400 }
2401
2402 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2403
2404 *DP = (*DP & ~mask) | signal_levels;
2405}
2406
a4fc5ed6 2407static bool
ea5b213a 2408intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2409 uint32_t *DP,
58e10eb9 2410 uint8_t dp_train_pat)
a4fc5ed6 2411{
174edf1f
PZ		 2412 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2413 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2414 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2415 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2416 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2417 int ret, len;
a4fc5ed6 2418
22b8bf17 2419 if (HAS_DDI(dev)) {
3ab9c637 2420 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2421
2422 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2423 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2424 else
2425 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2426
2427 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2428 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2429 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2430 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2431
2432 break;
2433 case DP_TRAINING_PATTERN_1:
2434 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2435 break;
2436 case DP_TRAINING_PATTERN_2:
2437 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2438 break;
2439 case DP_TRAINING_PATTERN_3:
2440 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2441 break;
2442 }
174edf1f 2443 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2444
bc7d38a4 2445 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2446 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2447
2448 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2449 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2450 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2451 break;
2452 case DP_TRAINING_PATTERN_1:
70aff66c 2453 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2454 break;
2455 case DP_TRAINING_PATTERN_2:
70aff66c 2456 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2457 break;
2458 case DP_TRAINING_PATTERN_3:
2459 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2460 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2461 break;
2462 }
2463
2464 } else {
70aff66c 2465 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2466
2467 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2468 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2469 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2470 break;
2471 case DP_TRAINING_PATTERN_1:
70aff66c 2472 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2473 break;
2474 case DP_TRAINING_PATTERN_2:
70aff66c 2475 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2476 break;
2477 case DP_TRAINING_PATTERN_3:
2478 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2479 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2480 break;
2481 }
2482 }
2483
70aff66c 2484 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2485 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2486
2cdfe6c8
JN		 2487 buf[0] = dp_train_pat;
2488 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2489 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2490 /* don't write DP_TRAINING_LANEx_SET on disable */
2491 len = 1;
2492 } else {
2493 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2494 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2495 len = intel_dp->lane_count + 1;
47ea7542 2496 }
a4fc5ed6 2497
9d1a1031
JN		 2498 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2499 buf, len);
2cdfe6c8
JN		 2500
2501 return ret == len;
a4fc5ed6
KP		 2502}
2503
70aff66c
JN		 2504static bool
2505intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2506 uint8_t dp_train_pat)
2507{
953d22e8 2508 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2509 intel_dp_set_signal_levels(intel_dp, DP);
2510 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2511}
2512
2513static bool
2514intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2515 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2516{
2517 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2518 struct drm_device *dev = intel_dig_port->base.base.dev;
2519 struct drm_i915_private *dev_priv = dev->dev_private;
2520 int ret;
2521
2522 intel_get_adjust_train(intel_dp, link_status);
2523 intel_dp_set_signal_levels(intel_dp, DP);
2524
2525 I915_WRITE(intel_dp->output_reg, *DP);
2526 POSTING_READ(intel_dp->output_reg);
2527
9d1a1031
JN		 2528 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2529 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 2530
2531 return ret == intel_dp->lane_count;
2532}
2533
3ab9c637
ID		 2534static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2535{
2536 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2537 struct drm_device *dev = intel_dig_port->base.base.dev;
2538 struct drm_i915_private *dev_priv = dev->dev_private;
2539 enum port port = intel_dig_port->port;
2540 uint32_t val;
2541
2542 if (!HAS_DDI(dev))
2543 return;
2544
2545 val = I915_READ(DP_TP_CTL(port));
2546 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2547 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2548 I915_WRITE(DP_TP_CTL(port), val);
2549
2550 /*
2551 * On PORT_A we can have only eDP in SST mode. There the only reason
2552 * we need to set idle transmission mode is to work around a HW issue
2553 * where we enable the pipe while not in idle link-training mode.
2554 * In this case there is requirement to wait for a minimum number of
2555 * idle patterns to be sent.
2556 */
2557 if (port == PORT_A)
2558 return;
2559
2560 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2561 1))
2562 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2563}
2564
33a34e4e 2565/* Enable corresponding port and start training pattern 1 */
c19b0669 2566void
33a34e4e 2567intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2568{
da63a9f2 2569 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2570 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2571 int i;
2572 uint8_t voltage;
cdb0e95b 2573 int voltage_tries, loop_tries;
ea5b213a 2574 uint32_t DP = intel_dp->DP;
6aba5b6c 2575 uint8_t link_config[2];
a4fc5ed6 2576
affa9354 2577 if (HAS_DDI(dev))
c19b0669
PZ		 2578 intel_ddi_prepare_link_retrain(encoder);
2579
3cf2efb1 2580 /* Write the link configuration data */
6aba5b6c
JN		 2581 link_config[0] = intel_dp->link_bw;
2582 link_config[1] = intel_dp->lane_count;
2583 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2584 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 2585 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 2586
2587 link_config[0] = 0;
2588 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 2589 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2590
2591 DP |= DP_PORT_EN;
1a2eb460 2592
70aff66c
JN		 2593 /* clock recovery */
2594 if (!intel_dp_reset_link_train(intel_dp, &DP,
2595 DP_TRAINING_PATTERN_1 |
2596 DP_LINK_SCRAMBLING_DISABLE)) {
2597 DRM_ERROR("failed to enable link training\n");
2598 return;
2599 }
2600
a4fc5ed6 2601 voltage = 0xff;
cdb0e95b
KP		 2602 voltage_tries = 0;
2603 loop_tries = 0;
a4fc5ed6 2604 for (;;) {
70aff66c 2605 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2606
a7c9655f 2607 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2608 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2609 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2610 break;
93f62dad 2611 }
a4fc5ed6 2612
01916270 2613 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2614 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2615 break;
2616 }
2617
2618 /* Check to see if we've tried the max voltage */
2619 for (i = 0; i < intel_dp->lane_count; i++)
2620 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2621 break;
3b4f819d 2622 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2623 ++loop_tries;
2624 if (loop_tries == 5) {
3def84b3 2625 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2626 break;
2627 }
70aff66c
JN		 2628 intel_dp_reset_link_train(intel_dp, &DP,
2629 DP_TRAINING_PATTERN_1 |
2630 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2631 voltage_tries = 0;
2632 continue;
2633 }
a4fc5ed6 2634
3cf2efb1 2635 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2636 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2637 ++voltage_tries;
b06fbda3 2638 if (voltage_tries == 5) {
3def84b3 2639 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2640 break;
2641 }
2642 } else
2643 voltage_tries = 0;
2644 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2645
70aff66c
JN		 2646 /* Update training set as requested by target */
2647 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2648 DRM_ERROR("failed to update link training\n");
2649 break;
2650 }
a4fc5ed6
KP		 2651 }
2652
33a34e4e
JB		 2653 intel_dp->DP = DP;
2654}
2655
c19b0669 2656void
33a34e4e
JB		 2657intel_dp_complete_link_train(struct intel_dp *intel_dp)
2658{
33a34e4e 2659 bool channel_eq = false;
37f80975 2660 int tries, cr_tries;
33a34e4e 2661 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 2662 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2663
2664 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2665 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2666 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 2667
a4fc5ed6 2668 /* channel equalization */
70aff66c 2669 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2670 training_pattern |
70aff66c
JN		 2671 DP_LINK_SCRAMBLING_DISABLE)) {
2672 DRM_ERROR("failed to start channel equalization\n");
2673 return;
2674 }
2675
a4fc5ed6 2676 tries = 0;
37f80975 2677 cr_tries = 0;
a4fc5ed6
KP		 2678 channel_eq = false;
2679 for (;;) {
70aff66c 2680 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2681
37f80975
JB		 2682 if (cr_tries > 5) {
2683 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2684 break;
2685 }
2686
a7c9655f 2687 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2688 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2689 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2690 break;
70aff66c 2691 }
a4fc5ed6 2692
37f80975 2693 /* Make sure clock is still ok */
01916270 2694 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2695 intel_dp_start_link_train(intel_dp);
70aff66c 2696 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2697 training_pattern |
70aff66c 2698 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2699 cr_tries++;
2700 continue;
2701 }
2702
1ffdff13 2703 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2704 channel_eq = true;
2705 break;
2706 }
a4fc5ed6 2707
37f80975
JB		 2708 /* Try 5 times, then try clock recovery if that fails */
2709 if (tries > 5) {
2710 intel_dp_link_down(intel_dp);
2711 intel_dp_start_link_train(intel_dp);
70aff66c 2712 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2713 training_pattern |
70aff66c 2714 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2715 tries = 0;
2716 cr_tries++;
2717 continue;
2718 }
a4fc5ed6 2719
70aff66c
JN		 2720 /* Update training set as requested by target */
2721 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2722 DRM_ERROR("failed to update link training\n");
2723 break;
2724 }
3cf2efb1 2725 ++tries;
869184a6 2726 }
3cf2efb1 2727
3ab9c637
ID		 2728 intel_dp_set_idle_link_train(intel_dp);
2729
2730 intel_dp->DP = DP;
2731
d6c0d722 2732 if (channel_eq)
07f42258 2733 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2734
3ab9c637
ID		 2735}
2736
2737void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2738{
70aff66c 2739 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2740 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2741}
2742
2743static void
ea5b213a 2744intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2745{
da63a9f2 2746 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2747 enum port port = intel_dig_port->port;
da63a9f2 2748 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2749 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2750 struct intel_crtc *intel_crtc =
2751 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2752 uint32_t DP = intel_dp->DP;
a4fc5ed6 2753
c19b0669
PZ		 2754 /*
2755 * DDI code has a strict mode set sequence and we should try to respect
2756 * it, otherwise we might hang the machine in many different ways. So we
2757 * really should be disabling the port only on a complete crtc_disable
2758 * sequence. This function is just called under two conditions on DDI
2759 * code:
2760 * - Link train failed while doing crtc_enable, and on this case we
2761 * really should respect the mode set sequence and wait for a
2762 * crtc_disable.
2763 * - Someone turned the monitor off and intel_dp_check_link_status
2764 * called us. We don't need to disable the whole port on this case, so
2765 * when someone turns the monitor on again,
2766 * intel_ddi_prepare_link_retrain will take care of redoing the link
2767 * train.
2768 */
affa9354 2769 if (HAS_DDI(dev))
c19b0669
PZ		 2770 return;
2771
0c33d8d7 2772 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2773 return;
2774
28c97730 2775 DRM_DEBUG_KMS("\n");
32f9d658 2776
bc7d38a4 2777 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2778 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2779 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2780 } else {
2781 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2782 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2783 }
fe255d00 2784 POSTING_READ(intel_dp->output_reg);
5eb08b69 2785
493a7081 2786 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2787 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2788 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2789
5bddd17f
EA		 2790 /* Hardware workaround: leaving our transcoder select
2791 * set to transcoder B while it's off will prevent the
2792 * corresponding HDMI output on transcoder A.
2793 *
2794 * Combine this with another hardware workaround:
2795 * transcoder select bit can only be cleared while the
2796 * port is enabled.
2797 */
2798 DP &= ~DP_PIPEB_SELECT;
2799 I915_WRITE(intel_dp->output_reg, DP);
2800
2801 /* Changes to enable or select take place the vblank
2802 * after being written.
2803 */
ff50afe9
DV		 2804 if (WARN_ON(crtc == NULL)) {
2805 /* We should never try to disable a port without a crtc
2806 * attached. For paranoia keep the code around for a
2807 * bit. */
31acbcc4
CW		 2808 POSTING_READ(intel_dp->output_reg);
2809 msleep(50);
2810 } else
ab527efc 2811 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2812 }
2813
832afda6 2814 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2815 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2816 POSTING_READ(intel_dp->output_reg);
f01eca2e 2817 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2818}
2819
26d61aad
KP		 2820static bool
2821intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2822{
a031d709
RV		 2823 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2824 struct drm_device *dev = dig_port->base.base.dev;
2825 struct drm_i915_private *dev_priv = dev->dev_private;
2826
577c7a50
DL		 2827 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2828
9d1a1031
JN		 2829 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
2830 sizeof(intel_dp->dpcd)) < 0)
edb39244 2831 return false; /* aux transfer failed */
92fd8fd1 2832
577c7a50
DL		 2833 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2834 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2835 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2836
edb39244
AJ		 2837 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2838 return false; /* DPCD not present */
2839
2293bb5c
SK		 2840 /* Check if the panel supports PSR */
2841 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 2842 if (is_edp(intel_dp)) {
9d1a1031
JN		 2843 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
2844 intel_dp->psr_dpcd,
2845 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2846 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2847 dev_priv->psr.sink_support = true;
50003939 2848 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2849 }
50003939
JN		 2850 }
2851
06ea66b6
TP		 2852 /* Training Pattern 3 support */
2853 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2854 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2855 intel_dp->use_tps3 = true;
2856 DRM_DEBUG_KMS("Displayport TPS3 supported");
2857 } else
2858 intel_dp->use_tps3 = false;
2859
edb39244
AJ		 2860 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2861 DP_DWN_STRM_PORT_PRESENT))
2862 return true; /* native DP sink */
2863
2864 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2865 return true; /* no per-port downstream info */
2866
9d1a1031
JN		 2867 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
2868 intel_dp->downstream_ports,
2869 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 2870 return false; /* downstream port status fetch failed */
2871
2872 return true;
92fd8fd1
KP		 2873}
2874
0d198328
AJ		 2875static void
2876intel_dp_probe_oui(struct intel_dp *intel_dp)
2877{
2878 u8 buf[3];
2879
2880 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2881 return;
2882
24f3e092 2883 intel_edp_panel_vdd_on(intel_dp);
351cfc34 2884
9d1a1031 2885 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 2886 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2887 buf[0], buf[1], buf[2]);
2888
9d1a1031 2889 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 2890 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2891 buf[0], buf[1], buf[2]);
351cfc34 2892
4be73780 2893 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2894}
2895
d2e216d0
RV		 2896int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2897{
2898 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2899 struct drm_device *dev = intel_dig_port->base.base.dev;
2900 struct intel_crtc *intel_crtc =
2901 to_intel_crtc(intel_dig_port->base.base.crtc);
2902 u8 buf[1];
2903
9d1a1031 2904 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 2905 return -EAGAIN;
2906
2907 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2908 return -ENOTTY;
2909
9d1a1031
JN		 2910 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
2911 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 2912 return -EAGAIN;
2913
2914 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2915 intel_wait_for_vblank(dev, intel_crtc->pipe);
2916 intel_wait_for_vblank(dev, intel_crtc->pipe);
2917
9d1a1031 2918 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 2919 return -EAGAIN;
2920
9d1a1031 2921 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 2922 return 0;
2923}
2924
a60f0e38
JB		 2925static bool
2926intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2927{
9d1a1031
JN		 2928 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2929 DP_DEVICE_SERVICE_IRQ_VECTOR,
2930 sink_irq_vector, 1) == 1;
a60f0e38
JB		 2931}
2932
2933static void
2934intel_dp_handle_test_request(struct intel_dp *intel_dp)
2935{
2936 /* NAK by default */
9d1a1031 2937 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2938}
2939
a4fc5ed6
KP		 2940/*
2941 * According to DP spec
2942 * 5.1.2:
2943 * 1. Read DPCD
2944 * 2. Configure link according to Receiver Capabilities
2945 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2946 * 4. Check link status on receipt of hot-plug interrupt
2947 */
2948
00c09d70 2949void
ea5b213a 2950intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2951{
da63a9f2 2952 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2953 u8 sink_irq_vector;
93f62dad 2954 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2955
da63a9f2 2956 if (!intel_encoder->connectors_active)
d2b996ac 2957 return;
59cd09e1 2958
da63a9f2 2959 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2960 return;
2961
92fd8fd1 2962 /* Try to read receiver status if the link appears to be up */
93f62dad 2963 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 2964 return;
2965 }
2966
92fd8fd1 2967 /* Now read the DPCD to see if it's actually running */
26d61aad 2968 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2969 return;
2970 }
2971
a60f0e38
JB		 2972 /* Try to read the source of the interrupt */
2973 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2974 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2975 /* Clear interrupt source */
9d1a1031
JN		 2976 drm_dp_dpcd_writeb(&intel_dp->aux,
2977 DP_DEVICE_SERVICE_IRQ_VECTOR,
2978 sink_irq_vector);
a60f0e38
JB		 2979
2980 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2981 intel_dp_handle_test_request(intel_dp);
2982 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2983 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2984 }
2985
1ffdff13 2986 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2987 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2988 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2989 intel_dp_start_link_train(intel_dp);
2990 intel_dp_complete_link_train(intel_dp);
3ab9c637 2991 intel_dp_stop_link_train(intel_dp);
33a34e4e 2992 }
a4fc5ed6 2993}
a4fc5ed6 2994
caf9ab24 2995/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2996static enum drm_connector_status
26d61aad 2997intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2998{
caf9ab24 2999 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3000 uint8_t type;
3001
3002 if (!intel_dp_get_dpcd(intel_dp))
3003 return connector_status_disconnected;
3004
3005 /* if there's no downstream port, we're done */
3006 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3007 return connector_status_connected;
caf9ab24
AJ		 3008
3009 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3010 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3011 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3012 uint8_t reg;
9d1a1031
JN		 3013
3014 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3015 &reg, 1) < 0)
caf9ab24 3016 return connector_status_unknown;
9d1a1031 3017
23235177
AJ		 3018 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3019 : connector_status_disconnected;
caf9ab24
AJ		 3020 }
3021
3022 /* If no HPD, poke DDC gently */
0b99836f 3023 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3024 return connector_status_connected;
caf9ab24
AJ		 3025
3026 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3027 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3028 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3029 if (type == DP_DS_PORT_TYPE_VGA ||
3030 type == DP_DS_PORT_TYPE_NON_EDID)
3031 return connector_status_unknown;
3032 } else {
3033 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3034 DP_DWN_STRM_PORT_TYPE_MASK;
3035 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3036 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3037 return connector_status_unknown;
3038 }
caf9ab24
AJ		 3039
3040 /* Anything else is out of spec, warn and ignore */
3041 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3042 return connector_status_disconnected;
71ba9000
AJ		 3043}
3044
5eb08b69 3045static enum drm_connector_status
a9756bb5 3046ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3047{
30add22d 3048 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3049 struct drm_i915_private *dev_priv = dev->dev_private;
3050 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3051 enum drm_connector_status status;
3052
fe16d949
CW		 3053 /* Can't disconnect eDP, but you can close the lid... */
3054 if (is_edp(intel_dp)) {
30add22d 3055 status = intel_panel_detect(dev);
fe16d949
CW		 3056 if (status == connector_status_unknown)
3057 status = connector_status_connected;
3058 return status;
3059 }
01cb9ea6 3060
1b469639
DL		 3061 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3062 return connector_status_disconnected;
3063
26d61aad 3064 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3065}
3066
a4fc5ed6 3067static enum drm_connector_status
a9756bb5 3068g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3069{
30add22d 3070 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3071 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3072 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3073 uint32_t bit;
5eb08b69 3074
35aad75f
JB		 3075 /* Can't disconnect eDP, but you can close the lid... */
3076 if (is_edp(intel_dp)) {
3077 enum drm_connector_status status;
3078
3079 status = intel_panel_detect(dev);
3080 if (status == connector_status_unknown)
3081 status = connector_status_connected;
3082 return status;
3083 }
3084
232a6ee9
TP		 3085 if (IS_VALLEYVIEW(dev)) {
3086 switch (intel_dig_port->port) {
3087 case PORT_B:
3088 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3089 break;
3090 case PORT_C:
3091 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3092 break;
3093 case PORT_D:
3094 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3095 break;
3096 default:
3097 return connector_status_unknown;
3098 }
3099 } else {
3100 switch (intel_dig_port->port) {
3101 case PORT_B:
3102 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3103 break;
3104 case PORT_C:
3105 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3106 break;
3107 case PORT_D:
3108 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3109 break;
3110 default:
3111 return connector_status_unknown;
3112 }
a4fc5ed6
KP		 3113 }
3114
10f76a38 3115 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3116 return connector_status_disconnected;
3117
26d61aad 3118 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3119}
3120
8c241fef
KP		 3121static struct edid *
3122intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3123{
9cd300e0 3124 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3125
9cd300e0
JN		 3126 /* use cached edid if we have one */
3127 if (intel_connector->edid) {
9cd300e0
JN		 3128 /* invalid edid */
3129 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3130 return NULL;
3131
55e9edeb 3132 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3133 }
8c241fef 3134
9cd300e0 3135 return drm_get_edid(connector, adapter);
8c241fef
KP		 3136}
3137
3138static int
3139intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3140{
9cd300e0 3141 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3142
9cd300e0
JN		 3143 /* use cached edid if we have one */
3144 if (intel_connector->edid) {
3145 /* invalid edid */
3146 if (IS_ERR(intel_connector->edid))
3147 return 0;
3148
3149 return intel_connector_update_modes(connector,
3150 intel_connector->edid);
d6f24d0f
JB		 3151 }
3152
9cd300e0 3153 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3154}
3155
a9756bb5
ZW		 3156static enum drm_connector_status
3157intel_dp_detect(struct drm_connector *connector, bool force)
3158{
3159 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3160 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3161 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3162 struct drm_device *dev = connector->dev;
c8c8fb33 3163 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3164 enum drm_connector_status status;
671dedd2 3165 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3166 struct edid *edid = NULL;
3167
c8c8fb33
PZ		 3168 intel_runtime_pm_get(dev_priv);
3169
671dedd2
ID		 3170 power_domain = intel_display_port_power_domain(intel_encoder);
3171 intel_display_power_get(dev_priv, power_domain);
3172
164c8598
CW		 3173 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3174 connector->base.id, drm_get_connector_name(connector));
3175
a9756bb5
ZW		 3176 intel_dp->has_audio = false;
3177
3178 if (HAS_PCH_SPLIT(dev))
3179 status = ironlake_dp_detect(intel_dp);
3180 else
3181 status = g4x_dp_detect(intel_dp);
1b9be9d0 3182
a9756bb5 3183 if (status != connector_status_connected)
c8c8fb33 3184 goto out;
a9756bb5 3185
0d198328
AJ		 3186 intel_dp_probe_oui(intel_dp);
3187
c3e5f67b
DV		 3188 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3189 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3190 } else {
0b99836f 3191 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3192 if (edid) {
3193 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3194 kfree(edid);
3195 }
a9756bb5
ZW		 3196 }
3197
d63885da
PZ		 3198 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3199 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3200 status = connector_status_connected;
3201
3202out:
671dedd2
ID		 3203 intel_display_power_put(dev_priv, power_domain);
3204
c8c8fb33 3205 intel_runtime_pm_put(dev_priv);
671dedd2 3206
c8c8fb33 3207 return status;
a4fc5ed6
KP		 3208}
3209
3210static int intel_dp_get_modes(struct drm_connector *connector)
3211{
df0e9248 3212 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3213 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3214 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3215 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3216 struct drm_device *dev = connector->dev;
671dedd2
ID		 3217 struct drm_i915_private *dev_priv = dev->dev_private;
3218 enum intel_display_power_domain power_domain;
32f9d658 3219 int ret;
a4fc5ed6
KP		 3220
3221 /* We should parse the EDID data and find out if it has an audio sink
3222 */
3223
671dedd2
ID		 3224 power_domain = intel_display_port_power_domain(intel_encoder);
3225 intel_display_power_get(dev_priv, power_domain);
3226
0b99836f 3227 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3228 intel_display_power_put(dev_priv, power_domain);
f8779fda 3229 if (ret)
32f9d658
ZW		 3230 return ret;
3231
f8779fda 3232 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3233 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3234 struct drm_display_mode *mode;
dd06f90e
JN		 3235 mode = drm_mode_duplicate(dev,
3236 intel_connector->panel.fixed_mode);
f8779fda 3237 if (mode) {
32f9d658
ZW		 3238 drm_mode_probed_add(connector, mode);
3239 return 1;
3240 }
3241 }
3242 return 0;
a4fc5ed6
KP		 3243}
3244
1aad7ac0
CW		 3245static bool
3246intel_dp_detect_audio(struct drm_connector *connector)
3247{
3248 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3249 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3250 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3251 struct drm_device *dev = connector->dev;
3252 struct drm_i915_private *dev_priv = dev->dev_private;
3253 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3254 struct edid *edid;
3255 bool has_audio = false;
3256
671dedd2
ID		 3257 power_domain = intel_display_port_power_domain(intel_encoder);
3258 intel_display_power_get(dev_priv, power_domain);
3259
0b99836f 3260 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3261 if (edid) {
3262 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3263 kfree(edid);
3264 }
3265
671dedd2
ID		 3266 intel_display_power_put(dev_priv, power_domain);
3267
1aad7ac0
CW		 3268 return has_audio;
3269}
3270
f684960e
CW		 3271static int
3272intel_dp_set_property(struct drm_connector *connector,
3273 struct drm_property *property,
3274 uint64_t val)
3275{
e953fd7b 3276 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3277 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3278 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3279 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3280 int ret;
3281
662595df 3282 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3283 if (ret)
3284 return ret;
3285
3f43c48d 3286 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3287 int i = val;
3288 bool has_audio;
3289
3290 if (i == intel_dp->force_audio)
f684960e
CW		 3291 return 0;
3292
1aad7ac0 3293 intel_dp->force_audio = i;
f684960e 3294
c3e5f67b 3295 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3296 has_audio = intel_dp_detect_audio(connector);
3297 else
c3e5f67b 3298 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3299
3300 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3301 return 0;
3302
1aad7ac0 3303 intel_dp->has_audio = has_audio;
f684960e
CW		 3304 goto done;
3305 }
3306
e953fd7b 3307 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3308 bool old_auto = intel_dp->color_range_auto;
3309 uint32_t old_range = intel_dp->color_range;
3310
55bc60db
VS		 3311 switch (val) {
3312 case INTEL_BROADCAST_RGB_AUTO:
3313 intel_dp->color_range_auto = true;
3314 break;
3315 case INTEL_BROADCAST_RGB_FULL:
3316 intel_dp->color_range_auto = false;
3317 intel_dp->color_range = 0;
3318 break;
3319 case INTEL_BROADCAST_RGB_LIMITED:
3320 intel_dp->color_range_auto = false;
3321 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3322 break;
3323 default:
3324 return -EINVAL;
3325 }
ae4edb80
DV		 3326
3327 if (old_auto == intel_dp->color_range_auto &&
3328 old_range == intel_dp->color_range)
3329 return 0;
3330
e953fd7b
CW		 3331 goto done;
3332 }
3333
53b41837
YN		 3334 if (is_edp(intel_dp) &&
3335 property == connector->dev->mode_config.scaling_mode_property) {
3336 if (val == DRM_MODE_SCALE_NONE) {
3337 DRM_DEBUG_KMS("no scaling not supported\n");
3338 return -EINVAL;
3339 }
3340
3341 if (intel_connector->panel.fitting_mode == val) {
3342 /* the eDP scaling property is not changed */
3343 return 0;
3344 }
3345 intel_connector->panel.fitting_mode = val;
3346
3347 goto done;
3348 }
3349
f684960e
CW		 3350 return -EINVAL;
3351
3352done:
c0c36b94
CW		 3353 if (intel_encoder->base.crtc)
3354 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3355
3356 return 0;
3357}
3358
a4fc5ed6 3359static void
73845adf 3360intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3361{
1d508706 3362 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3363
9cd300e0
JN		 3364 if (!IS_ERR_OR_NULL(intel_connector->edid))
3365 kfree(intel_connector->edid);
3366
acd8db10
PZ		 3367 /* Can't call is_edp() since the encoder may have been destroyed
3368 * already. */
3369 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3370 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3371
a4fc5ed6 3372 drm_connector_cleanup(connector);
55f78c43 3373 kfree(connector);
a4fc5ed6
KP		 3374}
3375
00c09d70 3376void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3377{
da63a9f2
PZ		 3378 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3379 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3380 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 3381
0b99836f 3382 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
24d05927 3383 drm_encoder_cleanup(encoder);
bd943159
KP		 3384 if (is_edp(intel_dp)) {
3385 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3386 mutex_lock(&dev->mode_config.mutex);
4be73780 3387 edp_panel_vdd_off_sync(intel_dp);
bd173813 3388 mutex_unlock(&dev->mode_config.mutex);
bd943159 3389 }
da63a9f2 3390 kfree(intel_dig_port);
24d05927
DV		 3391}
3392
a4fc5ed6 3393static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3394 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3395 .detect = intel_dp_detect,
3396 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3397 .set_property = intel_dp_set_property,
73845adf 3398 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3399};
3400
3401static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3402 .get_modes = intel_dp_get_modes,
3403 .mode_valid = intel_dp_mode_valid,
df0e9248 3404 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3405};
3406
a4fc5ed6 3407static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3408 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3409};
3410
995b6762 3411static void
21d40d37 3412intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3413{
fa90ecef 3414 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3415
885a5014 3416 intel_dp_check_link_status(intel_dp);
c8110e52 3417}
6207937d 3418
e3421a18
ZW		 3419/* Return which DP Port should be selected for Transcoder DP control */
3420int
0206e353 3421intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3422{
3423 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3424 struct intel_encoder *intel_encoder;
3425 struct intel_dp *intel_dp;
e3421a18 3426
fa90ecef
PZ		 3427 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3428 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3429
fa90ecef
PZ		 3430 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3431 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3432 return intel_dp->output_reg;
e3421a18 3433 }
ea5b213a 3434
e3421a18
ZW		 3435 return -1;
3436}
3437
36e83a18 3438/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3439bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3440{
3441 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3442 union child_device_config *p_child;
36e83a18 3443 int i;
5d8a7752
VS		 3444 static const short port_mapping[] = {
3445 [PORT_B] = PORT_IDPB,
3446 [PORT_C] = PORT_IDPC,
3447 [PORT_D] = PORT_IDPD,
3448 };
36e83a18 3449
3b32a35b
VS		 3450 if (port == PORT_A)
3451 return true;
3452
41aa3448 3453 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3454 return false;
3455
41aa3448
RV		 3456 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3457 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3458
5d8a7752 3459 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3460 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3461 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3462 return true;
3463 }
3464 return false;
3465}
3466
f684960e
CW		 3467static void
3468intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3469{
53b41837
YN		 3470 struct intel_connector *intel_connector = to_intel_connector(connector);
3471
3f43c48d 3472 intel_attach_force_audio_property(connector);
e953fd7b 3473 intel_attach_broadcast_rgb_property(connector);
55bc60db 3474 intel_dp->color_range_auto = true;
53b41837
YN		 3475
3476 if (is_edp(intel_dp)) {
3477 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3478 drm_object_attach_property(
3479 &connector->base,
53b41837 3480 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3481 DRM_MODE_SCALE_ASPECT);
3482 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3483 }
f684960e
CW		 3484}
3485
dada1a9f
ID		 3486static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3487{
3488 intel_dp->last_power_cycle = jiffies;
3489 intel_dp->last_power_on = jiffies;
3490 intel_dp->last_backlight_off = jiffies;
3491}
3492
67a54566
DV		 3493static void
3494intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3495 struct intel_dp *intel_dp,
3496 struct edp_power_seq *out)
67a54566
DV		 3497{
3498 struct drm_i915_private *dev_priv = dev->dev_private;
3499 struct edp_power_seq cur, vbt, spec, final;
3500 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3501 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3502
3503 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3504 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3505 pp_on_reg = PCH_PP_ON_DELAYS;
3506 pp_off_reg = PCH_PP_OFF_DELAYS;
3507 pp_div_reg = PCH_PP_DIVISOR;
3508 } else {
bf13e81b
JN		 3509 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3510
3511 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3512 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3513 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3514 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3515 }
67a54566
DV		 3516
3517 /* Workaround: Need to write PP_CONTROL with the unlock key as
3518 * the very first thing. */
453c5420 3519 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3520 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3521
453c5420
JB		 3522 pp_on = I915_READ(pp_on_reg);
3523 pp_off = I915_READ(pp_off_reg);
3524 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3525
3526 /* Pull timing values out of registers */
3527 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3528 PANEL_POWER_UP_DELAY_SHIFT;
3529
3530 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3531 PANEL_LIGHT_ON_DELAY_SHIFT;
3532
3533 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3534 PANEL_LIGHT_OFF_DELAY_SHIFT;
3535
3536 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3537 PANEL_POWER_DOWN_DELAY_SHIFT;
3538
3539 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3540 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3541
3542 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3543 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3544
41aa3448 3545 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3546
3547 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3548 * our hw here, which are all in 100usec. */
3549 spec.t1_t3 = 210 * 10;
3550 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3551 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3552 spec.t10 = 500 * 10;
3553 /* This one is special and actually in units of 100ms, but zero
3554 * based in the hw (so we need to add 100 ms). But the sw vbt
3555 * table multiplies it with 1000 to make it in units of 100usec,
3556 * too. */
3557 spec.t11_t12 = (510 + 100) * 10;
3558
3559 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3560 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3561
3562 /* Use the max of the register settings and vbt. If both are
3563 * unset, fall back to the spec limits. */
3564#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3565 spec.field : \
3566 max(cur.field, vbt.field))
3567 assign_final(t1_t3);
3568 assign_final(t8);
3569 assign_final(t9);
3570 assign_final(t10);
3571 assign_final(t11_t12);
3572#undef assign_final
3573
3574#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3575 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3576 intel_dp->backlight_on_delay = get_delay(t8);
3577 intel_dp->backlight_off_delay = get_delay(t9);
3578 intel_dp->panel_power_down_delay = get_delay(t10);
3579 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3580#undef get_delay
3581
f30d26e4
JN		 3582 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3583 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3584 intel_dp->panel_power_cycle_delay);
3585
3586 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3587 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3588
3589 if (out)
3590 *out = final;
3591}
3592
3593static void
3594intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3595 struct intel_dp *intel_dp,
3596 struct edp_power_seq *seq)
3597{
3598 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3599 u32 pp_on, pp_off, pp_div, port_sel = 0;
3600 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3601 int pp_on_reg, pp_off_reg, pp_div_reg;
3602
3603 if (HAS_PCH_SPLIT(dev)) {
3604 pp_on_reg = PCH_PP_ON_DELAYS;
3605 pp_off_reg = PCH_PP_OFF_DELAYS;
3606 pp_div_reg = PCH_PP_DIVISOR;
3607 } else {
bf13e81b
JN		 3608 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3609
3610 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3611 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3612 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3613 }
3614
b2f19d1a
PZ		 3615 /*
3616 * And finally store the new values in the power sequencer. The
3617 * backlight delays are set to 1 because we do manual waits on them. For
3618 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3619 * we'll end up waiting for the backlight off delay twice: once when we
3620 * do the manual sleep, and once when we disable the panel and wait for
3621 * the PP_STATUS bit to become zero.
3622 */
f30d26e4 3623 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 3624 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3625 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 3626 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3627 /* Compute the divisor for the pp clock, simply match the Bspec
3628 * formula. */
453c5420 3629 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3630 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3631 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3632
3633 /* Haswell doesn't have any port selection bits for the panel
3634 * power sequencer any more. */
bc7d38a4 3635 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3636 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3637 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3638 else
3639 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3640 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3641 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3642 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3643 else
a24c144c 3644 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3645 }
3646
453c5420
JB		 3647 pp_on |= port_sel;
3648
3649 I915_WRITE(pp_on_reg, pp_on);
3650 I915_WRITE(pp_off_reg, pp_off);
3651 I915_WRITE(pp_div_reg, pp_div);
67a54566 3652
67a54566 3653 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3654 I915_READ(pp_on_reg),
3655 I915_READ(pp_off_reg),
3656 I915_READ(pp_div_reg));
f684960e
CW		 3657}
3658
439d7ac0
PB		 3659void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
3660{
3661 struct drm_i915_private *dev_priv = dev->dev_private;
3662 struct intel_encoder *encoder;
3663 struct intel_dp *intel_dp = NULL;
3664 struct intel_crtc_config *config = NULL;
3665 struct intel_crtc *intel_crtc = NULL;
3666 struct intel_connector *intel_connector = dev_priv->drrs.connector;
3667 u32 reg, val;
3668 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
3669
3670 if (refresh_rate <= 0) {
3671 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
3672 return;
3673 }
3674
3675 if (intel_connector == NULL) {
3676 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
3677 return;
3678 }
3679
3680 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
3681 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
3682 return;
3683 }
3684
3685 encoder = intel_attached_encoder(&intel_connector->base);
3686 intel_dp = enc_to_intel_dp(&encoder->base);
3687 intel_crtc = encoder->new_crtc;
3688
3689 if (!intel_crtc) {
3690 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
3691 return;
3692 }
3693
3694 config = &intel_crtc->config;
3695
3696 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
3697 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
3698 return;
3699 }
3700
3701 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
3702 index = DRRS_LOW_RR;
3703
3704 if (index == intel_dp->drrs_state.refresh_rate_type) {
3705 DRM_DEBUG_KMS(
3706 "DRRS requested for previously set RR...ignoring\n");
3707 return;
3708 }
3709
3710 if (!intel_crtc->active) {
3711 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
3712 return;
3713 }
3714
3715 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
3716 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
3717 val = I915_READ(reg);
3718 if (index > DRRS_HIGH_RR) {
3719 val |= PIPECONF_EDP_RR_MODE_SWITCH;
3720 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
3721 } else {
3722 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
3723 }
3724 I915_WRITE(reg, val);
3725 }
3726
3727 /*
3728 * mutex taken to ensure that there is no race between differnt
3729 * drrs calls trying to update refresh rate. This scenario may occur
3730 * in future when idleness detection based DRRS in kernel and
3731 * possible calls from user space to set differnt RR are made.
3732 */
3733
3734 mutex_lock(&intel_dp->drrs_state.mutex);
3735
3736 intel_dp->drrs_state.refresh_rate_type = index;
3737
3738 mutex_unlock(&intel_dp->drrs_state.mutex);
3739
3740 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
3741}
3742
4f9db5b5
PB		 3743static struct drm_display_mode *
3744intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
3745 struct intel_connector *intel_connector,
3746 struct drm_display_mode *fixed_mode)
3747{
3748 struct drm_connector *connector = &intel_connector->base;
3749 struct intel_dp *intel_dp = &intel_dig_port->dp;
3750 struct drm_device *dev = intel_dig_port->base.base.dev;
3751 struct drm_i915_private *dev_priv = dev->dev_private;
3752 struct drm_display_mode *downclock_mode = NULL;
3753
3754 if (INTEL_INFO(dev)->gen <= 6) {
3755 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
3756 return NULL;
3757 }
3758
3759 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
3760 DRM_INFO("VBT doesn't support DRRS\n");
3761 return NULL;
3762 }
3763
3764 downclock_mode = intel_find_panel_downclock
3765 (dev, fixed_mode, connector);
3766
3767 if (!downclock_mode) {
3768 DRM_INFO("DRRS not supported\n");
3769 return NULL;
3770 }
3771
439d7ac0
PB		 3772 dev_priv->drrs.connector = intel_connector;
3773
3774 mutex_init(&intel_dp->drrs_state.mutex);
3775
4f9db5b5
PB		 3776 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
3777
3778 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
3779 DRM_INFO("seamless DRRS supported for eDP panel.\n");
3780 return downclock_mode;
3781}
3782
ed92f0b2 3783static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 3784 struct intel_connector *intel_connector,
3785 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 3786{
3787 struct drm_connector *connector = &intel_connector->base;
3788 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 3789 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3790 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 3791 struct drm_i915_private *dev_priv = dev->dev_private;
3792 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 3793 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 3794 bool has_dpcd;
3795 struct drm_display_mode *scan;
3796 struct edid *edid;
3797
4f9db5b5
PB		 3798 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
3799
ed92f0b2
PZ		 3800 if (!is_edp(intel_dp))
3801 return true;
3802
63635217
PZ		 3803 /* The VDD bit needs a power domain reference, so if the bit is already
3804 * enabled when we boot, grab this reference. */
3805 if (edp_have_panel_vdd(intel_dp)) {
3806 enum intel_display_power_domain power_domain;
3807 power_domain = intel_display_port_power_domain(intel_encoder);
3808 intel_display_power_get(dev_priv, power_domain);
3809 }
3810
ed92f0b2 3811 /* Cache DPCD and EDID for edp. */
24f3e092 3812 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 3813 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 3814 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 3815
3816 if (has_dpcd) {
3817 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3818 dev_priv->no_aux_handshake =
3819 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3820 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3821 } else {
3822 /* if this fails, presume the device is a ghost */
3823 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3824 return false;
3825 }
3826
3827 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 3828 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 3829
060c8778 3830 mutex_lock(&dev->mode_config.mutex);
0b99836f 3831 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 3832 if (edid) {
3833 if (drm_add_edid_modes(connector, edid)) {
3834 drm_mode_connector_update_edid_property(connector,
3835 edid);
3836 drm_edid_to_eld(connector, edid);
3837 } else {
3838 kfree(edid);
3839 edid = ERR_PTR(-EINVAL);
3840 }
3841 } else {
3842 edid = ERR_PTR(-ENOENT);
3843 }
3844 intel_connector->edid = edid;
3845
3846 /* prefer fixed mode from EDID if available */
3847 list_for_each_entry(scan, &connector->probed_modes, head) {
3848 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3849 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 3850 downclock_mode = intel_dp_drrs_init(
3851 intel_dig_port,
3852 intel_connector, fixed_mode);
ed92f0b2
PZ		 3853 break;
3854 }
3855 }
3856
3857 /* fallback to VBT if available for eDP */
3858 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3859 fixed_mode = drm_mode_duplicate(dev,
3860 dev_priv->vbt.lfp_lvds_vbt_mode);
3861 if (fixed_mode)
3862 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3863 }
060c8778 3864 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 3865
4f9db5b5 3866 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
ed92f0b2
PZ		 3867 intel_panel_setup_backlight(connector);
3868
3869 return true;
3870}
3871
16c25533 3872bool
f0fec3f2
PZ		 3873intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3874 struct intel_connector *intel_connector)
a4fc5ed6 3875{
f0fec3f2
PZ		 3876 struct drm_connector *connector = &intel_connector->base;
3877 struct intel_dp *intel_dp = &intel_dig_port->dp;
3878 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3879 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3880 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3881 enum port port = intel_dig_port->port;
0095e6dc 3882 struct edp_power_seq power_seq = { 0 };
0b99836f 3883 int type;
a4fc5ed6 3884
ec5b01dd
DL		 3885 /* intel_dp vfuncs */
3886 if (IS_VALLEYVIEW(dev))
3887 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3888 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3889 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3890 else if (HAS_PCH_SPLIT(dev))
3891 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3892 else
3893 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3894
153b1100
DL		 3895 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3896
0767935e
DV		 3897 /* Preserve the current hw state. */
3898 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3899 intel_dp->attached_connector = intel_connector;
3d3dc149 3900
3b32a35b 3901 if (intel_dp_is_edp(dev, port))
b329530c 3902 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 3903 else
3904 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 3905
f7d24902
ID		 3906 /*
3907 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3908 * for DP the encoder type can be set by the caller to
3909 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3910 */
3911 if (type == DRM_MODE_CONNECTOR_eDP)
3912 intel_encoder->type = INTEL_OUTPUT_EDP;
3913
e7281eab
ID		 3914 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3915 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3916 port_name(port));
3917
b329530c 3918 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3919 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3920
a4fc5ed6
KP		 3921 connector->interlace_allowed = true;
3922 connector->doublescan_allowed = 0;
3923
f0fec3f2 3924 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 3925 edp_panel_vdd_work);
a4fc5ed6 3926
df0e9248 3927 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3928 drm_sysfs_connector_add(connector);
3929
affa9354 3930 if (HAS_DDI(dev))
bcbc889b
PZ		 3931 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3932 else
3933 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 3934 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 3935
0b99836f 3936 /* Set up the hotplug pin. */
ab9d7c30
PZ		 3937 switch (port) {
3938 case PORT_A:
1d843f9d 3939 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3940 break;
3941 case PORT_B:
1d843f9d 3942 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3943 break;
3944 case PORT_C:
1d843f9d 3945 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3946 break;
3947 case PORT_D:
1d843f9d 3948 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3949 break;
3950 default:
ad1c0b19 3951 BUG();
5eb08b69
ZW		 3952 }
3953
dada1a9f
ID		 3954 if (is_edp(intel_dp)) {
3955 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 3956 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 3957 }
0095e6dc 3958
9d1a1031 3959 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 3960
2b28bb1b
RV		 3961 intel_dp->psr_setup_done = false;
3962
0095e6dc 3963 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
0b99836f 3964 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
15b1d171
PZ		 3965 if (is_edp(intel_dp)) {
3966 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3967 mutex_lock(&dev->mode_config.mutex);
4be73780 3968 edp_panel_vdd_off_sync(intel_dp);
15b1d171
PZ		 3969 mutex_unlock(&dev->mode_config.mutex);
3970 }
b2f246a8
PZ		 3971 drm_sysfs_connector_remove(connector);
3972 drm_connector_cleanup(connector);
16c25533 3973 return false;
b2f246a8 3974 }
32f9d658 3975
f684960e
CW		 3976 intel_dp_add_properties(intel_dp, connector);
3977
a4fc5ed6
KP		 3978 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3979 * 0xd. Failure to do so will result in spurious interrupts being
3980 * generated on the port when a cable is not attached.
3981 */
3982 if (IS_G4X(dev) && !IS_GM45(dev)) {
3983 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3984 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3985 }
16c25533
PZ		 3986
3987 return true;
a4fc5ed6 3988}
f0fec3f2
PZ		 3989
3990void
3991intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3992{
3993 struct intel_digital_port *intel_dig_port;
3994 struct intel_encoder *intel_encoder;
3995 struct drm_encoder *encoder;
3996 struct intel_connector *intel_connector;
3997
b14c5679 3998 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3999 if (!intel_dig_port)
4000 return;
4001
b14c5679 4002 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 4003 if (!intel_connector) {
4004 kfree(intel_dig_port);
4005 return;
4006 }
4007
4008 intel_encoder = &intel_dig_port->base;
4009 encoder = &intel_encoder->base;
4010
4011 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4012 DRM_MODE_ENCODER_TMDS);
4013
5bfe2ac0 4014 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 4015 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70 4016 intel_encoder->disable = intel_disable_dp;
00c09d70 4017 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4018 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 4019 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4020 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4021 intel_encoder->pre_enable = vlv_pre_enable_dp;
4022 intel_encoder->enable = vlv_enable_dp;
49277c31 4023 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4024 } else {
ecff4f3b
JN		 4025 intel_encoder->pre_enable = g4x_pre_enable_dp;
4026 intel_encoder->enable = g4x_enable_dp;
49277c31 4027 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4028 }
f0fec3f2 4029
174edf1f 4030 intel_dig_port->port = port;
f0fec3f2
PZ		 4031 intel_dig_port->dp.output_reg = output_reg;
4032
00c09d70 4033 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2 4034 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 4035 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4036 intel_encoder->hot_plug = intel_dp_hot_plug;
4037
15b1d171
PZ		 4038 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4039 drm_encoder_cleanup(encoder);
4040 kfree(intel_dig_port);
b2f246a8 4041 kfree(intel_connector);
15b1d171 4042 }
f0fec3f2 4043}
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