]> git.proxmox.com Git - mirror_ubuntu-focal-kernel.git/blame - drivers/gpu/drm/i915/intel_dp.c
projects / mirror_ubuntu-focal-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Don't call intel_plane_restore() when the prop value didn't change
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
293static enum pipe
294vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
298 struct drm_device *dev = intel_dig_port->base.base.dev;
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 enum port port = intel_dig_port->port;
301 enum pipe pipe;
302
303 /* modeset should have pipe */
304 if (crtc)
305 return to_intel_crtc(crtc)->pipe;
306
307 /* init time, try to find a pipe with this port selected */
308 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
309 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
310 PANEL_PORT_SELECT_MASK;
ad933b56 311 if (port_sel == PANEL_PORT_SELECT_VLV(port))
bf13e81b
JN		 312 return pipe;
313 }
314
315 /* shrug */
316 return PIPE_A;
317}
318
319static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
320{
321 struct drm_device *dev = intel_dp_to_dev(intel_dp);
322
323 if (HAS_PCH_SPLIT(dev))
324 return PCH_PP_CONTROL;
325 else
326 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
327}
328
329static u32 _pp_stat_reg(struct intel_dp *intel_dp)
330{
331 struct drm_device *dev = intel_dp_to_dev(intel_dp);
332
333 if (HAS_PCH_SPLIT(dev))
334 return PCH_PP_STATUS;
335 else
336 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
337}
338
01527b31
CT		 339/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
340 This function only applicable when panel PM state is not to be tracked */
341static int edp_notify_handler(struct notifier_block *this, unsigned long code,
342 void *unused)
343{
344 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
345 edp_notifier);
346 struct drm_device *dev = intel_dp_to_dev(intel_dp);
347 struct drm_i915_private *dev_priv = dev->dev_private;
348 u32 pp_div;
349 u32 pp_ctrl_reg, pp_div_reg;
350 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
351
352 if (!is_edp(intel_dp) || code != SYS_RESTART)
353 return 0;
354
355 if (IS_VALLEYVIEW(dev)) {
356 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
357 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
358 pp_div = I915_READ(pp_div_reg);
359 pp_div &= PP_REFERENCE_DIVIDER_MASK;
360
361 /* 0x1F write to PP_DIV_REG sets max cycle delay */
362 I915_WRITE(pp_div_reg, pp_div | 0x1F);
363 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
364 msleep(intel_dp->panel_power_cycle_delay);
365 }
366
367 return 0;
368}
369
4be73780 370static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 371{
30add22d 372 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 373 struct drm_i915_private *dev_priv = dev->dev_private;
374
bf13e81b 375 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 376}
377
4be73780 378static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 379{
30add22d 380 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 381 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 382 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
383 struct intel_encoder *intel_encoder = &intel_dig_port->base;
384 enum intel_display_power_domain power_domain;
ebf33b18 385
bb4932c4
ID		 386 power_domain = intel_display_port_power_domain(intel_encoder);
387 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 388 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 389}
390
9b984dae
KP		 391static void
392intel_dp_check_edp(struct intel_dp *intel_dp)
393{
30add22d 394 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 395 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 396
9b984dae
KP		 397 if (!is_edp(intel_dp))
398 return;
453c5420 399
4be73780 400 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 401 WARN(1, "eDP powered off while attempting aux channel communication.\n");
402 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 403 I915_READ(_pp_stat_reg(intel_dp)),
404 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 405 }
406}
407
9ee32fea
DV		 408static uint32_t
409intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
410{
411 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
412 struct drm_device *dev = intel_dig_port->base.base.dev;
413 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 414 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 415 uint32_t status;
416 bool done;
417
ef04f00d 418#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 419 if (has_aux_irq)
b18ac466 420 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 421 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 422 else
423 done = wait_for_atomic(C, 10) == 0;
424 if (!done)
425 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
426 has_aux_irq);
427#undef C
428
429 return status;
430}
431
ec5b01dd 432static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 433{
174edf1f
PZ		 434 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
435 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 436
ec5b01dd
DL		 437 /*
438 * The clock divider is based off the hrawclk, and would like to run at
439 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 440 */
ec5b01dd
DL		 441 return index ? 0 : intel_hrawclk(dev) / 2;
442}
443
444static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
445{
446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
447 struct drm_device *dev = intel_dig_port->base.base.dev;
448
449 if (index)
450 return 0;
451
452 if (intel_dig_port->port == PORT_A) {
453 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 454 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 455 else
b84a1cf8 456 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 457 } else {
458 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
459 }
460}
461
462static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
463{
464 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
465 struct drm_device *dev = intel_dig_port->base.base.dev;
466 struct drm_i915_private *dev_priv = dev->dev_private;
467
468 if (intel_dig_port->port == PORT_A) {
469 if (index)
470 return 0;
471 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 472 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
473 /* Workaround for non-ULT HSW */
bc86625a
CW		 474 switch (index) {
475 case 0: return 63;
476 case 1: return 72;
477 default: return 0;
478 }
ec5b01dd 479 } else {
bc86625a 480 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 481 }
b84a1cf8
RV		 482}
483
ec5b01dd
DL		 484static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
485{
486 return index ? 0 : 100;
487}
488
5ed12a19
DL		 489static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
490 bool has_aux_irq,
491 int send_bytes,
492 uint32_t aux_clock_divider)
493{
494 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
495 struct drm_device *dev = intel_dig_port->base.base.dev;
496 uint32_t precharge, timeout;
497
498 if (IS_GEN6(dev))
499 precharge = 3;
500 else
501 precharge = 5;
502
503 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
504 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
505 else
506 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
507
508 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 509 DP_AUX_CH_CTL_DONE |
5ed12a19 510 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 511 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 512 timeout |
788d4433 513 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 514 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
515 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 516 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 517}
518
b84a1cf8
RV		 519static int
520intel_dp_aux_ch(struct intel_dp *intel_dp,
521 uint8_t *send, int send_bytes,
522 uint8_t *recv, int recv_size)
523{
524 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
525 struct drm_device *dev = intel_dig_port->base.base.dev;
526 struct drm_i915_private *dev_priv = dev->dev_private;
527 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
528 uint32_t ch_data = ch_ctl + 4;
bc86625a 529 uint32_t aux_clock_divider;
b84a1cf8
RV		 530 int i, ret, recv_bytes;
531 uint32_t status;
5ed12a19 532 int try, clock = 0;
4e6b788c 533 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 534 bool vdd;
535
72c3500a
VS		 536 /*
537 * We will be called with VDD already enabled for dpcd/edid/oui reads.
538 * In such cases we want to leave VDD enabled and it's up to upper layers
539 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
540 * ourselves.
541 */
1e0560e0 542 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 543
544 /* dp aux is extremely sensitive to irq latency, hence request the
545 * lowest possible wakeup latency and so prevent the cpu from going into
546 * deep sleep states.
547 */
548 pm_qos_update_request(&dev_priv->pm_qos, 0);
549
550 intel_dp_check_edp(intel_dp);
5eb08b69 551
c67a470b
PZ		 552 intel_aux_display_runtime_get(dev_priv);
553
11bee43e
JB		 554 /* Try to wait for any previous AUX channel activity */
555 for (try = 0; try < 3; try++) {
ef04f00d 556 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 557 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
558 break;
559 msleep(1);
560 }
561
562 if (try == 3) {
563 WARN(1, "dp_aux_ch not started status 0x%08x\n",
564 I915_READ(ch_ctl));
9ee32fea
DV		 565 ret = -EBUSY;
566 goto out;
4f7f7b7e
CW		 567 }
568
46a5ae9f
PZ		 569 /* Only 5 data registers! */
570 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
571 ret = -E2BIG;
572 goto out;
573 }
574
ec5b01dd 575 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 576 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
577 has_aux_irq,
578 send_bytes,
579 aux_clock_divider);
5ed12a19 580
bc86625a
CW		 581 /* Must try at least 3 times according to DP spec */
582 for (try = 0; try < 5; try++) {
583 /* Load the send data into the aux channel data registers */
584 for (i = 0; i < send_bytes; i += 4)
585 I915_WRITE(ch_data + i,
586 pack_aux(send + i, send_bytes - i));
587
588 /* Send the command and wait for it to complete */
5ed12a19 589 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 590
591 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
592
593 /* Clear done status and any errors */
594 I915_WRITE(ch_ctl,
595 status |
596 DP_AUX_CH_CTL_DONE |
597 DP_AUX_CH_CTL_TIME_OUT_ERROR |
598 DP_AUX_CH_CTL_RECEIVE_ERROR);
599
600 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
601 DP_AUX_CH_CTL_RECEIVE_ERROR))
602 continue;
603 if (status & DP_AUX_CH_CTL_DONE)
604 break;
605 }
4f7f7b7e 606 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 607 break;
608 }
609
a4fc5ed6 610 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 611 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 612 ret = -EBUSY;
613 goto out;
a4fc5ed6
KP		 614 }
615
616 /* Check for timeout or receive error.
617 * Timeouts occur when the sink is not connected
618 */
a5b3da54 619 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 620 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 621 ret = -EIO;
622 goto out;
a5b3da54 623 }
1ae8c0a5
KP		 624
625 /* Timeouts occur when the device isn't connected, so they're
626 * "normal" -- don't fill the kernel log with these */
a5b3da54 627 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 628 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 629 ret = -ETIMEDOUT;
630 goto out;
a4fc5ed6
KP		 631 }
632
633 /* Unload any bytes sent back from the other side */
634 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
635 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 636 if (recv_bytes > recv_size)
637 recv_bytes = recv_size;
0206e353 638
4f7f7b7e
CW		 639 for (i = 0; i < recv_bytes; i += 4)
640 unpack_aux(I915_READ(ch_data + i),
641 recv + i, recv_bytes - i);
a4fc5ed6 642
9ee32fea
DV		 643 ret = recv_bytes;
644out:
645 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 646 intel_aux_display_runtime_put(dev_priv);
9ee32fea 647
884f19e9
JN		 648 if (vdd)
649 edp_panel_vdd_off(intel_dp, false);
650
9ee32fea 651 return ret;
a4fc5ed6
KP		 652}
653
a6c8aff0
JN		 654#define BARE_ADDRESS_SIZE 3
655#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 656static ssize_t
657intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 658{
9d1a1031
JN		 659 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
660 uint8_t txbuf[20], rxbuf[20];
661 size_t txsize, rxsize;
a4fc5ed6 662 int ret;
a4fc5ed6 663
9d1a1031
JN		 664 txbuf[0] = msg->request << 4;
665 txbuf[1] = msg->address >> 8;
666 txbuf[2] = msg->address & 0xff;
667 txbuf[3] = msg->size - 1;
46a5ae9f 668
9d1a1031
JN		 669 switch (msg->request & ~DP_AUX_I2C_MOT) {
670 case DP_AUX_NATIVE_WRITE:
671 case DP_AUX_I2C_WRITE:
a6c8aff0 672 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 673 rxsize = 1;
f51a44b9 674
9d1a1031
JN		 675 if (WARN_ON(txsize > 20))
676 return -E2BIG;
a4fc5ed6 677
9d1a1031 678 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 679
9d1a1031
JN		 680 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
681 if (ret > 0) {
682 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 683
9d1a1031
JN		 684 /* Return payload size. */
685 ret = msg->size;
686 }
687 break;
46a5ae9f 688
9d1a1031
JN		 689 case DP_AUX_NATIVE_READ:
690 case DP_AUX_I2C_READ:
a6c8aff0 691 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 692 rxsize = msg->size + 1;
a4fc5ed6 693
9d1a1031
JN		 694 if (WARN_ON(rxsize > 20))
695 return -E2BIG;
a4fc5ed6 696
9d1a1031
JN		 697 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
698 if (ret > 0) {
699 msg->reply = rxbuf[0] >> 4;
700 /*
701 * Assume happy day, and copy the data. The caller is
702 * expected to check msg->reply before touching it.
703 *
704 * Return payload size.
705 */
706 ret--;
707 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 708 }
9d1a1031
JN		 709 break;
710
711 default:
712 ret = -EINVAL;
713 break;
a4fc5ed6 714 }
f51a44b9 715
9d1a1031 716 return ret;
a4fc5ed6
KP		 717}
718
9d1a1031
JN		 719static void
720intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
721{
722 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 723 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
724 enum port port = intel_dig_port->port;
0b99836f 725 const char *name = NULL;
ab2c0672
DA		 726 int ret;
727
33ad6626
JN		 728 switch (port) {
729 case PORT_A:
730 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 731 name = "DPDDC-A";
ab2c0672 732 break;
33ad6626
JN		 733 case PORT_B:
734 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 735 name = "DPDDC-B";
ab2c0672 736 break;
33ad6626
JN		 737 case PORT_C:
738 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 739 name = "DPDDC-C";
ab2c0672 740 break;
33ad6626
JN		 741 case PORT_D:
742 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 743 name = "DPDDC-D";
33ad6626
JN		 744 break;
745 default:
746 BUG();
ab2c0672
DA		 747 }
748
33ad6626
JN		 749 if (!HAS_DDI(dev))
750 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 751
0b99836f 752 intel_dp->aux.name = name;
9d1a1031
JN		 753 intel_dp->aux.dev = dev->dev;
754 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 755
0b99836f
JN		 756 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
757 connector->base.kdev->kobj.name);
8316f337 758
4f71d0cb 759 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 760 if (ret < 0) {
4f71d0cb 761 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 762 name, ret);
763 return;
ab2c0672 764 }
8a5e6aeb 765
0b99836f
JN		 766 ret = sysfs_create_link(&connector->base.kdev->kobj,
767 &intel_dp->aux.ddc.dev.kobj,
768 intel_dp->aux.ddc.dev.kobj.name);
769 if (ret < 0) {
770 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 771 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 772 }
a4fc5ed6
KP		 773}
774
80f65de3
ID		 775static void
776intel_dp_connector_unregister(struct intel_connector *intel_connector)
777{
778 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
779
0e32b39c
DA		 780 if (!intel_connector->mst_port)
781 sysfs_remove_link(&intel_connector->base.kdev->kobj,
782 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 783 intel_connector_unregister(intel_connector);
784}
785
0e50338c
DV		 786static void
787hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
788{
789 switch (link_bw) {
790 case DP_LINK_BW_1_62:
791 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
792 break;
793 case DP_LINK_BW_2_7:
794 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
795 break;
796 case DP_LINK_BW_5_4:
797 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
798 break;
799 }
800}
801
c6bb3538
DV		 802static void
803intel_dp_set_clock(struct intel_encoder *encoder,
804 struct intel_crtc_config *pipe_config, int link_bw)
805{
806 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 807 const struct dp_link_dpll *divisor = NULL;
808 int i, count = 0;
c6bb3538
DV		 809
810 if (IS_G4X(dev)) {
9dd4ffdf
CML		 811 divisor = gen4_dpll;
812 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 813 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 814 divisor = pch_dpll;
815 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 816 } else if (IS_CHERRYVIEW(dev)) {
817 divisor = chv_dpll;
818 count = ARRAY_SIZE(chv_dpll);
c6bb3538 819 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 820 divisor = vlv_dpll;
821 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 822 }
9dd4ffdf
CML		 823
824 if (divisor && count) {
825 for (i = 0; i < count; i++) {
826 if (link_bw == divisor[i].link_bw) {
827 pipe_config->dpll = divisor[i].dpll;
828 pipe_config->clock_set = true;
829 break;
830 }
831 }
c6bb3538
DV		 832 }
833}
834
00c09d70 835bool
5bfe2ac0
DV		 836intel_dp_compute_config(struct intel_encoder *encoder,
837 struct intel_crtc_config *pipe_config)
a4fc5ed6 838{
5bfe2ac0 839 struct drm_device *dev = encoder->base.dev;
36008365 840 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 841 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 842 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 843 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 844 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 845 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 846 int lane_count, clock;
56071a20 847 int min_lane_count = 1;
eeb6324d 848 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 849 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 850 int min_clock = 0;
06ea66b6 851 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 852 int bpp, mode_rate;
06ea66b6 853 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 854 int link_avail, link_clock;
a4fc5ed6 855
bc7d38a4 856 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 857 pipe_config->has_pch_encoder = true;
858
03afc4a2 859 pipe_config->has_dp_encoder = true;
f769cd24 860 pipe_config->has_drrs = false;
9ed109a7 861 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 862
dd06f90e
JN		 863 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
864 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
865 adjusted_mode);
2dd24552
JB		 866 if (!HAS_PCH_SPLIT(dev))
867 intel_gmch_panel_fitting(intel_crtc, pipe_config,
868 intel_connector->panel.fitting_mode);
869 else
b074cec8
JB		 870 intel_pch_panel_fitting(intel_crtc, pipe_config,
871 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 872 }
873
cb1793ce 874 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 875 return false;
876
083f9560
DV		 877 DRM_DEBUG_KMS("DP link computation with max lane count %i "
878 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 879 max_lane_count, bws[max_clock],
880 adjusted_mode->crtc_clock);
083f9560 881
36008365
DV		 882 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
883 * bpc in between. */
3e7ca985 884 bpp = pipe_config->pipe_bpp;
56071a20
JN		 885 if (is_edp(intel_dp)) {
886 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
887 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
888 dev_priv->vbt.edp_bpp);
889 bpp = dev_priv->vbt.edp_bpp;
890 }
891
f4cdbc21
JN		 892 if (IS_BROADWELL(dev)) {
893 /* Yes, it's an ugly hack. */
894 min_lane_count = max_lane_count;
895 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
896 min_lane_count);
897 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 898 min_lane_count = min(dev_priv->vbt.edp_lanes,
899 max_lane_count);
900 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
901 min_lane_count);
902 }
903
904 if (dev_priv->vbt.edp_rate) {
905 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
906 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
907 bws[min_clock]);
908 }
7984211e 909 }
657445fe 910
36008365 911 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 912 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
913 bpp);
36008365 914
c6930992
DA		 915 for (clock = min_clock; clock <= max_clock; clock++) {
916 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 917 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
918 link_avail = intel_dp_max_data_rate(link_clock,
919 lane_count);
920
921 if (mode_rate <= link_avail) {
922 goto found;
923 }
924 }
925 }
926 }
c4867936 927
36008365 928 return false;
3685a8f3 929
36008365 930found:
55bc60db
VS		 931 if (intel_dp->color_range_auto) {
932 /*
933 * See:
934 * CEA-861-E - 5.1 Default Encoding Parameters
935 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
936 */
18316c8c 937 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 938 intel_dp->color_range = DP_COLOR_RANGE_16_235;
939 else
940 intel_dp->color_range = 0;
941 }
942
3685a8f3 943 if (intel_dp->color_range)
50f3b016 944 pipe_config->limited_color_range = true;
a4fc5ed6 945
36008365
DV		 946 intel_dp->link_bw = bws[clock];
947 intel_dp->lane_count = lane_count;
657445fe 948 pipe_config->pipe_bpp = bpp;
ff9a6750 949 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 950
36008365
DV		 951 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
952 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 953 pipe_config->port_clock, bpp);
36008365
DV		 954 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
955 mode_rate, link_avail);
a4fc5ed6 956
03afc4a2 957 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 958 adjusted_mode->crtc_clock,
959 pipe_config->port_clock,
03afc4a2 960 &pipe_config->dp_m_n);
9d1a455b 961
439d7ac0
PB		 962 if (intel_connector->panel.downclock_mode != NULL &&
963 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 964 pipe_config->has_drrs = true;
439d7ac0
PB		 965 intel_link_compute_m_n(bpp, lane_count,
966 intel_connector->panel.downclock_mode->clock,
967 pipe_config->port_clock,
968 &pipe_config->dp_m2_n2);
969 }
970
ea155f32 971 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 972 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
973 else
974 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 975
03afc4a2 976 return true;
a4fc5ed6
KP		 977}
978
7c62a164 979static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 980{
7c62a164
DV		 981 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
982 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
983 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 984 struct drm_i915_private *dev_priv = dev->dev_private;
985 u32 dpa_ctl;
986
ff9a6750 987 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 988 dpa_ctl = I915_READ(DP_A);
989 dpa_ctl &= ~DP_PLL_FREQ_MASK;
990
ff9a6750 991 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 992 /* For a long time we've carried around a ILK-DevA w/a for the
993 * 160MHz clock. If we're really unlucky, it's still required.
994 */
995 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 996 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 997 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 998 } else {
999 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1000 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1001 }
1ce17038 1002
ea9b6006
DV		 1003 I915_WRITE(DP_A, dpa_ctl);
1004
1005 POSTING_READ(DP_A);
1006 udelay(500);
1007}
1008
8ac33ed3 1009static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1010{
b934223d 1011 struct drm_device *dev = encoder->base.dev;
417e822d 1012 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1013 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1014 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1015 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1016 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1017
417e822d 1018 /*
1a2eb460 1019 * There are four kinds of DP registers:
417e822d
KP		 1020 *
1021 * IBX PCH
1a2eb460
KP		 1022 * SNB CPU
1023 * IVB CPU
417e822d
KP		 1024 * CPT PCH
1025 *
1026 * IBX PCH and CPU are the same for almost everything,
1027 * except that the CPU DP PLL is configured in this
1028 * register
1029 *
1030 * CPT PCH is quite different, having many bits moved
1031 * to the TRANS_DP_CTL register instead. That
1032 * configuration happens (oddly) in ironlake_pch_enable
1033 */
9c9e7927 1034
417e822d
KP		 1035 /* Preserve the BIOS-computed detected bit. This is
1036 * supposed to be read-only.
1037 */
1038 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1039
417e822d 1040 /* Handle DP bits in common between all three register formats */
417e822d 1041 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1042 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1043
9ed109a7 1044 if (crtc->config.has_audio) {
e0dac65e 1045 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1046 pipe_name(crtc->pipe));
ea5b213a 1047 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1048 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1049 }
247d89f6 1050
417e822d 1051 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1052
bc7d38a4 1053 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1054 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1055 intel_dp->DP |= DP_SYNC_HS_HIGH;
1056 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1057 intel_dp->DP |= DP_SYNC_VS_HIGH;
1058 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1059
6aba5b6c 1060 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1061 intel_dp->DP |= DP_ENHANCED_FRAMING;
1062
7c62a164 1063 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1064 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1065 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1066 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1067
1068 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1069 intel_dp->DP |= DP_SYNC_HS_HIGH;
1070 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1071 intel_dp->DP |= DP_SYNC_VS_HIGH;
1072 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1073
6aba5b6c 1074 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1075 intel_dp->DP |= DP_ENHANCED_FRAMING;
1076
44f37d1f
CML		 1077 if (!IS_CHERRYVIEW(dev)) {
1078 if (crtc->pipe == 1)
1079 intel_dp->DP |= DP_PIPEB_SELECT;
1080 } else {
1081 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1082 }
417e822d
KP		 1083 } else {
1084 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1085 }
a4fc5ed6
KP		 1086}
1087
ffd6749d
PZ		 1088#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1089#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1090
1a5ef5b7
PZ		 1091#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1092#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1093
ffd6749d
PZ		 1094#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1095#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1096
4be73780 1097static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1098 u32 mask,
1099 u32 value)
bd943159 1100{
30add22d 1101 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1102 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1103 u32 pp_stat_reg, pp_ctrl_reg;
1104
bf13e81b
JN		 1105 pp_stat_reg = _pp_stat_reg(intel_dp);
1106 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1107
99ea7127 1108 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1109 mask, value,
1110 I915_READ(pp_stat_reg),
1111 I915_READ(pp_ctrl_reg));
32ce697c 1112
453c5420 1113 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1114 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1115 I915_READ(pp_stat_reg),
1116 I915_READ(pp_ctrl_reg));
32ce697c 1117 }
54c136d4
CW		 1118
1119 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1120}
32ce697c 1121
4be73780 1122static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1123{
1124 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1125 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1126}
1127
4be73780 1128static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1129{
1130 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1131 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1132}
1133
4be73780 1134static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1135{
1136 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1137
1138 /* When we disable the VDD override bit last we have to do the manual
1139 * wait. */
1140 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1141 intel_dp->panel_power_cycle_delay);
1142
4be73780 1143 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1144}
1145
4be73780 1146static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1147{
1148 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1149 intel_dp->backlight_on_delay);
1150}
1151
4be73780 1152static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1153{
1154 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1155 intel_dp->backlight_off_delay);
1156}
99ea7127 1157
832dd3c1
KP		 1158/* Read the current pp_control value, unlocking the register if it
1159 * is locked
1160 */
1161
453c5420 1162static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1163{
453c5420
JB		 1164 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1165 struct drm_i915_private *dev_priv = dev->dev_private;
1166 u32 control;
832dd3c1 1167
bf13e81b 1168 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1169 control &= ~PANEL_UNLOCK_MASK;
1170 control |= PANEL_UNLOCK_REGS;
1171 return control;
bd943159
KP		 1172}
1173
1e0560e0 1174static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1175{
30add22d 1176 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1177 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1178 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1179 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1180 enum intel_display_power_domain power_domain;
5d613501 1181 u32 pp;
453c5420 1182 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1183 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1184
97af61f5 1185 if (!is_edp(intel_dp))
adddaaf4 1186 return false;
bd943159
KP		 1187
1188 intel_dp->want_panel_vdd = true;
99ea7127 1189
4be73780 1190 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1191 return need_to_disable;
b0665d57 1192
4e6e1a54
ID		 1193 power_domain = intel_display_port_power_domain(intel_encoder);
1194 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1195
b0665d57 1196 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1197
4be73780
DV		 1198 if (!edp_have_panel_power(intel_dp))
1199 wait_panel_power_cycle(intel_dp);
99ea7127 1200
453c5420 1201 pp = ironlake_get_pp_control(intel_dp);
5d613501 1202 pp |= EDP_FORCE_VDD;
ebf33b18 1203
bf13e81b
JN		 1204 pp_stat_reg = _pp_stat_reg(intel_dp);
1205 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1206
1207 I915_WRITE(pp_ctrl_reg, pp);
1208 POSTING_READ(pp_ctrl_reg);
1209 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1210 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1211 /*
1212 * If the panel wasn't on, delay before accessing aux channel
1213 */
4be73780 1214 if (!edp_have_panel_power(intel_dp)) {
bd943159 1215 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1216 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1217 }
adddaaf4
JN		 1218
1219 return need_to_disable;
1220}
1221
b80d6c78 1222void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1223{
c695b6b6 1224 bool vdd;
adddaaf4 1225
c695b6b6
VS		 1226 if (!is_edp(intel_dp))
1227 return;
1228
1229 vdd = edp_panel_vdd_on(intel_dp);
1230
1231 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1232}
1233
4be73780 1234static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1235{
30add22d 1236 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1237 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1238 struct intel_digital_port *intel_dig_port =
1239 dp_to_dig_port(intel_dp);
1240 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1241 enum intel_display_power_domain power_domain;
5d613501 1242 u32 pp;
453c5420 1243 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1244
51fd371b 1245 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
a0e99e68 1246
15e899a0
VS		 1247 WARN_ON(intel_dp->want_panel_vdd);
1248
1249 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1250 return;
4e6e1a54 1251
be2c9196 1252 DRM_DEBUG_KMS("Turning eDP VDD off\n");
b0665d57 1253
be2c9196
VS		 1254 pp = ironlake_get_pp_control(intel_dp);
1255 pp &= ~EDP_FORCE_VDD;
bd943159 1256
be2c9196
VS		 1257 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1258 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420 1259
be2c9196
VS		 1260 I915_WRITE(pp_ctrl_reg, pp);
1261 POSTING_READ(pp_ctrl_reg);
99ea7127 1262
be2c9196
VS		 1263 /* Make sure sequencer is idle before allowing subsequent activity */
1264 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1265 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c 1266
be2c9196
VS		 1267 if ((pp & POWER_TARGET_ON) == 0)
1268 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1269
be2c9196
VS		 1270 power_domain = intel_display_port_power_domain(intel_encoder);
1271 intel_display_power_put(dev_priv, power_domain);
bd943159 1272}
5d613501 1273
4be73780 1274static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1275{
1276 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1277 struct intel_dp, panel_vdd_work);
30add22d 1278 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1279
51fd371b 1280 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
15e899a0
VS		 1281 if (!intel_dp->want_panel_vdd)
1282 edp_panel_vdd_off_sync(intel_dp);
51fd371b 1283 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159
KP		 1284}
1285
aba86890
ID		 1286static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1287{
1288 unsigned long delay;
1289
1290 /*
1291 * Queue the timer to fire a long time from now (relative to the power
1292 * down delay) to keep the panel power up across a sequence of
1293 * operations.
1294 */
1295 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1296 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1297}
1298
4be73780 1299static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1300{
97af61f5
KP		 1301 if (!is_edp(intel_dp))
1302 return;
5d613501 1303
bd943159 1304 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1305
bd943159
KP		 1306 intel_dp->want_panel_vdd = false;
1307
aba86890 1308 if (sync)
4be73780 1309 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1310 else
1311 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1312}
1313
1e0560e0
VS		 1314static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1315{
1316 edp_panel_vdd_off(intel_dp, sync);
1317}
1318
4be73780 1319void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1320{
30add22d 1321 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1322 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1323 u32 pp;
453c5420 1324 u32 pp_ctrl_reg;
9934c132 1325
97af61f5 1326 if (!is_edp(intel_dp))
bd943159 1327 return;
99ea7127
KP		 1328
1329 DRM_DEBUG_KMS("Turn eDP power on\n");
1330
4be73780 1331 if (edp_have_panel_power(intel_dp)) {
99ea7127 1332 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1333 return;
99ea7127 1334 }
9934c132 1335
4be73780 1336 wait_panel_power_cycle(intel_dp);
37c6c9b0 1337
bf13e81b 1338 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1339 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1340 if (IS_GEN5(dev)) {
1341 /* ILK workaround: disable reset around power sequence */
1342 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1343 I915_WRITE(pp_ctrl_reg, pp);
1344 POSTING_READ(pp_ctrl_reg);
05ce1a49 1345 }
37c6c9b0 1346
1c0ae80a 1347 pp |= POWER_TARGET_ON;
99ea7127
KP		 1348 if (!IS_GEN5(dev))
1349 pp |= PANEL_POWER_RESET;
1350
453c5420
JB		 1351 I915_WRITE(pp_ctrl_reg, pp);
1352 POSTING_READ(pp_ctrl_reg);
9934c132 1353
4be73780 1354 wait_panel_on(intel_dp);
dce56b3c 1355 intel_dp->last_power_on = jiffies;
9934c132 1356
05ce1a49
KP		 1357 if (IS_GEN5(dev)) {
1358 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1359 I915_WRITE(pp_ctrl_reg, pp);
1360 POSTING_READ(pp_ctrl_reg);
05ce1a49 1361 }
9934c132
JB		 1362}
1363
4be73780 1364void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1365{
4e6e1a54
ID		 1366 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1367 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1368 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1369 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1370 enum intel_display_power_domain power_domain;
99ea7127 1371 u32 pp;
453c5420 1372 u32 pp_ctrl_reg;
9934c132 1373
97af61f5
KP		 1374 if (!is_edp(intel_dp))
1375 return;
37c6c9b0 1376
99ea7127 1377 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1378
24f3e092
JN		 1379 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1380
453c5420 1381 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1382 /* We need to switch off panel power _and_ force vdd, for otherwise some
1383 * panels get very unhappy and cease to work. */
b3064154
PJ		 1384 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1385 EDP_BLC_ENABLE);
453c5420 1386
bf13e81b 1387 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1388
849e39f5
PZ		 1389 intel_dp->want_panel_vdd = false;
1390
453c5420
JB		 1391 I915_WRITE(pp_ctrl_reg, pp);
1392 POSTING_READ(pp_ctrl_reg);
9934c132 1393
dce56b3c 1394 intel_dp->last_power_cycle = jiffies;
4be73780 1395 wait_panel_off(intel_dp);
849e39f5
PZ		 1396
1397 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1398 power_domain = intel_display_port_power_domain(intel_encoder);
1399 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1400}
1401
1250d107
JN		 1402/* Enable backlight in the panel power control. */
1403static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1404{
da63a9f2
PZ		 1405 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1406 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1407 struct drm_i915_private *dev_priv = dev->dev_private;
1408 u32 pp;
453c5420 1409 u32 pp_ctrl_reg;
32f9d658 1410
01cb9ea6
JB		 1411 /*
1412 * If we enable the backlight right away following a panel power
1413 * on, we may see slight flicker as the panel syncs with the eDP
1414 * link. So delay a bit to make sure the image is solid before
1415 * allowing it to appear.
1416 */
4be73780 1417 wait_backlight_on(intel_dp);
453c5420 1418 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1419 pp |= EDP_BLC_ENABLE;
453c5420 1420
bf13e81b 1421 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1422
1423 I915_WRITE(pp_ctrl_reg, pp);
1424 POSTING_READ(pp_ctrl_reg);
32f9d658
ZW		 1425}
1426
1250d107
JN		 1427/* Enable backlight PWM and backlight PP control. */
1428void intel_edp_backlight_on(struct intel_dp *intel_dp)
1429{
1430 if (!is_edp(intel_dp))
1431 return;
1432
1433 DRM_DEBUG_KMS("\n");
1434
1435 intel_panel_enable_backlight(intel_dp->attached_connector);
1436 _intel_edp_backlight_on(intel_dp);
1437}
1438
1439/* Disable backlight in the panel power control. */
1440static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1441{
30add22d 1442 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1443 struct drm_i915_private *dev_priv = dev->dev_private;
1444 u32 pp;
453c5420 1445 u32 pp_ctrl_reg;
32f9d658 1446
453c5420 1447 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1448 pp &= ~EDP_BLC_ENABLE;
453c5420 1449
bf13e81b 1450 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1451
1452 I915_WRITE(pp_ctrl_reg, pp);
1453 POSTING_READ(pp_ctrl_reg);
dce56b3c 1454 intel_dp->last_backlight_off = jiffies;
f7d2323c
JB		 1455
1456 edp_wait_backlight_off(intel_dp);
1250d107
JN		 1457}
1458
1459/* Disable backlight PP control and backlight PWM. */
1460void intel_edp_backlight_off(struct intel_dp *intel_dp)
1461{
1462 if (!is_edp(intel_dp))
1463 return;
1464
1465 DRM_DEBUG_KMS("\n");
f7d2323c 1466
1250d107 1467 _intel_edp_backlight_off(intel_dp);
f7d2323c 1468 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1469}
a4fc5ed6 1470
73580fb7
JN		 1471/*
1472 * Hook for controlling the panel power control backlight through the bl_power
1473 * sysfs attribute. Take care to handle multiple calls.
1474 */
1475static void intel_edp_backlight_power(struct intel_connector *connector,
1476 bool enable)
1477{
1478 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
1479 bool is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1480
1481 if (is_enabled == enable)
1482 return;
1483
23ba9373
JN		 1484 DRM_DEBUG_KMS("panel power control backlight %s\n",
1485 enable ? "enable" : "disable");
73580fb7
JN		 1486
1487 if (enable)
1488 _intel_edp_backlight_on(intel_dp);
1489 else
1490 _intel_edp_backlight_off(intel_dp);
1491}
1492
2bd2ad64 1493static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1494{
da63a9f2
PZ		 1495 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1496 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1497 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1498 struct drm_i915_private *dev_priv = dev->dev_private;
1499 u32 dpa_ctl;
1500
2bd2ad64
DV		 1501 assert_pipe_disabled(dev_priv,
1502 to_intel_crtc(crtc)->pipe);
1503
d240f20f
JB		 1504 DRM_DEBUG_KMS("\n");
1505 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1506 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1507 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1508
1509 /* We don't adjust intel_dp->DP while tearing down the link, to
1510 * facilitate link retraining (e.g. after hotplug). Hence clear all
1511 * enable bits here to ensure that we don't enable too much. */
1512 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1513 intel_dp->DP |= DP_PLL_ENABLE;
1514 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1515 POSTING_READ(DP_A);
1516 udelay(200);
d240f20f
JB		 1517}
1518
2bd2ad64 1519static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1520{
da63a9f2
PZ		 1521 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1522 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1523 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1524 struct drm_i915_private *dev_priv = dev->dev_private;
1525 u32 dpa_ctl;
1526
2bd2ad64
DV		 1527 assert_pipe_disabled(dev_priv,
1528 to_intel_crtc(crtc)->pipe);
1529
d240f20f 1530 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1531 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1532 "dp pll off, should be on\n");
1533 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1534
1535 /* We can't rely on the value tracked for the DP register in
1536 * intel_dp->DP because link_down must not change that (otherwise link
1537 * re-training will fail. */
298b0b39 1538 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1539 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1540 POSTING_READ(DP_A);
d240f20f
JB		 1541 udelay(200);
1542}
1543
c7ad3810 1544/* If the sink supports it, try to set the power state appropriately */
c19b0669 1545void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1546{
1547 int ret, i;
1548
1549 /* Should have a valid DPCD by this point */
1550 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1551 return;
1552
1553 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1554 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1555 DP_SET_POWER_D3);
c7ad3810
JB		 1556 if (ret != 1)
1557 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1558 } else {
1559 /*
1560 * When turning on, we need to retry for 1ms to give the sink
1561 * time to wake up.
1562 */
1563 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1564 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1565 DP_SET_POWER_D0);
c7ad3810
JB		 1566 if (ret == 1)
1567 break;
1568 msleep(1);
1569 }
1570 }
1571}
1572
19d8fe15
DV		 1573static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1574 enum pipe *pipe)
d240f20f 1575{
19d8fe15 1576 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1577 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1578 struct drm_device *dev = encoder->base.dev;
1579 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1580 enum intel_display_power_domain power_domain;
1581 u32 tmp;
1582
1583 power_domain = intel_display_port_power_domain(encoder);
1584 if (!intel_display_power_enabled(dev_priv, power_domain))
1585 return false;
1586
1587 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1588
1589 if (!(tmp & DP_PORT_EN))
1590 return false;
1591
bc7d38a4 1592 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1593 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1594 } else if (IS_CHERRYVIEW(dev)) {
1595 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1596 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1597 *pipe = PORT_TO_PIPE(tmp);
1598 } else {
1599 u32 trans_sel;
1600 u32 trans_dp;
1601 int i;
1602
1603 switch (intel_dp->output_reg) {
1604 case PCH_DP_B:
1605 trans_sel = TRANS_DP_PORT_SEL_B;
1606 break;
1607 case PCH_DP_C:
1608 trans_sel = TRANS_DP_PORT_SEL_C;
1609 break;
1610 case PCH_DP_D:
1611 trans_sel = TRANS_DP_PORT_SEL_D;
1612 break;
1613 default:
1614 return true;
1615 }
1616
055e393f 1617 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1618 trans_dp = I915_READ(TRANS_DP_CTL(i));
1619 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1620 *pipe = i;
1621 return true;
1622 }
1623 }
19d8fe15 1624
4a0833ec
DV		 1625 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1626 intel_dp->output_reg);
1627 }
d240f20f 1628
19d8fe15
DV		 1629 return true;
1630}
d240f20f 1631
045ac3b5
JB		 1632static void intel_dp_get_config(struct intel_encoder *encoder,
1633 struct intel_crtc_config *pipe_config)
1634{
1635 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1636 u32 tmp, flags = 0;
63000ef6
XZ		 1637 struct drm_device *dev = encoder->base.dev;
1638 struct drm_i915_private *dev_priv = dev->dev_private;
1639 enum port port = dp_to_dig_port(intel_dp)->port;
1640 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1641 int dotclock;
045ac3b5 1642
9ed109a7
DV		 1643 tmp = I915_READ(intel_dp->output_reg);
1644 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1645 pipe_config->has_audio = true;
1646
63000ef6 1647 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1648 if (tmp & DP_SYNC_HS_HIGH)
1649 flags |= DRM_MODE_FLAG_PHSYNC;
1650 else
1651 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1652
63000ef6
XZ		 1653 if (tmp & DP_SYNC_VS_HIGH)
1654 flags |= DRM_MODE_FLAG_PVSYNC;
1655 else
1656 flags |= DRM_MODE_FLAG_NVSYNC;
1657 } else {
1658 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1659 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1660 flags |= DRM_MODE_FLAG_PHSYNC;
1661 else
1662 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1663
63000ef6
XZ		 1664 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1665 flags |= DRM_MODE_FLAG_PVSYNC;
1666 else
1667 flags |= DRM_MODE_FLAG_NVSYNC;
1668 }
045ac3b5
JB		 1669
1670 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1671
eb14cb74
VS		 1672 pipe_config->has_dp_encoder = true;
1673
1674 intel_dp_get_m_n(crtc, pipe_config);
1675
18442d08 1676 if (port == PORT_A) {
f1f644dc
JB		 1677 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1678 pipe_config->port_clock = 162000;
1679 else
1680 pipe_config->port_clock = 270000;
1681 }
18442d08
VS		 1682
1683 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1684 &pipe_config->dp_m_n);
1685
1686 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1687 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1688
241bfc38 1689 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1690
c6cd2ee2
JN		 1691 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1692 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1693 /*
1694 * This is a big fat ugly hack.
1695 *
1696 * Some machines in UEFI boot mode provide us a VBT that has 18
1697 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1698 * unknown we fail to light up. Yet the same BIOS boots up with
1699 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1700 * max, not what it tells us to use.
1701 *
1702 * Note: This will still be broken if the eDP panel is not lit
1703 * up by the BIOS, and thus we can't get the mode at module
1704 * load.
1705 */
1706 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1707 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1708 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1709 }
045ac3b5
JB		 1710}
1711
34eb7579 1712static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1713{
34eb7579 1714 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1715}
1716
2b28bb1b
RV		 1717static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1718{
1719 struct drm_i915_private *dev_priv = dev->dev_private;
1720
18b5992c 1721 if (!HAS_PSR(dev))
2b28bb1b
RV		 1722 return false;
1723
18b5992c 1724 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1725}
1726
1727static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1728 struct edp_vsc_psr *vsc_psr)
1729{
1730 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1731 struct drm_device *dev = dig_port->base.base.dev;
1732 struct drm_i915_private *dev_priv = dev->dev_private;
1733 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1734 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1735 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1736 uint32_t *data = (uint32_t *) vsc_psr;
1737 unsigned int i;
1738
1739 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1740 the video DIP being updated before program video DIP data buffer
1741 registers for DIP being updated. */
1742 I915_WRITE(ctl_reg, 0);
1743 POSTING_READ(ctl_reg);
1744
1745 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1746 if (i < sizeof(struct edp_vsc_psr))
1747 I915_WRITE(data_reg + i, *data++);
1748 else
1749 I915_WRITE(data_reg + i, 0);
1750 }
1751
1752 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1753 POSTING_READ(ctl_reg);
1754}
1755
1756static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1757{
1758 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1759 struct drm_i915_private *dev_priv = dev->dev_private;
1760 struct edp_vsc_psr psr_vsc;
1761
2b28bb1b
RV		 1762 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1763 memset(&psr_vsc, 0, sizeof(psr_vsc));
1764 psr_vsc.sdp_header.HB0 = 0;
1765 psr_vsc.sdp_header.HB1 = 0x7;
1766 psr_vsc.sdp_header.HB2 = 0x2;
1767 psr_vsc.sdp_header.HB3 = 0x8;
1768 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1769
1770 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1771 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1772 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1773}
1774
1775static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1776{
0e0ae652
RV		 1777 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1778 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 1779 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1780 uint32_t aux_clock_divider;
2b28bb1b
RV		 1781 int precharge = 0x3;
1782 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 1783 bool only_standby = false;
2b28bb1b 1784
ec5b01dd
DL		 1785 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1786
0e0ae652
RV		 1787 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1788 only_standby = true;
1789
2b28bb1b 1790 /* Enable PSR in sink */
0e0ae652 1791 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 1792 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1793 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1794 else
9d1a1031
JN		 1795 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1796 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1797
1798 /* Setup AUX registers */
18b5992c
BW		 1799 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1800 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1801 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1802 DP_AUX_CH_CTL_TIME_OUT_400us |
1803 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1804 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1805 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1806}
1807
1808static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1809{
0e0ae652
RV		 1810 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1811 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 1812 struct drm_i915_private *dev_priv = dev->dev_private;
1813 uint32_t max_sleep_time = 0x1f;
1814 uint32_t idle_frames = 1;
1815 uint32_t val = 0x0;
ed8546ac 1816 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 1817 bool only_standby = false;
1818
1819 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1820 only_standby = true;
2b28bb1b 1821
0e0ae652 1822 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 1823 val |= EDP_PSR_LINK_STANDBY;
1824 val |= EDP_PSR_TP2_TP3_TIME_0us;
1825 val |= EDP_PSR_TP1_TIME_0us;
1826 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 1827 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 1828 } else
1829 val |= EDP_PSR_LINK_DISABLE;
1830
18b5992c 1831 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1832 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1833 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1834 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1835 EDP_PSR_ENABLE);
1836}
1837
3f51e471
RV		 1838static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1839{
1840 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1841 struct drm_device *dev = dig_port->base.base.dev;
1842 struct drm_i915_private *dev_priv = dev->dev_private;
1843 struct drm_crtc *crtc = dig_port->base.base.crtc;
1844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 1845
f0355c4a 1846 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 1847 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1848 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1849
a031d709
RV		 1850 dev_priv->psr.source_ok = false;
1851
9ca15301 1852 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 1853 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1854 return false;
1855 }
1856
d330a953 1857 if (!i915.enable_psr) {
105b7c11 1858 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1859 return false;
1860 }
1861
4c8c7000
RV		 1862 /* Below limitations aren't valid for Broadwell */
1863 if (IS_BROADWELL(dev))
1864 goto out;
1865
3f51e471
RV		 1866 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1867 S3D_ENABLE) {
1868 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1869 return false;
1870 }
1871
ca73b4f0 1872 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1873 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1874 return false;
1875 }
1876
4c8c7000 1877 out:
a031d709 1878 dev_priv->psr.source_ok = true;
3f51e471
RV		 1879 return true;
1880}
1881
3d739d92 1882static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 1883{
7c8f8a70
RV		 1884 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1885 struct drm_device *dev = intel_dig_port->base.base.dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 1887
3638379c
DV		 1888 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1889 WARN_ON(dev_priv->psr.active);
f0355c4a 1890 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 1891
2b28bb1b
RV		 1892 /* Enable PSR on the panel */
1893 intel_edp_psr_enable_sink(intel_dp);
1894
1895 /* Enable PSR on the host */
1896 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 1897
7c8f8a70 1898 dev_priv->psr.active = true;
2b28bb1b
RV		 1899}
1900
3d739d92
RV		 1901void intel_edp_psr_enable(struct intel_dp *intel_dp)
1902{
1903 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 1904 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 1905
4704c573
RV		 1906 if (!HAS_PSR(dev)) {
1907 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1908 return;
1909 }
1910
34eb7579
RV		 1911 if (!is_edp_psr(intel_dp)) {
1912 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1913 return;
1914 }
1915
f0355c4a 1916 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 1917 if (dev_priv->psr.enabled) {
1918 DRM_DEBUG_KMS("PSR already in use\n");
f0355c4a 1919 mutex_unlock(&dev_priv->psr.lock);
109fc2ad
DV		 1920 return;
1921 }
1922
9ca15301
DV		 1923 dev_priv->psr.busy_frontbuffer_bits = 0;
1924
16487254
RV		 1925 /* Setup PSR once */
1926 intel_edp_psr_setup(intel_dp);
1927
7c8f8a70 1928 if (intel_edp_psr_match_conditions(intel_dp))
9ca15301 1929 dev_priv->psr.enabled = intel_dp;
f0355c4a 1930 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 1931}
1932
2b28bb1b
RV		 1933void intel_edp_psr_disable(struct intel_dp *intel_dp)
1934{
1935 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1936 struct drm_i915_private *dev_priv = dev->dev_private;
1937
f0355c4a
DV		 1938 mutex_lock(&dev_priv->psr.lock);
1939 if (!dev_priv->psr.enabled) {
1940 mutex_unlock(&dev_priv->psr.lock);
1941 return;
1942 }
1943
3638379c
DV		 1944 if (dev_priv->psr.active) {
1945 I915_WRITE(EDP_PSR_CTL(dev),
1946 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1947
1948 /* Wait till PSR is idle */
1949 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1950 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1951 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 1952
3638379c
DV		 1953 dev_priv->psr.active = false;
1954 } else {
1955 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1956 }
7c8f8a70 1957
2807cf69 1958 dev_priv->psr.enabled = NULL;
f0355c4a 1959 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 1960
1961 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 1962}
1963
f02a326e 1964static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 1965{
1966 struct drm_i915_private *dev_priv =
1967 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 1968 struct intel_dp *intel_dp = dev_priv->psr.enabled;
1969
f0355c4a
DV		 1970 mutex_lock(&dev_priv->psr.lock);
1971 intel_dp = dev_priv->psr.enabled;
1972
2807cf69 1973 if (!intel_dp)
f0355c4a 1974 goto unlock;
2807cf69 1975
9ca15301
DV		 1976 /*
1977 * The delayed work can race with an invalidate hence we need to
1978 * recheck. Since psr_flush first clears this and then reschedules we
1979 * won't ever miss a flush when bailing out here.
1980 */
1981 if (dev_priv->psr.busy_frontbuffer_bits)
1982 goto unlock;
1983
1984 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 1985unlock:
1986 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 1987}
1988
9ca15301 1989static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 1990{
1991 struct drm_i915_private *dev_priv = dev->dev_private;
1992
3638379c
DV		 1993 if (dev_priv->psr.active) {
1994 u32 val = I915_READ(EDP_PSR_CTL(dev));
1995
1996 WARN_ON(!(val & EDP_PSR_ENABLE));
1997
1998 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
1999
2000 dev_priv->psr.active = false;
2001 }
7c8f8a70 2002
9ca15301
DV		 2003}
2004
2005void intel_edp_psr_invalidate(struct drm_device *dev,
2006 unsigned frontbuffer_bits)
2007{
2008 struct drm_i915_private *dev_priv = dev->dev_private;
2009 struct drm_crtc *crtc;
2010 enum pipe pipe;
2011
9ca15301
DV		 2012 mutex_lock(&dev_priv->psr.lock);
2013 if (!dev_priv->psr.enabled) {
2014 mutex_unlock(&dev_priv->psr.lock);
2015 return;
2016 }
2017
2018 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2019 pipe = to_intel_crtc(crtc)->pipe;
2020
2021 intel_edp_psr_do_exit(dev);
2022
2023 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2024
2025 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2026 mutex_unlock(&dev_priv->psr.lock);
2027}
2028
2029void intel_edp_psr_flush(struct drm_device *dev,
2030 unsigned frontbuffer_bits)
2031{
2032 struct drm_i915_private *dev_priv = dev->dev_private;
2033 struct drm_crtc *crtc;
2034 enum pipe pipe;
2035
9ca15301
DV		 2036 mutex_lock(&dev_priv->psr.lock);
2037 if (!dev_priv->psr.enabled) {
2038 mutex_unlock(&dev_priv->psr.lock);
2039 return;
2040 }
2041
2042 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2043 pipe = to_intel_crtc(crtc)->pipe;
2044 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2045
2046 /*
2047 * On Haswell sprite plane updates don't result in a psr invalidating
2048 * signal in the hardware. Which means we need to manually fake this in
2049 * software for all flushes, not just when we've seen a preceding
2050 * invalidation through frontbuffer rendering.
2051 */
2052 if (IS_HASWELL(dev) &&
2053 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2054 intel_edp_psr_do_exit(dev);
2055
2056 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2057 schedule_delayed_work(&dev_priv->psr.work,
2058 msecs_to_jiffies(100));
f0355c4a 2059 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2060}
2061
2062void intel_edp_psr_init(struct drm_device *dev)
2063{
2064 struct drm_i915_private *dev_priv = dev->dev_private;
2065
7c8f8a70 2066 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2067 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2068}
2069
e8cb4558 2070static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2071{
e8cb4558 2072 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 2073 enum port port = dp_to_dig_port(intel_dp)->port;
2074 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2075
2076 /* Make sure the panel is off before trying to change the mode. But also
2077 * ensure that we have vdd while we switch off the panel. */
24f3e092 2078 intel_edp_panel_vdd_on(intel_dp);
4be73780 2079 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2080 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2081 intel_edp_panel_off(intel_dp);
3739850b
DV		 2082
2083 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 2084 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 2085 intel_dp_link_down(intel_dp);
d240f20f
JB		 2086}
2087
49277c31 2088static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2089{
2bd2ad64 2090 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2091 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2092
49277c31
VS		 2093 if (port != PORT_A)
2094 return;
2095
2096 intel_dp_link_down(intel_dp);
2097 ironlake_edp_pll_off(intel_dp);
2098}
2099
2100static void vlv_post_disable_dp(struct intel_encoder *encoder)
2101{
2102 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2103
2104 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2105}
2106
580d3811
VS		 2107static void chv_post_disable_dp(struct intel_encoder *encoder)
2108{
2109 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2110 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2111 struct drm_device *dev = encoder->base.dev;
2112 struct drm_i915_private *dev_priv = dev->dev_private;
2113 struct intel_crtc *intel_crtc =
2114 to_intel_crtc(encoder->base.crtc);
2115 enum dpio_channel ch = vlv_dport_to_channel(dport);
2116 enum pipe pipe = intel_crtc->pipe;
2117 u32 val;
2118
2119 intel_dp_link_down(intel_dp);
2120
2121 mutex_lock(&dev_priv->dpio_lock);
2122
2123 /* Propagate soft reset to data lane reset */
97fd4d5c 2124 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2125 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2126 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2127
97fd4d5c
VS		 2128 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2129 val |= CHV_PCS_REQ_SOFTRESET_EN;
2130 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2131
2132 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2133 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2134 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2135
2136 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2137 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2138 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2139
2140 mutex_unlock(&dev_priv->dpio_lock);
2141}
2142
e8cb4558 2143static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2144{
e8cb4558
DV		 2145 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2146 struct drm_device *dev = encoder->base.dev;
2147 struct drm_i915_private *dev_priv = dev->dev_private;
2148 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2149
0c33d8d7
DV		 2150 if (WARN_ON(dp_reg & DP_PORT_EN))
2151 return;
5d613501 2152
24f3e092 2153 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 2154 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2155 intel_dp_start_link_train(intel_dp);
4be73780 2156 intel_edp_panel_on(intel_dp);
1e0560e0 2157 intel_edp_panel_vdd_off(intel_dp, true);
33a34e4e 2158 intel_dp_complete_link_train(intel_dp);
3ab9c637 2159 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2160}
89b667f8 2161
ecff4f3b
JN		 2162static void g4x_enable_dp(struct intel_encoder *encoder)
2163{
828f5c6e
JN		 2164 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2165
ecff4f3b 2166 intel_enable_dp(encoder);
4be73780 2167 intel_edp_backlight_on(intel_dp);
ab1f90f9 2168}
89b667f8 2169
ab1f90f9
JN		 2170static void vlv_enable_dp(struct intel_encoder *encoder)
2171{
828f5c6e
JN		 2172 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2173
4be73780 2174 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2175}
2176
ecff4f3b 2177static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2178{
2179 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2180 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2181
8ac33ed3
DV		 2182 intel_dp_prepare(encoder);
2183
d41f1efb
DV		 2184 /* Only ilk+ has port A */
2185 if (dport->port == PORT_A) {
2186 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2187 ironlake_edp_pll_on(intel_dp);
d41f1efb 2188 }
ab1f90f9
JN		 2189}
2190
2191static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2192{
2bd2ad64 2193 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2194 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2195 struct drm_device *dev = encoder->base.dev;
89b667f8 2196 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2197 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2198 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 2199 int pipe = intel_crtc->pipe;
bf13e81b 2200 struct edp_power_seq power_seq;
ab1f90f9 2201 u32 val;
a4fc5ed6 2202
ab1f90f9 2203 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2204
ab3c759a 2205 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2206 val = 0;
2207 if (pipe)
2208 val |= (1<<21);
2209 else
2210 val &= ~(1<<21);
2211 val |= 0x001000c4;
ab3c759a
CML		 2212 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2213 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2214 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2215
ab1f90f9
JN		 2216 mutex_unlock(&dev_priv->dpio_lock);
2217
2cac613b
ID		 2218 if (is_edp(intel_dp)) {
2219 /* init power sequencer on this pipe and port */
2220 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2221 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2222 &power_seq);
2223 }
bf13e81b 2224
ab1f90f9
JN		 2225 intel_enable_dp(encoder);
2226
e4607fcf 2227 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2228}
2229
ecff4f3b 2230static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2231{
2232 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2233 struct drm_device *dev = encoder->base.dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2235 struct intel_crtc *intel_crtc =
2236 to_intel_crtc(encoder->base.crtc);
e4607fcf 2237 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2238 int pipe = intel_crtc->pipe;
89b667f8 2239
8ac33ed3
DV		 2240 intel_dp_prepare(encoder);
2241
89b667f8 2242 /* Program Tx lane resets to default */
0980a60f 2243 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2244 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2245 DPIO_PCS_TX_LANE2_RESET |
2246 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2247 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2248 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2249 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2250 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2251 DPIO_PCS_CLK_SOFT_RESET);
2252
2253 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2254 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2255 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2256 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2257 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2258}
2259
e4a1d846
CML		 2260static void chv_pre_enable_dp(struct intel_encoder *encoder)
2261{
2262 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2263 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2264 struct drm_device *dev = encoder->base.dev;
2265 struct drm_i915_private *dev_priv = dev->dev_private;
2266 struct edp_power_seq power_seq;
2267 struct intel_crtc *intel_crtc =
2268 to_intel_crtc(encoder->base.crtc);
2269 enum dpio_channel ch = vlv_dport_to_channel(dport);
2270 int pipe = intel_crtc->pipe;
2271 int data, i;
949c1d43 2272 u32 val;
e4a1d846 2273
e4a1d846 2274 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2275
2276 /* Deassert soft data lane reset*/
97fd4d5c 2277 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2278 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2279 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2280
2281 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2282 val |= CHV_PCS_REQ_SOFTRESET_EN;
2283 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2284
2285 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2286 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2287 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2288
97fd4d5c 2289 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2290 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2291 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2292
2293 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2294 for (i = 0; i < 4; i++) {
2295 /* Set the latency optimal bit */
2296 data = (i == 1) ? 0x0 : 0x6;
2297 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2298 data << DPIO_FRC_LATENCY_SHFIT);
2299
2300 /* Set the upar bit */
2301 data = (i == 1) ? 0x0 : 0x1;
2302 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2303 data << DPIO_UPAR_SHIFT);
2304 }
2305
2306 /* Data lane stagger programming */
2307 /* FIXME: Fix up value only after power analysis */
2308
2309 mutex_unlock(&dev_priv->dpio_lock);
2310
2311 if (is_edp(intel_dp)) {
2312 /* init power sequencer on this pipe and port */
2313 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2314 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2315 &power_seq);
2316 }
2317
2318 intel_enable_dp(encoder);
2319
2320 vlv_wait_port_ready(dev_priv, dport);
2321}
2322
9197c88b
VS		 2323static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2324{
2325 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2326 struct drm_device *dev = encoder->base.dev;
2327 struct drm_i915_private *dev_priv = dev->dev_private;
2328 struct intel_crtc *intel_crtc =
2329 to_intel_crtc(encoder->base.crtc);
2330 enum dpio_channel ch = vlv_dport_to_channel(dport);
2331 enum pipe pipe = intel_crtc->pipe;
2332 u32 val;
2333
625695f8
VS		 2334 intel_dp_prepare(encoder);
2335
9197c88b
VS		 2336 mutex_lock(&dev_priv->dpio_lock);
2337
b9e5ac3c
VS		 2338 /* program left/right clock distribution */
2339 if (pipe != PIPE_B) {
2340 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2341 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2342 if (ch == DPIO_CH0)
2343 val |= CHV_BUFLEFTENA1_FORCE;
2344 if (ch == DPIO_CH1)
2345 val |= CHV_BUFRIGHTENA1_FORCE;
2346 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2347 } else {
2348 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2349 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2350 if (ch == DPIO_CH0)
2351 val |= CHV_BUFLEFTENA2_FORCE;
2352 if (ch == DPIO_CH1)
2353 val |= CHV_BUFRIGHTENA2_FORCE;
2354 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2355 }
2356
9197c88b
VS		 2357 /* program clock channel usage */
2358 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2359 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2360 if (pipe != PIPE_B)
2361 val &= ~CHV_PCS_USEDCLKCHANNEL;
2362 else
2363 val |= CHV_PCS_USEDCLKCHANNEL;
2364 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2365
2366 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2367 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2368 if (pipe != PIPE_B)
2369 val &= ~CHV_PCS_USEDCLKCHANNEL;
2370 else
2371 val |= CHV_PCS_USEDCLKCHANNEL;
2372 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2373
2374 /*
2375 * This a a bit weird since generally CL
2376 * matches the pipe, but here we need to
2377 * pick the CL based on the port.
2378 */
2379 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2380 if (pipe != PIPE_B)
2381 val &= ~CHV_CMN_USEDCLKCHANNEL;
2382 else
2383 val |= CHV_CMN_USEDCLKCHANNEL;
2384 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2385
2386 mutex_unlock(&dev_priv->dpio_lock);
2387}
2388
a4fc5ed6 2389/*
df0c237d
JB		 2390 * Native read with retry for link status and receiver capability reads for
2391 * cases where the sink may still be asleep.
9d1a1031
JN		 2392 *
2393 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2394 * supposed to retry 3 times per the spec.
a4fc5ed6 2395 */
9d1a1031
JN		 2396static ssize_t
2397intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2398 void *buffer, size_t size)
a4fc5ed6 2399{
9d1a1031
JN		 2400 ssize_t ret;
2401 int i;
61da5fab 2402
61da5fab 2403 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2404 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2405 if (ret == size)
2406 return ret;
61da5fab
JB		 2407 msleep(1);
2408 }
a4fc5ed6 2409
9d1a1031 2410 return ret;
a4fc5ed6
KP		 2411}
2412
2413/*
2414 * Fetch AUX CH registers 0x202 - 0x207 which contain
2415 * link status information
2416 */
2417static bool
93f62dad 2418intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2419{
9d1a1031
JN		 2420 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2421 DP_LANE0_1_STATUS,
2422 link_status,
2423 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2424}
2425
1100244e 2426/* These are source-specific values. */
a4fc5ed6 2427static uint8_t
1a2eb460 2428intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2429{
30add22d 2430 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2431 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2432
9576c27f 2433 if (IS_VALLEYVIEW(dev))
e2fa6fba 2434 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2435 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2436 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2437 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2438 return DP_TRAIN_VOLTAGE_SWING_1200;
2439 else
2440 return DP_TRAIN_VOLTAGE_SWING_800;
2441}
2442
2443static uint8_t
2444intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2445{
30add22d 2446 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2447 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2448
9576c27f 2449 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722
PZ		 2450 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2451 case DP_TRAIN_VOLTAGE_SWING_400:
2452 return DP_TRAIN_PRE_EMPHASIS_9_5;
2453 case DP_TRAIN_VOLTAGE_SWING_600:
2454 return DP_TRAIN_PRE_EMPHASIS_6;
2455 case DP_TRAIN_VOLTAGE_SWING_800:
2456 return DP_TRAIN_PRE_EMPHASIS_3_5;
2457 case DP_TRAIN_VOLTAGE_SWING_1200:
2458 default:
2459 return DP_TRAIN_PRE_EMPHASIS_0;
2460 }
e2fa6fba
P		 2461 } else if (IS_VALLEYVIEW(dev)) {
2462 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2463 case DP_TRAIN_VOLTAGE_SWING_400:
2464 return DP_TRAIN_PRE_EMPHASIS_9_5;
2465 case DP_TRAIN_VOLTAGE_SWING_600:
2466 return DP_TRAIN_PRE_EMPHASIS_6;
2467 case DP_TRAIN_VOLTAGE_SWING_800:
2468 return DP_TRAIN_PRE_EMPHASIS_3_5;
2469 case DP_TRAIN_VOLTAGE_SWING_1200:
2470 default:
2471 return DP_TRAIN_PRE_EMPHASIS_0;
2472 }
bc7d38a4 2473 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2474 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2475 case DP_TRAIN_VOLTAGE_SWING_400:
2476 return DP_TRAIN_PRE_EMPHASIS_6;
2477 case DP_TRAIN_VOLTAGE_SWING_600:
2478 case DP_TRAIN_VOLTAGE_SWING_800:
2479 return DP_TRAIN_PRE_EMPHASIS_3_5;
2480 default:
2481 return DP_TRAIN_PRE_EMPHASIS_0;
2482 }
2483 } else {
2484 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2485 case DP_TRAIN_VOLTAGE_SWING_400:
2486 return DP_TRAIN_PRE_EMPHASIS_6;
2487 case DP_TRAIN_VOLTAGE_SWING_600:
2488 return DP_TRAIN_PRE_EMPHASIS_6;
2489 case DP_TRAIN_VOLTAGE_SWING_800:
2490 return DP_TRAIN_PRE_EMPHASIS_3_5;
2491 case DP_TRAIN_VOLTAGE_SWING_1200:
2492 default:
2493 return DP_TRAIN_PRE_EMPHASIS_0;
2494 }
a4fc5ed6
KP		 2495 }
2496}
2497
e2fa6fba
P		 2498static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2499{
2500 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2501 struct drm_i915_private *dev_priv = dev->dev_private;
2502 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2503 struct intel_crtc *intel_crtc =
2504 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2505 unsigned long demph_reg_value, preemph_reg_value,
2506 uniqtranscale_reg_value;
2507 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2508 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2509 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2510
2511 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2512 case DP_TRAIN_PRE_EMPHASIS_0:
2513 preemph_reg_value = 0x0004000;
2514 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2515 case DP_TRAIN_VOLTAGE_SWING_400:
2516 demph_reg_value = 0x2B405555;
2517 uniqtranscale_reg_value = 0x552AB83A;
2518 break;
2519 case DP_TRAIN_VOLTAGE_SWING_600:
2520 demph_reg_value = 0x2B404040;
2521 uniqtranscale_reg_value = 0x5548B83A;
2522 break;
2523 case DP_TRAIN_VOLTAGE_SWING_800:
2524 demph_reg_value = 0x2B245555;
2525 uniqtranscale_reg_value = 0x5560B83A;
2526 break;
2527 case DP_TRAIN_VOLTAGE_SWING_1200:
2528 demph_reg_value = 0x2B405555;
2529 uniqtranscale_reg_value = 0x5598DA3A;
2530 break;
2531 default:
2532 return 0;
2533 }
2534 break;
2535 case DP_TRAIN_PRE_EMPHASIS_3_5:
2536 preemph_reg_value = 0x0002000;
2537 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2538 case DP_TRAIN_VOLTAGE_SWING_400:
2539 demph_reg_value = 0x2B404040;
2540 uniqtranscale_reg_value = 0x5552B83A;
2541 break;
2542 case DP_TRAIN_VOLTAGE_SWING_600:
2543 demph_reg_value = 0x2B404848;
2544 uniqtranscale_reg_value = 0x5580B83A;
2545 break;
2546 case DP_TRAIN_VOLTAGE_SWING_800:
2547 demph_reg_value = 0x2B404040;
2548 uniqtranscale_reg_value = 0x55ADDA3A;
2549 break;
2550 default:
2551 return 0;
2552 }
2553 break;
2554 case DP_TRAIN_PRE_EMPHASIS_6:
2555 preemph_reg_value = 0x0000000;
2556 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2557 case DP_TRAIN_VOLTAGE_SWING_400:
2558 demph_reg_value = 0x2B305555;
2559 uniqtranscale_reg_value = 0x5570B83A;
2560 break;
2561 case DP_TRAIN_VOLTAGE_SWING_600:
2562 demph_reg_value = 0x2B2B4040;
2563 uniqtranscale_reg_value = 0x55ADDA3A;
2564 break;
2565 default:
2566 return 0;
2567 }
2568 break;
2569 case DP_TRAIN_PRE_EMPHASIS_9_5:
2570 preemph_reg_value = 0x0006000;
2571 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2572 case DP_TRAIN_VOLTAGE_SWING_400:
2573 demph_reg_value = 0x1B405555;
2574 uniqtranscale_reg_value = 0x55ADDA3A;
2575 break;
2576 default:
2577 return 0;
2578 }
2579 break;
2580 default:
2581 return 0;
2582 }
2583
0980a60f 2584 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2585 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2586 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2587 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2588 uniqtranscale_reg_value);
ab3c759a
CML		 2589 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2590 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2591 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2592 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2593 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2594
2595 return 0;
2596}
2597
e4a1d846
CML		 2598static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2599{
2600 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2601 struct drm_i915_private *dev_priv = dev->dev_private;
2602 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2603 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2604 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2605 uint8_t train_set = intel_dp->train_set[0];
2606 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2607 enum pipe pipe = intel_crtc->pipe;
2608 int i;
e4a1d846
CML		 2609
2610 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2611 case DP_TRAIN_PRE_EMPHASIS_0:
2612 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2613 case DP_TRAIN_VOLTAGE_SWING_400:
2614 deemph_reg_value = 128;
2615 margin_reg_value = 52;
2616 break;
2617 case DP_TRAIN_VOLTAGE_SWING_600:
2618 deemph_reg_value = 128;
2619 margin_reg_value = 77;
2620 break;
2621 case DP_TRAIN_VOLTAGE_SWING_800:
2622 deemph_reg_value = 128;
2623 margin_reg_value = 102;
2624 break;
2625 case DP_TRAIN_VOLTAGE_SWING_1200:
2626 deemph_reg_value = 128;
2627 margin_reg_value = 154;
2628 /* FIXME extra to set for 1200 */
2629 break;
2630 default:
2631 return 0;
2632 }
2633 break;
2634 case DP_TRAIN_PRE_EMPHASIS_3_5:
2635 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2636 case DP_TRAIN_VOLTAGE_SWING_400:
2637 deemph_reg_value = 85;
2638 margin_reg_value = 78;
2639 break;
2640 case DP_TRAIN_VOLTAGE_SWING_600:
2641 deemph_reg_value = 85;
2642 margin_reg_value = 116;
2643 break;
2644 case DP_TRAIN_VOLTAGE_SWING_800:
2645 deemph_reg_value = 85;
2646 margin_reg_value = 154;
2647 break;
2648 default:
2649 return 0;
2650 }
2651 break;
2652 case DP_TRAIN_PRE_EMPHASIS_6:
2653 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2654 case DP_TRAIN_VOLTAGE_SWING_400:
2655 deemph_reg_value = 64;
2656 margin_reg_value = 104;
2657 break;
2658 case DP_TRAIN_VOLTAGE_SWING_600:
2659 deemph_reg_value = 64;
2660 margin_reg_value = 154;
2661 break;
2662 default:
2663 return 0;
2664 }
2665 break;
2666 case DP_TRAIN_PRE_EMPHASIS_9_5:
2667 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2668 case DP_TRAIN_VOLTAGE_SWING_400:
2669 deemph_reg_value = 43;
2670 margin_reg_value = 154;
2671 break;
2672 default:
2673 return 0;
2674 }
2675 break;
2676 default:
2677 return 0;
2678 }
2679
2680 mutex_lock(&dev_priv->dpio_lock);
2681
2682 /* Clear calc init */
1966e59e
VS		 2683 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2684 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2685 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2686
2687 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2688 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2689 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2690
2691 /* Program swing deemph */
f72df8db
VS		 2692 for (i = 0; i < 4; i++) {
2693 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2694 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2695 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2696 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2697 }
e4a1d846
CML		 2698
2699 /* Program swing margin */
f72df8db
VS		 2700 for (i = 0; i < 4; i++) {
2701 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 2702 val &= ~DPIO_SWING_MARGIN000_MASK;
2703 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 2704 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2705 }
e4a1d846
CML		 2706
2707 /* Disable unique transition scale */
f72df8db
VS		 2708 for (i = 0; i < 4; i++) {
2709 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2710 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2711 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2712 }
e4a1d846
CML		 2713
2714 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2715 == DP_TRAIN_PRE_EMPHASIS_0) &&
2716 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2717 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2718
2719 /*
2720 * The document said it needs to set bit 27 for ch0 and bit 26
2721 * for ch1. Might be a typo in the doc.
2722 * For now, for this unique transition scale selection, set bit
2723 * 27 for ch0 and ch1.
2724 */
f72df8db
VS		 2725 for (i = 0; i < 4; i++) {
2726 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2727 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2728 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2729 }
e4a1d846 2730
f72df8db
VS		 2731 for (i = 0; i < 4; i++) {
2732 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2733 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2734 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2735 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2736 }
e4a1d846
CML		 2737 }
2738
2739 /* Start swing calculation */
1966e59e
VS		 2740 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2741 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2742 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2743
2744 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2745 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2746 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2747
2748 /* LRC Bypass */
2749 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2750 val |= DPIO_LRC_BYPASS;
2751 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2752
2753 mutex_unlock(&dev_priv->dpio_lock);
2754
2755 return 0;
2756}
2757
a4fc5ed6 2758static void
0301b3ac
JN		 2759intel_get_adjust_train(struct intel_dp *intel_dp,
2760 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2761{
2762 uint8_t v = 0;
2763 uint8_t p = 0;
2764 int lane;
1a2eb460
KP		 2765 uint8_t voltage_max;
2766 uint8_t preemph_max;
a4fc5ed6 2767
33a34e4e 2768 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2769 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2770 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2771
2772 if (this_v > v)
2773 v = this_v;
2774 if (this_p > p)
2775 p = this_p;
2776 }
2777
1a2eb460 2778 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2779 if (v >= voltage_max)
2780 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2781
1a2eb460
KP		 2782 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2783 if (p >= preemph_max)
2784 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2785
2786 for (lane = 0; lane < 4; lane++)
33a34e4e 2787 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2788}
2789
2790static uint32_t
f0a3424e 2791intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2792{
3cf2efb1 2793 uint32_t signal_levels = 0;
a4fc5ed6 2794
3cf2efb1 2795 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2796 case DP_TRAIN_VOLTAGE_SWING_400:
2797 default:
2798 signal_levels |= DP_VOLTAGE_0_4;
2799 break;
2800 case DP_TRAIN_VOLTAGE_SWING_600:
2801 signal_levels |= DP_VOLTAGE_0_6;
2802 break;
2803 case DP_TRAIN_VOLTAGE_SWING_800:
2804 signal_levels |= DP_VOLTAGE_0_8;
2805 break;
2806 case DP_TRAIN_VOLTAGE_SWING_1200:
2807 signal_levels |= DP_VOLTAGE_1_2;
2808 break;
2809 }
3cf2efb1 2810 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2811 case DP_TRAIN_PRE_EMPHASIS_0:
2812 default:
2813 signal_levels |= DP_PRE_EMPHASIS_0;
2814 break;
2815 case DP_TRAIN_PRE_EMPHASIS_3_5:
2816 signal_levels |= DP_PRE_EMPHASIS_3_5;
2817 break;
2818 case DP_TRAIN_PRE_EMPHASIS_6:
2819 signal_levels |= DP_PRE_EMPHASIS_6;
2820 break;
2821 case DP_TRAIN_PRE_EMPHASIS_9_5:
2822 signal_levels |= DP_PRE_EMPHASIS_9_5;
2823 break;
2824 }
2825 return signal_levels;
2826}
2827
e3421a18
ZW		 2828/* Gen6's DP voltage swing and pre-emphasis control */
2829static uint32_t
2830intel_gen6_edp_signal_levels(uint8_t train_set)
2831{
3c5a62b5
YL		 2832 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2833 DP_TRAIN_PRE_EMPHASIS_MASK);
2834 switch (signal_levels) {
e3421a18 2835 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2836 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2837 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2838 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2839 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2840 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2841 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2842 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2843 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2844 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2845 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2846 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2847 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2848 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2849 default:
3c5a62b5
YL		 2850 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2851 "0x%x\n", signal_levels);
2852 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2853 }
2854}
2855
1a2eb460
KP		 2856/* Gen7's DP voltage swing and pre-emphasis control */
2857static uint32_t
2858intel_gen7_edp_signal_levels(uint8_t train_set)
2859{
2860 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2861 DP_TRAIN_PRE_EMPHASIS_MASK);
2862 switch (signal_levels) {
2863 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2864 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2865 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2866 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2867 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2868 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2869
2870 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2871 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2872 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2873 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2874
2875 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2876 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2877 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2878 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2879
2880 default:
2881 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2882 "0x%x\n", signal_levels);
2883 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2884 }
2885}
2886
d6c0d722
PZ		 2887/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2888static uint32_t
f0a3424e 2889intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2890{
d6c0d722
PZ		 2891 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2892 DP_TRAIN_PRE_EMPHASIS_MASK);
2893 switch (signal_levels) {
2894 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
c5fe6a06 2895 return DDI_BUF_TRANS_SELECT(0);
d6c0d722 2896 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
c5fe6a06 2897 return DDI_BUF_TRANS_SELECT(1);
d6c0d722 2898 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
c5fe6a06 2899 return DDI_BUF_TRANS_SELECT(2);
d6c0d722 2900 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
c5fe6a06 2901 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 2902
d6c0d722 2903 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
c5fe6a06 2904 return DDI_BUF_TRANS_SELECT(4);
d6c0d722 2905 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
c5fe6a06 2906 return DDI_BUF_TRANS_SELECT(5);
d6c0d722 2907 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
c5fe6a06 2908 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 2909
d6c0d722 2910 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
c5fe6a06 2911 return DDI_BUF_TRANS_SELECT(7);
d6c0d722 2912 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
c5fe6a06 2913 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 2914 default:
2915 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2916 "0x%x\n", signal_levels);
c5fe6a06 2917 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 2918 }
a4fc5ed6
KP		 2919}
2920
f0a3424e
PZ		 2921/* Properly updates "DP" with the correct signal levels. */
2922static void
2923intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2924{
2925 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2926 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2927 struct drm_device *dev = intel_dig_port->base.base.dev;
2928 uint32_t signal_levels, mask;
2929 uint8_t train_set = intel_dp->train_set[0];
2930
9576c27f 2931 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 2932 signal_levels = intel_hsw_signal_levels(train_set);
2933 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 2934 } else if (IS_CHERRYVIEW(dev)) {
2935 signal_levels = intel_chv_signal_levels(intel_dp);
2936 mask = 0;
e2fa6fba
P		 2937 } else if (IS_VALLEYVIEW(dev)) {
2938 signal_levels = intel_vlv_signal_levels(intel_dp);
2939 mask = 0;
bc7d38a4 2940 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2941 signal_levels = intel_gen7_edp_signal_levels(train_set);
2942 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2943 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2944 signal_levels = intel_gen6_edp_signal_levels(train_set);
2945 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2946 } else {
2947 signal_levels = intel_gen4_signal_levels(train_set);
2948 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2949 }
2950
2951 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2952
2953 *DP = (*DP & ~mask) | signal_levels;
2954}
2955
a4fc5ed6 2956static bool
ea5b213a 2957intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2958 uint32_t *DP,
58e10eb9 2959 uint8_t dp_train_pat)
a4fc5ed6 2960{
174edf1f
PZ		 2961 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2962 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2963 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2964 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2965 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2966 int ret, len;
a4fc5ed6 2967
22b8bf17 2968 if (HAS_DDI(dev)) {
3ab9c637 2969 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2970
2971 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2972 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2973 else
2974 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2975
2976 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2977 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2978 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2979 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2980
2981 break;
2982 case DP_TRAINING_PATTERN_1:
2983 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2984 break;
2985 case DP_TRAINING_PATTERN_2:
2986 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2987 break;
2988 case DP_TRAINING_PATTERN_3:
2989 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2990 break;
2991 }
174edf1f 2992 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2993
bc7d38a4 2994 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2995 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2996
2997 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2998 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2999 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 3000 break;
3001 case DP_TRAINING_PATTERN_1:
70aff66c 3002 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 3003 break;
3004 case DP_TRAINING_PATTERN_2:
70aff66c 3005 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 3006 break;
3007 case DP_TRAINING_PATTERN_3:
3008 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 3009 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 3010 break;
3011 }
3012
3013 } else {
aad3d14d
VS		 3014 if (IS_CHERRYVIEW(dev))
3015 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
3016 else
3017 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 3018
3019 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3020 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 3021 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 3022 break;
3023 case DP_TRAINING_PATTERN_1:
70aff66c 3024 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 3025 break;
3026 case DP_TRAINING_PATTERN_2:
70aff66c 3027 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 3028 break;
3029 case DP_TRAINING_PATTERN_3:
aad3d14d
VS		 3030 if (IS_CHERRYVIEW(dev)) {
3031 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
3032 } else {
3033 DRM_ERROR("DP training pattern 3 not supported\n");
3034 *DP |= DP_LINK_TRAIN_PAT_2;
3035 }
47ea7542
PZ		 3036 break;
3037 }
3038 }
3039
70aff66c 3040 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3041 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3042
2cdfe6c8
JN		 3043 buf[0] = dp_train_pat;
3044 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3045 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3046 /* don't write DP_TRAINING_LANEx_SET on disable */
3047 len = 1;
3048 } else {
3049 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3050 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3051 len = intel_dp->lane_count + 1;
47ea7542 3052 }
a4fc5ed6 3053
9d1a1031
JN		 3054 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3055 buf, len);
2cdfe6c8
JN		 3056
3057 return ret == len;
a4fc5ed6
KP		 3058}
3059
70aff66c
JN		 3060static bool
3061intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3062 uint8_t dp_train_pat)
3063{
953d22e8 3064 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3065 intel_dp_set_signal_levels(intel_dp, DP);
3066 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3067}
3068
3069static bool
3070intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3071 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3072{
3073 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3074 struct drm_device *dev = intel_dig_port->base.base.dev;
3075 struct drm_i915_private *dev_priv = dev->dev_private;
3076 int ret;
3077
3078 intel_get_adjust_train(intel_dp, link_status);
3079 intel_dp_set_signal_levels(intel_dp, DP);
3080
3081 I915_WRITE(intel_dp->output_reg, *DP);
3082 POSTING_READ(intel_dp->output_reg);
3083
9d1a1031
JN		 3084 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3085 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3086
3087 return ret == intel_dp->lane_count;
3088}
3089
3ab9c637
ID		 3090static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3091{
3092 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3093 struct drm_device *dev = intel_dig_port->base.base.dev;
3094 struct drm_i915_private *dev_priv = dev->dev_private;
3095 enum port port = intel_dig_port->port;
3096 uint32_t val;
3097
3098 if (!HAS_DDI(dev))
3099 return;
3100
3101 val = I915_READ(DP_TP_CTL(port));
3102 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3103 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3104 I915_WRITE(DP_TP_CTL(port), val);
3105
3106 /*
3107 * On PORT_A we can have only eDP in SST mode. There the only reason
3108 * we need to set idle transmission mode is to work around a HW issue
3109 * where we enable the pipe while not in idle link-training mode.
3110 * In this case there is requirement to wait for a minimum number of
3111 * idle patterns to be sent.
3112 */
3113 if (port == PORT_A)
3114 return;
3115
3116 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3117 1))
3118 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3119}
3120
33a34e4e 3121/* Enable corresponding port and start training pattern 1 */
c19b0669 3122void
33a34e4e 3123intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3124{
da63a9f2 3125 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3126 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3127 int i;
3128 uint8_t voltage;
cdb0e95b 3129 int voltage_tries, loop_tries;
ea5b213a 3130 uint32_t DP = intel_dp->DP;
6aba5b6c 3131 uint8_t link_config[2];
a4fc5ed6 3132
affa9354 3133 if (HAS_DDI(dev))
c19b0669
PZ		 3134 intel_ddi_prepare_link_retrain(encoder);
3135
3cf2efb1 3136 /* Write the link configuration data */
6aba5b6c
JN		 3137 link_config[0] = intel_dp->link_bw;
3138 link_config[1] = intel_dp->lane_count;
3139 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3140 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3141 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3142
3143 link_config[0] = 0;
3144 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3145 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3146
3147 DP |= DP_PORT_EN;
1a2eb460 3148
70aff66c
JN		 3149 /* clock recovery */
3150 if (!intel_dp_reset_link_train(intel_dp, &DP,
3151 DP_TRAINING_PATTERN_1 |
3152 DP_LINK_SCRAMBLING_DISABLE)) {
3153 DRM_ERROR("failed to enable link training\n");
3154 return;
3155 }
3156
a4fc5ed6 3157 voltage = 0xff;
cdb0e95b
KP		 3158 voltage_tries = 0;
3159 loop_tries = 0;
a4fc5ed6 3160 for (;;) {
70aff66c 3161 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3162
a7c9655f 3163 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3164 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3165 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3166 break;
93f62dad 3167 }
a4fc5ed6 3168
01916270 3169 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3170 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3171 break;
3172 }
3173
3174 /* Check to see if we've tried the max voltage */
3175 for (i = 0; i < intel_dp->lane_count; i++)
3176 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3177 break;
3b4f819d 3178 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3179 ++loop_tries;
3180 if (loop_tries == 5) {
3def84b3 3181 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3182 break;
3183 }
70aff66c
JN		 3184 intel_dp_reset_link_train(intel_dp, &DP,
3185 DP_TRAINING_PATTERN_1 |
3186 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3187 voltage_tries = 0;
3188 continue;
3189 }
a4fc5ed6 3190
3cf2efb1 3191 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3192 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3193 ++voltage_tries;
b06fbda3 3194 if (voltage_tries == 5) {
3def84b3 3195 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3196 break;
3197 }
3198 } else
3199 voltage_tries = 0;
3200 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3201
70aff66c
JN		 3202 /* Update training set as requested by target */
3203 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3204 DRM_ERROR("failed to update link training\n");
3205 break;
3206 }
a4fc5ed6
KP		 3207 }
3208
33a34e4e
JB		 3209 intel_dp->DP = DP;
3210}
3211
c19b0669 3212void
33a34e4e
JB		 3213intel_dp_complete_link_train(struct intel_dp *intel_dp)
3214{
33a34e4e 3215 bool channel_eq = false;
37f80975 3216 int tries, cr_tries;
33a34e4e 3217 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3218 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3219
3220 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3221 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3222 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3223
a4fc5ed6 3224 /* channel equalization */
70aff66c 3225 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3226 training_pattern |
70aff66c
JN		 3227 DP_LINK_SCRAMBLING_DISABLE)) {
3228 DRM_ERROR("failed to start channel equalization\n");
3229 return;
3230 }
3231
a4fc5ed6 3232 tries = 0;
37f80975 3233 cr_tries = 0;
a4fc5ed6
KP		 3234 channel_eq = false;
3235 for (;;) {
70aff66c 3236 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3237
37f80975
JB		 3238 if (cr_tries > 5) {
3239 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3240 break;
3241 }
3242
a7c9655f 3243 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3244 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3245 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3246 break;
70aff66c 3247 }
a4fc5ed6 3248
37f80975 3249 /* Make sure clock is still ok */
01916270 3250 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3251 intel_dp_start_link_train(intel_dp);
70aff66c 3252 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3253 training_pattern |
70aff66c 3254 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3255 cr_tries++;
3256 continue;
3257 }
3258
1ffdff13 3259 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3260 channel_eq = true;
3261 break;
3262 }
a4fc5ed6 3263
37f80975
JB		 3264 /* Try 5 times, then try clock recovery if that fails */
3265 if (tries > 5) {
3266 intel_dp_link_down(intel_dp);
3267 intel_dp_start_link_train(intel_dp);
70aff66c 3268 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3269 training_pattern |
70aff66c 3270 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3271 tries = 0;
3272 cr_tries++;
3273 continue;
3274 }
a4fc5ed6 3275
70aff66c
JN		 3276 /* Update training set as requested by target */
3277 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3278 DRM_ERROR("failed to update link training\n");
3279 break;
3280 }
3cf2efb1 3281 ++tries;
869184a6 3282 }
3cf2efb1 3283
3ab9c637
ID		 3284 intel_dp_set_idle_link_train(intel_dp);
3285
3286 intel_dp->DP = DP;
3287
d6c0d722 3288 if (channel_eq)
07f42258 3289 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3290
3ab9c637
ID		 3291}
3292
3293void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3294{
70aff66c 3295 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3296 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3297}
3298
3299static void
ea5b213a 3300intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3301{
da63a9f2 3302 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3303 enum port port = intel_dig_port->port;
da63a9f2 3304 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3305 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3306 struct intel_crtc *intel_crtc =
3307 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3308 uint32_t DP = intel_dp->DP;
a4fc5ed6 3309
bc76e320 3310 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3311 return;
3312
0c33d8d7 3313 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3314 return;
3315
28c97730 3316 DRM_DEBUG_KMS("\n");
32f9d658 3317
bc7d38a4 3318 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3319 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3320 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3321 } else {
aad3d14d
VS		 3322 if (IS_CHERRYVIEW(dev))
3323 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3324 else
3325 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3326 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3327 }
fe255d00 3328 POSTING_READ(intel_dp->output_reg);
5eb08b69 3329
493a7081 3330 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3331 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3332 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3333
5bddd17f
EA		 3334 /* Hardware workaround: leaving our transcoder select
3335 * set to transcoder B while it's off will prevent the
3336 * corresponding HDMI output on transcoder A.
3337 *
3338 * Combine this with another hardware workaround:
3339 * transcoder select bit can only be cleared while the
3340 * port is enabled.
3341 */
3342 DP &= ~DP_PIPEB_SELECT;
3343 I915_WRITE(intel_dp->output_reg, DP);
3344
3345 /* Changes to enable or select take place the vblank
3346 * after being written.
3347 */
ff50afe9
DV		 3348 if (WARN_ON(crtc == NULL)) {
3349 /* We should never try to disable a port without a crtc
3350 * attached. For paranoia keep the code around for a
3351 * bit. */
31acbcc4
CW		 3352 POSTING_READ(intel_dp->output_reg);
3353 msleep(50);
3354 } else
ab527efc 3355 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3356 }
3357
832afda6 3358 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3359 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3360 POSTING_READ(intel_dp->output_reg);
f01eca2e 3361 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3362}
3363
26d61aad
KP		 3364static bool
3365intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3366{
a031d709
RV		 3367 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3368 struct drm_device *dev = dig_port->base.base.dev;
3369 struct drm_i915_private *dev_priv = dev->dev_private;
3370
9d1a1031
JN		 3371 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3372 sizeof(intel_dp->dpcd)) < 0)
edb39244 3373 return false; /* aux transfer failed */
92fd8fd1 3374
a8e98153 3375 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3376
edb39244
AJ		 3377 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3378 return false; /* DPCD not present */
3379
2293bb5c
SK		 3380 /* Check if the panel supports PSR */
3381 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3382 if (is_edp(intel_dp)) {
9d1a1031
JN		 3383 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3384 intel_dp->psr_dpcd,
3385 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3386 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3387 dev_priv->psr.sink_support = true;
50003939 3388 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3389 }
50003939
JN		 3390 }
3391
06ea66b6
TP		 3392 /* Training Pattern 3 support */
3393 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3394 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3395 intel_dp->use_tps3 = true;
3396 DRM_DEBUG_KMS("Displayport TPS3 supported");
3397 } else
3398 intel_dp->use_tps3 = false;
3399
edb39244
AJ		 3400 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3401 DP_DWN_STRM_PORT_PRESENT))
3402 return true; /* native DP sink */
3403
3404 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3405 return true; /* no per-port downstream info */
3406
9d1a1031
JN		 3407 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3408 intel_dp->downstream_ports,
3409 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3410 return false; /* downstream port status fetch failed */
3411
3412 return true;
92fd8fd1
KP		 3413}
3414
0d198328
AJ		 3415static void
3416intel_dp_probe_oui(struct intel_dp *intel_dp)
3417{
3418 u8 buf[3];
3419
3420 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3421 return;
3422
24f3e092 3423 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3424
9d1a1031 3425 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3426 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3427 buf[0], buf[1], buf[2]);
3428
9d1a1031 3429 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3430 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3431 buf[0], buf[1], buf[2]);
351cfc34 3432
1e0560e0 3433 intel_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3434}
3435
0e32b39c
DA		 3436static bool
3437intel_dp_probe_mst(struct intel_dp *intel_dp)
3438{
3439 u8 buf[1];
3440
3441 if (!intel_dp->can_mst)
3442 return false;
3443
3444 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3445 return false;
3446
d337a341 3447 intel_edp_panel_vdd_on(intel_dp);
0e32b39c
DA		 3448 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3449 if (buf[0] & DP_MST_CAP) {
3450 DRM_DEBUG_KMS("Sink is MST capable\n");
3451 intel_dp->is_mst = true;
3452 } else {
3453 DRM_DEBUG_KMS("Sink is not MST capable\n");
3454 intel_dp->is_mst = false;
3455 }
3456 }
1e0560e0 3457 intel_edp_panel_vdd_off(intel_dp, false);
0e32b39c
DA		 3458
3459 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3460 return intel_dp->is_mst;
3461}
3462
d2e216d0
RV		 3463int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3464{
3465 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3466 struct drm_device *dev = intel_dig_port->base.base.dev;
3467 struct intel_crtc *intel_crtc =
3468 to_intel_crtc(intel_dig_port->base.base.crtc);
3469 u8 buf[1];
3470
9d1a1031 3471 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3472 return -EAGAIN;
3473
3474 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3475 return -ENOTTY;
3476
9d1a1031
JN		 3477 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3478 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3479 return -EAGAIN;
3480
3481 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3482 intel_wait_for_vblank(dev, intel_crtc->pipe);
3483 intel_wait_for_vblank(dev, intel_crtc->pipe);
3484
9d1a1031 3485 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3486 return -EAGAIN;
3487
9d1a1031 3488 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3489 return 0;
3490}
3491
a60f0e38
JB		 3492static bool
3493intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3494{
9d1a1031
JN		 3495 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3496 DP_DEVICE_SERVICE_IRQ_VECTOR,
3497 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3498}
3499
0e32b39c
DA		 3500static bool
3501intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3502{
3503 int ret;
3504
3505 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3506 DP_SINK_COUNT_ESI,
3507 sink_irq_vector, 14);
3508 if (ret != 14)
3509 return false;
3510
3511 return true;
3512}
3513
a60f0e38
JB		 3514static void
3515intel_dp_handle_test_request(struct intel_dp *intel_dp)
3516{
3517 /* NAK by default */
9d1a1031 3518 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3519}
3520
0e32b39c
DA		 3521static int
3522intel_dp_check_mst_status(struct intel_dp *intel_dp)
3523{
3524 bool bret;
3525
3526 if (intel_dp->is_mst) {
3527 u8 esi[16] = { 0 };
3528 int ret = 0;
3529 int retry;
3530 bool handled;
3531 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3532go_again:
3533 if (bret == true) {
3534
3535 /* check link status - esi[10] = 0x200c */
3536 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3537 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3538 intel_dp_start_link_train(intel_dp);
3539 intel_dp_complete_link_train(intel_dp);
3540 intel_dp_stop_link_train(intel_dp);
3541 }
3542
3543 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3544 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3545
3546 if (handled) {
3547 for (retry = 0; retry < 3; retry++) {
3548 int wret;
3549 wret = drm_dp_dpcd_write(&intel_dp->aux,
3550 DP_SINK_COUNT_ESI+1,
3551 &esi[1], 3);
3552 if (wret == 3) {
3553 break;
3554 }
3555 }
3556
3557 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3558 if (bret == true) {
3559 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3560 goto go_again;
3561 }
3562 } else
3563 ret = 0;
3564
3565 return ret;
3566 } else {
3567 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3568 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3569 intel_dp->is_mst = false;
3570 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3571 /* send a hotplug event */
3572 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3573 }
3574 }
3575 return -EINVAL;
3576}
3577
a4fc5ed6
KP		 3578/*
3579 * According to DP spec
3580 * 5.1.2:
3581 * 1. Read DPCD
3582 * 2. Configure link according to Receiver Capabilities
3583 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3584 * 4. Check link status on receipt of hot-plug interrupt
3585 */
00c09d70 3586void
ea5b213a 3587intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3588{
5b215bcf 3589 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3590 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3591 u8 sink_irq_vector;
93f62dad 3592 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3593
5b215bcf
DA		 3594 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3595
da63a9f2 3596 if (!intel_encoder->connectors_active)
d2b996ac 3597 return;
59cd09e1 3598
da63a9f2 3599 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3600 return;
3601
1a125d8a
ID		 3602 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3603 return;
3604
92fd8fd1 3605 /* Try to read receiver status if the link appears to be up */
93f62dad 3606 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3607 return;
3608 }
3609
92fd8fd1 3610 /* Now read the DPCD to see if it's actually running */
26d61aad 3611 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3612 return;
3613 }
3614
a60f0e38
JB		 3615 /* Try to read the source of the interrupt */
3616 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3617 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3618 /* Clear interrupt source */
9d1a1031
JN		 3619 drm_dp_dpcd_writeb(&intel_dp->aux,
3620 DP_DEVICE_SERVICE_IRQ_VECTOR,
3621 sink_irq_vector);
a60f0e38
JB		 3622
3623 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3624 intel_dp_handle_test_request(intel_dp);
3625 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3626 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3627 }
3628
1ffdff13 3629 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3630 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3631 intel_encoder->base.name);
33a34e4e
JB		 3632 intel_dp_start_link_train(intel_dp);
3633 intel_dp_complete_link_train(intel_dp);
3ab9c637 3634 intel_dp_stop_link_train(intel_dp);
33a34e4e 3635 }
a4fc5ed6 3636}
a4fc5ed6 3637
caf9ab24 3638/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3639static enum drm_connector_status
26d61aad 3640intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3641{
caf9ab24 3642 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3643 uint8_t type;
3644
3645 if (!intel_dp_get_dpcd(intel_dp))
3646 return connector_status_disconnected;
3647
3648 /* if there's no downstream port, we're done */
3649 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3650 return connector_status_connected;
caf9ab24
AJ		 3651
3652 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3653 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3654 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3655 uint8_t reg;
9d1a1031
JN		 3656
3657 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3658 &reg, 1) < 0)
caf9ab24 3659 return connector_status_unknown;
9d1a1031 3660
23235177
AJ		 3661 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3662 : connector_status_disconnected;
caf9ab24
AJ		 3663 }
3664
3665 /* If no HPD, poke DDC gently */
0b99836f 3666 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3667 return connector_status_connected;
caf9ab24
AJ		 3668
3669 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3670 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3671 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3672 if (type == DP_DS_PORT_TYPE_VGA ||
3673 type == DP_DS_PORT_TYPE_NON_EDID)
3674 return connector_status_unknown;
3675 } else {
3676 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3677 DP_DWN_STRM_PORT_TYPE_MASK;
3678 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3679 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3680 return connector_status_unknown;
3681 }
caf9ab24
AJ		 3682
3683 /* Anything else is out of spec, warn and ignore */
3684 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3685 return connector_status_disconnected;
71ba9000
AJ		 3686}
3687
5eb08b69 3688static enum drm_connector_status
a9756bb5 3689ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3690{
30add22d 3691 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3692 struct drm_i915_private *dev_priv = dev->dev_private;
3693 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3694 enum drm_connector_status status;
3695
fe16d949
CW		 3696 /* Can't disconnect eDP, but you can close the lid... */
3697 if (is_edp(intel_dp)) {
30add22d 3698 status = intel_panel_detect(dev);
fe16d949
CW		 3699 if (status == connector_status_unknown)
3700 status = connector_status_connected;
3701 return status;
3702 }
01cb9ea6 3703
1b469639
DL		 3704 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3705 return connector_status_disconnected;
3706
26d61aad 3707 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3708}
3709
a4fc5ed6 3710static enum drm_connector_status
a9756bb5 3711g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3712{
30add22d 3713 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3714 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3715 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3716 uint32_t bit;
5eb08b69 3717
35aad75f
JB		 3718 /* Can't disconnect eDP, but you can close the lid... */
3719 if (is_edp(intel_dp)) {
3720 enum drm_connector_status status;
3721
3722 status = intel_panel_detect(dev);
3723 if (status == connector_status_unknown)
3724 status = connector_status_connected;
3725 return status;
3726 }
3727
232a6ee9
TP		 3728 if (IS_VALLEYVIEW(dev)) {
3729 switch (intel_dig_port->port) {
3730 case PORT_B:
3731 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3732 break;
3733 case PORT_C:
3734 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3735 break;
3736 case PORT_D:
3737 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3738 break;
3739 default:
3740 return connector_status_unknown;
3741 }
3742 } else {
3743 switch (intel_dig_port->port) {
3744 case PORT_B:
3745 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3746 break;
3747 case PORT_C:
3748 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3749 break;
3750 case PORT_D:
3751 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3752 break;
3753 default:
3754 return connector_status_unknown;
3755 }
a4fc5ed6
KP		 3756 }
3757
10f76a38 3758 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3759 return connector_status_disconnected;
3760
26d61aad 3761 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3762}
3763
8c241fef
KP		 3764static struct edid *
3765intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3766{
9cd300e0 3767 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3768
9cd300e0
JN		 3769 /* use cached edid if we have one */
3770 if (intel_connector->edid) {
9cd300e0
JN		 3771 /* invalid edid */
3772 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3773 return NULL;
3774
55e9edeb 3775 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3776 }
8c241fef 3777
9cd300e0 3778 return drm_get_edid(connector, adapter);
8c241fef
KP		 3779}
3780
3781static int
3782intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3783{
9cd300e0 3784 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3785
9cd300e0
JN		 3786 /* use cached edid if we have one */
3787 if (intel_connector->edid) {
3788 /* invalid edid */
3789 if (IS_ERR(intel_connector->edid))
3790 return 0;
3791
3792 return intel_connector_update_modes(connector,
3793 intel_connector->edid);
d6f24d0f
JB		 3794 }
3795
9cd300e0 3796 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3797}
3798
a9756bb5
ZW		 3799static enum drm_connector_status
3800intel_dp_detect(struct drm_connector *connector, bool force)
3801{
3802 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3803 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3804 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3805 struct drm_device *dev = connector->dev;
c8c8fb33 3806 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3807 enum drm_connector_status status;
671dedd2 3808 enum intel_display_power_domain power_domain;
a9756bb5 3809 struct edid *edid = NULL;
0e32b39c 3810 bool ret;
a9756bb5 3811
671dedd2
ID		 3812 power_domain = intel_display_port_power_domain(intel_encoder);
3813 intel_display_power_get(dev_priv, power_domain);
3814
164c8598 3815 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 3816 connector->base.id, connector->name);
164c8598 3817
0e32b39c
DA		 3818 if (intel_dp->is_mst) {
3819 /* MST devices are disconnected from a monitor POV */
3820 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3821 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3822 status = connector_status_disconnected;
3823 goto out;
3824 }
3825
a9756bb5
ZW		 3826 intel_dp->has_audio = false;
3827
3828 if (HAS_PCH_SPLIT(dev))
3829 status = ironlake_dp_detect(intel_dp);
3830 else
3831 status = g4x_dp_detect(intel_dp);
1b9be9d0 3832
a9756bb5 3833 if (status != connector_status_connected)
c8c8fb33 3834 goto out;
a9756bb5 3835
0d198328
AJ		 3836 intel_dp_probe_oui(intel_dp);
3837
0e32b39c
DA		 3838 ret = intel_dp_probe_mst(intel_dp);
3839 if (ret) {
3840 /* if we are in MST mode then this connector
3841 won't appear connected or have anything with EDID on it */
3842 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3843 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3844 status = connector_status_disconnected;
3845 goto out;
3846 }
3847
c3e5f67b
DV		 3848 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3849 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3850 } else {
0b99836f 3851 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3852 if (edid) {
3853 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3854 kfree(edid);
3855 }
a9756bb5
ZW		 3856 }
3857
d63885da
PZ		 3858 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3859 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3860 status = connector_status_connected;
3861
3862out:
671dedd2 3863 intel_display_power_put(dev_priv, power_domain);
c8c8fb33 3864 return status;
a4fc5ed6
KP		 3865}
3866
3867static int intel_dp_get_modes(struct drm_connector *connector)
3868{
df0e9248 3869 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3870 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3871 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3872 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3873 struct drm_device *dev = connector->dev;
671dedd2
ID		 3874 struct drm_i915_private *dev_priv = dev->dev_private;
3875 enum intel_display_power_domain power_domain;
32f9d658 3876 int ret;
a4fc5ed6
KP		 3877
3878 /* We should parse the EDID data and find out if it has an audio sink
3879 */
3880
671dedd2
ID		 3881 power_domain = intel_display_port_power_domain(intel_encoder);
3882 intel_display_power_get(dev_priv, power_domain);
3883
0b99836f 3884 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3885 intel_display_power_put(dev_priv, power_domain);
f8779fda 3886 if (ret)
32f9d658
ZW		 3887 return ret;
3888
f8779fda 3889 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3890 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3891 struct drm_display_mode *mode;
dd06f90e
JN		 3892 mode = drm_mode_duplicate(dev,
3893 intel_connector->panel.fixed_mode);
f8779fda 3894 if (mode) {
32f9d658
ZW		 3895 drm_mode_probed_add(connector, mode);
3896 return 1;
3897 }
3898 }
3899 return 0;
a4fc5ed6
KP		 3900}
3901
1aad7ac0
CW		 3902static bool
3903intel_dp_detect_audio(struct drm_connector *connector)
3904{
3905 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3906 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3907 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3908 struct drm_device *dev = connector->dev;
3909 struct drm_i915_private *dev_priv = dev->dev_private;
3910 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3911 struct edid *edid;
3912 bool has_audio = false;
3913
671dedd2
ID		 3914 power_domain = intel_display_port_power_domain(intel_encoder);
3915 intel_display_power_get(dev_priv, power_domain);
3916
0b99836f 3917 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3918 if (edid) {
3919 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3920 kfree(edid);
3921 }
3922
671dedd2
ID		 3923 intel_display_power_put(dev_priv, power_domain);
3924
1aad7ac0
CW		 3925 return has_audio;
3926}
3927
f684960e
CW		 3928static int
3929intel_dp_set_property(struct drm_connector *connector,
3930 struct drm_property *property,
3931 uint64_t val)
3932{
e953fd7b 3933 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3934 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3935 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3936 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3937 int ret;
3938
662595df 3939 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3940 if (ret)
3941 return ret;
3942
3f43c48d 3943 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3944 int i = val;
3945 bool has_audio;
3946
3947 if (i == intel_dp->force_audio)
f684960e
CW		 3948 return 0;
3949
1aad7ac0 3950 intel_dp->force_audio = i;
f684960e 3951
c3e5f67b 3952 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3953 has_audio = intel_dp_detect_audio(connector);
3954 else
c3e5f67b 3955 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3956
3957 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3958 return 0;
3959
1aad7ac0 3960 intel_dp->has_audio = has_audio;
f684960e
CW		 3961 goto done;
3962 }
3963
e953fd7b 3964 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3965 bool old_auto = intel_dp->color_range_auto;
3966 uint32_t old_range = intel_dp->color_range;
3967
55bc60db
VS		 3968 switch (val) {
3969 case INTEL_BROADCAST_RGB_AUTO:
3970 intel_dp->color_range_auto = true;
3971 break;
3972 case INTEL_BROADCAST_RGB_FULL:
3973 intel_dp->color_range_auto = false;
3974 intel_dp->color_range = 0;
3975 break;
3976 case INTEL_BROADCAST_RGB_LIMITED:
3977 intel_dp->color_range_auto = false;
3978 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3979 break;
3980 default:
3981 return -EINVAL;
3982 }
ae4edb80
DV		 3983
3984 if (old_auto == intel_dp->color_range_auto &&
3985 old_range == intel_dp->color_range)
3986 return 0;
3987
e953fd7b
CW		 3988 goto done;
3989 }
3990
53b41837
YN		 3991 if (is_edp(intel_dp) &&
3992 property == connector->dev->mode_config.scaling_mode_property) {
3993 if (val == DRM_MODE_SCALE_NONE) {
3994 DRM_DEBUG_KMS("no scaling not supported\n");
3995 return -EINVAL;
3996 }
3997
3998 if (intel_connector->panel.fitting_mode == val) {
3999 /* the eDP scaling property is not changed */
4000 return 0;
4001 }
4002 intel_connector->panel.fitting_mode = val;
4003
4004 goto done;
4005 }
4006
f684960e
CW		 4007 return -EINVAL;
4008
4009done:
c0c36b94
CW		 4010 if (intel_encoder->base.crtc)
4011 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4012
4013 return 0;
4014}
4015
a4fc5ed6 4016static void
73845adf 4017intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4018{
1d508706 4019 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4020
9cd300e0
JN		 4021 if (!IS_ERR_OR_NULL(intel_connector->edid))
4022 kfree(intel_connector->edid);
4023
acd8db10
PZ		 4024 /* Can't call is_edp() since the encoder may have been destroyed
4025 * already. */
4026 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4027 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4028
a4fc5ed6 4029 drm_connector_cleanup(connector);
55f78c43 4030 kfree(connector);
a4fc5ed6
KP		 4031}
4032
00c09d70 4033void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4034{
da63a9f2
PZ		 4035 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4036 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 4037 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 4038
4f71d0cb 4039 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4040 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4041 drm_encoder_cleanup(encoder);
bd943159
KP		 4042 if (is_edp(intel_dp)) {
4043 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4044 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4045 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4046 drm_modeset_unlock(&dev->mode_config.connection_mutex);
01527b31
CT		 4047 if (intel_dp->edp_notifier.notifier_call) {
4048 unregister_reboot_notifier(&intel_dp->edp_notifier);
4049 intel_dp->edp_notifier.notifier_call = NULL;
4050 }
bd943159 4051 }
da63a9f2 4052 kfree(intel_dig_port);
24d05927
DV		 4053}
4054
07f9cd0b
ID		 4055static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4056{
4057 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4058
4059 if (!is_edp(intel_dp))
4060 return;
4061
4062 edp_panel_vdd_off_sync(intel_dp);
4063}
4064
6d93c0c4
ID		 4065static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4066{
4067 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4068}
4069
a4fc5ed6 4070static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4071 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 4072 .detect = intel_dp_detect,
4073 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4074 .set_property = intel_dp_set_property,
73845adf 4075 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4076};
4077
4078static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4079 .get_modes = intel_dp_get_modes,
4080 .mode_valid = intel_dp_mode_valid,
df0e9248 4081 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4082};
4083
a4fc5ed6 4084static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4085 .reset = intel_dp_encoder_reset,
24d05927 4086 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4087};
4088
0e32b39c 4089void
21d40d37 4090intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4091{
0e32b39c 4092 return;
c8110e52 4093}
6207937d 4094
13cf5504
DA		 4095bool
4096intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4097{
4098 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4099 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4100 struct drm_device *dev = intel_dig_port->base.base.dev;
4101 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4102 enum intel_display_power_domain power_domain;
4103 bool ret = true;
4104
0e32b39c
DA		 4105 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4106 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4107
26fbb774
VS		 4108 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4109 port_name(intel_dig_port->port),
0e32b39c 4110 long_hpd ? "long" : "short");
13cf5504 4111
1c767b33
ID		 4112 power_domain = intel_display_port_power_domain(intel_encoder);
4113 intel_display_power_get(dev_priv, power_domain);
4114
0e32b39c
DA		 4115 if (long_hpd) {
4116 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4117 goto mst_fail;
4118
4119 if (!intel_dp_get_dpcd(intel_dp)) {
4120 goto mst_fail;
4121 }
4122
4123 intel_dp_probe_oui(intel_dp);
4124
4125 if (!intel_dp_probe_mst(intel_dp))
4126 goto mst_fail;
4127
4128 } else {
4129 if (intel_dp->is_mst) {
1c767b33 4130 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4131 goto mst_fail;
4132 }
4133
4134 if (!intel_dp->is_mst) {
4135 /*
4136 * we'll check the link status via the normal hot plug path later -
4137 * but for short hpds we should check it now
4138 */
5b215bcf 4139 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4140 intel_dp_check_link_status(intel_dp);
5b215bcf 4141 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4142 }
4143 }
1c767b33
ID		 4144 ret = false;
4145 goto put_power;
0e32b39c
DA		 4146mst_fail:
4147 /* if we were in MST mode, and device is not there get out of MST mode */
4148 if (intel_dp->is_mst) {
4149 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4150 intel_dp->is_mst = false;
4151 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4152 }
1c767b33
ID		 4153put_power:
4154 intel_display_power_put(dev_priv, power_domain);
4155
4156 return ret;
13cf5504
DA		 4157}
4158
e3421a18
ZW		 4159/* Return which DP Port should be selected for Transcoder DP control */
4160int
0206e353 4161intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4162{
4163 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4164 struct intel_encoder *intel_encoder;
4165 struct intel_dp *intel_dp;
e3421a18 4166
fa90ecef
PZ		 4167 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4168 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4169
fa90ecef
PZ		 4170 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4171 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4172 return intel_dp->output_reg;
e3421a18 4173 }
ea5b213a 4174
e3421a18
ZW		 4175 return -1;
4176}
4177
36e83a18 4178/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4179bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4180{
4181 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4182 union child_device_config *p_child;
36e83a18 4183 int i;
5d8a7752
VS		 4184 static const short port_mapping[] = {
4185 [PORT_B] = PORT_IDPB,
4186 [PORT_C] = PORT_IDPC,
4187 [PORT_D] = PORT_IDPD,
4188 };
36e83a18 4189
3b32a35b
VS		 4190 if (port == PORT_A)
4191 return true;
4192
41aa3448 4193 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4194 return false;
4195
41aa3448
RV		 4196 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4197 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4198
5d8a7752 4199 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4200 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4201 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4202 return true;
4203 }
4204 return false;
4205}
4206
0e32b39c 4207void
f684960e
CW		 4208intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4209{
53b41837
YN		 4210 struct intel_connector *intel_connector = to_intel_connector(connector);
4211
3f43c48d 4212 intel_attach_force_audio_property(connector);
e953fd7b 4213 intel_attach_broadcast_rgb_property(connector);
55bc60db 4214 intel_dp->color_range_auto = true;
53b41837
YN		 4215
4216 if (is_edp(intel_dp)) {
4217 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4218 drm_object_attach_property(
4219 &connector->base,
53b41837 4220 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4221 DRM_MODE_SCALE_ASPECT);
4222 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4223 }
f684960e
CW		 4224}
4225
dada1a9f
ID		 4226static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4227{
4228 intel_dp->last_power_cycle = jiffies;
4229 intel_dp->last_power_on = jiffies;
4230 intel_dp->last_backlight_off = jiffies;
4231}
4232
67a54566
DV		 4233static void
4234intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4235 struct intel_dp *intel_dp,
4236 struct edp_power_seq *out)
67a54566
DV		 4237{
4238 struct drm_i915_private *dev_priv = dev->dev_private;
4239 struct edp_power_seq cur, vbt, spec, final;
4240 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4241 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 4242
4243 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4244 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4245 pp_on_reg = PCH_PP_ON_DELAYS;
4246 pp_off_reg = PCH_PP_OFF_DELAYS;
4247 pp_div_reg = PCH_PP_DIVISOR;
4248 } else {
bf13e81b
JN		 4249 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4250
4251 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4252 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4253 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4254 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4255 }
67a54566
DV		 4256
4257 /* Workaround: Need to write PP_CONTROL with the unlock key as
4258 * the very first thing. */
453c5420 4259 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4260 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4261
453c5420
JB		 4262 pp_on = I915_READ(pp_on_reg);
4263 pp_off = I915_READ(pp_off_reg);
4264 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4265
4266 /* Pull timing values out of registers */
4267 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4268 PANEL_POWER_UP_DELAY_SHIFT;
4269
4270 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4271 PANEL_LIGHT_ON_DELAY_SHIFT;
4272
4273 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4274 PANEL_LIGHT_OFF_DELAY_SHIFT;
4275
4276 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4277 PANEL_POWER_DOWN_DELAY_SHIFT;
4278
4279 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4280 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4281
4282 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4283 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4284
41aa3448 4285 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4286
4287 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4288 * our hw here, which are all in 100usec. */
4289 spec.t1_t3 = 210 * 10;
4290 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4291 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4292 spec.t10 = 500 * 10;
4293 /* This one is special and actually in units of 100ms, but zero
4294 * based in the hw (so we need to add 100 ms). But the sw vbt
4295 * table multiplies it with 1000 to make it in units of 100usec,
4296 * too. */
4297 spec.t11_t12 = (510 + 100) * 10;
4298
4299 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4300 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4301
4302 /* Use the max of the register settings and vbt. If both are
4303 * unset, fall back to the spec limits. */
4304#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4305 spec.field : \
4306 max(cur.field, vbt.field))
4307 assign_final(t1_t3);
4308 assign_final(t8);
4309 assign_final(t9);
4310 assign_final(t10);
4311 assign_final(t11_t12);
4312#undef assign_final
4313
4314#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4315 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4316 intel_dp->backlight_on_delay = get_delay(t8);
4317 intel_dp->backlight_off_delay = get_delay(t9);
4318 intel_dp->panel_power_down_delay = get_delay(t10);
4319 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4320#undef get_delay
4321
f30d26e4
JN		 4322 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4323 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4324 intel_dp->panel_power_cycle_delay);
4325
4326 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4327 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4328
4329 if (out)
4330 *out = final;
4331}
4332
4333static void
4334intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4335 struct intel_dp *intel_dp,
4336 struct edp_power_seq *seq)
4337{
4338 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4339 u32 pp_on, pp_off, pp_div, port_sel = 0;
4340 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4341 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4342 enum port port = dp_to_dig_port(intel_dp)->port;
453c5420
JB		 4343
4344 if (HAS_PCH_SPLIT(dev)) {
4345 pp_on_reg = PCH_PP_ON_DELAYS;
4346 pp_off_reg = PCH_PP_OFF_DELAYS;
4347 pp_div_reg = PCH_PP_DIVISOR;
4348 } else {
bf13e81b
JN		 4349 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4350
4351 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4352 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4353 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4354 }
4355
b2f19d1a
PZ		 4356 /*
4357 * And finally store the new values in the power sequencer. The
4358 * backlight delays are set to 1 because we do manual waits on them. For
4359 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4360 * we'll end up waiting for the backlight off delay twice: once when we
4361 * do the manual sleep, and once when we disable the panel and wait for
4362 * the PP_STATUS bit to become zero.
4363 */
f30d26e4 4364 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4365 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4366 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4367 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4368 /* Compute the divisor for the pp clock, simply match the Bspec
4369 * formula. */
453c5420 4370 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4371 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4372 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4373
4374 /* Haswell doesn't have any port selection bits for the panel
4375 * power sequencer any more. */
bc7d38a4 4376 if (IS_VALLEYVIEW(dev)) {
ad933b56 4377 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4378 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4379 if (port == PORT_A)
a24c144c 4380 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4381 else
a24c144c 4382 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4383 }
4384
453c5420
JB		 4385 pp_on |= port_sel;
4386
4387 I915_WRITE(pp_on_reg, pp_on);
4388 I915_WRITE(pp_off_reg, pp_off);
4389 I915_WRITE(pp_div_reg, pp_div);
67a54566 4390
67a54566 4391 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4392 I915_READ(pp_on_reg),
4393 I915_READ(pp_off_reg),
4394 I915_READ(pp_div_reg));
f684960e
CW		 4395}
4396
439d7ac0
PB		 4397void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4398{
4399 struct drm_i915_private *dev_priv = dev->dev_private;
4400 struct intel_encoder *encoder;
4401 struct intel_dp *intel_dp = NULL;
4402 struct intel_crtc_config *config = NULL;
4403 struct intel_crtc *intel_crtc = NULL;
4404 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4405 u32 reg, val;
4406 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4407
4408 if (refresh_rate <= 0) {
4409 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4410 return;
4411 }
4412
4413 if (intel_connector == NULL) {
4414 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4415 return;
4416 }
4417
1fcc9d1c
DV		 4418 /*
4419 * FIXME: This needs proper synchronization with psr state. But really
4420 * hard to tell without seeing the user of this function of this code.
4421 * Check locking and ordering once that lands.
4422 */
439d7ac0
PB		 4423 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4424 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4425 return;
4426 }
4427
4428 encoder = intel_attached_encoder(&intel_connector->base);
4429 intel_dp = enc_to_intel_dp(&encoder->base);
4430 intel_crtc = encoder->new_crtc;
4431
4432 if (!intel_crtc) {
4433 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4434 return;
4435 }
4436
4437 config = &intel_crtc->config;
4438
4439 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4440 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4441 return;
4442 }
4443
4444 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4445 index = DRRS_LOW_RR;
4446
4447 if (index == intel_dp->drrs_state.refresh_rate_type) {
4448 DRM_DEBUG_KMS(
4449 "DRRS requested for previously set RR...ignoring\n");
4450 return;
4451 }
4452
4453 if (!intel_crtc->active) {
4454 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4455 return;
4456 }
4457
4458 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4459 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4460 val = I915_READ(reg);
4461 if (index > DRRS_HIGH_RR) {
4462 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4463 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4464 } else {
4465 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4466 }
4467 I915_WRITE(reg, val);
4468 }
4469
4470 /*
4471 * mutex taken to ensure that there is no race between differnt
4472 * drrs calls trying to update refresh rate. This scenario may occur
4473 * in future when idleness detection based DRRS in kernel and
4474 * possible calls from user space to set differnt RR are made.
4475 */
4476
4477 mutex_lock(&intel_dp->drrs_state.mutex);
4478
4479 intel_dp->drrs_state.refresh_rate_type = index;
4480
4481 mutex_unlock(&intel_dp->drrs_state.mutex);
4482
4483 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4484}
4485
4f9db5b5
PB		 4486static struct drm_display_mode *
4487intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4488 struct intel_connector *intel_connector,
4489 struct drm_display_mode *fixed_mode)
4490{
4491 struct drm_connector *connector = &intel_connector->base;
4492 struct intel_dp *intel_dp = &intel_dig_port->dp;
4493 struct drm_device *dev = intel_dig_port->base.base.dev;
4494 struct drm_i915_private *dev_priv = dev->dev_private;
4495 struct drm_display_mode *downclock_mode = NULL;
4496
4497 if (INTEL_INFO(dev)->gen <= 6) {
4498 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4499 return NULL;
4500 }
4501
4502 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4503 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4504 return NULL;
4505 }
4506
4507 downclock_mode = intel_find_panel_downclock
4508 (dev, fixed_mode, connector);
4509
4510 if (!downclock_mode) {
4079b8d1 4511 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4512 return NULL;
4513 }
4514
439d7ac0
PB		 4515 dev_priv->drrs.connector = intel_connector;
4516
4517 mutex_init(&intel_dp->drrs_state.mutex);
4518
4f9db5b5
PB		 4519 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4520
4521 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4522 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4523 return downclock_mode;
4524}
4525
aba86890
ID		 4526void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4527{
4528 struct drm_device *dev = intel_encoder->base.dev;
4529 struct drm_i915_private *dev_priv = dev->dev_private;
4530 struct intel_dp *intel_dp;
4531 enum intel_display_power_domain power_domain;
4532
4533 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4534 return;
4535
4536 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4537 if (!edp_have_panel_vdd(intel_dp))
4538 return;
4539 /*
4540 * The VDD bit needs a power domain reference, so if the bit is
4541 * already enabled when we boot or resume, grab this reference and
4542 * schedule a vdd off, so we don't hold on to the reference
4543 * indefinitely.
4544 */
4545 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4546 power_domain = intel_display_port_power_domain(intel_encoder);
4547 intel_display_power_get(dev_priv, power_domain);
4548
4549 edp_panel_vdd_schedule_off(intel_dp);
4550}
4551
ed92f0b2 4552static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4553 struct intel_connector *intel_connector,
4554 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4555{
4556 struct drm_connector *connector = &intel_connector->base;
4557 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4558 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4559 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4560 struct drm_i915_private *dev_priv = dev->dev_private;
4561 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4562 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4563 bool has_dpcd;
4564 struct drm_display_mode *scan;
4565 struct edid *edid;
4566
4f9db5b5
PB		 4567 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4568
ed92f0b2
PZ		 4569 if (!is_edp(intel_dp))
4570 return true;
4571
aba86890 4572 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 4573
ed92f0b2 4574 /* Cache DPCD and EDID for edp. */
24f3e092 4575 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4576 has_dpcd = intel_dp_get_dpcd(intel_dp);
1e0560e0 4577 intel_edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4578
4579 if (has_dpcd) {
4580 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4581 dev_priv->no_aux_handshake =
4582 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4583 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4584 } else {
4585 /* if this fails, presume the device is a ghost */
4586 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4587 return false;
4588 }
4589
4590 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 4591 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 4592
060c8778 4593 mutex_lock(&dev->mode_config.mutex);
0b99836f 4594 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4595 if (edid) {
4596 if (drm_add_edid_modes(connector, edid)) {
4597 drm_mode_connector_update_edid_property(connector,
4598 edid);
4599 drm_edid_to_eld(connector, edid);
4600 } else {
4601 kfree(edid);
4602 edid = ERR_PTR(-EINVAL);
4603 }
4604 } else {
4605 edid = ERR_PTR(-ENOENT);
4606 }
4607 intel_connector->edid = edid;
4608
4609 /* prefer fixed mode from EDID if available */
4610 list_for_each_entry(scan, &connector->probed_modes, head) {
4611 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4612 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4613 downclock_mode = intel_dp_drrs_init(
4614 intel_dig_port,
4615 intel_connector, fixed_mode);
ed92f0b2
PZ		 4616 break;
4617 }
4618 }
4619
4620 /* fallback to VBT if available for eDP */
4621 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4622 fixed_mode = drm_mode_duplicate(dev,
4623 dev_priv->vbt.lfp_lvds_vbt_mode);
4624 if (fixed_mode)
4625 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4626 }
060c8778 4627 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4628
01527b31
CT		 4629 if (IS_VALLEYVIEW(dev)) {
4630 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4631 register_reboot_notifier(&intel_dp->edp_notifier);
4632 }
4633
4f9db5b5 4634 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 4635 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 4636 intel_panel_setup_backlight(connector);
4637
4638 return true;
4639}
4640
16c25533 4641bool
f0fec3f2
PZ		 4642intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4643 struct intel_connector *intel_connector)
a4fc5ed6 4644{
f0fec3f2
PZ		 4645 struct drm_connector *connector = &intel_connector->base;
4646 struct intel_dp *intel_dp = &intel_dig_port->dp;
4647 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4648 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4649 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4650 enum port port = intel_dig_port->port;
0095e6dc 4651 struct edp_power_seq power_seq = { 0 };
0b99836f 4652 int type;
a4fc5ed6 4653
ec5b01dd
DL		 4654 /* intel_dp vfuncs */
4655 if (IS_VALLEYVIEW(dev))
4656 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4657 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4658 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4659 else if (HAS_PCH_SPLIT(dev))
4660 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4661 else
4662 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4663
153b1100
DL		 4664 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4665
0767935e
DV		 4666 /* Preserve the current hw state. */
4667 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4668 intel_dp->attached_connector = intel_connector;
3d3dc149 4669
3b32a35b 4670 if (intel_dp_is_edp(dev, port))
b329530c 4671 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4672 else
4673 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4674
f7d24902
ID		 4675 /*
4676 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4677 * for DP the encoder type can be set by the caller to
4678 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4679 */
4680 if (type == DRM_MODE_CONNECTOR_eDP)
4681 intel_encoder->type = INTEL_OUTPUT_EDP;
4682
e7281eab
ID		 4683 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4684 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4685 port_name(port));
4686
b329530c 4687 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4688 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4689
a4fc5ed6
KP		 4690 connector->interlace_allowed = true;
4691 connector->doublescan_allowed = 0;
4692
f0fec3f2 4693 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4694 edp_panel_vdd_work);
a4fc5ed6 4695
df0e9248 4696 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 4697 drm_connector_register(connector);
a4fc5ed6 4698
affa9354 4699 if (HAS_DDI(dev))
bcbc889b
PZ		 4700 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4701 else
4702 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 4703 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 4704
0b99836f 4705 /* Set up the hotplug pin. */
ab9d7c30
PZ		 4706 switch (port) {
4707 case PORT_A:
1d843f9d 4708 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 4709 break;
4710 case PORT_B:
1d843f9d 4711 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 4712 break;
4713 case PORT_C:
1d843f9d 4714 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 4715 break;
4716 case PORT_D:
1d843f9d 4717 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 4718 break;
4719 default:
ad1c0b19 4720 BUG();
5eb08b69
ZW		 4721 }
4722
dada1a9f
ID		 4723 if (is_edp(intel_dp)) {
4724 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 4725 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 4726 }
0095e6dc 4727
9d1a1031 4728 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 4729
0e32b39c
DA		 4730 /* init MST on ports that can support it */
4731 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4732 if (port == PORT_B || port == PORT_C || port == PORT_D) {
4733 intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
4734 }
4735 }
4736
0095e6dc 4737 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 4738 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 4739 if (is_edp(intel_dp)) {
4740 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4741 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4742 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4743 drm_modeset_unlock(&dev->mode_config.connection_mutex);
15b1d171 4744 }
34ea3d38 4745 drm_connector_unregister(connector);
b2f246a8 4746 drm_connector_cleanup(connector);
16c25533 4747 return false;
b2f246a8 4748 }
32f9d658 4749
f684960e
CW		 4750 intel_dp_add_properties(intel_dp, connector);
4751
a4fc5ed6
KP		 4752 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4753 * 0xd. Failure to do so will result in spurious interrupts being
4754 * generated on the port when a cable is not attached.
4755 */
4756 if (IS_G4X(dev) && !IS_GM45(dev)) {
4757 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4758 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4759 }
16c25533
PZ		 4760
4761 return true;
a4fc5ed6 4762}
f0fec3f2
PZ		 4763
4764void
4765intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4766{
13cf5504 4767 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 4768 struct intel_digital_port *intel_dig_port;
4769 struct intel_encoder *intel_encoder;
4770 struct drm_encoder *encoder;
4771 struct intel_connector *intel_connector;
4772
b14c5679 4773 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 4774 if (!intel_dig_port)
4775 return;
4776
b14c5679 4777 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 4778 if (!intel_connector) {
4779 kfree(intel_dig_port);
4780 return;
4781 }
4782
4783 intel_encoder = &intel_dig_port->base;
4784 encoder = &intel_encoder->base;
4785
4786 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4787 DRM_MODE_ENCODER_TMDS);
4788
5bfe2ac0 4789 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 4790 intel_encoder->disable = intel_disable_dp;
00c09d70 4791 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4792 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 4793 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 4794 if (IS_CHERRYVIEW(dev)) {
9197c88b 4795 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 4796 intel_encoder->pre_enable = chv_pre_enable_dp;
4797 intel_encoder->enable = vlv_enable_dp;
580d3811 4798 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 4799 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4800 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4801 intel_encoder->pre_enable = vlv_pre_enable_dp;
4802 intel_encoder->enable = vlv_enable_dp;
49277c31 4803 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4804 } else {
ecff4f3b
JN		 4805 intel_encoder->pre_enable = g4x_pre_enable_dp;
4806 intel_encoder->enable = g4x_enable_dp;
49277c31 4807 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4808 }
f0fec3f2 4809
174edf1f 4810 intel_dig_port->port = port;
f0fec3f2
PZ		 4811 intel_dig_port->dp.output_reg = output_reg;
4812
00c09d70 4813 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 4814 if (IS_CHERRYVIEW(dev)) {
4815 if (port == PORT_D)
4816 intel_encoder->crtc_mask = 1 << 2;
4817 else
4818 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4819 } else {
4820 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4821 }
bc079e8b 4822 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4823 intel_encoder->hot_plug = intel_dp_hot_plug;
4824
13cf5504
DA		 4825 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4826 dev_priv->hpd_irq_port[port] = intel_dig_port;
4827
15b1d171
PZ		 4828 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4829 drm_encoder_cleanup(encoder);
4830 kfree(intel_dig_port);
b2f246a8 4831 kfree(intel_connector);
15b1d171 4832 }
f0fec3f2 4833}
0e32b39c
DA		 4834
4835void intel_dp_mst_suspend(struct drm_device *dev)
4836{
4837 struct drm_i915_private *dev_priv = dev->dev_private;
4838 int i;
4839
4840 /* disable MST */
4841 for (i = 0; i < I915_MAX_PORTS; i++) {
4842 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4843 if (!intel_dig_port)
4844 continue;
4845
4846 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4847 if (!intel_dig_port->dp.can_mst)
4848 continue;
4849 if (intel_dig_port->dp.is_mst)
4850 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
4851 }
4852 }
4853}
4854
4855void intel_dp_mst_resume(struct drm_device *dev)
4856{
4857 struct drm_i915_private *dev_priv = dev->dev_private;
4858 int i;
4859
4860 for (i = 0; i < I915_MAX_PORTS; i++) {
4861 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4862 if (!intel_dig_port)
4863 continue;
4864 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4865 int ret;
4866
4867 if (!intel_dig_port->dp.can_mst)
4868 continue;
4869
4870 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
4871 if (ret != 0) {
4872 intel_dp_check_mst_status(&intel_dig_port->dp);
4873 }
4874 }
4875 }
4876}
Ubuntu Focal Linux kernel mirror