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drm/i915: PSR: Organize PSR enable function
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
773538e8
VS		 293static void pps_lock(struct intel_dp *intel_dp)
294{
295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct intel_encoder *encoder = &intel_dig_port->base;
297 struct drm_device *dev = encoder->base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
299 enum intel_display_power_domain power_domain;
300
301 /*
302 * See vlv_power_sequencer_reset() why we need
303 * a power domain reference here.
304 */
305 power_domain = intel_display_port_power_domain(encoder);
306 intel_display_power_get(dev_priv, power_domain);
307
308 mutex_lock(&dev_priv->pps_mutex);
309}
310
311static void pps_unlock(struct intel_dp *intel_dp)
312{
313 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
314 struct intel_encoder *encoder = &intel_dig_port->base;
315 struct drm_device *dev = encoder->base.dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317 enum intel_display_power_domain power_domain;
318
319 mutex_unlock(&dev_priv->pps_mutex);
320
321 power_domain = intel_display_port_power_domain(encoder);
322 intel_display_power_put(dev_priv, power_domain);
323}
324
bf13e81b
JN		 325static enum pipe
326vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
327{
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 331 struct intel_encoder *encoder;
332 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
333 struct edp_power_seq power_seq;
bf13e81b 334
e39b999a
VS		 335 lockdep_assert_held(&dev_priv->pps_mutex);
336
a4a5d2f8
VS		 337 if (intel_dp->pps_pipe != INVALID_PIPE)
338 return intel_dp->pps_pipe;
339
340 /*
341 * We don't have power sequencer currently.
342 * Pick one that's not used by other ports.
343 */
344 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
345 base.head) {
346 struct intel_dp *tmp;
347
348 if (encoder->type != INTEL_OUTPUT_EDP)
349 continue;
350
351 tmp = enc_to_intel_dp(&encoder->base);
352
353 if (tmp->pps_pipe != INVALID_PIPE)
354 pipes &= ~(1 << tmp->pps_pipe);
355 }
356
357 /*
358 * Didn't find one. This should not happen since there
359 * are two power sequencers and up to two eDP ports.
360 */
361 if (WARN_ON(pipes == 0))
362 return PIPE_A;
363
364 intel_dp->pps_pipe = ffs(pipes) - 1;
365
366 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
367 pipe_name(intel_dp->pps_pipe),
368 port_name(intel_dig_port->port));
369
370 /* init power sequencer on this pipe and port */
371 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
372 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
373 &power_seq);
374
375 return intel_dp->pps_pipe;
376}
377
6491ab27
VS		 378typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
379 enum pipe pipe);
380
381static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
382 enum pipe pipe)
383{
384 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
385}
386
387static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
388 enum pipe pipe)
389{
390 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
391}
392
393static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
394 enum pipe pipe)
395{
396 return true;
397}
bf13e81b 398
a4a5d2f8 399static enum pipe
6491ab27
VS		 400vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
401 enum port port,
402 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 403{
404 enum pipe pipe;
bf13e81b 405
bf13e81b
JN		 406 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
407 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
408 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 409
410 if (port_sel != PANEL_PORT_SELECT_VLV(port))
411 continue;
412
6491ab27
VS		 413 if (!pipe_check(dev_priv, pipe))
414 continue;
415
a4a5d2f8 416 return pipe;
bf13e81b
JN		 417 }
418
a4a5d2f8
VS		 419 return INVALID_PIPE;
420}
421
422static void
423vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
424{
425 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
426 struct drm_device *dev = intel_dig_port->base.base.dev;
427 struct drm_i915_private *dev_priv = dev->dev_private;
428 struct edp_power_seq power_seq;
429 enum port port = intel_dig_port->port;
430
431 lockdep_assert_held(&dev_priv->pps_mutex);
432
433 /* try to find a pipe with this port selected */
6491ab27
VS		 434 /* first pick one where the panel is on */
435 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
436 vlv_pipe_has_pp_on);
437 /* didn't find one? pick one where vdd is on */
438 if (intel_dp->pps_pipe == INVALID_PIPE)
439 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
440 vlv_pipe_has_vdd_on);
441 /* didn't find one? pick one with just the correct port */
442 if (intel_dp->pps_pipe == INVALID_PIPE)
443 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
444 vlv_pipe_any);
a4a5d2f8
VS		 445
446 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
447 if (intel_dp->pps_pipe == INVALID_PIPE) {
448 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
449 port_name(port));
450 return;
bf13e81b
JN		 451 }
452
a4a5d2f8
VS		 453 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
454 port_name(port), pipe_name(intel_dp->pps_pipe));
455
456 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
457 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
458 &power_seq);
bf13e81b
JN		 459}
460
773538e8
VS		 461void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
462{
463 struct drm_device *dev = dev_priv->dev;
464 struct intel_encoder *encoder;
465
466 if (WARN_ON(!IS_VALLEYVIEW(dev)))
467 return;
468
469 /*
470 * We can't grab pps_mutex here due to deadlock with power_domain
471 * mutex when power_domain functions are called while holding pps_mutex.
472 * That also means that in order to use pps_pipe the code needs to
473 * hold both a power domain reference and pps_mutex, and the power domain
474 * reference get/put must be done while _not_ holding pps_mutex.
475 * pps_{lock,unlock}() do these steps in the correct order, so one
476 * should use them always.
477 */
478
479 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
480 struct intel_dp *intel_dp;
481
482 if (encoder->type != INTEL_OUTPUT_EDP)
483 continue;
484
485 intel_dp = enc_to_intel_dp(&encoder->base);
486 intel_dp->pps_pipe = INVALID_PIPE;
487 }
bf13e81b
JN		 488}
489
490static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
491{
492 struct drm_device *dev = intel_dp_to_dev(intel_dp);
493
494 if (HAS_PCH_SPLIT(dev))
495 return PCH_PP_CONTROL;
496 else
497 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
498}
499
500static u32 _pp_stat_reg(struct intel_dp *intel_dp)
501{
502 struct drm_device *dev = intel_dp_to_dev(intel_dp);
503
504 if (HAS_PCH_SPLIT(dev))
505 return PCH_PP_STATUS;
506 else
507 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
508}
509
01527b31
CT		 510/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
511 This function only applicable when panel PM state is not to be tracked */
512static int edp_notify_handler(struct notifier_block *this, unsigned long code,
513 void *unused)
514{
515 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
516 edp_notifier);
517 struct drm_device *dev = intel_dp_to_dev(intel_dp);
518 struct drm_i915_private *dev_priv = dev->dev_private;
519 u32 pp_div;
520 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 521
522 if (!is_edp(intel_dp) || code != SYS_RESTART)
523 return 0;
524
773538e8 525 pps_lock(intel_dp);
e39b999a 526
01527b31 527 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 528 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
529
01527b31
CT		 530 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
531 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
532 pp_div = I915_READ(pp_div_reg);
533 pp_div &= PP_REFERENCE_DIVIDER_MASK;
534
535 /* 0x1F write to PP_DIV_REG sets max cycle delay */
536 I915_WRITE(pp_div_reg, pp_div | 0x1F);
537 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
538 msleep(intel_dp->panel_power_cycle_delay);
539 }
540
773538e8 541 pps_unlock(intel_dp);
e39b999a 542
01527b31
CT		 543 return 0;
544}
545
4be73780 546static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 547{
30add22d 548 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 549 struct drm_i915_private *dev_priv = dev->dev_private;
550
e39b999a
VS		 551 lockdep_assert_held(&dev_priv->pps_mutex);
552
bf13e81b 553 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 554}
555
4be73780 556static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 557{
30add22d 558 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 559 struct drm_i915_private *dev_priv = dev->dev_private;
560
e39b999a
VS		 561 lockdep_assert_held(&dev_priv->pps_mutex);
562
773538e8 563 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 564}
565
9b984dae
KP		 566static void
567intel_dp_check_edp(struct intel_dp *intel_dp)
568{
30add22d 569 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 570 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 571
9b984dae
KP		 572 if (!is_edp(intel_dp))
573 return;
453c5420 574
4be73780 575 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 576 WARN(1, "eDP powered off while attempting aux channel communication.\n");
577 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 578 I915_READ(_pp_stat_reg(intel_dp)),
579 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 580 }
581}
582
9ee32fea
DV		 583static uint32_t
584intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
585{
586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
587 struct drm_device *dev = intel_dig_port->base.base.dev;
588 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 589 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 590 uint32_t status;
591 bool done;
592
ef04f00d 593#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 594 if (has_aux_irq)
b18ac466 595 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 596 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 597 else
598 done = wait_for_atomic(C, 10) == 0;
599 if (!done)
600 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
601 has_aux_irq);
602#undef C
603
604 return status;
605}
606
ec5b01dd 607static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 608{
174edf1f
PZ		 609 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
610 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 611
ec5b01dd
DL		 612 /*
613 * The clock divider is based off the hrawclk, and would like to run at
614 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 615 */
ec5b01dd
DL		 616 return index ? 0 : intel_hrawclk(dev) / 2;
617}
618
619static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
620{
621 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
622 struct drm_device *dev = intel_dig_port->base.base.dev;
623
624 if (index)
625 return 0;
626
627 if (intel_dig_port->port == PORT_A) {
628 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 629 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 630 else
b84a1cf8 631 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 632 } else {
633 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
634 }
635}
636
637static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
638{
639 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
640 struct drm_device *dev = intel_dig_port->base.base.dev;
641 struct drm_i915_private *dev_priv = dev->dev_private;
642
643 if (intel_dig_port->port == PORT_A) {
644 if (index)
645 return 0;
646 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 647 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
648 /* Workaround for non-ULT HSW */
bc86625a
CW		 649 switch (index) {
650 case 0: return 63;
651 case 1: return 72;
652 default: return 0;
653 }
ec5b01dd 654 } else {
bc86625a 655 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 656 }
b84a1cf8
RV		 657}
658
ec5b01dd
DL		 659static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
660{
661 return index ? 0 : 100;
662}
663
5ed12a19
DL		 664static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
665 bool has_aux_irq,
666 int send_bytes,
667 uint32_t aux_clock_divider)
668{
669 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
670 struct drm_device *dev = intel_dig_port->base.base.dev;
671 uint32_t precharge, timeout;
672
673 if (IS_GEN6(dev))
674 precharge = 3;
675 else
676 precharge = 5;
677
678 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
679 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
680 else
681 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
682
683 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 684 DP_AUX_CH_CTL_DONE |
5ed12a19 685 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 686 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 687 timeout |
788d4433 688 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 689 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
690 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 691 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 692}
693
b84a1cf8
RV		 694static int
695intel_dp_aux_ch(struct intel_dp *intel_dp,
696 uint8_t *send, int send_bytes,
697 uint8_t *recv, int recv_size)
698{
699 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
700 struct drm_device *dev = intel_dig_port->base.base.dev;
701 struct drm_i915_private *dev_priv = dev->dev_private;
702 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
703 uint32_t ch_data = ch_ctl + 4;
bc86625a 704 uint32_t aux_clock_divider;
b84a1cf8
RV		 705 int i, ret, recv_bytes;
706 uint32_t status;
5ed12a19 707 int try, clock = 0;
4e6b788c 708 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 709 bool vdd;
710
773538e8 711 pps_lock(intel_dp);
e39b999a 712
72c3500a
VS		 713 /*
714 * We will be called with VDD already enabled for dpcd/edid/oui reads.
715 * In such cases we want to leave VDD enabled and it's up to upper layers
716 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
717 * ourselves.
718 */
1e0560e0 719 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 720
721 /* dp aux is extremely sensitive to irq latency, hence request the
722 * lowest possible wakeup latency and so prevent the cpu from going into
723 * deep sleep states.
724 */
725 pm_qos_update_request(&dev_priv->pm_qos, 0);
726
727 intel_dp_check_edp(intel_dp);
5eb08b69 728
c67a470b
PZ		 729 intel_aux_display_runtime_get(dev_priv);
730
11bee43e
JB		 731 /* Try to wait for any previous AUX channel activity */
732 for (try = 0; try < 3; try++) {
ef04f00d 733 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 734 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
735 break;
736 msleep(1);
737 }
738
739 if (try == 3) {
740 WARN(1, "dp_aux_ch not started status 0x%08x\n",
741 I915_READ(ch_ctl));
9ee32fea
DV		 742 ret = -EBUSY;
743 goto out;
4f7f7b7e
CW		 744 }
745
46a5ae9f
PZ		 746 /* Only 5 data registers! */
747 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
748 ret = -E2BIG;
749 goto out;
750 }
751
ec5b01dd 752 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 753 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
754 has_aux_irq,
755 send_bytes,
756 aux_clock_divider);
5ed12a19 757
bc86625a
CW		 758 /* Must try at least 3 times according to DP spec */
759 for (try = 0; try < 5; try++) {
760 /* Load the send data into the aux channel data registers */
761 for (i = 0; i < send_bytes; i += 4)
762 I915_WRITE(ch_data + i,
763 pack_aux(send + i, send_bytes - i));
764
765 /* Send the command and wait for it to complete */
5ed12a19 766 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 767
768 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
769
770 /* Clear done status and any errors */
771 I915_WRITE(ch_ctl,
772 status |
773 DP_AUX_CH_CTL_DONE |
774 DP_AUX_CH_CTL_TIME_OUT_ERROR |
775 DP_AUX_CH_CTL_RECEIVE_ERROR);
776
777 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
778 DP_AUX_CH_CTL_RECEIVE_ERROR))
779 continue;
780 if (status & DP_AUX_CH_CTL_DONE)
781 break;
782 }
4f7f7b7e 783 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 784 break;
785 }
786
a4fc5ed6 787 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 788 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 789 ret = -EBUSY;
790 goto out;
a4fc5ed6
KP		 791 }
792
793 /* Check for timeout or receive error.
794 * Timeouts occur when the sink is not connected
795 */
a5b3da54 796 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 797 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 798 ret = -EIO;
799 goto out;
a5b3da54 800 }
1ae8c0a5
KP		 801
802 /* Timeouts occur when the device isn't connected, so they're
803 * "normal" -- don't fill the kernel log with these */
a5b3da54 804 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 805 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 806 ret = -ETIMEDOUT;
807 goto out;
a4fc5ed6
KP		 808 }
809
810 /* Unload any bytes sent back from the other side */
811 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
812 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 813 if (recv_bytes > recv_size)
814 recv_bytes = recv_size;
0206e353 815
4f7f7b7e
CW		 816 for (i = 0; i < recv_bytes; i += 4)
817 unpack_aux(I915_READ(ch_data + i),
818 recv + i, recv_bytes - i);
a4fc5ed6 819
9ee32fea
DV		 820 ret = recv_bytes;
821out:
822 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 823 intel_aux_display_runtime_put(dev_priv);
9ee32fea 824
884f19e9
JN		 825 if (vdd)
826 edp_panel_vdd_off(intel_dp, false);
827
773538e8 828 pps_unlock(intel_dp);
e39b999a 829
9ee32fea 830 return ret;
a4fc5ed6
KP		 831}
832
a6c8aff0
JN		 833#define BARE_ADDRESS_SIZE 3
834#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 835static ssize_t
836intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 837{
9d1a1031
JN		 838 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
839 uint8_t txbuf[20], rxbuf[20];
840 size_t txsize, rxsize;
a4fc5ed6 841 int ret;
a4fc5ed6 842
9d1a1031
JN		 843 txbuf[0] = msg->request << 4;
844 txbuf[1] = msg->address >> 8;
845 txbuf[2] = msg->address & 0xff;
846 txbuf[3] = msg->size - 1;
46a5ae9f 847
9d1a1031
JN		 848 switch (msg->request & ~DP_AUX_I2C_MOT) {
849 case DP_AUX_NATIVE_WRITE:
850 case DP_AUX_I2C_WRITE:
a6c8aff0 851 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 852 rxsize = 1;
f51a44b9 853
9d1a1031
JN		 854 if (WARN_ON(txsize > 20))
855 return -E2BIG;
a4fc5ed6 856
9d1a1031 857 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 858
9d1a1031
JN		 859 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
860 if (ret > 0) {
861 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 862
9d1a1031
JN		 863 /* Return payload size. */
864 ret = msg->size;
865 }
866 break;
46a5ae9f 867
9d1a1031
JN		 868 case DP_AUX_NATIVE_READ:
869 case DP_AUX_I2C_READ:
a6c8aff0 870 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 871 rxsize = msg->size + 1;
a4fc5ed6 872
9d1a1031
JN		 873 if (WARN_ON(rxsize > 20))
874 return -E2BIG;
a4fc5ed6 875
9d1a1031
JN		 876 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
877 if (ret > 0) {
878 msg->reply = rxbuf[0] >> 4;
879 /*
880 * Assume happy day, and copy the data. The caller is
881 * expected to check msg->reply before touching it.
882 *
883 * Return payload size.
884 */
885 ret--;
886 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 887 }
9d1a1031
JN		 888 break;
889
890 default:
891 ret = -EINVAL;
892 break;
a4fc5ed6 893 }
f51a44b9 894
9d1a1031 895 return ret;
a4fc5ed6
KP		 896}
897
9d1a1031
JN		 898static void
899intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
900{
901 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 902 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
903 enum port port = intel_dig_port->port;
0b99836f 904 const char *name = NULL;
ab2c0672
DA		 905 int ret;
906
33ad6626
JN		 907 switch (port) {
908 case PORT_A:
909 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 910 name = "DPDDC-A";
ab2c0672 911 break;
33ad6626
JN		 912 case PORT_B:
913 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 914 name = "DPDDC-B";
ab2c0672 915 break;
33ad6626
JN		 916 case PORT_C:
917 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 918 name = "DPDDC-C";
ab2c0672 919 break;
33ad6626
JN		 920 case PORT_D:
921 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 922 name = "DPDDC-D";
33ad6626
JN		 923 break;
924 default:
925 BUG();
ab2c0672
DA		 926 }
927
33ad6626
JN		 928 if (!HAS_DDI(dev))
929 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 930
0b99836f 931 intel_dp->aux.name = name;
9d1a1031
JN		 932 intel_dp->aux.dev = dev->dev;
933 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 934
0b99836f
JN		 935 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
936 connector->base.kdev->kobj.name);
8316f337 937
4f71d0cb 938 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 939 if (ret < 0) {
4f71d0cb 940 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 941 name, ret);
942 return;
ab2c0672 943 }
8a5e6aeb 944
0b99836f
JN		 945 ret = sysfs_create_link(&connector->base.kdev->kobj,
946 &intel_dp->aux.ddc.dev.kobj,
947 intel_dp->aux.ddc.dev.kobj.name);
948 if (ret < 0) {
949 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 950 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 951 }
a4fc5ed6
KP		 952}
953
80f65de3
ID		 954static void
955intel_dp_connector_unregister(struct intel_connector *intel_connector)
956{
957 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
958
0e32b39c
DA		 959 if (!intel_connector->mst_port)
960 sysfs_remove_link(&intel_connector->base.kdev->kobj,
961 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 962 intel_connector_unregister(intel_connector);
963}
964
0e50338c
DV		 965static void
966hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
967{
968 switch (link_bw) {
969 case DP_LINK_BW_1_62:
970 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
971 break;
972 case DP_LINK_BW_2_7:
973 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
974 break;
975 case DP_LINK_BW_5_4:
976 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
977 break;
978 }
979}
980
c6bb3538
DV		 981static void
982intel_dp_set_clock(struct intel_encoder *encoder,
983 struct intel_crtc_config *pipe_config, int link_bw)
984{
985 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 986 const struct dp_link_dpll *divisor = NULL;
987 int i, count = 0;
c6bb3538
DV		 988
989 if (IS_G4X(dev)) {
9dd4ffdf
CML		 990 divisor = gen4_dpll;
991 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 992 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 993 divisor = pch_dpll;
994 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 995 } else if (IS_CHERRYVIEW(dev)) {
996 divisor = chv_dpll;
997 count = ARRAY_SIZE(chv_dpll);
c6bb3538 998 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 999 divisor = vlv_dpll;
1000 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1001 }
9dd4ffdf
CML		 1002
1003 if (divisor && count) {
1004 for (i = 0; i < count; i++) {
1005 if (link_bw == divisor[i].link_bw) {
1006 pipe_config->dpll = divisor[i].dpll;
1007 pipe_config->clock_set = true;
1008 break;
1009 }
1010 }
c6bb3538
DV		 1011 }
1012}
1013
00c09d70 1014bool
5bfe2ac0
DV		 1015intel_dp_compute_config(struct intel_encoder *encoder,
1016 struct intel_crtc_config *pipe_config)
a4fc5ed6 1017{
5bfe2ac0 1018 struct drm_device *dev = encoder->base.dev;
36008365 1019 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1020 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1021 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1022 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1023 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1024 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1025 int lane_count, clock;
56071a20 1026 int min_lane_count = 1;
eeb6324d 1027 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1028 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1029 int min_clock = 0;
06ea66b6 1030 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1031 int bpp, mode_rate;
06ea66b6 1032 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1033 int link_avail, link_clock;
a4fc5ed6 1034
bc7d38a4 1035 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1036 pipe_config->has_pch_encoder = true;
1037
03afc4a2 1038 pipe_config->has_dp_encoder = true;
f769cd24 1039 pipe_config->has_drrs = false;
9ed109a7 1040 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1041
dd06f90e
JN		 1042 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1043 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1044 adjusted_mode);
2dd24552
JB		 1045 if (!HAS_PCH_SPLIT(dev))
1046 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1047 intel_connector->panel.fitting_mode);
1048 else
b074cec8
JB		 1049 intel_pch_panel_fitting(intel_crtc, pipe_config,
1050 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1051 }
1052
cb1793ce 1053 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1054 return false;
1055
083f9560
DV		 1056 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1057 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1058 max_lane_count, bws[max_clock],
1059 adjusted_mode->crtc_clock);
083f9560 1060
36008365
DV		 1061 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1062 * bpc in between. */
3e7ca985 1063 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1064 if (is_edp(intel_dp)) {
1065 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1066 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1067 dev_priv->vbt.edp_bpp);
1068 bpp = dev_priv->vbt.edp_bpp;
1069 }
1070
344c5bbc
JN		 1071 /*
1072 * Use the maximum clock and number of lanes the eDP panel
1073 * advertizes being capable of. The panels are generally
1074 * designed to support only a single clock and lane
1075 * configuration, and typically these values correspond to the
1076 * native resolution of the panel.
1077 */
1078 min_lane_count = max_lane_count;
1079 min_clock = max_clock;
7984211e 1080 }
657445fe 1081
36008365 1082 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1083 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1084 bpp);
36008365 1085
c6930992
DA		 1086 for (clock = min_clock; clock <= max_clock; clock++) {
1087 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1088 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1089 link_avail = intel_dp_max_data_rate(link_clock,
1090 lane_count);
1091
1092 if (mode_rate <= link_avail) {
1093 goto found;
1094 }
1095 }
1096 }
1097 }
c4867936 1098
36008365 1099 return false;
3685a8f3 1100
36008365 1101found:
55bc60db
VS		 1102 if (intel_dp->color_range_auto) {
1103 /*
1104 * See:
1105 * CEA-861-E - 5.1 Default Encoding Parameters
1106 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1107 */
18316c8c 1108 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1109 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1110 else
1111 intel_dp->color_range = 0;
1112 }
1113
3685a8f3 1114 if (intel_dp->color_range)
50f3b016 1115 pipe_config->limited_color_range = true;
a4fc5ed6 1116
36008365
DV		 1117 intel_dp->link_bw = bws[clock];
1118 intel_dp->lane_count = lane_count;
657445fe 1119 pipe_config->pipe_bpp = bpp;
ff9a6750 1120 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1121
36008365
DV		 1122 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1123 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1124 pipe_config->port_clock, bpp);
36008365
DV		 1125 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1126 mode_rate, link_avail);
a4fc5ed6 1127
03afc4a2 1128 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1129 adjusted_mode->crtc_clock,
1130 pipe_config->port_clock,
03afc4a2 1131 &pipe_config->dp_m_n);
9d1a455b 1132
439d7ac0
PB		 1133 if (intel_connector->panel.downclock_mode != NULL &&
1134 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1135 pipe_config->has_drrs = true;
439d7ac0
PB		 1136 intel_link_compute_m_n(bpp, lane_count,
1137 intel_connector->panel.downclock_mode->clock,
1138 pipe_config->port_clock,
1139 &pipe_config->dp_m2_n2);
1140 }
1141
ea155f32 1142 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1143 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1144 else
1145 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1146
03afc4a2 1147 return true;
a4fc5ed6
KP		 1148}
1149
7c62a164 1150static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1151{
7c62a164
DV		 1152 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1153 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1154 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1155 struct drm_i915_private *dev_priv = dev->dev_private;
1156 u32 dpa_ctl;
1157
ff9a6750 1158 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1159 dpa_ctl = I915_READ(DP_A);
1160 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1161
ff9a6750 1162 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1163 /* For a long time we've carried around a ILK-DevA w/a for the
1164 * 160MHz clock. If we're really unlucky, it's still required.
1165 */
1166 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1167 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1168 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1169 } else {
1170 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1171 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1172 }
1ce17038 1173
ea9b6006
DV		 1174 I915_WRITE(DP_A, dpa_ctl);
1175
1176 POSTING_READ(DP_A);
1177 udelay(500);
1178}
1179
8ac33ed3 1180static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1181{
b934223d 1182 struct drm_device *dev = encoder->base.dev;
417e822d 1183 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1184 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1185 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1186 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1187 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1188
417e822d 1189 /*
1a2eb460 1190 * There are four kinds of DP registers:
417e822d
KP		 1191 *
1192 * IBX PCH
1a2eb460
KP		 1193 * SNB CPU
1194 * IVB CPU
417e822d
KP		 1195 * CPT PCH
1196 *
1197 * IBX PCH and CPU are the same for almost everything,
1198 * except that the CPU DP PLL is configured in this
1199 * register
1200 *
1201 * CPT PCH is quite different, having many bits moved
1202 * to the TRANS_DP_CTL register instead. That
1203 * configuration happens (oddly) in ironlake_pch_enable
1204 */
9c9e7927 1205
417e822d
KP		 1206 /* Preserve the BIOS-computed detected bit. This is
1207 * supposed to be read-only.
1208 */
1209 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1210
417e822d 1211 /* Handle DP bits in common between all three register formats */
417e822d 1212 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1213 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1214
9ed109a7 1215 if (crtc->config.has_audio) {
e0dac65e 1216 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1217 pipe_name(crtc->pipe));
ea5b213a 1218 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1219 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1220 }
247d89f6 1221
417e822d 1222 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1223
bc7d38a4 1224 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1225 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1226 intel_dp->DP |= DP_SYNC_HS_HIGH;
1227 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1228 intel_dp->DP |= DP_SYNC_VS_HIGH;
1229 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1230
6aba5b6c 1231 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1232 intel_dp->DP |= DP_ENHANCED_FRAMING;
1233
7c62a164 1234 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1235 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1236 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1237 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1238
1239 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1240 intel_dp->DP |= DP_SYNC_HS_HIGH;
1241 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1242 intel_dp->DP |= DP_SYNC_VS_HIGH;
1243 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1244
6aba5b6c 1245 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1246 intel_dp->DP |= DP_ENHANCED_FRAMING;
1247
44f37d1f
CML		 1248 if (!IS_CHERRYVIEW(dev)) {
1249 if (crtc->pipe == 1)
1250 intel_dp->DP |= DP_PIPEB_SELECT;
1251 } else {
1252 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1253 }
417e822d
KP		 1254 } else {
1255 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1256 }
a4fc5ed6
KP		 1257}
1258
ffd6749d
PZ		 1259#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1260#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1261
1a5ef5b7
PZ		 1262#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1263#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1264
ffd6749d
PZ		 1265#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1266#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1267
4be73780 1268static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1269 u32 mask,
1270 u32 value)
bd943159 1271{
30add22d 1272 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1273 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1274 u32 pp_stat_reg, pp_ctrl_reg;
1275
e39b999a
VS		 1276 lockdep_assert_held(&dev_priv->pps_mutex);
1277
bf13e81b
JN		 1278 pp_stat_reg = _pp_stat_reg(intel_dp);
1279 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1280
99ea7127 1281 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1282 mask, value,
1283 I915_READ(pp_stat_reg),
1284 I915_READ(pp_ctrl_reg));
32ce697c 1285
453c5420 1286 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1287 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1288 I915_READ(pp_stat_reg),
1289 I915_READ(pp_ctrl_reg));
32ce697c 1290 }
54c136d4
CW		 1291
1292 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1293}
32ce697c 1294
4be73780 1295static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1296{
1297 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1298 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1299}
1300
4be73780 1301static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1302{
1303 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1304 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1305}
1306
4be73780 1307static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1308{
1309 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1310
1311 /* When we disable the VDD override bit last we have to do the manual
1312 * wait. */
1313 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1314 intel_dp->panel_power_cycle_delay);
1315
4be73780 1316 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1317}
1318
4be73780 1319static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1320{
1321 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1322 intel_dp->backlight_on_delay);
1323}
1324
4be73780 1325static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1326{
1327 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1328 intel_dp->backlight_off_delay);
1329}
99ea7127 1330
832dd3c1
KP		 1331/* Read the current pp_control value, unlocking the register if it
1332 * is locked
1333 */
1334
453c5420 1335static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1336{
453c5420
JB		 1337 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1338 struct drm_i915_private *dev_priv = dev->dev_private;
1339 u32 control;
832dd3c1 1340
e39b999a
VS		 1341 lockdep_assert_held(&dev_priv->pps_mutex);
1342
bf13e81b 1343 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1344 control &= ~PANEL_UNLOCK_MASK;
1345 control |= PANEL_UNLOCK_REGS;
1346 return control;
bd943159
KP		 1347}
1348
951468f3
VS		 1349/*
1350 * Must be paired with edp_panel_vdd_off().
1351 * Must hold pps_mutex around the whole on/off sequence.
1352 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1353 */
1e0560e0 1354static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1355{
30add22d 1356 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1358 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1359 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1360 enum intel_display_power_domain power_domain;
5d613501 1361 u32 pp;
453c5420 1362 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1363 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1364
e39b999a
VS		 1365 lockdep_assert_held(&dev_priv->pps_mutex);
1366
97af61f5 1367 if (!is_edp(intel_dp))
adddaaf4 1368 return false;
bd943159
KP		 1369
1370 intel_dp->want_panel_vdd = true;
99ea7127 1371
4be73780 1372 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1373 return need_to_disable;
b0665d57 1374
4e6e1a54
ID		 1375 power_domain = intel_display_port_power_domain(intel_encoder);
1376 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1377
b0665d57 1378 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1379
4be73780
DV		 1380 if (!edp_have_panel_power(intel_dp))
1381 wait_panel_power_cycle(intel_dp);
99ea7127 1382
453c5420 1383 pp = ironlake_get_pp_control(intel_dp);
5d613501 1384 pp |= EDP_FORCE_VDD;
ebf33b18 1385
bf13e81b
JN		 1386 pp_stat_reg = _pp_stat_reg(intel_dp);
1387 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1388
1389 I915_WRITE(pp_ctrl_reg, pp);
1390 POSTING_READ(pp_ctrl_reg);
1391 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1392 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1393 /*
1394 * If the panel wasn't on, delay before accessing aux channel
1395 */
4be73780 1396 if (!edp_have_panel_power(intel_dp)) {
bd943159 1397 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1398 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1399 }
adddaaf4
JN		 1400
1401 return need_to_disable;
1402}
1403
951468f3
VS		 1404/*
1405 * Must be paired with intel_edp_panel_vdd_off() or
1406 * intel_edp_panel_off().
1407 * Nested calls to these functions are not allowed since
1408 * we drop the lock. Caller must use some higher level
1409 * locking to prevent nested calls from other threads.
1410 */
b80d6c78 1411void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1412{
c695b6b6 1413 bool vdd;
adddaaf4 1414
c695b6b6
VS		 1415 if (!is_edp(intel_dp))
1416 return;
1417
773538e8 1418 pps_lock(intel_dp);
c695b6b6 1419 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1420 pps_unlock(intel_dp);
c695b6b6
VS		 1421
1422 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1423}
1424
4be73780 1425static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1426{
30add22d 1427 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1428 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1429 struct intel_digital_port *intel_dig_port =
1430 dp_to_dig_port(intel_dp);
1431 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1432 enum intel_display_power_domain power_domain;
5d613501 1433 u32 pp;
453c5420 1434 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1435
e39b999a 1436 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1437
15e899a0 1438 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1439
15e899a0 1440 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1441 return;
b0665d57 1442
be2c9196 1443 DRM_DEBUG_KMS("Turning eDP VDD off\n");
bd943159 1444
be2c9196
VS		 1445 pp = ironlake_get_pp_control(intel_dp);
1446 pp &= ~EDP_FORCE_VDD;
453c5420 1447
be2c9196
VS		 1448 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1449 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420 1450
be2c9196
VS		 1451 I915_WRITE(pp_ctrl_reg, pp);
1452 POSTING_READ(pp_ctrl_reg);
99ea7127 1453
be2c9196
VS		 1454 /* Make sure sequencer is idle before allowing subsequent activity */
1455 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1456 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c 1457
be2c9196
VS		 1458 if ((pp & POWER_TARGET_ON) == 0)
1459 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1460
be2c9196
VS		 1461 power_domain = intel_display_port_power_domain(intel_encoder);
1462 intel_display_power_put(dev_priv, power_domain);
bd943159 1463}
5d613501 1464
4be73780 1465static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1466{
1467 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1468 struct intel_dp, panel_vdd_work);
bd943159 1469
773538e8 1470 pps_lock(intel_dp);
15e899a0
VS		 1471 if (!intel_dp->want_panel_vdd)
1472 edp_panel_vdd_off_sync(intel_dp);
773538e8 1473 pps_unlock(intel_dp);
bd943159
KP		 1474}
1475
aba86890
ID		 1476static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1477{
1478 unsigned long delay;
1479
1480 /*
1481 * Queue the timer to fire a long time from now (relative to the power
1482 * down delay) to keep the panel power up across a sequence of
1483 * operations.
1484 */
1485 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1486 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1487}
1488
951468f3
VS		 1489/*
1490 * Must be paired with edp_panel_vdd_on().
1491 * Must hold pps_mutex around the whole on/off sequence.
1492 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1493 */
4be73780 1494static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1495{
e39b999a
VS		 1496 struct drm_i915_private *dev_priv =
1497 intel_dp_to_dev(intel_dp)->dev_private;
1498
1499 lockdep_assert_held(&dev_priv->pps_mutex);
1500
97af61f5
KP		 1501 if (!is_edp(intel_dp))
1502 return;
5d613501 1503
bd943159 1504 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1505
bd943159
KP		 1506 intel_dp->want_panel_vdd = false;
1507
aba86890 1508 if (sync)
4be73780 1509 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1510 else
1511 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1512}
1513
951468f3
VS		 1514/*
1515 * Must be paired with intel_edp_panel_vdd_on().
1516 * Nested calls to these functions are not allowed since
1517 * we drop the lock. Caller must use some higher level
1518 * locking to prevent nested calls from other threads.
1519 */
1e0560e0
VS		 1520static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1521{
e39b999a
VS		 1522 if (!is_edp(intel_dp))
1523 return;
1524
773538e8 1525 pps_lock(intel_dp);
1e0560e0 1526 edp_panel_vdd_off(intel_dp, sync);
773538e8 1527 pps_unlock(intel_dp);
1e0560e0
VS		 1528}
1529
4be73780 1530void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1531{
30add22d 1532 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1533 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1534 u32 pp;
453c5420 1535 u32 pp_ctrl_reg;
9934c132 1536
97af61f5 1537 if (!is_edp(intel_dp))
bd943159 1538 return;
99ea7127
KP		 1539
1540 DRM_DEBUG_KMS("Turn eDP power on\n");
1541
773538e8 1542 pps_lock(intel_dp);
e39b999a 1543
4be73780 1544 if (edp_have_panel_power(intel_dp)) {
99ea7127 1545 DRM_DEBUG_KMS("eDP power already on\n");
e39b999a 1546 goto out;
99ea7127 1547 }
9934c132 1548
4be73780 1549 wait_panel_power_cycle(intel_dp);
37c6c9b0 1550
bf13e81b 1551 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1552 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1553 if (IS_GEN5(dev)) {
1554 /* ILK workaround: disable reset around power sequence */
1555 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1556 I915_WRITE(pp_ctrl_reg, pp);
1557 POSTING_READ(pp_ctrl_reg);
05ce1a49 1558 }
37c6c9b0 1559
1c0ae80a 1560 pp |= POWER_TARGET_ON;
99ea7127
KP		 1561 if (!IS_GEN5(dev))
1562 pp |= PANEL_POWER_RESET;
1563
453c5420
JB		 1564 I915_WRITE(pp_ctrl_reg, pp);
1565 POSTING_READ(pp_ctrl_reg);
9934c132 1566
4be73780 1567 wait_panel_on(intel_dp);
dce56b3c 1568 intel_dp->last_power_on = jiffies;
9934c132 1569
05ce1a49
KP		 1570 if (IS_GEN5(dev)) {
1571 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1572 I915_WRITE(pp_ctrl_reg, pp);
1573 POSTING_READ(pp_ctrl_reg);
05ce1a49 1574 }
e39b999a
VS		 1575
1576 out:
773538e8 1577 pps_unlock(intel_dp);
9934c132
JB		 1578}
1579
4be73780 1580void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1581{
4e6e1a54
ID		 1582 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1583 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1584 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1585 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1586 enum intel_display_power_domain power_domain;
99ea7127 1587 u32 pp;
453c5420 1588 u32 pp_ctrl_reg;
9934c132 1589
97af61f5
KP		 1590 if (!is_edp(intel_dp))
1591 return;
37c6c9b0 1592
99ea7127 1593 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1594
773538e8 1595 pps_lock(intel_dp);
e39b999a 1596
24f3e092
JN		 1597 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1598
453c5420 1599 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1600 /* We need to switch off panel power _and_ force vdd, for otherwise some
1601 * panels get very unhappy and cease to work. */
b3064154
PJ		 1602 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1603 EDP_BLC_ENABLE);
453c5420 1604
bf13e81b 1605 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1606
849e39f5
PZ		 1607 intel_dp->want_panel_vdd = false;
1608
453c5420
JB		 1609 I915_WRITE(pp_ctrl_reg, pp);
1610 POSTING_READ(pp_ctrl_reg);
9934c132 1611
dce56b3c 1612 intel_dp->last_power_cycle = jiffies;
4be73780 1613 wait_panel_off(intel_dp);
849e39f5
PZ		 1614
1615 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1616 power_domain = intel_display_port_power_domain(intel_encoder);
1617 intel_display_power_put(dev_priv, power_domain);
e39b999a 1618
773538e8 1619 pps_unlock(intel_dp);
9934c132
JB		 1620}
1621
1250d107
JN		 1622/* Enable backlight in the panel power control. */
1623static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1624{
da63a9f2
PZ		 1625 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1626 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1627 struct drm_i915_private *dev_priv = dev->dev_private;
1628 u32 pp;
453c5420 1629 u32 pp_ctrl_reg;
32f9d658 1630
01cb9ea6
JB		 1631 /*
1632 * If we enable the backlight right away following a panel power
1633 * on, we may see slight flicker as the panel syncs with the eDP
1634 * link. So delay a bit to make sure the image is solid before
1635 * allowing it to appear.
1636 */
4be73780 1637 wait_backlight_on(intel_dp);
e39b999a 1638
773538e8 1639 pps_lock(intel_dp);
e39b999a 1640
453c5420 1641 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1642 pp |= EDP_BLC_ENABLE;
453c5420 1643
bf13e81b 1644 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1645
1646 I915_WRITE(pp_ctrl_reg, pp);
1647 POSTING_READ(pp_ctrl_reg);
e39b999a 1648
773538e8 1649 pps_unlock(intel_dp);
32f9d658
ZW		 1650}
1651
1250d107
JN		 1652/* Enable backlight PWM and backlight PP control. */
1653void intel_edp_backlight_on(struct intel_dp *intel_dp)
1654{
1655 if (!is_edp(intel_dp))
1656 return;
1657
1658 DRM_DEBUG_KMS("\n");
1659
1660 intel_panel_enable_backlight(intel_dp->attached_connector);
1661 _intel_edp_backlight_on(intel_dp);
1662}
1663
1664/* Disable backlight in the panel power control. */
1665static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1666{
30add22d 1667 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 u32 pp;
453c5420 1670 u32 pp_ctrl_reg;
32f9d658 1671
f01eca2e
KP		 1672 if (!is_edp(intel_dp))
1673 return;
1674
773538e8 1675 pps_lock(intel_dp);
e39b999a 1676
453c5420 1677 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1678 pp &= ~EDP_BLC_ENABLE;
453c5420 1679
bf13e81b 1680 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1681
1682 I915_WRITE(pp_ctrl_reg, pp);
1683 POSTING_READ(pp_ctrl_reg);
f7d2323c 1684
773538e8 1685 pps_unlock(intel_dp);
e39b999a
VS		 1686
1687 intel_dp->last_backlight_off = jiffies;
f7d2323c 1688 edp_wait_backlight_off(intel_dp);
1250d107 1689}
f7d2323c 1690
1250d107
JN		 1691/* Disable backlight PP control and backlight PWM. */
1692void intel_edp_backlight_off(struct intel_dp *intel_dp)
1693{
1694 if (!is_edp(intel_dp))
1695 return;
1696
1697 DRM_DEBUG_KMS("\n");
f7d2323c 1698
1250d107 1699 _intel_edp_backlight_off(intel_dp);
f7d2323c 1700 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1701}
a4fc5ed6 1702
73580fb7
JN		 1703/*
1704 * Hook for controlling the panel power control backlight through the bl_power
1705 * sysfs attribute. Take care to handle multiple calls.
1706 */
1707static void intel_edp_backlight_power(struct intel_connector *connector,
1708 bool enable)
1709{
1710 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1711 bool is_enabled;
1712
773538e8 1713 pps_lock(intel_dp);
e39b999a 1714 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1715 pps_unlock(intel_dp);
73580fb7
JN		 1716
1717 if (is_enabled == enable)
1718 return;
1719
23ba9373
JN		 1720 DRM_DEBUG_KMS("panel power control backlight %s\n",
1721 enable ? "enable" : "disable");
73580fb7
JN		 1722
1723 if (enable)
1724 _intel_edp_backlight_on(intel_dp);
1725 else
1726 _intel_edp_backlight_off(intel_dp);
1727}
1728
2bd2ad64 1729static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1730{
da63a9f2
PZ		 1731 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1732 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1733 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1734 struct drm_i915_private *dev_priv = dev->dev_private;
1735 u32 dpa_ctl;
1736
2bd2ad64
DV		 1737 assert_pipe_disabled(dev_priv,
1738 to_intel_crtc(crtc)->pipe);
1739
d240f20f
JB		 1740 DRM_DEBUG_KMS("\n");
1741 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1742 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1743 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1744
1745 /* We don't adjust intel_dp->DP while tearing down the link, to
1746 * facilitate link retraining (e.g. after hotplug). Hence clear all
1747 * enable bits here to ensure that we don't enable too much. */
1748 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1749 intel_dp->DP |= DP_PLL_ENABLE;
1750 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1751 POSTING_READ(DP_A);
1752 udelay(200);
d240f20f
JB		 1753}
1754
2bd2ad64 1755static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1756{
da63a9f2
PZ		 1757 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1758 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1759 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1760 struct drm_i915_private *dev_priv = dev->dev_private;
1761 u32 dpa_ctl;
1762
2bd2ad64
DV		 1763 assert_pipe_disabled(dev_priv,
1764 to_intel_crtc(crtc)->pipe);
1765
d240f20f 1766 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1767 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1768 "dp pll off, should be on\n");
1769 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1770
1771 /* We can't rely on the value tracked for the DP register in
1772 * intel_dp->DP because link_down must not change that (otherwise link
1773 * re-training will fail. */
298b0b39 1774 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1775 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1776 POSTING_READ(DP_A);
d240f20f
JB		 1777 udelay(200);
1778}
1779
c7ad3810 1780/* If the sink supports it, try to set the power state appropriately */
c19b0669 1781void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1782{
1783 int ret, i;
1784
1785 /* Should have a valid DPCD by this point */
1786 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1787 return;
1788
1789 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1790 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1791 DP_SET_POWER_D3);
c7ad3810
JB		 1792 } else {
1793 /*
1794 * When turning on, we need to retry for 1ms to give the sink
1795 * time to wake up.
1796 */
1797 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1798 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1799 DP_SET_POWER_D0);
c7ad3810
JB		 1800 if (ret == 1)
1801 break;
1802 msleep(1);
1803 }
1804 }
f9cac721
JN		 1805
1806 if (ret != 1)
1807 DRM_DEBUG_KMS("failed to %s sink power state\n",
1808 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1809}
1810
19d8fe15
DV		 1811static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1812 enum pipe *pipe)
d240f20f 1813{
19d8fe15 1814 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1815 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1816 struct drm_device *dev = encoder->base.dev;
1817 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1818 enum intel_display_power_domain power_domain;
1819 u32 tmp;
1820
1821 power_domain = intel_display_port_power_domain(encoder);
1822 if (!intel_display_power_enabled(dev_priv, power_domain))
1823 return false;
1824
1825 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1826
1827 if (!(tmp & DP_PORT_EN))
1828 return false;
1829
bc7d38a4 1830 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1831 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1832 } else if (IS_CHERRYVIEW(dev)) {
1833 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1834 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1835 *pipe = PORT_TO_PIPE(tmp);
1836 } else {
1837 u32 trans_sel;
1838 u32 trans_dp;
1839 int i;
1840
1841 switch (intel_dp->output_reg) {
1842 case PCH_DP_B:
1843 trans_sel = TRANS_DP_PORT_SEL_B;
1844 break;
1845 case PCH_DP_C:
1846 trans_sel = TRANS_DP_PORT_SEL_C;
1847 break;
1848 case PCH_DP_D:
1849 trans_sel = TRANS_DP_PORT_SEL_D;
1850 break;
1851 default:
1852 return true;
1853 }
1854
055e393f 1855 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1856 trans_dp = I915_READ(TRANS_DP_CTL(i));
1857 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1858 *pipe = i;
1859 return true;
1860 }
1861 }
19d8fe15 1862
4a0833ec
DV		 1863 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1864 intel_dp->output_reg);
1865 }
d240f20f 1866
19d8fe15
DV		 1867 return true;
1868}
d240f20f 1869
045ac3b5
JB		 1870static void intel_dp_get_config(struct intel_encoder *encoder,
1871 struct intel_crtc_config *pipe_config)
1872{
1873 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1874 u32 tmp, flags = 0;
63000ef6
XZ		 1875 struct drm_device *dev = encoder->base.dev;
1876 struct drm_i915_private *dev_priv = dev->dev_private;
1877 enum port port = dp_to_dig_port(intel_dp)->port;
1878 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1879 int dotclock;
045ac3b5 1880
9ed109a7
DV		 1881 tmp = I915_READ(intel_dp->output_reg);
1882 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1883 pipe_config->has_audio = true;
1884
63000ef6 1885 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1886 if (tmp & DP_SYNC_HS_HIGH)
1887 flags |= DRM_MODE_FLAG_PHSYNC;
1888 else
1889 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1890
63000ef6
XZ		 1891 if (tmp & DP_SYNC_VS_HIGH)
1892 flags |= DRM_MODE_FLAG_PVSYNC;
1893 else
1894 flags |= DRM_MODE_FLAG_NVSYNC;
1895 } else {
1896 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1897 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1898 flags |= DRM_MODE_FLAG_PHSYNC;
1899 else
1900 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1901
63000ef6
XZ		 1902 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1903 flags |= DRM_MODE_FLAG_PVSYNC;
1904 else
1905 flags |= DRM_MODE_FLAG_NVSYNC;
1906 }
045ac3b5
JB		 1907
1908 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1909
eb14cb74
VS		 1910 pipe_config->has_dp_encoder = true;
1911
1912 intel_dp_get_m_n(crtc, pipe_config);
1913
18442d08 1914 if (port == PORT_A) {
f1f644dc
JB		 1915 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1916 pipe_config->port_clock = 162000;
1917 else
1918 pipe_config->port_clock = 270000;
1919 }
18442d08
VS		 1920
1921 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1922 &pipe_config->dp_m_n);
1923
1924 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1925 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1926
241bfc38 1927 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1928
c6cd2ee2
JN		 1929 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1930 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1931 /*
1932 * This is a big fat ugly hack.
1933 *
1934 * Some machines in UEFI boot mode provide us a VBT that has 18
1935 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1936 * unknown we fail to light up. Yet the same BIOS boots up with
1937 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1938 * max, not what it tells us to use.
1939 *
1940 * Note: This will still be broken if the eDP panel is not lit
1941 * up by the BIOS, and thus we can't get the mode at module
1942 * load.
1943 */
1944 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1945 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1946 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1947 }
045ac3b5
JB		 1948}
1949
34eb7579 1950static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1951{
34eb7579 1952 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1953}
1954
2b28bb1b
RV		 1955static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1956{
1957 struct drm_i915_private *dev_priv = dev->dev_private;
1958
18b5992c 1959 if (!HAS_PSR(dev))
2b28bb1b
RV		 1960 return false;
1961
18b5992c 1962 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1963}
1964
1965static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1966 struct edp_vsc_psr *vsc_psr)
1967{
1968 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1969 struct drm_device *dev = dig_port->base.base.dev;
1970 struct drm_i915_private *dev_priv = dev->dev_private;
1971 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1972 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1973 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1974 uint32_t *data = (uint32_t *) vsc_psr;
1975 unsigned int i;
1976
1977 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1978 the video DIP being updated before program video DIP data buffer
1979 registers for DIP being updated. */
1980 I915_WRITE(ctl_reg, 0);
1981 POSTING_READ(ctl_reg);
1982
1983 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1984 if (i < sizeof(struct edp_vsc_psr))
1985 I915_WRITE(data_reg + i, *data++);
1986 else
1987 I915_WRITE(data_reg + i, 0);
1988 }
1989
1990 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1991 POSTING_READ(ctl_reg);
1992}
1993
ba80f4d4 1994static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp)
2b28bb1b 1995{
2b28bb1b
RV		 1996 struct edp_vsc_psr psr_vsc;
1997
2b28bb1b
RV		 1998 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1999 memset(&psr_vsc, 0, sizeof(psr_vsc));
2000 psr_vsc.sdp_header.HB0 = 0;
2001 psr_vsc.sdp_header.HB1 = 0x7;
2002 psr_vsc.sdp_header.HB2 = 0x2;
2003 psr_vsc.sdp_header.HB3 = 0x8;
2004 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2b28bb1b
RV		 2005}
2006
2007static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2008{
0e0ae652
RV		 2009 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2010 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 2011 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 2012 uint32_t aux_clock_divider;
2b28bb1b
RV		 2013 int precharge = 0x3;
2014 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 2015 bool only_standby = false;
2b28bb1b 2016
ec5b01dd
DL		 2017 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2018
0e0ae652
RV		 2019 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2020 only_standby = true;
2021
2b28bb1b 2022 /* Enable PSR in sink */
0e0ae652 2023 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 2024 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2025 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 2026 else
9d1a1031
JN		 2027 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2028 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 2029
2030 /* Setup AUX registers */
18b5992c
BW		 2031 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
2032 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
2033 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 2034 DP_AUX_CH_CTL_TIME_OUT_400us |
2035 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2036 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2037 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2038}
2039
2040static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2041{
0e0ae652
RV		 2042 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2043 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 2044 struct drm_i915_private *dev_priv = dev->dev_private;
2045 uint32_t max_sleep_time = 0x1f;
2046 uint32_t idle_frames = 1;
2047 uint32_t val = 0x0;
ed8546ac 2048 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 2049 bool only_standby = false;
2050
2051 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2052 only_standby = true;
2b28bb1b 2053
0e0ae652 2054 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 2055 val |= EDP_PSR_LINK_STANDBY;
2056 val |= EDP_PSR_TP2_TP3_TIME_0us;
2057 val |= EDP_PSR_TP1_TIME_0us;
2058 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 2059 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 2060 } else
2061 val |= EDP_PSR_LINK_DISABLE;
2062
18b5992c 2063 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 2064 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 2065 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2066 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2067 EDP_PSR_ENABLE);
2068}
2069
3f51e471
RV		 2070static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2071{
2072 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2073 struct drm_device *dev = dig_port->base.base.dev;
2074 struct drm_i915_private *dev_priv = dev->dev_private;
2075 struct drm_crtc *crtc = dig_port->base.base.crtc;
2076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 2077
f0355c4a 2078 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 2079 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2080 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2081
a031d709
RV		 2082 dev_priv->psr.source_ok = false;
2083
9ca15301 2084 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 2085 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 2086 return false;
2087 }
2088
d330a953 2089 if (!i915.enable_psr) {
105b7c11 2090 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 2091 return false;
2092 }
2093
4c8c7000
RV		 2094 /* Below limitations aren't valid for Broadwell */
2095 if (IS_BROADWELL(dev))
2096 goto out;
2097
3f51e471
RV		 2098 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2099 S3D_ENABLE) {
2100 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 2101 return false;
2102 }
2103
ca73b4f0 2104 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 2105 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 2106 return false;
2107 }
2108
4c8c7000 2109 out:
a031d709 2110 dev_priv->psr.source_ok = true;
3f51e471
RV		 2111 return true;
2112}
2113
3d739d92 2114static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 2115{
7c8f8a70
RV		 2116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2117 struct drm_device *dev = intel_dig_port->base.base.dev;
2118 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 2119
3638379c
DV		 2120 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2121 WARN_ON(dev_priv->psr.active);
f0355c4a 2122 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 2123
2b28bb1b
RV		 2124 /* Enable PSR on the panel */
2125 intel_edp_psr_enable_sink(intel_dp);
2126
2127 /* Enable PSR on the host */
2128 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 2129
7c8f8a70 2130 dev_priv->psr.active = true;
2b28bb1b
RV		 2131}
2132
3d739d92
RV		 2133void intel_edp_psr_enable(struct intel_dp *intel_dp)
2134{
2135 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 2136 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 2137
4704c573
RV		 2138 if (!HAS_PSR(dev)) {
2139 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2140 return;
2141 }
2142
34eb7579
RV		 2143 if (!is_edp_psr(intel_dp)) {
2144 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2145 return;
2146 }
2147
f0355c4a 2148 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 2149 if (dev_priv->psr.enabled) {
2150 DRM_DEBUG_KMS("PSR already in use\n");
0aa48783 2151 goto unlock;
109fc2ad
DV		 2152 }
2153
0aa48783
RV		 2154 if (!intel_edp_psr_match_conditions(intel_dp))
2155 goto unlock;
2156
9ca15301
DV		 2157 dev_priv->psr.busy_frontbuffer_bits = 0;
2158
ba80f4d4
RV		 2159 intel_edp_psr_setup_vsc(intel_dp);
2160
2161 /* Avoid continuous PSR exit by masking memup and hpd */
2162 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
2163 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
16487254 2164
0aa48783
RV		 2165 dev_priv->psr.enabled = intel_dp;
2166unlock:
f0355c4a 2167 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2168}
2169
2b28bb1b
RV		 2170void intel_edp_psr_disable(struct intel_dp *intel_dp)
2171{
2172 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2173 struct drm_i915_private *dev_priv = dev->dev_private;
2174
f0355c4a
DV		 2175 mutex_lock(&dev_priv->psr.lock);
2176 if (!dev_priv->psr.enabled) {
2177 mutex_unlock(&dev_priv->psr.lock);
2178 return;
2179 }
2180
3638379c
DV		 2181 if (dev_priv->psr.active) {
2182 I915_WRITE(EDP_PSR_CTL(dev),
2183 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2184
2185 /* Wait till PSR is idle */
2186 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2187 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2188 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2189
3638379c
DV		 2190 dev_priv->psr.active = false;
2191 } else {
2192 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2193 }
7c8f8a70 2194
2807cf69 2195 dev_priv->psr.enabled = NULL;
f0355c4a 2196 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2197
2198 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2199}
2200
f02a326e 2201static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2202{
2203 struct drm_i915_private *dev_priv =
2204 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2205 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2206
f0355c4a
DV		 2207 mutex_lock(&dev_priv->psr.lock);
2208 intel_dp = dev_priv->psr.enabled;
2209
2807cf69 2210 if (!intel_dp)
f0355c4a 2211 goto unlock;
2807cf69 2212
9ca15301
DV		 2213 /*
2214 * The delayed work can race with an invalidate hence we need to
2215 * recheck. Since psr_flush first clears this and then reschedules we
2216 * won't ever miss a flush when bailing out here.
2217 */
2218 if (dev_priv->psr.busy_frontbuffer_bits)
2219 goto unlock;
2220
2221 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2222unlock:
2223 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2224}
2225
9ca15301 2226static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2227{
2228 struct drm_i915_private *dev_priv = dev->dev_private;
2229
3638379c
DV		 2230 if (dev_priv->psr.active) {
2231 u32 val = I915_READ(EDP_PSR_CTL(dev));
2232
2233 WARN_ON(!(val & EDP_PSR_ENABLE));
2234
2235 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2236
2237 dev_priv->psr.active = false;
2238 }
7c8f8a70 2239
9ca15301
DV		 2240}
2241
2242void intel_edp_psr_invalidate(struct drm_device *dev,
2243 unsigned frontbuffer_bits)
2244{
2245 struct drm_i915_private *dev_priv = dev->dev_private;
2246 struct drm_crtc *crtc;
2247 enum pipe pipe;
2248
9ca15301
DV		 2249 mutex_lock(&dev_priv->psr.lock);
2250 if (!dev_priv->psr.enabled) {
2251 mutex_unlock(&dev_priv->psr.lock);
2252 return;
2253 }
2254
2255 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2256 pipe = to_intel_crtc(crtc)->pipe;
2257
2258 intel_edp_psr_do_exit(dev);
2259
2260 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2261
2262 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2263 mutex_unlock(&dev_priv->psr.lock);
2264}
2265
2266void intel_edp_psr_flush(struct drm_device *dev,
2267 unsigned frontbuffer_bits)
2268{
2269 struct drm_i915_private *dev_priv = dev->dev_private;
2270 struct drm_crtc *crtc;
2271 enum pipe pipe;
2272
9ca15301
DV		 2273 mutex_lock(&dev_priv->psr.lock);
2274 if (!dev_priv->psr.enabled) {
2275 mutex_unlock(&dev_priv->psr.lock);
2276 return;
2277 }
2278
2279 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2280 pipe = to_intel_crtc(crtc)->pipe;
2281 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2282
2283 /*
2284 * On Haswell sprite plane updates don't result in a psr invalidating
2285 * signal in the hardware. Which means we need to manually fake this in
2286 * software for all flushes, not just when we've seen a preceding
2287 * invalidation through frontbuffer rendering.
2288 */
2289 if (IS_HASWELL(dev) &&
2290 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2291 intel_edp_psr_do_exit(dev);
2292
2293 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2294 schedule_delayed_work(&dev_priv->psr.work,
2295 msecs_to_jiffies(100));
f0355c4a 2296 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2297}
2298
2299void intel_edp_psr_init(struct drm_device *dev)
2300{
2301 struct drm_i915_private *dev_priv = dev->dev_private;
2302
7c8f8a70 2303 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2304 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2305}
2306
e8cb4558 2307static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2308{
e8cb4558 2309 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2310 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2311
2312 /* Make sure the panel is off before trying to change the mode. But also
2313 * ensure that we have vdd while we switch off the panel. */
24f3e092 2314 intel_edp_panel_vdd_on(intel_dp);
4be73780 2315 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2316 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2317 intel_edp_panel_off(intel_dp);
3739850b 2318
08aff3fe
VS		 2319 /* disable the port before the pipe on g4x */
2320 if (INTEL_INFO(dev)->gen < 5)
3739850b 2321 intel_dp_link_down(intel_dp);
d240f20f
JB		 2322}
2323
08aff3fe 2324static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2325{
2bd2ad64 2326 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2327 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2328
49277c31 2329 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2330 if (port == PORT_A)
2331 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2332}
2333
2334static void vlv_post_disable_dp(struct intel_encoder *encoder)
2335{
2336 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2337
2338 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2339}
2340
580d3811
VS		 2341static void chv_post_disable_dp(struct intel_encoder *encoder)
2342{
2343 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2344 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2345 struct drm_device *dev = encoder->base.dev;
2346 struct drm_i915_private *dev_priv = dev->dev_private;
2347 struct intel_crtc *intel_crtc =
2348 to_intel_crtc(encoder->base.crtc);
2349 enum dpio_channel ch = vlv_dport_to_channel(dport);
2350 enum pipe pipe = intel_crtc->pipe;
2351 u32 val;
2352
2353 intel_dp_link_down(intel_dp);
2354
2355 mutex_lock(&dev_priv->dpio_lock);
2356
2357 /* Propagate soft reset to data lane reset */
97fd4d5c 2358 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2359 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2360 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2361
97fd4d5c
VS		 2362 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2363 val |= CHV_PCS_REQ_SOFTRESET_EN;
2364 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2365
2366 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2367 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2368 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2369
2370 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2371 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2372 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2373
2374 mutex_unlock(&dev_priv->dpio_lock);
2375}
2376
7b13b58a
VS		 2377static void
2378_intel_dp_set_link_train(struct intel_dp *intel_dp,
2379 uint32_t *DP,
2380 uint8_t dp_train_pat)
2381{
2382 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2383 struct drm_device *dev = intel_dig_port->base.base.dev;
2384 struct drm_i915_private *dev_priv = dev->dev_private;
2385 enum port port = intel_dig_port->port;
2386
2387 if (HAS_DDI(dev)) {
2388 uint32_t temp = I915_READ(DP_TP_CTL(port));
2389
2390 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2391 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2392 else
2393 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2394
2395 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2396 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2397 case DP_TRAINING_PATTERN_DISABLE:
2398 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2399
2400 break;
2401 case DP_TRAINING_PATTERN_1:
2402 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2403 break;
2404 case DP_TRAINING_PATTERN_2:
2405 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2406 break;
2407 case DP_TRAINING_PATTERN_3:
2408 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2409 break;
2410 }
2411 I915_WRITE(DP_TP_CTL(port), temp);
2412
2413 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2414 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2415
2416 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2417 case DP_TRAINING_PATTERN_DISABLE:
2418 *DP |= DP_LINK_TRAIN_OFF_CPT;
2419 break;
2420 case DP_TRAINING_PATTERN_1:
2421 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2422 break;
2423 case DP_TRAINING_PATTERN_2:
2424 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2425 break;
2426 case DP_TRAINING_PATTERN_3:
2427 DRM_ERROR("DP training pattern 3 not supported\n");
2428 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2429 break;
2430 }
2431
2432 } else {
2433 if (IS_CHERRYVIEW(dev))
2434 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2435 else
2436 *DP &= ~DP_LINK_TRAIN_MASK;
2437
2438 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2439 case DP_TRAINING_PATTERN_DISABLE:
2440 *DP |= DP_LINK_TRAIN_OFF;
2441 break;
2442 case DP_TRAINING_PATTERN_1:
2443 *DP |= DP_LINK_TRAIN_PAT_1;
2444 break;
2445 case DP_TRAINING_PATTERN_2:
2446 *DP |= DP_LINK_TRAIN_PAT_2;
2447 break;
2448 case DP_TRAINING_PATTERN_3:
2449 if (IS_CHERRYVIEW(dev)) {
2450 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2451 } else {
2452 DRM_ERROR("DP training pattern 3 not supported\n");
2453 *DP |= DP_LINK_TRAIN_PAT_2;
2454 }
2455 break;
2456 }
2457 }
2458}
2459
2460static void intel_dp_enable_port(struct intel_dp *intel_dp)
2461{
2462 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2463 struct drm_i915_private *dev_priv = dev->dev_private;
2464
2465 intel_dp->DP |= DP_PORT_EN;
2466
2467 /* enable with pattern 1 (as per spec) */
2468 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2469 DP_TRAINING_PATTERN_1);
2470
2471 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2472 POSTING_READ(intel_dp->output_reg);
2473}
2474
e8cb4558 2475static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2476{
e8cb4558
DV		 2477 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2478 struct drm_device *dev = encoder->base.dev;
2479 struct drm_i915_private *dev_priv = dev->dev_private;
2480 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2481
0c33d8d7
DV		 2482 if (WARN_ON(dp_reg & DP_PORT_EN))
2483 return;
5d613501 2484
7b13b58a 2485 intel_dp_enable_port(intel_dp);
24f3e092 2486 intel_edp_panel_vdd_on(intel_dp);
4be73780 2487 intel_edp_panel_on(intel_dp);
1e0560e0 2488 intel_edp_panel_vdd_off(intel_dp, true);
f01eca2e 2489 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2490 intel_dp_start_link_train(intel_dp);
33a34e4e 2491 intel_dp_complete_link_train(intel_dp);
3ab9c637 2492 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2493}
89b667f8 2494
ecff4f3b
JN		 2495static void g4x_enable_dp(struct intel_encoder *encoder)
2496{
828f5c6e
JN		 2497 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2498
ecff4f3b 2499 intel_enable_dp(encoder);
4be73780 2500 intel_edp_backlight_on(intel_dp);
ab1f90f9 2501}
89b667f8 2502
ab1f90f9
JN		 2503static void vlv_enable_dp(struct intel_encoder *encoder)
2504{
828f5c6e
JN		 2505 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2506
4be73780 2507 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2508}
2509
ecff4f3b 2510static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2511{
2512 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2513 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2514
8ac33ed3
DV		 2515 intel_dp_prepare(encoder);
2516
d41f1efb
DV		 2517 /* Only ilk+ has port A */
2518 if (dport->port == PORT_A) {
2519 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2520 ironlake_edp_pll_on(intel_dp);
d41f1efb 2521 }
ab1f90f9
JN		 2522}
2523
a4a5d2f8
VS		 2524static void vlv_steal_power_sequencer(struct drm_device *dev,
2525 enum pipe pipe)
2526{
2527 struct drm_i915_private *dev_priv = dev->dev_private;
2528 struct intel_encoder *encoder;
2529
2530 lockdep_assert_held(&dev_priv->pps_mutex);
2531
2532 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2533 base.head) {
2534 struct intel_dp *intel_dp;
773538e8 2535 enum port port;
a4a5d2f8
VS		 2536
2537 if (encoder->type != INTEL_OUTPUT_EDP)
2538 continue;
2539
2540 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2541 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2542
2543 if (intel_dp->pps_pipe != pipe)
2544 continue;
2545
2546 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2547 pipe_name(pipe), port_name(port));
a4a5d2f8
VS		 2548
2549 /* make sure vdd is off before we steal it */
2550 edp_panel_vdd_off_sync(intel_dp);
2551
2552 intel_dp->pps_pipe = INVALID_PIPE;
2553 }
2554}
2555
2556static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2557{
2558 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2559 struct intel_encoder *encoder = &intel_dig_port->base;
2560 struct drm_device *dev = encoder->base.dev;
2561 struct drm_i915_private *dev_priv = dev->dev_private;
2562 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2563 struct edp_power_seq power_seq;
2564
2565 lockdep_assert_held(&dev_priv->pps_mutex);
2566
2567 if (intel_dp->pps_pipe == crtc->pipe)
2568 return;
2569
2570 /*
2571 * If another power sequencer was being used on this
2572 * port previously make sure to turn off vdd there while
2573 * we still have control of it.
2574 */
2575 if (intel_dp->pps_pipe != INVALID_PIPE)
2576 edp_panel_vdd_off_sync(intel_dp);
2577
2578 /*
2579 * We may be stealing the power
2580 * sequencer from another port.
2581 */
2582 vlv_steal_power_sequencer(dev, crtc->pipe);
2583
2584 /* now it's all ours */
2585 intel_dp->pps_pipe = crtc->pipe;
2586
2587 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2588 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2589
2590 /* init power sequencer on this pipe and port */
2591 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2592 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2593 &power_seq);
2594}
2595
ab1f90f9 2596static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2597{
2bd2ad64 2598 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2599 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2600 struct drm_device *dev = encoder->base.dev;
89b667f8 2601 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2602 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2603 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2604 int pipe = intel_crtc->pipe;
2605 u32 val;
a4fc5ed6 2606
ab1f90f9 2607 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2608
ab3c759a 2609 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2610 val = 0;
2611 if (pipe)
2612 val |= (1<<21);
2613 else
2614 val &= ~(1<<21);
2615 val |= 0x001000c4;
ab3c759a
CML		 2616 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2617 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2618 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2619
ab1f90f9
JN		 2620 mutex_unlock(&dev_priv->dpio_lock);
2621
2cac613b 2622 if (is_edp(intel_dp)) {
773538e8 2623 pps_lock(intel_dp);
a4a5d2f8 2624 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2625 pps_unlock(intel_dp);
2cac613b 2626 }
bf13e81b 2627
ab1f90f9
JN		 2628 intel_enable_dp(encoder);
2629
e4607fcf 2630 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2631}
2632
ecff4f3b 2633static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2634{
2635 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2636 struct drm_device *dev = encoder->base.dev;
2637 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2638 struct intel_crtc *intel_crtc =
2639 to_intel_crtc(encoder->base.crtc);
e4607fcf 2640 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2641 int pipe = intel_crtc->pipe;
89b667f8 2642
8ac33ed3
DV		 2643 intel_dp_prepare(encoder);
2644
89b667f8 2645 /* Program Tx lane resets to default */
0980a60f 2646 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2647 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2648 DPIO_PCS_TX_LANE2_RESET |
2649 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2650 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2651 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2652 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2653 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2654 DPIO_PCS_CLK_SOFT_RESET);
2655
2656 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2657 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2658 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2659 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2660 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2661}
2662
e4a1d846
CML		 2663static void chv_pre_enable_dp(struct intel_encoder *encoder)
2664{
2665 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2666 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2667 struct drm_device *dev = encoder->base.dev;
2668 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2669 struct intel_crtc *intel_crtc =
2670 to_intel_crtc(encoder->base.crtc);
2671 enum dpio_channel ch = vlv_dport_to_channel(dport);
2672 int pipe = intel_crtc->pipe;
2673 int data, i;
949c1d43 2674 u32 val;
e4a1d846 2675
e4a1d846 2676 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2677
2678 /* Deassert soft data lane reset*/
97fd4d5c 2679 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2680 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2681 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2682
2683 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2684 val |= CHV_PCS_REQ_SOFTRESET_EN;
2685 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2686
2687 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2688 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2689 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2690
97fd4d5c 2691 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2692 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2693 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2694
2695 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2696 for (i = 0; i < 4; i++) {
2697 /* Set the latency optimal bit */
2698 data = (i == 1) ? 0x0 : 0x6;
2699 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2700 data << DPIO_FRC_LATENCY_SHFIT);
2701
2702 /* Set the upar bit */
2703 data = (i == 1) ? 0x0 : 0x1;
2704 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2705 data << DPIO_UPAR_SHIFT);
2706 }
2707
2708 /* Data lane stagger programming */
2709 /* FIXME: Fix up value only after power analysis */
2710
2711 mutex_unlock(&dev_priv->dpio_lock);
2712
2713 if (is_edp(intel_dp)) {
773538e8 2714 pps_lock(intel_dp);
a4a5d2f8 2715 vlv_init_panel_power_sequencer(intel_dp);
773538e8 2716 pps_unlock(intel_dp);
e4a1d846
CML		 2717 }
2718
2719 intel_enable_dp(encoder);
2720
2721 vlv_wait_port_ready(dev_priv, dport);
2722}
2723
9197c88b
VS		 2724static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2725{
2726 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2727 struct drm_device *dev = encoder->base.dev;
2728 struct drm_i915_private *dev_priv = dev->dev_private;
2729 struct intel_crtc *intel_crtc =
2730 to_intel_crtc(encoder->base.crtc);
2731 enum dpio_channel ch = vlv_dport_to_channel(dport);
2732 enum pipe pipe = intel_crtc->pipe;
2733 u32 val;
2734
625695f8
VS		 2735 intel_dp_prepare(encoder);
2736
9197c88b
VS		 2737 mutex_lock(&dev_priv->dpio_lock);
2738
b9e5ac3c
VS		 2739 /* program left/right clock distribution */
2740 if (pipe != PIPE_B) {
2741 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2742 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2743 if (ch == DPIO_CH0)
2744 val |= CHV_BUFLEFTENA1_FORCE;
2745 if (ch == DPIO_CH1)
2746 val |= CHV_BUFRIGHTENA1_FORCE;
2747 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2748 } else {
2749 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2750 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2751 if (ch == DPIO_CH0)
2752 val |= CHV_BUFLEFTENA2_FORCE;
2753 if (ch == DPIO_CH1)
2754 val |= CHV_BUFRIGHTENA2_FORCE;
2755 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2756 }
2757
9197c88b
VS		 2758 /* program clock channel usage */
2759 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2760 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2761 if (pipe != PIPE_B)
2762 val &= ~CHV_PCS_USEDCLKCHANNEL;
2763 else
2764 val |= CHV_PCS_USEDCLKCHANNEL;
2765 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2766
2767 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2768 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2769 if (pipe != PIPE_B)
2770 val &= ~CHV_PCS_USEDCLKCHANNEL;
2771 else
2772 val |= CHV_PCS_USEDCLKCHANNEL;
2773 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2774
2775 /*
2776 * This a a bit weird since generally CL
2777 * matches the pipe, but here we need to
2778 * pick the CL based on the port.
2779 */
2780 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2781 if (pipe != PIPE_B)
2782 val &= ~CHV_CMN_USEDCLKCHANNEL;
2783 else
2784 val |= CHV_CMN_USEDCLKCHANNEL;
2785 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2786
2787 mutex_unlock(&dev_priv->dpio_lock);
2788}
2789
a4fc5ed6 2790/*
df0c237d
JB		 2791 * Native read with retry for link status and receiver capability reads for
2792 * cases where the sink may still be asleep.
9d1a1031
JN		 2793 *
2794 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2795 * supposed to retry 3 times per the spec.
a4fc5ed6 2796 */
9d1a1031
JN		 2797static ssize_t
2798intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2799 void *buffer, size_t size)
a4fc5ed6 2800{
9d1a1031
JN		 2801 ssize_t ret;
2802 int i;
61da5fab 2803
61da5fab 2804 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2805 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2806 if (ret == size)
2807 return ret;
61da5fab
JB		 2808 msleep(1);
2809 }
a4fc5ed6 2810
9d1a1031 2811 return ret;
a4fc5ed6
KP		 2812}
2813
2814/*
2815 * Fetch AUX CH registers 0x202 - 0x207 which contain
2816 * link status information
2817 */
2818static bool
93f62dad 2819intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2820{
9d1a1031
JN		 2821 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2822 DP_LANE0_1_STATUS,
2823 link_status,
2824 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2825}
2826
1100244e 2827/* These are source-specific values. */
a4fc5ed6 2828static uint8_t
1a2eb460 2829intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2830{
30add22d 2831 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2832 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2833
9576c27f 2834 if (IS_VALLEYVIEW(dev))
bd60018a 2835 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2836 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2837 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2838 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2839 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2840 else
bd60018a 2841 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2842}
2843
2844static uint8_t
2845intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2846{
30add22d 2847 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2848 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2849
9576c27f 2850 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2851 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2852 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2853 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2854 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2855 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2856 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2857 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2858 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2859 default:
bd60018a 2860 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2861 }
e2fa6fba
P		 2862 } else if (IS_VALLEYVIEW(dev)) {
2863 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2864 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2865 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2866 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2867 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2868 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2869 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2870 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2871 default:
bd60018a 2872 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2873 }
bc7d38a4 2874 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2875 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2876 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2877 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2878 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2879 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2880 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2881 default:
bd60018a 2882 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2883 }
2884 } else {
2885 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2886 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2887 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2888 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2889 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2890 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2891 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2892 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2893 default:
bd60018a 2894 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2895 }
a4fc5ed6
KP		 2896 }
2897}
2898
e2fa6fba
P		 2899static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2900{
2901 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2902 struct drm_i915_private *dev_priv = dev->dev_private;
2903 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2904 struct intel_crtc *intel_crtc =
2905 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2906 unsigned long demph_reg_value, preemph_reg_value,
2907 uniqtranscale_reg_value;
2908 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2909 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2910 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2911
2912 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2913 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2914 preemph_reg_value = 0x0004000;
2915 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2916 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2917 demph_reg_value = 0x2B405555;
2918 uniqtranscale_reg_value = 0x552AB83A;
2919 break;
bd60018a 2920 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2921 demph_reg_value = 0x2B404040;
2922 uniqtranscale_reg_value = 0x5548B83A;
2923 break;
bd60018a 2924 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2925 demph_reg_value = 0x2B245555;
2926 uniqtranscale_reg_value = 0x5560B83A;
2927 break;
bd60018a 2928 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2929 demph_reg_value = 0x2B405555;
2930 uniqtranscale_reg_value = 0x5598DA3A;
2931 break;
2932 default:
2933 return 0;
2934 }
2935 break;
bd60018a 2936 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2937 preemph_reg_value = 0x0002000;
2938 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2939 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2940 demph_reg_value = 0x2B404040;
2941 uniqtranscale_reg_value = 0x5552B83A;
2942 break;
bd60018a 2943 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2944 demph_reg_value = 0x2B404848;
2945 uniqtranscale_reg_value = 0x5580B83A;
2946 break;
bd60018a 2947 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2948 demph_reg_value = 0x2B404040;
2949 uniqtranscale_reg_value = 0x55ADDA3A;
2950 break;
2951 default:
2952 return 0;
2953 }
2954 break;
bd60018a 2955 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 2956 preemph_reg_value = 0x0000000;
2957 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2958 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2959 demph_reg_value = 0x2B305555;
2960 uniqtranscale_reg_value = 0x5570B83A;
2961 break;
bd60018a 2962 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2963 demph_reg_value = 0x2B2B4040;
2964 uniqtranscale_reg_value = 0x55ADDA3A;
2965 break;
2966 default:
2967 return 0;
2968 }
2969 break;
bd60018a 2970 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 2971 preemph_reg_value = 0x0006000;
2972 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2973 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2974 demph_reg_value = 0x1B405555;
2975 uniqtranscale_reg_value = 0x55ADDA3A;
2976 break;
2977 default:
2978 return 0;
2979 }
2980 break;
2981 default:
2982 return 0;
2983 }
2984
0980a60f 2985 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2986 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2987 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2988 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2989 uniqtranscale_reg_value);
ab3c759a
CML		 2990 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2991 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2992 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2993 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2994 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2995
2996 return 0;
2997}
2998
e4a1d846
CML		 2999static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3000{
3001 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3002 struct drm_i915_private *dev_priv = dev->dev_private;
3003 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3004 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3005 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3006 uint8_t train_set = intel_dp->train_set[0];
3007 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3008 enum pipe pipe = intel_crtc->pipe;
3009 int i;
e4a1d846
CML		 3010
3011 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3012 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3013 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3014 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3015 deemph_reg_value = 128;
3016 margin_reg_value = 52;
3017 break;
bd60018a 3018 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3019 deemph_reg_value = 128;
3020 margin_reg_value = 77;
3021 break;
bd60018a 3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3023 deemph_reg_value = 128;
3024 margin_reg_value = 102;
3025 break;
bd60018a 3026 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3027 deemph_reg_value = 128;
3028 margin_reg_value = 154;
3029 /* FIXME extra to set for 1200 */
3030 break;
3031 default:
3032 return 0;
3033 }
3034 break;
bd60018a 3035 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3036 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3037 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3038 deemph_reg_value = 85;
3039 margin_reg_value = 78;
3040 break;
bd60018a 3041 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3042 deemph_reg_value = 85;
3043 margin_reg_value = 116;
3044 break;
bd60018a 3045 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3046 deemph_reg_value = 85;
3047 margin_reg_value = 154;
3048 break;
3049 default:
3050 return 0;
3051 }
3052 break;
bd60018a 3053 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3054 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3055 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3056 deemph_reg_value = 64;
3057 margin_reg_value = 104;
3058 break;
bd60018a 3059 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3060 deemph_reg_value = 64;
3061 margin_reg_value = 154;
3062 break;
3063 default:
3064 return 0;
3065 }
3066 break;
bd60018a 3067 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3068 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3069 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3070 deemph_reg_value = 43;
3071 margin_reg_value = 154;
3072 break;
3073 default:
3074 return 0;
3075 }
3076 break;
3077 default:
3078 return 0;
3079 }
3080
3081 mutex_lock(&dev_priv->dpio_lock);
3082
3083 /* Clear calc init */
1966e59e
VS		 3084 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3085 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3086 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3087
3088 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3089 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3090 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3091
3092 /* Program swing deemph */
f72df8db
VS		 3093 for (i = 0; i < 4; i++) {
3094 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3095 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3096 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3097 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3098 }
e4a1d846
CML		 3099
3100 /* Program swing margin */
f72df8db
VS		 3101 for (i = 0; i < 4; i++) {
3102 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3103 val &= ~DPIO_SWING_MARGIN000_MASK;
3104 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3105 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3106 }
e4a1d846
CML		 3107
3108 /* Disable unique transition scale */
f72df8db
VS		 3109 for (i = 0; i < 4; i++) {
3110 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3111 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3112 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3113 }
e4a1d846
CML		 3114
3115 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3116 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3117 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3118 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3119
3120 /*
3121 * The document said it needs to set bit 27 for ch0 and bit 26
3122 * for ch1. Might be a typo in the doc.
3123 * For now, for this unique transition scale selection, set bit
3124 * 27 for ch0 and ch1.
3125 */
f72df8db
VS		 3126 for (i = 0; i < 4; i++) {
3127 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3128 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3129 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3130 }
e4a1d846 3131
f72df8db
VS		 3132 for (i = 0; i < 4; i++) {
3133 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3134 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3135 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3136 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3137 }
e4a1d846
CML		 3138 }
3139
3140 /* Start swing calculation */
1966e59e
VS		 3141 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3142 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3143 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3144
3145 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3146 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3147 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3148
3149 /* LRC Bypass */
3150 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3151 val |= DPIO_LRC_BYPASS;
3152 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3153
3154 mutex_unlock(&dev_priv->dpio_lock);
3155
3156 return 0;
3157}
3158
a4fc5ed6 3159static void
0301b3ac
JN		 3160intel_get_adjust_train(struct intel_dp *intel_dp,
3161 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3162{
3163 uint8_t v = 0;
3164 uint8_t p = 0;
3165 int lane;
1a2eb460
KP		 3166 uint8_t voltage_max;
3167 uint8_t preemph_max;
a4fc5ed6 3168
33a34e4e 3169 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3170 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3171 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3172
3173 if (this_v > v)
3174 v = this_v;
3175 if (this_p > p)
3176 p = this_p;
3177 }
3178
1a2eb460 3179 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3180 if (v >= voltage_max)
3181 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3182
1a2eb460
KP		 3183 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3184 if (p >= preemph_max)
3185 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3186
3187 for (lane = 0; lane < 4; lane++)
33a34e4e 3188 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3189}
3190
3191static uint32_t
f0a3424e 3192intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3193{
3cf2efb1 3194 uint32_t signal_levels = 0;
a4fc5ed6 3195
3cf2efb1 3196 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3197 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3198 default:
3199 signal_levels |= DP_VOLTAGE_0_4;
3200 break;
bd60018a 3201 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3202 signal_levels |= DP_VOLTAGE_0_6;
3203 break;
bd60018a 3204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3205 signal_levels |= DP_VOLTAGE_0_8;
3206 break;
bd60018a 3207 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3208 signal_levels |= DP_VOLTAGE_1_2;
3209 break;
3210 }
3cf2efb1 3211 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3212 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3213 default:
3214 signal_levels |= DP_PRE_EMPHASIS_0;
3215 break;
bd60018a 3216 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3217 signal_levels |= DP_PRE_EMPHASIS_3_5;
3218 break;
bd60018a 3219 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3220 signal_levels |= DP_PRE_EMPHASIS_6;
3221 break;
bd60018a 3222 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3223 signal_levels |= DP_PRE_EMPHASIS_9_5;
3224 break;
3225 }
3226 return signal_levels;
3227}
3228
e3421a18
ZW		 3229/* Gen6's DP voltage swing and pre-emphasis control */
3230static uint32_t
3231intel_gen6_edp_signal_levels(uint8_t train_set)
3232{
3c5a62b5
YL		 3233 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3234 DP_TRAIN_PRE_EMPHASIS_MASK);
3235 switch (signal_levels) {
bd60018a
SJ		 3236 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3237 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3238 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3239 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3240 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3241 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3243 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3244 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3245 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3246 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3247 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3248 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3249 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3250 default:
3c5a62b5
YL		 3251 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3252 "0x%x\n", signal_levels);
3253 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3254 }
3255}
3256
1a2eb460
KP		 3257/* Gen7's DP voltage swing and pre-emphasis control */
3258static uint32_t
3259intel_gen7_edp_signal_levels(uint8_t train_set)
3260{
3261 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3262 DP_TRAIN_PRE_EMPHASIS_MASK);
3263 switch (signal_levels) {
bd60018a 3264 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3265 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3266 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3267 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3268 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3269 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3270
bd60018a 3271 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3272 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3273 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3274 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3275
bd60018a 3276 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3277 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3278 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3279 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3280
3281 default:
3282 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3283 "0x%x\n", signal_levels);
3284 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3285 }
3286}
3287
d6c0d722
PZ		 3288/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3289static uint32_t
f0a3424e 3290intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3291{
d6c0d722
PZ		 3292 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3293 DP_TRAIN_PRE_EMPHASIS_MASK);
3294 switch (signal_levels) {
bd60018a 3295 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3296 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3297 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3298 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3299 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3300 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3301 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3302 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3303
bd60018a 3304 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3305 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3306 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3307 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3308 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3309 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3310
bd60018a 3311 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3312 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3313 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3314 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3315 default:
3316 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3317 "0x%x\n", signal_levels);
c5fe6a06 3318 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3319 }
a4fc5ed6
KP		 3320}
3321
f0a3424e
PZ		 3322/* Properly updates "DP" with the correct signal levels. */
3323static void
3324intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3325{
3326 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3327 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3328 struct drm_device *dev = intel_dig_port->base.base.dev;
3329 uint32_t signal_levels, mask;
3330 uint8_t train_set = intel_dp->train_set[0];
3331
9576c27f 3332 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 3333 signal_levels = intel_hsw_signal_levels(train_set);
3334 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3335 } else if (IS_CHERRYVIEW(dev)) {
3336 signal_levels = intel_chv_signal_levels(intel_dp);
3337 mask = 0;
e2fa6fba
P		 3338 } else if (IS_VALLEYVIEW(dev)) {
3339 signal_levels = intel_vlv_signal_levels(intel_dp);
3340 mask = 0;
bc7d38a4 3341 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3342 signal_levels = intel_gen7_edp_signal_levels(train_set);
3343 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3344 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3345 signal_levels = intel_gen6_edp_signal_levels(train_set);
3346 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3347 } else {
3348 signal_levels = intel_gen4_signal_levels(train_set);
3349 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3350 }
3351
3352 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3353
3354 *DP = (*DP & ~mask) | signal_levels;
3355}
3356
a4fc5ed6 3357static bool
ea5b213a 3358intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3359 uint32_t *DP,
58e10eb9 3360 uint8_t dp_train_pat)
a4fc5ed6 3361{
174edf1f
PZ		 3362 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3363 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3364 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3365 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3366 int ret, len;
a4fc5ed6 3367
7b13b58a 3368 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3369
70aff66c 3370 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3371 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3372
2cdfe6c8
JN		 3373 buf[0] = dp_train_pat;
3374 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3375 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3376 /* don't write DP_TRAINING_LANEx_SET on disable */
3377 len = 1;
3378 } else {
3379 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3380 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3381 len = intel_dp->lane_count + 1;
47ea7542 3382 }
a4fc5ed6 3383
9d1a1031
JN		 3384 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3385 buf, len);
2cdfe6c8
JN		 3386
3387 return ret == len;
a4fc5ed6
KP		 3388}
3389
70aff66c
JN		 3390static bool
3391intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3392 uint8_t dp_train_pat)
3393{
953d22e8 3394 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3395 intel_dp_set_signal_levels(intel_dp, DP);
3396 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3397}
3398
3399static bool
3400intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3401 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3402{
3403 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3404 struct drm_device *dev = intel_dig_port->base.base.dev;
3405 struct drm_i915_private *dev_priv = dev->dev_private;
3406 int ret;
3407
3408 intel_get_adjust_train(intel_dp, link_status);
3409 intel_dp_set_signal_levels(intel_dp, DP);
3410
3411 I915_WRITE(intel_dp->output_reg, *DP);
3412 POSTING_READ(intel_dp->output_reg);
3413
9d1a1031
JN		 3414 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3415 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3416
3417 return ret == intel_dp->lane_count;
3418}
3419
3ab9c637
ID		 3420static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3421{
3422 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3423 struct drm_device *dev = intel_dig_port->base.base.dev;
3424 struct drm_i915_private *dev_priv = dev->dev_private;
3425 enum port port = intel_dig_port->port;
3426 uint32_t val;
3427
3428 if (!HAS_DDI(dev))
3429 return;
3430
3431 val = I915_READ(DP_TP_CTL(port));
3432 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3433 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3434 I915_WRITE(DP_TP_CTL(port), val);
3435
3436 /*
3437 * On PORT_A we can have only eDP in SST mode. There the only reason
3438 * we need to set idle transmission mode is to work around a HW issue
3439 * where we enable the pipe while not in idle link-training mode.
3440 * In this case there is requirement to wait for a minimum number of
3441 * idle patterns to be sent.
3442 */
3443 if (port == PORT_A)
3444 return;
3445
3446 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3447 1))
3448 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3449}
3450
33a34e4e 3451/* Enable corresponding port and start training pattern 1 */
c19b0669 3452void
33a34e4e 3453intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3454{
da63a9f2 3455 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3456 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3457 int i;
3458 uint8_t voltage;
cdb0e95b 3459 int voltage_tries, loop_tries;
ea5b213a 3460 uint32_t DP = intel_dp->DP;
6aba5b6c 3461 uint8_t link_config[2];
a4fc5ed6 3462
affa9354 3463 if (HAS_DDI(dev))
c19b0669
PZ		 3464 intel_ddi_prepare_link_retrain(encoder);
3465
3cf2efb1 3466 /* Write the link configuration data */
6aba5b6c
JN		 3467 link_config[0] = intel_dp->link_bw;
3468 link_config[1] = intel_dp->lane_count;
3469 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3470 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3471 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3472
3473 link_config[0] = 0;
3474 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3475 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3476
3477 DP |= DP_PORT_EN;
1a2eb460 3478
70aff66c
JN		 3479 /* clock recovery */
3480 if (!intel_dp_reset_link_train(intel_dp, &DP,
3481 DP_TRAINING_PATTERN_1 |
3482 DP_LINK_SCRAMBLING_DISABLE)) {
3483 DRM_ERROR("failed to enable link training\n");
3484 return;
3485 }
3486
a4fc5ed6 3487 voltage = 0xff;
cdb0e95b
KP		 3488 voltage_tries = 0;
3489 loop_tries = 0;
a4fc5ed6 3490 for (;;) {
70aff66c 3491 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3492
a7c9655f 3493 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3494 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3495 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3496 break;
93f62dad 3497 }
a4fc5ed6 3498
01916270 3499 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3500 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3501 break;
3502 }
3503
3504 /* Check to see if we've tried the max voltage */
3505 for (i = 0; i < intel_dp->lane_count; i++)
3506 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3507 break;
3b4f819d 3508 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3509 ++loop_tries;
3510 if (loop_tries == 5) {
3def84b3 3511 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3512 break;
3513 }
70aff66c
JN		 3514 intel_dp_reset_link_train(intel_dp, &DP,
3515 DP_TRAINING_PATTERN_1 |
3516 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3517 voltage_tries = 0;
3518 continue;
3519 }
a4fc5ed6 3520
3cf2efb1 3521 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3522 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3523 ++voltage_tries;
b06fbda3 3524 if (voltage_tries == 5) {
3def84b3 3525 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3526 break;
3527 }
3528 } else
3529 voltage_tries = 0;
3530 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3531
70aff66c
JN		 3532 /* Update training set as requested by target */
3533 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3534 DRM_ERROR("failed to update link training\n");
3535 break;
3536 }
a4fc5ed6
KP		 3537 }
3538
33a34e4e
JB		 3539 intel_dp->DP = DP;
3540}
3541
c19b0669 3542void
33a34e4e
JB		 3543intel_dp_complete_link_train(struct intel_dp *intel_dp)
3544{
33a34e4e 3545 bool channel_eq = false;
37f80975 3546 int tries, cr_tries;
33a34e4e 3547 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3548 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3549
3550 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3551 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3552 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3553
a4fc5ed6 3554 /* channel equalization */
70aff66c 3555 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3556 training_pattern |
70aff66c
JN		 3557 DP_LINK_SCRAMBLING_DISABLE)) {
3558 DRM_ERROR("failed to start channel equalization\n");
3559 return;
3560 }
3561
a4fc5ed6 3562 tries = 0;
37f80975 3563 cr_tries = 0;
a4fc5ed6
KP		 3564 channel_eq = false;
3565 for (;;) {
70aff66c 3566 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3567
37f80975
JB		 3568 if (cr_tries > 5) {
3569 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3570 break;
3571 }
3572
a7c9655f 3573 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3574 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3575 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3576 break;
70aff66c 3577 }
a4fc5ed6 3578
37f80975 3579 /* Make sure clock is still ok */
01916270 3580 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3581 intel_dp_start_link_train(intel_dp);
70aff66c 3582 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3583 training_pattern |
70aff66c 3584 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3585 cr_tries++;
3586 continue;
3587 }
3588
1ffdff13 3589 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3590 channel_eq = true;
3591 break;
3592 }
a4fc5ed6 3593
37f80975
JB		 3594 /* Try 5 times, then try clock recovery if that fails */
3595 if (tries > 5) {
3596 intel_dp_link_down(intel_dp);
3597 intel_dp_start_link_train(intel_dp);
70aff66c 3598 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3599 training_pattern |
70aff66c 3600 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3601 tries = 0;
3602 cr_tries++;
3603 continue;
3604 }
a4fc5ed6 3605
70aff66c
JN		 3606 /* Update training set as requested by target */
3607 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3608 DRM_ERROR("failed to update link training\n");
3609 break;
3610 }
3cf2efb1 3611 ++tries;
869184a6 3612 }
3cf2efb1 3613
3ab9c637
ID		 3614 intel_dp_set_idle_link_train(intel_dp);
3615
3616 intel_dp->DP = DP;
3617
d6c0d722 3618 if (channel_eq)
07f42258 3619 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3620
3ab9c637
ID		 3621}
3622
3623void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3624{
70aff66c 3625 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3626 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3627}
3628
3629static void
ea5b213a 3630intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3631{
da63a9f2 3632 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3633 enum port port = intel_dig_port->port;
da63a9f2 3634 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3635 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3636 struct intel_crtc *intel_crtc =
3637 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3638 uint32_t DP = intel_dp->DP;
a4fc5ed6 3639
bc76e320 3640 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3641 return;
3642
0c33d8d7 3643 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3644 return;
3645
28c97730 3646 DRM_DEBUG_KMS("\n");
32f9d658 3647
bc7d38a4 3648 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3649 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3650 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3651 } else {
aad3d14d
VS		 3652 if (IS_CHERRYVIEW(dev))
3653 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3654 else
3655 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3656 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3657 }
fe255d00 3658 POSTING_READ(intel_dp->output_reg);
5eb08b69 3659
493a7081 3660 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3661 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3662 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3663
5bddd17f
EA		 3664 /* Hardware workaround: leaving our transcoder select
3665 * set to transcoder B while it's off will prevent the
3666 * corresponding HDMI output on transcoder A.
3667 *
3668 * Combine this with another hardware workaround:
3669 * transcoder select bit can only be cleared while the
3670 * port is enabled.
3671 */
3672 DP &= ~DP_PIPEB_SELECT;
3673 I915_WRITE(intel_dp->output_reg, DP);
3674
3675 /* Changes to enable or select take place the vblank
3676 * after being written.
3677 */
ff50afe9
DV		 3678 if (WARN_ON(crtc == NULL)) {
3679 /* We should never try to disable a port without a crtc
3680 * attached. For paranoia keep the code around for a
3681 * bit. */
31acbcc4
CW		 3682 POSTING_READ(intel_dp->output_reg);
3683 msleep(50);
3684 } else
ab527efc 3685 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3686 }
3687
832afda6 3688 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3689 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3690 POSTING_READ(intel_dp->output_reg);
f01eca2e 3691 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3692}
3693
26d61aad
KP		 3694static bool
3695intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3696{
a031d709
RV		 3697 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3698 struct drm_device *dev = dig_port->base.base.dev;
3699 struct drm_i915_private *dev_priv = dev->dev_private;
3700
9d1a1031
JN		 3701 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3702 sizeof(intel_dp->dpcd)) < 0)
edb39244 3703 return false; /* aux transfer failed */
92fd8fd1 3704
a8e98153 3705 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3706
edb39244
AJ		 3707 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3708 return false; /* DPCD not present */
3709
2293bb5c
SK		 3710 /* Check if the panel supports PSR */
3711 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3712 if (is_edp(intel_dp)) {
9d1a1031
JN		 3713 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3714 intel_dp->psr_dpcd,
3715 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3716 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3717 dev_priv->psr.sink_support = true;
50003939 3718 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3719 }
50003939
JN		 3720 }
3721
06ea66b6
TP		 3722 /* Training Pattern 3 support */
3723 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3724 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3725 intel_dp->use_tps3 = true;
f8d8a672 3726 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3727 } else
3728 intel_dp->use_tps3 = false;
3729
edb39244
AJ		 3730 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3731 DP_DWN_STRM_PORT_PRESENT))
3732 return true; /* native DP sink */
3733
3734 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3735 return true; /* no per-port downstream info */
3736
9d1a1031
JN		 3737 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3738 intel_dp->downstream_ports,
3739 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3740 return false; /* downstream port status fetch failed */
3741
3742 return true;
92fd8fd1
KP		 3743}
3744
0d198328
AJ		 3745static void
3746intel_dp_probe_oui(struct intel_dp *intel_dp)
3747{
3748 u8 buf[3];
3749
3750 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3751 return;
3752
24f3e092 3753 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3754
9d1a1031 3755 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3756 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3757 buf[0], buf[1], buf[2]);
3758
9d1a1031 3759 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3760 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3761 buf[0], buf[1], buf[2]);
351cfc34 3762
1e0560e0 3763 intel_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3764}
3765
0e32b39c
DA		 3766static bool
3767intel_dp_probe_mst(struct intel_dp *intel_dp)
3768{
3769 u8 buf[1];
3770
3771 if (!intel_dp->can_mst)
3772 return false;
3773
3774 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3775 return false;
3776
d337a341 3777 intel_edp_panel_vdd_on(intel_dp);
0e32b39c
DA		 3778 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3779 if (buf[0] & DP_MST_CAP) {
3780 DRM_DEBUG_KMS("Sink is MST capable\n");
3781 intel_dp->is_mst = true;
3782 } else {
3783 DRM_DEBUG_KMS("Sink is not MST capable\n");
3784 intel_dp->is_mst = false;
3785 }
3786 }
1e0560e0 3787 intel_edp_panel_vdd_off(intel_dp, false);
0e32b39c
DA		 3788
3789 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3790 return intel_dp->is_mst;
3791}
3792
d2e216d0
RV		 3793int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3794{
3795 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3796 struct drm_device *dev = intel_dig_port->base.base.dev;
3797 struct intel_crtc *intel_crtc =
3798 to_intel_crtc(intel_dig_port->base.base.crtc);
3799 u8 buf[1];
3800
9d1a1031 3801 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
bda0381e 3802 return -EIO;
d2e216d0
RV		 3803
3804 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3805 return -ENOTTY;
3806
9d1a1031
JN		 3807 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3808 DP_TEST_SINK_START) < 0)
bda0381e 3809 return -EIO;
d2e216d0
RV		 3810
3811 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3812 intel_wait_for_vblank(dev, intel_crtc->pipe);
3813 intel_wait_for_vblank(dev, intel_crtc->pipe);
3814
9d1a1031 3815 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 3816 return -EIO;
d2e216d0 3817
9d1a1031 3818 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3819 return 0;
3820}
3821
a60f0e38
JB		 3822static bool
3823intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3824{
9d1a1031
JN		 3825 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3826 DP_DEVICE_SERVICE_IRQ_VECTOR,
3827 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3828}
3829
0e32b39c
DA		 3830static bool
3831intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3832{
3833 int ret;
3834
3835 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3836 DP_SINK_COUNT_ESI,
3837 sink_irq_vector, 14);
3838 if (ret != 14)
3839 return false;
3840
3841 return true;
3842}
3843
a60f0e38
JB		 3844static void
3845intel_dp_handle_test_request(struct intel_dp *intel_dp)
3846{
3847 /* NAK by default */
9d1a1031 3848 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3849}
3850
0e32b39c
DA		 3851static int
3852intel_dp_check_mst_status(struct intel_dp *intel_dp)
3853{
3854 bool bret;
3855
3856 if (intel_dp->is_mst) {
3857 u8 esi[16] = { 0 };
3858 int ret = 0;
3859 int retry;
3860 bool handled;
3861 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3862go_again:
3863 if (bret == true) {
3864
3865 /* check link status - esi[10] = 0x200c */
3866 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3867 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3868 intel_dp_start_link_train(intel_dp);
3869 intel_dp_complete_link_train(intel_dp);
3870 intel_dp_stop_link_train(intel_dp);
3871 }
3872
3873 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3874 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3875
3876 if (handled) {
3877 for (retry = 0; retry < 3; retry++) {
3878 int wret;
3879 wret = drm_dp_dpcd_write(&intel_dp->aux,
3880 DP_SINK_COUNT_ESI+1,
3881 &esi[1], 3);
3882 if (wret == 3) {
3883 break;
3884 }
3885 }
3886
3887 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3888 if (bret == true) {
3889 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3890 goto go_again;
3891 }
3892 } else
3893 ret = 0;
3894
3895 return ret;
3896 } else {
3897 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3898 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3899 intel_dp->is_mst = false;
3900 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3901 /* send a hotplug event */
3902 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3903 }
3904 }
3905 return -EINVAL;
3906}
3907
a4fc5ed6
KP		 3908/*
3909 * According to DP spec
3910 * 5.1.2:
3911 * 1. Read DPCD
3912 * 2. Configure link according to Receiver Capabilities
3913 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3914 * 4. Check link status on receipt of hot-plug interrupt
3915 */
00c09d70 3916void
ea5b213a 3917intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3918{
5b215bcf 3919 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3920 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3921 u8 sink_irq_vector;
93f62dad 3922 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3923
5b215bcf
DA		 3924 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3925
da63a9f2 3926 if (!intel_encoder->connectors_active)
d2b996ac 3927 return;
59cd09e1 3928
da63a9f2 3929 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3930 return;
3931
1a125d8a
ID		 3932 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3933 return;
3934
92fd8fd1 3935 /* Try to read receiver status if the link appears to be up */
93f62dad 3936 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3937 return;
3938 }
3939
92fd8fd1 3940 /* Now read the DPCD to see if it's actually running */
26d61aad 3941 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3942 return;
3943 }
3944
a60f0e38
JB		 3945 /* Try to read the source of the interrupt */
3946 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3947 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3948 /* Clear interrupt source */
9d1a1031
JN		 3949 drm_dp_dpcd_writeb(&intel_dp->aux,
3950 DP_DEVICE_SERVICE_IRQ_VECTOR,
3951 sink_irq_vector);
a60f0e38
JB		 3952
3953 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3954 intel_dp_handle_test_request(intel_dp);
3955 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3956 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3957 }
3958
1ffdff13 3959 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3960 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3961 intel_encoder->base.name);
33a34e4e
JB		 3962 intel_dp_start_link_train(intel_dp);
3963 intel_dp_complete_link_train(intel_dp);
3ab9c637 3964 intel_dp_stop_link_train(intel_dp);
33a34e4e 3965 }
a4fc5ed6 3966}
a4fc5ed6 3967
caf9ab24 3968/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3969static enum drm_connector_status
26d61aad 3970intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3971{
caf9ab24 3972 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3973 uint8_t type;
3974
3975 if (!intel_dp_get_dpcd(intel_dp))
3976 return connector_status_disconnected;
3977
3978 /* if there's no downstream port, we're done */
3979 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3980 return connector_status_connected;
caf9ab24
AJ		 3981
3982 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3983 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3984 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3985 uint8_t reg;
9d1a1031
JN		 3986
3987 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3988 &reg, 1) < 0)
caf9ab24 3989 return connector_status_unknown;
9d1a1031 3990
23235177
AJ		 3991 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3992 : connector_status_disconnected;
caf9ab24
AJ		 3993 }
3994
3995 /* If no HPD, poke DDC gently */
0b99836f 3996 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3997 return connector_status_connected;
caf9ab24
AJ		 3998
3999 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4000 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4001 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4002 if (type == DP_DS_PORT_TYPE_VGA ||
4003 type == DP_DS_PORT_TYPE_NON_EDID)
4004 return connector_status_unknown;
4005 } else {
4006 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4007 DP_DWN_STRM_PORT_TYPE_MASK;
4008 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4009 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4010 return connector_status_unknown;
4011 }
caf9ab24
AJ		 4012
4013 /* Anything else is out of spec, warn and ignore */
4014 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4015 return connector_status_disconnected;
71ba9000
AJ		 4016}
4017
d410b56d
CW		 4018static enum drm_connector_status
4019edp_detect(struct intel_dp *intel_dp)
4020{
4021 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4022 enum drm_connector_status status;
4023
4024 status = intel_panel_detect(dev);
4025 if (status == connector_status_unknown)
4026 status = connector_status_connected;
4027
4028 return status;
4029}
4030
5eb08b69 4031static enum drm_connector_status
a9756bb5 4032ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4033{
30add22d 4034 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4035 struct drm_i915_private *dev_priv = dev->dev_private;
4036 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4037
1b469639
DL		 4038 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4039 return connector_status_disconnected;
4040
26d61aad 4041 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4042}
4043
2a592bec
DA		 4044static int g4x_digital_port_connected(struct drm_device *dev,
4045 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4046{
a4fc5ed6 4047 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4048 uint32_t bit;
5eb08b69 4049
232a6ee9
TP		 4050 if (IS_VALLEYVIEW(dev)) {
4051 switch (intel_dig_port->port) {
4052 case PORT_B:
4053 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4054 break;
4055 case PORT_C:
4056 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4057 break;
4058 case PORT_D:
4059 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4060 break;
4061 default:
2a592bec 4062 return -EINVAL;
232a6ee9
TP		 4063 }
4064 } else {
4065 switch (intel_dig_port->port) {
4066 case PORT_B:
4067 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4068 break;
4069 case PORT_C:
4070 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4071 break;
4072 case PORT_D:
4073 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4074 break;
4075 default:
2a592bec 4076 return -EINVAL;
232a6ee9 4077 }
a4fc5ed6
KP		 4078 }
4079
10f76a38 4080 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4081 return 0;
4082 return 1;
4083}
4084
4085static enum drm_connector_status
4086g4x_dp_detect(struct intel_dp *intel_dp)
4087{
4088 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4089 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4090 int ret;
4091
4092 /* Can't disconnect eDP, but you can close the lid... */
4093 if (is_edp(intel_dp)) {
4094 enum drm_connector_status status;
4095
4096 status = intel_panel_detect(dev);
4097 if (status == connector_status_unknown)
4098 status = connector_status_connected;
4099 return status;
4100 }
4101
4102 ret = g4x_digital_port_connected(dev, intel_dig_port);
4103 if (ret == -EINVAL)
4104 return connector_status_unknown;
4105 else if (ret == 0)
a4fc5ed6
KP		 4106 return connector_status_disconnected;
4107
26d61aad 4108 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4109}
4110
8c241fef 4111static struct edid *
beb60608 4112intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4113{
beb60608 4114 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4115
9cd300e0
JN		 4116 /* use cached edid if we have one */
4117 if (intel_connector->edid) {
9cd300e0
JN		 4118 /* invalid edid */
4119 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4120 return NULL;
4121
55e9edeb 4122 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4123 } else
4124 return drm_get_edid(&intel_connector->base,
4125 &intel_dp->aux.ddc);
4126}
8c241fef 4127
beb60608
CW		 4128static void
4129intel_dp_set_edid(struct intel_dp *intel_dp)
4130{
4131 struct intel_connector *intel_connector = intel_dp->attached_connector;
4132 struct edid *edid;
8c241fef 4133
beb60608
CW		 4134 edid = intel_dp_get_edid(intel_dp);
4135 intel_connector->detect_edid = edid;
4136
4137 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4138 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4139 else
4140 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4141}
4142
beb60608
CW		 4143static void
4144intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4145{
beb60608 4146 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4147
beb60608
CW		 4148 kfree(intel_connector->detect_edid);
4149 intel_connector->detect_edid = NULL;
9cd300e0 4150
beb60608
CW		 4151 intel_dp->has_audio = false;
4152}
d6f24d0f 4153
beb60608
CW		 4154static enum intel_display_power_domain
4155intel_dp_power_get(struct intel_dp *dp)
4156{
4157 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4158 enum intel_display_power_domain power_domain;
4159
4160 power_domain = intel_display_port_power_domain(encoder);
4161 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4162
4163 return power_domain;
4164}
d6f24d0f 4165
beb60608
CW		 4166static void
4167intel_dp_power_put(struct intel_dp *dp,
4168 enum intel_display_power_domain power_domain)
4169{
4170 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4171 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4172}
4173
a9756bb5
ZW		 4174static enum drm_connector_status
4175intel_dp_detect(struct drm_connector *connector, bool force)
4176{
4177 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4178 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4179 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4180 struct drm_device *dev = connector->dev;
a9756bb5 4181 enum drm_connector_status status;
671dedd2 4182 enum intel_display_power_domain power_domain;
0e32b39c 4183 bool ret;
a9756bb5 4184
164c8598 4185 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4186 connector->base.id, connector->name);
beb60608 4187 intel_dp_unset_edid(intel_dp);
164c8598 4188
0e32b39c
DA		 4189 if (intel_dp->is_mst) {
4190 /* MST devices are disconnected from a monitor POV */
4191 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4192 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4193 return connector_status_disconnected;
0e32b39c
DA		 4194 }
4195
beb60608 4196 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4197
d410b56d
CW		 4198 /* Can't disconnect eDP, but you can close the lid... */
4199 if (is_edp(intel_dp))
4200 status = edp_detect(intel_dp);
4201 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4202 status = ironlake_dp_detect(intel_dp);
4203 else
4204 status = g4x_dp_detect(intel_dp);
4205 if (status != connector_status_connected)
c8c8fb33 4206 goto out;
a9756bb5 4207
0d198328
AJ		 4208 intel_dp_probe_oui(intel_dp);
4209
0e32b39c
DA		 4210 ret = intel_dp_probe_mst(intel_dp);
4211 if (ret) {
4212 /* if we are in MST mode then this connector
4213 won't appear connected or have anything with EDID on it */
4214 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4215 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4216 status = connector_status_disconnected;
4217 goto out;
4218 }
4219
beb60608 4220 intel_dp_set_edid(intel_dp);
a9756bb5 4221
d63885da
PZ		 4222 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4223 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4224 status = connector_status_connected;
4225
4226out:
beb60608 4227 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4228 return status;
a4fc5ed6
KP		 4229}
4230
beb60608
CW		 4231static void
4232intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4233{
df0e9248 4234 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4235 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4236 enum intel_display_power_domain power_domain;
a4fc5ed6 4237
beb60608
CW		 4238 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4239 connector->base.id, connector->name);
4240 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4241
beb60608
CW		 4242 if (connector->status != connector_status_connected)
4243 return;
671dedd2 4244
beb60608
CW		 4245 power_domain = intel_dp_power_get(intel_dp);
4246
4247 intel_dp_set_edid(intel_dp);
4248
4249 intel_dp_power_put(intel_dp, power_domain);
4250
4251 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4252 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4253}
4254
4255static int intel_dp_get_modes(struct drm_connector *connector)
4256{
4257 struct intel_connector *intel_connector = to_intel_connector(connector);
4258 struct edid *edid;
4259
4260 edid = intel_connector->detect_edid;
4261 if (edid) {
4262 int ret = intel_connector_update_modes(connector, edid);
4263 if (ret)
4264 return ret;
4265 }
32f9d658 4266
f8779fda 4267 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4268 if (is_edp(intel_attached_dp(connector)) &&
4269 intel_connector->panel.fixed_mode) {
f8779fda 4270 struct drm_display_mode *mode;
beb60608
CW		 4271
4272 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4273 intel_connector->panel.fixed_mode);
f8779fda 4274 if (mode) {
32f9d658
ZW		 4275 drm_mode_probed_add(connector, mode);
4276 return 1;
4277 }
4278 }
beb60608 4279
32f9d658 4280 return 0;
a4fc5ed6
KP		 4281}
4282
1aad7ac0
CW		 4283static bool
4284intel_dp_detect_audio(struct drm_connector *connector)
4285{
1aad7ac0 4286 bool has_audio = false;
beb60608 4287 struct edid *edid;
1aad7ac0 4288
beb60608
CW		 4289 edid = to_intel_connector(connector)->detect_edid;
4290 if (edid)
1aad7ac0 4291 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4292
1aad7ac0
CW		 4293 return has_audio;
4294}
4295
f684960e
CW		 4296static int
4297intel_dp_set_property(struct drm_connector *connector,
4298 struct drm_property *property,
4299 uint64_t val)
4300{
e953fd7b 4301 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4302 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4303 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4304 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4305 int ret;
4306
662595df 4307 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4308 if (ret)
4309 return ret;
4310
3f43c48d 4311 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4312 int i = val;
4313 bool has_audio;
4314
4315 if (i == intel_dp->force_audio)
f684960e
CW		 4316 return 0;
4317
1aad7ac0 4318 intel_dp->force_audio = i;
f684960e 4319
c3e5f67b 4320 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4321 has_audio = intel_dp_detect_audio(connector);
4322 else
c3e5f67b 4323 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4324
4325 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4326 return 0;
4327
1aad7ac0 4328 intel_dp->has_audio = has_audio;
f684960e
CW		 4329 goto done;
4330 }
4331
e953fd7b 4332 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4333 bool old_auto = intel_dp->color_range_auto;
4334 uint32_t old_range = intel_dp->color_range;
4335
55bc60db
VS		 4336 switch (val) {
4337 case INTEL_BROADCAST_RGB_AUTO:
4338 intel_dp->color_range_auto = true;
4339 break;
4340 case INTEL_BROADCAST_RGB_FULL:
4341 intel_dp->color_range_auto = false;
4342 intel_dp->color_range = 0;
4343 break;
4344 case INTEL_BROADCAST_RGB_LIMITED:
4345 intel_dp->color_range_auto = false;
4346 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4347 break;
4348 default:
4349 return -EINVAL;
4350 }
ae4edb80
DV		 4351
4352 if (old_auto == intel_dp->color_range_auto &&
4353 old_range == intel_dp->color_range)
4354 return 0;
4355
e953fd7b
CW		 4356 goto done;
4357 }
4358
53b41837
YN		 4359 if (is_edp(intel_dp) &&
4360 property == connector->dev->mode_config.scaling_mode_property) {
4361 if (val == DRM_MODE_SCALE_NONE) {
4362 DRM_DEBUG_KMS("no scaling not supported\n");
4363 return -EINVAL;
4364 }
4365
4366 if (intel_connector->panel.fitting_mode == val) {
4367 /* the eDP scaling property is not changed */
4368 return 0;
4369 }
4370 intel_connector->panel.fitting_mode = val;
4371
4372 goto done;
4373 }
4374
f684960e
CW		 4375 return -EINVAL;
4376
4377done:
c0c36b94
CW		 4378 if (intel_encoder->base.crtc)
4379 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4380
4381 return 0;
4382}
4383
a4fc5ed6 4384static void
73845adf 4385intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4386{
1d508706 4387 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4388
10e972d3 4389 kfree(intel_connector->detect_edid);
beb60608 4390
9cd300e0
JN		 4391 if (!IS_ERR_OR_NULL(intel_connector->edid))
4392 kfree(intel_connector->edid);
4393
acd8db10
PZ		 4394 /* Can't call is_edp() since the encoder may have been destroyed
4395 * already. */
4396 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4397 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4398
a4fc5ed6 4399 drm_connector_cleanup(connector);
55f78c43 4400 kfree(connector);
a4fc5ed6
KP		 4401}
4402
00c09d70 4403void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4404{
da63a9f2
PZ		 4405 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4406 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4407
4f71d0cb 4408 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4409 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4410 drm_encoder_cleanup(encoder);
bd943159
KP		 4411 if (is_edp(intel_dp)) {
4412 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4413 /*
4414 * vdd might still be enabled do to the delayed vdd off.
4415 * Make sure vdd is actually turned off here.
4416 */
773538e8 4417 pps_lock(intel_dp);
4be73780 4418 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4419 pps_unlock(intel_dp);
4420
01527b31
CT		 4421 if (intel_dp->edp_notifier.notifier_call) {
4422 unregister_reboot_notifier(&intel_dp->edp_notifier);
4423 intel_dp->edp_notifier.notifier_call = NULL;
4424 }
bd943159 4425 }
da63a9f2 4426 kfree(intel_dig_port);
24d05927
DV		 4427}
4428
07f9cd0b
ID		 4429static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4430{
4431 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4432
4433 if (!is_edp(intel_dp))
4434 return;
4435
951468f3
VS		 4436 /*
4437 * vdd might still be enabled do to the delayed vdd off.
4438 * Make sure vdd is actually turned off here.
4439 */
773538e8 4440 pps_lock(intel_dp);
07f9cd0b 4441 edp_panel_vdd_off_sync(intel_dp);
773538e8 4442 pps_unlock(intel_dp);
07f9cd0b
ID		 4443}
4444
6d93c0c4
ID		 4445static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4446{
4447 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4448}
4449
a4fc5ed6 4450static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4451 .dpms = intel_connector_dpms,
a4fc5ed6 4452 .detect = intel_dp_detect,
beb60608 4453 .force = intel_dp_force,
a4fc5ed6 4454 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4455 .set_property = intel_dp_set_property,
73845adf 4456 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4457};
4458
4459static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4460 .get_modes = intel_dp_get_modes,
4461 .mode_valid = intel_dp_mode_valid,
df0e9248 4462 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4463};
4464
a4fc5ed6 4465static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4466 .reset = intel_dp_encoder_reset,
24d05927 4467 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4468};
4469
0e32b39c 4470void
21d40d37 4471intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4472{
0e32b39c 4473 return;
c8110e52 4474}
6207937d 4475
13cf5504
DA		 4476bool
4477intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4478{
4479 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4480 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4481 struct drm_device *dev = intel_dig_port->base.base.dev;
4482 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4483 enum intel_display_power_domain power_domain;
4484 bool ret = true;
4485
0e32b39c
DA		 4486 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4487 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4488
26fbb774
VS		 4489 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4490 port_name(intel_dig_port->port),
0e32b39c 4491 long_hpd ? "long" : "short");
13cf5504 4492
1c767b33
ID		 4493 power_domain = intel_display_port_power_domain(intel_encoder);
4494 intel_display_power_get(dev_priv, power_domain);
4495
0e32b39c 4496 if (long_hpd) {
2a592bec
DA		 4497
4498 if (HAS_PCH_SPLIT(dev)) {
4499 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4500 goto mst_fail;
4501 } else {
4502 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4503 goto mst_fail;
4504 }
0e32b39c
DA		 4505
4506 if (!intel_dp_get_dpcd(intel_dp)) {
4507 goto mst_fail;
4508 }
4509
4510 intel_dp_probe_oui(intel_dp);
4511
4512 if (!intel_dp_probe_mst(intel_dp))
4513 goto mst_fail;
4514
4515 } else {
4516 if (intel_dp->is_mst) {
1c767b33 4517 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4518 goto mst_fail;
4519 }
4520
4521 if (!intel_dp->is_mst) {
4522 /*
4523 * we'll check the link status via the normal hot plug path later -
4524 * but for short hpds we should check it now
4525 */
5b215bcf 4526 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4527 intel_dp_check_link_status(intel_dp);
5b215bcf 4528 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4529 }
4530 }
1c767b33
ID		 4531 ret = false;
4532 goto put_power;
0e32b39c
DA		 4533mst_fail:
4534 /* if we were in MST mode, and device is not there get out of MST mode */
4535 if (intel_dp->is_mst) {
4536 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4537 intel_dp->is_mst = false;
4538 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4539 }
1c767b33
ID		 4540put_power:
4541 intel_display_power_put(dev_priv, power_domain);
4542
4543 return ret;
13cf5504
DA		 4544}
4545
e3421a18
ZW		 4546/* Return which DP Port should be selected for Transcoder DP control */
4547int
0206e353 4548intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4549{
4550 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4551 struct intel_encoder *intel_encoder;
4552 struct intel_dp *intel_dp;
e3421a18 4553
fa90ecef
PZ		 4554 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4555 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4556
fa90ecef
PZ		 4557 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4558 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4559 return intel_dp->output_reg;
e3421a18 4560 }
ea5b213a 4561
e3421a18
ZW		 4562 return -1;
4563}
4564
36e83a18 4565/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4566bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4567{
4568 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4569 union child_device_config *p_child;
36e83a18 4570 int i;
5d8a7752
VS		 4571 static const short port_mapping[] = {
4572 [PORT_B] = PORT_IDPB,
4573 [PORT_C] = PORT_IDPC,
4574 [PORT_D] = PORT_IDPD,
4575 };
36e83a18 4576
3b32a35b
VS		 4577 if (port == PORT_A)
4578 return true;
4579
41aa3448 4580 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4581 return false;
4582
41aa3448
RV		 4583 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4584 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4585
5d8a7752 4586 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4587 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4588 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4589 return true;
4590 }
4591 return false;
4592}
4593
0e32b39c 4594void
f684960e
CW		 4595intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4596{
53b41837
YN		 4597 struct intel_connector *intel_connector = to_intel_connector(connector);
4598
3f43c48d 4599 intel_attach_force_audio_property(connector);
e953fd7b 4600 intel_attach_broadcast_rgb_property(connector);
55bc60db 4601 intel_dp->color_range_auto = true;
53b41837
YN		 4602
4603 if (is_edp(intel_dp)) {
4604 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4605 drm_object_attach_property(
4606 &connector->base,
53b41837 4607 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4608 DRM_MODE_SCALE_ASPECT);
4609 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4610 }
f684960e
CW		 4611}
4612
dada1a9f
ID		 4613static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4614{
4615 intel_dp->last_power_cycle = jiffies;
4616 intel_dp->last_power_on = jiffies;
4617 intel_dp->last_backlight_off = jiffies;
4618}
4619
67a54566
DV		 4620static void
4621intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4622 struct intel_dp *intel_dp,
4623 struct edp_power_seq *out)
67a54566
DV		 4624{
4625 struct drm_i915_private *dev_priv = dev->dev_private;
4626 struct edp_power_seq cur, vbt, spec, final;
4627 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4628 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4629
e39b999a
VS		 4630 lockdep_assert_held(&dev_priv->pps_mutex);
4631
453c5420 4632 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4633 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4634 pp_on_reg = PCH_PP_ON_DELAYS;
4635 pp_off_reg = PCH_PP_OFF_DELAYS;
4636 pp_div_reg = PCH_PP_DIVISOR;
4637 } else {
bf13e81b
JN		 4638 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4639
4640 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4641 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4642 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4643 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4644 }
67a54566
DV		 4645
4646 /* Workaround: Need to write PP_CONTROL with the unlock key as
4647 * the very first thing. */
453c5420 4648 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4649 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4650
453c5420
JB		 4651 pp_on = I915_READ(pp_on_reg);
4652 pp_off = I915_READ(pp_off_reg);
4653 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4654
4655 /* Pull timing values out of registers */
4656 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4657 PANEL_POWER_UP_DELAY_SHIFT;
4658
4659 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4660 PANEL_LIGHT_ON_DELAY_SHIFT;
4661
4662 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4663 PANEL_LIGHT_OFF_DELAY_SHIFT;
4664
4665 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4666 PANEL_POWER_DOWN_DELAY_SHIFT;
4667
4668 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4669 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4670
4671 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4672 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4673
41aa3448 4674 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4675
4676 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4677 * our hw here, which are all in 100usec. */
4678 spec.t1_t3 = 210 * 10;
4679 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4680 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4681 spec.t10 = 500 * 10;
4682 /* This one is special and actually in units of 100ms, but zero
4683 * based in the hw (so we need to add 100 ms). But the sw vbt
4684 * table multiplies it with 1000 to make it in units of 100usec,
4685 * too. */
4686 spec.t11_t12 = (510 + 100) * 10;
4687
4688 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4689 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4690
4691 /* Use the max of the register settings and vbt. If both are
4692 * unset, fall back to the spec limits. */
4693#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4694 spec.field : \
4695 max(cur.field, vbt.field))
4696 assign_final(t1_t3);
4697 assign_final(t8);
4698 assign_final(t9);
4699 assign_final(t10);
4700 assign_final(t11_t12);
4701#undef assign_final
4702
4703#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4704 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4705 intel_dp->backlight_on_delay = get_delay(t8);
4706 intel_dp->backlight_off_delay = get_delay(t9);
4707 intel_dp->panel_power_down_delay = get_delay(t10);
4708 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4709#undef get_delay
4710
f30d26e4
JN		 4711 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4712 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4713 intel_dp->panel_power_cycle_delay);
4714
4715 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4716 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4717
4718 if (out)
4719 *out = final;
4720}
4721
4722static void
4723intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4724 struct intel_dp *intel_dp,
4725 struct edp_power_seq *seq)
4726{
4727 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4728 u32 pp_on, pp_off, pp_div, port_sel = 0;
4729 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4730 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4731 enum port port = dp_to_dig_port(intel_dp)->port;
453c5420 4732
e39b999a 4733 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4734
4735 if (HAS_PCH_SPLIT(dev)) {
4736 pp_on_reg = PCH_PP_ON_DELAYS;
4737 pp_off_reg = PCH_PP_OFF_DELAYS;
4738 pp_div_reg = PCH_PP_DIVISOR;
4739 } else {
bf13e81b
JN		 4740 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4741
4742 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4743 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4744 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4745 }
4746
b2f19d1a
PZ		 4747 /*
4748 * And finally store the new values in the power sequencer. The
4749 * backlight delays are set to 1 because we do manual waits on them. For
4750 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4751 * we'll end up waiting for the backlight off delay twice: once when we
4752 * do the manual sleep, and once when we disable the panel and wait for
4753 * the PP_STATUS bit to become zero.
4754 */
f30d26e4 4755 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4756 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4757 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4758 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4759 /* Compute the divisor for the pp clock, simply match the Bspec
4760 * formula. */
453c5420 4761 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4762 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4763 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4764
4765 /* Haswell doesn't have any port selection bits for the panel
4766 * power sequencer any more. */
bc7d38a4 4767 if (IS_VALLEYVIEW(dev)) {
ad933b56 4768 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4769 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4770 if (port == PORT_A)
a24c144c 4771 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4772 else
a24c144c 4773 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4774 }
4775
453c5420
JB		 4776 pp_on |= port_sel;
4777
4778 I915_WRITE(pp_on_reg, pp_on);
4779 I915_WRITE(pp_off_reg, pp_off);
4780 I915_WRITE(pp_div_reg, pp_div);
67a54566 4781
67a54566 4782 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4783 I915_READ(pp_on_reg),
4784 I915_READ(pp_off_reg),
4785 I915_READ(pp_div_reg));
f684960e
CW		 4786}
4787
439d7ac0
PB		 4788void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4789{
4790 struct drm_i915_private *dev_priv = dev->dev_private;
4791 struct intel_encoder *encoder;
4792 struct intel_dp *intel_dp = NULL;
4793 struct intel_crtc_config *config = NULL;
4794 struct intel_crtc *intel_crtc = NULL;
4795 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4796 u32 reg, val;
4797 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4798
4799 if (refresh_rate <= 0) {
4800 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4801 return;
4802 }
4803
4804 if (intel_connector == NULL) {
4805 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4806 return;
4807 }
4808
1fcc9d1c
DV		 4809 /*
4810 * FIXME: This needs proper synchronization with psr state. But really
4811 * hard to tell without seeing the user of this function of this code.
4812 * Check locking and ordering once that lands.
4813 */
439d7ac0
PB		 4814 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4815 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4816 return;
4817 }
4818
4819 encoder = intel_attached_encoder(&intel_connector->base);
4820 intel_dp = enc_to_intel_dp(&encoder->base);
4821 intel_crtc = encoder->new_crtc;
4822
4823 if (!intel_crtc) {
4824 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4825 return;
4826 }
4827
4828 config = &intel_crtc->config;
4829
4830 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4831 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4832 return;
4833 }
4834
4835 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4836 index = DRRS_LOW_RR;
4837
4838 if (index == intel_dp->drrs_state.refresh_rate_type) {
4839 DRM_DEBUG_KMS(
4840 "DRRS requested for previously set RR...ignoring\n");
4841 return;
4842 }
4843
4844 if (!intel_crtc->active) {
4845 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4846 return;
4847 }
4848
4849 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4850 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4851 val = I915_READ(reg);
4852 if (index > DRRS_HIGH_RR) {
4853 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4854 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4855 } else {
4856 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4857 }
4858 I915_WRITE(reg, val);
4859 }
4860
4861 /*
4862 * mutex taken to ensure that there is no race between differnt
4863 * drrs calls trying to update refresh rate. This scenario may occur
4864 * in future when idleness detection based DRRS in kernel and
4865 * possible calls from user space to set differnt RR are made.
4866 */
4867
4868 mutex_lock(&intel_dp->drrs_state.mutex);
4869
4870 intel_dp->drrs_state.refresh_rate_type = index;
4871
4872 mutex_unlock(&intel_dp->drrs_state.mutex);
4873
4874 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4875}
4876
4f9db5b5
PB		 4877static struct drm_display_mode *
4878intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4879 struct intel_connector *intel_connector,
4880 struct drm_display_mode *fixed_mode)
4881{
4882 struct drm_connector *connector = &intel_connector->base;
4883 struct intel_dp *intel_dp = &intel_dig_port->dp;
4884 struct drm_device *dev = intel_dig_port->base.base.dev;
4885 struct drm_i915_private *dev_priv = dev->dev_private;
4886 struct drm_display_mode *downclock_mode = NULL;
4887
4888 if (INTEL_INFO(dev)->gen <= 6) {
4889 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4890 return NULL;
4891 }
4892
4893 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4894 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4895 return NULL;
4896 }
4897
4898 downclock_mode = intel_find_panel_downclock
4899 (dev, fixed_mode, connector);
4900
4901 if (!downclock_mode) {
4079b8d1 4902 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4903 return NULL;
4904 }
4905
439d7ac0
PB		 4906 dev_priv->drrs.connector = intel_connector;
4907
4908 mutex_init(&intel_dp->drrs_state.mutex);
4909
4f9db5b5
PB		 4910 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4911
4912 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4913 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4914 return downclock_mode;
4915}
4916
aba86890
ID		 4917void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4918{
4919 struct drm_device *dev = intel_encoder->base.dev;
4920 struct drm_i915_private *dev_priv = dev->dev_private;
4921 struct intel_dp *intel_dp;
4922 enum intel_display_power_domain power_domain;
4923
4924 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4925 return;
4926
4927 intel_dp = enc_to_intel_dp(&intel_encoder->base);
773538e8
VS		 4928
4929 pps_lock(intel_dp);
4930
aba86890 4931 if (!edp_have_panel_vdd(intel_dp))
e39b999a 4932 goto out;
aba86890
ID		 4933 /*
4934 * The VDD bit needs a power domain reference, so if the bit is
4935 * already enabled when we boot or resume, grab this reference and
4936 * schedule a vdd off, so we don't hold on to the reference
4937 * indefinitely.
4938 */
4939 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4940 power_domain = intel_display_port_power_domain(intel_encoder);
4941 intel_display_power_get(dev_priv, power_domain);
4942
4943 edp_panel_vdd_schedule_off(intel_dp);
e39b999a 4944 out:
773538e8 4945 pps_unlock(intel_dp);
aba86890
ID		 4946}
4947
ed92f0b2 4948static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4949 struct intel_connector *intel_connector,
4950 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4951{
4952 struct drm_connector *connector = &intel_connector->base;
4953 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4954 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4955 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4956 struct drm_i915_private *dev_priv = dev->dev_private;
4957 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4958 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4959 bool has_dpcd;
4960 struct drm_display_mode *scan;
4961 struct edid *edid;
4962
4f9db5b5
PB		 4963 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4964
ed92f0b2
PZ		 4965 if (!is_edp(intel_dp))
4966 return true;
4967
aba86890 4968 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 4969
ed92f0b2 4970 /* Cache DPCD and EDID for edp. */
24f3e092 4971 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4972 has_dpcd = intel_dp_get_dpcd(intel_dp);
1e0560e0 4973 intel_edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4974
4975 if (has_dpcd) {
4976 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4977 dev_priv->no_aux_handshake =
4978 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4979 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4980 } else {
4981 /* if this fails, presume the device is a ghost */
4982 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4983 return false;
4984 }
4985
4986 /* We now know it's not a ghost, init power sequence regs. */
773538e8 4987 pps_lock(intel_dp);
0095e6dc 4988 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
773538e8 4989 pps_unlock(intel_dp);
ed92f0b2 4990
060c8778 4991 mutex_lock(&dev->mode_config.mutex);
0b99836f 4992 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4993 if (edid) {
4994 if (drm_add_edid_modes(connector, edid)) {
4995 drm_mode_connector_update_edid_property(connector,
4996 edid);
4997 drm_edid_to_eld(connector, edid);
4998 } else {
4999 kfree(edid);
5000 edid = ERR_PTR(-EINVAL);
5001 }
5002 } else {
5003 edid = ERR_PTR(-ENOENT);
5004 }
5005 intel_connector->edid = edid;
5006
5007 /* prefer fixed mode from EDID if available */
5008 list_for_each_entry(scan, &connector->probed_modes, head) {
5009 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5010 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 5011 downclock_mode = intel_dp_drrs_init(
5012 intel_dig_port,
5013 intel_connector, fixed_mode);
ed92f0b2
PZ		 5014 break;
5015 }
5016 }
5017
5018 /* fallback to VBT if available for eDP */
5019 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5020 fixed_mode = drm_mode_duplicate(dev,
5021 dev_priv->vbt.lfp_lvds_vbt_mode);
5022 if (fixed_mode)
5023 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5024 }
060c8778 5025 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5026
01527b31
CT		 5027 if (IS_VALLEYVIEW(dev)) {
5028 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5029 register_reboot_notifier(&intel_dp->edp_notifier);
5030 }
5031
4f9db5b5 5032 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5033 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 5034 intel_panel_setup_backlight(connector);
5035
5036 return true;
5037}
5038
16c25533 5039bool
f0fec3f2
PZ		 5040intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5041 struct intel_connector *intel_connector)
a4fc5ed6 5042{
f0fec3f2
PZ		 5043 struct drm_connector *connector = &intel_connector->base;
5044 struct intel_dp *intel_dp = &intel_dig_port->dp;
5045 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5046 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5047 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5048 enum port port = intel_dig_port->port;
0095e6dc 5049 struct edp_power_seq power_seq = { 0 };
0b99836f 5050 int type;
a4fc5ed6 5051
a4a5d2f8
VS		 5052 intel_dp->pps_pipe = INVALID_PIPE;
5053
ec5b01dd
DL		 5054 /* intel_dp vfuncs */
5055 if (IS_VALLEYVIEW(dev))
5056 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5057 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5058 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5059 else if (HAS_PCH_SPLIT(dev))
5060 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5061 else
5062 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5063
153b1100
DL		 5064 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5065
0767935e
DV		 5066 /* Preserve the current hw state. */
5067 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5068 intel_dp->attached_connector = intel_connector;
3d3dc149 5069
3b32a35b 5070 if (intel_dp_is_edp(dev, port))
b329530c 5071 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5072 else
5073 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5074
f7d24902
ID		 5075 /*
5076 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5077 * for DP the encoder type can be set by the caller to
5078 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5079 */
5080 if (type == DRM_MODE_CONNECTOR_eDP)
5081 intel_encoder->type = INTEL_OUTPUT_EDP;
5082
e7281eab
ID		 5083 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5084 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5085 port_name(port));
5086
b329530c 5087 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5088 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5089
a4fc5ed6
KP		 5090 connector->interlace_allowed = true;
5091 connector->doublescan_allowed = 0;
5092
f0fec3f2 5093 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5094 edp_panel_vdd_work);
a4fc5ed6 5095
df0e9248 5096 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5097 drm_connector_register(connector);
a4fc5ed6 5098
affa9354 5099 if (HAS_DDI(dev))
bcbc889b
PZ		 5100 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5101 else
5102 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5103 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5104
0b99836f 5105 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5106 switch (port) {
5107 case PORT_A:
1d843f9d 5108 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5109 break;
5110 case PORT_B:
1d843f9d 5111 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5112 break;
5113 case PORT_C:
1d843f9d 5114 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5115 break;
5116 case PORT_D:
1d843f9d 5117 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5118 break;
5119 default:
ad1c0b19 5120 BUG();
5eb08b69
ZW		 5121 }
5122
dada1a9f 5123 if (is_edp(intel_dp)) {
773538e8 5124 pps_lock(intel_dp);
a4a5d2f8
VS		 5125 if (IS_VALLEYVIEW(dev)) {
5126 vlv_initial_power_sequencer_setup(intel_dp);
5127 } else {
5128 intel_dp_init_panel_power_timestamps(intel_dp);
5129 intel_dp_init_panel_power_sequencer(dev, intel_dp,
5130 &power_seq);
5131 }
773538e8 5132 pps_unlock(intel_dp);
dada1a9f 5133 }
0095e6dc 5134
9d1a1031 5135 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5136
0e32b39c
DA		 5137 /* init MST on ports that can support it */
5138 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5139 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5140 intel_dp_mst_encoder_init(intel_dig_port,
5141 intel_connector->base.base.id);
0e32b39c
DA		 5142 }
5143 }
5144
0095e6dc 5145 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 5146 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5147 if (is_edp(intel_dp)) {
5148 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5149 /*
5150 * vdd might still be enabled do to the delayed vdd off.
5151 * Make sure vdd is actually turned off here.
5152 */
773538e8 5153 pps_lock(intel_dp);
4be73780 5154 edp_panel_vdd_off_sync(intel_dp);
773538e8 5155 pps_unlock(intel_dp);
15b1d171 5156 }
34ea3d38 5157 drm_connector_unregister(connector);
b2f246a8 5158 drm_connector_cleanup(connector);
16c25533 5159 return false;
b2f246a8 5160 }
32f9d658 5161
f684960e
CW		 5162 intel_dp_add_properties(intel_dp, connector);
5163
a4fc5ed6
KP		 5164 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5165 * 0xd. Failure to do so will result in spurious interrupts being
5166 * generated on the port when a cable is not attached.
5167 */
5168 if (IS_G4X(dev) && !IS_GM45(dev)) {
5169 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5170 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5171 }
16c25533
PZ		 5172
5173 return true;
a4fc5ed6 5174}
f0fec3f2
PZ		 5175
5176void
5177intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5178{
13cf5504 5179 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5180 struct intel_digital_port *intel_dig_port;
5181 struct intel_encoder *intel_encoder;
5182 struct drm_encoder *encoder;
5183 struct intel_connector *intel_connector;
5184
b14c5679 5185 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5186 if (!intel_dig_port)
5187 return;
5188
b14c5679 5189 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5190 if (!intel_connector) {
5191 kfree(intel_dig_port);
5192 return;
5193 }
5194
5195 intel_encoder = &intel_dig_port->base;
5196 encoder = &intel_encoder->base;
5197
5198 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5199 DRM_MODE_ENCODER_TMDS);
5200
5bfe2ac0 5201 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5202 intel_encoder->disable = intel_disable_dp;
00c09d70 5203 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5204 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5205 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5206 if (IS_CHERRYVIEW(dev)) {
9197c88b 5207 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5208 intel_encoder->pre_enable = chv_pre_enable_dp;
5209 intel_encoder->enable = vlv_enable_dp;
580d3811 5210 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5211 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5212 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5213 intel_encoder->pre_enable = vlv_pre_enable_dp;
5214 intel_encoder->enable = vlv_enable_dp;
49277c31 5215 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5216 } else {
ecff4f3b
JN		 5217 intel_encoder->pre_enable = g4x_pre_enable_dp;
5218 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5219 if (INTEL_INFO(dev)->gen >= 5)
5220 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5221 }
f0fec3f2 5222
174edf1f 5223 intel_dig_port->port = port;
f0fec3f2
PZ		 5224 intel_dig_port->dp.output_reg = output_reg;
5225
00c09d70 5226 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5227 if (IS_CHERRYVIEW(dev)) {
5228 if (port == PORT_D)
5229 intel_encoder->crtc_mask = 1 << 2;
5230 else
5231 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5232 } else {
5233 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5234 }
bc079e8b 5235 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5236 intel_encoder->hot_plug = intel_dp_hot_plug;
5237
13cf5504
DA		 5238 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5239 dev_priv->hpd_irq_port[port] = intel_dig_port;
5240
15b1d171
PZ		 5241 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5242 drm_encoder_cleanup(encoder);
5243 kfree(intel_dig_port);
b2f246a8 5244 kfree(intel_connector);
15b1d171 5245 }
f0fec3f2 5246}
0e32b39c
DA		 5247
5248void intel_dp_mst_suspend(struct drm_device *dev)
5249{
5250 struct drm_i915_private *dev_priv = dev->dev_private;
5251 int i;
5252
5253 /* disable MST */
5254 for (i = 0; i < I915_MAX_PORTS; i++) {
5255 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5256 if (!intel_dig_port)
5257 continue;
5258
5259 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5260 if (!intel_dig_port->dp.can_mst)
5261 continue;
5262 if (intel_dig_port->dp.is_mst)
5263 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5264 }
5265 }
5266}
5267
5268void intel_dp_mst_resume(struct drm_device *dev)
5269{
5270 struct drm_i915_private *dev_priv = dev->dev_private;
5271 int i;
5272
5273 for (i = 0; i < I915_MAX_PORTS; i++) {
5274 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5275 if (!intel_dig_port)
5276 continue;
5277 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5278 int ret;
5279
5280 if (!intel_dig_port->dp.can_mst)
5281 continue;
5282
5283 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5284 if (ret != 0) {
5285 intel_dp_check_mst_status(&intel_dig_port->dp);
5286 }
5287 }
5288 }
5289}
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