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drm/i915: Always use the fixed panel timing for eDP
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
a4fc5ed6
KP		 30#include "drmP.h"
31#include "drm.h"
32#include "drm_crtc.h"
33#include "drm_crtc_helper.h"
34#include "intel_drv.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
ab2c0672 37#include "drm_dp_helper.h"
a4fc5ed6 38
ae266c98 39
a4fc5ed6
KP		 40#define DP_LINK_STATUS_SIZE 6
41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43#define DP_LINK_CONFIGURATION_SIZE 9
44
32f9d658 45#define IS_eDP(i) ((i)->type == INTEL_OUTPUT_EDP)
f0917379 46#define IS_PCH_eDP(dp_priv) ((dp_priv)->is_pch_edp)
32f9d658 47
a4fc5ed6
KP		 48struct intel_dp_priv {
49 uint32_t output_reg;
50 uint32_t DP;
51 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
a4fc5ed6 52 bool has_audio;
c8110e52 53 int dpms_mode;
a4fc5ed6
KP		 54 uint8_t link_bw;
55 uint8_t lane_count;
56 uint8_t dpcd[4];
21d40d37 57 struct intel_encoder *intel_encoder;
a4fc5ed6
KP		 58 struct i2c_adapter adapter;
59 struct i2c_algo_dp_aux_data algo;
f0917379 60 bool is_pch_edp;
a4fc5ed6
KP		 61};
62
63static void
21d40d37 64intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
a4fc5ed6
KP		 65 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]);
66
67static void
21d40d37 68intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP);
a4fc5ed6 69
32f9d658 70void
21d40d37 71intel_edp_link_config (struct intel_encoder *intel_encoder,
32f9d658
ZW		 72 int *lane_num, int *link_bw)
73{
21d40d37 74 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
32f9d658
ZW		 75
76 *lane_num = dp_priv->lane_count;
77 if (dp_priv->link_bw == DP_LINK_BW_1_62)
78 *link_bw = 162000;
79 else if (dp_priv->link_bw == DP_LINK_BW_2_7)
80 *link_bw = 270000;
81}
82
a4fc5ed6 83static int
21d40d37 84intel_dp_max_lane_count(struct intel_encoder *intel_encoder)
a4fc5ed6 85{
21d40d37 86 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 87 int max_lane_count = 4;
88
89 if (dp_priv->dpcd[0] >= 0x11) {
90 max_lane_count = dp_priv->dpcd[2] & 0x1f;
91 switch (max_lane_count) {
92 case 1: case 2: case 4:
93 break;
94 default:
95 max_lane_count = 4;
96 }
97 }
98 return max_lane_count;
99}
100
101static int
21d40d37 102intel_dp_max_link_bw(struct intel_encoder *intel_encoder)
a4fc5ed6 103{
21d40d37 104 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 105 int max_link_bw = dp_priv->dpcd[1];
106
107 switch (max_link_bw) {
108 case DP_LINK_BW_1_62:
109 case DP_LINK_BW_2_7:
110 break;
111 default:
112 max_link_bw = DP_LINK_BW_1_62;
113 break;
114 }
115 return max_link_bw;
116}
117
118static int
119intel_dp_link_clock(uint8_t link_bw)
120{
121 if (link_bw == DP_LINK_BW_2_7)
122 return 270000;
123 else
124 return 162000;
125}
126
127/* I think this is a fiction */
128static int
885a5fb5 129intel_dp_link_required(struct drm_device *dev,
21d40d37 130 struct intel_encoder *intel_encoder, int pixel_clock)
a4fc5ed6 131{
885a5fb5 132 struct drm_i915_private *dev_priv = dev->dev_private;
36e83a18 133 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
885a5fb5 134
36e83a18 135 if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv))
885a5fb5
ZW		 136 return (pixel_clock * dev_priv->edp_bpp) / 8;
137 else
138 return pixel_clock * 3;
a4fc5ed6
KP		 139}
140
fe27d53e
DA		 141static int
142intel_dp_max_data_rate(int max_link_clock, int max_lanes)
143{
144 return (max_link_clock * max_lanes * 8) / 10;
145}
146
a4fc5ed6
KP		 147static int
148intel_dp_mode_valid(struct drm_connector *connector,
149 struct drm_display_mode *mode)
150{
55f78c43
ZW		 151 struct drm_encoder *encoder = intel_attached_encoder(connector);
152 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
21d40d37
EA		 153 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_encoder));
154 int max_lanes = intel_dp_max_lane_count(intel_encoder);
a4fc5ed6 155
fe27d53e
DA		 156 /* only refuse the mode on non eDP since we have seen some wierd eDP panels
157 which are outside spec tolerances but somehow work by magic */
158 if (!IS_eDP(intel_encoder) &&
159 (intel_dp_link_required(connector->dev, intel_encoder, mode->clock)
160 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
a4fc5ed6
KP		 161 return MODE_CLOCK_HIGH;
162
163 if (mode->clock < 10000)
164 return MODE_CLOCK_LOW;
165
166 return MODE_OK;
167}
168
169static uint32_t
170pack_aux(uint8_t *src, int src_bytes)
171{
172 int i;
173 uint32_t v = 0;
174
175 if (src_bytes > 4)
176 src_bytes = 4;
177 for (i = 0; i < src_bytes; i++)
178 v |= ((uint32_t) src[i]) << ((3-i) * 8);
179 return v;
180}
181
182static void
183unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
184{
185 int i;
186 if (dst_bytes > 4)
187 dst_bytes = 4;
188 for (i = 0; i < dst_bytes; i++)
189 dst[i] = src >> ((3-i) * 8);
190}
191
fb0f8fbf
KP		 192/* hrawclock is 1/4 the FSB frequency */
193static int
194intel_hrawclk(struct drm_device *dev)
195{
196 struct drm_i915_private *dev_priv = dev->dev_private;
197 uint32_t clkcfg;
198
199 clkcfg = I915_READ(CLKCFG);
200 switch (clkcfg & CLKCFG_FSB_MASK) {
201 case CLKCFG_FSB_400:
202 return 100;
203 case CLKCFG_FSB_533:
204 return 133;
205 case CLKCFG_FSB_667:
206 return 166;
207 case CLKCFG_FSB_800:
208 return 200;
209 case CLKCFG_FSB_1067:
210 return 266;
211 case CLKCFG_FSB_1333:
212 return 333;
213 /* these two are just a guess; one of them might be right */
214 case CLKCFG_FSB_1600:
215 case CLKCFG_FSB_1600_ALT:
216 return 400;
217 default:
218 return 133;
219 }
220}
221
a4fc5ed6 222static int
21d40d37 223intel_dp_aux_ch(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 224 uint8_t *send, int send_bytes,
225 uint8_t *recv, int recv_size)
226{
21d40d37 227 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6 228 uint32_t output_reg = dp_priv->output_reg;
55f78c43 229 struct drm_device *dev = intel_encoder->enc.dev;
a4fc5ed6
KP		 230 struct drm_i915_private *dev_priv = dev->dev_private;
231 uint32_t ch_ctl = output_reg + 0x10;
232 uint32_t ch_data = ch_ctl + 4;
233 int i;
234 int recv_bytes;
235 uint32_t ctl;
236 uint32_t status;
fb0f8fbf 237 uint32_t aux_clock_divider;
e3421a18 238 int try, precharge;
a4fc5ed6
KP		 239
240 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 241 * and would like to run at 2MHz. So, take the
242 * hrawclk value and divide by 2 and use that
a4fc5ed6 243 */
e3421a18
ZW		 244 if (IS_eDP(intel_encoder)) {
245 if (IS_GEN6(dev))
246 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
247 else
248 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
249 } else if (HAS_PCH_SPLIT(dev))
f2b115e6 250 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 251 else
252 aux_clock_divider = intel_hrawclk(dev) / 2;
253
e3421a18
ZW		 254 if (IS_GEN6(dev))
255 precharge = 3;
256 else
257 precharge = 5;
258
fb0f8fbf
KP		 259 /* Must try at least 3 times according to DP spec */
260 for (try = 0; try < 5; try++) {
261 /* Load the send data into the aux channel data registers */
262 for (i = 0; i < send_bytes; i += 4) {
a419aef8 263 uint32_t d = pack_aux(send + i, send_bytes - i);
fb0f8fbf
KP		 264
265 I915_WRITE(ch_data + i, d);
266 }
267
268 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
269 DP_AUX_CH_CTL_TIME_OUT_400us |
270 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
e3421a18 271 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
fb0f8fbf
KP		 272 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
273 DP_AUX_CH_CTL_DONE |
274 DP_AUX_CH_CTL_TIME_OUT_ERROR |
275 DP_AUX_CH_CTL_RECEIVE_ERROR);
276
277 /* Send the command and wait for it to complete */
278 I915_WRITE(ch_ctl, ctl);
279 (void) I915_READ(ch_ctl);
280 for (;;) {
281 udelay(100);
282 status = I915_READ(ch_ctl);
283 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
284 break;
285 }
286
287 /* Clear done status and any errors */
eebc863e 288 I915_WRITE(ch_ctl, (status |
fb0f8fbf
KP		 289 DP_AUX_CH_CTL_DONE |
290 DP_AUX_CH_CTL_TIME_OUT_ERROR |
291 DP_AUX_CH_CTL_RECEIVE_ERROR));
292 (void) I915_READ(ch_ctl);
293 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
a4fc5ed6
KP		 294 break;
295 }
296
a4fc5ed6 297 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 298 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 299 return -EBUSY;
a4fc5ed6
KP		 300 }
301
302 /* Check for timeout or receive error.
303 * Timeouts occur when the sink is not connected
304 */
a5b3da54 305 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 306 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 307 return -EIO;
308 }
1ae8c0a5
KP		 309
310 /* Timeouts occur when the device isn't connected, so they're
311 * "normal" -- don't fill the kernel log with these */
a5b3da54 312 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 313 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 314 return -ETIMEDOUT;
a4fc5ed6
KP		 315 }
316
317 /* Unload any bytes sent back from the other side */
318 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
319 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
320
321 if (recv_bytes > recv_size)
322 recv_bytes = recv_size;
323
324 for (i = 0; i < recv_bytes; i += 4) {
325 uint32_t d = I915_READ(ch_data + i);
326
327 unpack_aux(d, recv + i, recv_bytes - i);
328 }
329
330 return recv_bytes;
331}
332
333/* Write data to the aux channel in native mode */
334static int
21d40d37 335intel_dp_aux_native_write(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 336 uint16_t address, uint8_t *send, int send_bytes)
337{
338 int ret;
339 uint8_t msg[20];
340 int msg_bytes;
341 uint8_t ack;
342
343 if (send_bytes > 16)
344 return -1;
345 msg[0] = AUX_NATIVE_WRITE << 4;
346 msg[1] = address >> 8;
eebc863e 347 msg[2] = address & 0xff;
a4fc5ed6
KP		 348 msg[3] = send_bytes - 1;
349 memcpy(&msg[4], send, send_bytes);
350 msg_bytes = send_bytes + 4;
351 for (;;) {
21d40d37 352 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 353 if (ret < 0)
354 return ret;
355 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
356 break;
357 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
358 udelay(100);
359 else
a5b3da54 360 return -EIO;
a4fc5ed6
KP		 361 }
362 return send_bytes;
363}
364
365/* Write a single byte to the aux channel in native mode */
366static int
21d40d37 367intel_dp_aux_native_write_1(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 368 uint16_t address, uint8_t byte)
369{
21d40d37 370 return intel_dp_aux_native_write(intel_encoder, address, &byte, 1);
a4fc5ed6
KP		 371}
372
373/* read bytes from a native aux channel */
374static int
21d40d37 375intel_dp_aux_native_read(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 376 uint16_t address, uint8_t *recv, int recv_bytes)
377{
378 uint8_t msg[4];
379 int msg_bytes;
380 uint8_t reply[20];
381 int reply_bytes;
382 uint8_t ack;
383 int ret;
384
385 msg[0] = AUX_NATIVE_READ << 4;
386 msg[1] = address >> 8;
387 msg[2] = address & 0xff;
388 msg[3] = recv_bytes - 1;
389
390 msg_bytes = 4;
391 reply_bytes = recv_bytes + 1;
392
393 for (;;) {
21d40d37 394 ret = intel_dp_aux_ch(intel_encoder, msg, msg_bytes,
a4fc5ed6 395 reply, reply_bytes);
a5b3da54
KP		 396 if (ret == 0)
397 return -EPROTO;
398 if (ret < 0)
a4fc5ed6
KP		 399 return ret;
400 ack = reply[0];
401 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
402 memcpy(recv, reply + 1, ret - 1);
403 return ret - 1;
404 }
405 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
406 udelay(100);
407 else
a5b3da54 408 return -EIO;
a4fc5ed6
KP		 409 }
410}
411
412static int
ab2c0672
DA		 413intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
414 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 415{
ab2c0672 416 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
a4fc5ed6
KP		 417 struct intel_dp_priv *dp_priv = container_of(adapter,
418 struct intel_dp_priv,
419 adapter);
21d40d37 420 struct intel_encoder *intel_encoder = dp_priv->intel_encoder;
ab2c0672
DA		 421 uint16_t address = algo_data->address;
422 uint8_t msg[5];
423 uint8_t reply[2];
424 int msg_bytes;
425 int reply_bytes;
426 int ret;
427
428 /* Set up the command byte */
429 if (mode & MODE_I2C_READ)
430 msg[0] = AUX_I2C_READ << 4;
431 else
432 msg[0] = AUX_I2C_WRITE << 4;
433
434 if (!(mode & MODE_I2C_STOP))
435 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 436
ab2c0672
DA		 437 msg[1] = address >> 8;
438 msg[2] = address;
439
440 switch (mode) {
441 case MODE_I2C_WRITE:
442 msg[3] = 0;
443 msg[4] = write_byte;
444 msg_bytes = 5;
445 reply_bytes = 1;
446 break;
447 case MODE_I2C_READ:
448 msg[3] = 0;
449 msg_bytes = 4;
450 reply_bytes = 2;
451 break;
452 default:
453 msg_bytes = 3;
454 reply_bytes = 1;
455 break;
456 }
457
458 for (;;) {
21d40d37 459 ret = intel_dp_aux_ch(intel_encoder,
ab2c0672
DA		 460 msg, msg_bytes,
461 reply, reply_bytes);
462 if (ret < 0) {
3ff99164 463 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 464 return ret;
465 }
466 switch (reply[0] & AUX_I2C_REPLY_MASK) {
467 case AUX_I2C_REPLY_ACK:
468 if (mode == MODE_I2C_READ) {
469 *read_byte = reply[1];
470 }
471 return reply_bytes - 1;
472 case AUX_I2C_REPLY_NACK:
3ff99164 473 DRM_DEBUG_KMS("aux_ch nack\n");
ab2c0672
DA		 474 return -EREMOTEIO;
475 case AUX_I2C_REPLY_DEFER:
3ff99164 476 DRM_DEBUG_KMS("aux_ch defer\n");
ab2c0672
DA		 477 udelay(100);
478 break;
479 default:
480 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
481 return -EREMOTEIO;
482 }
483 }
a4fc5ed6
KP		 484}
485
486static int
55f78c43
ZW		 487intel_dp_i2c_init(struct intel_encoder *intel_encoder,
488 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 489{
21d40d37 490 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6 491
d54e9d28 492 DRM_DEBUG_KMS("i2c_init %s\n", name);
a4fc5ed6
KP		 493 dp_priv->algo.running = false;
494 dp_priv->algo.address = 0;
495 dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
496
497 memset(&dp_priv->adapter, '\0', sizeof (dp_priv->adapter));
498 dp_priv->adapter.owner = THIS_MODULE;
499 dp_priv->adapter.class = I2C_CLASS_DDC;
eebc863e
ZW		 500 strncpy (dp_priv->adapter.name, name, sizeof(dp_priv->adapter.name) - 1);
501 dp_priv->adapter.name[sizeof(dp_priv->adapter.name) - 1] = '\0';
a4fc5ed6 502 dp_priv->adapter.algo_data = &dp_priv->algo;
55f78c43 503 dp_priv->adapter.dev.parent = &intel_connector->base.kdev;
a4fc5ed6
KP		 504
505 return i2c_dp_aux_add_bus(&dp_priv->adapter);
506}
507
508static bool
509intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
510 struct drm_display_mode *adjusted_mode)
511{
21d40d37
EA		 512 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
513 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
0d3a1bee
ZY		 514 struct drm_device *dev = encoder->dev;
515 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6 516 int lane_count, clock;
21d40d37
EA		 517 int max_lane_count = intel_dp_max_lane_count(intel_encoder);
518 int max_clock = intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
a4fc5ed6
KP		 519 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
520
0d3a1bee
ZY		 521 if ((IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) &&
522 dev_priv->panel_fixed_mode) {
523 struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode;
524
525 adjusted_mode->hdisplay = fixed_mode->hdisplay;
526 adjusted_mode->hsync_start = fixed_mode->hsync_start;
527 adjusted_mode->hsync_end = fixed_mode->hsync_end;
528 adjusted_mode->htotal = fixed_mode->htotal;
529
530 adjusted_mode->vdisplay = fixed_mode->vdisplay;
531 adjusted_mode->vsync_start = fixed_mode->vsync_start;
532 adjusted_mode->vsync_end = fixed_mode->vsync_end;
533 adjusted_mode->vtotal = fixed_mode->vtotal;
534
535 adjusted_mode->clock = fixed_mode->clock;
536 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
537
538 /*
539 * the mode->clock is used to calculate the Data&Link M/N
540 * of the pipe. For the eDP the fixed clock should be used.
541 */
542 mode->clock = dev_priv->panel_fixed_mode->clock;
543 }
544
a4fc5ed6
KP		 545 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
546 for (clock = 0; clock <= max_clock; clock++) {
fe27d53e 547 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 548
21d40d37 549 if (intel_dp_link_required(encoder->dev, intel_encoder, mode->clock)
885a5fb5 550 <= link_avail) {
a4fc5ed6
KP		 551 dp_priv->link_bw = bws[clock];
552 dp_priv->lane_count = lane_count;
553 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
28c97730
ZY		 554 DRM_DEBUG_KMS("Display port link bw %02x lane "
555 "count %d clock %d\n",
a4fc5ed6
KP		 556 dp_priv->link_bw, dp_priv->lane_count,
557 adjusted_mode->clock);
558 return true;
559 }
560 }
561 }
fe27d53e 562
4f444071 563 if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) {
fe27d53e
DA		 564 /* okay we failed just pick the highest */
565 dp_priv->lane_count = max_lane_count;
566 dp_priv->link_bw = bws[max_clock];
567 adjusted_mode->clock = intel_dp_link_clock(dp_priv->link_bw);
568 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
569 "count %d clock %d\n",
570 dp_priv->link_bw, dp_priv->lane_count,
571 adjusted_mode->clock);
572 return true;
573 }
a4fc5ed6
KP		 574 return false;
575}
576
577struct intel_dp_m_n {
578 uint32_t tu;
579 uint32_t gmch_m;
580 uint32_t gmch_n;
581 uint32_t link_m;
582 uint32_t link_n;
583};
584
585static void
586intel_reduce_ratio(uint32_t *num, uint32_t *den)
587{
588 while (*num > 0xffffff || *den > 0xffffff) {
589 *num >>= 1;
590 *den >>= 1;
591 }
592}
593
594static void
36e83a18 595intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 596 int nlanes,
597 int pixel_clock,
598 int link_clock,
599 struct intel_dp_m_n *m_n)
600{
601 m_n->tu = 64;
36e83a18 602 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 603 m_n->gmch_n = link_clock * nlanes;
604 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
605 m_n->link_m = pixel_clock;
606 m_n->link_n = link_clock;
607 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
608}
609
36e83a18
ZY		 610bool intel_pch_has_edp(struct drm_crtc *crtc)
611{
612 struct drm_device *dev = crtc->dev;
613 struct drm_mode_config *mode_config = &dev->mode_config;
614 struct drm_encoder *encoder;
615
616 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
617 struct intel_encoder *intel_encoder;
618 struct intel_dp_priv *dp_priv;
619
620 if (!encoder || encoder->crtc != crtc)
621 continue;
622
623 intel_encoder = enc_to_intel_encoder(encoder);
624 dp_priv = intel_encoder->dev_priv;
625
626 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT)
f0917379 627 return dp_priv->is_pch_edp;
36e83a18
ZY		 628 }
629 return false;
630}
631
a4fc5ed6
KP		 632void
633intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
634 struct drm_display_mode *adjusted_mode)
635{
636 struct drm_device *dev = crtc->dev;
637 struct drm_mode_config *mode_config = &dev->mode_config;
55f78c43 638 struct drm_encoder *encoder;
a4fc5ed6
KP		 639 struct drm_i915_private *dev_priv = dev->dev_private;
640 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
36e83a18 641 int lane_count = 4, bpp = 24;
a4fc5ed6
KP		 642 struct intel_dp_m_n m_n;
643
644 /*
21d40d37 645 * Find the lane count in the intel_encoder private
a4fc5ed6 646 */
55f78c43
ZW		 647 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
648 struct intel_encoder *intel_encoder;
649 struct intel_dp_priv *dp_priv;
a4fc5ed6 650
d8201ab6 651 if (encoder->crtc != crtc)
a4fc5ed6
KP		 652 continue;
653
55f78c43
ZW		 654 intel_encoder = enc_to_intel_encoder(encoder);
655 dp_priv = intel_encoder->dev_priv;
656
21d40d37 657 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
a4fc5ed6 658 lane_count = dp_priv->lane_count;
36e83a18
ZY		 659 if (IS_PCH_eDP(dp_priv))
660 bpp = dev_priv->edp_bpp;
a4fc5ed6
KP		 661 break;
662 }
663 }
664
665 /*
666 * Compute the GMCH and Link ratios. The '3' here is
667 * the number of bytes_per_pixel post-LUT, which we always
668 * set up for 8-bits of R/G/B, or 3 bytes total.
669 */
36e83a18 670 intel_dp_compute_m_n(bpp, lane_count,
a4fc5ed6
KP		 671 mode->clock, adjusted_mode->clock, &m_n);
672
c619eed4 673 if (HAS_PCH_SPLIT(dev)) {
5eb08b69
ZW		 674 if (intel_crtc->pipe == 0) {
675 I915_WRITE(TRANSA_DATA_M1,
676 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
677 m_n.gmch_m);
678 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
679 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
680 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
681 } else {
682 I915_WRITE(TRANSB_DATA_M1,
683 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
684 m_n.gmch_m);
685 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
686 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
687 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
688 }
a4fc5ed6 689 } else {
5eb08b69
ZW		 690 if (intel_crtc->pipe == 0) {
691 I915_WRITE(PIPEA_GMCH_DATA_M,
692 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
693 m_n.gmch_m);
694 I915_WRITE(PIPEA_GMCH_DATA_N,
695 m_n.gmch_n);
696 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
697 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
698 } else {
699 I915_WRITE(PIPEB_GMCH_DATA_M,
700 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
701 m_n.gmch_m);
702 I915_WRITE(PIPEB_GMCH_DATA_N,
703 m_n.gmch_n);
704 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
705 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
706 }
a4fc5ed6
KP		 707 }
708}
709
710static void
711intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
712 struct drm_display_mode *adjusted_mode)
713{
e3421a18 714 struct drm_device *dev = encoder->dev;
21d40d37
EA		 715 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
716 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
717 struct drm_crtc *crtc = intel_encoder->enc.crtc;
a4fc5ed6
KP		 718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
719
e3421a18 720 dp_priv->DP = (DP_VOLTAGE_0_4 |
9c9e7927
AJ		 721 DP_PRE_EMPHASIS_0);
722
723 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
724 dp_priv->DP |= DP_SYNC_HS_HIGH;
725 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
726 dp_priv->DP |= DP_SYNC_VS_HIGH;
a4fc5ed6 727
e3421a18
ZW		 728 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
729 dp_priv->DP |= DP_LINK_TRAIN_OFF_CPT;
730 else
731 dp_priv->DP |= DP_LINK_TRAIN_OFF;
a4fc5ed6
KP		 732
733 switch (dp_priv->lane_count) {
734 case 1:
735 dp_priv->DP |= DP_PORT_WIDTH_1;
736 break;
737 case 2:
738 dp_priv->DP |= DP_PORT_WIDTH_2;
739 break;
740 case 4:
741 dp_priv->DP |= DP_PORT_WIDTH_4;
742 break;
743 }
744 if (dp_priv->has_audio)
745 dp_priv->DP |= DP_AUDIO_OUTPUT_ENABLE;
746
747 memset(dp_priv->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
748 dp_priv->link_configuration[0] = dp_priv->link_bw;
749 dp_priv->link_configuration[1] = dp_priv->lane_count;
750
751 /*
9962c925 752 * Check for DPCD version > 1.1 and enhanced framing support
a4fc5ed6 753 */
9962c925 754 if (dp_priv->dpcd[0] >= 0x11 && (dp_priv->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
a4fc5ed6
KP		 755 dp_priv->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
756 dp_priv->DP |= DP_ENHANCED_FRAMING;
757 }
758
e3421a18
ZW		 759 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
760 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
a4fc5ed6 761 dp_priv->DP |= DP_PIPEB_SELECT;
32f9d658 762
21d40d37 763 if (IS_eDP(intel_encoder)) {
32f9d658
ZW		 764 /* don't miss out required setting for eDP */
765 dp_priv->DP |= DP_PLL_ENABLE;
766 if (adjusted_mode->clock < 200000)
767 dp_priv->DP |= DP_PLL_FREQ_160MHZ;
768 else
769 dp_priv->DP |= DP_PLL_FREQ_270MHZ;
770 }
a4fc5ed6
KP		 771}
772
9934c132
JB		 773static void ironlake_edp_panel_on (struct drm_device *dev)
774{
775 struct drm_i915_private *dev_priv = dev->dev_private;
776 unsigned long timeout = jiffies + msecs_to_jiffies(5000);
777 u32 pp, pp_status;
778
779 pp_status = I915_READ(PCH_PP_STATUS);
780 if (pp_status & PP_ON)
781 return;
782
783 pp = I915_READ(PCH_PP_CONTROL);
784 pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
785 I915_WRITE(PCH_PP_CONTROL, pp);
786 do {
787 pp_status = I915_READ(PCH_PP_STATUS);
788 } while (((pp_status & PP_ON) == 0) && !time_after(jiffies, timeout));
789
790 if (time_after(jiffies, timeout))
791 DRM_DEBUG_KMS("panel on wait timed out: 0x%08x\n", pp_status);
792
793 pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD);
794 I915_WRITE(PCH_PP_CONTROL, pp);
795}
796
797static void ironlake_edp_panel_off (struct drm_device *dev)
798{
799 struct drm_i915_private *dev_priv = dev->dev_private;
800 unsigned long timeout = jiffies + msecs_to_jiffies(5000);
801 u32 pp, pp_status;
802
803 pp = I915_READ(PCH_PP_CONTROL);
804 pp &= ~POWER_TARGET_ON;
805 I915_WRITE(PCH_PP_CONTROL, pp);
806 do {
807 pp_status = I915_READ(PCH_PP_STATUS);
808 } while ((pp_status & PP_ON) && !time_after(jiffies, timeout));
809
810 if (time_after(jiffies, timeout))
811 DRM_DEBUG_KMS("panel off wait timed out\n");
812
813 /* Make sure VDD is enabled so DP AUX will work */
814 pp |= EDP_FORCE_VDD;
815 I915_WRITE(PCH_PP_CONTROL, pp);
816}
817
f2b115e6 818static void ironlake_edp_backlight_on (struct drm_device *dev)
32f9d658
ZW		 819{
820 struct drm_i915_private *dev_priv = dev->dev_private;
821 u32 pp;
822
28c97730 823 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 824 pp = I915_READ(PCH_PP_CONTROL);
825 pp |= EDP_BLC_ENABLE;
826 I915_WRITE(PCH_PP_CONTROL, pp);
827}
828
f2b115e6 829static void ironlake_edp_backlight_off (struct drm_device *dev)
32f9d658
ZW		 830{
831 struct drm_i915_private *dev_priv = dev->dev_private;
832 u32 pp;
833
28c97730 834 DRM_DEBUG_KMS("\n");
32f9d658
ZW		 835 pp = I915_READ(PCH_PP_CONTROL);
836 pp &= ~EDP_BLC_ENABLE;
837 I915_WRITE(PCH_PP_CONTROL, pp);
838}
a4fc5ed6
KP		 839
840static void
841intel_dp_dpms(struct drm_encoder *encoder, int mode)
842{
21d40d37
EA		 843 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
844 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
55f78c43 845 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 846 struct drm_i915_private *dev_priv = dev->dev_private;
847 uint32_t dp_reg = I915_READ(dp_priv->output_reg);
848
849 if (mode != DRM_MODE_DPMS_ON) {
32f9d658 850 if (dp_reg & DP_PORT_EN) {
21d40d37 851 intel_dp_link_down(intel_encoder, dp_priv->DP);
2bd34f6c 852 if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) {
f2b115e6 853 ironlake_edp_backlight_off(dev);
5620ae29 854 ironlake_edp_panel_off(dev);
9934c132 855 }
32f9d658 856 }
a4fc5ed6 857 } else {
32f9d658 858 if (!(dp_reg & DP_PORT_EN)) {
21d40d37 859 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
2bd34f6c 860 if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) {
9934c132 861 ironlake_edp_panel_on(dev);
f2b115e6 862 ironlake_edp_backlight_on(dev);
9934c132 863 }
32f9d658 864 }
a4fc5ed6 865 }
c8110e52 866 dp_priv->dpms_mode = mode;
a4fc5ed6
KP		 867}
868
869/*
870 * Fetch AUX CH registers 0x202 - 0x207 which contain
871 * link status information
872 */
873static bool
21d40d37 874intel_dp_get_link_status(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 875 uint8_t link_status[DP_LINK_STATUS_SIZE])
876{
877 int ret;
878
21d40d37 879 ret = intel_dp_aux_native_read(intel_encoder,
a4fc5ed6
KP		 880 DP_LANE0_1_STATUS,
881 link_status, DP_LINK_STATUS_SIZE);
882 if (ret != DP_LINK_STATUS_SIZE)
883 return false;
884 return true;
885}
886
887static uint8_t
888intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
889 int r)
890{
891 return link_status[r - DP_LANE0_1_STATUS];
892}
893
a4fc5ed6
KP		 894static uint8_t
895intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
896 int lane)
897{
898 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
899 int s = ((lane & 1) ?
900 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
901 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
902 uint8_t l = intel_dp_link_status(link_status, i);
903
904 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
905}
906
907static uint8_t
908intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
909 int lane)
910{
911 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
912 int s = ((lane & 1) ?
913 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
914 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
915 uint8_t l = intel_dp_link_status(link_status, i);
916
917 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
918}
919
920
921#if 0
922static char *voltage_names[] = {
923 "0.4V", "0.6V", "0.8V", "1.2V"
924};
925static char *pre_emph_names[] = {
926 "0dB", "3.5dB", "6dB", "9.5dB"
927};
928static char *link_train_names[] = {
929 "pattern 1", "pattern 2", "idle", "off"
930};
931#endif
932
933/*
934 * These are source-specific values; current Intel hardware supports
935 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
936 */
937#define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
938
939static uint8_t
940intel_dp_pre_emphasis_max(uint8_t voltage_swing)
941{
942 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
943 case DP_TRAIN_VOLTAGE_SWING_400:
944 return DP_TRAIN_PRE_EMPHASIS_6;
945 case DP_TRAIN_VOLTAGE_SWING_600:
946 return DP_TRAIN_PRE_EMPHASIS_6;
947 case DP_TRAIN_VOLTAGE_SWING_800:
948 return DP_TRAIN_PRE_EMPHASIS_3_5;
949 case DP_TRAIN_VOLTAGE_SWING_1200:
950 default:
951 return DP_TRAIN_PRE_EMPHASIS_0;
952 }
953}
954
955static void
21d40d37 956intel_get_adjust_train(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 957 uint8_t link_status[DP_LINK_STATUS_SIZE],
958 int lane_count,
959 uint8_t train_set[4])
960{
961 uint8_t v = 0;
962 uint8_t p = 0;
963 int lane;
964
965 for (lane = 0; lane < lane_count; lane++) {
966 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
967 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
968
969 if (this_v > v)
970 v = this_v;
971 if (this_p > p)
972 p = this_p;
973 }
974
975 if (v >= I830_DP_VOLTAGE_MAX)
976 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
977
978 if (p >= intel_dp_pre_emphasis_max(v))
979 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
980
981 for (lane = 0; lane < 4; lane++)
982 train_set[lane] = v | p;
983}
984
985static uint32_t
986intel_dp_signal_levels(uint8_t train_set, int lane_count)
987{
988 uint32_t signal_levels = 0;
989
990 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
991 case DP_TRAIN_VOLTAGE_SWING_400:
992 default:
993 signal_levels |= DP_VOLTAGE_0_4;
994 break;
995 case DP_TRAIN_VOLTAGE_SWING_600:
996 signal_levels |= DP_VOLTAGE_0_6;
997 break;
998 case DP_TRAIN_VOLTAGE_SWING_800:
999 signal_levels |= DP_VOLTAGE_0_8;
1000 break;
1001 case DP_TRAIN_VOLTAGE_SWING_1200:
1002 signal_levels |= DP_VOLTAGE_1_2;
1003 break;
1004 }
1005 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1006 case DP_TRAIN_PRE_EMPHASIS_0:
1007 default:
1008 signal_levels |= DP_PRE_EMPHASIS_0;
1009 break;
1010 case DP_TRAIN_PRE_EMPHASIS_3_5:
1011 signal_levels |= DP_PRE_EMPHASIS_3_5;
1012 break;
1013 case DP_TRAIN_PRE_EMPHASIS_6:
1014 signal_levels |= DP_PRE_EMPHASIS_6;
1015 break;
1016 case DP_TRAIN_PRE_EMPHASIS_9_5:
1017 signal_levels |= DP_PRE_EMPHASIS_9_5;
1018 break;
1019 }
1020 return signal_levels;
1021}
1022
e3421a18
ZW		 1023/* Gen6's DP voltage swing and pre-emphasis control */
1024static uint32_t
1025intel_gen6_edp_signal_levels(uint8_t train_set)
1026{
1027 switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
1028 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1029 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1030 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1031 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
1032 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1033 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
1034 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1035 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
1036 default:
1037 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
1038 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1039 }
1040}
1041
a4fc5ed6
KP		 1042static uint8_t
1043intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1044 int lane)
1045{
1046 int i = DP_LANE0_1_STATUS + (lane >> 1);
1047 int s = (lane & 1) * 4;
1048 uint8_t l = intel_dp_link_status(link_status, i);
1049
1050 return (l >> s) & 0xf;
1051}
1052
1053/* Check for clock recovery is done on all channels */
1054static bool
1055intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1056{
1057 int lane;
1058 uint8_t lane_status;
1059
1060 for (lane = 0; lane < lane_count; lane++) {
1061 lane_status = intel_get_lane_status(link_status, lane);
1062 if ((lane_status & DP_LANE_CR_DONE) == 0)
1063 return false;
1064 }
1065 return true;
1066}
1067
1068/* Check to see if channel eq is done on all channels */
1069#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1070 DP_LANE_CHANNEL_EQ_DONE|\
1071 DP_LANE_SYMBOL_LOCKED)
1072static bool
1073intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1074{
1075 uint8_t lane_align;
1076 uint8_t lane_status;
1077 int lane;
1078
1079 lane_align = intel_dp_link_status(link_status,
1080 DP_LANE_ALIGN_STATUS_UPDATED);
1081 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1082 return false;
1083 for (lane = 0; lane < lane_count; lane++) {
1084 lane_status = intel_get_lane_status(link_status, lane);
1085 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1086 return false;
1087 }
1088 return true;
1089}
1090
1091static bool
21d40d37 1092intel_dp_set_link_train(struct intel_encoder *intel_encoder,
a4fc5ed6
KP		 1093 uint32_t dp_reg_value,
1094 uint8_t dp_train_pat,
1095 uint8_t train_set[4],
1096 bool first)
1097{
55f78c43 1098 struct drm_device *dev = intel_encoder->enc.dev;
a4fc5ed6 1099 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 1100 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 1101 int ret;
1102
1103 I915_WRITE(dp_priv->output_reg, dp_reg_value);
1104 POSTING_READ(dp_priv->output_reg);
1105 if (first)
1106 intel_wait_for_vblank(dev);
1107
21d40d37 1108 intel_dp_aux_native_write_1(intel_encoder,
a4fc5ed6
KP		 1109 DP_TRAINING_PATTERN_SET,
1110 dp_train_pat);
1111
21d40d37 1112 ret = intel_dp_aux_native_write(intel_encoder,
a4fc5ed6
KP		 1113 DP_TRAINING_LANE0_SET, train_set, 4);
1114 if (ret != 4)
1115 return false;
1116
1117 return true;
1118}
1119
1120static void
21d40d37 1121intel_dp_link_train(struct intel_encoder *intel_encoder, uint32_t DP,
a4fc5ed6
KP		 1122 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE])
1123{
55f78c43 1124 struct drm_device *dev = intel_encoder->enc.dev;
a4fc5ed6 1125 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 1126 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 1127 uint8_t train_set[4];
1128 uint8_t link_status[DP_LINK_STATUS_SIZE];
1129 int i;
1130 uint8_t voltage;
1131 bool clock_recovery = false;
1132 bool channel_eq = false;
1133 bool first = true;
1134 int tries;
e3421a18 1135 u32 reg;
a4fc5ed6
KP		 1136
1137 /* Write the link configuration data */
ab00a9ef 1138 intel_dp_aux_native_write(intel_encoder, DP_LINK_BW_SET,
a4fc5ed6
KP		 1139 link_configuration, DP_LINK_CONFIGURATION_SIZE);
1140
1141 DP |= DP_PORT_EN;
e3421a18
ZW		 1142 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1143 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1144 else
1145 DP &= ~DP_LINK_TRAIN_MASK;
a4fc5ed6
KP		 1146 memset(train_set, 0, 4);
1147 voltage = 0xff;
1148 tries = 0;
1149 clock_recovery = false;
1150 for (;;) {
1151 /* Use train_set[0] to set the voltage and pre emphasis values */
e3421a18
ZW		 1152 uint32_t signal_levels;
1153 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
1154 signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1155 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1156 } else {
1157 signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1158 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1159 }
a4fc5ed6 1160
e3421a18
ZW		 1161 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1162 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1163 else
1164 reg = DP | DP_LINK_TRAIN_PAT_1;
1165
1166 if (!intel_dp_set_link_train(intel_encoder, reg,
a4fc5ed6
KP		 1167 DP_TRAINING_PATTERN_1, train_set, first))
1168 break;
1169 first = false;
1170 /* Set training pattern 1 */
1171
1172 udelay(100);
21d40d37 1173 if (!intel_dp_get_link_status(intel_encoder, link_status))
a4fc5ed6
KP		 1174 break;
1175
1176 if (intel_clock_recovery_ok(link_status, dp_priv->lane_count)) {
1177 clock_recovery = true;
1178 break;
1179 }
1180
1181 /* Check to see if we've tried the max voltage */
1182 for (i = 0; i < dp_priv->lane_count; i++)
1183 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1184 break;
1185 if (i == dp_priv->lane_count)
1186 break;
1187
1188 /* Check to see if we've tried the same voltage 5 times */
1189 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1190 ++tries;
1191 if (tries == 5)
1192 break;
1193 } else
1194 tries = 0;
1195 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1196
1197 /* Compute new train_set as requested by target */
21d40d37 1198 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
a4fc5ed6
KP		 1199 }
1200
1201 /* channel equalization */
1202 tries = 0;
1203 channel_eq = false;
1204 for (;;) {
1205 /* Use train_set[0] to set the voltage and pre emphasis values */
e3421a18
ZW		 1206 uint32_t signal_levels;
1207
1208 if (IS_GEN6(dev) && IS_eDP(intel_encoder)) {
1209 signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1210 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1211 } else {
1212 signal_levels = intel_dp_signal_levels(train_set[0], dp_priv->lane_count);
1213 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1214 }
1215
1216 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1217 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1218 else
1219 reg = DP | DP_LINK_TRAIN_PAT_2;
a4fc5ed6
KP		 1220
1221 /* channel eq pattern */
e3421a18 1222 if (!intel_dp_set_link_train(intel_encoder, reg,
a4fc5ed6
KP		 1223 DP_TRAINING_PATTERN_2, train_set,
1224 false))
1225 break;
1226
1227 udelay(400);
21d40d37 1228 if (!intel_dp_get_link_status(intel_encoder, link_status))
a4fc5ed6
KP		 1229 break;
1230
1231 if (intel_channel_eq_ok(link_status, dp_priv->lane_count)) {
1232 channel_eq = true;
1233 break;
1234 }
1235
1236 /* Try 5 times */
1237 if (tries > 5)
1238 break;
1239
1240 /* Compute new train_set as requested by target */
21d40d37 1241 intel_get_adjust_train(intel_encoder, link_status, dp_priv->lane_count, train_set);
a4fc5ed6
KP		 1242 ++tries;
1243 }
1244
e3421a18
ZW		 1245 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder))
1246 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1247 else
1248 reg = DP | DP_LINK_TRAIN_OFF;
1249
1250 I915_WRITE(dp_priv->output_reg, reg);
a4fc5ed6 1251 POSTING_READ(dp_priv->output_reg);
21d40d37 1252 intel_dp_aux_native_write_1(intel_encoder,
a4fc5ed6
KP		 1253 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1254}
1255
1256static void
21d40d37 1257intel_dp_link_down(struct intel_encoder *intel_encoder, uint32_t DP)
a4fc5ed6 1258{
55f78c43 1259 struct drm_device *dev = intel_encoder->enc.dev;
a4fc5ed6 1260 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 1261 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6 1262
28c97730 1263 DRM_DEBUG_KMS("\n");
32f9d658 1264
21d40d37 1265 if (IS_eDP(intel_encoder)) {
32f9d658
ZW		 1266 DP &= ~DP_PLL_ENABLE;
1267 I915_WRITE(dp_priv->output_reg, DP);
1268 POSTING_READ(dp_priv->output_reg);
1269 udelay(100);
1270 }
1271
e3421a18
ZW		 1272 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_encoder)) {
1273 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1274 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1275 POSTING_READ(dp_priv->output_reg);
1276 } else {
1277 DP &= ~DP_LINK_TRAIN_MASK;
1278 I915_WRITE(dp_priv->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1279 POSTING_READ(dp_priv->output_reg);
1280 }
5eb08b69
ZW		 1281
1282 udelay(17000);
1283
21d40d37 1284 if (IS_eDP(intel_encoder))
32f9d658 1285 DP |= DP_LINK_TRAIN_OFF;
a4fc5ed6
KP		 1286 I915_WRITE(dp_priv->output_reg, DP & ~DP_PORT_EN);
1287 POSTING_READ(dp_priv->output_reg);
1288}
1289
a4fc5ed6
KP		 1290/*
1291 * According to DP spec
1292 * 5.1.2:
1293 * 1. Read DPCD
1294 * 2. Configure link according to Receiver Capabilities
1295 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1296 * 4. Check link status on receipt of hot-plug interrupt
1297 */
1298
1299static void
21d40d37 1300intel_dp_check_link_status(struct intel_encoder *intel_encoder)
a4fc5ed6 1301{
21d40d37 1302 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 1303 uint8_t link_status[DP_LINK_STATUS_SIZE];
1304
21d40d37 1305 if (!intel_encoder->enc.crtc)
a4fc5ed6
KP		 1306 return;
1307
21d40d37
EA		 1308 if (!intel_dp_get_link_status(intel_encoder, link_status)) {
1309 intel_dp_link_down(intel_encoder, dp_priv->DP);
a4fc5ed6
KP		 1310 return;
1311 }
1312
1313 if (!intel_channel_eq_ok(link_status, dp_priv->lane_count))
21d40d37 1314 intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
a4fc5ed6 1315}
a4fc5ed6 1316
5eb08b69 1317static enum drm_connector_status
f2b115e6 1318ironlake_dp_detect(struct drm_connector *connector)
5eb08b69 1319{
55f78c43
ZW		 1320 struct drm_encoder *encoder = intel_attached_encoder(connector);
1321 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
21d40d37 1322 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
5eb08b69
ZW		 1323 enum drm_connector_status status;
1324
1325 status = connector_status_disconnected;
21d40d37 1326 if (intel_dp_aux_native_read(intel_encoder,
5eb08b69
ZW		 1327 0x000, dp_priv->dpcd,
1328 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1329 {
1330 if (dp_priv->dpcd[0] != 0)
1331 status = connector_status_connected;
1332 }
a7de64e5
AJ		 1333 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", dp_priv->dpcd[0],
1334 dp_priv->dpcd[1], dp_priv->dpcd[2], dp_priv->dpcd[3]);
5eb08b69
ZW		 1335 return status;
1336}
1337
a4fc5ed6
KP		 1338/**
1339 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1340 *
1341 * \return true if DP port is connected.
1342 * \return false if DP port is disconnected.
1343 */
1344static enum drm_connector_status
1345intel_dp_detect(struct drm_connector *connector)
1346{
55f78c43
ZW		 1347 struct drm_encoder *encoder = intel_attached_encoder(connector);
1348 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1349 struct drm_device *dev = intel_encoder->enc.dev;
a4fc5ed6 1350 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 1351 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
a4fc5ed6
KP		 1352 uint32_t temp, bit;
1353 enum drm_connector_status status;
1354
1355 dp_priv->has_audio = false;
1356
c619eed4 1357 if (HAS_PCH_SPLIT(dev))
f2b115e6 1358 return ironlake_dp_detect(connector);
5eb08b69 1359
a4fc5ed6
KP		 1360 switch (dp_priv->output_reg) {
1361 case DP_B:
1362 bit = DPB_HOTPLUG_INT_STATUS;
1363 break;
1364 case DP_C:
1365 bit = DPC_HOTPLUG_INT_STATUS;
1366 break;
1367 case DP_D:
1368 bit = DPD_HOTPLUG_INT_STATUS;
1369 break;
1370 default:
1371 return connector_status_unknown;
1372 }
1373
1374 temp = I915_READ(PORT_HOTPLUG_STAT);
1375
1376 if ((temp & bit) == 0)
1377 return connector_status_disconnected;
1378
1379 status = connector_status_disconnected;
21d40d37 1380 if (intel_dp_aux_native_read(intel_encoder,
a4fc5ed6
KP		 1381 0x000, dp_priv->dpcd,
1382 sizeof (dp_priv->dpcd)) == sizeof (dp_priv->dpcd))
1383 {
1384 if (dp_priv->dpcd[0] != 0)
1385 status = connector_status_connected;
1386 }
1387 return status;
1388}
1389
1390static int intel_dp_get_modes(struct drm_connector *connector)
1391{
55f78c43
ZW		 1392 struct drm_encoder *encoder = intel_attached_encoder(connector);
1393 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1394 struct drm_device *dev = intel_encoder->enc.dev;
32f9d658 1395 struct drm_i915_private *dev_priv = dev->dev_private;
36e83a18 1396 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
32f9d658 1397 int ret;
a4fc5ed6
KP		 1398
1399 /* We should parse the EDID data and find out if it has an audio sink
1400 */
1401
335af9a2 1402 ret = intel_ddc_get_modes(connector, intel_encoder->ddc_bus);
b9efc480
ZY		 1403 if (ret) {
1404 if ((IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) &&
1405 !dev_priv->panel_fixed_mode) {
1406 struct drm_display_mode *newmode;
1407 list_for_each_entry(newmode, &connector->probed_modes,
1408 head) {
1409 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1410 dev_priv->panel_fixed_mode =
1411 drm_mode_duplicate(dev, newmode);
1412 break;
1413 }
1414 }
1415 }
1416
32f9d658 1417 return ret;
b9efc480 1418 }
32f9d658
ZW		 1419
1420 /* if eDP has no EDID, try to use fixed panel mode from VBT */
36e83a18 1421 if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) {
32f9d658
ZW		 1422 if (dev_priv->panel_fixed_mode != NULL) {
1423 struct drm_display_mode *mode;
1424 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1425 drm_mode_probed_add(connector, mode);
1426 return 1;
1427 }
1428 }
1429 return 0;
a4fc5ed6
KP		 1430}
1431
1432static void
1433intel_dp_destroy (struct drm_connector *connector)
1434{
a4fc5ed6
KP		 1435 drm_sysfs_connector_remove(connector);
1436 drm_connector_cleanup(connector);
55f78c43 1437 kfree(connector);
a4fc5ed6
KP		 1438}
1439
1440static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1441 .dpms = intel_dp_dpms,
1442 .mode_fixup = intel_dp_mode_fixup,
1443 .prepare = intel_encoder_prepare,
1444 .mode_set = intel_dp_mode_set,
1445 .commit = intel_encoder_commit,
1446};
1447
1448static const struct drm_connector_funcs intel_dp_connector_funcs = {
1449 .dpms = drm_helper_connector_dpms,
a4fc5ed6
KP		 1450 .detect = intel_dp_detect,
1451 .fill_modes = drm_helper_probe_single_connector_modes,
1452 .destroy = intel_dp_destroy,
1453};
1454
1455static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1456 .get_modes = intel_dp_get_modes,
1457 .mode_valid = intel_dp_mode_valid,
55f78c43 1458 .best_encoder = intel_attached_encoder,
a4fc5ed6
KP		 1459};
1460
1461static void intel_dp_enc_destroy(struct drm_encoder *encoder)
1462{
55f78c43
ZW		 1463 struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
1464
1465 if (intel_encoder->i2c_bus)
1466 intel_i2c_destroy(intel_encoder->i2c_bus);
a4fc5ed6 1467 drm_encoder_cleanup(encoder);
55f78c43 1468 kfree(intel_encoder);
a4fc5ed6
KP		 1469}
1470
1471static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1472 .destroy = intel_dp_enc_destroy,
1473};
1474
c8110e52 1475void
21d40d37 1476intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 1477{
21d40d37 1478 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
c8110e52
KP		 1479
1480 if (dp_priv->dpms_mode == DRM_MODE_DPMS_ON)
21d40d37 1481 intel_dp_check_link_status(intel_encoder);
c8110e52 1482}
6207937d 1483
e3421a18
ZW		 1484/* Return which DP Port should be selected for Transcoder DP control */
1485int
1486intel_trans_dp_port_sel (struct drm_crtc *crtc)
1487{
1488 struct drm_device *dev = crtc->dev;
1489 struct drm_mode_config *mode_config = &dev->mode_config;
1490 struct drm_encoder *encoder;
1491 struct intel_encoder *intel_encoder = NULL;
1492
1493 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
d8201ab6 1494 if (encoder->crtc != crtc)
e3421a18
ZW		 1495 continue;
1496
1497 intel_encoder = enc_to_intel_encoder(encoder);
1498 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1499 struct intel_dp_priv *dp_priv = intel_encoder->dev_priv;
1500 return dp_priv->output_reg;
1501 }
1502 }
1503 return -1;
1504}
1505
36e83a18 1506/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 1507bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 1508{
1509 struct drm_i915_private *dev_priv = dev->dev_private;
1510 struct child_device_config *p_child;
1511 int i;
1512
1513 if (!dev_priv->child_dev_num)
1514 return false;
1515
1516 for (i = 0; i < dev_priv->child_dev_num; i++) {
1517 p_child = dev_priv->child_dev + i;
1518
1519 if (p_child->dvo_port == PORT_IDPD &&
1520 p_child->device_type == DEVICE_TYPE_eDP)
1521 return true;
1522 }
1523 return false;
1524}
1525
a4fc5ed6
KP		 1526void
1527intel_dp_init(struct drm_device *dev, int output_reg)
1528{
1529 struct drm_i915_private *dev_priv = dev->dev_private;
1530 struct drm_connector *connector;
21d40d37 1531 struct intel_encoder *intel_encoder;
55f78c43 1532 struct intel_connector *intel_connector;
a4fc5ed6 1533 struct intel_dp_priv *dp_priv;
5eb08b69 1534 const char *name = NULL;
b329530c 1535 int type;
a4fc5ed6 1536
21d40d37 1537 intel_encoder = kcalloc(sizeof(struct intel_encoder) +
a4fc5ed6 1538 sizeof(struct intel_dp_priv), 1, GFP_KERNEL);
21d40d37 1539 if (!intel_encoder)
a4fc5ed6
KP		 1540 return;
1541
55f78c43
ZW		 1542 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1543 if (!intel_connector) {
1544 kfree(intel_encoder);
1545 return;
1546 }
1547
21d40d37 1548 dp_priv = (struct intel_dp_priv *)(intel_encoder + 1);
a4fc5ed6 1549
b329530c
AJ		 1550 if (HAS_PCH_SPLIT(dev) && (output_reg == PCH_DP_D))
1551 if (intel_dpd_is_edp(dev))
1552 dp_priv->is_pch_edp = true;
1553
1554 if (output_reg == DP_A || IS_PCH_eDP(dp_priv)) {
1555 type = DRM_MODE_CONNECTOR_eDP;
1556 intel_encoder->type = INTEL_OUTPUT_EDP;
1557 } else {
1558 type = DRM_MODE_CONNECTOR_DisplayPort;
1559 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1560 }
1561
55f78c43 1562 connector = &intel_connector->base;
b329530c 1563 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 1564 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1565
eb1f8e4f
DA		 1566 connector->polled = DRM_CONNECTOR_POLL_HPD;
1567
652af9d7 1568 if (output_reg == DP_B || output_reg == PCH_DP_B)
21d40d37 1569 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
652af9d7 1570 else if (output_reg == DP_C || output_reg == PCH_DP_C)
21d40d37 1571 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
652af9d7 1572 else if (output_reg == DP_D || output_reg == PCH_DP_D)
21d40d37 1573 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
f8aed700 1574
21d40d37
EA		 1575 if (IS_eDP(intel_encoder))
1576 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
6251ec0a 1577
21d40d37 1578 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
a4fc5ed6
KP		 1579 connector->interlace_allowed = true;
1580 connector->doublescan_allowed = 0;
1581
21d40d37 1582 dp_priv->intel_encoder = intel_encoder;
a4fc5ed6
KP		 1583 dp_priv->output_reg = output_reg;
1584 dp_priv->has_audio = false;
c8110e52 1585 dp_priv->dpms_mode = DRM_MODE_DPMS_ON;
21d40d37 1586 intel_encoder->dev_priv = dp_priv;
a4fc5ed6 1587
21d40d37 1588 drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
a4fc5ed6 1589 DRM_MODE_ENCODER_TMDS);
21d40d37 1590 drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs);
a4fc5ed6 1591
55f78c43 1592 drm_mode_connector_attach_encoder(&intel_connector->base,
21d40d37 1593 &intel_encoder->enc);
a4fc5ed6
KP		 1594 drm_sysfs_connector_add(connector);
1595
1596 /* Set up the DDC bus. */
5eb08b69 1597 switch (output_reg) {
32f9d658
ZW		 1598 case DP_A:
1599 name = "DPDDC-A";
1600 break;
5eb08b69
ZW		 1601 case DP_B:
1602 case PCH_DP_B:
b01f2c3a
JB		 1603 dev_priv->hotplug_supported_mask |=
1604 HDMIB_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1605 name = "DPDDC-B";
1606 break;
1607 case DP_C:
1608 case PCH_DP_C:
b01f2c3a
JB		 1609 dev_priv->hotplug_supported_mask |=
1610 HDMIC_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1611 name = "DPDDC-C";
1612 break;
1613 case DP_D:
1614 case PCH_DP_D:
b01f2c3a
JB		 1615 dev_priv->hotplug_supported_mask |=
1616 HDMID_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 1617 name = "DPDDC-D";
1618 break;
1619 }
1620
55f78c43 1621 intel_dp_i2c_init(intel_encoder, intel_connector, name);
32f9d658 1622
21d40d37
EA		 1623 intel_encoder->ddc_bus = &dp_priv->adapter;
1624 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 1625
36e83a18 1626 if (output_reg == DP_A || IS_PCH_eDP(dp_priv)) {
32f9d658
ZW		 1627 /* initialize panel mode from VBT if available for eDP */
1628 if (dev_priv->lfp_lvds_vbt_mode) {
1629 dev_priv->panel_fixed_mode =
1630 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1631 if (dev_priv->panel_fixed_mode) {
1632 dev_priv->panel_fixed_mode->type |=
1633 DRM_MODE_TYPE_PREFERRED;
1634 }
1635 }
1636 }
1637
a4fc5ed6
KP		 1638 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1639 * 0xd. Failure to do so will result in spurious interrupts being
1640 * generated on the port when a cable is not attached.
1641 */
1642 if (IS_G4X(dev) && !IS_GM45(dev)) {
1643 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1644 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1645 }
1646}
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