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drm/i915: add DP 1.2 MST support (v0.7)
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
ef9348c8
CML		 67/*
68 * CHV supports eDP 1.4 that have more link rates.
69 * Below only provides the fixed rate but exclude variable rate.
70 */
71static const struct dp_link_dpll chv_dpll[] = {
72 /*
73 * CHV requires to program fractional division for m2.
74 * m2 is stored in fixed point format using formula below
75 * (m2_int << 22) | m2_fraction
76 */
77 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
78 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
79 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
80 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
81 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
83};
84
cfcb0fc9
JB		 85/**
86 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
87 * @intel_dp: DP struct
88 *
89 * If a CPU or PCH DP output is attached to an eDP panel, this function
90 * will return true, and false otherwise.
91 */
92static bool is_edp(struct intel_dp *intel_dp)
93{
da63a9f2
PZ		 94 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
95
96 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 97}
98
68b4d824 99static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 100{
68b4d824
ID		 101 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
102
103 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 104}
105
df0e9248
CW		 106static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
107{
fa90ecef 108 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 109}
110
ea5b213a 111static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 112static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 113static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 114
0e32b39c 115int
ea5b213a 116intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 117{
7183dc29 118 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 119 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 120
121 switch (max_link_bw) {
122 case DP_LINK_BW_1_62:
123 case DP_LINK_BW_2_7:
124 break;
d4eead50 125 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 126 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
127 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 128 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
129 max_link_bw = DP_LINK_BW_5_4;
130 else
131 max_link_bw = DP_LINK_BW_2_7;
d4eead50 132 break;
a4fc5ed6 133 default:
d4eead50
ID		 134 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
135 max_link_bw);
a4fc5ed6
KP		 136 max_link_bw = DP_LINK_BW_1_62;
137 break;
138 }
139 return max_link_bw;
140}
141
eeb6324d
PZ		 142static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
143{
144 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
145 struct drm_device *dev = intel_dig_port->base.base.dev;
146 u8 source_max, sink_max;
147
148 source_max = 4;
149 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
150 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
151 source_max = 2;
152
153 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
154
155 return min(source_max, sink_max);
156}
157
cd9dde44
AJ		 158/*
159 * The units on the numbers in the next two are... bizarre. Examples will
160 * make it clearer; this one parallels an example in the eDP spec.
161 *
162 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
163 *
164 * 270000 * 1 * 8 / 10 == 216000
165 *
166 * The actual data capacity of that configuration is 2.16Gbit/s, so the
167 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
168 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
169 * 119000. At 18bpp that's 2142000 kilobits per second.
170 *
171 * Thus the strange-looking division by 10 in intel_dp_link_required, to
172 * get the result in decakilobits instead of kilobits.
173 */
174
a4fc5ed6 175static int
c898261c 176intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 177{
cd9dde44 178 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 179}
180
fe27d53e
DA		 181static int
182intel_dp_max_data_rate(int max_link_clock, int max_lanes)
183{
184 return (max_link_clock * max_lanes * 8) / 10;
185}
186
c19de8eb 187static enum drm_mode_status
a4fc5ed6
KP		 188intel_dp_mode_valid(struct drm_connector *connector,
189 struct drm_display_mode *mode)
190{
df0e9248 191 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 192 struct intel_connector *intel_connector = to_intel_connector(connector);
193 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 194 int target_clock = mode->clock;
195 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 196
dd06f90e
JN		 197 if (is_edp(intel_dp) && fixed_mode) {
198 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 199 return MODE_PANEL;
200
dd06f90e 201 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 202 return MODE_PANEL;
03afc4a2
DV		 203
204 target_clock = fixed_mode->clock;
7de56f43
ZY		 205 }
206
36008365 207 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 208 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 209
210 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
211 mode_rate = intel_dp_link_required(target_clock, 18);
212
213 if (mode_rate > max_rate)
c4867936 214 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 215
216 if (mode->clock < 10000)
217 return MODE_CLOCK_LOW;
218
0af78a2b
DV		 219 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
220 return MODE_H_ILLEGAL;
221
a4fc5ed6
KP		 222 return MODE_OK;
223}
224
225static uint32_t
226pack_aux(uint8_t *src, int src_bytes)
227{
228 int i;
229 uint32_t v = 0;
230
231 if (src_bytes > 4)
232 src_bytes = 4;
233 for (i = 0; i < src_bytes; i++)
234 v |= ((uint32_t) src[i]) << ((3-i) * 8);
235 return v;
236}
237
238static void
239unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
240{
241 int i;
242 if (dst_bytes > 4)
243 dst_bytes = 4;
244 for (i = 0; i < dst_bytes; i++)
245 dst[i] = src >> ((3-i) * 8);
246}
247
fb0f8fbf
KP		 248/* hrawclock is 1/4 the FSB frequency */
249static int
250intel_hrawclk(struct drm_device *dev)
251{
252 struct drm_i915_private *dev_priv = dev->dev_private;
253 uint32_t clkcfg;
254
9473c8f4
VP		 255 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
256 if (IS_VALLEYVIEW(dev))
257 return 200;
258
fb0f8fbf
KP		 259 clkcfg = I915_READ(CLKCFG);
260 switch (clkcfg & CLKCFG_FSB_MASK) {
261 case CLKCFG_FSB_400:
262 return 100;
263 case CLKCFG_FSB_533:
264 return 133;
265 case CLKCFG_FSB_667:
266 return 166;
267 case CLKCFG_FSB_800:
268 return 200;
269 case CLKCFG_FSB_1067:
270 return 266;
271 case CLKCFG_FSB_1333:
272 return 333;
273 /* these two are just a guess; one of them might be right */
274 case CLKCFG_FSB_1600:
275 case CLKCFG_FSB_1600_ALT:
276 return 400;
277 default:
278 return 133;
279 }
280}
281
bf13e81b
JN		 282static void
283intel_dp_init_panel_power_sequencer(struct drm_device *dev,
284 struct intel_dp *intel_dp,
285 struct edp_power_seq *out);
286static void
287intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
288 struct intel_dp *intel_dp,
289 struct edp_power_seq *out);
290
291static enum pipe
292vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
293{
294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
295 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
296 struct drm_device *dev = intel_dig_port->base.base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum port port = intel_dig_port->port;
299 enum pipe pipe;
300
301 /* modeset should have pipe */
302 if (crtc)
303 return to_intel_crtc(crtc)->pipe;
304
305 /* init time, try to find a pipe with this port selected */
306 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
307 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
308 PANEL_PORT_SELECT_MASK;
309 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
310 return pipe;
311 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
312 return pipe;
313 }
314
315 /* shrug */
316 return PIPE_A;
317}
318
319static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
320{
321 struct drm_device *dev = intel_dp_to_dev(intel_dp);
322
323 if (HAS_PCH_SPLIT(dev))
324 return PCH_PP_CONTROL;
325 else
326 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
327}
328
329static u32 _pp_stat_reg(struct intel_dp *intel_dp)
330{
331 struct drm_device *dev = intel_dp_to_dev(intel_dp);
332
333 if (HAS_PCH_SPLIT(dev))
334 return PCH_PP_STATUS;
335 else
336 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
337}
338
4be73780 339static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 340{
30add22d 341 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 342 struct drm_i915_private *dev_priv = dev->dev_private;
343
bf13e81b 344 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 345}
346
4be73780 347static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 348{
30add22d 349 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 350 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 351 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
352 struct intel_encoder *intel_encoder = &intel_dig_port->base;
353 enum intel_display_power_domain power_domain;
ebf33b18 354
bb4932c4
ID		 355 power_domain = intel_display_port_power_domain(intel_encoder);
356 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 357 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 358}
359
9b984dae
KP		 360static void
361intel_dp_check_edp(struct intel_dp *intel_dp)
362{
30add22d 363 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 364 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 365
9b984dae
KP		 366 if (!is_edp(intel_dp))
367 return;
453c5420 368
4be73780 369 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 370 WARN(1, "eDP powered off while attempting aux channel communication.\n");
371 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 372 I915_READ(_pp_stat_reg(intel_dp)),
373 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 374 }
375}
376
9ee32fea
DV		 377static uint32_t
378intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
379{
380 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
381 struct drm_device *dev = intel_dig_port->base.base.dev;
382 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 383 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 384 uint32_t status;
385 bool done;
386
ef04f00d 387#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 388 if (has_aux_irq)
b18ac466 389 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 390 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 391 else
392 done = wait_for_atomic(C, 10) == 0;
393 if (!done)
394 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
395 has_aux_irq);
396#undef C
397
398 return status;
399}
400
ec5b01dd 401static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 402{
174edf1f
PZ		 403 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
404 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 405
ec5b01dd
DL		 406 /*
407 * The clock divider is based off the hrawclk, and would like to run at
408 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 409 */
ec5b01dd
DL		 410 return index ? 0 : intel_hrawclk(dev) / 2;
411}
412
413static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
414{
415 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
416 struct drm_device *dev = intel_dig_port->base.base.dev;
417
418 if (index)
419 return 0;
420
421 if (intel_dig_port->port == PORT_A) {
422 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 423 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 424 else
b84a1cf8 425 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 426 } else {
427 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
428 }
429}
430
431static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
432{
433 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
434 struct drm_device *dev = intel_dig_port->base.base.dev;
435 struct drm_i915_private *dev_priv = dev->dev_private;
436
437 if (intel_dig_port->port == PORT_A) {
438 if (index)
439 return 0;
440 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 441 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
442 /* Workaround for non-ULT HSW */
bc86625a
CW		 443 switch (index) {
444 case 0: return 63;
445 case 1: return 72;
446 default: return 0;
447 }
ec5b01dd 448 } else {
bc86625a 449 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 450 }
b84a1cf8
RV		 451}
452
ec5b01dd
DL		 453static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
454{
455 return index ? 0 : 100;
456}
457
5ed12a19
DL		 458static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
459 bool has_aux_irq,
460 int send_bytes,
461 uint32_t aux_clock_divider)
462{
463 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
464 struct drm_device *dev = intel_dig_port->base.base.dev;
465 uint32_t precharge, timeout;
466
467 if (IS_GEN6(dev))
468 precharge = 3;
469 else
470 precharge = 5;
471
472 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
473 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
474 else
475 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
476
477 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 478 DP_AUX_CH_CTL_DONE |
5ed12a19 479 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 480 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 481 timeout |
788d4433 482 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 483 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
484 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 485 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 486}
487
b84a1cf8
RV		 488static int
489intel_dp_aux_ch(struct intel_dp *intel_dp,
490 uint8_t *send, int send_bytes,
491 uint8_t *recv, int recv_size)
492{
493 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
494 struct drm_device *dev = intel_dig_port->base.base.dev;
495 struct drm_i915_private *dev_priv = dev->dev_private;
496 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
497 uint32_t ch_data = ch_ctl + 4;
bc86625a 498 uint32_t aux_clock_divider;
b84a1cf8
RV		 499 int i, ret, recv_bytes;
500 uint32_t status;
5ed12a19 501 int try, clock = 0;
4e6b788c 502 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 503 bool vdd;
504
505 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 506
507 /* dp aux is extremely sensitive to irq latency, hence request the
508 * lowest possible wakeup latency and so prevent the cpu from going into
509 * deep sleep states.
510 */
511 pm_qos_update_request(&dev_priv->pm_qos, 0);
512
513 intel_dp_check_edp(intel_dp);
5eb08b69 514
c67a470b
PZ		 515 intel_aux_display_runtime_get(dev_priv);
516
11bee43e
JB		 517 /* Try to wait for any previous AUX channel activity */
518 for (try = 0; try < 3; try++) {
ef04f00d 519 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 520 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
521 break;
522 msleep(1);
523 }
524
525 if (try == 3) {
526 WARN(1, "dp_aux_ch not started status 0x%08x\n",
527 I915_READ(ch_ctl));
9ee32fea
DV		 528 ret = -EBUSY;
529 goto out;
4f7f7b7e
CW		 530 }
531
46a5ae9f
PZ		 532 /* Only 5 data registers! */
533 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
534 ret = -E2BIG;
535 goto out;
536 }
537
ec5b01dd 538 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 539 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
540 has_aux_irq,
541 send_bytes,
542 aux_clock_divider);
5ed12a19 543
bc86625a
CW		 544 /* Must try at least 3 times according to DP spec */
545 for (try = 0; try < 5; try++) {
546 /* Load the send data into the aux channel data registers */
547 for (i = 0; i < send_bytes; i += 4)
548 I915_WRITE(ch_data + i,
549 pack_aux(send + i, send_bytes - i));
550
551 /* Send the command and wait for it to complete */
5ed12a19 552 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 553
554 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
555
556 /* Clear done status and any errors */
557 I915_WRITE(ch_ctl,
558 status |
559 DP_AUX_CH_CTL_DONE |
560 DP_AUX_CH_CTL_TIME_OUT_ERROR |
561 DP_AUX_CH_CTL_RECEIVE_ERROR);
562
563 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
564 DP_AUX_CH_CTL_RECEIVE_ERROR))
565 continue;
566 if (status & DP_AUX_CH_CTL_DONE)
567 break;
568 }
4f7f7b7e 569 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 570 break;
571 }
572
a4fc5ed6 573 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 574 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 575 ret = -EBUSY;
576 goto out;
a4fc5ed6
KP		 577 }
578
579 /* Check for timeout or receive error.
580 * Timeouts occur when the sink is not connected
581 */
a5b3da54 582 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 583 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 584 ret = -EIO;
585 goto out;
a5b3da54 586 }
1ae8c0a5
KP		 587
588 /* Timeouts occur when the device isn't connected, so they're
589 * "normal" -- don't fill the kernel log with these */
a5b3da54 590 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 591 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 592 ret = -ETIMEDOUT;
593 goto out;
a4fc5ed6
KP		 594 }
595
596 /* Unload any bytes sent back from the other side */
597 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
598 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 599 if (recv_bytes > recv_size)
600 recv_bytes = recv_size;
0206e353 601
4f7f7b7e
CW		 602 for (i = 0; i < recv_bytes; i += 4)
603 unpack_aux(I915_READ(ch_data + i),
604 recv + i, recv_bytes - i);
a4fc5ed6 605
9ee32fea
DV		 606 ret = recv_bytes;
607out:
608 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 609 intel_aux_display_runtime_put(dev_priv);
9ee32fea 610
884f19e9
JN		 611 if (vdd)
612 edp_panel_vdd_off(intel_dp, false);
613
9ee32fea 614 return ret;
a4fc5ed6
KP		 615}
616
a6c8aff0
JN		 617#define BARE_ADDRESS_SIZE 3
618#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 619static ssize_t
620intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 621{
9d1a1031
JN		 622 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
623 uint8_t txbuf[20], rxbuf[20];
624 size_t txsize, rxsize;
a4fc5ed6 625 int ret;
a4fc5ed6 626
9d1a1031
JN		 627 txbuf[0] = msg->request << 4;
628 txbuf[1] = msg->address >> 8;
629 txbuf[2] = msg->address & 0xff;
630 txbuf[3] = msg->size - 1;
46a5ae9f 631
9d1a1031
JN		 632 switch (msg->request & ~DP_AUX_I2C_MOT) {
633 case DP_AUX_NATIVE_WRITE:
634 case DP_AUX_I2C_WRITE:
a6c8aff0 635 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 636 rxsize = 1;
f51a44b9 637
9d1a1031
JN		 638 if (WARN_ON(txsize > 20))
639 return -E2BIG;
a4fc5ed6 640
9d1a1031 641 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 642
9d1a1031
JN		 643 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
644 if (ret > 0) {
645 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 646
9d1a1031
JN		 647 /* Return payload size. */
648 ret = msg->size;
649 }
650 break;
46a5ae9f 651
9d1a1031
JN		 652 case DP_AUX_NATIVE_READ:
653 case DP_AUX_I2C_READ:
a6c8aff0 654 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 655 rxsize = msg->size + 1;
a4fc5ed6 656
9d1a1031
JN		 657 if (WARN_ON(rxsize > 20))
658 return -E2BIG;
a4fc5ed6 659
9d1a1031
JN		 660 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
661 if (ret > 0) {
662 msg->reply = rxbuf[0] >> 4;
663 /*
664 * Assume happy day, and copy the data. The caller is
665 * expected to check msg->reply before touching it.
666 *
667 * Return payload size.
668 */
669 ret--;
670 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 671 }
9d1a1031
JN		 672 break;
673
674 default:
675 ret = -EINVAL;
676 break;
a4fc5ed6 677 }
f51a44b9 678
9d1a1031 679 return ret;
a4fc5ed6
KP		 680}
681
9d1a1031
JN		 682static void
683intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
684{
685 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 686 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
687 enum port port = intel_dig_port->port;
0b99836f 688 const char *name = NULL;
ab2c0672
DA		 689 int ret;
690
33ad6626
JN		 691 switch (port) {
692 case PORT_A:
693 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 694 name = "DPDDC-A";
ab2c0672 695 break;
33ad6626
JN		 696 case PORT_B:
697 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 698 name = "DPDDC-B";
ab2c0672 699 break;
33ad6626
JN		 700 case PORT_C:
701 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 702 name = "DPDDC-C";
ab2c0672 703 break;
33ad6626
JN		 704 case PORT_D:
705 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 706 name = "DPDDC-D";
33ad6626
JN		 707 break;
708 default:
709 BUG();
ab2c0672
DA		 710 }
711
33ad6626
JN		 712 if (!HAS_DDI(dev))
713 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 714
0b99836f 715 intel_dp->aux.name = name;
9d1a1031
JN		 716 intel_dp->aux.dev = dev->dev;
717 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 718
0b99836f
JN		 719 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
720 connector->base.kdev->kobj.name);
8316f337 721
4f71d0cb 722 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 723 if (ret < 0) {
4f71d0cb 724 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 725 name, ret);
726 return;
ab2c0672 727 }
8a5e6aeb 728
0b99836f
JN		 729 ret = sysfs_create_link(&connector->base.kdev->kobj,
730 &intel_dp->aux.ddc.dev.kobj,
731 intel_dp->aux.ddc.dev.kobj.name);
732 if (ret < 0) {
733 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 734 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 735 }
a4fc5ed6
KP		 736}
737
80f65de3
ID		 738static void
739intel_dp_connector_unregister(struct intel_connector *intel_connector)
740{
741 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
742
0e32b39c
DA		 743 if (!intel_connector->mst_port)
744 sysfs_remove_link(&intel_connector->base.kdev->kobj,
745 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 746 intel_connector_unregister(intel_connector);
747}
748
0e50338c
DV		 749static void
750hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
751{
752 switch (link_bw) {
753 case DP_LINK_BW_1_62:
754 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
755 break;
756 case DP_LINK_BW_2_7:
757 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
758 break;
759 case DP_LINK_BW_5_4:
760 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
761 break;
762 }
763}
764
c6bb3538
DV		 765static void
766intel_dp_set_clock(struct intel_encoder *encoder,
767 struct intel_crtc_config *pipe_config, int link_bw)
768{
769 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 770 const struct dp_link_dpll *divisor = NULL;
771 int i, count = 0;
c6bb3538
DV		 772
773 if (IS_G4X(dev)) {
9dd4ffdf
CML		 774 divisor = gen4_dpll;
775 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 776 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 777 divisor = pch_dpll;
778 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 779 } else if (IS_CHERRYVIEW(dev)) {
780 divisor = chv_dpll;
781 count = ARRAY_SIZE(chv_dpll);
c6bb3538 782 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 783 divisor = vlv_dpll;
784 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 785 }
9dd4ffdf
CML		 786
787 if (divisor && count) {
788 for (i = 0; i < count; i++) {
789 if (link_bw == divisor[i].link_bw) {
790 pipe_config->dpll = divisor[i].dpll;
791 pipe_config->clock_set = true;
792 break;
793 }
794 }
c6bb3538
DV		 795 }
796}
797
439d7ac0
PB		 798static void
799intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
800{
801 struct drm_device *dev = crtc->base.dev;
802 struct drm_i915_private *dev_priv = dev->dev_private;
803 enum transcoder transcoder = crtc->config.cpu_transcoder;
804
805 I915_WRITE(PIPE_DATA_M2(transcoder),
806 TU_SIZE(m_n->tu) | m_n->gmch_m);
807 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
808 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
809 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
810}
811
00c09d70 812bool
5bfe2ac0
DV		 813intel_dp_compute_config(struct intel_encoder *encoder,
814 struct intel_crtc_config *pipe_config)
a4fc5ed6 815{
5bfe2ac0 816 struct drm_device *dev = encoder->base.dev;
36008365 817 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 818 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 819 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 820 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 821 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 822 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 823 int lane_count, clock;
56071a20 824 int min_lane_count = 1;
eeb6324d 825 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 826 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 827 int min_clock = 0;
06ea66b6 828 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 829 int bpp, mode_rate;
06ea66b6 830 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 831 int link_avail, link_clock;
a4fc5ed6 832
bc7d38a4 833 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 834 pipe_config->has_pch_encoder = true;
835
03afc4a2 836 pipe_config->has_dp_encoder = true;
9ed109a7 837 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 838
dd06f90e
JN		 839 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
840 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
841 adjusted_mode);
2dd24552
JB		 842 if (!HAS_PCH_SPLIT(dev))
843 intel_gmch_panel_fitting(intel_crtc, pipe_config,
844 intel_connector->panel.fitting_mode);
845 else
b074cec8
JB		 846 intel_pch_panel_fitting(intel_crtc, pipe_config,
847 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 848 }
849
cb1793ce 850 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 851 return false;
852
083f9560
DV		 853 DRM_DEBUG_KMS("DP link computation with max lane count %i "
854 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 855 max_lane_count, bws[max_clock],
856 adjusted_mode->crtc_clock);
083f9560 857
36008365
DV		 858 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
859 * bpc in between. */
3e7ca985 860 bpp = pipe_config->pipe_bpp;
56071a20
JN		 861 if (is_edp(intel_dp)) {
862 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
863 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
864 dev_priv->vbt.edp_bpp);
865 bpp = dev_priv->vbt.edp_bpp;
866 }
867
f4cdbc21
JN		 868 if (IS_BROADWELL(dev)) {
869 /* Yes, it's an ugly hack. */
870 min_lane_count = max_lane_count;
871 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
872 min_lane_count);
873 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 874 min_lane_count = min(dev_priv->vbt.edp_lanes,
875 max_lane_count);
876 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
877 min_lane_count);
878 }
879
880 if (dev_priv->vbt.edp_rate) {
881 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
882 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
883 bws[min_clock]);
884 }
7984211e 885 }
657445fe 886
36008365 887 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 888 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
889 bpp);
36008365 890
56071a20
JN		 891 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
892 for (clock = min_clock; clock <= max_clock; clock++) {
36008365
DV		 893 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
894 link_avail = intel_dp_max_data_rate(link_clock,
895 lane_count);
896
897 if (mode_rate <= link_avail) {
898 goto found;
899 }
900 }
901 }
902 }
c4867936 903
36008365 904 return false;
3685a8f3 905
36008365 906found:
55bc60db
VS		 907 if (intel_dp->color_range_auto) {
908 /*
909 * See:
910 * CEA-861-E - 5.1 Default Encoding Parameters
911 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
912 */
18316c8c 913 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 914 intel_dp->color_range = DP_COLOR_RANGE_16_235;
915 else
916 intel_dp->color_range = 0;
917 }
918
3685a8f3 919 if (intel_dp->color_range)
50f3b016 920 pipe_config->limited_color_range = true;
a4fc5ed6 921
36008365
DV		 922 intel_dp->link_bw = bws[clock];
923 intel_dp->lane_count = lane_count;
657445fe 924 pipe_config->pipe_bpp = bpp;
ff9a6750 925 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 926
36008365
DV		 927 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
928 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 929 pipe_config->port_clock, bpp);
36008365
DV		 930 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
931 mode_rate, link_avail);
a4fc5ed6 932
03afc4a2 933 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 934 adjusted_mode->crtc_clock,
935 pipe_config->port_clock,
03afc4a2 936 &pipe_config->dp_m_n);
9d1a455b 937
439d7ac0
PB		 938 if (intel_connector->panel.downclock_mode != NULL &&
939 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
940 intel_link_compute_m_n(bpp, lane_count,
941 intel_connector->panel.downclock_mode->clock,
942 pipe_config->port_clock,
943 &pipe_config->dp_m2_n2);
944 }
945
0e50338c
DV		 946 if (HAS_DDI(dev))
947 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
948 else
949 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 950
03afc4a2 951 return true;
a4fc5ed6
KP		 952}
953
7c62a164 954static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 955{
7c62a164
DV		 956 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
957 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
958 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 959 struct drm_i915_private *dev_priv = dev->dev_private;
960 u32 dpa_ctl;
961
ff9a6750 962 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 963 dpa_ctl = I915_READ(DP_A);
964 dpa_ctl &= ~DP_PLL_FREQ_MASK;
965
ff9a6750 966 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 967 /* For a long time we've carried around a ILK-DevA w/a for the
968 * 160MHz clock. If we're really unlucky, it's still required.
969 */
970 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 971 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 972 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 973 } else {
974 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 975 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 976 }
1ce17038 977
ea9b6006
DV		 978 I915_WRITE(DP_A, dpa_ctl);
979
980 POSTING_READ(DP_A);
981 udelay(500);
982}
983
8ac33ed3 984static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 985{
b934223d 986 struct drm_device *dev = encoder->base.dev;
417e822d 987 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 988 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 989 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 990 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
991 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 992
417e822d 993 /*
1a2eb460 994 * There are four kinds of DP registers:
417e822d
KP		 995 *
996 * IBX PCH
1a2eb460
KP		 997 * SNB CPU
998 * IVB CPU
417e822d
KP		 999 * CPT PCH
1000 *
1001 * IBX PCH and CPU are the same for almost everything,
1002 * except that the CPU DP PLL is configured in this
1003 * register
1004 *
1005 * CPT PCH is quite different, having many bits moved
1006 * to the TRANS_DP_CTL register instead. That
1007 * configuration happens (oddly) in ironlake_pch_enable
1008 */
9c9e7927 1009
417e822d
KP		 1010 /* Preserve the BIOS-computed detected bit. This is
1011 * supposed to be read-only.
1012 */
1013 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1014
417e822d 1015 /* Handle DP bits in common between all three register formats */
417e822d 1016 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1017 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1018
9ed109a7 1019 if (crtc->config.has_audio) {
e0dac65e 1020 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1021 pipe_name(crtc->pipe));
ea5b213a 1022 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1023 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1024 }
247d89f6 1025
417e822d 1026 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1027
bc7d38a4 1028 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1029 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1030 intel_dp->DP |= DP_SYNC_HS_HIGH;
1031 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1032 intel_dp->DP |= DP_SYNC_VS_HIGH;
1033 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1034
6aba5b6c 1035 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1036 intel_dp->DP |= DP_ENHANCED_FRAMING;
1037
7c62a164 1038 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1039 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1040 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1041 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1042
1043 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1044 intel_dp->DP |= DP_SYNC_HS_HIGH;
1045 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1046 intel_dp->DP |= DP_SYNC_VS_HIGH;
1047 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1048
6aba5b6c 1049 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1050 intel_dp->DP |= DP_ENHANCED_FRAMING;
1051
44f37d1f
CML		 1052 if (!IS_CHERRYVIEW(dev)) {
1053 if (crtc->pipe == 1)
1054 intel_dp->DP |= DP_PIPEB_SELECT;
1055 } else {
1056 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1057 }
417e822d
KP		 1058 } else {
1059 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1060 }
a4fc5ed6
KP		 1061}
1062
ffd6749d
PZ		 1063#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1064#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1065
1a5ef5b7
PZ		 1066#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1067#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1068
ffd6749d
PZ		 1069#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1070#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1071
4be73780 1072static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1073 u32 mask,
1074 u32 value)
bd943159 1075{
30add22d 1076 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1077 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1078 u32 pp_stat_reg, pp_ctrl_reg;
1079
bf13e81b
JN		 1080 pp_stat_reg = _pp_stat_reg(intel_dp);
1081 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1082
99ea7127 1083 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1084 mask, value,
1085 I915_READ(pp_stat_reg),
1086 I915_READ(pp_ctrl_reg));
32ce697c 1087
453c5420 1088 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1089 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1090 I915_READ(pp_stat_reg),
1091 I915_READ(pp_ctrl_reg));
32ce697c 1092 }
54c136d4
CW		 1093
1094 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1095}
32ce697c 1096
4be73780 1097static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1098{
1099 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1100 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1101}
1102
4be73780 1103static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1104{
1105 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1106 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1107}
1108
4be73780 1109static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1110{
1111 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1112
1113 /* When we disable the VDD override bit last we have to do the manual
1114 * wait. */
1115 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1116 intel_dp->panel_power_cycle_delay);
1117
4be73780 1118 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1119}
1120
4be73780 1121static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1122{
1123 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1124 intel_dp->backlight_on_delay);
1125}
1126
4be73780 1127static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1128{
1129 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1130 intel_dp->backlight_off_delay);
1131}
99ea7127 1132
832dd3c1
KP		 1133/* Read the current pp_control value, unlocking the register if it
1134 * is locked
1135 */
1136
453c5420 1137static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1138{
453c5420
JB		 1139 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1140 struct drm_i915_private *dev_priv = dev->dev_private;
1141 u32 control;
832dd3c1 1142
bf13e81b 1143 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1144 control &= ~PANEL_UNLOCK_MASK;
1145 control |= PANEL_UNLOCK_REGS;
1146 return control;
bd943159
KP		 1147}
1148
adddaaf4 1149static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1150{
30add22d 1151 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1152 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1153 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1154 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1155 enum intel_display_power_domain power_domain;
5d613501 1156 u32 pp;
453c5420 1157 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1158 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1159
97af61f5 1160 if (!is_edp(intel_dp))
adddaaf4 1161 return false;
bd943159
KP		 1162
1163 intel_dp->want_panel_vdd = true;
99ea7127 1164
4be73780 1165 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1166 return need_to_disable;
b0665d57 1167
4e6e1a54
ID		 1168 power_domain = intel_display_port_power_domain(intel_encoder);
1169 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1170
b0665d57 1171 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1172
4be73780
DV		 1173 if (!edp_have_panel_power(intel_dp))
1174 wait_panel_power_cycle(intel_dp);
99ea7127 1175
453c5420 1176 pp = ironlake_get_pp_control(intel_dp);
5d613501 1177 pp |= EDP_FORCE_VDD;
ebf33b18 1178
bf13e81b
JN		 1179 pp_stat_reg = _pp_stat_reg(intel_dp);
1180 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1181
1182 I915_WRITE(pp_ctrl_reg, pp);
1183 POSTING_READ(pp_ctrl_reg);
1184 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1185 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1186 /*
1187 * If the panel wasn't on, delay before accessing aux channel
1188 */
4be73780 1189 if (!edp_have_panel_power(intel_dp)) {
bd943159 1190 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1191 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1192 }
adddaaf4
JN		 1193
1194 return need_to_disable;
1195}
1196
b80d6c78 1197void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1198{
1199 if (is_edp(intel_dp)) {
1200 bool vdd = _edp_panel_vdd_on(intel_dp);
1201
1202 WARN(!vdd, "eDP VDD already requested on\n");
1203 }
5d613501
JB		 1204}
1205
4be73780 1206static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1207{
30add22d 1208 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1209 struct drm_i915_private *dev_priv = dev->dev_private;
1210 u32 pp;
453c5420 1211 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1212
51fd371b 1213 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
a0e99e68 1214
4be73780 1215 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
4e6e1a54
ID		 1216 struct intel_digital_port *intel_dig_port =
1217 dp_to_dig_port(intel_dp);
1218 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1219 enum intel_display_power_domain power_domain;
1220
b0665d57
PZ		 1221 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1222
453c5420 1223 pp = ironlake_get_pp_control(intel_dp);
bd943159 1224 pp &= ~EDP_FORCE_VDD;
bd943159 1225
9f08ef59
PZ		 1226 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1227 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1228
1229 I915_WRITE(pp_ctrl_reg, pp);
1230 POSTING_READ(pp_ctrl_reg);
99ea7127 1231
453c5420
JB		 1232 /* Make sure sequencer is idle before allowing subsequent activity */
1233 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1234 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1235
1236 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1237 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1238
4e6e1a54
ID		 1239 power_domain = intel_display_port_power_domain(intel_encoder);
1240 intel_display_power_put(dev_priv, power_domain);
bd943159
KP		 1241 }
1242}
5d613501 1243
4be73780 1244static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1245{
1246 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1247 struct intel_dp, panel_vdd_work);
30add22d 1248 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1249
51fd371b 1250 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 1251 edp_panel_vdd_off_sync(intel_dp);
51fd371b 1252 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159
KP		 1253}
1254
4be73780 1255static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1256{
97af61f5
KP		 1257 if (!is_edp(intel_dp))
1258 return;
5d613501 1259
bd943159 1260 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1261
bd943159
KP		 1262 intel_dp->want_panel_vdd = false;
1263
1264 if (sync) {
4be73780 1265 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1266 } else {
1267 /*
1268 * Queue the timer to fire a long
1269 * time from now (relative to the power down delay)
1270 * to keep the panel power up across a sequence of operations
1271 */
1272 schedule_delayed_work(&intel_dp->panel_vdd_work,
1273 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1274 }
5d613501
JB		 1275}
1276
4be73780 1277void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1278{
30add22d 1279 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1280 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1281 u32 pp;
453c5420 1282 u32 pp_ctrl_reg;
9934c132 1283
97af61f5 1284 if (!is_edp(intel_dp))
bd943159 1285 return;
99ea7127
KP		 1286
1287 DRM_DEBUG_KMS("Turn eDP power on\n");
1288
4be73780 1289 if (edp_have_panel_power(intel_dp)) {
99ea7127 1290 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1291 return;
99ea7127 1292 }
9934c132 1293
4be73780 1294 wait_panel_power_cycle(intel_dp);
37c6c9b0 1295
bf13e81b 1296 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1297 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1298 if (IS_GEN5(dev)) {
1299 /* ILK workaround: disable reset around power sequence */
1300 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1301 I915_WRITE(pp_ctrl_reg, pp);
1302 POSTING_READ(pp_ctrl_reg);
05ce1a49 1303 }
37c6c9b0 1304
1c0ae80a 1305 pp |= POWER_TARGET_ON;
99ea7127
KP		 1306 if (!IS_GEN5(dev))
1307 pp |= PANEL_POWER_RESET;
1308
453c5420
JB		 1309 I915_WRITE(pp_ctrl_reg, pp);
1310 POSTING_READ(pp_ctrl_reg);
9934c132 1311
4be73780 1312 wait_panel_on(intel_dp);
dce56b3c 1313 intel_dp->last_power_on = jiffies;
9934c132 1314
05ce1a49
KP		 1315 if (IS_GEN5(dev)) {
1316 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1317 I915_WRITE(pp_ctrl_reg, pp);
1318 POSTING_READ(pp_ctrl_reg);
05ce1a49 1319 }
9934c132
JB		 1320}
1321
4be73780 1322void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1323{
4e6e1a54
ID		 1324 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1325 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1326 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1327 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1328 enum intel_display_power_domain power_domain;
99ea7127 1329 u32 pp;
453c5420 1330 u32 pp_ctrl_reg;
9934c132 1331
97af61f5
KP		 1332 if (!is_edp(intel_dp))
1333 return;
37c6c9b0 1334
99ea7127 1335 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1336
24f3e092
JN		 1337 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1338
453c5420 1339 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1340 /* We need to switch off panel power _and_ force vdd, for otherwise some
1341 * panels get very unhappy and cease to work. */
b3064154
PJ		 1342 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1343 EDP_BLC_ENABLE);
453c5420 1344
bf13e81b 1345 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1346
849e39f5
PZ		 1347 intel_dp->want_panel_vdd = false;
1348
453c5420
JB		 1349 I915_WRITE(pp_ctrl_reg, pp);
1350 POSTING_READ(pp_ctrl_reg);
9934c132 1351
dce56b3c 1352 intel_dp->last_power_cycle = jiffies;
4be73780 1353 wait_panel_off(intel_dp);
849e39f5
PZ		 1354
1355 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1356 power_domain = intel_display_port_power_domain(intel_encoder);
1357 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1358}
1359
4be73780 1360void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1361{
da63a9f2
PZ		 1362 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1363 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1364 struct drm_i915_private *dev_priv = dev->dev_private;
1365 u32 pp;
453c5420 1366 u32 pp_ctrl_reg;
32f9d658 1367
f01eca2e
KP		 1368 if (!is_edp(intel_dp))
1369 return;
1370
28c97730 1371 DRM_DEBUG_KMS("\n");
f7d2323c
JB		 1372
1373 intel_panel_enable_backlight(intel_dp->attached_connector);
1374
01cb9ea6
JB		 1375 /*
1376 * If we enable the backlight right away following a panel power
1377 * on, we may see slight flicker as the panel syncs with the eDP
1378 * link. So delay a bit to make sure the image is solid before
1379 * allowing it to appear.
1380 */
4be73780 1381 wait_backlight_on(intel_dp);
453c5420 1382 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1383 pp |= EDP_BLC_ENABLE;
453c5420 1384
bf13e81b 1385 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1386
1387 I915_WRITE(pp_ctrl_reg, pp);
1388 POSTING_READ(pp_ctrl_reg);
32f9d658
ZW		 1389}
1390
4be73780 1391void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1392{
30add22d 1393 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1394 struct drm_i915_private *dev_priv = dev->dev_private;
1395 u32 pp;
453c5420 1396 u32 pp_ctrl_reg;
32f9d658 1397
f01eca2e
KP		 1398 if (!is_edp(intel_dp))
1399 return;
1400
28c97730 1401 DRM_DEBUG_KMS("\n");
453c5420 1402 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1403 pp &= ~EDP_BLC_ENABLE;
453c5420 1404
bf13e81b 1405 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1406
1407 I915_WRITE(pp_ctrl_reg, pp);
1408 POSTING_READ(pp_ctrl_reg);
dce56b3c 1409 intel_dp->last_backlight_off = jiffies;
f7d2323c
JB		 1410
1411 edp_wait_backlight_off(intel_dp);
1412
1413 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1414}
a4fc5ed6 1415
2bd2ad64 1416static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1417{
da63a9f2
PZ		 1418 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1419 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1420 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1421 struct drm_i915_private *dev_priv = dev->dev_private;
1422 u32 dpa_ctl;
1423
2bd2ad64
DV		 1424 assert_pipe_disabled(dev_priv,
1425 to_intel_crtc(crtc)->pipe);
1426
d240f20f
JB		 1427 DRM_DEBUG_KMS("\n");
1428 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1429 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1430 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1431
1432 /* We don't adjust intel_dp->DP while tearing down the link, to
1433 * facilitate link retraining (e.g. after hotplug). Hence clear all
1434 * enable bits here to ensure that we don't enable too much. */
1435 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1436 intel_dp->DP |= DP_PLL_ENABLE;
1437 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1438 POSTING_READ(DP_A);
1439 udelay(200);
d240f20f
JB		 1440}
1441
2bd2ad64 1442static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1443{
da63a9f2
PZ		 1444 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1445 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1446 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1447 struct drm_i915_private *dev_priv = dev->dev_private;
1448 u32 dpa_ctl;
1449
2bd2ad64
DV		 1450 assert_pipe_disabled(dev_priv,
1451 to_intel_crtc(crtc)->pipe);
1452
d240f20f 1453 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1454 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1455 "dp pll off, should be on\n");
1456 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1457
1458 /* We can't rely on the value tracked for the DP register in
1459 * intel_dp->DP because link_down must not change that (otherwise link
1460 * re-training will fail. */
298b0b39 1461 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1462 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1463 POSTING_READ(DP_A);
d240f20f
JB		 1464 udelay(200);
1465}
1466
c7ad3810 1467/* If the sink supports it, try to set the power state appropriately */
c19b0669 1468void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1469{
1470 int ret, i;
1471
1472 /* Should have a valid DPCD by this point */
1473 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1474 return;
1475
1476 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1477 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1478 DP_SET_POWER_D3);
c7ad3810
JB		 1479 if (ret != 1)
1480 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1481 } else {
1482 /*
1483 * When turning on, we need to retry for 1ms to give the sink
1484 * time to wake up.
1485 */
1486 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1487 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1488 DP_SET_POWER_D0);
c7ad3810
JB		 1489 if (ret == 1)
1490 break;
1491 msleep(1);
1492 }
1493 }
1494}
1495
19d8fe15
DV		 1496static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1497 enum pipe *pipe)
d240f20f 1498{
19d8fe15 1499 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1500 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1501 struct drm_device *dev = encoder->base.dev;
1502 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1503 enum intel_display_power_domain power_domain;
1504 u32 tmp;
1505
1506 power_domain = intel_display_port_power_domain(encoder);
1507 if (!intel_display_power_enabled(dev_priv, power_domain))
1508 return false;
1509
1510 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1511
1512 if (!(tmp & DP_PORT_EN))
1513 return false;
1514
bc7d38a4 1515 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1516 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1517 } else if (IS_CHERRYVIEW(dev)) {
1518 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1519 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1520 *pipe = PORT_TO_PIPE(tmp);
1521 } else {
1522 u32 trans_sel;
1523 u32 trans_dp;
1524 int i;
1525
1526 switch (intel_dp->output_reg) {
1527 case PCH_DP_B:
1528 trans_sel = TRANS_DP_PORT_SEL_B;
1529 break;
1530 case PCH_DP_C:
1531 trans_sel = TRANS_DP_PORT_SEL_C;
1532 break;
1533 case PCH_DP_D:
1534 trans_sel = TRANS_DP_PORT_SEL_D;
1535 break;
1536 default:
1537 return true;
1538 }
1539
1540 for_each_pipe(i) {
1541 trans_dp = I915_READ(TRANS_DP_CTL(i));
1542 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1543 *pipe = i;
1544 return true;
1545 }
1546 }
19d8fe15 1547
4a0833ec
DV		 1548 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1549 intel_dp->output_reg);
1550 }
d240f20f 1551
19d8fe15
DV		 1552 return true;
1553}
d240f20f 1554
045ac3b5
JB		 1555static void intel_dp_get_config(struct intel_encoder *encoder,
1556 struct intel_crtc_config *pipe_config)
1557{
1558 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1559 u32 tmp, flags = 0;
63000ef6
XZ		 1560 struct drm_device *dev = encoder->base.dev;
1561 struct drm_i915_private *dev_priv = dev->dev_private;
1562 enum port port = dp_to_dig_port(intel_dp)->port;
1563 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1564 int dotclock;
045ac3b5 1565
9ed109a7
DV		 1566 tmp = I915_READ(intel_dp->output_reg);
1567 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1568 pipe_config->has_audio = true;
1569
63000ef6 1570 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1571 if (tmp & DP_SYNC_HS_HIGH)
1572 flags |= DRM_MODE_FLAG_PHSYNC;
1573 else
1574 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1575
63000ef6
XZ		 1576 if (tmp & DP_SYNC_VS_HIGH)
1577 flags |= DRM_MODE_FLAG_PVSYNC;
1578 else
1579 flags |= DRM_MODE_FLAG_NVSYNC;
1580 } else {
1581 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1582 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1583 flags |= DRM_MODE_FLAG_PHSYNC;
1584 else
1585 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1586
63000ef6
XZ		 1587 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1588 flags |= DRM_MODE_FLAG_PVSYNC;
1589 else
1590 flags |= DRM_MODE_FLAG_NVSYNC;
1591 }
045ac3b5
JB		 1592
1593 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1594
eb14cb74
VS		 1595 pipe_config->has_dp_encoder = true;
1596
1597 intel_dp_get_m_n(crtc, pipe_config);
1598
18442d08 1599 if (port == PORT_A) {
f1f644dc
JB		 1600 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1601 pipe_config->port_clock = 162000;
1602 else
1603 pipe_config->port_clock = 270000;
1604 }
18442d08
VS		 1605
1606 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1607 &pipe_config->dp_m_n);
1608
1609 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1610 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1611
241bfc38 1612 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1613
c6cd2ee2
JN		 1614 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1615 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1616 /*
1617 * This is a big fat ugly hack.
1618 *
1619 * Some machines in UEFI boot mode provide us a VBT that has 18
1620 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1621 * unknown we fail to light up. Yet the same BIOS boots up with
1622 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1623 * max, not what it tells us to use.
1624 *
1625 * Note: This will still be broken if the eDP panel is not lit
1626 * up by the BIOS, and thus we can't get the mode at module
1627 * load.
1628 */
1629 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1630 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1631 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1632 }
045ac3b5
JB		 1633}
1634
34eb7579 1635static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1636{
34eb7579 1637 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1638}
1639
2b28bb1b
RV		 1640static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1641{
1642 struct drm_i915_private *dev_priv = dev->dev_private;
1643
18b5992c 1644 if (!HAS_PSR(dev))
2b28bb1b
RV		 1645 return false;
1646
18b5992c 1647 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1648}
1649
1650static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1651 struct edp_vsc_psr *vsc_psr)
1652{
1653 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1654 struct drm_device *dev = dig_port->base.base.dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1657 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1658 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1659 uint32_t *data = (uint32_t *) vsc_psr;
1660 unsigned int i;
1661
1662 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1663 the video DIP being updated before program video DIP data buffer
1664 registers for DIP being updated. */
1665 I915_WRITE(ctl_reg, 0);
1666 POSTING_READ(ctl_reg);
1667
1668 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1669 if (i < sizeof(struct edp_vsc_psr))
1670 I915_WRITE(data_reg + i, *data++);
1671 else
1672 I915_WRITE(data_reg + i, 0);
1673 }
1674
1675 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1676 POSTING_READ(ctl_reg);
1677}
1678
1679static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1680{
1681 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1682 struct drm_i915_private *dev_priv = dev->dev_private;
1683 struct edp_vsc_psr psr_vsc;
1684
6118efe5 1685 if (dev_priv->psr.setup_done)
2b28bb1b
RV		 1686 return;
1687
1688 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1689 memset(&psr_vsc, 0, sizeof(psr_vsc));
1690 psr_vsc.sdp_header.HB0 = 0;
1691 psr_vsc.sdp_header.HB1 = 0x7;
1692 psr_vsc.sdp_header.HB2 = 0x2;
1693 psr_vsc.sdp_header.HB3 = 0x8;
1694 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1695
1696 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1697 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1698 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b 1699
6118efe5 1700 dev_priv->psr.setup_done = true;
2b28bb1b
RV		 1701}
1702
1703static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1704{
0e0ae652
RV		 1705 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1706 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 1707 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1708 uint32_t aux_clock_divider;
2b28bb1b
RV		 1709 int precharge = 0x3;
1710 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 1711 bool only_standby = false;
2b28bb1b 1712
ec5b01dd
DL		 1713 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1714
0e0ae652
RV		 1715 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1716 only_standby = true;
1717
2b28bb1b 1718 /* Enable PSR in sink */
0e0ae652 1719 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 1720 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1721 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1722 else
9d1a1031
JN		 1723 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1724 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1725
1726 /* Setup AUX registers */
18b5992c
BW		 1727 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1728 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1729 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1730 DP_AUX_CH_CTL_TIME_OUT_400us |
1731 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1732 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1733 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1734}
1735
1736static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1737{
0e0ae652
RV		 1738 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1739 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 1740 struct drm_i915_private *dev_priv = dev->dev_private;
1741 uint32_t max_sleep_time = 0x1f;
1742 uint32_t idle_frames = 1;
1743 uint32_t val = 0x0;
ed8546ac 1744 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 1745 bool only_standby = false;
1746
1747 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1748 only_standby = true;
2b28bb1b 1749
0e0ae652 1750 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 1751 val |= EDP_PSR_LINK_STANDBY;
1752 val |= EDP_PSR_TP2_TP3_TIME_0us;
1753 val |= EDP_PSR_TP1_TIME_0us;
1754 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 1755 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 1756 } else
1757 val |= EDP_PSR_LINK_DISABLE;
1758
18b5992c 1759 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1760 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1761 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1762 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1763 EDP_PSR_ENABLE);
1764}
1765
3f51e471
RV		 1766static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1767{
1768 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1769 struct drm_device *dev = dig_port->base.base.dev;
1770 struct drm_i915_private *dev_priv = dev->dev_private;
b1972961
DA		 1771 struct drm_crtc *crtc;
1772 struct intel_crtc *intel_crtc;
1773 struct drm_i915_gem_object *obj;
3f51e471
RV		 1774 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1775
a031d709
RV		 1776 dev_priv->psr.source_ok = false;
1777
18b5992c 1778 if (!HAS_PSR(dev)) {
3f51e471 1779 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1780 return false;
1781 }
1782
0e0ae652
RV		 1783 if (IS_HASWELL(dev) && (intel_encoder->type != INTEL_OUTPUT_EDP ||
1784 dig_port->port != PORT_A)) {
3f51e471 1785 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1786 return false;
1787 }
1788
d330a953 1789 if (!i915.enable_psr) {
105b7c11 1790 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1791 return false;
1792 }
1793
cd234b0b
CW		 1794 crtc = dig_port->base.base.crtc;
1795 if (crtc == NULL) {
1796 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1797 return false;
1798 }
1799
1800 intel_crtc = to_intel_crtc(crtc);
20ddf665 1801 if (!intel_crtc_active(crtc)) {
3f51e471 1802 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1803 return false;
1804 }
1805
b1972961 1806 obj = intel_fb_obj(crtc->primary->fb);
3f51e471
RV		 1807 if (obj->tiling_mode != I915_TILING_X ||
1808 obj->fence_reg == I915_FENCE_REG_NONE) {
1809 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1810 return false;
1811 }
1812
4c8c7000
RV		 1813 /* Below limitations aren't valid for Broadwell */
1814 if (IS_BROADWELL(dev))
1815 goto out;
1816
3f51e471
RV		 1817 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1818 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1819 return false;
1820 }
1821
1822 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1823 S3D_ENABLE) {
1824 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1825 return false;
1826 }
1827
ca73b4f0 1828 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1829 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1830 return false;
1831 }
1832
4c8c7000 1833 out:
a031d709 1834 dev_priv->psr.source_ok = true;
3f51e471
RV		 1835 return true;
1836}
1837
3d739d92 1838static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 1839{
7c8f8a70
RV		 1840 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1841 struct drm_device *dev = intel_dig_port->base.base.dev;
1842 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 1843
7c8f8a70 1844 if (intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1845 return;
1846
2b28bb1b
RV		 1847 /* Enable PSR on the panel */
1848 intel_edp_psr_enable_sink(intel_dp);
1849
1850 /* Enable PSR on the host */
1851 intel_edp_psr_enable_source(intel_dp);
7c8f8a70
RV		 1852
1853 dev_priv->psr.enabled = true;
1854 dev_priv->psr.active = true;
2b28bb1b
RV		 1855}
1856
3d739d92
RV		 1857void intel_edp_psr_enable(struct intel_dp *intel_dp)
1858{
1859 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1860
4704c573
RV		 1861 if (!HAS_PSR(dev)) {
1862 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1863 return;
1864 }
1865
34eb7579
RV		 1866 if (!is_edp_psr(intel_dp)) {
1867 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1868 return;
1869 }
1870
16487254
RV		 1871 /* Setup PSR once */
1872 intel_edp_psr_setup(intel_dp);
1873
7c8f8a70 1874 if (intel_edp_psr_match_conditions(intel_dp))
3d739d92
RV		 1875 intel_edp_psr_do_enable(intel_dp);
1876}
1877
2b28bb1b
RV		 1878void intel_edp_psr_disable(struct intel_dp *intel_dp)
1879{
1880 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1881 struct drm_i915_private *dev_priv = dev->dev_private;
1882
7c8f8a70 1883 if (!dev_priv->psr.enabled)
2b28bb1b
RV		 1884 return;
1885
18b5992c
BW		 1886 I915_WRITE(EDP_PSR_CTL(dev),
1887 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1888
1889 /* Wait till PSR is idle */
18b5992c 1890 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1891 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1892 DRM_ERROR("Timed out waiting for PSR Idle State\n");
7c8f8a70
RV		 1893
1894 dev_priv->psr.enabled = false;
2b28bb1b
RV		 1895}
1896
f02a326e 1897static void intel_edp_psr_work(struct work_struct *work)
3d739d92 1898{
7c8f8a70
RV		 1899 struct drm_i915_private *dev_priv =
1900 container_of(work, typeof(*dev_priv), psr.work.work);
1901 struct drm_device *dev = dev_priv->dev;
3d739d92
RV		 1902 struct intel_encoder *encoder;
1903 struct intel_dp *intel_dp = NULL;
1904
1905 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1906 if (encoder->type == INTEL_OUTPUT_EDP) {
1907 intel_dp = enc_to_intel_dp(&encoder->base);
1908
3d739d92
RV		 1909 if (!intel_edp_psr_match_conditions(intel_dp))
1910 intel_edp_psr_disable(intel_dp);
1911 else
7c8f8a70 1912 intel_edp_psr_do_enable(intel_dp);
3d739d92
RV		 1913 }
1914}
1915
f02a326e 1916static void intel_edp_psr_inactivate(struct drm_device *dev)
7c8f8a70
RV		 1917{
1918 struct drm_i915_private *dev_priv = dev->dev_private;
7c8f8a70 1919
77c70c56 1920 dev_priv->psr.active = false;
7c8f8a70 1921
77c70c56
DV		 1922 I915_WRITE(EDP_PSR_CTL(dev), I915_READ(EDP_PSR_CTL(dev))
1923 & ~EDP_PSR_ENABLE);
7c8f8a70
RV		 1924}
1925
3108e99e 1926void intel_edp_psr_exit(struct drm_device *dev)
7c8f8a70
RV		 1927{
1928 struct drm_i915_private *dev_priv = dev->dev_private;
1929
1930 if (!HAS_PSR(dev))
1931 return;
1932
1933 if (!dev_priv->psr.setup_done)
1934 return;
1935
1936 cancel_delayed_work_sync(&dev_priv->psr.work);
1937
1938 if (dev_priv->psr.active)
1939 intel_edp_psr_inactivate(dev);
1940
3108e99e
DV		 1941 schedule_delayed_work(&dev_priv->psr.work,
1942 msecs_to_jiffies(100));
7c8f8a70
RV		 1943}
1944
1945void intel_edp_psr_init(struct drm_device *dev)
1946{
1947 struct drm_i915_private *dev_priv = dev->dev_private;
1948
1949 if (!HAS_PSR(dev))
1950 return;
1951
1952 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
1953}
1954
e8cb4558 1955static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1956{
e8cb4558 1957 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1958 enum port port = dp_to_dig_port(intel_dp)->port;
1959 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1960
1961 /* Make sure the panel is off before trying to change the mode. But also
1962 * ensure that we have vdd while we switch off the panel. */
24f3e092 1963 intel_edp_panel_vdd_on(intel_dp);
4be73780 1964 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1965 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1966 intel_edp_panel_off(intel_dp);
3739850b
DV		 1967
1968 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1969 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1970 intel_dp_link_down(intel_dp);
d240f20f
JB		 1971}
1972
49277c31 1973static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1974{
2bd2ad64 1975 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1976 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 1977
49277c31
VS		 1978 if (port != PORT_A)
1979 return;
1980
1981 intel_dp_link_down(intel_dp);
1982 ironlake_edp_pll_off(intel_dp);
1983}
1984
1985static void vlv_post_disable_dp(struct intel_encoder *encoder)
1986{
1987 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1988
1989 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 1990}
1991
580d3811
VS		 1992static void chv_post_disable_dp(struct intel_encoder *encoder)
1993{
1994 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1995 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1996 struct drm_device *dev = encoder->base.dev;
1997 struct drm_i915_private *dev_priv = dev->dev_private;
1998 struct intel_crtc *intel_crtc =
1999 to_intel_crtc(encoder->base.crtc);
2000 enum dpio_channel ch = vlv_dport_to_channel(dport);
2001 enum pipe pipe = intel_crtc->pipe;
2002 u32 val;
2003
2004 intel_dp_link_down(intel_dp);
2005
2006 mutex_lock(&dev_priv->dpio_lock);
2007
2008 /* Propagate soft reset to data lane reset */
97fd4d5c 2009 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2010 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2011 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2012
97fd4d5c
VS		 2013 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2014 val |= CHV_PCS_REQ_SOFTRESET_EN;
2015 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2016
2017 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2018 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2019 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2020
2021 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2022 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2023 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2024
2025 mutex_unlock(&dev_priv->dpio_lock);
2026}
2027
e8cb4558 2028static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2029{
e8cb4558
DV		 2030 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2031 struct drm_device *dev = encoder->base.dev;
2032 struct drm_i915_private *dev_priv = dev->dev_private;
2033 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2034
0c33d8d7
DV		 2035 if (WARN_ON(dp_reg & DP_PORT_EN))
2036 return;
5d613501 2037
24f3e092 2038 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 2039 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2040 intel_dp_start_link_train(intel_dp);
4be73780
DV		 2041 intel_edp_panel_on(intel_dp);
2042 edp_panel_vdd_off(intel_dp, true);
33a34e4e 2043 intel_dp_complete_link_train(intel_dp);
3ab9c637 2044 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2045}
89b667f8 2046
ecff4f3b
JN		 2047static void g4x_enable_dp(struct intel_encoder *encoder)
2048{
828f5c6e
JN		 2049 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2050
ecff4f3b 2051 intel_enable_dp(encoder);
4be73780 2052 intel_edp_backlight_on(intel_dp);
ab1f90f9 2053}
89b667f8 2054
ab1f90f9
JN		 2055static void vlv_enable_dp(struct intel_encoder *encoder)
2056{
828f5c6e
JN		 2057 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2058
4be73780 2059 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2060}
2061
ecff4f3b 2062static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2063{
2064 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2065 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2066
8ac33ed3
DV		 2067 intel_dp_prepare(encoder);
2068
d41f1efb
DV		 2069 /* Only ilk+ has port A */
2070 if (dport->port == PORT_A) {
2071 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2072 ironlake_edp_pll_on(intel_dp);
d41f1efb 2073 }
ab1f90f9
JN		 2074}
2075
2076static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2077{
2bd2ad64 2078 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2079 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2080 struct drm_device *dev = encoder->base.dev;
89b667f8 2081 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2082 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2083 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 2084 int pipe = intel_crtc->pipe;
bf13e81b 2085 struct edp_power_seq power_seq;
ab1f90f9 2086 u32 val;
a4fc5ed6 2087
ab1f90f9 2088 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2089
ab3c759a 2090 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2091 val = 0;
2092 if (pipe)
2093 val |= (1<<21);
2094 else
2095 val &= ~(1<<21);
2096 val |= 0x001000c4;
ab3c759a
CML		 2097 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2098 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2099 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2100
ab1f90f9
JN		 2101 mutex_unlock(&dev_priv->dpio_lock);
2102
2cac613b
ID		 2103 if (is_edp(intel_dp)) {
2104 /* init power sequencer on this pipe and port */
2105 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2106 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2107 &power_seq);
2108 }
bf13e81b 2109
ab1f90f9
JN		 2110 intel_enable_dp(encoder);
2111
e4607fcf 2112 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2113}
2114
ecff4f3b 2115static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2116{
2117 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2118 struct drm_device *dev = encoder->base.dev;
2119 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2120 struct intel_crtc *intel_crtc =
2121 to_intel_crtc(encoder->base.crtc);
e4607fcf 2122 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2123 int pipe = intel_crtc->pipe;
89b667f8 2124
8ac33ed3
DV		 2125 intel_dp_prepare(encoder);
2126
89b667f8 2127 /* Program Tx lane resets to default */
0980a60f 2128 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2129 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2130 DPIO_PCS_TX_LANE2_RESET |
2131 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2132 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2133 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2134 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2135 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2136 DPIO_PCS_CLK_SOFT_RESET);
2137
2138 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2139 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2140 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2141 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2142 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2143}
2144
e4a1d846
CML		 2145static void chv_pre_enable_dp(struct intel_encoder *encoder)
2146{
2147 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2148 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2149 struct drm_device *dev = encoder->base.dev;
2150 struct drm_i915_private *dev_priv = dev->dev_private;
2151 struct edp_power_seq power_seq;
2152 struct intel_crtc *intel_crtc =
2153 to_intel_crtc(encoder->base.crtc);
2154 enum dpio_channel ch = vlv_dport_to_channel(dport);
2155 int pipe = intel_crtc->pipe;
2156 int data, i;
949c1d43 2157 u32 val;
e4a1d846 2158
e4a1d846 2159 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2160
2161 /* Deassert soft data lane reset*/
97fd4d5c 2162 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2163 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2164 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2165
2166 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2167 val |= CHV_PCS_REQ_SOFTRESET_EN;
2168 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2169
2170 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2171 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2172 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2173
97fd4d5c 2174 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2175 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2176 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2177
2178 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2179 for (i = 0; i < 4; i++) {
2180 /* Set the latency optimal bit */
2181 data = (i == 1) ? 0x0 : 0x6;
2182 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2183 data << DPIO_FRC_LATENCY_SHFIT);
2184
2185 /* Set the upar bit */
2186 data = (i == 1) ? 0x0 : 0x1;
2187 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2188 data << DPIO_UPAR_SHIFT);
2189 }
2190
2191 /* Data lane stagger programming */
2192 /* FIXME: Fix up value only after power analysis */
2193
2194 mutex_unlock(&dev_priv->dpio_lock);
2195
2196 if (is_edp(intel_dp)) {
2197 /* init power sequencer on this pipe and port */
2198 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2199 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2200 &power_seq);
2201 }
2202
2203 intel_enable_dp(encoder);
2204
2205 vlv_wait_port_ready(dev_priv, dport);
2206}
2207
9197c88b
VS		 2208static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2209{
2210 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2211 struct drm_device *dev = encoder->base.dev;
2212 struct drm_i915_private *dev_priv = dev->dev_private;
2213 struct intel_crtc *intel_crtc =
2214 to_intel_crtc(encoder->base.crtc);
2215 enum dpio_channel ch = vlv_dport_to_channel(dport);
2216 enum pipe pipe = intel_crtc->pipe;
2217 u32 val;
2218
2219 mutex_lock(&dev_priv->dpio_lock);
2220
b9e5ac3c
VS		 2221 /* program left/right clock distribution */
2222 if (pipe != PIPE_B) {
2223 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2224 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2225 if (ch == DPIO_CH0)
2226 val |= CHV_BUFLEFTENA1_FORCE;
2227 if (ch == DPIO_CH1)
2228 val |= CHV_BUFRIGHTENA1_FORCE;
2229 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2230 } else {
2231 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2232 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2233 if (ch == DPIO_CH0)
2234 val |= CHV_BUFLEFTENA2_FORCE;
2235 if (ch == DPIO_CH1)
2236 val |= CHV_BUFRIGHTENA2_FORCE;
2237 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2238 }
2239
9197c88b
VS		 2240 /* program clock channel usage */
2241 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2242 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2243 if (pipe != PIPE_B)
2244 val &= ~CHV_PCS_USEDCLKCHANNEL;
2245 else
2246 val |= CHV_PCS_USEDCLKCHANNEL;
2247 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2248
2249 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2250 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2251 if (pipe != PIPE_B)
2252 val &= ~CHV_PCS_USEDCLKCHANNEL;
2253 else
2254 val |= CHV_PCS_USEDCLKCHANNEL;
2255 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2256
2257 /*
2258 * This a a bit weird since generally CL
2259 * matches the pipe, but here we need to
2260 * pick the CL based on the port.
2261 */
2262 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2263 if (pipe != PIPE_B)
2264 val &= ~CHV_CMN_USEDCLKCHANNEL;
2265 else
2266 val |= CHV_CMN_USEDCLKCHANNEL;
2267 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2268
2269 mutex_unlock(&dev_priv->dpio_lock);
2270}
2271
a4fc5ed6 2272/*
df0c237d
JB		 2273 * Native read with retry for link status and receiver capability reads for
2274 * cases where the sink may still be asleep.
9d1a1031
JN		 2275 *
2276 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2277 * supposed to retry 3 times per the spec.
a4fc5ed6 2278 */
9d1a1031
JN		 2279static ssize_t
2280intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2281 void *buffer, size_t size)
a4fc5ed6 2282{
9d1a1031
JN		 2283 ssize_t ret;
2284 int i;
61da5fab 2285
61da5fab 2286 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2287 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2288 if (ret == size)
2289 return ret;
61da5fab
JB		 2290 msleep(1);
2291 }
a4fc5ed6 2292
9d1a1031 2293 return ret;
a4fc5ed6
KP		 2294}
2295
2296/*
2297 * Fetch AUX CH registers 0x202 - 0x207 which contain
2298 * link status information
2299 */
2300static bool
93f62dad 2301intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2302{
9d1a1031
JN		 2303 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2304 DP_LANE0_1_STATUS,
2305 link_status,
2306 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2307}
2308
1100244e 2309/* These are source-specific values. */
a4fc5ed6 2310static uint8_t
1a2eb460 2311intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2312{
30add22d 2313 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2314 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2315
9576c27f 2316 if (IS_VALLEYVIEW(dev))
e2fa6fba 2317 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2318 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2319 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2320 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2321 return DP_TRAIN_VOLTAGE_SWING_1200;
2322 else
2323 return DP_TRAIN_VOLTAGE_SWING_800;
2324}
2325
2326static uint8_t
2327intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2328{
30add22d 2329 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2330 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2331
9576c27f 2332 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722
PZ		 2333 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2334 case DP_TRAIN_VOLTAGE_SWING_400:
2335 return DP_TRAIN_PRE_EMPHASIS_9_5;
2336 case DP_TRAIN_VOLTAGE_SWING_600:
2337 return DP_TRAIN_PRE_EMPHASIS_6;
2338 case DP_TRAIN_VOLTAGE_SWING_800:
2339 return DP_TRAIN_PRE_EMPHASIS_3_5;
2340 case DP_TRAIN_VOLTAGE_SWING_1200:
2341 default:
2342 return DP_TRAIN_PRE_EMPHASIS_0;
2343 }
e2fa6fba
P		 2344 } else if (IS_VALLEYVIEW(dev)) {
2345 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2346 case DP_TRAIN_VOLTAGE_SWING_400:
2347 return DP_TRAIN_PRE_EMPHASIS_9_5;
2348 case DP_TRAIN_VOLTAGE_SWING_600:
2349 return DP_TRAIN_PRE_EMPHASIS_6;
2350 case DP_TRAIN_VOLTAGE_SWING_800:
2351 return DP_TRAIN_PRE_EMPHASIS_3_5;
2352 case DP_TRAIN_VOLTAGE_SWING_1200:
2353 default:
2354 return DP_TRAIN_PRE_EMPHASIS_0;
2355 }
bc7d38a4 2356 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2357 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2358 case DP_TRAIN_VOLTAGE_SWING_400:
2359 return DP_TRAIN_PRE_EMPHASIS_6;
2360 case DP_TRAIN_VOLTAGE_SWING_600:
2361 case DP_TRAIN_VOLTAGE_SWING_800:
2362 return DP_TRAIN_PRE_EMPHASIS_3_5;
2363 default:
2364 return DP_TRAIN_PRE_EMPHASIS_0;
2365 }
2366 } else {
2367 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2368 case DP_TRAIN_VOLTAGE_SWING_400:
2369 return DP_TRAIN_PRE_EMPHASIS_6;
2370 case DP_TRAIN_VOLTAGE_SWING_600:
2371 return DP_TRAIN_PRE_EMPHASIS_6;
2372 case DP_TRAIN_VOLTAGE_SWING_800:
2373 return DP_TRAIN_PRE_EMPHASIS_3_5;
2374 case DP_TRAIN_VOLTAGE_SWING_1200:
2375 default:
2376 return DP_TRAIN_PRE_EMPHASIS_0;
2377 }
a4fc5ed6
KP		 2378 }
2379}
2380
e2fa6fba
P		 2381static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2382{
2383 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2384 struct drm_i915_private *dev_priv = dev->dev_private;
2385 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2386 struct intel_crtc *intel_crtc =
2387 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2388 unsigned long demph_reg_value, preemph_reg_value,
2389 uniqtranscale_reg_value;
2390 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2391 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2392 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2393
2394 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2395 case DP_TRAIN_PRE_EMPHASIS_0:
2396 preemph_reg_value = 0x0004000;
2397 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2398 case DP_TRAIN_VOLTAGE_SWING_400:
2399 demph_reg_value = 0x2B405555;
2400 uniqtranscale_reg_value = 0x552AB83A;
2401 break;
2402 case DP_TRAIN_VOLTAGE_SWING_600:
2403 demph_reg_value = 0x2B404040;
2404 uniqtranscale_reg_value = 0x5548B83A;
2405 break;
2406 case DP_TRAIN_VOLTAGE_SWING_800:
2407 demph_reg_value = 0x2B245555;
2408 uniqtranscale_reg_value = 0x5560B83A;
2409 break;
2410 case DP_TRAIN_VOLTAGE_SWING_1200:
2411 demph_reg_value = 0x2B405555;
2412 uniqtranscale_reg_value = 0x5598DA3A;
2413 break;
2414 default:
2415 return 0;
2416 }
2417 break;
2418 case DP_TRAIN_PRE_EMPHASIS_3_5:
2419 preemph_reg_value = 0x0002000;
2420 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2421 case DP_TRAIN_VOLTAGE_SWING_400:
2422 demph_reg_value = 0x2B404040;
2423 uniqtranscale_reg_value = 0x5552B83A;
2424 break;
2425 case DP_TRAIN_VOLTAGE_SWING_600:
2426 demph_reg_value = 0x2B404848;
2427 uniqtranscale_reg_value = 0x5580B83A;
2428 break;
2429 case DP_TRAIN_VOLTAGE_SWING_800:
2430 demph_reg_value = 0x2B404040;
2431 uniqtranscale_reg_value = 0x55ADDA3A;
2432 break;
2433 default:
2434 return 0;
2435 }
2436 break;
2437 case DP_TRAIN_PRE_EMPHASIS_6:
2438 preemph_reg_value = 0x0000000;
2439 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2440 case DP_TRAIN_VOLTAGE_SWING_400:
2441 demph_reg_value = 0x2B305555;
2442 uniqtranscale_reg_value = 0x5570B83A;
2443 break;
2444 case DP_TRAIN_VOLTAGE_SWING_600:
2445 demph_reg_value = 0x2B2B4040;
2446 uniqtranscale_reg_value = 0x55ADDA3A;
2447 break;
2448 default:
2449 return 0;
2450 }
2451 break;
2452 case DP_TRAIN_PRE_EMPHASIS_9_5:
2453 preemph_reg_value = 0x0006000;
2454 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2455 case DP_TRAIN_VOLTAGE_SWING_400:
2456 demph_reg_value = 0x1B405555;
2457 uniqtranscale_reg_value = 0x55ADDA3A;
2458 break;
2459 default:
2460 return 0;
2461 }
2462 break;
2463 default:
2464 return 0;
2465 }
2466
0980a60f 2467 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2468 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2469 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2470 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2471 uniqtranscale_reg_value);
ab3c759a
CML		 2472 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2473 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2474 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2475 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2476 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2477
2478 return 0;
2479}
2480
e4a1d846
CML		 2481static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2482{
2483 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2484 struct drm_i915_private *dev_priv = dev->dev_private;
2485 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2486 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2487 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2488 uint8_t train_set = intel_dp->train_set[0];
2489 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2490 enum pipe pipe = intel_crtc->pipe;
2491 int i;
e4a1d846
CML		 2492
2493 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2494 case DP_TRAIN_PRE_EMPHASIS_0:
2495 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2496 case DP_TRAIN_VOLTAGE_SWING_400:
2497 deemph_reg_value = 128;
2498 margin_reg_value = 52;
2499 break;
2500 case DP_TRAIN_VOLTAGE_SWING_600:
2501 deemph_reg_value = 128;
2502 margin_reg_value = 77;
2503 break;
2504 case DP_TRAIN_VOLTAGE_SWING_800:
2505 deemph_reg_value = 128;
2506 margin_reg_value = 102;
2507 break;
2508 case DP_TRAIN_VOLTAGE_SWING_1200:
2509 deemph_reg_value = 128;
2510 margin_reg_value = 154;
2511 /* FIXME extra to set for 1200 */
2512 break;
2513 default:
2514 return 0;
2515 }
2516 break;
2517 case DP_TRAIN_PRE_EMPHASIS_3_5:
2518 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2519 case DP_TRAIN_VOLTAGE_SWING_400:
2520 deemph_reg_value = 85;
2521 margin_reg_value = 78;
2522 break;
2523 case DP_TRAIN_VOLTAGE_SWING_600:
2524 deemph_reg_value = 85;
2525 margin_reg_value = 116;
2526 break;
2527 case DP_TRAIN_VOLTAGE_SWING_800:
2528 deemph_reg_value = 85;
2529 margin_reg_value = 154;
2530 break;
2531 default:
2532 return 0;
2533 }
2534 break;
2535 case DP_TRAIN_PRE_EMPHASIS_6:
2536 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2537 case DP_TRAIN_VOLTAGE_SWING_400:
2538 deemph_reg_value = 64;
2539 margin_reg_value = 104;
2540 break;
2541 case DP_TRAIN_VOLTAGE_SWING_600:
2542 deemph_reg_value = 64;
2543 margin_reg_value = 154;
2544 break;
2545 default:
2546 return 0;
2547 }
2548 break;
2549 case DP_TRAIN_PRE_EMPHASIS_9_5:
2550 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2551 case DP_TRAIN_VOLTAGE_SWING_400:
2552 deemph_reg_value = 43;
2553 margin_reg_value = 154;
2554 break;
2555 default:
2556 return 0;
2557 }
2558 break;
2559 default:
2560 return 0;
2561 }
2562
2563 mutex_lock(&dev_priv->dpio_lock);
2564
2565 /* Clear calc init */
1966e59e
VS		 2566 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2567 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2568 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2569
2570 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2571 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2572 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2573
2574 /* Program swing deemph */
f72df8db
VS		 2575 for (i = 0; i < 4; i++) {
2576 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2577 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2578 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2579 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2580 }
e4a1d846
CML		 2581
2582 /* Program swing margin */
f72df8db
VS		 2583 for (i = 0; i < 4; i++) {
2584 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2585 val &= ~DPIO_SWING_MARGIN_MASK;
2586 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2587 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2588 }
e4a1d846
CML		 2589
2590 /* Disable unique transition scale */
f72df8db
VS		 2591 for (i = 0; i < 4; i++) {
2592 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2593 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2594 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2595 }
e4a1d846
CML		 2596
2597 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2598 == DP_TRAIN_PRE_EMPHASIS_0) &&
2599 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2600 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2601
2602 /*
2603 * The document said it needs to set bit 27 for ch0 and bit 26
2604 * for ch1. Might be a typo in the doc.
2605 * For now, for this unique transition scale selection, set bit
2606 * 27 for ch0 and ch1.
2607 */
f72df8db
VS		 2608 for (i = 0; i < 4; i++) {
2609 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2610 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2611 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2612 }
e4a1d846 2613
f72df8db
VS		 2614 for (i = 0; i < 4; i++) {
2615 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2616 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2617 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2618 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2619 }
e4a1d846
CML		 2620 }
2621
2622 /* Start swing calculation */
1966e59e
VS		 2623 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2624 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2625 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2626
2627 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2628 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2629 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2630
2631 /* LRC Bypass */
2632 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2633 val |= DPIO_LRC_BYPASS;
2634 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2635
2636 mutex_unlock(&dev_priv->dpio_lock);
2637
2638 return 0;
2639}
2640
a4fc5ed6 2641static void
0301b3ac
JN		 2642intel_get_adjust_train(struct intel_dp *intel_dp,
2643 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2644{
2645 uint8_t v = 0;
2646 uint8_t p = 0;
2647 int lane;
1a2eb460
KP		 2648 uint8_t voltage_max;
2649 uint8_t preemph_max;
a4fc5ed6 2650
33a34e4e 2651 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2652 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2653 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2654
2655 if (this_v > v)
2656 v = this_v;
2657 if (this_p > p)
2658 p = this_p;
2659 }
2660
1a2eb460 2661 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2662 if (v >= voltage_max)
2663 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2664
1a2eb460
KP		 2665 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2666 if (p >= preemph_max)
2667 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2668
2669 for (lane = 0; lane < 4; lane++)
33a34e4e 2670 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2671}
2672
2673static uint32_t
f0a3424e 2674intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2675{
3cf2efb1 2676 uint32_t signal_levels = 0;
a4fc5ed6 2677
3cf2efb1 2678 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2679 case DP_TRAIN_VOLTAGE_SWING_400:
2680 default:
2681 signal_levels |= DP_VOLTAGE_0_4;
2682 break;
2683 case DP_TRAIN_VOLTAGE_SWING_600:
2684 signal_levels |= DP_VOLTAGE_0_6;
2685 break;
2686 case DP_TRAIN_VOLTAGE_SWING_800:
2687 signal_levels |= DP_VOLTAGE_0_8;
2688 break;
2689 case DP_TRAIN_VOLTAGE_SWING_1200:
2690 signal_levels |= DP_VOLTAGE_1_2;
2691 break;
2692 }
3cf2efb1 2693 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2694 case DP_TRAIN_PRE_EMPHASIS_0:
2695 default:
2696 signal_levels |= DP_PRE_EMPHASIS_0;
2697 break;
2698 case DP_TRAIN_PRE_EMPHASIS_3_5:
2699 signal_levels |= DP_PRE_EMPHASIS_3_5;
2700 break;
2701 case DP_TRAIN_PRE_EMPHASIS_6:
2702 signal_levels |= DP_PRE_EMPHASIS_6;
2703 break;
2704 case DP_TRAIN_PRE_EMPHASIS_9_5:
2705 signal_levels |= DP_PRE_EMPHASIS_9_5;
2706 break;
2707 }
2708 return signal_levels;
2709}
2710
e3421a18
ZW		 2711/* Gen6's DP voltage swing and pre-emphasis control */
2712static uint32_t
2713intel_gen6_edp_signal_levels(uint8_t train_set)
2714{
3c5a62b5
YL		 2715 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2716 DP_TRAIN_PRE_EMPHASIS_MASK);
2717 switch (signal_levels) {
e3421a18 2718 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2719 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2720 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2721 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2722 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2723 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2724 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2725 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2726 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2727 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2728 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2729 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2730 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2731 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2732 default:
3c5a62b5
YL		 2733 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2734 "0x%x\n", signal_levels);
2735 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2736 }
2737}
2738
1a2eb460
KP		 2739/* Gen7's DP voltage swing and pre-emphasis control */
2740static uint32_t
2741intel_gen7_edp_signal_levels(uint8_t train_set)
2742{
2743 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2744 DP_TRAIN_PRE_EMPHASIS_MASK);
2745 switch (signal_levels) {
2746 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2747 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2748 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2749 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2750 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2751 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2752
2753 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2754 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2755 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2756 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2757
2758 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2759 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2760 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2761 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2762
2763 default:
2764 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2765 "0x%x\n", signal_levels);
2766 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2767 }
2768}
2769
d6c0d722
PZ		 2770/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2771static uint32_t
f0a3424e 2772intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2773{
d6c0d722
PZ		 2774 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2775 DP_TRAIN_PRE_EMPHASIS_MASK);
2776 switch (signal_levels) {
2777 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2778 return DDI_BUF_EMP_400MV_0DB_HSW;
2779 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2780 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2781 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2782 return DDI_BUF_EMP_400MV_6DB_HSW;
2783 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2784 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2785
d6c0d722
PZ		 2786 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2787 return DDI_BUF_EMP_600MV_0DB_HSW;
2788 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2789 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2790 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2791 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2792
d6c0d722
PZ		 2793 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2794 return DDI_BUF_EMP_800MV_0DB_HSW;
2795 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2796 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2797 default:
2798 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2799 "0x%x\n", signal_levels);
2800 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2801 }
a4fc5ed6
KP		 2802}
2803
f0a3424e
PZ		 2804/* Properly updates "DP" with the correct signal levels. */
2805static void
2806intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2807{
2808 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2809 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2810 struct drm_device *dev = intel_dig_port->base.base.dev;
2811 uint32_t signal_levels, mask;
2812 uint8_t train_set = intel_dp->train_set[0];
2813
9576c27f 2814 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 2815 signal_levels = intel_hsw_signal_levels(train_set);
2816 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 2817 } else if (IS_CHERRYVIEW(dev)) {
2818 signal_levels = intel_chv_signal_levels(intel_dp);
2819 mask = 0;
e2fa6fba
P		 2820 } else if (IS_VALLEYVIEW(dev)) {
2821 signal_levels = intel_vlv_signal_levels(intel_dp);
2822 mask = 0;
bc7d38a4 2823 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2824 signal_levels = intel_gen7_edp_signal_levels(train_set);
2825 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2826 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2827 signal_levels = intel_gen6_edp_signal_levels(train_set);
2828 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2829 } else {
2830 signal_levels = intel_gen4_signal_levels(train_set);
2831 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2832 }
2833
2834 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2835
2836 *DP = (*DP & ~mask) | signal_levels;
2837}
2838
a4fc5ed6 2839static bool
ea5b213a 2840intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2841 uint32_t *DP,
58e10eb9 2842 uint8_t dp_train_pat)
a4fc5ed6 2843{
174edf1f
PZ		 2844 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2845 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2846 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2847 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2848 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2849 int ret, len;
a4fc5ed6 2850
22b8bf17 2851 if (HAS_DDI(dev)) {
3ab9c637 2852 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2853
2854 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2855 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2856 else
2857 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2858
2859 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2860 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2861 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2862 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2863
2864 break;
2865 case DP_TRAINING_PATTERN_1:
2866 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2867 break;
2868 case DP_TRAINING_PATTERN_2:
2869 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2870 break;
2871 case DP_TRAINING_PATTERN_3:
2872 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2873 break;
2874 }
174edf1f 2875 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2876
bc7d38a4 2877 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2878 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2879
2880 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2881 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2882 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2883 break;
2884 case DP_TRAINING_PATTERN_1:
70aff66c 2885 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2886 break;
2887 case DP_TRAINING_PATTERN_2:
70aff66c 2888 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2889 break;
2890 case DP_TRAINING_PATTERN_3:
2891 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2892 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2893 break;
2894 }
2895
2896 } else {
70aff66c 2897 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2898
2899 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2900 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2901 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2902 break;
2903 case DP_TRAINING_PATTERN_1:
70aff66c 2904 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2905 break;
2906 case DP_TRAINING_PATTERN_2:
70aff66c 2907 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2908 break;
2909 case DP_TRAINING_PATTERN_3:
2910 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2911 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2912 break;
2913 }
2914 }
2915
70aff66c 2916 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2917 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2918
2cdfe6c8
JN		 2919 buf[0] = dp_train_pat;
2920 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2921 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2922 /* don't write DP_TRAINING_LANEx_SET on disable */
2923 len = 1;
2924 } else {
2925 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2926 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2927 len = intel_dp->lane_count + 1;
47ea7542 2928 }
a4fc5ed6 2929
9d1a1031
JN		 2930 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2931 buf, len);
2cdfe6c8
JN		 2932
2933 return ret == len;
a4fc5ed6
KP		 2934}
2935
70aff66c
JN		 2936static bool
2937intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2938 uint8_t dp_train_pat)
2939{
953d22e8 2940 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2941 intel_dp_set_signal_levels(intel_dp, DP);
2942 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2943}
2944
2945static bool
2946intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2947 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2948{
2949 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2950 struct drm_device *dev = intel_dig_port->base.base.dev;
2951 struct drm_i915_private *dev_priv = dev->dev_private;
2952 int ret;
2953
2954 intel_get_adjust_train(intel_dp, link_status);
2955 intel_dp_set_signal_levels(intel_dp, DP);
2956
2957 I915_WRITE(intel_dp->output_reg, *DP);
2958 POSTING_READ(intel_dp->output_reg);
2959
9d1a1031
JN		 2960 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2961 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 2962
2963 return ret == intel_dp->lane_count;
2964}
2965
3ab9c637
ID		 2966static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2967{
2968 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2969 struct drm_device *dev = intel_dig_port->base.base.dev;
2970 struct drm_i915_private *dev_priv = dev->dev_private;
2971 enum port port = intel_dig_port->port;
2972 uint32_t val;
2973
2974 if (!HAS_DDI(dev))
2975 return;
2976
2977 val = I915_READ(DP_TP_CTL(port));
2978 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2979 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2980 I915_WRITE(DP_TP_CTL(port), val);
2981
2982 /*
2983 * On PORT_A we can have only eDP in SST mode. There the only reason
2984 * we need to set idle transmission mode is to work around a HW issue
2985 * where we enable the pipe while not in idle link-training mode.
2986 * In this case there is requirement to wait for a minimum number of
2987 * idle patterns to be sent.
2988 */
2989 if (port == PORT_A)
2990 return;
2991
2992 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2993 1))
2994 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2995}
2996
33a34e4e 2997/* Enable corresponding port and start training pattern 1 */
c19b0669 2998void
33a34e4e 2999intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3000{
da63a9f2 3001 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3002 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3003 int i;
3004 uint8_t voltage;
cdb0e95b 3005 int voltage_tries, loop_tries;
ea5b213a 3006 uint32_t DP = intel_dp->DP;
6aba5b6c 3007 uint8_t link_config[2];
a4fc5ed6 3008
affa9354 3009 if (HAS_DDI(dev))
c19b0669
PZ		 3010 intel_ddi_prepare_link_retrain(encoder);
3011
3cf2efb1 3012 /* Write the link configuration data */
6aba5b6c
JN		 3013 link_config[0] = intel_dp->link_bw;
3014 link_config[1] = intel_dp->lane_count;
3015 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3016 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3017 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3018
3019 link_config[0] = 0;
3020 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3021 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3022
3023 DP |= DP_PORT_EN;
1a2eb460 3024
70aff66c
JN		 3025 /* clock recovery */
3026 if (!intel_dp_reset_link_train(intel_dp, &DP,
3027 DP_TRAINING_PATTERN_1 |
3028 DP_LINK_SCRAMBLING_DISABLE)) {
3029 DRM_ERROR("failed to enable link training\n");
3030 return;
3031 }
3032
a4fc5ed6 3033 voltage = 0xff;
cdb0e95b
KP		 3034 voltage_tries = 0;
3035 loop_tries = 0;
a4fc5ed6 3036 for (;;) {
70aff66c 3037 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3038
a7c9655f 3039 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3040 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3041 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3042 break;
93f62dad 3043 }
a4fc5ed6 3044
01916270 3045 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3046 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3047 break;
3048 }
3049
3050 /* Check to see if we've tried the max voltage */
3051 for (i = 0; i < intel_dp->lane_count; i++)
3052 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3053 break;
3b4f819d 3054 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3055 ++loop_tries;
3056 if (loop_tries == 5) {
3def84b3 3057 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3058 break;
3059 }
70aff66c
JN		 3060 intel_dp_reset_link_train(intel_dp, &DP,
3061 DP_TRAINING_PATTERN_1 |
3062 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3063 voltage_tries = 0;
3064 continue;
3065 }
a4fc5ed6 3066
3cf2efb1 3067 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3068 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3069 ++voltage_tries;
b06fbda3 3070 if (voltage_tries == 5) {
3def84b3 3071 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3072 break;
3073 }
3074 } else
3075 voltage_tries = 0;
3076 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3077
70aff66c
JN		 3078 /* Update training set as requested by target */
3079 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3080 DRM_ERROR("failed to update link training\n");
3081 break;
3082 }
a4fc5ed6
KP		 3083 }
3084
33a34e4e
JB		 3085 intel_dp->DP = DP;
3086}
3087
c19b0669 3088void
33a34e4e
JB		 3089intel_dp_complete_link_train(struct intel_dp *intel_dp)
3090{
33a34e4e 3091 bool channel_eq = false;
37f80975 3092 int tries, cr_tries;
33a34e4e 3093 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3094 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3095
3096 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3097 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3098 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3099
a4fc5ed6 3100 /* channel equalization */
70aff66c 3101 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3102 training_pattern |
70aff66c
JN		 3103 DP_LINK_SCRAMBLING_DISABLE)) {
3104 DRM_ERROR("failed to start channel equalization\n");
3105 return;
3106 }
3107
a4fc5ed6 3108 tries = 0;
37f80975 3109 cr_tries = 0;
a4fc5ed6
KP		 3110 channel_eq = false;
3111 for (;;) {
70aff66c 3112 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3113
37f80975
JB		 3114 if (cr_tries > 5) {
3115 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3116 break;
3117 }
3118
a7c9655f 3119 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3120 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3121 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3122 break;
70aff66c 3123 }
a4fc5ed6 3124
37f80975 3125 /* Make sure clock is still ok */
01916270 3126 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3127 intel_dp_start_link_train(intel_dp);
70aff66c 3128 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3129 training_pattern |
70aff66c 3130 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3131 cr_tries++;
3132 continue;
3133 }
3134
1ffdff13 3135 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3136 channel_eq = true;
3137 break;
3138 }
a4fc5ed6 3139
37f80975
JB		 3140 /* Try 5 times, then try clock recovery if that fails */
3141 if (tries > 5) {
3142 intel_dp_link_down(intel_dp);
3143 intel_dp_start_link_train(intel_dp);
70aff66c 3144 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3145 training_pattern |
70aff66c 3146 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3147 tries = 0;
3148 cr_tries++;
3149 continue;
3150 }
a4fc5ed6 3151
70aff66c
JN		 3152 /* Update training set as requested by target */
3153 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3154 DRM_ERROR("failed to update link training\n");
3155 break;
3156 }
3cf2efb1 3157 ++tries;
869184a6 3158 }
3cf2efb1 3159
3ab9c637
ID		 3160 intel_dp_set_idle_link_train(intel_dp);
3161
3162 intel_dp->DP = DP;
3163
d6c0d722 3164 if (channel_eq)
07f42258 3165 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3166
3ab9c637
ID		 3167}
3168
3169void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3170{
70aff66c 3171 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3172 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3173}
3174
3175static void
ea5b213a 3176intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3177{
da63a9f2 3178 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3179 enum port port = intel_dig_port->port;
da63a9f2 3180 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3181 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3182 struct intel_crtc *intel_crtc =
3183 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3184 uint32_t DP = intel_dp->DP;
a4fc5ed6 3185
bc76e320 3186 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3187 return;
3188
0c33d8d7 3189 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3190 return;
3191
28c97730 3192 DRM_DEBUG_KMS("\n");
32f9d658 3193
bc7d38a4 3194 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3195 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3196 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 3197 } else {
3198 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3199 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3200 }
fe255d00 3201 POSTING_READ(intel_dp->output_reg);
5eb08b69 3202
493a7081 3203 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3204 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3205 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3206
5bddd17f
EA		 3207 /* Hardware workaround: leaving our transcoder select
3208 * set to transcoder B while it's off will prevent the
3209 * corresponding HDMI output on transcoder A.
3210 *
3211 * Combine this with another hardware workaround:
3212 * transcoder select bit can only be cleared while the
3213 * port is enabled.
3214 */
3215 DP &= ~DP_PIPEB_SELECT;
3216 I915_WRITE(intel_dp->output_reg, DP);
3217
3218 /* Changes to enable or select take place the vblank
3219 * after being written.
3220 */
ff50afe9
DV		 3221 if (WARN_ON(crtc == NULL)) {
3222 /* We should never try to disable a port without a crtc
3223 * attached. For paranoia keep the code around for a
3224 * bit. */
31acbcc4
CW		 3225 POSTING_READ(intel_dp->output_reg);
3226 msleep(50);
3227 } else
ab527efc 3228 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3229 }
3230
832afda6 3231 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3232 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3233 POSTING_READ(intel_dp->output_reg);
f01eca2e 3234 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3235}
3236
26d61aad
KP		 3237static bool
3238intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3239{
a031d709
RV		 3240 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3241 struct drm_device *dev = dig_port->base.base.dev;
3242 struct drm_i915_private *dev_priv = dev->dev_private;
3243
577c7a50
DL		 3244 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3245
9d1a1031
JN		 3246 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3247 sizeof(intel_dp->dpcd)) < 0)
edb39244 3248 return false; /* aux transfer failed */
92fd8fd1 3249
577c7a50
DL		 3250 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3251 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3252 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3253
edb39244
AJ		 3254 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3255 return false; /* DPCD not present */
3256
2293bb5c
SK		 3257 /* Check if the panel supports PSR */
3258 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3259 if (is_edp(intel_dp)) {
9d1a1031
JN		 3260 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3261 intel_dp->psr_dpcd,
3262 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3263 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3264 dev_priv->psr.sink_support = true;
50003939 3265 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3266 }
50003939
JN		 3267 }
3268
06ea66b6
TP		 3269 /* Training Pattern 3 support */
3270 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3271 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3272 intel_dp->use_tps3 = true;
3273 DRM_DEBUG_KMS("Displayport TPS3 supported");
3274 } else
3275 intel_dp->use_tps3 = false;
3276
edb39244
AJ		 3277 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3278 DP_DWN_STRM_PORT_PRESENT))
3279 return true; /* native DP sink */
3280
3281 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3282 return true; /* no per-port downstream info */
3283
9d1a1031
JN		 3284 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3285 intel_dp->downstream_ports,
3286 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3287 return false; /* downstream port status fetch failed */
3288
3289 return true;
92fd8fd1
KP		 3290}
3291
0d198328
AJ		 3292static void
3293intel_dp_probe_oui(struct intel_dp *intel_dp)
3294{
3295 u8 buf[3];
3296
3297 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3298 return;
3299
24f3e092 3300 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3301
9d1a1031 3302 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3303 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3304 buf[0], buf[1], buf[2]);
3305
9d1a1031 3306 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3307 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3308 buf[0], buf[1], buf[2]);
351cfc34 3309
4be73780 3310 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3311}
3312
0e32b39c
DA		 3313static bool
3314intel_dp_probe_mst(struct intel_dp *intel_dp)
3315{
3316 u8 buf[1];
3317
3318 if (!intel_dp->can_mst)
3319 return false;
3320
3321 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3322 return false;
3323
3324 _edp_panel_vdd_on(intel_dp);
3325 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3326 if (buf[0] & DP_MST_CAP) {
3327 DRM_DEBUG_KMS("Sink is MST capable\n");
3328 intel_dp->is_mst = true;
3329 } else {
3330 DRM_DEBUG_KMS("Sink is not MST capable\n");
3331 intel_dp->is_mst = false;
3332 }
3333 }
3334 edp_panel_vdd_off(intel_dp, false);
3335
3336 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3337 return intel_dp->is_mst;
3338}
3339
d2e216d0
RV		 3340int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3341{
3342 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3343 struct drm_device *dev = intel_dig_port->base.base.dev;
3344 struct intel_crtc *intel_crtc =
3345 to_intel_crtc(intel_dig_port->base.base.crtc);
3346 u8 buf[1];
3347
9d1a1031 3348 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3349 return -EAGAIN;
3350
3351 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3352 return -ENOTTY;
3353
9d1a1031
JN		 3354 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3355 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3356 return -EAGAIN;
3357
3358 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3359 intel_wait_for_vblank(dev, intel_crtc->pipe);
3360 intel_wait_for_vblank(dev, intel_crtc->pipe);
3361
9d1a1031 3362 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3363 return -EAGAIN;
3364
9d1a1031 3365 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3366 return 0;
3367}
3368
a60f0e38
JB		 3369static bool
3370intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3371{
9d1a1031
JN		 3372 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3373 DP_DEVICE_SERVICE_IRQ_VECTOR,
3374 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3375}
3376
0e32b39c
DA		 3377static bool
3378intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3379{
3380 int ret;
3381
3382 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3383 DP_SINK_COUNT_ESI,
3384 sink_irq_vector, 14);
3385 if (ret != 14)
3386 return false;
3387
3388 return true;
3389}
3390
a60f0e38
JB		 3391static void
3392intel_dp_handle_test_request(struct intel_dp *intel_dp)
3393{
3394 /* NAK by default */
9d1a1031 3395 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3396}
3397
0e32b39c
DA		 3398static int
3399intel_dp_check_mst_status(struct intel_dp *intel_dp)
3400{
3401 bool bret;
3402
3403 if (intel_dp->is_mst) {
3404 u8 esi[16] = { 0 };
3405 int ret = 0;
3406 int retry;
3407 bool handled;
3408 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3409go_again:
3410 if (bret == true) {
3411
3412 /* check link status - esi[10] = 0x200c */
3413 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3414 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3415 intel_dp_start_link_train(intel_dp);
3416 intel_dp_complete_link_train(intel_dp);
3417 intel_dp_stop_link_train(intel_dp);
3418 }
3419
3420 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3421 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3422
3423 if (handled) {
3424 for (retry = 0; retry < 3; retry++) {
3425 int wret;
3426 wret = drm_dp_dpcd_write(&intel_dp->aux,
3427 DP_SINK_COUNT_ESI+1,
3428 &esi[1], 3);
3429 if (wret == 3) {
3430 break;
3431 }
3432 }
3433
3434 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3435 if (bret == true) {
3436 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3437 goto go_again;
3438 }
3439 } else
3440 ret = 0;
3441
3442 return ret;
3443 } else {
3444 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3445 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3446 intel_dp->is_mst = false;
3447 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3448 /* send a hotplug event */
3449 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3450 }
3451 }
3452 return -EINVAL;
3453}
3454
a4fc5ed6
KP		 3455/*
3456 * According to DP spec
3457 * 5.1.2:
3458 * 1. Read DPCD
3459 * 2. Configure link according to Receiver Capabilities
3460 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3461 * 4. Check link status on receipt of hot-plug interrupt
3462 */
00c09d70 3463void
ea5b213a 3464intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3465{
da63a9f2 3466 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3467 u8 sink_irq_vector;
93f62dad 3468 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3469
6e9f798d 3470 /* FIXME: This access isn't protected by any locks. */
da63a9f2 3471 if (!intel_encoder->connectors_active)
d2b996ac 3472 return;
59cd09e1 3473
da63a9f2 3474 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3475 return;
3476
92fd8fd1 3477 /* Try to read receiver status if the link appears to be up */
93f62dad 3478 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3479 return;
3480 }
3481
92fd8fd1 3482 /* Now read the DPCD to see if it's actually running */
26d61aad 3483 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3484 return;
3485 }
3486
a60f0e38
JB		 3487 /* Try to read the source of the interrupt */
3488 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3489 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3490 /* Clear interrupt source */
9d1a1031
JN		 3491 drm_dp_dpcd_writeb(&intel_dp->aux,
3492 DP_DEVICE_SERVICE_IRQ_VECTOR,
3493 sink_irq_vector);
a60f0e38
JB		 3494
3495 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3496 intel_dp_handle_test_request(intel_dp);
3497 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3498 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3499 }
3500
1ffdff13 3501 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3502 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3503 intel_encoder->base.name);
33a34e4e
JB		 3504 intel_dp_start_link_train(intel_dp);
3505 intel_dp_complete_link_train(intel_dp);
3ab9c637 3506 intel_dp_stop_link_train(intel_dp);
33a34e4e 3507 }
a4fc5ed6 3508}
a4fc5ed6 3509
caf9ab24 3510/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3511static enum drm_connector_status
26d61aad 3512intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3513{
caf9ab24 3514 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3515 uint8_t type;
3516
3517 if (!intel_dp_get_dpcd(intel_dp))
3518 return connector_status_disconnected;
3519
3520 /* if there's no downstream port, we're done */
3521 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3522 return connector_status_connected;
caf9ab24
AJ		 3523
3524 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3525 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3526 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3527 uint8_t reg;
9d1a1031
JN		 3528
3529 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3530 &reg, 1) < 0)
caf9ab24 3531 return connector_status_unknown;
9d1a1031 3532
23235177
AJ		 3533 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3534 : connector_status_disconnected;
caf9ab24
AJ		 3535 }
3536
3537 /* If no HPD, poke DDC gently */
0b99836f 3538 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3539 return connector_status_connected;
caf9ab24
AJ		 3540
3541 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3542 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3543 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3544 if (type == DP_DS_PORT_TYPE_VGA ||
3545 type == DP_DS_PORT_TYPE_NON_EDID)
3546 return connector_status_unknown;
3547 } else {
3548 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3549 DP_DWN_STRM_PORT_TYPE_MASK;
3550 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3551 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3552 return connector_status_unknown;
3553 }
caf9ab24
AJ		 3554
3555 /* Anything else is out of spec, warn and ignore */
3556 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3557 return connector_status_disconnected;
71ba9000
AJ		 3558}
3559
5eb08b69 3560static enum drm_connector_status
a9756bb5 3561ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3562{
30add22d 3563 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3564 struct drm_i915_private *dev_priv = dev->dev_private;
3565 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3566 enum drm_connector_status status;
3567
fe16d949
CW		 3568 /* Can't disconnect eDP, but you can close the lid... */
3569 if (is_edp(intel_dp)) {
30add22d 3570 status = intel_panel_detect(dev);
fe16d949
CW		 3571 if (status == connector_status_unknown)
3572 status = connector_status_connected;
3573 return status;
3574 }
01cb9ea6 3575
1b469639
DL		 3576 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3577 return connector_status_disconnected;
3578
26d61aad 3579 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3580}
3581
a4fc5ed6 3582static enum drm_connector_status
a9756bb5 3583g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3584{
30add22d 3585 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3586 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3587 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3588 uint32_t bit;
5eb08b69 3589
35aad75f
JB		 3590 /* Can't disconnect eDP, but you can close the lid... */
3591 if (is_edp(intel_dp)) {
3592 enum drm_connector_status status;
3593
3594 status = intel_panel_detect(dev);
3595 if (status == connector_status_unknown)
3596 status = connector_status_connected;
3597 return status;
3598 }
3599
232a6ee9
TP		 3600 if (IS_VALLEYVIEW(dev)) {
3601 switch (intel_dig_port->port) {
3602 case PORT_B:
3603 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3604 break;
3605 case PORT_C:
3606 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3607 break;
3608 case PORT_D:
3609 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3610 break;
3611 default:
3612 return connector_status_unknown;
3613 }
3614 } else {
3615 switch (intel_dig_port->port) {
3616 case PORT_B:
3617 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3618 break;
3619 case PORT_C:
3620 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3621 break;
3622 case PORT_D:
3623 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3624 break;
3625 default:
3626 return connector_status_unknown;
3627 }
a4fc5ed6
KP		 3628 }
3629
10f76a38 3630 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3631 return connector_status_disconnected;
3632
26d61aad 3633 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3634}
3635
8c241fef
KP		 3636static struct edid *
3637intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3638{
9cd300e0 3639 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3640
9cd300e0
JN		 3641 /* use cached edid if we have one */
3642 if (intel_connector->edid) {
9cd300e0
JN		 3643 /* invalid edid */
3644 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3645 return NULL;
3646
55e9edeb 3647 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3648 }
8c241fef 3649
9cd300e0 3650 return drm_get_edid(connector, adapter);
8c241fef
KP		 3651}
3652
3653static int
3654intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3655{
9cd300e0 3656 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3657
9cd300e0
JN		 3658 /* use cached edid if we have one */
3659 if (intel_connector->edid) {
3660 /* invalid edid */
3661 if (IS_ERR(intel_connector->edid))
3662 return 0;
3663
3664 return intel_connector_update_modes(connector,
3665 intel_connector->edid);
d6f24d0f
JB		 3666 }
3667
9cd300e0 3668 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3669}
3670
a9756bb5
ZW		 3671static enum drm_connector_status
3672intel_dp_detect(struct drm_connector *connector, bool force)
3673{
3674 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3675 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3676 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3677 struct drm_device *dev = connector->dev;
c8c8fb33 3678 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3679 enum drm_connector_status status;
671dedd2 3680 enum intel_display_power_domain power_domain;
a9756bb5 3681 struct edid *edid = NULL;
0e32b39c 3682 bool ret;
a9756bb5 3683
c8c8fb33
PZ		 3684 intel_runtime_pm_get(dev_priv);
3685
671dedd2
ID		 3686 power_domain = intel_display_port_power_domain(intel_encoder);
3687 intel_display_power_get(dev_priv, power_domain);
3688
164c8598 3689 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 3690 connector->base.id, connector->name);
164c8598 3691
0e32b39c
DA		 3692 if (intel_dp->is_mst) {
3693 /* MST devices are disconnected from a monitor POV */
3694 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3695 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3696 status = connector_status_disconnected;
3697 goto out;
3698 }
3699
a9756bb5
ZW		 3700 intel_dp->has_audio = false;
3701
3702 if (HAS_PCH_SPLIT(dev))
3703 status = ironlake_dp_detect(intel_dp);
3704 else
3705 status = g4x_dp_detect(intel_dp);
1b9be9d0 3706
a9756bb5 3707 if (status != connector_status_connected)
c8c8fb33 3708 goto out;
a9756bb5 3709
0d198328
AJ		 3710 intel_dp_probe_oui(intel_dp);
3711
0e32b39c
DA		 3712 ret = intel_dp_probe_mst(intel_dp);
3713 if (ret) {
3714 /* if we are in MST mode then this connector
3715 won't appear connected or have anything with EDID on it */
3716 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3717 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3718 status = connector_status_disconnected;
3719 goto out;
3720 }
3721
c3e5f67b
DV		 3722 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3723 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3724 } else {
0b99836f 3725 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3726 if (edid) {
3727 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3728 kfree(edid);
3729 }
a9756bb5
ZW		 3730 }
3731
d63885da
PZ		 3732 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3733 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3734 status = connector_status_connected;
3735
3736out:
671dedd2
ID		 3737 intel_display_power_put(dev_priv, power_domain);
3738
c8c8fb33 3739 intel_runtime_pm_put(dev_priv);
671dedd2 3740
c8c8fb33 3741 return status;
a4fc5ed6
KP		 3742}
3743
3744static int intel_dp_get_modes(struct drm_connector *connector)
3745{
df0e9248 3746 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3747 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3748 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3749 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3750 struct drm_device *dev = connector->dev;
671dedd2
ID		 3751 struct drm_i915_private *dev_priv = dev->dev_private;
3752 enum intel_display_power_domain power_domain;
32f9d658 3753 int ret;
a4fc5ed6
KP		 3754
3755 /* We should parse the EDID data and find out if it has an audio sink
3756 */
3757
671dedd2
ID		 3758 power_domain = intel_display_port_power_domain(intel_encoder);
3759 intel_display_power_get(dev_priv, power_domain);
3760
0b99836f 3761 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3762 intel_display_power_put(dev_priv, power_domain);
f8779fda 3763 if (ret)
32f9d658
ZW		 3764 return ret;
3765
f8779fda 3766 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3767 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3768 struct drm_display_mode *mode;
dd06f90e
JN		 3769 mode = drm_mode_duplicate(dev,
3770 intel_connector->panel.fixed_mode);
f8779fda 3771 if (mode) {
32f9d658
ZW		 3772 drm_mode_probed_add(connector, mode);
3773 return 1;
3774 }
3775 }
3776 return 0;
a4fc5ed6
KP		 3777}
3778
1aad7ac0
CW		 3779static bool
3780intel_dp_detect_audio(struct drm_connector *connector)
3781{
3782 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3783 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3784 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3785 struct drm_device *dev = connector->dev;
3786 struct drm_i915_private *dev_priv = dev->dev_private;
3787 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3788 struct edid *edid;
3789 bool has_audio = false;
3790
671dedd2
ID		 3791 power_domain = intel_display_port_power_domain(intel_encoder);
3792 intel_display_power_get(dev_priv, power_domain);
3793
0b99836f 3794 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3795 if (edid) {
3796 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3797 kfree(edid);
3798 }
3799
671dedd2
ID		 3800 intel_display_power_put(dev_priv, power_domain);
3801
1aad7ac0
CW		 3802 return has_audio;
3803}
3804
f684960e
CW		 3805static int
3806intel_dp_set_property(struct drm_connector *connector,
3807 struct drm_property *property,
3808 uint64_t val)
3809{
e953fd7b 3810 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3811 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3812 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3813 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3814 int ret;
3815
662595df 3816 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3817 if (ret)
3818 return ret;
3819
3f43c48d 3820 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3821 int i = val;
3822 bool has_audio;
3823
3824 if (i == intel_dp->force_audio)
f684960e
CW		 3825 return 0;
3826
1aad7ac0 3827 intel_dp->force_audio = i;
f684960e 3828
c3e5f67b 3829 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3830 has_audio = intel_dp_detect_audio(connector);
3831 else
c3e5f67b 3832 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3833
3834 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3835 return 0;
3836
1aad7ac0 3837 intel_dp->has_audio = has_audio;
f684960e
CW		 3838 goto done;
3839 }
3840
e953fd7b 3841 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3842 bool old_auto = intel_dp->color_range_auto;
3843 uint32_t old_range = intel_dp->color_range;
3844
55bc60db
VS		 3845 switch (val) {
3846 case INTEL_BROADCAST_RGB_AUTO:
3847 intel_dp->color_range_auto = true;
3848 break;
3849 case INTEL_BROADCAST_RGB_FULL:
3850 intel_dp->color_range_auto = false;
3851 intel_dp->color_range = 0;
3852 break;
3853 case INTEL_BROADCAST_RGB_LIMITED:
3854 intel_dp->color_range_auto = false;
3855 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3856 break;
3857 default:
3858 return -EINVAL;
3859 }
ae4edb80
DV		 3860
3861 if (old_auto == intel_dp->color_range_auto &&
3862 old_range == intel_dp->color_range)
3863 return 0;
3864
e953fd7b
CW		 3865 goto done;
3866 }
3867
53b41837
YN		 3868 if (is_edp(intel_dp) &&
3869 property == connector->dev->mode_config.scaling_mode_property) {
3870 if (val == DRM_MODE_SCALE_NONE) {
3871 DRM_DEBUG_KMS("no scaling not supported\n");
3872 return -EINVAL;
3873 }
3874
3875 if (intel_connector->panel.fitting_mode == val) {
3876 /* the eDP scaling property is not changed */
3877 return 0;
3878 }
3879 intel_connector->panel.fitting_mode = val;
3880
3881 goto done;
3882 }
3883
f684960e
CW		 3884 return -EINVAL;
3885
3886done:
c0c36b94
CW		 3887 if (intel_encoder->base.crtc)
3888 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3889
3890 return 0;
3891}
3892
a4fc5ed6 3893static void
73845adf 3894intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3895{
1d508706 3896 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3897
9cd300e0
JN		 3898 if (!IS_ERR_OR_NULL(intel_connector->edid))
3899 kfree(intel_connector->edid);
3900
acd8db10
PZ		 3901 /* Can't call is_edp() since the encoder may have been destroyed
3902 * already. */
3903 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3904 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3905
a4fc5ed6 3906 drm_connector_cleanup(connector);
55f78c43 3907 kfree(connector);
a4fc5ed6
KP		 3908}
3909
00c09d70 3910void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3911{
da63a9f2
PZ		 3912 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3913 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3914 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 3915
4f71d0cb 3916 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 3917 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 3918 drm_encoder_cleanup(encoder);
bd943159
KP		 3919 if (is_edp(intel_dp)) {
3920 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 3921 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 3922 edp_panel_vdd_off_sync(intel_dp);
51fd371b 3923 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159 3924 }
da63a9f2 3925 kfree(intel_dig_port);
24d05927
DV		 3926}
3927
a4fc5ed6 3928static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3929 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3930 .detect = intel_dp_detect,
3931 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3932 .set_property = intel_dp_set_property,
73845adf 3933 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3934};
3935
3936static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3937 .get_modes = intel_dp_get_modes,
3938 .mode_valid = intel_dp_mode_valid,
df0e9248 3939 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3940};
3941
a4fc5ed6 3942static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3943 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3944};
3945
0e32b39c 3946void
21d40d37 3947intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3948{
0e32b39c 3949 return;
c8110e52 3950}
6207937d 3951
13cf5504
DA		 3952bool
3953intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
3954{
3955 struct intel_dp *intel_dp = &intel_dig_port->dp;
0e32b39c
DA		 3956 struct drm_device *dev = intel_dig_port->base.base.dev;
3957 struct drm_i915_private *dev_priv = dev->dev_private;
3958 int ret;
3959 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
3960 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 3961
0e32b39c
DA		 3962 DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port,
3963 long_hpd ? "long" : "short");
13cf5504 3964
0e32b39c
DA		 3965 if (long_hpd) {
3966 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3967 goto mst_fail;
3968
3969 if (!intel_dp_get_dpcd(intel_dp)) {
3970 goto mst_fail;
3971 }
3972
3973 intel_dp_probe_oui(intel_dp);
3974
3975 if (!intel_dp_probe_mst(intel_dp))
3976 goto mst_fail;
3977
3978 } else {
3979 if (intel_dp->is_mst) {
3980 ret = intel_dp_check_mst_status(intel_dp);
3981 if (ret == -EINVAL)
3982 goto mst_fail;
3983 }
3984
3985 if (!intel_dp->is_mst) {
3986 /*
3987 * we'll check the link status via the normal hot plug path later -
3988 * but for short hpds we should check it now
3989 */
3990 intel_dp_check_link_status(intel_dp);
3991 }
3992 }
13cf5504 3993 return false;
0e32b39c
DA		 3994mst_fail:
3995 /* if we were in MST mode, and device is not there get out of MST mode */
3996 if (intel_dp->is_mst) {
3997 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
3998 intel_dp->is_mst = false;
3999 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4000 }
4001 return true;
13cf5504
DA		 4002}
4003
e3421a18
ZW		 4004/* Return which DP Port should be selected for Transcoder DP control */
4005int
0206e353 4006intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4007{
4008 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4009 struct intel_encoder *intel_encoder;
4010 struct intel_dp *intel_dp;
e3421a18 4011
fa90ecef
PZ		 4012 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4013 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4014
fa90ecef
PZ		 4015 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4016 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4017 return intel_dp->output_reg;
e3421a18 4018 }
ea5b213a 4019
e3421a18
ZW		 4020 return -1;
4021}
4022
36e83a18 4023/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4024bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4025{
4026 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4027 union child_device_config *p_child;
36e83a18 4028 int i;
5d8a7752
VS		 4029 static const short port_mapping[] = {
4030 [PORT_B] = PORT_IDPB,
4031 [PORT_C] = PORT_IDPC,
4032 [PORT_D] = PORT_IDPD,
4033 };
36e83a18 4034
3b32a35b
VS		 4035 if (port == PORT_A)
4036 return true;
4037
41aa3448 4038 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4039 return false;
4040
41aa3448
RV		 4041 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4042 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4043
5d8a7752 4044 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4045 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4046 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4047 return true;
4048 }
4049 return false;
4050}
4051
0e32b39c 4052void
f684960e
CW		 4053intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4054{
53b41837
YN		 4055 struct intel_connector *intel_connector = to_intel_connector(connector);
4056
3f43c48d 4057 intel_attach_force_audio_property(connector);
e953fd7b 4058 intel_attach_broadcast_rgb_property(connector);
55bc60db 4059 intel_dp->color_range_auto = true;
53b41837
YN		 4060
4061 if (is_edp(intel_dp)) {
4062 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4063 drm_object_attach_property(
4064 &connector->base,
53b41837 4065 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4066 DRM_MODE_SCALE_ASPECT);
4067 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4068 }
f684960e
CW		 4069}
4070
dada1a9f
ID		 4071static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4072{
4073 intel_dp->last_power_cycle = jiffies;
4074 intel_dp->last_power_on = jiffies;
4075 intel_dp->last_backlight_off = jiffies;
4076}
4077
67a54566
DV		 4078static void
4079intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4080 struct intel_dp *intel_dp,
4081 struct edp_power_seq *out)
67a54566
DV		 4082{
4083 struct drm_i915_private *dev_priv = dev->dev_private;
4084 struct edp_power_seq cur, vbt, spec, final;
4085 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4086 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 4087
4088 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4089 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4090 pp_on_reg = PCH_PP_ON_DELAYS;
4091 pp_off_reg = PCH_PP_OFF_DELAYS;
4092 pp_div_reg = PCH_PP_DIVISOR;
4093 } else {
bf13e81b
JN		 4094 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4095
4096 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4097 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4098 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4099 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4100 }
67a54566
DV		 4101
4102 /* Workaround: Need to write PP_CONTROL with the unlock key as
4103 * the very first thing. */
453c5420 4104 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4105 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4106
453c5420
JB		 4107 pp_on = I915_READ(pp_on_reg);
4108 pp_off = I915_READ(pp_off_reg);
4109 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4110
4111 /* Pull timing values out of registers */
4112 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4113 PANEL_POWER_UP_DELAY_SHIFT;
4114
4115 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4116 PANEL_LIGHT_ON_DELAY_SHIFT;
4117
4118 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4119 PANEL_LIGHT_OFF_DELAY_SHIFT;
4120
4121 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4122 PANEL_POWER_DOWN_DELAY_SHIFT;
4123
4124 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4125 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4126
4127 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4128 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4129
41aa3448 4130 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4131
4132 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4133 * our hw here, which are all in 100usec. */
4134 spec.t1_t3 = 210 * 10;
4135 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4136 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4137 spec.t10 = 500 * 10;
4138 /* This one is special and actually in units of 100ms, but zero
4139 * based in the hw (so we need to add 100 ms). But the sw vbt
4140 * table multiplies it with 1000 to make it in units of 100usec,
4141 * too. */
4142 spec.t11_t12 = (510 + 100) * 10;
4143
4144 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4145 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4146
4147 /* Use the max of the register settings and vbt. If both are
4148 * unset, fall back to the spec limits. */
4149#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4150 spec.field : \
4151 max(cur.field, vbt.field))
4152 assign_final(t1_t3);
4153 assign_final(t8);
4154 assign_final(t9);
4155 assign_final(t10);
4156 assign_final(t11_t12);
4157#undef assign_final
4158
4159#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4160 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4161 intel_dp->backlight_on_delay = get_delay(t8);
4162 intel_dp->backlight_off_delay = get_delay(t9);
4163 intel_dp->panel_power_down_delay = get_delay(t10);
4164 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4165#undef get_delay
4166
f30d26e4
JN		 4167 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4168 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4169 intel_dp->panel_power_cycle_delay);
4170
4171 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4172 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4173
4174 if (out)
4175 *out = final;
4176}
4177
4178static void
4179intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4180 struct intel_dp *intel_dp,
4181 struct edp_power_seq *seq)
4182{
4183 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4184 u32 pp_on, pp_off, pp_div, port_sel = 0;
4185 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4186 int pp_on_reg, pp_off_reg, pp_div_reg;
4187
4188 if (HAS_PCH_SPLIT(dev)) {
4189 pp_on_reg = PCH_PP_ON_DELAYS;
4190 pp_off_reg = PCH_PP_OFF_DELAYS;
4191 pp_div_reg = PCH_PP_DIVISOR;
4192 } else {
bf13e81b
JN		 4193 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4194
4195 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4196 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4197 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4198 }
4199
b2f19d1a
PZ		 4200 /*
4201 * And finally store the new values in the power sequencer. The
4202 * backlight delays are set to 1 because we do manual waits on them. For
4203 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4204 * we'll end up waiting for the backlight off delay twice: once when we
4205 * do the manual sleep, and once when we disable the panel and wait for
4206 * the PP_STATUS bit to become zero.
4207 */
f30d26e4 4208 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4209 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4210 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4211 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4212 /* Compute the divisor for the pp clock, simply match the Bspec
4213 * formula. */
453c5420 4214 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4215 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4216 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4217
4218 /* Haswell doesn't have any port selection bits for the panel
4219 * power sequencer any more. */
bc7d38a4 4220 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 4221 if (dp_to_dig_port(intel_dp)->port == PORT_B)
4222 port_sel = PANEL_PORT_SELECT_DPB_VLV;
4223 else
4224 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 4225 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4226 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 4227 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4228 else
a24c144c 4229 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4230 }
4231
453c5420
JB		 4232 pp_on |= port_sel;
4233
4234 I915_WRITE(pp_on_reg, pp_on);
4235 I915_WRITE(pp_off_reg, pp_off);
4236 I915_WRITE(pp_div_reg, pp_div);
67a54566 4237
67a54566 4238 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4239 I915_READ(pp_on_reg),
4240 I915_READ(pp_off_reg),
4241 I915_READ(pp_div_reg));
f684960e
CW		 4242}
4243
439d7ac0
PB		 4244void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4245{
4246 struct drm_i915_private *dev_priv = dev->dev_private;
4247 struct intel_encoder *encoder;
4248 struct intel_dp *intel_dp = NULL;
4249 struct intel_crtc_config *config = NULL;
4250 struct intel_crtc *intel_crtc = NULL;
4251 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4252 u32 reg, val;
4253 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4254
4255 if (refresh_rate <= 0) {
4256 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4257 return;
4258 }
4259
4260 if (intel_connector == NULL) {
4261 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4262 return;
4263 }
4264
4265 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4266 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4267 return;
4268 }
4269
4270 encoder = intel_attached_encoder(&intel_connector->base);
4271 intel_dp = enc_to_intel_dp(&encoder->base);
4272 intel_crtc = encoder->new_crtc;
4273
4274 if (!intel_crtc) {
4275 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4276 return;
4277 }
4278
4279 config = &intel_crtc->config;
4280
4281 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4282 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4283 return;
4284 }
4285
4286 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4287 index = DRRS_LOW_RR;
4288
4289 if (index == intel_dp->drrs_state.refresh_rate_type) {
4290 DRM_DEBUG_KMS(
4291 "DRRS requested for previously set RR...ignoring\n");
4292 return;
4293 }
4294
4295 if (!intel_crtc->active) {
4296 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4297 return;
4298 }
4299
4300 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4301 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4302 val = I915_READ(reg);
4303 if (index > DRRS_HIGH_RR) {
4304 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4305 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
4306 } else {
4307 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4308 }
4309 I915_WRITE(reg, val);
4310 }
4311
4312 /*
4313 * mutex taken to ensure that there is no race between differnt
4314 * drrs calls trying to update refresh rate. This scenario may occur
4315 * in future when idleness detection based DRRS in kernel and
4316 * possible calls from user space to set differnt RR are made.
4317 */
4318
4319 mutex_lock(&intel_dp->drrs_state.mutex);
4320
4321 intel_dp->drrs_state.refresh_rate_type = index;
4322
4323 mutex_unlock(&intel_dp->drrs_state.mutex);
4324
4325 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4326}
4327
4f9db5b5
PB		 4328static struct drm_display_mode *
4329intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4330 struct intel_connector *intel_connector,
4331 struct drm_display_mode *fixed_mode)
4332{
4333 struct drm_connector *connector = &intel_connector->base;
4334 struct intel_dp *intel_dp = &intel_dig_port->dp;
4335 struct drm_device *dev = intel_dig_port->base.base.dev;
4336 struct drm_i915_private *dev_priv = dev->dev_private;
4337 struct drm_display_mode *downclock_mode = NULL;
4338
4339 if (INTEL_INFO(dev)->gen <= 6) {
4340 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4341 return NULL;
4342 }
4343
4344 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4345 DRM_INFO("VBT doesn't support DRRS\n");
4346 return NULL;
4347 }
4348
4349 downclock_mode = intel_find_panel_downclock
4350 (dev, fixed_mode, connector);
4351
4352 if (!downclock_mode) {
4353 DRM_INFO("DRRS not supported\n");
4354 return NULL;
4355 }
4356
439d7ac0
PB		 4357 dev_priv->drrs.connector = intel_connector;
4358
4359 mutex_init(&intel_dp->drrs_state.mutex);
4360
4f9db5b5
PB		 4361 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4362
4363 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4364 DRM_INFO("seamless DRRS supported for eDP panel.\n");
4365 return downclock_mode;
4366}
4367
ed92f0b2 4368static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4369 struct intel_connector *intel_connector,
4370 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4371{
4372 struct drm_connector *connector = &intel_connector->base;
4373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4374 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4375 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4376 struct drm_i915_private *dev_priv = dev->dev_private;
4377 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4378 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4379 bool has_dpcd;
4380 struct drm_display_mode *scan;
4381 struct edid *edid;
4382
4f9db5b5
PB		 4383 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4384
ed92f0b2
PZ		 4385 if (!is_edp(intel_dp))
4386 return true;
4387
63635217
PZ		 4388 /* The VDD bit needs a power domain reference, so if the bit is already
4389 * enabled when we boot, grab this reference. */
4390 if (edp_have_panel_vdd(intel_dp)) {
4391 enum intel_display_power_domain power_domain;
4392 power_domain = intel_display_port_power_domain(intel_encoder);
4393 intel_display_power_get(dev_priv, power_domain);
4394 }
4395
ed92f0b2 4396 /* Cache DPCD and EDID for edp. */
24f3e092 4397 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4398 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 4399 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4400
4401 if (has_dpcd) {
4402 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4403 dev_priv->no_aux_handshake =
4404 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4405 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4406 } else {
4407 /* if this fails, presume the device is a ghost */
4408 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4409 return false;
4410 }
4411
4412 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 4413 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 4414
060c8778 4415 mutex_lock(&dev->mode_config.mutex);
0b99836f 4416 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4417 if (edid) {
4418 if (drm_add_edid_modes(connector, edid)) {
4419 drm_mode_connector_update_edid_property(connector,
4420 edid);
4421 drm_edid_to_eld(connector, edid);
4422 } else {
4423 kfree(edid);
4424 edid = ERR_PTR(-EINVAL);
4425 }
4426 } else {
4427 edid = ERR_PTR(-ENOENT);
4428 }
4429 intel_connector->edid = edid;
4430
4431 /* prefer fixed mode from EDID if available */
4432 list_for_each_entry(scan, &connector->probed_modes, head) {
4433 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4434 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4435 downclock_mode = intel_dp_drrs_init(
4436 intel_dig_port,
4437 intel_connector, fixed_mode);
ed92f0b2
PZ		 4438 break;
4439 }
4440 }
4441
4442 /* fallback to VBT if available for eDP */
4443 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4444 fixed_mode = drm_mode_duplicate(dev,
4445 dev_priv->vbt.lfp_lvds_vbt_mode);
4446 if (fixed_mode)
4447 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4448 }
060c8778 4449 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4450
4f9db5b5 4451 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
ed92f0b2
PZ		 4452 intel_panel_setup_backlight(connector);
4453
4454 return true;
4455}
4456
16c25533 4457bool
f0fec3f2
PZ		 4458intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4459 struct intel_connector *intel_connector)
a4fc5ed6 4460{
f0fec3f2
PZ		 4461 struct drm_connector *connector = &intel_connector->base;
4462 struct intel_dp *intel_dp = &intel_dig_port->dp;
4463 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4464 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4465 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4466 enum port port = intel_dig_port->port;
0095e6dc 4467 struct edp_power_seq power_seq = { 0 };
0b99836f 4468 int type;
a4fc5ed6 4469
ec5b01dd
DL		 4470 /* intel_dp vfuncs */
4471 if (IS_VALLEYVIEW(dev))
4472 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4473 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4474 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4475 else if (HAS_PCH_SPLIT(dev))
4476 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4477 else
4478 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4479
153b1100
DL		 4480 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4481
0767935e
DV		 4482 /* Preserve the current hw state. */
4483 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4484 intel_dp->attached_connector = intel_connector;
3d3dc149 4485
3b32a35b 4486 if (intel_dp_is_edp(dev, port))
b329530c 4487 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4488 else
4489 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4490
f7d24902
ID		 4491 /*
4492 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4493 * for DP the encoder type can be set by the caller to
4494 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4495 */
4496 if (type == DRM_MODE_CONNECTOR_eDP)
4497 intel_encoder->type = INTEL_OUTPUT_EDP;
4498
e7281eab
ID		 4499 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4500 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4501 port_name(port));
4502
b329530c 4503 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4504 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4505
a4fc5ed6
KP		 4506 connector->interlace_allowed = true;
4507 connector->doublescan_allowed = 0;
4508
f0fec3f2 4509 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4510 edp_panel_vdd_work);
a4fc5ed6 4511
df0e9248 4512 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 4513 drm_connector_register(connector);
a4fc5ed6 4514
affa9354 4515 if (HAS_DDI(dev))
bcbc889b
PZ		 4516 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4517 else
4518 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 4519 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 4520
0b99836f 4521 /* Set up the hotplug pin. */
ab9d7c30
PZ		 4522 switch (port) {
4523 case PORT_A:
1d843f9d 4524 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 4525 break;
4526 case PORT_B:
1d843f9d 4527 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 4528 break;
4529 case PORT_C:
1d843f9d 4530 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 4531 break;
4532 case PORT_D:
1d843f9d 4533 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 4534 break;
4535 default:
ad1c0b19 4536 BUG();
5eb08b69
ZW		 4537 }
4538
dada1a9f
ID		 4539 if (is_edp(intel_dp)) {
4540 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 4541 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 4542 }
0095e6dc 4543
9d1a1031 4544 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 4545
0e32b39c
DA		 4546 /* init MST on ports that can support it */
4547 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4548 if (port == PORT_B || port == PORT_C || port == PORT_D) {
4549 intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
4550 }
4551 }
4552
0095e6dc 4553 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 4554 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 4555 if (is_edp(intel_dp)) {
4556 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4557 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4558 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4559 drm_modeset_unlock(&dev->mode_config.connection_mutex);
15b1d171 4560 }
34ea3d38 4561 drm_connector_unregister(connector);
b2f246a8 4562 drm_connector_cleanup(connector);
16c25533 4563 return false;
b2f246a8 4564 }
32f9d658 4565
f684960e
CW		 4566 intel_dp_add_properties(intel_dp, connector);
4567
a4fc5ed6
KP		 4568 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4569 * 0xd. Failure to do so will result in spurious interrupts being
4570 * generated on the port when a cable is not attached.
4571 */
4572 if (IS_G4X(dev) && !IS_GM45(dev)) {
4573 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4574 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4575 }
16c25533
PZ		 4576
4577 return true;
a4fc5ed6 4578}
f0fec3f2
PZ		 4579
4580void
4581intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4582{
13cf5504 4583 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 4584 struct intel_digital_port *intel_dig_port;
4585 struct intel_encoder *intel_encoder;
4586 struct drm_encoder *encoder;
4587 struct intel_connector *intel_connector;
4588
b14c5679 4589 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 4590 if (!intel_dig_port)
4591 return;
4592
b14c5679 4593 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 4594 if (!intel_connector) {
4595 kfree(intel_dig_port);
4596 return;
4597 }
4598
4599 intel_encoder = &intel_dig_port->base;
4600 encoder = &intel_encoder->base;
4601
4602 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4603 DRM_MODE_ENCODER_TMDS);
4604
5bfe2ac0 4605 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 4606 intel_encoder->disable = intel_disable_dp;
00c09d70 4607 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4608 intel_encoder->get_config = intel_dp_get_config;
e4a1d846 4609 if (IS_CHERRYVIEW(dev)) {
9197c88b 4610 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 4611 intel_encoder->pre_enable = chv_pre_enable_dp;
4612 intel_encoder->enable = vlv_enable_dp;
580d3811 4613 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 4614 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4615 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4616 intel_encoder->pre_enable = vlv_pre_enable_dp;
4617 intel_encoder->enable = vlv_enable_dp;
49277c31 4618 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4619 } else {
ecff4f3b
JN		 4620 intel_encoder->pre_enable = g4x_pre_enable_dp;
4621 intel_encoder->enable = g4x_enable_dp;
49277c31 4622 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4623 }
f0fec3f2 4624
174edf1f 4625 intel_dig_port->port = port;
f0fec3f2
PZ		 4626 intel_dig_port->dp.output_reg = output_reg;
4627
00c09d70 4628 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 4629 if (IS_CHERRYVIEW(dev)) {
4630 if (port == PORT_D)
4631 intel_encoder->crtc_mask = 1 << 2;
4632 else
4633 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4634 } else {
4635 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4636 }
bc079e8b 4637 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4638 intel_encoder->hot_plug = intel_dp_hot_plug;
4639
13cf5504
DA		 4640 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4641 dev_priv->hpd_irq_port[port] = intel_dig_port;
4642
15b1d171
PZ		 4643 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4644 drm_encoder_cleanup(encoder);
4645 kfree(intel_dig_port);
b2f246a8 4646 kfree(intel_connector);
15b1d171 4647 }
f0fec3f2 4648}
0e32b39c
DA		 4649
4650void intel_dp_mst_suspend(struct drm_device *dev)
4651{
4652 struct drm_i915_private *dev_priv = dev->dev_private;
4653 int i;
4654
4655 /* disable MST */
4656 for (i = 0; i < I915_MAX_PORTS; i++) {
4657 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4658 if (!intel_dig_port)
4659 continue;
4660
4661 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4662 if (!intel_dig_port->dp.can_mst)
4663 continue;
4664 if (intel_dig_port->dp.is_mst)
4665 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
4666 }
4667 }
4668}
4669
4670void intel_dp_mst_resume(struct drm_device *dev)
4671{
4672 struct drm_i915_private *dev_priv = dev->dev_private;
4673 int i;
4674
4675 for (i = 0; i < I915_MAX_PORTS; i++) {
4676 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4677 if (!intel_dig_port)
4678 continue;
4679 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4680 int ret;
4681
4682 if (!intel_dig_port->dp.can_mst)
4683 continue;
4684
4685 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
4686 if (ret != 0) {
4687 intel_dp_check_mst_status(&intel_dig_port->dp);
4688 }
4689 }
4690 }
4691}
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