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drm/i915/dp/mst: Fix MST logic in intel_dp_long_pulse()
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
559be30c
TP		 44/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
9dd4ffdf 50struct dp_link_dpll {
840b32b7 51 int clock;
9dd4ffdf
CML		 52 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
840b32b7 56 { 162000,
9dd4ffdf 57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
840b32b7 58 { 270000,
9dd4ffdf
CML		 59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
840b32b7 63 { 162000,
9dd4ffdf 64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
840b32b7 65 { 270000,
9dd4ffdf
CML		 66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
65ce4bf5 69static const struct dp_link_dpll vlv_dpll[] = {
840b32b7 70 { 162000,
58f6e632 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
840b32b7 72 { 270000,
65ce4bf5
CML		 73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
ef9348c8
CML		 76/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
840b32b7 86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
ef9348c8 87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
840b32b7 88 { 270000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8 89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
840b32b7 90 { 540000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8
CML		 91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
637a9c63 93
64987fc5
SJ		 94static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
637a9c63 96static const int skl_rates[] = { 162000, 216000, 270000,
f4896f15
VS		 97 324000, 432000, 540000 };
98static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 99
cfcb0fc9
JB		 100/**
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
103 *
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
106 */
107static bool is_edp(struct intel_dp *intel_dp)
108{
da63a9f2
PZ		 109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
110
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 112}
113
68b4d824 114static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 115{
68b4d824
ID		 116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
117
118 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 119}
120
df0e9248
CW		 121static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
122{
fa90ecef 123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 124}
125
ea5b213a 126static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 127static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 128static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 129static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 130static void vlv_steal_power_sequencer(struct drm_device *dev,
131 enum pipe pipe);
f21a2198 132static void intel_dp_unset_edid(struct intel_dp *intel_dp);
a4fc5ed6 133
e0fce78f
VS		 134static unsigned int intel_dp_unused_lane_mask(int lane_count)
135{
136 return ~((1 << lane_count) - 1) & 0xf;
137}
138
ed4e9c1d
VS		 139static int
140intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 141{
7183dc29 142 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 143
144 switch (max_link_bw) {
145 case DP_LINK_BW_1_62:
146 case DP_LINK_BW_2_7:
1db10e28 147 case DP_LINK_BW_5_4:
d4eead50 148 break;
a4fc5ed6 149 default:
d4eead50
ID		 150 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
151 max_link_bw);
a4fc5ed6
KP		 152 max_link_bw = DP_LINK_BW_1_62;
153 break;
154 }
155 return max_link_bw;
156}
157
eeb6324d
PZ		 158static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
159{
160 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
eeb6324d
PZ		 161 u8 source_max, sink_max;
162
ccb1a831 163 source_max = intel_dig_port->max_lanes;
eeb6324d
PZ		 164 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
165
166 return min(source_max, sink_max);
167}
168
cd9dde44
AJ		 169/*
170 * The units on the numbers in the next two are... bizarre. Examples will
171 * make it clearer; this one parallels an example in the eDP spec.
172 *
173 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
174 *
175 * 270000 * 1 * 8 / 10 == 216000
176 *
177 * The actual data capacity of that configuration is 2.16Gbit/s, so the
178 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
179 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
180 * 119000. At 18bpp that's 2142000 kilobits per second.
181 *
182 * Thus the strange-looking division by 10 in intel_dp_link_required, to
183 * get the result in decakilobits instead of kilobits.
184 */
185
a4fc5ed6 186static int
c898261c 187intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 188{
cd9dde44 189 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 190}
191
fe27d53e
DA		 192static int
193intel_dp_max_data_rate(int max_link_clock, int max_lanes)
194{
195 return (max_link_clock * max_lanes * 8) / 10;
196}
197
c19de8eb 198static enum drm_mode_status
a4fc5ed6
KP		 199intel_dp_mode_valid(struct drm_connector *connector,
200 struct drm_display_mode *mode)
201{
df0e9248 202 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 203 struct intel_connector *intel_connector = to_intel_connector(connector);
204 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 205 int target_clock = mode->clock;
206 int max_rate, mode_rate, max_lanes, max_link_clock;
799487f5 207 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
a4fc5ed6 208
dd06f90e
JN		 209 if (is_edp(intel_dp) && fixed_mode) {
210 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 211 return MODE_PANEL;
212
dd06f90e 213 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 214 return MODE_PANEL;
03afc4a2
DV		 215
216 target_clock = fixed_mode->clock;
7de56f43
ZY		 217 }
218
50fec21a 219 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 220 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 221
222 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
223 mode_rate = intel_dp_link_required(target_clock, 18);
224
799487f5 225 if (mode_rate > max_rate || target_clock > max_dotclk)
c4867936 226 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 227
228 if (mode->clock < 10000)
229 return MODE_CLOCK_LOW;
230
0af78a2b
DV		 231 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
232 return MODE_H_ILLEGAL;
233
a4fc5ed6
KP		 234 return MODE_OK;
235}
236
a4f1289e 237uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 238{
239 int i;
240 uint32_t v = 0;
241
242 if (src_bytes > 4)
243 src_bytes = 4;
244 for (i = 0; i < src_bytes; i++)
245 v |= ((uint32_t) src[i]) << ((3-i) * 8);
246 return v;
247}
248
c2af70e2 249static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 250{
251 int i;
252 if (dst_bytes > 4)
253 dst_bytes = 4;
254 for (i = 0; i < dst_bytes; i++)
255 dst[i] = src >> ((3-i) * 8);
256}
257
bf13e81b
JN		 258static void
259intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 260 struct intel_dp *intel_dp);
bf13e81b
JN		 261static void
262intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 263 struct intel_dp *intel_dp);
bf13e81b 264
773538e8
VS		 265static void pps_lock(struct intel_dp *intel_dp)
266{
267 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
268 struct intel_encoder *encoder = &intel_dig_port->base;
269 struct drm_device *dev = encoder->base.dev;
270 struct drm_i915_private *dev_priv = dev->dev_private;
271 enum intel_display_power_domain power_domain;
272
273 /*
274 * See vlv_power_sequencer_reset() why we need
275 * a power domain reference here.
276 */
25f78f58 277 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 278 intel_display_power_get(dev_priv, power_domain);
279
280 mutex_lock(&dev_priv->pps_mutex);
281}
282
283static void pps_unlock(struct intel_dp *intel_dp)
284{
285 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
286 struct intel_encoder *encoder = &intel_dig_port->base;
287 struct drm_device *dev = encoder->base.dev;
288 struct drm_i915_private *dev_priv = dev->dev_private;
289 enum intel_display_power_domain power_domain;
290
291 mutex_unlock(&dev_priv->pps_mutex);
292
25f78f58 293 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 294 intel_display_power_put(dev_priv, power_domain);
295}
296
961a0db0
VS		 297static void
298vlv_power_sequencer_kick(struct intel_dp *intel_dp)
299{
300 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
301 struct drm_device *dev = intel_dig_port->base.base.dev;
302 struct drm_i915_private *dev_priv = dev->dev_private;
303 enum pipe pipe = intel_dp->pps_pipe;
0047eedc
VS		 304 bool pll_enabled, release_cl_override = false;
305 enum dpio_phy phy = DPIO_PHY(pipe);
306 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
961a0db0
VS		 307 uint32_t DP;
308
309 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
310 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
311 pipe_name(pipe), port_name(intel_dig_port->port)))
312 return;
313
314 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
315 pipe_name(pipe), port_name(intel_dig_port->port));
316
317 /* Preserve the BIOS-computed detected bit. This is
318 * supposed to be read-only.
319 */
320 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
321 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
322 DP |= DP_PORT_WIDTH(1);
323 DP |= DP_LINK_TRAIN_PAT_1;
324
325 if (IS_CHERRYVIEW(dev))
326 DP |= DP_PIPE_SELECT_CHV(pipe);
327 else if (pipe == PIPE_B)
328 DP |= DP_PIPEB_SELECT;
329
d288f65f
VS		 330 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
331
332 /*
333 * The DPLL for the pipe must be enabled for this to work.
334 * So enable temporarily it if it's not already enabled.
335 */
0047eedc
VS		 336 if (!pll_enabled) {
337 release_cl_override = IS_CHERRYVIEW(dev) &&
338 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
339
3f36b937
TU		 340 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
341 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
342 DRM_ERROR("Failed to force on pll for pipe %c!\n",
343 pipe_name(pipe));
344 return;
345 }
0047eedc 346 }
d288f65f 347
961a0db0
VS		 348 /*
349 * Similar magic as in intel_dp_enable_port().
350 * We _must_ do this port enable + disable trick
351 * to make this power seqeuencer lock onto the port.
352 * Otherwise even VDD force bit won't work.
353 */
354 I915_WRITE(intel_dp->output_reg, DP);
355 POSTING_READ(intel_dp->output_reg);
356
357 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
358 POSTING_READ(intel_dp->output_reg);
359
360 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
361 POSTING_READ(intel_dp->output_reg);
d288f65f 362
0047eedc 363 if (!pll_enabled) {
d288f65f 364 vlv_force_pll_off(dev, pipe);
0047eedc
VS		 365
366 if (release_cl_override)
367 chv_phy_powergate_ch(dev_priv, phy, ch, false);
368 }
961a0db0
VS		 369}
370
bf13e81b
JN		 371static enum pipe
372vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
373{
374 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 375 struct drm_device *dev = intel_dig_port->base.base.dev;
376 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 377 struct intel_encoder *encoder;
378 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 379 enum pipe pipe;
bf13e81b 380
e39b999a 381 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 382
a8c3344e
VS		 383 /* We should never land here with regular DP ports */
384 WARN_ON(!is_edp(intel_dp));
385
a4a5d2f8
VS		 386 if (intel_dp->pps_pipe != INVALID_PIPE)
387 return intel_dp->pps_pipe;
388
389 /*
390 * We don't have power sequencer currently.
391 * Pick one that's not used by other ports.
392 */
19c8054c 393 for_each_intel_encoder(dev, encoder) {
a4a5d2f8
VS		 394 struct intel_dp *tmp;
395
396 if (encoder->type != INTEL_OUTPUT_EDP)
397 continue;
398
399 tmp = enc_to_intel_dp(&encoder->base);
400
401 if (tmp->pps_pipe != INVALID_PIPE)
402 pipes &= ~(1 << tmp->pps_pipe);
403 }
404
405 /*
406 * Didn't find one. This should not happen since there
407 * are two power sequencers and up to two eDP ports.
408 */
409 if (WARN_ON(pipes == 0))
a8c3344e
VS		 410 pipe = PIPE_A;
411 else
412 pipe = ffs(pipes) - 1;
a4a5d2f8 413
a8c3344e
VS		 414 vlv_steal_power_sequencer(dev, pipe);
415 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 416
417 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
418 pipe_name(intel_dp->pps_pipe),
419 port_name(intel_dig_port->port));
420
421 /* init power sequencer on this pipe and port */
36b5f425
VS		 422 intel_dp_init_panel_power_sequencer(dev, intel_dp);
423 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 424
961a0db0
VS		 425 /*
426 * Even vdd force doesn't work until we've made
427 * the power sequencer lock in on the port.
428 */
429 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 430
431 return intel_dp->pps_pipe;
432}
433
6491ab27
VS		 434typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
435 enum pipe pipe);
436
437static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
438 enum pipe pipe)
439{
440 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
441}
442
443static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
444 enum pipe pipe)
445{
446 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
447}
448
449static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
450 enum pipe pipe)
451{
452 return true;
453}
bf13e81b 454
a4a5d2f8 455static enum pipe
6491ab27
VS		 456vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
457 enum port port,
458 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 459{
460 enum pipe pipe;
bf13e81b 461
bf13e81b
JN		 462 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
463 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
464 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 465
466 if (port_sel != PANEL_PORT_SELECT_VLV(port))
467 continue;
468
6491ab27
VS		 469 if (!pipe_check(dev_priv, pipe))
470 continue;
471
a4a5d2f8 472 return pipe;
bf13e81b
JN		 473 }
474
a4a5d2f8
VS		 475 return INVALID_PIPE;
476}
477
478static void
479vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
480{
481 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
482 struct drm_device *dev = intel_dig_port->base.base.dev;
483 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 484 enum port port = intel_dig_port->port;
485
486 lockdep_assert_held(&dev_priv->pps_mutex);
487
488 /* try to find a pipe with this port selected */
6491ab27
VS		 489 /* first pick one where the panel is on */
490 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
491 vlv_pipe_has_pp_on);
492 /* didn't find one? pick one where vdd is on */
493 if (intel_dp->pps_pipe == INVALID_PIPE)
494 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
495 vlv_pipe_has_vdd_on);
496 /* didn't find one? pick one with just the correct port */
497 if (intel_dp->pps_pipe == INVALID_PIPE)
498 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
499 vlv_pipe_any);
a4a5d2f8
VS		 500
501 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
502 if (intel_dp->pps_pipe == INVALID_PIPE) {
503 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
504 port_name(port));
505 return;
bf13e81b
JN		 506 }
507
a4a5d2f8
VS		 508 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
509 port_name(port), pipe_name(intel_dp->pps_pipe));
510
36b5f425
VS		 511 intel_dp_init_panel_power_sequencer(dev, intel_dp);
512 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 513}
514
773538e8
VS		 515void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
516{
517 struct drm_device *dev = dev_priv->dev;
518 struct intel_encoder *encoder;
519
666a4537 520 if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)))
773538e8
VS		 521 return;
522
523 /*
524 * We can't grab pps_mutex here due to deadlock with power_domain
525 * mutex when power_domain functions are called while holding pps_mutex.
526 * That also means that in order to use pps_pipe the code needs to
527 * hold both a power domain reference and pps_mutex, and the power domain
528 * reference get/put must be done while _not_ holding pps_mutex.
529 * pps_{lock,unlock}() do these steps in the correct order, so one
530 * should use them always.
531 */
532
19c8054c 533 for_each_intel_encoder(dev, encoder) {
773538e8
VS		 534 struct intel_dp *intel_dp;
535
536 if (encoder->type != INTEL_OUTPUT_EDP)
537 continue;
538
539 intel_dp = enc_to_intel_dp(&encoder->base);
540 intel_dp->pps_pipe = INVALID_PIPE;
541 }
bf13e81b
JN		 542}
543
f0f59a00
VS		 544static i915_reg_t
545_pp_ctrl_reg(struct intel_dp *intel_dp)
bf13e81b
JN		 546{
547 struct drm_device *dev = intel_dp_to_dev(intel_dp);
548
b0a08bec
VK		 549 if (IS_BROXTON(dev))
550 return BXT_PP_CONTROL(0);
551 else if (HAS_PCH_SPLIT(dev))
bf13e81b
JN		 552 return PCH_PP_CONTROL;
553 else
554 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
555}
556
f0f59a00
VS		 557static i915_reg_t
558_pp_stat_reg(struct intel_dp *intel_dp)
bf13e81b
JN		 559{
560 struct drm_device *dev = intel_dp_to_dev(intel_dp);
561
b0a08bec
VK		 562 if (IS_BROXTON(dev))
563 return BXT_PP_STATUS(0);
564 else if (HAS_PCH_SPLIT(dev))
bf13e81b
JN		 565 return PCH_PP_STATUS;
566 else
567 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
568}
569
01527b31
CT		 570/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
571 This function only applicable when panel PM state is not to be tracked */
572static int edp_notify_handler(struct notifier_block *this, unsigned long code,
573 void *unused)
574{
575 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
576 edp_notifier);
577 struct drm_device *dev = intel_dp_to_dev(intel_dp);
578 struct drm_i915_private *dev_priv = dev->dev_private;
01527b31
CT		 579
580 if (!is_edp(intel_dp) || code != SYS_RESTART)
581 return 0;
582
773538e8 583 pps_lock(intel_dp);
e39b999a 584
666a4537 585 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e39b999a 586 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
f0f59a00 587 i915_reg_t pp_ctrl_reg, pp_div_reg;
649636ef 588 u32 pp_div;
e39b999a 589
01527b31
CT		 590 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
591 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
592 pp_div = I915_READ(pp_div_reg);
593 pp_div &= PP_REFERENCE_DIVIDER_MASK;
594
595 /* 0x1F write to PP_DIV_REG sets max cycle delay */
596 I915_WRITE(pp_div_reg, pp_div | 0x1F);
597 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
598 msleep(intel_dp->panel_power_cycle_delay);
599 }
600
773538e8 601 pps_unlock(intel_dp);
e39b999a 602
01527b31
CT		 603 return 0;
604}
605
4be73780 606static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 607{
30add22d 608 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 609 struct drm_i915_private *dev_priv = dev->dev_private;
610
e39b999a
VS		 611 lockdep_assert_held(&dev_priv->pps_mutex);
612
666a4537 613 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 614 intel_dp->pps_pipe == INVALID_PIPE)
615 return false;
616
bf13e81b 617 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 618}
619
4be73780 620static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 621{
30add22d 622 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 623 struct drm_i915_private *dev_priv = dev->dev_private;
624
e39b999a
VS		 625 lockdep_assert_held(&dev_priv->pps_mutex);
626
666a4537 627 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 628 intel_dp->pps_pipe == INVALID_PIPE)
629 return false;
630
773538e8 631 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 632}
633
9b984dae
KP		 634static void
635intel_dp_check_edp(struct intel_dp *intel_dp)
636{
30add22d 637 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 638 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 639
9b984dae
KP		 640 if (!is_edp(intel_dp))
641 return;
453c5420 642
4be73780 643 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 644 WARN(1, "eDP powered off while attempting aux channel communication.\n");
645 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 646 I915_READ(_pp_stat_reg(intel_dp)),
647 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 648 }
649}
650
9ee32fea
DV		 651static uint32_t
652intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
653{
654 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
655 struct drm_device *dev = intel_dig_port->base.base.dev;
656 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 657 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 658 uint32_t status;
659 bool done;
660
ef04f00d 661#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 662 if (has_aux_irq)
b18ac466 663 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 664 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 665 else
666 done = wait_for_atomic(C, 10) == 0;
667 if (!done)
668 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
669 has_aux_irq);
670#undef C
671
672 return status;
673}
674
6ffb1be7 675static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 676{
174edf1f 677 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
e7dc33f3 678 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
9ee32fea 679
a457f54b
VS		 680 if (index)
681 return 0;
682
ec5b01dd
DL		 683 /*
684 * The clock divider is based off the hrawclk, and would like to run at
a457f54b 685 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
a4fc5ed6 686 */
a457f54b 687 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 688}
689
690static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
691{
692 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 693 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd
DL		 694
695 if (index)
696 return 0;
697
a457f54b
VS		 698 /*
699 * The clock divider is based off the cdclk or PCH rawclk, and would
700 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
701 * divide by 2000 and use that
702 */
e7dc33f3 703 if (intel_dig_port->port == PORT_A)
fce18c4c 704 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
e7dc33f3
VS		 705 else
706 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 707}
708
709static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
710{
711 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 712 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd 713
a457f54b 714 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
2c55c336 715 /* Workaround for non-ULT HSW */
bc86625a
CW		 716 switch (index) {
717 case 0: return 63;
718 case 1: return 72;
719 default: return 0;
720 }
2c55c336 721 }
a457f54b
VS		 722
723 return ilk_get_aux_clock_divider(intel_dp, index);
b84a1cf8
RV		 724}
725
b6b5e383
DL		 726static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
727{
728 /*
729 * SKL doesn't need us to program the AUX clock divider (Hardware will
730 * derive the clock from CDCLK automatically). We still implement the
731 * get_aux_clock_divider vfunc to plug-in into the existing code.
732 */
733 return index ? 0 : 1;
734}
735
6ffb1be7
VS		 736static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
737 bool has_aux_irq,
738 int send_bytes,
739 uint32_t aux_clock_divider)
5ed12a19
DL		 740{
741 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
742 struct drm_device *dev = intel_dig_port->base.base.dev;
743 uint32_t precharge, timeout;
744
745 if (IS_GEN6(dev))
746 precharge = 3;
747 else
748 precharge = 5;
749
f3c6a3a7 750 if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
5ed12a19
DL		 751 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
752 else
753 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
754
755 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 756 DP_AUX_CH_CTL_DONE |
5ed12a19 757 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 758 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 759 timeout |
788d4433 760 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 761 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
762 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 763 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 764}
765
b9ca5fad
DL		 766static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
767 bool has_aux_irq,
768 int send_bytes,
769 uint32_t unused)
770{
771 return DP_AUX_CH_CTL_SEND_BUSY |
772 DP_AUX_CH_CTL_DONE |
773 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
774 DP_AUX_CH_CTL_TIME_OUT_ERROR |
775 DP_AUX_CH_CTL_TIME_OUT_1600us |
776 DP_AUX_CH_CTL_RECEIVE_ERROR |
777 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
778 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
779}
780
b84a1cf8
RV		 781static int
782intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 783 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 784 uint8_t *recv, int recv_size)
785{
786 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
787 struct drm_device *dev = intel_dig_port->base.base.dev;
788 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 789 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
bc86625a 790 uint32_t aux_clock_divider;
b84a1cf8
RV		 791 int i, ret, recv_bytes;
792 uint32_t status;
5ed12a19 793 int try, clock = 0;
4e6b788c 794 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 795 bool vdd;
796
773538e8 797 pps_lock(intel_dp);
e39b999a 798
72c3500a
VS		 799 /*
800 * We will be called with VDD already enabled for dpcd/edid/oui reads.
801 * In such cases we want to leave VDD enabled and it's up to upper layers
802 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
803 * ourselves.
804 */
1e0560e0 805 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 806
807 /* dp aux is extremely sensitive to irq latency, hence request the
808 * lowest possible wakeup latency and so prevent the cpu from going into
809 * deep sleep states.
810 */
811 pm_qos_update_request(&dev_priv->pm_qos, 0);
812
813 intel_dp_check_edp(intel_dp);
5eb08b69 814
11bee43e
JB		 815 /* Try to wait for any previous AUX channel activity */
816 for (try = 0; try < 3; try++) {
ef04f00d 817 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 818 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
819 break;
820 msleep(1);
821 }
822
823 if (try == 3) {
02196c77
MK		 824 static u32 last_status = -1;
825 const u32 status = I915_READ(ch_ctl);
826
827 if (status != last_status) {
828 WARN(1, "dp_aux_ch not started status 0x%08x\n",
829 status);
830 last_status = status;
831 }
832
9ee32fea
DV		 833 ret = -EBUSY;
834 goto out;
4f7f7b7e
CW		 835 }
836
46a5ae9f
PZ		 837 /* Only 5 data registers! */
838 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
839 ret = -E2BIG;
840 goto out;
841 }
842
ec5b01dd 843 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 844 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
845 has_aux_irq,
846 send_bytes,
847 aux_clock_divider);
5ed12a19 848
bc86625a
CW		 849 /* Must try at least 3 times according to DP spec */
850 for (try = 0; try < 5; try++) {
851 /* Load the send data into the aux channel data registers */
852 for (i = 0; i < send_bytes; i += 4)
330e20ec 853 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
a4f1289e
RV		 854 intel_dp_pack_aux(send + i,
855 send_bytes - i));
bc86625a
CW		 856
857 /* Send the command and wait for it to complete */
5ed12a19 858 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 859
860 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
861
862 /* Clear done status and any errors */
863 I915_WRITE(ch_ctl,
864 status |
865 DP_AUX_CH_CTL_DONE |
866 DP_AUX_CH_CTL_TIME_OUT_ERROR |
867 DP_AUX_CH_CTL_RECEIVE_ERROR);
868
74ebf294 869 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
bc86625a 870 continue;
74ebf294
TP		 871
872 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
873 * 400us delay required for errors and timeouts
874 * Timeout errors from the HW already meet this
875 * requirement so skip to next iteration
876 */
877 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
878 usleep_range(400, 500);
bc86625a 879 continue;
74ebf294 880 }
bc86625a 881 if (status & DP_AUX_CH_CTL_DONE)
e058c945 882 goto done;
bc86625a 883 }
a4fc5ed6
KP		 884 }
885
a4fc5ed6 886 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 887 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 888 ret = -EBUSY;
889 goto out;
a4fc5ed6
KP		 890 }
891
e058c945 892done:
a4fc5ed6
KP		 893 /* Check for timeout or receive error.
894 * Timeouts occur when the sink is not connected
895 */
a5b3da54 896 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 897 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 898 ret = -EIO;
899 goto out;
a5b3da54 900 }
1ae8c0a5
KP		 901
902 /* Timeouts occur when the device isn't connected, so they're
903 * "normal" -- don't fill the kernel log with these */
a5b3da54 904 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 905 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 906 ret = -ETIMEDOUT;
907 goto out;
a4fc5ed6
KP		 908 }
909
910 /* Unload any bytes sent back from the other side */
911 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
912 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
14e01889
RV		 913
914 /*
915 * By BSpec: "Message sizes of 0 or >20 are not allowed."
916 * We have no idea of what happened so we return -EBUSY so
917 * drm layer takes care for the necessary retries.
918 */
919 if (recv_bytes == 0 || recv_bytes > 20) {
920 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
921 recv_bytes);
922 /*
923 * FIXME: This patch was created on top of a series that
924 * organize the retries at drm level. There EBUSY should
925 * also take care for 1ms wait before retrying.
926 * That aux retries re-org is still needed and after that is
927 * merged we remove this sleep from here.
928 */
929 usleep_range(1000, 1500);
930 ret = -EBUSY;
931 goto out;
932 }
933
a4fc5ed6
KP		 934 if (recv_bytes > recv_size)
935 recv_bytes = recv_size;
0206e353 936
4f7f7b7e 937 for (i = 0; i < recv_bytes; i += 4)
330e20ec 938 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
a4f1289e 939 recv + i, recv_bytes - i);
a4fc5ed6 940
9ee32fea
DV		 941 ret = recv_bytes;
942out:
943 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
944
884f19e9
JN		 945 if (vdd)
946 edp_panel_vdd_off(intel_dp, false);
947
773538e8 948 pps_unlock(intel_dp);
e39b999a 949
9ee32fea 950 return ret;
a4fc5ed6
KP		 951}
952
a6c8aff0
JN		 953#define BARE_ADDRESS_SIZE 3
954#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 955static ssize_t
956intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 957{
9d1a1031
JN		 958 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
959 uint8_t txbuf[20], rxbuf[20];
960 size_t txsize, rxsize;
a4fc5ed6 961 int ret;
a4fc5ed6 962
d2d9cbbd
VS		 963 txbuf[0] = (msg->request << 4) |
964 ((msg->address >> 16) & 0xf);
965 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 966 txbuf[2] = msg->address & 0xff;
967 txbuf[3] = msg->size - 1;
46a5ae9f 968
9d1a1031
JN		 969 switch (msg->request & ~DP_AUX_I2C_MOT) {
970 case DP_AUX_NATIVE_WRITE:
971 case DP_AUX_I2C_WRITE:
c1e74122 972 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
a6c8aff0 973 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 974 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 975
9d1a1031
JN		 976 if (WARN_ON(txsize > 20))
977 return -E2BIG;
a4fc5ed6 978
d81a67cc
ID		 979 if (msg->buffer)
980 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
981 else
982 WARN_ON(msg->size);
a4fc5ed6 983
9d1a1031
JN		 984 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
985 if (ret > 0) {
986 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 987
a1ddefd8
JN		 988 if (ret > 1) {
989 /* Number of bytes written in a short write. */
990 ret = clamp_t(int, rxbuf[1], 0, msg->size);
991 } else {
992 /* Return payload size. */
993 ret = msg->size;
994 }
9d1a1031
JN		 995 }
996 break;
46a5ae9f 997
9d1a1031
JN		 998 case DP_AUX_NATIVE_READ:
999 case DP_AUX_I2C_READ:
a6c8aff0 1000 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 1001 rxsize = msg->size + 1;
a4fc5ed6 1002
9d1a1031
JN		 1003 if (WARN_ON(rxsize > 20))
1004 return -E2BIG;
a4fc5ed6 1005
9d1a1031
JN		 1006 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1007 if (ret > 0) {
1008 msg->reply = rxbuf[0] >> 4;
1009 /*
1010 * Assume happy day, and copy the data. The caller is
1011 * expected to check msg->reply before touching it.
1012 *
1013 * Return payload size.
1014 */
1015 ret--;
1016 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 1017 }
9d1a1031
JN		 1018 break;
1019
1020 default:
1021 ret = -EINVAL;
1022 break;
a4fc5ed6 1023 }
f51a44b9 1024
9d1a1031 1025 return ret;
a4fc5ed6
KP		 1026}
1027
f0f59a00
VS		 1028static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1029 enum port port)
da00bdcf
VS		 1030{
1031 switch (port) {
1032 case PORT_B:
1033 case PORT_C:
1034 case PORT_D:
1035 return DP_AUX_CH_CTL(port);
1036 default:
1037 MISSING_CASE(port);
1038 return DP_AUX_CH_CTL(PORT_B);
1039 }
1040}
1041
f0f59a00
VS		 1042static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1043 enum port port, int index)
330e20ec
VS		 1044{
1045 switch (port) {
1046 case PORT_B:
1047 case PORT_C:
1048 case PORT_D:
1049 return DP_AUX_CH_DATA(port, index);
1050 default:
1051 MISSING_CASE(port);
1052 return DP_AUX_CH_DATA(PORT_B, index);
1053 }
1054}
1055
f0f59a00
VS		 1056static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1057 enum port port)
da00bdcf
VS		 1058{
1059 switch (port) {
1060 case PORT_A:
1061 return DP_AUX_CH_CTL(port);
1062 case PORT_B:
1063 case PORT_C:
1064 case PORT_D:
1065 return PCH_DP_AUX_CH_CTL(port);
1066 default:
1067 MISSING_CASE(port);
1068 return DP_AUX_CH_CTL(PORT_A);
1069 }
1070}
1071
f0f59a00
VS		 1072static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1073 enum port port, int index)
330e20ec
VS		 1074{
1075 switch (port) {
1076 case PORT_A:
1077 return DP_AUX_CH_DATA(port, index);
1078 case PORT_B:
1079 case PORT_C:
1080 case PORT_D:
1081 return PCH_DP_AUX_CH_DATA(port, index);
1082 default:
1083 MISSING_CASE(port);
1084 return DP_AUX_CH_DATA(PORT_A, index);
1085 }
1086}
1087
da00bdcf
VS		 1088/*
1089 * On SKL we don't have Aux for port E so we rely
1090 * on VBT to set a proper alternate aux channel.
1091 */
1092static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1093{
1094 const struct ddi_vbt_port_info *info =
1095 &dev_priv->vbt.ddi_port_info[PORT_E];
1096
1097 switch (info->alternate_aux_channel) {
1098 case DP_AUX_A:
1099 return PORT_A;
1100 case DP_AUX_B:
1101 return PORT_B;
1102 case DP_AUX_C:
1103 return PORT_C;
1104 case DP_AUX_D:
1105 return PORT_D;
1106 default:
1107 MISSING_CASE(info->alternate_aux_channel);
1108 return PORT_A;
1109 }
1110}
1111
f0f59a00
VS		 1112static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1113 enum port port)
da00bdcf
VS		 1114{
1115 if (port == PORT_E)
1116 port = skl_porte_aux_port(dev_priv);
1117
1118 switch (port) {
1119 case PORT_A:
1120 case PORT_B:
1121 case PORT_C:
1122 case PORT_D:
1123 return DP_AUX_CH_CTL(port);
1124 default:
1125 MISSING_CASE(port);
1126 return DP_AUX_CH_CTL(PORT_A);
1127 }
1128}
1129
f0f59a00
VS		 1130static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1131 enum port port, int index)
330e20ec
VS		 1132{
1133 if (port == PORT_E)
1134 port = skl_porte_aux_port(dev_priv);
1135
1136 switch (port) {
1137 case PORT_A:
1138 case PORT_B:
1139 case PORT_C:
1140 case PORT_D:
1141 return DP_AUX_CH_DATA(port, index);
1142 default:
1143 MISSING_CASE(port);
1144 return DP_AUX_CH_DATA(PORT_A, index);
1145 }
1146}
1147
f0f59a00
VS		 1148static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1149 enum port port)
330e20ec
VS		 1150{
1151 if (INTEL_INFO(dev_priv)->gen >= 9)
1152 return skl_aux_ctl_reg(dev_priv, port);
1153 else if (HAS_PCH_SPLIT(dev_priv))
1154 return ilk_aux_ctl_reg(dev_priv, port);
1155 else
1156 return g4x_aux_ctl_reg(dev_priv, port);
1157}
1158
f0f59a00
VS		 1159static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1160 enum port port, int index)
330e20ec
VS		 1161{
1162 if (INTEL_INFO(dev_priv)->gen >= 9)
1163 return skl_aux_data_reg(dev_priv, port, index);
1164 else if (HAS_PCH_SPLIT(dev_priv))
1165 return ilk_aux_data_reg(dev_priv, port, index);
1166 else
1167 return g4x_aux_data_reg(dev_priv, port, index);
1168}
1169
1170static void intel_aux_reg_init(struct intel_dp *intel_dp)
1171{
1172 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1173 enum port port = dp_to_dig_port(intel_dp)->port;
1174 int i;
1175
1176 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1177 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1178 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1179}
1180
9d1a1031 1181static void
a121f4e5
VS		 1182intel_dp_aux_fini(struct intel_dp *intel_dp)
1183{
1184 drm_dp_aux_unregister(&intel_dp->aux);
1185 kfree(intel_dp->aux.name);
1186}
1187
1188static int
9d1a1031
JN		 1189intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1190{
33ad6626
JN		 1191 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1192 enum port port = intel_dig_port->port;
ab2c0672
DA		 1193 int ret;
1194
330e20ec 1195 intel_aux_reg_init(intel_dp);
8316f337 1196
a121f4e5
VS		 1197 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1198 if (!intel_dp->aux.name)
1199 return -ENOMEM;
1200
4d32c0d8 1201 intel_dp->aux.dev = connector->base.kdev;
9d1a1031 1202 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 1203
a121f4e5
VS		 1204 DRM_DEBUG_KMS("registering %s bus for %s\n",
1205 intel_dp->aux.name,
0b99836f 1206 connector->base.kdev->kobj.name);
8316f337 1207
4f71d0cb 1208 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 1209 if (ret < 0) {
4f71d0cb 1210 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
a121f4e5
VS		 1211 intel_dp->aux.name, ret);
1212 kfree(intel_dp->aux.name);
1213 return ret;
ab2c0672 1214 }
8a5e6aeb 1215
a121f4e5 1216 return 0;
a4fc5ed6
KP		 1217}
1218
80f65de3
ID		 1219static void
1220intel_dp_connector_unregister(struct intel_connector *intel_connector)
1221{
1222 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1223
4d32c0d8 1224 intel_dp_aux_fini(intel_dp);
80f65de3
ID		 1225 intel_connector_unregister(intel_connector);
1226}
1227
fc0f8e25 1228static int
12f6a2e2 1229intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1230{
94ca719e
VS		 1231 if (intel_dp->num_sink_rates) {
1232 *sink_rates = intel_dp->sink_rates;
1233 return intel_dp->num_sink_rates;
fc0f8e25 1234 }
12f6a2e2
VS		 1235
1236 *sink_rates = default_rates;
1237
1238 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1239}
1240
e588fa18 1241bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
ed63baaf 1242{
e588fa18
ACO		 1243 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1244 struct drm_device *dev = dig_port->base.base.dev;
1245
ed63baaf 1246 /* WaDisableHBR2:skl */
e87a005d 1247 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
ed63baaf
TS		 1248 return false;
1249
1250 if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1251 (INTEL_INFO(dev)->gen >= 9))
1252 return true;
1253 else
1254 return false;
1255}
1256
a8f3ef61 1257static int
e588fa18 1258intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
a8f3ef61 1259{
e588fa18
ACO		 1260 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1261 struct drm_device *dev = dig_port->base.base.dev;
af7080f5
TS		 1262 int size;
1263
64987fc5
SJ		 1264 if (IS_BROXTON(dev)) {
1265 *source_rates = bxt_rates;
af7080f5 1266 size = ARRAY_SIZE(bxt_rates);
ef11bdb3 1267 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
637a9c63 1268 *source_rates = skl_rates;
af7080f5
TS		 1269 size = ARRAY_SIZE(skl_rates);
1270 } else {
1271 *source_rates = default_rates;
1272 size = ARRAY_SIZE(default_rates);
a8f3ef61 1273 }
636280ba 1274
ed63baaf 1275 /* This depends on the fact that 5.4 is last value in the array */
e588fa18 1276 if (!intel_dp_source_supports_hbr2(intel_dp))
af7080f5 1277 size--;
636280ba 1278
af7080f5 1279 return size;
a8f3ef61
SJ		 1280}
1281
c6bb3538
DV		 1282static void
1283intel_dp_set_clock(struct intel_encoder *encoder,
840b32b7 1284 struct intel_crtc_state *pipe_config)
c6bb3538
DV		 1285{
1286 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1287 const struct dp_link_dpll *divisor = NULL;
1288 int i, count = 0;
c6bb3538
DV		 1289
1290 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1291 divisor = gen4_dpll;
1292 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1293 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1294 divisor = pch_dpll;
1295 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1296 } else if (IS_CHERRYVIEW(dev)) {
1297 divisor = chv_dpll;
1298 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1299 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1300 divisor = vlv_dpll;
1301 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1302 }
9dd4ffdf
CML		 1303
1304 if (divisor && count) {
1305 for (i = 0; i < count; i++) {
840b32b7 1306 if (pipe_config->port_clock == divisor[i].clock) {
9dd4ffdf
CML		 1307 pipe_config->dpll = divisor[i].dpll;
1308 pipe_config->clock_set = true;
1309 break;
1310 }
1311 }
c6bb3538
DV		 1312 }
1313}
1314
2ecae76a
VS		 1315static int intersect_rates(const int *source_rates, int source_len,
1316 const int *sink_rates, int sink_len,
94ca719e 1317 int *common_rates)
a8f3ef61
SJ		 1318{
1319 int i = 0, j = 0, k = 0;
1320
a8f3ef61
SJ		 1321 while (i < source_len && j < sink_len) {
1322 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1323 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1324 return k;
94ca719e 1325 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1326 ++k;
1327 ++i;
1328 ++j;
1329 } else if (source_rates[i] < sink_rates[j]) {
1330 ++i;
1331 } else {
1332 ++j;
1333 }
1334 }
1335 return k;
1336}
1337
94ca719e
VS		 1338static int intel_dp_common_rates(struct intel_dp *intel_dp,
1339 int *common_rates)
2ecae76a 1340{
2ecae76a
VS		 1341 const int *source_rates, *sink_rates;
1342 int source_len, sink_len;
1343
1344 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
e588fa18 1345 source_len = intel_dp_source_rates(intel_dp, &source_rates);
2ecae76a
VS		 1346
1347 return intersect_rates(source_rates, source_len,
1348 sink_rates, sink_len,
94ca719e 1349 common_rates);
2ecae76a
VS		 1350}
1351
0336400e
VS		 1352static void snprintf_int_array(char *str, size_t len,
1353 const int *array, int nelem)
1354{
1355 int i;
1356
1357 str[0] = '\0';
1358
1359 for (i = 0; i < nelem; i++) {
b2f505be 1360 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
0336400e
VS		 1361 if (r >= len)
1362 return;
1363 str += r;
1364 len -= r;
1365 }
1366}
1367
1368static void intel_dp_print_rates(struct intel_dp *intel_dp)
1369{
0336400e 1370 const int *source_rates, *sink_rates;
94ca719e
VS		 1371 int source_len, sink_len, common_len;
1372 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1373 char str[128]; /* FIXME: too big for stack? */
1374
1375 if ((drm_debug & DRM_UT_KMS) == 0)
1376 return;
1377
e588fa18 1378 source_len = intel_dp_source_rates(intel_dp, &source_rates);
0336400e
VS		 1379 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1380 DRM_DEBUG_KMS("source rates: %s\n", str);
1381
1382 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1383 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1384 DRM_DEBUG_KMS("sink rates: %s\n", str);
1385
94ca719e
VS		 1386 common_len = intel_dp_common_rates(intel_dp, common_rates);
1387 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1388 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1389}
1390
f4896f15 1391static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1392{
1393 int i = 0;
1394
1395 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1396 if (find == rates[i])
1397 break;
1398
1399 return i;
1400}
1401
50fec21a
VS		 1402int
1403intel_dp_max_link_rate(struct intel_dp *intel_dp)
1404{
1405 int rates[DP_MAX_SUPPORTED_RATES] = {};
1406 int len;
1407
94ca719e 1408 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1409 if (WARN_ON(len <= 0))
1410 return 162000;
1411
1412 return rates[rate_to_index(0, rates) - 1];
1413}
1414
ed4e9c1d
VS		 1415int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1416{
94ca719e 1417 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1418}
1419
94223d04
ACO		 1420void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1421 uint8_t *link_bw, uint8_t *rate_select)
04a60f9f
VS		 1422{
1423 if (intel_dp->num_sink_rates) {
1424 *link_bw = 0;
1425 *rate_select =
1426 intel_dp_rate_select(intel_dp, port_clock);
1427 } else {
1428 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1429 *rate_select = 0;
1430 }
1431}
1432
00c09d70 1433bool
5bfe2ac0 1434intel_dp_compute_config(struct intel_encoder *encoder,
5cec258b 1435 struct intel_crtc_state *pipe_config)
a4fc5ed6 1436{
5bfe2ac0 1437 struct drm_device *dev = encoder->base.dev;
36008365 1438 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 1439 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1440 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1441 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1442 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1443 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1444 int lane_count, clock;
56071a20 1445 int min_lane_count = 1;
eeb6324d 1446 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1447 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1448 int min_clock = 0;
a8f3ef61 1449 int max_clock;
083f9560 1450 int bpp, mode_rate;
ff9a6750 1451 int link_avail, link_clock;
94ca719e
VS		 1452 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1453 int common_len;
04a60f9f 1454 uint8_t link_bw, rate_select;
a8f3ef61 1455
94ca719e 1456 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1457
1458 /* No common link rates between source and sink */
94ca719e 1459 WARN_ON(common_len <= 0);
a8f3ef61 1460
94ca719e 1461 max_clock = common_len - 1;
a4fc5ed6 1462
bc7d38a4 1463 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1464 pipe_config->has_pch_encoder = true;
1465
03afc4a2 1466 pipe_config->has_dp_encoder = true;
f769cd24 1467 pipe_config->has_drrs = false;
9fcb1704 1468 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
a4fc5ed6 1469
dd06f90e
JN		 1470 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1471 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1472 adjusted_mode);
a1b2278e
CK		 1473
1474 if (INTEL_INFO(dev)->gen >= 9) {
1475 int ret;
e435d6e5 1476 ret = skl_update_scaler_crtc(pipe_config);
a1b2278e
CK		 1477 if (ret)
1478 return ret;
1479 }
1480
b5667627 1481 if (HAS_GMCH_DISPLAY(dev))
2dd24552
JB		 1482 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1483 intel_connector->panel.fitting_mode);
1484 else
b074cec8
JB		 1485 intel_pch_panel_fitting(intel_crtc, pipe_config,
1486 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1487 }
1488
cb1793ce 1489 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1490 return false;
1491
083f9560 1492 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1493 "max bw %d pixel clock %iKHz\n",
94ca719e 1494 max_lane_count, common_rates[max_clock],
241bfc38 1495 adjusted_mode->crtc_clock);
083f9560 1496
36008365
DV		 1497 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1498 * bpc in between. */
3e7ca985 1499 bpp = pipe_config->pipe_bpp;
56071a20 1500 if (is_edp(intel_dp)) {
22ce5628
TS		 1501
1502 /* Get bpp from vbt only for panels that dont have bpp in edid */
1503 if (intel_connector->base.display_info.bpc == 0 &&
6aa23e65 1504 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
56071a20 1505 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
6aa23e65
JN		 1506 dev_priv->vbt.edp.bpp);
1507 bpp = dev_priv->vbt.edp.bpp;
56071a20
JN		 1508 }
1509
344c5bbc
JN		 1510 /*
1511 * Use the maximum clock and number of lanes the eDP panel
1512 * advertizes being capable of. The panels are generally
1513 * designed to support only a single clock and lane
1514 * configuration, and typically these values correspond to the
1515 * native resolution of the panel.
1516 */
1517 min_lane_count = max_lane_count;
1518 min_clock = max_clock;
7984211e 1519 }
657445fe 1520
36008365 1521 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1522 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1523 bpp);
36008365 1524
c6930992 1525 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1526 for (lane_count = min_lane_count;
1527 lane_count <= max_lane_count;
1528 lane_count <<= 1) {
1529
94ca719e 1530 link_clock = common_rates[clock];
36008365
DV		 1531 link_avail = intel_dp_max_data_rate(link_clock,
1532 lane_count);
1533
1534 if (mode_rate <= link_avail) {
1535 goto found;
1536 }
1537 }
1538 }
1539 }
c4867936 1540
36008365 1541 return false;
3685a8f3 1542
36008365 1543found:
55bc60db
VS		 1544 if (intel_dp->color_range_auto) {
1545 /*
1546 * See:
1547 * CEA-861-E - 5.1 Default Encoding Parameters
1548 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1549 */
0f2a2a75
VS		 1550 pipe_config->limited_color_range =
1551 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1552 } else {
1553 pipe_config->limited_color_range =
1554 intel_dp->limited_color_range;
55bc60db
VS		 1555 }
1556
90a6b7b0 1557 pipe_config->lane_count = lane_count;
a8f3ef61 1558
657445fe 1559 pipe_config->pipe_bpp = bpp;
94ca719e 1560 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1561
04a60f9f
VS		 1562 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1563 &link_bw, &rate_select);
1564
1565 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1566 link_bw, rate_select, pipe_config->lane_count,
ff9a6750 1567 pipe_config->port_clock, bpp);
36008365
DV		 1568 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1569 mode_rate, link_avail);
a4fc5ed6 1570
03afc4a2 1571 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1572 adjusted_mode->crtc_clock,
1573 pipe_config->port_clock,
03afc4a2 1574 &pipe_config->dp_m_n);
9d1a455b 1575
439d7ac0 1576 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1577 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1578 pipe_config->has_drrs = true;
439d7ac0
PB		 1579 intel_link_compute_m_n(bpp, lane_count,
1580 intel_connector->panel.downclock_mode->clock,
1581 pipe_config->port_clock,
1582 &pipe_config->dp_m2_n2);
1583 }
1584
a3c988ea 1585 if (!HAS_DDI(dev))
840b32b7 1586 intel_dp_set_clock(encoder, pipe_config);
c6bb3538 1587
03afc4a2 1588 return true;
a4fc5ed6
KP		 1589}
1590
901c2daf
VS		 1591void intel_dp_set_link_params(struct intel_dp *intel_dp,
1592 const struct intel_crtc_state *pipe_config)
1593{
1594 intel_dp->link_rate = pipe_config->port_clock;
1595 intel_dp->lane_count = pipe_config->lane_count;
1596}
1597
8ac33ed3 1598static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1599{
b934223d 1600 struct drm_device *dev = encoder->base.dev;
417e822d 1601 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1602 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1603 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1604 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
7c5f93b0 1605 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
a4fc5ed6 1606
901c2daf
VS		 1607 intel_dp_set_link_params(intel_dp, crtc->config);
1608
417e822d 1609 /*
1a2eb460 1610 * There are four kinds of DP registers:
417e822d
KP		 1611 *
1612 * IBX PCH
1a2eb460
KP		 1613 * SNB CPU
1614 * IVB CPU
417e822d
KP		 1615 * CPT PCH
1616 *
1617 * IBX PCH and CPU are the same for almost everything,
1618 * except that the CPU DP PLL is configured in this
1619 * register
1620 *
1621 * CPT PCH is quite different, having many bits moved
1622 * to the TRANS_DP_CTL register instead. That
1623 * configuration happens (oddly) in ironlake_pch_enable
1624 */
9c9e7927 1625
417e822d
KP		 1626 /* Preserve the BIOS-computed detected bit. This is
1627 * supposed to be read-only.
1628 */
1629 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1630
417e822d 1631 /* Handle DP bits in common between all three register formats */
417e822d 1632 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
90a6b7b0 1633 intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
a4fc5ed6 1634
417e822d 1635 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1636
39e5fa88 1637 if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1638 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1639 intel_dp->DP |= DP_SYNC_HS_HIGH;
1640 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1641 intel_dp->DP |= DP_SYNC_VS_HIGH;
1642 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1643
6aba5b6c 1644 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1645 intel_dp->DP |= DP_ENHANCED_FRAMING;
1646
7c62a164 1647 intel_dp->DP |= crtc->pipe << 29;
39e5fa88 1648 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
e3ef4479
VS		 1649 u32 trans_dp;
1650
39e5fa88 1651 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3ef4479
VS		 1652
1653 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1654 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1655 trans_dp |= TRANS_DP_ENH_FRAMING;
1656 else
1657 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1658 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
39e5fa88 1659 } else {
0f2a2a75 1660 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
666a4537 1661 !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
0f2a2a75 1662 intel_dp->DP |= DP_COLOR_RANGE_16_235;
417e822d
KP		 1663
1664 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1665 intel_dp->DP |= DP_SYNC_HS_HIGH;
1666 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1667 intel_dp->DP |= DP_SYNC_VS_HIGH;
1668 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1669
6aba5b6c 1670 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1671 intel_dp->DP |= DP_ENHANCED_FRAMING;
1672
39e5fa88 1673 if (IS_CHERRYVIEW(dev))
44f37d1f 1674 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
39e5fa88
VS		 1675 else if (crtc->pipe == PIPE_B)
1676 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 1677 }
a4fc5ed6
KP		 1678}
1679
ffd6749d
PZ		 1680#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1681#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1682
1a5ef5b7
PZ		 1683#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1684#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1685
ffd6749d
PZ		 1686#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1687#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1688
4be73780 1689static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1690 u32 mask,
1691 u32 value)
bd943159 1692{
30add22d 1693 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1694 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 1695 i915_reg_t pp_stat_reg, pp_ctrl_reg;
453c5420 1696
e39b999a
VS		 1697 lockdep_assert_held(&dev_priv->pps_mutex);
1698
bf13e81b
JN		 1699 pp_stat_reg = _pp_stat_reg(intel_dp);
1700 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1701
99ea7127 1702 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1703 mask, value,
1704 I915_READ(pp_stat_reg),
1705 I915_READ(pp_ctrl_reg));
32ce697c 1706
3f177625
TU		 1707 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value,
1708 5 * USEC_PER_SEC, 10 * USEC_PER_MSEC))
99ea7127 1709 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1710 I915_READ(pp_stat_reg),
1711 I915_READ(pp_ctrl_reg));
54c136d4
CW		 1712
1713 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1714}
32ce697c 1715
4be73780 1716static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1717{
1718 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1719 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1720}
1721
4be73780 1722static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1723{
1724 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1725 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1726}
1727
4be73780 1728static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127 1729{
d28d4731
AK		 1730 ktime_t panel_power_on_time;
1731 s64 panel_power_off_duration;
1732
99ea7127 1733 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c 1734
d28d4731
AK		 1735 /* take the difference of currrent time and panel power off time
1736 * and then make panel wait for t11_t12 if needed. */
1737 panel_power_on_time = ktime_get_boottime();
1738 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1739
dce56b3c
PZ		 1740 /* When we disable the VDD override bit last we have to do the manual
1741 * wait. */
d28d4731
AK		 1742 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1743 wait_remaining_ms_from_jiffies(jiffies,
1744 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
dce56b3c 1745
4be73780 1746 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1747}
1748
4be73780 1749static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1750{
1751 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1752 intel_dp->backlight_on_delay);
1753}
1754
4be73780 1755static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1756{
1757 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1758 intel_dp->backlight_off_delay);
1759}
99ea7127 1760
832dd3c1
KP		 1761/* Read the current pp_control value, unlocking the register if it
1762 * is locked
1763 */
1764
453c5420 1765static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1766{
453c5420
JB		 1767 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1768 struct drm_i915_private *dev_priv = dev->dev_private;
1769 u32 control;
832dd3c1 1770
e39b999a
VS		 1771 lockdep_assert_held(&dev_priv->pps_mutex);
1772
bf13e81b 1773 control = I915_READ(_pp_ctrl_reg(intel_dp));
b0a08bec
VK		 1774 if (!IS_BROXTON(dev)) {
1775 control &= ~PANEL_UNLOCK_MASK;
1776 control |= PANEL_UNLOCK_REGS;
1777 }
832dd3c1 1778 return control;
bd943159
KP		 1779}
1780
951468f3
VS		 1781/*
1782 * Must be paired with edp_panel_vdd_off().
1783 * Must hold pps_mutex around the whole on/off sequence.
1784 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1785 */
1e0560e0 1786static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1787{
30add22d 1788 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1789 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1790 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1791 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1792 enum intel_display_power_domain power_domain;
5d613501 1793 u32 pp;
f0f59a00 1794 i915_reg_t pp_stat_reg, pp_ctrl_reg;
adddaaf4 1795 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1796
e39b999a
VS		 1797 lockdep_assert_held(&dev_priv->pps_mutex);
1798
97af61f5 1799 if (!is_edp(intel_dp))
adddaaf4 1800 return false;
bd943159 1801
2c623c11 1802 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1803 intel_dp->want_panel_vdd = true;
99ea7127 1804
4be73780 1805 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1806 return need_to_disable;
b0665d57 1807
25f78f58 1808 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 1809 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1810
3936fcf4
VS		 1811 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1812 port_name(intel_dig_port->port));
bd943159 1813
4be73780
DV		 1814 if (!edp_have_panel_power(intel_dp))
1815 wait_panel_power_cycle(intel_dp);
99ea7127 1816
453c5420 1817 pp = ironlake_get_pp_control(intel_dp);
5d613501 1818 pp |= EDP_FORCE_VDD;
ebf33b18 1819
bf13e81b
JN		 1820 pp_stat_reg = _pp_stat_reg(intel_dp);
1821 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1822
1823 I915_WRITE(pp_ctrl_reg, pp);
1824 POSTING_READ(pp_ctrl_reg);
1825 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1826 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1827 /*
1828 * If the panel wasn't on, delay before accessing aux channel
1829 */
4be73780 1830 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1831 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1832 port_name(intel_dig_port->port));
f01eca2e 1833 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1834 }
adddaaf4
JN		 1835
1836 return need_to_disable;
1837}
1838
951468f3
VS		 1839/*
1840 * Must be paired with intel_edp_panel_vdd_off() or
1841 * intel_edp_panel_off().
1842 * Nested calls to these functions are not allowed since
1843 * we drop the lock. Caller must use some higher level
1844 * locking to prevent nested calls from other threads.
1845 */
b80d6c78 1846void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1847{
c695b6b6 1848 bool vdd;
adddaaf4 1849
c695b6b6
VS		 1850 if (!is_edp(intel_dp))
1851 return;
1852
773538e8 1853 pps_lock(intel_dp);
c695b6b6 1854 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1855 pps_unlock(intel_dp);
c695b6b6 1856
e2c719b7 1857 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1858 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1859}
1860
4be73780 1861static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1862{
30add22d 1863 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1864 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1865 struct intel_digital_port *intel_dig_port =
1866 dp_to_dig_port(intel_dp);
1867 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1868 enum intel_display_power_domain power_domain;
5d613501 1869 u32 pp;
f0f59a00 1870 i915_reg_t pp_stat_reg, pp_ctrl_reg;
5d613501 1871
e39b999a 1872 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1873
15e899a0 1874 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1875
15e899a0 1876 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1877 return;
b0665d57 1878
3936fcf4
VS		 1879 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1880 port_name(intel_dig_port->port));
bd943159 1881
be2c9196
VS		 1882 pp = ironlake_get_pp_control(intel_dp);
1883 pp &= ~EDP_FORCE_VDD;
453c5420 1884
be2c9196
VS		 1885 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1886 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1887
be2c9196
VS		 1888 I915_WRITE(pp_ctrl_reg, pp);
1889 POSTING_READ(pp_ctrl_reg);
90791a5c 1890
be2c9196
VS		 1891 /* Make sure sequencer is idle before allowing subsequent activity */
1892 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1893 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1894
be2c9196 1895 if ((pp & POWER_TARGET_ON) == 0)
d28d4731 1896 intel_dp->panel_power_off_time = ktime_get_boottime();
e9cb81a2 1897
25f78f58 1898 power_domain = intel_display_port_aux_power_domain(intel_encoder);
be2c9196 1899 intel_display_power_put(dev_priv, power_domain);
bd943159 1900}
5d613501 1901
4be73780 1902static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1903{
1904 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1905 struct intel_dp, panel_vdd_work);
bd943159 1906
773538e8 1907 pps_lock(intel_dp);
15e899a0
VS		 1908 if (!intel_dp->want_panel_vdd)
1909 edp_panel_vdd_off_sync(intel_dp);
773538e8 1910 pps_unlock(intel_dp);
bd943159
KP		 1911}
1912
aba86890
ID		 1913static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1914{
1915 unsigned long delay;
1916
1917 /*
1918 * Queue the timer to fire a long time from now (relative to the power
1919 * down delay) to keep the panel power up across a sequence of
1920 * operations.
1921 */
1922 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1923 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1924}
1925
951468f3
VS		 1926/*
1927 * Must be paired with edp_panel_vdd_on().
1928 * Must hold pps_mutex around the whole on/off sequence.
1929 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1930 */
4be73780 1931static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1932{
e39b999a
VS		 1933 struct drm_i915_private *dev_priv =
1934 intel_dp_to_dev(intel_dp)->dev_private;
1935
1936 lockdep_assert_held(&dev_priv->pps_mutex);
1937
97af61f5
KP		 1938 if (!is_edp(intel_dp))
1939 return;
5d613501 1940
e2c719b7 1941 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 1942 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 1943
bd943159
KP		 1944 intel_dp->want_panel_vdd = false;
1945
aba86890 1946 if (sync)
4be73780 1947 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1948 else
1949 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1950}
1951
9f0fb5be 1952static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1953{
30add22d 1954 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1955 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1956 u32 pp;
f0f59a00 1957 i915_reg_t pp_ctrl_reg;
9934c132 1958
9f0fb5be
VS		 1959 lockdep_assert_held(&dev_priv->pps_mutex);
1960
97af61f5 1961 if (!is_edp(intel_dp))
bd943159 1962 return;
99ea7127 1963
3936fcf4
VS		 1964 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
1965 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 1966
e7a89ace
VS		 1967 if (WARN(edp_have_panel_power(intel_dp),
1968 "eDP port %c panel power already on\n",
1969 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 1970 return;
9934c132 1971
4be73780 1972 wait_panel_power_cycle(intel_dp);
37c6c9b0 1973
bf13e81b 1974 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1975 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1976 if (IS_GEN5(dev)) {
1977 /* ILK workaround: disable reset around power sequence */
1978 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1979 I915_WRITE(pp_ctrl_reg, pp);
1980 POSTING_READ(pp_ctrl_reg);
05ce1a49 1981 }
37c6c9b0 1982
1c0ae80a 1983 pp |= POWER_TARGET_ON;
99ea7127
KP		 1984 if (!IS_GEN5(dev))
1985 pp |= PANEL_POWER_RESET;
1986
453c5420
JB		 1987 I915_WRITE(pp_ctrl_reg, pp);
1988 POSTING_READ(pp_ctrl_reg);
9934c132 1989
4be73780 1990 wait_panel_on(intel_dp);
dce56b3c 1991 intel_dp->last_power_on = jiffies;
9934c132 1992
05ce1a49
KP		 1993 if (IS_GEN5(dev)) {
1994 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1995 I915_WRITE(pp_ctrl_reg, pp);
1996 POSTING_READ(pp_ctrl_reg);
05ce1a49 1997 }
9f0fb5be 1998}
e39b999a 1999
9f0fb5be
VS		 2000void intel_edp_panel_on(struct intel_dp *intel_dp)
2001{
2002 if (!is_edp(intel_dp))
2003 return;
2004
2005 pps_lock(intel_dp);
2006 edp_panel_on(intel_dp);
773538e8 2007 pps_unlock(intel_dp);
9934c132
JB		 2008}
2009
9f0fb5be
VS		 2010
2011static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 2012{
4e6e1a54
ID		 2013 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2014 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 2015 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 2016 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 2017 enum intel_display_power_domain power_domain;
99ea7127 2018 u32 pp;
f0f59a00 2019 i915_reg_t pp_ctrl_reg;
9934c132 2020
9f0fb5be
VS		 2021 lockdep_assert_held(&dev_priv->pps_mutex);
2022
97af61f5
KP		 2023 if (!is_edp(intel_dp))
2024 return;
37c6c9b0 2025
3936fcf4
VS		 2026 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2027 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 2028
3936fcf4
VS		 2029 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2030 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 2031
453c5420 2032 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 2033 /* We need to switch off panel power _and_ force vdd, for otherwise some
2034 * panels get very unhappy and cease to work. */
b3064154
PJ		 2035 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2036 EDP_BLC_ENABLE);
453c5420 2037
bf13e81b 2038 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2039
849e39f5
PZ		 2040 intel_dp->want_panel_vdd = false;
2041
453c5420
JB		 2042 I915_WRITE(pp_ctrl_reg, pp);
2043 POSTING_READ(pp_ctrl_reg);
9934c132 2044
d28d4731 2045 intel_dp->panel_power_off_time = ktime_get_boottime();
4be73780 2046 wait_panel_off(intel_dp);
849e39f5
PZ		 2047
2048 /* We got a reference when we enabled the VDD. */
25f78f58 2049 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 2050 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 2051}
e39b999a 2052
9f0fb5be
VS		 2053void intel_edp_panel_off(struct intel_dp *intel_dp)
2054{
2055 if (!is_edp(intel_dp))
2056 return;
e39b999a 2057
9f0fb5be
VS		 2058 pps_lock(intel_dp);
2059 edp_panel_off(intel_dp);
773538e8 2060 pps_unlock(intel_dp);
9934c132
JB		 2061}
2062
1250d107
JN		 2063/* Enable backlight in the panel power control. */
2064static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 2065{
da63a9f2
PZ		 2066 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2067 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 2068 struct drm_i915_private *dev_priv = dev->dev_private;
2069 u32 pp;
f0f59a00 2070 i915_reg_t pp_ctrl_reg;
32f9d658 2071
01cb9ea6
JB		 2072 /*
2073 * If we enable the backlight right away following a panel power
2074 * on, we may see slight flicker as the panel syncs with the eDP
2075 * link. So delay a bit to make sure the image is solid before
2076 * allowing it to appear.
2077 */
4be73780 2078 wait_backlight_on(intel_dp);
e39b999a 2079
773538e8 2080 pps_lock(intel_dp);
e39b999a 2081
453c5420 2082 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2083 pp |= EDP_BLC_ENABLE;
453c5420 2084
bf13e81b 2085 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2086
2087 I915_WRITE(pp_ctrl_reg, pp);
2088 POSTING_READ(pp_ctrl_reg);
e39b999a 2089
773538e8 2090 pps_unlock(intel_dp);
32f9d658
ZW		 2091}
2092
1250d107
JN		 2093/* Enable backlight PWM and backlight PP control. */
2094void intel_edp_backlight_on(struct intel_dp *intel_dp)
2095{
2096 if (!is_edp(intel_dp))
2097 return;
2098
2099 DRM_DEBUG_KMS("\n");
2100
2101 intel_panel_enable_backlight(intel_dp->attached_connector);
2102 _intel_edp_backlight_on(intel_dp);
2103}
2104
2105/* Disable backlight in the panel power control. */
2106static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2107{
30add22d 2108 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 2109 struct drm_i915_private *dev_priv = dev->dev_private;
2110 u32 pp;
f0f59a00 2111 i915_reg_t pp_ctrl_reg;
32f9d658 2112
f01eca2e
KP		 2113 if (!is_edp(intel_dp))
2114 return;
2115
773538e8 2116 pps_lock(intel_dp);
e39b999a 2117
453c5420 2118 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2119 pp &= ~EDP_BLC_ENABLE;
453c5420 2120
bf13e81b 2121 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2122
2123 I915_WRITE(pp_ctrl_reg, pp);
2124 POSTING_READ(pp_ctrl_reg);
f7d2323c 2125
773538e8 2126 pps_unlock(intel_dp);
e39b999a
VS		 2127
2128 intel_dp->last_backlight_off = jiffies;
f7d2323c 2129 edp_wait_backlight_off(intel_dp);
1250d107 2130}
f7d2323c 2131
1250d107
JN		 2132/* Disable backlight PP control and backlight PWM. */
2133void intel_edp_backlight_off(struct intel_dp *intel_dp)
2134{
2135 if (!is_edp(intel_dp))
2136 return;
2137
2138 DRM_DEBUG_KMS("\n");
f7d2323c 2139
1250d107 2140 _intel_edp_backlight_off(intel_dp);
f7d2323c 2141 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2142}
a4fc5ed6 2143
73580fb7
JN		 2144/*
2145 * Hook for controlling the panel power control backlight through the bl_power
2146 * sysfs attribute. Take care to handle multiple calls.
2147 */
2148static void intel_edp_backlight_power(struct intel_connector *connector,
2149 bool enable)
2150{
2151 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2152 bool is_enabled;
2153
773538e8 2154 pps_lock(intel_dp);
e39b999a 2155 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2156 pps_unlock(intel_dp);
73580fb7
JN		 2157
2158 if (is_enabled == enable)
2159 return;
2160
23ba9373
JN		 2161 DRM_DEBUG_KMS("panel power control backlight %s\n",
2162 enable ? "enable" : "disable");
73580fb7
JN		 2163
2164 if (enable)
2165 _intel_edp_backlight_on(intel_dp);
2166 else
2167 _intel_edp_backlight_off(intel_dp);
2168}
2169
64e1077a
VS		 2170static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2171{
2172 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2173 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2174 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2175
2176 I915_STATE_WARN(cur_state != state,
2177 "DP port %c state assertion failure (expected %s, current %s)\n",
2178 port_name(dig_port->port),
87ad3212 2179 onoff(state), onoff(cur_state));
64e1077a
VS		 2180}
2181#define assert_dp_port_disabled(d) assert_dp_port((d), false)
2182
2183static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2184{
2185 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2186
2187 I915_STATE_WARN(cur_state != state,
2188 "eDP PLL state assertion failure (expected %s, current %s)\n",
87ad3212 2189 onoff(state), onoff(cur_state));
64e1077a
VS		 2190}
2191#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2192#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2193
2bd2ad64 2194static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 2195{
da63a9f2 2196 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2197 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2198 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2199
64e1077a
VS		 2200 assert_pipe_disabled(dev_priv, crtc->pipe);
2201 assert_dp_port_disabled(intel_dp);
2202 assert_edp_pll_disabled(dev_priv);
2bd2ad64 2203
abfce949
VS		 2204 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2205 crtc->config->port_clock);
2206
2207 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2208
2209 if (crtc->config->port_clock == 162000)
2210 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2211 else
2212 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2213
2214 I915_WRITE(DP_A, intel_dp->DP);
2215 POSTING_READ(DP_A);
2216 udelay(500);
2217
6b23f3e8
VS		 2218 /*
2219 * [DevILK] Work around required when enabling DP PLL
2220 * while a pipe is enabled going to FDI:
2221 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2222 * 2. Program DP PLL enable
2223 */
2224 if (IS_GEN5(dev_priv))
2225 intel_wait_for_vblank_if_active(dev_priv->dev, !crtc->pipe);
2226
0767935e 2227 intel_dp->DP |= DP_PLL_ENABLE;
6fec7662 2228
0767935e 2229 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2230 POSTING_READ(DP_A);
2231 udelay(200);
d240f20f
JB		 2232}
2233
2bd2ad64 2234static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2235{
da63a9f2 2236 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2237 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2238 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2239
64e1077a
VS		 2240 assert_pipe_disabled(dev_priv, crtc->pipe);
2241 assert_dp_port_disabled(intel_dp);
2242 assert_edp_pll_enabled(dev_priv);
2bd2ad64 2243
abfce949
VS		 2244 DRM_DEBUG_KMS("disabling eDP PLL\n");
2245
6fec7662 2246 intel_dp->DP &= ~DP_PLL_ENABLE;
0767935e 2247
6fec7662 2248 I915_WRITE(DP_A, intel_dp->DP);
1af5fa1b 2249 POSTING_READ(DP_A);
d240f20f
JB		 2250 udelay(200);
2251}
2252
c7ad3810 2253/* If the sink supports it, try to set the power state appropriately */
c19b0669 2254void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2255{
2256 int ret, i;
2257
2258 /* Should have a valid DPCD by this point */
2259 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2260 return;
2261
2262 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2263 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2264 DP_SET_POWER_D3);
c7ad3810
JB		 2265 } else {
2266 /*
2267 * When turning on, we need to retry for 1ms to give the sink
2268 * time to wake up.
2269 */
2270 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2271 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2272 DP_SET_POWER_D0);
c7ad3810
JB		 2273 if (ret == 1)
2274 break;
2275 msleep(1);
2276 }
2277 }
f9cac721
JN		 2278
2279 if (ret != 1)
2280 DRM_DEBUG_KMS("failed to %s sink power state\n",
2281 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2282}
2283
19d8fe15
DV		 2284static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2285 enum pipe *pipe)
d240f20f 2286{
19d8fe15 2287 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2288 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 2289 struct drm_device *dev = encoder->base.dev;
2290 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 2291 enum intel_display_power_domain power_domain;
2292 u32 tmp;
6fa9a5ec 2293 bool ret;
6d129bea
ID		 2294
2295 power_domain = intel_display_port_power_domain(encoder);
6fa9a5ec 2296 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 2297 return false;
2298
6fa9a5ec
ID		 2299 ret = false;
2300
6d129bea 2301 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2302
2303 if (!(tmp & DP_PORT_EN))
6fa9a5ec 2304 goto out;
19d8fe15 2305
39e5fa88 2306 if (IS_GEN7(dev) && port == PORT_A) {
19d8fe15 2307 *pipe = PORT_TO_PIPE_CPT(tmp);
39e5fa88 2308 } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
adc289d7 2309 enum pipe p;
19d8fe15 2310
adc289d7
VS		 2311 for_each_pipe(dev_priv, p) {
2312 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2313 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2314 *pipe = p;
6fa9a5ec
ID		 2315 ret = true;
2316
2317 goto out;
19d8fe15
DV		 2318 }
2319 }
19d8fe15 2320
4a0833ec 2321 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
f0f59a00 2322 i915_mmio_reg_offset(intel_dp->output_reg));
39e5fa88
VS		 2323 } else if (IS_CHERRYVIEW(dev)) {
2324 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2325 } else {
2326 *pipe = PORT_TO_PIPE(tmp);
4a0833ec 2327 }
d240f20f 2328
6fa9a5ec
ID		 2329 ret = true;
2330
2331out:
2332 intel_display_power_put(dev_priv, power_domain);
2333
2334 return ret;
19d8fe15 2335}
d240f20f 2336
045ac3b5 2337static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2338 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2339{
2340 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2341 u32 tmp, flags = 0;
63000ef6
XZ		 2342 struct drm_device *dev = encoder->base.dev;
2343 struct drm_i915_private *dev_priv = dev->dev_private;
2344 enum port port = dp_to_dig_port(intel_dp)->port;
2345 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
045ac3b5 2346
9ed109a7 2347 tmp = I915_READ(intel_dp->output_reg);
9fcb1704
JN		 2348
2349 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
9ed109a7 2350
39e5fa88 2351 if (HAS_PCH_CPT(dev) && port != PORT_A) {
b81e34c2
VS		 2352 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2353
2354 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2355 flags |= DRM_MODE_FLAG_PHSYNC;
2356 else
2357 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2358
b81e34c2 2359 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2360 flags |= DRM_MODE_FLAG_PVSYNC;
2361 else
2362 flags |= DRM_MODE_FLAG_NVSYNC;
2363 } else {
39e5fa88 2364 if (tmp & DP_SYNC_HS_HIGH)
63000ef6
XZ		 2365 flags |= DRM_MODE_FLAG_PHSYNC;
2366 else
2367 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2368
39e5fa88 2369 if (tmp & DP_SYNC_VS_HIGH)
63000ef6
XZ		 2370 flags |= DRM_MODE_FLAG_PVSYNC;
2371 else
2372 flags |= DRM_MODE_FLAG_NVSYNC;
2373 }
045ac3b5 2374
2d112de7 2375 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2376
8c875fca 2377 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
666a4537 2378 !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
8c875fca
VS		 2379 pipe_config->limited_color_range = true;
2380
eb14cb74
VS		 2381 pipe_config->has_dp_encoder = true;
2382
90a6b7b0
VS		 2383 pipe_config->lane_count =
2384 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2385
eb14cb74
VS		 2386 intel_dp_get_m_n(crtc, pipe_config);
2387
18442d08 2388 if (port == PORT_A) {
b377e0df 2389 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
f1f644dc
JB		 2390 pipe_config->port_clock = 162000;
2391 else
2392 pipe_config->port_clock = 270000;
2393 }
18442d08 2394
e3b247da
VS		 2395 pipe_config->base.adjusted_mode.crtc_clock =
2396 intel_dotclock_calculate(pipe_config->port_clock,
2397 &pipe_config->dp_m_n);
7f16e5c1 2398
6aa23e65
JN		 2399 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2400 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
c6cd2ee2
JN		 2401 /*
2402 * This is a big fat ugly hack.
2403 *
2404 * Some machines in UEFI boot mode provide us a VBT that has 18
2405 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2406 * unknown we fail to light up. Yet the same BIOS boots up with
2407 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2408 * max, not what it tells us to use.
2409 *
2410 * Note: This will still be broken if the eDP panel is not lit
2411 * up by the BIOS, and thus we can't get the mode at module
2412 * load.
2413 */
2414 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2415 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2416 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
c6cd2ee2 2417 }
045ac3b5
JB		 2418}
2419
e8cb4558 2420static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2421{
e8cb4558 2422 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2423 struct drm_device *dev = encoder->base.dev;
495a5bb8
JN		 2424 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2425
6e3c9717 2426 if (crtc->config->has_audio)
495a5bb8 2427 intel_audio_codec_disable(encoder);
6cb49835 2428
b32c6f48
RV		 2429 if (HAS_PSR(dev) && !HAS_DDI(dev))
2430 intel_psr_disable(intel_dp);
2431
6cb49835
DV		 2432 /* Make sure the panel is off before trying to change the mode. But also
2433 * ensure that we have vdd while we switch off the panel. */
24f3e092 2434 intel_edp_panel_vdd_on(intel_dp);
4be73780 2435 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2436 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2437 intel_edp_panel_off(intel_dp);
3739850b 2438
08aff3fe
VS		 2439 /* disable the port before the pipe on g4x */
2440 if (INTEL_INFO(dev)->gen < 5)
3739850b 2441 intel_dp_link_down(intel_dp);
d240f20f
JB		 2442}
2443
08aff3fe 2444static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2445{
2bd2ad64 2446 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2447 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2448
49277c31 2449 intel_dp_link_down(intel_dp);
abfce949
VS		 2450
2451 /* Only ilk+ has port A */
08aff3fe
VS		 2452 if (port == PORT_A)
2453 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2454}
2455
2456static void vlv_post_disable_dp(struct intel_encoder *encoder)
2457{
2458 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2459
2460 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2461}
2462
a8f327fb
VS		 2463static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
2464 bool reset)
580d3811 2465{
a8f327fb
VS		 2466 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2467 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
2468 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2469 enum pipe pipe = crtc->pipe;
2470 uint32_t val;
580d3811 2471
a8f327fb
VS		 2472 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2473 if (reset)
2474 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2475 else
2476 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2477 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
580d3811 2478
a8f327fb
VS		 2479 if (crtc->config->lane_count > 2) {
2480 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2481 if (reset)
2482 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2483 else
2484 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2485 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2486 }
580d3811 2487
97fd4d5c 2488 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2489 val |= CHV_PCS_REQ_SOFTRESET_EN;
a8f327fb
VS		 2490 if (reset)
2491 val &= ~DPIO_PCS_CLK_SOFT_RESET;
2492 else
2493 val |= DPIO_PCS_CLK_SOFT_RESET;
97fd4d5c 2494 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2495
a8f327fb 2496 if (crtc->config->lane_count > 2) {
e0fce78f
VS		 2497 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2498 val |= CHV_PCS_REQ_SOFTRESET_EN;
a8f327fb
VS		 2499 if (reset)
2500 val &= ~DPIO_PCS_CLK_SOFT_RESET;
2501 else
2502 val |= DPIO_PCS_CLK_SOFT_RESET;
e0fce78f
VS		 2503 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2504 }
a8f327fb 2505}
97fd4d5c 2506
a8f327fb
VS		 2507static void chv_post_disable_dp(struct intel_encoder *encoder)
2508{
2509 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2510 struct drm_device *dev = encoder->base.dev;
2511 struct drm_i915_private *dev_priv = dev->dev_private;
97fd4d5c 2512
a8f327fb
VS		 2513 intel_dp_link_down(intel_dp);
2514
2515 mutex_lock(&dev_priv->sb_lock);
2516
2517 /* Assert data lane reset */
2518 chv_data_lane_soft_reset(encoder, true);
580d3811 2519
a580516d 2520 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 2521}
2522
7b13b58a
VS		 2523static void
2524_intel_dp_set_link_train(struct intel_dp *intel_dp,
2525 uint32_t *DP,
2526 uint8_t dp_train_pat)
2527{
2528 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2529 struct drm_device *dev = intel_dig_port->base.base.dev;
2530 struct drm_i915_private *dev_priv = dev->dev_private;
2531 enum port port = intel_dig_port->port;
2532
2533 if (HAS_DDI(dev)) {
2534 uint32_t temp = I915_READ(DP_TP_CTL(port));
2535
2536 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2537 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2538 else
2539 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2540
2541 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2542 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2543 case DP_TRAINING_PATTERN_DISABLE:
2544 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2545
2546 break;
2547 case DP_TRAINING_PATTERN_1:
2548 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2549 break;
2550 case DP_TRAINING_PATTERN_2:
2551 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2552 break;
2553 case DP_TRAINING_PATTERN_3:
2554 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2555 break;
2556 }
2557 I915_WRITE(DP_TP_CTL(port), temp);
2558
39e5fa88
VS		 2559 } else if ((IS_GEN7(dev) && port == PORT_A) ||
2560 (HAS_PCH_CPT(dev) && port != PORT_A)) {
7b13b58a
VS		 2561 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2562
2563 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2564 case DP_TRAINING_PATTERN_DISABLE:
2565 *DP |= DP_LINK_TRAIN_OFF_CPT;
2566 break;
2567 case DP_TRAINING_PATTERN_1:
2568 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2569 break;
2570 case DP_TRAINING_PATTERN_2:
2571 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2572 break;
2573 case DP_TRAINING_PATTERN_3:
2574 DRM_ERROR("DP training pattern 3 not supported\n");
2575 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2576 break;
2577 }
2578
2579 } else {
2580 if (IS_CHERRYVIEW(dev))
2581 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2582 else
2583 *DP &= ~DP_LINK_TRAIN_MASK;
2584
2585 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2586 case DP_TRAINING_PATTERN_DISABLE:
2587 *DP |= DP_LINK_TRAIN_OFF;
2588 break;
2589 case DP_TRAINING_PATTERN_1:
2590 *DP |= DP_LINK_TRAIN_PAT_1;
2591 break;
2592 case DP_TRAINING_PATTERN_2:
2593 *DP |= DP_LINK_TRAIN_PAT_2;
2594 break;
2595 case DP_TRAINING_PATTERN_3:
2596 if (IS_CHERRYVIEW(dev)) {
2597 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2598 } else {
2599 DRM_ERROR("DP training pattern 3 not supported\n");
2600 *DP |= DP_LINK_TRAIN_PAT_2;
2601 }
2602 break;
2603 }
2604 }
2605}
2606
2607static void intel_dp_enable_port(struct intel_dp *intel_dp)
2608{
2609 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2610 struct drm_i915_private *dev_priv = dev->dev_private;
6fec7662
VS		 2611 struct intel_crtc *crtc =
2612 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
7b13b58a 2613
7b13b58a
VS		 2614 /* enable with pattern 1 (as per spec) */
2615 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2616 DP_TRAINING_PATTERN_1);
2617
2618 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2619 POSTING_READ(intel_dp->output_reg);
7b713f50
VS		 2620
2621 /*
2622 * Magic for VLV/CHV. We _must_ first set up the register
2623 * without actually enabling the port, and then do another
2624 * write to enable the port. Otherwise link training will
2625 * fail when the power sequencer is freshly used for this port.
2626 */
2627 intel_dp->DP |= DP_PORT_EN;
6fec7662
VS		 2628 if (crtc->config->has_audio)
2629 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
7b713f50
VS		 2630
2631 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2632 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2633}
2634
e8cb4558 2635static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2636{
e8cb4558
DV		 2637 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2638 struct drm_device *dev = encoder->base.dev;
2639 struct drm_i915_private *dev_priv = dev->dev_private;
c1dec79a 2640 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2641 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
d6fbdd15 2642 enum pipe pipe = crtc->pipe;
5d613501 2643
0c33d8d7
DV		 2644 if (WARN_ON(dp_reg & DP_PORT_EN))
2645 return;
5d613501 2646
093e3f13
VS		 2647 pps_lock(intel_dp);
2648
666a4537 2649 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
093e3f13
VS		 2650 vlv_init_panel_power_sequencer(intel_dp);
2651
7b13b58a 2652 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2653
2654 edp_panel_vdd_on(intel_dp);
2655 edp_panel_on(intel_dp);
2656 edp_panel_vdd_off(intel_dp, true);
2657
2658 pps_unlock(intel_dp);
2659
666a4537 2660 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e0fce78f
VS		 2661 unsigned int lane_mask = 0x0;
2662
2663 if (IS_CHERRYVIEW(dev))
2664 lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2665
9b6de0a1
VS		 2666 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2667 lane_mask);
e0fce78f 2668 }
61234fa5 2669
f01eca2e 2670 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2671 intel_dp_start_link_train(intel_dp);
3ab9c637 2672 intel_dp_stop_link_train(intel_dp);
c1dec79a 2673
6e3c9717 2674 if (crtc->config->has_audio) {
c1dec79a 2675 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
d6fbdd15 2676 pipe_name(pipe));
c1dec79a
JN		 2677 intel_audio_codec_enable(encoder);
2678 }
ab1f90f9 2679}
89b667f8 2680
ecff4f3b
JN		 2681static void g4x_enable_dp(struct intel_encoder *encoder)
2682{
828f5c6e
JN		 2683 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2684
ecff4f3b 2685 intel_enable_dp(encoder);
4be73780 2686 intel_edp_backlight_on(intel_dp);
ab1f90f9 2687}
89b667f8 2688
ab1f90f9
JN		 2689static void vlv_enable_dp(struct intel_encoder *encoder)
2690{
828f5c6e
JN		 2691 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2692
4be73780 2693 intel_edp_backlight_on(intel_dp);
b32c6f48 2694 intel_psr_enable(intel_dp);
d240f20f
JB		 2695}
2696
ecff4f3b 2697static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2698{
2699 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6fbdd15 2700 enum port port = dp_to_dig_port(intel_dp)->port;
ab1f90f9 2701
8ac33ed3
DV		 2702 intel_dp_prepare(encoder);
2703
d41f1efb 2704 /* Only ilk+ has port A */
abfce949 2705 if (port == PORT_A)
ab1f90f9
JN		 2706 ironlake_edp_pll_on(intel_dp);
2707}
2708
83b84597
VS		 2709static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2710{
2711 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2712 struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2713 enum pipe pipe = intel_dp->pps_pipe;
f0f59a00 2714 i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
83b84597
VS		 2715
2716 edp_panel_vdd_off_sync(intel_dp);
2717
2718 /*
2719 * VLV seems to get confused when multiple power seqeuencers
2720 * have the same port selected (even if only one has power/vdd
2721 * enabled). The failure manifests as vlv_wait_port_ready() failing
2722 * CHV on the other hand doesn't seem to mind having the same port
2723 * selected in multiple power seqeuencers, but let's clear the
2724 * port select always when logically disconnecting a power sequencer
2725 * from a port.
2726 */
2727 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2728 pipe_name(pipe), port_name(intel_dig_port->port));
2729 I915_WRITE(pp_on_reg, 0);
2730 POSTING_READ(pp_on_reg);
2731
2732 intel_dp->pps_pipe = INVALID_PIPE;
2733}
2734
a4a5d2f8
VS		 2735static void vlv_steal_power_sequencer(struct drm_device *dev,
2736 enum pipe pipe)
2737{
2738 struct drm_i915_private *dev_priv = dev->dev_private;
2739 struct intel_encoder *encoder;
2740
2741 lockdep_assert_held(&dev_priv->pps_mutex);
2742
ac3c12e4
VS		 2743 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2744 return;
2745
19c8054c 2746 for_each_intel_encoder(dev, encoder) {
a4a5d2f8 2747 struct intel_dp *intel_dp;
773538e8 2748 enum port port;
a4a5d2f8
VS		 2749
2750 if (encoder->type != INTEL_OUTPUT_EDP)
2751 continue;
2752
2753 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2754 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2755
2756 if (intel_dp->pps_pipe != pipe)
2757 continue;
2758
2759 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2760 pipe_name(pipe), port_name(port));
a4a5d2f8 2761
e02f9a06 2762 WARN(encoder->base.crtc,
034e43c6
VS		 2763 "stealing pipe %c power sequencer from active eDP port %c\n",
2764 pipe_name(pipe), port_name(port));
a4a5d2f8 2765
a4a5d2f8 2766 /* make sure vdd is off before we steal it */
83b84597 2767 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2768 }
2769}
2770
2771static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2772{
2773 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2774 struct intel_encoder *encoder = &intel_dig_port->base;
2775 struct drm_device *dev = encoder->base.dev;
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2778
2779 lockdep_assert_held(&dev_priv->pps_mutex);
2780
093e3f13
VS		 2781 if (!is_edp(intel_dp))
2782 return;
2783
a4a5d2f8
VS		 2784 if (intel_dp->pps_pipe == crtc->pipe)
2785 return;
2786
2787 /*
2788 * If another power sequencer was being used on this
2789 * port previously make sure to turn off vdd there while
2790 * we still have control of it.
2791 */
2792 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2793 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2794
2795 /*
2796 * We may be stealing the power
2797 * sequencer from another port.
2798 */
2799 vlv_steal_power_sequencer(dev, crtc->pipe);
2800
2801 /* now it's all ours */
2802 intel_dp->pps_pipe = crtc->pipe;
2803
2804 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2805 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2806
2807 /* init power sequencer on this pipe and port */
36b5f425
VS		 2808 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2809 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2810}
2811
ab1f90f9 2812static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2813{
2bd2ad64 2814 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2815 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2816 struct drm_device *dev = encoder->base.dev;
89b667f8 2817 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2818 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2819 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2820 int pipe = intel_crtc->pipe;
2821 u32 val;
a4fc5ed6 2822
a580516d 2823 mutex_lock(&dev_priv->sb_lock);
89b667f8 2824
ab3c759a 2825 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2826 val = 0;
2827 if (pipe)
2828 val |= (1<<21);
2829 else
2830 val &= ~(1<<21);
2831 val |= 0x001000c4;
ab3c759a
CML		 2832 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2833 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2834 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2835
a580516d 2836 mutex_unlock(&dev_priv->sb_lock);
ab1f90f9
JN		 2837
2838 intel_enable_dp(encoder);
89b667f8
JB		 2839}
2840
ecff4f3b 2841static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2842{
2843 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2844 struct drm_device *dev = encoder->base.dev;
2845 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2846 struct intel_crtc *intel_crtc =
2847 to_intel_crtc(encoder->base.crtc);
e4607fcf 2848 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2849 int pipe = intel_crtc->pipe;
89b667f8 2850
8ac33ed3
DV		 2851 intel_dp_prepare(encoder);
2852
89b667f8 2853 /* Program Tx lane resets to default */
a580516d 2854 mutex_lock(&dev_priv->sb_lock);
ab3c759a 2855 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2856 DPIO_PCS_TX_LANE2_RESET |
2857 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2858 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2859 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2860 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2861 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2862 DPIO_PCS_CLK_SOFT_RESET);
2863
2864 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2865 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2866 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2867 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
a580516d 2868 mutex_unlock(&dev_priv->sb_lock);
a4fc5ed6
KP		 2869}
2870
e4a1d846
CML		 2871static void chv_pre_enable_dp(struct intel_encoder *encoder)
2872{
2873 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2874 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2875 struct drm_device *dev = encoder->base.dev;
2876 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2877 struct intel_crtc *intel_crtc =
2878 to_intel_crtc(encoder->base.crtc);
2879 enum dpio_channel ch = vlv_dport_to_channel(dport);
2880 int pipe = intel_crtc->pipe;
2e523e98 2881 int data, i, stagger;
949c1d43 2882 u32 val;
e4a1d846 2883
a580516d 2884 mutex_lock(&dev_priv->sb_lock);
949c1d43 2885
570e2a74
VS		 2886 /* allow hardware to manage TX FIFO reset source */
2887 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2888 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2889 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2890
e0fce78f
VS		 2891 if (intel_crtc->config->lane_count > 2) {
2892 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2893 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2894 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2895 }
570e2a74 2896
949c1d43 2897 /* Program Tx lane latency optimal setting*/
e0fce78f 2898 for (i = 0; i < intel_crtc->config->lane_count; i++) {
e4a1d846 2899 /* Set the upar bit */
e0fce78f
VS		 2900 if (intel_crtc->config->lane_count == 1)
2901 data = 0x0;
2902 else
2903 data = (i == 1) ? 0x0 : 0x1;
e4a1d846
CML		 2904 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2905 data << DPIO_UPAR_SHIFT);
2906 }
2907
2908 /* Data lane stagger programming */
2e523e98
VS		 2909 if (intel_crtc->config->port_clock > 270000)
2910 stagger = 0x18;
2911 else if (intel_crtc->config->port_clock > 135000)
2912 stagger = 0xd;
2913 else if (intel_crtc->config->port_clock > 67500)
2914 stagger = 0x7;
2915 else if (intel_crtc->config->port_clock > 33750)
2916 stagger = 0x4;
2917 else
2918 stagger = 0x2;
2919
2920 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2921 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2922 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2923
e0fce78f
VS		 2924 if (intel_crtc->config->lane_count > 2) {
2925 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2926 val |= DPIO_TX2_STAGGER_MASK(0x1f);
2927 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2928 }
2e523e98
VS		 2929
2930 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
2931 DPIO_LANESTAGGER_STRAP(stagger) |
2932 DPIO_LANESTAGGER_STRAP_OVRD |
2933 DPIO_TX1_STAGGER_MASK(0x1f) |
2934 DPIO_TX1_STAGGER_MULT(6) |
2935 DPIO_TX2_STAGGER_MULT(0));
2936
e0fce78f
VS		 2937 if (intel_crtc->config->lane_count > 2) {
2938 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
2939 DPIO_LANESTAGGER_STRAP(stagger) |
2940 DPIO_LANESTAGGER_STRAP_OVRD |
2941 DPIO_TX1_STAGGER_MASK(0x1f) |
2942 DPIO_TX1_STAGGER_MULT(7) |
2943 DPIO_TX2_STAGGER_MULT(5));
2944 }
e4a1d846 2945
a8f327fb
VS		 2946 /* Deassert data lane reset */
2947 chv_data_lane_soft_reset(encoder, false);
2948
a580516d 2949 mutex_unlock(&dev_priv->sb_lock);
e4a1d846 2950
e4a1d846 2951 intel_enable_dp(encoder);
b0b33846
VS		 2952
2953 /* Second common lane will stay alive on its own now */
2954 if (dport->release_cl2_override) {
2955 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
2956 dport->release_cl2_override = false;
2957 }
e4a1d846
CML		 2958}
2959
9197c88b
VS		 2960static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2961{
2962 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2963 struct drm_device *dev = encoder->base.dev;
2964 struct drm_i915_private *dev_priv = dev->dev_private;
2965 struct intel_crtc *intel_crtc =
2966 to_intel_crtc(encoder->base.crtc);
2967 enum dpio_channel ch = vlv_dport_to_channel(dport);
2968 enum pipe pipe = intel_crtc->pipe;
e0fce78f
VS		 2969 unsigned int lane_mask =
2970 intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
9197c88b
VS		 2971 u32 val;
2972
625695f8
VS		 2973 intel_dp_prepare(encoder);
2974
b0b33846
VS		 2975 /*
2976 * Must trick the second common lane into life.
2977 * Otherwise we can't even access the PLL.
2978 */
2979 if (ch == DPIO_CH0 && pipe == PIPE_B)
2980 dport->release_cl2_override =
2981 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
2982
e0fce78f
VS		 2983 chv_phy_powergate_lanes(encoder, true, lane_mask);
2984
a580516d 2985 mutex_lock(&dev_priv->sb_lock);
9197c88b 2986
a8f327fb
VS		 2987 /* Assert data lane reset */
2988 chv_data_lane_soft_reset(encoder, true);
2989
b9e5ac3c
VS		 2990 /* program left/right clock distribution */
2991 if (pipe != PIPE_B) {
2992 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2993 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2994 if (ch == DPIO_CH0)
2995 val |= CHV_BUFLEFTENA1_FORCE;
2996 if (ch == DPIO_CH1)
2997 val |= CHV_BUFRIGHTENA1_FORCE;
2998 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2999 } else {
3000 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
3001 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
3002 if (ch == DPIO_CH0)
3003 val |= CHV_BUFLEFTENA2_FORCE;
3004 if (ch == DPIO_CH1)
3005 val |= CHV_BUFRIGHTENA2_FORCE;
3006 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
3007 }
3008
9197c88b
VS		 3009 /* program clock channel usage */
3010 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
3011 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
3012 if (pipe != PIPE_B)
3013 val &= ~CHV_PCS_USEDCLKCHANNEL;
3014 else
3015 val |= CHV_PCS_USEDCLKCHANNEL;
3016 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
3017
e0fce78f
VS		 3018 if (intel_crtc->config->lane_count > 2) {
3019 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
3020 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
3021 if (pipe != PIPE_B)
3022 val &= ~CHV_PCS_USEDCLKCHANNEL;
3023 else
3024 val |= CHV_PCS_USEDCLKCHANNEL;
3025 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
3026 }
9197c88b
VS		 3027
3028 /*
3029 * This a a bit weird since generally CL
3030 * matches the pipe, but here we need to
3031 * pick the CL based on the port.
3032 */
3033 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
3034 if (pipe != PIPE_B)
3035 val &= ~CHV_CMN_USEDCLKCHANNEL;
3036 else
3037 val |= CHV_CMN_USEDCLKCHANNEL;
3038 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
3039
a580516d 3040 mutex_unlock(&dev_priv->sb_lock);
9197c88b
VS		 3041}
3042
d6db995f
VS		 3043static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
3044{
3045 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3046 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
3047 u32 val;
3048
3049 mutex_lock(&dev_priv->sb_lock);
3050
3051 /* disable left/right clock distribution */
3052 if (pipe != PIPE_B) {
3053 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
3054 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
3055 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
3056 } else {
3057 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
3058 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
3059 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
3060 }
3061
3062 mutex_unlock(&dev_priv->sb_lock);
e0fce78f 3063
b0b33846
VS		 3064 /*
3065 * Leave the power down bit cleared for at least one
3066 * lane so that chv_powergate_phy_ch() will power
3067 * on something when the channel is otherwise unused.
3068 * When the port is off and the override is removed
3069 * the lanes power down anyway, so otherwise it doesn't
3070 * really matter what the state of power down bits is
3071 * after this.
3072 */
e0fce78f 3073 chv_phy_powergate_lanes(encoder, false, 0x0);
d6db995f
VS		 3074}
3075
a4fc5ed6 3076/*
df0c237d
JB		 3077 * Native read with retry for link status and receiver capability reads for
3078 * cases where the sink may still be asleep.
9d1a1031
JN		 3079 *
3080 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
3081 * supposed to retry 3 times per the spec.
a4fc5ed6 3082 */
9d1a1031
JN		 3083static ssize_t
3084intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
3085 void *buffer, size_t size)
a4fc5ed6 3086{
9d1a1031
JN		 3087 ssize_t ret;
3088 int i;
61da5fab 3089
f6a19066
VS		 3090 /*
3091 * Sometime we just get the same incorrect byte repeated
3092 * over the entire buffer. Doing just one throw away read
3093 * initially seems to "solve" it.
3094 */
3095 drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
3096
61da5fab 3097 for (i = 0; i < 3; i++) {
9d1a1031
JN		 3098 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
3099 if (ret == size)
3100 return ret;
61da5fab
JB		 3101 msleep(1);
3102 }
a4fc5ed6 3103
9d1a1031 3104 return ret;
a4fc5ed6
KP		 3105}
3106
3107/*
3108 * Fetch AUX CH registers 0x202 - 0x207 which contain
3109 * link status information
3110 */
94223d04 3111bool
93f62dad 3112intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 3113{
9d1a1031
JN		 3114 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3115 DP_LANE0_1_STATUS,
3116 link_status,
3117 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 3118}
3119
1100244e 3120/* These are source-specific values. */
94223d04 3121uint8_t
1a2eb460 3122intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 3123{
30add22d 3124 struct drm_device *dev = intel_dp_to_dev(intel_dp);
7ad14a29 3125 struct drm_i915_private *dev_priv = dev->dev_private;
bc7d38a4 3126 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 3127
9314726b
VK		 3128 if (IS_BROXTON(dev))
3129 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3130 else if (INTEL_INFO(dev)->gen >= 9) {
06411f08 3131 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
7ad14a29 3132 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 3133 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
666a4537 3134 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
bd60018a 3135 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 3136 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 3137 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 3138 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 3139 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 3140 else
bd60018a 3141 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 3142}
3143
94223d04 3144uint8_t
1a2eb460
KP		 3145intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3146{
30add22d 3147 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 3148 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 3149
5a9d1f1a
DL		 3150 if (INTEL_INFO(dev)->gen >= 9) {
3151 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3152 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3153 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3154 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3155 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3156 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3157 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 3158 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3159 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 3160 default:
3161 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3162 }
3163 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 3164 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3165 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3166 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3167 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3168 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3169 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3170 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3171 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 3172 default:
bd60018a 3173 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 3174 }
666a4537 3175 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e2fa6fba 3176 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3177 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3178 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3179 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3180 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3181 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3182 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3183 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 3184 default:
bd60018a 3185 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 3186 }
bc7d38a4 3187 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 3188 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3189 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3190 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3191 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3192 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3193 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 3194 default:
bd60018a 3195 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 3196 }
3197 } else {
3198 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3199 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3200 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3201 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3202 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3203 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3204 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3205 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 3206 default:
bd60018a 3207 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 3208 }
a4fc5ed6
KP		 3209 }
3210}
3211
5829975c 3212static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba
P		 3213{
3214 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3215 struct drm_i915_private *dev_priv = dev->dev_private;
3216 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 3217 struct intel_crtc *intel_crtc =
3218 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 3219 unsigned long demph_reg_value, preemph_reg_value,
3220 uniqtranscale_reg_value;
3221 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 3222 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 3223 int pipe = intel_crtc->pipe;
e2fa6fba
P		 3224
3225 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3226 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3227 preemph_reg_value = 0x0004000;
3228 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3229 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3230 demph_reg_value = 0x2B405555;
3231 uniqtranscale_reg_value = 0x552AB83A;
3232 break;
bd60018a 3233 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3234 demph_reg_value = 0x2B404040;
3235 uniqtranscale_reg_value = 0x5548B83A;
3236 break;
bd60018a 3237 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3238 demph_reg_value = 0x2B245555;
3239 uniqtranscale_reg_value = 0x5560B83A;
3240 break;
bd60018a 3241 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3242 demph_reg_value = 0x2B405555;
3243 uniqtranscale_reg_value = 0x5598DA3A;
3244 break;
3245 default:
3246 return 0;
3247 }
3248 break;
bd60018a 3249 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3250 preemph_reg_value = 0x0002000;
3251 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3252 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3253 demph_reg_value = 0x2B404040;
3254 uniqtranscale_reg_value = 0x5552B83A;
3255 break;
bd60018a 3256 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3257 demph_reg_value = 0x2B404848;
3258 uniqtranscale_reg_value = 0x5580B83A;
3259 break;
bd60018a 3260 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3261 demph_reg_value = 0x2B404040;
3262 uniqtranscale_reg_value = 0x55ADDA3A;
3263 break;
3264 default:
3265 return 0;
3266 }
3267 break;
bd60018a 3268 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3269 preemph_reg_value = 0x0000000;
3270 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3271 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3272 demph_reg_value = 0x2B305555;
3273 uniqtranscale_reg_value = 0x5570B83A;
3274 break;
bd60018a 3275 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3276 demph_reg_value = 0x2B2B4040;
3277 uniqtranscale_reg_value = 0x55ADDA3A;
3278 break;
3279 default:
3280 return 0;
3281 }
3282 break;
bd60018a 3283 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3284 preemph_reg_value = 0x0006000;
3285 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3286 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3287 demph_reg_value = 0x1B405555;
3288 uniqtranscale_reg_value = 0x55ADDA3A;
3289 break;
3290 default:
3291 return 0;
3292 }
3293 break;
3294 default:
3295 return 0;
3296 }
3297
a580516d 3298 mutex_lock(&dev_priv->sb_lock);
ab3c759a
CML		 3299 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3300 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3301 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3302 uniqtranscale_reg_value);
ab3c759a
CML		 3303 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3304 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3305 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3306 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
a580516d 3307 mutex_unlock(&dev_priv->sb_lock);
e2fa6fba
P		 3308
3309 return 0;
3310}
3311
67fa24b4
VS		 3312static bool chv_need_uniq_trans_scale(uint8_t train_set)
3313{
3314 return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
3315 (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3316}
3317
5829975c 3318static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846
CML		 3319{
3320 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3321 struct drm_i915_private *dev_priv = dev->dev_private;
3322 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3323 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3324 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3325 uint8_t train_set = intel_dp->train_set[0];
3326 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3327 enum pipe pipe = intel_crtc->pipe;
3328 int i;
e4a1d846
CML		 3329
3330 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3331 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3332 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3333 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3334 deemph_reg_value = 128;
3335 margin_reg_value = 52;
3336 break;
bd60018a 3337 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3338 deemph_reg_value = 128;
3339 margin_reg_value = 77;
3340 break;
bd60018a 3341 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3342 deemph_reg_value = 128;
3343 margin_reg_value = 102;
3344 break;
bd60018a 3345 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3346 deemph_reg_value = 128;
3347 margin_reg_value = 154;
3348 /* FIXME extra to set for 1200 */
3349 break;
3350 default:
3351 return 0;
3352 }
3353 break;
bd60018a 3354 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3355 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3356 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3357 deemph_reg_value = 85;
3358 margin_reg_value = 78;
3359 break;
bd60018a 3360 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3361 deemph_reg_value = 85;
3362 margin_reg_value = 116;
3363 break;
bd60018a 3364 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3365 deemph_reg_value = 85;
3366 margin_reg_value = 154;
3367 break;
3368 default:
3369 return 0;
3370 }
3371 break;
bd60018a 3372 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3373 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3374 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3375 deemph_reg_value = 64;
3376 margin_reg_value = 104;
3377 break;
bd60018a 3378 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3379 deemph_reg_value = 64;
3380 margin_reg_value = 154;
3381 break;
3382 default:
3383 return 0;
3384 }
3385 break;
bd60018a 3386 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3387 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3388 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3389 deemph_reg_value = 43;
3390 margin_reg_value = 154;
3391 break;
3392 default:
3393 return 0;
3394 }
3395 break;
3396 default:
3397 return 0;
3398 }
3399
a580516d 3400 mutex_lock(&dev_priv->sb_lock);
e4a1d846
CML		 3401
3402 /* Clear calc init */
1966e59e
VS		 3403 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3404 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3405 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3406 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3407 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3408
e0fce78f
VS		 3409 if (intel_crtc->config->lane_count > 2) {
3410 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3411 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3412 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3413 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3414 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3415 }
e4a1d846 3416
a02ef3c7
VS		 3417 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3418 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3419 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3420 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3421
e0fce78f
VS		 3422 if (intel_crtc->config->lane_count > 2) {
3423 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3424 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3425 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3426 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3427 }
a02ef3c7 3428
e4a1d846 3429 /* Program swing deemph */
e0fce78f 3430 for (i = 0; i < intel_crtc->config->lane_count; i++) {
f72df8db
VS		 3431 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3432 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3433 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3434 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3435 }
e4a1d846
CML		 3436
3437 /* Program swing margin */
e0fce78f 3438 for (i = 0; i < intel_crtc->config->lane_count; i++) {
f72df8db 3439 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
67fa24b4 3440
1fb44505
VS		 3441 val &= ~DPIO_SWING_MARGIN000_MASK;
3442 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
67fa24b4
VS		 3443
3444 /*
3445 * Supposedly this value shouldn't matter when unique transition
3446 * scale is disabled, but in fact it does matter. Let's just
3447 * always program the same value and hope it's OK.
3448 */
3449 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3450 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
3451
f72df8db
VS		 3452 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3453 }
e4a1d846 3454
67fa24b4
VS		 3455 /*
3456 * The document said it needs to set bit 27 for ch0 and bit 26
3457 * for ch1. Might be a typo in the doc.
3458 * For now, for this unique transition scale selection, set bit
3459 * 27 for ch0 and ch1.
3460 */
e0fce78f 3461 for (i = 0; i < intel_crtc->config->lane_count; i++) {
f72df8db 3462 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
67fa24b4 3463 if (chv_need_uniq_trans_scale(train_set))
f72df8db 3464 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
67fa24b4
VS		 3465 else
3466 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3467 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
e4a1d846
CML		 3468 }
3469
3470 /* Start swing calculation */
1966e59e
VS		 3471 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3472 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3473 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3474
e0fce78f
VS		 3475 if (intel_crtc->config->lane_count > 2) {
3476 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3477 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3478 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3479 }
e4a1d846 3480
a580516d 3481 mutex_unlock(&dev_priv->sb_lock);
e4a1d846
CML		 3482
3483 return 0;
3484}
3485
a4fc5ed6 3486static uint32_t
5829975c 3487gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3488{
3cf2efb1 3489 uint32_t signal_levels = 0;
a4fc5ed6 3490
3cf2efb1 3491 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3492 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3493 default:
3494 signal_levels |= DP_VOLTAGE_0_4;
3495 break;
bd60018a 3496 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3497 signal_levels |= DP_VOLTAGE_0_6;
3498 break;
bd60018a 3499 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3500 signal_levels |= DP_VOLTAGE_0_8;
3501 break;
bd60018a 3502 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3503 signal_levels |= DP_VOLTAGE_1_2;
3504 break;
3505 }
3cf2efb1 3506 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3507 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3508 default:
3509 signal_levels |= DP_PRE_EMPHASIS_0;
3510 break;
bd60018a 3511 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3512 signal_levels |= DP_PRE_EMPHASIS_3_5;
3513 break;
bd60018a 3514 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3515 signal_levels |= DP_PRE_EMPHASIS_6;
3516 break;
bd60018a 3517 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3518 signal_levels |= DP_PRE_EMPHASIS_9_5;
3519 break;
3520 }
3521 return signal_levels;
3522}
3523
e3421a18
ZW		 3524/* Gen6's DP voltage swing and pre-emphasis control */
3525static uint32_t
5829975c 3526gen6_edp_signal_levels(uint8_t train_set)
e3421a18 3527{
3c5a62b5
YL		 3528 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3529 DP_TRAIN_PRE_EMPHASIS_MASK);
3530 switch (signal_levels) {
bd60018a
SJ		 3531 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3532 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3533 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3534 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3535 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3536 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3537 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3538 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3539 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3540 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3541 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3542 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3543 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3544 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3545 default:
3c5a62b5
YL		 3546 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3547 "0x%x\n", signal_levels);
3548 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3549 }
3550}
3551
1a2eb460
KP		 3552/* Gen7's DP voltage swing and pre-emphasis control */
3553static uint32_t
5829975c 3554gen7_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3555{
3556 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3557 DP_TRAIN_PRE_EMPHASIS_MASK);
3558 switch (signal_levels) {
bd60018a 3559 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3560 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3561 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3562 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3563 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3564 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3565
bd60018a 3566 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3567 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3568 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3569 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3570
bd60018a 3571 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3572 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3573 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3574 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3575
3576 default:
3577 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3578 "0x%x\n", signal_levels);
3579 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3580 }
3581}
3582
94223d04 3583void
f4eb692e 3584intel_dp_set_signal_levels(struct intel_dp *intel_dp)
f0a3424e
PZ		 3585{
3586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3587 enum port port = intel_dig_port->port;
f0a3424e 3588 struct drm_device *dev = intel_dig_port->base.base.dev;
b905a915 3589 struct drm_i915_private *dev_priv = to_i915(dev);
f8896f5d 3590 uint32_t signal_levels, mask = 0;
f0a3424e
PZ		 3591 uint8_t train_set = intel_dp->train_set[0];
3592
f8896f5d
DW		 3593 if (HAS_DDI(dev)) {
3594 signal_levels = ddi_signal_levels(intel_dp);
3595
3596 if (IS_BROXTON(dev))
3597 signal_levels = 0;
3598 else
3599 mask = DDI_BUF_EMP_MASK;
e4a1d846 3600 } else if (IS_CHERRYVIEW(dev)) {
5829975c 3601 signal_levels = chv_signal_levels(intel_dp);
e2fa6fba 3602 } else if (IS_VALLEYVIEW(dev)) {
5829975c 3603 signal_levels = vlv_signal_levels(intel_dp);
bc7d38a4 3604 } else if (IS_GEN7(dev) && port == PORT_A) {
5829975c 3605 signal_levels = gen7_edp_signal_levels(train_set);
f0a3424e 3606 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3607 } else if (IS_GEN6(dev) && port == PORT_A) {
5829975c 3608 signal_levels = gen6_edp_signal_levels(train_set);
f0a3424e
PZ		 3609 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3610 } else {
5829975c 3611 signal_levels = gen4_signal_levels(train_set);
f0a3424e
PZ		 3612 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3613 }
3614
96fb9f9b
VK		 3615 if (mask)
3616 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3617
3618 DRM_DEBUG_KMS("Using vswing level %d\n",
3619 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3620 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3621 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3622 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e 3623
f4eb692e 3624 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
b905a915
ACO		 3625
3626 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3627 POSTING_READ(intel_dp->output_reg);
f0a3424e
PZ		 3628}
3629
94223d04 3630void
e9c176d5
ACO		 3631intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3632 uint8_t dp_train_pat)
a4fc5ed6 3633{
174edf1f 3634 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
90a6b7b0
VS		 3635 struct drm_i915_private *dev_priv =
3636 to_i915(intel_dig_port->base.base.dev);
a4fc5ed6 3637
f4eb692e 3638 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
47ea7542 3639
f4eb692e 3640 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
ea5b213a 3641 POSTING_READ(intel_dp->output_reg);
e9c176d5
ACO		 3642}
3643
94223d04 3644void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3ab9c637
ID		 3645{
3646 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3647 struct drm_device *dev = intel_dig_port->base.base.dev;
3648 struct drm_i915_private *dev_priv = dev->dev_private;
3649 enum port port = intel_dig_port->port;
3650 uint32_t val;
3651
3652 if (!HAS_DDI(dev))
3653 return;
3654
3655 val = I915_READ(DP_TP_CTL(port));
3656 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3657 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3658 I915_WRITE(DP_TP_CTL(port), val);
3659
3660 /*
3661 * On PORT_A we can have only eDP in SST mode. There the only reason
3662 * we need to set idle transmission mode is to work around a HW issue
3663 * where we enable the pipe while not in idle link-training mode.
3664 * In this case there is requirement to wait for a minimum number of
3665 * idle patterns to be sent.
3666 */
3667 if (port == PORT_A)
3668 return;
3669
3670 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3671 1))
3672 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3673}
3674
a4fc5ed6 3675static void
ea5b213a 3676intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3677{
da63a9f2 3678 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1612c8bd 3679 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
bc7d38a4 3680 enum port port = intel_dig_port->port;
da63a9f2 3681 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3682 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 3683 uint32_t DP = intel_dp->DP;
a4fc5ed6 3684
bc76e320 3685 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3686 return;
3687
0c33d8d7 3688 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3689 return;
3690
28c97730 3691 DRM_DEBUG_KMS("\n");
32f9d658 3692
39e5fa88
VS		 3693 if ((IS_GEN7(dev) && port == PORT_A) ||
3694 (HAS_PCH_CPT(dev) && port != PORT_A)) {
e3421a18 3695 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1612c8bd 3696 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
e3421a18 3697 } else {
aad3d14d
VS		 3698 if (IS_CHERRYVIEW(dev))
3699 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3700 else
3701 DP &= ~DP_LINK_TRAIN_MASK;
1612c8bd 3702 DP |= DP_LINK_TRAIN_PAT_IDLE;
e3421a18 3703 }
1612c8bd 3704 I915_WRITE(intel_dp->output_reg, DP);
fe255d00 3705 POSTING_READ(intel_dp->output_reg);
5eb08b69 3706
1612c8bd
VS		 3707 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3708 I915_WRITE(intel_dp->output_reg, DP);
3709 POSTING_READ(intel_dp->output_reg);
3710
3711 /*
3712 * HW workaround for IBX, we need to move the port
3713 * to transcoder A after disabling it to allow the
3714 * matching HDMI port to be enabled on transcoder A.
3715 */
3716 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
0c241d5b
VS		 3717 /*
3718 * We get CPU/PCH FIFO underruns on the other pipe when
3719 * doing the workaround. Sweep them under the rug.
3720 */
3721 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3722 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3723
1612c8bd
VS		 3724 /* always enable with pattern 1 (as per spec) */
3725 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3726 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3727 I915_WRITE(intel_dp->output_reg, DP);
3728 POSTING_READ(intel_dp->output_reg);
3729
3730 DP &= ~DP_PORT_EN;
5bddd17f 3731 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3732 POSTING_READ(intel_dp->output_reg);
0c241d5b
VS		 3733
3734 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
3735 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3736 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5bddd17f
EA		 3737 }
3738
f01eca2e 3739 msleep(intel_dp->panel_power_down_delay);
6fec7662
VS		 3740
3741 intel_dp->DP = DP;
a4fc5ed6
KP		 3742}
3743
26d61aad
KP		 3744static bool
3745intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3746{
a031d709
RV		 3747 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3748 struct drm_device *dev = dig_port->base.base.dev;
3749 struct drm_i915_private *dev_priv = dev->dev_private;
fc0f8e25 3750 uint8_t rev;
a031d709 3751
9d1a1031
JN		 3752 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3753 sizeof(intel_dp->dpcd)) < 0)
edb39244 3754 return false; /* aux transfer failed */
92fd8fd1 3755
a8e98153 3756 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3757
edb39244
AJ		 3758 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3759 return false; /* DPCD not present */
3760
30d9aa42
SS		 3761 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3762 &intel_dp->sink_count, 1) < 0)
3763 return false;
3764
3765 /*
3766 * Sink count can change between short pulse hpd hence
3767 * a member variable in intel_dp will track any changes
3768 * between short pulse interrupts.
3769 */
3770 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3771
3772 /*
3773 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3774 * a dongle is present but no display. Unless we require to know
3775 * if a dongle is present or not, we don't need to update
3776 * downstream port information. So, an early return here saves
3777 * time from performing other operations which are not required.
3778 */
3779 if (!intel_dp->sink_count)
3780 return false;
3781
2293bb5c
SK		 3782 /* Check if the panel supports PSR */
3783 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3784 if (is_edp(intel_dp)) {
9d1a1031
JN		 3785 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3786 intel_dp->psr_dpcd,
3787 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3788 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3789 dev_priv->psr.sink_support = true;
50003939 3790 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3791 }
474d1ec4
SJ		 3792
3793 if (INTEL_INFO(dev)->gen >= 9 &&
3794 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3795 uint8_t frame_sync_cap;
3796
3797 dev_priv->psr.sink_support = true;
3798 intel_dp_dpcd_read_wake(&intel_dp->aux,
3799 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3800 &frame_sync_cap, 1);
3801 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3802 /* PSR2 needs frame sync as well */
3803 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3804 DRM_DEBUG_KMS("PSR2 %s on sink",
3805 dev_priv->psr.psr2_support ? "supported" : "not supported");
3806 }
50003939
JN		 3807 }
3808
bc5133d5 3809 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
e588fa18 3810 yesno(intel_dp_source_supports_hbr2(intel_dp)),
742f491d 3811 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
06ea66b6 3812
fc0f8e25
SJ		 3813 /* Intermediate frequency support */
3814 if (is_edp(intel_dp) &&
3815 (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3816 (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3817 (rev >= 0x03)) { /* eDp v1.4 or higher */
94ca719e 3818 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3819 int i;
3820
fc0f8e25
SJ		 3821 intel_dp_dpcd_read_wake(&intel_dp->aux,
3822 DP_SUPPORTED_LINK_RATES,
94ca719e
VS		 3823 sink_rates,
3824 sizeof(sink_rates));
ea2d8a42 3825
94ca719e
VS		 3826 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3827 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3828
3829 if (val == 0)
3830 break;
3831
af77b974
SJ		 3832 /* Value read is in kHz while drm clock is saved in deca-kHz */
3833 intel_dp->sink_rates[i] = (val * 200) / 10;
ea2d8a42 3834 }
94ca719e 3835 intel_dp->num_sink_rates = i;
fc0f8e25 3836 }
0336400e
VS		 3837
3838 intel_dp_print_rates(intel_dp);
3839
edb39244
AJ		 3840 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3841 DP_DWN_STRM_PORT_PRESENT))
3842 return true; /* native DP sink */
3843
3844 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3845 return true; /* no per-port downstream info */
3846
9d1a1031
JN		 3847 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3848 intel_dp->downstream_ports,
3849 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3850 return false; /* downstream port status fetch failed */
3851
3852 return true;
92fd8fd1
KP		 3853}
3854
0d198328
AJ		 3855static void
3856intel_dp_probe_oui(struct intel_dp *intel_dp)
3857{
3858 u8 buf[3];
3859
3860 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3861 return;
3862
9d1a1031 3863 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3864 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3865 buf[0], buf[1], buf[2]);
3866
9d1a1031 3867 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3868 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3869 buf[0], buf[1], buf[2]);
3870}
3871
0e32b39c
DA		 3872static bool
3873intel_dp_probe_mst(struct intel_dp *intel_dp)
3874{
3875 u8 buf[1];
3876
7cc96139
NS		 3877 if (!i915.enable_dp_mst)
3878 return false;
3879
0e32b39c
DA		 3880 if (!intel_dp->can_mst)
3881 return false;
3882
3883 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3884 return false;
3885
0e32b39c
DA		 3886 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3887 if (buf[0] & DP_MST_CAP) {
3888 DRM_DEBUG_KMS("Sink is MST capable\n");
3889 intel_dp->is_mst = true;
3890 } else {
3891 DRM_DEBUG_KMS("Sink is not MST capable\n");
3892 intel_dp->is_mst = false;
3893 }
3894 }
0e32b39c
DA		 3895
3896 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3897 return intel_dp->is_mst;
3898}
3899
e5a1cab5 3900static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
d2e216d0 3901{
082dcc7c 3902 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3903 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c 3904 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
ad9dc91b 3905 u8 buf;
e5a1cab5 3906 int ret = 0;
c6297843
RV		 3907 int count = 0;
3908 int attempts = 10;
d2e216d0 3909
082dcc7c
RV		 3910 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3911 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3912 ret = -EIO;
3913 goto out;
4373f0f2
PZ		 3914 }
3915
082dcc7c 3916 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
e5a1cab5 3917 buf & ~DP_TEST_SINK_START) < 0) {
082dcc7c 3918 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3919 ret = -EIO;
3920 goto out;
3921 }
d2e216d0 3922
c6297843
RV		 3923 do {
3924 intel_wait_for_vblank(dev, intel_crtc->pipe);
3925
3926 if (drm_dp_dpcd_readb(&intel_dp->aux,
3927 DP_TEST_SINK_MISC, &buf) < 0) {
3928 ret = -EIO;
3929 goto out;
3930 }
3931 count = buf & DP_TEST_COUNT_MASK;
3932 } while (--attempts && count);
3933
3934 if (attempts == 0) {
dc5a9037 3935 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
c6297843
RV		 3936 ret = -ETIMEDOUT;
3937 }
3938
e5a1cab5 3939 out:
082dcc7c 3940 hsw_enable_ips(intel_crtc);
e5a1cab5 3941 return ret;
082dcc7c
RV		 3942}
3943
3944static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3945{
3946 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3947 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c
RV		 3948 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3949 u8 buf;
e5a1cab5
RV		 3950 int ret;
3951
082dcc7c
RV		 3952 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3953 return -EIO;
3954
3955 if (!(buf & DP_TEST_CRC_SUPPORTED))
3956 return -ENOTTY;
3957
3958 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3959 return -EIO;
3960
6d8175da
RV		 3961 if (buf & DP_TEST_SINK_START) {
3962 ret = intel_dp_sink_crc_stop(intel_dp);
3963 if (ret)
3964 return ret;
3965 }
3966
082dcc7c 3967 hsw_disable_ips(intel_crtc);
1dda5f93 3968
9d1a1031 3969 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
082dcc7c
RV		 3970 buf | DP_TEST_SINK_START) < 0) {
3971 hsw_enable_ips(intel_crtc);
3972 return -EIO;
4373f0f2
PZ		 3973 }
3974
d72f9d91 3975 intel_wait_for_vblank(dev, intel_crtc->pipe);
082dcc7c
RV		 3976 return 0;
3977}
3978
3979int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3980{
3981 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3982 struct drm_device *dev = dig_port->base.base.dev;
3983 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3984 u8 buf;
621d4c76 3985 int count, ret;
082dcc7c 3986 int attempts = 6;
082dcc7c
RV		 3987
3988 ret = intel_dp_sink_crc_start(intel_dp);
3989 if (ret)
3990 return ret;
3991
ad9dc91b 3992 do {
621d4c76
RV		 3993 intel_wait_for_vblank(dev, intel_crtc->pipe);
3994
1dda5f93 3995 if (drm_dp_dpcd_readb(&intel_dp->aux,
4373f0f2
PZ		 3996 DP_TEST_SINK_MISC, &buf) < 0) {
3997 ret = -EIO;
afe0d67e 3998 goto stop;
4373f0f2 3999 }
621d4c76 4000 count = buf & DP_TEST_COUNT_MASK;
aabc95dc 4001
7e38eeff 4002 } while (--attempts && count == 0);
ad9dc91b
RV		 4003
4004 if (attempts == 0) {
7e38eeff
RV		 4005 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
4006 ret = -ETIMEDOUT;
4007 goto stop;
4008 }
4009
4010 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
4011 ret = -EIO;
4012 goto stop;
ad9dc91b 4013 }
d2e216d0 4014
afe0d67e 4015stop:
082dcc7c 4016 intel_dp_sink_crc_stop(intel_dp);
4373f0f2 4017 return ret;
d2e216d0
RV		 4018}
4019
a60f0e38
JB		 4020static bool
4021intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4022{
9d1a1031
JN		 4023 return intel_dp_dpcd_read_wake(&intel_dp->aux,
4024 DP_DEVICE_SERVICE_IRQ_VECTOR,
4025 sink_irq_vector, 1) == 1;
a60f0e38
JB		 4026}
4027
0e32b39c
DA		 4028static bool
4029intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4030{
4031 int ret;
4032
4033 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4034 DP_SINK_COUNT_ESI,
4035 sink_irq_vector, 14);
4036 if (ret != 14)
4037 return false;
4038
4039 return true;
4040}
4041
c5d5ab7a
TP		 4042static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4043{
4044 uint8_t test_result = DP_TEST_ACK;
4045 return test_result;
4046}
4047
4048static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4049{
4050 uint8_t test_result = DP_TEST_NAK;
4051 return test_result;
4052}
4053
4054static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
a60f0e38 4055{
c5d5ab7a 4056 uint8_t test_result = DP_TEST_NAK;
559be30c
TP		 4057 struct intel_connector *intel_connector = intel_dp->attached_connector;
4058 struct drm_connector *connector = &intel_connector->base;
4059
4060 if (intel_connector->detect_edid == NULL ||
ac6f2e29 4061 connector->edid_corrupt ||
559be30c
TP		 4062 intel_dp->aux.i2c_defer_count > 6) {
4063 /* Check EDID read for NACKs, DEFERs and corruption
4064 * (DP CTS 1.2 Core r1.1)
4065 * 4.2.2.4 : Failed EDID read, I2C_NAK
4066 * 4.2.2.5 : Failed EDID read, I2C_DEFER
4067 * 4.2.2.6 : EDID corruption detected
4068 * Use failsafe mode for all cases
4069 */
4070 if (intel_dp->aux.i2c_nack_count > 0 ||
4071 intel_dp->aux.i2c_defer_count > 0)
4072 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4073 intel_dp->aux.i2c_nack_count,
4074 intel_dp->aux.i2c_defer_count);
4075 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
4076 } else {
f79b468e
TS		 4077 struct edid *block = intel_connector->detect_edid;
4078
4079 /* We have to write the checksum
4080 * of the last block read
4081 */
4082 block += intel_connector->detect_edid->extensions;
4083
559be30c
TP		 4084 if (!drm_dp_dpcd_write(&intel_dp->aux,
4085 DP_TEST_EDID_CHECKSUM,
f79b468e 4086 &block->checksum,
5a1cc655 4087 1))
559be30c
TP		 4088 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4089
4090 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4091 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
4092 }
4093
4094 /* Set test active flag here so userspace doesn't interrupt things */
4095 intel_dp->compliance_test_active = 1;
4096
c5d5ab7a
TP		 4097 return test_result;
4098}
4099
4100static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 4101{
c5d5ab7a
TP		 4102 uint8_t test_result = DP_TEST_NAK;
4103 return test_result;
4104}
4105
4106static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4107{
4108 uint8_t response = DP_TEST_NAK;
4109 uint8_t rxdata = 0;
4110 int status = 0;
4111
c5d5ab7a
TP		 4112 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4113 if (status <= 0) {
4114 DRM_DEBUG_KMS("Could not read test request from sink\n");
4115 goto update_status;
4116 }
4117
4118 switch (rxdata) {
4119 case DP_TEST_LINK_TRAINING:
4120 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4121 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4122 response = intel_dp_autotest_link_training(intel_dp);
4123 break;
4124 case DP_TEST_LINK_VIDEO_PATTERN:
4125 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4126 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4127 response = intel_dp_autotest_video_pattern(intel_dp);
4128 break;
4129 case DP_TEST_LINK_EDID_READ:
4130 DRM_DEBUG_KMS("EDID test requested\n");
4131 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4132 response = intel_dp_autotest_edid(intel_dp);
4133 break;
4134 case DP_TEST_LINK_PHY_TEST_PATTERN:
4135 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4136 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4137 response = intel_dp_autotest_phy_pattern(intel_dp);
4138 break;
4139 default:
4140 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4141 break;
4142 }
4143
4144update_status:
4145 status = drm_dp_dpcd_write(&intel_dp->aux,
4146 DP_TEST_RESPONSE,
4147 &response, 1);
4148 if (status <= 0)
4149 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 4150}
4151
0e32b39c
DA		 4152static int
4153intel_dp_check_mst_status(struct intel_dp *intel_dp)
4154{
4155 bool bret;
4156
4157 if (intel_dp->is_mst) {
4158 u8 esi[16] = { 0 };
4159 int ret = 0;
4160 int retry;
4161 bool handled;
4162 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4163go_again:
4164 if (bret == true) {
4165
4166 /* check link status - esi[10] = 0x200c */
90a6b7b0 4167 if (intel_dp->active_mst_links &&
901c2daf 4168 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
0e32b39c
DA		 4169 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4170 intel_dp_start_link_train(intel_dp);
0e32b39c
DA		 4171 intel_dp_stop_link_train(intel_dp);
4172 }
4173
6f34cc39 4174 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 4175 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4176
4177 if (handled) {
4178 for (retry = 0; retry < 3; retry++) {
4179 int wret;
4180 wret = drm_dp_dpcd_write(&intel_dp->aux,
4181 DP_SINK_COUNT_ESI+1,
4182 &esi[1], 3);
4183 if (wret == 3) {
4184 break;
4185 }
4186 }
4187
4188 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4189 if (bret == true) {
6f34cc39 4190 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 4191 goto go_again;
4192 }
4193 } else
4194 ret = 0;
4195
4196 return ret;
4197 } else {
4198 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4199 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4200 intel_dp->is_mst = false;
4201 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4202 /* send a hotplug event */
4203 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4204 }
4205 }
4206 return -EINVAL;
4207}
4208
5c9114d0
SS		 4209static void
4210intel_dp_check_link_status(struct intel_dp *intel_dp)
4211{
4212 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4213 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4214 u8 link_status[DP_LINK_STATUS_SIZE];
4215
4216 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4217
4218 if (!intel_dp_get_link_status(intel_dp, link_status)) {
4219 DRM_ERROR("Failed to get link status\n");
4220 return;
4221 }
4222
4223 if (!intel_encoder->base.crtc)
4224 return;
4225
4226 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4227 return;
4228
4229 /* if link training is requested we should perform it always */
4230 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
4231 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
4232 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4233 intel_encoder->base.name);
4234 intel_dp_start_link_train(intel_dp);
4235 intel_dp_stop_link_train(intel_dp);
4236 }
4237}
4238
a4fc5ed6
KP		 4239/*
4240 * According to DP spec
4241 * 5.1.2:
4242 * 1. Read DPCD
4243 * 2. Configure link according to Receiver Capabilities
4244 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4245 * 4. Check link status on receipt of hot-plug interrupt
39ff747b
SS		 4246 *
4247 * intel_dp_short_pulse - handles short pulse interrupts
4248 * when full detection is not required.
4249 * Returns %true if short pulse is handled and full detection
4250 * is NOT required and %false otherwise.
a4fc5ed6 4251 */
39ff747b 4252static bool
5c9114d0 4253intel_dp_short_pulse(struct intel_dp *intel_dp)
a4fc5ed6 4254{
5b215bcf 4255 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a60f0e38 4256 u8 sink_irq_vector;
39ff747b
SS		 4257 u8 old_sink_count = intel_dp->sink_count;
4258 bool ret;
5b215bcf 4259
4df6960e
SS		 4260 /*
4261 * Clearing compliance test variables to allow capturing
4262 * of values for next automated test request.
4263 */
4264 intel_dp->compliance_test_active = 0;
4265 intel_dp->compliance_test_type = 0;
4266 intel_dp->compliance_test_data = 0;
4267
39ff747b
SS		 4268 /*
4269 * Now read the DPCD to see if it's actually running
4270 * If the current value of sink count doesn't match with
4271 * the value that was stored earlier or dpcd read failed
4272 * we need to do full detection
4273 */
4274 ret = intel_dp_get_dpcd(intel_dp);
4275
4276 if ((old_sink_count != intel_dp->sink_count) || !ret) {
4277 /* No need to proceed if we are going to do full detect */
4278 return false;
59cd09e1
JB		 4279 }
4280
a60f0e38
JB		 4281 /* Try to read the source of the interrupt */
4282 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4283 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4284 /* Clear interrupt source */
9d1a1031
JN		 4285 drm_dp_dpcd_writeb(&intel_dp->aux,
4286 DP_DEVICE_SERVICE_IRQ_VECTOR,
4287 sink_irq_vector);
a60f0e38
JB		 4288
4289 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
09b1eb13 4290 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
a60f0e38
JB		 4291 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4292 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4293 }
4294
5c9114d0
SS		 4295 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4296 intel_dp_check_link_status(intel_dp);
4297 drm_modeset_unlock(&dev->mode_config.connection_mutex);
39ff747b
SS		 4298
4299 return true;
a4fc5ed6 4300}
a4fc5ed6 4301
caf9ab24 4302/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4303static enum drm_connector_status
26d61aad 4304intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4305{
caf9ab24 4306 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4307 uint8_t type;
4308
4309 if (!intel_dp_get_dpcd(intel_dp))
4310 return connector_status_disconnected;
4311
4312 /* if there's no downstream port, we're done */
4313 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4314 return connector_status_connected;
caf9ab24
AJ		 4315
4316 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4317 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4318 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
9d1a1031 4319
30d9aa42
SS		 4320 return intel_dp->sink_count ?
4321 connector_status_connected : connector_status_disconnected;
caf9ab24
AJ		 4322 }
4323
4324 /* If no HPD, poke DDC gently */
0b99836f 4325 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4326 return connector_status_connected;
caf9ab24
AJ		 4327
4328 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4329 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4330 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4331 if (type == DP_DS_PORT_TYPE_VGA ||
4332 type == DP_DS_PORT_TYPE_NON_EDID)
4333 return connector_status_unknown;
4334 } else {
4335 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4336 DP_DWN_STRM_PORT_TYPE_MASK;
4337 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4338 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4339 return connector_status_unknown;
4340 }
caf9ab24
AJ		 4341
4342 /* Anything else is out of spec, warn and ignore */
4343 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4344 return connector_status_disconnected;
71ba9000
AJ		 4345}
4346
d410b56d
CW		 4347static enum drm_connector_status
4348edp_detect(struct intel_dp *intel_dp)
4349{
4350 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4351 enum drm_connector_status status;
4352
4353 status = intel_panel_detect(dev);
4354 if (status == connector_status_unknown)
4355 status = connector_status_connected;
4356
4357 return status;
4358}
4359
b93433cc
JN		 4360static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4361 struct intel_digital_port *port)
5eb08b69 4362{
b93433cc 4363 u32 bit;
01cb9ea6 4364
0df53b77
JN		 4365 switch (port->port) {
4366 case PORT_A:
4367 return true;
4368 case PORT_B:
4369 bit = SDE_PORTB_HOTPLUG;
4370 break;
4371 case PORT_C:
4372 bit = SDE_PORTC_HOTPLUG;
4373 break;
4374 case PORT_D:
4375 bit = SDE_PORTD_HOTPLUG;
4376 break;
4377 default:
4378 MISSING_CASE(port->port);
4379 return false;
4380 }
4381
4382 return I915_READ(SDEISR) & bit;
4383}
4384
4385static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4386 struct intel_digital_port *port)
4387{
4388 u32 bit;
4389
4390 switch (port->port) {
4391 case PORT_A:
4392 return true;
4393 case PORT_B:
4394 bit = SDE_PORTB_HOTPLUG_CPT;
4395 break;
4396 case PORT_C:
4397 bit = SDE_PORTC_HOTPLUG_CPT;
4398 break;
4399 case PORT_D:
4400 bit = SDE_PORTD_HOTPLUG_CPT;
4401 break;
a78695d3
JN		 4402 case PORT_E:
4403 bit = SDE_PORTE_HOTPLUG_SPT;
4404 break;
0df53b77
JN		 4405 default:
4406 MISSING_CASE(port->port);
4407 return false;
b93433cc 4408 }
1b469639 4409
b93433cc 4410 return I915_READ(SDEISR) & bit;
5eb08b69
ZW		 4411}
4412
7e66bcf2 4413static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
1d245987 4414 struct intel_digital_port *port)
a4fc5ed6 4415{
9642c81c 4416 u32 bit;
5eb08b69 4417
9642c81c
JN		 4418 switch (port->port) {
4419 case PORT_B:
4420 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4421 break;
4422 case PORT_C:
4423 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4424 break;
4425 case PORT_D:
4426 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4427 break;
4428 default:
4429 MISSING_CASE(port->port);
4430 return false;
4431 }
4432
4433 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4434}
4435
0780cd36
VS		 4436static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4437 struct intel_digital_port *port)
9642c81c
JN		 4438{
4439 u32 bit;
4440
4441 switch (port->port) {
4442 case PORT_B:
0780cd36 4443 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4444 break;
4445 case PORT_C:
0780cd36 4446 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4447 break;
4448 case PORT_D:
0780cd36 4449 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4450 break;
4451 default:
4452 MISSING_CASE(port->port);
4453 return false;
a4fc5ed6
KP		 4454 }
4455
1d245987 4456 return I915_READ(PORT_HOTPLUG_STAT) & bit;
2a592bec
DA		 4457}
4458
e464bfde 4459static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
e2ec35a5 4460 struct intel_digital_port *intel_dig_port)
e464bfde 4461{
e2ec35a5
SJ		 4462 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4463 enum port port;
e464bfde
JN		 4464 u32 bit;
4465
e2ec35a5
SJ		 4466 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4467 switch (port) {
e464bfde
JN		 4468 case PORT_A:
4469 bit = BXT_DE_PORT_HP_DDIA;
4470 break;
4471 case PORT_B:
4472 bit = BXT_DE_PORT_HP_DDIB;
4473 break;
4474 case PORT_C:
4475 bit = BXT_DE_PORT_HP_DDIC;
4476 break;
4477 default:
e2ec35a5 4478 MISSING_CASE(port);
e464bfde
JN		 4479 return false;
4480 }
4481
4482 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4483}
4484
7e66bcf2
JN		 4485/*
4486 * intel_digital_port_connected - is the specified port connected?
4487 * @dev_priv: i915 private structure
4488 * @port: the port to test
4489 *
4490 * Return %true if @port is connected, %false otherwise.
4491 */
237ed86c 4492bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
7e66bcf2
JN		 4493 struct intel_digital_port *port)
4494{
0df53b77 4495 if (HAS_PCH_IBX(dev_priv))
7e66bcf2 4496 return ibx_digital_port_connected(dev_priv, port);
22824fac 4497 else if (HAS_PCH_SPLIT(dev_priv))
0df53b77 4498 return cpt_digital_port_connected(dev_priv, port);
e464bfde
JN		 4499 else if (IS_BROXTON(dev_priv))
4500 return bxt_digital_port_connected(dev_priv, port);
0780cd36
VS		 4501 else if (IS_GM45(dev_priv))
4502 return gm45_digital_port_connected(dev_priv, port);
7e66bcf2
JN		 4503 else
4504 return g4x_digital_port_connected(dev_priv, port);
4505}
4506
8c241fef 4507static struct edid *
beb60608 4508intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4509{
beb60608 4510 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4511
9cd300e0
JN		 4512 /* use cached edid if we have one */
4513 if (intel_connector->edid) {
9cd300e0
JN		 4514 /* invalid edid */
4515 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4516 return NULL;
4517
55e9edeb 4518 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4519 } else
4520 return drm_get_edid(&intel_connector->base,
4521 &intel_dp->aux.ddc);
4522}
8c241fef 4523
beb60608
CW		 4524static void
4525intel_dp_set_edid(struct intel_dp *intel_dp)
4526{
4527 struct intel_connector *intel_connector = intel_dp->attached_connector;
4528 struct edid *edid;
8c241fef 4529
f21a2198 4530 intel_dp_unset_edid(intel_dp);
beb60608
CW		 4531 edid = intel_dp_get_edid(intel_dp);
4532 intel_connector->detect_edid = edid;
4533
4534 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4535 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4536 else
4537 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4538}
4539
beb60608
CW		 4540static void
4541intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4542{
beb60608 4543 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4544
beb60608
CW		 4545 kfree(intel_connector->detect_edid);
4546 intel_connector->detect_edid = NULL;
9cd300e0 4547
beb60608
CW		 4548 intel_dp->has_audio = false;
4549}
d6f24d0f 4550
f21a2198
SS		 4551static void
4552intel_dp_long_pulse(struct intel_connector *intel_connector)
a9756bb5 4553{
f21a2198 4554 struct drm_connector *connector = &intel_connector->base;
a9756bb5 4555 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4556 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4557 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4558 struct drm_device *dev = connector->dev;
a9756bb5 4559 enum drm_connector_status status;
671dedd2 4560 enum intel_display_power_domain power_domain;
0e32b39c 4561 bool ret;
09b1eb13 4562 u8 sink_irq_vector;
a9756bb5 4563
25f78f58
VS		 4564 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4565 intel_display_power_get(to_i915(dev), power_domain);
a9756bb5 4566
d410b56d
CW		 4567 /* Can't disconnect eDP, but you can close the lid... */
4568 if (is_edp(intel_dp))
4569 status = edp_detect(intel_dp);
c555a81d
ACO		 4570 else if (intel_digital_port_connected(to_i915(dev),
4571 dp_to_dig_port(intel_dp)))
4572 status = intel_dp_detect_dpcd(intel_dp);
a9756bb5 4573 else
c555a81d
ACO		 4574 status = connector_status_disconnected;
4575
4df6960e
SS		 4576 if (status != connector_status_connected) {
4577 intel_dp->compliance_test_active = 0;
4578 intel_dp->compliance_test_type = 0;
4579 intel_dp->compliance_test_data = 0;
4580
0e505a08 4581 if (intel_dp->is_mst) {
4582 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4583 intel_dp->is_mst,
4584 intel_dp->mst_mgr.mst_state);
4585 intel_dp->is_mst = false;
4586 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4587 intel_dp->is_mst);
4588 }
4589
c8c8fb33 4590 goto out;
4df6960e 4591 }
a9756bb5 4592
f21a2198
SS		 4593 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4594 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4595
0d198328
AJ		 4596 intel_dp_probe_oui(intel_dp);
4597
0e32b39c
DA		 4598 ret = intel_dp_probe_mst(intel_dp);
4599 if (ret) {
f21a2198
SS		 4600 /*
4601 * If we are in MST mode then this connector
4602 * won't appear connected or have anything
4603 * with EDID on it
4604 */
0e32b39c
DA		 4605 status = connector_status_disconnected;
4606 goto out;
7d23e3c3
SS		 4607 } else if (connector->status == connector_status_connected) {
4608 /*
4609 * If display was connected already and is still connected
4610 * check links status, there has been known issues of
4611 * link loss triggerring long pulse!!!!
4612 */
4613 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4614 intel_dp_check_link_status(intel_dp);
4615 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4616 goto out;
0e32b39c
DA		 4617 }
4618
4df6960e
SS		 4619 /*
4620 * Clearing NACK and defer counts to get their exact values
4621 * while reading EDID which are required by Compliance tests
4622 * 4.2.2.4 and 4.2.2.5
4623 */
4624 intel_dp->aux.i2c_nack_count = 0;
4625 intel_dp->aux.i2c_defer_count = 0;
4626
beb60608 4627 intel_dp_set_edid(intel_dp);
a9756bb5 4628
c8c8fb33 4629 status = connector_status_connected;
7d23e3c3 4630 intel_dp->detect_done = true;
c8c8fb33 4631
09b1eb13
TP		 4632 /* Try to read the source of the interrupt */
4633 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4634 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4635 /* Clear interrupt source */
4636 drm_dp_dpcd_writeb(&intel_dp->aux,
4637 DP_DEVICE_SERVICE_IRQ_VECTOR,
4638 sink_irq_vector);
4639
4640 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4641 intel_dp_handle_test_request(intel_dp);
4642 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4643 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4644 }
4645
c8c8fb33 4646out:
0e505a08 4647 if ((status != connector_status_connected) &&
4648 (intel_dp->is_mst == false))
f21a2198 4649 intel_dp_unset_edid(intel_dp);
7d23e3c3 4650
25f78f58 4651 intel_display_power_put(to_i915(dev), power_domain);
f21a2198
SS		 4652 return;
4653}
4654
4655static enum drm_connector_status
4656intel_dp_detect(struct drm_connector *connector, bool force)
4657{
4658 struct intel_dp *intel_dp = intel_attached_dp(connector);
4659 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4660 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4661 struct intel_connector *intel_connector = to_intel_connector(connector);
4662
4663 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4664 connector->base.id, connector->name);
4665
4666 if (intel_dp->is_mst) {
4667 /* MST devices are disconnected from a monitor POV */
4668 intel_dp_unset_edid(intel_dp);
4669 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4670 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4671 return connector_status_disconnected;
4672 }
4673
7d23e3c3
SS		 4674 /* If full detect is not performed yet, do a full detect */
4675 if (!intel_dp->detect_done)
4676 intel_dp_long_pulse(intel_dp->attached_connector);
4677
4678 intel_dp->detect_done = false;
f21a2198
SS		 4679
4680 if (intel_connector->detect_edid)
4681 return connector_status_connected;
4682 else
4683 return connector_status_disconnected;
a4fc5ed6
KP		 4684}
4685
beb60608
CW		 4686static void
4687intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4688{
df0e9248 4689 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4690 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
25f78f58 4691 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
671dedd2 4692 enum intel_display_power_domain power_domain;
a4fc5ed6 4693
beb60608
CW		 4694 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4695 connector->base.id, connector->name);
4696 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4697
beb60608
CW		 4698 if (connector->status != connector_status_connected)
4699 return;
671dedd2 4700
25f78f58
VS		 4701 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4702 intel_display_power_get(dev_priv, power_domain);
beb60608
CW		 4703
4704 intel_dp_set_edid(intel_dp);
4705
25f78f58 4706 intel_display_power_put(dev_priv, power_domain);
beb60608
CW		 4707
4708 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4709 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4710}
4711
4712static int intel_dp_get_modes(struct drm_connector *connector)
4713{
4714 struct intel_connector *intel_connector = to_intel_connector(connector);
4715 struct edid *edid;
4716
4717 edid = intel_connector->detect_edid;
4718 if (edid) {
4719 int ret = intel_connector_update_modes(connector, edid);
4720 if (ret)
4721 return ret;
4722 }
32f9d658 4723
f8779fda 4724 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4725 if (is_edp(intel_attached_dp(connector)) &&
4726 intel_connector->panel.fixed_mode) {
f8779fda 4727 struct drm_display_mode *mode;
beb60608
CW		 4728
4729 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4730 intel_connector->panel.fixed_mode);
f8779fda 4731 if (mode) {
32f9d658
ZW		 4732 drm_mode_probed_add(connector, mode);
4733 return 1;
4734 }
4735 }
beb60608 4736
32f9d658 4737 return 0;
a4fc5ed6
KP		 4738}
4739
1aad7ac0
CW		 4740static bool
4741intel_dp_detect_audio(struct drm_connector *connector)
4742{
1aad7ac0 4743 bool has_audio = false;
beb60608 4744 struct edid *edid;
1aad7ac0 4745
beb60608
CW		 4746 edid = to_intel_connector(connector)->detect_edid;
4747 if (edid)
1aad7ac0 4748 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4749
1aad7ac0
CW		 4750 return has_audio;
4751}
4752
f684960e
CW		 4753static int
4754intel_dp_set_property(struct drm_connector *connector,
4755 struct drm_property *property,
4756 uint64_t val)
4757{
e953fd7b 4758 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4759 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4760 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4761 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4762 int ret;
4763
662595df 4764 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4765 if (ret)
4766 return ret;
4767
3f43c48d 4768 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4769 int i = val;
4770 bool has_audio;
4771
4772 if (i == intel_dp->force_audio)
f684960e
CW		 4773 return 0;
4774
1aad7ac0 4775 intel_dp->force_audio = i;
f684960e 4776
c3e5f67b 4777 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4778 has_audio = intel_dp_detect_audio(connector);
4779 else
c3e5f67b 4780 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4781
4782 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4783 return 0;
4784
1aad7ac0 4785 intel_dp->has_audio = has_audio;
f684960e
CW		 4786 goto done;
4787 }
4788
e953fd7b 4789 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80 4790 bool old_auto = intel_dp->color_range_auto;
0f2a2a75 4791 bool old_range = intel_dp->limited_color_range;
ae4edb80 4792
55bc60db
VS		 4793 switch (val) {
4794 case INTEL_BROADCAST_RGB_AUTO:
4795 intel_dp->color_range_auto = true;
4796 break;
4797 case INTEL_BROADCAST_RGB_FULL:
4798 intel_dp->color_range_auto = false;
0f2a2a75 4799 intel_dp->limited_color_range = false;
55bc60db
VS		 4800 break;
4801 case INTEL_BROADCAST_RGB_LIMITED:
4802 intel_dp->color_range_auto = false;
0f2a2a75 4803 intel_dp->limited_color_range = true;
55bc60db
VS		 4804 break;
4805 default:
4806 return -EINVAL;
4807 }
ae4edb80
DV		 4808
4809 if (old_auto == intel_dp->color_range_auto &&
0f2a2a75 4810 old_range == intel_dp->limited_color_range)
ae4edb80
DV		 4811 return 0;
4812
e953fd7b
CW		 4813 goto done;
4814 }
4815
53b41837
YN		 4816 if (is_edp(intel_dp) &&
4817 property == connector->dev->mode_config.scaling_mode_property) {
4818 if (val == DRM_MODE_SCALE_NONE) {
4819 DRM_DEBUG_KMS("no scaling not supported\n");
4820 return -EINVAL;
4821 }
234126c6
VS		 4822 if (HAS_GMCH_DISPLAY(dev_priv) &&
4823 val == DRM_MODE_SCALE_CENTER) {
4824 DRM_DEBUG_KMS("centering not supported\n");
4825 return -EINVAL;
4826 }
53b41837
YN		 4827
4828 if (intel_connector->panel.fitting_mode == val) {
4829 /* the eDP scaling property is not changed */
4830 return 0;
4831 }
4832 intel_connector->panel.fitting_mode = val;
4833
4834 goto done;
4835 }
4836
f684960e
CW		 4837 return -EINVAL;
4838
4839done:
c0c36b94
CW		 4840 if (intel_encoder->base.crtc)
4841 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4842
4843 return 0;
4844}
4845
a4fc5ed6 4846static void
73845adf 4847intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4848{
1d508706 4849 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4850
10e972d3 4851 kfree(intel_connector->detect_edid);
beb60608 4852
9cd300e0
JN		 4853 if (!IS_ERR_OR_NULL(intel_connector->edid))
4854 kfree(intel_connector->edid);
4855
acd8db10
PZ		 4856 /* Can't call is_edp() since the encoder may have been destroyed
4857 * already. */
4858 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4859 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4860
a4fc5ed6 4861 drm_connector_cleanup(connector);
55f78c43 4862 kfree(connector);
a4fc5ed6
KP		 4863}
4864
00c09d70 4865void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4866{
da63a9f2
PZ		 4867 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4868 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4869
0e32b39c 4870 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4871 if (is_edp(intel_dp)) {
4872 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4873 /*
4874 * vdd might still be enabled do to the delayed vdd off.
4875 * Make sure vdd is actually turned off here.
4876 */
773538e8 4877 pps_lock(intel_dp);
4be73780 4878 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4879 pps_unlock(intel_dp);
4880
01527b31
CT		 4881 if (intel_dp->edp_notifier.notifier_call) {
4882 unregister_reboot_notifier(&intel_dp->edp_notifier);
4883 intel_dp->edp_notifier.notifier_call = NULL;
4884 }
bd943159 4885 }
c8bd0e49 4886 drm_encoder_cleanup(encoder);
da63a9f2 4887 kfree(intel_dig_port);
24d05927
DV		 4888}
4889
bf93ba67 4890void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
07f9cd0b
ID		 4891{
4892 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4893
4894 if (!is_edp(intel_dp))
4895 return;
4896
951468f3
VS		 4897 /*
4898 * vdd might still be enabled do to the delayed vdd off.
4899 * Make sure vdd is actually turned off here.
4900 */
afa4e53a 4901 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4902 pps_lock(intel_dp);
07f9cd0b 4903 edp_panel_vdd_off_sync(intel_dp);
773538e8 4904 pps_unlock(intel_dp);
07f9cd0b
ID		 4905}
4906
49e6bc51
VS		 4907static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4908{
4909 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4910 struct drm_device *dev = intel_dig_port->base.base.dev;
4911 struct drm_i915_private *dev_priv = dev->dev_private;
4912 enum intel_display_power_domain power_domain;
4913
4914 lockdep_assert_held(&dev_priv->pps_mutex);
4915
4916 if (!edp_have_panel_vdd(intel_dp))
4917 return;
4918
4919 /*
4920 * The VDD bit needs a power domain reference, so if the bit is
4921 * already enabled when we boot or resume, grab this reference and
4922 * schedule a vdd off, so we don't hold on to the reference
4923 * indefinitely.
4924 */
4925 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
25f78f58 4926 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
49e6bc51
VS		 4927 intel_display_power_get(dev_priv, power_domain);
4928
4929 edp_panel_vdd_schedule_off(intel_dp);
4930}
4931
bf93ba67 4932void intel_dp_encoder_reset(struct drm_encoder *encoder)
6d93c0c4 4933{
49e6bc51
VS		 4934 struct intel_dp *intel_dp;
4935
4936 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4937 return;
4938
4939 intel_dp = enc_to_intel_dp(encoder);
4940
4941 pps_lock(intel_dp);
4942
4943 /*
4944 * Read out the current power sequencer assignment,
4945 * in case the BIOS did something with it.
4946 */
666a4537 4947 if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
49e6bc51
VS		 4948 vlv_initial_power_sequencer_setup(intel_dp);
4949
4950 intel_edp_panel_vdd_sanitize(intel_dp);
4951
4952 pps_unlock(intel_dp);
6d93c0c4
ID		 4953}
4954
a4fc5ed6 4955static const struct drm_connector_funcs intel_dp_connector_funcs = {
4d688a2a 4956 .dpms = drm_atomic_helper_connector_dpms,
a4fc5ed6 4957 .detect = intel_dp_detect,
beb60608 4958 .force = intel_dp_force,
a4fc5ed6 4959 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4960 .set_property = intel_dp_set_property,
2545e4a6 4961 .atomic_get_property = intel_connector_atomic_get_property,
73845adf 4962 .destroy = intel_dp_connector_destroy,
c6f95f27 4963 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4964 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4965};
4966
4967static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4968 .get_modes = intel_dp_get_modes,
4969 .mode_valid = intel_dp_mode_valid,
df0e9248 4970 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4971};
4972
a4fc5ed6 4973static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4974 .reset = intel_dp_encoder_reset,
24d05927 4975 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4976};
4977
b2c5c181 4978enum irqreturn
13cf5504
DA		 4979intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4980{
4981 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4982 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4983 struct drm_device *dev = intel_dig_port->base.base.dev;
4984 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33 4985 enum intel_display_power_domain power_domain;
b2c5c181 4986 enum irqreturn ret = IRQ_NONE;
1c767b33 4987
2540058f
TI		 4988 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4989 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
0e32b39c 4990 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4991
7a7f84cc
VS		 4992 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4993 /*
4994 * vdd off can generate a long pulse on eDP which
4995 * would require vdd on to handle it, and thus we
4996 * would end up in an endless cycle of
4997 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4998 */
4999 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5000 port_name(intel_dig_port->port));
a8b3d52f 5001 return IRQ_HANDLED;
7a7f84cc
VS		 5002 }
5003
26fbb774
VS		 5004 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5005 port_name(intel_dig_port->port),
0e32b39c 5006 long_hpd ? "long" : "short");
13cf5504 5007
25f78f58 5008 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1c767b33
ID		 5009 intel_display_power_get(dev_priv, power_domain);
5010
0e32b39c 5011 if (long_hpd) {
5fa836a9
MK		 5012 /* indicate that we need to restart link training */
5013 intel_dp->train_set_valid = false;
2a592bec 5014
7d23e3c3
SS		 5015 intel_dp_long_pulse(intel_dp->attached_connector);
5016 if (intel_dp->is_mst)
5017 ret = IRQ_HANDLED;
5018 goto put_power;
0e32b39c 5019
0e32b39c
DA		 5020 } else {
5021 if (intel_dp->is_mst) {
7d23e3c3
SS		 5022 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5023 /*
5024 * If we were in MST mode, and device is not
5025 * there, get out of MST mode
5026 */
5027 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5028 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5029 intel_dp->is_mst = false;
5030 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5031 intel_dp->is_mst);
5032 goto put_power;
5033 }
0e32b39c
DA		 5034 }
5035
39ff747b
SS		 5036 if (!intel_dp->is_mst) {
5037 if (!intel_dp_short_pulse(intel_dp)) {
5038 intel_dp_long_pulse(intel_dp->attached_connector);
5039 goto put_power;
5040 }
5041 }
0e32b39c 5042 }
b2c5c181
DV		 5043
5044 ret = IRQ_HANDLED;
5045
1c767b33
ID		 5046put_power:
5047 intel_display_power_put(dev_priv, power_domain);
5048
5049 return ret;
13cf5504
DA		 5050}
5051
477ec328 5052/* check the VBT to see whether the eDP is on another port */
5d8a7752 5053bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 5054{
5055 struct drm_i915_private *dev_priv = dev->dev_private;
36e83a18 5056
53ce81a7
VS		 5057 /*
5058 * eDP not supported on g4x. so bail out early just
5059 * for a bit extra safety in case the VBT is bonkers.
5060 */
5061 if (INTEL_INFO(dev)->gen < 5)
5062 return false;
5063
3b32a35b
VS		 5064 if (port == PORT_A)
5065 return true;
5066
951d9efe 5067 return intel_bios_is_port_edp(dev_priv, port);
36e83a18
ZY		 5068}
5069
0e32b39c 5070void
f684960e
CW		 5071intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5072{
53b41837
YN		 5073 struct intel_connector *intel_connector = to_intel_connector(connector);
5074
3f43c48d 5075 intel_attach_force_audio_property(connector);
e953fd7b 5076 intel_attach_broadcast_rgb_property(connector);
55bc60db 5077 intel_dp->color_range_auto = true;
53b41837
YN		 5078
5079 if (is_edp(intel_dp)) {
5080 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 5081 drm_object_attach_property(
5082 &connector->base,
53b41837 5083 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 5084 DRM_MODE_SCALE_ASPECT);
5085 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 5086 }
f684960e
CW		 5087}
5088
dada1a9f
ID		 5089static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5090{
d28d4731 5091 intel_dp->panel_power_off_time = ktime_get_boottime();
dada1a9f
ID		 5092 intel_dp->last_power_on = jiffies;
5093 intel_dp->last_backlight_off = jiffies;
5094}
5095
67a54566
DV		 5096static void
5097intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 5098 struct intel_dp *intel_dp)
67a54566
DV		 5099{
5100 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 5101 struct edp_power_seq cur, vbt, spec,
5102 *final = &intel_dp->pps_delays;
b0a08bec 5103 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
f0f59a00 5104 i915_reg_t pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 5105
e39b999a
VS		 5106 lockdep_assert_held(&dev_priv->pps_mutex);
5107
81ddbc69
VS		 5108 /* already initialized? */
5109 if (final->t11_t12 != 0)
5110 return;
5111
b0a08bec
VK		 5112 if (IS_BROXTON(dev)) {
5113 /*
5114 * TODO: BXT has 2 sets of PPS registers.
5115 * Correct Register for Broxton need to be identified
5116 * using VBT. hardcoding for now
5117 */
5118 pp_ctrl_reg = BXT_PP_CONTROL(0);
5119 pp_on_reg = BXT_PP_ON_DELAYS(0);
5120 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5121 } else if (HAS_PCH_SPLIT(dev)) {
bf13e81b 5122 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 5123 pp_on_reg = PCH_PP_ON_DELAYS;
5124 pp_off_reg = PCH_PP_OFF_DELAYS;
5125 pp_div_reg = PCH_PP_DIVISOR;
5126 } else {
bf13e81b
JN		 5127 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5128
5129 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
5130 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5131 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5132 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 5133 }
67a54566
DV		 5134
5135 /* Workaround: Need to write PP_CONTROL with the unlock key as
5136 * the very first thing. */
b0a08bec 5137 pp_ctl = ironlake_get_pp_control(intel_dp);
67a54566 5138
453c5420
JB		 5139 pp_on = I915_READ(pp_on_reg);
5140 pp_off = I915_READ(pp_off_reg);
b0a08bec
VK		 5141 if (!IS_BROXTON(dev)) {
5142 I915_WRITE(pp_ctrl_reg, pp_ctl);
5143 pp_div = I915_READ(pp_div_reg);
5144 }
67a54566
DV		 5145
5146 /* Pull timing values out of registers */
5147 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5148 PANEL_POWER_UP_DELAY_SHIFT;
5149
5150 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5151 PANEL_LIGHT_ON_DELAY_SHIFT;
5152
5153 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5154 PANEL_LIGHT_OFF_DELAY_SHIFT;
5155
5156 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5157 PANEL_POWER_DOWN_DELAY_SHIFT;
5158
b0a08bec
VK		 5159 if (IS_BROXTON(dev)) {
5160 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5161 BXT_POWER_CYCLE_DELAY_SHIFT;
5162 if (tmp > 0)
5163 cur.t11_t12 = (tmp - 1) * 1000;
5164 else
5165 cur.t11_t12 = 0;
5166 } else {
5167 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
67a54566 5168 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
b0a08bec 5169 }
67a54566
DV		 5170
5171 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5172 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5173
6aa23e65 5174 vbt = dev_priv->vbt.edp.pps;
67a54566
DV		 5175
5176 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5177 * our hw here, which are all in 100usec. */
5178 spec.t1_t3 = 210 * 10;
5179 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5180 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5181 spec.t10 = 500 * 10;
5182 /* This one is special and actually in units of 100ms, but zero
5183 * based in the hw (so we need to add 100 ms). But the sw vbt
5184 * table multiplies it with 1000 to make it in units of 100usec,
5185 * too. */
5186 spec.t11_t12 = (510 + 100) * 10;
5187
5188 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5189 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5190
5191 /* Use the max of the register settings and vbt. If both are
5192 * unset, fall back to the spec limits. */
36b5f425 5193#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 5194 spec.field : \
5195 max(cur.field, vbt.field))
5196 assign_final(t1_t3);
5197 assign_final(t8);
5198 assign_final(t9);
5199 assign_final(t10);
5200 assign_final(t11_t12);
5201#undef assign_final
5202
36b5f425 5203#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 5204 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5205 intel_dp->backlight_on_delay = get_delay(t8);
5206 intel_dp->backlight_off_delay = get_delay(t9);
5207 intel_dp->panel_power_down_delay = get_delay(t10);
5208 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5209#undef get_delay
5210
f30d26e4
JN		 5211 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5212 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5213 intel_dp->panel_power_cycle_delay);
5214
5215 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5216 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 5217}
5218
5219static void
5220intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 5221 struct intel_dp *intel_dp)
f30d26e4
JN		 5222{
5223 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 5224 u32 pp_on, pp_off, pp_div, port_sel = 0;
e7dc33f3 5225 int div = dev_priv->rawclk_freq / 1000;
f0f59a00 5226 i915_reg_t pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg;
ad933b56 5227 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 5228 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 5229
e39b999a 5230 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420 5231
b0a08bec
VK		 5232 if (IS_BROXTON(dev)) {
5233 /*
5234 * TODO: BXT has 2 sets of PPS registers.
5235 * Correct Register for Broxton need to be identified
5236 * using VBT. hardcoding for now
5237 */
5238 pp_ctrl_reg = BXT_PP_CONTROL(0);
5239 pp_on_reg = BXT_PP_ON_DELAYS(0);
5240 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5241
5242 } else if (HAS_PCH_SPLIT(dev)) {
453c5420
JB		 5243 pp_on_reg = PCH_PP_ON_DELAYS;
5244 pp_off_reg = PCH_PP_OFF_DELAYS;
5245 pp_div_reg = PCH_PP_DIVISOR;
5246 } else {
bf13e81b
JN		 5247 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5248
5249 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5250 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5251 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 5252 }
5253
b2f19d1a
PZ		 5254 /*
5255 * And finally store the new values in the power sequencer. The
5256 * backlight delays are set to 1 because we do manual waits on them. For
5257 * T8, even BSpec recommends doing it. For T9, if we don't do this,
5258 * we'll end up waiting for the backlight off delay twice: once when we
5259 * do the manual sleep, and once when we disable the panel and wait for
5260 * the PP_STATUS bit to become zero.
5261 */
f30d26e4 5262 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 5263 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5264 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 5265 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 5266 /* Compute the divisor for the pp clock, simply match the Bspec
5267 * formula. */
b0a08bec
VK		 5268 if (IS_BROXTON(dev)) {
5269 pp_div = I915_READ(pp_ctrl_reg);
5270 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5271 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5272 << BXT_POWER_CYCLE_DELAY_SHIFT);
5273 } else {
5274 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5275 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5276 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5277 }
67a54566
DV		 5278
5279 /* Haswell doesn't have any port selection bits for the panel
5280 * power sequencer any more. */
666a4537 5281 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
ad933b56 5282 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 5283 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 5284 if (port == PORT_A)
a24c144c 5285 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 5286 else
a24c144c 5287 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 5288 }
5289
453c5420
JB		 5290 pp_on |= port_sel;
5291
5292 I915_WRITE(pp_on_reg, pp_on);
5293 I915_WRITE(pp_off_reg, pp_off);
b0a08bec
VK		 5294 if (IS_BROXTON(dev))
5295 I915_WRITE(pp_ctrl_reg, pp_div);
5296 else
5297 I915_WRITE(pp_div_reg, pp_div);
67a54566 5298
67a54566 5299 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 5300 I915_READ(pp_on_reg),
5301 I915_READ(pp_off_reg),
b0a08bec
VK		 5302 IS_BROXTON(dev) ?
5303 (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
453c5420 5304 I915_READ(pp_div_reg));
f684960e
CW		 5305}
5306
b33a2815
VK		 5307/**
5308 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5309 * @dev: DRM device
5310 * @refresh_rate: RR to be programmed
5311 *
5312 * This function gets called when refresh rate (RR) has to be changed from
5313 * one frequency to another. Switches can be between high and low RR
5314 * supported by the panel or to any other RR based on media playback (in
5315 * this case, RR value needs to be passed from user space).
5316 *
5317 * The caller of this function needs to take a lock on dev_priv->drrs.
5318 */
96178eeb 5319static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
439d7ac0
PB		 5320{
5321 struct drm_i915_private *dev_priv = dev->dev_private;
5322 struct intel_encoder *encoder;
96178eeb
VK		 5323 struct intel_digital_port *dig_port = NULL;
5324 struct intel_dp *intel_dp = dev_priv->drrs.dp;
5cec258b 5325 struct intel_crtc_state *config = NULL;
439d7ac0 5326 struct intel_crtc *intel_crtc = NULL;
96178eeb 5327 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 5328
5329 if (refresh_rate <= 0) {
5330 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5331 return;
5332 }
5333
96178eeb
VK		 5334 if (intel_dp == NULL) {
5335 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 5336 return;
5337 }
5338
1fcc9d1c 5339 /*
e4d59f6b
RV		 5340 * FIXME: This needs proper synchronization with psr state for some
5341 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 5342 */
439d7ac0 5343
96178eeb
VK		 5344 dig_port = dp_to_dig_port(intel_dp);
5345 encoder = &dig_port->base;
723f9aab 5346 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 5347
5348 if (!intel_crtc) {
5349 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5350 return;
5351 }
5352
6e3c9717 5353 config = intel_crtc->config;
439d7ac0 5354
96178eeb 5355 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 5356 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5357 return;
5358 }
5359
96178eeb
VK		 5360 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5361 refresh_rate)
439d7ac0
PB		 5362 index = DRRS_LOW_RR;
5363
96178eeb 5364 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5365 DRM_DEBUG_KMS(
5366 "DRRS requested for previously set RR...ignoring\n");
5367 return;
5368 }
5369
5370 if (!intel_crtc->active) {
5371 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5372 return;
5373 }
5374
44395bfe 5375 if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
a4c30b1d
VK		 5376 switch (index) {
5377 case DRRS_HIGH_RR:
5378 intel_dp_set_m_n(intel_crtc, M1_N1);
5379 break;
5380 case DRRS_LOW_RR:
5381 intel_dp_set_m_n(intel_crtc, M2_N2);
5382 break;
5383 case DRRS_MAX_RR:
5384 default:
5385 DRM_ERROR("Unsupported refreshrate type\n");
5386 }
5387 } else if (INTEL_INFO(dev)->gen > 6) {
f0f59a00 5388 i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder);
649636ef 5389 u32 val;
a4c30b1d 5390
649636ef 5391 val = I915_READ(reg);
439d7ac0 5392 if (index > DRRS_HIGH_RR) {
666a4537 5393 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
6fa7aec1
VK		 5394 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5395 else
5396 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5397 } else {
666a4537 5398 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
6fa7aec1
VK		 5399 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5400 else
5401 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5402 }
5403 I915_WRITE(reg, val);
5404 }
5405
4e9ac947
VK		 5406 dev_priv->drrs.refresh_rate_type = index;
5407
5408 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5409}
5410
b33a2815
VK		 5411/**
5412 * intel_edp_drrs_enable - init drrs struct if supported
5413 * @intel_dp: DP struct
5414 *
5415 * Initializes frontbuffer_bits and drrs.dp
5416 */
c395578e
VK		 5417void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5418{
5419 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5420 struct drm_i915_private *dev_priv = dev->dev_private;
5421 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5422 struct drm_crtc *crtc = dig_port->base.base.crtc;
5423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5424
5425 if (!intel_crtc->config->has_drrs) {
5426 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5427 return;
5428 }
5429
5430 mutex_lock(&dev_priv->drrs.mutex);
5431 if (WARN_ON(dev_priv->drrs.dp)) {
5432 DRM_ERROR("DRRS already enabled\n");
5433 goto unlock;
5434 }
5435
5436 dev_priv->drrs.busy_frontbuffer_bits = 0;
5437
5438 dev_priv->drrs.dp = intel_dp;
5439
5440unlock:
5441 mutex_unlock(&dev_priv->drrs.mutex);
5442}
5443
b33a2815
VK		 5444/**
5445 * intel_edp_drrs_disable - Disable DRRS
5446 * @intel_dp: DP struct
5447 *
5448 */
c395578e
VK		 5449void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5450{
5451 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5452 struct drm_i915_private *dev_priv = dev->dev_private;
5453 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5454 struct drm_crtc *crtc = dig_port->base.base.crtc;
5455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5456
5457 if (!intel_crtc->config->has_drrs)
5458 return;
5459
5460 mutex_lock(&dev_priv->drrs.mutex);
5461 if (!dev_priv->drrs.dp) {
5462 mutex_unlock(&dev_priv->drrs.mutex);
5463 return;
5464 }
5465
5466 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5467 intel_dp_set_drrs_state(dev_priv->dev,
5468 intel_dp->attached_connector->panel.
5469 fixed_mode->vrefresh);
5470
5471 dev_priv->drrs.dp = NULL;
5472 mutex_unlock(&dev_priv->drrs.mutex);
5473
5474 cancel_delayed_work_sync(&dev_priv->drrs.work);
5475}
5476
4e9ac947
VK		 5477static void intel_edp_drrs_downclock_work(struct work_struct *work)
5478{
5479 struct drm_i915_private *dev_priv =
5480 container_of(work, typeof(*dev_priv), drrs.work.work);
5481 struct intel_dp *intel_dp;
5482
5483 mutex_lock(&dev_priv->drrs.mutex);
5484
5485 intel_dp = dev_priv->drrs.dp;
5486
5487 if (!intel_dp)
5488 goto unlock;
5489
439d7ac0 5490 /*
4e9ac947
VK		 5491 * The delayed work can race with an invalidate hence we need to
5492 * recheck.
439d7ac0
PB		 5493 */
5494
4e9ac947
VK		 5495 if (dev_priv->drrs.busy_frontbuffer_bits)
5496 goto unlock;
439d7ac0 5497
4e9ac947
VK		 5498 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5499 intel_dp_set_drrs_state(dev_priv->dev,
5500 intel_dp->attached_connector->panel.
5501 downclock_mode->vrefresh);
439d7ac0 5502
4e9ac947 5503unlock:
4e9ac947 5504 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5505}
5506
b33a2815 5507/**
0ddfd203 5508 * intel_edp_drrs_invalidate - Disable Idleness DRRS
b33a2815
VK		 5509 * @dev: DRM device
5510 * @frontbuffer_bits: frontbuffer plane tracking bits
5511 *
0ddfd203
R		 5512 * This function gets called everytime rendering on the given planes start.
5513 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
b33a2815
VK		 5514 *
5515 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5516 */
a93fad0f
VK		 5517void intel_edp_drrs_invalidate(struct drm_device *dev,
5518 unsigned frontbuffer_bits)
5519{
5520 struct drm_i915_private *dev_priv = dev->dev_private;
5521 struct drm_crtc *crtc;
5522 enum pipe pipe;
5523
9da7d693 5524 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5525 return;
5526
88f933a8 5527 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5528
a93fad0f 5529 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5530 if (!dev_priv->drrs.dp) {
5531 mutex_unlock(&dev_priv->drrs.mutex);
5532 return;
5533 }
5534
a93fad0f
VK		 5535 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5536 pipe = to_intel_crtc(crtc)->pipe;
5537
c1d038c6
DV		 5538 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5539 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5540
0ddfd203 5541 /* invalidate means busy screen hence upclock */
c1d038c6 5542 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
a93fad0f
VK		 5543 intel_dp_set_drrs_state(dev_priv->dev,
5544 dev_priv->drrs.dp->attached_connector->panel.
5545 fixed_mode->vrefresh);
a93fad0f 5546
a93fad0f
VK		 5547 mutex_unlock(&dev_priv->drrs.mutex);
5548}
5549
b33a2815 5550/**
0ddfd203 5551 * intel_edp_drrs_flush - Restart Idleness DRRS
b33a2815
VK		 5552 * @dev: DRM device
5553 * @frontbuffer_bits: frontbuffer plane tracking bits
5554 *
0ddfd203
R		 5555 * This function gets called every time rendering on the given planes has
5556 * completed or flip on a crtc is completed. So DRRS should be upclocked
5557 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5558 * if no other planes are dirty.
b33a2815
VK		 5559 *
5560 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5561 */
a93fad0f
VK		 5562void intel_edp_drrs_flush(struct drm_device *dev,
5563 unsigned frontbuffer_bits)
5564{
5565 struct drm_i915_private *dev_priv = dev->dev_private;
5566 struct drm_crtc *crtc;
5567 enum pipe pipe;
5568
9da7d693 5569 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5570 return;
5571
88f933a8 5572 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5573
a93fad0f 5574 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5575 if (!dev_priv->drrs.dp) {
5576 mutex_unlock(&dev_priv->drrs.mutex);
5577 return;
5578 }
5579
a93fad0f
VK		 5580 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5581 pipe = to_intel_crtc(crtc)->pipe;
c1d038c6
DV		 5582
5583 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
a93fad0f
VK		 5584 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5585
0ddfd203 5586 /* flush means busy screen hence upclock */
c1d038c6 5587 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
0ddfd203
R		 5588 intel_dp_set_drrs_state(dev_priv->dev,
5589 dev_priv->drrs.dp->attached_connector->panel.
5590 fixed_mode->vrefresh);
5591
5592 /*
5593 * flush also means no more activity hence schedule downclock, if all
5594 * other fbs are quiescent too
5595 */
5596 if (!dev_priv->drrs.busy_frontbuffer_bits)
a93fad0f
VK		 5597 schedule_delayed_work(&dev_priv->drrs.work,
5598 msecs_to_jiffies(1000));
5599 mutex_unlock(&dev_priv->drrs.mutex);
5600}
5601
b33a2815
VK		 5602/**
5603 * DOC: Display Refresh Rate Switching (DRRS)
5604 *
5605 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5606 * which enables swtching between low and high refresh rates,
5607 * dynamically, based on the usage scenario. This feature is applicable
5608 * for internal panels.
5609 *
5610 * Indication that the panel supports DRRS is given by the panel EDID, which
5611 * would list multiple refresh rates for one resolution.
5612 *
5613 * DRRS is of 2 types - static and seamless.
5614 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5615 * (may appear as a blink on screen) and is used in dock-undock scenario.
5616 * Seamless DRRS involves changing RR without any visual effect to the user
5617 * and can be used during normal system usage. This is done by programming
5618 * certain registers.
5619 *
5620 * Support for static/seamless DRRS may be indicated in the VBT based on
5621 * inputs from the panel spec.
5622 *
5623 * DRRS saves power by switching to low RR based on usage scenarios.
5624 *
5625 * eDP DRRS:-
5626 * The implementation is based on frontbuffer tracking implementation.
5627 * When there is a disturbance on the screen triggered by user activity or a
5628 * periodic system activity, DRRS is disabled (RR is changed to high RR).
5629 * When there is no movement on screen, after a timeout of 1 second, a switch
5630 * to low RR is made.
5631 * For integration with frontbuffer tracking code,
5632 * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5633 *
5634 * DRRS can be further extended to support other internal panels and also
5635 * the scenario of video playback wherein RR is set based on the rate
5636 * requested by userspace.
5637 */
5638
5639/**
5640 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5641 * @intel_connector: eDP connector
5642 * @fixed_mode: preferred mode of panel
5643 *
5644 * This function is called only once at driver load to initialize basic
5645 * DRRS stuff.
5646 *
5647 * Returns:
5648 * Downclock mode if panel supports it, else return NULL.
5649 * DRRS support is determined by the presence of downclock mode (apart
5650 * from VBT setting).
5651 */
4f9db5b5 5652static struct drm_display_mode *
96178eeb
VK		 5653intel_dp_drrs_init(struct intel_connector *intel_connector,
5654 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5655{
5656 struct drm_connector *connector = &intel_connector->base;
96178eeb 5657 struct drm_device *dev = connector->dev;
4f9db5b5
PB		 5658 struct drm_i915_private *dev_priv = dev->dev_private;
5659 struct drm_display_mode *downclock_mode = NULL;
5660
9da7d693
DV		 5661 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5662 mutex_init(&dev_priv->drrs.mutex);
5663
4f9db5b5
PB		 5664 if (INTEL_INFO(dev)->gen <= 6) {
5665 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5666 return NULL;
5667 }
5668
5669 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5670 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5671 return NULL;
5672 }
5673
5674 downclock_mode = intel_find_panel_downclock
5675 (dev, fixed_mode, connector);
5676
5677 if (!downclock_mode) {
a1d26342 5678 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5679 return NULL;
5680 }
5681
96178eeb 5682 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5683
96178eeb 5684 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5685 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5686 return downclock_mode;
5687}
5688
ed92f0b2 5689static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5690 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5691{
5692 struct drm_connector *connector = &intel_connector->base;
5693 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5694 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5695 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5696 struct drm_i915_private *dev_priv = dev->dev_private;
5697 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5698 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5699 bool has_dpcd;
5700 struct drm_display_mode *scan;
5701 struct edid *edid;
6517d273 5702 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5703
5704 if (!is_edp(intel_dp))
5705 return true;
5706
49e6bc51
VS		 5707 pps_lock(intel_dp);
5708 intel_edp_panel_vdd_sanitize(intel_dp);
5709 pps_unlock(intel_dp);
63635217 5710
ed92f0b2 5711 /* Cache DPCD and EDID for edp. */
ed92f0b2 5712 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5713
5714 if (has_dpcd) {
5715 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5716 dev_priv->no_aux_handshake =
5717 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5718 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5719 } else {
5720 /* if this fails, presume the device is a ghost */
5721 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5722 return false;
5723 }
5724
5725 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5726 pps_lock(intel_dp);
36b5f425 5727 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5728 pps_unlock(intel_dp);
ed92f0b2 5729
060c8778 5730 mutex_lock(&dev->mode_config.mutex);
0b99836f 5731 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5732 if (edid) {
5733 if (drm_add_edid_modes(connector, edid)) {
5734 drm_mode_connector_update_edid_property(connector,
5735 edid);
5736 drm_edid_to_eld(connector, edid);
5737 } else {
5738 kfree(edid);
5739 edid = ERR_PTR(-EINVAL);
5740 }
5741 } else {
5742 edid = ERR_PTR(-ENOENT);
5743 }
5744 intel_connector->edid = edid;
5745
5746 /* prefer fixed mode from EDID if available */
5747 list_for_each_entry(scan, &connector->probed_modes, head) {
5748 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5749 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5750 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5751 intel_connector, fixed_mode);
ed92f0b2
PZ		 5752 break;
5753 }
5754 }
5755
5756 /* fallback to VBT if available for eDP */
5757 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5758 fixed_mode = drm_mode_duplicate(dev,
5759 dev_priv->vbt.lfp_lvds_vbt_mode);
5760 if (fixed_mode)
5761 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5762 }
060c8778 5763 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5764
666a4537 5765 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
01527b31
CT		 5766 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5767 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5768
5769 /*
5770 * Figure out the current pipe for the initial backlight setup.
5771 * If the current pipe isn't valid, try the PPS pipe, and if that
5772 * fails just assume pipe A.
5773 */
5774 if (IS_CHERRYVIEW(dev))
5775 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5776 else
5777 pipe = PORT_TO_PIPE(intel_dp->DP);
5778
5779 if (pipe != PIPE_A && pipe != PIPE_B)
5780 pipe = intel_dp->pps_pipe;
5781
5782 if (pipe != PIPE_A && pipe != PIPE_B)
5783 pipe = PIPE_A;
5784
5785 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5786 pipe_name(pipe));
01527b31
CT		 5787 }
5788
4f9db5b5 5789 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5507faeb 5790 intel_connector->panel.backlight.power = intel_edp_backlight_power;
6517d273 5791 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5792
5793 return true;
5794}
5795
16c25533 5796bool
f0fec3f2
PZ		 5797intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5798 struct intel_connector *intel_connector)
a4fc5ed6 5799{
f0fec3f2
PZ		 5800 struct drm_connector *connector = &intel_connector->base;
5801 struct intel_dp *intel_dp = &intel_dig_port->dp;
5802 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5803 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5804 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5805 enum port port = intel_dig_port->port;
a121f4e5 5806 int type, ret;
a4fc5ed6 5807
ccb1a831
VS		 5808 if (WARN(intel_dig_port->max_lanes < 1,
5809 "Not enough lanes (%d) for DP on port %c\n",
5810 intel_dig_port->max_lanes, port_name(port)))
5811 return false;
5812
a4a5d2f8
VS		 5813 intel_dp->pps_pipe = INVALID_PIPE;
5814
ec5b01dd 5815 /* intel_dp vfuncs */
b6b5e383
DL		 5816 if (INTEL_INFO(dev)->gen >= 9)
5817 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
ec5b01dd
DL		 5818 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5819 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5820 else if (HAS_PCH_SPLIT(dev))
5821 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5822 else
6ffb1be7 5823 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
ec5b01dd 5824
b9ca5fad
DL		 5825 if (INTEL_INFO(dev)->gen >= 9)
5826 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5827 else
6ffb1be7 5828 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
153b1100 5829
ad64217b
ACO		 5830 if (HAS_DDI(dev))
5831 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5832
0767935e
DV		 5833 /* Preserve the current hw state. */
5834 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5835 intel_dp->attached_connector = intel_connector;
3d3dc149 5836
3b32a35b 5837 if (intel_dp_is_edp(dev, port))
b329530c 5838 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5839 else
5840 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5841
f7d24902
ID		 5842 /*
5843 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5844 * for DP the encoder type can be set by the caller to
5845 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5846 */
5847 if (type == DRM_MODE_CONNECTOR_eDP)
5848 intel_encoder->type = INTEL_OUTPUT_EDP;
5849
c17ed5b5 5850 /* eDP only on port B and/or C on vlv/chv */
666a4537
WB		 5851 if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5852 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
c17ed5b5
VS		 5853 return false;
5854
e7281eab
ID		 5855 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5856 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5857 port_name(port));
5858
b329530c 5859 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5860 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5861
a4fc5ed6
KP		 5862 connector->interlace_allowed = true;
5863 connector->doublescan_allowed = 0;
5864
f0fec3f2 5865 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5866 edp_panel_vdd_work);
a4fc5ed6 5867
df0e9248 5868 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5869 drm_connector_register(connector);
a4fc5ed6 5870
affa9354 5871 if (HAS_DDI(dev))
bcbc889b
PZ		 5872 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5873 else
5874 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5875 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5876
0b99836f 5877 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5878 switch (port) {
5879 case PORT_A:
1d843f9d 5880 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5881 break;
5882 case PORT_B:
1d843f9d 5883 intel_encoder->hpd_pin = HPD_PORT_B;
e87a005d 5884 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
cf1d5883 5885 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5886 break;
5887 case PORT_C:
1d843f9d 5888 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5889 break;
5890 case PORT_D:
1d843f9d 5891 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30 5892 break;
26951caf
XZ		 5893 case PORT_E:
5894 intel_encoder->hpd_pin = HPD_PORT_E;
5895 break;
ab9d7c30 5896 default:
ad1c0b19 5897 BUG();
5eb08b69
ZW		 5898 }
5899
dada1a9f 5900 if (is_edp(intel_dp)) {
773538e8 5901 pps_lock(intel_dp);
1e74a324 5902 intel_dp_init_panel_power_timestamps(intel_dp);
666a4537 5903 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
a4a5d2f8 5904 vlv_initial_power_sequencer_setup(intel_dp);
1e74a324 5905 else
36b5f425 5906 intel_dp_init_panel_power_sequencer(dev, intel_dp);
773538e8 5907 pps_unlock(intel_dp);
dada1a9f 5908 }
0095e6dc 5909
a121f4e5
VS		 5910 ret = intel_dp_aux_init(intel_dp, intel_connector);
5911 if (ret)
5912 goto fail;
c1f05264 5913
0e32b39c 5914 /* init MST on ports that can support it */
0c9b3715
JN		 5915 if (HAS_DP_MST(dev) &&
5916 (port == PORT_B || port == PORT_C || port == PORT_D))
5917 intel_dp_mst_encoder_init(intel_dig_port,
5918 intel_connector->base.base.id);
0e32b39c 5919
36b5f425 5920 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
a121f4e5
VS		 5921 intel_dp_aux_fini(intel_dp);
5922 intel_dp_mst_encoder_cleanup(intel_dig_port);
5923 goto fail;
b2f246a8 5924 }
32f9d658 5925
f684960e
CW		 5926 intel_dp_add_properties(intel_dp, connector);
5927
a4fc5ed6
KP		 5928 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5929 * 0xd. Failure to do so will result in spurious interrupts being
5930 * generated on the port when a cable is not attached.
5931 */
5932 if (IS_G4X(dev) && !IS_GM45(dev)) {
5933 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5934 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5935 }
16c25533 5936
aa7471d2
JN		 5937 i915_debugfs_connector_add(connector);
5938
16c25533 5939 return true;
a121f4e5
VS		 5940
5941fail:
5942 if (is_edp(intel_dp)) {
5943 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5944 /*
5945 * vdd might still be enabled do to the delayed vdd off.
5946 * Make sure vdd is actually turned off here.
5947 */
5948 pps_lock(intel_dp);
5949 edp_panel_vdd_off_sync(intel_dp);
5950 pps_unlock(intel_dp);
5951 }
5952 drm_connector_unregister(connector);
5953 drm_connector_cleanup(connector);
5954
5955 return false;
a4fc5ed6 5956}
f0fec3f2
PZ		 5957
5958void
f0f59a00
VS		 5959intel_dp_init(struct drm_device *dev,
5960 i915_reg_t output_reg, enum port port)
f0fec3f2 5961{
13cf5504 5962 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5963 struct intel_digital_port *intel_dig_port;
5964 struct intel_encoder *intel_encoder;
5965 struct drm_encoder *encoder;
5966 struct intel_connector *intel_connector;
5967
b14c5679 5968 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5969 if (!intel_dig_port)
5970 return;
5971
08d9bc92 5972 intel_connector = intel_connector_alloc();
11aee0f6
SM		 5973 if (!intel_connector)
5974 goto err_connector_alloc;
f0fec3f2
PZ		 5975
5976 intel_encoder = &intel_dig_port->base;
5977 encoder = &intel_encoder->base;
5978
893da0c9 5979 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
ade1ba73 5980 DRM_MODE_ENCODER_TMDS, NULL))
893da0c9 5981 goto err_encoder_init;
f0fec3f2 5982
5bfe2ac0 5983 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5984 intel_encoder->disable = intel_disable_dp;
00c09d70 5985 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5986 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5987 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5988 if (IS_CHERRYVIEW(dev)) {
9197c88b 5989 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5990 intel_encoder->pre_enable = chv_pre_enable_dp;
5991 intel_encoder->enable = vlv_enable_dp;
580d3811 5992 intel_encoder->post_disable = chv_post_disable_dp;
d6db995f 5993 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
e4a1d846 5994 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5995 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5996 intel_encoder->pre_enable = vlv_pre_enable_dp;
5997 intel_encoder->enable = vlv_enable_dp;
49277c31 5998 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5999 } else {
ecff4f3b
JN		 6000 intel_encoder->pre_enable = g4x_pre_enable_dp;
6001 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 6002 if (INTEL_INFO(dev)->gen >= 5)
6003 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 6004 }
f0fec3f2 6005
174edf1f 6006 intel_dig_port->port = port;
f0fec3f2 6007 intel_dig_port->dp.output_reg = output_reg;
ccb1a831 6008 intel_dig_port->max_lanes = 4;
f0fec3f2 6009
00c09d70 6010 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 6011 if (IS_CHERRYVIEW(dev)) {
6012 if (port == PORT_D)
6013 intel_encoder->crtc_mask = 1 << 2;
6014 else
6015 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6016 } else {
6017 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6018 }
bc079e8b 6019 intel_encoder->cloneable = 0;
f0fec3f2 6020
13cf5504 6021 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 6022 dev_priv->hotplug.irq_port[port] = intel_dig_port;
13cf5504 6023
11aee0f6
SM		 6024 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6025 goto err_init_connector;
6026
6027 return;
6028
6029err_init_connector:
6030 drm_encoder_cleanup(encoder);
893da0c9 6031err_encoder_init:
11aee0f6
SM		 6032 kfree(intel_connector);
6033err_connector_alloc:
6034 kfree(intel_dig_port);
6035
6036 return;
f0fec3f2 6037}
0e32b39c
DA		 6038
6039void intel_dp_mst_suspend(struct drm_device *dev)
6040{
6041 struct drm_i915_private *dev_priv = dev->dev_private;
6042 int i;
6043
6044 /* disable MST */
6045 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 6046 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 6047 if (!intel_dig_port)
6048 continue;
6049
6050 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6051 if (!intel_dig_port->dp.can_mst)
6052 continue;
6053 if (intel_dig_port->dp.is_mst)
6054 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6055 }
6056 }
6057}
6058
6059void intel_dp_mst_resume(struct drm_device *dev)
6060{
6061 struct drm_i915_private *dev_priv = dev->dev_private;
6062 int i;
6063
6064 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 6065 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
0e32b39c
DA		 6066 if (!intel_dig_port)
6067 continue;
6068 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6069 int ret;
6070
6071 if (!intel_dig_port->dp.can_mst)
6072 continue;
6073
6074 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6075 if (ret != 0) {
6076 intel_dp_check_mst_status(&intel_dig_port->dp);
6077 }
6078 }
6079 }
6080}
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