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drm/i915: wait for all DSI FIFOs to be empty
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 114static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
293static enum pipe
294vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
298 struct drm_device *dev = intel_dig_port->base.base.dev;
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 enum port port = intel_dig_port->port;
301 enum pipe pipe;
302
303 /* modeset should have pipe */
304 if (crtc)
305 return to_intel_crtc(crtc)->pipe;
306
307 /* init time, try to find a pipe with this port selected */
308 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
309 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
310 PANEL_PORT_SELECT_MASK;
311 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
312 return pipe;
313 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
314 return pipe;
315 }
316
317 /* shrug */
318 return PIPE_A;
319}
320
321static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
322{
323 struct drm_device *dev = intel_dp_to_dev(intel_dp);
324
325 if (HAS_PCH_SPLIT(dev))
326 return PCH_PP_CONTROL;
327 else
328 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
329}
330
331static u32 _pp_stat_reg(struct intel_dp *intel_dp)
332{
333 struct drm_device *dev = intel_dp_to_dev(intel_dp);
334
335 if (HAS_PCH_SPLIT(dev))
336 return PCH_PP_STATUS;
337 else
338 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
339}
340
01527b31
CT		 341/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
342 This function only applicable when panel PM state is not to be tracked */
343static int edp_notify_handler(struct notifier_block *this, unsigned long code,
344 void *unused)
345{
346 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
347 edp_notifier);
348 struct drm_device *dev = intel_dp_to_dev(intel_dp);
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 u32 pp_div;
351 u32 pp_ctrl_reg, pp_div_reg;
352 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
353
354 if (!is_edp(intel_dp) || code != SYS_RESTART)
355 return 0;
356
357 if (IS_VALLEYVIEW(dev)) {
358 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
359 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
360 pp_div = I915_READ(pp_div_reg);
361 pp_div &= PP_REFERENCE_DIVIDER_MASK;
362
363 /* 0x1F write to PP_DIV_REG sets max cycle delay */
364 I915_WRITE(pp_div_reg, pp_div | 0x1F);
365 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
366 msleep(intel_dp->panel_power_cycle_delay);
367 }
368
369 return 0;
370}
371
4be73780 372static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 373{
30add22d 374 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 375 struct drm_i915_private *dev_priv = dev->dev_private;
376
bf13e81b 377 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 378}
379
4be73780 380static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 381{
30add22d 382 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 383 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 384 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
385 struct intel_encoder *intel_encoder = &intel_dig_port->base;
386 enum intel_display_power_domain power_domain;
ebf33b18 387
bb4932c4
ID		 388 power_domain = intel_display_port_power_domain(intel_encoder);
389 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 390 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 391}
392
9b984dae
KP		 393static void
394intel_dp_check_edp(struct intel_dp *intel_dp)
395{
30add22d 396 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 397 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 398
9b984dae
KP		 399 if (!is_edp(intel_dp))
400 return;
453c5420 401
4be73780 402 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 403 WARN(1, "eDP powered off while attempting aux channel communication.\n");
404 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 405 I915_READ(_pp_stat_reg(intel_dp)),
406 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 407 }
408}
409
9ee32fea
DV		 410static uint32_t
411intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
412{
413 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
414 struct drm_device *dev = intel_dig_port->base.base.dev;
415 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 416 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 417 uint32_t status;
418 bool done;
419
ef04f00d 420#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 421 if (has_aux_irq)
b18ac466 422 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 423 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 424 else
425 done = wait_for_atomic(C, 10) == 0;
426 if (!done)
427 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
428 has_aux_irq);
429#undef C
430
431 return status;
432}
433
ec5b01dd 434static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 435{
174edf1f
PZ		 436 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
437 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 438
ec5b01dd
DL		 439 /*
440 * The clock divider is based off the hrawclk, and would like to run at
441 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 442 */
ec5b01dd
DL		 443 return index ? 0 : intel_hrawclk(dev) / 2;
444}
445
446static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
447{
448 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
449 struct drm_device *dev = intel_dig_port->base.base.dev;
450
451 if (index)
452 return 0;
453
454 if (intel_dig_port->port == PORT_A) {
455 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 456 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 457 else
b84a1cf8 458 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 459 } else {
460 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
461 }
462}
463
464static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
465{
466 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
467 struct drm_device *dev = intel_dig_port->base.base.dev;
468 struct drm_i915_private *dev_priv = dev->dev_private;
469
470 if (intel_dig_port->port == PORT_A) {
471 if (index)
472 return 0;
473 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 474 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
475 /* Workaround for non-ULT HSW */
bc86625a
CW		 476 switch (index) {
477 case 0: return 63;
478 case 1: return 72;
479 default: return 0;
480 }
ec5b01dd 481 } else {
bc86625a 482 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 483 }
b84a1cf8
RV		 484}
485
ec5b01dd
DL		 486static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
487{
488 return index ? 0 : 100;
489}
490
5ed12a19
DL		 491static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
492 bool has_aux_irq,
493 int send_bytes,
494 uint32_t aux_clock_divider)
495{
496 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
497 struct drm_device *dev = intel_dig_port->base.base.dev;
498 uint32_t precharge, timeout;
499
500 if (IS_GEN6(dev))
501 precharge = 3;
502 else
503 precharge = 5;
504
505 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
506 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
507 else
508 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
509
510 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 511 DP_AUX_CH_CTL_DONE |
5ed12a19 512 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 513 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 514 timeout |
788d4433 515 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 516 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
517 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 518 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 519}
520
b84a1cf8
RV		 521static int
522intel_dp_aux_ch(struct intel_dp *intel_dp,
523 uint8_t *send, int send_bytes,
524 uint8_t *recv, int recv_size)
525{
526 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
527 struct drm_device *dev = intel_dig_port->base.base.dev;
528 struct drm_i915_private *dev_priv = dev->dev_private;
529 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
530 uint32_t ch_data = ch_ctl + 4;
bc86625a 531 uint32_t aux_clock_divider;
b84a1cf8
RV		 532 int i, ret, recv_bytes;
533 uint32_t status;
5ed12a19 534 int try, clock = 0;
4e6b788c 535 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 536 bool vdd;
537
538 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 539
540 /* dp aux is extremely sensitive to irq latency, hence request the
541 * lowest possible wakeup latency and so prevent the cpu from going into
542 * deep sleep states.
543 */
544 pm_qos_update_request(&dev_priv->pm_qos, 0);
545
546 intel_dp_check_edp(intel_dp);
5eb08b69 547
c67a470b
PZ		 548 intel_aux_display_runtime_get(dev_priv);
549
11bee43e
JB		 550 /* Try to wait for any previous AUX channel activity */
551 for (try = 0; try < 3; try++) {
ef04f00d 552 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 553 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
554 break;
555 msleep(1);
556 }
557
558 if (try == 3) {
559 WARN(1, "dp_aux_ch not started status 0x%08x\n",
560 I915_READ(ch_ctl));
9ee32fea
DV		 561 ret = -EBUSY;
562 goto out;
4f7f7b7e
CW		 563 }
564
46a5ae9f
PZ		 565 /* Only 5 data registers! */
566 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
567 ret = -E2BIG;
568 goto out;
569 }
570
ec5b01dd 571 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 572 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
573 has_aux_irq,
574 send_bytes,
575 aux_clock_divider);
5ed12a19 576
bc86625a
CW		 577 /* Must try at least 3 times according to DP spec */
578 for (try = 0; try < 5; try++) {
579 /* Load the send data into the aux channel data registers */
580 for (i = 0; i < send_bytes; i += 4)
581 I915_WRITE(ch_data + i,
582 pack_aux(send + i, send_bytes - i));
583
584 /* Send the command and wait for it to complete */
5ed12a19 585 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 586
587 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
588
589 /* Clear done status and any errors */
590 I915_WRITE(ch_ctl,
591 status |
592 DP_AUX_CH_CTL_DONE |
593 DP_AUX_CH_CTL_TIME_OUT_ERROR |
594 DP_AUX_CH_CTL_RECEIVE_ERROR);
595
596 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
597 DP_AUX_CH_CTL_RECEIVE_ERROR))
598 continue;
599 if (status & DP_AUX_CH_CTL_DONE)
600 break;
601 }
4f7f7b7e 602 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 603 break;
604 }
605
a4fc5ed6 606 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 607 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 608 ret = -EBUSY;
609 goto out;
a4fc5ed6
KP		 610 }
611
612 /* Check for timeout or receive error.
613 * Timeouts occur when the sink is not connected
614 */
a5b3da54 615 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 616 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 617 ret = -EIO;
618 goto out;
a5b3da54 619 }
1ae8c0a5
KP		 620
621 /* Timeouts occur when the device isn't connected, so they're
622 * "normal" -- don't fill the kernel log with these */
a5b3da54 623 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 624 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 625 ret = -ETIMEDOUT;
626 goto out;
a4fc5ed6
KP		 627 }
628
629 /* Unload any bytes sent back from the other side */
630 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
631 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 632 if (recv_bytes > recv_size)
633 recv_bytes = recv_size;
0206e353 634
4f7f7b7e
CW		 635 for (i = 0; i < recv_bytes; i += 4)
636 unpack_aux(I915_READ(ch_data + i),
637 recv + i, recv_bytes - i);
a4fc5ed6 638
9ee32fea
DV		 639 ret = recv_bytes;
640out:
641 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 642 intel_aux_display_runtime_put(dev_priv);
9ee32fea 643
884f19e9
JN		 644 if (vdd)
645 edp_panel_vdd_off(intel_dp, false);
646
9ee32fea 647 return ret;
a4fc5ed6
KP		 648}
649
a6c8aff0
JN		 650#define BARE_ADDRESS_SIZE 3
651#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 652static ssize_t
653intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 654{
9d1a1031
JN		 655 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
656 uint8_t txbuf[20], rxbuf[20];
657 size_t txsize, rxsize;
a4fc5ed6 658 int ret;
a4fc5ed6 659
9d1a1031
JN		 660 txbuf[0] = msg->request << 4;
661 txbuf[1] = msg->address >> 8;
662 txbuf[2] = msg->address & 0xff;
663 txbuf[3] = msg->size - 1;
46a5ae9f 664
9d1a1031
JN		 665 switch (msg->request & ~DP_AUX_I2C_MOT) {
666 case DP_AUX_NATIVE_WRITE:
667 case DP_AUX_I2C_WRITE:
a6c8aff0 668 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 669 rxsize = 1;
f51a44b9 670
9d1a1031
JN		 671 if (WARN_ON(txsize > 20))
672 return -E2BIG;
a4fc5ed6 673
9d1a1031 674 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 675
9d1a1031
JN		 676 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
677 if (ret > 0) {
678 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 679
9d1a1031
JN		 680 /* Return payload size. */
681 ret = msg->size;
682 }
683 break;
46a5ae9f 684
9d1a1031
JN		 685 case DP_AUX_NATIVE_READ:
686 case DP_AUX_I2C_READ:
a6c8aff0 687 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 688 rxsize = msg->size + 1;
a4fc5ed6 689
9d1a1031
JN		 690 if (WARN_ON(rxsize > 20))
691 return -E2BIG;
a4fc5ed6 692
9d1a1031
JN		 693 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
694 if (ret > 0) {
695 msg->reply = rxbuf[0] >> 4;
696 /*
697 * Assume happy day, and copy the data. The caller is
698 * expected to check msg->reply before touching it.
699 *
700 * Return payload size.
701 */
702 ret--;
703 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 704 }
9d1a1031
JN		 705 break;
706
707 default:
708 ret = -EINVAL;
709 break;
a4fc5ed6 710 }
f51a44b9 711
9d1a1031 712 return ret;
a4fc5ed6
KP		 713}
714
9d1a1031
JN		 715static void
716intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
717{
718 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 719 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
720 enum port port = intel_dig_port->port;
0b99836f 721 const char *name = NULL;
ab2c0672
DA		 722 int ret;
723
33ad6626
JN		 724 switch (port) {
725 case PORT_A:
726 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 727 name = "DPDDC-A";
ab2c0672 728 break;
33ad6626
JN		 729 case PORT_B:
730 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 731 name = "DPDDC-B";
ab2c0672 732 break;
33ad6626
JN		 733 case PORT_C:
734 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 735 name = "DPDDC-C";
ab2c0672 736 break;
33ad6626
JN		 737 case PORT_D:
738 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 739 name = "DPDDC-D";
33ad6626
JN		 740 break;
741 default:
742 BUG();
ab2c0672
DA		 743 }
744
33ad6626
JN		 745 if (!HAS_DDI(dev))
746 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 747
0b99836f 748 intel_dp->aux.name = name;
9d1a1031
JN		 749 intel_dp->aux.dev = dev->dev;
750 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 751
0b99836f
JN		 752 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
753 connector->base.kdev->kobj.name);
8316f337 754
4f71d0cb 755 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 756 if (ret < 0) {
4f71d0cb 757 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 758 name, ret);
759 return;
ab2c0672 760 }
8a5e6aeb 761
0b99836f
JN		 762 ret = sysfs_create_link(&connector->base.kdev->kobj,
763 &intel_dp->aux.ddc.dev.kobj,
764 intel_dp->aux.ddc.dev.kobj.name);
765 if (ret < 0) {
766 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 767 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 768 }
a4fc5ed6
KP		 769}
770
80f65de3
ID		 771static void
772intel_dp_connector_unregister(struct intel_connector *intel_connector)
773{
774 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
775
0e32b39c
DA		 776 if (!intel_connector->mst_port)
777 sysfs_remove_link(&intel_connector->base.kdev->kobj,
778 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 779 intel_connector_unregister(intel_connector);
780}
781
0e50338c
DV		 782static void
783hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
784{
785 switch (link_bw) {
786 case DP_LINK_BW_1_62:
787 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
788 break;
789 case DP_LINK_BW_2_7:
790 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
791 break;
792 case DP_LINK_BW_5_4:
793 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
794 break;
795 }
796}
797
c6bb3538
DV		 798static void
799intel_dp_set_clock(struct intel_encoder *encoder,
800 struct intel_crtc_config *pipe_config, int link_bw)
801{
802 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 803 const struct dp_link_dpll *divisor = NULL;
804 int i, count = 0;
c6bb3538
DV		 805
806 if (IS_G4X(dev)) {
9dd4ffdf
CML		 807 divisor = gen4_dpll;
808 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 809 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 810 divisor = pch_dpll;
811 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 812 } else if (IS_CHERRYVIEW(dev)) {
813 divisor = chv_dpll;
814 count = ARRAY_SIZE(chv_dpll);
c6bb3538 815 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 816 divisor = vlv_dpll;
817 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 818 }
9dd4ffdf
CML		 819
820 if (divisor && count) {
821 for (i = 0; i < count; i++) {
822 if (link_bw == divisor[i].link_bw) {
823 pipe_config->dpll = divisor[i].dpll;
824 pipe_config->clock_set = true;
825 break;
826 }
827 }
c6bb3538
DV		 828 }
829}
830
439d7ac0
PB		 831static void
832intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
833{
834 struct drm_device *dev = crtc->base.dev;
835 struct drm_i915_private *dev_priv = dev->dev_private;
836 enum transcoder transcoder = crtc->config.cpu_transcoder;
837
838 I915_WRITE(PIPE_DATA_M2(transcoder),
839 TU_SIZE(m_n->tu) | m_n->gmch_m);
840 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
841 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
842 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
843}
844
00c09d70 845bool
5bfe2ac0
DV		 846intel_dp_compute_config(struct intel_encoder *encoder,
847 struct intel_crtc_config *pipe_config)
a4fc5ed6 848{
5bfe2ac0 849 struct drm_device *dev = encoder->base.dev;
36008365 850 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 851 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 852 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 853 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 854 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 855 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 856 int lane_count, clock;
56071a20 857 int min_lane_count = 1;
eeb6324d 858 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 859 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 860 int min_clock = 0;
06ea66b6 861 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 862 int bpp, mode_rate;
06ea66b6 863 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 864 int link_avail, link_clock;
a4fc5ed6 865
bc7d38a4 866 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 867 pipe_config->has_pch_encoder = true;
868
03afc4a2 869 pipe_config->has_dp_encoder = true;
9ed109a7 870 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 871
dd06f90e
JN		 872 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
873 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
874 adjusted_mode);
2dd24552
JB		 875 if (!HAS_PCH_SPLIT(dev))
876 intel_gmch_panel_fitting(intel_crtc, pipe_config,
877 intel_connector->panel.fitting_mode);
878 else
b074cec8
JB		 879 intel_pch_panel_fitting(intel_crtc, pipe_config,
880 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 881 }
882
cb1793ce 883 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 884 return false;
885
083f9560
DV		 886 DRM_DEBUG_KMS("DP link computation with max lane count %i "
887 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 888 max_lane_count, bws[max_clock],
889 adjusted_mode->crtc_clock);
083f9560 890
36008365
DV		 891 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
892 * bpc in between. */
3e7ca985 893 bpp = pipe_config->pipe_bpp;
56071a20
JN		 894 if (is_edp(intel_dp)) {
895 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
896 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
897 dev_priv->vbt.edp_bpp);
898 bpp = dev_priv->vbt.edp_bpp;
899 }
900
f4cdbc21
JN		 901 if (IS_BROADWELL(dev)) {
902 /* Yes, it's an ugly hack. */
903 min_lane_count = max_lane_count;
904 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
905 min_lane_count);
906 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 907 min_lane_count = min(dev_priv->vbt.edp_lanes,
908 max_lane_count);
909 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
910 min_lane_count);
911 }
912
913 if (dev_priv->vbt.edp_rate) {
914 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
915 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
916 bws[min_clock]);
917 }
7984211e 918 }
657445fe 919
36008365 920 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 921 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
922 bpp);
36008365 923
c6930992
DA		 924 for (clock = min_clock; clock <= max_clock; clock++) {
925 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 926 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
927 link_avail = intel_dp_max_data_rate(link_clock,
928 lane_count);
929
930 if (mode_rate <= link_avail) {
931 goto found;
932 }
933 }
934 }
935 }
c4867936 936
36008365 937 return false;
3685a8f3 938
36008365 939found:
55bc60db
VS		 940 if (intel_dp->color_range_auto) {
941 /*
942 * See:
943 * CEA-861-E - 5.1 Default Encoding Parameters
944 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
945 */
18316c8c 946 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 947 intel_dp->color_range = DP_COLOR_RANGE_16_235;
948 else
949 intel_dp->color_range = 0;
950 }
951
3685a8f3 952 if (intel_dp->color_range)
50f3b016 953 pipe_config->limited_color_range = true;
a4fc5ed6 954
36008365
DV		 955 intel_dp->link_bw = bws[clock];
956 intel_dp->lane_count = lane_count;
657445fe 957 pipe_config->pipe_bpp = bpp;
ff9a6750 958 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 959
36008365
DV		 960 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
961 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 962 pipe_config->port_clock, bpp);
36008365
DV		 963 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
964 mode_rate, link_avail);
a4fc5ed6 965
03afc4a2 966 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 967 adjusted_mode->crtc_clock,
968 pipe_config->port_clock,
03afc4a2 969 &pipe_config->dp_m_n);
9d1a455b 970
439d7ac0
PB		 971 if (intel_connector->panel.downclock_mode != NULL &&
972 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
973 intel_link_compute_m_n(bpp, lane_count,
974 intel_connector->panel.downclock_mode->clock,
975 pipe_config->port_clock,
976 &pipe_config->dp_m2_n2);
977 }
978
0e50338c
DV		 979 if (HAS_DDI(dev))
980 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
981 else
982 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 983
03afc4a2 984 return true;
a4fc5ed6
KP		 985}
986
7c62a164 987static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 988{
7c62a164
DV		 989 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
990 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
991 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 992 struct drm_i915_private *dev_priv = dev->dev_private;
993 u32 dpa_ctl;
994
ff9a6750 995 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 996 dpa_ctl = I915_READ(DP_A);
997 dpa_ctl &= ~DP_PLL_FREQ_MASK;
998
ff9a6750 999 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1000 /* For a long time we've carried around a ILK-DevA w/a for the
1001 * 160MHz clock. If we're really unlucky, it's still required.
1002 */
1003 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1004 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1005 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1006 } else {
1007 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1008 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1009 }
1ce17038 1010
ea9b6006
DV		 1011 I915_WRITE(DP_A, dpa_ctl);
1012
1013 POSTING_READ(DP_A);
1014 udelay(500);
1015}
1016
8ac33ed3 1017static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1018{
b934223d 1019 struct drm_device *dev = encoder->base.dev;
417e822d 1020 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1021 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1022 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1023 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1024 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1025
417e822d 1026 /*
1a2eb460 1027 * There are four kinds of DP registers:
417e822d
KP		 1028 *
1029 * IBX PCH
1a2eb460
KP		 1030 * SNB CPU
1031 * IVB CPU
417e822d
KP		 1032 * CPT PCH
1033 *
1034 * IBX PCH and CPU are the same for almost everything,
1035 * except that the CPU DP PLL is configured in this
1036 * register
1037 *
1038 * CPT PCH is quite different, having many bits moved
1039 * to the TRANS_DP_CTL register instead. That
1040 * configuration happens (oddly) in ironlake_pch_enable
1041 */
9c9e7927 1042
417e822d
KP		 1043 /* Preserve the BIOS-computed detected bit. This is
1044 * supposed to be read-only.
1045 */
1046 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1047
417e822d 1048 /* Handle DP bits in common between all three register formats */
417e822d 1049 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1050 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1051
9ed109a7 1052 if (crtc->config.has_audio) {
e0dac65e 1053 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1054 pipe_name(crtc->pipe));
ea5b213a 1055 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1056 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1057 }
247d89f6 1058
417e822d 1059 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1060
bc7d38a4 1061 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1062 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1063 intel_dp->DP |= DP_SYNC_HS_HIGH;
1064 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1065 intel_dp->DP |= DP_SYNC_VS_HIGH;
1066 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1067
6aba5b6c 1068 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1069 intel_dp->DP |= DP_ENHANCED_FRAMING;
1070
7c62a164 1071 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1072 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1073 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1074 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1075
1076 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1077 intel_dp->DP |= DP_SYNC_HS_HIGH;
1078 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1079 intel_dp->DP |= DP_SYNC_VS_HIGH;
1080 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1081
6aba5b6c 1082 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1083 intel_dp->DP |= DP_ENHANCED_FRAMING;
1084
44f37d1f
CML		 1085 if (!IS_CHERRYVIEW(dev)) {
1086 if (crtc->pipe == 1)
1087 intel_dp->DP |= DP_PIPEB_SELECT;
1088 } else {
1089 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1090 }
417e822d
KP		 1091 } else {
1092 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1093 }
a4fc5ed6
KP		 1094}
1095
ffd6749d
PZ		 1096#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1097#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1098
1a5ef5b7
PZ		 1099#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1100#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1101
ffd6749d
PZ		 1102#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1103#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1104
4be73780 1105static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1106 u32 mask,
1107 u32 value)
bd943159 1108{
30add22d 1109 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1110 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1111 u32 pp_stat_reg, pp_ctrl_reg;
1112
bf13e81b
JN		 1113 pp_stat_reg = _pp_stat_reg(intel_dp);
1114 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1115
99ea7127 1116 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1117 mask, value,
1118 I915_READ(pp_stat_reg),
1119 I915_READ(pp_ctrl_reg));
32ce697c 1120
453c5420 1121 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1122 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1123 I915_READ(pp_stat_reg),
1124 I915_READ(pp_ctrl_reg));
32ce697c 1125 }
54c136d4
CW		 1126
1127 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1128}
32ce697c 1129
4be73780 1130static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1131{
1132 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1133 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1134}
1135
4be73780 1136static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1137{
1138 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1139 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1140}
1141
4be73780 1142static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1143{
1144 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1145
1146 /* When we disable the VDD override bit last we have to do the manual
1147 * wait. */
1148 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1149 intel_dp->panel_power_cycle_delay);
1150
4be73780 1151 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1152}
1153
4be73780 1154static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1155{
1156 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1157 intel_dp->backlight_on_delay);
1158}
1159
4be73780 1160static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1161{
1162 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1163 intel_dp->backlight_off_delay);
1164}
99ea7127 1165
832dd3c1
KP		 1166/* Read the current pp_control value, unlocking the register if it
1167 * is locked
1168 */
1169
453c5420 1170static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1171{
453c5420
JB		 1172 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1173 struct drm_i915_private *dev_priv = dev->dev_private;
1174 u32 control;
832dd3c1 1175
bf13e81b 1176 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1177 control &= ~PANEL_UNLOCK_MASK;
1178 control |= PANEL_UNLOCK_REGS;
1179 return control;
bd943159
KP		 1180}
1181
adddaaf4 1182static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1183{
30add22d 1184 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1185 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1186 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1187 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1188 enum intel_display_power_domain power_domain;
5d613501 1189 u32 pp;
453c5420 1190 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1191 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1192
97af61f5 1193 if (!is_edp(intel_dp))
adddaaf4 1194 return false;
bd943159
KP		 1195
1196 intel_dp->want_panel_vdd = true;
99ea7127 1197
4be73780 1198 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1199 return need_to_disable;
b0665d57 1200
4e6e1a54
ID		 1201 power_domain = intel_display_port_power_domain(intel_encoder);
1202 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1203
b0665d57 1204 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1205
4be73780
DV		 1206 if (!edp_have_panel_power(intel_dp))
1207 wait_panel_power_cycle(intel_dp);
99ea7127 1208
453c5420 1209 pp = ironlake_get_pp_control(intel_dp);
5d613501 1210 pp |= EDP_FORCE_VDD;
ebf33b18 1211
bf13e81b
JN		 1212 pp_stat_reg = _pp_stat_reg(intel_dp);
1213 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1214
1215 I915_WRITE(pp_ctrl_reg, pp);
1216 POSTING_READ(pp_ctrl_reg);
1217 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1218 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1219 /*
1220 * If the panel wasn't on, delay before accessing aux channel
1221 */
4be73780 1222 if (!edp_have_panel_power(intel_dp)) {
bd943159 1223 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1224 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1225 }
adddaaf4
JN		 1226
1227 return need_to_disable;
1228}
1229
b80d6c78 1230void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1231{
1232 if (is_edp(intel_dp)) {
1233 bool vdd = _edp_panel_vdd_on(intel_dp);
1234
1235 WARN(!vdd, "eDP VDD already requested on\n");
1236 }
5d613501
JB		 1237}
1238
4be73780 1239static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1240{
30add22d 1241 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1242 struct drm_i915_private *dev_priv = dev->dev_private;
1243 u32 pp;
453c5420 1244 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1245
51fd371b 1246 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
a0e99e68 1247
4be73780 1248 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
4e6e1a54
ID		 1249 struct intel_digital_port *intel_dig_port =
1250 dp_to_dig_port(intel_dp);
1251 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1252 enum intel_display_power_domain power_domain;
1253
b0665d57
PZ		 1254 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1255
453c5420 1256 pp = ironlake_get_pp_control(intel_dp);
bd943159 1257 pp &= ~EDP_FORCE_VDD;
bd943159 1258
9f08ef59
PZ		 1259 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1260 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1261
1262 I915_WRITE(pp_ctrl_reg, pp);
1263 POSTING_READ(pp_ctrl_reg);
99ea7127 1264
453c5420
JB		 1265 /* Make sure sequencer is idle before allowing subsequent activity */
1266 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1267 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1268
1269 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1270 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1271
4e6e1a54
ID		 1272 power_domain = intel_display_port_power_domain(intel_encoder);
1273 intel_display_power_put(dev_priv, power_domain);
bd943159
KP		 1274 }
1275}
5d613501 1276
4be73780 1277static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1278{
1279 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1280 struct intel_dp, panel_vdd_work);
30add22d 1281 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1282
51fd371b 1283 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 1284 edp_panel_vdd_off_sync(intel_dp);
51fd371b 1285 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159
KP		 1286}
1287
4be73780 1288static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1289{
97af61f5
KP		 1290 if (!is_edp(intel_dp))
1291 return;
5d613501 1292
bd943159 1293 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1294
bd943159
KP		 1295 intel_dp->want_panel_vdd = false;
1296
1297 if (sync) {
4be73780 1298 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1299 } else {
1300 /*
1301 * Queue the timer to fire a long
1302 * time from now (relative to the power down delay)
1303 * to keep the panel power up across a sequence of operations
1304 */
1305 schedule_delayed_work(&intel_dp->panel_vdd_work,
1306 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1307 }
5d613501
JB		 1308}
1309
4be73780 1310void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1311{
30add22d 1312 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1313 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1314 u32 pp;
453c5420 1315 u32 pp_ctrl_reg;
9934c132 1316
97af61f5 1317 if (!is_edp(intel_dp))
bd943159 1318 return;
99ea7127
KP		 1319
1320 DRM_DEBUG_KMS("Turn eDP power on\n");
1321
4be73780 1322 if (edp_have_panel_power(intel_dp)) {
99ea7127 1323 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1324 return;
99ea7127 1325 }
9934c132 1326
4be73780 1327 wait_panel_power_cycle(intel_dp);
37c6c9b0 1328
bf13e81b 1329 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1330 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1331 if (IS_GEN5(dev)) {
1332 /* ILK workaround: disable reset around power sequence */
1333 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1334 I915_WRITE(pp_ctrl_reg, pp);
1335 POSTING_READ(pp_ctrl_reg);
05ce1a49 1336 }
37c6c9b0 1337
1c0ae80a 1338 pp |= POWER_TARGET_ON;
99ea7127
KP		 1339 if (!IS_GEN5(dev))
1340 pp |= PANEL_POWER_RESET;
1341
453c5420
JB		 1342 I915_WRITE(pp_ctrl_reg, pp);
1343 POSTING_READ(pp_ctrl_reg);
9934c132 1344
4be73780 1345 wait_panel_on(intel_dp);
dce56b3c 1346 intel_dp->last_power_on = jiffies;
9934c132 1347
05ce1a49
KP		 1348 if (IS_GEN5(dev)) {
1349 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1350 I915_WRITE(pp_ctrl_reg, pp);
1351 POSTING_READ(pp_ctrl_reg);
05ce1a49 1352 }
9934c132
JB		 1353}
1354
4be73780 1355void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1356{
4e6e1a54
ID		 1357 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1358 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1359 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1360 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1361 enum intel_display_power_domain power_domain;
99ea7127 1362 u32 pp;
453c5420 1363 u32 pp_ctrl_reg;
9934c132 1364
97af61f5
KP		 1365 if (!is_edp(intel_dp))
1366 return;
37c6c9b0 1367
99ea7127 1368 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1369
24f3e092
JN		 1370 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1371
453c5420 1372 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1373 /* We need to switch off panel power _and_ force vdd, for otherwise some
1374 * panels get very unhappy and cease to work. */
b3064154
PJ		 1375 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1376 EDP_BLC_ENABLE);
453c5420 1377
bf13e81b 1378 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1379
849e39f5
PZ		 1380 intel_dp->want_panel_vdd = false;
1381
453c5420
JB		 1382 I915_WRITE(pp_ctrl_reg, pp);
1383 POSTING_READ(pp_ctrl_reg);
9934c132 1384
dce56b3c 1385 intel_dp->last_power_cycle = jiffies;
4be73780 1386 wait_panel_off(intel_dp);
849e39f5
PZ		 1387
1388 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1389 power_domain = intel_display_port_power_domain(intel_encoder);
1390 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1391}
1392
4be73780 1393void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1394{
da63a9f2
PZ		 1395 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1396 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1397 struct drm_i915_private *dev_priv = dev->dev_private;
1398 u32 pp;
453c5420 1399 u32 pp_ctrl_reg;
32f9d658 1400
f01eca2e
KP		 1401 if (!is_edp(intel_dp))
1402 return;
1403
28c97730 1404 DRM_DEBUG_KMS("\n");
f7d2323c
JB		 1405
1406 intel_panel_enable_backlight(intel_dp->attached_connector);
1407
01cb9ea6
JB		 1408 /*
1409 * If we enable the backlight right away following a panel power
1410 * on, we may see slight flicker as the panel syncs with the eDP
1411 * link. So delay a bit to make sure the image is solid before
1412 * allowing it to appear.
1413 */
4be73780 1414 wait_backlight_on(intel_dp);
453c5420 1415 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1416 pp |= EDP_BLC_ENABLE;
453c5420 1417
bf13e81b 1418 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1419
1420 I915_WRITE(pp_ctrl_reg, pp);
1421 POSTING_READ(pp_ctrl_reg);
32f9d658
ZW		 1422}
1423
4be73780 1424void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1425{
30add22d 1426 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1427 struct drm_i915_private *dev_priv = dev->dev_private;
1428 u32 pp;
453c5420 1429 u32 pp_ctrl_reg;
32f9d658 1430
f01eca2e
KP		 1431 if (!is_edp(intel_dp))
1432 return;
1433
28c97730 1434 DRM_DEBUG_KMS("\n");
453c5420 1435 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1436 pp &= ~EDP_BLC_ENABLE;
453c5420 1437
bf13e81b 1438 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1439
1440 I915_WRITE(pp_ctrl_reg, pp);
1441 POSTING_READ(pp_ctrl_reg);
dce56b3c 1442 intel_dp->last_backlight_off = jiffies;
f7d2323c
JB		 1443
1444 edp_wait_backlight_off(intel_dp);
1445
1446 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1447}
a4fc5ed6 1448
2bd2ad64 1449static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1450{
da63a9f2
PZ		 1451 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1452 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1453 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1454 struct drm_i915_private *dev_priv = dev->dev_private;
1455 u32 dpa_ctl;
1456
2bd2ad64
DV		 1457 assert_pipe_disabled(dev_priv,
1458 to_intel_crtc(crtc)->pipe);
1459
d240f20f
JB		 1460 DRM_DEBUG_KMS("\n");
1461 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1462 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1463 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1464
1465 /* We don't adjust intel_dp->DP while tearing down the link, to
1466 * facilitate link retraining (e.g. after hotplug). Hence clear all
1467 * enable bits here to ensure that we don't enable too much. */
1468 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1469 intel_dp->DP |= DP_PLL_ENABLE;
1470 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1471 POSTING_READ(DP_A);
1472 udelay(200);
d240f20f
JB		 1473}
1474
2bd2ad64 1475static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1476{
da63a9f2
PZ		 1477 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1478 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1479 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1480 struct drm_i915_private *dev_priv = dev->dev_private;
1481 u32 dpa_ctl;
1482
2bd2ad64
DV		 1483 assert_pipe_disabled(dev_priv,
1484 to_intel_crtc(crtc)->pipe);
1485
d240f20f 1486 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1487 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1488 "dp pll off, should be on\n");
1489 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1490
1491 /* We can't rely on the value tracked for the DP register in
1492 * intel_dp->DP because link_down must not change that (otherwise link
1493 * re-training will fail. */
298b0b39 1494 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1495 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1496 POSTING_READ(DP_A);
d240f20f
JB		 1497 udelay(200);
1498}
1499
c7ad3810 1500/* If the sink supports it, try to set the power state appropriately */
c19b0669 1501void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1502{
1503 int ret, i;
1504
1505 /* Should have a valid DPCD by this point */
1506 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1507 return;
1508
1509 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1510 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1511 DP_SET_POWER_D3);
c7ad3810
JB		 1512 if (ret != 1)
1513 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1514 } else {
1515 /*
1516 * When turning on, we need to retry for 1ms to give the sink
1517 * time to wake up.
1518 */
1519 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1520 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1521 DP_SET_POWER_D0);
c7ad3810
JB		 1522 if (ret == 1)
1523 break;
1524 msleep(1);
1525 }
1526 }
1527}
1528
19d8fe15
DV		 1529static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1530 enum pipe *pipe)
d240f20f 1531{
19d8fe15 1532 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1533 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1534 struct drm_device *dev = encoder->base.dev;
1535 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1536 enum intel_display_power_domain power_domain;
1537 u32 tmp;
1538
1539 power_domain = intel_display_port_power_domain(encoder);
1540 if (!intel_display_power_enabled(dev_priv, power_domain))
1541 return false;
1542
1543 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1544
1545 if (!(tmp & DP_PORT_EN))
1546 return false;
1547
bc7d38a4 1548 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1549 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1550 } else if (IS_CHERRYVIEW(dev)) {
1551 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1552 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1553 *pipe = PORT_TO_PIPE(tmp);
1554 } else {
1555 u32 trans_sel;
1556 u32 trans_dp;
1557 int i;
1558
1559 switch (intel_dp->output_reg) {
1560 case PCH_DP_B:
1561 trans_sel = TRANS_DP_PORT_SEL_B;
1562 break;
1563 case PCH_DP_C:
1564 trans_sel = TRANS_DP_PORT_SEL_C;
1565 break;
1566 case PCH_DP_D:
1567 trans_sel = TRANS_DP_PORT_SEL_D;
1568 break;
1569 default:
1570 return true;
1571 }
1572
1573 for_each_pipe(i) {
1574 trans_dp = I915_READ(TRANS_DP_CTL(i));
1575 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1576 *pipe = i;
1577 return true;
1578 }
1579 }
19d8fe15 1580
4a0833ec
DV		 1581 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1582 intel_dp->output_reg);
1583 }
d240f20f 1584
19d8fe15
DV		 1585 return true;
1586}
d240f20f 1587
045ac3b5
JB		 1588static void intel_dp_get_config(struct intel_encoder *encoder,
1589 struct intel_crtc_config *pipe_config)
1590{
1591 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1592 u32 tmp, flags = 0;
63000ef6
XZ		 1593 struct drm_device *dev = encoder->base.dev;
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595 enum port port = dp_to_dig_port(intel_dp)->port;
1596 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1597 int dotclock;
045ac3b5 1598
9ed109a7
DV		 1599 tmp = I915_READ(intel_dp->output_reg);
1600 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1601 pipe_config->has_audio = true;
1602
63000ef6 1603 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1604 if (tmp & DP_SYNC_HS_HIGH)
1605 flags |= DRM_MODE_FLAG_PHSYNC;
1606 else
1607 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1608
63000ef6
XZ		 1609 if (tmp & DP_SYNC_VS_HIGH)
1610 flags |= DRM_MODE_FLAG_PVSYNC;
1611 else
1612 flags |= DRM_MODE_FLAG_NVSYNC;
1613 } else {
1614 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1615 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1616 flags |= DRM_MODE_FLAG_PHSYNC;
1617 else
1618 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1619
63000ef6
XZ		 1620 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1621 flags |= DRM_MODE_FLAG_PVSYNC;
1622 else
1623 flags |= DRM_MODE_FLAG_NVSYNC;
1624 }
045ac3b5
JB		 1625
1626 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1627
eb14cb74
VS		 1628 pipe_config->has_dp_encoder = true;
1629
1630 intel_dp_get_m_n(crtc, pipe_config);
1631
18442d08 1632 if (port == PORT_A) {
f1f644dc
JB		 1633 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1634 pipe_config->port_clock = 162000;
1635 else
1636 pipe_config->port_clock = 270000;
1637 }
18442d08
VS		 1638
1639 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1640 &pipe_config->dp_m_n);
1641
1642 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1643 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1644
241bfc38 1645 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1646
c6cd2ee2
JN		 1647 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1648 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1649 /*
1650 * This is a big fat ugly hack.
1651 *
1652 * Some machines in UEFI boot mode provide us a VBT that has 18
1653 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1654 * unknown we fail to light up. Yet the same BIOS boots up with
1655 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1656 * max, not what it tells us to use.
1657 *
1658 * Note: This will still be broken if the eDP panel is not lit
1659 * up by the BIOS, and thus we can't get the mode at module
1660 * load.
1661 */
1662 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1663 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1664 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1665 }
045ac3b5
JB		 1666}
1667
34eb7579 1668static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1669{
34eb7579 1670 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1671}
1672
2b28bb1b
RV		 1673static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1674{
1675 struct drm_i915_private *dev_priv = dev->dev_private;
1676
18b5992c 1677 if (!HAS_PSR(dev))
2b28bb1b
RV		 1678 return false;
1679
18b5992c 1680 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1681}
1682
1683static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1684 struct edp_vsc_psr *vsc_psr)
1685{
1686 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1687 struct drm_device *dev = dig_port->base.base.dev;
1688 struct drm_i915_private *dev_priv = dev->dev_private;
1689 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1690 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1691 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1692 uint32_t *data = (uint32_t *) vsc_psr;
1693 unsigned int i;
1694
1695 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1696 the video DIP being updated before program video DIP data buffer
1697 registers for DIP being updated. */
1698 I915_WRITE(ctl_reg, 0);
1699 POSTING_READ(ctl_reg);
1700
1701 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1702 if (i < sizeof(struct edp_vsc_psr))
1703 I915_WRITE(data_reg + i, *data++);
1704 else
1705 I915_WRITE(data_reg + i, 0);
1706 }
1707
1708 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1709 POSTING_READ(ctl_reg);
1710}
1711
1712static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1713{
1714 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1715 struct drm_i915_private *dev_priv = dev->dev_private;
1716 struct edp_vsc_psr psr_vsc;
1717
2b28bb1b
RV		 1718 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1719 memset(&psr_vsc, 0, sizeof(psr_vsc));
1720 psr_vsc.sdp_header.HB0 = 0;
1721 psr_vsc.sdp_header.HB1 = 0x7;
1722 psr_vsc.sdp_header.HB2 = 0x2;
1723 psr_vsc.sdp_header.HB3 = 0x8;
1724 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1725
1726 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1727 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1728 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1729}
1730
1731static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1732{
0e0ae652
RV		 1733 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1734 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 1735 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1736 uint32_t aux_clock_divider;
2b28bb1b
RV		 1737 int precharge = 0x3;
1738 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 1739 bool only_standby = false;
2b28bb1b 1740
ec5b01dd
DL		 1741 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1742
0e0ae652
RV		 1743 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1744 only_standby = true;
1745
2b28bb1b 1746 /* Enable PSR in sink */
0e0ae652 1747 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 1748 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1749 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1750 else
9d1a1031
JN		 1751 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1752 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1753
1754 /* Setup AUX registers */
18b5992c
BW		 1755 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1756 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1757 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1758 DP_AUX_CH_CTL_TIME_OUT_400us |
1759 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1760 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1761 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1762}
1763
1764static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1765{
0e0ae652
RV		 1766 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1767 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 1768 struct drm_i915_private *dev_priv = dev->dev_private;
1769 uint32_t max_sleep_time = 0x1f;
1770 uint32_t idle_frames = 1;
1771 uint32_t val = 0x0;
ed8546ac 1772 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 1773 bool only_standby = false;
1774
1775 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1776 only_standby = true;
2b28bb1b 1777
0e0ae652 1778 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 1779 val |= EDP_PSR_LINK_STANDBY;
1780 val |= EDP_PSR_TP2_TP3_TIME_0us;
1781 val |= EDP_PSR_TP1_TIME_0us;
1782 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 1783 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 1784 } else
1785 val |= EDP_PSR_LINK_DISABLE;
1786
18b5992c 1787 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1788 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1789 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1790 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1791 EDP_PSR_ENABLE);
1792}
1793
3f51e471
RV		 1794static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1795{
1796 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1797 struct drm_device *dev = dig_port->base.base.dev;
1798 struct drm_i915_private *dev_priv = dev->dev_private;
1799 struct drm_crtc *crtc = dig_port->base.base.crtc;
1800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 1801
f0355c4a
DV		 1802 lockdep_assert_held(&dev_priv->psr.lock);
1803 lockdep_assert_held(&dev->struct_mutex);
1804 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1805 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1806
a031d709
RV		 1807 dev_priv->psr.source_ok = false;
1808
9ca15301 1809 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 1810 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1811 return false;
1812 }
1813
d330a953 1814 if (!i915.enable_psr) {
105b7c11 1815 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1816 return false;
1817 }
1818
4c8c7000
RV		 1819 /* Below limitations aren't valid for Broadwell */
1820 if (IS_BROADWELL(dev))
1821 goto out;
1822
3f51e471
RV		 1823 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1824 S3D_ENABLE) {
1825 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1826 return false;
1827 }
1828
ca73b4f0 1829 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1830 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1831 return false;
1832 }
1833
4c8c7000 1834 out:
a031d709 1835 dev_priv->psr.source_ok = true;
3f51e471
RV		 1836 return true;
1837}
1838
3d739d92 1839static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 1840{
7c8f8a70
RV		 1841 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1842 struct drm_device *dev = intel_dig_port->base.base.dev;
1843 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 1844
3638379c
DV		 1845 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1846 WARN_ON(dev_priv->psr.active);
f0355c4a 1847 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 1848
2b28bb1b
RV		 1849 /* Enable PSR on the panel */
1850 intel_edp_psr_enable_sink(intel_dp);
1851
1852 /* Enable PSR on the host */
1853 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 1854
7c8f8a70 1855 dev_priv->psr.active = true;
2b28bb1b
RV		 1856}
1857
3d739d92
RV		 1858void intel_edp_psr_enable(struct intel_dp *intel_dp)
1859{
1860 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 1861 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 1862
4704c573
RV		 1863 if (!HAS_PSR(dev)) {
1864 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1865 return;
1866 }
1867
34eb7579
RV		 1868 if (!is_edp_psr(intel_dp)) {
1869 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1870 return;
1871 }
1872
f0355c4a 1873 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 1874 if (dev_priv->psr.enabled) {
1875 DRM_DEBUG_KMS("PSR already in use\n");
f0355c4a 1876 mutex_unlock(&dev_priv->psr.lock);
109fc2ad
DV		 1877 return;
1878 }
1879
9ca15301
DV		 1880 dev_priv->psr.busy_frontbuffer_bits = 0;
1881
16487254
RV		 1882 /* Setup PSR once */
1883 intel_edp_psr_setup(intel_dp);
1884
7c8f8a70 1885 if (intel_edp_psr_match_conditions(intel_dp))
9ca15301 1886 dev_priv->psr.enabled = intel_dp;
f0355c4a 1887 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 1888}
1889
2b28bb1b
RV		 1890void intel_edp_psr_disable(struct intel_dp *intel_dp)
1891{
1892 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1893 struct drm_i915_private *dev_priv = dev->dev_private;
1894
f0355c4a
DV		 1895 mutex_lock(&dev_priv->psr.lock);
1896 if (!dev_priv->psr.enabled) {
1897 mutex_unlock(&dev_priv->psr.lock);
1898 return;
1899 }
1900
3638379c
DV		 1901 if (dev_priv->psr.active) {
1902 I915_WRITE(EDP_PSR_CTL(dev),
1903 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1904
1905 /* Wait till PSR is idle */
1906 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1907 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1908 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 1909
3638379c
DV		 1910 dev_priv->psr.active = false;
1911 } else {
1912 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1913 }
7c8f8a70 1914
2807cf69 1915 dev_priv->psr.enabled = NULL;
f0355c4a 1916 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 1917
1918 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 1919}
1920
f02a326e 1921static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 1922{
1923 struct drm_i915_private *dev_priv =
1924 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 1925 struct intel_dp *intel_dp = dev_priv->psr.enabled;
1926
f0355c4a
DV		 1927 mutex_lock(&dev_priv->psr.lock);
1928 intel_dp = dev_priv->psr.enabled;
1929
2807cf69 1930 if (!intel_dp)
f0355c4a 1931 goto unlock;
2807cf69 1932
9ca15301
DV		 1933 /*
1934 * The delayed work can race with an invalidate hence we need to
1935 * recheck. Since psr_flush first clears this and then reschedules we
1936 * won't ever miss a flush when bailing out here.
1937 */
1938 if (dev_priv->psr.busy_frontbuffer_bits)
1939 goto unlock;
1940
1941 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 1942unlock:
1943 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 1944}
1945
9ca15301 1946static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 1947{
1948 struct drm_i915_private *dev_priv = dev->dev_private;
1949
3638379c
DV		 1950 if (dev_priv->psr.active) {
1951 u32 val = I915_READ(EDP_PSR_CTL(dev));
1952
1953 WARN_ON(!(val & EDP_PSR_ENABLE));
1954
1955 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
1956
1957 dev_priv->psr.active = false;
1958 }
7c8f8a70 1959
9ca15301
DV		 1960}
1961
1962void intel_edp_psr_invalidate(struct drm_device *dev,
1963 unsigned frontbuffer_bits)
1964{
1965 struct drm_i915_private *dev_priv = dev->dev_private;
1966 struct drm_crtc *crtc;
1967 enum pipe pipe;
1968
9ca15301
DV		 1969 mutex_lock(&dev_priv->psr.lock);
1970 if (!dev_priv->psr.enabled) {
1971 mutex_unlock(&dev_priv->psr.lock);
1972 return;
1973 }
1974
1975 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
1976 pipe = to_intel_crtc(crtc)->pipe;
1977
1978 intel_edp_psr_do_exit(dev);
1979
1980 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
1981
1982 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
1983 mutex_unlock(&dev_priv->psr.lock);
1984}
1985
1986void intel_edp_psr_flush(struct drm_device *dev,
1987 unsigned frontbuffer_bits)
1988{
1989 struct drm_i915_private *dev_priv = dev->dev_private;
1990 struct drm_crtc *crtc;
1991 enum pipe pipe;
1992
9ca15301
DV		 1993 mutex_lock(&dev_priv->psr.lock);
1994 if (!dev_priv->psr.enabled) {
1995 mutex_unlock(&dev_priv->psr.lock);
1996 return;
1997 }
1998
1999 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2000 pipe = to_intel_crtc(crtc)->pipe;
2001 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2002
2003 /*
2004 * On Haswell sprite plane updates don't result in a psr invalidating
2005 * signal in the hardware. Which means we need to manually fake this in
2006 * software for all flushes, not just when we've seen a preceding
2007 * invalidation through frontbuffer rendering.
2008 */
2009 if (IS_HASWELL(dev) &&
2010 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2011 intel_edp_psr_do_exit(dev);
2012
2013 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2014 schedule_delayed_work(&dev_priv->psr.work,
2015 msecs_to_jiffies(100));
f0355c4a 2016 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2017}
2018
2019void intel_edp_psr_init(struct drm_device *dev)
2020{
2021 struct drm_i915_private *dev_priv = dev->dev_private;
2022
7c8f8a70 2023 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2024 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2025}
2026
e8cb4558 2027static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2028{
e8cb4558 2029 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 2030 enum port port = dp_to_dig_port(intel_dp)->port;
2031 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2032
2033 /* Make sure the panel is off before trying to change the mode. But also
2034 * ensure that we have vdd while we switch off the panel. */
24f3e092 2035 intel_edp_panel_vdd_on(intel_dp);
4be73780 2036 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2037 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2038 intel_edp_panel_off(intel_dp);
3739850b
DV		 2039
2040 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 2041 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 2042 intel_dp_link_down(intel_dp);
d240f20f
JB		 2043}
2044
49277c31 2045static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2046{
2bd2ad64 2047 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2048 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2049
49277c31
VS		 2050 if (port != PORT_A)
2051 return;
2052
2053 intel_dp_link_down(intel_dp);
2054 ironlake_edp_pll_off(intel_dp);
2055}
2056
2057static void vlv_post_disable_dp(struct intel_encoder *encoder)
2058{
2059 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2060
2061 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2062}
2063
580d3811
VS		 2064static void chv_post_disable_dp(struct intel_encoder *encoder)
2065{
2066 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2067 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2068 struct drm_device *dev = encoder->base.dev;
2069 struct drm_i915_private *dev_priv = dev->dev_private;
2070 struct intel_crtc *intel_crtc =
2071 to_intel_crtc(encoder->base.crtc);
2072 enum dpio_channel ch = vlv_dport_to_channel(dport);
2073 enum pipe pipe = intel_crtc->pipe;
2074 u32 val;
2075
2076 intel_dp_link_down(intel_dp);
2077
2078 mutex_lock(&dev_priv->dpio_lock);
2079
2080 /* Propagate soft reset to data lane reset */
97fd4d5c 2081 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2082 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2083 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2084
97fd4d5c
VS		 2085 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2086 val |= CHV_PCS_REQ_SOFTRESET_EN;
2087 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2088
2089 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2090 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2091 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2092
2093 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2094 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2095 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2096
2097 mutex_unlock(&dev_priv->dpio_lock);
2098}
2099
e8cb4558 2100static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2101{
e8cb4558
DV		 2102 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2103 struct drm_device *dev = encoder->base.dev;
2104 struct drm_i915_private *dev_priv = dev->dev_private;
2105 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2106
0c33d8d7
DV		 2107 if (WARN_ON(dp_reg & DP_PORT_EN))
2108 return;
5d613501 2109
24f3e092 2110 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 2111 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2112 intel_dp_start_link_train(intel_dp);
4be73780
DV		 2113 intel_edp_panel_on(intel_dp);
2114 edp_panel_vdd_off(intel_dp, true);
33a34e4e 2115 intel_dp_complete_link_train(intel_dp);
3ab9c637 2116 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2117}
89b667f8 2118
ecff4f3b
JN		 2119static void g4x_enable_dp(struct intel_encoder *encoder)
2120{
828f5c6e
JN		 2121 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2122
ecff4f3b 2123 intel_enable_dp(encoder);
4be73780 2124 intel_edp_backlight_on(intel_dp);
ab1f90f9 2125}
89b667f8 2126
ab1f90f9
JN		 2127static void vlv_enable_dp(struct intel_encoder *encoder)
2128{
828f5c6e
JN		 2129 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2130
4be73780 2131 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2132}
2133
ecff4f3b 2134static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2135{
2136 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2137 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2138
8ac33ed3
DV		 2139 intel_dp_prepare(encoder);
2140
d41f1efb
DV		 2141 /* Only ilk+ has port A */
2142 if (dport->port == PORT_A) {
2143 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2144 ironlake_edp_pll_on(intel_dp);
d41f1efb 2145 }
ab1f90f9
JN		 2146}
2147
2148static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2149{
2bd2ad64 2150 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2151 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2152 struct drm_device *dev = encoder->base.dev;
89b667f8 2153 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2154 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2155 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 2156 int pipe = intel_crtc->pipe;
bf13e81b 2157 struct edp_power_seq power_seq;
ab1f90f9 2158 u32 val;
a4fc5ed6 2159
ab1f90f9 2160 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2161
ab3c759a 2162 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2163 val = 0;
2164 if (pipe)
2165 val |= (1<<21);
2166 else
2167 val &= ~(1<<21);
2168 val |= 0x001000c4;
ab3c759a
CML		 2169 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2170 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2171 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2172
ab1f90f9
JN		 2173 mutex_unlock(&dev_priv->dpio_lock);
2174
2cac613b
ID		 2175 if (is_edp(intel_dp)) {
2176 /* init power sequencer on this pipe and port */
2177 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2178 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2179 &power_seq);
2180 }
bf13e81b 2181
ab1f90f9
JN		 2182 intel_enable_dp(encoder);
2183
e4607fcf 2184 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2185}
2186
ecff4f3b 2187static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2188{
2189 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2190 struct drm_device *dev = encoder->base.dev;
2191 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2192 struct intel_crtc *intel_crtc =
2193 to_intel_crtc(encoder->base.crtc);
e4607fcf 2194 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2195 int pipe = intel_crtc->pipe;
89b667f8 2196
8ac33ed3
DV		 2197 intel_dp_prepare(encoder);
2198
89b667f8 2199 /* Program Tx lane resets to default */
0980a60f 2200 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2201 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2202 DPIO_PCS_TX_LANE2_RESET |
2203 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2204 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2205 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2206 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2207 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2208 DPIO_PCS_CLK_SOFT_RESET);
2209
2210 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2211 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2212 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2213 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2214 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2215}
2216
e4a1d846
CML		 2217static void chv_pre_enable_dp(struct intel_encoder *encoder)
2218{
2219 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2220 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2221 struct drm_device *dev = encoder->base.dev;
2222 struct drm_i915_private *dev_priv = dev->dev_private;
2223 struct edp_power_seq power_seq;
2224 struct intel_crtc *intel_crtc =
2225 to_intel_crtc(encoder->base.crtc);
2226 enum dpio_channel ch = vlv_dport_to_channel(dport);
2227 int pipe = intel_crtc->pipe;
2228 int data, i;
949c1d43 2229 u32 val;
e4a1d846 2230
e4a1d846 2231 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2232
2233 /* Deassert soft data lane reset*/
97fd4d5c 2234 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2235 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2236 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2237
2238 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2239 val |= CHV_PCS_REQ_SOFTRESET_EN;
2240 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2241
2242 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2243 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2244 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2245
97fd4d5c 2246 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2247 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2248 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2249
2250 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2251 for (i = 0; i < 4; i++) {
2252 /* Set the latency optimal bit */
2253 data = (i == 1) ? 0x0 : 0x6;
2254 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2255 data << DPIO_FRC_LATENCY_SHFIT);
2256
2257 /* Set the upar bit */
2258 data = (i == 1) ? 0x0 : 0x1;
2259 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2260 data << DPIO_UPAR_SHIFT);
2261 }
2262
2263 /* Data lane stagger programming */
2264 /* FIXME: Fix up value only after power analysis */
2265
2266 mutex_unlock(&dev_priv->dpio_lock);
2267
2268 if (is_edp(intel_dp)) {
2269 /* init power sequencer on this pipe and port */
2270 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2271 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2272 &power_seq);
2273 }
2274
2275 intel_enable_dp(encoder);
2276
2277 vlv_wait_port_ready(dev_priv, dport);
2278}
2279
9197c88b
VS		 2280static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2281{
2282 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2283 struct drm_device *dev = encoder->base.dev;
2284 struct drm_i915_private *dev_priv = dev->dev_private;
2285 struct intel_crtc *intel_crtc =
2286 to_intel_crtc(encoder->base.crtc);
2287 enum dpio_channel ch = vlv_dport_to_channel(dport);
2288 enum pipe pipe = intel_crtc->pipe;
2289 u32 val;
2290
2291 mutex_lock(&dev_priv->dpio_lock);
2292
b9e5ac3c
VS		 2293 /* program left/right clock distribution */
2294 if (pipe != PIPE_B) {
2295 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2296 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2297 if (ch == DPIO_CH0)
2298 val |= CHV_BUFLEFTENA1_FORCE;
2299 if (ch == DPIO_CH1)
2300 val |= CHV_BUFRIGHTENA1_FORCE;
2301 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2302 } else {
2303 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2304 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2305 if (ch == DPIO_CH0)
2306 val |= CHV_BUFLEFTENA2_FORCE;
2307 if (ch == DPIO_CH1)
2308 val |= CHV_BUFRIGHTENA2_FORCE;
2309 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2310 }
2311
9197c88b
VS		 2312 /* program clock channel usage */
2313 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2314 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2315 if (pipe != PIPE_B)
2316 val &= ~CHV_PCS_USEDCLKCHANNEL;
2317 else
2318 val |= CHV_PCS_USEDCLKCHANNEL;
2319 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2320
2321 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2322 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2323 if (pipe != PIPE_B)
2324 val &= ~CHV_PCS_USEDCLKCHANNEL;
2325 else
2326 val |= CHV_PCS_USEDCLKCHANNEL;
2327 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2328
2329 /*
2330 * This a a bit weird since generally CL
2331 * matches the pipe, but here we need to
2332 * pick the CL based on the port.
2333 */
2334 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2335 if (pipe != PIPE_B)
2336 val &= ~CHV_CMN_USEDCLKCHANNEL;
2337 else
2338 val |= CHV_CMN_USEDCLKCHANNEL;
2339 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2340
2341 mutex_unlock(&dev_priv->dpio_lock);
2342}
2343
a4fc5ed6 2344/*
df0c237d
JB		 2345 * Native read with retry for link status and receiver capability reads for
2346 * cases where the sink may still be asleep.
9d1a1031
JN		 2347 *
2348 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2349 * supposed to retry 3 times per the spec.
a4fc5ed6 2350 */
9d1a1031
JN		 2351static ssize_t
2352intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2353 void *buffer, size_t size)
a4fc5ed6 2354{
9d1a1031
JN		 2355 ssize_t ret;
2356 int i;
61da5fab 2357
61da5fab 2358 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2359 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2360 if (ret == size)
2361 return ret;
61da5fab
JB		 2362 msleep(1);
2363 }
a4fc5ed6 2364
9d1a1031 2365 return ret;
a4fc5ed6
KP		 2366}
2367
2368/*
2369 * Fetch AUX CH registers 0x202 - 0x207 which contain
2370 * link status information
2371 */
2372static bool
93f62dad 2373intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2374{
9d1a1031
JN		 2375 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2376 DP_LANE0_1_STATUS,
2377 link_status,
2378 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2379}
2380
1100244e 2381/* These are source-specific values. */
a4fc5ed6 2382static uint8_t
1a2eb460 2383intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2384{
30add22d 2385 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2386 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2387
9576c27f 2388 if (IS_VALLEYVIEW(dev))
e2fa6fba 2389 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2390 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2391 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2392 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2393 return DP_TRAIN_VOLTAGE_SWING_1200;
2394 else
2395 return DP_TRAIN_VOLTAGE_SWING_800;
2396}
2397
2398static uint8_t
2399intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2400{
30add22d 2401 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2402 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2403
9576c27f 2404 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722
PZ		 2405 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2406 case DP_TRAIN_VOLTAGE_SWING_400:
2407 return DP_TRAIN_PRE_EMPHASIS_9_5;
2408 case DP_TRAIN_VOLTAGE_SWING_600:
2409 return DP_TRAIN_PRE_EMPHASIS_6;
2410 case DP_TRAIN_VOLTAGE_SWING_800:
2411 return DP_TRAIN_PRE_EMPHASIS_3_5;
2412 case DP_TRAIN_VOLTAGE_SWING_1200:
2413 default:
2414 return DP_TRAIN_PRE_EMPHASIS_0;
2415 }
e2fa6fba
P		 2416 } else if (IS_VALLEYVIEW(dev)) {
2417 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2418 case DP_TRAIN_VOLTAGE_SWING_400:
2419 return DP_TRAIN_PRE_EMPHASIS_9_5;
2420 case DP_TRAIN_VOLTAGE_SWING_600:
2421 return DP_TRAIN_PRE_EMPHASIS_6;
2422 case DP_TRAIN_VOLTAGE_SWING_800:
2423 return DP_TRAIN_PRE_EMPHASIS_3_5;
2424 case DP_TRAIN_VOLTAGE_SWING_1200:
2425 default:
2426 return DP_TRAIN_PRE_EMPHASIS_0;
2427 }
bc7d38a4 2428 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2429 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2430 case DP_TRAIN_VOLTAGE_SWING_400:
2431 return DP_TRAIN_PRE_EMPHASIS_6;
2432 case DP_TRAIN_VOLTAGE_SWING_600:
2433 case DP_TRAIN_VOLTAGE_SWING_800:
2434 return DP_TRAIN_PRE_EMPHASIS_3_5;
2435 default:
2436 return DP_TRAIN_PRE_EMPHASIS_0;
2437 }
2438 } else {
2439 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2440 case DP_TRAIN_VOLTAGE_SWING_400:
2441 return DP_TRAIN_PRE_EMPHASIS_6;
2442 case DP_TRAIN_VOLTAGE_SWING_600:
2443 return DP_TRAIN_PRE_EMPHASIS_6;
2444 case DP_TRAIN_VOLTAGE_SWING_800:
2445 return DP_TRAIN_PRE_EMPHASIS_3_5;
2446 case DP_TRAIN_VOLTAGE_SWING_1200:
2447 default:
2448 return DP_TRAIN_PRE_EMPHASIS_0;
2449 }
a4fc5ed6
KP		 2450 }
2451}
2452
e2fa6fba
P		 2453static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2454{
2455 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2456 struct drm_i915_private *dev_priv = dev->dev_private;
2457 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2458 struct intel_crtc *intel_crtc =
2459 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2460 unsigned long demph_reg_value, preemph_reg_value,
2461 uniqtranscale_reg_value;
2462 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2463 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2464 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2465
2466 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2467 case DP_TRAIN_PRE_EMPHASIS_0:
2468 preemph_reg_value = 0x0004000;
2469 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2470 case DP_TRAIN_VOLTAGE_SWING_400:
2471 demph_reg_value = 0x2B405555;
2472 uniqtranscale_reg_value = 0x552AB83A;
2473 break;
2474 case DP_TRAIN_VOLTAGE_SWING_600:
2475 demph_reg_value = 0x2B404040;
2476 uniqtranscale_reg_value = 0x5548B83A;
2477 break;
2478 case DP_TRAIN_VOLTAGE_SWING_800:
2479 demph_reg_value = 0x2B245555;
2480 uniqtranscale_reg_value = 0x5560B83A;
2481 break;
2482 case DP_TRAIN_VOLTAGE_SWING_1200:
2483 demph_reg_value = 0x2B405555;
2484 uniqtranscale_reg_value = 0x5598DA3A;
2485 break;
2486 default:
2487 return 0;
2488 }
2489 break;
2490 case DP_TRAIN_PRE_EMPHASIS_3_5:
2491 preemph_reg_value = 0x0002000;
2492 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2493 case DP_TRAIN_VOLTAGE_SWING_400:
2494 demph_reg_value = 0x2B404040;
2495 uniqtranscale_reg_value = 0x5552B83A;
2496 break;
2497 case DP_TRAIN_VOLTAGE_SWING_600:
2498 demph_reg_value = 0x2B404848;
2499 uniqtranscale_reg_value = 0x5580B83A;
2500 break;
2501 case DP_TRAIN_VOLTAGE_SWING_800:
2502 demph_reg_value = 0x2B404040;
2503 uniqtranscale_reg_value = 0x55ADDA3A;
2504 break;
2505 default:
2506 return 0;
2507 }
2508 break;
2509 case DP_TRAIN_PRE_EMPHASIS_6:
2510 preemph_reg_value = 0x0000000;
2511 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2512 case DP_TRAIN_VOLTAGE_SWING_400:
2513 demph_reg_value = 0x2B305555;
2514 uniqtranscale_reg_value = 0x5570B83A;
2515 break;
2516 case DP_TRAIN_VOLTAGE_SWING_600:
2517 demph_reg_value = 0x2B2B4040;
2518 uniqtranscale_reg_value = 0x55ADDA3A;
2519 break;
2520 default:
2521 return 0;
2522 }
2523 break;
2524 case DP_TRAIN_PRE_EMPHASIS_9_5:
2525 preemph_reg_value = 0x0006000;
2526 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2527 case DP_TRAIN_VOLTAGE_SWING_400:
2528 demph_reg_value = 0x1B405555;
2529 uniqtranscale_reg_value = 0x55ADDA3A;
2530 break;
2531 default:
2532 return 0;
2533 }
2534 break;
2535 default:
2536 return 0;
2537 }
2538
0980a60f 2539 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2540 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2541 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2542 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2543 uniqtranscale_reg_value);
ab3c759a
CML		 2544 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2545 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2546 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2547 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2548 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2549
2550 return 0;
2551}
2552
e4a1d846
CML		 2553static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2554{
2555 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2556 struct drm_i915_private *dev_priv = dev->dev_private;
2557 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2558 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2559 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2560 uint8_t train_set = intel_dp->train_set[0];
2561 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2562 enum pipe pipe = intel_crtc->pipe;
2563 int i;
e4a1d846
CML		 2564
2565 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2566 case DP_TRAIN_PRE_EMPHASIS_0:
2567 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2568 case DP_TRAIN_VOLTAGE_SWING_400:
2569 deemph_reg_value = 128;
2570 margin_reg_value = 52;
2571 break;
2572 case DP_TRAIN_VOLTAGE_SWING_600:
2573 deemph_reg_value = 128;
2574 margin_reg_value = 77;
2575 break;
2576 case DP_TRAIN_VOLTAGE_SWING_800:
2577 deemph_reg_value = 128;
2578 margin_reg_value = 102;
2579 break;
2580 case DP_TRAIN_VOLTAGE_SWING_1200:
2581 deemph_reg_value = 128;
2582 margin_reg_value = 154;
2583 /* FIXME extra to set for 1200 */
2584 break;
2585 default:
2586 return 0;
2587 }
2588 break;
2589 case DP_TRAIN_PRE_EMPHASIS_3_5:
2590 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2591 case DP_TRAIN_VOLTAGE_SWING_400:
2592 deemph_reg_value = 85;
2593 margin_reg_value = 78;
2594 break;
2595 case DP_TRAIN_VOLTAGE_SWING_600:
2596 deemph_reg_value = 85;
2597 margin_reg_value = 116;
2598 break;
2599 case DP_TRAIN_VOLTAGE_SWING_800:
2600 deemph_reg_value = 85;
2601 margin_reg_value = 154;
2602 break;
2603 default:
2604 return 0;
2605 }
2606 break;
2607 case DP_TRAIN_PRE_EMPHASIS_6:
2608 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2609 case DP_TRAIN_VOLTAGE_SWING_400:
2610 deemph_reg_value = 64;
2611 margin_reg_value = 104;
2612 break;
2613 case DP_TRAIN_VOLTAGE_SWING_600:
2614 deemph_reg_value = 64;
2615 margin_reg_value = 154;
2616 break;
2617 default:
2618 return 0;
2619 }
2620 break;
2621 case DP_TRAIN_PRE_EMPHASIS_9_5:
2622 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2623 case DP_TRAIN_VOLTAGE_SWING_400:
2624 deemph_reg_value = 43;
2625 margin_reg_value = 154;
2626 break;
2627 default:
2628 return 0;
2629 }
2630 break;
2631 default:
2632 return 0;
2633 }
2634
2635 mutex_lock(&dev_priv->dpio_lock);
2636
2637 /* Clear calc init */
1966e59e
VS		 2638 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2639 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2640 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2641
2642 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2643 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2644 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2645
2646 /* Program swing deemph */
f72df8db
VS		 2647 for (i = 0; i < 4; i++) {
2648 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2649 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2650 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2651 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2652 }
e4a1d846
CML		 2653
2654 /* Program swing margin */
f72df8db
VS		 2655 for (i = 0; i < 4; i++) {
2656 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2657 val &= ~DPIO_SWING_MARGIN_MASK;
2658 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2659 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2660 }
e4a1d846
CML		 2661
2662 /* Disable unique transition scale */
f72df8db
VS		 2663 for (i = 0; i < 4; i++) {
2664 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2665 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2666 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2667 }
e4a1d846
CML		 2668
2669 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2670 == DP_TRAIN_PRE_EMPHASIS_0) &&
2671 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2672 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2673
2674 /*
2675 * The document said it needs to set bit 27 for ch0 and bit 26
2676 * for ch1. Might be a typo in the doc.
2677 * For now, for this unique transition scale selection, set bit
2678 * 27 for ch0 and ch1.
2679 */
f72df8db
VS		 2680 for (i = 0; i < 4; i++) {
2681 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2682 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2683 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2684 }
e4a1d846 2685
f72df8db
VS		 2686 for (i = 0; i < 4; i++) {
2687 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2688 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2689 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2690 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2691 }
e4a1d846
CML		 2692 }
2693
2694 /* Start swing calculation */
1966e59e
VS		 2695 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2696 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2697 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2698
2699 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2700 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2701 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2702
2703 /* LRC Bypass */
2704 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2705 val |= DPIO_LRC_BYPASS;
2706 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2707
2708 mutex_unlock(&dev_priv->dpio_lock);
2709
2710 return 0;
2711}
2712
a4fc5ed6 2713static void
0301b3ac
JN		 2714intel_get_adjust_train(struct intel_dp *intel_dp,
2715 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2716{
2717 uint8_t v = 0;
2718 uint8_t p = 0;
2719 int lane;
1a2eb460
KP		 2720 uint8_t voltage_max;
2721 uint8_t preemph_max;
a4fc5ed6 2722
33a34e4e 2723 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2724 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2725 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2726
2727 if (this_v > v)
2728 v = this_v;
2729 if (this_p > p)
2730 p = this_p;
2731 }
2732
1a2eb460 2733 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2734 if (v >= voltage_max)
2735 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2736
1a2eb460
KP		 2737 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2738 if (p >= preemph_max)
2739 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2740
2741 for (lane = 0; lane < 4; lane++)
33a34e4e 2742 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2743}
2744
2745static uint32_t
f0a3424e 2746intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2747{
3cf2efb1 2748 uint32_t signal_levels = 0;
a4fc5ed6 2749
3cf2efb1 2750 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2751 case DP_TRAIN_VOLTAGE_SWING_400:
2752 default:
2753 signal_levels |= DP_VOLTAGE_0_4;
2754 break;
2755 case DP_TRAIN_VOLTAGE_SWING_600:
2756 signal_levels |= DP_VOLTAGE_0_6;
2757 break;
2758 case DP_TRAIN_VOLTAGE_SWING_800:
2759 signal_levels |= DP_VOLTAGE_0_8;
2760 break;
2761 case DP_TRAIN_VOLTAGE_SWING_1200:
2762 signal_levels |= DP_VOLTAGE_1_2;
2763 break;
2764 }
3cf2efb1 2765 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2766 case DP_TRAIN_PRE_EMPHASIS_0:
2767 default:
2768 signal_levels |= DP_PRE_EMPHASIS_0;
2769 break;
2770 case DP_TRAIN_PRE_EMPHASIS_3_5:
2771 signal_levels |= DP_PRE_EMPHASIS_3_5;
2772 break;
2773 case DP_TRAIN_PRE_EMPHASIS_6:
2774 signal_levels |= DP_PRE_EMPHASIS_6;
2775 break;
2776 case DP_TRAIN_PRE_EMPHASIS_9_5:
2777 signal_levels |= DP_PRE_EMPHASIS_9_5;
2778 break;
2779 }
2780 return signal_levels;
2781}
2782
e3421a18
ZW		 2783/* Gen6's DP voltage swing and pre-emphasis control */
2784static uint32_t
2785intel_gen6_edp_signal_levels(uint8_t train_set)
2786{
3c5a62b5
YL		 2787 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2788 DP_TRAIN_PRE_EMPHASIS_MASK);
2789 switch (signal_levels) {
e3421a18 2790 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2791 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2792 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2793 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2794 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2795 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2796 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2797 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2798 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2799 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2800 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2801 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2802 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2803 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2804 default:
3c5a62b5
YL		 2805 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2806 "0x%x\n", signal_levels);
2807 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2808 }
2809}
2810
1a2eb460
KP		 2811/* Gen7's DP voltage swing and pre-emphasis control */
2812static uint32_t
2813intel_gen7_edp_signal_levels(uint8_t train_set)
2814{
2815 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2816 DP_TRAIN_PRE_EMPHASIS_MASK);
2817 switch (signal_levels) {
2818 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2819 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2820 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2821 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2822 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2823 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2824
2825 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2826 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2827 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2828 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2829
2830 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2831 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2832 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2833 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2834
2835 default:
2836 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2837 "0x%x\n", signal_levels);
2838 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2839 }
2840}
2841
d6c0d722
PZ		 2842/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2843static uint32_t
f0a3424e 2844intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2845{
d6c0d722
PZ		 2846 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2847 DP_TRAIN_PRE_EMPHASIS_MASK);
2848 switch (signal_levels) {
2849 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2850 return DDI_BUF_EMP_400MV_0DB_HSW;
2851 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2852 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2853 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2854 return DDI_BUF_EMP_400MV_6DB_HSW;
2855 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2856 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2857
d6c0d722
PZ		 2858 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2859 return DDI_BUF_EMP_600MV_0DB_HSW;
2860 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2861 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2862 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2863 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2864
d6c0d722
PZ		 2865 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2866 return DDI_BUF_EMP_800MV_0DB_HSW;
2867 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2868 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2869 default:
2870 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2871 "0x%x\n", signal_levels);
2872 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2873 }
a4fc5ed6
KP		 2874}
2875
f0a3424e
PZ		 2876/* Properly updates "DP" with the correct signal levels. */
2877static void
2878intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2879{
2880 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2881 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2882 struct drm_device *dev = intel_dig_port->base.base.dev;
2883 uint32_t signal_levels, mask;
2884 uint8_t train_set = intel_dp->train_set[0];
2885
9576c27f 2886 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 2887 signal_levels = intel_hsw_signal_levels(train_set);
2888 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 2889 } else if (IS_CHERRYVIEW(dev)) {
2890 signal_levels = intel_chv_signal_levels(intel_dp);
2891 mask = 0;
e2fa6fba
P		 2892 } else if (IS_VALLEYVIEW(dev)) {
2893 signal_levels = intel_vlv_signal_levels(intel_dp);
2894 mask = 0;
bc7d38a4 2895 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2896 signal_levels = intel_gen7_edp_signal_levels(train_set);
2897 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2898 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2899 signal_levels = intel_gen6_edp_signal_levels(train_set);
2900 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2901 } else {
2902 signal_levels = intel_gen4_signal_levels(train_set);
2903 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2904 }
2905
2906 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2907
2908 *DP = (*DP & ~mask) | signal_levels;
2909}
2910
a4fc5ed6 2911static bool
ea5b213a 2912intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2913 uint32_t *DP,
58e10eb9 2914 uint8_t dp_train_pat)
a4fc5ed6 2915{
174edf1f
PZ		 2916 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2917 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2918 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2919 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2920 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2921 int ret, len;
a4fc5ed6 2922
22b8bf17 2923 if (HAS_DDI(dev)) {
3ab9c637 2924 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2925
2926 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2927 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2928 else
2929 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2930
2931 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2932 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2933 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2934 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2935
2936 break;
2937 case DP_TRAINING_PATTERN_1:
2938 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2939 break;
2940 case DP_TRAINING_PATTERN_2:
2941 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2942 break;
2943 case DP_TRAINING_PATTERN_3:
2944 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2945 break;
2946 }
174edf1f 2947 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2948
bc7d38a4 2949 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2950 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2951
2952 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2953 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2954 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2955 break;
2956 case DP_TRAINING_PATTERN_1:
70aff66c 2957 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2958 break;
2959 case DP_TRAINING_PATTERN_2:
70aff66c 2960 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2961 break;
2962 case DP_TRAINING_PATTERN_3:
2963 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2964 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2965 break;
2966 }
2967
2968 } else {
70aff66c 2969 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2970
2971 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2972 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2973 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2974 break;
2975 case DP_TRAINING_PATTERN_1:
70aff66c 2976 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2977 break;
2978 case DP_TRAINING_PATTERN_2:
70aff66c 2979 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2980 break;
2981 case DP_TRAINING_PATTERN_3:
2982 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2983 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2984 break;
2985 }
2986 }
2987
70aff66c 2988 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2989 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2990
2cdfe6c8
JN		 2991 buf[0] = dp_train_pat;
2992 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2993 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2994 /* don't write DP_TRAINING_LANEx_SET on disable */
2995 len = 1;
2996 } else {
2997 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2998 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2999 len = intel_dp->lane_count + 1;
47ea7542 3000 }
a4fc5ed6 3001
9d1a1031
JN		 3002 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3003 buf, len);
2cdfe6c8
JN		 3004
3005 return ret == len;
a4fc5ed6
KP		 3006}
3007
70aff66c
JN		 3008static bool
3009intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3010 uint8_t dp_train_pat)
3011{
953d22e8 3012 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3013 intel_dp_set_signal_levels(intel_dp, DP);
3014 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3015}
3016
3017static bool
3018intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3019 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3020{
3021 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3022 struct drm_device *dev = intel_dig_port->base.base.dev;
3023 struct drm_i915_private *dev_priv = dev->dev_private;
3024 int ret;
3025
3026 intel_get_adjust_train(intel_dp, link_status);
3027 intel_dp_set_signal_levels(intel_dp, DP);
3028
3029 I915_WRITE(intel_dp->output_reg, *DP);
3030 POSTING_READ(intel_dp->output_reg);
3031
9d1a1031
JN		 3032 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3033 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3034
3035 return ret == intel_dp->lane_count;
3036}
3037
3ab9c637
ID		 3038static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3039{
3040 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3041 struct drm_device *dev = intel_dig_port->base.base.dev;
3042 struct drm_i915_private *dev_priv = dev->dev_private;
3043 enum port port = intel_dig_port->port;
3044 uint32_t val;
3045
3046 if (!HAS_DDI(dev))
3047 return;
3048
3049 val = I915_READ(DP_TP_CTL(port));
3050 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3051 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3052 I915_WRITE(DP_TP_CTL(port), val);
3053
3054 /*
3055 * On PORT_A we can have only eDP in SST mode. There the only reason
3056 * we need to set idle transmission mode is to work around a HW issue
3057 * where we enable the pipe while not in idle link-training mode.
3058 * In this case there is requirement to wait for a minimum number of
3059 * idle patterns to be sent.
3060 */
3061 if (port == PORT_A)
3062 return;
3063
3064 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3065 1))
3066 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3067}
3068
33a34e4e 3069/* Enable corresponding port and start training pattern 1 */
c19b0669 3070void
33a34e4e 3071intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3072{
da63a9f2 3073 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3074 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3075 int i;
3076 uint8_t voltage;
cdb0e95b 3077 int voltage_tries, loop_tries;
ea5b213a 3078 uint32_t DP = intel_dp->DP;
6aba5b6c 3079 uint8_t link_config[2];
a4fc5ed6 3080
affa9354 3081 if (HAS_DDI(dev))
c19b0669
PZ		 3082 intel_ddi_prepare_link_retrain(encoder);
3083
3cf2efb1 3084 /* Write the link configuration data */
6aba5b6c
JN		 3085 link_config[0] = intel_dp->link_bw;
3086 link_config[1] = intel_dp->lane_count;
3087 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3088 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3089 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3090
3091 link_config[0] = 0;
3092 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3093 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3094
3095 DP |= DP_PORT_EN;
1a2eb460 3096
70aff66c
JN		 3097 /* clock recovery */
3098 if (!intel_dp_reset_link_train(intel_dp, &DP,
3099 DP_TRAINING_PATTERN_1 |
3100 DP_LINK_SCRAMBLING_DISABLE)) {
3101 DRM_ERROR("failed to enable link training\n");
3102 return;
3103 }
3104
a4fc5ed6 3105 voltage = 0xff;
cdb0e95b
KP		 3106 voltage_tries = 0;
3107 loop_tries = 0;
a4fc5ed6 3108 for (;;) {
70aff66c 3109 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3110
a7c9655f 3111 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3112 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3113 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3114 break;
93f62dad 3115 }
a4fc5ed6 3116
01916270 3117 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3118 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3119 break;
3120 }
3121
3122 /* Check to see if we've tried the max voltage */
3123 for (i = 0; i < intel_dp->lane_count; i++)
3124 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3125 break;
3b4f819d 3126 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3127 ++loop_tries;
3128 if (loop_tries == 5) {
3def84b3 3129 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3130 break;
3131 }
70aff66c
JN		 3132 intel_dp_reset_link_train(intel_dp, &DP,
3133 DP_TRAINING_PATTERN_1 |
3134 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3135 voltage_tries = 0;
3136 continue;
3137 }
a4fc5ed6 3138
3cf2efb1 3139 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3140 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3141 ++voltage_tries;
b06fbda3 3142 if (voltage_tries == 5) {
3def84b3 3143 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3144 break;
3145 }
3146 } else
3147 voltage_tries = 0;
3148 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3149
70aff66c
JN		 3150 /* Update training set as requested by target */
3151 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3152 DRM_ERROR("failed to update link training\n");
3153 break;
3154 }
a4fc5ed6
KP		 3155 }
3156
33a34e4e
JB		 3157 intel_dp->DP = DP;
3158}
3159
c19b0669 3160void
33a34e4e
JB		 3161intel_dp_complete_link_train(struct intel_dp *intel_dp)
3162{
33a34e4e 3163 bool channel_eq = false;
37f80975 3164 int tries, cr_tries;
33a34e4e 3165 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3166 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3167
3168 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3169 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3170 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3171
a4fc5ed6 3172 /* channel equalization */
70aff66c 3173 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3174 training_pattern |
70aff66c
JN		 3175 DP_LINK_SCRAMBLING_DISABLE)) {
3176 DRM_ERROR("failed to start channel equalization\n");
3177 return;
3178 }
3179
a4fc5ed6 3180 tries = 0;
37f80975 3181 cr_tries = 0;
a4fc5ed6
KP		 3182 channel_eq = false;
3183 for (;;) {
70aff66c 3184 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3185
37f80975
JB		 3186 if (cr_tries > 5) {
3187 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3188 break;
3189 }
3190
a7c9655f 3191 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3192 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3193 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3194 break;
70aff66c 3195 }
a4fc5ed6 3196
37f80975 3197 /* Make sure clock is still ok */
01916270 3198 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3199 intel_dp_start_link_train(intel_dp);
70aff66c 3200 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3201 training_pattern |
70aff66c 3202 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3203 cr_tries++;
3204 continue;
3205 }
3206
1ffdff13 3207 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3208 channel_eq = true;
3209 break;
3210 }
a4fc5ed6 3211
37f80975
JB		 3212 /* Try 5 times, then try clock recovery if that fails */
3213 if (tries > 5) {
3214 intel_dp_link_down(intel_dp);
3215 intel_dp_start_link_train(intel_dp);
70aff66c 3216 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3217 training_pattern |
70aff66c 3218 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3219 tries = 0;
3220 cr_tries++;
3221 continue;
3222 }
a4fc5ed6 3223
70aff66c
JN		 3224 /* Update training set as requested by target */
3225 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3226 DRM_ERROR("failed to update link training\n");
3227 break;
3228 }
3cf2efb1 3229 ++tries;
869184a6 3230 }
3cf2efb1 3231
3ab9c637
ID		 3232 intel_dp_set_idle_link_train(intel_dp);
3233
3234 intel_dp->DP = DP;
3235
d6c0d722 3236 if (channel_eq)
07f42258 3237 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3238
3ab9c637
ID		 3239}
3240
3241void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3242{
70aff66c 3243 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3244 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3245}
3246
3247static void
ea5b213a 3248intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3249{
da63a9f2 3250 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3251 enum port port = intel_dig_port->port;
da63a9f2 3252 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3253 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3254 struct intel_crtc *intel_crtc =
3255 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3256 uint32_t DP = intel_dp->DP;
a4fc5ed6 3257
bc76e320 3258 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3259 return;
3260
0c33d8d7 3261 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3262 return;
3263
28c97730 3264 DRM_DEBUG_KMS("\n");
32f9d658 3265
bc7d38a4 3266 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3267 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3268 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 3269 } else {
3270 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3271 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3272 }
fe255d00 3273 POSTING_READ(intel_dp->output_reg);
5eb08b69 3274
493a7081 3275 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3276 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3277 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3278
5bddd17f
EA		 3279 /* Hardware workaround: leaving our transcoder select
3280 * set to transcoder B while it's off will prevent the
3281 * corresponding HDMI output on transcoder A.
3282 *
3283 * Combine this with another hardware workaround:
3284 * transcoder select bit can only be cleared while the
3285 * port is enabled.
3286 */
3287 DP &= ~DP_PIPEB_SELECT;
3288 I915_WRITE(intel_dp->output_reg, DP);
3289
3290 /* Changes to enable or select take place the vblank
3291 * after being written.
3292 */
ff50afe9
DV		 3293 if (WARN_ON(crtc == NULL)) {
3294 /* We should never try to disable a port without a crtc
3295 * attached. For paranoia keep the code around for a
3296 * bit. */
31acbcc4
CW		 3297 POSTING_READ(intel_dp->output_reg);
3298 msleep(50);
3299 } else
ab527efc 3300 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3301 }
3302
832afda6 3303 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3304 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3305 POSTING_READ(intel_dp->output_reg);
f01eca2e 3306 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3307}
3308
26d61aad
KP		 3309static bool
3310intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3311{
a031d709
RV		 3312 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3313 struct drm_device *dev = dig_port->base.base.dev;
3314 struct drm_i915_private *dev_priv = dev->dev_private;
3315
577c7a50
DL		 3316 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3317
9d1a1031
JN		 3318 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3319 sizeof(intel_dp->dpcd)) < 0)
edb39244 3320 return false; /* aux transfer failed */
92fd8fd1 3321
577c7a50
DL		 3322 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3323 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3324 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3325
edb39244
AJ		 3326 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3327 return false; /* DPCD not present */
3328
2293bb5c
SK		 3329 /* Check if the panel supports PSR */
3330 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3331 if (is_edp(intel_dp)) {
9d1a1031
JN		 3332 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3333 intel_dp->psr_dpcd,
3334 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3335 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3336 dev_priv->psr.sink_support = true;
50003939 3337 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3338 }
50003939
JN		 3339 }
3340
06ea66b6
TP		 3341 /* Training Pattern 3 support */
3342 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3343 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3344 intel_dp->use_tps3 = true;
3345 DRM_DEBUG_KMS("Displayport TPS3 supported");
3346 } else
3347 intel_dp->use_tps3 = false;
3348
edb39244
AJ		 3349 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3350 DP_DWN_STRM_PORT_PRESENT))
3351 return true; /* native DP sink */
3352
3353 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3354 return true; /* no per-port downstream info */
3355
9d1a1031
JN		 3356 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3357 intel_dp->downstream_ports,
3358 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3359 return false; /* downstream port status fetch failed */
3360
3361 return true;
92fd8fd1
KP		 3362}
3363
0d198328
AJ		 3364static void
3365intel_dp_probe_oui(struct intel_dp *intel_dp)
3366{
3367 u8 buf[3];
3368
3369 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3370 return;
3371
24f3e092 3372 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3373
9d1a1031 3374 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3375 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3376 buf[0], buf[1], buf[2]);
3377
9d1a1031 3378 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3379 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3380 buf[0], buf[1], buf[2]);
351cfc34 3381
4be73780 3382 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3383}
3384
0e32b39c
DA		 3385static bool
3386intel_dp_probe_mst(struct intel_dp *intel_dp)
3387{
3388 u8 buf[1];
3389
3390 if (!intel_dp->can_mst)
3391 return false;
3392
3393 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3394 return false;
3395
3396 _edp_panel_vdd_on(intel_dp);
3397 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3398 if (buf[0] & DP_MST_CAP) {
3399 DRM_DEBUG_KMS("Sink is MST capable\n");
3400 intel_dp->is_mst = true;
3401 } else {
3402 DRM_DEBUG_KMS("Sink is not MST capable\n");
3403 intel_dp->is_mst = false;
3404 }
3405 }
3406 edp_panel_vdd_off(intel_dp, false);
3407
3408 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3409 return intel_dp->is_mst;
3410}
3411
d2e216d0
RV		 3412int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3413{
3414 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3415 struct drm_device *dev = intel_dig_port->base.base.dev;
3416 struct intel_crtc *intel_crtc =
3417 to_intel_crtc(intel_dig_port->base.base.crtc);
3418 u8 buf[1];
3419
9d1a1031 3420 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3421 return -EAGAIN;
3422
3423 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3424 return -ENOTTY;
3425
9d1a1031
JN		 3426 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3427 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3428 return -EAGAIN;
3429
3430 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3431 intel_wait_for_vblank(dev, intel_crtc->pipe);
3432 intel_wait_for_vblank(dev, intel_crtc->pipe);
3433
9d1a1031 3434 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3435 return -EAGAIN;
3436
9d1a1031 3437 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3438 return 0;
3439}
3440
a60f0e38
JB		 3441static bool
3442intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3443{
9d1a1031
JN		 3444 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3445 DP_DEVICE_SERVICE_IRQ_VECTOR,
3446 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3447}
3448
0e32b39c
DA		 3449static bool
3450intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3451{
3452 int ret;
3453
3454 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3455 DP_SINK_COUNT_ESI,
3456 sink_irq_vector, 14);
3457 if (ret != 14)
3458 return false;
3459
3460 return true;
3461}
3462
a60f0e38
JB		 3463static void
3464intel_dp_handle_test_request(struct intel_dp *intel_dp)
3465{
3466 /* NAK by default */
9d1a1031 3467 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3468}
3469
0e32b39c
DA		 3470static int
3471intel_dp_check_mst_status(struct intel_dp *intel_dp)
3472{
3473 bool bret;
3474
3475 if (intel_dp->is_mst) {
3476 u8 esi[16] = { 0 };
3477 int ret = 0;
3478 int retry;
3479 bool handled;
3480 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3481go_again:
3482 if (bret == true) {
3483
3484 /* check link status - esi[10] = 0x200c */
3485 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3486 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3487 intel_dp_start_link_train(intel_dp);
3488 intel_dp_complete_link_train(intel_dp);
3489 intel_dp_stop_link_train(intel_dp);
3490 }
3491
3492 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3493 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3494
3495 if (handled) {
3496 for (retry = 0; retry < 3; retry++) {
3497 int wret;
3498 wret = drm_dp_dpcd_write(&intel_dp->aux,
3499 DP_SINK_COUNT_ESI+1,
3500 &esi[1], 3);
3501 if (wret == 3) {
3502 break;
3503 }
3504 }
3505
3506 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3507 if (bret == true) {
3508 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3509 goto go_again;
3510 }
3511 } else
3512 ret = 0;
3513
3514 return ret;
3515 } else {
3516 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3517 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3518 intel_dp->is_mst = false;
3519 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3520 /* send a hotplug event */
3521 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3522 }
3523 }
3524 return -EINVAL;
3525}
3526
a4fc5ed6
KP		 3527/*
3528 * According to DP spec
3529 * 5.1.2:
3530 * 1. Read DPCD
3531 * 2. Configure link according to Receiver Capabilities
3532 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3533 * 4. Check link status on receipt of hot-plug interrupt
3534 */
00c09d70 3535void
ea5b213a 3536intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3537{
da63a9f2 3538 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3539 u8 sink_irq_vector;
93f62dad 3540 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3541
6e9f798d 3542 /* FIXME: This access isn't protected by any locks. */
da63a9f2 3543 if (!intel_encoder->connectors_active)
d2b996ac 3544 return;
59cd09e1 3545
da63a9f2 3546 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3547 return;
3548
92fd8fd1 3549 /* Try to read receiver status if the link appears to be up */
93f62dad 3550 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3551 return;
3552 }
3553
92fd8fd1 3554 /* Now read the DPCD to see if it's actually running */
26d61aad 3555 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3556 return;
3557 }
3558
a60f0e38
JB		 3559 /* Try to read the source of the interrupt */
3560 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3561 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3562 /* Clear interrupt source */
9d1a1031
JN		 3563 drm_dp_dpcd_writeb(&intel_dp->aux,
3564 DP_DEVICE_SERVICE_IRQ_VECTOR,
3565 sink_irq_vector);
a60f0e38
JB		 3566
3567 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3568 intel_dp_handle_test_request(intel_dp);
3569 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3570 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3571 }
3572
1ffdff13 3573 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3574 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3575 intel_encoder->base.name);
33a34e4e
JB		 3576 intel_dp_start_link_train(intel_dp);
3577 intel_dp_complete_link_train(intel_dp);
3ab9c637 3578 intel_dp_stop_link_train(intel_dp);
33a34e4e 3579 }
a4fc5ed6 3580}
a4fc5ed6 3581
caf9ab24 3582/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3583static enum drm_connector_status
26d61aad 3584intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3585{
caf9ab24 3586 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3587 uint8_t type;
3588
3589 if (!intel_dp_get_dpcd(intel_dp))
3590 return connector_status_disconnected;
3591
3592 /* if there's no downstream port, we're done */
3593 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3594 return connector_status_connected;
caf9ab24
AJ		 3595
3596 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3597 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3598 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3599 uint8_t reg;
9d1a1031
JN		 3600
3601 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3602 &reg, 1) < 0)
caf9ab24 3603 return connector_status_unknown;
9d1a1031 3604
23235177
AJ		 3605 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3606 : connector_status_disconnected;
caf9ab24
AJ		 3607 }
3608
3609 /* If no HPD, poke DDC gently */
0b99836f 3610 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3611 return connector_status_connected;
caf9ab24
AJ		 3612
3613 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3614 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3615 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3616 if (type == DP_DS_PORT_TYPE_VGA ||
3617 type == DP_DS_PORT_TYPE_NON_EDID)
3618 return connector_status_unknown;
3619 } else {
3620 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3621 DP_DWN_STRM_PORT_TYPE_MASK;
3622 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3623 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3624 return connector_status_unknown;
3625 }
caf9ab24
AJ		 3626
3627 /* Anything else is out of spec, warn and ignore */
3628 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3629 return connector_status_disconnected;
71ba9000
AJ		 3630}
3631
5eb08b69 3632static enum drm_connector_status
a9756bb5 3633ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3634{
30add22d 3635 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3636 struct drm_i915_private *dev_priv = dev->dev_private;
3637 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3638 enum drm_connector_status status;
3639
fe16d949
CW		 3640 /* Can't disconnect eDP, but you can close the lid... */
3641 if (is_edp(intel_dp)) {
30add22d 3642 status = intel_panel_detect(dev);
fe16d949
CW		 3643 if (status == connector_status_unknown)
3644 status = connector_status_connected;
3645 return status;
3646 }
01cb9ea6 3647
1b469639
DL		 3648 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3649 return connector_status_disconnected;
3650
26d61aad 3651 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3652}
3653
a4fc5ed6 3654static enum drm_connector_status
a9756bb5 3655g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3656{
30add22d 3657 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3658 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3659 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3660 uint32_t bit;
5eb08b69 3661
35aad75f
JB		 3662 /* Can't disconnect eDP, but you can close the lid... */
3663 if (is_edp(intel_dp)) {
3664 enum drm_connector_status status;
3665
3666 status = intel_panel_detect(dev);
3667 if (status == connector_status_unknown)
3668 status = connector_status_connected;
3669 return status;
3670 }
3671
232a6ee9
TP		 3672 if (IS_VALLEYVIEW(dev)) {
3673 switch (intel_dig_port->port) {
3674 case PORT_B:
3675 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3676 break;
3677 case PORT_C:
3678 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3679 break;
3680 case PORT_D:
3681 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3682 break;
3683 default:
3684 return connector_status_unknown;
3685 }
3686 } else {
3687 switch (intel_dig_port->port) {
3688 case PORT_B:
3689 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3690 break;
3691 case PORT_C:
3692 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3693 break;
3694 case PORT_D:
3695 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3696 break;
3697 default:
3698 return connector_status_unknown;
3699 }
a4fc5ed6
KP		 3700 }
3701
10f76a38 3702 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3703 return connector_status_disconnected;
3704
26d61aad 3705 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3706}
3707
8c241fef
KP		 3708static struct edid *
3709intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3710{
9cd300e0 3711 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3712
9cd300e0
JN		 3713 /* use cached edid if we have one */
3714 if (intel_connector->edid) {
9cd300e0
JN		 3715 /* invalid edid */
3716 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3717 return NULL;
3718
55e9edeb 3719 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3720 }
8c241fef 3721
9cd300e0 3722 return drm_get_edid(connector, adapter);
8c241fef
KP		 3723}
3724
3725static int
3726intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3727{
9cd300e0 3728 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3729
9cd300e0
JN		 3730 /* use cached edid if we have one */
3731 if (intel_connector->edid) {
3732 /* invalid edid */
3733 if (IS_ERR(intel_connector->edid))
3734 return 0;
3735
3736 return intel_connector_update_modes(connector,
3737 intel_connector->edid);
d6f24d0f
JB		 3738 }
3739
9cd300e0 3740 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3741}
3742
a9756bb5
ZW		 3743static enum drm_connector_status
3744intel_dp_detect(struct drm_connector *connector, bool force)
3745{
3746 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3747 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3748 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3749 struct drm_device *dev = connector->dev;
c8c8fb33 3750 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3751 enum drm_connector_status status;
671dedd2 3752 enum intel_display_power_domain power_domain;
a9756bb5 3753 struct edid *edid = NULL;
0e32b39c 3754 bool ret;
a9756bb5 3755
671dedd2
ID		 3756 power_domain = intel_display_port_power_domain(intel_encoder);
3757 intel_display_power_get(dev_priv, power_domain);
3758
164c8598 3759 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 3760 connector->base.id, connector->name);
164c8598 3761
0e32b39c
DA		 3762 if (intel_dp->is_mst) {
3763 /* MST devices are disconnected from a monitor POV */
3764 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3765 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3766 status = connector_status_disconnected;
3767 goto out;
3768 }
3769
a9756bb5
ZW		 3770 intel_dp->has_audio = false;
3771
3772 if (HAS_PCH_SPLIT(dev))
3773 status = ironlake_dp_detect(intel_dp);
3774 else
3775 status = g4x_dp_detect(intel_dp);
1b9be9d0 3776
a9756bb5 3777 if (status != connector_status_connected)
c8c8fb33 3778 goto out;
a9756bb5 3779
0d198328
AJ		 3780 intel_dp_probe_oui(intel_dp);
3781
0e32b39c
DA		 3782 ret = intel_dp_probe_mst(intel_dp);
3783 if (ret) {
3784 /* if we are in MST mode then this connector
3785 won't appear connected or have anything with EDID on it */
3786 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3787 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3788 status = connector_status_disconnected;
3789 goto out;
3790 }
3791
c3e5f67b
DV		 3792 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3793 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3794 } else {
0b99836f 3795 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3796 if (edid) {
3797 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3798 kfree(edid);
3799 }
a9756bb5
ZW		 3800 }
3801
d63885da
PZ		 3802 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3803 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3804 status = connector_status_connected;
3805
3806out:
671dedd2 3807 intel_display_power_put(dev_priv, power_domain);
c8c8fb33 3808 return status;
a4fc5ed6
KP		 3809}
3810
3811static int intel_dp_get_modes(struct drm_connector *connector)
3812{
df0e9248 3813 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3814 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3815 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3816 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3817 struct drm_device *dev = connector->dev;
671dedd2
ID		 3818 struct drm_i915_private *dev_priv = dev->dev_private;
3819 enum intel_display_power_domain power_domain;
32f9d658 3820 int ret;
a4fc5ed6
KP		 3821
3822 /* We should parse the EDID data and find out if it has an audio sink
3823 */
3824
671dedd2
ID		 3825 power_domain = intel_display_port_power_domain(intel_encoder);
3826 intel_display_power_get(dev_priv, power_domain);
3827
0b99836f 3828 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3829 intel_display_power_put(dev_priv, power_domain);
f8779fda 3830 if (ret)
32f9d658
ZW		 3831 return ret;
3832
f8779fda 3833 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3834 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3835 struct drm_display_mode *mode;
dd06f90e
JN		 3836 mode = drm_mode_duplicate(dev,
3837 intel_connector->panel.fixed_mode);
f8779fda 3838 if (mode) {
32f9d658
ZW		 3839 drm_mode_probed_add(connector, mode);
3840 return 1;
3841 }
3842 }
3843 return 0;
a4fc5ed6
KP		 3844}
3845
1aad7ac0
CW		 3846static bool
3847intel_dp_detect_audio(struct drm_connector *connector)
3848{
3849 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3850 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3851 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3852 struct drm_device *dev = connector->dev;
3853 struct drm_i915_private *dev_priv = dev->dev_private;
3854 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3855 struct edid *edid;
3856 bool has_audio = false;
3857
671dedd2
ID		 3858 power_domain = intel_display_port_power_domain(intel_encoder);
3859 intel_display_power_get(dev_priv, power_domain);
3860
0b99836f 3861 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3862 if (edid) {
3863 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3864 kfree(edid);
3865 }
3866
671dedd2
ID		 3867 intel_display_power_put(dev_priv, power_domain);
3868
1aad7ac0
CW		 3869 return has_audio;
3870}
3871
f684960e
CW		 3872static int
3873intel_dp_set_property(struct drm_connector *connector,
3874 struct drm_property *property,
3875 uint64_t val)
3876{
e953fd7b 3877 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3878 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3879 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3880 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3881 int ret;
3882
662595df 3883 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3884 if (ret)
3885 return ret;
3886
3f43c48d 3887 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3888 int i = val;
3889 bool has_audio;
3890
3891 if (i == intel_dp->force_audio)
f684960e
CW		 3892 return 0;
3893
1aad7ac0 3894 intel_dp->force_audio = i;
f684960e 3895
c3e5f67b 3896 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3897 has_audio = intel_dp_detect_audio(connector);
3898 else
c3e5f67b 3899 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3900
3901 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3902 return 0;
3903
1aad7ac0 3904 intel_dp->has_audio = has_audio;
f684960e
CW		 3905 goto done;
3906 }
3907
e953fd7b 3908 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3909 bool old_auto = intel_dp->color_range_auto;
3910 uint32_t old_range = intel_dp->color_range;
3911
55bc60db
VS		 3912 switch (val) {
3913 case INTEL_BROADCAST_RGB_AUTO:
3914 intel_dp->color_range_auto = true;
3915 break;
3916 case INTEL_BROADCAST_RGB_FULL:
3917 intel_dp->color_range_auto = false;
3918 intel_dp->color_range = 0;
3919 break;
3920 case INTEL_BROADCAST_RGB_LIMITED:
3921 intel_dp->color_range_auto = false;
3922 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3923 break;
3924 default:
3925 return -EINVAL;
3926 }
ae4edb80
DV		 3927
3928 if (old_auto == intel_dp->color_range_auto &&
3929 old_range == intel_dp->color_range)
3930 return 0;
3931
e953fd7b
CW		 3932 goto done;
3933 }
3934
53b41837
YN		 3935 if (is_edp(intel_dp) &&
3936 property == connector->dev->mode_config.scaling_mode_property) {
3937 if (val == DRM_MODE_SCALE_NONE) {
3938 DRM_DEBUG_KMS("no scaling not supported\n");
3939 return -EINVAL;
3940 }
3941
3942 if (intel_connector->panel.fitting_mode == val) {
3943 /* the eDP scaling property is not changed */
3944 return 0;
3945 }
3946 intel_connector->panel.fitting_mode = val;
3947
3948 goto done;
3949 }
3950
f684960e
CW		 3951 return -EINVAL;
3952
3953done:
c0c36b94
CW		 3954 if (intel_encoder->base.crtc)
3955 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3956
3957 return 0;
3958}
3959
a4fc5ed6 3960static void
73845adf 3961intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3962{
1d508706 3963 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3964
9cd300e0
JN		 3965 if (!IS_ERR_OR_NULL(intel_connector->edid))
3966 kfree(intel_connector->edid);
3967
acd8db10
PZ		 3968 /* Can't call is_edp() since the encoder may have been destroyed
3969 * already. */
3970 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3971 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3972
a4fc5ed6 3973 drm_connector_cleanup(connector);
55f78c43 3974 kfree(connector);
a4fc5ed6
KP		 3975}
3976
00c09d70 3977void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3978{
da63a9f2
PZ		 3979 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3980 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3981 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 3982
4f71d0cb 3983 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 3984 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 3985 drm_encoder_cleanup(encoder);
bd943159
KP		 3986 if (is_edp(intel_dp)) {
3987 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 3988 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 3989 edp_panel_vdd_off_sync(intel_dp);
51fd371b 3990 drm_modeset_unlock(&dev->mode_config.connection_mutex);
01527b31
CT		 3991 if (intel_dp->edp_notifier.notifier_call) {
3992 unregister_reboot_notifier(&intel_dp->edp_notifier);
3993 intel_dp->edp_notifier.notifier_call = NULL;
3994 }
bd943159 3995 }
da63a9f2 3996 kfree(intel_dig_port);
24d05927
DV		 3997}
3998
a4fc5ed6 3999static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4000 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 4001 .detect = intel_dp_detect,
4002 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4003 .set_property = intel_dp_set_property,
73845adf 4004 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4005};
4006
4007static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4008 .get_modes = intel_dp_get_modes,
4009 .mode_valid = intel_dp_mode_valid,
df0e9248 4010 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4011};
4012
a4fc5ed6 4013static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 4014 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4015};
4016
0e32b39c 4017void
21d40d37 4018intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4019{
0e32b39c 4020 return;
c8110e52 4021}
6207937d 4022
13cf5504
DA		 4023bool
4024intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4025{
4026 struct intel_dp *intel_dp = &intel_dig_port->dp;
0e32b39c
DA		 4027 struct drm_device *dev = intel_dig_port->base.base.dev;
4028 struct drm_i915_private *dev_priv = dev->dev_private;
4029 int ret;
4030 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4031 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4032
0e32b39c
DA		 4033 DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port,
4034 long_hpd ? "long" : "short");
13cf5504 4035
0e32b39c
DA		 4036 if (long_hpd) {
4037 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4038 goto mst_fail;
4039
4040 if (!intel_dp_get_dpcd(intel_dp)) {
4041 goto mst_fail;
4042 }
4043
4044 intel_dp_probe_oui(intel_dp);
4045
4046 if (!intel_dp_probe_mst(intel_dp))
4047 goto mst_fail;
4048
4049 } else {
4050 if (intel_dp->is_mst) {
4051 ret = intel_dp_check_mst_status(intel_dp);
4052 if (ret == -EINVAL)
4053 goto mst_fail;
4054 }
4055
4056 if (!intel_dp->is_mst) {
4057 /*
4058 * we'll check the link status via the normal hot plug path later -
4059 * but for short hpds we should check it now
4060 */
4061 intel_dp_check_link_status(intel_dp);
4062 }
4063 }
13cf5504 4064 return false;
0e32b39c
DA		 4065mst_fail:
4066 /* if we were in MST mode, and device is not there get out of MST mode */
4067 if (intel_dp->is_mst) {
4068 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4069 intel_dp->is_mst = false;
4070 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4071 }
4072 return true;
13cf5504
DA		 4073}
4074
e3421a18
ZW		 4075/* Return which DP Port should be selected for Transcoder DP control */
4076int
0206e353 4077intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4078{
4079 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4080 struct intel_encoder *intel_encoder;
4081 struct intel_dp *intel_dp;
e3421a18 4082
fa90ecef
PZ		 4083 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4084 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4085
fa90ecef
PZ		 4086 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4087 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4088 return intel_dp->output_reg;
e3421a18 4089 }
ea5b213a 4090
e3421a18
ZW		 4091 return -1;
4092}
4093
36e83a18 4094/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4095bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4096{
4097 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4098 union child_device_config *p_child;
36e83a18 4099 int i;
5d8a7752
VS		 4100 static const short port_mapping[] = {
4101 [PORT_B] = PORT_IDPB,
4102 [PORT_C] = PORT_IDPC,
4103 [PORT_D] = PORT_IDPD,
4104 };
36e83a18 4105
3b32a35b
VS		 4106 if (port == PORT_A)
4107 return true;
4108
41aa3448 4109 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4110 return false;
4111
41aa3448
RV		 4112 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4113 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4114
5d8a7752 4115 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4116 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4117 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4118 return true;
4119 }
4120 return false;
4121}
4122
0e32b39c 4123void
f684960e
CW		 4124intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4125{
53b41837
YN		 4126 struct intel_connector *intel_connector = to_intel_connector(connector);
4127
3f43c48d 4128 intel_attach_force_audio_property(connector);
e953fd7b 4129 intel_attach_broadcast_rgb_property(connector);
55bc60db 4130 intel_dp->color_range_auto = true;
53b41837
YN		 4131
4132 if (is_edp(intel_dp)) {
4133 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4134 drm_object_attach_property(
4135 &connector->base,
53b41837 4136 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4137 DRM_MODE_SCALE_ASPECT);
4138 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4139 }
f684960e
CW		 4140}
4141
dada1a9f
ID		 4142static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4143{
4144 intel_dp->last_power_cycle = jiffies;
4145 intel_dp->last_power_on = jiffies;
4146 intel_dp->last_backlight_off = jiffies;
4147}
4148
67a54566
DV		 4149static void
4150intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4151 struct intel_dp *intel_dp,
4152 struct edp_power_seq *out)
67a54566
DV		 4153{
4154 struct drm_i915_private *dev_priv = dev->dev_private;
4155 struct edp_power_seq cur, vbt, spec, final;
4156 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4157 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 4158
4159 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4160 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4161 pp_on_reg = PCH_PP_ON_DELAYS;
4162 pp_off_reg = PCH_PP_OFF_DELAYS;
4163 pp_div_reg = PCH_PP_DIVISOR;
4164 } else {
bf13e81b
JN		 4165 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4166
4167 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4168 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4169 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4170 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4171 }
67a54566
DV		 4172
4173 /* Workaround: Need to write PP_CONTROL with the unlock key as
4174 * the very first thing. */
453c5420 4175 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4176 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4177
453c5420
JB		 4178 pp_on = I915_READ(pp_on_reg);
4179 pp_off = I915_READ(pp_off_reg);
4180 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4181
4182 /* Pull timing values out of registers */
4183 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4184 PANEL_POWER_UP_DELAY_SHIFT;
4185
4186 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4187 PANEL_LIGHT_ON_DELAY_SHIFT;
4188
4189 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4190 PANEL_LIGHT_OFF_DELAY_SHIFT;
4191
4192 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4193 PANEL_POWER_DOWN_DELAY_SHIFT;
4194
4195 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4196 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4197
4198 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4199 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4200
41aa3448 4201 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4202
4203 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4204 * our hw here, which are all in 100usec. */
4205 spec.t1_t3 = 210 * 10;
4206 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4207 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4208 spec.t10 = 500 * 10;
4209 /* This one is special and actually in units of 100ms, but zero
4210 * based in the hw (so we need to add 100 ms). But the sw vbt
4211 * table multiplies it with 1000 to make it in units of 100usec,
4212 * too. */
4213 spec.t11_t12 = (510 + 100) * 10;
4214
4215 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4216 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4217
4218 /* Use the max of the register settings and vbt. If both are
4219 * unset, fall back to the spec limits. */
4220#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4221 spec.field : \
4222 max(cur.field, vbt.field))
4223 assign_final(t1_t3);
4224 assign_final(t8);
4225 assign_final(t9);
4226 assign_final(t10);
4227 assign_final(t11_t12);
4228#undef assign_final
4229
4230#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4231 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4232 intel_dp->backlight_on_delay = get_delay(t8);
4233 intel_dp->backlight_off_delay = get_delay(t9);
4234 intel_dp->panel_power_down_delay = get_delay(t10);
4235 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4236#undef get_delay
4237
f30d26e4
JN		 4238 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4239 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4240 intel_dp->panel_power_cycle_delay);
4241
4242 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4243 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4244
4245 if (out)
4246 *out = final;
4247}
4248
4249static void
4250intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4251 struct intel_dp *intel_dp,
4252 struct edp_power_seq *seq)
4253{
4254 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4255 u32 pp_on, pp_off, pp_div, port_sel = 0;
4256 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4257 int pp_on_reg, pp_off_reg, pp_div_reg;
4258
4259 if (HAS_PCH_SPLIT(dev)) {
4260 pp_on_reg = PCH_PP_ON_DELAYS;
4261 pp_off_reg = PCH_PP_OFF_DELAYS;
4262 pp_div_reg = PCH_PP_DIVISOR;
4263 } else {
bf13e81b
JN		 4264 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4265
4266 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4267 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4268 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4269 }
4270
b2f19d1a
PZ		 4271 /*
4272 * And finally store the new values in the power sequencer. The
4273 * backlight delays are set to 1 because we do manual waits on them. For
4274 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4275 * we'll end up waiting for the backlight off delay twice: once when we
4276 * do the manual sleep, and once when we disable the panel and wait for
4277 * the PP_STATUS bit to become zero.
4278 */
f30d26e4 4279 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4280 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4281 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4282 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4283 /* Compute the divisor for the pp clock, simply match the Bspec
4284 * formula. */
453c5420 4285 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4286 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4287 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4288
4289 /* Haswell doesn't have any port selection bits for the panel
4290 * power sequencer any more. */
bc7d38a4 4291 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 4292 if (dp_to_dig_port(intel_dp)->port == PORT_B)
4293 port_sel = PANEL_PORT_SELECT_DPB_VLV;
4294 else
4295 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 4296 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4297 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 4298 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4299 else
a24c144c 4300 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4301 }
4302
453c5420
JB		 4303 pp_on |= port_sel;
4304
4305 I915_WRITE(pp_on_reg, pp_on);
4306 I915_WRITE(pp_off_reg, pp_off);
4307 I915_WRITE(pp_div_reg, pp_div);
67a54566 4308
67a54566 4309 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4310 I915_READ(pp_on_reg),
4311 I915_READ(pp_off_reg),
4312 I915_READ(pp_div_reg));
f684960e
CW		 4313}
4314
439d7ac0
PB		 4315void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4316{
4317 struct drm_i915_private *dev_priv = dev->dev_private;
4318 struct intel_encoder *encoder;
4319 struct intel_dp *intel_dp = NULL;
4320 struct intel_crtc_config *config = NULL;
4321 struct intel_crtc *intel_crtc = NULL;
4322 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4323 u32 reg, val;
4324 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4325
4326 if (refresh_rate <= 0) {
4327 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4328 return;
4329 }
4330
4331 if (intel_connector == NULL) {
4332 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4333 return;
4334 }
4335
1fcc9d1c
DV		 4336 /*
4337 * FIXME: This needs proper synchronization with psr state. But really
4338 * hard to tell without seeing the user of this function of this code.
4339 * Check locking and ordering once that lands.
4340 */
439d7ac0
PB		 4341 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4342 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4343 return;
4344 }
4345
4346 encoder = intel_attached_encoder(&intel_connector->base);
4347 intel_dp = enc_to_intel_dp(&encoder->base);
4348 intel_crtc = encoder->new_crtc;
4349
4350 if (!intel_crtc) {
4351 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4352 return;
4353 }
4354
4355 config = &intel_crtc->config;
4356
4357 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4358 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4359 return;
4360 }
4361
4362 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4363 index = DRRS_LOW_RR;
4364
4365 if (index == intel_dp->drrs_state.refresh_rate_type) {
4366 DRM_DEBUG_KMS(
4367 "DRRS requested for previously set RR...ignoring\n");
4368 return;
4369 }
4370
4371 if (!intel_crtc->active) {
4372 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4373 return;
4374 }
4375
4376 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4377 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4378 val = I915_READ(reg);
4379 if (index > DRRS_HIGH_RR) {
4380 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4381 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
4382 } else {
4383 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4384 }
4385 I915_WRITE(reg, val);
4386 }
4387
4388 /*
4389 * mutex taken to ensure that there is no race between differnt
4390 * drrs calls trying to update refresh rate. This scenario may occur
4391 * in future when idleness detection based DRRS in kernel and
4392 * possible calls from user space to set differnt RR are made.
4393 */
4394
4395 mutex_lock(&intel_dp->drrs_state.mutex);
4396
4397 intel_dp->drrs_state.refresh_rate_type = index;
4398
4399 mutex_unlock(&intel_dp->drrs_state.mutex);
4400
4401 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4402}
4403
4f9db5b5
PB		 4404static struct drm_display_mode *
4405intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4406 struct intel_connector *intel_connector,
4407 struct drm_display_mode *fixed_mode)
4408{
4409 struct drm_connector *connector = &intel_connector->base;
4410 struct intel_dp *intel_dp = &intel_dig_port->dp;
4411 struct drm_device *dev = intel_dig_port->base.base.dev;
4412 struct drm_i915_private *dev_priv = dev->dev_private;
4413 struct drm_display_mode *downclock_mode = NULL;
4414
4415 if (INTEL_INFO(dev)->gen <= 6) {
4416 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4417 return NULL;
4418 }
4419
4420 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4421 DRM_INFO("VBT doesn't support DRRS\n");
4422 return NULL;
4423 }
4424
4425 downclock_mode = intel_find_panel_downclock
4426 (dev, fixed_mode, connector);
4427
4428 if (!downclock_mode) {
4429 DRM_INFO("DRRS not supported\n");
4430 return NULL;
4431 }
4432
439d7ac0
PB		 4433 dev_priv->drrs.connector = intel_connector;
4434
4435 mutex_init(&intel_dp->drrs_state.mutex);
4436
4f9db5b5
PB		 4437 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4438
4439 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4440 DRM_INFO("seamless DRRS supported for eDP panel.\n");
4441 return downclock_mode;
4442}
4443
ed92f0b2 4444static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4445 struct intel_connector *intel_connector,
4446 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4447{
4448 struct drm_connector *connector = &intel_connector->base;
4449 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4450 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4451 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4452 struct drm_i915_private *dev_priv = dev->dev_private;
4453 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4454 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4455 bool has_dpcd;
4456 struct drm_display_mode *scan;
4457 struct edid *edid;
4458
4f9db5b5
PB		 4459 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4460
ed92f0b2
PZ		 4461 if (!is_edp(intel_dp))
4462 return true;
4463
63635217
PZ		 4464 /* The VDD bit needs a power domain reference, so if the bit is already
4465 * enabled when we boot, grab this reference. */
4466 if (edp_have_panel_vdd(intel_dp)) {
4467 enum intel_display_power_domain power_domain;
4468 power_domain = intel_display_port_power_domain(intel_encoder);
4469 intel_display_power_get(dev_priv, power_domain);
4470 }
4471
ed92f0b2 4472 /* Cache DPCD and EDID for edp. */
24f3e092 4473 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4474 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 4475 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4476
4477 if (has_dpcd) {
4478 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4479 dev_priv->no_aux_handshake =
4480 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4481 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4482 } else {
4483 /* if this fails, presume the device is a ghost */
4484 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4485 return false;
4486 }
4487
4488 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 4489 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 4490
060c8778 4491 mutex_lock(&dev->mode_config.mutex);
0b99836f 4492 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4493 if (edid) {
4494 if (drm_add_edid_modes(connector, edid)) {
4495 drm_mode_connector_update_edid_property(connector,
4496 edid);
4497 drm_edid_to_eld(connector, edid);
4498 } else {
4499 kfree(edid);
4500 edid = ERR_PTR(-EINVAL);
4501 }
4502 } else {
4503 edid = ERR_PTR(-ENOENT);
4504 }
4505 intel_connector->edid = edid;
4506
4507 /* prefer fixed mode from EDID if available */
4508 list_for_each_entry(scan, &connector->probed_modes, head) {
4509 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4510 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4511 downclock_mode = intel_dp_drrs_init(
4512 intel_dig_port,
4513 intel_connector, fixed_mode);
ed92f0b2
PZ		 4514 break;
4515 }
4516 }
4517
4518 /* fallback to VBT if available for eDP */
4519 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4520 fixed_mode = drm_mode_duplicate(dev,
4521 dev_priv->vbt.lfp_lvds_vbt_mode);
4522 if (fixed_mode)
4523 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4524 }
060c8778 4525 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4526
01527b31
CT		 4527 if (IS_VALLEYVIEW(dev)) {
4528 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4529 register_reboot_notifier(&intel_dp->edp_notifier);
4530 }
4531
4f9db5b5 4532 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
ed92f0b2
PZ		 4533 intel_panel_setup_backlight(connector);
4534
4535 return true;
4536}
4537
16c25533 4538bool
f0fec3f2
PZ		 4539intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4540 struct intel_connector *intel_connector)
a4fc5ed6 4541{
f0fec3f2
PZ		 4542 struct drm_connector *connector = &intel_connector->base;
4543 struct intel_dp *intel_dp = &intel_dig_port->dp;
4544 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4545 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4546 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4547 enum port port = intel_dig_port->port;
0095e6dc 4548 struct edp_power_seq power_seq = { 0 };
0b99836f 4549 int type;
a4fc5ed6 4550
ec5b01dd
DL		 4551 /* intel_dp vfuncs */
4552 if (IS_VALLEYVIEW(dev))
4553 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4554 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4555 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4556 else if (HAS_PCH_SPLIT(dev))
4557 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4558 else
4559 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4560
153b1100
DL		 4561 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4562
0767935e
DV		 4563 /* Preserve the current hw state. */
4564 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4565 intel_dp->attached_connector = intel_connector;
3d3dc149 4566
3b32a35b 4567 if (intel_dp_is_edp(dev, port))
b329530c 4568 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4569 else
4570 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4571
f7d24902
ID		 4572 /*
4573 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4574 * for DP the encoder type can be set by the caller to
4575 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4576 */
4577 if (type == DRM_MODE_CONNECTOR_eDP)
4578 intel_encoder->type = INTEL_OUTPUT_EDP;
4579
e7281eab
ID		 4580 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4581 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4582 port_name(port));
4583
b329530c 4584 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4585 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4586
a4fc5ed6
KP		 4587 connector->interlace_allowed = true;
4588 connector->doublescan_allowed = 0;
4589
f0fec3f2 4590 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4591 edp_panel_vdd_work);
a4fc5ed6 4592
df0e9248 4593 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 4594 drm_connector_register(connector);
a4fc5ed6 4595
affa9354 4596 if (HAS_DDI(dev))
bcbc889b
PZ		 4597 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4598 else
4599 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 4600 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 4601
0b99836f 4602 /* Set up the hotplug pin. */
ab9d7c30
PZ		 4603 switch (port) {
4604 case PORT_A:
1d843f9d 4605 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 4606 break;
4607 case PORT_B:
1d843f9d 4608 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 4609 break;
4610 case PORT_C:
1d843f9d 4611 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 4612 break;
4613 case PORT_D:
1d843f9d 4614 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 4615 break;
4616 default:
ad1c0b19 4617 BUG();
5eb08b69
ZW		 4618 }
4619
dada1a9f
ID		 4620 if (is_edp(intel_dp)) {
4621 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 4622 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 4623 }
0095e6dc 4624
9d1a1031 4625 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 4626
0e32b39c
DA		 4627 /* init MST on ports that can support it */
4628 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4629 if (port == PORT_B || port == PORT_C || port == PORT_D) {
4630 intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
4631 }
4632 }
4633
0095e6dc 4634 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 4635 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 4636 if (is_edp(intel_dp)) {
4637 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4638 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4639 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4640 drm_modeset_unlock(&dev->mode_config.connection_mutex);
15b1d171 4641 }
34ea3d38 4642 drm_connector_unregister(connector);
b2f246a8 4643 drm_connector_cleanup(connector);
16c25533 4644 return false;
b2f246a8 4645 }
32f9d658 4646
f684960e
CW		 4647 intel_dp_add_properties(intel_dp, connector);
4648
a4fc5ed6
KP		 4649 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4650 * 0xd. Failure to do so will result in spurious interrupts being
4651 * generated on the port when a cable is not attached.
4652 */
4653 if (IS_G4X(dev) && !IS_GM45(dev)) {
4654 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4655 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4656 }
16c25533
PZ		 4657
4658 return true;
a4fc5ed6 4659}
f0fec3f2
PZ		 4660
4661void
4662intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4663{
13cf5504 4664 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 4665 struct intel_digital_port *intel_dig_port;
4666 struct intel_encoder *intel_encoder;
4667 struct drm_encoder *encoder;
4668 struct intel_connector *intel_connector;
4669
b14c5679 4670 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 4671 if (!intel_dig_port)
4672 return;
4673
b14c5679 4674 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 4675 if (!intel_connector) {
4676 kfree(intel_dig_port);
4677 return;
4678 }
4679
4680 intel_encoder = &intel_dig_port->base;
4681 encoder = &intel_encoder->base;
4682
4683 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4684 DRM_MODE_ENCODER_TMDS);
4685
5bfe2ac0 4686 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 4687 intel_encoder->disable = intel_disable_dp;
00c09d70 4688 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4689 intel_encoder->get_config = intel_dp_get_config;
e4a1d846 4690 if (IS_CHERRYVIEW(dev)) {
9197c88b 4691 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 4692 intel_encoder->pre_enable = chv_pre_enable_dp;
4693 intel_encoder->enable = vlv_enable_dp;
580d3811 4694 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 4695 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4696 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4697 intel_encoder->pre_enable = vlv_pre_enable_dp;
4698 intel_encoder->enable = vlv_enable_dp;
49277c31 4699 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4700 } else {
ecff4f3b
JN		 4701 intel_encoder->pre_enable = g4x_pre_enable_dp;
4702 intel_encoder->enable = g4x_enable_dp;
49277c31 4703 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4704 }
f0fec3f2 4705
174edf1f 4706 intel_dig_port->port = port;
f0fec3f2
PZ		 4707 intel_dig_port->dp.output_reg = output_reg;
4708
00c09d70 4709 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 4710 if (IS_CHERRYVIEW(dev)) {
4711 if (port == PORT_D)
4712 intel_encoder->crtc_mask = 1 << 2;
4713 else
4714 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4715 } else {
4716 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4717 }
bc079e8b 4718 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4719 intel_encoder->hot_plug = intel_dp_hot_plug;
4720
13cf5504
DA		 4721 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4722 dev_priv->hpd_irq_port[port] = intel_dig_port;
4723
15b1d171
PZ		 4724 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4725 drm_encoder_cleanup(encoder);
4726 kfree(intel_dig_port);
b2f246a8 4727 kfree(intel_connector);
15b1d171 4728 }
f0fec3f2 4729}
0e32b39c
DA		 4730
4731void intel_dp_mst_suspend(struct drm_device *dev)
4732{
4733 struct drm_i915_private *dev_priv = dev->dev_private;
4734 int i;
4735
4736 /* disable MST */
4737 for (i = 0; i < I915_MAX_PORTS; i++) {
4738 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4739 if (!intel_dig_port)
4740 continue;
4741
4742 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4743 if (!intel_dig_port->dp.can_mst)
4744 continue;
4745 if (intel_dig_port->dp.is_mst)
4746 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
4747 }
4748 }
4749}
4750
4751void intel_dp_mst_resume(struct drm_device *dev)
4752{
4753 struct drm_i915_private *dev_priv = dev->dev_private;
4754 int i;
4755
4756 for (i = 0; i < I915_MAX_PORTS; i++) {
4757 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4758 if (!intel_dig_port)
4759 continue;
4760 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4761 int ret;
4762
4763 if (!intel_dig_port->dp.can_mst)
4764 continue;
4765
4766 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
4767 if (ret != 0) {
4768 intel_dp_check_mst_status(&intel_dig_port->dp);
4769 }
4770 }
4771 }
4772}
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