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drm/i915: remove is_pch_edp() helpers and state variable
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
68b4d824
ID		 55static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
56{
57 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
58
59 return intel_dig_port->base.base.dev;
60}
61
1c95822a
AJ		 62/**
63 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
64 * @intel_dp: DP struct
65 *
66 * Returns true if the given DP struct corresponds to a CPU eDP port.
67 */
68static bool is_cpu_edp(struct intel_dp *intel_dp)
69{
68b4d824 70 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 71 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
68b4d824 72 enum port port = intel_dig_port->port;
da63a9f2 73
68b4d824
ID		 74 return is_edp(intel_dp) &&
75 (port == PORT_A || (port == PORT_C && IS_VALLEYVIEW(dev)));
ea5b213a 76}
a4fc5ed6 77
df0e9248
CW		 78static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
79{
fa90ecef 80 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 81}
82
ea5b213a 83static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 84
a4fc5ed6 85static int
ea5b213a 86intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 87{
7183dc29 88 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 89
90 switch (max_link_bw) {
91 case DP_LINK_BW_1_62:
92 case DP_LINK_BW_2_7:
93 break;
94 default:
95 max_link_bw = DP_LINK_BW_1_62;
96 break;
97 }
98 return max_link_bw;
99}
100
cd9dde44
AJ		 101/*
102 * The units on the numbers in the next two are... bizarre. Examples will
103 * make it clearer; this one parallels an example in the eDP spec.
104 *
105 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
106 *
107 * 270000 * 1 * 8 / 10 == 216000
108 *
109 * The actual data capacity of that configuration is 2.16Gbit/s, so the
110 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
111 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
112 * 119000. At 18bpp that's 2142000 kilobits per second.
113 *
114 * Thus the strange-looking division by 10 in intel_dp_link_required, to
115 * get the result in decakilobits instead of kilobits.
116 */
117
a4fc5ed6 118static int
c898261c 119intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 120{
cd9dde44 121 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 122}
123
fe27d53e
DA		 124static int
125intel_dp_max_data_rate(int max_link_clock, int max_lanes)
126{
127 return (max_link_clock * max_lanes * 8) / 10;
128}
129
a4fc5ed6
KP		 130static int
131intel_dp_mode_valid(struct drm_connector *connector,
132 struct drm_display_mode *mode)
133{
df0e9248 134 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 135 struct intel_connector *intel_connector = to_intel_connector(connector);
136 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 137 int target_clock = mode->clock;
138 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 139
dd06f90e
JN		 140 if (is_edp(intel_dp) && fixed_mode) {
141 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 142 return MODE_PANEL;
143
dd06f90e 144 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 145 return MODE_PANEL;
03afc4a2
DV		 146
147 target_clock = fixed_mode->clock;
7de56f43
ZY		 148 }
149
36008365
DV		 150 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
151 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
152
153 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
154 mode_rate = intel_dp_link_required(target_clock, 18);
155
156 if (mode_rate > max_rate)
c4867936 157 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 158
159 if (mode->clock < 10000)
160 return MODE_CLOCK_LOW;
161
0af78a2b
DV		 162 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
163 return MODE_H_ILLEGAL;
164
a4fc5ed6
KP		 165 return MODE_OK;
166}
167
168static uint32_t
169pack_aux(uint8_t *src, int src_bytes)
170{
171 int i;
172 uint32_t v = 0;
173
174 if (src_bytes > 4)
175 src_bytes = 4;
176 for (i = 0; i < src_bytes; i++)
177 v |= ((uint32_t) src[i]) << ((3-i) * 8);
178 return v;
179}
180
181static void
182unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
183{
184 int i;
185 if (dst_bytes > 4)
186 dst_bytes = 4;
187 for (i = 0; i < dst_bytes; i++)
188 dst[i] = src >> ((3-i) * 8);
189}
190
fb0f8fbf
KP		 191/* hrawclock is 1/4 the FSB frequency */
192static int
193intel_hrawclk(struct drm_device *dev)
194{
195 struct drm_i915_private *dev_priv = dev->dev_private;
196 uint32_t clkcfg;
197
9473c8f4
VP		 198 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
199 if (IS_VALLEYVIEW(dev))
200 return 200;
201
fb0f8fbf
KP		 202 clkcfg = I915_READ(CLKCFG);
203 switch (clkcfg & CLKCFG_FSB_MASK) {
204 case CLKCFG_FSB_400:
205 return 100;
206 case CLKCFG_FSB_533:
207 return 133;
208 case CLKCFG_FSB_667:
209 return 166;
210 case CLKCFG_FSB_800:
211 return 200;
212 case CLKCFG_FSB_1067:
213 return 266;
214 case CLKCFG_FSB_1333:
215 return 333;
216 /* these two are just a guess; one of them might be right */
217 case CLKCFG_FSB_1600:
218 case CLKCFG_FSB_1600_ALT:
219 return 400;
220 default:
221 return 133;
222 }
223}
224
ebf33b18
KP		 225static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
226{
30add22d 227 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 228 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 229 u32 pp_stat_reg;
ebf33b18 230
453c5420
JB		 231 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
232 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
ebf33b18
KP		 233}
234
235static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
236{
30add22d 237 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 238 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 239 u32 pp_ctrl_reg;
ebf33b18 240
453c5420
JB		 241 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
242 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 243}
244
9b984dae
KP		 245static void
246intel_dp_check_edp(struct intel_dp *intel_dp)
247{
30add22d 248 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 249 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 250 u32 pp_stat_reg, pp_ctrl_reg;
ebf33b18 251
9b984dae
KP		 252 if (!is_edp(intel_dp))
253 return;
453c5420
JB		 254
255 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
256 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
257
ebf33b18 258 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 259 WARN(1, "eDP powered off while attempting aux channel communication.\n");
260 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
453c5420
JB		 261 I915_READ(pp_stat_reg),
262 I915_READ(pp_ctrl_reg));
9b984dae
KP		 263 }
264}
265
9ee32fea
DV		 266static uint32_t
267intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
268{
269 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
270 struct drm_device *dev = intel_dig_port->base.base.dev;
271 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 272 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 273 uint32_t status;
274 bool done;
275
ef04f00d 276#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 277 if (has_aux_irq)
b90f5176
PZ		 278 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
279 msecs_to_jiffies(10));
9ee32fea
DV		 280 else
281 done = wait_for_atomic(C, 10) == 0;
282 if (!done)
283 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
284 has_aux_irq);
285#undef C
286
287 return status;
288}
289
a4fc5ed6 290static int
ea5b213a 291intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 292 uint8_t *send, int send_bytes,
293 uint8_t *recv, int recv_size)
294{
174edf1f
PZ		 295 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
296 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 297 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 298 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
a4fc5ed6 299 uint32_t ch_data = ch_ctl + 4;
9ee32fea 300 int i, ret, recv_bytes;
a4fc5ed6 301 uint32_t status;
fb0f8fbf 302 uint32_t aux_clock_divider;
6b4e0a93 303 int try, precharge;
9ee32fea
DV		 304 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
305
306 /* dp aux is extremely sensitive to irq latency, hence request the
307 * lowest possible wakeup latency and so prevent the cpu from going into
308 * deep sleep states.
309 */
310 pm_qos_update_request(&dev_priv->pm_qos, 0);
a4fc5ed6 311
9b984dae 312 intel_dp_check_edp(intel_dp);
a4fc5ed6 313 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 314 * and would like to run at 2MHz. So, take the
315 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 316 *
317 * Note that PCH attached eDP panels should use a 125MHz input
318 * clock divider.
a4fc5ed6 319 */
1c95822a 320 if (is_cpu_edp(intel_dp)) {
affa9354 321 if (HAS_DDI(dev))
b8fc2f6a
PZ		 322 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
323 else if (IS_VALLEYVIEW(dev))
9473c8f4
VP		 324 aux_clock_divider = 100;
325 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 326 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 327 else
328 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 329 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
330 /* Workaround for non-ULT HSW */
331 aux_clock_divider = 74;
332 } else if (HAS_PCH_SPLIT(dev)) {
6b3ec1c9 333 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 334 } else {
5eb08b69 335 aux_clock_divider = intel_hrawclk(dev) / 2;
2c55c336 336 }
5eb08b69 337
6b4e0a93
DV		 338 if (IS_GEN6(dev))
339 precharge = 3;
340 else
341 precharge = 5;
342
11bee43e
JB		 343 /* Try to wait for any previous AUX channel activity */
344 for (try = 0; try < 3; try++) {
ef04f00d 345 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 346 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
347 break;
348 msleep(1);
349 }
350
351 if (try == 3) {
352 WARN(1, "dp_aux_ch not started status 0x%08x\n",
353 I915_READ(ch_ctl));
9ee32fea
DV		 354 ret = -EBUSY;
355 goto out;
4f7f7b7e
CW		 356 }
357
fb0f8fbf
KP		 358 /* Must try at least 3 times according to DP spec */
359 for (try = 0; try < 5; try++) {
360 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 361 for (i = 0; i < send_bytes; i += 4)
362 I915_WRITE(ch_data + i,
363 pack_aux(send + i, send_bytes - i));
0206e353 364
fb0f8fbf 365 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 366 I915_WRITE(ch_ctl,
367 DP_AUX_CH_CTL_SEND_BUSY |
9ee32fea 368 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
4f7f7b7e
CW		 369 DP_AUX_CH_CTL_TIME_OUT_400us |
370 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
371 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
372 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
373 DP_AUX_CH_CTL_DONE |
374 DP_AUX_CH_CTL_TIME_OUT_ERROR |
375 DP_AUX_CH_CTL_RECEIVE_ERROR);
9ee32fea
DV		 376
377 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
0206e353 378
fb0f8fbf 379 /* Clear done status and any errors */
4f7f7b7e
CW		 380 I915_WRITE(ch_ctl,
381 status |
382 DP_AUX_CH_CTL_DONE |
383 DP_AUX_CH_CTL_TIME_OUT_ERROR |
384 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 385
386 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
387 DP_AUX_CH_CTL_RECEIVE_ERROR))
388 continue;
4f7f7b7e 389 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 390 break;
391 }
392
a4fc5ed6 393 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 394 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 395 ret = -EBUSY;
396 goto out;
a4fc5ed6
KP		 397 }
398
399 /* Check for timeout or receive error.
400 * Timeouts occur when the sink is not connected
401 */
a5b3da54 402 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 403 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 404 ret = -EIO;
405 goto out;
a5b3da54 406 }
1ae8c0a5
KP		 407
408 /* Timeouts occur when the device isn't connected, so they're
409 * "normal" -- don't fill the kernel log with these */
a5b3da54 410 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 411 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 412 ret = -ETIMEDOUT;
413 goto out;
a4fc5ed6
KP		 414 }
415
416 /* Unload any bytes sent back from the other side */
417 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
418 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 419 if (recv_bytes > recv_size)
420 recv_bytes = recv_size;
0206e353 421
4f7f7b7e
CW		 422 for (i = 0; i < recv_bytes; i += 4)
423 unpack_aux(I915_READ(ch_data + i),
424 recv + i, recv_bytes - i);
a4fc5ed6 425
9ee32fea
DV		 426 ret = recv_bytes;
427out:
428 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
429
430 return ret;
a4fc5ed6
KP		 431}
432
433/* Write data to the aux channel in native mode */
434static int
ea5b213a 435intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 436 uint16_t address, uint8_t *send, int send_bytes)
437{
438 int ret;
439 uint8_t msg[20];
440 int msg_bytes;
441 uint8_t ack;
442
9b984dae 443 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 444 if (send_bytes > 16)
445 return -1;
446 msg[0] = AUX_NATIVE_WRITE << 4;
447 msg[1] = address >> 8;
eebc863e 448 msg[2] = address & 0xff;
a4fc5ed6
KP		 449 msg[3] = send_bytes - 1;
450 memcpy(&msg[4], send, send_bytes);
451 msg_bytes = send_bytes + 4;
452 for (;;) {
ea5b213a 453 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 454 if (ret < 0)
455 return ret;
456 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
457 break;
458 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
459 udelay(100);
460 else
a5b3da54 461 return -EIO;
a4fc5ed6
KP		 462 }
463 return send_bytes;
464}
465
466/* Write a single byte to the aux channel in native mode */
467static int
ea5b213a 468intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 469 uint16_t address, uint8_t byte)
470{
ea5b213a 471 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 472}
473
474/* read bytes from a native aux channel */
475static int
ea5b213a 476intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 477 uint16_t address, uint8_t *recv, int recv_bytes)
478{
479 uint8_t msg[4];
480 int msg_bytes;
481 uint8_t reply[20];
482 int reply_bytes;
483 uint8_t ack;
484 int ret;
485
9b984dae 486 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 487 msg[0] = AUX_NATIVE_READ << 4;
488 msg[1] = address >> 8;
489 msg[2] = address & 0xff;
490 msg[3] = recv_bytes - 1;
491
492 msg_bytes = 4;
493 reply_bytes = recv_bytes + 1;
494
495 for (;;) {
ea5b213a 496 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 497 reply, reply_bytes);
a5b3da54
KP		 498 if (ret == 0)
499 return -EPROTO;
500 if (ret < 0)
a4fc5ed6
KP		 501 return ret;
502 ack = reply[0];
503 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
504 memcpy(recv, reply + 1, ret - 1);
505 return ret - 1;
506 }
507 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
508 udelay(100);
509 else
a5b3da54 510 return -EIO;
a4fc5ed6
KP		 511 }
512}
513
514static int
ab2c0672
DA		 515intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
516 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 517{
ab2c0672 518 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 519 struct intel_dp *intel_dp = container_of(adapter,
520 struct intel_dp,
521 adapter);
ab2c0672
DA		 522 uint16_t address = algo_data->address;
523 uint8_t msg[5];
524 uint8_t reply[2];
8316f337 525 unsigned retry;
ab2c0672
DA		 526 int msg_bytes;
527 int reply_bytes;
528 int ret;
529
9b984dae 530 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 531 /* Set up the command byte */
532 if (mode & MODE_I2C_READ)
533 msg[0] = AUX_I2C_READ << 4;
534 else
535 msg[0] = AUX_I2C_WRITE << 4;
536
537 if (!(mode & MODE_I2C_STOP))
538 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 539
ab2c0672
DA		 540 msg[1] = address >> 8;
541 msg[2] = address;
542
543 switch (mode) {
544 case MODE_I2C_WRITE:
545 msg[3] = 0;
546 msg[4] = write_byte;
547 msg_bytes = 5;
548 reply_bytes = 1;
549 break;
550 case MODE_I2C_READ:
551 msg[3] = 0;
552 msg_bytes = 4;
553 reply_bytes = 2;
554 break;
555 default:
556 msg_bytes = 3;
557 reply_bytes = 1;
558 break;
559 }
560
8316f337
DF		 561 for (retry = 0; retry < 5; retry++) {
562 ret = intel_dp_aux_ch(intel_dp,
563 msg, msg_bytes,
564 reply, reply_bytes);
ab2c0672 565 if (ret < 0) {
3ff99164 566 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 567 return ret;
568 }
8316f337
DF		 569
570 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
571 case AUX_NATIVE_REPLY_ACK:
572 /* I2C-over-AUX Reply field is only valid
573 * when paired with AUX ACK.
574 */
575 break;
576 case AUX_NATIVE_REPLY_NACK:
577 DRM_DEBUG_KMS("aux_ch native nack\n");
578 return -EREMOTEIO;
579 case AUX_NATIVE_REPLY_DEFER:
580 udelay(100);
581 continue;
582 default:
583 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
584 reply[0]);
585 return -EREMOTEIO;
586 }
587
ab2c0672
DA		 588 switch (reply[0] & AUX_I2C_REPLY_MASK) {
589 case AUX_I2C_REPLY_ACK:
590 if (mode == MODE_I2C_READ) {
591 *read_byte = reply[1];
592 }
593 return reply_bytes - 1;
594 case AUX_I2C_REPLY_NACK:
8316f337 595 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 596 return -EREMOTEIO;
597 case AUX_I2C_REPLY_DEFER:
8316f337 598 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 599 udelay(100);
600 break;
601 default:
8316f337 602 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 603 return -EREMOTEIO;
604 }
605 }
8316f337
DF		 606
607 DRM_ERROR("too many retries, giving up\n");
608 return -EREMOTEIO;
a4fc5ed6
KP		 609}
610
611static int
ea5b213a 612intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 613 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 614{
0b5c541b
KP		 615 int ret;
616
d54e9d28 617 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 618 intel_dp->algo.running = false;
619 intel_dp->algo.address = 0;
620 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
621
0206e353 622 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 623 intel_dp->adapter.owner = THIS_MODULE;
624 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 625 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 626 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
627 intel_dp->adapter.algo_data = &intel_dp->algo;
628 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
629
0b5c541b
KP		 630 ironlake_edp_panel_vdd_on(intel_dp);
631 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 632 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 633 return ret;
a4fc5ed6
KP		 634}
635
c6bb3538
DV		 636static void
637intel_dp_set_clock(struct intel_encoder *encoder,
638 struct intel_crtc_config *pipe_config, int link_bw)
639{
640 struct drm_device *dev = encoder->base.dev;
641
642 if (IS_G4X(dev)) {
643 if (link_bw == DP_LINK_BW_1_62) {
644 pipe_config->dpll.p1 = 2;
645 pipe_config->dpll.p2 = 10;
646 pipe_config->dpll.n = 2;
647 pipe_config->dpll.m1 = 23;
648 pipe_config->dpll.m2 = 8;
649 } else {
650 pipe_config->dpll.p1 = 1;
651 pipe_config->dpll.p2 = 10;
652 pipe_config->dpll.n = 1;
653 pipe_config->dpll.m1 = 14;
654 pipe_config->dpll.m2 = 2;
655 }
656 pipe_config->clock_set = true;
657 } else if (IS_HASWELL(dev)) {
658 /* Haswell has special-purpose DP DDI clocks. */
659 } else if (HAS_PCH_SPLIT(dev)) {
660 if (link_bw == DP_LINK_BW_1_62) {
661 pipe_config->dpll.n = 1;
662 pipe_config->dpll.p1 = 2;
663 pipe_config->dpll.p2 = 10;
664 pipe_config->dpll.m1 = 12;
665 pipe_config->dpll.m2 = 9;
666 } else {
667 pipe_config->dpll.n = 2;
668 pipe_config->dpll.p1 = 1;
669 pipe_config->dpll.p2 = 10;
670 pipe_config->dpll.m1 = 14;
671 pipe_config->dpll.m2 = 8;
672 }
673 pipe_config->clock_set = true;
674 } else if (IS_VALLEYVIEW(dev)) {
675 /* FIXME: Need to figure out optimized DP clocks for vlv. */
676 }
677}
678
00c09d70 679bool
5bfe2ac0
DV		 680intel_dp_compute_config(struct intel_encoder *encoder,
681 struct intel_crtc_config *pipe_config)
a4fc5ed6 682{
5bfe2ac0 683 struct drm_device *dev = encoder->base.dev;
36008365 684 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 685 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 686 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2dd24552 687 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 688 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 689 int lane_count, clock;
397fe157 690 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 691 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 692 int bpp, mode_rate;
a4fc5ed6 693 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
36008365 694 int target_clock, link_avail, link_clock;
a4fc5ed6 695
5bfe2ac0
DV		 696 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
697 pipe_config->has_pch_encoder = true;
698
03afc4a2
DV		 699 pipe_config->has_dp_encoder = true;
700
dd06f90e
JN		 701 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
702 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
703 adjusted_mode);
2dd24552
JB		 704 if (!HAS_PCH_SPLIT(dev))
705 intel_gmch_panel_fitting(intel_crtc, pipe_config,
706 intel_connector->panel.fitting_mode);
707 else
b074cec8
JB		 708 intel_pch_panel_fitting(intel_crtc, pipe_config,
709 intel_connector->panel.fitting_mode);
0d3a1bee 710 }
36008365
DV		 711 /* We need to take the panel's fixed mode into account. */
712 target_clock = adjusted_mode->clock;
0d3a1bee 713
cb1793ce 714 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 715 return false;
716
083f9560
DV		 717 DRM_DEBUG_KMS("DP link computation with max lane count %i "
718 "max bw %02x pixel clock %iKHz\n",
71244653 719 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 720
36008365
DV		 721 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
722 * bpc in between. */
52541e30 723 bpp = pipe_config->pipe_bpp;
af13188a
DV		 724
725 /*
726 * eDP panels are really fickle, try to enfore the bpp the firmware
727 * recomments. This means we'll up-dither 16bpp framebuffers on
728 * high-depth panels.
729 */
730 if (is_edp(intel_dp) && dev_priv->edp.bpp) {
731 DRM_DEBUG_KMS("forcing bpp for eDP panel to BIOS-provided %i\n",
732 dev_priv->edp.bpp);
733 bpp = dev_priv->edp.bpp;
734 }
735
36008365
DV		 736 for (; bpp >= 6*3; bpp -= 2*3) {
737 mode_rate = intel_dp_link_required(target_clock, bpp);
738
739 for (clock = 0; clock <= max_clock; clock++) {
740 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
741 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
742 link_avail = intel_dp_max_data_rate(link_clock,
743 lane_count);
744
745 if (mode_rate <= link_avail) {
746 goto found;
747 }
748 }
749 }
750 }
c4867936 751
36008365 752 return false;
3685a8f3 753
36008365 754found:
55bc60db
VS		 755 if (intel_dp->color_range_auto) {
756 /*
757 * See:
758 * CEA-861-E - 5.1 Default Encoding Parameters
759 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
760 */
18316c8c 761 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 762 intel_dp->color_range = DP_COLOR_RANGE_16_235;
763 else
764 intel_dp->color_range = 0;
765 }
766
3685a8f3 767 if (intel_dp->color_range)
50f3b016 768 pipe_config->limited_color_range = true;
3685a8f3 769
36008365
DV		 770 intel_dp->link_bw = bws[clock];
771 intel_dp->lane_count = lane_count;
772 adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
df92b1e6 773 pipe_config->pixel_target_clock = target_clock;
fe27d53e 774
36008365
DV		 775 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
776 intel_dp->link_bw, intel_dp->lane_count,
777 adjusted_mode->clock, bpp);
778 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
779 mode_rate, link_avail);
780
03afc4a2
DV		 781 intel_link_compute_m_n(bpp, lane_count,
782 target_clock, adjusted_mode->clock,
783 &pipe_config->dp_m_n);
a4fc5ed6 784
57c21963
DV		 785 pipe_config->pipe_bpp = bpp;
786
c6bb3538
DV		 787 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
788
03afc4a2 789 return true;
a4fc5ed6
KP		 790}
791
247d89f6
PZ		 792void intel_dp_init_link_config(struct intel_dp *intel_dp)
793{
794 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
795 intel_dp->link_configuration[0] = intel_dp->link_bw;
796 intel_dp->link_configuration[1] = intel_dp->lane_count;
797 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
798 /*
799 * Check for DPCD version > 1.1 and enhanced framing support
800 */
801 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
802 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
803 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
804 }
805}
806
ea9b6006
DV		 807static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
808{
809 struct drm_device *dev = crtc->dev;
810 struct drm_i915_private *dev_priv = dev->dev_private;
811 u32 dpa_ctl;
812
813 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
814 dpa_ctl = I915_READ(DP_A);
815 dpa_ctl &= ~DP_PLL_FREQ_MASK;
816
817 if (clock < 200000) {
1ce17038
DV		 818 /* For a long time we've carried around a ILK-DevA w/a for the
819 * 160MHz clock. If we're really unlucky, it's still required.
820 */
821 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 822 dpa_ctl |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 823 } else {
824 dpa_ctl |= DP_PLL_FREQ_270MHZ;
825 }
1ce17038 826
ea9b6006
DV		 827 I915_WRITE(DP_A, dpa_ctl);
828
829 POSTING_READ(DP_A);
830 udelay(500);
831}
832
a4fc5ed6
KP		 833static void
834intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
835 struct drm_display_mode *adjusted_mode)
836{
e3421a18 837 struct drm_device *dev = encoder->dev;
417e822d 838 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 839 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
fa90ecef 840 struct drm_crtc *crtc = encoder->crtc;
a4fc5ed6
KP		 841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
842
417e822d 843 /*
1a2eb460 844 * There are four kinds of DP registers:
417e822d
KP		 845 *
846 * IBX PCH
1a2eb460
KP		 847 * SNB CPU
848 * IVB CPU
417e822d
KP		 849 * CPT PCH
850 *
851 * IBX PCH and CPU are the same for almost everything,
852 * except that the CPU DP PLL is configured in this
853 * register
854 *
855 * CPT PCH is quite different, having many bits moved
856 * to the TRANS_DP_CTL register instead. That
857 * configuration happens (oddly) in ironlake_pch_enable
858 */
9c9e7927 859
417e822d
KP		 860 /* Preserve the BIOS-computed detected bit. This is
861 * supposed to be read-only.
862 */
863 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 864
417e822d 865 /* Handle DP bits in common between all three register formats */
417e822d 866 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 867 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 868
e0dac65e
WF		 869 if (intel_dp->has_audio) {
870 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
871 pipe_name(intel_crtc->pipe));
ea5b213a 872 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 873 intel_write_eld(encoder, adjusted_mode);
874 }
247d89f6
PZ		 875
876 intel_dp_init_link_config(intel_dp);
a4fc5ed6 877
417e822d 878 /* Split out the IBX/CPU vs CPT settings */
32f9d658 879
19c03924 880 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 881 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
882 intel_dp->DP |= DP_SYNC_HS_HIGH;
883 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
884 intel_dp->DP |= DP_SYNC_VS_HIGH;
885 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
886
887 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
888 intel_dp->DP |= DP_ENHANCED_FRAMING;
889
890 intel_dp->DP |= intel_crtc->pipe << 29;
891
892 /* don't miss out required setting for eDP */
1a2eb460
KP		 893 if (adjusted_mode->clock < 200000)
894 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
895 else
896 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
897 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
b2634017 898 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 899 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 900
901 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
902 intel_dp->DP |= DP_SYNC_HS_HIGH;
903 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
904 intel_dp->DP |= DP_SYNC_VS_HIGH;
905 intel_dp->DP |= DP_LINK_TRAIN_OFF;
906
907 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
908 intel_dp->DP |= DP_ENHANCED_FRAMING;
909
910 if (intel_crtc->pipe == 1)
911 intel_dp->DP |= DP_PIPEB_SELECT;
912
b2634017 913 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
417e822d 914 /* don't miss out required setting for eDP */
417e822d
KP		 915 if (adjusted_mode->clock < 200000)
916 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
917 else
918 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
919 }
920 } else {
921 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 922 }
ea9b6006 923
5d66d5b6 924 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
ea9b6006 925 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
a4fc5ed6
KP		 926}
927
99ea7127
KP		 928#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
929#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
930
931#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
932#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
933
934#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
935#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
936
937static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
938 u32 mask,
939 u32 value)
bd943159 940{
30add22d 941 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 942 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 943 u32 pp_stat_reg, pp_ctrl_reg;
944
945 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
946 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
32ce697c 947
99ea7127 948 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 949 mask, value,
950 I915_READ(pp_stat_reg),
951 I915_READ(pp_ctrl_reg));
32ce697c 952
453c5420 953 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 954 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 955 I915_READ(pp_stat_reg),
956 I915_READ(pp_ctrl_reg));
32ce697c 957 }
99ea7127 958}
32ce697c 959
99ea7127
KP		 960static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
961{
962 DRM_DEBUG_KMS("Wait for panel power on\n");
963 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 964}
965
99ea7127
KP		 966static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
967{
968 DRM_DEBUG_KMS("Wait for panel power off time\n");
969 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
970}
971
972static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
973{
974 DRM_DEBUG_KMS("Wait for panel power cycle\n");
975 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
976}
977
978
832dd3c1
KP		 979/* Read the current pp_control value, unlocking the register if it
980 * is locked
981 */
982
453c5420 983static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 984{
453c5420
JB		 985 struct drm_device *dev = intel_dp_to_dev(intel_dp);
986 struct drm_i915_private *dev_priv = dev->dev_private;
987 u32 control;
988 u32 pp_ctrl_reg;
989
990 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
991 control = I915_READ(pp_ctrl_reg);
832dd3c1
KP		 992
993 control &= ~PANEL_UNLOCK_MASK;
994 control |= PANEL_UNLOCK_REGS;
995 return control;
bd943159
KP		 996}
997
82a4d9c0 998void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 999{
30add22d 1000 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1001 struct drm_i915_private *dev_priv = dev->dev_private;
1002 u32 pp;
453c5420 1003 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1004
97af61f5
KP		 1005 if (!is_edp(intel_dp))
1006 return;
f01eca2e 1007 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1008
bd943159
KP		 1009 WARN(intel_dp->want_panel_vdd,
1010 "eDP VDD already requested on\n");
1011
1012 intel_dp->want_panel_vdd = true;
99ea7127 1013
bd943159
KP		 1014 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1015 DRM_DEBUG_KMS("eDP VDD already on\n");
1016 return;
1017 }
1018
99ea7127
KP		 1019 if (!ironlake_edp_have_panel_power(intel_dp))
1020 ironlake_wait_panel_power_cycle(intel_dp);
1021
453c5420 1022 pp = ironlake_get_pp_control(intel_dp);
5d613501 1023 pp |= EDP_FORCE_VDD;
ebf33b18 1024
453c5420
JB		 1025 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1026 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1027
1028 I915_WRITE(pp_ctrl_reg, pp);
1029 POSTING_READ(pp_ctrl_reg);
1030 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1031 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1032 /*
1033 * If the panel wasn't on, delay before accessing aux channel
1034 */
1035 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1036 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1037 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1038 }
5d613501
JB		 1039}
1040
bd943159 1041static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1042{
30add22d 1043 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1044 struct drm_i915_private *dev_priv = dev->dev_private;
1045 u32 pp;
453c5420 1046 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1047
a0e99e68
DV		 1048 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1049
bd943159 1050 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
453c5420 1051 pp = ironlake_get_pp_control(intel_dp);
bd943159 1052 pp &= ~EDP_FORCE_VDD;
bd943159 1053
453c5420
JB		 1054 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1055 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1056
1057 I915_WRITE(pp_ctrl_reg, pp);
1058 POSTING_READ(pp_ctrl_reg);
99ea7127 1059
453c5420
JB		 1060 /* Make sure sequencer is idle before allowing subsequent activity */
1061 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1062 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1063 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1064 }
1065}
5d613501 1066
bd943159
KP		 1067static void ironlake_panel_vdd_work(struct work_struct *__work)
1068{
1069 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1070 struct intel_dp, panel_vdd_work);
30add22d 1071 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1072
627f7675 1073 mutex_lock(&dev->mode_config.mutex);
bd943159 1074 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1075 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1076}
1077
82a4d9c0 1078void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1079{
97af61f5
KP		 1080 if (!is_edp(intel_dp))
1081 return;
5d613501 1082
bd943159
KP		 1083 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1084 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1085
bd943159
KP		 1086 intel_dp->want_panel_vdd = false;
1087
1088 if (sync) {
1089 ironlake_panel_vdd_off_sync(intel_dp);
1090 } else {
1091 /*
1092 * Queue the timer to fire a long
1093 * time from now (relative to the power down delay)
1094 * to keep the panel power up across a sequence of operations
1095 */
1096 schedule_delayed_work(&intel_dp->panel_vdd_work,
1097 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1098 }
5d613501
JB		 1099}
1100
82a4d9c0 1101void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1102{
30add22d 1103 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1104 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1105 u32 pp;
453c5420 1106 u32 pp_ctrl_reg;
9934c132 1107
97af61f5 1108 if (!is_edp(intel_dp))
bd943159 1109 return;
99ea7127
KP		 1110
1111 DRM_DEBUG_KMS("Turn eDP power on\n");
1112
1113 if (ironlake_edp_have_panel_power(intel_dp)) {
1114 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1115 return;
99ea7127 1116 }
9934c132 1117
99ea7127 1118 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1119
453c5420 1120 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1121 if (IS_GEN5(dev)) {
1122 /* ILK workaround: disable reset around power sequence */
1123 pp &= ~PANEL_POWER_RESET;
1124 I915_WRITE(PCH_PP_CONTROL, pp);
1125 POSTING_READ(PCH_PP_CONTROL);
1126 }
37c6c9b0 1127
1c0ae80a 1128 pp |= POWER_TARGET_ON;
99ea7127
KP		 1129 if (!IS_GEN5(dev))
1130 pp |= PANEL_POWER_RESET;
1131
453c5420
JB		 1132 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1133
1134 I915_WRITE(pp_ctrl_reg, pp);
1135 POSTING_READ(pp_ctrl_reg);
9934c132 1136
99ea7127 1137 ironlake_wait_panel_on(intel_dp);
9934c132 1138
05ce1a49
KP		 1139 if (IS_GEN5(dev)) {
1140 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1141 I915_WRITE(PCH_PP_CONTROL, pp);
1142 POSTING_READ(PCH_PP_CONTROL);
1143 }
9934c132
JB		 1144}
1145
82a4d9c0 1146void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1147{
30add22d 1148 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1149 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1150 u32 pp;
453c5420 1151 u32 pp_ctrl_reg;
9934c132 1152
97af61f5
KP		 1153 if (!is_edp(intel_dp))
1154 return;
37c6c9b0 1155
99ea7127 1156 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1157
6cb49835 1158 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1159
453c5420 1160 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1161 /* We need to switch off panel power _and_ force vdd, for otherwise some
1162 * panels get very unhappy and cease to work. */
1163 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420
JB		 1164
1165 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1166
1167 I915_WRITE(pp_ctrl_reg, pp);
1168 POSTING_READ(pp_ctrl_reg);
9934c132 1169
35a38556
DV		 1170 intel_dp->want_panel_vdd = false;
1171
99ea7127 1172 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1173}
1174
d6c50ff8 1175void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1176{
da63a9f2
PZ		 1177 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1178 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1179 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1180 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658 1181 u32 pp;
453c5420 1182 u32 pp_ctrl_reg;
32f9d658 1183
f01eca2e
KP		 1184 if (!is_edp(intel_dp))
1185 return;
1186
28c97730 1187 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1188 /*
1189 * If we enable the backlight right away following a panel power
1190 * on, we may see slight flicker as the panel syncs with the eDP
1191 * link. So delay a bit to make sure the image is solid before
1192 * allowing it to appear.
1193 */
f01eca2e 1194 msleep(intel_dp->backlight_on_delay);
453c5420 1195 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1196 pp |= EDP_BLC_ENABLE;
453c5420
JB		 1197
1198 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1199
1200 I915_WRITE(pp_ctrl_reg, pp);
1201 POSTING_READ(pp_ctrl_reg);
035aa3de
DV		 1202
1203 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1204}
1205
d6c50ff8 1206void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1207{
30add22d 1208 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1209 struct drm_i915_private *dev_priv = dev->dev_private;
1210 u32 pp;
453c5420 1211 u32 pp_ctrl_reg;
32f9d658 1212
f01eca2e
KP		 1213 if (!is_edp(intel_dp))
1214 return;
1215
035aa3de
DV		 1216 intel_panel_disable_backlight(dev);
1217
28c97730 1218 DRM_DEBUG_KMS("\n");
453c5420 1219 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1220 pp &= ~EDP_BLC_ENABLE;
453c5420
JB		 1221
1222 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1223
1224 I915_WRITE(pp_ctrl_reg, pp);
1225 POSTING_READ(pp_ctrl_reg);
f01eca2e 1226 msleep(intel_dp->backlight_off_delay);
32f9d658 1227}
a4fc5ed6 1228
2bd2ad64 1229static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1230{
da63a9f2
PZ		 1231 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1232 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1233 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1234 struct drm_i915_private *dev_priv = dev->dev_private;
1235 u32 dpa_ctl;
1236
2bd2ad64
DV		 1237 assert_pipe_disabled(dev_priv,
1238 to_intel_crtc(crtc)->pipe);
1239
d240f20f
JB		 1240 DRM_DEBUG_KMS("\n");
1241 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1242 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1243 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1244
1245 /* We don't adjust intel_dp->DP while tearing down the link, to
1246 * facilitate link retraining (e.g. after hotplug). Hence clear all
1247 * enable bits here to ensure that we don't enable too much. */
1248 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1249 intel_dp->DP |= DP_PLL_ENABLE;
1250 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1251 POSTING_READ(DP_A);
1252 udelay(200);
d240f20f
JB		 1253}
1254
2bd2ad64 1255static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1256{
da63a9f2
PZ		 1257 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1258 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1259 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1260 struct drm_i915_private *dev_priv = dev->dev_private;
1261 u32 dpa_ctl;
1262
2bd2ad64
DV		 1263 assert_pipe_disabled(dev_priv,
1264 to_intel_crtc(crtc)->pipe);
1265
d240f20f 1266 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1267 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1268 "dp pll off, should be on\n");
1269 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1270
1271 /* We can't rely on the value tracked for the DP register in
1272 * intel_dp->DP because link_down must not change that (otherwise link
1273 * re-training will fail. */
298b0b39 1274 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1275 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1276 POSTING_READ(DP_A);
d240f20f
JB		 1277 udelay(200);
1278}
1279
c7ad3810 1280/* If the sink supports it, try to set the power state appropriately */
c19b0669 1281void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1282{
1283 int ret, i;
1284
1285 /* Should have a valid DPCD by this point */
1286 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1287 return;
1288
1289 if (mode != DRM_MODE_DPMS_ON) {
1290 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1291 DP_SET_POWER_D3);
1292 if (ret != 1)
1293 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1294 } else {
1295 /*
1296 * When turning on, we need to retry for 1ms to give the sink
1297 * time to wake up.
1298 */
1299 for (i = 0; i < 3; i++) {
1300 ret = intel_dp_aux_native_write_1(intel_dp,
1301 DP_SET_POWER,
1302 DP_SET_POWER_D0);
1303 if (ret == 1)
1304 break;
1305 msleep(1);
1306 }
1307 }
1308}
1309
19d8fe15
DV		 1310static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1311 enum pipe *pipe)
d240f20f 1312{
19d8fe15
DV		 1313 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1314 struct drm_device *dev = encoder->base.dev;
1315 struct drm_i915_private *dev_priv = dev->dev_private;
1316 u32 tmp = I915_READ(intel_dp->output_reg);
1317
1318 if (!(tmp & DP_PORT_EN))
1319 return false;
1320
5d66d5b6 1321 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15
DV		 1322 *pipe = PORT_TO_PIPE_CPT(tmp);
1323 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1324 *pipe = PORT_TO_PIPE(tmp);
1325 } else {
1326 u32 trans_sel;
1327 u32 trans_dp;
1328 int i;
1329
1330 switch (intel_dp->output_reg) {
1331 case PCH_DP_B:
1332 trans_sel = TRANS_DP_PORT_SEL_B;
1333 break;
1334 case PCH_DP_C:
1335 trans_sel = TRANS_DP_PORT_SEL_C;
1336 break;
1337 case PCH_DP_D:
1338 trans_sel = TRANS_DP_PORT_SEL_D;
1339 break;
1340 default:
1341 return true;
1342 }
1343
1344 for_each_pipe(i) {
1345 trans_dp = I915_READ(TRANS_DP_CTL(i));
1346 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1347 *pipe = i;
1348 return true;
1349 }
1350 }
19d8fe15 1351
4a0833ec
DV		 1352 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1353 intel_dp->output_reg);
1354 }
d240f20f 1355
2af8898b 1356 return true;
19d8fe15 1357}
d240f20f 1358
e8cb4558 1359static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1360{
e8cb4558 1361 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1362
1363 /* Make sure the panel is off before trying to change the mode. But also
1364 * ensure that we have vdd while we switch off the panel. */
1365 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1366 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1367 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1368 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1369
1370 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1371 if (!is_cpu_edp(intel_dp))
1372 intel_dp_link_down(intel_dp);
d240f20f
JB		 1373}
1374
2bd2ad64 1375static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1376{
2bd2ad64 1377 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
b2634017 1378 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1379
3739850b
DV		 1380 if (is_cpu_edp(intel_dp)) {
1381 intel_dp_link_down(intel_dp);
b2634017
JB		 1382 if (!IS_VALLEYVIEW(dev))
1383 ironlake_edp_pll_off(intel_dp);
3739850b 1384 }
2bd2ad64
DV		 1385}
1386
e8cb4558 1387static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1388{
e8cb4558
DV		 1389 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1390 struct drm_device *dev = encoder->base.dev;
1391 struct drm_i915_private *dev_priv = dev->dev_private;
1392 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1393
0c33d8d7
DV		 1394 if (WARN_ON(dp_reg & DP_PORT_EN))
1395 return;
5d613501 1396
97af61f5 1397 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1398 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1399 intel_dp_start_link_train(intel_dp);
97af61f5 1400 ironlake_edp_panel_on(intel_dp);
bd943159 1401 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1402 intel_dp_complete_link_train(intel_dp);
f01eca2e 1403 ironlake_edp_backlight_on(intel_dp);
89b667f8
JB		 1404
1405 if (IS_VALLEYVIEW(dev)) {
1406 struct intel_digital_port *dport =
1407 enc_to_dig_port(&encoder->base);
1408 int channel = vlv_dport_to_channel(dport);
1409
1410 vlv_wait_port_ready(dev_priv, channel);
1411 }
d240f20f
JB		 1412}
1413
2bd2ad64 1414static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1415{
2bd2ad64 1416 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
b2634017 1417 struct drm_device *dev = encoder->base.dev;
89b667f8 1418 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6 1419
b2634017 1420 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
2bd2ad64 1421 ironlake_edp_pll_on(intel_dp);
89b667f8
JB		 1422
1423 if (IS_VALLEYVIEW(dev)) {
1424 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1425 struct intel_crtc *intel_crtc =
1426 to_intel_crtc(encoder->base.crtc);
1427 int port = vlv_dport_to_channel(dport);
1428 int pipe = intel_crtc->pipe;
1429 u32 val;
1430
1431 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1432
1433 val = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1434 val = 0;
1435 if (pipe)
1436 val |= (1<<21);
1437 else
1438 val &= ~(1<<21);
1439 val |= 0x001000c4;
1440 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1441
1442 intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1443 0x00760018);
1444 intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1445 0x00400888);
1446 }
1447}
1448
1449static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1450{
1451 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1452 struct drm_device *dev = encoder->base.dev;
1453 struct drm_i915_private *dev_priv = dev->dev_private;
1454 int port = vlv_dport_to_channel(dport);
1455
1456 if (!IS_VALLEYVIEW(dev))
1457 return;
1458
1459 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1460
1461 /* Program Tx lane resets to default */
1462 intel_dpio_write(dev_priv, DPIO_PCS_TX(port),
1463 DPIO_PCS_TX_LANE2_RESET |
1464 DPIO_PCS_TX_LANE1_RESET);
1465 intel_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1466 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1467 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1468 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1469 DPIO_PCS_CLK_SOFT_RESET);
1470
1471 /* Fix up inter-pair skew failure */
1472 intel_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1473 intel_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1474 intel_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
a4fc5ed6
KP		 1475}
1476
1477/*
df0c237d
JB		 1478 * Native read with retry for link status and receiver capability reads for
1479 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1480 */
1481static bool
df0c237d
JB		 1482intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1483 uint8_t *recv, int recv_bytes)
a4fc5ed6 1484{
61da5fab
JB		 1485 int ret, i;
1486
df0c237d
JB		 1487 /*
1488 * Sinks are *supposed* to come up within 1ms from an off state,
1489 * but we're also supposed to retry 3 times per the spec.
1490 */
61da5fab 1491 for (i = 0; i < 3; i++) {
df0c237d
JB		 1492 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1493 recv_bytes);
1494 if (ret == recv_bytes)
61da5fab
JB		 1495 return true;
1496 msleep(1);
1497 }
a4fc5ed6 1498
61da5fab 1499 return false;
a4fc5ed6
KP		 1500}
1501
1502/*
1503 * Fetch AUX CH registers 0x202 - 0x207 which contain
1504 * link status information
1505 */
1506static bool
93f62dad 1507intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1508{
df0c237d
JB		 1509 return intel_dp_aux_native_read_retry(intel_dp,
1510 DP_LANE0_1_STATUS,
93f62dad 1511 link_status,
df0c237d 1512 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1513}
1514
a4fc5ed6
KP		 1515#if 0
1516static char *voltage_names[] = {
1517 "0.4V", "0.6V", "0.8V", "1.2V"
1518};
1519static char *pre_emph_names[] = {
1520 "0dB", "3.5dB", "6dB", "9.5dB"
1521};
1522static char *link_train_names[] = {
1523 "pattern 1", "pattern 2", "idle", "off"
1524};
1525#endif
1526
1527/*
1528 * These are source-specific values; current Intel hardware supports
1529 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1530 */
a4fc5ed6
KP		 1531
1532static uint8_t
1a2eb460 1533intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1534{
30add22d 1535 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1536
e2fa6fba
P		 1537 if (IS_VALLEYVIEW(dev))
1538 return DP_TRAIN_VOLTAGE_SWING_1200;
1539 else if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1a2eb460
KP		 1540 return DP_TRAIN_VOLTAGE_SWING_800;
1541 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1542 return DP_TRAIN_VOLTAGE_SWING_1200;
1543 else
1544 return DP_TRAIN_VOLTAGE_SWING_800;
1545}
1546
1547static uint8_t
1548intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1549{
30add22d 1550 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1551
22b8bf17 1552 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1553 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1554 case DP_TRAIN_VOLTAGE_SWING_400:
1555 return DP_TRAIN_PRE_EMPHASIS_9_5;
1556 case DP_TRAIN_VOLTAGE_SWING_600:
1557 return DP_TRAIN_PRE_EMPHASIS_6;
1558 case DP_TRAIN_VOLTAGE_SWING_800:
1559 return DP_TRAIN_PRE_EMPHASIS_3_5;
1560 case DP_TRAIN_VOLTAGE_SWING_1200:
1561 default:
1562 return DP_TRAIN_PRE_EMPHASIS_0;
1563 }
e2fa6fba
P		 1564 } else if (IS_VALLEYVIEW(dev)) {
1565 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1566 case DP_TRAIN_VOLTAGE_SWING_400:
1567 return DP_TRAIN_PRE_EMPHASIS_9_5;
1568 case DP_TRAIN_VOLTAGE_SWING_600:
1569 return DP_TRAIN_PRE_EMPHASIS_6;
1570 case DP_TRAIN_VOLTAGE_SWING_800:
1571 return DP_TRAIN_PRE_EMPHASIS_3_5;
1572 case DP_TRAIN_VOLTAGE_SWING_1200:
1573 default:
1574 return DP_TRAIN_PRE_EMPHASIS_0;
1575 }
1576 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1a2eb460
KP		 1577 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1578 case DP_TRAIN_VOLTAGE_SWING_400:
1579 return DP_TRAIN_PRE_EMPHASIS_6;
1580 case DP_TRAIN_VOLTAGE_SWING_600:
1581 case DP_TRAIN_VOLTAGE_SWING_800:
1582 return DP_TRAIN_PRE_EMPHASIS_3_5;
1583 default:
1584 return DP_TRAIN_PRE_EMPHASIS_0;
1585 }
1586 } else {
1587 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1588 case DP_TRAIN_VOLTAGE_SWING_400:
1589 return DP_TRAIN_PRE_EMPHASIS_6;
1590 case DP_TRAIN_VOLTAGE_SWING_600:
1591 return DP_TRAIN_PRE_EMPHASIS_6;
1592 case DP_TRAIN_VOLTAGE_SWING_800:
1593 return DP_TRAIN_PRE_EMPHASIS_3_5;
1594 case DP_TRAIN_VOLTAGE_SWING_1200:
1595 default:
1596 return DP_TRAIN_PRE_EMPHASIS_0;
1597 }
a4fc5ed6
KP		 1598 }
1599}
1600
e2fa6fba
P		 1601static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1602{
1603 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1605 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1606 unsigned long demph_reg_value, preemph_reg_value,
1607 uniqtranscale_reg_value;
1608 uint8_t train_set = intel_dp->train_set[0];
cece5d58 1609 int port = vlv_dport_to_channel(dport);
e2fa6fba 1610
89b667f8
JB		 1611 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1612
e2fa6fba
P		 1613 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1614 case DP_TRAIN_PRE_EMPHASIS_0:
1615 preemph_reg_value = 0x0004000;
1616 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1617 case DP_TRAIN_VOLTAGE_SWING_400:
1618 demph_reg_value = 0x2B405555;
1619 uniqtranscale_reg_value = 0x552AB83A;
1620 break;
1621 case DP_TRAIN_VOLTAGE_SWING_600:
1622 demph_reg_value = 0x2B404040;
1623 uniqtranscale_reg_value = 0x5548B83A;
1624 break;
1625 case DP_TRAIN_VOLTAGE_SWING_800:
1626 demph_reg_value = 0x2B245555;
1627 uniqtranscale_reg_value = 0x5560B83A;
1628 break;
1629 case DP_TRAIN_VOLTAGE_SWING_1200:
1630 demph_reg_value = 0x2B405555;
1631 uniqtranscale_reg_value = 0x5598DA3A;
1632 break;
1633 default:
1634 return 0;
1635 }
1636 break;
1637 case DP_TRAIN_PRE_EMPHASIS_3_5:
1638 preemph_reg_value = 0x0002000;
1639 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1640 case DP_TRAIN_VOLTAGE_SWING_400:
1641 demph_reg_value = 0x2B404040;
1642 uniqtranscale_reg_value = 0x5552B83A;
1643 break;
1644 case DP_TRAIN_VOLTAGE_SWING_600:
1645 demph_reg_value = 0x2B404848;
1646 uniqtranscale_reg_value = 0x5580B83A;
1647 break;
1648 case DP_TRAIN_VOLTAGE_SWING_800:
1649 demph_reg_value = 0x2B404040;
1650 uniqtranscale_reg_value = 0x55ADDA3A;
1651 break;
1652 default:
1653 return 0;
1654 }
1655 break;
1656 case DP_TRAIN_PRE_EMPHASIS_6:
1657 preemph_reg_value = 0x0000000;
1658 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1659 case DP_TRAIN_VOLTAGE_SWING_400:
1660 demph_reg_value = 0x2B305555;
1661 uniqtranscale_reg_value = 0x5570B83A;
1662 break;
1663 case DP_TRAIN_VOLTAGE_SWING_600:
1664 demph_reg_value = 0x2B2B4040;
1665 uniqtranscale_reg_value = 0x55ADDA3A;
1666 break;
1667 default:
1668 return 0;
1669 }
1670 break;
1671 case DP_TRAIN_PRE_EMPHASIS_9_5:
1672 preemph_reg_value = 0x0006000;
1673 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1674 case DP_TRAIN_VOLTAGE_SWING_400:
1675 demph_reg_value = 0x1B405555;
1676 uniqtranscale_reg_value = 0x55ADDA3A;
1677 break;
1678 default:
1679 return 0;
1680 }
1681 break;
1682 default:
1683 return 0;
1684 }
1685
e2fa6fba
P		 1686 intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1687 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1688 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1689 uniqtranscale_reg_value);
1690 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1691 intel_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1692 intel_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1693 intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
e2fa6fba
P		 1694
1695 return 0;
1696}
1697
a4fc5ed6 1698static void
93f62dad 1699intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1700{
1701 uint8_t v = 0;
1702 uint8_t p = 0;
1703 int lane;
1a2eb460
KP		 1704 uint8_t voltage_max;
1705 uint8_t preemph_max;
a4fc5ed6 1706
33a34e4e 1707 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1708 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1709 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1710
1711 if (this_v > v)
1712 v = this_v;
1713 if (this_p > p)
1714 p = this_p;
1715 }
1716
1a2eb460 1717 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1718 if (v >= voltage_max)
1719 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1720
1a2eb460
KP		 1721 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1722 if (p >= preemph_max)
1723 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1724
1725 for (lane = 0; lane < 4; lane++)
33a34e4e 1726 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1727}
1728
1729static uint32_t
f0a3424e 1730intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 1731{
3cf2efb1 1732 uint32_t signal_levels = 0;
a4fc5ed6 1733
3cf2efb1 1734 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1735 case DP_TRAIN_VOLTAGE_SWING_400:
1736 default:
1737 signal_levels |= DP_VOLTAGE_0_4;
1738 break;
1739 case DP_TRAIN_VOLTAGE_SWING_600:
1740 signal_levels |= DP_VOLTAGE_0_6;
1741 break;
1742 case DP_TRAIN_VOLTAGE_SWING_800:
1743 signal_levels |= DP_VOLTAGE_0_8;
1744 break;
1745 case DP_TRAIN_VOLTAGE_SWING_1200:
1746 signal_levels |= DP_VOLTAGE_1_2;
1747 break;
1748 }
3cf2efb1 1749 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1750 case DP_TRAIN_PRE_EMPHASIS_0:
1751 default:
1752 signal_levels |= DP_PRE_EMPHASIS_0;
1753 break;
1754 case DP_TRAIN_PRE_EMPHASIS_3_5:
1755 signal_levels |= DP_PRE_EMPHASIS_3_5;
1756 break;
1757 case DP_TRAIN_PRE_EMPHASIS_6:
1758 signal_levels |= DP_PRE_EMPHASIS_6;
1759 break;
1760 case DP_TRAIN_PRE_EMPHASIS_9_5:
1761 signal_levels |= DP_PRE_EMPHASIS_9_5;
1762 break;
1763 }
1764 return signal_levels;
1765}
1766
e3421a18
ZW		 1767/* Gen6's DP voltage swing and pre-emphasis control */
1768static uint32_t
1769intel_gen6_edp_signal_levels(uint8_t train_set)
1770{
3c5a62b5
YL		 1771 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1772 DP_TRAIN_PRE_EMPHASIS_MASK);
1773 switch (signal_levels) {
e3421a18 1774 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1775 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1776 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1777 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1778 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1779 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1780 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1781 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1782 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1783 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1784 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1785 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1786 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1787 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1788 default:
3c5a62b5
YL		 1789 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1790 "0x%x\n", signal_levels);
1791 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1792 }
1793}
1794
1a2eb460
KP		 1795/* Gen7's DP voltage swing and pre-emphasis control */
1796static uint32_t
1797intel_gen7_edp_signal_levels(uint8_t train_set)
1798{
1799 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1800 DP_TRAIN_PRE_EMPHASIS_MASK);
1801 switch (signal_levels) {
1802 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1803 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1804 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1805 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1806 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1807 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1808
1809 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1810 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1811 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1812 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1813
1814 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1815 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1816 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1817 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1818
1819 default:
1820 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1821 "0x%x\n", signal_levels);
1822 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1823 }
1824}
1825
d6c0d722
PZ		 1826/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1827static uint32_t
f0a3424e 1828intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 1829{
d6c0d722
PZ		 1830 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1831 DP_TRAIN_PRE_EMPHASIS_MASK);
1832 switch (signal_levels) {
1833 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1834 return DDI_BUF_EMP_400MV_0DB_HSW;
1835 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1836 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1837 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1838 return DDI_BUF_EMP_400MV_6DB_HSW;
1839 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1840 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 1841
d6c0d722
PZ		 1842 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1843 return DDI_BUF_EMP_600MV_0DB_HSW;
1844 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1845 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1846 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1847 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 1848
d6c0d722
PZ		 1849 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1850 return DDI_BUF_EMP_800MV_0DB_HSW;
1851 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1852 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1853 default:
1854 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1855 "0x%x\n", signal_levels);
1856 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 1857 }
a4fc5ed6
KP		 1858}
1859
f0a3424e
PZ		 1860/* Properly updates "DP" with the correct signal levels. */
1861static void
1862intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1863{
1864 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1865 struct drm_device *dev = intel_dig_port->base.base.dev;
1866 uint32_t signal_levels, mask;
1867 uint8_t train_set = intel_dp->train_set[0];
1868
22b8bf17 1869 if (HAS_DDI(dev)) {
f0a3424e
PZ		 1870 signal_levels = intel_hsw_signal_levels(train_set);
1871 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 1872 } else if (IS_VALLEYVIEW(dev)) {
1873 signal_levels = intel_vlv_signal_levels(intel_dp);
1874 mask = 0;
1875 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
f0a3424e
PZ		 1876 signal_levels = intel_gen7_edp_signal_levels(train_set);
1877 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1878 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1879 signal_levels = intel_gen6_edp_signal_levels(train_set);
1880 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1881 } else {
1882 signal_levels = intel_gen4_signal_levels(train_set);
1883 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1884 }
1885
1886 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1887
1888 *DP = (*DP & ~mask) | signal_levels;
1889}
1890
a4fc5ed6 1891static bool
ea5b213a 1892intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1893 uint32_t dp_reg_value,
58e10eb9 1894 uint8_t dp_train_pat)
a4fc5ed6 1895{
174edf1f
PZ		 1896 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1897 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1898 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 1899 enum port port = intel_dig_port->port;
a4fc5ed6 1900 int ret;
d6c0d722 1901 uint32_t temp;
a4fc5ed6 1902
22b8bf17 1903 if (HAS_DDI(dev)) {
174edf1f 1904 temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 1905
1906 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1907 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1908 else
1909 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1910
1911 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1912 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1913 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722 1914
10aa17c8
PZ		 1915 if (port != PORT_A) {
1916 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1917 I915_WRITE(DP_TP_CTL(port), temp);
1918
1919 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1920 DP_TP_STATUS_IDLE_DONE), 1))
1921 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1922
1923 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1924 }
d6c0d722 1925
d6c0d722
PZ		 1926 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1927
1928 break;
1929 case DP_TRAINING_PATTERN_1:
1930 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1931 break;
1932 case DP_TRAINING_PATTERN_2:
1933 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1934 break;
1935 case DP_TRAINING_PATTERN_3:
1936 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1937 break;
1938 }
174edf1f 1939 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722
PZ		 1940
1941 } else if (HAS_PCH_CPT(dev) &&
1942 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1943 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1944
1945 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1946 case DP_TRAINING_PATTERN_DISABLE:
1947 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1948 break;
1949 case DP_TRAINING_PATTERN_1:
1950 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1951 break;
1952 case DP_TRAINING_PATTERN_2:
1953 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1954 break;
1955 case DP_TRAINING_PATTERN_3:
1956 DRM_ERROR("DP training pattern 3 not supported\n");
1957 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1958 break;
1959 }
1960
1961 } else {
1962 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1963
1964 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1965 case DP_TRAINING_PATTERN_DISABLE:
1966 dp_reg_value |= DP_LINK_TRAIN_OFF;
1967 break;
1968 case DP_TRAINING_PATTERN_1:
1969 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1970 break;
1971 case DP_TRAINING_PATTERN_2:
1972 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1973 break;
1974 case DP_TRAINING_PATTERN_3:
1975 DRM_ERROR("DP training pattern 3 not supported\n");
1976 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1977 break;
1978 }
1979 }
1980
ea5b213a
CW		 1981 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1982 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1983
ea5b213a 1984 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1985 DP_TRAINING_PATTERN_SET,
1986 dp_train_pat);
1987
47ea7542
PZ		 1988 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1989 DP_TRAINING_PATTERN_DISABLE) {
1990 ret = intel_dp_aux_native_write(intel_dp,
1991 DP_TRAINING_LANE0_SET,
1992 intel_dp->train_set,
1993 intel_dp->lane_count);
1994 if (ret != intel_dp->lane_count)
1995 return false;
1996 }
a4fc5ed6
KP		 1997
1998 return true;
1999}
2000
33a34e4e 2001/* Enable corresponding port and start training pattern 1 */
c19b0669 2002void
33a34e4e 2003intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2004{
da63a9f2 2005 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2006 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2007 int i;
2008 uint8_t voltage;
2009 bool clock_recovery = false;
cdb0e95b 2010 int voltage_tries, loop_tries;
ea5b213a 2011 uint32_t DP = intel_dp->DP;
a4fc5ed6 2012
affa9354 2013 if (HAS_DDI(dev))
c19b0669
PZ		 2014 intel_ddi_prepare_link_retrain(encoder);
2015
3cf2efb1
CW		 2016 /* Write the link configuration data */
2017 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2018 intel_dp->link_configuration,
2019 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 2020
2021 DP |= DP_PORT_EN;
1a2eb460 2022
33a34e4e 2023 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 2024 voltage = 0xff;
cdb0e95b
KP		 2025 voltage_tries = 0;
2026 loop_tries = 0;
a4fc5ed6
KP		 2027 clock_recovery = false;
2028 for (;;) {
33a34e4e 2029 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 2030 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 2031
2032 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 2033
a7c9655f 2034 /* Set training pattern 1 */
47ea7542 2035 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2036 DP_TRAINING_PATTERN_1 |
2037 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 2038 break;
a4fc5ed6 2039
a7c9655f 2040 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2041 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2042 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2043 break;
93f62dad 2044 }
a4fc5ed6 2045
01916270 2046 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2047 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2048 clock_recovery = true;
2049 break;
2050 }
2051
2052 /* Check to see if we've tried the max voltage */
2053 for (i = 0; i < intel_dp->lane_count; i++)
2054 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2055 break;
3b4f819d 2056 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2057 ++loop_tries;
2058 if (loop_tries == 5) {
cdb0e95b
KP		 2059 DRM_DEBUG_KMS("too many full retries, give up\n");
2060 break;
2061 }
2062 memset(intel_dp->train_set, 0, 4);
2063 voltage_tries = 0;
2064 continue;
2065 }
a4fc5ed6 2066
3cf2efb1 2067 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2068 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2069 ++voltage_tries;
b06fbda3
DV		 2070 if (voltage_tries == 5) {
2071 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2072 break;
2073 }
2074 } else
2075 voltage_tries = 0;
2076 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2077
3cf2efb1 2078 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2079 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 2080 }
2081
33a34e4e
JB		 2082 intel_dp->DP = DP;
2083}
2084
c19b0669 2085void
33a34e4e
JB		 2086intel_dp_complete_link_train(struct intel_dp *intel_dp)
2087{
33a34e4e 2088 bool channel_eq = false;
37f80975 2089 int tries, cr_tries;
33a34e4e
JB		 2090 uint32_t DP = intel_dp->DP;
2091
a4fc5ed6
KP		 2092 /* channel equalization */
2093 tries = 0;
37f80975 2094 cr_tries = 0;
a4fc5ed6
KP		 2095 channel_eq = false;
2096 for (;;) {
93f62dad 2097 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2098
37f80975
JB		 2099 if (cr_tries > 5) {
2100 DRM_ERROR("failed to train DP, aborting\n");
2101 intel_dp_link_down(intel_dp);
2102 break;
2103 }
2104
f0a3424e 2105 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 2106
a4fc5ed6 2107 /* channel eq pattern */
47ea7542 2108 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2109 DP_TRAINING_PATTERN_2 |
2110 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 2111 break;
2112
a7c9655f 2113 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 2114 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 2115 break;
a4fc5ed6 2116
37f80975 2117 /* Make sure clock is still ok */
01916270 2118 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 2119 intel_dp_start_link_train(intel_dp);
2120 cr_tries++;
2121 continue;
2122 }
2123
1ffdff13 2124 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2125 channel_eq = true;
2126 break;
2127 }
a4fc5ed6 2128
37f80975
JB		 2129 /* Try 5 times, then try clock recovery if that fails */
2130 if (tries > 5) {
2131 intel_dp_link_down(intel_dp);
2132 intel_dp_start_link_train(intel_dp);
2133 tries = 0;
2134 cr_tries++;
2135 continue;
2136 }
a4fc5ed6 2137
3cf2efb1 2138 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2139 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2140 ++tries;
869184a6 2141 }
3cf2efb1 2142
d6c0d722
PZ		 2143 if (channel_eq)
2144 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2145
47ea7542 2146 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2147}
2148
2149static void
ea5b213a 2150intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2151{
da63a9f2
PZ		 2152 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2153 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2154 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2155 struct intel_crtc *intel_crtc =
2156 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2157 uint32_t DP = intel_dp->DP;
a4fc5ed6 2158
c19b0669
PZ		 2159 /*
2160 * DDI code has a strict mode set sequence and we should try to respect
2161 * it, otherwise we might hang the machine in many different ways. So we
2162 * really should be disabling the port only on a complete crtc_disable
2163 * sequence. This function is just called under two conditions on DDI
2164 * code:
2165 * - Link train failed while doing crtc_enable, and on this case we
2166 * really should respect the mode set sequence and wait for a
2167 * crtc_disable.
2168 * - Someone turned the monitor off and intel_dp_check_link_status
2169 * called us. We don't need to disable the whole port on this case, so
2170 * when someone turns the monitor on again,
2171 * intel_ddi_prepare_link_retrain will take care of redoing the link
2172 * train.
2173 */
affa9354 2174 if (HAS_DDI(dev))
c19b0669
PZ		 2175 return;
2176
0c33d8d7 2177 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2178 return;
2179
28c97730 2180 DRM_DEBUG_KMS("\n");
32f9d658 2181
1a2eb460 2182 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 2183 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2184 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2185 } else {
2186 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2187 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2188 }
fe255d00 2189 POSTING_READ(intel_dp->output_reg);
5eb08b69 2190
ab527efc
DV		 2191 /* We don't really know why we're doing this */
2192 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2193
493a7081 2194 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2195 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2196 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2197
5bddd17f
EA		 2198 /* Hardware workaround: leaving our transcoder select
2199 * set to transcoder B while it's off will prevent the
2200 * corresponding HDMI output on transcoder A.
2201 *
2202 * Combine this with another hardware workaround:
2203 * transcoder select bit can only be cleared while the
2204 * port is enabled.
2205 */
2206 DP &= ~DP_PIPEB_SELECT;
2207 I915_WRITE(intel_dp->output_reg, DP);
2208
2209 /* Changes to enable or select take place the vblank
2210 * after being written.
2211 */
ff50afe9
DV		 2212 if (WARN_ON(crtc == NULL)) {
2213 /* We should never try to disable a port without a crtc
2214 * attached. For paranoia keep the code around for a
2215 * bit. */
31acbcc4
CW		 2216 POSTING_READ(intel_dp->output_reg);
2217 msleep(50);
2218 } else
ab527efc 2219 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2220 }
2221
832afda6 2222 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2223 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2224 POSTING_READ(intel_dp->output_reg);
f01eca2e 2225 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2226}
2227
26d61aad
KP		 2228static bool
2229intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2230{
577c7a50
DL		 2231 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2232
92fd8fd1 2233 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2234 sizeof(intel_dp->dpcd)) == 0)
2235 return false; /* aux transfer failed */
92fd8fd1 2236
577c7a50
DL		 2237 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2238 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2239 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2240
edb39244
AJ		 2241 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2242 return false; /* DPCD not present */
2243
2244 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2245 DP_DWN_STRM_PORT_PRESENT))
2246 return true; /* native DP sink */
2247
2248 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2249 return true; /* no per-port downstream info */
2250
2251 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2252 intel_dp->downstream_ports,
2253 DP_MAX_DOWNSTREAM_PORTS) == 0)
2254 return false; /* downstream port status fetch failed */
2255
2256 return true;
92fd8fd1
KP		 2257}
2258
0d198328
AJ		 2259static void
2260intel_dp_probe_oui(struct intel_dp *intel_dp)
2261{
2262 u8 buf[3];
2263
2264 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2265 return;
2266
351cfc34
DV		 2267 ironlake_edp_panel_vdd_on(intel_dp);
2268
0d198328
AJ		 2269 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2270 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2271 buf[0], buf[1], buf[2]);
2272
2273 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2274 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2275 buf[0], buf[1], buf[2]);
351cfc34
DV		 2276
2277 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2278}
2279
a60f0e38
JB		 2280static bool
2281intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2282{
2283 int ret;
2284
2285 ret = intel_dp_aux_native_read_retry(intel_dp,
2286 DP_DEVICE_SERVICE_IRQ_VECTOR,
2287 sink_irq_vector, 1);
2288 if (!ret)
2289 return false;
2290
2291 return true;
2292}
2293
2294static void
2295intel_dp_handle_test_request(struct intel_dp *intel_dp)
2296{
2297 /* NAK by default */
9324cf7f 2298 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2299}
2300
a4fc5ed6
KP		 2301/*
2302 * According to DP spec
2303 * 5.1.2:
2304 * 1. Read DPCD
2305 * 2. Configure link according to Receiver Capabilities
2306 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2307 * 4. Check link status on receipt of hot-plug interrupt
2308 */
2309
00c09d70 2310void
ea5b213a 2311intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2312{
da63a9f2 2313 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2314 u8 sink_irq_vector;
93f62dad 2315 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2316
da63a9f2 2317 if (!intel_encoder->connectors_active)
d2b996ac 2318 return;
59cd09e1 2319
da63a9f2 2320 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2321 return;
2322
92fd8fd1 2323 /* Try to read receiver status if the link appears to be up */
93f62dad 2324 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2325 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2326 return;
2327 }
2328
92fd8fd1 2329 /* Now read the DPCD to see if it's actually running */
26d61aad 2330 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2331 intel_dp_link_down(intel_dp);
2332 return;
2333 }
2334
a60f0e38
JB		 2335 /* Try to read the source of the interrupt */
2336 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2337 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2338 /* Clear interrupt source */
2339 intel_dp_aux_native_write_1(intel_dp,
2340 DP_DEVICE_SERVICE_IRQ_VECTOR,
2341 sink_irq_vector);
2342
2343 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2344 intel_dp_handle_test_request(intel_dp);
2345 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2346 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2347 }
2348
1ffdff13 2349 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2350 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2351 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2352 intel_dp_start_link_train(intel_dp);
2353 intel_dp_complete_link_train(intel_dp);
2354 }
a4fc5ed6 2355}
a4fc5ed6 2356
caf9ab24 2357/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2358static enum drm_connector_status
26d61aad 2359intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2360{
caf9ab24
AJ		 2361 uint8_t *dpcd = intel_dp->dpcd;
2362 bool hpd;
2363 uint8_t type;
2364
2365 if (!intel_dp_get_dpcd(intel_dp))
2366 return connector_status_disconnected;
2367
2368 /* if there's no downstream port, we're done */
2369 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2370 return connector_status_connected;
caf9ab24
AJ		 2371
2372 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2373 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2374 if (hpd) {
23235177 2375 uint8_t reg;
caf9ab24 2376 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2377 &reg, 1))
caf9ab24 2378 return connector_status_unknown;
23235177
AJ		 2379 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2380 : connector_status_disconnected;
caf9ab24
AJ		 2381 }
2382
2383 /* If no HPD, poke DDC gently */
2384 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2385 return connector_status_connected;
caf9ab24
AJ		 2386
2387 /* Well we tried, say unknown for unreliable port types */
2388 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2389 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2390 return connector_status_unknown;
2391
2392 /* Anything else is out of spec, warn and ignore */
2393 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2394 return connector_status_disconnected;
71ba9000
AJ		 2395}
2396
5eb08b69 2397static enum drm_connector_status
a9756bb5 2398ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2399{
30add22d 2400 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2401 struct drm_i915_private *dev_priv = dev->dev_private;
2402 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2403 enum drm_connector_status status;
2404
fe16d949
CW		 2405 /* Can't disconnect eDP, but you can close the lid... */
2406 if (is_edp(intel_dp)) {
30add22d 2407 status = intel_panel_detect(dev);
fe16d949
CW		 2408 if (status == connector_status_unknown)
2409 status = connector_status_connected;
2410 return status;
2411 }
01cb9ea6 2412
1b469639
DL		 2413 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2414 return connector_status_disconnected;
2415
26d61aad 2416 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2417}
2418
a4fc5ed6 2419static enum drm_connector_status
a9756bb5 2420g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2421{
30add22d 2422 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2423 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2424 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2425 uint32_t bit;
5eb08b69 2426
35aad75f
JB		 2427 /* Can't disconnect eDP, but you can close the lid... */
2428 if (is_edp(intel_dp)) {
2429 enum drm_connector_status status;
2430
2431 status = intel_panel_detect(dev);
2432 if (status == connector_status_unknown)
2433 status = connector_status_connected;
2434 return status;
2435 }
2436
34f2be46
VS		 2437 switch (intel_dig_port->port) {
2438 case PORT_B:
26739f12 2439 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2440 break;
34f2be46 2441 case PORT_C:
26739f12 2442 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2443 break;
34f2be46 2444 case PORT_D:
26739f12 2445 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2446 break;
2447 default:
2448 return connector_status_unknown;
2449 }
2450
10f76a38 2451 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2452 return connector_status_disconnected;
2453
26d61aad 2454 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2455}
2456
8c241fef
KP		 2457static struct edid *
2458intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2459{
9cd300e0 2460 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2461
9cd300e0
JN		 2462 /* use cached edid if we have one */
2463 if (intel_connector->edid) {
2464 struct edid *edid;
2465 int size;
2466
2467 /* invalid edid */
2468 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2469 return NULL;
2470
9cd300e0 2471 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
d6f24d0f
JB		 2472 edid = kmalloc(size, GFP_KERNEL);
2473 if (!edid)
2474 return NULL;
2475
9cd300e0 2476 memcpy(edid, intel_connector->edid, size);
d6f24d0f
JB		 2477 return edid;
2478 }
8c241fef 2479
9cd300e0 2480 return drm_get_edid(connector, adapter);
8c241fef
KP		 2481}
2482
2483static int
2484intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2485{
9cd300e0 2486 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2487
9cd300e0
JN		 2488 /* use cached edid if we have one */
2489 if (intel_connector->edid) {
2490 /* invalid edid */
2491 if (IS_ERR(intel_connector->edid))
2492 return 0;
2493
2494 return intel_connector_update_modes(connector,
2495 intel_connector->edid);
d6f24d0f
JB		 2496 }
2497
9cd300e0 2498 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2499}
2500
a9756bb5
ZW		 2501static enum drm_connector_status
2502intel_dp_detect(struct drm_connector *connector, bool force)
2503{
2504 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2505 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2506 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2507 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2508 enum drm_connector_status status;
2509 struct edid *edid = NULL;
2510
2511 intel_dp->has_audio = false;
2512
2513 if (HAS_PCH_SPLIT(dev))
2514 status = ironlake_dp_detect(intel_dp);
2515 else
2516 status = g4x_dp_detect(intel_dp);
1b9be9d0 2517
a9756bb5
ZW		 2518 if (status != connector_status_connected)
2519 return status;
2520
0d198328
AJ		 2521 intel_dp_probe_oui(intel_dp);
2522
c3e5f67b
DV		 2523 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2524 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2525 } else {
8c241fef 2526 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2527 if (edid) {
2528 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2529 kfree(edid);
2530 }
a9756bb5
ZW		 2531 }
2532
d63885da
PZ		 2533 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2534 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2535 return connector_status_connected;
a4fc5ed6
KP		 2536}
2537
2538static int intel_dp_get_modes(struct drm_connector *connector)
2539{
df0e9248 2540 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2541 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2542 struct drm_device *dev = connector->dev;
32f9d658 2543 int ret;
a4fc5ed6
KP		 2544
2545 /* We should parse the EDID data and find out if it has an audio sink
2546 */
2547
8c241fef 2548 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2549 if (ret)
32f9d658
ZW		 2550 return ret;
2551
f8779fda 2552 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2553 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2554 struct drm_display_mode *mode;
dd06f90e
JN		 2555 mode = drm_mode_duplicate(dev,
2556 intel_connector->panel.fixed_mode);
f8779fda 2557 if (mode) {
32f9d658
ZW		 2558 drm_mode_probed_add(connector, mode);
2559 return 1;
2560 }
2561 }
2562 return 0;
a4fc5ed6
KP		 2563}
2564
1aad7ac0
CW		 2565static bool
2566intel_dp_detect_audio(struct drm_connector *connector)
2567{
2568 struct intel_dp *intel_dp = intel_attached_dp(connector);
2569 struct edid *edid;
2570 bool has_audio = false;
2571
8c241fef 2572 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2573 if (edid) {
2574 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2575 kfree(edid);
2576 }
2577
2578 return has_audio;
2579}
2580
f684960e
CW		 2581static int
2582intel_dp_set_property(struct drm_connector *connector,
2583 struct drm_property *property,
2584 uint64_t val)
2585{
e953fd7b 2586 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2587 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2588 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2589 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2590 int ret;
2591
662595df 2592 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2593 if (ret)
2594 return ret;
2595
3f43c48d 2596 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2597 int i = val;
2598 bool has_audio;
2599
2600 if (i == intel_dp->force_audio)
f684960e
CW		 2601 return 0;
2602
1aad7ac0 2603 intel_dp->force_audio = i;
f684960e 2604
c3e5f67b 2605 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2606 has_audio = intel_dp_detect_audio(connector);
2607 else
c3e5f67b 2608 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2609
2610 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2611 return 0;
2612
1aad7ac0 2613 intel_dp->has_audio = has_audio;
f684960e
CW		 2614 goto done;
2615 }
2616
e953fd7b 2617 if (property == dev_priv->broadcast_rgb_property) {
55bc60db
VS		 2618 switch (val) {
2619 case INTEL_BROADCAST_RGB_AUTO:
2620 intel_dp->color_range_auto = true;
2621 break;
2622 case INTEL_BROADCAST_RGB_FULL:
2623 intel_dp->color_range_auto = false;
2624 intel_dp->color_range = 0;
2625 break;
2626 case INTEL_BROADCAST_RGB_LIMITED:
2627 intel_dp->color_range_auto = false;
2628 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2629 break;
2630 default:
2631 return -EINVAL;
2632 }
e953fd7b
CW		 2633 goto done;
2634 }
2635
53b41837
YN		 2636 if (is_edp(intel_dp) &&
2637 property == connector->dev->mode_config.scaling_mode_property) {
2638 if (val == DRM_MODE_SCALE_NONE) {
2639 DRM_DEBUG_KMS("no scaling not supported\n");
2640 return -EINVAL;
2641 }
2642
2643 if (intel_connector->panel.fitting_mode == val) {
2644 /* the eDP scaling property is not changed */
2645 return 0;
2646 }
2647 intel_connector->panel.fitting_mode = val;
2648
2649 goto done;
2650 }
2651
f684960e
CW		 2652 return -EINVAL;
2653
2654done:
c0c36b94
CW		 2655 if (intel_encoder->base.crtc)
2656 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 2657
2658 return 0;
2659}
2660
a4fc5ed6 2661static void
0206e353 2662intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2663{
be3cd5e3 2664 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2665 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2666
9cd300e0
JN		 2667 if (!IS_ERR_OR_NULL(intel_connector->edid))
2668 kfree(intel_connector->edid);
2669
dc652f90 2670 if (is_edp(intel_dp))
1d508706 2671 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 2672
a4fc5ed6
KP		 2673 drm_sysfs_connector_remove(connector);
2674 drm_connector_cleanup(connector);
55f78c43 2675 kfree(connector);
a4fc5ed6
KP		 2676}
2677
00c09d70 2678void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 2679{
da63a9f2
PZ		 2680 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2681 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927
DV		 2682
2683 i2c_del_adapter(&intel_dp->adapter);
2684 drm_encoder_cleanup(encoder);
bd943159
KP		 2685 if (is_edp(intel_dp)) {
2686 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2687 ironlake_panel_vdd_off_sync(intel_dp);
2688 }
da63a9f2 2689 kfree(intel_dig_port);
24d05927
DV		 2690}
2691
a4fc5ed6 2692static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2693 .mode_set = intel_dp_mode_set,
a4fc5ed6
KP		 2694};
2695
2696static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2697 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2698 .detect = intel_dp_detect,
2699 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2700 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2701 .destroy = intel_dp_destroy,
2702};
2703
2704static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2705 .get_modes = intel_dp_get_modes,
2706 .mode_valid = intel_dp_mode_valid,
df0e9248 2707 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2708};
2709
a4fc5ed6 2710static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2711 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2712};
2713
995b6762 2714static void
21d40d37 2715intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2716{
fa90ecef 2717 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 2718
885a5014 2719 intel_dp_check_link_status(intel_dp);
c8110e52 2720}
6207937d 2721
e3421a18
ZW		 2722/* Return which DP Port should be selected for Transcoder DP control */
2723int
0206e353 2724intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2725{
2726 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 2727 struct intel_encoder *intel_encoder;
2728 struct intel_dp *intel_dp;
e3421a18 2729
fa90ecef
PZ		 2730 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2731 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 2732
fa90ecef
PZ		 2733 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2734 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 2735 return intel_dp->output_reg;
e3421a18 2736 }
ea5b213a 2737
e3421a18
ZW		 2738 return -1;
2739}
2740
36e83a18 2741/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2742bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2743{
2744 struct drm_i915_private *dev_priv = dev->dev_private;
2745 struct child_device_config *p_child;
2746 int i;
2747
2748 if (!dev_priv->child_dev_num)
2749 return false;
2750
2751 for (i = 0; i < dev_priv->child_dev_num; i++) {
2752 p_child = dev_priv->child_dev + i;
2753
2754 if (p_child->dvo_port == PORT_IDPD &&
2755 p_child->device_type == DEVICE_TYPE_eDP)
2756 return true;
2757 }
2758 return false;
2759}
2760
f684960e
CW		 2761static void
2762intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2763{
53b41837
YN		 2764 struct intel_connector *intel_connector = to_intel_connector(connector);
2765
3f43c48d 2766 intel_attach_force_audio_property(connector);
e953fd7b 2767 intel_attach_broadcast_rgb_property(connector);
55bc60db 2768 intel_dp->color_range_auto = true;
53b41837
YN		 2769
2770 if (is_edp(intel_dp)) {
2771 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 2772 drm_object_attach_property(
2773 &connector->base,
53b41837 2774 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 2775 DRM_MODE_SCALE_ASPECT);
2776 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 2777 }
f684960e
CW		 2778}
2779
67a54566
DV		 2780static void
2781intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 2782 struct intel_dp *intel_dp,
2783 struct edp_power_seq *out)
67a54566
DV		 2784{
2785 struct drm_i915_private *dev_priv = dev->dev_private;
2786 struct edp_power_seq cur, vbt, spec, final;
2787 u32 pp_on, pp_off, pp_div, pp;
453c5420
JB		 2788 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2789
2790 if (HAS_PCH_SPLIT(dev)) {
2791 pp_control_reg = PCH_PP_CONTROL;
2792 pp_on_reg = PCH_PP_ON_DELAYS;
2793 pp_off_reg = PCH_PP_OFF_DELAYS;
2794 pp_div_reg = PCH_PP_DIVISOR;
2795 } else {
2796 pp_control_reg = PIPEA_PP_CONTROL;
2797 pp_on_reg = PIPEA_PP_ON_DELAYS;
2798 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2799 pp_div_reg = PIPEA_PP_DIVISOR;
2800 }
67a54566
DV		 2801
2802 /* Workaround: Need to write PP_CONTROL with the unlock key as
2803 * the very first thing. */
453c5420
JB		 2804 pp = ironlake_get_pp_control(intel_dp);
2805 I915_WRITE(pp_control_reg, pp);
67a54566 2806
453c5420
JB		 2807 pp_on = I915_READ(pp_on_reg);
2808 pp_off = I915_READ(pp_off_reg);
2809 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 2810
2811 /* Pull timing values out of registers */
2812 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2813 PANEL_POWER_UP_DELAY_SHIFT;
2814
2815 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2816 PANEL_LIGHT_ON_DELAY_SHIFT;
2817
2818 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2819 PANEL_LIGHT_OFF_DELAY_SHIFT;
2820
2821 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2822 PANEL_POWER_DOWN_DELAY_SHIFT;
2823
2824 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2825 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2826
2827 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2828 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2829
2830 vbt = dev_priv->edp.pps;
2831
2832 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2833 * our hw here, which are all in 100usec. */
2834 spec.t1_t3 = 210 * 10;
2835 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2836 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2837 spec.t10 = 500 * 10;
2838 /* This one is special and actually in units of 100ms, but zero
2839 * based in the hw (so we need to add 100 ms). But the sw vbt
2840 * table multiplies it with 1000 to make it in units of 100usec,
2841 * too. */
2842 spec.t11_t12 = (510 + 100) * 10;
2843
2844 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2845 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2846
2847 /* Use the max of the register settings and vbt. If both are
2848 * unset, fall back to the spec limits. */
2849#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2850 spec.field : \
2851 max(cur.field, vbt.field))
2852 assign_final(t1_t3);
2853 assign_final(t8);
2854 assign_final(t9);
2855 assign_final(t10);
2856 assign_final(t11_t12);
2857#undef assign_final
2858
2859#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2860 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2861 intel_dp->backlight_on_delay = get_delay(t8);
2862 intel_dp->backlight_off_delay = get_delay(t9);
2863 intel_dp->panel_power_down_delay = get_delay(t10);
2864 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2865#undef get_delay
2866
f30d26e4
JN		 2867 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2868 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2869 intel_dp->panel_power_cycle_delay);
2870
2871 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2872 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2873
2874 if (out)
2875 *out = final;
2876}
2877
2878static void
2879intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2880 struct intel_dp *intel_dp,
2881 struct edp_power_seq *seq)
2882{
2883 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 2884 u32 pp_on, pp_off, pp_div, port_sel = 0;
2885 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2886 int pp_on_reg, pp_off_reg, pp_div_reg;
2887
2888 if (HAS_PCH_SPLIT(dev)) {
2889 pp_on_reg = PCH_PP_ON_DELAYS;
2890 pp_off_reg = PCH_PP_OFF_DELAYS;
2891 pp_div_reg = PCH_PP_DIVISOR;
2892 } else {
2893 pp_on_reg = PIPEA_PP_ON_DELAYS;
2894 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2895 pp_div_reg = PIPEA_PP_DIVISOR;
2896 }
2897
2898 if (IS_VALLEYVIEW(dev))
2899 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
f30d26e4 2900
67a54566 2901 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 2902 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2903 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2904 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2905 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 2906 /* Compute the divisor for the pp clock, simply match the Bspec
2907 * formula. */
453c5420 2908 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 2909 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 2910 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2911
2912 /* Haswell doesn't have any port selection bits for the panel
2913 * power sequencer any more. */
2914 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2915 if (is_cpu_edp(intel_dp))
453c5420 2916 port_sel = PANEL_POWER_PORT_DP_A;
67a54566 2917 else
453c5420 2918 port_sel = PANEL_POWER_PORT_DP_D;
67a54566
DV		 2919 }
2920
453c5420
JB		 2921 pp_on |= port_sel;
2922
2923 I915_WRITE(pp_on_reg, pp_on);
2924 I915_WRITE(pp_off_reg, pp_off);
2925 I915_WRITE(pp_div_reg, pp_div);
67a54566 2926
67a54566 2927 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 2928 I915_READ(pp_on_reg),
2929 I915_READ(pp_off_reg),
2930 I915_READ(pp_div_reg));
f684960e
CW		 2931}
2932
a4fc5ed6 2933void
f0fec3f2
PZ		 2934intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2935 struct intel_connector *intel_connector)
a4fc5ed6 2936{
f0fec3f2
PZ		 2937 struct drm_connector *connector = &intel_connector->base;
2938 struct intel_dp *intel_dp = &intel_dig_port->dp;
2939 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2940 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 2941 struct drm_i915_private *dev_priv = dev->dev_private;
f8779fda 2942 struct drm_display_mode *fixed_mode = NULL;
f30d26e4 2943 struct edp_power_seq power_seq = { 0 };
174edf1f 2944 enum port port = intel_dig_port->port;
5eb08b69 2945 const char *name = NULL;
b329530c 2946 int type;
a4fc5ed6 2947
0767935e
DV		 2948 /* Preserve the current hw state. */
2949 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 2950 intel_dp->attached_connector = intel_connector;
3d3dc149 2951
f7d24902 2952 type = DRM_MODE_CONNECTOR_DisplayPort;
19c03924
GB		 2953 /*
2954 * FIXME : We need to initialize built-in panels before external panels.
2955 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2956 */
f7d24902
ID		 2957 switch (port) {
2958 case PORT_A:
19c03924 2959 type = DRM_MODE_CONNECTOR_eDP;
f7d24902
ID		 2960 break;
2961 case PORT_C:
2962 if (IS_VALLEYVIEW(dev))
2963 type = DRM_MODE_CONNECTOR_eDP;
2964 break;
2965 case PORT_D:
2966 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
2967 type = DRM_MODE_CONNECTOR_eDP;
2968 break;
2969 default: /* silence GCC warning */
2970 break;
b329530c
AJ		 2971 }
2972
f7d24902
ID		 2973 /*
2974 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
2975 * for DP the encoder type can be set by the caller to
2976 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
2977 */
2978 if (type == DRM_MODE_CONNECTOR_eDP)
2979 intel_encoder->type = INTEL_OUTPUT_EDP;
2980
b329530c 2981 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2982 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2983
a4fc5ed6
KP		 2984 connector->interlace_allowed = true;
2985 connector->doublescan_allowed = 0;
2986
f0fec3f2
PZ		 2987 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2988 ironlake_panel_vdd_work);
a4fc5ed6 2989
df0e9248 2990 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2991 drm_sysfs_connector_add(connector);
2992
affa9354 2993 if (HAS_DDI(dev))
bcbc889b
PZ		 2994 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2995 else
2996 intel_connector->get_hw_state = intel_connector_get_hw_state;
2997
9ed35ab1
PZ		 2998 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
2999 if (HAS_DDI(dev)) {
3000 switch (intel_dig_port->port) {
3001 case PORT_A:
3002 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3003 break;
3004 case PORT_B:
3005 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3006 break;
3007 case PORT_C:
3008 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3009 break;
3010 case PORT_D:
3011 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3012 break;
3013 default:
3014 BUG();
3015 }
3016 }
e8cb4558 3017
a4fc5ed6 3018 /* Set up the DDC bus. */
ab9d7c30
PZ		 3019 switch (port) {
3020 case PORT_A:
1d843f9d 3021 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3022 name = "DPDDC-A";
3023 break;
3024 case PORT_B:
1d843f9d 3025 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3026 name = "DPDDC-B";
3027 break;
3028 case PORT_C:
1d843f9d 3029 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3030 name = "DPDDC-C";
3031 break;
3032 case PORT_D:
1d843f9d 3033 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3034 name = "DPDDC-D";
3035 break;
3036 default:
ad1c0b19 3037 BUG();
5eb08b69
ZW		 3038 }
3039
67a54566 3040 if (is_edp(intel_dp))
f30d26e4 3041 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
c1f05264
DA		 3042
3043 intel_dp_i2c_init(intel_dp, intel_connector, name);
3044
67a54566 3045 /* Cache DPCD and EDID for edp. */
c1f05264
DA		 3046 if (is_edp(intel_dp)) {
3047 bool ret;
f8779fda 3048 struct drm_display_mode *scan;
c1f05264 3049 struct edid *edid;
5d613501
JB		 3050
3051 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 3052 ret = intel_dp_get_dpcd(intel_dp);
bd943159 3053 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 3054
59f3e272 3055 if (ret) {
7183dc29
JB		 3056 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3057 dev_priv->no_aux_handshake =
3058 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 3059 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3060 } else {
3d3dc149 3061 /* if this fails, presume the device is a ghost */
48898b03 3062 DRM_INFO("failed to retrieve link info, disabling eDP\n");
fa90ecef
PZ		 3063 intel_dp_encoder_destroy(&intel_encoder->base);
3064 intel_dp_destroy(connector);
3d3dc149 3065 return;
89667383 3066 }
89667383 3067
f30d26e4
JN		 3068 /* We now know it's not a ghost, init power sequence regs. */
3069 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3070 &power_seq);
3071
d6f24d0f
JB		 3072 ironlake_edp_panel_vdd_on(intel_dp);
3073 edid = drm_get_edid(connector, &intel_dp->adapter);
3074 if (edid) {
9cd300e0
JN		 3075 if (drm_add_edid_modes(connector, edid)) {
3076 drm_mode_connector_update_edid_property(connector, edid);
3077 drm_edid_to_eld(connector, edid);
3078 } else {
3079 kfree(edid);
3080 edid = ERR_PTR(-EINVAL);
3081 }
3082 } else {
3083 edid = ERR_PTR(-ENOENT);
d6f24d0f 3084 }
9cd300e0 3085 intel_connector->edid = edid;
f8779fda
JN		 3086
3087 /* prefer fixed mode from EDID if available */
3088 list_for_each_entry(scan, &connector->probed_modes, head) {
3089 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3090 fixed_mode = drm_mode_duplicate(dev, scan);
3091 break;
3092 }
d6f24d0f 3093 }
f8779fda
JN		 3094
3095 /* fallback to VBT if available for eDP */
3096 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
3097 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
3098 if (fixed_mode)
3099 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3100 }
f8779fda 3101
d6f24d0f
JB		 3102 ironlake_edp_panel_vdd_off(intel_dp, false);
3103 }
552fb0b7 3104
4d926461 3105 if (is_edp(intel_dp)) {
dd06f90e 3106 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 3107 intel_panel_setup_backlight(connector);
32f9d658
ZW		 3108 }
3109
f684960e
CW		 3110 intel_dp_add_properties(intel_dp, connector);
3111
a4fc5ed6
KP		 3112 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3113 * 0xd. Failure to do so will result in spurious interrupts being
3114 * generated on the port when a cable is not attached.
3115 */
3116 if (IS_G4X(dev) && !IS_GM45(dev)) {
3117 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3118 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3119 }
3120}
f0fec3f2
PZ		 3121
3122void
3123intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3124{
3125 struct intel_digital_port *intel_dig_port;
3126 struct intel_encoder *intel_encoder;
3127 struct drm_encoder *encoder;
3128 struct intel_connector *intel_connector;
3129
3130 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3131 if (!intel_dig_port)
3132 return;
3133
3134 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3135 if (!intel_connector) {
3136 kfree(intel_dig_port);
3137 return;
3138 }
3139
3140 intel_encoder = &intel_dig_port->base;
3141 encoder = &intel_encoder->base;
3142
3143 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3144 DRM_MODE_ENCODER_TMDS);
00c09d70 3145 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
f0fec3f2 3146
5bfe2ac0 3147 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70
PZ		 3148 intel_encoder->enable = intel_enable_dp;
3149 intel_encoder->pre_enable = intel_pre_enable_dp;
3150 intel_encoder->disable = intel_disable_dp;
3151 intel_encoder->post_disable = intel_post_disable_dp;
3152 intel_encoder->get_hw_state = intel_dp_get_hw_state;
89b667f8
JB		 3153 if (IS_VALLEYVIEW(dev))
3154 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
f0fec3f2 3155
174edf1f 3156 intel_dig_port->port = port;
f0fec3f2
PZ		 3157 intel_dig_port->dp.output_reg = output_reg;
3158
00c09d70 3159 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3160 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3161 intel_encoder->cloneable = false;
3162 intel_encoder->hot_plug = intel_dp_hot_plug;
3163
3164 intel_dp_init_connector(intel_dig_port, intel_connector);
3165}
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