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drm/i915: simplify config->pixel_multiplier handling
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
55/**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63static bool is_pch_edp(struct intel_dp *intel_dp)
64{
65 return intel_dp->is_pch_edp;
66}
67
1c95822a
AJ		 68/**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74static bool is_cpu_edp(struct intel_dp *intel_dp)
75{
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77}
78
30add22d 79static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
ea5b213a 80{
da63a9f2
PZ		 81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
82
83 return intel_dig_port->base.base.dev;
ea5b213a 84}
a4fc5ed6 85
df0e9248
CW		 86static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
87{
fa90ecef 88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 89}
90
814948ad
JB		 91/**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99{
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108}
109
ea5b213a 110static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 111
a4fc5ed6 112static int
ea5b213a 113intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 114{
7183dc29 115 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 116
117 switch (max_link_bw) {
118 case DP_LINK_BW_1_62:
119 case DP_LINK_BW_2_7:
120 break;
121 default:
122 max_link_bw = DP_LINK_BW_1_62;
123 break;
124 }
125 return max_link_bw;
126}
127
cd9dde44
AJ		 128/*
129 * The units on the numbers in the next two are... bizarre. Examples will
130 * make it clearer; this one parallels an example in the eDP spec.
131 *
132 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
133 *
134 * 270000 * 1 * 8 / 10 == 216000
135 *
136 * The actual data capacity of that configuration is 2.16Gbit/s, so the
137 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
138 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
139 * 119000. At 18bpp that's 2142000 kilobits per second.
140 *
141 * Thus the strange-looking division by 10 in intel_dp_link_required, to
142 * get the result in decakilobits instead of kilobits.
143 */
144
a4fc5ed6 145static int
c898261c 146intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 147{
cd9dde44 148 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 149}
150
fe27d53e
DA		 151static int
152intel_dp_max_data_rate(int max_link_clock, int max_lanes)
153{
154 return (max_link_clock * max_lanes * 8) / 10;
155}
156
a4fc5ed6
KP		 157static int
158intel_dp_mode_valid(struct drm_connector *connector,
159 struct drm_display_mode *mode)
160{
df0e9248 161 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 162 struct intel_connector *intel_connector = to_intel_connector(connector);
163 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 164 int target_clock = mode->clock;
165 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 166
dd06f90e
JN		 167 if (is_edp(intel_dp) && fixed_mode) {
168 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 169 return MODE_PANEL;
170
dd06f90e 171 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 172 return MODE_PANEL;
03afc4a2
DV		 173
174 target_clock = fixed_mode->clock;
7de56f43
ZY		 175 }
176
36008365
DV		 177 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
178 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
179
180 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
181 mode_rate = intel_dp_link_required(target_clock, 18);
182
183 if (mode_rate > max_rate)
c4867936 184 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 185
186 if (mode->clock < 10000)
187 return MODE_CLOCK_LOW;
188
0af78a2b
DV		 189 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
190 return MODE_H_ILLEGAL;
191
a4fc5ed6
KP		 192 return MODE_OK;
193}
194
195static uint32_t
196pack_aux(uint8_t *src, int src_bytes)
197{
198 int i;
199 uint32_t v = 0;
200
201 if (src_bytes > 4)
202 src_bytes = 4;
203 for (i = 0; i < src_bytes; i++)
204 v |= ((uint32_t) src[i]) << ((3-i) * 8);
205 return v;
206}
207
208static void
209unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
210{
211 int i;
212 if (dst_bytes > 4)
213 dst_bytes = 4;
214 for (i = 0; i < dst_bytes; i++)
215 dst[i] = src >> ((3-i) * 8);
216}
217
fb0f8fbf
KP		 218/* hrawclock is 1/4 the FSB frequency */
219static int
220intel_hrawclk(struct drm_device *dev)
221{
222 struct drm_i915_private *dev_priv = dev->dev_private;
223 uint32_t clkcfg;
224
9473c8f4
VP		 225 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
226 if (IS_VALLEYVIEW(dev))
227 return 200;
228
fb0f8fbf
KP		 229 clkcfg = I915_READ(CLKCFG);
230 switch (clkcfg & CLKCFG_FSB_MASK) {
231 case CLKCFG_FSB_400:
232 return 100;
233 case CLKCFG_FSB_533:
234 return 133;
235 case CLKCFG_FSB_667:
236 return 166;
237 case CLKCFG_FSB_800:
238 return 200;
239 case CLKCFG_FSB_1067:
240 return 266;
241 case CLKCFG_FSB_1333:
242 return 333;
243 /* these two are just a guess; one of them might be right */
244 case CLKCFG_FSB_1600:
245 case CLKCFG_FSB_1600_ALT:
246 return 400;
247 default:
248 return 133;
249 }
250}
251
ebf33b18
KP		 252static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
253{
30add22d 254 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 255 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 256 u32 pp_stat_reg;
ebf33b18 257
453c5420
JB		 258 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
259 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
ebf33b18
KP		 260}
261
262static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
263{
30add22d 264 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 265 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 266 u32 pp_ctrl_reg;
ebf33b18 267
453c5420
JB		 268 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
269 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 270}
271
9b984dae
KP		 272static void
273intel_dp_check_edp(struct intel_dp *intel_dp)
274{
30add22d 275 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 276 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 277 u32 pp_stat_reg, pp_ctrl_reg;
ebf33b18 278
9b984dae
KP		 279 if (!is_edp(intel_dp))
280 return;
453c5420
JB		 281
282 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
283 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
284
ebf33b18 285 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 286 WARN(1, "eDP powered off while attempting aux channel communication.\n");
287 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
453c5420
JB		 288 I915_READ(pp_stat_reg),
289 I915_READ(pp_ctrl_reg));
9b984dae
KP		 290 }
291}
292
9ee32fea
DV		 293static uint32_t
294intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_device *dev = intel_dig_port->base.base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 299 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 300 uint32_t status;
301 bool done;
302
ef04f00d 303#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 304 if (has_aux_irq)
b90f5176
PZ		 305 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
306 msecs_to_jiffies(10));
9ee32fea
DV		 307 else
308 done = wait_for_atomic(C, 10) == 0;
309 if (!done)
310 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
311 has_aux_irq);
312#undef C
313
314 return status;
315}
316
a4fc5ed6 317static int
ea5b213a 318intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 319 uint8_t *send, int send_bytes,
320 uint8_t *recv, int recv_size)
321{
174edf1f
PZ		 322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
323 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 324 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 325 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
a4fc5ed6 326 uint32_t ch_data = ch_ctl + 4;
9ee32fea 327 int i, ret, recv_bytes;
a4fc5ed6 328 uint32_t status;
fb0f8fbf 329 uint32_t aux_clock_divider;
6b4e0a93 330 int try, precharge;
9ee32fea
DV		 331 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
332
333 /* dp aux is extremely sensitive to irq latency, hence request the
334 * lowest possible wakeup latency and so prevent the cpu from going into
335 * deep sleep states.
336 */
337 pm_qos_update_request(&dev_priv->pm_qos, 0);
a4fc5ed6 338
9b984dae 339 intel_dp_check_edp(intel_dp);
a4fc5ed6 340 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 341 * and would like to run at 2MHz. So, take the
342 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 343 *
344 * Note that PCH attached eDP panels should use a 125MHz input
345 * clock divider.
a4fc5ed6 346 */
1c95822a 347 if (is_cpu_edp(intel_dp)) {
affa9354 348 if (HAS_DDI(dev))
b8fc2f6a
PZ		 349 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
350 else if (IS_VALLEYVIEW(dev))
9473c8f4
VP		 351 aux_clock_divider = 100;
352 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 353 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 354 else
355 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 356 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
357 /* Workaround for non-ULT HSW */
358 aux_clock_divider = 74;
359 } else if (HAS_PCH_SPLIT(dev)) {
6b3ec1c9 360 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 361 } else {
5eb08b69 362 aux_clock_divider = intel_hrawclk(dev) / 2;
2c55c336 363 }
5eb08b69 364
6b4e0a93
DV		 365 if (IS_GEN6(dev))
366 precharge = 3;
367 else
368 precharge = 5;
369
11bee43e
JB		 370 /* Try to wait for any previous AUX channel activity */
371 for (try = 0; try < 3; try++) {
ef04f00d 372 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 373 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
374 break;
375 msleep(1);
376 }
377
378 if (try == 3) {
379 WARN(1, "dp_aux_ch not started status 0x%08x\n",
380 I915_READ(ch_ctl));
9ee32fea
DV		 381 ret = -EBUSY;
382 goto out;
4f7f7b7e
CW		 383 }
384
fb0f8fbf
KP		 385 /* Must try at least 3 times according to DP spec */
386 for (try = 0; try < 5; try++) {
387 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 388 for (i = 0; i < send_bytes; i += 4)
389 I915_WRITE(ch_data + i,
390 pack_aux(send + i, send_bytes - i));
0206e353 391
fb0f8fbf 392 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 393 I915_WRITE(ch_ctl,
394 DP_AUX_CH_CTL_SEND_BUSY |
9ee32fea 395 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
4f7f7b7e
CW		 396 DP_AUX_CH_CTL_TIME_OUT_400us |
397 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
398 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
399 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
400 DP_AUX_CH_CTL_DONE |
401 DP_AUX_CH_CTL_TIME_OUT_ERROR |
402 DP_AUX_CH_CTL_RECEIVE_ERROR);
9ee32fea
DV		 403
404 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
0206e353 405
fb0f8fbf 406 /* Clear done status and any errors */
4f7f7b7e
CW		 407 I915_WRITE(ch_ctl,
408 status |
409 DP_AUX_CH_CTL_DONE |
410 DP_AUX_CH_CTL_TIME_OUT_ERROR |
411 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 412
413 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
414 DP_AUX_CH_CTL_RECEIVE_ERROR))
415 continue;
4f7f7b7e 416 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 417 break;
418 }
419
a4fc5ed6 420 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 421 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 422 ret = -EBUSY;
423 goto out;
a4fc5ed6
KP		 424 }
425
426 /* Check for timeout or receive error.
427 * Timeouts occur when the sink is not connected
428 */
a5b3da54 429 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 430 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 431 ret = -EIO;
432 goto out;
a5b3da54 433 }
1ae8c0a5
KP		 434
435 /* Timeouts occur when the device isn't connected, so they're
436 * "normal" -- don't fill the kernel log with these */
a5b3da54 437 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 438 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 439 ret = -ETIMEDOUT;
440 goto out;
a4fc5ed6
KP		 441 }
442
443 /* Unload any bytes sent back from the other side */
444 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
445 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 446 if (recv_bytes > recv_size)
447 recv_bytes = recv_size;
0206e353 448
4f7f7b7e
CW		 449 for (i = 0; i < recv_bytes; i += 4)
450 unpack_aux(I915_READ(ch_data + i),
451 recv + i, recv_bytes - i);
a4fc5ed6 452
9ee32fea
DV		 453 ret = recv_bytes;
454out:
455 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
456
457 return ret;
a4fc5ed6
KP		 458}
459
460/* Write data to the aux channel in native mode */
461static int
ea5b213a 462intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 463 uint16_t address, uint8_t *send, int send_bytes)
464{
465 int ret;
466 uint8_t msg[20];
467 int msg_bytes;
468 uint8_t ack;
469
9b984dae 470 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 471 if (send_bytes > 16)
472 return -1;
473 msg[0] = AUX_NATIVE_WRITE << 4;
474 msg[1] = address >> 8;
eebc863e 475 msg[2] = address & 0xff;
a4fc5ed6
KP		 476 msg[3] = send_bytes - 1;
477 memcpy(&msg[4], send, send_bytes);
478 msg_bytes = send_bytes + 4;
479 for (;;) {
ea5b213a 480 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 481 if (ret < 0)
482 return ret;
483 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
484 break;
485 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
486 udelay(100);
487 else
a5b3da54 488 return -EIO;
a4fc5ed6
KP		 489 }
490 return send_bytes;
491}
492
493/* Write a single byte to the aux channel in native mode */
494static int
ea5b213a 495intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 496 uint16_t address, uint8_t byte)
497{
ea5b213a 498 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 499}
500
501/* read bytes from a native aux channel */
502static int
ea5b213a 503intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 504 uint16_t address, uint8_t *recv, int recv_bytes)
505{
506 uint8_t msg[4];
507 int msg_bytes;
508 uint8_t reply[20];
509 int reply_bytes;
510 uint8_t ack;
511 int ret;
512
9b984dae 513 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 514 msg[0] = AUX_NATIVE_READ << 4;
515 msg[1] = address >> 8;
516 msg[2] = address & 0xff;
517 msg[3] = recv_bytes - 1;
518
519 msg_bytes = 4;
520 reply_bytes = recv_bytes + 1;
521
522 for (;;) {
ea5b213a 523 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 524 reply, reply_bytes);
a5b3da54
KP		 525 if (ret == 0)
526 return -EPROTO;
527 if (ret < 0)
a4fc5ed6
KP		 528 return ret;
529 ack = reply[0];
530 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
531 memcpy(recv, reply + 1, ret - 1);
532 return ret - 1;
533 }
534 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
535 udelay(100);
536 else
a5b3da54 537 return -EIO;
a4fc5ed6
KP		 538 }
539}
540
541static int
ab2c0672
DA		 542intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
543 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 544{
ab2c0672 545 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 546 struct intel_dp *intel_dp = container_of(adapter,
547 struct intel_dp,
548 adapter);
ab2c0672
DA		 549 uint16_t address = algo_data->address;
550 uint8_t msg[5];
551 uint8_t reply[2];
8316f337 552 unsigned retry;
ab2c0672
DA		 553 int msg_bytes;
554 int reply_bytes;
555 int ret;
556
9b984dae 557 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 558 /* Set up the command byte */
559 if (mode & MODE_I2C_READ)
560 msg[0] = AUX_I2C_READ << 4;
561 else
562 msg[0] = AUX_I2C_WRITE << 4;
563
564 if (!(mode & MODE_I2C_STOP))
565 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 566
ab2c0672
DA		 567 msg[1] = address >> 8;
568 msg[2] = address;
569
570 switch (mode) {
571 case MODE_I2C_WRITE:
572 msg[3] = 0;
573 msg[4] = write_byte;
574 msg_bytes = 5;
575 reply_bytes = 1;
576 break;
577 case MODE_I2C_READ:
578 msg[3] = 0;
579 msg_bytes = 4;
580 reply_bytes = 2;
581 break;
582 default:
583 msg_bytes = 3;
584 reply_bytes = 1;
585 break;
586 }
587
8316f337
DF		 588 for (retry = 0; retry < 5; retry++) {
589 ret = intel_dp_aux_ch(intel_dp,
590 msg, msg_bytes,
591 reply, reply_bytes);
ab2c0672 592 if (ret < 0) {
3ff99164 593 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 594 return ret;
595 }
8316f337
DF		 596
597 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
598 case AUX_NATIVE_REPLY_ACK:
599 /* I2C-over-AUX Reply field is only valid
600 * when paired with AUX ACK.
601 */
602 break;
603 case AUX_NATIVE_REPLY_NACK:
604 DRM_DEBUG_KMS("aux_ch native nack\n");
605 return -EREMOTEIO;
606 case AUX_NATIVE_REPLY_DEFER:
607 udelay(100);
608 continue;
609 default:
610 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
611 reply[0]);
612 return -EREMOTEIO;
613 }
614
ab2c0672
DA		 615 switch (reply[0] & AUX_I2C_REPLY_MASK) {
616 case AUX_I2C_REPLY_ACK:
617 if (mode == MODE_I2C_READ) {
618 *read_byte = reply[1];
619 }
620 return reply_bytes - 1;
621 case AUX_I2C_REPLY_NACK:
8316f337 622 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 623 return -EREMOTEIO;
624 case AUX_I2C_REPLY_DEFER:
8316f337 625 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 626 udelay(100);
627 break;
628 default:
8316f337 629 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 630 return -EREMOTEIO;
631 }
632 }
8316f337
DF		 633
634 DRM_ERROR("too many retries, giving up\n");
635 return -EREMOTEIO;
a4fc5ed6
KP		 636}
637
638static int
ea5b213a 639intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 640 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 641{
0b5c541b
KP		 642 int ret;
643
d54e9d28 644 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 645 intel_dp->algo.running = false;
646 intel_dp->algo.address = 0;
647 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
648
0206e353 649 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 650 intel_dp->adapter.owner = THIS_MODULE;
651 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 652 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 653 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
654 intel_dp->adapter.algo_data = &intel_dp->algo;
655 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
656
0b5c541b
KP		 657 ironlake_edp_panel_vdd_on(intel_dp);
658 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 659 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 660 return ret;
a4fc5ed6
KP		 661}
662
c6bb3538
DV		 663static void
664intel_dp_set_clock(struct intel_encoder *encoder,
665 struct intel_crtc_config *pipe_config, int link_bw)
666{
667 struct drm_device *dev = encoder->base.dev;
668
669 if (IS_G4X(dev)) {
670 if (link_bw == DP_LINK_BW_1_62) {
671 pipe_config->dpll.p1 = 2;
672 pipe_config->dpll.p2 = 10;
673 pipe_config->dpll.n = 2;
674 pipe_config->dpll.m1 = 23;
675 pipe_config->dpll.m2 = 8;
676 } else {
677 pipe_config->dpll.p1 = 1;
678 pipe_config->dpll.p2 = 10;
679 pipe_config->dpll.n = 1;
680 pipe_config->dpll.m1 = 14;
681 pipe_config->dpll.m2 = 2;
682 }
683 pipe_config->clock_set = true;
684 } else if (IS_HASWELL(dev)) {
685 /* Haswell has special-purpose DP DDI clocks. */
686 } else if (HAS_PCH_SPLIT(dev)) {
687 if (link_bw == DP_LINK_BW_1_62) {
688 pipe_config->dpll.n = 1;
689 pipe_config->dpll.p1 = 2;
690 pipe_config->dpll.p2 = 10;
691 pipe_config->dpll.m1 = 12;
692 pipe_config->dpll.m2 = 9;
693 } else {
694 pipe_config->dpll.n = 2;
695 pipe_config->dpll.p1 = 1;
696 pipe_config->dpll.p2 = 10;
697 pipe_config->dpll.m1 = 14;
698 pipe_config->dpll.m2 = 8;
699 }
700 pipe_config->clock_set = true;
701 } else if (IS_VALLEYVIEW(dev)) {
702 /* FIXME: Need to figure out optimized DP clocks for vlv. */
703 }
704}
705
00c09d70 706bool
5bfe2ac0
DV		 707intel_dp_compute_config(struct intel_encoder *encoder,
708 struct intel_crtc_config *pipe_config)
a4fc5ed6 709{
5bfe2ac0 710 struct drm_device *dev = encoder->base.dev;
36008365 711 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0
DV		 712 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
713 struct drm_display_mode *mode = &pipe_config->requested_mode;
714 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
dd06f90e 715 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 716 int lane_count, clock;
397fe157 717 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 718 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 719 int bpp, mode_rate;
a4fc5ed6 720 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
36008365 721 int target_clock, link_avail, link_clock;
a4fc5ed6 722
5bfe2ac0
DV		 723 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
724 pipe_config->has_pch_encoder = true;
725
03afc4a2
DV		 726 pipe_config->has_dp_encoder = true;
727
dd06f90e
JN		 728 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
729 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
730 adjusted_mode);
53b41837
YN		 731 intel_pch_panel_fitting(dev,
732 intel_connector->panel.fitting_mode,
1d8e1c75 733 mode, adjusted_mode);
0d3a1bee 734 }
36008365
DV		 735 /* We need to take the panel's fixed mode into account. */
736 target_clock = adjusted_mode->clock;
0d3a1bee 737
cb1793ce 738 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 739 return false;
740
083f9560
DV		 741 DRM_DEBUG_KMS("DP link computation with max lane count %i "
742 "max bw %02x pixel clock %iKHz\n",
71244653 743 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 744
36008365
DV		 745 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
746 * bpc in between. */
03afc4a2 747 bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
36008365
DV		 748 for (; bpp >= 6*3; bpp -= 2*3) {
749 mode_rate = intel_dp_link_required(target_clock, bpp);
750
751 for (clock = 0; clock <= max_clock; clock++) {
752 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
753 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
754 link_avail = intel_dp_max_data_rate(link_clock,
755 lane_count);
756
757 if (mode_rate <= link_avail) {
758 goto found;
759 }
760 }
761 }
762 }
c4867936 763
36008365 764 return false;
3685a8f3 765
36008365 766found:
55bc60db
VS		 767 if (intel_dp->color_range_auto) {
768 /*
769 * See:
770 * CEA-861-E - 5.1 Default Encoding Parameters
771 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
772 */
18316c8c 773 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 774 intel_dp->color_range = DP_COLOR_RANGE_16_235;
775 else
776 intel_dp->color_range = 0;
777 }
778
3685a8f3 779 if (intel_dp->color_range)
50f3b016 780 pipe_config->limited_color_range = true;
3685a8f3 781
36008365
DV		 782 intel_dp->link_bw = bws[clock];
783 intel_dp->lane_count = lane_count;
784 adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
df92b1e6 785 pipe_config->pixel_target_clock = target_clock;
fe27d53e 786
36008365
DV		 787 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
788 intel_dp->link_bw, intel_dp->lane_count,
789 adjusted_mode->clock, bpp);
790 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
791 mode_rate, link_avail);
792
03afc4a2
DV		 793 intel_link_compute_m_n(bpp, lane_count,
794 target_clock, adjusted_mode->clock,
795 &pipe_config->dp_m_n);
a4fc5ed6 796
57c21963
DV		 797 /*
798 * XXX: We have a strange regression where using the vbt edp bpp value
799 * for the link bw computation results in black screens, the panel only
800 * works when we do the computation at the usual 24bpp (but still
801 * requires us to use 18bpp). Until that's fully debugged, stay
802 * bug-for-bug compatible with the old code.
803 */
804 if (is_edp(intel_dp) && dev_priv->edp.bpp) {
805 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n",
806 bpp, dev_priv->edp.bpp);
807 bpp = min_t(int, bpp, dev_priv->edp.bpp);
808 }
809 pipe_config->pipe_bpp = bpp;
810
c6bb3538
DV		 811 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
812
03afc4a2 813 return true;
a4fc5ed6
KP		 814}
815
247d89f6
PZ		 816void intel_dp_init_link_config(struct intel_dp *intel_dp)
817{
818 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
819 intel_dp->link_configuration[0] = intel_dp->link_bw;
820 intel_dp->link_configuration[1] = intel_dp->lane_count;
821 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
822 /*
823 * Check for DPCD version > 1.1 and enhanced framing support
824 */
825 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
826 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
827 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
828 }
829}
830
ea9b6006
DV		 831static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
832{
833 struct drm_device *dev = crtc->dev;
834 struct drm_i915_private *dev_priv = dev->dev_private;
835 u32 dpa_ctl;
836
837 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
838 dpa_ctl = I915_READ(DP_A);
839 dpa_ctl &= ~DP_PLL_FREQ_MASK;
840
841 if (clock < 200000) {
1ce17038
DV		 842 /* For a long time we've carried around a ILK-DevA w/a for the
843 * 160MHz clock. If we're really unlucky, it's still required.
844 */
845 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 846 dpa_ctl |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 847 } else {
848 dpa_ctl |= DP_PLL_FREQ_270MHZ;
849 }
1ce17038 850
ea9b6006
DV		 851 I915_WRITE(DP_A, dpa_ctl);
852
853 POSTING_READ(DP_A);
854 udelay(500);
855}
856
a4fc5ed6
KP		 857static void
858intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
859 struct drm_display_mode *adjusted_mode)
860{
e3421a18 861 struct drm_device *dev = encoder->dev;
417e822d 862 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 863 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
fa90ecef 864 struct drm_crtc *crtc = encoder->crtc;
a4fc5ed6
KP		 865 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
866
417e822d 867 /*
1a2eb460 868 * There are four kinds of DP registers:
417e822d
KP		 869 *
870 * IBX PCH
1a2eb460
KP		 871 * SNB CPU
872 * IVB CPU
417e822d
KP		 873 * CPT PCH
874 *
875 * IBX PCH and CPU are the same for almost everything,
876 * except that the CPU DP PLL is configured in this
877 * register
878 *
879 * CPT PCH is quite different, having many bits moved
880 * to the TRANS_DP_CTL register instead. That
881 * configuration happens (oddly) in ironlake_pch_enable
882 */
9c9e7927 883
417e822d
KP		 884 /* Preserve the BIOS-computed detected bit. This is
885 * supposed to be read-only.
886 */
887 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 888
417e822d 889 /* Handle DP bits in common between all three register formats */
417e822d 890 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 891
ea5b213a 892 switch (intel_dp->lane_count) {
a4fc5ed6 893 case 1:
ea5b213a 894 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 895 break;
896 case 2:
ea5b213a 897 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 898 break;
899 case 4:
ea5b213a 900 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 901 break;
902 }
e0dac65e
WF		 903 if (intel_dp->has_audio) {
904 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
905 pipe_name(intel_crtc->pipe));
ea5b213a 906 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 907 intel_write_eld(encoder, adjusted_mode);
908 }
247d89f6
PZ		 909
910 intel_dp_init_link_config(intel_dp);
a4fc5ed6 911
417e822d 912 /* Split out the IBX/CPU vs CPT settings */
32f9d658 913
19c03924 914 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 915 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
916 intel_dp->DP |= DP_SYNC_HS_HIGH;
917 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
918 intel_dp->DP |= DP_SYNC_VS_HIGH;
919 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
920
921 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
922 intel_dp->DP |= DP_ENHANCED_FRAMING;
923
924 intel_dp->DP |= intel_crtc->pipe << 29;
925
926 /* don't miss out required setting for eDP */
1a2eb460
KP		 927 if (adjusted_mode->clock < 200000)
928 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
929 else
930 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
931 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
b2634017 932 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 933 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 934
935 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
936 intel_dp->DP |= DP_SYNC_HS_HIGH;
937 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
938 intel_dp->DP |= DP_SYNC_VS_HIGH;
939 intel_dp->DP |= DP_LINK_TRAIN_OFF;
940
941 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
942 intel_dp->DP |= DP_ENHANCED_FRAMING;
943
944 if (intel_crtc->pipe == 1)
945 intel_dp->DP |= DP_PIPEB_SELECT;
946
b2634017 947 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
417e822d 948 /* don't miss out required setting for eDP */
417e822d
KP		 949 if (adjusted_mode->clock < 200000)
950 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
951 else
952 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
953 }
954 } else {
955 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 956 }
ea9b6006 957
5d66d5b6 958 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
ea9b6006 959 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
a4fc5ed6
KP		 960}
961
99ea7127
KP		 962#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
963#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
964
965#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
966#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
967
968#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
969#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
970
971static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
972 u32 mask,
973 u32 value)
bd943159 974{
30add22d 975 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 976 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 977 u32 pp_stat_reg, pp_ctrl_reg;
978
979 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
980 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
32ce697c 981
99ea7127 982 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 983 mask, value,
984 I915_READ(pp_stat_reg),
985 I915_READ(pp_ctrl_reg));
32ce697c 986
453c5420 987 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 988 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 989 I915_READ(pp_stat_reg),
990 I915_READ(pp_ctrl_reg));
32ce697c 991 }
99ea7127 992}
32ce697c 993
99ea7127
KP		 994static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
995{
996 DRM_DEBUG_KMS("Wait for panel power on\n");
997 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 998}
999
99ea7127
KP		 1000static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1001{
1002 DRM_DEBUG_KMS("Wait for panel power off time\n");
1003 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1004}
1005
1006static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1007{
1008 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1009 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1010}
1011
1012
832dd3c1
KP		 1013/* Read the current pp_control value, unlocking the register if it
1014 * is locked
1015 */
1016
453c5420 1017static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1018{
453c5420
JB		 1019 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1020 struct drm_i915_private *dev_priv = dev->dev_private;
1021 u32 control;
1022 u32 pp_ctrl_reg;
1023
1024 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1025 control = I915_READ(pp_ctrl_reg);
832dd3c1
KP		 1026
1027 control &= ~PANEL_UNLOCK_MASK;
1028 control |= PANEL_UNLOCK_REGS;
1029 return control;
bd943159
KP		 1030}
1031
82a4d9c0 1032void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1033{
30add22d 1034 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1035 struct drm_i915_private *dev_priv = dev->dev_private;
1036 u32 pp;
453c5420 1037 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1038
97af61f5
KP		 1039 if (!is_edp(intel_dp))
1040 return;
f01eca2e 1041 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1042
bd943159
KP		 1043 WARN(intel_dp->want_panel_vdd,
1044 "eDP VDD already requested on\n");
1045
1046 intel_dp->want_panel_vdd = true;
99ea7127 1047
bd943159
KP		 1048 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1049 DRM_DEBUG_KMS("eDP VDD already on\n");
1050 return;
1051 }
1052
99ea7127
KP		 1053 if (!ironlake_edp_have_panel_power(intel_dp))
1054 ironlake_wait_panel_power_cycle(intel_dp);
1055
453c5420 1056 pp = ironlake_get_pp_control(intel_dp);
5d613501 1057 pp |= EDP_FORCE_VDD;
ebf33b18 1058
453c5420
JB		 1059 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1060 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1061
1062 I915_WRITE(pp_ctrl_reg, pp);
1063 POSTING_READ(pp_ctrl_reg);
1064 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1065 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1066 /*
1067 * If the panel wasn't on, delay before accessing aux channel
1068 */
1069 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1070 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1071 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1072 }
5d613501
JB		 1073}
1074
bd943159 1075static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1076{
30add22d 1077 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1078 struct drm_i915_private *dev_priv = dev->dev_private;
1079 u32 pp;
453c5420 1080 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1081
a0e99e68
DV		 1082 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1083
bd943159 1084 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
453c5420 1085 pp = ironlake_get_pp_control(intel_dp);
bd943159 1086 pp &= ~EDP_FORCE_VDD;
bd943159 1087
453c5420
JB		 1088 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1089 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1090
1091 I915_WRITE(pp_ctrl_reg, pp);
1092 POSTING_READ(pp_ctrl_reg);
99ea7127 1093
453c5420
JB		 1094 /* Make sure sequencer is idle before allowing subsequent activity */
1095 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1096 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1097 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1098 }
1099}
5d613501 1100
bd943159
KP		 1101static void ironlake_panel_vdd_work(struct work_struct *__work)
1102{
1103 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1104 struct intel_dp, panel_vdd_work);
30add22d 1105 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1106
627f7675 1107 mutex_lock(&dev->mode_config.mutex);
bd943159 1108 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1109 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1110}
1111
82a4d9c0 1112void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1113{
97af61f5
KP		 1114 if (!is_edp(intel_dp))
1115 return;
5d613501 1116
bd943159
KP		 1117 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1118 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1119
bd943159
KP		 1120 intel_dp->want_panel_vdd = false;
1121
1122 if (sync) {
1123 ironlake_panel_vdd_off_sync(intel_dp);
1124 } else {
1125 /*
1126 * Queue the timer to fire a long
1127 * time from now (relative to the power down delay)
1128 * to keep the panel power up across a sequence of operations
1129 */
1130 schedule_delayed_work(&intel_dp->panel_vdd_work,
1131 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1132 }
5d613501
JB		 1133}
1134
82a4d9c0 1135void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1136{
30add22d 1137 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1138 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1139 u32 pp;
453c5420 1140 u32 pp_ctrl_reg;
9934c132 1141
97af61f5 1142 if (!is_edp(intel_dp))
bd943159 1143 return;
99ea7127
KP		 1144
1145 DRM_DEBUG_KMS("Turn eDP power on\n");
1146
1147 if (ironlake_edp_have_panel_power(intel_dp)) {
1148 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1149 return;
99ea7127 1150 }
9934c132 1151
99ea7127 1152 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1153
453c5420 1154 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1155 if (IS_GEN5(dev)) {
1156 /* ILK workaround: disable reset around power sequence */
1157 pp &= ~PANEL_POWER_RESET;
1158 I915_WRITE(PCH_PP_CONTROL, pp);
1159 POSTING_READ(PCH_PP_CONTROL);
1160 }
37c6c9b0 1161
1c0ae80a 1162 pp |= POWER_TARGET_ON;
99ea7127
KP		 1163 if (!IS_GEN5(dev))
1164 pp |= PANEL_POWER_RESET;
1165
453c5420
JB		 1166 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1167
1168 I915_WRITE(pp_ctrl_reg, pp);
1169 POSTING_READ(pp_ctrl_reg);
9934c132 1170
99ea7127 1171 ironlake_wait_panel_on(intel_dp);
9934c132 1172
05ce1a49
KP		 1173 if (IS_GEN5(dev)) {
1174 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1175 I915_WRITE(PCH_PP_CONTROL, pp);
1176 POSTING_READ(PCH_PP_CONTROL);
1177 }
9934c132
JB		 1178}
1179
82a4d9c0 1180void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1181{
30add22d 1182 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1183 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1184 u32 pp;
453c5420 1185 u32 pp_ctrl_reg;
9934c132 1186
97af61f5
KP		 1187 if (!is_edp(intel_dp))
1188 return;
37c6c9b0 1189
99ea7127 1190 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1191
6cb49835 1192 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1193
453c5420 1194 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1195 /* We need to switch off panel power _and_ force vdd, for otherwise some
1196 * panels get very unhappy and cease to work. */
1197 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420
JB		 1198
1199 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1200
1201 I915_WRITE(pp_ctrl_reg, pp);
1202 POSTING_READ(pp_ctrl_reg);
9934c132 1203
35a38556
DV		 1204 intel_dp->want_panel_vdd = false;
1205
99ea7127 1206 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1207}
1208
d6c50ff8 1209void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1210{
da63a9f2
PZ		 1211 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1212 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1213 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1214 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658 1215 u32 pp;
453c5420 1216 u32 pp_ctrl_reg;
32f9d658 1217
f01eca2e
KP		 1218 if (!is_edp(intel_dp))
1219 return;
1220
28c97730 1221 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1222 /*
1223 * If we enable the backlight right away following a panel power
1224 * on, we may see slight flicker as the panel syncs with the eDP
1225 * link. So delay a bit to make sure the image is solid before
1226 * allowing it to appear.
1227 */
f01eca2e 1228 msleep(intel_dp->backlight_on_delay);
453c5420 1229 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1230 pp |= EDP_BLC_ENABLE;
453c5420
JB		 1231
1232 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1233
1234 I915_WRITE(pp_ctrl_reg, pp);
1235 POSTING_READ(pp_ctrl_reg);
035aa3de
DV		 1236
1237 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1238}
1239
d6c50ff8 1240void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1241{
30add22d 1242 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1243 struct drm_i915_private *dev_priv = dev->dev_private;
1244 u32 pp;
453c5420 1245 u32 pp_ctrl_reg;
32f9d658 1246
f01eca2e
KP		 1247 if (!is_edp(intel_dp))
1248 return;
1249
035aa3de
DV		 1250 intel_panel_disable_backlight(dev);
1251
28c97730 1252 DRM_DEBUG_KMS("\n");
453c5420 1253 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1254 pp &= ~EDP_BLC_ENABLE;
453c5420
JB		 1255
1256 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1257
1258 I915_WRITE(pp_ctrl_reg, pp);
1259 POSTING_READ(pp_ctrl_reg);
f01eca2e 1260 msleep(intel_dp->backlight_off_delay);
32f9d658 1261}
a4fc5ed6 1262
2bd2ad64 1263static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1264{
da63a9f2
PZ		 1265 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1266 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1267 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1268 struct drm_i915_private *dev_priv = dev->dev_private;
1269 u32 dpa_ctl;
1270
2bd2ad64
DV		 1271 assert_pipe_disabled(dev_priv,
1272 to_intel_crtc(crtc)->pipe);
1273
d240f20f
JB		 1274 DRM_DEBUG_KMS("\n");
1275 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1276 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1277 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1278
1279 /* We don't adjust intel_dp->DP while tearing down the link, to
1280 * facilitate link retraining (e.g. after hotplug). Hence clear all
1281 * enable bits here to ensure that we don't enable too much. */
1282 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1283 intel_dp->DP |= DP_PLL_ENABLE;
1284 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1285 POSTING_READ(DP_A);
1286 udelay(200);
d240f20f
JB		 1287}
1288
2bd2ad64 1289static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1290{
da63a9f2
PZ		 1291 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1292 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1293 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1294 struct drm_i915_private *dev_priv = dev->dev_private;
1295 u32 dpa_ctl;
1296
2bd2ad64
DV		 1297 assert_pipe_disabled(dev_priv,
1298 to_intel_crtc(crtc)->pipe);
1299
d240f20f 1300 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1301 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1302 "dp pll off, should be on\n");
1303 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1304
1305 /* We can't rely on the value tracked for the DP register in
1306 * intel_dp->DP because link_down must not change that (otherwise link
1307 * re-training will fail. */
298b0b39 1308 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1309 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1310 POSTING_READ(DP_A);
d240f20f
JB		 1311 udelay(200);
1312}
1313
c7ad3810 1314/* If the sink supports it, try to set the power state appropriately */
c19b0669 1315void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1316{
1317 int ret, i;
1318
1319 /* Should have a valid DPCD by this point */
1320 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1321 return;
1322
1323 if (mode != DRM_MODE_DPMS_ON) {
1324 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1325 DP_SET_POWER_D3);
1326 if (ret != 1)
1327 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1328 } else {
1329 /*
1330 * When turning on, we need to retry for 1ms to give the sink
1331 * time to wake up.
1332 */
1333 for (i = 0; i < 3; i++) {
1334 ret = intel_dp_aux_native_write_1(intel_dp,
1335 DP_SET_POWER,
1336 DP_SET_POWER_D0);
1337 if (ret == 1)
1338 break;
1339 msleep(1);
1340 }
1341 }
1342}
1343
19d8fe15
DV		 1344static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1345 enum pipe *pipe)
d240f20f 1346{
19d8fe15
DV		 1347 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1348 struct drm_device *dev = encoder->base.dev;
1349 struct drm_i915_private *dev_priv = dev->dev_private;
1350 u32 tmp = I915_READ(intel_dp->output_reg);
1351
1352 if (!(tmp & DP_PORT_EN))
1353 return false;
1354
5d66d5b6 1355 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15
DV		 1356 *pipe = PORT_TO_PIPE_CPT(tmp);
1357 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1358 *pipe = PORT_TO_PIPE(tmp);
1359 } else {
1360 u32 trans_sel;
1361 u32 trans_dp;
1362 int i;
1363
1364 switch (intel_dp->output_reg) {
1365 case PCH_DP_B:
1366 trans_sel = TRANS_DP_PORT_SEL_B;
1367 break;
1368 case PCH_DP_C:
1369 trans_sel = TRANS_DP_PORT_SEL_C;
1370 break;
1371 case PCH_DP_D:
1372 trans_sel = TRANS_DP_PORT_SEL_D;
1373 break;
1374 default:
1375 return true;
1376 }
1377
1378 for_each_pipe(i) {
1379 trans_dp = I915_READ(TRANS_DP_CTL(i));
1380 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1381 *pipe = i;
1382 return true;
1383 }
1384 }
19d8fe15 1385
4a0833ec
DV		 1386 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1387 intel_dp->output_reg);
1388 }
d240f20f 1389
2af8898b 1390 return true;
19d8fe15 1391}
d240f20f 1392
e8cb4558 1393static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1394{
e8cb4558 1395 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1396
1397 /* Make sure the panel is off before trying to change the mode. But also
1398 * ensure that we have vdd while we switch off the panel. */
1399 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1400 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1401 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1402 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1403
1404 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1405 if (!is_cpu_edp(intel_dp))
1406 intel_dp_link_down(intel_dp);
d240f20f
JB		 1407}
1408
2bd2ad64 1409static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1410{
2bd2ad64 1411 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
b2634017 1412 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1413
3739850b
DV		 1414 if (is_cpu_edp(intel_dp)) {
1415 intel_dp_link_down(intel_dp);
b2634017
JB		 1416 if (!IS_VALLEYVIEW(dev))
1417 ironlake_edp_pll_off(intel_dp);
3739850b 1418 }
2bd2ad64
DV		 1419}
1420
e8cb4558 1421static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1422{
e8cb4558
DV		 1423 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1424 struct drm_device *dev = encoder->base.dev;
1425 struct drm_i915_private *dev_priv = dev->dev_private;
1426 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1427
0c33d8d7
DV		 1428 if (WARN_ON(dp_reg & DP_PORT_EN))
1429 return;
5d613501 1430
97af61f5 1431 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1432 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1433 intel_dp_start_link_train(intel_dp);
97af61f5 1434 ironlake_edp_panel_on(intel_dp);
bd943159 1435 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1436 intel_dp_complete_link_train(intel_dp);
f01eca2e 1437 ironlake_edp_backlight_on(intel_dp);
89b667f8
JB		 1438
1439 if (IS_VALLEYVIEW(dev)) {
1440 struct intel_digital_port *dport =
1441 enc_to_dig_port(&encoder->base);
1442 int channel = vlv_dport_to_channel(dport);
1443
1444 vlv_wait_port_ready(dev_priv, channel);
1445 }
d240f20f
JB		 1446}
1447
2bd2ad64 1448static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1449{
2bd2ad64 1450 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
b2634017 1451 struct drm_device *dev = encoder->base.dev;
89b667f8 1452 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6 1453
b2634017 1454 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
2bd2ad64 1455 ironlake_edp_pll_on(intel_dp);
89b667f8
JB		 1456
1457 if (IS_VALLEYVIEW(dev)) {
1458 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1459 struct intel_crtc *intel_crtc =
1460 to_intel_crtc(encoder->base.crtc);
1461 int port = vlv_dport_to_channel(dport);
1462 int pipe = intel_crtc->pipe;
1463 u32 val;
1464
1465 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1466
1467 val = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1468 val = 0;
1469 if (pipe)
1470 val |= (1<<21);
1471 else
1472 val &= ~(1<<21);
1473 val |= 0x001000c4;
1474 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1475
1476 intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1477 0x00760018);
1478 intel_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1479 0x00400888);
1480 }
1481}
1482
1483static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1484{
1485 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1486 struct drm_device *dev = encoder->base.dev;
1487 struct drm_i915_private *dev_priv = dev->dev_private;
1488 int port = vlv_dport_to_channel(dport);
1489
1490 if (!IS_VALLEYVIEW(dev))
1491 return;
1492
1493 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1494
1495 /* Program Tx lane resets to default */
1496 intel_dpio_write(dev_priv, DPIO_PCS_TX(port),
1497 DPIO_PCS_TX_LANE2_RESET |
1498 DPIO_PCS_TX_LANE1_RESET);
1499 intel_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1500 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1501 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1502 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1503 DPIO_PCS_CLK_SOFT_RESET);
1504
1505 /* Fix up inter-pair skew failure */
1506 intel_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1507 intel_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1508 intel_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
a4fc5ed6
KP		 1509}
1510
1511/*
df0c237d
JB		 1512 * Native read with retry for link status and receiver capability reads for
1513 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1514 */
1515static bool
df0c237d
JB		 1516intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1517 uint8_t *recv, int recv_bytes)
a4fc5ed6 1518{
61da5fab
JB		 1519 int ret, i;
1520
df0c237d
JB		 1521 /*
1522 * Sinks are *supposed* to come up within 1ms from an off state,
1523 * but we're also supposed to retry 3 times per the spec.
1524 */
61da5fab 1525 for (i = 0; i < 3; i++) {
df0c237d
JB		 1526 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1527 recv_bytes);
1528 if (ret == recv_bytes)
61da5fab
JB		 1529 return true;
1530 msleep(1);
1531 }
a4fc5ed6 1532
61da5fab 1533 return false;
a4fc5ed6
KP		 1534}
1535
1536/*
1537 * Fetch AUX CH registers 0x202 - 0x207 which contain
1538 * link status information
1539 */
1540static bool
93f62dad 1541intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1542{
df0c237d
JB		 1543 return intel_dp_aux_native_read_retry(intel_dp,
1544 DP_LANE0_1_STATUS,
93f62dad 1545 link_status,
df0c237d 1546 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1547}
1548
a4fc5ed6
KP		 1549#if 0
1550static char *voltage_names[] = {
1551 "0.4V", "0.6V", "0.8V", "1.2V"
1552};
1553static char *pre_emph_names[] = {
1554 "0dB", "3.5dB", "6dB", "9.5dB"
1555};
1556static char *link_train_names[] = {
1557 "pattern 1", "pattern 2", "idle", "off"
1558};
1559#endif
1560
1561/*
1562 * These are source-specific values; current Intel hardware supports
1563 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1564 */
a4fc5ed6
KP		 1565
1566static uint8_t
1a2eb460 1567intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1568{
30add22d 1569 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1570
e2fa6fba
P		 1571 if (IS_VALLEYVIEW(dev))
1572 return DP_TRAIN_VOLTAGE_SWING_1200;
1573 else if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1a2eb460
KP		 1574 return DP_TRAIN_VOLTAGE_SWING_800;
1575 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1576 return DP_TRAIN_VOLTAGE_SWING_1200;
1577 else
1578 return DP_TRAIN_VOLTAGE_SWING_800;
1579}
1580
1581static uint8_t
1582intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1583{
30add22d 1584 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1585
22b8bf17 1586 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1587 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1588 case DP_TRAIN_VOLTAGE_SWING_400:
1589 return DP_TRAIN_PRE_EMPHASIS_9_5;
1590 case DP_TRAIN_VOLTAGE_SWING_600:
1591 return DP_TRAIN_PRE_EMPHASIS_6;
1592 case DP_TRAIN_VOLTAGE_SWING_800:
1593 return DP_TRAIN_PRE_EMPHASIS_3_5;
1594 case DP_TRAIN_VOLTAGE_SWING_1200:
1595 default:
1596 return DP_TRAIN_PRE_EMPHASIS_0;
1597 }
e2fa6fba
P		 1598 } else if (IS_VALLEYVIEW(dev)) {
1599 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1600 case DP_TRAIN_VOLTAGE_SWING_400:
1601 return DP_TRAIN_PRE_EMPHASIS_9_5;
1602 case DP_TRAIN_VOLTAGE_SWING_600:
1603 return DP_TRAIN_PRE_EMPHASIS_6;
1604 case DP_TRAIN_VOLTAGE_SWING_800:
1605 return DP_TRAIN_PRE_EMPHASIS_3_5;
1606 case DP_TRAIN_VOLTAGE_SWING_1200:
1607 default:
1608 return DP_TRAIN_PRE_EMPHASIS_0;
1609 }
1610 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1a2eb460
KP		 1611 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1612 case DP_TRAIN_VOLTAGE_SWING_400:
1613 return DP_TRAIN_PRE_EMPHASIS_6;
1614 case DP_TRAIN_VOLTAGE_SWING_600:
1615 case DP_TRAIN_VOLTAGE_SWING_800:
1616 return DP_TRAIN_PRE_EMPHASIS_3_5;
1617 default:
1618 return DP_TRAIN_PRE_EMPHASIS_0;
1619 }
1620 } else {
1621 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1622 case DP_TRAIN_VOLTAGE_SWING_400:
1623 return DP_TRAIN_PRE_EMPHASIS_6;
1624 case DP_TRAIN_VOLTAGE_SWING_600:
1625 return DP_TRAIN_PRE_EMPHASIS_6;
1626 case DP_TRAIN_VOLTAGE_SWING_800:
1627 return DP_TRAIN_PRE_EMPHASIS_3_5;
1628 case DP_TRAIN_VOLTAGE_SWING_1200:
1629 default:
1630 return DP_TRAIN_PRE_EMPHASIS_0;
1631 }
a4fc5ed6
KP		 1632 }
1633}
1634
e2fa6fba
P		 1635static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1636{
1637 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1638 struct drm_i915_private *dev_priv = dev->dev_private;
1639 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1640 unsigned long demph_reg_value, preemph_reg_value,
1641 uniqtranscale_reg_value;
1642 uint8_t train_set = intel_dp->train_set[0];
cece5d58 1643 int port = vlv_dport_to_channel(dport);
e2fa6fba 1644
89b667f8
JB		 1645 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1646
e2fa6fba
P		 1647 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1648 case DP_TRAIN_PRE_EMPHASIS_0:
1649 preemph_reg_value = 0x0004000;
1650 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1651 case DP_TRAIN_VOLTAGE_SWING_400:
1652 demph_reg_value = 0x2B405555;
1653 uniqtranscale_reg_value = 0x552AB83A;
1654 break;
1655 case DP_TRAIN_VOLTAGE_SWING_600:
1656 demph_reg_value = 0x2B404040;
1657 uniqtranscale_reg_value = 0x5548B83A;
1658 break;
1659 case DP_TRAIN_VOLTAGE_SWING_800:
1660 demph_reg_value = 0x2B245555;
1661 uniqtranscale_reg_value = 0x5560B83A;
1662 break;
1663 case DP_TRAIN_VOLTAGE_SWING_1200:
1664 demph_reg_value = 0x2B405555;
1665 uniqtranscale_reg_value = 0x5598DA3A;
1666 break;
1667 default:
1668 return 0;
1669 }
1670 break;
1671 case DP_TRAIN_PRE_EMPHASIS_3_5:
1672 preemph_reg_value = 0x0002000;
1673 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1674 case DP_TRAIN_VOLTAGE_SWING_400:
1675 demph_reg_value = 0x2B404040;
1676 uniqtranscale_reg_value = 0x5552B83A;
1677 break;
1678 case DP_TRAIN_VOLTAGE_SWING_600:
1679 demph_reg_value = 0x2B404848;
1680 uniqtranscale_reg_value = 0x5580B83A;
1681 break;
1682 case DP_TRAIN_VOLTAGE_SWING_800:
1683 demph_reg_value = 0x2B404040;
1684 uniqtranscale_reg_value = 0x55ADDA3A;
1685 break;
1686 default:
1687 return 0;
1688 }
1689 break;
1690 case DP_TRAIN_PRE_EMPHASIS_6:
1691 preemph_reg_value = 0x0000000;
1692 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1693 case DP_TRAIN_VOLTAGE_SWING_400:
1694 demph_reg_value = 0x2B305555;
1695 uniqtranscale_reg_value = 0x5570B83A;
1696 break;
1697 case DP_TRAIN_VOLTAGE_SWING_600:
1698 demph_reg_value = 0x2B2B4040;
1699 uniqtranscale_reg_value = 0x55ADDA3A;
1700 break;
1701 default:
1702 return 0;
1703 }
1704 break;
1705 case DP_TRAIN_PRE_EMPHASIS_9_5:
1706 preemph_reg_value = 0x0006000;
1707 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1708 case DP_TRAIN_VOLTAGE_SWING_400:
1709 demph_reg_value = 0x1B405555;
1710 uniqtranscale_reg_value = 0x55ADDA3A;
1711 break;
1712 default:
1713 return 0;
1714 }
1715 break;
1716 default:
1717 return 0;
1718 }
1719
e2fa6fba
P		 1720 intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1721 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1722 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1723 uniqtranscale_reg_value);
1724 intel_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1725 intel_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1726 intel_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1727 intel_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
e2fa6fba
P		 1728
1729 return 0;
1730}
1731
a4fc5ed6 1732static void
93f62dad 1733intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1734{
1735 uint8_t v = 0;
1736 uint8_t p = 0;
1737 int lane;
1a2eb460
KP		 1738 uint8_t voltage_max;
1739 uint8_t preemph_max;
a4fc5ed6 1740
33a34e4e 1741 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1742 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1743 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1744
1745 if (this_v > v)
1746 v = this_v;
1747 if (this_p > p)
1748 p = this_p;
1749 }
1750
1a2eb460 1751 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1752 if (v >= voltage_max)
1753 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1754
1a2eb460
KP		 1755 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1756 if (p >= preemph_max)
1757 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1758
1759 for (lane = 0; lane < 4; lane++)
33a34e4e 1760 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1761}
1762
1763static uint32_t
f0a3424e 1764intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 1765{
3cf2efb1 1766 uint32_t signal_levels = 0;
a4fc5ed6 1767
3cf2efb1 1768 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1769 case DP_TRAIN_VOLTAGE_SWING_400:
1770 default:
1771 signal_levels |= DP_VOLTAGE_0_4;
1772 break;
1773 case DP_TRAIN_VOLTAGE_SWING_600:
1774 signal_levels |= DP_VOLTAGE_0_6;
1775 break;
1776 case DP_TRAIN_VOLTAGE_SWING_800:
1777 signal_levels |= DP_VOLTAGE_0_8;
1778 break;
1779 case DP_TRAIN_VOLTAGE_SWING_1200:
1780 signal_levels |= DP_VOLTAGE_1_2;
1781 break;
1782 }
3cf2efb1 1783 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1784 case DP_TRAIN_PRE_EMPHASIS_0:
1785 default:
1786 signal_levels |= DP_PRE_EMPHASIS_0;
1787 break;
1788 case DP_TRAIN_PRE_EMPHASIS_3_5:
1789 signal_levels |= DP_PRE_EMPHASIS_3_5;
1790 break;
1791 case DP_TRAIN_PRE_EMPHASIS_6:
1792 signal_levels |= DP_PRE_EMPHASIS_6;
1793 break;
1794 case DP_TRAIN_PRE_EMPHASIS_9_5:
1795 signal_levels |= DP_PRE_EMPHASIS_9_5;
1796 break;
1797 }
1798 return signal_levels;
1799}
1800
e3421a18
ZW		 1801/* Gen6's DP voltage swing and pre-emphasis control */
1802static uint32_t
1803intel_gen6_edp_signal_levels(uint8_t train_set)
1804{
3c5a62b5
YL		 1805 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1806 DP_TRAIN_PRE_EMPHASIS_MASK);
1807 switch (signal_levels) {
e3421a18 1808 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1809 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1810 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1811 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1812 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1813 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1814 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1815 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1816 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1817 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1818 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1819 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1820 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1821 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1822 default:
3c5a62b5
YL		 1823 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1824 "0x%x\n", signal_levels);
1825 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1826 }
1827}
1828
1a2eb460
KP		 1829/* Gen7's DP voltage swing and pre-emphasis control */
1830static uint32_t
1831intel_gen7_edp_signal_levels(uint8_t train_set)
1832{
1833 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1834 DP_TRAIN_PRE_EMPHASIS_MASK);
1835 switch (signal_levels) {
1836 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1837 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1838 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1839 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1840 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1841 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1842
1843 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1844 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1845 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1846 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1847
1848 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1849 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1850 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1851 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1852
1853 default:
1854 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1855 "0x%x\n", signal_levels);
1856 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1857 }
1858}
1859
d6c0d722
PZ		 1860/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1861static uint32_t
f0a3424e 1862intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 1863{
d6c0d722
PZ		 1864 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1865 DP_TRAIN_PRE_EMPHASIS_MASK);
1866 switch (signal_levels) {
1867 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1868 return DDI_BUF_EMP_400MV_0DB_HSW;
1869 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1870 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1871 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1872 return DDI_BUF_EMP_400MV_6DB_HSW;
1873 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1874 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 1875
d6c0d722
PZ		 1876 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1877 return DDI_BUF_EMP_600MV_0DB_HSW;
1878 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1879 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1880 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1881 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 1882
d6c0d722
PZ		 1883 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1884 return DDI_BUF_EMP_800MV_0DB_HSW;
1885 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1886 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1887 default:
1888 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1889 "0x%x\n", signal_levels);
1890 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 1891 }
a4fc5ed6
KP		 1892}
1893
f0a3424e
PZ		 1894/* Properly updates "DP" with the correct signal levels. */
1895static void
1896intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1897{
1898 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1899 struct drm_device *dev = intel_dig_port->base.base.dev;
1900 uint32_t signal_levels, mask;
1901 uint8_t train_set = intel_dp->train_set[0];
1902
22b8bf17 1903 if (HAS_DDI(dev)) {
f0a3424e
PZ		 1904 signal_levels = intel_hsw_signal_levels(train_set);
1905 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 1906 } else if (IS_VALLEYVIEW(dev)) {
1907 signal_levels = intel_vlv_signal_levels(intel_dp);
1908 mask = 0;
1909 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
f0a3424e
PZ		 1910 signal_levels = intel_gen7_edp_signal_levels(train_set);
1911 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1912 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1913 signal_levels = intel_gen6_edp_signal_levels(train_set);
1914 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1915 } else {
1916 signal_levels = intel_gen4_signal_levels(train_set);
1917 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1918 }
1919
1920 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1921
1922 *DP = (*DP & ~mask) | signal_levels;
1923}
1924
a4fc5ed6 1925static bool
ea5b213a 1926intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1927 uint32_t dp_reg_value,
58e10eb9 1928 uint8_t dp_train_pat)
a4fc5ed6 1929{
174edf1f
PZ		 1930 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1931 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1932 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 1933 enum port port = intel_dig_port->port;
a4fc5ed6 1934 int ret;
d6c0d722 1935 uint32_t temp;
a4fc5ed6 1936
22b8bf17 1937 if (HAS_DDI(dev)) {
174edf1f 1938 temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 1939
1940 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1941 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1942 else
1943 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1944
1945 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1946 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1947 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722 1948
10aa17c8
PZ		 1949 if (port != PORT_A) {
1950 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1951 I915_WRITE(DP_TP_CTL(port), temp);
1952
1953 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1954 DP_TP_STATUS_IDLE_DONE), 1))
1955 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1956
1957 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1958 }
d6c0d722 1959
d6c0d722
PZ		 1960 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1961
1962 break;
1963 case DP_TRAINING_PATTERN_1:
1964 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1965 break;
1966 case DP_TRAINING_PATTERN_2:
1967 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1968 break;
1969 case DP_TRAINING_PATTERN_3:
1970 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1971 break;
1972 }
174edf1f 1973 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722
PZ		 1974
1975 } else if (HAS_PCH_CPT(dev) &&
1976 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1977 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1978
1979 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1980 case DP_TRAINING_PATTERN_DISABLE:
1981 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1982 break;
1983 case DP_TRAINING_PATTERN_1:
1984 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1985 break;
1986 case DP_TRAINING_PATTERN_2:
1987 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1988 break;
1989 case DP_TRAINING_PATTERN_3:
1990 DRM_ERROR("DP training pattern 3 not supported\n");
1991 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1992 break;
1993 }
1994
1995 } else {
1996 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1997
1998 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1999 case DP_TRAINING_PATTERN_DISABLE:
2000 dp_reg_value |= DP_LINK_TRAIN_OFF;
2001 break;
2002 case DP_TRAINING_PATTERN_1:
2003 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
2004 break;
2005 case DP_TRAINING_PATTERN_2:
2006 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2007 break;
2008 case DP_TRAINING_PATTERN_3:
2009 DRM_ERROR("DP training pattern 3 not supported\n");
2010 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2011 break;
2012 }
2013 }
2014
ea5b213a
CW		 2015 I915_WRITE(intel_dp->output_reg, dp_reg_value);
2016 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2017
ea5b213a 2018 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 2019 DP_TRAINING_PATTERN_SET,
2020 dp_train_pat);
2021
47ea7542
PZ		 2022 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2023 DP_TRAINING_PATTERN_DISABLE) {
2024 ret = intel_dp_aux_native_write(intel_dp,
2025 DP_TRAINING_LANE0_SET,
2026 intel_dp->train_set,
2027 intel_dp->lane_count);
2028 if (ret != intel_dp->lane_count)
2029 return false;
2030 }
a4fc5ed6
KP		 2031
2032 return true;
2033}
2034
33a34e4e 2035/* Enable corresponding port and start training pattern 1 */
c19b0669 2036void
33a34e4e 2037intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2038{
da63a9f2 2039 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2040 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2041 int i;
2042 uint8_t voltage;
2043 bool clock_recovery = false;
cdb0e95b 2044 int voltage_tries, loop_tries;
ea5b213a 2045 uint32_t DP = intel_dp->DP;
a4fc5ed6 2046
affa9354 2047 if (HAS_DDI(dev))
c19b0669
PZ		 2048 intel_ddi_prepare_link_retrain(encoder);
2049
3cf2efb1
CW		 2050 /* Write the link configuration data */
2051 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2052 intel_dp->link_configuration,
2053 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 2054
2055 DP |= DP_PORT_EN;
1a2eb460 2056
33a34e4e 2057 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 2058 voltage = 0xff;
cdb0e95b
KP		 2059 voltage_tries = 0;
2060 loop_tries = 0;
a4fc5ed6
KP		 2061 clock_recovery = false;
2062 for (;;) {
33a34e4e 2063 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 2064 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 2065
2066 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 2067
a7c9655f 2068 /* Set training pattern 1 */
47ea7542 2069 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2070 DP_TRAINING_PATTERN_1 |
2071 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 2072 break;
a4fc5ed6 2073
a7c9655f 2074 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2075 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2076 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2077 break;
93f62dad 2078 }
a4fc5ed6 2079
01916270 2080 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2081 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2082 clock_recovery = true;
2083 break;
2084 }
2085
2086 /* Check to see if we've tried the max voltage */
2087 for (i = 0; i < intel_dp->lane_count; i++)
2088 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2089 break;
3b4f819d 2090 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2091 ++loop_tries;
2092 if (loop_tries == 5) {
cdb0e95b
KP		 2093 DRM_DEBUG_KMS("too many full retries, give up\n");
2094 break;
2095 }
2096 memset(intel_dp->train_set, 0, 4);
2097 voltage_tries = 0;
2098 continue;
2099 }
a4fc5ed6 2100
3cf2efb1 2101 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2102 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2103 ++voltage_tries;
b06fbda3
DV		 2104 if (voltage_tries == 5) {
2105 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2106 break;
2107 }
2108 } else
2109 voltage_tries = 0;
2110 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2111
3cf2efb1 2112 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2113 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 2114 }
2115
33a34e4e
JB		 2116 intel_dp->DP = DP;
2117}
2118
c19b0669 2119void
33a34e4e
JB		 2120intel_dp_complete_link_train(struct intel_dp *intel_dp)
2121{
33a34e4e 2122 bool channel_eq = false;
37f80975 2123 int tries, cr_tries;
33a34e4e
JB		 2124 uint32_t DP = intel_dp->DP;
2125
a4fc5ed6
KP		 2126 /* channel equalization */
2127 tries = 0;
37f80975 2128 cr_tries = 0;
a4fc5ed6
KP		 2129 channel_eq = false;
2130 for (;;) {
93f62dad 2131 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2132
37f80975
JB		 2133 if (cr_tries > 5) {
2134 DRM_ERROR("failed to train DP, aborting\n");
2135 intel_dp_link_down(intel_dp);
2136 break;
2137 }
2138
f0a3424e 2139 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 2140
a4fc5ed6 2141 /* channel eq pattern */
47ea7542 2142 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2143 DP_TRAINING_PATTERN_2 |
2144 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 2145 break;
2146
a7c9655f 2147 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 2148 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 2149 break;
a4fc5ed6 2150
37f80975 2151 /* Make sure clock is still ok */
01916270 2152 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 2153 intel_dp_start_link_train(intel_dp);
2154 cr_tries++;
2155 continue;
2156 }
2157
1ffdff13 2158 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2159 channel_eq = true;
2160 break;
2161 }
a4fc5ed6 2162
37f80975
JB		 2163 /* Try 5 times, then try clock recovery if that fails */
2164 if (tries > 5) {
2165 intel_dp_link_down(intel_dp);
2166 intel_dp_start_link_train(intel_dp);
2167 tries = 0;
2168 cr_tries++;
2169 continue;
2170 }
a4fc5ed6 2171
3cf2efb1 2172 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2173 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2174 ++tries;
869184a6 2175 }
3cf2efb1 2176
d6c0d722
PZ		 2177 if (channel_eq)
2178 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2179
47ea7542 2180 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2181}
2182
2183static void
ea5b213a 2184intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2185{
da63a9f2
PZ		 2186 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2187 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2188 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2189 struct intel_crtc *intel_crtc =
2190 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2191 uint32_t DP = intel_dp->DP;
a4fc5ed6 2192
c19b0669
PZ		 2193 /*
2194 * DDI code has a strict mode set sequence and we should try to respect
2195 * it, otherwise we might hang the machine in many different ways. So we
2196 * really should be disabling the port only on a complete crtc_disable
2197 * sequence. This function is just called under two conditions on DDI
2198 * code:
2199 * - Link train failed while doing crtc_enable, and on this case we
2200 * really should respect the mode set sequence and wait for a
2201 * crtc_disable.
2202 * - Someone turned the monitor off and intel_dp_check_link_status
2203 * called us. We don't need to disable the whole port on this case, so
2204 * when someone turns the monitor on again,
2205 * intel_ddi_prepare_link_retrain will take care of redoing the link
2206 * train.
2207 */
affa9354 2208 if (HAS_DDI(dev))
c19b0669
PZ		 2209 return;
2210
0c33d8d7 2211 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2212 return;
2213
28c97730 2214 DRM_DEBUG_KMS("\n");
32f9d658 2215
1a2eb460 2216 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 2217 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2218 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2219 } else {
2220 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2221 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2222 }
fe255d00 2223 POSTING_READ(intel_dp->output_reg);
5eb08b69 2224
ab527efc
DV		 2225 /* We don't really know why we're doing this */
2226 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2227
493a7081 2228 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2229 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2230 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2231
5bddd17f
EA		 2232 /* Hardware workaround: leaving our transcoder select
2233 * set to transcoder B while it's off will prevent the
2234 * corresponding HDMI output on transcoder A.
2235 *
2236 * Combine this with another hardware workaround:
2237 * transcoder select bit can only be cleared while the
2238 * port is enabled.
2239 */
2240 DP &= ~DP_PIPEB_SELECT;
2241 I915_WRITE(intel_dp->output_reg, DP);
2242
2243 /* Changes to enable or select take place the vblank
2244 * after being written.
2245 */
ff50afe9
DV		 2246 if (WARN_ON(crtc == NULL)) {
2247 /* We should never try to disable a port without a crtc
2248 * attached. For paranoia keep the code around for a
2249 * bit. */
31acbcc4
CW		 2250 POSTING_READ(intel_dp->output_reg);
2251 msleep(50);
2252 } else
ab527efc 2253 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2254 }
2255
832afda6 2256 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2257 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2258 POSTING_READ(intel_dp->output_reg);
f01eca2e 2259 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2260}
2261
26d61aad
KP		 2262static bool
2263intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2264{
577c7a50
DL		 2265 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2266
92fd8fd1 2267 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2268 sizeof(intel_dp->dpcd)) == 0)
2269 return false; /* aux transfer failed */
92fd8fd1 2270
577c7a50
DL		 2271 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2272 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2273 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2274
edb39244
AJ		 2275 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2276 return false; /* DPCD not present */
2277
2278 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2279 DP_DWN_STRM_PORT_PRESENT))
2280 return true; /* native DP sink */
2281
2282 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2283 return true; /* no per-port downstream info */
2284
2285 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2286 intel_dp->downstream_ports,
2287 DP_MAX_DOWNSTREAM_PORTS) == 0)
2288 return false; /* downstream port status fetch failed */
2289
2290 return true;
92fd8fd1
KP		 2291}
2292
0d198328
AJ		 2293static void
2294intel_dp_probe_oui(struct intel_dp *intel_dp)
2295{
2296 u8 buf[3];
2297
2298 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2299 return;
2300
351cfc34
DV		 2301 ironlake_edp_panel_vdd_on(intel_dp);
2302
0d198328
AJ		 2303 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2304 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2305 buf[0], buf[1], buf[2]);
2306
2307 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2308 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2309 buf[0], buf[1], buf[2]);
351cfc34
DV		 2310
2311 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2312}
2313
a60f0e38
JB		 2314static bool
2315intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2316{
2317 int ret;
2318
2319 ret = intel_dp_aux_native_read_retry(intel_dp,
2320 DP_DEVICE_SERVICE_IRQ_VECTOR,
2321 sink_irq_vector, 1);
2322 if (!ret)
2323 return false;
2324
2325 return true;
2326}
2327
2328static void
2329intel_dp_handle_test_request(struct intel_dp *intel_dp)
2330{
2331 /* NAK by default */
9324cf7f 2332 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2333}
2334
a4fc5ed6
KP		 2335/*
2336 * According to DP spec
2337 * 5.1.2:
2338 * 1. Read DPCD
2339 * 2. Configure link according to Receiver Capabilities
2340 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2341 * 4. Check link status on receipt of hot-plug interrupt
2342 */
2343
00c09d70 2344void
ea5b213a 2345intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2346{
da63a9f2 2347 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2348 u8 sink_irq_vector;
93f62dad 2349 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2350
da63a9f2 2351 if (!intel_encoder->connectors_active)
d2b996ac 2352 return;
59cd09e1 2353
da63a9f2 2354 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2355 return;
2356
92fd8fd1 2357 /* Try to read receiver status if the link appears to be up */
93f62dad 2358 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2359 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2360 return;
2361 }
2362
92fd8fd1 2363 /* Now read the DPCD to see if it's actually running */
26d61aad 2364 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2365 intel_dp_link_down(intel_dp);
2366 return;
2367 }
2368
a60f0e38
JB		 2369 /* Try to read the source of the interrupt */
2370 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2371 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2372 /* Clear interrupt source */
2373 intel_dp_aux_native_write_1(intel_dp,
2374 DP_DEVICE_SERVICE_IRQ_VECTOR,
2375 sink_irq_vector);
2376
2377 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2378 intel_dp_handle_test_request(intel_dp);
2379 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2380 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2381 }
2382
1ffdff13 2383 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2384 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2385 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2386 intel_dp_start_link_train(intel_dp);
2387 intel_dp_complete_link_train(intel_dp);
2388 }
a4fc5ed6 2389}
a4fc5ed6 2390
caf9ab24 2391/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2392static enum drm_connector_status
26d61aad 2393intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2394{
caf9ab24
AJ		 2395 uint8_t *dpcd = intel_dp->dpcd;
2396 bool hpd;
2397 uint8_t type;
2398
2399 if (!intel_dp_get_dpcd(intel_dp))
2400 return connector_status_disconnected;
2401
2402 /* if there's no downstream port, we're done */
2403 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2404 return connector_status_connected;
caf9ab24
AJ		 2405
2406 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2407 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2408 if (hpd) {
23235177 2409 uint8_t reg;
caf9ab24 2410 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2411 &reg, 1))
caf9ab24 2412 return connector_status_unknown;
23235177
AJ		 2413 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2414 : connector_status_disconnected;
caf9ab24
AJ		 2415 }
2416
2417 /* If no HPD, poke DDC gently */
2418 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2419 return connector_status_connected;
caf9ab24
AJ		 2420
2421 /* Well we tried, say unknown for unreliable port types */
2422 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2423 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2424 return connector_status_unknown;
2425
2426 /* Anything else is out of spec, warn and ignore */
2427 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2428 return connector_status_disconnected;
71ba9000
AJ		 2429}
2430
5eb08b69 2431static enum drm_connector_status
a9756bb5 2432ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2433{
30add22d 2434 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2435 struct drm_i915_private *dev_priv = dev->dev_private;
2436 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2437 enum drm_connector_status status;
2438
fe16d949
CW		 2439 /* Can't disconnect eDP, but you can close the lid... */
2440 if (is_edp(intel_dp)) {
30add22d 2441 status = intel_panel_detect(dev);
fe16d949
CW		 2442 if (status == connector_status_unknown)
2443 status = connector_status_connected;
2444 return status;
2445 }
01cb9ea6 2446
1b469639
DL		 2447 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2448 return connector_status_disconnected;
2449
26d61aad 2450 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2451}
2452
a4fc5ed6 2453static enum drm_connector_status
a9756bb5 2454g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2455{
30add22d 2456 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2457 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2458 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2459 uint32_t bit;
5eb08b69 2460
35aad75f
JB		 2461 /* Can't disconnect eDP, but you can close the lid... */
2462 if (is_edp(intel_dp)) {
2463 enum drm_connector_status status;
2464
2465 status = intel_panel_detect(dev);
2466 if (status == connector_status_unknown)
2467 status = connector_status_connected;
2468 return status;
2469 }
2470
34f2be46
VS		 2471 switch (intel_dig_port->port) {
2472 case PORT_B:
26739f12 2473 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2474 break;
34f2be46 2475 case PORT_C:
26739f12 2476 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2477 break;
34f2be46 2478 case PORT_D:
26739f12 2479 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2480 break;
2481 default:
2482 return connector_status_unknown;
2483 }
2484
10f76a38 2485 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2486 return connector_status_disconnected;
2487
26d61aad 2488 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2489}
2490
8c241fef
KP		 2491static struct edid *
2492intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2493{
9cd300e0 2494 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2495
9cd300e0
JN		 2496 /* use cached edid if we have one */
2497 if (intel_connector->edid) {
2498 struct edid *edid;
2499 int size;
2500
2501 /* invalid edid */
2502 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2503 return NULL;
2504
9cd300e0 2505 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
d6f24d0f
JB		 2506 edid = kmalloc(size, GFP_KERNEL);
2507 if (!edid)
2508 return NULL;
2509
9cd300e0 2510 memcpy(edid, intel_connector->edid, size);
d6f24d0f
JB		 2511 return edid;
2512 }
8c241fef 2513
9cd300e0 2514 return drm_get_edid(connector, adapter);
8c241fef
KP		 2515}
2516
2517static int
2518intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2519{
9cd300e0 2520 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2521
9cd300e0
JN		 2522 /* use cached edid if we have one */
2523 if (intel_connector->edid) {
2524 /* invalid edid */
2525 if (IS_ERR(intel_connector->edid))
2526 return 0;
2527
2528 return intel_connector_update_modes(connector,
2529 intel_connector->edid);
d6f24d0f
JB		 2530 }
2531
9cd300e0 2532 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2533}
2534
a9756bb5
ZW		 2535static enum drm_connector_status
2536intel_dp_detect(struct drm_connector *connector, bool force)
2537{
2538 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2539 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2540 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2541 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2542 enum drm_connector_status status;
2543 struct edid *edid = NULL;
2544
2545 intel_dp->has_audio = false;
2546
2547 if (HAS_PCH_SPLIT(dev))
2548 status = ironlake_dp_detect(intel_dp);
2549 else
2550 status = g4x_dp_detect(intel_dp);
1b9be9d0 2551
a9756bb5
ZW		 2552 if (status != connector_status_connected)
2553 return status;
2554
0d198328
AJ		 2555 intel_dp_probe_oui(intel_dp);
2556
c3e5f67b
DV		 2557 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2558 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2559 } else {
8c241fef 2560 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2561 if (edid) {
2562 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2563 kfree(edid);
2564 }
a9756bb5
ZW		 2565 }
2566
d63885da
PZ		 2567 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2568 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2569 return connector_status_connected;
a4fc5ed6
KP		 2570}
2571
2572static int intel_dp_get_modes(struct drm_connector *connector)
2573{
df0e9248 2574 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2575 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2576 struct drm_device *dev = connector->dev;
32f9d658 2577 int ret;
a4fc5ed6
KP		 2578
2579 /* We should parse the EDID data and find out if it has an audio sink
2580 */
2581
8c241fef 2582 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2583 if (ret)
32f9d658
ZW		 2584 return ret;
2585
f8779fda 2586 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2587 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2588 struct drm_display_mode *mode;
dd06f90e
JN		 2589 mode = drm_mode_duplicate(dev,
2590 intel_connector->panel.fixed_mode);
f8779fda 2591 if (mode) {
32f9d658
ZW		 2592 drm_mode_probed_add(connector, mode);
2593 return 1;
2594 }
2595 }
2596 return 0;
a4fc5ed6
KP		 2597}
2598
1aad7ac0
CW		 2599static bool
2600intel_dp_detect_audio(struct drm_connector *connector)
2601{
2602 struct intel_dp *intel_dp = intel_attached_dp(connector);
2603 struct edid *edid;
2604 bool has_audio = false;
2605
8c241fef 2606 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2607 if (edid) {
2608 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2609 kfree(edid);
2610 }
2611
2612 return has_audio;
2613}
2614
f684960e
CW		 2615static int
2616intel_dp_set_property(struct drm_connector *connector,
2617 struct drm_property *property,
2618 uint64_t val)
2619{
e953fd7b 2620 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2621 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2622 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2623 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2624 int ret;
2625
662595df 2626 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2627 if (ret)
2628 return ret;
2629
3f43c48d 2630 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2631 int i = val;
2632 bool has_audio;
2633
2634 if (i == intel_dp->force_audio)
f684960e
CW		 2635 return 0;
2636
1aad7ac0 2637 intel_dp->force_audio = i;
f684960e 2638
c3e5f67b 2639 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2640 has_audio = intel_dp_detect_audio(connector);
2641 else
c3e5f67b 2642 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2643
2644 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2645 return 0;
2646
1aad7ac0 2647 intel_dp->has_audio = has_audio;
f684960e
CW		 2648 goto done;
2649 }
2650
e953fd7b 2651 if (property == dev_priv->broadcast_rgb_property) {
55bc60db
VS		 2652 switch (val) {
2653 case INTEL_BROADCAST_RGB_AUTO:
2654 intel_dp->color_range_auto = true;
2655 break;
2656 case INTEL_BROADCAST_RGB_FULL:
2657 intel_dp->color_range_auto = false;
2658 intel_dp->color_range = 0;
2659 break;
2660 case INTEL_BROADCAST_RGB_LIMITED:
2661 intel_dp->color_range_auto = false;
2662 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2663 break;
2664 default:
2665 return -EINVAL;
2666 }
e953fd7b
CW		 2667 goto done;
2668 }
2669
53b41837
YN		 2670 if (is_edp(intel_dp) &&
2671 property == connector->dev->mode_config.scaling_mode_property) {
2672 if (val == DRM_MODE_SCALE_NONE) {
2673 DRM_DEBUG_KMS("no scaling not supported\n");
2674 return -EINVAL;
2675 }
2676
2677 if (intel_connector->panel.fitting_mode == val) {
2678 /* the eDP scaling property is not changed */
2679 return 0;
2680 }
2681 intel_connector->panel.fitting_mode = val;
2682
2683 goto done;
2684 }
2685
f684960e
CW		 2686 return -EINVAL;
2687
2688done:
c0c36b94
CW		 2689 if (intel_encoder->base.crtc)
2690 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 2691
2692 return 0;
2693}
2694
a4fc5ed6 2695static void
0206e353 2696intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2697{
be3cd5e3 2698 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2699 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2700
9cd300e0
JN		 2701 if (!IS_ERR_OR_NULL(intel_connector->edid))
2702 kfree(intel_connector->edid);
2703
dc652f90 2704 if (is_edp(intel_dp))
1d508706 2705 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 2706
a4fc5ed6
KP		 2707 drm_sysfs_connector_remove(connector);
2708 drm_connector_cleanup(connector);
55f78c43 2709 kfree(connector);
a4fc5ed6
KP		 2710}
2711
00c09d70 2712void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 2713{
da63a9f2
PZ		 2714 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2715 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927
DV		 2716
2717 i2c_del_adapter(&intel_dp->adapter);
2718 drm_encoder_cleanup(encoder);
bd943159
KP		 2719 if (is_edp(intel_dp)) {
2720 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2721 ironlake_panel_vdd_off_sync(intel_dp);
2722 }
da63a9f2 2723 kfree(intel_dig_port);
24d05927
DV		 2724}
2725
a4fc5ed6 2726static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2727 .mode_set = intel_dp_mode_set,
a4fc5ed6
KP		 2728};
2729
2730static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2731 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2732 .detect = intel_dp_detect,
2733 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2734 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2735 .destroy = intel_dp_destroy,
2736};
2737
2738static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2739 .get_modes = intel_dp_get_modes,
2740 .mode_valid = intel_dp_mode_valid,
df0e9248 2741 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2742};
2743
a4fc5ed6 2744static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2745 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2746};
2747
995b6762 2748static void
21d40d37 2749intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2750{
fa90ecef 2751 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 2752
885a5014 2753 intel_dp_check_link_status(intel_dp);
c8110e52 2754}
6207937d 2755
e3421a18
ZW		 2756/* Return which DP Port should be selected for Transcoder DP control */
2757int
0206e353 2758intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2759{
2760 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 2761 struct intel_encoder *intel_encoder;
2762 struct intel_dp *intel_dp;
e3421a18 2763
fa90ecef
PZ		 2764 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2765 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 2766
fa90ecef
PZ		 2767 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2768 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 2769 return intel_dp->output_reg;
e3421a18 2770 }
ea5b213a 2771
e3421a18
ZW		 2772 return -1;
2773}
2774
36e83a18 2775/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2776bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2777{
2778 struct drm_i915_private *dev_priv = dev->dev_private;
2779 struct child_device_config *p_child;
2780 int i;
2781
2782 if (!dev_priv->child_dev_num)
2783 return false;
2784
2785 for (i = 0; i < dev_priv->child_dev_num; i++) {
2786 p_child = dev_priv->child_dev + i;
2787
2788 if (p_child->dvo_port == PORT_IDPD &&
2789 p_child->device_type == DEVICE_TYPE_eDP)
2790 return true;
2791 }
2792 return false;
2793}
2794
f684960e
CW		 2795static void
2796intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2797{
53b41837
YN		 2798 struct intel_connector *intel_connector = to_intel_connector(connector);
2799
3f43c48d 2800 intel_attach_force_audio_property(connector);
e953fd7b 2801 intel_attach_broadcast_rgb_property(connector);
55bc60db 2802 intel_dp->color_range_auto = true;
53b41837
YN		 2803
2804 if (is_edp(intel_dp)) {
2805 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 2806 drm_object_attach_property(
2807 &connector->base,
53b41837 2808 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 2809 DRM_MODE_SCALE_ASPECT);
2810 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 2811 }
f684960e
CW		 2812}
2813
67a54566
DV		 2814static void
2815intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 2816 struct intel_dp *intel_dp,
2817 struct edp_power_seq *out)
67a54566
DV		 2818{
2819 struct drm_i915_private *dev_priv = dev->dev_private;
2820 struct edp_power_seq cur, vbt, spec, final;
2821 u32 pp_on, pp_off, pp_div, pp;
453c5420
JB		 2822 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2823
2824 if (HAS_PCH_SPLIT(dev)) {
2825 pp_control_reg = PCH_PP_CONTROL;
2826 pp_on_reg = PCH_PP_ON_DELAYS;
2827 pp_off_reg = PCH_PP_OFF_DELAYS;
2828 pp_div_reg = PCH_PP_DIVISOR;
2829 } else {
2830 pp_control_reg = PIPEA_PP_CONTROL;
2831 pp_on_reg = PIPEA_PP_ON_DELAYS;
2832 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2833 pp_div_reg = PIPEA_PP_DIVISOR;
2834 }
67a54566
DV		 2835
2836 /* Workaround: Need to write PP_CONTROL with the unlock key as
2837 * the very first thing. */
453c5420
JB		 2838 pp = ironlake_get_pp_control(intel_dp);
2839 I915_WRITE(pp_control_reg, pp);
67a54566 2840
453c5420
JB		 2841 pp_on = I915_READ(pp_on_reg);
2842 pp_off = I915_READ(pp_off_reg);
2843 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 2844
2845 /* Pull timing values out of registers */
2846 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2847 PANEL_POWER_UP_DELAY_SHIFT;
2848
2849 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2850 PANEL_LIGHT_ON_DELAY_SHIFT;
2851
2852 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2853 PANEL_LIGHT_OFF_DELAY_SHIFT;
2854
2855 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2856 PANEL_POWER_DOWN_DELAY_SHIFT;
2857
2858 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2859 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2860
2861 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2862 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2863
2864 vbt = dev_priv->edp.pps;
2865
2866 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2867 * our hw here, which are all in 100usec. */
2868 spec.t1_t3 = 210 * 10;
2869 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2870 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2871 spec.t10 = 500 * 10;
2872 /* This one is special and actually in units of 100ms, but zero
2873 * based in the hw (so we need to add 100 ms). But the sw vbt
2874 * table multiplies it with 1000 to make it in units of 100usec,
2875 * too. */
2876 spec.t11_t12 = (510 + 100) * 10;
2877
2878 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2879 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2880
2881 /* Use the max of the register settings and vbt. If both are
2882 * unset, fall back to the spec limits. */
2883#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2884 spec.field : \
2885 max(cur.field, vbt.field))
2886 assign_final(t1_t3);
2887 assign_final(t8);
2888 assign_final(t9);
2889 assign_final(t10);
2890 assign_final(t11_t12);
2891#undef assign_final
2892
2893#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2894 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2895 intel_dp->backlight_on_delay = get_delay(t8);
2896 intel_dp->backlight_off_delay = get_delay(t9);
2897 intel_dp->panel_power_down_delay = get_delay(t10);
2898 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2899#undef get_delay
2900
f30d26e4
JN		 2901 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2902 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2903 intel_dp->panel_power_cycle_delay);
2904
2905 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2906 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2907
2908 if (out)
2909 *out = final;
2910}
2911
2912static void
2913intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2914 struct intel_dp *intel_dp,
2915 struct edp_power_seq *seq)
2916{
2917 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 2918 u32 pp_on, pp_off, pp_div, port_sel = 0;
2919 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2920 int pp_on_reg, pp_off_reg, pp_div_reg;
2921
2922 if (HAS_PCH_SPLIT(dev)) {
2923 pp_on_reg = PCH_PP_ON_DELAYS;
2924 pp_off_reg = PCH_PP_OFF_DELAYS;
2925 pp_div_reg = PCH_PP_DIVISOR;
2926 } else {
2927 pp_on_reg = PIPEA_PP_ON_DELAYS;
2928 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2929 pp_div_reg = PIPEA_PP_DIVISOR;
2930 }
2931
2932 if (IS_VALLEYVIEW(dev))
2933 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
f30d26e4 2934
67a54566 2935 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 2936 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2937 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2938 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2939 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 2940 /* Compute the divisor for the pp clock, simply match the Bspec
2941 * formula. */
453c5420 2942 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 2943 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 2944 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2945
2946 /* Haswell doesn't have any port selection bits for the panel
2947 * power sequencer any more. */
2948 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2949 if (is_cpu_edp(intel_dp))
453c5420 2950 port_sel = PANEL_POWER_PORT_DP_A;
67a54566 2951 else
453c5420 2952 port_sel = PANEL_POWER_PORT_DP_D;
67a54566
DV		 2953 }
2954
453c5420
JB		 2955 pp_on |= port_sel;
2956
2957 I915_WRITE(pp_on_reg, pp_on);
2958 I915_WRITE(pp_off_reg, pp_off);
2959 I915_WRITE(pp_div_reg, pp_div);
67a54566 2960
67a54566 2961 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 2962 I915_READ(pp_on_reg),
2963 I915_READ(pp_off_reg),
2964 I915_READ(pp_div_reg));
f684960e
CW		 2965}
2966
a4fc5ed6 2967void
f0fec3f2
PZ		 2968intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2969 struct intel_connector *intel_connector)
a4fc5ed6 2970{
f0fec3f2
PZ		 2971 struct drm_connector *connector = &intel_connector->base;
2972 struct intel_dp *intel_dp = &intel_dig_port->dp;
2973 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2974 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 2975 struct drm_i915_private *dev_priv = dev->dev_private;
f8779fda 2976 struct drm_display_mode *fixed_mode = NULL;
f30d26e4 2977 struct edp_power_seq power_seq = { 0 };
174edf1f 2978 enum port port = intel_dig_port->port;
5eb08b69 2979 const char *name = NULL;
b329530c 2980 int type;
a4fc5ed6 2981
0767935e
DV		 2982 /* Preserve the current hw state. */
2983 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 2984 intel_dp->attached_connector = intel_connector;
3d3dc149 2985
f0fec3f2 2986 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
b329530c 2987 if (intel_dpd_is_edp(dev))
ea5b213a 2988 intel_dp->is_pch_edp = true;
b329530c 2989
19c03924
GB		 2990 /*
2991 * FIXME : We need to initialize built-in panels before external panels.
2992 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2993 */
f0fec3f2 2994 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
19c03924
GB		 2995 type = DRM_MODE_CONNECTOR_eDP;
2996 intel_encoder->type = INTEL_OUTPUT_EDP;
f0fec3f2 2997 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2998 type = DRM_MODE_CONNECTOR_eDP;
2999 intel_encoder->type = INTEL_OUTPUT_EDP;
3000 } else {
00c09d70
PZ		 3001 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
3002 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
3003 * rewrite it.
3004 */
b329530c 3005 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c
AJ		 3006 }
3007
b329530c 3008 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3009 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3010
a4fc5ed6
KP		 3011 connector->interlace_allowed = true;
3012 connector->doublescan_allowed = 0;
3013
f0fec3f2
PZ		 3014 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3015 ironlake_panel_vdd_work);
a4fc5ed6 3016
df0e9248 3017 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3018 drm_sysfs_connector_add(connector);
3019
affa9354 3020 if (HAS_DDI(dev))
bcbc889b
PZ		 3021 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3022 else
3023 intel_connector->get_hw_state = intel_connector_get_hw_state;
3024
9ed35ab1
PZ		 3025 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3026 if (HAS_DDI(dev)) {
3027 switch (intel_dig_port->port) {
3028 case PORT_A:
3029 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3030 break;
3031 case PORT_B:
3032 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3033 break;
3034 case PORT_C:
3035 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3036 break;
3037 case PORT_D:
3038 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3039 break;
3040 default:
3041 BUG();
3042 }
3043 }
e8cb4558 3044
a4fc5ed6 3045 /* Set up the DDC bus. */
ab9d7c30
PZ		 3046 switch (port) {
3047 case PORT_A:
1d843f9d 3048 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3049 name = "DPDDC-A";
3050 break;
3051 case PORT_B:
1d843f9d 3052 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3053 name = "DPDDC-B";
3054 break;
3055 case PORT_C:
1d843f9d 3056 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3057 name = "DPDDC-C";
3058 break;
3059 case PORT_D:
1d843f9d 3060 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3061 name = "DPDDC-D";
3062 break;
3063 default:
ad1c0b19 3064 BUG();
5eb08b69
ZW		 3065 }
3066
67a54566 3067 if (is_edp(intel_dp))
f30d26e4 3068 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
c1f05264
DA		 3069
3070 intel_dp_i2c_init(intel_dp, intel_connector, name);
3071
67a54566 3072 /* Cache DPCD and EDID for edp. */
c1f05264
DA		 3073 if (is_edp(intel_dp)) {
3074 bool ret;
f8779fda 3075 struct drm_display_mode *scan;
c1f05264 3076 struct edid *edid;
5d613501
JB		 3077
3078 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 3079 ret = intel_dp_get_dpcd(intel_dp);
bd943159 3080 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 3081
59f3e272 3082 if (ret) {
7183dc29
JB		 3083 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3084 dev_priv->no_aux_handshake =
3085 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 3086 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3087 } else {
3d3dc149 3088 /* if this fails, presume the device is a ghost */
48898b03 3089 DRM_INFO("failed to retrieve link info, disabling eDP\n");
fa90ecef
PZ		 3090 intel_dp_encoder_destroy(&intel_encoder->base);
3091 intel_dp_destroy(connector);
3d3dc149 3092 return;
89667383 3093 }
89667383 3094
f30d26e4
JN		 3095 /* We now know it's not a ghost, init power sequence regs. */
3096 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3097 &power_seq);
3098
d6f24d0f
JB		 3099 ironlake_edp_panel_vdd_on(intel_dp);
3100 edid = drm_get_edid(connector, &intel_dp->adapter);
3101 if (edid) {
9cd300e0
JN		 3102 if (drm_add_edid_modes(connector, edid)) {
3103 drm_mode_connector_update_edid_property(connector, edid);
3104 drm_edid_to_eld(connector, edid);
3105 } else {
3106 kfree(edid);
3107 edid = ERR_PTR(-EINVAL);
3108 }
3109 } else {
3110 edid = ERR_PTR(-ENOENT);
d6f24d0f 3111 }
9cd300e0 3112 intel_connector->edid = edid;
f8779fda
JN		 3113
3114 /* prefer fixed mode from EDID if available */
3115 list_for_each_entry(scan, &connector->probed_modes, head) {
3116 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3117 fixed_mode = drm_mode_duplicate(dev, scan);
3118 break;
3119 }
d6f24d0f 3120 }
f8779fda
JN		 3121
3122 /* fallback to VBT if available for eDP */
3123 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
3124 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
3125 if (fixed_mode)
3126 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3127 }
f8779fda 3128
d6f24d0f
JB		 3129 ironlake_edp_panel_vdd_off(intel_dp, false);
3130 }
552fb0b7 3131
4d926461 3132 if (is_edp(intel_dp)) {
dd06f90e 3133 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 3134 intel_panel_setup_backlight(connector);
32f9d658
ZW		 3135 }
3136
f684960e
CW		 3137 intel_dp_add_properties(intel_dp, connector);
3138
a4fc5ed6
KP		 3139 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3140 * 0xd. Failure to do so will result in spurious interrupts being
3141 * generated on the port when a cable is not attached.
3142 */
3143 if (IS_G4X(dev) && !IS_GM45(dev)) {
3144 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3145 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3146 }
3147}
f0fec3f2
PZ		 3148
3149void
3150intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3151{
3152 struct intel_digital_port *intel_dig_port;
3153 struct intel_encoder *intel_encoder;
3154 struct drm_encoder *encoder;
3155 struct intel_connector *intel_connector;
3156
3157 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3158 if (!intel_dig_port)
3159 return;
3160
3161 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3162 if (!intel_connector) {
3163 kfree(intel_dig_port);
3164 return;
3165 }
3166
3167 intel_encoder = &intel_dig_port->base;
3168 encoder = &intel_encoder->base;
3169
3170 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3171 DRM_MODE_ENCODER_TMDS);
00c09d70 3172 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
f0fec3f2 3173
5bfe2ac0 3174 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70
PZ		 3175 intel_encoder->enable = intel_enable_dp;
3176 intel_encoder->pre_enable = intel_pre_enable_dp;
3177 intel_encoder->disable = intel_disable_dp;
3178 intel_encoder->post_disable = intel_post_disable_dp;
3179 intel_encoder->get_hw_state = intel_dp_get_hw_state;
89b667f8
JB		 3180 if (IS_VALLEYVIEW(dev))
3181 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
f0fec3f2 3182
174edf1f 3183 intel_dig_port->port = port;
f0fec3f2
PZ		 3184 intel_dig_port->dp.output_reg = output_reg;
3185
00c09d70 3186 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3187 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3188 intel_encoder->cloneable = false;
3189 intel_encoder->hot_plug = intel_dp_hot_plug;
3190
3191 intel_dp_init_connector(intel_dig_port, intel_connector);
3192}
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