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drm/i915: rip out pre-production ilk cpu edp w/a
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
55/**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63static bool is_pch_edp(struct intel_dp *intel_dp)
64{
65 return intel_dp->is_pch_edp;
66}
67
1c95822a
AJ		 68/**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74static bool is_cpu_edp(struct intel_dp *intel_dp)
75{
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77}
78
30add22d 79static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
ea5b213a 80{
da63a9f2
PZ		 81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
82
83 return intel_dig_port->base.base.dev;
ea5b213a 84}
a4fc5ed6 85
df0e9248
CW		 86static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
87{
fa90ecef 88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 89}
90
814948ad
JB		 91/**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99{
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108}
109
ea5b213a 110static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 111
32f9d658 112void
0206e353 113intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 114 int *lane_num, int *link_bw)
32f9d658 115{
fa90ecef 116 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
32f9d658 117
ea5b213a 118 *lane_num = intel_dp->lane_count;
3b5c662e 119 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
32f9d658
ZW		 120}
121
94bf2ced
DV		 122int
123intel_edp_target_clock(struct intel_encoder *intel_encoder,
124 struct drm_display_mode *mode)
125{
fa90ecef 126 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
dd06f90e 127 struct intel_connector *intel_connector = intel_dp->attached_connector;
94bf2ced 128
dd06f90e
JN		 129 if (intel_connector->panel.fixed_mode)
130 return intel_connector->panel.fixed_mode->clock;
94bf2ced
DV		 131 else
132 return mode->clock;
133}
134
a4fc5ed6 135static int
ea5b213a 136intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 137{
7183dc29 138 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 139
140 switch (max_link_bw) {
141 case DP_LINK_BW_1_62:
142 case DP_LINK_BW_2_7:
143 break;
144 default:
145 max_link_bw = DP_LINK_BW_1_62;
146 break;
147 }
148 return max_link_bw;
149}
150
cd9dde44
AJ		 151/*
152 * The units on the numbers in the next two are... bizarre. Examples will
153 * make it clearer; this one parallels an example in the eDP spec.
154 *
155 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
156 *
157 * 270000 * 1 * 8 / 10 == 216000
158 *
159 * The actual data capacity of that configuration is 2.16Gbit/s, so the
160 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
161 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
162 * 119000. At 18bpp that's 2142000 kilobits per second.
163 *
164 * Thus the strange-looking division by 10 in intel_dp_link_required, to
165 * get the result in decakilobits instead of kilobits.
166 */
167
a4fc5ed6 168static int
c898261c 169intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 170{
cd9dde44 171 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 172}
173
fe27d53e
DA		 174static int
175intel_dp_max_data_rate(int max_link_clock, int max_lanes)
176{
177 return (max_link_clock * max_lanes * 8) / 10;
178}
179
c4867936
DV		 180static bool
181intel_dp_adjust_dithering(struct intel_dp *intel_dp,
182 struct drm_display_mode *mode,
cb1793ce 183 bool adjust_mode)
c4867936 184{
9fa5f652
PZ		 185 int max_link_clock =
186 drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
397fe157 187 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
c4867936
DV		 188 int max_rate, mode_rate;
189
190 mode_rate = intel_dp_link_required(mode->clock, 24);
191 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
192
193 if (mode_rate > max_rate) {
194 mode_rate = intel_dp_link_required(mode->clock, 18);
195 if (mode_rate > max_rate)
196 return false;
197
cb1793ce
DV		 198 if (adjust_mode)
199 mode->private_flags
c4867936
DV		 200 |= INTEL_MODE_DP_FORCE_6BPC;
201
202 return true;
203 }
204
205 return true;
206}
207
a4fc5ed6
KP		 208static int
209intel_dp_mode_valid(struct drm_connector *connector,
210 struct drm_display_mode *mode)
211{
df0e9248 212 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 213 struct intel_connector *intel_connector = to_intel_connector(connector);
214 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
a4fc5ed6 215
dd06f90e
JN		 216 if (is_edp(intel_dp) && fixed_mode) {
217 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 218 return MODE_PANEL;
219
dd06f90e 220 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43
ZY		 221 return MODE_PANEL;
222 }
223
cb1793ce 224 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 225 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 226
227 if (mode->clock < 10000)
228 return MODE_CLOCK_LOW;
229
0af78a2b
DV		 230 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
231 return MODE_H_ILLEGAL;
232
a4fc5ed6
KP		 233 return MODE_OK;
234}
235
236static uint32_t
237pack_aux(uint8_t *src, int src_bytes)
238{
239 int i;
240 uint32_t v = 0;
241
242 if (src_bytes > 4)
243 src_bytes = 4;
244 for (i = 0; i < src_bytes; i++)
245 v |= ((uint32_t) src[i]) << ((3-i) * 8);
246 return v;
247}
248
249static void
250unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
251{
252 int i;
253 if (dst_bytes > 4)
254 dst_bytes = 4;
255 for (i = 0; i < dst_bytes; i++)
256 dst[i] = src >> ((3-i) * 8);
257}
258
fb0f8fbf
KP		 259/* hrawclock is 1/4 the FSB frequency */
260static int
261intel_hrawclk(struct drm_device *dev)
262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 uint32_t clkcfg;
265
9473c8f4
VP		 266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev))
268 return 200;
269
fb0f8fbf
KP		 270 clkcfg = I915_READ(CLKCFG);
271 switch (clkcfg & CLKCFG_FSB_MASK) {
272 case CLKCFG_FSB_400:
273 return 100;
274 case CLKCFG_FSB_533:
275 return 133;
276 case CLKCFG_FSB_667:
277 return 166;
278 case CLKCFG_FSB_800:
279 return 200;
280 case CLKCFG_FSB_1067:
281 return 266;
282 case CLKCFG_FSB_1333:
283 return 333;
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600:
286 case CLKCFG_FSB_1600_ALT:
287 return 400;
288 default:
289 return 133;
290 }
291}
292
ebf33b18
KP		 293static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
294{
30add22d 295 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 296 struct drm_i915_private *dev_priv = dev->dev_private;
297
298 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
299}
300
301static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
302{
30add22d 303 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 304 struct drm_i915_private *dev_priv = dev->dev_private;
305
306 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
307}
308
9b984dae
KP		 309static void
310intel_dp_check_edp(struct intel_dp *intel_dp)
311{
30add22d 312 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 313 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 314
9b984dae
KP		 315 if (!is_edp(intel_dp))
316 return;
ebf33b18 317 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 318 WARN(1, "eDP powered off while attempting aux channel communication.\n");
319 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 320 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 321 I915_READ(PCH_PP_CONTROL));
322 }
323}
324
9ee32fea
DV		 325static uint32_t
326intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
327{
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
331 uint32_t ch_ctl = intel_dp->output_reg + 0x10;
332 uint32_t status;
333 bool done;
334
335 if (IS_HASWELL(dev)) {
336 switch (intel_dig_port->port) {
337 case PORT_A:
338 ch_ctl = DPA_AUX_CH_CTL;
339 break;
340 case PORT_B:
341 ch_ctl = PCH_DPB_AUX_CH_CTL;
342 break;
343 case PORT_C:
344 ch_ctl = PCH_DPC_AUX_CH_CTL;
345 break;
346 case PORT_D:
347 ch_ctl = PCH_DPD_AUX_CH_CTL;
348 break;
349 default:
350 BUG();
351 }
352 }
353
ef04f00d 354#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea
DV		 355 if (has_aux_irq)
356 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10);
357 else
358 done = wait_for_atomic(C, 10) == 0;
359 if (!done)
360 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
361 has_aux_irq);
362#undef C
363
364 return status;
365}
366
a4fc5ed6 367static int
ea5b213a 368intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 369 uint8_t *send, int send_bytes,
370 uint8_t *recv, int recv_size)
371{
ea5b213a 372 uint32_t output_reg = intel_dp->output_reg;
174edf1f
PZ		 373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
374 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6
KP		 375 struct drm_i915_private *dev_priv = dev->dev_private;
376 uint32_t ch_ctl = output_reg + 0x10;
377 uint32_t ch_data = ch_ctl + 4;
9ee32fea 378 int i, ret, recv_bytes;
a4fc5ed6 379 uint32_t status;
fb0f8fbf 380 uint32_t aux_clock_divider;
6b4e0a93 381 int try, precharge;
9ee32fea
DV		 382 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
383
384 /* dp aux is extremely sensitive to irq latency, hence request the
385 * lowest possible wakeup latency and so prevent the cpu from going into
386 * deep sleep states.
387 */
388 pm_qos_update_request(&dev_priv->pm_qos, 0);
a4fc5ed6 389
750eb99e 390 if (IS_HASWELL(dev)) {
174edf1f 391 switch (intel_dig_port->port) {
750eb99e
PZ		 392 case PORT_A:
393 ch_ctl = DPA_AUX_CH_CTL;
394 ch_data = DPA_AUX_CH_DATA1;
395 break;
396 case PORT_B:
397 ch_ctl = PCH_DPB_AUX_CH_CTL;
398 ch_data = PCH_DPB_AUX_CH_DATA1;
399 break;
400 case PORT_C:
401 ch_ctl = PCH_DPC_AUX_CH_CTL;
402 ch_data = PCH_DPC_AUX_CH_DATA1;
403 break;
404 case PORT_D:
405 ch_ctl = PCH_DPD_AUX_CH_CTL;
406 ch_data = PCH_DPD_AUX_CH_DATA1;
407 break;
408 default:
409 BUG();
410 }
411 }
412
9b984dae 413 intel_dp_check_edp(intel_dp);
a4fc5ed6 414 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 415 * and would like to run at 2MHz. So, take the
416 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 417 *
418 * Note that PCH attached eDP panels should use a 125MHz input
419 * clock divider.
a4fc5ed6 420 */
1c95822a 421 if (is_cpu_edp(intel_dp)) {
affa9354 422 if (HAS_DDI(dev))
b8fc2f6a
PZ		 423 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
424 else if (IS_VALLEYVIEW(dev))
9473c8f4
VP		 425 aux_clock_divider = 100;
426 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 427 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 428 else
429 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
430 } else if (HAS_PCH_SPLIT(dev))
6b3ec1c9 431 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
5eb08b69
ZW		 432 else
433 aux_clock_divider = intel_hrawclk(dev) / 2;
434
6b4e0a93
DV		 435 if (IS_GEN6(dev))
436 precharge = 3;
437 else
438 precharge = 5;
439
11bee43e
JB		 440 /* Try to wait for any previous AUX channel activity */
441 for (try = 0; try < 3; try++) {
ef04f00d 442 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 443 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
444 break;
445 msleep(1);
446 }
447
448 if (try == 3) {
449 WARN(1, "dp_aux_ch not started status 0x%08x\n",
450 I915_READ(ch_ctl));
9ee32fea
DV		 451 ret = -EBUSY;
452 goto out;
4f7f7b7e
CW		 453 }
454
fb0f8fbf
KP		 455 /* Must try at least 3 times according to DP spec */
456 for (try = 0; try < 5; try++) {
457 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 458 for (i = 0; i < send_bytes; i += 4)
459 I915_WRITE(ch_data + i,
460 pack_aux(send + i, send_bytes - i));
0206e353 461
fb0f8fbf 462 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 463 I915_WRITE(ch_ctl,
464 DP_AUX_CH_CTL_SEND_BUSY |
9ee32fea 465 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
4f7f7b7e
CW		 466 DP_AUX_CH_CTL_TIME_OUT_400us |
467 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
468 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
469 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
470 DP_AUX_CH_CTL_DONE |
471 DP_AUX_CH_CTL_TIME_OUT_ERROR |
472 DP_AUX_CH_CTL_RECEIVE_ERROR);
9ee32fea
DV		 473
474 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
0206e353 475
fb0f8fbf 476 /* Clear done status and any errors */
4f7f7b7e
CW		 477 I915_WRITE(ch_ctl,
478 status |
479 DP_AUX_CH_CTL_DONE |
480 DP_AUX_CH_CTL_TIME_OUT_ERROR |
481 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 482
483 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
484 DP_AUX_CH_CTL_RECEIVE_ERROR))
485 continue;
4f7f7b7e 486 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 487 break;
488 }
489
a4fc5ed6 490 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 491 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 492 ret = -EBUSY;
493 goto out;
a4fc5ed6
KP		 494 }
495
496 /* Check for timeout or receive error.
497 * Timeouts occur when the sink is not connected
498 */
a5b3da54 499 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 500 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 501 ret = -EIO;
502 goto out;
a5b3da54 503 }
1ae8c0a5
KP		 504
505 /* Timeouts occur when the device isn't connected, so they're
506 * "normal" -- don't fill the kernel log with these */
a5b3da54 507 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 508 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 509 ret = -ETIMEDOUT;
510 goto out;
a4fc5ed6
KP		 511 }
512
513 /* Unload any bytes sent back from the other side */
514 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
515 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 516 if (recv_bytes > recv_size)
517 recv_bytes = recv_size;
0206e353 518
4f7f7b7e
CW		 519 for (i = 0; i < recv_bytes; i += 4)
520 unpack_aux(I915_READ(ch_data + i),
521 recv + i, recv_bytes - i);
a4fc5ed6 522
9ee32fea
DV		 523 ret = recv_bytes;
524out:
525 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
526
527 return ret;
a4fc5ed6
KP		 528}
529
530/* Write data to the aux channel in native mode */
531static int
ea5b213a 532intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 533 uint16_t address, uint8_t *send, int send_bytes)
534{
535 int ret;
536 uint8_t msg[20];
537 int msg_bytes;
538 uint8_t ack;
539
9b984dae 540 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 541 if (send_bytes > 16)
542 return -1;
543 msg[0] = AUX_NATIVE_WRITE << 4;
544 msg[1] = address >> 8;
eebc863e 545 msg[2] = address & 0xff;
a4fc5ed6
KP		 546 msg[3] = send_bytes - 1;
547 memcpy(&msg[4], send, send_bytes);
548 msg_bytes = send_bytes + 4;
549 for (;;) {
ea5b213a 550 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 551 if (ret < 0)
552 return ret;
553 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
554 break;
555 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
556 udelay(100);
557 else
a5b3da54 558 return -EIO;
a4fc5ed6
KP		 559 }
560 return send_bytes;
561}
562
563/* Write a single byte to the aux channel in native mode */
564static int
ea5b213a 565intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 566 uint16_t address, uint8_t byte)
567{
ea5b213a 568 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 569}
570
571/* read bytes from a native aux channel */
572static int
ea5b213a 573intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 574 uint16_t address, uint8_t *recv, int recv_bytes)
575{
576 uint8_t msg[4];
577 int msg_bytes;
578 uint8_t reply[20];
579 int reply_bytes;
580 uint8_t ack;
581 int ret;
582
9b984dae 583 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 584 msg[0] = AUX_NATIVE_READ << 4;
585 msg[1] = address >> 8;
586 msg[2] = address & 0xff;
587 msg[3] = recv_bytes - 1;
588
589 msg_bytes = 4;
590 reply_bytes = recv_bytes + 1;
591
592 for (;;) {
ea5b213a 593 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 594 reply, reply_bytes);
a5b3da54
KP		 595 if (ret == 0)
596 return -EPROTO;
597 if (ret < 0)
a4fc5ed6
KP		 598 return ret;
599 ack = reply[0];
600 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
601 memcpy(recv, reply + 1, ret - 1);
602 return ret - 1;
603 }
604 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
605 udelay(100);
606 else
a5b3da54 607 return -EIO;
a4fc5ed6
KP		 608 }
609}
610
611static int
ab2c0672
DA		 612intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
613 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 614{
ab2c0672 615 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 616 struct intel_dp *intel_dp = container_of(adapter,
617 struct intel_dp,
618 adapter);
ab2c0672
DA		 619 uint16_t address = algo_data->address;
620 uint8_t msg[5];
621 uint8_t reply[2];
8316f337 622 unsigned retry;
ab2c0672
DA		 623 int msg_bytes;
624 int reply_bytes;
625 int ret;
626
9b984dae 627 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 628 /* Set up the command byte */
629 if (mode & MODE_I2C_READ)
630 msg[0] = AUX_I2C_READ << 4;
631 else
632 msg[0] = AUX_I2C_WRITE << 4;
633
634 if (!(mode & MODE_I2C_STOP))
635 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 636
ab2c0672
DA		 637 msg[1] = address >> 8;
638 msg[2] = address;
639
640 switch (mode) {
641 case MODE_I2C_WRITE:
642 msg[3] = 0;
643 msg[4] = write_byte;
644 msg_bytes = 5;
645 reply_bytes = 1;
646 break;
647 case MODE_I2C_READ:
648 msg[3] = 0;
649 msg_bytes = 4;
650 reply_bytes = 2;
651 break;
652 default:
653 msg_bytes = 3;
654 reply_bytes = 1;
655 break;
656 }
657
8316f337
DF		 658 for (retry = 0; retry < 5; retry++) {
659 ret = intel_dp_aux_ch(intel_dp,
660 msg, msg_bytes,
661 reply, reply_bytes);
ab2c0672 662 if (ret < 0) {
3ff99164 663 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 664 return ret;
665 }
8316f337
DF		 666
667 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
668 case AUX_NATIVE_REPLY_ACK:
669 /* I2C-over-AUX Reply field is only valid
670 * when paired with AUX ACK.
671 */
672 break;
673 case AUX_NATIVE_REPLY_NACK:
674 DRM_DEBUG_KMS("aux_ch native nack\n");
675 return -EREMOTEIO;
676 case AUX_NATIVE_REPLY_DEFER:
677 udelay(100);
678 continue;
679 default:
680 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
681 reply[0]);
682 return -EREMOTEIO;
683 }
684
ab2c0672
DA		 685 switch (reply[0] & AUX_I2C_REPLY_MASK) {
686 case AUX_I2C_REPLY_ACK:
687 if (mode == MODE_I2C_READ) {
688 *read_byte = reply[1];
689 }
690 return reply_bytes - 1;
691 case AUX_I2C_REPLY_NACK:
8316f337 692 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 693 return -EREMOTEIO;
694 case AUX_I2C_REPLY_DEFER:
8316f337 695 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 696 udelay(100);
697 break;
698 default:
8316f337 699 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 700 return -EREMOTEIO;
701 }
702 }
8316f337
DF		 703
704 DRM_ERROR("too many retries, giving up\n");
705 return -EREMOTEIO;
a4fc5ed6
KP		 706}
707
708static int
ea5b213a 709intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 710 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 711{
0b5c541b
KP		 712 int ret;
713
d54e9d28 714 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 715 intel_dp->algo.running = false;
716 intel_dp->algo.address = 0;
717 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
718
0206e353 719 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 720 intel_dp->adapter.owner = THIS_MODULE;
721 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 722 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 723 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
724 intel_dp->adapter.algo_data = &intel_dp->algo;
725 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
726
0b5c541b
KP		 727 ironlake_edp_panel_vdd_on(intel_dp);
728 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 729 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 730 return ret;
a4fc5ed6
KP		 731}
732
00c09d70 733bool
e811f5ae
LP		 734intel_dp_mode_fixup(struct drm_encoder *encoder,
735 const struct drm_display_mode *mode,
a4fc5ed6
KP		 736 struct drm_display_mode *adjusted_mode)
737{
0d3a1bee 738 struct drm_device *dev = encoder->dev;
ea5b213a 739 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
dd06f90e 740 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 741 int lane_count, clock;
397fe157 742 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 743 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 744 int bpp, mode_rate;
a4fc5ed6
KP		 745 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
746
dd06f90e
JN		 747 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
748 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
749 adjusted_mode);
53b41837
YN		 750 intel_pch_panel_fitting(dev,
751 intel_connector->panel.fitting_mode,
1d8e1c75 752 mode, adjusted_mode);
0d3a1bee
ZY		 753 }
754
cb1793ce 755 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 756 return false;
757
083f9560
DV		 758 DRM_DEBUG_KMS("DP link computation with max lane count %i "
759 "max bw %02x pixel clock %iKHz\n",
71244653 760 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 761
cb1793ce 762 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 763 return false;
764
765 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
71244653 766 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 767
2514bc51
JB		 768 for (clock = 0; clock <= max_clock; clock++) {
769 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
9fa5f652
PZ		 770 int link_bw_clock =
771 drm_dp_bw_code_to_link_rate(bws[clock]);
772 int link_avail = intel_dp_max_data_rate(link_bw_clock,
773 lane_count);
a4fc5ed6 774
083f9560 775 if (mode_rate <= link_avail) {
ea5b213a
CW		 776 intel_dp->link_bw = bws[clock];
777 intel_dp->lane_count = lane_count;
9fa5f652 778 adjusted_mode->clock = link_bw_clock;
083f9560
DV		 779 DRM_DEBUG_KMS("DP link bw %02x lane "
780 "count %d clock %d bpp %d\n",
ea5b213a 781 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 782 adjusted_mode->clock, bpp);
783 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
784 mode_rate, link_avail);
a4fc5ed6
KP		 785 return true;
786 }
787 }
788 }
fe27d53e 789
a4fc5ed6
KP		 790 return false;
791}
792
793struct intel_dp_m_n {
794 uint32_t tu;
795 uint32_t gmch_m;
796 uint32_t gmch_n;
797 uint32_t link_m;
798 uint32_t link_n;
799};
800
801static void
802intel_reduce_ratio(uint32_t *num, uint32_t *den)
803{
804 while (*num > 0xffffff || *den > 0xffffff) {
805 *num >>= 1;
806 *den >>= 1;
807 }
808}
809
810static void
36e83a18 811intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 812 int nlanes,
813 int pixel_clock,
814 int link_clock,
815 struct intel_dp_m_n *m_n)
816{
817 m_n->tu = 64;
36e83a18 818 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 819 m_n->gmch_n = link_clock * nlanes;
820 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
821 m_n->link_m = pixel_clock;
822 m_n->link_n = link_clock;
823 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
824}
825
826void
827intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
828 struct drm_display_mode *adjusted_mode)
829{
830 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 831 struct intel_encoder *intel_encoder;
832 struct intel_dp *intel_dp;
a4fc5ed6
KP		 833 struct drm_i915_private *dev_priv = dev->dev_private;
834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 835 int lane_count = 4;
a4fc5ed6 836 struct intel_dp_m_n m_n;
9db4a9c7 837 int pipe = intel_crtc->pipe;
afe2fcf5 838 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
a4fc5ed6
KP		 839
840 /*
21d40d37 841 * Find the lane count in the intel_encoder private
a4fc5ed6 842 */
fa90ecef
PZ		 843 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
844 intel_dp = enc_to_intel_dp(&intel_encoder->base);
a4fc5ed6 845
fa90ecef
PZ		 846 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
847 intel_encoder->type == INTEL_OUTPUT_EDP)
9a10f401 848 {
ea5b213a 849 lane_count = intel_dp->lane_count;
51190667 850 break;
a4fc5ed6
KP		 851 }
852 }
853
854 /*
855 * Compute the GMCH and Link ratios. The '3' here is
856 * the number of bytes_per_pixel post-LUT, which we always
857 * set up for 8-bits of R/G/B, or 3 bytes total.
858 */
858fa035 859 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 860 mode->clock, adjusted_mode->clock, &m_n);
861
1eb8dfec 862 if (IS_HASWELL(dev)) {
afe2fcf5
PZ		 863 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
864 TU_SIZE(m_n.tu) | m_n.gmch_m);
865 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
866 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
867 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
1eb8dfec 868 } else if (HAS_PCH_SPLIT(dev)) {
7346bfa0 869 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 870 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
871 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
872 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
74a4dd2e
VP		 873 } else if (IS_VALLEYVIEW(dev)) {
874 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
875 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
876 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
877 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
a4fc5ed6 878 } else {
9db4a9c7 879 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
7346bfa0 880 TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 881 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
882 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
883 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 884 }
885}
886
247d89f6
PZ		 887void intel_dp_init_link_config(struct intel_dp *intel_dp)
888{
889 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
890 intel_dp->link_configuration[0] = intel_dp->link_bw;
891 intel_dp->link_configuration[1] = intel_dp->lane_count;
892 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
893 /*
894 * Check for DPCD version > 1.1 and enhanced framing support
895 */
896 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
897 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
898 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
899 }
900}
901
ea9b6006
DV		 902static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
903{
904 struct drm_device *dev = crtc->dev;
905 struct drm_i915_private *dev_priv = dev->dev_private;
906 u32 dpa_ctl;
907
908 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
909 dpa_ctl = I915_READ(DP_A);
910 dpa_ctl &= ~DP_PLL_FREQ_MASK;
911
912 if (clock < 200000) {
1ce17038
DV		 913 /* For a long time we've carried around a ILK-DevA w/a for the
914 * 160MHz clock. If we're really unlucky, it's still required.
915 */
916 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 917 dpa_ctl |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 918 } else {
919 dpa_ctl |= DP_PLL_FREQ_270MHZ;
920 }
1ce17038 921
ea9b6006
DV		 922 I915_WRITE(DP_A, dpa_ctl);
923
924 POSTING_READ(DP_A);
925 udelay(500);
926}
927
a4fc5ed6
KP		 928static void
929intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
930 struct drm_display_mode *adjusted_mode)
931{
e3421a18 932 struct drm_device *dev = encoder->dev;
417e822d 933 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 934 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
fa90ecef 935 struct drm_crtc *crtc = encoder->crtc;
a4fc5ed6
KP		 936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
937
417e822d 938 /*
1a2eb460 939 * There are four kinds of DP registers:
417e822d
KP		 940 *
941 * IBX PCH
1a2eb460
KP		 942 * SNB CPU
943 * IVB CPU
417e822d
KP		 944 * CPT PCH
945 *
946 * IBX PCH and CPU are the same for almost everything,
947 * except that the CPU DP PLL is configured in this
948 * register
949 *
950 * CPT PCH is quite different, having many bits moved
951 * to the TRANS_DP_CTL register instead. That
952 * configuration happens (oddly) in ironlake_pch_enable
953 */
9c9e7927 954
417e822d
KP		 955 /* Preserve the BIOS-computed detected bit. This is
956 * supposed to be read-only.
957 */
958 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 959
417e822d 960 /* Handle DP bits in common between all three register formats */
417e822d 961 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 962
ea5b213a 963 switch (intel_dp->lane_count) {
a4fc5ed6 964 case 1:
ea5b213a 965 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 966 break;
967 case 2:
ea5b213a 968 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 969 break;
970 case 4:
ea5b213a 971 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 972 break;
973 }
e0dac65e
WF		 974 if (intel_dp->has_audio) {
975 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
976 pipe_name(intel_crtc->pipe));
ea5b213a 977 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 978 intel_write_eld(encoder, adjusted_mode);
979 }
247d89f6
PZ		 980
981 intel_dp_init_link_config(intel_dp);
a4fc5ed6 982
417e822d 983 /* Split out the IBX/CPU vs CPT settings */
32f9d658 984
19c03924 985 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 986 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
987 intel_dp->DP |= DP_SYNC_HS_HIGH;
988 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
989 intel_dp->DP |= DP_SYNC_VS_HIGH;
990 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
991
992 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
993 intel_dp->DP |= DP_ENHANCED_FRAMING;
994
995 intel_dp->DP |= intel_crtc->pipe << 29;
996
997 /* don't miss out required setting for eDP */
1a2eb460
KP		 998 if (adjusted_mode->clock < 200000)
999 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1000 else
1001 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1002 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 1003 intel_dp->DP |= intel_dp->color_range;
1004
1005 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1006 intel_dp->DP |= DP_SYNC_HS_HIGH;
1007 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1008 intel_dp->DP |= DP_SYNC_VS_HIGH;
1009 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1010
1011 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
1012 intel_dp->DP |= DP_ENHANCED_FRAMING;
1013
1014 if (intel_crtc->pipe == 1)
1015 intel_dp->DP |= DP_PIPEB_SELECT;
1016
1017 if (is_cpu_edp(intel_dp)) {
1018 /* don't miss out required setting for eDP */
417e822d
KP		 1019 if (adjusted_mode->clock < 200000)
1020 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1021 else
1022 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1023 }
1024 } else {
1025 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1026 }
ea9b6006
DV		 1027
1028 if (is_cpu_edp(intel_dp))
1029 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
a4fc5ed6
KP		 1030}
1031
99ea7127
KP		 1032#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1033#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1034
1035#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1036#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1037
1038#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1039#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1040
1041static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1042 u32 mask,
1043 u32 value)
bd943159 1044{
30add22d 1045 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1046 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 1047
99ea7127
KP		 1048 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1049 mask, value,
1050 I915_READ(PCH_PP_STATUS),
1051 I915_READ(PCH_PP_CONTROL));
32ce697c 1052
99ea7127
KP		 1053 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
1054 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1055 I915_READ(PCH_PP_STATUS),
1056 I915_READ(PCH_PP_CONTROL));
32ce697c 1057 }
99ea7127 1058}
32ce697c 1059
99ea7127
KP		 1060static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1061{
1062 DRM_DEBUG_KMS("Wait for panel power on\n");
1063 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1064}
1065
99ea7127
KP		 1066static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1067{
1068 DRM_DEBUG_KMS("Wait for panel power off time\n");
1069 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1070}
1071
1072static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1073{
1074 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1075 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1076}
1077
1078
832dd3c1
KP		 1079/* Read the current pp_control value, unlocking the register if it
1080 * is locked
1081 */
1082
1083static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1084{
1085 u32 control = I915_READ(PCH_PP_CONTROL);
1086
1087 control &= ~PANEL_UNLOCK_MASK;
1088 control |= PANEL_UNLOCK_REGS;
1089 return control;
bd943159
KP		 1090}
1091
82a4d9c0 1092void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1093{
30add22d 1094 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1095 struct drm_i915_private *dev_priv = dev->dev_private;
1096 u32 pp;
1097
97af61f5
KP		 1098 if (!is_edp(intel_dp))
1099 return;
f01eca2e 1100 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1101
bd943159
KP		 1102 WARN(intel_dp->want_panel_vdd,
1103 "eDP VDD already requested on\n");
1104
1105 intel_dp->want_panel_vdd = true;
99ea7127 1106
bd943159
KP		 1107 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1108 DRM_DEBUG_KMS("eDP VDD already on\n");
1109 return;
1110 }
1111
99ea7127
KP		 1112 if (!ironlake_edp_have_panel_power(intel_dp))
1113 ironlake_wait_panel_power_cycle(intel_dp);
1114
832dd3c1 1115 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1116 pp |= EDP_FORCE_VDD;
1117 I915_WRITE(PCH_PP_CONTROL, pp);
1118 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1119 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1120 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1121
1122 /*
1123 * If the panel wasn't on, delay before accessing aux channel
1124 */
1125 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1126 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1127 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1128 }
5d613501
JB		 1129}
1130
bd943159 1131static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1132{
30add22d 1133 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1134 struct drm_i915_private *dev_priv = dev->dev_private;
1135 u32 pp;
1136
bd943159 1137 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1138 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1139 pp &= ~EDP_FORCE_VDD;
1140 I915_WRITE(PCH_PP_CONTROL, pp);
1141 POSTING_READ(PCH_PP_CONTROL);
1142
1143 /* Make sure sequencer is idle before allowing subsequent activity */
1144 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1145 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1146
1147 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1148 }
1149}
5d613501 1150
bd943159
KP		 1151static void ironlake_panel_vdd_work(struct work_struct *__work)
1152{
1153 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1154 struct intel_dp, panel_vdd_work);
30add22d 1155 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1156
627f7675 1157 mutex_lock(&dev->mode_config.mutex);
bd943159 1158 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1159 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1160}
1161
82a4d9c0 1162void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1163{
97af61f5
KP		 1164 if (!is_edp(intel_dp))
1165 return;
5d613501 1166
bd943159
KP		 1167 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1168 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1169
bd943159
KP		 1170 intel_dp->want_panel_vdd = false;
1171
1172 if (sync) {
1173 ironlake_panel_vdd_off_sync(intel_dp);
1174 } else {
1175 /*
1176 * Queue the timer to fire a long
1177 * time from now (relative to the power down delay)
1178 * to keep the panel power up across a sequence of operations
1179 */
1180 schedule_delayed_work(&intel_dp->panel_vdd_work,
1181 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1182 }
5d613501
JB		 1183}
1184
82a4d9c0 1185void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1186{
30add22d 1187 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1188 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1189 u32 pp;
9934c132 1190
97af61f5 1191 if (!is_edp(intel_dp))
bd943159 1192 return;
99ea7127
KP		 1193
1194 DRM_DEBUG_KMS("Turn eDP power on\n");
1195
1196 if (ironlake_edp_have_panel_power(intel_dp)) {
1197 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1198 return;
99ea7127 1199 }
9934c132 1200
99ea7127 1201 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1202
99ea7127 1203 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1204 if (IS_GEN5(dev)) {
1205 /* ILK workaround: disable reset around power sequence */
1206 pp &= ~PANEL_POWER_RESET;
1207 I915_WRITE(PCH_PP_CONTROL, pp);
1208 POSTING_READ(PCH_PP_CONTROL);
1209 }
37c6c9b0 1210
1c0ae80a 1211 pp |= POWER_TARGET_ON;
99ea7127
KP		 1212 if (!IS_GEN5(dev))
1213 pp |= PANEL_POWER_RESET;
1214
9934c132 1215 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1216 POSTING_READ(PCH_PP_CONTROL);
9934c132 1217
99ea7127 1218 ironlake_wait_panel_on(intel_dp);
9934c132 1219
05ce1a49
KP		 1220 if (IS_GEN5(dev)) {
1221 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1222 I915_WRITE(PCH_PP_CONTROL, pp);
1223 POSTING_READ(PCH_PP_CONTROL);
1224 }
9934c132
JB		 1225}
1226
82a4d9c0 1227void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1228{
30add22d 1229 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1230 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1231 u32 pp;
9934c132 1232
97af61f5
KP		 1233 if (!is_edp(intel_dp))
1234 return;
37c6c9b0 1235
99ea7127 1236 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1237
6cb49835 1238 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1239
99ea7127 1240 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1241 /* We need to switch off panel power _and_ force vdd, for otherwise some
1242 * panels get very unhappy and cease to work. */
1243 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1244 I915_WRITE(PCH_PP_CONTROL, pp);
1245 POSTING_READ(PCH_PP_CONTROL);
9934c132 1246
35a38556
DV		 1247 intel_dp->want_panel_vdd = false;
1248
99ea7127 1249 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1250}
1251
d6c50ff8 1252void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1253{
da63a9f2
PZ		 1254 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1255 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1256 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1257 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658
ZW		 1258 u32 pp;
1259
f01eca2e
KP		 1260 if (!is_edp(intel_dp))
1261 return;
1262
28c97730 1263 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1264 /*
1265 * If we enable the backlight right away following a panel power
1266 * on, we may see slight flicker as the panel syncs with the eDP
1267 * link. So delay a bit to make sure the image is solid before
1268 * allowing it to appear.
1269 */
f01eca2e 1270 msleep(intel_dp->backlight_on_delay);
832dd3c1 1271 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1272 pp |= EDP_BLC_ENABLE;
1273 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1274 POSTING_READ(PCH_PP_CONTROL);
035aa3de
DV		 1275
1276 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1277}
1278
d6c50ff8 1279void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1280{
30add22d 1281 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1282 struct drm_i915_private *dev_priv = dev->dev_private;
1283 u32 pp;
1284
f01eca2e
KP		 1285 if (!is_edp(intel_dp))
1286 return;
1287
035aa3de
DV		 1288 intel_panel_disable_backlight(dev);
1289
28c97730 1290 DRM_DEBUG_KMS("\n");
832dd3c1 1291 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1292 pp &= ~EDP_BLC_ENABLE;
1293 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1294 POSTING_READ(PCH_PP_CONTROL);
1295 msleep(intel_dp->backlight_off_delay);
32f9d658 1296}
a4fc5ed6 1297
2bd2ad64 1298static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1299{
da63a9f2
PZ		 1300 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1301 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1302 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1303 struct drm_i915_private *dev_priv = dev->dev_private;
1304 u32 dpa_ctl;
1305
2bd2ad64
DV		 1306 assert_pipe_disabled(dev_priv,
1307 to_intel_crtc(crtc)->pipe);
1308
d240f20f
JB		 1309 DRM_DEBUG_KMS("\n");
1310 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1311 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1312 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1313
1314 /* We don't adjust intel_dp->DP while tearing down the link, to
1315 * facilitate link retraining (e.g. after hotplug). Hence clear all
1316 * enable bits here to ensure that we don't enable too much. */
1317 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1318 intel_dp->DP |= DP_PLL_ENABLE;
1319 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1320 POSTING_READ(DP_A);
1321 udelay(200);
d240f20f
JB		 1322}
1323
2bd2ad64 1324static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1325{
da63a9f2
PZ		 1326 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1327 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1328 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1329 struct drm_i915_private *dev_priv = dev->dev_private;
1330 u32 dpa_ctl;
1331
2bd2ad64
DV		 1332 assert_pipe_disabled(dev_priv,
1333 to_intel_crtc(crtc)->pipe);
1334
d240f20f 1335 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1336 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1337 "dp pll off, should be on\n");
1338 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1339
1340 /* We can't rely on the value tracked for the DP register in
1341 * intel_dp->DP because link_down must not change that (otherwise link
1342 * re-training will fail. */
298b0b39 1343 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1344 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1345 POSTING_READ(DP_A);
d240f20f
JB		 1346 udelay(200);
1347}
1348
c7ad3810 1349/* If the sink supports it, try to set the power state appropriately */
c19b0669 1350void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1351{
1352 int ret, i;
1353
1354 /* Should have a valid DPCD by this point */
1355 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1356 return;
1357
1358 if (mode != DRM_MODE_DPMS_ON) {
1359 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1360 DP_SET_POWER_D3);
1361 if (ret != 1)
1362 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1363 } else {
1364 /*
1365 * When turning on, we need to retry for 1ms to give the sink
1366 * time to wake up.
1367 */
1368 for (i = 0; i < 3; i++) {
1369 ret = intel_dp_aux_native_write_1(intel_dp,
1370 DP_SET_POWER,
1371 DP_SET_POWER_D0);
1372 if (ret == 1)
1373 break;
1374 msleep(1);
1375 }
1376 }
1377}
1378
19d8fe15
DV		 1379static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1380 enum pipe *pipe)
d240f20f 1381{
19d8fe15
DV		 1382 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1383 struct drm_device *dev = encoder->base.dev;
1384 struct drm_i915_private *dev_priv = dev->dev_private;
1385 u32 tmp = I915_READ(intel_dp->output_reg);
1386
1387 if (!(tmp & DP_PORT_EN))
1388 return false;
1389
1390 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1391 *pipe = PORT_TO_PIPE_CPT(tmp);
1392 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1393 *pipe = PORT_TO_PIPE(tmp);
1394 } else {
1395 u32 trans_sel;
1396 u32 trans_dp;
1397 int i;
1398
1399 switch (intel_dp->output_reg) {
1400 case PCH_DP_B:
1401 trans_sel = TRANS_DP_PORT_SEL_B;
1402 break;
1403 case PCH_DP_C:
1404 trans_sel = TRANS_DP_PORT_SEL_C;
1405 break;
1406 case PCH_DP_D:
1407 trans_sel = TRANS_DP_PORT_SEL_D;
1408 break;
1409 default:
1410 return true;
1411 }
1412
1413 for_each_pipe(i) {
1414 trans_dp = I915_READ(TRANS_DP_CTL(i));
1415 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1416 *pipe = i;
1417 return true;
1418 }
1419 }
19d8fe15 1420
4a0833ec
DV		 1421 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1422 intel_dp->output_reg);
1423 }
d240f20f 1424
19d8fe15
DV		 1425 return true;
1426}
d240f20f 1427
e8cb4558 1428static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1429{
e8cb4558 1430 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1431
1432 /* Make sure the panel is off before trying to change the mode. But also
1433 * ensure that we have vdd while we switch off the panel. */
1434 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1435 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1436 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1437 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1438
1439 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1440 if (!is_cpu_edp(intel_dp))
1441 intel_dp_link_down(intel_dp);
d240f20f
JB		 1442}
1443
2bd2ad64 1444static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1445{
2bd2ad64
DV		 1446 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1447
3739850b
DV		 1448 if (is_cpu_edp(intel_dp)) {
1449 intel_dp_link_down(intel_dp);
2bd2ad64 1450 ironlake_edp_pll_off(intel_dp);
3739850b 1451 }
2bd2ad64
DV		 1452}
1453
e8cb4558 1454static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1455{
e8cb4558
DV		 1456 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1457 struct drm_device *dev = encoder->base.dev;
1458 struct drm_i915_private *dev_priv = dev->dev_private;
1459 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1460
0c33d8d7
DV		 1461 if (WARN_ON(dp_reg & DP_PORT_EN))
1462 return;
5d613501 1463
97af61f5 1464 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1465 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1466 intel_dp_start_link_train(intel_dp);
97af61f5 1467 ironlake_edp_panel_on(intel_dp);
bd943159 1468 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1469 intel_dp_complete_link_train(intel_dp);
f01eca2e 1470 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1471}
1472
2bd2ad64 1473static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1474{
2bd2ad64 1475 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 1476
2bd2ad64
DV		 1477 if (is_cpu_edp(intel_dp))
1478 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1479}
1480
1481/*
df0c237d
JB		 1482 * Native read with retry for link status and receiver capability reads for
1483 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1484 */
1485static bool
df0c237d
JB		 1486intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1487 uint8_t *recv, int recv_bytes)
a4fc5ed6 1488{
61da5fab
JB		 1489 int ret, i;
1490
df0c237d
JB		 1491 /*
1492 * Sinks are *supposed* to come up within 1ms from an off state,
1493 * but we're also supposed to retry 3 times per the spec.
1494 */
61da5fab 1495 for (i = 0; i < 3; i++) {
df0c237d
JB		 1496 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1497 recv_bytes);
1498 if (ret == recv_bytes)
61da5fab
JB		 1499 return true;
1500 msleep(1);
1501 }
a4fc5ed6 1502
61da5fab 1503 return false;
a4fc5ed6
KP		 1504}
1505
1506/*
1507 * Fetch AUX CH registers 0x202 - 0x207 which contain
1508 * link status information
1509 */
1510static bool
93f62dad 1511intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1512{
df0c237d
JB		 1513 return intel_dp_aux_native_read_retry(intel_dp,
1514 DP_LANE0_1_STATUS,
93f62dad 1515 link_status,
df0c237d 1516 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1517}
1518
a4fc5ed6
KP		 1519#if 0
1520static char *voltage_names[] = {
1521 "0.4V", "0.6V", "0.8V", "1.2V"
1522};
1523static char *pre_emph_names[] = {
1524 "0dB", "3.5dB", "6dB", "9.5dB"
1525};
1526static char *link_train_names[] = {
1527 "pattern 1", "pattern 2", "idle", "off"
1528};
1529#endif
1530
1531/*
1532 * These are source-specific values; current Intel hardware supports
1533 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1534 */
a4fc5ed6
KP		 1535
1536static uint8_t
1a2eb460 1537intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1538{
30add22d 1539 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460
KP		 1540
1541 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1542 return DP_TRAIN_VOLTAGE_SWING_800;
1543 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1544 return DP_TRAIN_VOLTAGE_SWING_1200;
1545 else
1546 return DP_TRAIN_VOLTAGE_SWING_800;
1547}
1548
1549static uint8_t
1550intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1551{
30add22d 1552 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1553
d6c0d722
PZ		 1554 if (IS_HASWELL(dev)) {
1555 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1556 case DP_TRAIN_VOLTAGE_SWING_400:
1557 return DP_TRAIN_PRE_EMPHASIS_9_5;
1558 case DP_TRAIN_VOLTAGE_SWING_600:
1559 return DP_TRAIN_PRE_EMPHASIS_6;
1560 case DP_TRAIN_VOLTAGE_SWING_800:
1561 return DP_TRAIN_PRE_EMPHASIS_3_5;
1562 case DP_TRAIN_VOLTAGE_SWING_1200:
1563 default:
1564 return DP_TRAIN_PRE_EMPHASIS_0;
1565 }
1566 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1567 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1568 case DP_TRAIN_VOLTAGE_SWING_400:
1569 return DP_TRAIN_PRE_EMPHASIS_6;
1570 case DP_TRAIN_VOLTAGE_SWING_600:
1571 case DP_TRAIN_VOLTAGE_SWING_800:
1572 return DP_TRAIN_PRE_EMPHASIS_3_5;
1573 default:
1574 return DP_TRAIN_PRE_EMPHASIS_0;
1575 }
1576 } else {
1577 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1578 case DP_TRAIN_VOLTAGE_SWING_400:
1579 return DP_TRAIN_PRE_EMPHASIS_6;
1580 case DP_TRAIN_VOLTAGE_SWING_600:
1581 return DP_TRAIN_PRE_EMPHASIS_6;
1582 case DP_TRAIN_VOLTAGE_SWING_800:
1583 return DP_TRAIN_PRE_EMPHASIS_3_5;
1584 case DP_TRAIN_VOLTAGE_SWING_1200:
1585 default:
1586 return DP_TRAIN_PRE_EMPHASIS_0;
1587 }
a4fc5ed6
KP		 1588 }
1589}
1590
1591static void
93f62dad 1592intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1593{
1594 uint8_t v = 0;
1595 uint8_t p = 0;
1596 int lane;
1a2eb460
KP		 1597 uint8_t voltage_max;
1598 uint8_t preemph_max;
a4fc5ed6 1599
33a34e4e 1600 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1601 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1602 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1603
1604 if (this_v > v)
1605 v = this_v;
1606 if (this_p > p)
1607 p = this_p;
1608 }
1609
1a2eb460 1610 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1611 if (v >= voltage_max)
1612 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1613
1a2eb460
KP		 1614 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1615 if (p >= preemph_max)
1616 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1617
1618 for (lane = 0; lane < 4; lane++)
33a34e4e 1619 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1620}
1621
1622static uint32_t
93f62dad 1623intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1624{
3cf2efb1 1625 uint32_t signal_levels = 0;
a4fc5ed6 1626
3cf2efb1 1627 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1628 case DP_TRAIN_VOLTAGE_SWING_400:
1629 default:
1630 signal_levels |= DP_VOLTAGE_0_4;
1631 break;
1632 case DP_TRAIN_VOLTAGE_SWING_600:
1633 signal_levels |= DP_VOLTAGE_0_6;
1634 break;
1635 case DP_TRAIN_VOLTAGE_SWING_800:
1636 signal_levels |= DP_VOLTAGE_0_8;
1637 break;
1638 case DP_TRAIN_VOLTAGE_SWING_1200:
1639 signal_levels |= DP_VOLTAGE_1_2;
1640 break;
1641 }
3cf2efb1 1642 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1643 case DP_TRAIN_PRE_EMPHASIS_0:
1644 default:
1645 signal_levels |= DP_PRE_EMPHASIS_0;
1646 break;
1647 case DP_TRAIN_PRE_EMPHASIS_3_5:
1648 signal_levels |= DP_PRE_EMPHASIS_3_5;
1649 break;
1650 case DP_TRAIN_PRE_EMPHASIS_6:
1651 signal_levels |= DP_PRE_EMPHASIS_6;
1652 break;
1653 case DP_TRAIN_PRE_EMPHASIS_9_5:
1654 signal_levels |= DP_PRE_EMPHASIS_9_5;
1655 break;
1656 }
1657 return signal_levels;
1658}
1659
e3421a18
ZW		 1660/* Gen6's DP voltage swing and pre-emphasis control */
1661static uint32_t
1662intel_gen6_edp_signal_levels(uint8_t train_set)
1663{
3c5a62b5
YL		 1664 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1665 DP_TRAIN_PRE_EMPHASIS_MASK);
1666 switch (signal_levels) {
e3421a18 1667 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1668 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1669 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1670 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1671 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1672 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1673 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1674 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1675 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1676 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1677 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1678 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1679 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1680 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1681 default:
3c5a62b5
YL		 1682 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1683 "0x%x\n", signal_levels);
1684 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1685 }
1686}
1687
1a2eb460
KP		 1688/* Gen7's DP voltage swing and pre-emphasis control */
1689static uint32_t
1690intel_gen7_edp_signal_levels(uint8_t train_set)
1691{
1692 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1693 DP_TRAIN_PRE_EMPHASIS_MASK);
1694 switch (signal_levels) {
1695 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1696 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1697 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1698 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1699 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1700 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1701
1702 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1703 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1704 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1705 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1706
1707 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1708 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1709 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1710 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1711
1712 default:
1713 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1714 "0x%x\n", signal_levels);
1715 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1716 }
1717}
1718
d6c0d722
PZ		 1719/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1720static uint32_t
1721intel_dp_signal_levels_hsw(uint8_t train_set)
a4fc5ed6 1722{
d6c0d722
PZ		 1723 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1724 DP_TRAIN_PRE_EMPHASIS_MASK);
1725 switch (signal_levels) {
1726 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1727 return DDI_BUF_EMP_400MV_0DB_HSW;
1728 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1729 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1730 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1731 return DDI_BUF_EMP_400MV_6DB_HSW;
1732 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1733 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 1734
d6c0d722
PZ		 1735 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1736 return DDI_BUF_EMP_600MV_0DB_HSW;
1737 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1738 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1739 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1740 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 1741
d6c0d722
PZ		 1742 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1743 return DDI_BUF_EMP_800MV_0DB_HSW;
1744 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1745 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1746 default:
1747 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1748 "0x%x\n", signal_levels);
1749 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 1750 }
a4fc5ed6
KP		 1751}
1752
1753static bool
ea5b213a 1754intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1755 uint32_t dp_reg_value,
58e10eb9 1756 uint8_t dp_train_pat)
a4fc5ed6 1757{
174edf1f
PZ		 1758 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1759 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1760 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 1761 enum port port = intel_dig_port->port;
a4fc5ed6 1762 int ret;
d6c0d722 1763 uint32_t temp;
a4fc5ed6 1764
d6c0d722 1765 if (IS_HASWELL(dev)) {
174edf1f 1766 temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 1767
1768 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1769 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1770 else
1771 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1772
1773 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1774 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1775 case DP_TRAINING_PATTERN_DISABLE:
1776 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
174edf1f 1777 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 1778
174edf1f 1779 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
d6c0d722
PZ		 1780 DP_TP_STATUS_IDLE_DONE), 1))
1781 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1782
1783 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1784 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1785
1786 break;
1787 case DP_TRAINING_PATTERN_1:
1788 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1789 break;
1790 case DP_TRAINING_PATTERN_2:
1791 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1792 break;
1793 case DP_TRAINING_PATTERN_3:
1794 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1795 break;
1796 }
174edf1f 1797 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722
PZ		 1798
1799 } else if (HAS_PCH_CPT(dev) &&
1800 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1801 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1802
1803 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1804 case DP_TRAINING_PATTERN_DISABLE:
1805 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1806 break;
1807 case DP_TRAINING_PATTERN_1:
1808 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1809 break;
1810 case DP_TRAINING_PATTERN_2:
1811 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1812 break;
1813 case DP_TRAINING_PATTERN_3:
1814 DRM_ERROR("DP training pattern 3 not supported\n");
1815 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1816 break;
1817 }
1818
1819 } else {
1820 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1821
1822 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1823 case DP_TRAINING_PATTERN_DISABLE:
1824 dp_reg_value |= DP_LINK_TRAIN_OFF;
1825 break;
1826 case DP_TRAINING_PATTERN_1:
1827 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1828 break;
1829 case DP_TRAINING_PATTERN_2:
1830 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1831 break;
1832 case DP_TRAINING_PATTERN_3:
1833 DRM_ERROR("DP training pattern 3 not supported\n");
1834 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1835 break;
1836 }
1837 }
1838
ea5b213a
CW		 1839 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1840 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1841
ea5b213a 1842 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1843 DP_TRAINING_PATTERN_SET,
1844 dp_train_pat);
1845
47ea7542
PZ		 1846 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1847 DP_TRAINING_PATTERN_DISABLE) {
1848 ret = intel_dp_aux_native_write(intel_dp,
1849 DP_TRAINING_LANE0_SET,
1850 intel_dp->train_set,
1851 intel_dp->lane_count);
1852 if (ret != intel_dp->lane_count)
1853 return false;
1854 }
a4fc5ed6
KP		 1855
1856 return true;
1857}
1858
33a34e4e 1859/* Enable corresponding port and start training pattern 1 */
c19b0669 1860void
33a34e4e 1861intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1862{
da63a9f2 1863 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 1864 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 1865 int i;
1866 uint8_t voltage;
1867 bool clock_recovery = false;
cdb0e95b 1868 int voltage_tries, loop_tries;
ea5b213a 1869 uint32_t DP = intel_dp->DP;
a4fc5ed6 1870
affa9354 1871 if (HAS_DDI(dev))
c19b0669
PZ		 1872 intel_ddi_prepare_link_retrain(encoder);
1873
3cf2efb1
CW		 1874 /* Write the link configuration data */
1875 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1876 intel_dp->link_configuration,
1877 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1878
1879 DP |= DP_PORT_EN;
1a2eb460 1880
33a34e4e 1881 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1882 voltage = 0xff;
cdb0e95b
KP		 1883 voltage_tries = 0;
1884 loop_tries = 0;
a4fc5ed6
KP		 1885 clock_recovery = false;
1886 for (;;) {
33a34e4e 1887 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1888 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1889 uint32_t signal_levels;
417e822d 1890
d6c0d722
PZ		 1891 if (IS_HASWELL(dev)) {
1892 signal_levels = intel_dp_signal_levels_hsw(
1893 intel_dp->train_set[0]);
1894 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1895 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1896 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1897 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1898 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1899 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1900 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1901 } else {
93f62dad 1902 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1903 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1904 }
d6c0d722
PZ		 1905 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1906 signal_levels);
a4fc5ed6 1907
a7c9655f 1908 /* Set training pattern 1 */
47ea7542 1909 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1910 DP_TRAINING_PATTERN_1 |
1911 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1912 break;
a4fc5ed6 1913
a7c9655f 1914 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 1915 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1916 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1917 break;
93f62dad 1918 }
a4fc5ed6 1919
01916270 1920 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 1921 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1922 clock_recovery = true;
1923 break;
1924 }
1925
1926 /* Check to see if we've tried the max voltage */
1927 for (i = 0; i < intel_dp->lane_count; i++)
1928 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1929 break;
0d710688 1930 if (i == intel_dp->lane_count && voltage_tries == 5) {
b06fbda3
DV		 1931 ++loop_tries;
1932 if (loop_tries == 5) {
cdb0e95b
KP		 1933 DRM_DEBUG_KMS("too many full retries, give up\n");
1934 break;
1935 }
1936 memset(intel_dp->train_set, 0, 4);
1937 voltage_tries = 0;
1938 continue;
1939 }
a4fc5ed6 1940
3cf2efb1 1941 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 1942 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 1943 ++voltage_tries;
b06fbda3
DV		 1944 if (voltage_tries == 5) {
1945 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1946 break;
1947 }
1948 } else
1949 voltage_tries = 0;
1950 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1951
3cf2efb1 1952 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1953 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1954 }
1955
33a34e4e
JB		 1956 intel_dp->DP = DP;
1957}
1958
c19b0669 1959void
33a34e4e
JB		 1960intel_dp_complete_link_train(struct intel_dp *intel_dp)
1961{
30add22d 1962 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33a34e4e 1963 bool channel_eq = false;
37f80975 1964 int tries, cr_tries;
33a34e4e
JB		 1965 uint32_t DP = intel_dp->DP;
1966
a4fc5ed6
KP		 1967 /* channel equalization */
1968 tries = 0;
37f80975 1969 cr_tries = 0;
a4fc5ed6
KP		 1970 channel_eq = false;
1971 for (;;) {
33a34e4e 1972 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1973 uint32_t signal_levels;
93f62dad 1974 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1975
37f80975
JB		 1976 if (cr_tries > 5) {
1977 DRM_ERROR("failed to train DP, aborting\n");
1978 intel_dp_link_down(intel_dp);
1979 break;
1980 }
1981
d6c0d722
PZ		 1982 if (IS_HASWELL(dev)) {
1983 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1984 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1985 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1986 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1987 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1988 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1989 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1990 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1991 } else {
93f62dad 1992 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1993 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1994 }
1995
a4fc5ed6 1996 /* channel eq pattern */
47ea7542 1997 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1998 DP_TRAINING_PATTERN_2 |
1999 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 2000 break;
2001
a7c9655f 2002 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 2003 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 2004 break;
a4fc5ed6 2005
37f80975 2006 /* Make sure clock is still ok */
01916270 2007 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 2008 intel_dp_start_link_train(intel_dp);
2009 cr_tries++;
2010 continue;
2011 }
2012
1ffdff13 2013 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2014 channel_eq = true;
2015 break;
2016 }
a4fc5ed6 2017
37f80975
JB		 2018 /* Try 5 times, then try clock recovery if that fails */
2019 if (tries > 5) {
2020 intel_dp_link_down(intel_dp);
2021 intel_dp_start_link_train(intel_dp);
2022 tries = 0;
2023 cr_tries++;
2024 continue;
2025 }
a4fc5ed6 2026
3cf2efb1 2027 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2028 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2029 ++tries;
869184a6 2030 }
3cf2efb1 2031
d6c0d722
PZ		 2032 if (channel_eq)
2033 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2034
47ea7542 2035 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2036}
2037
2038static void
ea5b213a 2039intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2040{
da63a9f2
PZ		 2041 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2042 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2043 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 2044 uint32_t DP = intel_dp->DP;
a4fc5ed6 2045
c19b0669
PZ		 2046 /*
2047 * DDI code has a strict mode set sequence and we should try to respect
2048 * it, otherwise we might hang the machine in many different ways. So we
2049 * really should be disabling the port only on a complete crtc_disable
2050 * sequence. This function is just called under two conditions on DDI
2051 * code:
2052 * - Link train failed while doing crtc_enable, and on this case we
2053 * really should respect the mode set sequence and wait for a
2054 * crtc_disable.
2055 * - Someone turned the monitor off and intel_dp_check_link_status
2056 * called us. We don't need to disable the whole port on this case, so
2057 * when someone turns the monitor on again,
2058 * intel_ddi_prepare_link_retrain will take care of redoing the link
2059 * train.
2060 */
affa9354 2061 if (HAS_DDI(dev))
c19b0669
PZ		 2062 return;
2063
0c33d8d7 2064 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2065 return;
2066
28c97730 2067 DRM_DEBUG_KMS("\n");
32f9d658 2068
1a2eb460 2069 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 2070 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2071 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2072 } else {
2073 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2074 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2075 }
fe255d00 2076 POSTING_READ(intel_dp->output_reg);
5eb08b69 2077
fe255d00 2078 msleep(17);
5eb08b69 2079
493a7081 2080 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2081 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2082 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2083
5bddd17f
EA		 2084 /* Hardware workaround: leaving our transcoder select
2085 * set to transcoder B while it's off will prevent the
2086 * corresponding HDMI output on transcoder A.
2087 *
2088 * Combine this with another hardware workaround:
2089 * transcoder select bit can only be cleared while the
2090 * port is enabled.
2091 */
2092 DP &= ~DP_PIPEB_SELECT;
2093 I915_WRITE(intel_dp->output_reg, DP);
2094
2095 /* Changes to enable or select take place the vblank
2096 * after being written.
2097 */
31acbcc4
CW		 2098 if (crtc == NULL) {
2099 /* We can arrive here never having been attached
2100 * to a CRTC, for instance, due to inheriting
2101 * random state from the BIOS.
2102 *
2103 * If the pipe is not running, play safe and
2104 * wait for the clocks to stabilise before
2105 * continuing.
2106 */
2107 POSTING_READ(intel_dp->output_reg);
2108 msleep(50);
2109 } else
2110 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 2111 }
2112
832afda6 2113 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2114 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2115 POSTING_READ(intel_dp->output_reg);
f01eca2e 2116 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2117}
2118
26d61aad
KP		 2119static bool
2120intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2121{
92fd8fd1 2122 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2123 sizeof(intel_dp->dpcd)) == 0)
2124 return false; /* aux transfer failed */
92fd8fd1 2125
edb39244
AJ		 2126 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2127 return false; /* DPCD not present */
2128
2129 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2130 DP_DWN_STRM_PORT_PRESENT))
2131 return true; /* native DP sink */
2132
2133 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2134 return true; /* no per-port downstream info */
2135
2136 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2137 intel_dp->downstream_ports,
2138 DP_MAX_DOWNSTREAM_PORTS) == 0)
2139 return false; /* downstream port status fetch failed */
2140
2141 return true;
92fd8fd1
KP		 2142}
2143
0d198328
AJ		 2144static void
2145intel_dp_probe_oui(struct intel_dp *intel_dp)
2146{
2147 u8 buf[3];
2148
2149 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2150 return;
2151
351cfc34
DV		 2152 ironlake_edp_panel_vdd_on(intel_dp);
2153
0d198328
AJ		 2154 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2155 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2156 buf[0], buf[1], buf[2]);
2157
2158 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2159 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2160 buf[0], buf[1], buf[2]);
351cfc34
DV		 2161
2162 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2163}
2164
a60f0e38
JB		 2165static bool
2166intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2167{
2168 int ret;
2169
2170 ret = intel_dp_aux_native_read_retry(intel_dp,
2171 DP_DEVICE_SERVICE_IRQ_VECTOR,
2172 sink_irq_vector, 1);
2173 if (!ret)
2174 return false;
2175
2176 return true;
2177}
2178
2179static void
2180intel_dp_handle_test_request(struct intel_dp *intel_dp)
2181{
2182 /* NAK by default */
9324cf7f 2183 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2184}
2185
a4fc5ed6
KP		 2186/*
2187 * According to DP spec
2188 * 5.1.2:
2189 * 1. Read DPCD
2190 * 2. Configure link according to Receiver Capabilities
2191 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2192 * 4. Check link status on receipt of hot-plug interrupt
2193 */
2194
00c09d70 2195void
ea5b213a 2196intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2197{
da63a9f2 2198 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2199 u8 sink_irq_vector;
93f62dad 2200 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2201
da63a9f2 2202 if (!intel_encoder->connectors_active)
d2b996ac 2203 return;
59cd09e1 2204
da63a9f2 2205 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2206 return;
2207
92fd8fd1 2208 /* Try to read receiver status if the link appears to be up */
93f62dad 2209 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2210 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2211 return;
2212 }
2213
92fd8fd1 2214 /* Now read the DPCD to see if it's actually running */
26d61aad 2215 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2216 intel_dp_link_down(intel_dp);
2217 return;
2218 }
2219
a60f0e38
JB		 2220 /* Try to read the source of the interrupt */
2221 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2222 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2223 /* Clear interrupt source */
2224 intel_dp_aux_native_write_1(intel_dp,
2225 DP_DEVICE_SERVICE_IRQ_VECTOR,
2226 sink_irq_vector);
2227
2228 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2229 intel_dp_handle_test_request(intel_dp);
2230 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2231 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2232 }
2233
1ffdff13 2234 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2235 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2236 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2237 intel_dp_start_link_train(intel_dp);
2238 intel_dp_complete_link_train(intel_dp);
2239 }
a4fc5ed6 2240}
a4fc5ed6 2241
caf9ab24 2242/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2243static enum drm_connector_status
26d61aad 2244intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2245{
caf9ab24
AJ		 2246 uint8_t *dpcd = intel_dp->dpcd;
2247 bool hpd;
2248 uint8_t type;
2249
2250 if (!intel_dp_get_dpcd(intel_dp))
2251 return connector_status_disconnected;
2252
2253 /* if there's no downstream port, we're done */
2254 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2255 return connector_status_connected;
caf9ab24
AJ		 2256
2257 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2258 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2259 if (hpd) {
23235177 2260 uint8_t reg;
caf9ab24 2261 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2262 &reg, 1))
caf9ab24 2263 return connector_status_unknown;
23235177
AJ		 2264 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2265 : connector_status_disconnected;
caf9ab24
AJ		 2266 }
2267
2268 /* If no HPD, poke DDC gently */
2269 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2270 return connector_status_connected;
caf9ab24
AJ		 2271
2272 /* Well we tried, say unknown for unreliable port types */
2273 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2274 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2275 return connector_status_unknown;
2276
2277 /* Anything else is out of spec, warn and ignore */
2278 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2279 return connector_status_disconnected;
71ba9000
AJ		 2280}
2281
5eb08b69 2282static enum drm_connector_status
a9756bb5 2283ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2284{
30add22d 2285 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5eb08b69
ZW		 2286 enum drm_connector_status status;
2287
fe16d949
CW		 2288 /* Can't disconnect eDP, but you can close the lid... */
2289 if (is_edp(intel_dp)) {
30add22d 2290 status = intel_panel_detect(dev);
fe16d949
CW		 2291 if (status == connector_status_unknown)
2292 status = connector_status_connected;
2293 return status;
2294 }
01cb9ea6 2295
26d61aad 2296 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2297}
2298
a4fc5ed6 2299static enum drm_connector_status
a9756bb5 2300g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2301{
30add22d 2302 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2303 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 2304 uint32_t bit;
5eb08b69 2305
ea5b213a 2306 switch (intel_dp->output_reg) {
a4fc5ed6 2307 case DP_B:
10f76a38 2308 bit = DPB_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2309 break;
2310 case DP_C:
10f76a38 2311 bit = DPC_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2312 break;
2313 case DP_D:
10f76a38 2314 bit = DPD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2315 break;
2316 default:
2317 return connector_status_unknown;
2318 }
2319
10f76a38 2320 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2321 return connector_status_disconnected;
2322
26d61aad 2323 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2324}
2325
8c241fef
KP		 2326static struct edid *
2327intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2328{
9cd300e0 2329 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2330
9cd300e0
JN		 2331 /* use cached edid if we have one */
2332 if (intel_connector->edid) {
2333 struct edid *edid;
2334 int size;
2335
2336 /* invalid edid */
2337 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2338 return NULL;
2339
9cd300e0 2340 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
d6f24d0f
JB		 2341 edid = kmalloc(size, GFP_KERNEL);
2342 if (!edid)
2343 return NULL;
2344
9cd300e0 2345 memcpy(edid, intel_connector->edid, size);
d6f24d0f
JB		 2346 return edid;
2347 }
8c241fef 2348
9cd300e0 2349 return drm_get_edid(connector, adapter);
8c241fef
KP		 2350}
2351
2352static int
2353intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2354{
9cd300e0 2355 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2356
9cd300e0
JN		 2357 /* use cached edid if we have one */
2358 if (intel_connector->edid) {
2359 /* invalid edid */
2360 if (IS_ERR(intel_connector->edid))
2361 return 0;
2362
2363 return intel_connector_update_modes(connector,
2364 intel_connector->edid);
d6f24d0f
JB		 2365 }
2366
9cd300e0 2367 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2368}
2369
2370
a9756bb5
ZW		 2371/**
2372 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2373 *
2374 * \return true if DP port is connected.
2375 * \return false if DP port is disconnected.
2376 */
2377static enum drm_connector_status
2378intel_dp_detect(struct drm_connector *connector, bool force)
2379{
2380 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2381 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2382 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2383 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2384 enum drm_connector_status status;
2385 struct edid *edid = NULL;
898076ed 2386 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
a9756bb5
ZW		 2387
2388 intel_dp->has_audio = false;
2389
2390 if (HAS_PCH_SPLIT(dev))
2391 status = ironlake_dp_detect(intel_dp);
2392 else
2393 status = g4x_dp_detect(intel_dp);
1b9be9d0 2394
898076ed
JN		 2395 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2396 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2397 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
1b9be9d0 2398
a9756bb5
ZW		 2399 if (status != connector_status_connected)
2400 return status;
2401
0d198328
AJ		 2402 intel_dp_probe_oui(intel_dp);
2403
c3e5f67b
DV		 2404 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2405 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2406 } else {
8c241fef 2407 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2408 if (edid) {
2409 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2410 kfree(edid);
2411 }
a9756bb5
ZW		 2412 }
2413
d63885da
PZ		 2414 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2415 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2416 return connector_status_connected;
a4fc5ed6
KP		 2417}
2418
2419static int intel_dp_get_modes(struct drm_connector *connector)
2420{
df0e9248 2421 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2422 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2423 struct drm_device *dev = connector->dev;
32f9d658 2424 int ret;
a4fc5ed6
KP		 2425
2426 /* We should parse the EDID data and find out if it has an audio sink
2427 */
2428
8c241fef 2429 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2430 if (ret)
32f9d658
ZW		 2431 return ret;
2432
f8779fda 2433 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2434 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2435 struct drm_display_mode *mode;
dd06f90e
JN		 2436 mode = drm_mode_duplicate(dev,
2437 intel_connector->panel.fixed_mode);
f8779fda 2438 if (mode) {
32f9d658
ZW		 2439 drm_mode_probed_add(connector, mode);
2440 return 1;
2441 }
2442 }
2443 return 0;
a4fc5ed6
KP		 2444}
2445
1aad7ac0
CW		 2446static bool
2447intel_dp_detect_audio(struct drm_connector *connector)
2448{
2449 struct intel_dp *intel_dp = intel_attached_dp(connector);
2450 struct edid *edid;
2451 bool has_audio = false;
2452
8c241fef 2453 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2454 if (edid) {
2455 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2456 kfree(edid);
2457 }
2458
2459 return has_audio;
2460}
2461
f684960e
CW		 2462static int
2463intel_dp_set_property(struct drm_connector *connector,
2464 struct drm_property *property,
2465 uint64_t val)
2466{
e953fd7b 2467 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2468 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2469 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2470 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2471 int ret;
2472
662595df 2473 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2474 if (ret)
2475 return ret;
2476
3f43c48d 2477 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2478 int i = val;
2479 bool has_audio;
2480
2481 if (i == intel_dp->force_audio)
f684960e
CW		 2482 return 0;
2483
1aad7ac0 2484 intel_dp->force_audio = i;
f684960e 2485
c3e5f67b 2486 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2487 has_audio = intel_dp_detect_audio(connector);
2488 else
c3e5f67b 2489 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2490
2491 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2492 return 0;
2493
1aad7ac0 2494 intel_dp->has_audio = has_audio;
f684960e
CW		 2495 goto done;
2496 }
2497
e953fd7b
CW		 2498 if (property == dev_priv->broadcast_rgb_property) {
2499 if (val == !!intel_dp->color_range)
2500 return 0;
2501
2502 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2503 goto done;
2504 }
2505
53b41837
YN		 2506 if (is_edp(intel_dp) &&
2507 property == connector->dev->mode_config.scaling_mode_property) {
2508 if (val == DRM_MODE_SCALE_NONE) {
2509 DRM_DEBUG_KMS("no scaling not supported\n");
2510 return -EINVAL;
2511 }
2512
2513 if (intel_connector->panel.fitting_mode == val) {
2514 /* the eDP scaling property is not changed */
2515 return 0;
2516 }
2517 intel_connector->panel.fitting_mode = val;
2518
2519 goto done;
2520 }
2521
f684960e
CW		 2522 return -EINVAL;
2523
2524done:
da63a9f2
PZ		 2525 if (intel_encoder->base.crtc) {
2526 struct drm_crtc *crtc = intel_encoder->base.crtc;
a6778b3c
DV		 2527 intel_set_mode(crtc, &crtc->mode,
2528 crtc->x, crtc->y, crtc->fb);
f684960e
CW		 2529 }
2530
2531 return 0;
2532}
2533
a4fc5ed6 2534static void
0206e353 2535intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2536{
aaa6fd2a 2537 struct drm_device *dev = connector->dev;
be3cd5e3 2538 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2539 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2540
9cd300e0
JN		 2541 if (!IS_ERR_OR_NULL(intel_connector->edid))
2542 kfree(intel_connector->edid);
2543
1d508706 2544 if (is_edp(intel_dp)) {
aaa6fd2a 2545 intel_panel_destroy_backlight(dev);
1d508706
JN		 2546 intel_panel_fini(&intel_connector->panel);
2547 }
aaa6fd2a 2548
a4fc5ed6
KP		 2549 drm_sysfs_connector_remove(connector);
2550 drm_connector_cleanup(connector);
55f78c43 2551 kfree(connector);
a4fc5ed6
KP		 2552}
2553
00c09d70 2554void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 2555{
da63a9f2
PZ		 2556 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2557 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927
DV		 2558
2559 i2c_del_adapter(&intel_dp->adapter);
2560 drm_encoder_cleanup(encoder);
bd943159
KP		 2561 if (is_edp(intel_dp)) {
2562 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2563 ironlake_panel_vdd_off_sync(intel_dp);
2564 }
da63a9f2 2565 kfree(intel_dig_port);
24d05927
DV		 2566}
2567
a4fc5ed6 2568static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2569 .mode_fixup = intel_dp_mode_fixup,
a4fc5ed6 2570 .mode_set = intel_dp_mode_set,
1f703855 2571 .disable = intel_encoder_noop,
a4fc5ed6
KP		 2572};
2573
2574static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2575 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2576 .detect = intel_dp_detect,
2577 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2578 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2579 .destroy = intel_dp_destroy,
2580};
2581
2582static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2583 .get_modes = intel_dp_get_modes,
2584 .mode_valid = intel_dp_mode_valid,
df0e9248 2585 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2586};
2587
a4fc5ed6 2588static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2589 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2590};
2591
995b6762 2592static void
21d40d37 2593intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2594{
fa90ecef 2595 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 2596
885a5014 2597 intel_dp_check_link_status(intel_dp);
c8110e52 2598}
6207937d 2599
e3421a18
ZW		 2600/* Return which DP Port should be selected for Transcoder DP control */
2601int
0206e353 2602intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2603{
2604 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 2605 struct intel_encoder *intel_encoder;
2606 struct intel_dp *intel_dp;
e3421a18 2607
fa90ecef
PZ		 2608 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2609 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 2610
fa90ecef
PZ		 2611 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2612 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 2613 return intel_dp->output_reg;
e3421a18 2614 }
ea5b213a 2615
e3421a18
ZW		 2616 return -1;
2617}
2618
36e83a18 2619/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2620bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2621{
2622 struct drm_i915_private *dev_priv = dev->dev_private;
2623 struct child_device_config *p_child;
2624 int i;
2625
2626 if (!dev_priv->child_dev_num)
2627 return false;
2628
2629 for (i = 0; i < dev_priv->child_dev_num; i++) {
2630 p_child = dev_priv->child_dev + i;
2631
2632 if (p_child->dvo_port == PORT_IDPD &&
2633 p_child->device_type == DEVICE_TYPE_eDP)
2634 return true;
2635 }
2636 return false;
2637}
2638
f684960e
CW		 2639static void
2640intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2641{
53b41837
YN		 2642 struct intel_connector *intel_connector = to_intel_connector(connector);
2643
3f43c48d 2644 intel_attach_force_audio_property(connector);
e953fd7b 2645 intel_attach_broadcast_rgb_property(connector);
53b41837
YN		 2646
2647 if (is_edp(intel_dp)) {
2648 drm_mode_create_scaling_mode_property(connector->dev);
2649 drm_connector_attach_property(
2650 connector,
2651 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 2652 DRM_MODE_SCALE_ASPECT);
2653 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 2654 }
f684960e
CW		 2655}
2656
67a54566
DV		 2657static void
2658intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2659 struct intel_dp *intel_dp)
2660{
2661 struct drm_i915_private *dev_priv = dev->dev_private;
2662 struct edp_power_seq cur, vbt, spec, final;
2663 u32 pp_on, pp_off, pp_div, pp;
2664
2665 /* Workaround: Need to write PP_CONTROL with the unlock key as
2666 * the very first thing. */
2667 pp = ironlake_get_pp_control(dev_priv);
2668 I915_WRITE(PCH_PP_CONTROL, pp);
2669
2670 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2671 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2672 pp_div = I915_READ(PCH_PP_DIVISOR);
2673
2674 /* Pull timing values out of registers */
2675 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2676 PANEL_POWER_UP_DELAY_SHIFT;
2677
2678 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2679 PANEL_LIGHT_ON_DELAY_SHIFT;
2680
2681 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2682 PANEL_LIGHT_OFF_DELAY_SHIFT;
2683
2684 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2685 PANEL_POWER_DOWN_DELAY_SHIFT;
2686
2687 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2688 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2689
2690 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2691 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2692
2693 vbt = dev_priv->edp.pps;
2694
2695 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2696 * our hw here, which are all in 100usec. */
2697 spec.t1_t3 = 210 * 10;
2698 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2699 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2700 spec.t10 = 500 * 10;
2701 /* This one is special and actually in units of 100ms, but zero
2702 * based in the hw (so we need to add 100 ms). But the sw vbt
2703 * table multiplies it with 1000 to make it in units of 100usec,
2704 * too. */
2705 spec.t11_t12 = (510 + 100) * 10;
2706
2707 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2708 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2709
2710 /* Use the max of the register settings and vbt. If both are
2711 * unset, fall back to the spec limits. */
2712#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2713 spec.field : \
2714 max(cur.field, vbt.field))
2715 assign_final(t1_t3);
2716 assign_final(t8);
2717 assign_final(t9);
2718 assign_final(t10);
2719 assign_final(t11_t12);
2720#undef assign_final
2721
2722#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2723 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2724 intel_dp->backlight_on_delay = get_delay(t8);
2725 intel_dp->backlight_off_delay = get_delay(t9);
2726 intel_dp->panel_power_down_delay = get_delay(t10);
2727 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2728#undef get_delay
2729
2730 /* And finally store the new values in the power sequencer. */
2731 pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2732 (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2733 pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2734 (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2735 /* Compute the divisor for the pp clock, simply match the Bspec
2736 * formula. */
2737 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2738 << PP_REFERENCE_DIVIDER_SHIFT;
2739 pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
2740 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2741
2742 /* Haswell doesn't have any port selection bits for the panel
2743 * power sequencer any more. */
2744 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2745 if (is_cpu_edp(intel_dp))
2746 pp_on |= PANEL_POWER_PORT_DP_A;
2747 else
2748 pp_on |= PANEL_POWER_PORT_DP_D;
2749 }
2750
2751 I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2752 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2753 I915_WRITE(PCH_PP_DIVISOR, pp_div);
2754
2755
2756 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2757 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2758 intel_dp->panel_power_cycle_delay);
2759
2760 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2761 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2762
2763 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2764 I915_READ(PCH_PP_ON_DELAYS),
2765 I915_READ(PCH_PP_OFF_DELAYS),
2766 I915_READ(PCH_PP_DIVISOR));
f684960e
CW		 2767}
2768
a4fc5ed6 2769void
f0fec3f2
PZ		 2770intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2771 struct intel_connector *intel_connector)
a4fc5ed6 2772{
f0fec3f2
PZ		 2773 struct drm_connector *connector = &intel_connector->base;
2774 struct intel_dp *intel_dp = &intel_dig_port->dp;
2775 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2776 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 2777 struct drm_i915_private *dev_priv = dev->dev_private;
f8779fda 2778 struct drm_display_mode *fixed_mode = NULL;
174edf1f 2779 enum port port = intel_dig_port->port;
5eb08b69 2780 const char *name = NULL;
b329530c 2781 int type;
a4fc5ed6 2782
0767935e
DV		 2783 /* Preserve the current hw state. */
2784 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 2785 intel_dp->attached_connector = intel_connector;
3d3dc149 2786
f0fec3f2 2787 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
b329530c 2788 if (intel_dpd_is_edp(dev))
ea5b213a 2789 intel_dp->is_pch_edp = true;
b329530c 2790
19c03924
GB		 2791 /*
2792 * FIXME : We need to initialize built-in panels before external panels.
2793 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2794 */
f0fec3f2 2795 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
19c03924
GB		 2796 type = DRM_MODE_CONNECTOR_eDP;
2797 intel_encoder->type = INTEL_OUTPUT_EDP;
f0fec3f2 2798 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2799 type = DRM_MODE_CONNECTOR_eDP;
2800 intel_encoder->type = INTEL_OUTPUT_EDP;
2801 } else {
00c09d70
PZ		 2802 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2803 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2804 * rewrite it.
2805 */
b329530c 2806 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c
AJ		 2807 }
2808
b329530c 2809 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2810 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2811
eb1f8e4f 2812 connector->polled = DRM_CONNECTOR_POLL_HPD;
a4fc5ed6
KP		 2813 connector->interlace_allowed = true;
2814 connector->doublescan_allowed = 0;
2815
f0fec3f2
PZ		 2816 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2817 ironlake_panel_vdd_work);
a4fc5ed6 2818
df0e9248 2819 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2820 drm_sysfs_connector_add(connector);
2821
affa9354 2822 if (HAS_DDI(dev))
bcbc889b
PZ		 2823 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2824 else
2825 intel_connector->get_hw_state = intel_connector_get_hw_state;
2826
e8cb4558 2827
a4fc5ed6 2828 /* Set up the DDC bus. */
ab9d7c30
PZ		 2829 switch (port) {
2830 case PORT_A:
2831 name = "DPDDC-A";
2832 break;
2833 case PORT_B:
2834 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2835 name = "DPDDC-B";
2836 break;
2837 case PORT_C:
2838 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2839 name = "DPDDC-C";
2840 break;
2841 case PORT_D:
2842 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2843 name = "DPDDC-D";
2844 break;
2845 default:
2846 WARN(1, "Invalid port %c\n", port_name(port));
2847 break;
5eb08b69
ZW		 2848 }
2849
67a54566
DV		 2850 if (is_edp(intel_dp))
2851 intel_dp_init_panel_power_sequencer(dev, intel_dp);
c1f05264
DA		 2852
2853 intel_dp_i2c_init(intel_dp, intel_connector, name);
2854
67a54566 2855 /* Cache DPCD and EDID for edp. */
c1f05264
DA		 2856 if (is_edp(intel_dp)) {
2857 bool ret;
f8779fda 2858 struct drm_display_mode *scan;
c1f05264 2859 struct edid *edid;
5d613501
JB		 2860
2861 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2862 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2863 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2864
59f3e272 2865 if (ret) {
7183dc29
JB		 2866 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2867 dev_priv->no_aux_handshake =
2868 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2869 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2870 } else {
3d3dc149 2871 /* if this fails, presume the device is a ghost */
48898b03 2872 DRM_INFO("failed to retrieve link info, disabling eDP\n");
fa90ecef
PZ		 2873 intel_dp_encoder_destroy(&intel_encoder->base);
2874 intel_dp_destroy(connector);
3d3dc149 2875 return;
89667383 2876 }
89667383 2877
d6f24d0f
JB		 2878 ironlake_edp_panel_vdd_on(intel_dp);
2879 edid = drm_get_edid(connector, &intel_dp->adapter);
2880 if (edid) {
9cd300e0
JN		 2881 if (drm_add_edid_modes(connector, edid)) {
2882 drm_mode_connector_update_edid_property(connector, edid);
2883 drm_edid_to_eld(connector, edid);
2884 } else {
2885 kfree(edid);
2886 edid = ERR_PTR(-EINVAL);
2887 }
2888 } else {
2889 edid = ERR_PTR(-ENOENT);
d6f24d0f 2890 }
9cd300e0 2891 intel_connector->edid = edid;
f8779fda
JN		 2892
2893 /* prefer fixed mode from EDID if available */
2894 list_for_each_entry(scan, &connector->probed_modes, head) {
2895 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2896 fixed_mode = drm_mode_duplicate(dev, scan);
2897 break;
2898 }
d6f24d0f 2899 }
f8779fda
JN		 2900
2901 /* fallback to VBT if available for eDP */
2902 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2903 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2904 if (fixed_mode)
2905 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2906 }
f8779fda 2907
d6f24d0f
JB		 2908 ironlake_edp_panel_vdd_off(intel_dp, false);
2909 }
552fb0b7 2910
4d926461 2911 if (is_edp(intel_dp)) {
dd06f90e 2912 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 2913 intel_panel_setup_backlight(connector);
32f9d658
ZW		 2914 }
2915
f684960e
CW		 2916 intel_dp_add_properties(intel_dp, connector);
2917
a4fc5ed6
KP		 2918 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2919 * 0xd. Failure to do so will result in spurious interrupts being
2920 * generated on the port when a cable is not attached.
2921 */
2922 if (IS_G4X(dev) && !IS_GM45(dev)) {
2923 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2924 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2925 }
2926}
f0fec3f2
PZ		 2927
2928void
2929intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2930{
2931 struct intel_digital_port *intel_dig_port;
2932 struct intel_encoder *intel_encoder;
2933 struct drm_encoder *encoder;
2934 struct intel_connector *intel_connector;
2935
2936 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2937 if (!intel_dig_port)
2938 return;
2939
2940 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2941 if (!intel_connector) {
2942 kfree(intel_dig_port);
2943 return;
2944 }
2945
2946 intel_encoder = &intel_dig_port->base;
2947 encoder = &intel_encoder->base;
2948
2949 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2950 DRM_MODE_ENCODER_TMDS);
00c09d70 2951 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
f0fec3f2 2952
00c09d70
PZ		 2953 intel_encoder->enable = intel_enable_dp;
2954 intel_encoder->pre_enable = intel_pre_enable_dp;
2955 intel_encoder->disable = intel_disable_dp;
2956 intel_encoder->post_disable = intel_post_disable_dp;
2957 intel_encoder->get_hw_state = intel_dp_get_hw_state;
f0fec3f2 2958
174edf1f 2959 intel_dig_port->port = port;
f0fec3f2
PZ		 2960 intel_dig_port->dp.output_reg = output_reg;
2961
00c09d70 2962 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 2963 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2964 intel_encoder->cloneable = false;
2965 intel_encoder->hot_plug = intel_dp_hot_plug;
2966
2967 intel_dp_init_connector(intel_dig_port, intel_connector);
2968}
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