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drm/i915: fix Haswell DP M/N registers
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
a4fc5ed6
KP		 31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
34#include "drm_crtc_helper.h"
d6f24d0f 35#include "drm_edid.h"
a4fc5ed6
KP		 36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
a4fc5ed6 39
b091cd92 40#define DP_RECEIVER_CAP_SIZE 0xf
a4fc5ed6
KP		 41#define DP_LINK_STATUS_SIZE 6
42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
cfcb0fc9
JB		 44/**
45 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
46 * @intel_dp: DP struct
47 *
48 * If a CPU or PCH DP output is attached to an eDP panel, this function
49 * will return true, and false otherwise.
50 */
51static bool is_edp(struct intel_dp *intel_dp)
52{
53 return intel_dp->base.type == INTEL_OUTPUT_EDP;
54}
55
56/**
57 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
58 * @intel_dp: DP struct
59 *
60 * Returns true if the given DP struct corresponds to a PCH DP port attached
61 * to an eDP panel, false otherwise. Helpful for determining whether we
62 * may need FDI resources for a given DP output or not.
63 */
64static bool is_pch_edp(struct intel_dp *intel_dp)
65{
66 return intel_dp->is_pch_edp;
67}
68
1c95822a
AJ		 69/**
70 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
71 * @intel_dp: DP struct
72 *
73 * Returns true if the given DP struct corresponds to a CPU eDP port.
74 */
75static bool is_cpu_edp(struct intel_dp *intel_dp)
76{
77 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
78}
79
df0e9248
CW		 80static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
81{
82 return container_of(intel_attached_encoder(connector),
83 struct intel_dp, base);
84}
85
814948ad
JB		 86/**
87 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
88 * @encoder: DRM encoder
89 *
90 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
91 * by intel_display.c.
92 */
93bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
94{
95 struct intel_dp *intel_dp;
96
97 if (!encoder)
98 return false;
99
100 intel_dp = enc_to_intel_dp(encoder);
101
102 return is_pch_edp(intel_dp);
103}
104
33a34e4e
JB		 105static void intel_dp_start_link_train(struct intel_dp *intel_dp);
106static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
ea5b213a 107static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 108
32f9d658 109void
0206e353 110intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 111 int *lane_num, int *link_bw)
32f9d658 112{
ea5b213a 113 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 114
ea5b213a
CW		 115 *lane_num = intel_dp->lane_count;
116 if (intel_dp->link_bw == DP_LINK_BW_1_62)
32f9d658 117 *link_bw = 162000;
ea5b213a 118 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
32f9d658
ZW		 119 *link_bw = 270000;
120}
121
94bf2ced
DV		 122int
123intel_edp_target_clock(struct intel_encoder *intel_encoder,
124 struct drm_display_mode *mode)
125{
126 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
127
128 if (intel_dp->panel_fixed_mode)
129 return intel_dp->panel_fixed_mode->clock;
130 else
131 return mode->clock;
132}
133
a4fc5ed6 134static int
ea5b213a 135intel_dp_max_lane_count(struct intel_dp *intel_dp)
a4fc5ed6 136{
9a10f401
KP		 137 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
138 switch (max_lane_count) {
139 case 1: case 2: case 4:
140 break;
141 default:
142 max_lane_count = 4;
a4fc5ed6
KP		 143 }
144 return max_lane_count;
145}
146
147static int
ea5b213a 148intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 149{
7183dc29 150 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 151
152 switch (max_link_bw) {
153 case DP_LINK_BW_1_62:
154 case DP_LINK_BW_2_7:
155 break;
156 default:
157 max_link_bw = DP_LINK_BW_1_62;
158 break;
159 }
160 return max_link_bw;
161}
162
163static int
164intel_dp_link_clock(uint8_t link_bw)
165{
166 if (link_bw == DP_LINK_BW_2_7)
167 return 270000;
168 else
169 return 162000;
170}
171
cd9dde44
AJ		 172/*
173 * The units on the numbers in the next two are... bizarre. Examples will
174 * make it clearer; this one parallels an example in the eDP spec.
175 *
176 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
177 *
178 * 270000 * 1 * 8 / 10 == 216000
179 *
180 * The actual data capacity of that configuration is 2.16Gbit/s, so the
181 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
182 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
183 * 119000. At 18bpp that's 2142000 kilobits per second.
184 *
185 * Thus the strange-looking division by 10 in intel_dp_link_required, to
186 * get the result in decakilobits instead of kilobits.
187 */
188
a4fc5ed6 189static int
c898261c 190intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 191{
cd9dde44 192 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 193}
194
fe27d53e
DA		 195static int
196intel_dp_max_data_rate(int max_link_clock, int max_lanes)
197{
198 return (max_link_clock * max_lanes * 8) / 10;
199}
200
c4867936
DV		 201static bool
202intel_dp_adjust_dithering(struct intel_dp *intel_dp,
203 struct drm_display_mode *mode,
cb1793ce 204 bool adjust_mode)
c4867936
DV		 205{
206 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
207 int max_lanes = intel_dp_max_lane_count(intel_dp);
208 int max_rate, mode_rate;
209
210 mode_rate = intel_dp_link_required(mode->clock, 24);
211 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
212
213 if (mode_rate > max_rate) {
214 mode_rate = intel_dp_link_required(mode->clock, 18);
215 if (mode_rate > max_rate)
216 return false;
217
cb1793ce
DV		 218 if (adjust_mode)
219 mode->private_flags
c4867936
DV		 220 |= INTEL_MODE_DP_FORCE_6BPC;
221
222 return true;
223 }
224
225 return true;
226}
227
a4fc5ed6
KP		 228static int
229intel_dp_mode_valid(struct drm_connector *connector,
230 struct drm_display_mode *mode)
231{
df0e9248 232 struct intel_dp *intel_dp = intel_attached_dp(connector);
a4fc5ed6 233
d15456de
KP		 234 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
235 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
7de56f43
ZY		 236 return MODE_PANEL;
237
d15456de 238 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
7de56f43
ZY		 239 return MODE_PANEL;
240 }
241
cb1793ce 242 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 243 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 244
245 if (mode->clock < 10000)
246 return MODE_CLOCK_LOW;
247
0af78a2b
DV		 248 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
249 return MODE_H_ILLEGAL;
250
a4fc5ed6
KP		 251 return MODE_OK;
252}
253
254static uint32_t
255pack_aux(uint8_t *src, int src_bytes)
256{
257 int i;
258 uint32_t v = 0;
259
260 if (src_bytes > 4)
261 src_bytes = 4;
262 for (i = 0; i < src_bytes; i++)
263 v |= ((uint32_t) src[i]) << ((3-i) * 8);
264 return v;
265}
266
267static void
268unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
269{
270 int i;
271 if (dst_bytes > 4)
272 dst_bytes = 4;
273 for (i = 0; i < dst_bytes; i++)
274 dst[i] = src >> ((3-i) * 8);
275}
276
fb0f8fbf
KP		 277/* hrawclock is 1/4 the FSB frequency */
278static int
279intel_hrawclk(struct drm_device *dev)
280{
281 struct drm_i915_private *dev_priv = dev->dev_private;
282 uint32_t clkcfg;
283
9473c8f4
VP		 284 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
285 if (IS_VALLEYVIEW(dev))
286 return 200;
287
fb0f8fbf
KP		 288 clkcfg = I915_READ(CLKCFG);
289 switch (clkcfg & CLKCFG_FSB_MASK) {
290 case CLKCFG_FSB_400:
291 return 100;
292 case CLKCFG_FSB_533:
293 return 133;
294 case CLKCFG_FSB_667:
295 return 166;
296 case CLKCFG_FSB_800:
297 return 200;
298 case CLKCFG_FSB_1067:
299 return 266;
300 case CLKCFG_FSB_1333:
301 return 333;
302 /* these two are just a guess; one of them might be right */
303 case CLKCFG_FSB_1600:
304 case CLKCFG_FSB_1600_ALT:
305 return 400;
306 default:
307 return 133;
308 }
309}
310
ebf33b18
KP		 311static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
312{
313 struct drm_device *dev = intel_dp->base.base.dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315
316 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
317}
318
319static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
320{
321 struct drm_device *dev = intel_dp->base.base.dev;
322 struct drm_i915_private *dev_priv = dev->dev_private;
323
324 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
325}
326
9b984dae
KP		 327static void
328intel_dp_check_edp(struct intel_dp *intel_dp)
329{
330 struct drm_device *dev = intel_dp->base.base.dev;
331 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 332
9b984dae
KP		 333 if (!is_edp(intel_dp))
334 return;
ebf33b18 335 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 336 WARN(1, "eDP powered off while attempting aux channel communication.\n");
337 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 338 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 339 I915_READ(PCH_PP_CONTROL));
340 }
341}
342
a4fc5ed6 343static int
ea5b213a 344intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 345 uint8_t *send, int send_bytes,
346 uint8_t *recv, int recv_size)
347{
ea5b213a 348 uint32_t output_reg = intel_dp->output_reg;
4ef69c7a 349 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 350 struct drm_i915_private *dev_priv = dev->dev_private;
351 uint32_t ch_ctl = output_reg + 0x10;
352 uint32_t ch_data = ch_ctl + 4;
353 int i;
354 int recv_bytes;
a4fc5ed6 355 uint32_t status;
fb0f8fbf 356 uint32_t aux_clock_divider;
6b4e0a93 357 int try, precharge;
a4fc5ed6 358
750eb99e
PZ		 359 if (IS_HASWELL(dev)) {
360 switch (intel_dp->port) {
361 case PORT_A:
362 ch_ctl = DPA_AUX_CH_CTL;
363 ch_data = DPA_AUX_CH_DATA1;
364 break;
365 case PORT_B:
366 ch_ctl = PCH_DPB_AUX_CH_CTL;
367 ch_data = PCH_DPB_AUX_CH_DATA1;
368 break;
369 case PORT_C:
370 ch_ctl = PCH_DPC_AUX_CH_CTL;
371 ch_data = PCH_DPC_AUX_CH_DATA1;
372 break;
373 case PORT_D:
374 ch_ctl = PCH_DPD_AUX_CH_CTL;
375 ch_data = PCH_DPD_AUX_CH_DATA1;
376 break;
377 default:
378 BUG();
379 }
380 }
381
9b984dae 382 intel_dp_check_edp(intel_dp);
a4fc5ed6 383 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 384 * and would like to run at 2MHz. So, take the
385 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 386 *
387 * Note that PCH attached eDP panels should use a 125MHz input
388 * clock divider.
a4fc5ed6 389 */
1c95822a 390 if (is_cpu_edp(intel_dp)) {
9473c8f4
VP		 391 if (IS_VALLEYVIEW(dev))
392 aux_clock_divider = 100;
393 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 394 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 395 else
396 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
397 } else if (HAS_PCH_SPLIT(dev))
6919132e 398 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 399 else
400 aux_clock_divider = intel_hrawclk(dev) / 2;
401
6b4e0a93
DV		 402 if (IS_GEN6(dev))
403 precharge = 3;
404 else
405 precharge = 5;
406
11bee43e
JB		 407 /* Try to wait for any previous AUX channel activity */
408 for (try = 0; try < 3; try++) {
409 status = I915_READ(ch_ctl);
410 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
411 break;
412 msleep(1);
413 }
414
415 if (try == 3) {
416 WARN(1, "dp_aux_ch not started status 0x%08x\n",
417 I915_READ(ch_ctl));
4f7f7b7e
CW		 418 return -EBUSY;
419 }
420
fb0f8fbf
KP		 421 /* Must try at least 3 times according to DP spec */
422 for (try = 0; try < 5; try++) {
423 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 424 for (i = 0; i < send_bytes; i += 4)
425 I915_WRITE(ch_data + i,
426 pack_aux(send + i, send_bytes - i));
0206e353 427
fb0f8fbf 428 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 429 I915_WRITE(ch_ctl,
430 DP_AUX_CH_CTL_SEND_BUSY |
431 DP_AUX_CH_CTL_TIME_OUT_400us |
432 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
433 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
434 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
435 DP_AUX_CH_CTL_DONE |
436 DP_AUX_CH_CTL_TIME_OUT_ERROR |
437 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 438 for (;;) {
fb0f8fbf
KP		 439 status = I915_READ(ch_ctl);
440 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
441 break;
4f7f7b7e 442 udelay(100);
fb0f8fbf 443 }
0206e353 444
fb0f8fbf 445 /* Clear done status and any errors */
4f7f7b7e
CW		 446 I915_WRITE(ch_ctl,
447 status |
448 DP_AUX_CH_CTL_DONE |
449 DP_AUX_CH_CTL_TIME_OUT_ERROR |
450 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 451
452 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
453 DP_AUX_CH_CTL_RECEIVE_ERROR))
454 continue;
4f7f7b7e 455 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 456 break;
457 }
458
a4fc5ed6 459 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 460 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 461 return -EBUSY;
a4fc5ed6
KP		 462 }
463
464 /* Check for timeout or receive error.
465 * Timeouts occur when the sink is not connected
466 */
a5b3da54 467 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 468 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 469 return -EIO;
470 }
1ae8c0a5
KP		 471
472 /* Timeouts occur when the device isn't connected, so they're
473 * "normal" -- don't fill the kernel log with these */
a5b3da54 474 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 475 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 476 return -ETIMEDOUT;
a4fc5ed6
KP		 477 }
478
479 /* Unload any bytes sent back from the other side */
480 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
481 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 482 if (recv_bytes > recv_size)
483 recv_bytes = recv_size;
0206e353 484
4f7f7b7e
CW		 485 for (i = 0; i < recv_bytes; i += 4)
486 unpack_aux(I915_READ(ch_data + i),
487 recv + i, recv_bytes - i);
a4fc5ed6
KP		 488
489 return recv_bytes;
490}
491
492/* Write data to the aux channel in native mode */
493static int
ea5b213a 494intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 495 uint16_t address, uint8_t *send, int send_bytes)
496{
497 int ret;
498 uint8_t msg[20];
499 int msg_bytes;
500 uint8_t ack;
501
9b984dae 502 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 503 if (send_bytes > 16)
504 return -1;
505 msg[0] = AUX_NATIVE_WRITE << 4;
506 msg[1] = address >> 8;
eebc863e 507 msg[2] = address & 0xff;
a4fc5ed6
KP		 508 msg[3] = send_bytes - 1;
509 memcpy(&msg[4], send, send_bytes);
510 msg_bytes = send_bytes + 4;
511 for (;;) {
ea5b213a 512 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 513 if (ret < 0)
514 return ret;
515 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
516 break;
517 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
518 udelay(100);
519 else
a5b3da54 520 return -EIO;
a4fc5ed6
KP		 521 }
522 return send_bytes;
523}
524
525/* Write a single byte to the aux channel in native mode */
526static int
ea5b213a 527intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 528 uint16_t address, uint8_t byte)
529{
ea5b213a 530 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 531}
532
533/* read bytes from a native aux channel */
534static int
ea5b213a 535intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 536 uint16_t address, uint8_t *recv, int recv_bytes)
537{
538 uint8_t msg[4];
539 int msg_bytes;
540 uint8_t reply[20];
541 int reply_bytes;
542 uint8_t ack;
543 int ret;
544
9b984dae 545 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 546 msg[0] = AUX_NATIVE_READ << 4;
547 msg[1] = address >> 8;
548 msg[2] = address & 0xff;
549 msg[3] = recv_bytes - 1;
550
551 msg_bytes = 4;
552 reply_bytes = recv_bytes + 1;
553
554 for (;;) {
ea5b213a 555 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 556 reply, reply_bytes);
a5b3da54
KP		 557 if (ret == 0)
558 return -EPROTO;
559 if (ret < 0)
a4fc5ed6
KP		 560 return ret;
561 ack = reply[0];
562 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
563 memcpy(recv, reply + 1, ret - 1);
564 return ret - 1;
565 }
566 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
567 udelay(100);
568 else
a5b3da54 569 return -EIO;
a4fc5ed6
KP		 570 }
571}
572
573static int
ab2c0672
DA		 574intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
575 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 576{
ab2c0672 577 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 578 struct intel_dp *intel_dp = container_of(adapter,
579 struct intel_dp,
580 adapter);
ab2c0672
DA		 581 uint16_t address = algo_data->address;
582 uint8_t msg[5];
583 uint8_t reply[2];
8316f337 584 unsigned retry;
ab2c0672
DA		 585 int msg_bytes;
586 int reply_bytes;
587 int ret;
588
9b984dae 589 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 590 /* Set up the command byte */
591 if (mode & MODE_I2C_READ)
592 msg[0] = AUX_I2C_READ << 4;
593 else
594 msg[0] = AUX_I2C_WRITE << 4;
595
596 if (!(mode & MODE_I2C_STOP))
597 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 598
ab2c0672
DA		 599 msg[1] = address >> 8;
600 msg[2] = address;
601
602 switch (mode) {
603 case MODE_I2C_WRITE:
604 msg[3] = 0;
605 msg[4] = write_byte;
606 msg_bytes = 5;
607 reply_bytes = 1;
608 break;
609 case MODE_I2C_READ:
610 msg[3] = 0;
611 msg_bytes = 4;
612 reply_bytes = 2;
613 break;
614 default:
615 msg_bytes = 3;
616 reply_bytes = 1;
617 break;
618 }
619
8316f337
DF		 620 for (retry = 0; retry < 5; retry++) {
621 ret = intel_dp_aux_ch(intel_dp,
622 msg, msg_bytes,
623 reply, reply_bytes);
ab2c0672 624 if (ret < 0) {
3ff99164 625 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 626 return ret;
627 }
8316f337
DF		 628
629 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
630 case AUX_NATIVE_REPLY_ACK:
631 /* I2C-over-AUX Reply field is only valid
632 * when paired with AUX ACK.
633 */
634 break;
635 case AUX_NATIVE_REPLY_NACK:
636 DRM_DEBUG_KMS("aux_ch native nack\n");
637 return -EREMOTEIO;
638 case AUX_NATIVE_REPLY_DEFER:
639 udelay(100);
640 continue;
641 default:
642 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
643 reply[0]);
644 return -EREMOTEIO;
645 }
646
ab2c0672
DA		 647 switch (reply[0] & AUX_I2C_REPLY_MASK) {
648 case AUX_I2C_REPLY_ACK:
649 if (mode == MODE_I2C_READ) {
650 *read_byte = reply[1];
651 }
652 return reply_bytes - 1;
653 case AUX_I2C_REPLY_NACK:
8316f337 654 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 655 return -EREMOTEIO;
656 case AUX_I2C_REPLY_DEFER:
8316f337 657 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 658 udelay(100);
659 break;
660 default:
8316f337 661 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 662 return -EREMOTEIO;
663 }
664 }
8316f337
DF		 665
666 DRM_ERROR("too many retries, giving up\n");
667 return -EREMOTEIO;
a4fc5ed6
KP		 668}
669
0b5c541b 670static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
bd943159 671static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0b5c541b 672
a4fc5ed6 673static int
ea5b213a 674intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 675 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 676{
0b5c541b
KP		 677 int ret;
678
d54e9d28 679 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 680 intel_dp->algo.running = false;
681 intel_dp->algo.address = 0;
682 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
683
0206e353 684 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 685 intel_dp->adapter.owner = THIS_MODULE;
686 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 687 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 688 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
689 intel_dp->adapter.algo_data = &intel_dp->algo;
690 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
691
0b5c541b
KP		 692 ironlake_edp_panel_vdd_on(intel_dp);
693 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 694 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 695 return ret;
a4fc5ed6
KP		 696}
697
698static bool
e811f5ae
LP		 699intel_dp_mode_fixup(struct drm_encoder *encoder,
700 const struct drm_display_mode *mode,
a4fc5ed6
KP		 701 struct drm_display_mode *adjusted_mode)
702{
0d3a1bee 703 struct drm_device *dev = encoder->dev;
ea5b213a 704 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
a4fc5ed6 705 int lane_count, clock;
ea5b213a
CW		 706 int max_lane_count = intel_dp_max_lane_count(intel_dp);
707 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 708 int bpp, mode_rate;
a4fc5ed6
KP		 709 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
710
d15456de
KP		 711 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
712 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
1d8e1c75
CW		 713 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
714 mode, adjusted_mode);
0d3a1bee
ZY		 715 }
716
cb1793ce 717 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 718 return false;
719
083f9560
DV		 720 DRM_DEBUG_KMS("DP link computation with max lane count %i "
721 "max bw %02x pixel clock %iKHz\n",
71244653 722 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 723
cb1793ce 724 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 725 return false;
726
727 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
71244653 728 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 729
2514bc51
JB		 730 for (clock = 0; clock <= max_clock; clock++) {
731 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
fe27d53e 732 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 733
083f9560 734 if (mode_rate <= link_avail) {
ea5b213a
CW		 735 intel_dp->link_bw = bws[clock];
736 intel_dp->lane_count = lane_count;
737 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
083f9560
DV		 738 DRM_DEBUG_KMS("DP link bw %02x lane "
739 "count %d clock %d bpp %d\n",
ea5b213a 740 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 741 adjusted_mode->clock, bpp);
742 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
743 mode_rate, link_avail);
a4fc5ed6
KP		 744 return true;
745 }
746 }
747 }
fe27d53e 748
a4fc5ed6
KP		 749 return false;
750}
751
752struct intel_dp_m_n {
753 uint32_t tu;
754 uint32_t gmch_m;
755 uint32_t gmch_n;
756 uint32_t link_m;
757 uint32_t link_n;
758};
759
760static void
761intel_reduce_ratio(uint32_t *num, uint32_t *den)
762{
763 while (*num > 0xffffff || *den > 0xffffff) {
764 *num >>= 1;
765 *den >>= 1;
766 }
767}
768
769static void
36e83a18 770intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 771 int nlanes,
772 int pixel_clock,
773 int link_clock,
774 struct intel_dp_m_n *m_n)
775{
776 m_n->tu = 64;
36e83a18 777 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 778 m_n->gmch_n = link_clock * nlanes;
779 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
780 m_n->link_m = pixel_clock;
781 m_n->link_n = link_clock;
782 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
783}
784
785void
786intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
787 struct drm_display_mode *adjusted_mode)
788{
789 struct drm_device *dev = crtc->dev;
6c2b7c12 790 struct intel_encoder *encoder;
a4fc5ed6
KP		 791 struct drm_i915_private *dev_priv = dev->dev_private;
792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 793 int lane_count = 4;
a4fc5ed6 794 struct intel_dp_m_n m_n;
9db4a9c7 795 int pipe = intel_crtc->pipe;
a4fc5ed6
KP		 796
797 /*
21d40d37 798 * Find the lane count in the intel_encoder private
a4fc5ed6 799 */
6c2b7c12
DV		 800 for_each_encoder_on_crtc(dev, crtc, encoder) {
801 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 802
9a10f401
KP		 803 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
804 intel_dp->base.type == INTEL_OUTPUT_EDP)
805 {
ea5b213a 806 lane_count = intel_dp->lane_count;
51190667 807 break;
a4fc5ed6
KP		 808 }
809 }
810
811 /*
812 * Compute the GMCH and Link ratios. The '3' here is
813 * the number of bytes_per_pixel post-LUT, which we always
814 * set up for 8-bits of R/G/B, or 3 bytes total.
815 */
858fa035 816 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 817 mode->clock, adjusted_mode->clock, &m_n);
818
1eb8dfec
PZ		 819 if (IS_HASWELL(dev)) {
820 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
821 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
822 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
823 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
824 } else if (HAS_PCH_SPLIT(dev)) {
7346bfa0 825 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 826 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
827 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
828 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
74a4dd2e
VP		 829 } else if (IS_VALLEYVIEW(dev)) {
830 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
831 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
832 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
833 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
a4fc5ed6 834 } else {
9db4a9c7 835 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
7346bfa0 836 TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 837 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
838 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
839 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 840 }
841}
842
247d89f6
PZ		 843void intel_dp_init_link_config(struct intel_dp *intel_dp)
844{
845 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
846 intel_dp->link_configuration[0] = intel_dp->link_bw;
847 intel_dp->link_configuration[1] = intel_dp->lane_count;
848 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
849 /*
850 * Check for DPCD version > 1.1 and enhanced framing support
851 */
852 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
853 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
854 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
855 }
856}
857
a4fc5ed6
KP		 858static void
859intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
860 struct drm_display_mode *adjusted_mode)
861{
e3421a18 862 struct drm_device *dev = encoder->dev;
417e822d 863 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 864 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4ef69c7a 865 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a4fc5ed6
KP		 866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
867
417e822d 868 /*
1a2eb460 869 * There are four kinds of DP registers:
417e822d
KP		 870 *
871 * IBX PCH
1a2eb460
KP		 872 * SNB CPU
873 * IVB CPU
417e822d
KP		 874 * CPT PCH
875 *
876 * IBX PCH and CPU are the same for almost everything,
877 * except that the CPU DP PLL is configured in this
878 * register
879 *
880 * CPT PCH is quite different, having many bits moved
881 * to the TRANS_DP_CTL register instead. That
882 * configuration happens (oddly) in ironlake_pch_enable
883 */
9c9e7927 884
417e822d
KP		 885 /* Preserve the BIOS-computed detected bit. This is
886 * supposed to be read-only.
887 */
888 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 889
417e822d 890 /* Handle DP bits in common between all three register formats */
417e822d 891 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 892
ea5b213a 893 switch (intel_dp->lane_count) {
a4fc5ed6 894 case 1:
ea5b213a 895 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 896 break;
897 case 2:
ea5b213a 898 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 899 break;
900 case 4:
ea5b213a 901 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 902 break;
903 }
e0dac65e
WF		 904 if (intel_dp->has_audio) {
905 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
906 pipe_name(intel_crtc->pipe));
ea5b213a 907 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 908 intel_write_eld(encoder, adjusted_mode);
909 }
247d89f6
PZ		 910
911 intel_dp_init_link_config(intel_dp);
a4fc5ed6 912
417e822d 913 /* Split out the IBX/CPU vs CPT settings */
32f9d658 914
19c03924 915 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 916 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
917 intel_dp->DP |= DP_SYNC_HS_HIGH;
918 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
919 intel_dp->DP |= DP_SYNC_VS_HIGH;
920 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
921
922 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
923 intel_dp->DP |= DP_ENHANCED_FRAMING;
924
925 intel_dp->DP |= intel_crtc->pipe << 29;
926
927 /* don't miss out required setting for eDP */
1a2eb460
KP		 928 if (adjusted_mode->clock < 200000)
929 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
930 else
931 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
932 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 933 intel_dp->DP |= intel_dp->color_range;
934
935 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
936 intel_dp->DP |= DP_SYNC_HS_HIGH;
937 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
938 intel_dp->DP |= DP_SYNC_VS_HIGH;
939 intel_dp->DP |= DP_LINK_TRAIN_OFF;
940
941 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
942 intel_dp->DP |= DP_ENHANCED_FRAMING;
943
944 if (intel_crtc->pipe == 1)
945 intel_dp->DP |= DP_PIPEB_SELECT;
946
947 if (is_cpu_edp(intel_dp)) {
948 /* don't miss out required setting for eDP */
417e822d
KP		 949 if (adjusted_mode->clock < 200000)
950 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
951 else
952 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
953 }
954 } else {
955 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 956 }
a4fc5ed6
KP		 957}
958
99ea7127
KP		 959#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
960#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
961
962#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
963#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
964
965#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
966#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
967
968static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
969 u32 mask,
970 u32 value)
bd943159 971{
99ea7127
KP		 972 struct drm_device *dev = intel_dp->base.base.dev;
973 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 974
99ea7127
KP		 975 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
976 mask, value,
977 I915_READ(PCH_PP_STATUS),
978 I915_READ(PCH_PP_CONTROL));
32ce697c 979
99ea7127
KP		 980 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
981 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
982 I915_READ(PCH_PP_STATUS),
983 I915_READ(PCH_PP_CONTROL));
32ce697c 984 }
99ea7127 985}
32ce697c 986
99ea7127
KP		 987static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
988{
989 DRM_DEBUG_KMS("Wait for panel power on\n");
990 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 991}
992
99ea7127
KP		 993static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
994{
995 DRM_DEBUG_KMS("Wait for panel power off time\n");
996 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
997}
998
999static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1000{
1001 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1002 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1003}
1004
1005
832dd3c1
KP		 1006/* Read the current pp_control value, unlocking the register if it
1007 * is locked
1008 */
1009
1010static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1011{
1012 u32 control = I915_READ(PCH_PP_CONTROL);
1013
1014 control &= ~PANEL_UNLOCK_MASK;
1015 control |= PANEL_UNLOCK_REGS;
1016 return control;
bd943159
KP		 1017}
1018
5d613501
JB		 1019static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1020{
1021 struct drm_device *dev = intel_dp->base.base.dev;
1022 struct drm_i915_private *dev_priv = dev->dev_private;
1023 u32 pp;
1024
97af61f5
KP		 1025 if (!is_edp(intel_dp))
1026 return;
f01eca2e 1027 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1028
bd943159
KP		 1029 WARN(intel_dp->want_panel_vdd,
1030 "eDP VDD already requested on\n");
1031
1032 intel_dp->want_panel_vdd = true;
99ea7127 1033
bd943159
KP		 1034 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1035 DRM_DEBUG_KMS("eDP VDD already on\n");
1036 return;
1037 }
1038
99ea7127
KP		 1039 if (!ironlake_edp_have_panel_power(intel_dp))
1040 ironlake_wait_panel_power_cycle(intel_dp);
1041
832dd3c1 1042 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1043 pp |= EDP_FORCE_VDD;
1044 I915_WRITE(PCH_PP_CONTROL, pp);
1045 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1046 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1047 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1048
1049 /*
1050 * If the panel wasn't on, delay before accessing aux channel
1051 */
1052 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1053 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1054 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1055 }
5d613501
JB		 1056}
1057
bd943159 1058static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501
JB		 1059{
1060 struct drm_device *dev = intel_dp->base.base.dev;
1061 struct drm_i915_private *dev_priv = dev->dev_private;
1062 u32 pp;
1063
bd943159 1064 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1065 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1066 pp &= ~EDP_FORCE_VDD;
1067 I915_WRITE(PCH_PP_CONTROL, pp);
1068 POSTING_READ(PCH_PP_CONTROL);
1069
1070 /* Make sure sequencer is idle before allowing subsequent activity */
1071 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1072 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1073
1074 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1075 }
1076}
5d613501 1077
bd943159
KP		 1078static void ironlake_panel_vdd_work(struct work_struct *__work)
1079{
1080 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1081 struct intel_dp, panel_vdd_work);
1082 struct drm_device *dev = intel_dp->base.base.dev;
1083
627f7675 1084 mutex_lock(&dev->mode_config.mutex);
bd943159 1085 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1086 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1087}
1088
1089static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1090{
97af61f5
KP		 1091 if (!is_edp(intel_dp))
1092 return;
5d613501 1093
bd943159
KP		 1094 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1095 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1096
bd943159
KP		 1097 intel_dp->want_panel_vdd = false;
1098
1099 if (sync) {
1100 ironlake_panel_vdd_off_sync(intel_dp);
1101 } else {
1102 /*
1103 * Queue the timer to fire a long
1104 * time from now (relative to the power down delay)
1105 * to keep the panel power up across a sequence of operations
1106 */
1107 schedule_delayed_work(&intel_dp->panel_vdd_work,
1108 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1109 }
5d613501
JB		 1110}
1111
86a3073e 1112static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1113{
01cb9ea6 1114 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1115 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1116 u32 pp;
9934c132 1117
97af61f5 1118 if (!is_edp(intel_dp))
bd943159 1119 return;
99ea7127
KP		 1120
1121 DRM_DEBUG_KMS("Turn eDP power on\n");
1122
1123 if (ironlake_edp_have_panel_power(intel_dp)) {
1124 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1125 return;
99ea7127 1126 }
9934c132 1127
99ea7127 1128 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1129
99ea7127 1130 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1131 if (IS_GEN5(dev)) {
1132 /* ILK workaround: disable reset around power sequence */
1133 pp &= ~PANEL_POWER_RESET;
1134 I915_WRITE(PCH_PP_CONTROL, pp);
1135 POSTING_READ(PCH_PP_CONTROL);
1136 }
37c6c9b0 1137
1c0ae80a 1138 pp |= POWER_TARGET_ON;
99ea7127
KP		 1139 if (!IS_GEN5(dev))
1140 pp |= PANEL_POWER_RESET;
1141
9934c132 1142 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1143 POSTING_READ(PCH_PP_CONTROL);
9934c132 1144
99ea7127 1145 ironlake_wait_panel_on(intel_dp);
9934c132 1146
05ce1a49
KP		 1147 if (IS_GEN5(dev)) {
1148 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1149 I915_WRITE(PCH_PP_CONTROL, pp);
1150 POSTING_READ(PCH_PP_CONTROL);
1151 }
9934c132
JB		 1152}
1153
99ea7127 1154static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1155{
99ea7127 1156 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1157 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1158 u32 pp;
9934c132 1159
97af61f5
KP		 1160 if (!is_edp(intel_dp))
1161 return;
37c6c9b0 1162
99ea7127 1163 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1164
6cb49835 1165 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1166
99ea7127 1167 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1168 /* We need to switch off panel power _and_ force vdd, for otherwise some
1169 * panels get very unhappy and cease to work. */
1170 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1171 I915_WRITE(PCH_PP_CONTROL, pp);
1172 POSTING_READ(PCH_PP_CONTROL);
9934c132 1173
35a38556
DV		 1174 intel_dp->want_panel_vdd = false;
1175
99ea7127 1176 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1177}
1178
86a3073e 1179static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1180{
f01eca2e 1181 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1182 struct drm_i915_private *dev_priv = dev->dev_private;
1183 u32 pp;
1184
f01eca2e
KP		 1185 if (!is_edp(intel_dp))
1186 return;
1187
28c97730 1188 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1189 /*
1190 * If we enable the backlight right away following a panel power
1191 * on, we may see slight flicker as the panel syncs with the eDP
1192 * link. So delay a bit to make sure the image is solid before
1193 * allowing it to appear.
1194 */
f01eca2e 1195 msleep(intel_dp->backlight_on_delay);
832dd3c1 1196 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1197 pp |= EDP_BLC_ENABLE;
1198 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1199 POSTING_READ(PCH_PP_CONTROL);
32f9d658
ZW		 1200}
1201
86a3073e 1202static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1203{
f01eca2e 1204 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1205 struct drm_i915_private *dev_priv = dev->dev_private;
1206 u32 pp;
1207
f01eca2e
KP		 1208 if (!is_edp(intel_dp))
1209 return;
1210
28c97730 1211 DRM_DEBUG_KMS("\n");
832dd3c1 1212 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1213 pp &= ~EDP_BLC_ENABLE;
1214 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1215 POSTING_READ(PCH_PP_CONTROL);
1216 msleep(intel_dp->backlight_off_delay);
32f9d658 1217}
a4fc5ed6 1218
2bd2ad64 1219static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1220{
2bd2ad64
DV		 1221 struct drm_device *dev = intel_dp->base.base.dev;
1222 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1223 struct drm_i915_private *dev_priv = dev->dev_private;
1224 u32 dpa_ctl;
1225
2bd2ad64
DV		 1226 assert_pipe_disabled(dev_priv,
1227 to_intel_crtc(crtc)->pipe);
1228
d240f20f
JB		 1229 DRM_DEBUG_KMS("\n");
1230 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1231 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1232 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1233
1234 /* We don't adjust intel_dp->DP while tearing down the link, to
1235 * facilitate link retraining (e.g. after hotplug). Hence clear all
1236 * enable bits here to ensure that we don't enable too much. */
1237 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1238 intel_dp->DP |= DP_PLL_ENABLE;
1239 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1240 POSTING_READ(DP_A);
1241 udelay(200);
d240f20f
JB		 1242}
1243
2bd2ad64 1244static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1245{
2bd2ad64
DV		 1246 struct drm_device *dev = intel_dp->base.base.dev;
1247 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1248 struct drm_i915_private *dev_priv = dev->dev_private;
1249 u32 dpa_ctl;
1250
2bd2ad64
DV		 1251 assert_pipe_disabled(dev_priv,
1252 to_intel_crtc(crtc)->pipe);
1253
d240f20f 1254 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1255 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1256 "dp pll off, should be on\n");
1257 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1258
1259 /* We can't rely on the value tracked for the DP register in
1260 * intel_dp->DP because link_down must not change that (otherwise link
1261 * re-training will fail. */
298b0b39 1262 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1263 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1264 POSTING_READ(DP_A);
d240f20f
JB		 1265 udelay(200);
1266}
1267
c7ad3810
JB		 1268/* If the sink supports it, try to set the power state appropriately */
1269static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1270{
1271 int ret, i;
1272
1273 /* Should have a valid DPCD by this point */
1274 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1275 return;
1276
1277 if (mode != DRM_MODE_DPMS_ON) {
1278 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1279 DP_SET_POWER_D3);
1280 if (ret != 1)
1281 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1282 } else {
1283 /*
1284 * When turning on, we need to retry for 1ms to give the sink
1285 * time to wake up.
1286 */
1287 for (i = 0; i < 3; i++) {
1288 ret = intel_dp_aux_native_write_1(intel_dp,
1289 DP_SET_POWER,
1290 DP_SET_POWER_D0);
1291 if (ret == 1)
1292 break;
1293 msleep(1);
1294 }
1295 }
1296}
1297
19d8fe15
DV		 1298static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1299 enum pipe *pipe)
d240f20f 1300{
19d8fe15
DV		 1301 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1302 struct drm_device *dev = encoder->base.dev;
1303 struct drm_i915_private *dev_priv = dev->dev_private;
1304 u32 tmp = I915_READ(intel_dp->output_reg);
1305
1306 if (!(tmp & DP_PORT_EN))
1307 return false;
1308
1309 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1310 *pipe = PORT_TO_PIPE_CPT(tmp);
1311 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1312 *pipe = PORT_TO_PIPE(tmp);
1313 } else {
1314 u32 trans_sel;
1315 u32 trans_dp;
1316 int i;
1317
1318 switch (intel_dp->output_reg) {
1319 case PCH_DP_B:
1320 trans_sel = TRANS_DP_PORT_SEL_B;
1321 break;
1322 case PCH_DP_C:
1323 trans_sel = TRANS_DP_PORT_SEL_C;
1324 break;
1325 case PCH_DP_D:
1326 trans_sel = TRANS_DP_PORT_SEL_D;
1327 break;
1328 default:
1329 return true;
1330 }
1331
1332 for_each_pipe(i) {
1333 trans_dp = I915_READ(TRANS_DP_CTL(i));
1334 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1335 *pipe = i;
1336 return true;
1337 }
1338 }
1339 }
1340
1341 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
d240f20f 1342
19d8fe15
DV		 1343 return true;
1344}
1345
e8cb4558 1346static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1347{
e8cb4558 1348 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1349
1350 /* Make sure the panel is off before trying to change the mode. But also
1351 * ensure that we have vdd while we switch off the panel. */
1352 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1353 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1354 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1355 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1356
1357 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1358 if (!is_cpu_edp(intel_dp))
1359 intel_dp_link_down(intel_dp);
d240f20f
JB		 1360}
1361
2bd2ad64
DV		 1362static void intel_post_disable_dp(struct intel_encoder *encoder)
1363{
1364 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1365
3739850b
DV		 1366 if (is_cpu_edp(intel_dp)) {
1367 intel_dp_link_down(intel_dp);
2bd2ad64 1368 ironlake_edp_pll_off(intel_dp);
3739850b 1369 }
2bd2ad64
DV		 1370}
1371
e8cb4558 1372static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1373{
e8cb4558
DV		 1374 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1375 struct drm_device *dev = encoder->base.dev;
1376 struct drm_i915_private *dev_priv = dev->dev_private;
1377 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1378
0c33d8d7
DV		 1379 if (WARN_ON(dp_reg & DP_PORT_EN))
1380 return;
1381
97af61f5 1382 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1383 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
0c33d8d7
DV		 1384 intel_dp_start_link_train(intel_dp);
1385 ironlake_edp_panel_on(intel_dp);
1386 ironlake_edp_panel_vdd_off(intel_dp, true);
1387 intel_dp_complete_link_train(intel_dp);
f01eca2e 1388 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1389}
1390
2bd2ad64 1391static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1392{
2bd2ad64 1393 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0a91ca29 1394
2bd2ad64
DV		 1395 if (is_cpu_edp(intel_dp))
1396 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1397}
1398
1399/*
df0c237d
JB		 1400 * Native read with retry for link status and receiver capability reads for
1401 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1402 */
1403static bool
df0c237d
JB		 1404intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1405 uint8_t *recv, int recv_bytes)
a4fc5ed6 1406{
61da5fab
JB		 1407 int ret, i;
1408
df0c237d
JB		 1409 /*
1410 * Sinks are *supposed* to come up within 1ms from an off state,
1411 * but we're also supposed to retry 3 times per the spec.
1412 */
61da5fab 1413 for (i = 0; i < 3; i++) {
df0c237d
JB		 1414 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1415 recv_bytes);
1416 if (ret == recv_bytes)
61da5fab
JB		 1417 return true;
1418 msleep(1);
1419 }
a4fc5ed6 1420
61da5fab 1421 return false;
a4fc5ed6
KP		 1422}
1423
1424/*
1425 * Fetch AUX CH registers 0x202 - 0x207 which contain
1426 * link status information
1427 */
1428static bool
93f62dad 1429intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1430{
df0c237d
JB		 1431 return intel_dp_aux_native_read_retry(intel_dp,
1432 DP_LANE0_1_STATUS,
93f62dad 1433 link_status,
df0c237d 1434 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1435}
1436
1437static uint8_t
1438intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1439 int r)
1440{
1441 return link_status[r - DP_LANE0_1_STATUS];
1442}
1443
a4fc5ed6 1444static uint8_t
93f62dad 1445intel_get_adjust_request_voltage(uint8_t adjust_request[2],
a4fc5ed6
KP		 1446 int lane)
1447{
a4fc5ed6
KP		 1448 int s = ((lane & 1) ?
1449 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1450 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
93f62dad 1451 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1452
1453 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1454}
1455
1456static uint8_t
93f62dad 1457intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
a4fc5ed6
KP		 1458 int lane)
1459{
a4fc5ed6
KP		 1460 int s = ((lane & 1) ?
1461 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1462 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
93f62dad 1463 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1464
1465 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1466}
1467
1468
1469#if 0
1470static char *voltage_names[] = {
1471 "0.4V", "0.6V", "0.8V", "1.2V"
1472};
1473static char *pre_emph_names[] = {
1474 "0dB", "3.5dB", "6dB", "9.5dB"
1475};
1476static char *link_train_names[] = {
1477 "pattern 1", "pattern 2", "idle", "off"
1478};
1479#endif
1480
1481/*
1482 * These are source-specific values; current Intel hardware supports
1483 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1484 */
a4fc5ed6
KP		 1485
1486static uint8_t
1a2eb460 1487intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1488{
1a2eb460
KP		 1489 struct drm_device *dev = intel_dp->base.base.dev;
1490
1491 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1492 return DP_TRAIN_VOLTAGE_SWING_800;
1493 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1494 return DP_TRAIN_VOLTAGE_SWING_1200;
1495 else
1496 return DP_TRAIN_VOLTAGE_SWING_800;
1497}
1498
1499static uint8_t
1500intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1501{
1502 struct drm_device *dev = intel_dp->base.base.dev;
1503
d6c0d722
PZ		 1504 if (IS_HASWELL(dev)) {
1505 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1506 case DP_TRAIN_VOLTAGE_SWING_400:
1507 return DP_TRAIN_PRE_EMPHASIS_9_5;
1508 case DP_TRAIN_VOLTAGE_SWING_600:
1509 return DP_TRAIN_PRE_EMPHASIS_6;
1510 case DP_TRAIN_VOLTAGE_SWING_800:
1511 return DP_TRAIN_PRE_EMPHASIS_3_5;
1512 case DP_TRAIN_VOLTAGE_SWING_1200:
1513 default:
1514 return DP_TRAIN_PRE_EMPHASIS_0;
1515 }
1516 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1517 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1518 case DP_TRAIN_VOLTAGE_SWING_400:
1519 return DP_TRAIN_PRE_EMPHASIS_6;
1520 case DP_TRAIN_VOLTAGE_SWING_600:
1521 case DP_TRAIN_VOLTAGE_SWING_800:
1522 return DP_TRAIN_PRE_EMPHASIS_3_5;
1523 default:
1524 return DP_TRAIN_PRE_EMPHASIS_0;
1525 }
1526 } else {
1527 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1528 case DP_TRAIN_VOLTAGE_SWING_400:
1529 return DP_TRAIN_PRE_EMPHASIS_6;
1530 case DP_TRAIN_VOLTAGE_SWING_600:
1531 return DP_TRAIN_PRE_EMPHASIS_6;
1532 case DP_TRAIN_VOLTAGE_SWING_800:
1533 return DP_TRAIN_PRE_EMPHASIS_3_5;
1534 case DP_TRAIN_VOLTAGE_SWING_1200:
1535 default:
1536 return DP_TRAIN_PRE_EMPHASIS_0;
1537 }
a4fc5ed6
KP		 1538 }
1539}
1540
1541static void
93f62dad 1542intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1543{
1544 uint8_t v = 0;
1545 uint8_t p = 0;
1546 int lane;
93f62dad 1547 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1a2eb460
KP		 1548 uint8_t voltage_max;
1549 uint8_t preemph_max;
a4fc5ed6 1550
33a34e4e 1551 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad
KP		 1552 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1553 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
a4fc5ed6
KP		 1554
1555 if (this_v > v)
1556 v = this_v;
1557 if (this_p > p)
1558 p = this_p;
1559 }
1560
1a2eb460 1561 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1562 if (v >= voltage_max)
1563 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1564
1a2eb460
KP		 1565 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1566 if (p >= preemph_max)
1567 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1568
1569 for (lane = 0; lane < 4; lane++)
33a34e4e 1570 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1571}
1572
1573static uint32_t
93f62dad 1574intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1575{
3cf2efb1 1576 uint32_t signal_levels = 0;
a4fc5ed6 1577
3cf2efb1 1578 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1579 case DP_TRAIN_VOLTAGE_SWING_400:
1580 default:
1581 signal_levels |= DP_VOLTAGE_0_4;
1582 break;
1583 case DP_TRAIN_VOLTAGE_SWING_600:
1584 signal_levels |= DP_VOLTAGE_0_6;
1585 break;
1586 case DP_TRAIN_VOLTAGE_SWING_800:
1587 signal_levels |= DP_VOLTAGE_0_8;
1588 break;
1589 case DP_TRAIN_VOLTAGE_SWING_1200:
1590 signal_levels |= DP_VOLTAGE_1_2;
1591 break;
1592 }
3cf2efb1 1593 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1594 case DP_TRAIN_PRE_EMPHASIS_0:
1595 default:
1596 signal_levels |= DP_PRE_EMPHASIS_0;
1597 break;
1598 case DP_TRAIN_PRE_EMPHASIS_3_5:
1599 signal_levels |= DP_PRE_EMPHASIS_3_5;
1600 break;
1601 case DP_TRAIN_PRE_EMPHASIS_6:
1602 signal_levels |= DP_PRE_EMPHASIS_6;
1603 break;
1604 case DP_TRAIN_PRE_EMPHASIS_9_5:
1605 signal_levels |= DP_PRE_EMPHASIS_9_5;
1606 break;
1607 }
1608 return signal_levels;
1609}
1610
e3421a18
ZW		 1611/* Gen6's DP voltage swing and pre-emphasis control */
1612static uint32_t
1613intel_gen6_edp_signal_levels(uint8_t train_set)
1614{
3c5a62b5
YL		 1615 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1616 DP_TRAIN_PRE_EMPHASIS_MASK);
1617 switch (signal_levels) {
e3421a18 1618 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1619 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1620 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1621 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1622 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1623 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1624 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1625 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1626 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1627 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1628 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1629 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1630 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1631 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1632 default:
3c5a62b5
YL		 1633 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1634 "0x%x\n", signal_levels);
1635 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1636 }
1637}
1638
1a2eb460
KP		 1639/* Gen7's DP voltage swing and pre-emphasis control */
1640static uint32_t
1641intel_gen7_edp_signal_levels(uint8_t train_set)
1642{
1643 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1644 DP_TRAIN_PRE_EMPHASIS_MASK);
1645 switch (signal_levels) {
1646 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1647 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1648 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1649 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1650 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1651 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1652
1653 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1654 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1655 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1656 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1657
1658 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1659 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1660 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1661 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1662
1663 default:
1664 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1665 "0x%x\n", signal_levels);
1666 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1667 }
1668}
1669
d6c0d722
PZ		 1670/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1671static uint32_t
1672intel_dp_signal_levels_hsw(uint8_t train_set)
1673{
1674 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1675 DP_TRAIN_PRE_EMPHASIS_MASK);
1676 switch (signal_levels) {
1677 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1678 return DDI_BUF_EMP_400MV_0DB_HSW;
1679 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1680 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1681 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1682 return DDI_BUF_EMP_400MV_6DB_HSW;
1683 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1684 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1685
1686 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1687 return DDI_BUF_EMP_600MV_0DB_HSW;
1688 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1689 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1690 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1691 return DDI_BUF_EMP_600MV_6DB_HSW;
1692
1693 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1694 return DDI_BUF_EMP_800MV_0DB_HSW;
1695 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1696 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1697 default:
1698 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1699 "0x%x\n", signal_levels);
1700 return DDI_BUF_EMP_400MV_0DB_HSW;
1701 }
1702}
1703
a4fc5ed6
KP		 1704static uint8_t
1705intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1706 int lane)
1707{
a4fc5ed6 1708 int s = (lane & 1) * 4;
93f62dad 1709 uint8_t l = link_status[lane>>1];
a4fc5ed6
KP		 1710
1711 return (l >> s) & 0xf;
1712}
1713
1714/* Check for clock recovery is done on all channels */
1715static bool
1716intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1717{
1718 int lane;
1719 uint8_t lane_status;
1720
1721 for (lane = 0; lane < lane_count; lane++) {
1722 lane_status = intel_get_lane_status(link_status, lane);
1723 if ((lane_status & DP_LANE_CR_DONE) == 0)
1724 return false;
1725 }
1726 return true;
1727}
1728
1729/* Check to see if channel eq is done on all channels */
1730#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1731 DP_LANE_CHANNEL_EQ_DONE|\
1732 DP_LANE_SYMBOL_LOCKED)
1733static bool
93f62dad 1734intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1735{
1736 uint8_t lane_align;
1737 uint8_t lane_status;
1738 int lane;
1739
93f62dad 1740 lane_align = intel_dp_link_status(link_status,
a4fc5ed6
KP		 1741 DP_LANE_ALIGN_STATUS_UPDATED);
1742 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1743 return false;
33a34e4e 1744 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad 1745 lane_status = intel_get_lane_status(link_status, lane);
a4fc5ed6
KP		 1746 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1747 return false;
1748 }
1749 return true;
1750}
1751
1752static bool
ea5b213a 1753intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1754 uint32_t dp_reg_value,
58e10eb9 1755 uint8_t dp_train_pat)
a4fc5ed6 1756{
4ef69c7a 1757 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1758 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6 1759 int ret;
d6c0d722 1760 uint32_t temp;
a4fc5ed6 1761
d6c0d722
PZ		 1762 if (IS_HASWELL(dev)) {
1763 temp = I915_READ(DP_TP_CTL(intel_dp->port));
1764
1765 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1766 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1767 else
1768 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1769
1770 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1771 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1772 case DP_TRAINING_PATTERN_DISABLE:
1773 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1774 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1775
1776 if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) &
1777 DP_TP_STATUS_IDLE_DONE), 1))
1778 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1779
1780 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1781 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1782
1783 break;
1784 case DP_TRAINING_PATTERN_1:
1785 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1786 break;
1787 case DP_TRAINING_PATTERN_2:
1788 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1789 break;
1790 case DP_TRAINING_PATTERN_3:
1791 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1792 break;
1793 }
1794 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1795
1796 } else if (HAS_PCH_CPT(dev) &&
1797 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1798 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1799
1800 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1801 case DP_TRAINING_PATTERN_DISABLE:
1802 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1803 break;
1804 case DP_TRAINING_PATTERN_1:
1805 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1806 break;
1807 case DP_TRAINING_PATTERN_2:
1808 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1809 break;
1810 case DP_TRAINING_PATTERN_3:
1811 DRM_ERROR("DP training pattern 3 not supported\n");
1812 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1813 break;
1814 }
1815
1816 } else {
1817 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1818
1819 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1820 case DP_TRAINING_PATTERN_DISABLE:
1821 dp_reg_value |= DP_LINK_TRAIN_OFF;
1822 break;
1823 case DP_TRAINING_PATTERN_1:
1824 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1825 break;
1826 case DP_TRAINING_PATTERN_2:
1827 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1828 break;
1829 case DP_TRAINING_PATTERN_3:
1830 DRM_ERROR("DP training pattern 3 not supported\n");
1831 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1832 break;
1833 }
1834 }
1835
ea5b213a
CW		 1836 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1837 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1838
ea5b213a 1839 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1840 DP_TRAINING_PATTERN_SET,
1841 dp_train_pat);
1842
47ea7542
PZ		 1843 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1844 DP_TRAINING_PATTERN_DISABLE) {
1845 ret = intel_dp_aux_native_write(intel_dp,
1846 DP_TRAINING_LANE0_SET,
1847 intel_dp->train_set,
1848 intel_dp->lane_count);
1849 if (ret != intel_dp->lane_count)
1850 return false;
1851 }
a4fc5ed6
KP		 1852
1853 return true;
1854}
1855
33a34e4e 1856/* Enable corresponding port and start training pattern 1 */
a4fc5ed6 1857static void
33a34e4e 1858intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1859{
4ef69c7a 1860 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 1861 int i;
1862 uint8_t voltage;
1863 bool clock_recovery = false;
cdb0e95b 1864 int voltage_tries, loop_tries;
ea5b213a 1865 uint32_t DP = intel_dp->DP;
a4fc5ed6 1866
3cf2efb1
CW		 1867 /* Write the link configuration data */
1868 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1869 intel_dp->link_configuration,
1870 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1871
1872 DP |= DP_PORT_EN;
1a2eb460 1873
33a34e4e 1874 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1875 voltage = 0xff;
cdb0e95b
KP		 1876 voltage_tries = 0;
1877 loop_tries = 0;
a4fc5ed6
KP		 1878 clock_recovery = false;
1879 for (;;) {
33a34e4e 1880 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1881 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1882 uint32_t signal_levels;
417e822d 1883
d6c0d722
PZ		 1884 if (IS_HASWELL(dev)) {
1885 signal_levels = intel_dp_signal_levels_hsw(
1886 intel_dp->train_set[0]);
1887 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1888 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1889 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1890 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1891 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1892 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1893 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1894 } else {
93f62dad 1895 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1896 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1897 }
d6c0d722
PZ		 1898 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1899 signal_levels);
a4fc5ed6 1900
47ea7542 1901 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1902 DP_TRAINING_PATTERN_1 |
1903 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1904 break;
a4fc5ed6
KP		 1905 /* Set training pattern 1 */
1906
3cf2efb1 1907 udelay(100);
93f62dad
KP		 1908 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1909 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1910 break;
93f62dad 1911 }
a4fc5ed6 1912
93f62dad
KP		 1913 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1914 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1915 clock_recovery = true;
1916 break;
1917 }
1918
1919 /* Check to see if we've tried the max voltage */
1920 for (i = 0; i < intel_dp->lane_count; i++)
1921 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1922 break;
0d710688 1923 if (i == intel_dp->lane_count && voltage_tries == 5) {
cdb0e95b
KP		 1924 ++loop_tries;
1925 if (loop_tries == 5) {
1926 DRM_DEBUG_KMS("too many full retries, give up\n");
1927 break;
1928 }
1929 memset(intel_dp->train_set, 0, 4);
1930 voltage_tries = 0;
1931 continue;
1932 }
a4fc5ed6 1933
3cf2efb1
CW		 1934 /* Check to see if we've tried the same voltage 5 times */
1935 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
cdb0e95b
KP		 1936 ++voltage_tries;
1937 if (voltage_tries == 5) {
1938 DRM_DEBUG_KMS("too many voltage retries, give up\n");
a4fc5ed6 1939 break;
cdb0e95b 1940 }
3cf2efb1 1941 } else
cdb0e95b 1942 voltage_tries = 0;
3cf2efb1 1943 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1944
3cf2efb1 1945 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1946 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1947 }
1948
33a34e4e
JB		 1949 intel_dp->DP = DP;
1950}
1951
1952static void
1953intel_dp_complete_link_train(struct intel_dp *intel_dp)
1954{
4ef69c7a 1955 struct drm_device *dev = intel_dp->base.base.dev;
33a34e4e 1956 bool channel_eq = false;
37f80975 1957 int tries, cr_tries;
33a34e4e
JB		 1958 uint32_t DP = intel_dp->DP;
1959
a4fc5ed6
KP		 1960 /* channel equalization */
1961 tries = 0;
37f80975 1962 cr_tries = 0;
a4fc5ed6
KP		 1963 channel_eq = false;
1964 for (;;) {
33a34e4e 1965 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1966 uint32_t signal_levels;
93f62dad 1967 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1968
37f80975
JB		 1969 if (cr_tries > 5) {
1970 DRM_ERROR("failed to train DP, aborting\n");
1971 intel_dp_link_down(intel_dp);
1972 break;
1973 }
1974
d6c0d722
PZ		 1975 if (IS_HASWELL(dev)) {
1976 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1977 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1978 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1979 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1980 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1981 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1982 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1983 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1984 } else {
93f62dad 1985 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1986 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1987 }
1988
a4fc5ed6 1989 /* channel eq pattern */
47ea7542 1990 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1991 DP_TRAINING_PATTERN_2 |
1992 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1993 break;
1994
3cf2efb1 1995 udelay(400);
93f62dad 1996 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1997 break;
a4fc5ed6 1998
37f80975 1999 /* Make sure clock is still ok */
93f62dad 2000 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 2001 intel_dp_start_link_train(intel_dp);
2002 cr_tries++;
2003 continue;
2004 }
2005
93f62dad 2006 if (intel_channel_eq_ok(intel_dp, link_status)) {
3cf2efb1
CW		 2007 channel_eq = true;
2008 break;
2009 }
a4fc5ed6 2010
37f80975
JB		 2011 /* Try 5 times, then try clock recovery if that fails */
2012 if (tries > 5) {
2013 intel_dp_link_down(intel_dp);
2014 intel_dp_start_link_train(intel_dp);
2015 tries = 0;
2016 cr_tries++;
2017 continue;
2018 }
a4fc5ed6 2019
3cf2efb1 2020 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2021 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2022 ++tries;
869184a6 2023 }
3cf2efb1 2024
d6c0d722
PZ		 2025 if (channel_eq)
2026 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2027
47ea7542 2028 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2029}
2030
2031static void
ea5b213a 2032intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2033{
4ef69c7a 2034 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2035 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 2036 uint32_t DP = intel_dp->DP;
a4fc5ed6 2037
0c33d8d7 2038 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2039 return;
2040
28c97730 2041 DRM_DEBUG_KMS("\n");
32f9d658 2042
1a2eb460 2043 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 2044 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2045 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2046 } else {
2047 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2048 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2049 }
fe255d00 2050 POSTING_READ(intel_dp->output_reg);
5eb08b69 2051
fe255d00 2052 msleep(17);
5eb08b69 2053
493a7081 2054 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2055 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
31acbcc4
CW		 2056 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2057
5bddd17f
EA		 2058 /* Hardware workaround: leaving our transcoder select
2059 * set to transcoder B while it's off will prevent the
2060 * corresponding HDMI output on transcoder A.
2061 *
2062 * Combine this with another hardware workaround:
2063 * transcoder select bit can only be cleared while the
2064 * port is enabled.
2065 */
2066 DP &= ~DP_PIPEB_SELECT;
2067 I915_WRITE(intel_dp->output_reg, DP);
2068
2069 /* Changes to enable or select take place the vblank
2070 * after being written.
2071 */
31acbcc4
CW		 2072 if (crtc == NULL) {
2073 /* We can arrive here never having been attached
2074 * to a CRTC, for instance, due to inheriting
2075 * random state from the BIOS.
2076 *
2077 * If the pipe is not running, play safe and
2078 * wait for the clocks to stabilise before
2079 * continuing.
2080 */
2081 POSTING_READ(intel_dp->output_reg);
2082 msleep(50);
2083 } else
2084 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 2085 }
2086
832afda6 2087 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2088 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2089 POSTING_READ(intel_dp->output_reg);
f01eca2e 2090 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2091}
2092
26d61aad
KP		 2093static bool
2094intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2095{
92fd8fd1 2096 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
b091cd92
AJ		 2097 sizeof(intel_dp->dpcd)) == 0)
2098 return false; /* aux transfer failed */
92fd8fd1 2099
b091cd92
AJ		 2100 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2101 return false; /* DPCD not present */
2102
2103 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2104 DP_DWN_STRM_PORT_PRESENT))
2105 return true; /* native DP sink */
2106
2107 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2108 return true; /* no per-port downstream info */
2109
2110 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2111 intel_dp->downstream_ports,
2112 DP_MAX_DOWNSTREAM_PORTS) == 0)
2113 return false; /* downstream port status fetch failed */
2114
2115 return true;
92fd8fd1
KP		 2116}
2117
0d198328
AJ		 2118static void
2119intel_dp_probe_oui(struct intel_dp *intel_dp)
2120{
2121 u8 buf[3];
2122
2123 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2124 return;
2125
351cfc34
DV		 2126 ironlake_edp_panel_vdd_on(intel_dp);
2127
0d198328
AJ		 2128 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2129 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2130 buf[0], buf[1], buf[2]);
2131
2132 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2133 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2134 buf[0], buf[1], buf[2]);
351cfc34
DV		 2135
2136 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2137}
2138
a60f0e38
JB		 2139static bool
2140intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2141{
2142 int ret;
2143
2144 ret = intel_dp_aux_native_read_retry(intel_dp,
2145 DP_DEVICE_SERVICE_IRQ_VECTOR,
2146 sink_irq_vector, 1);
2147 if (!ret)
2148 return false;
2149
2150 return true;
2151}
2152
2153static void
2154intel_dp_handle_test_request(struct intel_dp *intel_dp)
2155{
2156 /* NAK by default */
2157 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2158}
2159
a4fc5ed6
KP		 2160/*
2161 * According to DP spec
2162 * 5.1.2:
2163 * 1. Read DPCD
2164 * 2. Configure link according to Receiver Capabilities
2165 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2166 * 4. Check link status on receipt of hot-plug interrupt
2167 */
2168
2169static void
ea5b213a 2170intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2171{
a60f0e38 2172 u8 sink_irq_vector;
93f62dad 2173 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2174
24e804ba 2175 if (!intel_dp->base.connectors_active)
d2b996ac 2176 return;
59cd09e1 2177
24e804ba 2178 if (WARN_ON(!intel_dp->base.base.crtc))
a4fc5ed6
KP		 2179 return;
2180
92fd8fd1 2181 /* Try to read receiver status if the link appears to be up */
93f62dad 2182 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2183 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2184 return;
2185 }
2186
92fd8fd1 2187 /* Now read the DPCD to see if it's actually running */
26d61aad 2188 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2189 intel_dp_link_down(intel_dp);
2190 return;
2191 }
2192
a60f0e38
JB		 2193 /* Try to read the source of the interrupt */
2194 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2195 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2196 /* Clear interrupt source */
2197 intel_dp_aux_native_write_1(intel_dp,
2198 DP_DEVICE_SERVICE_IRQ_VECTOR,
2199 sink_irq_vector);
2200
2201 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2202 intel_dp_handle_test_request(intel_dp);
2203 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2204 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2205 }
2206
93f62dad 2207 if (!intel_channel_eq_ok(intel_dp, link_status)) {
92fd8fd1
KP		 2208 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2209 drm_get_encoder_name(&intel_dp->base.base));
33a34e4e
JB		 2210 intel_dp_start_link_train(intel_dp);
2211 intel_dp_complete_link_train(intel_dp);
2212 }
a4fc5ed6 2213}
a4fc5ed6 2214
07d3dc18 2215/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2216static enum drm_connector_status
26d61aad 2217intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2218{
07d3dc18
AJ		 2219 uint8_t *dpcd = intel_dp->dpcd;
2220 bool hpd;
2221 uint8_t type;
2222
2223 if (!intel_dp_get_dpcd(intel_dp))
2224 return connector_status_disconnected;
2225
2226 /* if there's no downstream port, we're done */
2227 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2228 return connector_status_connected;
2229
2230 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2231 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2232 if (hpd) {
da131a46 2233 uint8_t reg;
07d3dc18 2234 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
da131a46 2235 &reg, 1))
07d3dc18 2236 return connector_status_unknown;
da131a46
AJ		 2237 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2238 : connector_status_disconnected;
07d3dc18
AJ		 2239 }
2240
2241 /* If no HPD, poke DDC gently */
2242 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2243 return connector_status_connected;
07d3dc18
AJ		 2244
2245 /* Well we tried, say unknown for unreliable port types */
2246 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2247 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2248 return connector_status_unknown;
2249
2250 /* Anything else is out of spec, warn and ignore */
2251 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2252 return connector_status_disconnected;
71ba9000
AJ		 2253}
2254
5eb08b69 2255static enum drm_connector_status
a9756bb5 2256ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2257{
5eb08b69
ZW		 2258 enum drm_connector_status status;
2259
fe16d949
CW		 2260 /* Can't disconnect eDP, but you can close the lid... */
2261 if (is_edp(intel_dp)) {
2262 status = intel_panel_detect(intel_dp->base.base.dev);
2263 if (status == connector_status_unknown)
2264 status = connector_status_connected;
2265 return status;
2266 }
01cb9ea6 2267
26d61aad 2268 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2269}
2270
a4fc5ed6 2271static enum drm_connector_status
a9756bb5 2272g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2273{
4ef69c7a 2274 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2275 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 2276 uint32_t bit;
5eb08b69 2277
ea5b213a 2278 switch (intel_dp->output_reg) {
a4fc5ed6 2279 case DP_B:
10f76a38 2280 bit = DPB_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2281 break;
2282 case DP_C:
10f76a38 2283 bit = DPC_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2284 break;
2285 case DP_D:
10f76a38 2286 bit = DPD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2287 break;
2288 default:
2289 return connector_status_unknown;
2290 }
2291
10f76a38 2292 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2293 return connector_status_disconnected;
2294
26d61aad 2295 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2296}
2297
8c241fef
KP		 2298static struct edid *
2299intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2300{
2301 struct intel_dp *intel_dp = intel_attached_dp(connector);
2302 struct edid *edid;
d6f24d0f
JB		 2303 int size;
2304
2305 if (is_edp(intel_dp)) {
2306 if (!intel_dp->edid)
2307 return NULL;
2308
2309 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2310 edid = kmalloc(size, GFP_KERNEL);
2311 if (!edid)
2312 return NULL;
2313
2314 memcpy(edid, intel_dp->edid, size);
2315 return edid;
2316 }
8c241fef 2317
8c241fef 2318 edid = drm_get_edid(connector, adapter);
8c241fef
KP		 2319 return edid;
2320}
2321
2322static int
2323intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2324{
2325 struct intel_dp *intel_dp = intel_attached_dp(connector);
2326 int ret;
2327
d6f24d0f
JB		 2328 if (is_edp(intel_dp)) {
2329 drm_mode_connector_update_edid_property(connector,
2330 intel_dp->edid);
2331 ret = drm_add_edid_modes(connector, intel_dp->edid);
2332 drm_edid_to_eld(connector,
2333 intel_dp->edid);
d6f24d0f
JB		 2334 return intel_dp->edid_mode_count;
2335 }
2336
8c241fef 2337 ret = intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2338 return ret;
2339}
2340
2341
a9756bb5
ZW		 2342/**
2343 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2344 *
2345 * \return true if DP port is connected.
2346 * \return false if DP port is disconnected.
2347 */
2348static enum drm_connector_status
2349intel_dp_detect(struct drm_connector *connector, bool force)
2350{
2351 struct intel_dp *intel_dp = intel_attached_dp(connector);
2352 struct drm_device *dev = intel_dp->base.base.dev;
2353 enum drm_connector_status status;
2354 struct edid *edid = NULL;
2355
2356 intel_dp->has_audio = false;
2357
2358 if (HAS_PCH_SPLIT(dev))
2359 status = ironlake_dp_detect(intel_dp);
2360 else
2361 status = g4x_dp_detect(intel_dp);
1b9be9d0 2362
ac66ae83
AJ		 2363 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2364 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2365 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2366 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1b9be9d0 2367
a9756bb5
ZW		 2368 if (status != connector_status_connected)
2369 return status;
2370
0d198328
AJ		 2371 intel_dp_probe_oui(intel_dp);
2372
c3e5f67b
DV		 2373 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2374 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2375 } else {
8c241fef 2376 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2377 if (edid) {
2378 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2379 kfree(edid);
2380 }
a9756bb5
ZW		 2381 }
2382
2383 return connector_status_connected;
a4fc5ed6
KP		 2384}
2385
2386static int intel_dp_get_modes(struct drm_connector *connector)
2387{
df0e9248 2388 struct intel_dp *intel_dp = intel_attached_dp(connector);
4ef69c7a 2389 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 2390 struct drm_i915_private *dev_priv = dev->dev_private;
2391 int ret;
a4fc5ed6
KP		 2392
2393 /* We should parse the EDID data and find out if it has an audio sink
2394 */
2395
8c241fef 2396 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
b9efc480 2397 if (ret) {
d15456de 2398 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
b9efc480
ZY		 2399 struct drm_display_mode *newmode;
2400 list_for_each_entry(newmode, &connector->probed_modes,
2401 head) {
d15456de
KP		 2402 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2403 intel_dp->panel_fixed_mode =
b9efc480
ZY		 2404 drm_mode_duplicate(dev, newmode);
2405 break;
2406 }
2407 }
2408 }
32f9d658 2409 return ret;
b9efc480 2410 }
32f9d658
ZW		 2411
2412 /* if eDP has no EDID, try to use fixed panel mode from VBT */
4d926461 2413 if (is_edp(intel_dp)) {
47f0eb22 2414 /* initialize panel mode from VBT if available for eDP */
d15456de
KP		 2415 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2416 intel_dp->panel_fixed_mode =
47f0eb22 2417 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
d15456de
KP		 2418 if (intel_dp->panel_fixed_mode) {
2419 intel_dp->panel_fixed_mode->type |=
47f0eb22
KP		 2420 DRM_MODE_TYPE_PREFERRED;
2421 }
2422 }
d15456de 2423 if (intel_dp->panel_fixed_mode) {
32f9d658 2424 struct drm_display_mode *mode;
d15456de 2425 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
32f9d658
ZW		 2426 drm_mode_probed_add(connector, mode);
2427 return 1;
2428 }
2429 }
2430 return 0;
a4fc5ed6
KP		 2431}
2432
1aad7ac0
CW		 2433static bool
2434intel_dp_detect_audio(struct drm_connector *connector)
2435{
2436 struct intel_dp *intel_dp = intel_attached_dp(connector);
2437 struct edid *edid;
2438 bool has_audio = false;
2439
8c241fef 2440 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2441 if (edid) {
2442 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2443 kfree(edid);
2444 }
2445
2446 return has_audio;
2447}
2448
f684960e
CW		 2449static int
2450intel_dp_set_property(struct drm_connector *connector,
2451 struct drm_property *property,
2452 uint64_t val)
2453{
e953fd7b 2454 struct drm_i915_private *dev_priv = connector->dev->dev_private;
f684960e
CW		 2455 struct intel_dp *intel_dp = intel_attached_dp(connector);
2456 int ret;
2457
2458 ret = drm_connector_property_set_value(connector, property, val);
2459 if (ret)
2460 return ret;
2461
3f43c48d 2462 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2463 int i = val;
2464 bool has_audio;
2465
2466 if (i == intel_dp->force_audio)
f684960e
CW		 2467 return 0;
2468
1aad7ac0 2469 intel_dp->force_audio = i;
f684960e 2470
c3e5f67b 2471 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2472 has_audio = intel_dp_detect_audio(connector);
2473 else
c3e5f67b 2474 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2475
2476 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2477 return 0;
2478
1aad7ac0 2479 intel_dp->has_audio = has_audio;
f684960e
CW		 2480 goto done;
2481 }
2482
e953fd7b
CW		 2483 if (property == dev_priv->broadcast_rgb_property) {
2484 if (val == !!intel_dp->color_range)
2485 return 0;
2486
2487 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2488 goto done;
2489 }
2490
f684960e
CW		 2491 return -EINVAL;
2492
2493done:
2494 if (intel_dp->base.base.crtc) {
2495 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a6778b3c
DV		 2496 intel_set_mode(crtc, &crtc->mode,
2497 crtc->x, crtc->y, crtc->fb);
f684960e
CW		 2498 }
2499
2500 return 0;
2501}
2502
a4fc5ed6 2503static void
0206e353 2504intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2505{
aaa6fd2a
MG		 2506 struct drm_device *dev = connector->dev;
2507
2508 if (intel_dpd_is_edp(dev))
2509 intel_panel_destroy_backlight(dev);
2510
a4fc5ed6
KP		 2511 drm_sysfs_connector_remove(connector);
2512 drm_connector_cleanup(connector);
55f78c43 2513 kfree(connector);
a4fc5ed6
KP		 2514}
2515
24d05927
DV		 2516static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2517{
2518 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2519
2520 i2c_del_adapter(&intel_dp->adapter);
2521 drm_encoder_cleanup(encoder);
bd943159 2522 if (is_edp(intel_dp)) {
d6f24d0f 2523 kfree(intel_dp->edid);
bd943159
KP		 2524 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2525 ironlake_panel_vdd_off_sync(intel_dp);
2526 }
24d05927
DV		 2527 kfree(intel_dp);
2528}
2529
a4fc5ed6 2530static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2531 .mode_fixup = intel_dp_mode_fixup,
a4fc5ed6 2532 .mode_set = intel_dp_mode_set,
1f703855 2533 .disable = intel_encoder_noop,
a4fc5ed6
KP		 2534};
2535
2536static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2537 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2538 .detect = intel_dp_detect,
2539 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2540 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2541 .destroy = intel_dp_destroy,
2542};
2543
2544static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2545 .get_modes = intel_dp_get_modes,
2546 .mode_valid = intel_dp_mode_valid,
df0e9248 2547 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2548};
2549
a4fc5ed6 2550static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2551 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2552};
2553
995b6762 2554static void
21d40d37 2555intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2556{
ea5b213a 2557 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 2558
885a5014 2559 intel_dp_check_link_status(intel_dp);
c8110e52 2560}
6207937d 2561
e3421a18
ZW		 2562/* Return which DP Port should be selected for Transcoder DP control */
2563int
0206e353 2564intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2565{
2566 struct drm_device *dev = crtc->dev;
6c2b7c12 2567 struct intel_encoder *encoder;
e3421a18 2568
6c2b7c12
DV		 2569 for_each_encoder_on_crtc(dev, crtc, encoder) {
2570 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
e3421a18 2571
417e822d
KP		 2572 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2573 intel_dp->base.type == INTEL_OUTPUT_EDP)
ea5b213a 2574 return intel_dp->output_reg;
e3421a18 2575 }
ea5b213a 2576
e3421a18
ZW		 2577 return -1;
2578}
2579
36e83a18 2580/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2581bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2582{
2583 struct drm_i915_private *dev_priv = dev->dev_private;
2584 struct child_device_config *p_child;
2585 int i;
2586
2587 if (!dev_priv->child_dev_num)
2588 return false;
2589
2590 for (i = 0; i < dev_priv->child_dev_num; i++) {
2591 p_child = dev_priv->child_dev + i;
2592
2593 if (p_child->dvo_port == PORT_IDPD &&
2594 p_child->device_type == DEVICE_TYPE_eDP)
2595 return true;
2596 }
2597 return false;
2598}
2599
f684960e
CW		 2600static void
2601intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2602{
3f43c48d 2603 intel_attach_force_audio_property(connector);
e953fd7b 2604 intel_attach_broadcast_rgb_property(connector);
f684960e
CW		 2605}
2606
a4fc5ed6 2607void
ab9d7c30 2608intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
a4fc5ed6
KP		 2609{
2610 struct drm_i915_private *dev_priv = dev->dev_private;
2611 struct drm_connector *connector;
ea5b213a 2612 struct intel_dp *intel_dp;
21d40d37 2613 struct intel_encoder *intel_encoder;
55f78c43 2614 struct intel_connector *intel_connector;
5eb08b69 2615 const char *name = NULL;
b329530c 2616 int type;
a4fc5ed6 2617
ea5b213a
CW		 2618 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2619 if (!intel_dp)
a4fc5ed6
KP		 2620 return;
2621
3d3dc149 2622 intel_dp->output_reg = output_reg;
ab9d7c30 2623 intel_dp->port = port;
0767935e
DV		 2624 /* Preserve the current hw state. */
2625 intel_dp->DP = I915_READ(intel_dp->output_reg);
3d3dc149 2626
55f78c43
ZW		 2627 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2628 if (!intel_connector) {
ea5b213a 2629 kfree(intel_dp);
55f78c43
ZW		 2630 return;
2631 }
ea5b213a 2632 intel_encoder = &intel_dp->base;
55f78c43 2633
ea5b213a 2634 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 2635 if (intel_dpd_is_edp(dev))
ea5b213a 2636 intel_dp->is_pch_edp = true;
b329530c 2637
19c03924
GB		 2638 /*
2639 * FIXME : We need to initialize built-in panels before external panels.
2640 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2641 */
2642 if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
2643 type = DRM_MODE_CONNECTOR_eDP;
2644 intel_encoder->type = INTEL_OUTPUT_EDP;
2645 } else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2646 type = DRM_MODE_CONNECTOR_eDP;
2647 intel_encoder->type = INTEL_OUTPUT_EDP;
2648 } else {
2649 type = DRM_MODE_CONNECTOR_DisplayPort;
2650 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2651 }
2652
55f78c43 2653 connector = &intel_connector->base;
b329530c 2654 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2655 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2656
eb1f8e4f
DA		 2657 connector->polled = DRM_CONNECTOR_POLL_HPD;
2658
66a9278e 2659 intel_encoder->cloneable = false;
f8aed700 2660
66a9278e
DV		 2661 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2662 ironlake_panel_vdd_work);
6251ec0a 2663
27f8227b 2664 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
ee7b9f93 2665
a4fc5ed6
KP		 2666 connector->interlace_allowed = true;
2667 connector->doublescan_allowed = 0;
2668
4ef69c7a 2669 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
a4fc5ed6 2670 DRM_MODE_ENCODER_TMDS);
4ef69c7a 2671 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
a4fc5ed6 2672
df0e9248 2673 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2674 drm_sysfs_connector_add(connector);
2675
e8cb4558 2676 intel_encoder->enable = intel_enable_dp;
2bd2ad64 2677 intel_encoder->pre_enable = intel_pre_enable_dp;
e8cb4558 2678 intel_encoder->disable = intel_disable_dp;
2bd2ad64 2679 intel_encoder->post_disable = intel_post_disable_dp;
19d8fe15
DV		 2680 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2681 intel_connector->get_hw_state = intel_connector_get_hw_state;
e8cb4558 2682
a4fc5ed6 2683 /* Set up the DDC bus. */
ab9d7c30
PZ		 2684 switch (port) {
2685 case PORT_A:
2686 name = "DPDDC-A";
2687 break;
2688 case PORT_B:
2689 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2690 name = "DPDDC-B";
2691 break;
2692 case PORT_C:
2693 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2694 name = "DPDDC-C";
2695 break;
2696 case PORT_D:
2697 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2698 name = "DPDDC-D";
2699 break;
2700 default:
2701 WARN(1, "Invalid port %c\n", port_name(port));
2702 break;
5eb08b69
ZW		 2703 }
2704
89667383
JB		 2705 /* Cache some DPCD data in the eDP case */
2706 if (is_edp(intel_dp)) {
f01eca2e
KP		 2707 struct edp_power_seq cur, vbt;
2708 u32 pp_on, pp_off, pp_div;
5d613501
JB		 2709
2710 pp_on = I915_READ(PCH_PP_ON_DELAYS);
f01eca2e 2711 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
5d613501 2712 pp_div = I915_READ(PCH_PP_DIVISOR);
89667383 2713
bfa3384a
JB		 2714 if (!pp_on || !pp_off || !pp_div) {
2715 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2716 intel_dp_encoder_destroy(&intel_dp->base.base);
2717 intel_dp_destroy(&intel_connector->base);
2718 return;
2719 }
2720
f01eca2e
KP		 2721 /* Pull timing values out of registers */
2722 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2723 PANEL_POWER_UP_DELAY_SHIFT;
2724
2725 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2726 PANEL_LIGHT_ON_DELAY_SHIFT;
f2e8b18a 2727
f01eca2e
KP		 2728 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2729 PANEL_LIGHT_OFF_DELAY_SHIFT;
2730
2731 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2732 PANEL_POWER_DOWN_DELAY_SHIFT;
2733
2734 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2735 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2736
2737 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2738 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2739
2740 vbt = dev_priv->edp.pps;
2741
2742 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2743 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2744
2745#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2746
2747 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2748 intel_dp->backlight_on_delay = get_delay(t8);
2749 intel_dp->backlight_off_delay = get_delay(t9);
2750 intel_dp->panel_power_down_delay = get_delay(t10);
2751 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2752
2753 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2754 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2755 intel_dp->panel_power_cycle_delay);
2756
2757 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2758 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
c1f05264
DA		 2759 }
2760
2761 intel_dp_i2c_init(intel_dp, intel_connector, name);
2762
2763 if (is_edp(intel_dp)) {
2764 bool ret;
2765 struct edid *edid;
5d613501
JB		 2766
2767 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2768 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2769 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2770
59f3e272 2771 if (ret) {
7183dc29
JB		 2772 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2773 dev_priv->no_aux_handshake =
2774 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2775 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2776 } else {
3d3dc149 2777 /* if this fails, presume the device is a ghost */
48898b03 2778 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3d3dc149 2779 intel_dp_encoder_destroy(&intel_dp->base.base);
48898b03 2780 intel_dp_destroy(&intel_connector->base);
3d3dc149 2781 return;
89667383 2782 }
89667383 2783
d6f24d0f
JB		 2784 ironlake_edp_panel_vdd_on(intel_dp);
2785 edid = drm_get_edid(connector, &intel_dp->adapter);
2786 if (edid) {
2787 drm_mode_connector_update_edid_property(connector,
2788 edid);
2789 intel_dp->edid_mode_count =
2790 drm_add_edid_modes(connector, edid);
2791 drm_edid_to_eld(connector, edid);
2792 intel_dp->edid = edid;
2793 }
2794 ironlake_edp_panel_vdd_off(intel_dp, false);
2795 }
552fb0b7 2796
21d40d37 2797 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 2798
4d926461 2799 if (is_edp(intel_dp)) {
aaa6fd2a
MG		 2800 dev_priv->int_edp_connector = connector;
2801 intel_panel_setup_backlight(dev);
32f9d658
ZW		 2802 }
2803
f684960e
CW		 2804 intel_dp_add_properties(intel_dp, connector);
2805
a4fc5ed6
KP		 2806 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2807 * 0xd. Failure to do so will result in spurious interrupts being
2808 * generated on the port when a cable is not attached.
2809 */
2810 if (IS_G4X(dev) && !IS_GM45(dev)) {
2811 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2812 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2813 }
2814}
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