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drm/i915: Add a FIXME about drrs/psr interactions
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
ef9348c8
CML		 67/*
68 * CHV supports eDP 1.4 that have more link rates.
69 * Below only provides the fixed rate but exclude variable rate.
70 */
71static const struct dp_link_dpll chv_dpll[] = {
72 /*
73 * CHV requires to program fractional division for m2.
74 * m2 is stored in fixed point format using formula below
75 * (m2_int << 22) | m2_fraction
76 */
77 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
78 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
79 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
80 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
81 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
83};
84
cfcb0fc9
JB		 85/**
86 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
87 * @intel_dp: DP struct
88 *
89 * If a CPU or PCH DP output is attached to an eDP panel, this function
90 * will return true, and false otherwise.
91 */
92static bool is_edp(struct intel_dp *intel_dp)
93{
da63a9f2
PZ		 94 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
95
96 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 97}
98
68b4d824 99static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 100{
68b4d824
ID		 101 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
102
103 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 104}
105
df0e9248
CW		 106static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
107{
fa90ecef 108 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 109}
110
ea5b213a 111static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 112static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 113static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 114
a4fc5ed6 115static int
ea5b213a 116intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 117{
7183dc29 118 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 119 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 120
121 switch (max_link_bw) {
122 case DP_LINK_BW_1_62:
123 case DP_LINK_BW_2_7:
124 break;
d4eead50 125 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 126 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
127 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 128 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
129 max_link_bw = DP_LINK_BW_5_4;
130 else
131 max_link_bw = DP_LINK_BW_2_7;
d4eead50 132 break;
a4fc5ed6 133 default:
d4eead50
ID		 134 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
135 max_link_bw);
a4fc5ed6
KP		 136 max_link_bw = DP_LINK_BW_1_62;
137 break;
138 }
139 return max_link_bw;
140}
141
eeb6324d
PZ		 142static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
143{
144 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
145 struct drm_device *dev = intel_dig_port->base.base.dev;
146 u8 source_max, sink_max;
147
148 source_max = 4;
149 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
150 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
151 source_max = 2;
152
153 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
154
155 return min(source_max, sink_max);
156}
157
cd9dde44
AJ		 158/*
159 * The units on the numbers in the next two are... bizarre. Examples will
160 * make it clearer; this one parallels an example in the eDP spec.
161 *
162 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
163 *
164 * 270000 * 1 * 8 / 10 == 216000
165 *
166 * The actual data capacity of that configuration is 2.16Gbit/s, so the
167 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
168 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
169 * 119000. At 18bpp that's 2142000 kilobits per second.
170 *
171 * Thus the strange-looking division by 10 in intel_dp_link_required, to
172 * get the result in decakilobits instead of kilobits.
173 */
174
a4fc5ed6 175static int
c898261c 176intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 177{
cd9dde44 178 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 179}
180
fe27d53e
DA		 181static int
182intel_dp_max_data_rate(int max_link_clock, int max_lanes)
183{
184 return (max_link_clock * max_lanes * 8) / 10;
185}
186
c19de8eb 187static enum drm_mode_status
a4fc5ed6
KP		 188intel_dp_mode_valid(struct drm_connector *connector,
189 struct drm_display_mode *mode)
190{
df0e9248 191 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 192 struct intel_connector *intel_connector = to_intel_connector(connector);
193 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 194 int target_clock = mode->clock;
195 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 196
dd06f90e
JN		 197 if (is_edp(intel_dp) && fixed_mode) {
198 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 199 return MODE_PANEL;
200
dd06f90e 201 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 202 return MODE_PANEL;
03afc4a2
DV		 203
204 target_clock = fixed_mode->clock;
7de56f43
ZY		 205 }
206
36008365 207 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 208 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 209
210 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
211 mode_rate = intel_dp_link_required(target_clock, 18);
212
213 if (mode_rate > max_rate)
c4867936 214 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 215
216 if (mode->clock < 10000)
217 return MODE_CLOCK_LOW;
218
0af78a2b
DV		 219 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
220 return MODE_H_ILLEGAL;
221
a4fc5ed6
KP		 222 return MODE_OK;
223}
224
225static uint32_t
226pack_aux(uint8_t *src, int src_bytes)
227{
228 int i;
229 uint32_t v = 0;
230
231 if (src_bytes > 4)
232 src_bytes = 4;
233 for (i = 0; i < src_bytes; i++)
234 v |= ((uint32_t) src[i]) << ((3-i) * 8);
235 return v;
236}
237
238static void
239unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
240{
241 int i;
242 if (dst_bytes > 4)
243 dst_bytes = 4;
244 for (i = 0; i < dst_bytes; i++)
245 dst[i] = src >> ((3-i) * 8);
246}
247
fb0f8fbf
KP		 248/* hrawclock is 1/4 the FSB frequency */
249static int
250intel_hrawclk(struct drm_device *dev)
251{
252 struct drm_i915_private *dev_priv = dev->dev_private;
253 uint32_t clkcfg;
254
9473c8f4
VP		 255 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
256 if (IS_VALLEYVIEW(dev))
257 return 200;
258
fb0f8fbf
KP		 259 clkcfg = I915_READ(CLKCFG);
260 switch (clkcfg & CLKCFG_FSB_MASK) {
261 case CLKCFG_FSB_400:
262 return 100;
263 case CLKCFG_FSB_533:
264 return 133;
265 case CLKCFG_FSB_667:
266 return 166;
267 case CLKCFG_FSB_800:
268 return 200;
269 case CLKCFG_FSB_1067:
270 return 266;
271 case CLKCFG_FSB_1333:
272 return 333;
273 /* these two are just a guess; one of them might be right */
274 case CLKCFG_FSB_1600:
275 case CLKCFG_FSB_1600_ALT:
276 return 400;
277 default:
278 return 133;
279 }
280}
281
bf13e81b
JN		 282static void
283intel_dp_init_panel_power_sequencer(struct drm_device *dev,
284 struct intel_dp *intel_dp,
285 struct edp_power_seq *out);
286static void
287intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
288 struct intel_dp *intel_dp,
289 struct edp_power_seq *out);
290
291static enum pipe
292vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
293{
294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
295 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
296 struct drm_device *dev = intel_dig_port->base.base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum port port = intel_dig_port->port;
299 enum pipe pipe;
300
301 /* modeset should have pipe */
302 if (crtc)
303 return to_intel_crtc(crtc)->pipe;
304
305 /* init time, try to find a pipe with this port selected */
306 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
307 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
308 PANEL_PORT_SELECT_MASK;
309 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
310 return pipe;
311 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
312 return pipe;
313 }
314
315 /* shrug */
316 return PIPE_A;
317}
318
319static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
320{
321 struct drm_device *dev = intel_dp_to_dev(intel_dp);
322
323 if (HAS_PCH_SPLIT(dev))
324 return PCH_PP_CONTROL;
325 else
326 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
327}
328
329static u32 _pp_stat_reg(struct intel_dp *intel_dp)
330{
331 struct drm_device *dev = intel_dp_to_dev(intel_dp);
332
333 if (HAS_PCH_SPLIT(dev))
334 return PCH_PP_STATUS;
335 else
336 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
337}
338
4be73780 339static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 340{
30add22d 341 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 342 struct drm_i915_private *dev_priv = dev->dev_private;
343
bf13e81b 344 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 345}
346
4be73780 347static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 348{
30add22d 349 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 350 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 351 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
352 struct intel_encoder *intel_encoder = &intel_dig_port->base;
353 enum intel_display_power_domain power_domain;
ebf33b18 354
bb4932c4
ID		 355 power_domain = intel_display_port_power_domain(intel_encoder);
356 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 357 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 358}
359
9b984dae
KP		 360static void
361intel_dp_check_edp(struct intel_dp *intel_dp)
362{
30add22d 363 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 364 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 365
9b984dae
KP		 366 if (!is_edp(intel_dp))
367 return;
453c5420 368
4be73780 369 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 370 WARN(1, "eDP powered off while attempting aux channel communication.\n");
371 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 372 I915_READ(_pp_stat_reg(intel_dp)),
373 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 374 }
375}
376
9ee32fea
DV		 377static uint32_t
378intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
379{
380 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
381 struct drm_device *dev = intel_dig_port->base.base.dev;
382 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 383 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 384 uint32_t status;
385 bool done;
386
ef04f00d 387#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 388 if (has_aux_irq)
b18ac466 389 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 390 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 391 else
392 done = wait_for_atomic(C, 10) == 0;
393 if (!done)
394 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
395 has_aux_irq);
396#undef C
397
398 return status;
399}
400
ec5b01dd 401static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 402{
174edf1f
PZ		 403 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
404 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 405
ec5b01dd
DL		 406 /*
407 * The clock divider is based off the hrawclk, and would like to run at
408 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 409 */
ec5b01dd
DL		 410 return index ? 0 : intel_hrawclk(dev) / 2;
411}
412
413static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
414{
415 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
416 struct drm_device *dev = intel_dig_port->base.base.dev;
417
418 if (index)
419 return 0;
420
421 if (intel_dig_port->port == PORT_A) {
422 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 423 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 424 else
b84a1cf8 425 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 426 } else {
427 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
428 }
429}
430
431static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
432{
433 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
434 struct drm_device *dev = intel_dig_port->base.base.dev;
435 struct drm_i915_private *dev_priv = dev->dev_private;
436
437 if (intel_dig_port->port == PORT_A) {
438 if (index)
439 return 0;
440 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 441 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
442 /* Workaround for non-ULT HSW */
bc86625a
CW		 443 switch (index) {
444 case 0: return 63;
445 case 1: return 72;
446 default: return 0;
447 }
ec5b01dd 448 } else {
bc86625a 449 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 450 }
b84a1cf8
RV		 451}
452
ec5b01dd
DL		 453static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
454{
455 return index ? 0 : 100;
456}
457
5ed12a19
DL		 458static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
459 bool has_aux_irq,
460 int send_bytes,
461 uint32_t aux_clock_divider)
462{
463 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
464 struct drm_device *dev = intel_dig_port->base.base.dev;
465 uint32_t precharge, timeout;
466
467 if (IS_GEN6(dev))
468 precharge = 3;
469 else
470 precharge = 5;
471
472 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
473 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
474 else
475 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
476
477 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 478 DP_AUX_CH_CTL_DONE |
5ed12a19 479 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 480 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 481 timeout |
788d4433 482 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 483 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
484 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 485 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 486}
487
b84a1cf8
RV		 488static int
489intel_dp_aux_ch(struct intel_dp *intel_dp,
490 uint8_t *send, int send_bytes,
491 uint8_t *recv, int recv_size)
492{
493 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
494 struct drm_device *dev = intel_dig_port->base.base.dev;
495 struct drm_i915_private *dev_priv = dev->dev_private;
496 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
497 uint32_t ch_data = ch_ctl + 4;
bc86625a 498 uint32_t aux_clock_divider;
b84a1cf8
RV		 499 int i, ret, recv_bytes;
500 uint32_t status;
5ed12a19 501 int try, clock = 0;
4e6b788c 502 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 503 bool vdd;
504
505 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 506
507 /* dp aux is extremely sensitive to irq latency, hence request the
508 * lowest possible wakeup latency and so prevent the cpu from going into
509 * deep sleep states.
510 */
511 pm_qos_update_request(&dev_priv->pm_qos, 0);
512
513 intel_dp_check_edp(intel_dp);
5eb08b69 514
c67a470b
PZ		 515 intel_aux_display_runtime_get(dev_priv);
516
11bee43e
JB		 517 /* Try to wait for any previous AUX channel activity */
518 for (try = 0; try < 3; try++) {
ef04f00d 519 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 520 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
521 break;
522 msleep(1);
523 }
524
525 if (try == 3) {
526 WARN(1, "dp_aux_ch not started status 0x%08x\n",
527 I915_READ(ch_ctl));
9ee32fea
DV		 528 ret = -EBUSY;
529 goto out;
4f7f7b7e
CW		 530 }
531
46a5ae9f
PZ		 532 /* Only 5 data registers! */
533 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
534 ret = -E2BIG;
535 goto out;
536 }
537
ec5b01dd 538 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 539 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
540 has_aux_irq,
541 send_bytes,
542 aux_clock_divider);
5ed12a19 543
bc86625a
CW		 544 /* Must try at least 3 times according to DP spec */
545 for (try = 0; try < 5; try++) {
546 /* Load the send data into the aux channel data registers */
547 for (i = 0; i < send_bytes; i += 4)
548 I915_WRITE(ch_data + i,
549 pack_aux(send + i, send_bytes - i));
550
551 /* Send the command and wait for it to complete */
5ed12a19 552 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 553
554 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
555
556 /* Clear done status and any errors */
557 I915_WRITE(ch_ctl,
558 status |
559 DP_AUX_CH_CTL_DONE |
560 DP_AUX_CH_CTL_TIME_OUT_ERROR |
561 DP_AUX_CH_CTL_RECEIVE_ERROR);
562
563 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
564 DP_AUX_CH_CTL_RECEIVE_ERROR))
565 continue;
566 if (status & DP_AUX_CH_CTL_DONE)
567 break;
568 }
4f7f7b7e 569 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 570 break;
571 }
572
a4fc5ed6 573 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 574 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 575 ret = -EBUSY;
576 goto out;
a4fc5ed6
KP		 577 }
578
579 /* Check for timeout or receive error.
580 * Timeouts occur when the sink is not connected
581 */
a5b3da54 582 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 583 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 584 ret = -EIO;
585 goto out;
a5b3da54 586 }
1ae8c0a5
KP		 587
588 /* Timeouts occur when the device isn't connected, so they're
589 * "normal" -- don't fill the kernel log with these */
a5b3da54 590 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 591 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 592 ret = -ETIMEDOUT;
593 goto out;
a4fc5ed6
KP		 594 }
595
596 /* Unload any bytes sent back from the other side */
597 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
598 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 599 if (recv_bytes > recv_size)
600 recv_bytes = recv_size;
0206e353 601
4f7f7b7e
CW		 602 for (i = 0; i < recv_bytes; i += 4)
603 unpack_aux(I915_READ(ch_data + i),
604 recv + i, recv_bytes - i);
a4fc5ed6 605
9ee32fea
DV		 606 ret = recv_bytes;
607out:
608 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 609 intel_aux_display_runtime_put(dev_priv);
9ee32fea 610
884f19e9
JN		 611 if (vdd)
612 edp_panel_vdd_off(intel_dp, false);
613
9ee32fea 614 return ret;
a4fc5ed6
KP		 615}
616
a6c8aff0
JN		 617#define BARE_ADDRESS_SIZE 3
618#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 619static ssize_t
620intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 621{
9d1a1031
JN		 622 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
623 uint8_t txbuf[20], rxbuf[20];
624 size_t txsize, rxsize;
a4fc5ed6 625 int ret;
a4fc5ed6 626
9d1a1031
JN		 627 txbuf[0] = msg->request << 4;
628 txbuf[1] = msg->address >> 8;
629 txbuf[2] = msg->address & 0xff;
630 txbuf[3] = msg->size - 1;
46a5ae9f 631
9d1a1031
JN		 632 switch (msg->request & ~DP_AUX_I2C_MOT) {
633 case DP_AUX_NATIVE_WRITE:
634 case DP_AUX_I2C_WRITE:
a6c8aff0 635 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 636 rxsize = 1;
f51a44b9 637
9d1a1031
JN		 638 if (WARN_ON(txsize > 20))
639 return -E2BIG;
a4fc5ed6 640
9d1a1031 641 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 642
9d1a1031
JN		 643 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
644 if (ret > 0) {
645 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 646
9d1a1031
JN		 647 /* Return payload size. */
648 ret = msg->size;
649 }
650 break;
46a5ae9f 651
9d1a1031
JN		 652 case DP_AUX_NATIVE_READ:
653 case DP_AUX_I2C_READ:
a6c8aff0 654 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 655 rxsize = msg->size + 1;
a4fc5ed6 656
9d1a1031
JN		 657 if (WARN_ON(rxsize > 20))
658 return -E2BIG;
a4fc5ed6 659
9d1a1031
JN		 660 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
661 if (ret > 0) {
662 msg->reply = rxbuf[0] >> 4;
663 /*
664 * Assume happy day, and copy the data. The caller is
665 * expected to check msg->reply before touching it.
666 *
667 * Return payload size.
668 */
669 ret--;
670 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 671 }
9d1a1031
JN		 672 break;
673
674 default:
675 ret = -EINVAL;
676 break;
a4fc5ed6 677 }
f51a44b9 678
9d1a1031 679 return ret;
a4fc5ed6
KP		 680}
681
9d1a1031
JN		 682static void
683intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
684{
685 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 686 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
687 enum port port = intel_dig_port->port;
0b99836f 688 const char *name = NULL;
ab2c0672
DA		 689 int ret;
690
33ad6626
JN		 691 switch (port) {
692 case PORT_A:
693 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 694 name = "DPDDC-A";
ab2c0672 695 break;
33ad6626
JN		 696 case PORT_B:
697 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 698 name = "DPDDC-B";
ab2c0672 699 break;
33ad6626
JN		 700 case PORT_C:
701 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 702 name = "DPDDC-C";
ab2c0672 703 break;
33ad6626
JN		 704 case PORT_D:
705 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 706 name = "DPDDC-D";
33ad6626
JN		 707 break;
708 default:
709 BUG();
ab2c0672
DA		 710 }
711
33ad6626
JN		 712 if (!HAS_DDI(dev))
713 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 714
0b99836f 715 intel_dp->aux.name = name;
9d1a1031
JN		 716 intel_dp->aux.dev = dev->dev;
717 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 718
0b99836f
JN		 719 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
720 connector->base.kdev->kobj.name);
8316f337 721
4f71d0cb 722 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 723 if (ret < 0) {
4f71d0cb 724 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 725 name, ret);
726 return;
ab2c0672 727 }
8a5e6aeb 728
0b99836f
JN		 729 ret = sysfs_create_link(&connector->base.kdev->kobj,
730 &intel_dp->aux.ddc.dev.kobj,
731 intel_dp->aux.ddc.dev.kobj.name);
732 if (ret < 0) {
733 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 734 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 735 }
a4fc5ed6
KP		 736}
737
80f65de3
ID		 738static void
739intel_dp_connector_unregister(struct intel_connector *intel_connector)
740{
741 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
742
743 sysfs_remove_link(&intel_connector->base.kdev->kobj,
0b99836f 744 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 745 intel_connector_unregister(intel_connector);
746}
747
0e50338c
DV		 748static void
749hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
750{
751 switch (link_bw) {
752 case DP_LINK_BW_1_62:
753 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
754 break;
755 case DP_LINK_BW_2_7:
756 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
757 break;
758 case DP_LINK_BW_5_4:
759 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
760 break;
761 }
762}
763
c6bb3538
DV		 764static void
765intel_dp_set_clock(struct intel_encoder *encoder,
766 struct intel_crtc_config *pipe_config, int link_bw)
767{
768 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 769 const struct dp_link_dpll *divisor = NULL;
770 int i, count = 0;
c6bb3538
DV		 771
772 if (IS_G4X(dev)) {
9dd4ffdf
CML		 773 divisor = gen4_dpll;
774 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 775 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 776 divisor = pch_dpll;
777 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 778 } else if (IS_CHERRYVIEW(dev)) {
779 divisor = chv_dpll;
780 count = ARRAY_SIZE(chv_dpll);
c6bb3538 781 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 782 divisor = vlv_dpll;
783 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 784 }
9dd4ffdf
CML		 785
786 if (divisor && count) {
787 for (i = 0; i < count; i++) {
788 if (link_bw == divisor[i].link_bw) {
789 pipe_config->dpll = divisor[i].dpll;
790 pipe_config->clock_set = true;
791 break;
792 }
793 }
c6bb3538
DV		 794 }
795}
796
439d7ac0
PB		 797static void
798intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
799{
800 struct drm_device *dev = crtc->base.dev;
801 struct drm_i915_private *dev_priv = dev->dev_private;
802 enum transcoder transcoder = crtc->config.cpu_transcoder;
803
804 I915_WRITE(PIPE_DATA_M2(transcoder),
805 TU_SIZE(m_n->tu) | m_n->gmch_m);
806 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
807 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
808 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
809}
810
00c09d70 811bool
5bfe2ac0
DV		 812intel_dp_compute_config(struct intel_encoder *encoder,
813 struct intel_crtc_config *pipe_config)
a4fc5ed6 814{
5bfe2ac0 815 struct drm_device *dev = encoder->base.dev;
36008365 816 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 817 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 818 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 819 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 820 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 821 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 822 int lane_count, clock;
56071a20 823 int min_lane_count = 1;
eeb6324d 824 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 825 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 826 int min_clock = 0;
06ea66b6 827 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 828 int bpp, mode_rate;
06ea66b6 829 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 830 int link_avail, link_clock;
a4fc5ed6 831
bc7d38a4 832 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 833 pipe_config->has_pch_encoder = true;
834
03afc4a2 835 pipe_config->has_dp_encoder = true;
9ed109a7 836 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 837
dd06f90e
JN		 838 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
839 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
840 adjusted_mode);
2dd24552
JB		 841 if (!HAS_PCH_SPLIT(dev))
842 intel_gmch_panel_fitting(intel_crtc, pipe_config,
843 intel_connector->panel.fitting_mode);
844 else
b074cec8
JB		 845 intel_pch_panel_fitting(intel_crtc, pipe_config,
846 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 847 }
848
cb1793ce 849 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 850 return false;
851
083f9560
DV		 852 DRM_DEBUG_KMS("DP link computation with max lane count %i "
853 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 854 max_lane_count, bws[max_clock],
855 adjusted_mode->crtc_clock);
083f9560 856
36008365
DV		 857 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
858 * bpc in between. */
3e7ca985 859 bpp = pipe_config->pipe_bpp;
56071a20
JN		 860 if (is_edp(intel_dp)) {
861 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
862 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
863 dev_priv->vbt.edp_bpp);
864 bpp = dev_priv->vbt.edp_bpp;
865 }
866
f4cdbc21
JN		 867 if (IS_BROADWELL(dev)) {
868 /* Yes, it's an ugly hack. */
869 min_lane_count = max_lane_count;
870 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
871 min_lane_count);
872 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 873 min_lane_count = min(dev_priv->vbt.edp_lanes,
874 max_lane_count);
875 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
876 min_lane_count);
877 }
878
879 if (dev_priv->vbt.edp_rate) {
880 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
881 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
882 bws[min_clock]);
883 }
7984211e 884 }
657445fe 885
36008365 886 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 887 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
888 bpp);
36008365 889
56071a20
JN		 890 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
891 for (clock = min_clock; clock <= max_clock; clock++) {
36008365
DV		 892 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
893 link_avail = intel_dp_max_data_rate(link_clock,
894 lane_count);
895
896 if (mode_rate <= link_avail) {
897 goto found;
898 }
899 }
900 }
901 }
c4867936 902
36008365 903 return false;
3685a8f3 904
36008365 905found:
55bc60db
VS		 906 if (intel_dp->color_range_auto) {
907 /*
908 * See:
909 * CEA-861-E - 5.1 Default Encoding Parameters
910 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
911 */
18316c8c 912 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 913 intel_dp->color_range = DP_COLOR_RANGE_16_235;
914 else
915 intel_dp->color_range = 0;
916 }
917
3685a8f3 918 if (intel_dp->color_range)
50f3b016 919 pipe_config->limited_color_range = true;
a4fc5ed6 920
36008365
DV		 921 intel_dp->link_bw = bws[clock];
922 intel_dp->lane_count = lane_count;
657445fe 923 pipe_config->pipe_bpp = bpp;
ff9a6750 924 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 925
36008365
DV		 926 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
927 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 928 pipe_config->port_clock, bpp);
36008365
DV		 929 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
930 mode_rate, link_avail);
a4fc5ed6 931
03afc4a2 932 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 933 adjusted_mode->crtc_clock,
934 pipe_config->port_clock,
03afc4a2 935 &pipe_config->dp_m_n);
9d1a455b 936
439d7ac0
PB		 937 if (intel_connector->panel.downclock_mode != NULL &&
938 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
939 intel_link_compute_m_n(bpp, lane_count,
940 intel_connector->panel.downclock_mode->clock,
941 pipe_config->port_clock,
942 &pipe_config->dp_m2_n2);
943 }
944
0e50338c
DV		 945 if (HAS_DDI(dev))
946 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
947 else
948 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 949
03afc4a2 950 return true;
a4fc5ed6
KP		 951}
952
7c62a164 953static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 954{
7c62a164
DV		 955 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
956 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
957 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 958 struct drm_i915_private *dev_priv = dev->dev_private;
959 u32 dpa_ctl;
960
ff9a6750 961 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 962 dpa_ctl = I915_READ(DP_A);
963 dpa_ctl &= ~DP_PLL_FREQ_MASK;
964
ff9a6750 965 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 966 /* For a long time we've carried around a ILK-DevA w/a for the
967 * 160MHz clock. If we're really unlucky, it's still required.
968 */
969 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 970 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 971 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 972 } else {
973 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 974 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 975 }
1ce17038 976
ea9b6006
DV		 977 I915_WRITE(DP_A, dpa_ctl);
978
979 POSTING_READ(DP_A);
980 udelay(500);
981}
982
8ac33ed3 983static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 984{
b934223d 985 struct drm_device *dev = encoder->base.dev;
417e822d 986 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 987 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 988 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 989 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
990 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 991
417e822d 992 /*
1a2eb460 993 * There are four kinds of DP registers:
417e822d
KP		 994 *
995 * IBX PCH
1a2eb460
KP		 996 * SNB CPU
997 * IVB CPU
417e822d
KP		 998 * CPT PCH
999 *
1000 * IBX PCH and CPU are the same for almost everything,
1001 * except that the CPU DP PLL is configured in this
1002 * register
1003 *
1004 * CPT PCH is quite different, having many bits moved
1005 * to the TRANS_DP_CTL register instead. That
1006 * configuration happens (oddly) in ironlake_pch_enable
1007 */
9c9e7927 1008
417e822d
KP		 1009 /* Preserve the BIOS-computed detected bit. This is
1010 * supposed to be read-only.
1011 */
1012 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1013
417e822d 1014 /* Handle DP bits in common between all three register formats */
417e822d 1015 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1016 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1017
9ed109a7 1018 if (crtc->config.has_audio) {
e0dac65e 1019 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1020 pipe_name(crtc->pipe));
ea5b213a 1021 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1022 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1023 }
247d89f6 1024
417e822d 1025 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1026
bc7d38a4 1027 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1028 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1029 intel_dp->DP |= DP_SYNC_HS_HIGH;
1030 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1031 intel_dp->DP |= DP_SYNC_VS_HIGH;
1032 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1033
6aba5b6c 1034 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1035 intel_dp->DP |= DP_ENHANCED_FRAMING;
1036
7c62a164 1037 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1038 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1039 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1040 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1041
1042 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1043 intel_dp->DP |= DP_SYNC_HS_HIGH;
1044 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1045 intel_dp->DP |= DP_SYNC_VS_HIGH;
1046 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1047
6aba5b6c 1048 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1049 intel_dp->DP |= DP_ENHANCED_FRAMING;
1050
44f37d1f
CML		 1051 if (!IS_CHERRYVIEW(dev)) {
1052 if (crtc->pipe == 1)
1053 intel_dp->DP |= DP_PIPEB_SELECT;
1054 } else {
1055 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1056 }
417e822d
KP		 1057 } else {
1058 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1059 }
a4fc5ed6
KP		 1060}
1061
ffd6749d
PZ		 1062#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1063#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1064
1a5ef5b7
PZ		 1065#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1066#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1067
ffd6749d
PZ		 1068#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1069#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1070
4be73780 1071static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1072 u32 mask,
1073 u32 value)
bd943159 1074{
30add22d 1075 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1076 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1077 u32 pp_stat_reg, pp_ctrl_reg;
1078
bf13e81b
JN		 1079 pp_stat_reg = _pp_stat_reg(intel_dp);
1080 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1081
99ea7127 1082 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1083 mask, value,
1084 I915_READ(pp_stat_reg),
1085 I915_READ(pp_ctrl_reg));
32ce697c 1086
453c5420 1087 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1088 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1089 I915_READ(pp_stat_reg),
1090 I915_READ(pp_ctrl_reg));
32ce697c 1091 }
54c136d4
CW		 1092
1093 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1094}
32ce697c 1095
4be73780 1096static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1097{
1098 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1099 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1100}
1101
4be73780 1102static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1103{
1104 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1105 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1106}
1107
4be73780 1108static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1109{
1110 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1111
1112 /* When we disable the VDD override bit last we have to do the manual
1113 * wait. */
1114 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1115 intel_dp->panel_power_cycle_delay);
1116
4be73780 1117 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1118}
1119
4be73780 1120static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1121{
1122 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1123 intel_dp->backlight_on_delay);
1124}
1125
4be73780 1126static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1127{
1128 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1129 intel_dp->backlight_off_delay);
1130}
99ea7127 1131
832dd3c1
KP		 1132/* Read the current pp_control value, unlocking the register if it
1133 * is locked
1134 */
1135
453c5420 1136static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1137{
453c5420
JB		 1138 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1139 struct drm_i915_private *dev_priv = dev->dev_private;
1140 u32 control;
832dd3c1 1141
bf13e81b 1142 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1143 control &= ~PANEL_UNLOCK_MASK;
1144 control |= PANEL_UNLOCK_REGS;
1145 return control;
bd943159
KP		 1146}
1147
adddaaf4 1148static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1149{
30add22d 1150 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1151 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1152 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1153 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1154 enum intel_display_power_domain power_domain;
5d613501 1155 u32 pp;
453c5420 1156 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1157 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1158
97af61f5 1159 if (!is_edp(intel_dp))
adddaaf4 1160 return false;
bd943159
KP		 1161
1162 intel_dp->want_panel_vdd = true;
99ea7127 1163
4be73780 1164 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1165 return need_to_disable;
b0665d57 1166
4e6e1a54
ID		 1167 power_domain = intel_display_port_power_domain(intel_encoder);
1168 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1169
b0665d57 1170 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1171
4be73780
DV		 1172 if (!edp_have_panel_power(intel_dp))
1173 wait_panel_power_cycle(intel_dp);
99ea7127 1174
453c5420 1175 pp = ironlake_get_pp_control(intel_dp);
5d613501 1176 pp |= EDP_FORCE_VDD;
ebf33b18 1177
bf13e81b
JN		 1178 pp_stat_reg = _pp_stat_reg(intel_dp);
1179 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1180
1181 I915_WRITE(pp_ctrl_reg, pp);
1182 POSTING_READ(pp_ctrl_reg);
1183 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1184 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1185 /*
1186 * If the panel wasn't on, delay before accessing aux channel
1187 */
4be73780 1188 if (!edp_have_panel_power(intel_dp)) {
bd943159 1189 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1190 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1191 }
adddaaf4
JN		 1192
1193 return need_to_disable;
1194}
1195
b80d6c78 1196void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1197{
1198 if (is_edp(intel_dp)) {
1199 bool vdd = _edp_panel_vdd_on(intel_dp);
1200
1201 WARN(!vdd, "eDP VDD already requested on\n");
1202 }
5d613501
JB		 1203}
1204
4be73780 1205static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1206{
30add22d 1207 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1208 struct drm_i915_private *dev_priv = dev->dev_private;
1209 u32 pp;
453c5420 1210 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1211
51fd371b 1212 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
a0e99e68 1213
4be73780 1214 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
4e6e1a54
ID		 1215 struct intel_digital_port *intel_dig_port =
1216 dp_to_dig_port(intel_dp);
1217 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1218 enum intel_display_power_domain power_domain;
1219
b0665d57
PZ		 1220 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1221
453c5420 1222 pp = ironlake_get_pp_control(intel_dp);
bd943159 1223 pp &= ~EDP_FORCE_VDD;
bd943159 1224
9f08ef59
PZ		 1225 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1226 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1227
1228 I915_WRITE(pp_ctrl_reg, pp);
1229 POSTING_READ(pp_ctrl_reg);
99ea7127 1230
453c5420
JB		 1231 /* Make sure sequencer is idle before allowing subsequent activity */
1232 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1233 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1234
1235 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1236 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1237
4e6e1a54
ID		 1238 power_domain = intel_display_port_power_domain(intel_encoder);
1239 intel_display_power_put(dev_priv, power_domain);
bd943159
KP		 1240 }
1241}
5d613501 1242
4be73780 1243static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1244{
1245 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1246 struct intel_dp, panel_vdd_work);
30add22d 1247 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1248
51fd371b 1249 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 1250 edp_panel_vdd_off_sync(intel_dp);
51fd371b 1251 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159
KP		 1252}
1253
4be73780 1254static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1255{
97af61f5
KP		 1256 if (!is_edp(intel_dp))
1257 return;
5d613501 1258
bd943159 1259 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1260
bd943159
KP		 1261 intel_dp->want_panel_vdd = false;
1262
1263 if (sync) {
4be73780 1264 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1265 } else {
1266 /*
1267 * Queue the timer to fire a long
1268 * time from now (relative to the power down delay)
1269 * to keep the panel power up across a sequence of operations
1270 */
1271 schedule_delayed_work(&intel_dp->panel_vdd_work,
1272 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1273 }
5d613501
JB		 1274}
1275
4be73780 1276void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1277{
30add22d 1278 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1279 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1280 u32 pp;
453c5420 1281 u32 pp_ctrl_reg;
9934c132 1282
97af61f5 1283 if (!is_edp(intel_dp))
bd943159 1284 return;
99ea7127
KP		 1285
1286 DRM_DEBUG_KMS("Turn eDP power on\n");
1287
4be73780 1288 if (edp_have_panel_power(intel_dp)) {
99ea7127 1289 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1290 return;
99ea7127 1291 }
9934c132 1292
4be73780 1293 wait_panel_power_cycle(intel_dp);
37c6c9b0 1294
bf13e81b 1295 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1296 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1297 if (IS_GEN5(dev)) {
1298 /* ILK workaround: disable reset around power sequence */
1299 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1300 I915_WRITE(pp_ctrl_reg, pp);
1301 POSTING_READ(pp_ctrl_reg);
05ce1a49 1302 }
37c6c9b0 1303
1c0ae80a 1304 pp |= POWER_TARGET_ON;
99ea7127
KP		 1305 if (!IS_GEN5(dev))
1306 pp |= PANEL_POWER_RESET;
1307
453c5420
JB		 1308 I915_WRITE(pp_ctrl_reg, pp);
1309 POSTING_READ(pp_ctrl_reg);
9934c132 1310
4be73780 1311 wait_panel_on(intel_dp);
dce56b3c 1312 intel_dp->last_power_on = jiffies;
9934c132 1313
05ce1a49
KP		 1314 if (IS_GEN5(dev)) {
1315 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1316 I915_WRITE(pp_ctrl_reg, pp);
1317 POSTING_READ(pp_ctrl_reg);
05ce1a49 1318 }
9934c132
JB		 1319}
1320
4be73780 1321void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1322{
4e6e1a54
ID		 1323 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1324 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1325 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1326 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1327 enum intel_display_power_domain power_domain;
99ea7127 1328 u32 pp;
453c5420 1329 u32 pp_ctrl_reg;
9934c132 1330
97af61f5
KP		 1331 if (!is_edp(intel_dp))
1332 return;
37c6c9b0 1333
99ea7127 1334 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1335
24f3e092
JN		 1336 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1337
453c5420 1338 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1339 /* We need to switch off panel power _and_ force vdd, for otherwise some
1340 * panels get very unhappy and cease to work. */
b3064154
PJ		 1341 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1342 EDP_BLC_ENABLE);
453c5420 1343
bf13e81b 1344 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1345
849e39f5
PZ		 1346 intel_dp->want_panel_vdd = false;
1347
453c5420
JB		 1348 I915_WRITE(pp_ctrl_reg, pp);
1349 POSTING_READ(pp_ctrl_reg);
9934c132 1350
dce56b3c 1351 intel_dp->last_power_cycle = jiffies;
4be73780 1352 wait_panel_off(intel_dp);
849e39f5
PZ		 1353
1354 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1355 power_domain = intel_display_port_power_domain(intel_encoder);
1356 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1357}
1358
4be73780 1359void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1360{
da63a9f2
PZ		 1361 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1362 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1363 struct drm_i915_private *dev_priv = dev->dev_private;
1364 u32 pp;
453c5420 1365 u32 pp_ctrl_reg;
32f9d658 1366
f01eca2e
KP		 1367 if (!is_edp(intel_dp))
1368 return;
1369
28c97730 1370 DRM_DEBUG_KMS("\n");
f7d2323c
JB		 1371
1372 intel_panel_enable_backlight(intel_dp->attached_connector);
1373
01cb9ea6
JB		 1374 /*
1375 * If we enable the backlight right away following a panel power
1376 * on, we may see slight flicker as the panel syncs with the eDP
1377 * link. So delay a bit to make sure the image is solid before
1378 * allowing it to appear.
1379 */
4be73780 1380 wait_backlight_on(intel_dp);
453c5420 1381 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1382 pp |= EDP_BLC_ENABLE;
453c5420 1383
bf13e81b 1384 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1385
1386 I915_WRITE(pp_ctrl_reg, pp);
1387 POSTING_READ(pp_ctrl_reg);
32f9d658
ZW		 1388}
1389
4be73780 1390void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1391{
30add22d 1392 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1393 struct drm_i915_private *dev_priv = dev->dev_private;
1394 u32 pp;
453c5420 1395 u32 pp_ctrl_reg;
32f9d658 1396
f01eca2e
KP		 1397 if (!is_edp(intel_dp))
1398 return;
1399
28c97730 1400 DRM_DEBUG_KMS("\n");
453c5420 1401 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1402 pp &= ~EDP_BLC_ENABLE;
453c5420 1403
bf13e81b 1404 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1405
1406 I915_WRITE(pp_ctrl_reg, pp);
1407 POSTING_READ(pp_ctrl_reg);
dce56b3c 1408 intel_dp->last_backlight_off = jiffies;
f7d2323c
JB		 1409
1410 edp_wait_backlight_off(intel_dp);
1411
1412 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1413}
a4fc5ed6 1414
2bd2ad64 1415static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1416{
da63a9f2
PZ		 1417 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1418 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1419 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1420 struct drm_i915_private *dev_priv = dev->dev_private;
1421 u32 dpa_ctl;
1422
2bd2ad64
DV		 1423 assert_pipe_disabled(dev_priv,
1424 to_intel_crtc(crtc)->pipe);
1425
d240f20f
JB		 1426 DRM_DEBUG_KMS("\n");
1427 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1428 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1429 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1430
1431 /* We don't adjust intel_dp->DP while tearing down the link, to
1432 * facilitate link retraining (e.g. after hotplug). Hence clear all
1433 * enable bits here to ensure that we don't enable too much. */
1434 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1435 intel_dp->DP |= DP_PLL_ENABLE;
1436 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1437 POSTING_READ(DP_A);
1438 udelay(200);
d240f20f
JB		 1439}
1440
2bd2ad64 1441static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1442{
da63a9f2
PZ		 1443 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1444 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1445 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1446 struct drm_i915_private *dev_priv = dev->dev_private;
1447 u32 dpa_ctl;
1448
2bd2ad64
DV		 1449 assert_pipe_disabled(dev_priv,
1450 to_intel_crtc(crtc)->pipe);
1451
d240f20f 1452 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1453 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1454 "dp pll off, should be on\n");
1455 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1456
1457 /* We can't rely on the value tracked for the DP register in
1458 * intel_dp->DP because link_down must not change that (otherwise link
1459 * re-training will fail. */
298b0b39 1460 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1461 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1462 POSTING_READ(DP_A);
d240f20f
JB		 1463 udelay(200);
1464}
1465
c7ad3810 1466/* If the sink supports it, try to set the power state appropriately */
c19b0669 1467void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1468{
1469 int ret, i;
1470
1471 /* Should have a valid DPCD by this point */
1472 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1473 return;
1474
1475 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1476 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1477 DP_SET_POWER_D3);
c7ad3810
JB		 1478 if (ret != 1)
1479 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1480 } else {
1481 /*
1482 * When turning on, we need to retry for 1ms to give the sink
1483 * time to wake up.
1484 */
1485 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1486 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1487 DP_SET_POWER_D0);
c7ad3810
JB		 1488 if (ret == 1)
1489 break;
1490 msleep(1);
1491 }
1492 }
1493}
1494
19d8fe15
DV		 1495static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1496 enum pipe *pipe)
d240f20f 1497{
19d8fe15 1498 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1499 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1500 struct drm_device *dev = encoder->base.dev;
1501 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1502 enum intel_display_power_domain power_domain;
1503 u32 tmp;
1504
1505 power_domain = intel_display_port_power_domain(encoder);
1506 if (!intel_display_power_enabled(dev_priv, power_domain))
1507 return false;
1508
1509 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1510
1511 if (!(tmp & DP_PORT_EN))
1512 return false;
1513
bc7d38a4 1514 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1515 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1516 } else if (IS_CHERRYVIEW(dev)) {
1517 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1518 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1519 *pipe = PORT_TO_PIPE(tmp);
1520 } else {
1521 u32 trans_sel;
1522 u32 trans_dp;
1523 int i;
1524
1525 switch (intel_dp->output_reg) {
1526 case PCH_DP_B:
1527 trans_sel = TRANS_DP_PORT_SEL_B;
1528 break;
1529 case PCH_DP_C:
1530 trans_sel = TRANS_DP_PORT_SEL_C;
1531 break;
1532 case PCH_DP_D:
1533 trans_sel = TRANS_DP_PORT_SEL_D;
1534 break;
1535 default:
1536 return true;
1537 }
1538
1539 for_each_pipe(i) {
1540 trans_dp = I915_READ(TRANS_DP_CTL(i));
1541 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1542 *pipe = i;
1543 return true;
1544 }
1545 }
19d8fe15 1546
4a0833ec
DV		 1547 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1548 intel_dp->output_reg);
1549 }
d240f20f 1550
19d8fe15
DV		 1551 return true;
1552}
d240f20f 1553
045ac3b5
JB		 1554static void intel_dp_get_config(struct intel_encoder *encoder,
1555 struct intel_crtc_config *pipe_config)
1556{
1557 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1558 u32 tmp, flags = 0;
63000ef6
XZ		 1559 struct drm_device *dev = encoder->base.dev;
1560 struct drm_i915_private *dev_priv = dev->dev_private;
1561 enum port port = dp_to_dig_port(intel_dp)->port;
1562 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1563 int dotclock;
045ac3b5 1564
9ed109a7
DV		 1565 tmp = I915_READ(intel_dp->output_reg);
1566 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1567 pipe_config->has_audio = true;
1568
63000ef6 1569 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1570 if (tmp & DP_SYNC_HS_HIGH)
1571 flags |= DRM_MODE_FLAG_PHSYNC;
1572 else
1573 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1574
63000ef6
XZ		 1575 if (tmp & DP_SYNC_VS_HIGH)
1576 flags |= DRM_MODE_FLAG_PVSYNC;
1577 else
1578 flags |= DRM_MODE_FLAG_NVSYNC;
1579 } else {
1580 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1581 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1582 flags |= DRM_MODE_FLAG_PHSYNC;
1583 else
1584 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1585
63000ef6
XZ		 1586 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1587 flags |= DRM_MODE_FLAG_PVSYNC;
1588 else
1589 flags |= DRM_MODE_FLAG_NVSYNC;
1590 }
045ac3b5
JB		 1591
1592 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1593
eb14cb74
VS		 1594 pipe_config->has_dp_encoder = true;
1595
1596 intel_dp_get_m_n(crtc, pipe_config);
1597
18442d08 1598 if (port == PORT_A) {
f1f644dc
JB		 1599 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1600 pipe_config->port_clock = 162000;
1601 else
1602 pipe_config->port_clock = 270000;
1603 }
18442d08
VS		 1604
1605 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1606 &pipe_config->dp_m_n);
1607
1608 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1609 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1610
241bfc38 1611 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1612
c6cd2ee2
JN		 1613 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1614 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1615 /*
1616 * This is a big fat ugly hack.
1617 *
1618 * Some machines in UEFI boot mode provide us a VBT that has 18
1619 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1620 * unknown we fail to light up. Yet the same BIOS boots up with
1621 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1622 * max, not what it tells us to use.
1623 *
1624 * Note: This will still be broken if the eDP panel is not lit
1625 * up by the BIOS, and thus we can't get the mode at module
1626 * load.
1627 */
1628 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1629 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1630 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1631 }
045ac3b5
JB		 1632}
1633
34eb7579 1634static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1635{
34eb7579 1636 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1637}
1638
2b28bb1b
RV		 1639static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1640{
1641 struct drm_i915_private *dev_priv = dev->dev_private;
1642
18b5992c 1643 if (!HAS_PSR(dev))
2b28bb1b
RV		 1644 return false;
1645
18b5992c 1646 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1647}
1648
1649static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1650 struct edp_vsc_psr *vsc_psr)
1651{
1652 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1653 struct drm_device *dev = dig_port->base.base.dev;
1654 struct drm_i915_private *dev_priv = dev->dev_private;
1655 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1656 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1657 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1658 uint32_t *data = (uint32_t *) vsc_psr;
1659 unsigned int i;
1660
1661 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1662 the video DIP being updated before program video DIP data buffer
1663 registers for DIP being updated. */
1664 I915_WRITE(ctl_reg, 0);
1665 POSTING_READ(ctl_reg);
1666
1667 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1668 if (i < sizeof(struct edp_vsc_psr))
1669 I915_WRITE(data_reg + i, *data++);
1670 else
1671 I915_WRITE(data_reg + i, 0);
1672 }
1673
1674 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1675 POSTING_READ(ctl_reg);
1676}
1677
1678static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1679{
1680 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1681 struct drm_i915_private *dev_priv = dev->dev_private;
1682 struct edp_vsc_psr psr_vsc;
1683
2b28bb1b
RV		 1684 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1685 memset(&psr_vsc, 0, sizeof(psr_vsc));
1686 psr_vsc.sdp_header.HB0 = 0;
1687 psr_vsc.sdp_header.HB1 = 0x7;
1688 psr_vsc.sdp_header.HB2 = 0x2;
1689 psr_vsc.sdp_header.HB3 = 0x8;
1690 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1691
1692 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1693 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1694 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1695}
1696
1697static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1698{
0e0ae652
RV		 1699 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1700 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 1701 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1702 uint32_t aux_clock_divider;
2b28bb1b
RV		 1703 int precharge = 0x3;
1704 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 1705 bool only_standby = false;
2b28bb1b 1706
ec5b01dd
DL		 1707 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1708
0e0ae652
RV		 1709 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1710 only_standby = true;
1711
2b28bb1b 1712 /* Enable PSR in sink */
0e0ae652 1713 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 1714 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1715 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1716 else
9d1a1031
JN		 1717 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1718 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1719
1720 /* Setup AUX registers */
18b5992c
BW		 1721 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1722 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1723 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1724 DP_AUX_CH_CTL_TIME_OUT_400us |
1725 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1726 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1727 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1728}
1729
1730static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1731{
0e0ae652
RV		 1732 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1733 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 1734 struct drm_i915_private *dev_priv = dev->dev_private;
1735 uint32_t max_sleep_time = 0x1f;
1736 uint32_t idle_frames = 1;
1737 uint32_t val = 0x0;
ed8546ac 1738 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 1739 bool only_standby = false;
1740
1741 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1742 only_standby = true;
2b28bb1b 1743
0e0ae652 1744 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 1745 val |= EDP_PSR_LINK_STANDBY;
1746 val |= EDP_PSR_TP2_TP3_TIME_0us;
1747 val |= EDP_PSR_TP1_TIME_0us;
1748 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 1749 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 1750 } else
1751 val |= EDP_PSR_LINK_DISABLE;
1752
18b5992c 1753 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1754 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1755 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1756 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1757 EDP_PSR_ENABLE);
1758}
1759
3f51e471
RV		 1760static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1761{
1762 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1763 struct drm_device *dev = dig_port->base.base.dev;
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1765 struct drm_crtc *crtc = dig_port->base.base.crtc;
1766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2ff8fde1 1767 struct drm_i915_gem_object *obj = intel_fb_obj(crtc->primary->fb);
3f51e471
RV		 1768 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1769
a031d709
RV		 1770 dev_priv->psr.source_ok = false;
1771
0e0ae652
RV		 1772 if (!HAS_PSR(dev)) {
1773 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1774 return false;
1775 }
1776
1777 if (IS_HASWELL(dev) && (intel_encoder->type != INTEL_OUTPUT_EDP ||
1778 dig_port->port != PORT_A)) {
3f51e471 1779 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1780 return false;
1781 }
1782
d330a953 1783 if (!i915.enable_psr) {
105b7c11 1784 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1785 return false;
1786 }
1787
cd234b0b
CW		 1788 crtc = dig_port->base.base.crtc;
1789 if (crtc == NULL) {
1790 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1791 return false;
1792 }
1793
1794 intel_crtc = to_intel_crtc(crtc);
20ddf665 1795 if (!intel_crtc_active(crtc)) {
3f51e471 1796 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1797 return false;
1798 }
1799
1800 if (obj->tiling_mode != I915_TILING_X ||
1801 obj->fence_reg == I915_FENCE_REG_NONE) {
1802 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1803 return false;
1804 }
1805
4c8c7000
RV		 1806 /* Below limitations aren't valid for Broadwell */
1807 if (IS_BROADWELL(dev))
1808 goto out;
1809
3f51e471
RV		 1810 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1811 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1812 return false;
1813 }
1814
1815 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1816 S3D_ENABLE) {
1817 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1818 return false;
1819 }
1820
ca73b4f0 1821 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1822 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1823 return false;
1824 }
1825
4c8c7000 1826 out:
a031d709 1827 dev_priv->psr.source_ok = true;
3f51e471
RV		 1828 return true;
1829}
1830
3d739d92 1831static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 1832{
7c8f8a70
RV		 1833 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1834 struct drm_device *dev = intel_dig_port->base.base.dev;
1835 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 1836
7c8f8a70 1837 if (intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1838 return;
1839
2b28bb1b
RV		 1840 /* Enable PSR on the panel */
1841 intel_edp_psr_enable_sink(intel_dp);
1842
1843 /* Enable PSR on the host */
1844 intel_edp_psr_enable_source(intel_dp);
7c8f8a70
RV		 1845
1846 dev_priv->psr.enabled = true;
1847 dev_priv->psr.active = true;
2b28bb1b
RV		 1848}
1849
3d739d92
RV		 1850void intel_edp_psr_enable(struct intel_dp *intel_dp)
1851{
1852 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1853
4704c573
RV		 1854 if (!HAS_PSR(dev)) {
1855 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1856 return;
1857 }
1858
34eb7579
RV		 1859 if (!is_edp_psr(intel_dp)) {
1860 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1861 return;
1862 }
1863
16487254
RV		 1864 /* Setup PSR once */
1865 intel_edp_psr_setup(intel_dp);
1866
7c8f8a70 1867 if (intel_edp_psr_match_conditions(intel_dp))
3d739d92
RV		 1868 intel_edp_psr_do_enable(intel_dp);
1869}
1870
2b28bb1b
RV		 1871void intel_edp_psr_disable(struct intel_dp *intel_dp)
1872{
1873 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1874 struct drm_i915_private *dev_priv = dev->dev_private;
1875
7c8f8a70 1876 if (!dev_priv->psr.enabled)
2b28bb1b
RV		 1877 return;
1878
18b5992c
BW		 1879 I915_WRITE(EDP_PSR_CTL(dev),
1880 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1881
1882 /* Wait till PSR is idle */
18b5992c 1883 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1884 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1885 DRM_ERROR("Timed out waiting for PSR Idle State\n");
7c8f8a70
RV		 1886
1887 dev_priv->psr.enabled = false;
2b28bb1b
RV		 1888}
1889
f02a326e 1890static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 1891{
1892 struct drm_i915_private *dev_priv =
1893 container_of(work, typeof(*dev_priv), psr.work.work);
1894 struct drm_device *dev = dev_priv->dev;
1895 struct intel_encoder *encoder;
1896 struct intel_dp *intel_dp = NULL;
1897
3d739d92
RV		 1898 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1899 if (encoder->type == INTEL_OUTPUT_EDP) {
1900 intel_dp = enc_to_intel_dp(&encoder->base);
1901
3d739d92
RV		 1902 if (!intel_edp_psr_match_conditions(intel_dp))
1903 intel_edp_psr_disable(intel_dp);
1904 else
7c8f8a70 1905 intel_edp_psr_do_enable(intel_dp);
3d739d92
RV		 1906 }
1907}
1908
f02a326e 1909static void intel_edp_psr_inactivate(struct drm_device *dev)
7c8f8a70
RV		 1910{
1911 struct drm_i915_private *dev_priv = dev->dev_private;
7c8f8a70 1912
77c70c56 1913 dev_priv->psr.active = false;
7c8f8a70 1914
77c70c56
DV		 1915 I915_WRITE(EDP_PSR_CTL(dev), I915_READ(EDP_PSR_CTL(dev))
1916 & ~EDP_PSR_ENABLE);
7c8f8a70
RV		 1917}
1918
3108e99e 1919void intel_edp_psr_exit(struct drm_device *dev)
7c8f8a70
RV		 1920{
1921 struct drm_i915_private *dev_priv = dev->dev_private;
1922
1923 if (!HAS_PSR(dev))
1924 return;
1925
9a603f48 1926 if (!dev_priv->psr.enabled)
7c8f8a70
RV		 1927 return;
1928
1929 cancel_delayed_work_sync(&dev_priv->psr.work);
1930
1931 if (dev_priv->psr.active)
1932 intel_edp_psr_inactivate(dev);
1933
3108e99e
DV		 1934 schedule_delayed_work(&dev_priv->psr.work,
1935 msecs_to_jiffies(100));
7c8f8a70
RV		 1936}
1937
1938void intel_edp_psr_init(struct drm_device *dev)
1939{
1940 struct drm_i915_private *dev_priv = dev->dev_private;
1941
1942 if (!HAS_PSR(dev))
1943 return;
1944
1945 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
1946}
1947
e8cb4558 1948static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1949{
e8cb4558 1950 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1951 enum port port = dp_to_dig_port(intel_dp)->port;
1952 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1953
1954 /* Make sure the panel is off before trying to change the mode. But also
1955 * ensure that we have vdd while we switch off the panel. */
24f3e092 1956 intel_edp_panel_vdd_on(intel_dp);
4be73780 1957 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1958 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1959 intel_edp_panel_off(intel_dp);
3739850b
DV		 1960
1961 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1962 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1963 intel_dp_link_down(intel_dp);
d240f20f
JB		 1964}
1965
49277c31 1966static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1967{
2bd2ad64 1968 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1969 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 1970
49277c31
VS		 1971 if (port != PORT_A)
1972 return;
1973
1974 intel_dp_link_down(intel_dp);
1975 ironlake_edp_pll_off(intel_dp);
1976}
1977
1978static void vlv_post_disable_dp(struct intel_encoder *encoder)
1979{
1980 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1981
1982 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 1983}
1984
580d3811
VS		 1985static void chv_post_disable_dp(struct intel_encoder *encoder)
1986{
1987 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1988 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1989 struct drm_device *dev = encoder->base.dev;
1990 struct drm_i915_private *dev_priv = dev->dev_private;
1991 struct intel_crtc *intel_crtc =
1992 to_intel_crtc(encoder->base.crtc);
1993 enum dpio_channel ch = vlv_dport_to_channel(dport);
1994 enum pipe pipe = intel_crtc->pipe;
1995 u32 val;
1996
1997 intel_dp_link_down(intel_dp);
1998
1999 mutex_lock(&dev_priv->dpio_lock);
2000
2001 /* Propagate soft reset to data lane reset */
97fd4d5c 2002 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2003 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2004 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2005
97fd4d5c
VS		 2006 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2007 val |= CHV_PCS_REQ_SOFTRESET_EN;
2008 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2009
2010 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2011 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2012 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2013
2014 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2015 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2016 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2017
2018 mutex_unlock(&dev_priv->dpio_lock);
2019}
2020
e8cb4558 2021static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2022{
e8cb4558
DV		 2023 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2024 struct drm_device *dev = encoder->base.dev;
2025 struct drm_i915_private *dev_priv = dev->dev_private;
2026 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2027
0c33d8d7
DV		 2028 if (WARN_ON(dp_reg & DP_PORT_EN))
2029 return;
5d613501 2030
24f3e092 2031 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 2032 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2033 intel_dp_start_link_train(intel_dp);
4be73780
DV		 2034 intel_edp_panel_on(intel_dp);
2035 edp_panel_vdd_off(intel_dp, true);
33a34e4e 2036 intel_dp_complete_link_train(intel_dp);
3ab9c637 2037 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2038}
89b667f8 2039
ecff4f3b
JN		 2040static void g4x_enable_dp(struct intel_encoder *encoder)
2041{
828f5c6e
JN		 2042 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2043
ecff4f3b 2044 intel_enable_dp(encoder);
4be73780 2045 intel_edp_backlight_on(intel_dp);
ab1f90f9 2046}
89b667f8 2047
ab1f90f9
JN		 2048static void vlv_enable_dp(struct intel_encoder *encoder)
2049{
828f5c6e
JN		 2050 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2051
4be73780 2052 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2053}
2054
ecff4f3b 2055static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2056{
2057 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2058 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2059
8ac33ed3
DV		 2060 intel_dp_prepare(encoder);
2061
d41f1efb
DV		 2062 /* Only ilk+ has port A */
2063 if (dport->port == PORT_A) {
2064 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2065 ironlake_edp_pll_on(intel_dp);
d41f1efb 2066 }
ab1f90f9
JN		 2067}
2068
2069static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2070{
2bd2ad64 2071 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2072 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2073 struct drm_device *dev = encoder->base.dev;
89b667f8 2074 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2075 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2076 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 2077 int pipe = intel_crtc->pipe;
bf13e81b 2078 struct edp_power_seq power_seq;
ab1f90f9 2079 u32 val;
a4fc5ed6 2080
ab1f90f9 2081 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2082
ab3c759a 2083 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2084 val = 0;
2085 if (pipe)
2086 val |= (1<<21);
2087 else
2088 val &= ~(1<<21);
2089 val |= 0x001000c4;
ab3c759a
CML		 2090 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2091 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2092 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2093
ab1f90f9
JN		 2094 mutex_unlock(&dev_priv->dpio_lock);
2095
2cac613b
ID		 2096 if (is_edp(intel_dp)) {
2097 /* init power sequencer on this pipe and port */
2098 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2099 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2100 &power_seq);
2101 }
bf13e81b 2102
ab1f90f9
JN		 2103 intel_enable_dp(encoder);
2104
e4607fcf 2105 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2106}
2107
ecff4f3b 2108static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2109{
2110 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2111 struct drm_device *dev = encoder->base.dev;
2112 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2113 struct intel_crtc *intel_crtc =
2114 to_intel_crtc(encoder->base.crtc);
e4607fcf 2115 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2116 int pipe = intel_crtc->pipe;
89b667f8 2117
8ac33ed3
DV		 2118 intel_dp_prepare(encoder);
2119
89b667f8 2120 /* Program Tx lane resets to default */
0980a60f 2121 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2122 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2123 DPIO_PCS_TX_LANE2_RESET |
2124 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2125 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2126 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2127 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2128 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2129 DPIO_PCS_CLK_SOFT_RESET);
2130
2131 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2132 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2133 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2134 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2135 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2136}
2137
e4a1d846
CML		 2138static void chv_pre_enable_dp(struct intel_encoder *encoder)
2139{
2140 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2141 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2142 struct drm_device *dev = encoder->base.dev;
2143 struct drm_i915_private *dev_priv = dev->dev_private;
2144 struct edp_power_seq power_seq;
2145 struct intel_crtc *intel_crtc =
2146 to_intel_crtc(encoder->base.crtc);
2147 enum dpio_channel ch = vlv_dport_to_channel(dport);
2148 int pipe = intel_crtc->pipe;
2149 int data, i;
949c1d43 2150 u32 val;
e4a1d846 2151
e4a1d846 2152 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2153
2154 /* Deassert soft data lane reset*/
97fd4d5c 2155 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2156 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2157 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2158
2159 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2160 val |= CHV_PCS_REQ_SOFTRESET_EN;
2161 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2162
2163 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2164 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2165 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2166
97fd4d5c 2167 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2168 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2169 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2170
2171 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2172 for (i = 0; i < 4; i++) {
2173 /* Set the latency optimal bit */
2174 data = (i == 1) ? 0x0 : 0x6;
2175 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2176 data << DPIO_FRC_LATENCY_SHFIT);
2177
2178 /* Set the upar bit */
2179 data = (i == 1) ? 0x0 : 0x1;
2180 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2181 data << DPIO_UPAR_SHIFT);
2182 }
2183
2184 /* Data lane stagger programming */
2185 /* FIXME: Fix up value only after power analysis */
2186
2187 mutex_unlock(&dev_priv->dpio_lock);
2188
2189 if (is_edp(intel_dp)) {
2190 /* init power sequencer on this pipe and port */
2191 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2192 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2193 &power_seq);
2194 }
2195
2196 intel_enable_dp(encoder);
2197
2198 vlv_wait_port_ready(dev_priv, dport);
2199}
2200
9197c88b
VS		 2201static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2202{
2203 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2204 struct drm_device *dev = encoder->base.dev;
2205 struct drm_i915_private *dev_priv = dev->dev_private;
2206 struct intel_crtc *intel_crtc =
2207 to_intel_crtc(encoder->base.crtc);
2208 enum dpio_channel ch = vlv_dport_to_channel(dport);
2209 enum pipe pipe = intel_crtc->pipe;
2210 u32 val;
2211
2212 mutex_lock(&dev_priv->dpio_lock);
2213
b9e5ac3c
VS		 2214 /* program left/right clock distribution */
2215 if (pipe != PIPE_B) {
2216 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2217 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2218 if (ch == DPIO_CH0)
2219 val |= CHV_BUFLEFTENA1_FORCE;
2220 if (ch == DPIO_CH1)
2221 val |= CHV_BUFRIGHTENA1_FORCE;
2222 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2223 } else {
2224 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2225 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2226 if (ch == DPIO_CH0)
2227 val |= CHV_BUFLEFTENA2_FORCE;
2228 if (ch == DPIO_CH1)
2229 val |= CHV_BUFRIGHTENA2_FORCE;
2230 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2231 }
2232
9197c88b
VS		 2233 /* program clock channel usage */
2234 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2235 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2236 if (pipe != PIPE_B)
2237 val &= ~CHV_PCS_USEDCLKCHANNEL;
2238 else
2239 val |= CHV_PCS_USEDCLKCHANNEL;
2240 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2241
2242 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2243 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2244 if (pipe != PIPE_B)
2245 val &= ~CHV_PCS_USEDCLKCHANNEL;
2246 else
2247 val |= CHV_PCS_USEDCLKCHANNEL;
2248 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2249
2250 /*
2251 * This a a bit weird since generally CL
2252 * matches the pipe, but here we need to
2253 * pick the CL based on the port.
2254 */
2255 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2256 if (pipe != PIPE_B)
2257 val &= ~CHV_CMN_USEDCLKCHANNEL;
2258 else
2259 val |= CHV_CMN_USEDCLKCHANNEL;
2260 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2261
2262 mutex_unlock(&dev_priv->dpio_lock);
2263}
2264
a4fc5ed6 2265/*
df0c237d
JB		 2266 * Native read with retry for link status and receiver capability reads for
2267 * cases where the sink may still be asleep.
9d1a1031
JN		 2268 *
2269 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2270 * supposed to retry 3 times per the spec.
a4fc5ed6 2271 */
9d1a1031
JN		 2272static ssize_t
2273intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2274 void *buffer, size_t size)
a4fc5ed6 2275{
9d1a1031
JN		 2276 ssize_t ret;
2277 int i;
61da5fab 2278
61da5fab 2279 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2280 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2281 if (ret == size)
2282 return ret;
61da5fab
JB		 2283 msleep(1);
2284 }
a4fc5ed6 2285
9d1a1031 2286 return ret;
a4fc5ed6
KP		 2287}
2288
2289/*
2290 * Fetch AUX CH registers 0x202 - 0x207 which contain
2291 * link status information
2292 */
2293static bool
93f62dad 2294intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2295{
9d1a1031
JN		 2296 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2297 DP_LANE0_1_STATUS,
2298 link_status,
2299 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2300}
2301
1100244e 2302/* These are source-specific values. */
a4fc5ed6 2303static uint8_t
1a2eb460 2304intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2305{
30add22d 2306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2307 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2308
9576c27f 2309 if (IS_VALLEYVIEW(dev))
e2fa6fba 2310 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2311 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2312 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2313 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2314 return DP_TRAIN_VOLTAGE_SWING_1200;
2315 else
2316 return DP_TRAIN_VOLTAGE_SWING_800;
2317}
2318
2319static uint8_t
2320intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2321{
30add22d 2322 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2323 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2324
9576c27f 2325 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722
PZ		 2326 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2327 case DP_TRAIN_VOLTAGE_SWING_400:
2328 return DP_TRAIN_PRE_EMPHASIS_9_5;
2329 case DP_TRAIN_VOLTAGE_SWING_600:
2330 return DP_TRAIN_PRE_EMPHASIS_6;
2331 case DP_TRAIN_VOLTAGE_SWING_800:
2332 return DP_TRAIN_PRE_EMPHASIS_3_5;
2333 case DP_TRAIN_VOLTAGE_SWING_1200:
2334 default:
2335 return DP_TRAIN_PRE_EMPHASIS_0;
2336 }
e2fa6fba
P		 2337 } else if (IS_VALLEYVIEW(dev)) {
2338 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2339 case DP_TRAIN_VOLTAGE_SWING_400:
2340 return DP_TRAIN_PRE_EMPHASIS_9_5;
2341 case DP_TRAIN_VOLTAGE_SWING_600:
2342 return DP_TRAIN_PRE_EMPHASIS_6;
2343 case DP_TRAIN_VOLTAGE_SWING_800:
2344 return DP_TRAIN_PRE_EMPHASIS_3_5;
2345 case DP_TRAIN_VOLTAGE_SWING_1200:
2346 default:
2347 return DP_TRAIN_PRE_EMPHASIS_0;
2348 }
bc7d38a4 2349 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2350 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2351 case DP_TRAIN_VOLTAGE_SWING_400:
2352 return DP_TRAIN_PRE_EMPHASIS_6;
2353 case DP_TRAIN_VOLTAGE_SWING_600:
2354 case DP_TRAIN_VOLTAGE_SWING_800:
2355 return DP_TRAIN_PRE_EMPHASIS_3_5;
2356 default:
2357 return DP_TRAIN_PRE_EMPHASIS_0;
2358 }
2359 } else {
2360 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2361 case DP_TRAIN_VOLTAGE_SWING_400:
2362 return DP_TRAIN_PRE_EMPHASIS_6;
2363 case DP_TRAIN_VOLTAGE_SWING_600:
2364 return DP_TRAIN_PRE_EMPHASIS_6;
2365 case DP_TRAIN_VOLTAGE_SWING_800:
2366 return DP_TRAIN_PRE_EMPHASIS_3_5;
2367 case DP_TRAIN_VOLTAGE_SWING_1200:
2368 default:
2369 return DP_TRAIN_PRE_EMPHASIS_0;
2370 }
a4fc5ed6
KP		 2371 }
2372}
2373
e2fa6fba
P		 2374static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2375{
2376 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2377 struct drm_i915_private *dev_priv = dev->dev_private;
2378 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2379 struct intel_crtc *intel_crtc =
2380 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2381 unsigned long demph_reg_value, preemph_reg_value,
2382 uniqtranscale_reg_value;
2383 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2384 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2385 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2386
2387 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2388 case DP_TRAIN_PRE_EMPHASIS_0:
2389 preemph_reg_value = 0x0004000;
2390 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2391 case DP_TRAIN_VOLTAGE_SWING_400:
2392 demph_reg_value = 0x2B405555;
2393 uniqtranscale_reg_value = 0x552AB83A;
2394 break;
2395 case DP_TRAIN_VOLTAGE_SWING_600:
2396 demph_reg_value = 0x2B404040;
2397 uniqtranscale_reg_value = 0x5548B83A;
2398 break;
2399 case DP_TRAIN_VOLTAGE_SWING_800:
2400 demph_reg_value = 0x2B245555;
2401 uniqtranscale_reg_value = 0x5560B83A;
2402 break;
2403 case DP_TRAIN_VOLTAGE_SWING_1200:
2404 demph_reg_value = 0x2B405555;
2405 uniqtranscale_reg_value = 0x5598DA3A;
2406 break;
2407 default:
2408 return 0;
2409 }
2410 break;
2411 case DP_TRAIN_PRE_EMPHASIS_3_5:
2412 preemph_reg_value = 0x0002000;
2413 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2414 case DP_TRAIN_VOLTAGE_SWING_400:
2415 demph_reg_value = 0x2B404040;
2416 uniqtranscale_reg_value = 0x5552B83A;
2417 break;
2418 case DP_TRAIN_VOLTAGE_SWING_600:
2419 demph_reg_value = 0x2B404848;
2420 uniqtranscale_reg_value = 0x5580B83A;
2421 break;
2422 case DP_TRAIN_VOLTAGE_SWING_800:
2423 demph_reg_value = 0x2B404040;
2424 uniqtranscale_reg_value = 0x55ADDA3A;
2425 break;
2426 default:
2427 return 0;
2428 }
2429 break;
2430 case DP_TRAIN_PRE_EMPHASIS_6:
2431 preemph_reg_value = 0x0000000;
2432 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2433 case DP_TRAIN_VOLTAGE_SWING_400:
2434 demph_reg_value = 0x2B305555;
2435 uniqtranscale_reg_value = 0x5570B83A;
2436 break;
2437 case DP_TRAIN_VOLTAGE_SWING_600:
2438 demph_reg_value = 0x2B2B4040;
2439 uniqtranscale_reg_value = 0x55ADDA3A;
2440 break;
2441 default:
2442 return 0;
2443 }
2444 break;
2445 case DP_TRAIN_PRE_EMPHASIS_9_5:
2446 preemph_reg_value = 0x0006000;
2447 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2448 case DP_TRAIN_VOLTAGE_SWING_400:
2449 demph_reg_value = 0x1B405555;
2450 uniqtranscale_reg_value = 0x55ADDA3A;
2451 break;
2452 default:
2453 return 0;
2454 }
2455 break;
2456 default:
2457 return 0;
2458 }
2459
0980a60f 2460 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2461 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2462 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2463 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2464 uniqtranscale_reg_value);
ab3c759a
CML		 2465 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2466 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2467 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2468 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2469 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2470
2471 return 0;
2472}
2473
e4a1d846
CML		 2474static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2475{
2476 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2477 struct drm_i915_private *dev_priv = dev->dev_private;
2478 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2479 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2480 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2481 uint8_t train_set = intel_dp->train_set[0];
2482 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2483 enum pipe pipe = intel_crtc->pipe;
2484 int i;
e4a1d846
CML		 2485
2486 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2487 case DP_TRAIN_PRE_EMPHASIS_0:
2488 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2489 case DP_TRAIN_VOLTAGE_SWING_400:
2490 deemph_reg_value = 128;
2491 margin_reg_value = 52;
2492 break;
2493 case DP_TRAIN_VOLTAGE_SWING_600:
2494 deemph_reg_value = 128;
2495 margin_reg_value = 77;
2496 break;
2497 case DP_TRAIN_VOLTAGE_SWING_800:
2498 deemph_reg_value = 128;
2499 margin_reg_value = 102;
2500 break;
2501 case DP_TRAIN_VOLTAGE_SWING_1200:
2502 deemph_reg_value = 128;
2503 margin_reg_value = 154;
2504 /* FIXME extra to set for 1200 */
2505 break;
2506 default:
2507 return 0;
2508 }
2509 break;
2510 case DP_TRAIN_PRE_EMPHASIS_3_5:
2511 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2512 case DP_TRAIN_VOLTAGE_SWING_400:
2513 deemph_reg_value = 85;
2514 margin_reg_value = 78;
2515 break;
2516 case DP_TRAIN_VOLTAGE_SWING_600:
2517 deemph_reg_value = 85;
2518 margin_reg_value = 116;
2519 break;
2520 case DP_TRAIN_VOLTAGE_SWING_800:
2521 deemph_reg_value = 85;
2522 margin_reg_value = 154;
2523 break;
2524 default:
2525 return 0;
2526 }
2527 break;
2528 case DP_TRAIN_PRE_EMPHASIS_6:
2529 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2530 case DP_TRAIN_VOLTAGE_SWING_400:
2531 deemph_reg_value = 64;
2532 margin_reg_value = 104;
2533 break;
2534 case DP_TRAIN_VOLTAGE_SWING_600:
2535 deemph_reg_value = 64;
2536 margin_reg_value = 154;
2537 break;
2538 default:
2539 return 0;
2540 }
2541 break;
2542 case DP_TRAIN_PRE_EMPHASIS_9_5:
2543 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2544 case DP_TRAIN_VOLTAGE_SWING_400:
2545 deemph_reg_value = 43;
2546 margin_reg_value = 154;
2547 break;
2548 default:
2549 return 0;
2550 }
2551 break;
2552 default:
2553 return 0;
2554 }
2555
2556 mutex_lock(&dev_priv->dpio_lock);
2557
2558 /* Clear calc init */
1966e59e
VS		 2559 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2560 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2561 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2562
2563 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2564 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2565 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2566
2567 /* Program swing deemph */
f72df8db
VS		 2568 for (i = 0; i < 4; i++) {
2569 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2570 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2571 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2572 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2573 }
e4a1d846
CML		 2574
2575 /* Program swing margin */
f72df8db
VS		 2576 for (i = 0; i < 4; i++) {
2577 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2578 val &= ~DPIO_SWING_MARGIN_MASK;
2579 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2580 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2581 }
e4a1d846
CML		 2582
2583 /* Disable unique transition scale */
f72df8db
VS		 2584 for (i = 0; i < 4; i++) {
2585 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2586 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2587 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2588 }
e4a1d846
CML		 2589
2590 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2591 == DP_TRAIN_PRE_EMPHASIS_0) &&
2592 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2593 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2594
2595 /*
2596 * The document said it needs to set bit 27 for ch0 and bit 26
2597 * for ch1. Might be a typo in the doc.
2598 * For now, for this unique transition scale selection, set bit
2599 * 27 for ch0 and ch1.
2600 */
f72df8db
VS		 2601 for (i = 0; i < 4; i++) {
2602 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2603 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2604 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2605 }
e4a1d846 2606
f72df8db
VS		 2607 for (i = 0; i < 4; i++) {
2608 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2609 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2610 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2611 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2612 }
e4a1d846
CML		 2613 }
2614
2615 /* Start swing calculation */
1966e59e
VS		 2616 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2617 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2618 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2619
2620 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2621 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2622 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2623
2624 /* LRC Bypass */
2625 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2626 val |= DPIO_LRC_BYPASS;
2627 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2628
2629 mutex_unlock(&dev_priv->dpio_lock);
2630
2631 return 0;
2632}
2633
a4fc5ed6 2634static void
0301b3ac
JN		 2635intel_get_adjust_train(struct intel_dp *intel_dp,
2636 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2637{
2638 uint8_t v = 0;
2639 uint8_t p = 0;
2640 int lane;
1a2eb460
KP		 2641 uint8_t voltage_max;
2642 uint8_t preemph_max;
a4fc5ed6 2643
33a34e4e 2644 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2645 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2646 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2647
2648 if (this_v > v)
2649 v = this_v;
2650 if (this_p > p)
2651 p = this_p;
2652 }
2653
1a2eb460 2654 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2655 if (v >= voltage_max)
2656 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2657
1a2eb460
KP		 2658 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2659 if (p >= preemph_max)
2660 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2661
2662 for (lane = 0; lane < 4; lane++)
33a34e4e 2663 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2664}
2665
2666static uint32_t
f0a3424e 2667intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2668{
3cf2efb1 2669 uint32_t signal_levels = 0;
a4fc5ed6 2670
3cf2efb1 2671 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2672 case DP_TRAIN_VOLTAGE_SWING_400:
2673 default:
2674 signal_levels |= DP_VOLTAGE_0_4;
2675 break;
2676 case DP_TRAIN_VOLTAGE_SWING_600:
2677 signal_levels |= DP_VOLTAGE_0_6;
2678 break;
2679 case DP_TRAIN_VOLTAGE_SWING_800:
2680 signal_levels |= DP_VOLTAGE_0_8;
2681 break;
2682 case DP_TRAIN_VOLTAGE_SWING_1200:
2683 signal_levels |= DP_VOLTAGE_1_2;
2684 break;
2685 }
3cf2efb1 2686 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2687 case DP_TRAIN_PRE_EMPHASIS_0:
2688 default:
2689 signal_levels |= DP_PRE_EMPHASIS_0;
2690 break;
2691 case DP_TRAIN_PRE_EMPHASIS_3_5:
2692 signal_levels |= DP_PRE_EMPHASIS_3_5;
2693 break;
2694 case DP_TRAIN_PRE_EMPHASIS_6:
2695 signal_levels |= DP_PRE_EMPHASIS_6;
2696 break;
2697 case DP_TRAIN_PRE_EMPHASIS_9_5:
2698 signal_levels |= DP_PRE_EMPHASIS_9_5;
2699 break;
2700 }
2701 return signal_levels;
2702}
2703
e3421a18
ZW		 2704/* Gen6's DP voltage swing and pre-emphasis control */
2705static uint32_t
2706intel_gen6_edp_signal_levels(uint8_t train_set)
2707{
3c5a62b5
YL		 2708 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2709 DP_TRAIN_PRE_EMPHASIS_MASK);
2710 switch (signal_levels) {
e3421a18 2711 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2712 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2713 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2714 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2715 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2716 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2717 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2718 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2719 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2720 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2721 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2722 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2723 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2724 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2725 default:
3c5a62b5
YL		 2726 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2727 "0x%x\n", signal_levels);
2728 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2729 }
2730}
2731
1a2eb460
KP		 2732/* Gen7's DP voltage swing and pre-emphasis control */
2733static uint32_t
2734intel_gen7_edp_signal_levels(uint8_t train_set)
2735{
2736 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2737 DP_TRAIN_PRE_EMPHASIS_MASK);
2738 switch (signal_levels) {
2739 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2740 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2741 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2742 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2743 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2744 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2745
2746 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2747 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2748 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2749 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2750
2751 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2752 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2753 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2754 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2755
2756 default:
2757 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2758 "0x%x\n", signal_levels);
2759 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2760 }
2761}
2762
d6c0d722
PZ		 2763/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2764static uint32_t
f0a3424e 2765intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2766{
d6c0d722
PZ		 2767 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2768 DP_TRAIN_PRE_EMPHASIS_MASK);
2769 switch (signal_levels) {
2770 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2771 return DDI_BUF_EMP_400MV_0DB_HSW;
2772 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2773 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2774 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2775 return DDI_BUF_EMP_400MV_6DB_HSW;
2776 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2777 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2778
d6c0d722
PZ		 2779 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2780 return DDI_BUF_EMP_600MV_0DB_HSW;
2781 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2782 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2783 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2784 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2785
d6c0d722
PZ		 2786 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2787 return DDI_BUF_EMP_800MV_0DB_HSW;
2788 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2789 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2790 default:
2791 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2792 "0x%x\n", signal_levels);
2793 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2794 }
a4fc5ed6
KP		 2795}
2796
f0a3424e
PZ		 2797/* Properly updates "DP" with the correct signal levels. */
2798static void
2799intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2800{
2801 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2802 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2803 struct drm_device *dev = intel_dig_port->base.base.dev;
2804 uint32_t signal_levels, mask;
2805 uint8_t train_set = intel_dp->train_set[0];
2806
9576c27f 2807 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 2808 signal_levels = intel_hsw_signal_levels(train_set);
2809 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 2810 } else if (IS_CHERRYVIEW(dev)) {
2811 signal_levels = intel_chv_signal_levels(intel_dp);
2812 mask = 0;
e2fa6fba
P		 2813 } else if (IS_VALLEYVIEW(dev)) {
2814 signal_levels = intel_vlv_signal_levels(intel_dp);
2815 mask = 0;
bc7d38a4 2816 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2817 signal_levels = intel_gen7_edp_signal_levels(train_set);
2818 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2819 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2820 signal_levels = intel_gen6_edp_signal_levels(train_set);
2821 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2822 } else {
2823 signal_levels = intel_gen4_signal_levels(train_set);
2824 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2825 }
2826
2827 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2828
2829 *DP = (*DP & ~mask) | signal_levels;
2830}
2831
a4fc5ed6 2832static bool
ea5b213a 2833intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2834 uint32_t *DP,
58e10eb9 2835 uint8_t dp_train_pat)
a4fc5ed6 2836{
174edf1f
PZ		 2837 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2838 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2839 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2840 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2841 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2842 int ret, len;
a4fc5ed6 2843
22b8bf17 2844 if (HAS_DDI(dev)) {
3ab9c637 2845 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2846
2847 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2848 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2849 else
2850 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2851
2852 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2853 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2854 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2855 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2856
2857 break;
2858 case DP_TRAINING_PATTERN_1:
2859 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2860 break;
2861 case DP_TRAINING_PATTERN_2:
2862 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2863 break;
2864 case DP_TRAINING_PATTERN_3:
2865 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2866 break;
2867 }
174edf1f 2868 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2869
bc7d38a4 2870 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2871 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2872
2873 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2874 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2875 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2876 break;
2877 case DP_TRAINING_PATTERN_1:
70aff66c 2878 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2879 break;
2880 case DP_TRAINING_PATTERN_2:
70aff66c 2881 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2882 break;
2883 case DP_TRAINING_PATTERN_3:
2884 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2885 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2886 break;
2887 }
2888
2889 } else {
70aff66c 2890 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2891
2892 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2893 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2894 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2895 break;
2896 case DP_TRAINING_PATTERN_1:
70aff66c 2897 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2898 break;
2899 case DP_TRAINING_PATTERN_2:
70aff66c 2900 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2901 break;
2902 case DP_TRAINING_PATTERN_3:
2903 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2904 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2905 break;
2906 }
2907 }
2908
70aff66c 2909 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2910 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2911
2cdfe6c8
JN		 2912 buf[0] = dp_train_pat;
2913 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2914 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2915 /* don't write DP_TRAINING_LANEx_SET on disable */
2916 len = 1;
2917 } else {
2918 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2919 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2920 len = intel_dp->lane_count + 1;
47ea7542 2921 }
a4fc5ed6 2922
9d1a1031
JN		 2923 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2924 buf, len);
2cdfe6c8
JN		 2925
2926 return ret == len;
a4fc5ed6
KP		 2927}
2928
70aff66c
JN		 2929static bool
2930intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2931 uint8_t dp_train_pat)
2932{
953d22e8 2933 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2934 intel_dp_set_signal_levels(intel_dp, DP);
2935 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2936}
2937
2938static bool
2939intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2940 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2941{
2942 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2943 struct drm_device *dev = intel_dig_port->base.base.dev;
2944 struct drm_i915_private *dev_priv = dev->dev_private;
2945 int ret;
2946
2947 intel_get_adjust_train(intel_dp, link_status);
2948 intel_dp_set_signal_levels(intel_dp, DP);
2949
2950 I915_WRITE(intel_dp->output_reg, *DP);
2951 POSTING_READ(intel_dp->output_reg);
2952
9d1a1031
JN		 2953 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2954 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 2955
2956 return ret == intel_dp->lane_count;
2957}
2958
3ab9c637
ID		 2959static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2960{
2961 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2962 struct drm_device *dev = intel_dig_port->base.base.dev;
2963 struct drm_i915_private *dev_priv = dev->dev_private;
2964 enum port port = intel_dig_port->port;
2965 uint32_t val;
2966
2967 if (!HAS_DDI(dev))
2968 return;
2969
2970 val = I915_READ(DP_TP_CTL(port));
2971 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2972 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2973 I915_WRITE(DP_TP_CTL(port), val);
2974
2975 /*
2976 * On PORT_A we can have only eDP in SST mode. There the only reason
2977 * we need to set idle transmission mode is to work around a HW issue
2978 * where we enable the pipe while not in idle link-training mode.
2979 * In this case there is requirement to wait for a minimum number of
2980 * idle patterns to be sent.
2981 */
2982 if (port == PORT_A)
2983 return;
2984
2985 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2986 1))
2987 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2988}
2989
33a34e4e 2990/* Enable corresponding port and start training pattern 1 */
c19b0669 2991void
33a34e4e 2992intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2993{
da63a9f2 2994 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2995 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2996 int i;
2997 uint8_t voltage;
cdb0e95b 2998 int voltage_tries, loop_tries;
ea5b213a 2999 uint32_t DP = intel_dp->DP;
6aba5b6c 3000 uint8_t link_config[2];
a4fc5ed6 3001
affa9354 3002 if (HAS_DDI(dev))
c19b0669
PZ		 3003 intel_ddi_prepare_link_retrain(encoder);
3004
3cf2efb1 3005 /* Write the link configuration data */
6aba5b6c
JN		 3006 link_config[0] = intel_dp->link_bw;
3007 link_config[1] = intel_dp->lane_count;
3008 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3009 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3010 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3011
3012 link_config[0] = 0;
3013 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3014 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3015
3016 DP |= DP_PORT_EN;
1a2eb460 3017
70aff66c
JN		 3018 /* clock recovery */
3019 if (!intel_dp_reset_link_train(intel_dp, &DP,
3020 DP_TRAINING_PATTERN_1 |
3021 DP_LINK_SCRAMBLING_DISABLE)) {
3022 DRM_ERROR("failed to enable link training\n");
3023 return;
3024 }
3025
a4fc5ed6 3026 voltage = 0xff;
cdb0e95b
KP		 3027 voltage_tries = 0;
3028 loop_tries = 0;
a4fc5ed6 3029 for (;;) {
70aff66c 3030 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3031
a7c9655f 3032 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3033 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3034 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3035 break;
93f62dad 3036 }
a4fc5ed6 3037
01916270 3038 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3039 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3040 break;
3041 }
3042
3043 /* Check to see if we've tried the max voltage */
3044 for (i = 0; i < intel_dp->lane_count; i++)
3045 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3046 break;
3b4f819d 3047 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3048 ++loop_tries;
3049 if (loop_tries == 5) {
3def84b3 3050 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3051 break;
3052 }
70aff66c
JN		 3053 intel_dp_reset_link_train(intel_dp, &DP,
3054 DP_TRAINING_PATTERN_1 |
3055 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3056 voltage_tries = 0;
3057 continue;
3058 }
a4fc5ed6 3059
3cf2efb1 3060 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3061 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3062 ++voltage_tries;
b06fbda3 3063 if (voltage_tries == 5) {
3def84b3 3064 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3065 break;
3066 }
3067 } else
3068 voltage_tries = 0;
3069 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3070
70aff66c
JN		 3071 /* Update training set as requested by target */
3072 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3073 DRM_ERROR("failed to update link training\n");
3074 break;
3075 }
a4fc5ed6
KP		 3076 }
3077
33a34e4e
JB		 3078 intel_dp->DP = DP;
3079}
3080
c19b0669 3081void
33a34e4e
JB		 3082intel_dp_complete_link_train(struct intel_dp *intel_dp)
3083{
33a34e4e 3084 bool channel_eq = false;
37f80975 3085 int tries, cr_tries;
33a34e4e 3086 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3087 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3088
3089 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3090 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3091 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3092
a4fc5ed6 3093 /* channel equalization */
70aff66c 3094 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3095 training_pattern |
70aff66c
JN		 3096 DP_LINK_SCRAMBLING_DISABLE)) {
3097 DRM_ERROR("failed to start channel equalization\n");
3098 return;
3099 }
3100
a4fc5ed6 3101 tries = 0;
37f80975 3102 cr_tries = 0;
a4fc5ed6
KP		 3103 channel_eq = false;
3104 for (;;) {
70aff66c 3105 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3106
37f80975
JB		 3107 if (cr_tries > 5) {
3108 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3109 break;
3110 }
3111
a7c9655f 3112 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3113 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3114 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3115 break;
70aff66c 3116 }
a4fc5ed6 3117
37f80975 3118 /* Make sure clock is still ok */
01916270 3119 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3120 intel_dp_start_link_train(intel_dp);
70aff66c 3121 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3122 training_pattern |
70aff66c 3123 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3124 cr_tries++;
3125 continue;
3126 }
3127
1ffdff13 3128 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3129 channel_eq = true;
3130 break;
3131 }
a4fc5ed6 3132
37f80975
JB		 3133 /* Try 5 times, then try clock recovery if that fails */
3134 if (tries > 5) {
3135 intel_dp_link_down(intel_dp);
3136 intel_dp_start_link_train(intel_dp);
70aff66c 3137 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3138 training_pattern |
70aff66c 3139 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3140 tries = 0;
3141 cr_tries++;
3142 continue;
3143 }
a4fc5ed6 3144
70aff66c
JN		 3145 /* Update training set as requested by target */
3146 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3147 DRM_ERROR("failed to update link training\n");
3148 break;
3149 }
3cf2efb1 3150 ++tries;
869184a6 3151 }
3cf2efb1 3152
3ab9c637
ID		 3153 intel_dp_set_idle_link_train(intel_dp);
3154
3155 intel_dp->DP = DP;
3156
d6c0d722 3157 if (channel_eq)
07f42258 3158 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3159
3ab9c637
ID		 3160}
3161
3162void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3163{
70aff66c 3164 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3165 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3166}
3167
3168static void
ea5b213a 3169intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3170{
da63a9f2 3171 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3172 enum port port = intel_dig_port->port;
da63a9f2 3173 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3174 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3175 struct intel_crtc *intel_crtc =
3176 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3177 uint32_t DP = intel_dp->DP;
a4fc5ed6 3178
bc76e320 3179 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3180 return;
3181
0c33d8d7 3182 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3183 return;
3184
28c97730 3185 DRM_DEBUG_KMS("\n");
32f9d658 3186
bc7d38a4 3187 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3188 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3189 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 3190 } else {
3191 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3192 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3193 }
fe255d00 3194 POSTING_READ(intel_dp->output_reg);
5eb08b69 3195
493a7081 3196 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3197 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3198 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3199
5bddd17f
EA		 3200 /* Hardware workaround: leaving our transcoder select
3201 * set to transcoder B while it's off will prevent the
3202 * corresponding HDMI output on transcoder A.
3203 *
3204 * Combine this with another hardware workaround:
3205 * transcoder select bit can only be cleared while the
3206 * port is enabled.
3207 */
3208 DP &= ~DP_PIPEB_SELECT;
3209 I915_WRITE(intel_dp->output_reg, DP);
3210
3211 /* Changes to enable or select take place the vblank
3212 * after being written.
3213 */
ff50afe9
DV		 3214 if (WARN_ON(crtc == NULL)) {
3215 /* We should never try to disable a port without a crtc
3216 * attached. For paranoia keep the code around for a
3217 * bit. */
31acbcc4
CW		 3218 POSTING_READ(intel_dp->output_reg);
3219 msleep(50);
3220 } else
ab527efc 3221 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3222 }
3223
832afda6 3224 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3225 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3226 POSTING_READ(intel_dp->output_reg);
f01eca2e 3227 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3228}
3229
26d61aad
KP		 3230static bool
3231intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3232{
a031d709
RV		 3233 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3234 struct drm_device *dev = dig_port->base.base.dev;
3235 struct drm_i915_private *dev_priv = dev->dev_private;
3236
577c7a50
DL		 3237 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3238
9d1a1031
JN		 3239 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3240 sizeof(intel_dp->dpcd)) < 0)
edb39244 3241 return false; /* aux transfer failed */
92fd8fd1 3242
577c7a50
DL		 3243 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3244 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3245 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3246
edb39244
AJ		 3247 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3248 return false; /* DPCD not present */
3249
2293bb5c
SK		 3250 /* Check if the panel supports PSR */
3251 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3252 if (is_edp(intel_dp)) {
9d1a1031
JN		 3253 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3254 intel_dp->psr_dpcd,
3255 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3256 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3257 dev_priv->psr.sink_support = true;
50003939 3258 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3259 }
50003939
JN		 3260 }
3261
06ea66b6
TP		 3262 /* Training Pattern 3 support */
3263 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3264 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3265 intel_dp->use_tps3 = true;
3266 DRM_DEBUG_KMS("Displayport TPS3 supported");
3267 } else
3268 intel_dp->use_tps3 = false;
3269
edb39244
AJ		 3270 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3271 DP_DWN_STRM_PORT_PRESENT))
3272 return true; /* native DP sink */
3273
3274 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3275 return true; /* no per-port downstream info */
3276
9d1a1031
JN		 3277 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3278 intel_dp->downstream_ports,
3279 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3280 return false; /* downstream port status fetch failed */
3281
3282 return true;
92fd8fd1
KP		 3283}
3284
0d198328
AJ		 3285static void
3286intel_dp_probe_oui(struct intel_dp *intel_dp)
3287{
3288 u8 buf[3];
3289
3290 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3291 return;
3292
24f3e092 3293 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3294
9d1a1031 3295 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3296 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3297 buf[0], buf[1], buf[2]);
3298
9d1a1031 3299 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3300 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3301 buf[0], buf[1], buf[2]);
351cfc34 3302
4be73780 3303 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3304}
3305
d2e216d0
RV		 3306int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3307{
3308 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3309 struct drm_device *dev = intel_dig_port->base.base.dev;
3310 struct intel_crtc *intel_crtc =
3311 to_intel_crtc(intel_dig_port->base.base.crtc);
3312 u8 buf[1];
3313
9d1a1031 3314 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3315 return -EAGAIN;
3316
3317 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3318 return -ENOTTY;
3319
9d1a1031
JN		 3320 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3321 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3322 return -EAGAIN;
3323
3324 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3325 intel_wait_for_vblank(dev, intel_crtc->pipe);
3326 intel_wait_for_vblank(dev, intel_crtc->pipe);
3327
9d1a1031 3328 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3329 return -EAGAIN;
3330
9d1a1031 3331 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3332 return 0;
3333}
3334
a60f0e38
JB		 3335static bool
3336intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3337{
9d1a1031
JN		 3338 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3339 DP_DEVICE_SERVICE_IRQ_VECTOR,
3340 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3341}
3342
3343static void
3344intel_dp_handle_test_request(struct intel_dp *intel_dp)
3345{
3346 /* NAK by default */
9d1a1031 3347 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3348}
3349
a4fc5ed6
KP		 3350/*
3351 * According to DP spec
3352 * 5.1.2:
3353 * 1. Read DPCD
3354 * 2. Configure link according to Receiver Capabilities
3355 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3356 * 4. Check link status on receipt of hot-plug interrupt
3357 */
3358
00c09d70 3359void
ea5b213a 3360intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3361{
da63a9f2 3362 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3363 u8 sink_irq_vector;
93f62dad 3364 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3365
6e9f798d 3366 /* FIXME: This access isn't protected by any locks. */
da63a9f2 3367 if (!intel_encoder->connectors_active)
d2b996ac 3368 return;
59cd09e1 3369
da63a9f2 3370 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3371 return;
3372
92fd8fd1 3373 /* Try to read receiver status if the link appears to be up */
93f62dad 3374 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3375 return;
3376 }
3377
92fd8fd1 3378 /* Now read the DPCD to see if it's actually running */
26d61aad 3379 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3380 return;
3381 }
3382
a60f0e38
JB		 3383 /* Try to read the source of the interrupt */
3384 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3385 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3386 /* Clear interrupt source */
9d1a1031
JN		 3387 drm_dp_dpcd_writeb(&intel_dp->aux,
3388 DP_DEVICE_SERVICE_IRQ_VECTOR,
3389 sink_irq_vector);
a60f0e38
JB		 3390
3391 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3392 intel_dp_handle_test_request(intel_dp);
3393 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3394 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3395 }
3396
1ffdff13 3397 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3398 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3399 intel_encoder->base.name);
33a34e4e
JB		 3400 intel_dp_start_link_train(intel_dp);
3401 intel_dp_complete_link_train(intel_dp);
3ab9c637 3402 intel_dp_stop_link_train(intel_dp);
33a34e4e 3403 }
a4fc5ed6 3404}
a4fc5ed6 3405
caf9ab24 3406/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3407static enum drm_connector_status
26d61aad 3408intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3409{
caf9ab24 3410 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3411 uint8_t type;
3412
3413 if (!intel_dp_get_dpcd(intel_dp))
3414 return connector_status_disconnected;
3415
3416 /* if there's no downstream port, we're done */
3417 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3418 return connector_status_connected;
caf9ab24
AJ		 3419
3420 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3421 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3422 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3423 uint8_t reg;
9d1a1031
JN		 3424
3425 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3426 &reg, 1) < 0)
caf9ab24 3427 return connector_status_unknown;
9d1a1031 3428
23235177
AJ		 3429 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3430 : connector_status_disconnected;
caf9ab24
AJ		 3431 }
3432
3433 /* If no HPD, poke DDC gently */
0b99836f 3434 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3435 return connector_status_connected;
caf9ab24
AJ		 3436
3437 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3438 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3439 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3440 if (type == DP_DS_PORT_TYPE_VGA ||
3441 type == DP_DS_PORT_TYPE_NON_EDID)
3442 return connector_status_unknown;
3443 } else {
3444 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3445 DP_DWN_STRM_PORT_TYPE_MASK;
3446 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3447 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3448 return connector_status_unknown;
3449 }
caf9ab24
AJ		 3450
3451 /* Anything else is out of spec, warn and ignore */
3452 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3453 return connector_status_disconnected;
71ba9000
AJ		 3454}
3455
5eb08b69 3456static enum drm_connector_status
a9756bb5 3457ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3458{
30add22d 3459 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3460 struct drm_i915_private *dev_priv = dev->dev_private;
3461 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3462 enum drm_connector_status status;
3463
fe16d949
CW		 3464 /* Can't disconnect eDP, but you can close the lid... */
3465 if (is_edp(intel_dp)) {
30add22d 3466 status = intel_panel_detect(dev);
fe16d949
CW		 3467 if (status == connector_status_unknown)
3468 status = connector_status_connected;
3469 return status;
3470 }
01cb9ea6 3471
1b469639
DL		 3472 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3473 return connector_status_disconnected;
3474
26d61aad 3475 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3476}
3477
a4fc5ed6 3478static enum drm_connector_status
a9756bb5 3479g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3480{
30add22d 3481 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3482 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3483 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3484 uint32_t bit;
5eb08b69 3485
35aad75f
JB		 3486 /* Can't disconnect eDP, but you can close the lid... */
3487 if (is_edp(intel_dp)) {
3488 enum drm_connector_status status;
3489
3490 status = intel_panel_detect(dev);
3491 if (status == connector_status_unknown)
3492 status = connector_status_connected;
3493 return status;
3494 }
3495
232a6ee9
TP		 3496 if (IS_VALLEYVIEW(dev)) {
3497 switch (intel_dig_port->port) {
3498 case PORT_B:
3499 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3500 break;
3501 case PORT_C:
3502 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3503 break;
3504 case PORT_D:
3505 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3506 break;
3507 default:
3508 return connector_status_unknown;
3509 }
3510 } else {
3511 switch (intel_dig_port->port) {
3512 case PORT_B:
3513 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3514 break;
3515 case PORT_C:
3516 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3517 break;
3518 case PORT_D:
3519 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3520 break;
3521 default:
3522 return connector_status_unknown;
3523 }
a4fc5ed6
KP		 3524 }
3525
10f76a38 3526 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3527 return connector_status_disconnected;
3528
26d61aad 3529 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3530}
3531
8c241fef
KP		 3532static struct edid *
3533intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3534{
9cd300e0 3535 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3536
9cd300e0
JN		 3537 /* use cached edid if we have one */
3538 if (intel_connector->edid) {
9cd300e0
JN		 3539 /* invalid edid */
3540 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3541 return NULL;
3542
55e9edeb 3543 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3544 }
8c241fef 3545
9cd300e0 3546 return drm_get_edid(connector, adapter);
8c241fef
KP		 3547}
3548
3549static int
3550intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3551{
9cd300e0 3552 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3553
9cd300e0
JN		 3554 /* use cached edid if we have one */
3555 if (intel_connector->edid) {
3556 /* invalid edid */
3557 if (IS_ERR(intel_connector->edid))
3558 return 0;
3559
3560 return intel_connector_update_modes(connector,
3561 intel_connector->edid);
d6f24d0f
JB		 3562 }
3563
9cd300e0 3564 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3565}
3566
a9756bb5
ZW		 3567static enum drm_connector_status
3568intel_dp_detect(struct drm_connector *connector, bool force)
3569{
3570 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3571 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3572 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3573 struct drm_device *dev = connector->dev;
c8c8fb33 3574 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3575 enum drm_connector_status status;
671dedd2 3576 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3577 struct edid *edid = NULL;
3578
c8c8fb33
PZ		 3579 intel_runtime_pm_get(dev_priv);
3580
671dedd2
ID		 3581 power_domain = intel_display_port_power_domain(intel_encoder);
3582 intel_display_power_get(dev_priv, power_domain);
3583
164c8598 3584 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 3585 connector->base.id, connector->name);
164c8598 3586
a9756bb5
ZW		 3587 intel_dp->has_audio = false;
3588
3589 if (HAS_PCH_SPLIT(dev))
3590 status = ironlake_dp_detect(intel_dp);
3591 else
3592 status = g4x_dp_detect(intel_dp);
1b9be9d0 3593
a9756bb5 3594 if (status != connector_status_connected)
c8c8fb33 3595 goto out;
a9756bb5 3596
0d198328
AJ		 3597 intel_dp_probe_oui(intel_dp);
3598
c3e5f67b
DV		 3599 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3600 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3601 } else {
0b99836f 3602 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3603 if (edid) {
3604 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3605 kfree(edid);
3606 }
a9756bb5
ZW		 3607 }
3608
d63885da
PZ		 3609 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3610 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3611 status = connector_status_connected;
3612
3613out:
671dedd2
ID		 3614 intel_display_power_put(dev_priv, power_domain);
3615
c8c8fb33 3616 intel_runtime_pm_put(dev_priv);
671dedd2 3617
c8c8fb33 3618 return status;
a4fc5ed6
KP		 3619}
3620
3621static int intel_dp_get_modes(struct drm_connector *connector)
3622{
df0e9248 3623 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3624 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3625 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3626 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3627 struct drm_device *dev = connector->dev;
671dedd2
ID		 3628 struct drm_i915_private *dev_priv = dev->dev_private;
3629 enum intel_display_power_domain power_domain;
32f9d658 3630 int ret;
a4fc5ed6
KP		 3631
3632 /* We should parse the EDID data and find out if it has an audio sink
3633 */
3634
671dedd2
ID		 3635 power_domain = intel_display_port_power_domain(intel_encoder);
3636 intel_display_power_get(dev_priv, power_domain);
3637
0b99836f 3638 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3639 intel_display_power_put(dev_priv, power_domain);
f8779fda 3640 if (ret)
32f9d658
ZW		 3641 return ret;
3642
f8779fda 3643 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3644 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3645 struct drm_display_mode *mode;
dd06f90e
JN		 3646 mode = drm_mode_duplicate(dev,
3647 intel_connector->panel.fixed_mode);
f8779fda 3648 if (mode) {
32f9d658
ZW		 3649 drm_mode_probed_add(connector, mode);
3650 return 1;
3651 }
3652 }
3653 return 0;
a4fc5ed6
KP		 3654}
3655
1aad7ac0
CW		 3656static bool
3657intel_dp_detect_audio(struct drm_connector *connector)
3658{
3659 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3660 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3661 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3662 struct drm_device *dev = connector->dev;
3663 struct drm_i915_private *dev_priv = dev->dev_private;
3664 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3665 struct edid *edid;
3666 bool has_audio = false;
3667
671dedd2
ID		 3668 power_domain = intel_display_port_power_domain(intel_encoder);
3669 intel_display_power_get(dev_priv, power_domain);
3670
0b99836f 3671 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3672 if (edid) {
3673 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3674 kfree(edid);
3675 }
3676
671dedd2
ID		 3677 intel_display_power_put(dev_priv, power_domain);
3678
1aad7ac0
CW		 3679 return has_audio;
3680}
3681
f684960e
CW		 3682static int
3683intel_dp_set_property(struct drm_connector *connector,
3684 struct drm_property *property,
3685 uint64_t val)
3686{
e953fd7b 3687 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3688 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3689 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3690 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3691 int ret;
3692
662595df 3693 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3694 if (ret)
3695 return ret;
3696
3f43c48d 3697 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3698 int i = val;
3699 bool has_audio;
3700
3701 if (i == intel_dp->force_audio)
f684960e
CW		 3702 return 0;
3703
1aad7ac0 3704 intel_dp->force_audio = i;
f684960e 3705
c3e5f67b 3706 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3707 has_audio = intel_dp_detect_audio(connector);
3708 else
c3e5f67b 3709 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3710
3711 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3712 return 0;
3713
1aad7ac0 3714 intel_dp->has_audio = has_audio;
f684960e
CW		 3715 goto done;
3716 }
3717
e953fd7b 3718 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3719 bool old_auto = intel_dp->color_range_auto;
3720 uint32_t old_range = intel_dp->color_range;
3721
55bc60db
VS		 3722 switch (val) {
3723 case INTEL_BROADCAST_RGB_AUTO:
3724 intel_dp->color_range_auto = true;
3725 break;
3726 case INTEL_BROADCAST_RGB_FULL:
3727 intel_dp->color_range_auto = false;
3728 intel_dp->color_range = 0;
3729 break;
3730 case INTEL_BROADCAST_RGB_LIMITED:
3731 intel_dp->color_range_auto = false;
3732 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3733 break;
3734 default:
3735 return -EINVAL;
3736 }
ae4edb80
DV		 3737
3738 if (old_auto == intel_dp->color_range_auto &&
3739 old_range == intel_dp->color_range)
3740 return 0;
3741
e953fd7b
CW		 3742 goto done;
3743 }
3744
53b41837
YN		 3745 if (is_edp(intel_dp) &&
3746 property == connector->dev->mode_config.scaling_mode_property) {
3747 if (val == DRM_MODE_SCALE_NONE) {
3748 DRM_DEBUG_KMS("no scaling not supported\n");
3749 return -EINVAL;
3750 }
3751
3752 if (intel_connector->panel.fitting_mode == val) {
3753 /* the eDP scaling property is not changed */
3754 return 0;
3755 }
3756 intel_connector->panel.fitting_mode = val;
3757
3758 goto done;
3759 }
3760
f684960e
CW		 3761 return -EINVAL;
3762
3763done:
c0c36b94
CW		 3764 if (intel_encoder->base.crtc)
3765 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3766
3767 return 0;
3768}
3769
a4fc5ed6 3770static void
73845adf 3771intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3772{
1d508706 3773 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3774
9cd300e0
JN		 3775 if (!IS_ERR_OR_NULL(intel_connector->edid))
3776 kfree(intel_connector->edid);
3777
acd8db10
PZ		 3778 /* Can't call is_edp() since the encoder may have been destroyed
3779 * already. */
3780 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3781 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3782
a4fc5ed6 3783 drm_connector_cleanup(connector);
55f78c43 3784 kfree(connector);
a4fc5ed6
KP		 3785}
3786
00c09d70 3787void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3788{
da63a9f2
PZ		 3789 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3790 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3791 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 3792
4f71d0cb 3793 drm_dp_aux_unregister(&intel_dp->aux);
24d05927 3794 drm_encoder_cleanup(encoder);
bd943159
KP		 3795 if (is_edp(intel_dp)) {
3796 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 3797 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 3798 edp_panel_vdd_off_sync(intel_dp);
51fd371b 3799 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159 3800 }
da63a9f2 3801 kfree(intel_dig_port);
24d05927
DV		 3802}
3803
a4fc5ed6 3804static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3805 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3806 .detect = intel_dp_detect,
3807 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3808 .set_property = intel_dp_set_property,
73845adf 3809 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3810};
3811
3812static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3813 .get_modes = intel_dp_get_modes,
3814 .mode_valid = intel_dp_mode_valid,
df0e9248 3815 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3816};
3817
a4fc5ed6 3818static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3819 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3820};
3821
995b6762 3822static void
21d40d37 3823intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3824{
fa90ecef 3825 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3826
885a5014 3827 intel_dp_check_link_status(intel_dp);
c8110e52 3828}
6207937d 3829
13cf5504
DA		 3830bool
3831intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
3832{
3833 struct intel_dp *intel_dp = &intel_dig_port->dp;
3834
3835 if (long_hpd)
3836 return true;
3837
3838 /*
3839 * we'll check the link status via the normal hot plug path later -
3840 * but for short hpds we should check it now
3841 */
3842 intel_dp_check_link_status(intel_dp);
3843 return false;
3844}
3845
e3421a18
ZW		 3846/* Return which DP Port should be selected for Transcoder DP control */
3847int
0206e353 3848intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3849{
3850 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3851 struct intel_encoder *intel_encoder;
3852 struct intel_dp *intel_dp;
e3421a18 3853
fa90ecef
PZ		 3854 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3855 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3856
fa90ecef
PZ		 3857 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3858 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3859 return intel_dp->output_reg;
e3421a18 3860 }
ea5b213a 3861
e3421a18
ZW		 3862 return -1;
3863}
3864
36e83a18 3865/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3866bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3867{
3868 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3869 union child_device_config *p_child;
36e83a18 3870 int i;
5d8a7752
VS		 3871 static const short port_mapping[] = {
3872 [PORT_B] = PORT_IDPB,
3873 [PORT_C] = PORT_IDPC,
3874 [PORT_D] = PORT_IDPD,
3875 };
36e83a18 3876
3b32a35b
VS		 3877 if (port == PORT_A)
3878 return true;
3879
41aa3448 3880 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3881 return false;
3882
41aa3448
RV		 3883 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3884 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3885
5d8a7752 3886 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3887 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3888 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3889 return true;
3890 }
3891 return false;
3892}
3893
f684960e
CW		 3894static void
3895intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3896{
53b41837
YN		 3897 struct intel_connector *intel_connector = to_intel_connector(connector);
3898
3f43c48d 3899 intel_attach_force_audio_property(connector);
e953fd7b 3900 intel_attach_broadcast_rgb_property(connector);
55bc60db 3901 intel_dp->color_range_auto = true;
53b41837
YN		 3902
3903 if (is_edp(intel_dp)) {
3904 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3905 drm_object_attach_property(
3906 &connector->base,
53b41837 3907 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3908 DRM_MODE_SCALE_ASPECT);
3909 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3910 }
f684960e
CW		 3911}
3912
dada1a9f
ID		 3913static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3914{
3915 intel_dp->last_power_cycle = jiffies;
3916 intel_dp->last_power_on = jiffies;
3917 intel_dp->last_backlight_off = jiffies;
3918}
3919
67a54566
DV		 3920static void
3921intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3922 struct intel_dp *intel_dp,
3923 struct edp_power_seq *out)
67a54566
DV		 3924{
3925 struct drm_i915_private *dev_priv = dev->dev_private;
3926 struct edp_power_seq cur, vbt, spec, final;
3927 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3928 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3929
3930 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3931 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3932 pp_on_reg = PCH_PP_ON_DELAYS;
3933 pp_off_reg = PCH_PP_OFF_DELAYS;
3934 pp_div_reg = PCH_PP_DIVISOR;
3935 } else {
bf13e81b
JN		 3936 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3937
3938 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3939 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3940 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3941 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3942 }
67a54566
DV		 3943
3944 /* Workaround: Need to write PP_CONTROL with the unlock key as
3945 * the very first thing. */
453c5420 3946 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3947 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3948
453c5420
JB		 3949 pp_on = I915_READ(pp_on_reg);
3950 pp_off = I915_READ(pp_off_reg);
3951 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3952
3953 /* Pull timing values out of registers */
3954 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3955 PANEL_POWER_UP_DELAY_SHIFT;
3956
3957 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3958 PANEL_LIGHT_ON_DELAY_SHIFT;
3959
3960 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3961 PANEL_LIGHT_OFF_DELAY_SHIFT;
3962
3963 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3964 PANEL_POWER_DOWN_DELAY_SHIFT;
3965
3966 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3967 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3968
3969 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3970 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3971
41aa3448 3972 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3973
3974 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3975 * our hw here, which are all in 100usec. */
3976 spec.t1_t3 = 210 * 10;
3977 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3978 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3979 spec.t10 = 500 * 10;
3980 /* This one is special and actually in units of 100ms, but zero
3981 * based in the hw (so we need to add 100 ms). But the sw vbt
3982 * table multiplies it with 1000 to make it in units of 100usec,
3983 * too. */
3984 spec.t11_t12 = (510 + 100) * 10;
3985
3986 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3987 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3988
3989 /* Use the max of the register settings and vbt. If both are
3990 * unset, fall back to the spec limits. */
3991#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3992 spec.field : \
3993 max(cur.field, vbt.field))
3994 assign_final(t1_t3);
3995 assign_final(t8);
3996 assign_final(t9);
3997 assign_final(t10);
3998 assign_final(t11_t12);
3999#undef assign_final
4000
4001#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4002 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4003 intel_dp->backlight_on_delay = get_delay(t8);
4004 intel_dp->backlight_off_delay = get_delay(t9);
4005 intel_dp->panel_power_down_delay = get_delay(t10);
4006 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4007#undef get_delay
4008
f30d26e4
JN		 4009 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4010 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4011 intel_dp->panel_power_cycle_delay);
4012
4013 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4014 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4015
4016 if (out)
4017 *out = final;
4018}
4019
4020static void
4021intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4022 struct intel_dp *intel_dp,
4023 struct edp_power_seq *seq)
4024{
4025 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4026 u32 pp_on, pp_off, pp_div, port_sel = 0;
4027 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4028 int pp_on_reg, pp_off_reg, pp_div_reg;
4029
4030 if (HAS_PCH_SPLIT(dev)) {
4031 pp_on_reg = PCH_PP_ON_DELAYS;
4032 pp_off_reg = PCH_PP_OFF_DELAYS;
4033 pp_div_reg = PCH_PP_DIVISOR;
4034 } else {
bf13e81b
JN		 4035 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4036
4037 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4038 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4039 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4040 }
4041
b2f19d1a
PZ		 4042 /*
4043 * And finally store the new values in the power sequencer. The
4044 * backlight delays are set to 1 because we do manual waits on them. For
4045 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4046 * we'll end up waiting for the backlight off delay twice: once when we
4047 * do the manual sleep, and once when we disable the panel and wait for
4048 * the PP_STATUS bit to become zero.
4049 */
f30d26e4 4050 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4051 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4052 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4053 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4054 /* Compute the divisor for the pp clock, simply match the Bspec
4055 * formula. */
453c5420 4056 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4057 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4058 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4059
4060 /* Haswell doesn't have any port selection bits for the panel
4061 * power sequencer any more. */
bc7d38a4 4062 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 4063 if (dp_to_dig_port(intel_dp)->port == PORT_B)
4064 port_sel = PANEL_PORT_SELECT_DPB_VLV;
4065 else
4066 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 4067 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4068 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 4069 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4070 else
a24c144c 4071 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4072 }
4073
453c5420
JB		 4074 pp_on |= port_sel;
4075
4076 I915_WRITE(pp_on_reg, pp_on);
4077 I915_WRITE(pp_off_reg, pp_off);
4078 I915_WRITE(pp_div_reg, pp_div);
67a54566 4079
67a54566 4080 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4081 I915_READ(pp_on_reg),
4082 I915_READ(pp_off_reg),
4083 I915_READ(pp_div_reg));
f684960e
CW		 4084}
4085
439d7ac0
PB		 4086void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4087{
4088 struct drm_i915_private *dev_priv = dev->dev_private;
4089 struct intel_encoder *encoder;
4090 struct intel_dp *intel_dp = NULL;
4091 struct intel_crtc_config *config = NULL;
4092 struct intel_crtc *intel_crtc = NULL;
4093 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4094 u32 reg, val;
4095 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4096
4097 if (refresh_rate <= 0) {
4098 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4099 return;
4100 }
4101
4102 if (intel_connector == NULL) {
4103 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4104 return;
4105 }
4106
1fcc9d1c
DV		 4107 /*
4108 * FIXME: This needs proper synchronization with psr state. But really
4109 * hard to tell without seeing the user of this function of this code.
4110 * Check locking and ordering once that lands.
4111 */
439d7ac0
PB		 4112 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4113 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4114 return;
4115 }
4116
4117 encoder = intel_attached_encoder(&intel_connector->base);
4118 intel_dp = enc_to_intel_dp(&encoder->base);
4119 intel_crtc = encoder->new_crtc;
4120
4121 if (!intel_crtc) {
4122 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4123 return;
4124 }
4125
4126 config = &intel_crtc->config;
4127
4128 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4129 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4130 return;
4131 }
4132
4133 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4134 index = DRRS_LOW_RR;
4135
4136 if (index == intel_dp->drrs_state.refresh_rate_type) {
4137 DRM_DEBUG_KMS(
4138 "DRRS requested for previously set RR...ignoring\n");
4139 return;
4140 }
4141
4142 if (!intel_crtc->active) {
4143 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4144 return;
4145 }
4146
4147 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4148 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4149 val = I915_READ(reg);
4150 if (index > DRRS_HIGH_RR) {
4151 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4152 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
4153 } else {
4154 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4155 }
4156 I915_WRITE(reg, val);
4157 }
4158
4159 /*
4160 * mutex taken to ensure that there is no race between differnt
4161 * drrs calls trying to update refresh rate. This scenario may occur
4162 * in future when idleness detection based DRRS in kernel and
4163 * possible calls from user space to set differnt RR are made.
4164 */
4165
4166 mutex_lock(&intel_dp->drrs_state.mutex);
4167
4168 intel_dp->drrs_state.refresh_rate_type = index;
4169
4170 mutex_unlock(&intel_dp->drrs_state.mutex);
4171
4172 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4173}
4174
4f9db5b5
PB		 4175static struct drm_display_mode *
4176intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4177 struct intel_connector *intel_connector,
4178 struct drm_display_mode *fixed_mode)
4179{
4180 struct drm_connector *connector = &intel_connector->base;
4181 struct intel_dp *intel_dp = &intel_dig_port->dp;
4182 struct drm_device *dev = intel_dig_port->base.base.dev;
4183 struct drm_i915_private *dev_priv = dev->dev_private;
4184 struct drm_display_mode *downclock_mode = NULL;
4185
4186 if (INTEL_INFO(dev)->gen <= 6) {
4187 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4188 return NULL;
4189 }
4190
4191 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4192 DRM_INFO("VBT doesn't support DRRS\n");
4193 return NULL;
4194 }
4195
4196 downclock_mode = intel_find_panel_downclock
4197 (dev, fixed_mode, connector);
4198
4199 if (!downclock_mode) {
4200 DRM_INFO("DRRS not supported\n");
4201 return NULL;
4202 }
4203
439d7ac0
PB		 4204 dev_priv->drrs.connector = intel_connector;
4205
4206 mutex_init(&intel_dp->drrs_state.mutex);
4207
4f9db5b5
PB		 4208 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4209
4210 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4211 DRM_INFO("seamless DRRS supported for eDP panel.\n");
4212 return downclock_mode;
4213}
4214
ed92f0b2 4215static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4216 struct intel_connector *intel_connector,
4217 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4218{
4219 struct drm_connector *connector = &intel_connector->base;
4220 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4221 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4222 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4223 struct drm_i915_private *dev_priv = dev->dev_private;
4224 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4225 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4226 bool has_dpcd;
4227 struct drm_display_mode *scan;
4228 struct edid *edid;
4229
4f9db5b5
PB		 4230 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4231
ed92f0b2
PZ		 4232 if (!is_edp(intel_dp))
4233 return true;
4234
63635217
PZ		 4235 /* The VDD bit needs a power domain reference, so if the bit is already
4236 * enabled when we boot, grab this reference. */
4237 if (edp_have_panel_vdd(intel_dp)) {
4238 enum intel_display_power_domain power_domain;
4239 power_domain = intel_display_port_power_domain(intel_encoder);
4240 intel_display_power_get(dev_priv, power_domain);
4241 }
4242
ed92f0b2 4243 /* Cache DPCD and EDID for edp. */
24f3e092 4244 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4245 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 4246 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4247
4248 if (has_dpcd) {
4249 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4250 dev_priv->no_aux_handshake =
4251 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4252 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4253 } else {
4254 /* if this fails, presume the device is a ghost */
4255 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4256 return false;
4257 }
4258
4259 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 4260 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 4261
060c8778 4262 mutex_lock(&dev->mode_config.mutex);
0b99836f 4263 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4264 if (edid) {
4265 if (drm_add_edid_modes(connector, edid)) {
4266 drm_mode_connector_update_edid_property(connector,
4267 edid);
4268 drm_edid_to_eld(connector, edid);
4269 } else {
4270 kfree(edid);
4271 edid = ERR_PTR(-EINVAL);
4272 }
4273 } else {
4274 edid = ERR_PTR(-ENOENT);
4275 }
4276 intel_connector->edid = edid;
4277
4278 /* prefer fixed mode from EDID if available */
4279 list_for_each_entry(scan, &connector->probed_modes, head) {
4280 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4281 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4282 downclock_mode = intel_dp_drrs_init(
4283 intel_dig_port,
4284 intel_connector, fixed_mode);
ed92f0b2
PZ		 4285 break;
4286 }
4287 }
4288
4289 /* fallback to VBT if available for eDP */
4290 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4291 fixed_mode = drm_mode_duplicate(dev,
4292 dev_priv->vbt.lfp_lvds_vbt_mode);
4293 if (fixed_mode)
4294 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4295 }
060c8778 4296 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4297
4f9db5b5 4298 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
ed92f0b2
PZ		 4299 intel_panel_setup_backlight(connector);
4300
4301 return true;
4302}
4303
16c25533 4304bool
f0fec3f2
PZ		 4305intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4306 struct intel_connector *intel_connector)
a4fc5ed6 4307{
f0fec3f2
PZ		 4308 struct drm_connector *connector = &intel_connector->base;
4309 struct intel_dp *intel_dp = &intel_dig_port->dp;
4310 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4311 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4312 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4313 enum port port = intel_dig_port->port;
0095e6dc 4314 struct edp_power_seq power_seq = { 0 };
0b99836f 4315 int type;
a4fc5ed6 4316
ec5b01dd
DL		 4317 /* intel_dp vfuncs */
4318 if (IS_VALLEYVIEW(dev))
4319 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4320 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4321 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4322 else if (HAS_PCH_SPLIT(dev))
4323 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4324 else
4325 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4326
153b1100
DL		 4327 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4328
0767935e
DV		 4329 /* Preserve the current hw state. */
4330 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4331 intel_dp->attached_connector = intel_connector;
3d3dc149 4332
3b32a35b 4333 if (intel_dp_is_edp(dev, port))
b329530c 4334 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4335 else
4336 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4337
f7d24902
ID		 4338 /*
4339 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4340 * for DP the encoder type can be set by the caller to
4341 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4342 */
4343 if (type == DRM_MODE_CONNECTOR_eDP)
4344 intel_encoder->type = INTEL_OUTPUT_EDP;
4345
e7281eab
ID		 4346 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4347 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4348 port_name(port));
4349
b329530c 4350 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4351 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4352
a4fc5ed6
KP		 4353 connector->interlace_allowed = true;
4354 connector->doublescan_allowed = 0;
4355
f0fec3f2 4356 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4357 edp_panel_vdd_work);
a4fc5ed6 4358
df0e9248 4359 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 4360 drm_sysfs_connector_add(connector);
4361
affa9354 4362 if (HAS_DDI(dev))
bcbc889b
PZ		 4363 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4364 else
4365 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 4366 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 4367
0b99836f 4368 /* Set up the hotplug pin. */
ab9d7c30
PZ		 4369 switch (port) {
4370 case PORT_A:
1d843f9d 4371 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 4372 break;
4373 case PORT_B:
1d843f9d 4374 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 4375 break;
4376 case PORT_C:
1d843f9d 4377 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 4378 break;
4379 case PORT_D:
1d843f9d 4380 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 4381 break;
4382 default:
ad1c0b19 4383 BUG();
5eb08b69
ZW		 4384 }
4385
dada1a9f
ID		 4386 if (is_edp(intel_dp)) {
4387 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 4388 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 4389 }
0095e6dc 4390
9d1a1031 4391 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 4392
0095e6dc 4393 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 4394 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 4395 if (is_edp(intel_dp)) {
4396 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4397 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4398 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4399 drm_modeset_unlock(&dev->mode_config.connection_mutex);
15b1d171 4400 }
b2f246a8
PZ		 4401 drm_sysfs_connector_remove(connector);
4402 drm_connector_cleanup(connector);
16c25533 4403 return false;
b2f246a8 4404 }
32f9d658 4405
f684960e
CW		 4406 intel_dp_add_properties(intel_dp, connector);
4407
a4fc5ed6
KP		 4408 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4409 * 0xd. Failure to do so will result in spurious interrupts being
4410 * generated on the port when a cable is not attached.
4411 */
4412 if (IS_G4X(dev) && !IS_GM45(dev)) {
4413 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4414 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4415 }
16c25533
PZ		 4416
4417 return true;
a4fc5ed6 4418}
f0fec3f2
PZ		 4419
4420void
4421intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4422{
13cf5504 4423 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 4424 struct intel_digital_port *intel_dig_port;
4425 struct intel_encoder *intel_encoder;
4426 struct drm_encoder *encoder;
4427 struct intel_connector *intel_connector;
4428
b14c5679 4429 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 4430 if (!intel_dig_port)
4431 return;
4432
b14c5679 4433 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 4434 if (!intel_connector) {
4435 kfree(intel_dig_port);
4436 return;
4437 }
4438
4439 intel_encoder = &intel_dig_port->base;
4440 encoder = &intel_encoder->base;
4441
4442 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4443 DRM_MODE_ENCODER_TMDS);
4444
5bfe2ac0 4445 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 4446 intel_encoder->disable = intel_disable_dp;
00c09d70 4447 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4448 intel_encoder->get_config = intel_dp_get_config;
e4a1d846 4449 if (IS_CHERRYVIEW(dev)) {
9197c88b 4450 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 4451 intel_encoder->pre_enable = chv_pre_enable_dp;
4452 intel_encoder->enable = vlv_enable_dp;
580d3811 4453 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 4454 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4455 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4456 intel_encoder->pre_enable = vlv_pre_enable_dp;
4457 intel_encoder->enable = vlv_enable_dp;
49277c31 4458 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4459 } else {
ecff4f3b
JN		 4460 intel_encoder->pre_enable = g4x_pre_enable_dp;
4461 intel_encoder->enable = g4x_enable_dp;
49277c31 4462 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4463 }
f0fec3f2 4464
174edf1f 4465 intel_dig_port->port = port;
f0fec3f2
PZ		 4466 intel_dig_port->dp.output_reg = output_reg;
4467
00c09d70 4468 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 4469 if (IS_CHERRYVIEW(dev)) {
4470 if (port == PORT_D)
4471 intel_encoder->crtc_mask = 1 << 2;
4472 else
4473 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4474 } else {
4475 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4476 }
bc079e8b 4477 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4478 intel_encoder->hot_plug = intel_dp_hot_plug;
4479
13cf5504
DA		 4480 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4481 dev_priv->hpd_irq_port[port] = intel_dig_port;
4482
15b1d171
PZ		 4483 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4484 drm_encoder_cleanup(encoder);
4485 kfree(intel_dig_port);
b2f246a8 4486 kfree(intel_connector);
15b1d171 4487 }
f0fec3f2 4488}
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