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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
01527b31 CT |
31 | #include <linux/notifier.h> |
32 | #include <linux/reboot.h> | |
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_crtc_helper.h> | |
37 | #include <drm/drm_edid.h> | |
a4fc5ed6 | 38 | #include "intel_drv.h" |
760285e7 | 39 | #include <drm/i915_drm.h> |
a4fc5ed6 | 40 | #include "i915_drv.h" |
a4fc5ed6 | 41 | |
a4fc5ed6 KP |
42 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
43 | ||
559be30c TP |
44 | /* Compliance test status bits */ |
45 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 | |
46 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
47 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
48 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
49 | ||
9dd4ffdf | 50 | struct dp_link_dpll { |
840b32b7 | 51 | int clock; |
9dd4ffdf CML |
52 | struct dpll dpll; |
53 | }; | |
54 | ||
55 | static const struct dp_link_dpll gen4_dpll[] = { | |
840b32b7 | 56 | { 162000, |
9dd4ffdf | 57 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
840b32b7 | 58 | { 270000, |
9dd4ffdf CML |
59 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
60 | }; | |
61 | ||
62 | static const struct dp_link_dpll pch_dpll[] = { | |
840b32b7 | 63 | { 162000, |
9dd4ffdf | 64 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
840b32b7 | 65 | { 270000, |
9dd4ffdf CML |
66 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
67 | }; | |
68 | ||
65ce4bf5 | 69 | static const struct dp_link_dpll vlv_dpll[] = { |
840b32b7 | 70 | { 162000, |
58f6e632 | 71 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
840b32b7 | 72 | { 270000, |
65ce4bf5 CML |
73 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
74 | }; | |
75 | ||
ef9348c8 CML |
76 | /* |
77 | * CHV supports eDP 1.4 that have more link rates. | |
78 | * Below only provides the fixed rate but exclude variable rate. | |
79 | */ | |
80 | static const struct dp_link_dpll chv_dpll[] = { | |
81 | /* | |
82 | * CHV requires to program fractional division for m2. | |
83 | * m2 is stored in fixed point format using formula below | |
84 | * (m2_int << 22) | m2_fraction | |
85 | */ | |
840b32b7 | 86 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
ef9348c8 | 87 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
840b32b7 | 88 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 | 89 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
840b32b7 | 90 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 CML |
91 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
92 | }; | |
637a9c63 | 93 | |
64987fc5 SJ |
94 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
95 | 324000, 432000, 540000 }; | |
637a9c63 | 96 | static const int skl_rates[] = { 162000, 216000, 270000, |
f4896f15 VS |
97 | 324000, 432000, 540000 }; |
98 | static const int default_rates[] = { 162000, 270000, 540000 }; | |
ef9348c8 | 99 | |
cfcb0fc9 JB |
100 | /** |
101 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
102 | * @intel_dp: DP struct | |
103 | * | |
104 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
105 | * will return true, and false otherwise. | |
106 | */ | |
107 | static bool is_edp(struct intel_dp *intel_dp) | |
108 | { | |
da63a9f2 PZ |
109 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
110 | ||
111 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
112 | } |
113 | ||
68b4d824 | 114 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
cfcb0fc9 | 115 | { |
68b4d824 ID |
116 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
117 | ||
118 | return intel_dig_port->base.base.dev; | |
cfcb0fc9 JB |
119 | } |
120 | ||
df0e9248 CW |
121 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
122 | { | |
fa90ecef | 123 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
124 | } |
125 | ||
ea5b213a | 126 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
1e0560e0 | 127 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 | 128 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
093e3f13 | 129 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
a8c3344e VS |
130 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
131 | enum pipe pipe); | |
f21a2198 | 132 | static void intel_dp_unset_edid(struct intel_dp *intel_dp); |
a4fc5ed6 | 133 | |
ed4e9c1d VS |
134 | static int |
135 | intel_dp_max_link_bw(struct intel_dp *intel_dp) | |
a4fc5ed6 | 136 | { |
7183dc29 | 137 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
138 | |
139 | switch (max_link_bw) { | |
140 | case DP_LINK_BW_1_62: | |
141 | case DP_LINK_BW_2_7: | |
1db10e28 | 142 | case DP_LINK_BW_5_4: |
d4eead50 | 143 | break; |
a4fc5ed6 | 144 | default: |
d4eead50 ID |
145 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
146 | max_link_bw); | |
a4fc5ed6 KP |
147 | max_link_bw = DP_LINK_BW_1_62; |
148 | break; | |
149 | } | |
150 | return max_link_bw; | |
151 | } | |
152 | ||
eeb6324d PZ |
153 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
154 | { | |
155 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
eeb6324d PZ |
156 | u8 source_max, sink_max; |
157 | ||
ccb1a831 | 158 | source_max = intel_dig_port->max_lanes; |
eeb6324d PZ |
159 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
160 | ||
161 | return min(source_max, sink_max); | |
162 | } | |
163 | ||
cd9dde44 AJ |
164 | /* |
165 | * The units on the numbers in the next two are... bizarre. Examples will | |
166 | * make it clearer; this one parallels an example in the eDP spec. | |
167 | * | |
168 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: | |
169 | * | |
170 | * 270000 * 1 * 8 / 10 == 216000 | |
171 | * | |
172 | * The actual data capacity of that configuration is 2.16Gbit/s, so the | |
173 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - | |
174 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be | |
175 | * 119000. At 18bpp that's 2142000 kilobits per second. | |
176 | * | |
177 | * Thus the strange-looking division by 10 in intel_dp_link_required, to | |
178 | * get the result in decakilobits instead of kilobits. | |
179 | */ | |
180 | ||
a4fc5ed6 | 181 | static int |
c898261c | 182 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 183 | { |
cd9dde44 | 184 | return (pixel_clock * bpp + 9) / 10; |
a4fc5ed6 KP |
185 | } |
186 | ||
fe27d53e DA |
187 | static int |
188 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
189 | { | |
190 | return (max_link_clock * max_lanes * 8) / 10; | |
191 | } | |
192 | ||
c19de8eb | 193 | static enum drm_mode_status |
a4fc5ed6 KP |
194 | intel_dp_mode_valid(struct drm_connector *connector, |
195 | struct drm_display_mode *mode) | |
196 | { | |
df0e9248 | 197 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e JN |
198 | struct intel_connector *intel_connector = to_intel_connector(connector); |
199 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
36008365 DV |
200 | int target_clock = mode->clock; |
201 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
799487f5 | 202 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
a4fc5ed6 | 203 | |
dd06f90e JN |
204 | if (is_edp(intel_dp) && fixed_mode) { |
205 | if (mode->hdisplay > fixed_mode->hdisplay) | |
7de56f43 ZY |
206 | return MODE_PANEL; |
207 | ||
dd06f90e | 208 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 209 | return MODE_PANEL; |
03afc4a2 DV |
210 | |
211 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
212 | } |
213 | ||
50fec21a | 214 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
eeb6324d | 215 | max_lanes = intel_dp_max_lane_count(intel_dp); |
36008365 DV |
216 | |
217 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
218 | mode_rate = intel_dp_link_required(target_clock, 18); | |
219 | ||
799487f5 | 220 | if (mode_rate > max_rate || target_clock > max_dotclk) |
c4867936 | 221 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
222 | |
223 | if (mode->clock < 10000) | |
224 | return MODE_CLOCK_LOW; | |
225 | ||
0af78a2b DV |
226 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
227 | return MODE_H_ILLEGAL; | |
228 | ||
a4fc5ed6 KP |
229 | return MODE_OK; |
230 | } | |
231 | ||
a4f1289e | 232 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
a4fc5ed6 KP |
233 | { |
234 | int i; | |
235 | uint32_t v = 0; | |
236 | ||
237 | if (src_bytes > 4) | |
238 | src_bytes = 4; | |
239 | for (i = 0; i < src_bytes; i++) | |
240 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
241 | return v; | |
242 | } | |
243 | ||
c2af70e2 | 244 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
a4fc5ed6 KP |
245 | { |
246 | int i; | |
247 | if (dst_bytes > 4) | |
248 | dst_bytes = 4; | |
249 | for (i = 0; i < dst_bytes; i++) | |
250 | dst[i] = src >> ((3-i) * 8); | |
251 | } | |
252 | ||
bf13e81b JN |
253 | static void |
254 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
36b5f425 | 255 | struct intel_dp *intel_dp); |
bf13e81b JN |
256 | static void |
257 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
36b5f425 | 258 | struct intel_dp *intel_dp); |
bf13e81b | 259 | |
773538e8 VS |
260 | static void pps_lock(struct intel_dp *intel_dp) |
261 | { | |
262 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
263 | struct intel_encoder *encoder = &intel_dig_port->base; | |
264 | struct drm_device *dev = encoder->base.dev; | |
265 | struct drm_i915_private *dev_priv = dev->dev_private; | |
266 | enum intel_display_power_domain power_domain; | |
267 | ||
268 | /* | |
269 | * See vlv_power_sequencer_reset() why we need | |
270 | * a power domain reference here. | |
271 | */ | |
25f78f58 | 272 | power_domain = intel_display_port_aux_power_domain(encoder); |
773538e8 VS |
273 | intel_display_power_get(dev_priv, power_domain); |
274 | ||
275 | mutex_lock(&dev_priv->pps_mutex); | |
276 | } | |
277 | ||
278 | static void pps_unlock(struct intel_dp *intel_dp) | |
279 | { | |
280 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
281 | struct intel_encoder *encoder = &intel_dig_port->base; | |
282 | struct drm_device *dev = encoder->base.dev; | |
283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
284 | enum intel_display_power_domain power_domain; | |
285 | ||
286 | mutex_unlock(&dev_priv->pps_mutex); | |
287 | ||
25f78f58 | 288 | power_domain = intel_display_port_aux_power_domain(encoder); |
773538e8 VS |
289 | intel_display_power_put(dev_priv, power_domain); |
290 | } | |
291 | ||
961a0db0 VS |
292 | static void |
293 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) | |
294 | { | |
295 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
296 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
298 | enum pipe pipe = intel_dp->pps_pipe; | |
0047eedc VS |
299 | bool pll_enabled, release_cl_override = false; |
300 | enum dpio_phy phy = DPIO_PHY(pipe); | |
301 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); | |
961a0db0 VS |
302 | uint32_t DP; |
303 | ||
304 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, | |
305 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", | |
306 | pipe_name(pipe), port_name(intel_dig_port->port))) | |
307 | return; | |
308 | ||
309 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", | |
310 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
311 | ||
312 | /* Preserve the BIOS-computed detected bit. This is | |
313 | * supposed to be read-only. | |
314 | */ | |
315 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
316 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
317 | DP |= DP_PORT_WIDTH(1); | |
318 | DP |= DP_LINK_TRAIN_PAT_1; | |
319 | ||
320 | if (IS_CHERRYVIEW(dev)) | |
321 | DP |= DP_PIPE_SELECT_CHV(pipe); | |
322 | else if (pipe == PIPE_B) | |
323 | DP |= DP_PIPEB_SELECT; | |
324 | ||
d288f65f VS |
325 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
326 | ||
327 | /* | |
328 | * The DPLL for the pipe must be enabled for this to work. | |
329 | * So enable temporarily it if it's not already enabled. | |
330 | */ | |
0047eedc VS |
331 | if (!pll_enabled) { |
332 | release_cl_override = IS_CHERRYVIEW(dev) && | |
333 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); | |
334 | ||
3f36b937 TU |
335 | if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? |
336 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { | |
337 | DRM_ERROR("Failed to force on pll for pipe %c!\n", | |
338 | pipe_name(pipe)); | |
339 | return; | |
340 | } | |
0047eedc | 341 | } |
d288f65f | 342 | |
961a0db0 VS |
343 | /* |
344 | * Similar magic as in intel_dp_enable_port(). | |
345 | * We _must_ do this port enable + disable trick | |
346 | * to make this power seqeuencer lock onto the port. | |
347 | * Otherwise even VDD force bit won't work. | |
348 | */ | |
349 | I915_WRITE(intel_dp->output_reg, DP); | |
350 | POSTING_READ(intel_dp->output_reg); | |
351 | ||
352 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); | |
353 | POSTING_READ(intel_dp->output_reg); | |
354 | ||
355 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); | |
356 | POSTING_READ(intel_dp->output_reg); | |
d288f65f | 357 | |
0047eedc | 358 | if (!pll_enabled) { |
d288f65f | 359 | vlv_force_pll_off(dev, pipe); |
0047eedc VS |
360 | |
361 | if (release_cl_override) | |
362 | chv_phy_powergate_ch(dev_priv, phy, ch, false); | |
363 | } | |
961a0db0 VS |
364 | } |
365 | ||
bf13e81b JN |
366 | static enum pipe |
367 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
368 | { | |
369 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bf13e81b JN |
370 | struct drm_device *dev = intel_dig_port->base.base.dev; |
371 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4a5d2f8 VS |
372 | struct intel_encoder *encoder; |
373 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); | |
a8c3344e | 374 | enum pipe pipe; |
bf13e81b | 375 | |
e39b999a | 376 | lockdep_assert_held(&dev_priv->pps_mutex); |
bf13e81b | 377 | |
a8c3344e VS |
378 | /* We should never land here with regular DP ports */ |
379 | WARN_ON(!is_edp(intel_dp)); | |
380 | ||
a4a5d2f8 VS |
381 | if (intel_dp->pps_pipe != INVALID_PIPE) |
382 | return intel_dp->pps_pipe; | |
383 | ||
384 | /* | |
385 | * We don't have power sequencer currently. | |
386 | * Pick one that's not used by other ports. | |
387 | */ | |
19c8054c | 388 | for_each_intel_encoder(dev, encoder) { |
a4a5d2f8 VS |
389 | struct intel_dp *tmp; |
390 | ||
391 | if (encoder->type != INTEL_OUTPUT_EDP) | |
392 | continue; | |
393 | ||
394 | tmp = enc_to_intel_dp(&encoder->base); | |
395 | ||
396 | if (tmp->pps_pipe != INVALID_PIPE) | |
397 | pipes &= ~(1 << tmp->pps_pipe); | |
398 | } | |
399 | ||
400 | /* | |
401 | * Didn't find one. This should not happen since there | |
402 | * are two power sequencers and up to two eDP ports. | |
403 | */ | |
404 | if (WARN_ON(pipes == 0)) | |
a8c3344e VS |
405 | pipe = PIPE_A; |
406 | else | |
407 | pipe = ffs(pipes) - 1; | |
a4a5d2f8 | 408 | |
a8c3344e VS |
409 | vlv_steal_power_sequencer(dev, pipe); |
410 | intel_dp->pps_pipe = pipe; | |
a4a5d2f8 VS |
411 | |
412 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", | |
413 | pipe_name(intel_dp->pps_pipe), | |
414 | port_name(intel_dig_port->port)); | |
415 | ||
416 | /* init power sequencer on this pipe and port */ | |
36b5f425 VS |
417 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
418 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
a4a5d2f8 | 419 | |
961a0db0 VS |
420 | /* |
421 | * Even vdd force doesn't work until we've made | |
422 | * the power sequencer lock in on the port. | |
423 | */ | |
424 | vlv_power_sequencer_kick(intel_dp); | |
a4a5d2f8 VS |
425 | |
426 | return intel_dp->pps_pipe; | |
427 | } | |
428 | ||
6491ab27 VS |
429 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
430 | enum pipe pipe); | |
431 | ||
432 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, | |
433 | enum pipe pipe) | |
434 | { | |
435 | return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; | |
436 | } | |
437 | ||
438 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, | |
439 | enum pipe pipe) | |
440 | { | |
441 | return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; | |
442 | } | |
443 | ||
444 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, | |
445 | enum pipe pipe) | |
446 | { | |
447 | return true; | |
448 | } | |
bf13e81b | 449 | |
a4a5d2f8 | 450 | static enum pipe |
6491ab27 VS |
451 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
452 | enum port port, | |
453 | vlv_pipe_check pipe_check) | |
a4a5d2f8 VS |
454 | { |
455 | enum pipe pipe; | |
bf13e81b | 456 | |
bf13e81b JN |
457 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
458 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & | |
459 | PANEL_PORT_SELECT_MASK; | |
a4a5d2f8 VS |
460 | |
461 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) | |
462 | continue; | |
463 | ||
6491ab27 VS |
464 | if (!pipe_check(dev_priv, pipe)) |
465 | continue; | |
466 | ||
a4a5d2f8 | 467 | return pipe; |
bf13e81b JN |
468 | } |
469 | ||
a4a5d2f8 VS |
470 | return INVALID_PIPE; |
471 | } | |
472 | ||
473 | static void | |
474 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) | |
475 | { | |
476 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
477 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
478 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4a5d2f8 VS |
479 | enum port port = intel_dig_port->port; |
480 | ||
481 | lockdep_assert_held(&dev_priv->pps_mutex); | |
482 | ||
483 | /* try to find a pipe with this port selected */ | |
6491ab27 VS |
484 | /* first pick one where the panel is on */ |
485 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
486 | vlv_pipe_has_pp_on); | |
487 | /* didn't find one? pick one where vdd is on */ | |
488 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
489 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
490 | vlv_pipe_has_vdd_on); | |
491 | /* didn't find one? pick one with just the correct port */ | |
492 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
493 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
494 | vlv_pipe_any); | |
a4a5d2f8 VS |
495 | |
496 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ | |
497 | if (intel_dp->pps_pipe == INVALID_PIPE) { | |
498 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", | |
499 | port_name(port)); | |
500 | return; | |
bf13e81b JN |
501 | } |
502 | ||
a4a5d2f8 VS |
503 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
504 | port_name(port), pipe_name(intel_dp->pps_pipe)); | |
505 | ||
36b5f425 VS |
506 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
507 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
bf13e81b JN |
508 | } |
509 | ||
773538e8 VS |
510 | void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv) |
511 | { | |
512 | struct drm_device *dev = dev_priv->dev; | |
513 | struct intel_encoder *encoder; | |
514 | ||
666a4537 | 515 | if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))) |
773538e8 VS |
516 | return; |
517 | ||
518 | /* | |
519 | * We can't grab pps_mutex here due to deadlock with power_domain | |
520 | * mutex when power_domain functions are called while holding pps_mutex. | |
521 | * That also means that in order to use pps_pipe the code needs to | |
522 | * hold both a power domain reference and pps_mutex, and the power domain | |
523 | * reference get/put must be done while _not_ holding pps_mutex. | |
524 | * pps_{lock,unlock}() do these steps in the correct order, so one | |
525 | * should use them always. | |
526 | */ | |
527 | ||
19c8054c | 528 | for_each_intel_encoder(dev, encoder) { |
773538e8 VS |
529 | struct intel_dp *intel_dp; |
530 | ||
531 | if (encoder->type != INTEL_OUTPUT_EDP) | |
532 | continue; | |
533 | ||
534 | intel_dp = enc_to_intel_dp(&encoder->base); | |
535 | intel_dp->pps_pipe = INVALID_PIPE; | |
536 | } | |
bf13e81b JN |
537 | } |
538 | ||
f0f59a00 VS |
539 | static i915_reg_t |
540 | _pp_ctrl_reg(struct intel_dp *intel_dp) | |
bf13e81b JN |
541 | { |
542 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
543 | ||
b0a08bec VK |
544 | if (IS_BROXTON(dev)) |
545 | return BXT_PP_CONTROL(0); | |
546 | else if (HAS_PCH_SPLIT(dev)) | |
bf13e81b JN |
547 | return PCH_PP_CONTROL; |
548 | else | |
549 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); | |
550 | } | |
551 | ||
f0f59a00 VS |
552 | static i915_reg_t |
553 | _pp_stat_reg(struct intel_dp *intel_dp) | |
bf13e81b JN |
554 | { |
555 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
556 | ||
b0a08bec VK |
557 | if (IS_BROXTON(dev)) |
558 | return BXT_PP_STATUS(0); | |
559 | else if (HAS_PCH_SPLIT(dev)) | |
bf13e81b JN |
560 | return PCH_PP_STATUS; |
561 | else | |
562 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); | |
563 | } | |
564 | ||
01527b31 CT |
565 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
566 | This function only applicable when panel PM state is not to be tracked */ | |
567 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, | |
568 | void *unused) | |
569 | { | |
570 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), | |
571 | edp_notifier); | |
572 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
573 | struct drm_i915_private *dev_priv = dev->dev_private; | |
01527b31 CT |
574 | |
575 | if (!is_edp(intel_dp) || code != SYS_RESTART) | |
576 | return 0; | |
577 | ||
773538e8 | 578 | pps_lock(intel_dp); |
e39b999a | 579 | |
666a4537 | 580 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e39b999a | 581 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
f0f59a00 | 582 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
649636ef | 583 | u32 pp_div; |
e39b999a | 584 | |
01527b31 CT |
585 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
586 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
587 | pp_div = I915_READ(pp_div_reg); | |
588 | pp_div &= PP_REFERENCE_DIVIDER_MASK; | |
589 | ||
590 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ | |
591 | I915_WRITE(pp_div_reg, pp_div | 0x1F); | |
592 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); | |
593 | msleep(intel_dp->panel_power_cycle_delay); | |
594 | } | |
595 | ||
773538e8 | 596 | pps_unlock(intel_dp); |
e39b999a | 597 | |
01527b31 CT |
598 | return 0; |
599 | } | |
600 | ||
4be73780 | 601 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
ebf33b18 | 602 | { |
30add22d | 603 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
ebf33b18 KP |
604 | struct drm_i915_private *dev_priv = dev->dev_private; |
605 | ||
e39b999a VS |
606 | lockdep_assert_held(&dev_priv->pps_mutex); |
607 | ||
666a4537 | 608 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
9a42356b VS |
609 | intel_dp->pps_pipe == INVALID_PIPE) |
610 | return false; | |
611 | ||
bf13e81b | 612 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
613 | } |
614 | ||
4be73780 | 615 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
ebf33b18 | 616 | { |
30add22d | 617 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
ebf33b18 KP |
618 | struct drm_i915_private *dev_priv = dev->dev_private; |
619 | ||
e39b999a VS |
620 | lockdep_assert_held(&dev_priv->pps_mutex); |
621 | ||
666a4537 | 622 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
9a42356b VS |
623 | intel_dp->pps_pipe == INVALID_PIPE) |
624 | return false; | |
625 | ||
773538e8 | 626 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
ebf33b18 KP |
627 | } |
628 | ||
9b984dae KP |
629 | static void |
630 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
631 | { | |
30add22d | 632 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9b984dae | 633 | struct drm_i915_private *dev_priv = dev->dev_private; |
ebf33b18 | 634 | |
9b984dae KP |
635 | if (!is_edp(intel_dp)) |
636 | return; | |
453c5420 | 637 | |
4be73780 | 638 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
639 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
640 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
bf13e81b JN |
641 | I915_READ(_pp_stat_reg(intel_dp)), |
642 | I915_READ(_pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
643 | } |
644 | } | |
645 | ||
9ee32fea DV |
646 | static uint32_t |
647 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) | |
648 | { | |
649 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
650 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
651 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 652 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
9ee32fea DV |
653 | uint32_t status; |
654 | bool done; | |
655 | ||
ef04f00d | 656 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
9ee32fea | 657 | if (has_aux_irq) |
b18ac466 | 658 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
3598706b | 659 | msecs_to_jiffies_timeout(10)); |
9ee32fea DV |
660 | else |
661 | done = wait_for_atomic(C, 10) == 0; | |
662 | if (!done) | |
663 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", | |
664 | has_aux_irq); | |
665 | #undef C | |
666 | ||
667 | return status; | |
668 | } | |
669 | ||
6ffb1be7 | 670 | static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
a4fc5ed6 | 671 | { |
174edf1f | 672 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
e7dc33f3 | 673 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
9ee32fea | 674 | |
a457f54b VS |
675 | if (index) |
676 | return 0; | |
677 | ||
ec5b01dd DL |
678 | /* |
679 | * The clock divider is based off the hrawclk, and would like to run at | |
a457f54b | 680 | * 2MHz. So, take the hrawclk value and divide by 2000 and use that |
a4fc5ed6 | 681 | */ |
a457f54b | 682 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
ec5b01dd DL |
683 | } |
684 | ||
685 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
686 | { | |
687 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
a457f54b | 688 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
ec5b01dd DL |
689 | |
690 | if (index) | |
691 | return 0; | |
692 | ||
a457f54b VS |
693 | /* |
694 | * The clock divider is based off the cdclk or PCH rawclk, and would | |
695 | * like to run at 2MHz. So, take the cdclk or PCH rawclk value and | |
696 | * divide by 2000 and use that | |
697 | */ | |
e7dc33f3 | 698 | if (intel_dig_port->port == PORT_A) |
fce18c4c | 699 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
e7dc33f3 VS |
700 | else |
701 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); | |
ec5b01dd DL |
702 | } |
703 | ||
704 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
705 | { | |
706 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
a457f54b | 707 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
ec5b01dd | 708 | |
a457f54b | 709 | if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) { |
2c55c336 | 710 | /* Workaround for non-ULT HSW */ |
bc86625a CW |
711 | switch (index) { |
712 | case 0: return 63; | |
713 | case 1: return 72; | |
714 | default: return 0; | |
715 | } | |
2c55c336 | 716 | } |
a457f54b VS |
717 | |
718 | return ilk_get_aux_clock_divider(intel_dp, index); | |
b84a1cf8 RV |
719 | } |
720 | ||
b6b5e383 DL |
721 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
722 | { | |
723 | /* | |
724 | * SKL doesn't need us to program the AUX clock divider (Hardware will | |
725 | * derive the clock from CDCLK automatically). We still implement the | |
726 | * get_aux_clock_divider vfunc to plug-in into the existing code. | |
727 | */ | |
728 | return index ? 0 : 1; | |
729 | } | |
730 | ||
6ffb1be7 VS |
731 | static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, |
732 | bool has_aux_irq, | |
733 | int send_bytes, | |
734 | uint32_t aux_clock_divider) | |
5ed12a19 DL |
735 | { |
736 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
737 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
738 | uint32_t precharge, timeout; | |
739 | ||
740 | if (IS_GEN6(dev)) | |
741 | precharge = 3; | |
742 | else | |
743 | precharge = 5; | |
744 | ||
f3c6a3a7 | 745 | if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A) |
5ed12a19 DL |
746 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
747 | else | |
748 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; | |
749 | ||
750 | return DP_AUX_CH_CTL_SEND_BUSY | | |
788d4433 | 751 | DP_AUX_CH_CTL_DONE | |
5ed12a19 | 752 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
788d4433 | 753 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
5ed12a19 | 754 | timeout | |
788d4433 | 755 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
5ed12a19 DL |
756 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
757 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
788d4433 | 758 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
5ed12a19 DL |
759 | } |
760 | ||
b9ca5fad DL |
761 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
762 | bool has_aux_irq, | |
763 | int send_bytes, | |
764 | uint32_t unused) | |
765 | { | |
766 | return DP_AUX_CH_CTL_SEND_BUSY | | |
767 | DP_AUX_CH_CTL_DONE | | |
768 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | | |
769 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
770 | DP_AUX_CH_CTL_TIME_OUT_1600us | | |
771 | DP_AUX_CH_CTL_RECEIVE_ERROR | | |
772 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
773 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); | |
774 | } | |
775 | ||
b84a1cf8 RV |
776 | static int |
777 | intel_dp_aux_ch(struct intel_dp *intel_dp, | |
bd9f74a5 | 778 | const uint8_t *send, int send_bytes, |
b84a1cf8 RV |
779 | uint8_t *recv, int recv_size) |
780 | { | |
781 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
782 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
783 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 784 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
bc86625a | 785 | uint32_t aux_clock_divider; |
b84a1cf8 RV |
786 | int i, ret, recv_bytes; |
787 | uint32_t status; | |
5ed12a19 | 788 | int try, clock = 0; |
4e6b788c | 789 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
884f19e9 JN |
790 | bool vdd; |
791 | ||
773538e8 | 792 | pps_lock(intel_dp); |
e39b999a | 793 | |
72c3500a VS |
794 | /* |
795 | * We will be called with VDD already enabled for dpcd/edid/oui reads. | |
796 | * In such cases we want to leave VDD enabled and it's up to upper layers | |
797 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off | |
798 | * ourselves. | |
799 | */ | |
1e0560e0 | 800 | vdd = edp_panel_vdd_on(intel_dp); |
b84a1cf8 RV |
801 | |
802 | /* dp aux is extremely sensitive to irq latency, hence request the | |
803 | * lowest possible wakeup latency and so prevent the cpu from going into | |
804 | * deep sleep states. | |
805 | */ | |
806 | pm_qos_update_request(&dev_priv->pm_qos, 0); | |
807 | ||
808 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 809 | |
11bee43e JB |
810 | /* Try to wait for any previous AUX channel activity */ |
811 | for (try = 0; try < 3; try++) { | |
ef04f00d | 812 | status = I915_READ_NOTRACE(ch_ctl); |
11bee43e JB |
813 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
814 | break; | |
815 | msleep(1); | |
816 | } | |
817 | ||
818 | if (try == 3) { | |
02196c77 MK |
819 | static u32 last_status = -1; |
820 | const u32 status = I915_READ(ch_ctl); | |
821 | ||
822 | if (status != last_status) { | |
823 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
824 | status); | |
825 | last_status = status; | |
826 | } | |
827 | ||
9ee32fea DV |
828 | ret = -EBUSY; |
829 | goto out; | |
4f7f7b7e CW |
830 | } |
831 | ||
46a5ae9f PZ |
832 | /* Only 5 data registers! */ |
833 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { | |
834 | ret = -E2BIG; | |
835 | goto out; | |
836 | } | |
837 | ||
ec5b01dd | 838 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
153b1100 DL |
839 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
840 | has_aux_irq, | |
841 | send_bytes, | |
842 | aux_clock_divider); | |
5ed12a19 | 843 | |
bc86625a CW |
844 | /* Must try at least 3 times according to DP spec */ |
845 | for (try = 0; try < 5; try++) { | |
846 | /* Load the send data into the aux channel data registers */ | |
847 | for (i = 0; i < send_bytes; i += 4) | |
330e20ec | 848 | I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], |
a4f1289e RV |
849 | intel_dp_pack_aux(send + i, |
850 | send_bytes - i)); | |
bc86625a CW |
851 | |
852 | /* Send the command and wait for it to complete */ | |
5ed12a19 | 853 | I915_WRITE(ch_ctl, send_ctl); |
bc86625a CW |
854 | |
855 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); | |
856 | ||
857 | /* Clear done status and any errors */ | |
858 | I915_WRITE(ch_ctl, | |
859 | status | | |
860 | DP_AUX_CH_CTL_DONE | | |
861 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
862 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
863 | ||
74ebf294 | 864 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
bc86625a | 865 | continue; |
74ebf294 TP |
866 | |
867 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 | |
868 | * 400us delay required for errors and timeouts | |
869 | * Timeout errors from the HW already meet this | |
870 | * requirement so skip to next iteration | |
871 | */ | |
872 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { | |
873 | usleep_range(400, 500); | |
bc86625a | 874 | continue; |
74ebf294 | 875 | } |
bc86625a | 876 | if (status & DP_AUX_CH_CTL_DONE) |
e058c945 | 877 | goto done; |
bc86625a | 878 | } |
a4fc5ed6 KP |
879 | } |
880 | ||
a4fc5ed6 | 881 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 882 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
9ee32fea DV |
883 | ret = -EBUSY; |
884 | goto out; | |
a4fc5ed6 KP |
885 | } |
886 | ||
e058c945 | 887 | done: |
a4fc5ed6 KP |
888 | /* Check for timeout or receive error. |
889 | * Timeouts occur when the sink is not connected | |
890 | */ | |
a5b3da54 | 891 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 892 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
9ee32fea DV |
893 | ret = -EIO; |
894 | goto out; | |
a5b3da54 | 895 | } |
1ae8c0a5 KP |
896 | |
897 | /* Timeouts occur when the device isn't connected, so they're | |
898 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 899 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 900 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
9ee32fea DV |
901 | ret = -ETIMEDOUT; |
902 | goto out; | |
a4fc5ed6 KP |
903 | } |
904 | ||
905 | /* Unload any bytes sent back from the other side */ | |
906 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
907 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
14e01889 RV |
908 | |
909 | /* | |
910 | * By BSpec: "Message sizes of 0 or >20 are not allowed." | |
911 | * We have no idea of what happened so we return -EBUSY so | |
912 | * drm layer takes care for the necessary retries. | |
913 | */ | |
914 | if (recv_bytes == 0 || recv_bytes > 20) { | |
915 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", | |
916 | recv_bytes); | |
917 | /* | |
918 | * FIXME: This patch was created on top of a series that | |
919 | * organize the retries at drm level. There EBUSY should | |
920 | * also take care for 1ms wait before retrying. | |
921 | * That aux retries re-org is still needed and after that is | |
922 | * merged we remove this sleep from here. | |
923 | */ | |
924 | usleep_range(1000, 1500); | |
925 | ret = -EBUSY; | |
926 | goto out; | |
927 | } | |
928 | ||
a4fc5ed6 KP |
929 | if (recv_bytes > recv_size) |
930 | recv_bytes = recv_size; | |
0206e353 | 931 | |
4f7f7b7e | 932 | for (i = 0; i < recv_bytes; i += 4) |
330e20ec | 933 | intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), |
a4f1289e | 934 | recv + i, recv_bytes - i); |
a4fc5ed6 | 935 | |
9ee32fea DV |
936 | ret = recv_bytes; |
937 | out: | |
938 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); | |
939 | ||
884f19e9 JN |
940 | if (vdd) |
941 | edp_panel_vdd_off(intel_dp, false); | |
942 | ||
773538e8 | 943 | pps_unlock(intel_dp); |
e39b999a | 944 | |
9ee32fea | 945 | return ret; |
a4fc5ed6 KP |
946 | } |
947 | ||
a6c8aff0 JN |
948 | #define BARE_ADDRESS_SIZE 3 |
949 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) | |
9d1a1031 JN |
950 | static ssize_t |
951 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
a4fc5ed6 | 952 | { |
9d1a1031 JN |
953 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
954 | uint8_t txbuf[20], rxbuf[20]; | |
955 | size_t txsize, rxsize; | |
a4fc5ed6 | 956 | int ret; |
a4fc5ed6 | 957 | |
d2d9cbbd VS |
958 | txbuf[0] = (msg->request << 4) | |
959 | ((msg->address >> 16) & 0xf); | |
960 | txbuf[1] = (msg->address >> 8) & 0xff; | |
9d1a1031 JN |
961 | txbuf[2] = msg->address & 0xff; |
962 | txbuf[3] = msg->size - 1; | |
46a5ae9f | 963 | |
9d1a1031 JN |
964 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
965 | case DP_AUX_NATIVE_WRITE: | |
966 | case DP_AUX_I2C_WRITE: | |
c1e74122 | 967 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
a6c8aff0 | 968 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
a1ddefd8 | 969 | rxsize = 2; /* 0 or 1 data bytes */ |
f51a44b9 | 970 | |
9d1a1031 JN |
971 | if (WARN_ON(txsize > 20)) |
972 | return -E2BIG; | |
a4fc5ed6 | 973 | |
d81a67cc ID |
974 | if (msg->buffer) |
975 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); | |
976 | else | |
977 | WARN_ON(msg->size); | |
a4fc5ed6 | 978 | |
9d1a1031 JN |
979 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
980 | if (ret > 0) { | |
981 | msg->reply = rxbuf[0] >> 4; | |
a4fc5ed6 | 982 | |
a1ddefd8 JN |
983 | if (ret > 1) { |
984 | /* Number of bytes written in a short write. */ | |
985 | ret = clamp_t(int, rxbuf[1], 0, msg->size); | |
986 | } else { | |
987 | /* Return payload size. */ | |
988 | ret = msg->size; | |
989 | } | |
9d1a1031 JN |
990 | } |
991 | break; | |
46a5ae9f | 992 | |
9d1a1031 JN |
993 | case DP_AUX_NATIVE_READ: |
994 | case DP_AUX_I2C_READ: | |
a6c8aff0 | 995 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
9d1a1031 | 996 | rxsize = msg->size + 1; |
a4fc5ed6 | 997 | |
9d1a1031 JN |
998 | if (WARN_ON(rxsize > 20)) |
999 | return -E2BIG; | |
a4fc5ed6 | 1000 | |
9d1a1031 JN |
1001 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1002 | if (ret > 0) { | |
1003 | msg->reply = rxbuf[0] >> 4; | |
1004 | /* | |
1005 | * Assume happy day, and copy the data. The caller is | |
1006 | * expected to check msg->reply before touching it. | |
1007 | * | |
1008 | * Return payload size. | |
1009 | */ | |
1010 | ret--; | |
1011 | memcpy(msg->buffer, rxbuf + 1, ret); | |
a4fc5ed6 | 1012 | } |
9d1a1031 JN |
1013 | break; |
1014 | ||
1015 | default: | |
1016 | ret = -EINVAL; | |
1017 | break; | |
a4fc5ed6 | 1018 | } |
f51a44b9 | 1019 | |
9d1a1031 | 1020 | return ret; |
a4fc5ed6 KP |
1021 | } |
1022 | ||
f0f59a00 VS |
1023 | static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1024 | enum port port) | |
da00bdcf VS |
1025 | { |
1026 | switch (port) { | |
1027 | case PORT_B: | |
1028 | case PORT_C: | |
1029 | case PORT_D: | |
1030 | return DP_AUX_CH_CTL(port); | |
1031 | default: | |
1032 | MISSING_CASE(port); | |
1033 | return DP_AUX_CH_CTL(PORT_B); | |
1034 | } | |
1035 | } | |
1036 | ||
f0f59a00 VS |
1037 | static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, |
1038 | enum port port, int index) | |
330e20ec VS |
1039 | { |
1040 | switch (port) { | |
1041 | case PORT_B: | |
1042 | case PORT_C: | |
1043 | case PORT_D: | |
1044 | return DP_AUX_CH_DATA(port, index); | |
1045 | default: | |
1046 | MISSING_CASE(port); | |
1047 | return DP_AUX_CH_DATA(PORT_B, index); | |
1048 | } | |
1049 | } | |
1050 | ||
f0f59a00 VS |
1051 | static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1052 | enum port port) | |
da00bdcf VS |
1053 | { |
1054 | switch (port) { | |
1055 | case PORT_A: | |
1056 | return DP_AUX_CH_CTL(port); | |
1057 | case PORT_B: | |
1058 | case PORT_C: | |
1059 | case PORT_D: | |
1060 | return PCH_DP_AUX_CH_CTL(port); | |
1061 | default: | |
1062 | MISSING_CASE(port); | |
1063 | return DP_AUX_CH_CTL(PORT_A); | |
1064 | } | |
1065 | } | |
1066 | ||
f0f59a00 VS |
1067 | static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, |
1068 | enum port port, int index) | |
330e20ec VS |
1069 | { |
1070 | switch (port) { | |
1071 | case PORT_A: | |
1072 | return DP_AUX_CH_DATA(port, index); | |
1073 | case PORT_B: | |
1074 | case PORT_C: | |
1075 | case PORT_D: | |
1076 | return PCH_DP_AUX_CH_DATA(port, index); | |
1077 | default: | |
1078 | MISSING_CASE(port); | |
1079 | return DP_AUX_CH_DATA(PORT_A, index); | |
1080 | } | |
1081 | } | |
1082 | ||
da00bdcf VS |
1083 | /* |
1084 | * On SKL we don't have Aux for port E so we rely | |
1085 | * on VBT to set a proper alternate aux channel. | |
1086 | */ | |
1087 | static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv) | |
1088 | { | |
1089 | const struct ddi_vbt_port_info *info = | |
1090 | &dev_priv->vbt.ddi_port_info[PORT_E]; | |
1091 | ||
1092 | switch (info->alternate_aux_channel) { | |
1093 | case DP_AUX_A: | |
1094 | return PORT_A; | |
1095 | case DP_AUX_B: | |
1096 | return PORT_B; | |
1097 | case DP_AUX_C: | |
1098 | return PORT_C; | |
1099 | case DP_AUX_D: | |
1100 | return PORT_D; | |
1101 | default: | |
1102 | MISSING_CASE(info->alternate_aux_channel); | |
1103 | return PORT_A; | |
1104 | } | |
1105 | } | |
1106 | ||
f0f59a00 VS |
1107 | static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1108 | enum port port) | |
da00bdcf VS |
1109 | { |
1110 | if (port == PORT_E) | |
1111 | port = skl_porte_aux_port(dev_priv); | |
1112 | ||
1113 | switch (port) { | |
1114 | case PORT_A: | |
1115 | case PORT_B: | |
1116 | case PORT_C: | |
1117 | case PORT_D: | |
1118 | return DP_AUX_CH_CTL(port); | |
1119 | default: | |
1120 | MISSING_CASE(port); | |
1121 | return DP_AUX_CH_CTL(PORT_A); | |
1122 | } | |
1123 | } | |
1124 | ||
f0f59a00 VS |
1125 | static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, |
1126 | enum port port, int index) | |
330e20ec VS |
1127 | { |
1128 | if (port == PORT_E) | |
1129 | port = skl_porte_aux_port(dev_priv); | |
1130 | ||
1131 | switch (port) { | |
1132 | case PORT_A: | |
1133 | case PORT_B: | |
1134 | case PORT_C: | |
1135 | case PORT_D: | |
1136 | return DP_AUX_CH_DATA(port, index); | |
1137 | default: | |
1138 | MISSING_CASE(port); | |
1139 | return DP_AUX_CH_DATA(PORT_A, index); | |
1140 | } | |
1141 | } | |
1142 | ||
f0f59a00 VS |
1143 | static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1144 | enum port port) | |
330e20ec VS |
1145 | { |
1146 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
1147 | return skl_aux_ctl_reg(dev_priv, port); | |
1148 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1149 | return ilk_aux_ctl_reg(dev_priv, port); | |
1150 | else | |
1151 | return g4x_aux_ctl_reg(dev_priv, port); | |
1152 | } | |
1153 | ||
f0f59a00 VS |
1154 | static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, |
1155 | enum port port, int index) | |
330e20ec VS |
1156 | { |
1157 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
1158 | return skl_aux_data_reg(dev_priv, port, index); | |
1159 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1160 | return ilk_aux_data_reg(dev_priv, port, index); | |
1161 | else | |
1162 | return g4x_aux_data_reg(dev_priv, port, index); | |
1163 | } | |
1164 | ||
1165 | static void intel_aux_reg_init(struct intel_dp *intel_dp) | |
1166 | { | |
1167 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); | |
1168 | enum port port = dp_to_dig_port(intel_dp)->port; | |
1169 | int i; | |
1170 | ||
1171 | intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); | |
1172 | for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) | |
1173 | intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); | |
1174 | } | |
1175 | ||
9d1a1031 | 1176 | static void |
a121f4e5 VS |
1177 | intel_dp_aux_fini(struct intel_dp *intel_dp) |
1178 | { | |
1179 | drm_dp_aux_unregister(&intel_dp->aux); | |
1180 | kfree(intel_dp->aux.name); | |
1181 | } | |
1182 | ||
1183 | static int | |
9d1a1031 JN |
1184 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) |
1185 | { | |
33ad6626 JN |
1186 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1187 | enum port port = intel_dig_port->port; | |
ab2c0672 DA |
1188 | int ret; |
1189 | ||
330e20ec | 1190 | intel_aux_reg_init(intel_dp); |
8316f337 | 1191 | |
a121f4e5 VS |
1192 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); |
1193 | if (!intel_dp->aux.name) | |
1194 | return -ENOMEM; | |
1195 | ||
4d32c0d8 | 1196 | intel_dp->aux.dev = connector->base.kdev; |
9d1a1031 | 1197 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
8316f337 | 1198 | |
a121f4e5 VS |
1199 | DRM_DEBUG_KMS("registering %s bus for %s\n", |
1200 | intel_dp->aux.name, | |
0b99836f | 1201 | connector->base.kdev->kobj.name); |
8316f337 | 1202 | |
4f71d0cb | 1203 | ret = drm_dp_aux_register(&intel_dp->aux); |
0b99836f | 1204 | if (ret < 0) { |
4f71d0cb | 1205 | DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n", |
a121f4e5 VS |
1206 | intel_dp->aux.name, ret); |
1207 | kfree(intel_dp->aux.name); | |
1208 | return ret; | |
ab2c0672 | 1209 | } |
8a5e6aeb | 1210 | |
a121f4e5 | 1211 | return 0; |
a4fc5ed6 KP |
1212 | } |
1213 | ||
80f65de3 ID |
1214 | static void |
1215 | intel_dp_connector_unregister(struct intel_connector *intel_connector) | |
1216 | { | |
1217 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); | |
1218 | ||
4d32c0d8 | 1219 | intel_dp_aux_fini(intel_dp); |
80f65de3 ID |
1220 | intel_connector_unregister(intel_connector); |
1221 | } | |
1222 | ||
fc0f8e25 | 1223 | static int |
12f6a2e2 | 1224 | intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) |
fc0f8e25 | 1225 | { |
94ca719e VS |
1226 | if (intel_dp->num_sink_rates) { |
1227 | *sink_rates = intel_dp->sink_rates; | |
1228 | return intel_dp->num_sink_rates; | |
fc0f8e25 | 1229 | } |
12f6a2e2 VS |
1230 | |
1231 | *sink_rates = default_rates; | |
1232 | ||
1233 | return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; | |
fc0f8e25 SJ |
1234 | } |
1235 | ||
e588fa18 | 1236 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
ed63baaf | 1237 | { |
e588fa18 ACO |
1238 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1239 | struct drm_device *dev = dig_port->base.base.dev; | |
1240 | ||
ed63baaf | 1241 | /* WaDisableHBR2:skl */ |
e87a005d | 1242 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0)) |
ed63baaf TS |
1243 | return false; |
1244 | ||
1245 | if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || | |
1246 | (INTEL_INFO(dev)->gen >= 9)) | |
1247 | return true; | |
1248 | else | |
1249 | return false; | |
1250 | } | |
1251 | ||
a8f3ef61 | 1252 | static int |
e588fa18 | 1253 | intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates) |
a8f3ef61 | 1254 | { |
e588fa18 ACO |
1255 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1256 | struct drm_device *dev = dig_port->base.base.dev; | |
af7080f5 TS |
1257 | int size; |
1258 | ||
64987fc5 SJ |
1259 | if (IS_BROXTON(dev)) { |
1260 | *source_rates = bxt_rates; | |
af7080f5 | 1261 | size = ARRAY_SIZE(bxt_rates); |
ef11bdb3 | 1262 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
637a9c63 | 1263 | *source_rates = skl_rates; |
af7080f5 TS |
1264 | size = ARRAY_SIZE(skl_rates); |
1265 | } else { | |
1266 | *source_rates = default_rates; | |
1267 | size = ARRAY_SIZE(default_rates); | |
a8f3ef61 | 1268 | } |
636280ba | 1269 | |
ed63baaf | 1270 | /* This depends on the fact that 5.4 is last value in the array */ |
e588fa18 | 1271 | if (!intel_dp_source_supports_hbr2(intel_dp)) |
af7080f5 | 1272 | size--; |
636280ba | 1273 | |
af7080f5 | 1274 | return size; |
a8f3ef61 SJ |
1275 | } |
1276 | ||
c6bb3538 DV |
1277 | static void |
1278 | intel_dp_set_clock(struct intel_encoder *encoder, | |
840b32b7 | 1279 | struct intel_crtc_state *pipe_config) |
c6bb3538 DV |
1280 | { |
1281 | struct drm_device *dev = encoder->base.dev; | |
9dd4ffdf CML |
1282 | const struct dp_link_dpll *divisor = NULL; |
1283 | int i, count = 0; | |
c6bb3538 DV |
1284 | |
1285 | if (IS_G4X(dev)) { | |
9dd4ffdf CML |
1286 | divisor = gen4_dpll; |
1287 | count = ARRAY_SIZE(gen4_dpll); | |
c6bb3538 | 1288 | } else if (HAS_PCH_SPLIT(dev)) { |
9dd4ffdf CML |
1289 | divisor = pch_dpll; |
1290 | count = ARRAY_SIZE(pch_dpll); | |
ef9348c8 CML |
1291 | } else if (IS_CHERRYVIEW(dev)) { |
1292 | divisor = chv_dpll; | |
1293 | count = ARRAY_SIZE(chv_dpll); | |
c6bb3538 | 1294 | } else if (IS_VALLEYVIEW(dev)) { |
65ce4bf5 CML |
1295 | divisor = vlv_dpll; |
1296 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 1297 | } |
9dd4ffdf CML |
1298 | |
1299 | if (divisor && count) { | |
1300 | for (i = 0; i < count; i++) { | |
840b32b7 | 1301 | if (pipe_config->port_clock == divisor[i].clock) { |
9dd4ffdf CML |
1302 | pipe_config->dpll = divisor[i].dpll; |
1303 | pipe_config->clock_set = true; | |
1304 | break; | |
1305 | } | |
1306 | } | |
c6bb3538 DV |
1307 | } |
1308 | } | |
1309 | ||
2ecae76a VS |
1310 | static int intersect_rates(const int *source_rates, int source_len, |
1311 | const int *sink_rates, int sink_len, | |
94ca719e | 1312 | int *common_rates) |
a8f3ef61 SJ |
1313 | { |
1314 | int i = 0, j = 0, k = 0; | |
1315 | ||
a8f3ef61 SJ |
1316 | while (i < source_len && j < sink_len) { |
1317 | if (source_rates[i] == sink_rates[j]) { | |
e6bda3e4 VS |
1318 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) |
1319 | return k; | |
94ca719e | 1320 | common_rates[k] = source_rates[i]; |
a8f3ef61 SJ |
1321 | ++k; |
1322 | ++i; | |
1323 | ++j; | |
1324 | } else if (source_rates[i] < sink_rates[j]) { | |
1325 | ++i; | |
1326 | } else { | |
1327 | ++j; | |
1328 | } | |
1329 | } | |
1330 | return k; | |
1331 | } | |
1332 | ||
94ca719e VS |
1333 | static int intel_dp_common_rates(struct intel_dp *intel_dp, |
1334 | int *common_rates) | |
2ecae76a | 1335 | { |
2ecae76a VS |
1336 | const int *source_rates, *sink_rates; |
1337 | int source_len, sink_len; | |
1338 | ||
1339 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); | |
e588fa18 | 1340 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
2ecae76a VS |
1341 | |
1342 | return intersect_rates(source_rates, source_len, | |
1343 | sink_rates, sink_len, | |
94ca719e | 1344 | common_rates); |
2ecae76a VS |
1345 | } |
1346 | ||
0336400e VS |
1347 | static void snprintf_int_array(char *str, size_t len, |
1348 | const int *array, int nelem) | |
1349 | { | |
1350 | int i; | |
1351 | ||
1352 | str[0] = '\0'; | |
1353 | ||
1354 | for (i = 0; i < nelem; i++) { | |
b2f505be | 1355 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
0336400e VS |
1356 | if (r >= len) |
1357 | return; | |
1358 | str += r; | |
1359 | len -= r; | |
1360 | } | |
1361 | } | |
1362 | ||
1363 | static void intel_dp_print_rates(struct intel_dp *intel_dp) | |
1364 | { | |
0336400e | 1365 | const int *source_rates, *sink_rates; |
94ca719e VS |
1366 | int source_len, sink_len, common_len; |
1367 | int common_rates[DP_MAX_SUPPORTED_RATES]; | |
0336400e VS |
1368 | char str[128]; /* FIXME: too big for stack? */ |
1369 | ||
1370 | if ((drm_debug & DRM_UT_KMS) == 0) | |
1371 | return; | |
1372 | ||
e588fa18 | 1373 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
0336400e VS |
1374 | snprintf_int_array(str, sizeof(str), source_rates, source_len); |
1375 | DRM_DEBUG_KMS("source rates: %s\n", str); | |
1376 | ||
1377 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); | |
1378 | snprintf_int_array(str, sizeof(str), sink_rates, sink_len); | |
1379 | DRM_DEBUG_KMS("sink rates: %s\n", str); | |
1380 | ||
94ca719e VS |
1381 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
1382 | snprintf_int_array(str, sizeof(str), common_rates, common_len); | |
1383 | DRM_DEBUG_KMS("common rates: %s\n", str); | |
0336400e VS |
1384 | } |
1385 | ||
f4896f15 | 1386 | static int rate_to_index(int find, const int *rates) |
a8f3ef61 SJ |
1387 | { |
1388 | int i = 0; | |
1389 | ||
1390 | for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) | |
1391 | if (find == rates[i]) | |
1392 | break; | |
1393 | ||
1394 | return i; | |
1395 | } | |
1396 | ||
50fec21a VS |
1397 | int |
1398 | intel_dp_max_link_rate(struct intel_dp *intel_dp) | |
1399 | { | |
1400 | int rates[DP_MAX_SUPPORTED_RATES] = {}; | |
1401 | int len; | |
1402 | ||
94ca719e | 1403 | len = intel_dp_common_rates(intel_dp, rates); |
50fec21a VS |
1404 | if (WARN_ON(len <= 0)) |
1405 | return 162000; | |
1406 | ||
1407 | return rates[rate_to_index(0, rates) - 1]; | |
1408 | } | |
1409 | ||
ed4e9c1d VS |
1410 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1411 | { | |
94ca719e | 1412 | return rate_to_index(rate, intel_dp->sink_rates); |
ed4e9c1d VS |
1413 | } |
1414 | ||
94223d04 ACO |
1415 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
1416 | uint8_t *link_bw, uint8_t *rate_select) | |
04a60f9f VS |
1417 | { |
1418 | if (intel_dp->num_sink_rates) { | |
1419 | *link_bw = 0; | |
1420 | *rate_select = | |
1421 | intel_dp_rate_select(intel_dp, port_clock); | |
1422 | } else { | |
1423 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); | |
1424 | *rate_select = 0; | |
1425 | } | |
1426 | } | |
1427 | ||
00c09d70 | 1428 | bool |
5bfe2ac0 | 1429 | intel_dp_compute_config(struct intel_encoder *encoder, |
5cec258b | 1430 | struct intel_crtc_state *pipe_config) |
a4fc5ed6 | 1431 | { |
5bfe2ac0 | 1432 | struct drm_device *dev = encoder->base.dev; |
36008365 | 1433 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 1434 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
5bfe2ac0 | 1435 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1436 | enum port port = dp_to_dig_port(intel_dp)->port; |
84556d58 | 1437 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
dd06f90e | 1438 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
a4fc5ed6 | 1439 | int lane_count, clock; |
56071a20 | 1440 | int min_lane_count = 1; |
eeb6324d | 1441 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
06ea66b6 | 1442 | /* Conveniently, the link BW constants become indices with a shift...*/ |
56071a20 | 1443 | int min_clock = 0; |
a8f3ef61 | 1444 | int max_clock; |
083f9560 | 1445 | int bpp, mode_rate; |
ff9a6750 | 1446 | int link_avail, link_clock; |
94ca719e VS |
1447 | int common_rates[DP_MAX_SUPPORTED_RATES] = {}; |
1448 | int common_len; | |
04a60f9f | 1449 | uint8_t link_bw, rate_select; |
a8f3ef61 | 1450 | |
94ca719e | 1451 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
a8f3ef61 SJ |
1452 | |
1453 | /* No common link rates between source and sink */ | |
94ca719e | 1454 | WARN_ON(common_len <= 0); |
a8f3ef61 | 1455 | |
94ca719e | 1456 | max_clock = common_len - 1; |
a4fc5ed6 | 1457 | |
bc7d38a4 | 1458 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
5bfe2ac0 DV |
1459 | pipe_config->has_pch_encoder = true; |
1460 | ||
03afc4a2 | 1461 | pipe_config->has_dp_encoder = true; |
f769cd24 | 1462 | pipe_config->has_drrs = false; |
9fcb1704 | 1463 | pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; |
a4fc5ed6 | 1464 | |
dd06f90e JN |
1465 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
1466 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, | |
1467 | adjusted_mode); | |
a1b2278e CK |
1468 | |
1469 | if (INTEL_INFO(dev)->gen >= 9) { | |
1470 | int ret; | |
e435d6e5 | 1471 | ret = skl_update_scaler_crtc(pipe_config); |
a1b2278e CK |
1472 | if (ret) |
1473 | return ret; | |
1474 | } | |
1475 | ||
b5667627 | 1476 | if (HAS_GMCH_DISPLAY(dev)) |
2dd24552 JB |
1477 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
1478 | intel_connector->panel.fitting_mode); | |
1479 | else | |
b074cec8 JB |
1480 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
1481 | intel_connector->panel.fitting_mode); | |
0d3a1bee ZY |
1482 | } |
1483 | ||
cb1793ce | 1484 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
0af78a2b DV |
1485 | return false; |
1486 | ||
083f9560 | 1487 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
a8f3ef61 | 1488 | "max bw %d pixel clock %iKHz\n", |
94ca719e | 1489 | max_lane_count, common_rates[max_clock], |
241bfc38 | 1490 | adjusted_mode->crtc_clock); |
083f9560 | 1491 | |
36008365 DV |
1492 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
1493 | * bpc in between. */ | |
3e7ca985 | 1494 | bpp = pipe_config->pipe_bpp; |
56071a20 | 1495 | if (is_edp(intel_dp)) { |
22ce5628 TS |
1496 | |
1497 | /* Get bpp from vbt only for panels that dont have bpp in edid */ | |
1498 | if (intel_connector->base.display_info.bpc == 0 && | |
6aa23e65 | 1499 | (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) { |
56071a20 | 1500 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
6aa23e65 JN |
1501 | dev_priv->vbt.edp.bpp); |
1502 | bpp = dev_priv->vbt.edp.bpp; | |
56071a20 JN |
1503 | } |
1504 | ||
344c5bbc JN |
1505 | /* |
1506 | * Use the maximum clock and number of lanes the eDP panel | |
1507 | * advertizes being capable of. The panels are generally | |
1508 | * designed to support only a single clock and lane | |
1509 | * configuration, and typically these values correspond to the | |
1510 | * native resolution of the panel. | |
1511 | */ | |
1512 | min_lane_count = max_lane_count; | |
1513 | min_clock = max_clock; | |
7984211e | 1514 | } |
657445fe | 1515 | |
36008365 | 1516 | for (; bpp >= 6*3; bpp -= 2*3) { |
241bfc38 DL |
1517 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
1518 | bpp); | |
36008365 | 1519 | |
c6930992 | 1520 | for (clock = min_clock; clock <= max_clock; clock++) { |
a8f3ef61 SJ |
1521 | for (lane_count = min_lane_count; |
1522 | lane_count <= max_lane_count; | |
1523 | lane_count <<= 1) { | |
1524 | ||
94ca719e | 1525 | link_clock = common_rates[clock]; |
36008365 DV |
1526 | link_avail = intel_dp_max_data_rate(link_clock, |
1527 | lane_count); | |
1528 | ||
1529 | if (mode_rate <= link_avail) { | |
1530 | goto found; | |
1531 | } | |
1532 | } | |
1533 | } | |
1534 | } | |
c4867936 | 1535 | |
36008365 | 1536 | return false; |
3685a8f3 | 1537 | |
36008365 | 1538 | found: |
55bc60db VS |
1539 | if (intel_dp->color_range_auto) { |
1540 | /* | |
1541 | * See: | |
1542 | * CEA-861-E - 5.1 Default Encoding Parameters | |
1543 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
1544 | */ | |
0f2a2a75 VS |
1545 | pipe_config->limited_color_range = |
1546 | bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; | |
1547 | } else { | |
1548 | pipe_config->limited_color_range = | |
1549 | intel_dp->limited_color_range; | |
55bc60db VS |
1550 | } |
1551 | ||
90a6b7b0 | 1552 | pipe_config->lane_count = lane_count; |
a8f3ef61 | 1553 | |
657445fe | 1554 | pipe_config->pipe_bpp = bpp; |
94ca719e | 1555 | pipe_config->port_clock = common_rates[clock]; |
a4fc5ed6 | 1556 | |
04a60f9f VS |
1557 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
1558 | &link_bw, &rate_select); | |
1559 | ||
1560 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", | |
1561 | link_bw, rate_select, pipe_config->lane_count, | |
ff9a6750 | 1562 | pipe_config->port_clock, bpp); |
36008365 DV |
1563 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
1564 | mode_rate, link_avail); | |
a4fc5ed6 | 1565 | |
03afc4a2 | 1566 | intel_link_compute_m_n(bpp, lane_count, |
241bfc38 DL |
1567 | adjusted_mode->crtc_clock, |
1568 | pipe_config->port_clock, | |
03afc4a2 | 1569 | &pipe_config->dp_m_n); |
9d1a455b | 1570 | |
439d7ac0 | 1571 | if (intel_connector->panel.downclock_mode != NULL && |
96178eeb | 1572 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
f769cd24 | 1573 | pipe_config->has_drrs = true; |
439d7ac0 PB |
1574 | intel_link_compute_m_n(bpp, lane_count, |
1575 | intel_connector->panel.downclock_mode->clock, | |
1576 | pipe_config->port_clock, | |
1577 | &pipe_config->dp_m2_n2); | |
1578 | } | |
1579 | ||
a3c988ea | 1580 | if (!HAS_DDI(dev)) |
840b32b7 | 1581 | intel_dp_set_clock(encoder, pipe_config); |
c6bb3538 | 1582 | |
03afc4a2 | 1583 | return true; |
a4fc5ed6 KP |
1584 | } |
1585 | ||
901c2daf VS |
1586 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
1587 | const struct intel_crtc_state *pipe_config) | |
1588 | { | |
1589 | intel_dp->link_rate = pipe_config->port_clock; | |
1590 | intel_dp->lane_count = pipe_config->lane_count; | |
1591 | } | |
1592 | ||
8ac33ed3 | 1593 | static void intel_dp_prepare(struct intel_encoder *encoder) |
a4fc5ed6 | 1594 | { |
b934223d | 1595 | struct drm_device *dev = encoder->base.dev; |
417e822d | 1596 | struct drm_i915_private *dev_priv = dev->dev_private; |
b934223d | 1597 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1598 | enum port port = dp_to_dig_port(intel_dp)->port; |
b934223d | 1599 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
7c5f93b0 | 1600 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
a4fc5ed6 | 1601 | |
901c2daf VS |
1602 | intel_dp_set_link_params(intel_dp, crtc->config); |
1603 | ||
417e822d | 1604 | /* |
1a2eb460 | 1605 | * There are four kinds of DP registers: |
417e822d KP |
1606 | * |
1607 | * IBX PCH | |
1a2eb460 KP |
1608 | * SNB CPU |
1609 | * IVB CPU | |
417e822d KP |
1610 | * CPT PCH |
1611 | * | |
1612 | * IBX PCH and CPU are the same for almost everything, | |
1613 | * except that the CPU DP PLL is configured in this | |
1614 | * register | |
1615 | * | |
1616 | * CPT PCH is quite different, having many bits moved | |
1617 | * to the TRANS_DP_CTL register instead. That | |
1618 | * configuration happens (oddly) in ironlake_pch_enable | |
1619 | */ | |
9c9e7927 | 1620 | |
417e822d KP |
1621 | /* Preserve the BIOS-computed detected bit. This is |
1622 | * supposed to be read-only. | |
1623 | */ | |
1624 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
a4fc5ed6 | 1625 | |
417e822d | 1626 | /* Handle DP bits in common between all three register formats */ |
417e822d | 1627 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
90a6b7b0 | 1628 | intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count); |
a4fc5ed6 | 1629 | |
417e822d | 1630 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 1631 | |
39e5fa88 | 1632 | if (IS_GEN7(dev) && port == PORT_A) { |
1a2eb460 KP |
1633 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1634 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1635 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1636 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1637 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
1638 | ||
6aba5b6c | 1639 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
1640 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1641 | ||
7c62a164 | 1642 | intel_dp->DP |= crtc->pipe << 29; |
39e5fa88 | 1643 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
e3ef4479 VS |
1644 | u32 trans_dp; |
1645 | ||
39e5fa88 | 1646 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3ef4479 VS |
1647 | |
1648 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); | |
1649 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
1650 | trans_dp |= TRANS_DP_ENH_FRAMING; | |
1651 | else | |
1652 | trans_dp &= ~TRANS_DP_ENH_FRAMING; | |
1653 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); | |
39e5fa88 | 1654 | } else { |
0f2a2a75 | 1655 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
666a4537 | 1656 | !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range) |
0f2a2a75 | 1657 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
417e822d KP |
1658 | |
1659 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
1660 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1661 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1662 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1663 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
1664 | ||
6aba5b6c | 1665 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
1666 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1667 | ||
39e5fa88 | 1668 | if (IS_CHERRYVIEW(dev)) |
44f37d1f | 1669 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
39e5fa88 VS |
1670 | else if (crtc->pipe == PIPE_B) |
1671 | intel_dp->DP |= DP_PIPEB_SELECT; | |
32f9d658 | 1672 | } |
a4fc5ed6 KP |
1673 | } |
1674 | ||
ffd6749d PZ |
1675 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1676 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
99ea7127 | 1677 | |
1a5ef5b7 PZ |
1678 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1679 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) | |
99ea7127 | 1680 | |
ffd6749d PZ |
1681 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1682 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
99ea7127 | 1683 | |
4be73780 | 1684 | static void wait_panel_status(struct intel_dp *intel_dp, |
99ea7127 KP |
1685 | u32 mask, |
1686 | u32 value) | |
bd943159 | 1687 | { |
30add22d | 1688 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
99ea7127 | 1689 | struct drm_i915_private *dev_priv = dev->dev_private; |
f0f59a00 | 1690 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
453c5420 | 1691 | |
e39b999a VS |
1692 | lockdep_assert_held(&dev_priv->pps_mutex); |
1693 | ||
bf13e81b JN |
1694 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1695 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 1696 | |
99ea7127 | 1697 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
453c5420 JB |
1698 | mask, value, |
1699 | I915_READ(pp_stat_reg), | |
1700 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1701 | |
3f177625 TU |
1702 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, |
1703 | 5 * USEC_PER_SEC, 10 * USEC_PER_MSEC)) | |
99ea7127 | 1704 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
453c5420 JB |
1705 | I915_READ(pp_stat_reg), |
1706 | I915_READ(pp_ctrl_reg)); | |
54c136d4 CW |
1707 | |
1708 | DRM_DEBUG_KMS("Wait complete\n"); | |
99ea7127 | 1709 | } |
32ce697c | 1710 | |
4be73780 | 1711 | static void wait_panel_on(struct intel_dp *intel_dp) |
99ea7127 KP |
1712 | { |
1713 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
4be73780 | 1714 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
bd943159 KP |
1715 | } |
1716 | ||
4be73780 | 1717 | static void wait_panel_off(struct intel_dp *intel_dp) |
99ea7127 KP |
1718 | { |
1719 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
4be73780 | 1720 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
99ea7127 KP |
1721 | } |
1722 | ||
4be73780 | 1723 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
99ea7127 | 1724 | { |
d28d4731 AK |
1725 | ktime_t panel_power_on_time; |
1726 | s64 panel_power_off_duration; | |
1727 | ||
99ea7127 | 1728 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
dce56b3c | 1729 | |
d28d4731 AK |
1730 | /* take the difference of currrent time and panel power off time |
1731 | * and then make panel wait for t11_t12 if needed. */ | |
1732 | panel_power_on_time = ktime_get_boottime(); | |
1733 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); | |
1734 | ||
dce56b3c PZ |
1735 | /* When we disable the VDD override bit last we have to do the manual |
1736 | * wait. */ | |
d28d4731 AK |
1737 | if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
1738 | wait_remaining_ms_from_jiffies(jiffies, | |
1739 | intel_dp->panel_power_cycle_delay - panel_power_off_duration); | |
dce56b3c | 1740 | |
4be73780 | 1741 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
99ea7127 KP |
1742 | } |
1743 | ||
4be73780 | 1744 | static void wait_backlight_on(struct intel_dp *intel_dp) |
dce56b3c PZ |
1745 | { |
1746 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, | |
1747 | intel_dp->backlight_on_delay); | |
1748 | } | |
1749 | ||
4be73780 | 1750 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
dce56b3c PZ |
1751 | { |
1752 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, | |
1753 | intel_dp->backlight_off_delay); | |
1754 | } | |
99ea7127 | 1755 | |
832dd3c1 KP |
1756 | /* Read the current pp_control value, unlocking the register if it |
1757 | * is locked | |
1758 | */ | |
1759 | ||
453c5420 | 1760 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 1761 | { |
453c5420 JB |
1762 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1763 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1764 | u32 control; | |
832dd3c1 | 1765 | |
e39b999a VS |
1766 | lockdep_assert_held(&dev_priv->pps_mutex); |
1767 | ||
bf13e81b | 1768 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
b0a08bec VK |
1769 | if (!IS_BROXTON(dev)) { |
1770 | control &= ~PANEL_UNLOCK_MASK; | |
1771 | control |= PANEL_UNLOCK_REGS; | |
1772 | } | |
832dd3c1 | 1773 | return control; |
bd943159 KP |
1774 | } |
1775 | ||
951468f3 VS |
1776 | /* |
1777 | * Must be paired with edp_panel_vdd_off(). | |
1778 | * Must hold pps_mutex around the whole on/off sequence. | |
1779 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
1780 | */ | |
1e0560e0 | 1781 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 1782 | { |
30add22d | 1783 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4e6e1a54 ID |
1784 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1785 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
5d613501 | 1786 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e6e1a54 | 1787 | enum intel_display_power_domain power_domain; |
5d613501 | 1788 | u32 pp; |
f0f59a00 | 1789 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
adddaaf4 | 1790 | bool need_to_disable = !intel_dp->want_panel_vdd; |
5d613501 | 1791 | |
e39b999a VS |
1792 | lockdep_assert_held(&dev_priv->pps_mutex); |
1793 | ||
97af61f5 | 1794 | if (!is_edp(intel_dp)) |
adddaaf4 | 1795 | return false; |
bd943159 | 1796 | |
2c623c11 | 1797 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
bd943159 | 1798 | intel_dp->want_panel_vdd = true; |
99ea7127 | 1799 | |
4be73780 | 1800 | if (edp_have_panel_vdd(intel_dp)) |
adddaaf4 | 1801 | return need_to_disable; |
b0665d57 | 1802 | |
25f78f58 | 1803 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4e6e1a54 | 1804 | intel_display_power_get(dev_priv, power_domain); |
e9cb81a2 | 1805 | |
3936fcf4 VS |
1806 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
1807 | port_name(intel_dig_port->port)); | |
bd943159 | 1808 | |
4be73780 DV |
1809 | if (!edp_have_panel_power(intel_dp)) |
1810 | wait_panel_power_cycle(intel_dp); | |
99ea7127 | 1811 | |
453c5420 | 1812 | pp = ironlake_get_pp_control(intel_dp); |
5d613501 | 1813 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 1814 | |
bf13e81b JN |
1815 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1816 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 JB |
1817 | |
1818 | I915_WRITE(pp_ctrl_reg, pp); | |
1819 | POSTING_READ(pp_ctrl_reg); | |
1820 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1821 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
ebf33b18 KP |
1822 | /* |
1823 | * If the panel wasn't on, delay before accessing aux channel | |
1824 | */ | |
4be73780 | 1825 | if (!edp_have_panel_power(intel_dp)) { |
3936fcf4 VS |
1826 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
1827 | port_name(intel_dig_port->port)); | |
f01eca2e | 1828 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 1829 | } |
adddaaf4 JN |
1830 | |
1831 | return need_to_disable; | |
1832 | } | |
1833 | ||
951468f3 VS |
1834 | /* |
1835 | * Must be paired with intel_edp_panel_vdd_off() or | |
1836 | * intel_edp_panel_off(). | |
1837 | * Nested calls to these functions are not allowed since | |
1838 | * we drop the lock. Caller must use some higher level | |
1839 | * locking to prevent nested calls from other threads. | |
1840 | */ | |
b80d6c78 | 1841 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
adddaaf4 | 1842 | { |
c695b6b6 | 1843 | bool vdd; |
adddaaf4 | 1844 | |
c695b6b6 VS |
1845 | if (!is_edp(intel_dp)) |
1846 | return; | |
1847 | ||
773538e8 | 1848 | pps_lock(intel_dp); |
c695b6b6 | 1849 | vdd = edp_panel_vdd_on(intel_dp); |
773538e8 | 1850 | pps_unlock(intel_dp); |
c695b6b6 | 1851 | |
e2c719b7 | 1852 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
3936fcf4 | 1853 | port_name(dp_to_dig_port(intel_dp)->port)); |
5d613501 JB |
1854 | } |
1855 | ||
4be73780 | 1856 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 1857 | { |
30add22d | 1858 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5d613501 | 1859 | struct drm_i915_private *dev_priv = dev->dev_private; |
be2c9196 VS |
1860 | struct intel_digital_port *intel_dig_port = |
1861 | dp_to_dig_port(intel_dp); | |
1862 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1863 | enum intel_display_power_domain power_domain; | |
5d613501 | 1864 | u32 pp; |
f0f59a00 | 1865 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
5d613501 | 1866 | |
e39b999a | 1867 | lockdep_assert_held(&dev_priv->pps_mutex); |
a0e99e68 | 1868 | |
15e899a0 | 1869 | WARN_ON(intel_dp->want_panel_vdd); |
4e6e1a54 | 1870 | |
15e899a0 | 1871 | if (!edp_have_panel_vdd(intel_dp)) |
be2c9196 | 1872 | return; |
b0665d57 | 1873 | |
3936fcf4 VS |
1874 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
1875 | port_name(intel_dig_port->port)); | |
bd943159 | 1876 | |
be2c9196 VS |
1877 | pp = ironlake_get_pp_control(intel_dp); |
1878 | pp &= ~EDP_FORCE_VDD; | |
453c5420 | 1879 | |
be2c9196 VS |
1880 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1881 | pp_stat_reg = _pp_stat_reg(intel_dp); | |
99ea7127 | 1882 | |
be2c9196 VS |
1883 | I915_WRITE(pp_ctrl_reg, pp); |
1884 | POSTING_READ(pp_ctrl_reg); | |
90791a5c | 1885 | |
be2c9196 VS |
1886 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1887 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1888 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
e9cb81a2 | 1889 | |
be2c9196 | 1890 | if ((pp & POWER_TARGET_ON) == 0) |
d28d4731 | 1891 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
e9cb81a2 | 1892 | |
25f78f58 | 1893 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
be2c9196 | 1894 | intel_display_power_put(dev_priv, power_domain); |
bd943159 | 1895 | } |
5d613501 | 1896 | |
4be73780 | 1897 | static void edp_panel_vdd_work(struct work_struct *__work) |
bd943159 KP |
1898 | { |
1899 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
1900 | struct intel_dp, panel_vdd_work); | |
bd943159 | 1901 | |
773538e8 | 1902 | pps_lock(intel_dp); |
15e899a0 VS |
1903 | if (!intel_dp->want_panel_vdd) |
1904 | edp_panel_vdd_off_sync(intel_dp); | |
773538e8 | 1905 | pps_unlock(intel_dp); |
bd943159 KP |
1906 | } |
1907 | ||
aba86890 ID |
1908 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
1909 | { | |
1910 | unsigned long delay; | |
1911 | ||
1912 | /* | |
1913 | * Queue the timer to fire a long time from now (relative to the power | |
1914 | * down delay) to keep the panel power up across a sequence of | |
1915 | * operations. | |
1916 | */ | |
1917 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); | |
1918 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); | |
1919 | } | |
1920 | ||
951468f3 VS |
1921 | /* |
1922 | * Must be paired with edp_panel_vdd_on(). | |
1923 | * Must hold pps_mutex around the whole on/off sequence. | |
1924 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
1925 | */ | |
4be73780 | 1926 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 1927 | { |
e39b999a VS |
1928 | struct drm_i915_private *dev_priv = |
1929 | intel_dp_to_dev(intel_dp)->dev_private; | |
1930 | ||
1931 | lockdep_assert_held(&dev_priv->pps_mutex); | |
1932 | ||
97af61f5 KP |
1933 | if (!is_edp(intel_dp)) |
1934 | return; | |
5d613501 | 1935 | |
e2c719b7 | 1936 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
3936fcf4 | 1937 | port_name(dp_to_dig_port(intel_dp)->port)); |
f2e8b18a | 1938 | |
bd943159 KP |
1939 | intel_dp->want_panel_vdd = false; |
1940 | ||
aba86890 | 1941 | if (sync) |
4be73780 | 1942 | edp_panel_vdd_off_sync(intel_dp); |
aba86890 ID |
1943 | else |
1944 | edp_panel_vdd_schedule_off(intel_dp); | |
5d613501 JB |
1945 | } |
1946 | ||
9f0fb5be | 1947 | static void edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 1948 | { |
30add22d | 1949 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9934c132 | 1950 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1951 | u32 pp; |
f0f59a00 | 1952 | i915_reg_t pp_ctrl_reg; |
9934c132 | 1953 | |
9f0fb5be VS |
1954 | lockdep_assert_held(&dev_priv->pps_mutex); |
1955 | ||
97af61f5 | 1956 | if (!is_edp(intel_dp)) |
bd943159 | 1957 | return; |
99ea7127 | 1958 | |
3936fcf4 VS |
1959 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
1960 | port_name(dp_to_dig_port(intel_dp)->port)); | |
e39b999a | 1961 | |
e7a89ace VS |
1962 | if (WARN(edp_have_panel_power(intel_dp), |
1963 | "eDP port %c panel power already on\n", | |
1964 | port_name(dp_to_dig_port(intel_dp)->port))) | |
9f0fb5be | 1965 | return; |
9934c132 | 1966 | |
4be73780 | 1967 | wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 1968 | |
bf13e81b | 1969 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 1970 | pp = ironlake_get_pp_control(intel_dp); |
05ce1a49 KP |
1971 | if (IS_GEN5(dev)) { |
1972 | /* ILK workaround: disable reset around power sequence */ | |
1973 | pp &= ~PANEL_POWER_RESET; | |
bf13e81b JN |
1974 | I915_WRITE(pp_ctrl_reg, pp); |
1975 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 1976 | } |
37c6c9b0 | 1977 | |
1c0ae80a | 1978 | pp |= POWER_TARGET_ON; |
99ea7127 KP |
1979 | if (!IS_GEN5(dev)) |
1980 | pp |= PANEL_POWER_RESET; | |
1981 | ||
453c5420 JB |
1982 | I915_WRITE(pp_ctrl_reg, pp); |
1983 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 1984 | |
4be73780 | 1985 | wait_panel_on(intel_dp); |
dce56b3c | 1986 | intel_dp->last_power_on = jiffies; |
9934c132 | 1987 | |
05ce1a49 KP |
1988 | if (IS_GEN5(dev)) { |
1989 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ | |
bf13e81b JN |
1990 | I915_WRITE(pp_ctrl_reg, pp); |
1991 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 1992 | } |
9f0fb5be | 1993 | } |
e39b999a | 1994 | |
9f0fb5be VS |
1995 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
1996 | { | |
1997 | if (!is_edp(intel_dp)) | |
1998 | return; | |
1999 | ||
2000 | pps_lock(intel_dp); | |
2001 | edp_panel_on(intel_dp); | |
773538e8 | 2002 | pps_unlock(intel_dp); |
9934c132 JB |
2003 | } |
2004 | ||
9f0fb5be VS |
2005 | |
2006 | static void edp_panel_off(struct intel_dp *intel_dp) | |
9934c132 | 2007 | { |
4e6e1a54 ID |
2008 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2009 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
30add22d | 2010 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9934c132 | 2011 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e6e1a54 | 2012 | enum intel_display_power_domain power_domain; |
99ea7127 | 2013 | u32 pp; |
f0f59a00 | 2014 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2015 | |
9f0fb5be VS |
2016 | lockdep_assert_held(&dev_priv->pps_mutex); |
2017 | ||
97af61f5 KP |
2018 | if (!is_edp(intel_dp)) |
2019 | return; | |
37c6c9b0 | 2020 | |
3936fcf4 VS |
2021 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
2022 | port_name(dp_to_dig_port(intel_dp)->port)); | |
37c6c9b0 | 2023 | |
3936fcf4 VS |
2024 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
2025 | port_name(dp_to_dig_port(intel_dp)->port)); | |
24f3e092 | 2026 | |
453c5420 | 2027 | pp = ironlake_get_pp_control(intel_dp); |
35a38556 DV |
2028 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
2029 | * panels get very unhappy and cease to work. */ | |
b3064154 PJ |
2030 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
2031 | EDP_BLC_ENABLE); | |
453c5420 | 2032 | |
bf13e81b | 2033 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2034 | |
849e39f5 PZ |
2035 | intel_dp->want_panel_vdd = false; |
2036 | ||
453c5420 JB |
2037 | I915_WRITE(pp_ctrl_reg, pp); |
2038 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2039 | |
d28d4731 | 2040 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
4be73780 | 2041 | wait_panel_off(intel_dp); |
849e39f5 PZ |
2042 | |
2043 | /* We got a reference when we enabled the VDD. */ | |
25f78f58 | 2044 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4e6e1a54 | 2045 | intel_display_power_put(dev_priv, power_domain); |
9f0fb5be | 2046 | } |
e39b999a | 2047 | |
9f0fb5be VS |
2048 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
2049 | { | |
2050 | if (!is_edp(intel_dp)) | |
2051 | return; | |
e39b999a | 2052 | |
9f0fb5be VS |
2053 | pps_lock(intel_dp); |
2054 | edp_panel_off(intel_dp); | |
773538e8 | 2055 | pps_unlock(intel_dp); |
9934c132 JB |
2056 | } |
2057 | ||
1250d107 JN |
2058 | /* Enable backlight in the panel power control. */ |
2059 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) | |
32f9d658 | 2060 | { |
da63a9f2 PZ |
2061 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2062 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
32f9d658 ZW |
2063 | struct drm_i915_private *dev_priv = dev->dev_private; |
2064 | u32 pp; | |
f0f59a00 | 2065 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2066 | |
01cb9ea6 JB |
2067 | /* |
2068 | * If we enable the backlight right away following a panel power | |
2069 | * on, we may see slight flicker as the panel syncs with the eDP | |
2070 | * link. So delay a bit to make sure the image is solid before | |
2071 | * allowing it to appear. | |
2072 | */ | |
4be73780 | 2073 | wait_backlight_on(intel_dp); |
e39b999a | 2074 | |
773538e8 | 2075 | pps_lock(intel_dp); |
e39b999a | 2076 | |
453c5420 | 2077 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2078 | pp |= EDP_BLC_ENABLE; |
453c5420 | 2079 | |
bf13e81b | 2080 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2081 | |
2082 | I915_WRITE(pp_ctrl_reg, pp); | |
2083 | POSTING_READ(pp_ctrl_reg); | |
e39b999a | 2084 | |
773538e8 | 2085 | pps_unlock(intel_dp); |
32f9d658 ZW |
2086 | } |
2087 | ||
1250d107 JN |
2088 | /* Enable backlight PWM and backlight PP control. */ |
2089 | void intel_edp_backlight_on(struct intel_dp *intel_dp) | |
2090 | { | |
2091 | if (!is_edp(intel_dp)) | |
2092 | return; | |
2093 | ||
2094 | DRM_DEBUG_KMS("\n"); | |
2095 | ||
2096 | intel_panel_enable_backlight(intel_dp->attached_connector); | |
2097 | _intel_edp_backlight_on(intel_dp); | |
2098 | } | |
2099 | ||
2100 | /* Disable backlight in the panel power control. */ | |
2101 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) | |
32f9d658 | 2102 | { |
30add22d | 2103 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
32f9d658 ZW |
2104 | struct drm_i915_private *dev_priv = dev->dev_private; |
2105 | u32 pp; | |
f0f59a00 | 2106 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2107 | |
f01eca2e KP |
2108 | if (!is_edp(intel_dp)) |
2109 | return; | |
2110 | ||
773538e8 | 2111 | pps_lock(intel_dp); |
e39b999a | 2112 | |
453c5420 | 2113 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2114 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 2115 | |
bf13e81b | 2116 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2117 | |
2118 | I915_WRITE(pp_ctrl_reg, pp); | |
2119 | POSTING_READ(pp_ctrl_reg); | |
f7d2323c | 2120 | |
773538e8 | 2121 | pps_unlock(intel_dp); |
e39b999a VS |
2122 | |
2123 | intel_dp->last_backlight_off = jiffies; | |
f7d2323c | 2124 | edp_wait_backlight_off(intel_dp); |
1250d107 | 2125 | } |
f7d2323c | 2126 | |
1250d107 JN |
2127 | /* Disable backlight PP control and backlight PWM. */ |
2128 | void intel_edp_backlight_off(struct intel_dp *intel_dp) | |
2129 | { | |
2130 | if (!is_edp(intel_dp)) | |
2131 | return; | |
2132 | ||
2133 | DRM_DEBUG_KMS("\n"); | |
f7d2323c | 2134 | |
1250d107 | 2135 | _intel_edp_backlight_off(intel_dp); |
f7d2323c | 2136 | intel_panel_disable_backlight(intel_dp->attached_connector); |
32f9d658 | 2137 | } |
a4fc5ed6 | 2138 | |
73580fb7 JN |
2139 | /* |
2140 | * Hook for controlling the panel power control backlight through the bl_power | |
2141 | * sysfs attribute. Take care to handle multiple calls. | |
2142 | */ | |
2143 | static void intel_edp_backlight_power(struct intel_connector *connector, | |
2144 | bool enable) | |
2145 | { | |
2146 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); | |
e39b999a VS |
2147 | bool is_enabled; |
2148 | ||
773538e8 | 2149 | pps_lock(intel_dp); |
e39b999a | 2150 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
773538e8 | 2151 | pps_unlock(intel_dp); |
73580fb7 JN |
2152 | |
2153 | if (is_enabled == enable) | |
2154 | return; | |
2155 | ||
23ba9373 JN |
2156 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
2157 | enable ? "enable" : "disable"); | |
73580fb7 JN |
2158 | |
2159 | if (enable) | |
2160 | _intel_edp_backlight_on(intel_dp); | |
2161 | else | |
2162 | _intel_edp_backlight_off(intel_dp); | |
2163 | } | |
2164 | ||
64e1077a VS |
2165 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
2166 | { | |
2167 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
2168 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
2169 | bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; | |
2170 | ||
2171 | I915_STATE_WARN(cur_state != state, | |
2172 | "DP port %c state assertion failure (expected %s, current %s)\n", | |
2173 | port_name(dig_port->port), | |
87ad3212 | 2174 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2175 | } |
2176 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) | |
2177 | ||
2178 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) | |
2179 | { | |
2180 | bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; | |
2181 | ||
2182 | I915_STATE_WARN(cur_state != state, | |
2183 | "eDP PLL state assertion failure (expected %s, current %s)\n", | |
87ad3212 | 2184 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2185 | } |
2186 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) | |
2187 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) | |
2188 | ||
2bd2ad64 | 2189 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
d240f20f | 2190 | { |
da63a9f2 | 2191 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
64e1077a VS |
2192 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
2193 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
d240f20f | 2194 | |
64e1077a VS |
2195 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2196 | assert_dp_port_disabled(intel_dp); | |
2197 | assert_edp_pll_disabled(dev_priv); | |
2bd2ad64 | 2198 | |
abfce949 VS |
2199 | DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", |
2200 | crtc->config->port_clock); | |
2201 | ||
2202 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; | |
2203 | ||
2204 | if (crtc->config->port_clock == 162000) | |
2205 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; | |
2206 | else | |
2207 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
2208 | ||
2209 | I915_WRITE(DP_A, intel_dp->DP); | |
2210 | POSTING_READ(DP_A); | |
2211 | udelay(500); | |
2212 | ||
6b23f3e8 VS |
2213 | /* |
2214 | * [DevILK] Work around required when enabling DP PLL | |
2215 | * while a pipe is enabled going to FDI: | |
2216 | * 1. Wait for the start of vertical blank on the enabled pipe going to FDI | |
2217 | * 2. Program DP PLL enable | |
2218 | */ | |
2219 | if (IS_GEN5(dev_priv)) | |
2220 | intel_wait_for_vblank_if_active(dev_priv->dev, !crtc->pipe); | |
2221 | ||
0767935e | 2222 | intel_dp->DP |= DP_PLL_ENABLE; |
6fec7662 | 2223 | |
0767935e | 2224 | I915_WRITE(DP_A, intel_dp->DP); |
298b0b39 JB |
2225 | POSTING_READ(DP_A); |
2226 | udelay(200); | |
d240f20f JB |
2227 | } |
2228 | ||
2bd2ad64 | 2229 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
d240f20f | 2230 | { |
da63a9f2 | 2231 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
64e1077a VS |
2232 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
2233 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
d240f20f | 2234 | |
64e1077a VS |
2235 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2236 | assert_dp_port_disabled(intel_dp); | |
2237 | assert_edp_pll_enabled(dev_priv); | |
2bd2ad64 | 2238 | |
abfce949 VS |
2239 | DRM_DEBUG_KMS("disabling eDP PLL\n"); |
2240 | ||
6fec7662 | 2241 | intel_dp->DP &= ~DP_PLL_ENABLE; |
0767935e | 2242 | |
6fec7662 | 2243 | I915_WRITE(DP_A, intel_dp->DP); |
1af5fa1b | 2244 | POSTING_READ(DP_A); |
d240f20f JB |
2245 | udelay(200); |
2246 | } | |
2247 | ||
c7ad3810 | 2248 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 2249 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 JB |
2250 | { |
2251 | int ret, i; | |
2252 | ||
2253 | /* Should have a valid DPCD by this point */ | |
2254 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
2255 | return; | |
2256 | ||
2257 | if (mode != DRM_MODE_DPMS_ON) { | |
9d1a1031 JN |
2258 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2259 | DP_SET_POWER_D3); | |
c7ad3810 JB |
2260 | } else { |
2261 | /* | |
2262 | * When turning on, we need to retry for 1ms to give the sink | |
2263 | * time to wake up. | |
2264 | */ | |
2265 | for (i = 0; i < 3; i++) { | |
9d1a1031 JN |
2266 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2267 | DP_SET_POWER_D0); | |
c7ad3810 JB |
2268 | if (ret == 1) |
2269 | break; | |
2270 | msleep(1); | |
2271 | } | |
2272 | } | |
f9cac721 JN |
2273 | |
2274 | if (ret != 1) | |
2275 | DRM_DEBUG_KMS("failed to %s sink power state\n", | |
2276 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); | |
c7ad3810 JB |
2277 | } |
2278 | ||
19d8fe15 DV |
2279 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
2280 | enum pipe *pipe) | |
d240f20f | 2281 | { |
19d8fe15 | 2282 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 2283 | enum port port = dp_to_dig_port(intel_dp)->port; |
19d8fe15 DV |
2284 | struct drm_device *dev = encoder->base.dev; |
2285 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d129bea ID |
2286 | enum intel_display_power_domain power_domain; |
2287 | u32 tmp; | |
6fa9a5ec | 2288 | bool ret; |
6d129bea ID |
2289 | |
2290 | power_domain = intel_display_port_power_domain(encoder); | |
6fa9a5ec | 2291 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
2292 | return false; |
2293 | ||
6fa9a5ec ID |
2294 | ret = false; |
2295 | ||
6d129bea | 2296 | tmp = I915_READ(intel_dp->output_reg); |
19d8fe15 DV |
2297 | |
2298 | if (!(tmp & DP_PORT_EN)) | |
6fa9a5ec | 2299 | goto out; |
19d8fe15 | 2300 | |
39e5fa88 | 2301 | if (IS_GEN7(dev) && port == PORT_A) { |
19d8fe15 | 2302 | *pipe = PORT_TO_PIPE_CPT(tmp); |
39e5fa88 | 2303 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
adc289d7 | 2304 | enum pipe p; |
19d8fe15 | 2305 | |
adc289d7 VS |
2306 | for_each_pipe(dev_priv, p) { |
2307 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); | |
2308 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { | |
2309 | *pipe = p; | |
6fa9a5ec ID |
2310 | ret = true; |
2311 | ||
2312 | goto out; | |
19d8fe15 DV |
2313 | } |
2314 | } | |
19d8fe15 | 2315 | |
4a0833ec | 2316 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
f0f59a00 | 2317 | i915_mmio_reg_offset(intel_dp->output_reg)); |
39e5fa88 VS |
2318 | } else if (IS_CHERRYVIEW(dev)) { |
2319 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); | |
2320 | } else { | |
2321 | *pipe = PORT_TO_PIPE(tmp); | |
4a0833ec | 2322 | } |
d240f20f | 2323 | |
6fa9a5ec ID |
2324 | ret = true; |
2325 | ||
2326 | out: | |
2327 | intel_display_power_put(dev_priv, power_domain); | |
2328 | ||
2329 | return ret; | |
19d8fe15 | 2330 | } |
d240f20f | 2331 | |
045ac3b5 | 2332 | static void intel_dp_get_config(struct intel_encoder *encoder, |
5cec258b | 2333 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
2334 | { |
2335 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
045ac3b5 | 2336 | u32 tmp, flags = 0; |
63000ef6 XZ |
2337 | struct drm_device *dev = encoder->base.dev; |
2338 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2339 | enum port port = dp_to_dig_port(intel_dp)->port; | |
2340 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
045ac3b5 | 2341 | |
9ed109a7 | 2342 | tmp = I915_READ(intel_dp->output_reg); |
9fcb1704 JN |
2343 | |
2344 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; | |
9ed109a7 | 2345 | |
39e5fa88 | 2346 | if (HAS_PCH_CPT(dev) && port != PORT_A) { |
b81e34c2 VS |
2347 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
2348 | ||
2349 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
63000ef6 XZ |
2350 | flags |= DRM_MODE_FLAG_PHSYNC; |
2351 | else | |
2352 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2353 | |
b81e34c2 | 2354 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
63000ef6 XZ |
2355 | flags |= DRM_MODE_FLAG_PVSYNC; |
2356 | else | |
2357 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2358 | } else { | |
39e5fa88 | 2359 | if (tmp & DP_SYNC_HS_HIGH) |
63000ef6 XZ |
2360 | flags |= DRM_MODE_FLAG_PHSYNC; |
2361 | else | |
2362 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2363 | |
39e5fa88 | 2364 | if (tmp & DP_SYNC_VS_HIGH) |
63000ef6 XZ |
2365 | flags |= DRM_MODE_FLAG_PVSYNC; |
2366 | else | |
2367 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2368 | } | |
045ac3b5 | 2369 | |
2d112de7 | 2370 | pipe_config->base.adjusted_mode.flags |= flags; |
f1f644dc | 2371 | |
8c875fca | 2372 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
666a4537 | 2373 | !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235) |
8c875fca VS |
2374 | pipe_config->limited_color_range = true; |
2375 | ||
eb14cb74 VS |
2376 | pipe_config->has_dp_encoder = true; |
2377 | ||
90a6b7b0 VS |
2378 | pipe_config->lane_count = |
2379 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; | |
2380 | ||
eb14cb74 VS |
2381 | intel_dp_get_m_n(crtc, pipe_config); |
2382 | ||
18442d08 | 2383 | if (port == PORT_A) { |
b377e0df | 2384 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
f1f644dc JB |
2385 | pipe_config->port_clock = 162000; |
2386 | else | |
2387 | pipe_config->port_clock = 270000; | |
2388 | } | |
18442d08 | 2389 | |
e3b247da VS |
2390 | pipe_config->base.adjusted_mode.crtc_clock = |
2391 | intel_dotclock_calculate(pipe_config->port_clock, | |
2392 | &pipe_config->dp_m_n); | |
7f16e5c1 | 2393 | |
6aa23e65 JN |
2394 | if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp && |
2395 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { | |
c6cd2ee2 JN |
2396 | /* |
2397 | * This is a big fat ugly hack. | |
2398 | * | |
2399 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
2400 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
2401 | * unknown we fail to light up. Yet the same BIOS boots up with | |
2402 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
2403 | * max, not what it tells us to use. | |
2404 | * | |
2405 | * Note: This will still be broken if the eDP panel is not lit | |
2406 | * up by the BIOS, and thus we can't get the mode at module | |
2407 | * load. | |
2408 | */ | |
2409 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
6aa23e65 JN |
2410 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
2411 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; | |
c6cd2ee2 | 2412 | } |
045ac3b5 JB |
2413 | } |
2414 | ||
e8cb4558 | 2415 | static void intel_disable_dp(struct intel_encoder *encoder) |
d240f20f | 2416 | { |
e8cb4558 | 2417 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 2418 | struct drm_device *dev = encoder->base.dev; |
495a5bb8 JN |
2419 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
2420 | ||
6e3c9717 | 2421 | if (crtc->config->has_audio) |
495a5bb8 | 2422 | intel_audio_codec_disable(encoder); |
6cb49835 | 2423 | |
b32c6f48 RV |
2424 | if (HAS_PSR(dev) && !HAS_DDI(dev)) |
2425 | intel_psr_disable(intel_dp); | |
2426 | ||
6cb49835 DV |
2427 | /* Make sure the panel is off before trying to change the mode. But also |
2428 | * ensure that we have vdd while we switch off the panel. */ | |
24f3e092 | 2429 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 2430 | intel_edp_backlight_off(intel_dp); |
fdbc3b1f | 2431 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
4be73780 | 2432 | intel_edp_panel_off(intel_dp); |
3739850b | 2433 | |
08aff3fe VS |
2434 | /* disable the port before the pipe on g4x */ |
2435 | if (INTEL_INFO(dev)->gen < 5) | |
3739850b | 2436 | intel_dp_link_down(intel_dp); |
d240f20f JB |
2437 | } |
2438 | ||
08aff3fe | 2439 | static void ilk_post_disable_dp(struct intel_encoder *encoder) |
d240f20f | 2440 | { |
2bd2ad64 | 2441 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 2442 | enum port port = dp_to_dig_port(intel_dp)->port; |
2bd2ad64 | 2443 | |
49277c31 | 2444 | intel_dp_link_down(intel_dp); |
abfce949 VS |
2445 | |
2446 | /* Only ilk+ has port A */ | |
08aff3fe VS |
2447 | if (port == PORT_A) |
2448 | ironlake_edp_pll_off(intel_dp); | |
49277c31 VS |
2449 | } |
2450 | ||
2451 | static void vlv_post_disable_dp(struct intel_encoder *encoder) | |
2452 | { | |
2453 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2454 | ||
2455 | intel_dp_link_down(intel_dp); | |
2bd2ad64 DV |
2456 | } |
2457 | ||
a8f327fb VS |
2458 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
2459 | { | |
2460 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2461 | struct drm_device *dev = encoder->base.dev; | |
2462 | struct drm_i915_private *dev_priv = dev->dev_private; | |
97fd4d5c | 2463 | |
a8f327fb VS |
2464 | intel_dp_link_down(intel_dp); |
2465 | ||
2466 | mutex_lock(&dev_priv->sb_lock); | |
2467 | ||
2468 | /* Assert data lane reset */ | |
2469 | chv_data_lane_soft_reset(encoder, true); | |
580d3811 | 2470 | |
a580516d | 2471 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
2472 | } |
2473 | ||
7b13b58a VS |
2474 | static void |
2475 | _intel_dp_set_link_train(struct intel_dp *intel_dp, | |
2476 | uint32_t *DP, | |
2477 | uint8_t dp_train_pat) | |
2478 | { | |
2479 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2480 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
2481 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2482 | enum port port = intel_dig_port->port; | |
2483 | ||
2484 | if (HAS_DDI(dev)) { | |
2485 | uint32_t temp = I915_READ(DP_TP_CTL(port)); | |
2486 | ||
2487 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
2488 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
2489 | else | |
2490 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
2491 | ||
2492 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2493 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2494 | case DP_TRAINING_PATTERN_DISABLE: | |
2495 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; | |
2496 | ||
2497 | break; | |
2498 | case DP_TRAINING_PATTERN_1: | |
2499 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2500 | break; | |
2501 | case DP_TRAINING_PATTERN_2: | |
2502 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
2503 | break; | |
2504 | case DP_TRAINING_PATTERN_3: | |
2505 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
2506 | break; | |
2507 | } | |
2508 | I915_WRITE(DP_TP_CTL(port), temp); | |
2509 | ||
39e5fa88 VS |
2510 | } else if ((IS_GEN7(dev) && port == PORT_A) || |
2511 | (HAS_PCH_CPT(dev) && port != PORT_A)) { | |
7b13b58a VS |
2512 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2513 | ||
2514 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2515 | case DP_TRAINING_PATTERN_DISABLE: | |
2516 | *DP |= DP_LINK_TRAIN_OFF_CPT; | |
2517 | break; | |
2518 | case DP_TRAINING_PATTERN_1: | |
2519 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; | |
2520 | break; | |
2521 | case DP_TRAINING_PATTERN_2: | |
2522 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
2523 | break; | |
2524 | case DP_TRAINING_PATTERN_3: | |
2525 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
2526 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
2527 | break; | |
2528 | } | |
2529 | ||
2530 | } else { | |
2531 | if (IS_CHERRYVIEW(dev)) | |
2532 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; | |
2533 | else | |
2534 | *DP &= ~DP_LINK_TRAIN_MASK; | |
2535 | ||
2536 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2537 | case DP_TRAINING_PATTERN_DISABLE: | |
2538 | *DP |= DP_LINK_TRAIN_OFF; | |
2539 | break; | |
2540 | case DP_TRAINING_PATTERN_1: | |
2541 | *DP |= DP_LINK_TRAIN_PAT_1; | |
2542 | break; | |
2543 | case DP_TRAINING_PATTERN_2: | |
2544 | *DP |= DP_LINK_TRAIN_PAT_2; | |
2545 | break; | |
2546 | case DP_TRAINING_PATTERN_3: | |
2547 | if (IS_CHERRYVIEW(dev)) { | |
2548 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; | |
2549 | } else { | |
2550 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
2551 | *DP |= DP_LINK_TRAIN_PAT_2; | |
2552 | } | |
2553 | break; | |
2554 | } | |
2555 | } | |
2556 | } | |
2557 | ||
2558 | static void intel_dp_enable_port(struct intel_dp *intel_dp) | |
2559 | { | |
2560 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
2561 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6fec7662 VS |
2562 | struct intel_crtc *crtc = |
2563 | to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc); | |
7b13b58a | 2564 | |
7b13b58a VS |
2565 | /* enable with pattern 1 (as per spec) */ |
2566 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, | |
2567 | DP_TRAINING_PATTERN_1); | |
2568 | ||
2569 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
2570 | POSTING_READ(intel_dp->output_reg); | |
7b713f50 VS |
2571 | |
2572 | /* | |
2573 | * Magic for VLV/CHV. We _must_ first set up the register | |
2574 | * without actually enabling the port, and then do another | |
2575 | * write to enable the port. Otherwise link training will | |
2576 | * fail when the power sequencer is freshly used for this port. | |
2577 | */ | |
2578 | intel_dp->DP |= DP_PORT_EN; | |
6fec7662 VS |
2579 | if (crtc->config->has_audio) |
2580 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; | |
7b713f50 VS |
2581 | |
2582 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
2583 | POSTING_READ(intel_dp->output_reg); | |
580d3811 VS |
2584 | } |
2585 | ||
e8cb4558 | 2586 | static void intel_enable_dp(struct intel_encoder *encoder) |
d240f20f | 2587 | { |
e8cb4558 DV |
2588 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2589 | struct drm_device *dev = encoder->base.dev; | |
2590 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c1dec79a | 2591 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
e8cb4558 | 2592 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
d6fbdd15 | 2593 | enum pipe pipe = crtc->pipe; |
5d613501 | 2594 | |
0c33d8d7 DV |
2595 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2596 | return; | |
5d613501 | 2597 | |
093e3f13 VS |
2598 | pps_lock(intel_dp); |
2599 | ||
666a4537 | 2600 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
093e3f13 VS |
2601 | vlv_init_panel_power_sequencer(intel_dp); |
2602 | ||
7b13b58a | 2603 | intel_dp_enable_port(intel_dp); |
093e3f13 VS |
2604 | |
2605 | edp_panel_vdd_on(intel_dp); | |
2606 | edp_panel_on(intel_dp); | |
2607 | edp_panel_vdd_off(intel_dp, true); | |
2608 | ||
2609 | pps_unlock(intel_dp); | |
2610 | ||
666a4537 | 2611 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e0fce78f VS |
2612 | unsigned int lane_mask = 0x0; |
2613 | ||
2614 | if (IS_CHERRYVIEW(dev)) | |
2615 | lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count); | |
2616 | ||
9b6de0a1 VS |
2617 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
2618 | lane_mask); | |
e0fce78f | 2619 | } |
61234fa5 | 2620 | |
f01eca2e | 2621 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 2622 | intel_dp_start_link_train(intel_dp); |
3ab9c637 | 2623 | intel_dp_stop_link_train(intel_dp); |
c1dec79a | 2624 | |
6e3c9717 | 2625 | if (crtc->config->has_audio) { |
c1dec79a | 2626 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
d6fbdd15 | 2627 | pipe_name(pipe)); |
c1dec79a JN |
2628 | intel_audio_codec_enable(encoder); |
2629 | } | |
ab1f90f9 | 2630 | } |
89b667f8 | 2631 | |
ecff4f3b JN |
2632 | static void g4x_enable_dp(struct intel_encoder *encoder) |
2633 | { | |
828f5c6e JN |
2634 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2635 | ||
ecff4f3b | 2636 | intel_enable_dp(encoder); |
4be73780 | 2637 | intel_edp_backlight_on(intel_dp); |
ab1f90f9 | 2638 | } |
89b667f8 | 2639 | |
ab1f90f9 JN |
2640 | static void vlv_enable_dp(struct intel_encoder *encoder) |
2641 | { | |
828f5c6e JN |
2642 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2643 | ||
4be73780 | 2644 | intel_edp_backlight_on(intel_dp); |
b32c6f48 | 2645 | intel_psr_enable(intel_dp); |
d240f20f JB |
2646 | } |
2647 | ||
ecff4f3b | 2648 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
ab1f90f9 JN |
2649 | { |
2650 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
d6fbdd15 | 2651 | enum port port = dp_to_dig_port(intel_dp)->port; |
ab1f90f9 | 2652 | |
8ac33ed3 DV |
2653 | intel_dp_prepare(encoder); |
2654 | ||
d41f1efb | 2655 | /* Only ilk+ has port A */ |
abfce949 | 2656 | if (port == PORT_A) |
ab1f90f9 JN |
2657 | ironlake_edp_pll_on(intel_dp); |
2658 | } | |
2659 | ||
83b84597 VS |
2660 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
2661 | { | |
2662 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2663 | struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private; | |
2664 | enum pipe pipe = intel_dp->pps_pipe; | |
f0f59a00 | 2665 | i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
83b84597 VS |
2666 | |
2667 | edp_panel_vdd_off_sync(intel_dp); | |
2668 | ||
2669 | /* | |
2670 | * VLV seems to get confused when multiple power seqeuencers | |
2671 | * have the same port selected (even if only one has power/vdd | |
2672 | * enabled). The failure manifests as vlv_wait_port_ready() failing | |
2673 | * CHV on the other hand doesn't seem to mind having the same port | |
2674 | * selected in multiple power seqeuencers, but let's clear the | |
2675 | * port select always when logically disconnecting a power sequencer | |
2676 | * from a port. | |
2677 | */ | |
2678 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", | |
2679 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
2680 | I915_WRITE(pp_on_reg, 0); | |
2681 | POSTING_READ(pp_on_reg); | |
2682 | ||
2683 | intel_dp->pps_pipe = INVALID_PIPE; | |
2684 | } | |
2685 | ||
a4a5d2f8 VS |
2686 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
2687 | enum pipe pipe) | |
2688 | { | |
2689 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2690 | struct intel_encoder *encoder; | |
2691 | ||
2692 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2693 | ||
ac3c12e4 VS |
2694 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
2695 | return; | |
2696 | ||
19c8054c | 2697 | for_each_intel_encoder(dev, encoder) { |
a4a5d2f8 | 2698 | struct intel_dp *intel_dp; |
773538e8 | 2699 | enum port port; |
a4a5d2f8 VS |
2700 | |
2701 | if (encoder->type != INTEL_OUTPUT_EDP) | |
2702 | continue; | |
2703 | ||
2704 | intel_dp = enc_to_intel_dp(&encoder->base); | |
773538e8 | 2705 | port = dp_to_dig_port(intel_dp)->port; |
a4a5d2f8 VS |
2706 | |
2707 | if (intel_dp->pps_pipe != pipe) | |
2708 | continue; | |
2709 | ||
2710 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", | |
773538e8 | 2711 | pipe_name(pipe), port_name(port)); |
a4a5d2f8 | 2712 | |
e02f9a06 | 2713 | WARN(encoder->base.crtc, |
034e43c6 VS |
2714 | "stealing pipe %c power sequencer from active eDP port %c\n", |
2715 | pipe_name(pipe), port_name(port)); | |
a4a5d2f8 | 2716 | |
a4a5d2f8 | 2717 | /* make sure vdd is off before we steal it */ |
83b84597 | 2718 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
2719 | } |
2720 | } | |
2721 | ||
2722 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) | |
2723 | { | |
2724 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2725 | struct intel_encoder *encoder = &intel_dig_port->base; | |
2726 | struct drm_device *dev = encoder->base.dev; | |
2727 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2728 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
a4a5d2f8 VS |
2729 | |
2730 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2731 | ||
093e3f13 VS |
2732 | if (!is_edp(intel_dp)) |
2733 | return; | |
2734 | ||
a4a5d2f8 VS |
2735 | if (intel_dp->pps_pipe == crtc->pipe) |
2736 | return; | |
2737 | ||
2738 | /* | |
2739 | * If another power sequencer was being used on this | |
2740 | * port previously make sure to turn off vdd there while | |
2741 | * we still have control of it. | |
2742 | */ | |
2743 | if (intel_dp->pps_pipe != INVALID_PIPE) | |
83b84597 | 2744 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
2745 | |
2746 | /* | |
2747 | * We may be stealing the power | |
2748 | * sequencer from another port. | |
2749 | */ | |
2750 | vlv_steal_power_sequencer(dev, crtc->pipe); | |
2751 | ||
2752 | /* now it's all ours */ | |
2753 | intel_dp->pps_pipe = crtc->pipe; | |
2754 | ||
2755 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", | |
2756 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); | |
2757 | ||
2758 | /* init power sequencer on this pipe and port */ | |
36b5f425 VS |
2759 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
2760 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
a4a5d2f8 VS |
2761 | } |
2762 | ||
ab1f90f9 | 2763 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
a4fc5ed6 | 2764 | { |
2bd2ad64 | 2765 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 2766 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
b2634017 | 2767 | struct drm_device *dev = encoder->base.dev; |
89b667f8 | 2768 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab1f90f9 | 2769 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
e4607fcf | 2770 | enum dpio_channel port = vlv_dport_to_channel(dport); |
ab1f90f9 JN |
2771 | int pipe = intel_crtc->pipe; |
2772 | u32 val; | |
a4fc5ed6 | 2773 | |
a580516d | 2774 | mutex_lock(&dev_priv->sb_lock); |
89b667f8 | 2775 | |
ab3c759a | 2776 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
ab1f90f9 JN |
2777 | val = 0; |
2778 | if (pipe) | |
2779 | val |= (1<<21); | |
2780 | else | |
2781 | val &= ~(1<<21); | |
2782 | val |= 0x001000c4; | |
ab3c759a CML |
2783 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
2784 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); | |
2785 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
89b667f8 | 2786 | |
a580516d | 2787 | mutex_unlock(&dev_priv->sb_lock); |
ab1f90f9 JN |
2788 | |
2789 | intel_enable_dp(encoder); | |
89b667f8 JB |
2790 | } |
2791 | ||
ecff4f3b | 2792 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
2793 | { |
2794 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2795 | struct drm_device *dev = encoder->base.dev; | |
2796 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
2797 | struct intel_crtc *intel_crtc = |
2798 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 2799 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 2800 | int pipe = intel_crtc->pipe; |
89b667f8 | 2801 | |
8ac33ed3 DV |
2802 | intel_dp_prepare(encoder); |
2803 | ||
89b667f8 | 2804 | /* Program Tx lane resets to default */ |
a580516d | 2805 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 2806 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
89b667f8 JB |
2807 | DPIO_PCS_TX_LANE2_RESET | |
2808 | DPIO_PCS_TX_LANE1_RESET); | |
ab3c759a | 2809 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
89b667f8 JB |
2810 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
2811 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
2812 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
2813 | DPIO_PCS_CLK_SOFT_RESET); | |
2814 | ||
2815 | /* Fix up inter-pair skew failure */ | |
ab3c759a CML |
2816 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
2817 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
2818 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
a580516d | 2819 | mutex_unlock(&dev_priv->sb_lock); |
a4fc5ed6 KP |
2820 | } |
2821 | ||
e4a1d846 CML |
2822 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
2823 | { | |
e7d2a717 | 2824 | chv_phy_pre_encoder_enable(encoder); |
e4a1d846 | 2825 | |
e4a1d846 | 2826 | intel_enable_dp(encoder); |
b0b33846 VS |
2827 | |
2828 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 2829 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
2830 | } |
2831 | ||
9197c88b VS |
2832 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder) |
2833 | { | |
625695f8 VS |
2834 | intel_dp_prepare(encoder); |
2835 | ||
419b1b7a | 2836 | chv_phy_pre_pll_enable(encoder); |
9197c88b VS |
2837 | } |
2838 | ||
d6db995f VS |
2839 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder) |
2840 | { | |
204970b5 | 2841 | chv_phy_post_pll_disable(encoder); |
d6db995f VS |
2842 | } |
2843 | ||
a4fc5ed6 | 2844 | /* |
df0c237d JB |
2845 | * Native read with retry for link status and receiver capability reads for |
2846 | * cases where the sink may still be asleep. | |
9d1a1031 JN |
2847 | * |
2848 | * Sinks are *supposed* to come up within 1ms from an off state, but we're also | |
2849 | * supposed to retry 3 times per the spec. | |
a4fc5ed6 | 2850 | */ |
9d1a1031 JN |
2851 | static ssize_t |
2852 | intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, | |
2853 | void *buffer, size_t size) | |
a4fc5ed6 | 2854 | { |
9d1a1031 JN |
2855 | ssize_t ret; |
2856 | int i; | |
61da5fab | 2857 | |
f6a19066 VS |
2858 | /* |
2859 | * Sometime we just get the same incorrect byte repeated | |
2860 | * over the entire buffer. Doing just one throw away read | |
2861 | * initially seems to "solve" it. | |
2862 | */ | |
2863 | drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1); | |
2864 | ||
61da5fab | 2865 | for (i = 0; i < 3; i++) { |
9d1a1031 JN |
2866 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
2867 | if (ret == size) | |
2868 | return ret; | |
61da5fab JB |
2869 | msleep(1); |
2870 | } | |
a4fc5ed6 | 2871 | |
9d1a1031 | 2872 | return ret; |
a4fc5ed6 KP |
2873 | } |
2874 | ||
2875 | /* | |
2876 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
2877 | * link status information | |
2878 | */ | |
94223d04 | 2879 | bool |
93f62dad | 2880 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 2881 | { |
9d1a1031 JN |
2882 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
2883 | DP_LANE0_1_STATUS, | |
2884 | link_status, | |
2885 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; | |
a4fc5ed6 KP |
2886 | } |
2887 | ||
1100244e | 2888 | /* These are source-specific values. */ |
94223d04 | 2889 | uint8_t |
1a2eb460 | 2890 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 2891 | { |
30add22d | 2892 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
7ad14a29 | 2893 | struct drm_i915_private *dev_priv = dev->dev_private; |
bc7d38a4 | 2894 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 2895 | |
9314726b VK |
2896 | if (IS_BROXTON(dev)) |
2897 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; | |
2898 | else if (INTEL_INFO(dev)->gen >= 9) { | |
06411f08 | 2899 | if (dev_priv->vbt.edp.low_vswing && port == PORT_A) |
7ad14a29 | 2900 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
5a9d1f1a | 2901 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
666a4537 | 2902 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
bd60018a | 2903 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
bc7d38a4 | 2904 | else if (IS_GEN7(dev) && port == PORT_A) |
bd60018a | 2905 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
bc7d38a4 | 2906 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
bd60018a | 2907 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
1a2eb460 | 2908 | else |
bd60018a | 2909 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
1a2eb460 KP |
2910 | } |
2911 | ||
94223d04 | 2912 | uint8_t |
1a2eb460 KP |
2913 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
2914 | { | |
30add22d | 2915 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bc7d38a4 | 2916 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 2917 | |
5a9d1f1a DL |
2918 | if (INTEL_INFO(dev)->gen >= 9) { |
2919 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2920 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: | |
2921 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
2922 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2923 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2924 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2925 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
7ad14a29 SJ |
2926 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
2927 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
5a9d1f1a DL |
2928 | default: |
2929 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
2930 | } | |
2931 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
d6c0d722 | 2932 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
2933 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2934 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
2935 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2936 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2937 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2938 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
2939 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
d6c0d722 | 2940 | default: |
bd60018a | 2941 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
d6c0d722 | 2942 | } |
666a4537 | 2943 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e2fa6fba | 2944 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
2945 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2946 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
2947 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2948 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2949 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2950 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
2951 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
e2fa6fba | 2952 | default: |
bd60018a | 2953 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
e2fa6fba | 2954 | } |
bc7d38a4 | 2955 | } else if (IS_GEN7(dev) && port == PORT_A) { |
1a2eb460 | 2956 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
2957 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2958 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2959 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2960 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2961 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
1a2eb460 | 2962 | default: |
bd60018a | 2963 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 KP |
2964 | } |
2965 | } else { | |
2966 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a SJ |
2967 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2968 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2969 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2970 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2971 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2972 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
2973 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
1a2eb460 | 2974 | default: |
bd60018a | 2975 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 | 2976 | } |
a4fc5ed6 KP |
2977 | } |
2978 | } | |
2979 | ||
5829975c | 2980 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
e2fa6fba P |
2981 | { |
2982 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
2983 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2984 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
5e69f97f CML |
2985 | struct intel_crtc *intel_crtc = |
2986 | to_intel_crtc(dport->base.base.crtc); | |
e2fa6fba P |
2987 | unsigned long demph_reg_value, preemph_reg_value, |
2988 | uniqtranscale_reg_value; | |
2989 | uint8_t train_set = intel_dp->train_set[0]; | |
e4607fcf | 2990 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 2991 | int pipe = intel_crtc->pipe; |
e2fa6fba P |
2992 | |
2993 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 2994 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e2fa6fba P |
2995 | preemph_reg_value = 0x0004000; |
2996 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 2997 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
2998 | demph_reg_value = 0x2B405555; |
2999 | uniqtranscale_reg_value = 0x552AB83A; | |
3000 | break; | |
bd60018a | 3001 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3002 | demph_reg_value = 0x2B404040; |
3003 | uniqtranscale_reg_value = 0x5548B83A; | |
3004 | break; | |
bd60018a | 3005 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3006 | demph_reg_value = 0x2B245555; |
3007 | uniqtranscale_reg_value = 0x5560B83A; | |
3008 | break; | |
bd60018a | 3009 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e2fa6fba P |
3010 | demph_reg_value = 0x2B405555; |
3011 | uniqtranscale_reg_value = 0x5598DA3A; | |
3012 | break; | |
3013 | default: | |
3014 | return 0; | |
3015 | } | |
3016 | break; | |
bd60018a | 3017 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e2fa6fba P |
3018 | preemph_reg_value = 0x0002000; |
3019 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3020 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3021 | demph_reg_value = 0x2B404040; |
3022 | uniqtranscale_reg_value = 0x5552B83A; | |
3023 | break; | |
bd60018a | 3024 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3025 | demph_reg_value = 0x2B404848; |
3026 | uniqtranscale_reg_value = 0x5580B83A; | |
3027 | break; | |
bd60018a | 3028 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3029 | demph_reg_value = 0x2B404040; |
3030 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3031 | break; | |
3032 | default: | |
3033 | return 0; | |
3034 | } | |
3035 | break; | |
bd60018a | 3036 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e2fa6fba P |
3037 | preemph_reg_value = 0x0000000; |
3038 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3039 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3040 | demph_reg_value = 0x2B305555; |
3041 | uniqtranscale_reg_value = 0x5570B83A; | |
3042 | break; | |
bd60018a | 3043 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3044 | demph_reg_value = 0x2B2B4040; |
3045 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3046 | break; | |
3047 | default: | |
3048 | return 0; | |
3049 | } | |
3050 | break; | |
bd60018a | 3051 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e2fa6fba P |
3052 | preemph_reg_value = 0x0006000; |
3053 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3054 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3055 | demph_reg_value = 0x1B405555; |
3056 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3057 | break; | |
3058 | default: | |
3059 | return 0; | |
3060 | } | |
3061 | break; | |
3062 | default: | |
3063 | return 0; | |
3064 | } | |
3065 | ||
a580516d | 3066 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a CML |
3067 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
3068 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); | |
3069 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), | |
e2fa6fba | 3070 | uniqtranscale_reg_value); |
ab3c759a CML |
3071 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
3072 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
3073 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); | |
3074 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); | |
a580516d | 3075 | mutex_unlock(&dev_priv->sb_lock); |
e2fa6fba P |
3076 | |
3077 | return 0; | |
3078 | } | |
3079 | ||
5829975c | 3080 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
e4a1d846 | 3081 | { |
b7fa22d8 ACO |
3082 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3083 | u32 deemph_reg_value, margin_reg_value; | |
3084 | bool uniq_trans_scale = false; | |
e4a1d846 | 3085 | uint8_t train_set = intel_dp->train_set[0]; |
e4a1d846 CML |
3086 | |
3087 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3088 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e4a1d846 | 3089 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3090 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3091 | deemph_reg_value = 128; |
3092 | margin_reg_value = 52; | |
3093 | break; | |
bd60018a | 3094 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3095 | deemph_reg_value = 128; |
3096 | margin_reg_value = 77; | |
3097 | break; | |
bd60018a | 3098 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3099 | deemph_reg_value = 128; |
3100 | margin_reg_value = 102; | |
3101 | break; | |
bd60018a | 3102 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e4a1d846 CML |
3103 | deemph_reg_value = 128; |
3104 | margin_reg_value = 154; | |
b7fa22d8 | 3105 | uniq_trans_scale = true; |
e4a1d846 CML |
3106 | break; |
3107 | default: | |
3108 | return 0; | |
3109 | } | |
3110 | break; | |
bd60018a | 3111 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e4a1d846 | 3112 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3113 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3114 | deemph_reg_value = 85; |
3115 | margin_reg_value = 78; | |
3116 | break; | |
bd60018a | 3117 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3118 | deemph_reg_value = 85; |
3119 | margin_reg_value = 116; | |
3120 | break; | |
bd60018a | 3121 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3122 | deemph_reg_value = 85; |
3123 | margin_reg_value = 154; | |
3124 | break; | |
3125 | default: | |
3126 | return 0; | |
3127 | } | |
3128 | break; | |
bd60018a | 3129 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e4a1d846 | 3130 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3131 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3132 | deemph_reg_value = 64; |
3133 | margin_reg_value = 104; | |
3134 | break; | |
bd60018a | 3135 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3136 | deemph_reg_value = 64; |
3137 | margin_reg_value = 154; | |
3138 | break; | |
3139 | default: | |
3140 | return 0; | |
3141 | } | |
3142 | break; | |
bd60018a | 3143 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e4a1d846 | 3144 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3145 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3146 | deemph_reg_value = 43; |
3147 | margin_reg_value = 154; | |
3148 | break; | |
3149 | default: | |
3150 | return 0; | |
3151 | } | |
3152 | break; | |
3153 | default: | |
3154 | return 0; | |
3155 | } | |
3156 | ||
b7fa22d8 ACO |
3157 | chv_set_phy_signal_level(encoder, deemph_reg_value, |
3158 | margin_reg_value, uniq_trans_scale); | |
e4a1d846 CML |
3159 | |
3160 | return 0; | |
3161 | } | |
3162 | ||
a4fc5ed6 | 3163 | static uint32_t |
5829975c | 3164 | gen4_signal_levels(uint8_t train_set) |
a4fc5ed6 | 3165 | { |
3cf2efb1 | 3166 | uint32_t signal_levels = 0; |
a4fc5ed6 | 3167 | |
3cf2efb1 | 3168 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3169 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
a4fc5ed6 KP |
3170 | default: |
3171 | signal_levels |= DP_VOLTAGE_0_4; | |
3172 | break; | |
bd60018a | 3173 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
a4fc5ed6 KP |
3174 | signal_levels |= DP_VOLTAGE_0_6; |
3175 | break; | |
bd60018a | 3176 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
a4fc5ed6 KP |
3177 | signal_levels |= DP_VOLTAGE_0_8; |
3178 | break; | |
bd60018a | 3179 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
a4fc5ed6 KP |
3180 | signal_levels |= DP_VOLTAGE_1_2; |
3181 | break; | |
3182 | } | |
3cf2efb1 | 3183 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
bd60018a | 3184 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
a4fc5ed6 KP |
3185 | default: |
3186 | signal_levels |= DP_PRE_EMPHASIS_0; | |
3187 | break; | |
bd60018a | 3188 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
a4fc5ed6 KP |
3189 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
3190 | break; | |
bd60018a | 3191 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
a4fc5ed6 KP |
3192 | signal_levels |= DP_PRE_EMPHASIS_6; |
3193 | break; | |
bd60018a | 3194 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
a4fc5ed6 KP |
3195 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
3196 | break; | |
3197 | } | |
3198 | return signal_levels; | |
3199 | } | |
3200 | ||
e3421a18 ZW |
3201 | /* Gen6's DP voltage swing and pre-emphasis control */ |
3202 | static uint32_t | |
5829975c | 3203 | gen6_edp_signal_levels(uint8_t train_set) |
e3421a18 | 3204 | { |
3c5a62b5 YL |
3205 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3206 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3207 | switch (signal_levels) { | |
bd60018a SJ |
3208 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3209 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3210 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
bd60018a | 3211 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3c5a62b5 | 3212 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
bd60018a SJ |
3213 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3214 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
3c5a62b5 | 3215 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
bd60018a SJ |
3216 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3217 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
3c5a62b5 | 3218 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
bd60018a SJ |
3219 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3220 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3221 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
e3421a18 | 3222 | default: |
3c5a62b5 YL |
3223 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3224 | "0x%x\n", signal_levels); | |
3225 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
3226 | } |
3227 | } | |
3228 | ||
1a2eb460 KP |
3229 | /* Gen7's DP voltage swing and pre-emphasis control */ |
3230 | static uint32_t | |
5829975c | 3231 | gen7_edp_signal_levels(uint8_t train_set) |
1a2eb460 KP |
3232 | { |
3233 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
3234 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3235 | switch (signal_levels) { | |
bd60018a | 3236 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3237 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
bd60018a | 3238 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 | 3239 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
bd60018a | 3240 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
1a2eb460 KP |
3241 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
3242 | ||
bd60018a | 3243 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3244 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
bd60018a | 3245 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3246 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
3247 | ||
bd60018a | 3248 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3249 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
bd60018a | 3250 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3251 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
3252 | ||
3253 | default: | |
3254 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
3255 | "0x%x\n", signal_levels); | |
3256 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
3257 | } | |
3258 | } | |
3259 | ||
94223d04 | 3260 | void |
f4eb692e | 3261 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
f0a3424e PZ |
3262 | { |
3263 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bc7d38a4 | 3264 | enum port port = intel_dig_port->port; |
f0a3424e | 3265 | struct drm_device *dev = intel_dig_port->base.base.dev; |
b905a915 | 3266 | struct drm_i915_private *dev_priv = to_i915(dev); |
f8896f5d | 3267 | uint32_t signal_levels, mask = 0; |
f0a3424e PZ |
3268 | uint8_t train_set = intel_dp->train_set[0]; |
3269 | ||
f8896f5d DW |
3270 | if (HAS_DDI(dev)) { |
3271 | signal_levels = ddi_signal_levels(intel_dp); | |
3272 | ||
3273 | if (IS_BROXTON(dev)) | |
3274 | signal_levels = 0; | |
3275 | else | |
3276 | mask = DDI_BUF_EMP_MASK; | |
e4a1d846 | 3277 | } else if (IS_CHERRYVIEW(dev)) { |
5829975c | 3278 | signal_levels = chv_signal_levels(intel_dp); |
e2fa6fba | 3279 | } else if (IS_VALLEYVIEW(dev)) { |
5829975c | 3280 | signal_levels = vlv_signal_levels(intel_dp); |
bc7d38a4 | 3281 | } else if (IS_GEN7(dev) && port == PORT_A) { |
5829975c | 3282 | signal_levels = gen7_edp_signal_levels(train_set); |
f0a3424e | 3283 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
bc7d38a4 | 3284 | } else if (IS_GEN6(dev) && port == PORT_A) { |
5829975c | 3285 | signal_levels = gen6_edp_signal_levels(train_set); |
f0a3424e PZ |
3286 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
3287 | } else { | |
5829975c | 3288 | signal_levels = gen4_signal_levels(train_set); |
f0a3424e PZ |
3289 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
3290 | } | |
3291 | ||
96fb9f9b VK |
3292 | if (mask) |
3293 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); | |
3294 | ||
3295 | DRM_DEBUG_KMS("Using vswing level %d\n", | |
3296 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); | |
3297 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", | |
3298 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> | |
3299 | DP_TRAIN_PRE_EMPHASIS_SHIFT); | |
f0a3424e | 3300 | |
f4eb692e | 3301 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
b905a915 ACO |
3302 | |
3303 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
3304 | POSTING_READ(intel_dp->output_reg); | |
f0a3424e PZ |
3305 | } |
3306 | ||
94223d04 | 3307 | void |
e9c176d5 ACO |
3308 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
3309 | uint8_t dp_train_pat) | |
a4fc5ed6 | 3310 | { |
174edf1f | 3311 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
90a6b7b0 VS |
3312 | struct drm_i915_private *dev_priv = |
3313 | to_i915(intel_dig_port->base.base.dev); | |
a4fc5ed6 | 3314 | |
f4eb692e | 3315 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
47ea7542 | 3316 | |
f4eb692e | 3317 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
ea5b213a | 3318 | POSTING_READ(intel_dp->output_reg); |
e9c176d5 ACO |
3319 | } |
3320 | ||
94223d04 | 3321 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3ab9c637 ID |
3322 | { |
3323 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3324 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
3325 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3326 | enum port port = intel_dig_port->port; | |
3327 | uint32_t val; | |
3328 | ||
3329 | if (!HAS_DDI(dev)) | |
3330 | return; | |
3331 | ||
3332 | val = I915_READ(DP_TP_CTL(port)); | |
3333 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
3334 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
3335 | I915_WRITE(DP_TP_CTL(port), val); | |
3336 | ||
3337 | /* | |
3338 | * On PORT_A we can have only eDP in SST mode. There the only reason | |
3339 | * we need to set idle transmission mode is to work around a HW issue | |
3340 | * where we enable the pipe while not in idle link-training mode. | |
3341 | * In this case there is requirement to wait for a minimum number of | |
3342 | * idle patterns to be sent. | |
3343 | */ | |
3344 | if (port == PORT_A) | |
3345 | return; | |
3346 | ||
3347 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), | |
3348 | 1)) | |
3349 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); | |
3350 | } | |
3351 | ||
a4fc5ed6 | 3352 | static void |
ea5b213a | 3353 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 3354 | { |
da63a9f2 | 3355 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1612c8bd | 3356 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
bc7d38a4 | 3357 | enum port port = intel_dig_port->port; |
da63a9f2 | 3358 | struct drm_device *dev = intel_dig_port->base.base.dev; |
a4fc5ed6 | 3359 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 3360 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 3361 | |
bc76e320 | 3362 | if (WARN_ON(HAS_DDI(dev))) |
c19b0669 PZ |
3363 | return; |
3364 | ||
0c33d8d7 | 3365 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
1b39d6f3 CW |
3366 | return; |
3367 | ||
28c97730 | 3368 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 3369 | |
39e5fa88 VS |
3370 | if ((IS_GEN7(dev) && port == PORT_A) || |
3371 | (HAS_PCH_CPT(dev) && port != PORT_A)) { | |
e3421a18 | 3372 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1612c8bd | 3373 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
e3421a18 | 3374 | } else { |
aad3d14d VS |
3375 | if (IS_CHERRYVIEW(dev)) |
3376 | DP &= ~DP_LINK_TRAIN_MASK_CHV; | |
3377 | else | |
3378 | DP &= ~DP_LINK_TRAIN_MASK; | |
1612c8bd | 3379 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
e3421a18 | 3380 | } |
1612c8bd | 3381 | I915_WRITE(intel_dp->output_reg, DP); |
fe255d00 | 3382 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 3383 | |
1612c8bd VS |
3384 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
3385 | I915_WRITE(intel_dp->output_reg, DP); | |
3386 | POSTING_READ(intel_dp->output_reg); | |
3387 | ||
3388 | /* | |
3389 | * HW workaround for IBX, we need to move the port | |
3390 | * to transcoder A after disabling it to allow the | |
3391 | * matching HDMI port to be enabled on transcoder A. | |
3392 | */ | |
3393 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) { | |
0c241d5b VS |
3394 | /* |
3395 | * We get CPU/PCH FIFO underruns on the other pipe when | |
3396 | * doing the workaround. Sweep them under the rug. | |
3397 | */ | |
3398 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3399 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3400 | ||
1612c8bd VS |
3401 | /* always enable with pattern 1 (as per spec) */ |
3402 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); | |
3403 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; | |
3404 | I915_WRITE(intel_dp->output_reg, DP); | |
3405 | POSTING_READ(intel_dp->output_reg); | |
3406 | ||
3407 | DP &= ~DP_PORT_EN; | |
5bddd17f | 3408 | I915_WRITE(intel_dp->output_reg, DP); |
0ca09685 | 3409 | POSTING_READ(intel_dp->output_reg); |
0c241d5b VS |
3410 | |
3411 | intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A); | |
3412 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
3413 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
5bddd17f EA |
3414 | } |
3415 | ||
f01eca2e | 3416 | msleep(intel_dp->panel_power_down_delay); |
6fec7662 VS |
3417 | |
3418 | intel_dp->DP = DP; | |
a4fc5ed6 KP |
3419 | } |
3420 | ||
26d61aad KP |
3421 | static bool |
3422 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
92fd8fd1 | 3423 | { |
a031d709 RV |
3424 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
3425 | struct drm_device *dev = dig_port->base.base.dev; | |
3426 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3427 | ||
9d1a1031 JN |
3428 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3429 | sizeof(intel_dp->dpcd)) < 0) | |
edb39244 | 3430 | return false; /* aux transfer failed */ |
92fd8fd1 | 3431 | |
a8e98153 | 3432 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
577c7a50 | 3433 | |
edb39244 AJ |
3434 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
3435 | return false; /* DPCD not present */ | |
3436 | ||
30d9aa42 SS |
3437 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, |
3438 | &intel_dp->sink_count, 1) < 0) | |
3439 | return false; | |
3440 | ||
3441 | /* | |
3442 | * Sink count can change between short pulse hpd hence | |
3443 | * a member variable in intel_dp will track any changes | |
3444 | * between short pulse interrupts. | |
3445 | */ | |
3446 | intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count); | |
3447 | ||
3448 | /* | |
3449 | * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that | |
3450 | * a dongle is present but no display. Unless we require to know | |
3451 | * if a dongle is present or not, we don't need to update | |
3452 | * downstream port information. So, an early return here saves | |
3453 | * time from performing other operations which are not required. | |
3454 | */ | |
1034ce70 | 3455 | if (!is_edp(intel_dp) && !intel_dp->sink_count) |
30d9aa42 SS |
3456 | return false; |
3457 | ||
2293bb5c SK |
3458 | /* Check if the panel supports PSR */ |
3459 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); | |
50003939 | 3460 | if (is_edp(intel_dp)) { |
9d1a1031 JN |
3461 | intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, |
3462 | intel_dp->psr_dpcd, | |
3463 | sizeof(intel_dp->psr_dpcd)); | |
a031d709 RV |
3464 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
3465 | dev_priv->psr.sink_support = true; | |
50003939 | 3466 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
a031d709 | 3467 | } |
474d1ec4 SJ |
3468 | |
3469 | if (INTEL_INFO(dev)->gen >= 9 && | |
3470 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { | |
3471 | uint8_t frame_sync_cap; | |
3472 | ||
3473 | dev_priv->psr.sink_support = true; | |
3474 | intel_dp_dpcd_read_wake(&intel_dp->aux, | |
3475 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, | |
3476 | &frame_sync_cap, 1); | |
3477 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; | |
3478 | /* PSR2 needs frame sync as well */ | |
3479 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; | |
3480 | DRM_DEBUG_KMS("PSR2 %s on sink", | |
3481 | dev_priv->psr.psr2_support ? "supported" : "not supported"); | |
3482 | } | |
86ee27b5 YA |
3483 | |
3484 | /* Read the eDP Display control capabilities registers */ | |
3485 | memset(intel_dp->edp_dpcd, 0, sizeof(intel_dp->edp_dpcd)); | |
3486 | if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && | |
3487 | (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, | |
3488 | intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == | |
3489 | sizeof(intel_dp->edp_dpcd))) | |
3490 | DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd), | |
3491 | intel_dp->edp_dpcd); | |
50003939 JN |
3492 | } |
3493 | ||
bc5133d5 | 3494 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
e588fa18 | 3495 | yesno(intel_dp_source_supports_hbr2(intel_dp)), |
742f491d | 3496 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); |
06ea66b6 | 3497 | |
fc0f8e25 | 3498 | /* Intermediate frequency support */ |
86ee27b5 | 3499 | if (is_edp(intel_dp) && (intel_dp->edp_dpcd[0] >= 0x03)) { /* eDp v1.4 or higher */ |
94ca719e | 3500 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
ea2d8a42 VS |
3501 | int i; |
3502 | ||
fc0f8e25 SJ |
3503 | intel_dp_dpcd_read_wake(&intel_dp->aux, |
3504 | DP_SUPPORTED_LINK_RATES, | |
94ca719e VS |
3505 | sink_rates, |
3506 | sizeof(sink_rates)); | |
ea2d8a42 | 3507 | |
94ca719e VS |
3508 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
3509 | int val = le16_to_cpu(sink_rates[i]); | |
ea2d8a42 VS |
3510 | |
3511 | if (val == 0) | |
3512 | break; | |
3513 | ||
af77b974 SJ |
3514 | /* Value read is in kHz while drm clock is saved in deca-kHz */ |
3515 | intel_dp->sink_rates[i] = (val * 200) / 10; | |
ea2d8a42 | 3516 | } |
94ca719e | 3517 | intel_dp->num_sink_rates = i; |
fc0f8e25 | 3518 | } |
0336400e VS |
3519 | |
3520 | intel_dp_print_rates(intel_dp); | |
3521 | ||
edb39244 AJ |
3522 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
3523 | DP_DWN_STRM_PORT_PRESENT)) | |
3524 | return true; /* native DP sink */ | |
3525 | ||
3526 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
3527 | return true; /* no per-port downstream info */ | |
3528 | ||
9d1a1031 JN |
3529 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
3530 | intel_dp->downstream_ports, | |
3531 | DP_MAX_DOWNSTREAM_PORTS) < 0) | |
edb39244 AJ |
3532 | return false; /* downstream port status fetch failed */ |
3533 | ||
3534 | return true; | |
92fd8fd1 KP |
3535 | } |
3536 | ||
0d198328 AJ |
3537 | static void |
3538 | intel_dp_probe_oui(struct intel_dp *intel_dp) | |
3539 | { | |
3540 | u8 buf[3]; | |
3541 | ||
3542 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) | |
3543 | return; | |
3544 | ||
9d1a1031 | 3545 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
0d198328 AJ |
3546 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
3547 | buf[0], buf[1], buf[2]); | |
3548 | ||
9d1a1031 | 3549 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
0d198328 AJ |
3550 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
3551 | buf[0], buf[1], buf[2]); | |
3552 | } | |
3553 | ||
0e32b39c DA |
3554 | static bool |
3555 | intel_dp_probe_mst(struct intel_dp *intel_dp) | |
3556 | { | |
3557 | u8 buf[1]; | |
3558 | ||
7cc96139 NS |
3559 | if (!i915.enable_dp_mst) |
3560 | return false; | |
3561 | ||
0e32b39c DA |
3562 | if (!intel_dp->can_mst) |
3563 | return false; | |
3564 | ||
3565 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) | |
3566 | return false; | |
3567 | ||
0e32b39c DA |
3568 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) { |
3569 | if (buf[0] & DP_MST_CAP) { | |
3570 | DRM_DEBUG_KMS("Sink is MST capable\n"); | |
3571 | intel_dp->is_mst = true; | |
3572 | } else { | |
3573 | DRM_DEBUG_KMS("Sink is not MST capable\n"); | |
3574 | intel_dp->is_mst = false; | |
3575 | } | |
3576 | } | |
0e32b39c DA |
3577 | |
3578 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | |
3579 | return intel_dp->is_mst; | |
3580 | } | |
3581 | ||
e5a1cab5 | 3582 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
d2e216d0 | 3583 | { |
082dcc7c | 3584 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
d72f9d91 | 3585 | struct drm_device *dev = dig_port->base.base.dev; |
082dcc7c | 3586 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
ad9dc91b | 3587 | u8 buf; |
e5a1cab5 | 3588 | int ret = 0; |
c6297843 RV |
3589 | int count = 0; |
3590 | int attempts = 10; | |
d2e216d0 | 3591 | |
082dcc7c RV |
3592 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
3593 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); | |
e5a1cab5 RV |
3594 | ret = -EIO; |
3595 | goto out; | |
4373f0f2 PZ |
3596 | } |
3597 | ||
082dcc7c | 3598 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
e5a1cab5 | 3599 | buf & ~DP_TEST_SINK_START) < 0) { |
082dcc7c | 3600 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
e5a1cab5 RV |
3601 | ret = -EIO; |
3602 | goto out; | |
3603 | } | |
d2e216d0 | 3604 | |
c6297843 RV |
3605 | do { |
3606 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
3607 | ||
3608 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
3609 | DP_TEST_SINK_MISC, &buf) < 0) { | |
3610 | ret = -EIO; | |
3611 | goto out; | |
3612 | } | |
3613 | count = buf & DP_TEST_COUNT_MASK; | |
3614 | } while (--attempts && count); | |
3615 | ||
3616 | if (attempts == 0) { | |
dc5a9037 | 3617 | DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); |
c6297843 RV |
3618 | ret = -ETIMEDOUT; |
3619 | } | |
3620 | ||
e5a1cab5 | 3621 | out: |
082dcc7c | 3622 | hsw_enable_ips(intel_crtc); |
e5a1cab5 | 3623 | return ret; |
082dcc7c RV |
3624 | } |
3625 | ||
3626 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) | |
3627 | { | |
3628 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
d72f9d91 | 3629 | struct drm_device *dev = dig_port->base.base.dev; |
082dcc7c RV |
3630 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
3631 | u8 buf; | |
e5a1cab5 RV |
3632 | int ret; |
3633 | ||
082dcc7c RV |
3634 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
3635 | return -EIO; | |
3636 | ||
3637 | if (!(buf & DP_TEST_CRC_SUPPORTED)) | |
3638 | return -ENOTTY; | |
3639 | ||
3640 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) | |
3641 | return -EIO; | |
3642 | ||
6d8175da RV |
3643 | if (buf & DP_TEST_SINK_START) { |
3644 | ret = intel_dp_sink_crc_stop(intel_dp); | |
3645 | if (ret) | |
3646 | return ret; | |
3647 | } | |
3648 | ||
082dcc7c | 3649 | hsw_disable_ips(intel_crtc); |
1dda5f93 | 3650 | |
9d1a1031 | 3651 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
082dcc7c RV |
3652 | buf | DP_TEST_SINK_START) < 0) { |
3653 | hsw_enable_ips(intel_crtc); | |
3654 | return -EIO; | |
4373f0f2 PZ |
3655 | } |
3656 | ||
d72f9d91 | 3657 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
082dcc7c RV |
3658 | return 0; |
3659 | } | |
3660 | ||
3661 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) | |
3662 | { | |
3663 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
3664 | struct drm_device *dev = dig_port->base.base.dev; | |
3665 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); | |
3666 | u8 buf; | |
621d4c76 | 3667 | int count, ret; |
082dcc7c | 3668 | int attempts = 6; |
082dcc7c RV |
3669 | |
3670 | ret = intel_dp_sink_crc_start(intel_dp); | |
3671 | if (ret) | |
3672 | return ret; | |
3673 | ||
ad9dc91b | 3674 | do { |
621d4c76 RV |
3675 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
3676 | ||
1dda5f93 | 3677 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4373f0f2 PZ |
3678 | DP_TEST_SINK_MISC, &buf) < 0) { |
3679 | ret = -EIO; | |
afe0d67e | 3680 | goto stop; |
4373f0f2 | 3681 | } |
621d4c76 | 3682 | count = buf & DP_TEST_COUNT_MASK; |
aabc95dc | 3683 | |
7e38eeff | 3684 | } while (--attempts && count == 0); |
ad9dc91b RV |
3685 | |
3686 | if (attempts == 0) { | |
7e38eeff RV |
3687 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
3688 | ret = -ETIMEDOUT; | |
3689 | goto stop; | |
3690 | } | |
3691 | ||
3692 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { | |
3693 | ret = -EIO; | |
3694 | goto stop; | |
ad9dc91b | 3695 | } |
d2e216d0 | 3696 | |
afe0d67e | 3697 | stop: |
082dcc7c | 3698 | intel_dp_sink_crc_stop(intel_dp); |
4373f0f2 | 3699 | return ret; |
d2e216d0 RV |
3700 | } |
3701 | ||
a60f0e38 JB |
3702 | static bool |
3703 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3704 | { | |
9d1a1031 JN |
3705 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
3706 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
3707 | sink_irq_vector, 1) == 1; | |
a60f0e38 JB |
3708 | } |
3709 | ||
0e32b39c DA |
3710 | static bool |
3711 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3712 | { | |
3713 | int ret; | |
3714 | ||
3715 | ret = intel_dp_dpcd_read_wake(&intel_dp->aux, | |
3716 | DP_SINK_COUNT_ESI, | |
3717 | sink_irq_vector, 14); | |
3718 | if (ret != 14) | |
3719 | return false; | |
3720 | ||
3721 | return true; | |
3722 | } | |
3723 | ||
c5d5ab7a TP |
3724 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
3725 | { | |
3726 | uint8_t test_result = DP_TEST_ACK; | |
3727 | return test_result; | |
3728 | } | |
3729 | ||
3730 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) | |
3731 | { | |
3732 | uint8_t test_result = DP_TEST_NAK; | |
3733 | return test_result; | |
3734 | } | |
3735 | ||
3736 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) | |
a60f0e38 | 3737 | { |
c5d5ab7a | 3738 | uint8_t test_result = DP_TEST_NAK; |
559be30c TP |
3739 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
3740 | struct drm_connector *connector = &intel_connector->base; | |
3741 | ||
3742 | if (intel_connector->detect_edid == NULL || | |
ac6f2e29 | 3743 | connector->edid_corrupt || |
559be30c TP |
3744 | intel_dp->aux.i2c_defer_count > 6) { |
3745 | /* Check EDID read for NACKs, DEFERs and corruption | |
3746 | * (DP CTS 1.2 Core r1.1) | |
3747 | * 4.2.2.4 : Failed EDID read, I2C_NAK | |
3748 | * 4.2.2.5 : Failed EDID read, I2C_DEFER | |
3749 | * 4.2.2.6 : EDID corruption detected | |
3750 | * Use failsafe mode for all cases | |
3751 | */ | |
3752 | if (intel_dp->aux.i2c_nack_count > 0 || | |
3753 | intel_dp->aux.i2c_defer_count > 0) | |
3754 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", | |
3755 | intel_dp->aux.i2c_nack_count, | |
3756 | intel_dp->aux.i2c_defer_count); | |
3757 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; | |
3758 | } else { | |
f79b468e TS |
3759 | struct edid *block = intel_connector->detect_edid; |
3760 | ||
3761 | /* We have to write the checksum | |
3762 | * of the last block read | |
3763 | */ | |
3764 | block += intel_connector->detect_edid->extensions; | |
3765 | ||
559be30c TP |
3766 | if (!drm_dp_dpcd_write(&intel_dp->aux, |
3767 | DP_TEST_EDID_CHECKSUM, | |
f79b468e | 3768 | &block->checksum, |
5a1cc655 | 3769 | 1)) |
559be30c TP |
3770 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
3771 | ||
3772 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; | |
3773 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; | |
3774 | } | |
3775 | ||
3776 | /* Set test active flag here so userspace doesn't interrupt things */ | |
3777 | intel_dp->compliance_test_active = 1; | |
3778 | ||
c5d5ab7a TP |
3779 | return test_result; |
3780 | } | |
3781 | ||
3782 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) | |
a60f0e38 | 3783 | { |
c5d5ab7a TP |
3784 | uint8_t test_result = DP_TEST_NAK; |
3785 | return test_result; | |
3786 | } | |
3787 | ||
3788 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
3789 | { | |
3790 | uint8_t response = DP_TEST_NAK; | |
3791 | uint8_t rxdata = 0; | |
3792 | int status = 0; | |
3793 | ||
c5d5ab7a TP |
3794 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); |
3795 | if (status <= 0) { | |
3796 | DRM_DEBUG_KMS("Could not read test request from sink\n"); | |
3797 | goto update_status; | |
3798 | } | |
3799 | ||
3800 | switch (rxdata) { | |
3801 | case DP_TEST_LINK_TRAINING: | |
3802 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); | |
3803 | intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; | |
3804 | response = intel_dp_autotest_link_training(intel_dp); | |
3805 | break; | |
3806 | case DP_TEST_LINK_VIDEO_PATTERN: | |
3807 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); | |
3808 | intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; | |
3809 | response = intel_dp_autotest_video_pattern(intel_dp); | |
3810 | break; | |
3811 | case DP_TEST_LINK_EDID_READ: | |
3812 | DRM_DEBUG_KMS("EDID test requested\n"); | |
3813 | intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; | |
3814 | response = intel_dp_autotest_edid(intel_dp); | |
3815 | break; | |
3816 | case DP_TEST_LINK_PHY_TEST_PATTERN: | |
3817 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); | |
3818 | intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; | |
3819 | response = intel_dp_autotest_phy_pattern(intel_dp); | |
3820 | break; | |
3821 | default: | |
3822 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); | |
3823 | break; | |
3824 | } | |
3825 | ||
3826 | update_status: | |
3827 | status = drm_dp_dpcd_write(&intel_dp->aux, | |
3828 | DP_TEST_RESPONSE, | |
3829 | &response, 1); | |
3830 | if (status <= 0) | |
3831 | DRM_DEBUG_KMS("Could not write test response to sink\n"); | |
a60f0e38 JB |
3832 | } |
3833 | ||
0e32b39c DA |
3834 | static int |
3835 | intel_dp_check_mst_status(struct intel_dp *intel_dp) | |
3836 | { | |
3837 | bool bret; | |
3838 | ||
3839 | if (intel_dp->is_mst) { | |
3840 | u8 esi[16] = { 0 }; | |
3841 | int ret = 0; | |
3842 | int retry; | |
3843 | bool handled; | |
3844 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
3845 | go_again: | |
3846 | if (bret == true) { | |
3847 | ||
3848 | /* check link status - esi[10] = 0x200c */ | |
90a6b7b0 | 3849 | if (intel_dp->active_mst_links && |
901c2daf | 3850 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
0e32b39c DA |
3851 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
3852 | intel_dp_start_link_train(intel_dp); | |
0e32b39c DA |
3853 | intel_dp_stop_link_train(intel_dp); |
3854 | } | |
3855 | ||
6f34cc39 | 3856 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
0e32b39c DA |
3857 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
3858 | ||
3859 | if (handled) { | |
3860 | for (retry = 0; retry < 3; retry++) { | |
3861 | int wret; | |
3862 | wret = drm_dp_dpcd_write(&intel_dp->aux, | |
3863 | DP_SINK_COUNT_ESI+1, | |
3864 | &esi[1], 3); | |
3865 | if (wret == 3) { | |
3866 | break; | |
3867 | } | |
3868 | } | |
3869 | ||
3870 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
3871 | if (bret == true) { | |
6f34cc39 | 3872 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
0e32b39c DA |
3873 | goto go_again; |
3874 | } | |
3875 | } else | |
3876 | ret = 0; | |
3877 | ||
3878 | return ret; | |
3879 | } else { | |
3880 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3881 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); | |
3882 | intel_dp->is_mst = false; | |
3883 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | |
3884 | /* send a hotplug event */ | |
3885 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); | |
3886 | } | |
3887 | } | |
3888 | return -EINVAL; | |
3889 | } | |
3890 | ||
5c9114d0 SS |
3891 | static void |
3892 | intel_dp_check_link_status(struct intel_dp *intel_dp) | |
3893 | { | |
3894 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; | |
3895 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
3896 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
3897 | ||
3898 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); | |
3899 | ||
3900 | if (!intel_dp_get_link_status(intel_dp, link_status)) { | |
3901 | DRM_ERROR("Failed to get link status\n"); | |
3902 | return; | |
3903 | } | |
3904 | ||
3905 | if (!intel_encoder->base.crtc) | |
3906 | return; | |
3907 | ||
3908 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) | |
3909 | return; | |
3910 | ||
3911 | /* if link training is requested we should perform it always */ | |
3912 | if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) || | |
3913 | (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { | |
3914 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", | |
3915 | intel_encoder->base.name); | |
3916 | intel_dp_start_link_train(intel_dp); | |
3917 | intel_dp_stop_link_train(intel_dp); | |
3918 | } | |
3919 | } | |
3920 | ||
a4fc5ed6 KP |
3921 | /* |
3922 | * According to DP spec | |
3923 | * 5.1.2: | |
3924 | * 1. Read DPCD | |
3925 | * 2. Configure link according to Receiver Capabilities | |
3926 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
3927 | * 4. Check link status on receipt of hot-plug interrupt | |
39ff747b SS |
3928 | * |
3929 | * intel_dp_short_pulse - handles short pulse interrupts | |
3930 | * when full detection is not required. | |
3931 | * Returns %true if short pulse is handled and full detection | |
3932 | * is NOT required and %false otherwise. | |
a4fc5ed6 | 3933 | */ |
39ff747b | 3934 | static bool |
5c9114d0 | 3935 | intel_dp_short_pulse(struct intel_dp *intel_dp) |
a4fc5ed6 | 3936 | { |
5b215bcf | 3937 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
a60f0e38 | 3938 | u8 sink_irq_vector; |
39ff747b SS |
3939 | u8 old_sink_count = intel_dp->sink_count; |
3940 | bool ret; | |
5b215bcf | 3941 | |
4df6960e SS |
3942 | /* |
3943 | * Clearing compliance test variables to allow capturing | |
3944 | * of values for next automated test request. | |
3945 | */ | |
3946 | intel_dp->compliance_test_active = 0; | |
3947 | intel_dp->compliance_test_type = 0; | |
3948 | intel_dp->compliance_test_data = 0; | |
3949 | ||
39ff747b SS |
3950 | /* |
3951 | * Now read the DPCD to see if it's actually running | |
3952 | * If the current value of sink count doesn't match with | |
3953 | * the value that was stored earlier or dpcd read failed | |
3954 | * we need to do full detection | |
3955 | */ | |
3956 | ret = intel_dp_get_dpcd(intel_dp); | |
3957 | ||
3958 | if ((old_sink_count != intel_dp->sink_count) || !ret) { | |
3959 | /* No need to proceed if we are going to do full detect */ | |
3960 | return false; | |
59cd09e1 JB |
3961 | } |
3962 | ||
a60f0e38 JB |
3963 | /* Try to read the source of the interrupt */ |
3964 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
3965 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { | |
3966 | /* Clear interrupt source */ | |
9d1a1031 JN |
3967 | drm_dp_dpcd_writeb(&intel_dp->aux, |
3968 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
3969 | sink_irq_vector); | |
a60f0e38 JB |
3970 | |
3971 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
09b1eb13 | 3972 | DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); |
a60f0e38 JB |
3973 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
3974 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
3975 | } | |
3976 | ||
5c9114d0 SS |
3977 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
3978 | intel_dp_check_link_status(intel_dp); | |
3979 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
39ff747b SS |
3980 | |
3981 | return true; | |
a4fc5ed6 | 3982 | } |
a4fc5ed6 | 3983 | |
caf9ab24 | 3984 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 3985 | static enum drm_connector_status |
26d61aad | 3986 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 3987 | { |
caf9ab24 | 3988 | uint8_t *dpcd = intel_dp->dpcd; |
caf9ab24 AJ |
3989 | uint8_t type; |
3990 | ||
3991 | if (!intel_dp_get_dpcd(intel_dp)) | |
3992 | return connector_status_disconnected; | |
3993 | ||
1034ce70 SS |
3994 | if (is_edp(intel_dp)) |
3995 | return connector_status_connected; | |
3996 | ||
caf9ab24 AJ |
3997 | /* if there's no downstream port, we're done */ |
3998 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) | |
26d61aad | 3999 | return connector_status_connected; |
caf9ab24 AJ |
4000 | |
4001 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
c9ff160b JN |
4002 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4003 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | |
9d1a1031 | 4004 | |
30d9aa42 SS |
4005 | return intel_dp->sink_count ? |
4006 | connector_status_connected : connector_status_disconnected; | |
caf9ab24 AJ |
4007 | } |
4008 | ||
4009 | /* If no HPD, poke DDC gently */ | |
0b99836f | 4010 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
26d61aad | 4011 | return connector_status_connected; |
caf9ab24 AJ |
4012 | |
4013 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
4014 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
4015 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
4016 | if (type == DP_DS_PORT_TYPE_VGA || | |
4017 | type == DP_DS_PORT_TYPE_NON_EDID) | |
4018 | return connector_status_unknown; | |
4019 | } else { | |
4020 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
4021 | DP_DWN_STRM_PORT_TYPE_MASK; | |
4022 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
4023 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
4024 | return connector_status_unknown; | |
4025 | } | |
caf9ab24 AJ |
4026 | |
4027 | /* Anything else is out of spec, warn and ignore */ | |
4028 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); | |
26d61aad | 4029 | return connector_status_disconnected; |
71ba9000 AJ |
4030 | } |
4031 | ||
d410b56d CW |
4032 | static enum drm_connector_status |
4033 | edp_detect(struct intel_dp *intel_dp) | |
4034 | { | |
4035 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
4036 | enum drm_connector_status status; | |
4037 | ||
4038 | status = intel_panel_detect(dev); | |
4039 | if (status == connector_status_unknown) | |
4040 | status = connector_status_connected; | |
4041 | ||
4042 | return status; | |
4043 | } | |
4044 | ||
b93433cc JN |
4045 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
4046 | struct intel_digital_port *port) | |
5eb08b69 | 4047 | { |
b93433cc | 4048 | u32 bit; |
01cb9ea6 | 4049 | |
0df53b77 JN |
4050 | switch (port->port) { |
4051 | case PORT_A: | |
4052 | return true; | |
4053 | case PORT_B: | |
4054 | bit = SDE_PORTB_HOTPLUG; | |
4055 | break; | |
4056 | case PORT_C: | |
4057 | bit = SDE_PORTC_HOTPLUG; | |
4058 | break; | |
4059 | case PORT_D: | |
4060 | bit = SDE_PORTD_HOTPLUG; | |
4061 | break; | |
4062 | default: | |
4063 | MISSING_CASE(port->port); | |
4064 | return false; | |
4065 | } | |
4066 | ||
4067 | return I915_READ(SDEISR) & bit; | |
4068 | } | |
4069 | ||
4070 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, | |
4071 | struct intel_digital_port *port) | |
4072 | { | |
4073 | u32 bit; | |
4074 | ||
4075 | switch (port->port) { | |
4076 | case PORT_A: | |
4077 | return true; | |
4078 | case PORT_B: | |
4079 | bit = SDE_PORTB_HOTPLUG_CPT; | |
4080 | break; | |
4081 | case PORT_C: | |
4082 | bit = SDE_PORTC_HOTPLUG_CPT; | |
4083 | break; | |
4084 | case PORT_D: | |
4085 | bit = SDE_PORTD_HOTPLUG_CPT; | |
4086 | break; | |
a78695d3 JN |
4087 | case PORT_E: |
4088 | bit = SDE_PORTE_HOTPLUG_SPT; | |
4089 | break; | |
0df53b77 JN |
4090 | default: |
4091 | MISSING_CASE(port->port); | |
4092 | return false; | |
b93433cc | 4093 | } |
1b469639 | 4094 | |
b93433cc | 4095 | return I915_READ(SDEISR) & bit; |
5eb08b69 ZW |
4096 | } |
4097 | ||
7e66bcf2 | 4098 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
1d245987 | 4099 | struct intel_digital_port *port) |
a4fc5ed6 | 4100 | { |
9642c81c | 4101 | u32 bit; |
5eb08b69 | 4102 | |
9642c81c JN |
4103 | switch (port->port) { |
4104 | case PORT_B: | |
4105 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; | |
4106 | break; | |
4107 | case PORT_C: | |
4108 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; | |
4109 | break; | |
4110 | case PORT_D: | |
4111 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; | |
4112 | break; | |
4113 | default: | |
4114 | MISSING_CASE(port->port); | |
4115 | return false; | |
4116 | } | |
4117 | ||
4118 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | |
4119 | } | |
4120 | ||
0780cd36 VS |
4121 | static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, |
4122 | struct intel_digital_port *port) | |
9642c81c JN |
4123 | { |
4124 | u32 bit; | |
4125 | ||
4126 | switch (port->port) { | |
4127 | case PORT_B: | |
0780cd36 | 4128 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4129 | break; |
4130 | case PORT_C: | |
0780cd36 | 4131 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4132 | break; |
4133 | case PORT_D: | |
0780cd36 | 4134 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4135 | break; |
4136 | default: | |
4137 | MISSING_CASE(port->port); | |
4138 | return false; | |
a4fc5ed6 KP |
4139 | } |
4140 | ||
1d245987 | 4141 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
2a592bec DA |
4142 | } |
4143 | ||
e464bfde | 4144 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
e2ec35a5 | 4145 | struct intel_digital_port *intel_dig_port) |
e464bfde | 4146 | { |
e2ec35a5 SJ |
4147 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4148 | enum port port; | |
e464bfde JN |
4149 | u32 bit; |
4150 | ||
e2ec35a5 SJ |
4151 | intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); |
4152 | switch (port) { | |
e464bfde JN |
4153 | case PORT_A: |
4154 | bit = BXT_DE_PORT_HP_DDIA; | |
4155 | break; | |
4156 | case PORT_B: | |
4157 | bit = BXT_DE_PORT_HP_DDIB; | |
4158 | break; | |
4159 | case PORT_C: | |
4160 | bit = BXT_DE_PORT_HP_DDIC; | |
4161 | break; | |
4162 | default: | |
e2ec35a5 | 4163 | MISSING_CASE(port); |
e464bfde JN |
4164 | return false; |
4165 | } | |
4166 | ||
4167 | return I915_READ(GEN8_DE_PORT_ISR) & bit; | |
4168 | } | |
4169 | ||
7e66bcf2 JN |
4170 | /* |
4171 | * intel_digital_port_connected - is the specified port connected? | |
4172 | * @dev_priv: i915 private structure | |
4173 | * @port: the port to test | |
4174 | * | |
4175 | * Return %true if @port is connected, %false otherwise. | |
4176 | */ | |
237ed86c | 4177 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
7e66bcf2 JN |
4178 | struct intel_digital_port *port) |
4179 | { | |
0df53b77 | 4180 | if (HAS_PCH_IBX(dev_priv)) |
7e66bcf2 | 4181 | return ibx_digital_port_connected(dev_priv, port); |
22824fac | 4182 | else if (HAS_PCH_SPLIT(dev_priv)) |
0df53b77 | 4183 | return cpt_digital_port_connected(dev_priv, port); |
e464bfde JN |
4184 | else if (IS_BROXTON(dev_priv)) |
4185 | return bxt_digital_port_connected(dev_priv, port); | |
0780cd36 VS |
4186 | else if (IS_GM45(dev_priv)) |
4187 | return gm45_digital_port_connected(dev_priv, port); | |
7e66bcf2 JN |
4188 | else |
4189 | return g4x_digital_port_connected(dev_priv, port); | |
4190 | } | |
4191 | ||
8c241fef | 4192 | static struct edid * |
beb60608 | 4193 | intel_dp_get_edid(struct intel_dp *intel_dp) |
8c241fef | 4194 | { |
beb60608 | 4195 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
d6f24d0f | 4196 | |
9cd300e0 JN |
4197 | /* use cached edid if we have one */ |
4198 | if (intel_connector->edid) { | |
9cd300e0 JN |
4199 | /* invalid edid */ |
4200 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
4201 | return NULL; |
4202 | ||
55e9edeb | 4203 | return drm_edid_duplicate(intel_connector->edid); |
beb60608 CW |
4204 | } else |
4205 | return drm_get_edid(&intel_connector->base, | |
4206 | &intel_dp->aux.ddc); | |
4207 | } | |
8c241fef | 4208 | |
beb60608 CW |
4209 | static void |
4210 | intel_dp_set_edid(struct intel_dp *intel_dp) | |
4211 | { | |
4212 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
4213 | struct edid *edid; | |
8c241fef | 4214 | |
f21a2198 | 4215 | intel_dp_unset_edid(intel_dp); |
beb60608 CW |
4216 | edid = intel_dp_get_edid(intel_dp); |
4217 | intel_connector->detect_edid = edid; | |
4218 | ||
4219 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) | |
4220 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; | |
4221 | else | |
4222 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
8c241fef KP |
4223 | } |
4224 | ||
beb60608 CW |
4225 | static void |
4226 | intel_dp_unset_edid(struct intel_dp *intel_dp) | |
8c241fef | 4227 | { |
beb60608 | 4228 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
8c241fef | 4229 | |
beb60608 CW |
4230 | kfree(intel_connector->detect_edid); |
4231 | intel_connector->detect_edid = NULL; | |
9cd300e0 | 4232 | |
beb60608 CW |
4233 | intel_dp->has_audio = false; |
4234 | } | |
d6f24d0f | 4235 | |
f21a2198 SS |
4236 | static void |
4237 | intel_dp_long_pulse(struct intel_connector *intel_connector) | |
a9756bb5 | 4238 | { |
f21a2198 | 4239 | struct drm_connector *connector = &intel_connector->base; |
a9756bb5 | 4240 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
d63885da PZ |
4241 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4242 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fa90ecef | 4243 | struct drm_device *dev = connector->dev; |
a9756bb5 | 4244 | enum drm_connector_status status; |
671dedd2 | 4245 | enum intel_display_power_domain power_domain; |
0e32b39c | 4246 | bool ret; |
09b1eb13 | 4247 | u8 sink_irq_vector; |
a9756bb5 | 4248 | |
25f78f58 VS |
4249 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4250 | intel_display_power_get(to_i915(dev), power_domain); | |
a9756bb5 | 4251 | |
d410b56d CW |
4252 | /* Can't disconnect eDP, but you can close the lid... */ |
4253 | if (is_edp(intel_dp)) | |
4254 | status = edp_detect(intel_dp); | |
c555a81d ACO |
4255 | else if (intel_digital_port_connected(to_i915(dev), |
4256 | dp_to_dig_port(intel_dp))) | |
4257 | status = intel_dp_detect_dpcd(intel_dp); | |
a9756bb5 | 4258 | else |
c555a81d ACO |
4259 | status = connector_status_disconnected; |
4260 | ||
4df6960e SS |
4261 | if (status != connector_status_connected) { |
4262 | intel_dp->compliance_test_active = 0; | |
4263 | intel_dp->compliance_test_type = 0; | |
4264 | intel_dp->compliance_test_data = 0; | |
4265 | ||
0e505a08 | 4266 | if (intel_dp->is_mst) { |
4267 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
4268 | intel_dp->is_mst, | |
4269 | intel_dp->mst_mgr.mst_state); | |
4270 | intel_dp->is_mst = false; | |
4271 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
4272 | intel_dp->is_mst); | |
4273 | } | |
4274 | ||
c8c8fb33 | 4275 | goto out; |
4df6960e | 4276 | } |
a9756bb5 | 4277 | |
f21a2198 SS |
4278 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
4279 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
4280 | ||
0d198328 AJ |
4281 | intel_dp_probe_oui(intel_dp); |
4282 | ||
0e32b39c DA |
4283 | ret = intel_dp_probe_mst(intel_dp); |
4284 | if (ret) { | |
f21a2198 SS |
4285 | /* |
4286 | * If we are in MST mode then this connector | |
4287 | * won't appear connected or have anything | |
4288 | * with EDID on it | |
4289 | */ | |
0e32b39c DA |
4290 | status = connector_status_disconnected; |
4291 | goto out; | |
7d23e3c3 SS |
4292 | } else if (connector->status == connector_status_connected) { |
4293 | /* | |
4294 | * If display was connected already and is still connected | |
4295 | * check links status, there has been known issues of | |
4296 | * link loss triggerring long pulse!!!! | |
4297 | */ | |
4298 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); | |
4299 | intel_dp_check_link_status(intel_dp); | |
4300 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
4301 | goto out; | |
0e32b39c DA |
4302 | } |
4303 | ||
4df6960e SS |
4304 | /* |
4305 | * Clearing NACK and defer counts to get their exact values | |
4306 | * while reading EDID which are required by Compliance tests | |
4307 | * 4.2.2.4 and 4.2.2.5 | |
4308 | */ | |
4309 | intel_dp->aux.i2c_nack_count = 0; | |
4310 | intel_dp->aux.i2c_defer_count = 0; | |
4311 | ||
beb60608 | 4312 | intel_dp_set_edid(intel_dp); |
a9756bb5 | 4313 | |
c8c8fb33 | 4314 | status = connector_status_connected; |
7d23e3c3 | 4315 | intel_dp->detect_done = true; |
c8c8fb33 | 4316 | |
09b1eb13 TP |
4317 | /* Try to read the source of the interrupt */ |
4318 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
4319 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { | |
4320 | /* Clear interrupt source */ | |
4321 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
4322 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4323 | sink_irq_vector); | |
4324 | ||
4325 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
4326 | intel_dp_handle_test_request(intel_dp); | |
4327 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
4328 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4329 | } | |
4330 | ||
c8c8fb33 | 4331 | out: |
0e505a08 | 4332 | if ((status != connector_status_connected) && |
4333 | (intel_dp->is_mst == false)) | |
f21a2198 | 4334 | intel_dp_unset_edid(intel_dp); |
7d23e3c3 | 4335 | |
25f78f58 | 4336 | intel_display_power_put(to_i915(dev), power_domain); |
f21a2198 SS |
4337 | return; |
4338 | } | |
4339 | ||
4340 | static enum drm_connector_status | |
4341 | intel_dp_detect(struct drm_connector *connector, bool force) | |
4342 | { | |
4343 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
4344 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4345 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
4346 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4347 | ||
4348 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4349 | connector->base.id, connector->name); | |
4350 | ||
4351 | if (intel_dp->is_mst) { | |
4352 | /* MST devices are disconnected from a monitor POV */ | |
4353 | intel_dp_unset_edid(intel_dp); | |
4354 | if (intel_encoder->type != INTEL_OUTPUT_EDP) | |
4355 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
4356 | return connector_status_disconnected; | |
4357 | } | |
4358 | ||
7d23e3c3 SS |
4359 | /* If full detect is not performed yet, do a full detect */ |
4360 | if (!intel_dp->detect_done) | |
4361 | intel_dp_long_pulse(intel_dp->attached_connector); | |
4362 | ||
4363 | intel_dp->detect_done = false; | |
f21a2198 SS |
4364 | |
4365 | if (intel_connector->detect_edid) | |
4366 | return connector_status_connected; | |
4367 | else | |
4368 | return connector_status_disconnected; | |
a4fc5ed6 KP |
4369 | } |
4370 | ||
beb60608 CW |
4371 | static void |
4372 | intel_dp_force(struct drm_connector *connector) | |
a4fc5ed6 | 4373 | { |
df0e9248 | 4374 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
beb60608 | 4375 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
25f78f58 | 4376 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
671dedd2 | 4377 | enum intel_display_power_domain power_domain; |
a4fc5ed6 | 4378 | |
beb60608 CW |
4379 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4380 | connector->base.id, connector->name); | |
4381 | intel_dp_unset_edid(intel_dp); | |
a4fc5ed6 | 4382 | |
beb60608 CW |
4383 | if (connector->status != connector_status_connected) |
4384 | return; | |
671dedd2 | 4385 | |
25f78f58 VS |
4386 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4387 | intel_display_power_get(dev_priv, power_domain); | |
beb60608 CW |
4388 | |
4389 | intel_dp_set_edid(intel_dp); | |
4390 | ||
25f78f58 | 4391 | intel_display_power_put(dev_priv, power_domain); |
beb60608 CW |
4392 | |
4393 | if (intel_encoder->type != INTEL_OUTPUT_EDP) | |
4394 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
4395 | } | |
4396 | ||
4397 | static int intel_dp_get_modes(struct drm_connector *connector) | |
4398 | { | |
4399 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4400 | struct edid *edid; | |
4401 | ||
4402 | edid = intel_connector->detect_edid; | |
4403 | if (edid) { | |
4404 | int ret = intel_connector_update_modes(connector, edid); | |
4405 | if (ret) | |
4406 | return ret; | |
4407 | } | |
32f9d658 | 4408 | |
f8779fda | 4409 | /* if eDP has no EDID, fall back to fixed mode */ |
beb60608 CW |
4410 | if (is_edp(intel_attached_dp(connector)) && |
4411 | intel_connector->panel.fixed_mode) { | |
f8779fda | 4412 | struct drm_display_mode *mode; |
beb60608 CW |
4413 | |
4414 | mode = drm_mode_duplicate(connector->dev, | |
dd06f90e | 4415 | intel_connector->panel.fixed_mode); |
f8779fda | 4416 | if (mode) { |
32f9d658 ZW |
4417 | drm_mode_probed_add(connector, mode); |
4418 | return 1; | |
4419 | } | |
4420 | } | |
beb60608 | 4421 | |
32f9d658 | 4422 | return 0; |
a4fc5ed6 KP |
4423 | } |
4424 | ||
1aad7ac0 CW |
4425 | static bool |
4426 | intel_dp_detect_audio(struct drm_connector *connector) | |
4427 | { | |
1aad7ac0 | 4428 | bool has_audio = false; |
beb60608 | 4429 | struct edid *edid; |
1aad7ac0 | 4430 | |
beb60608 CW |
4431 | edid = to_intel_connector(connector)->detect_edid; |
4432 | if (edid) | |
1aad7ac0 | 4433 | has_audio = drm_detect_monitor_audio(edid); |
671dedd2 | 4434 | |
1aad7ac0 CW |
4435 | return has_audio; |
4436 | } | |
4437 | ||
f684960e CW |
4438 | static int |
4439 | intel_dp_set_property(struct drm_connector *connector, | |
4440 | struct drm_property *property, | |
4441 | uint64_t val) | |
4442 | { | |
e953fd7b | 4443 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
53b41837 | 4444 | struct intel_connector *intel_connector = to_intel_connector(connector); |
da63a9f2 PZ |
4445 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
4446 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
f684960e CW |
4447 | int ret; |
4448 | ||
662595df | 4449 | ret = drm_object_property_set_value(&connector->base, property, val); |
f684960e CW |
4450 | if (ret) |
4451 | return ret; | |
4452 | ||
3f43c48d | 4453 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
4454 | int i = val; |
4455 | bool has_audio; | |
4456 | ||
4457 | if (i == intel_dp->force_audio) | |
f684960e CW |
4458 | return 0; |
4459 | ||
1aad7ac0 | 4460 | intel_dp->force_audio = i; |
f684960e | 4461 | |
c3e5f67b | 4462 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
4463 | has_audio = intel_dp_detect_audio(connector); |
4464 | else | |
c3e5f67b | 4465 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 CW |
4466 | |
4467 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
4468 | return 0; |
4469 | ||
1aad7ac0 | 4470 | intel_dp->has_audio = has_audio; |
f684960e CW |
4471 | goto done; |
4472 | } | |
4473 | ||
e953fd7b | 4474 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 | 4475 | bool old_auto = intel_dp->color_range_auto; |
0f2a2a75 | 4476 | bool old_range = intel_dp->limited_color_range; |
ae4edb80 | 4477 | |
55bc60db VS |
4478 | switch (val) { |
4479 | case INTEL_BROADCAST_RGB_AUTO: | |
4480 | intel_dp->color_range_auto = true; | |
4481 | break; | |
4482 | case INTEL_BROADCAST_RGB_FULL: | |
4483 | intel_dp->color_range_auto = false; | |
0f2a2a75 | 4484 | intel_dp->limited_color_range = false; |
55bc60db VS |
4485 | break; |
4486 | case INTEL_BROADCAST_RGB_LIMITED: | |
4487 | intel_dp->color_range_auto = false; | |
0f2a2a75 | 4488 | intel_dp->limited_color_range = true; |
55bc60db VS |
4489 | break; |
4490 | default: | |
4491 | return -EINVAL; | |
4492 | } | |
ae4edb80 DV |
4493 | |
4494 | if (old_auto == intel_dp->color_range_auto && | |
0f2a2a75 | 4495 | old_range == intel_dp->limited_color_range) |
ae4edb80 DV |
4496 | return 0; |
4497 | ||
e953fd7b CW |
4498 | goto done; |
4499 | } | |
4500 | ||
53b41837 YN |
4501 | if (is_edp(intel_dp) && |
4502 | property == connector->dev->mode_config.scaling_mode_property) { | |
4503 | if (val == DRM_MODE_SCALE_NONE) { | |
4504 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
4505 | return -EINVAL; | |
4506 | } | |
234126c6 VS |
4507 | if (HAS_GMCH_DISPLAY(dev_priv) && |
4508 | val == DRM_MODE_SCALE_CENTER) { | |
4509 | DRM_DEBUG_KMS("centering not supported\n"); | |
4510 | return -EINVAL; | |
4511 | } | |
53b41837 YN |
4512 | |
4513 | if (intel_connector->panel.fitting_mode == val) { | |
4514 | /* the eDP scaling property is not changed */ | |
4515 | return 0; | |
4516 | } | |
4517 | intel_connector->panel.fitting_mode = val; | |
4518 | ||
4519 | goto done; | |
4520 | } | |
4521 | ||
f684960e CW |
4522 | return -EINVAL; |
4523 | ||
4524 | done: | |
c0c36b94 CW |
4525 | if (intel_encoder->base.crtc) |
4526 | intel_crtc_restore_mode(intel_encoder->base.crtc); | |
f684960e CW |
4527 | |
4528 | return 0; | |
4529 | } | |
4530 | ||
a4fc5ed6 | 4531 | static void |
73845adf | 4532 | intel_dp_connector_destroy(struct drm_connector *connector) |
a4fc5ed6 | 4533 | { |
1d508706 | 4534 | struct intel_connector *intel_connector = to_intel_connector(connector); |
aaa6fd2a | 4535 | |
10e972d3 | 4536 | kfree(intel_connector->detect_edid); |
beb60608 | 4537 | |
9cd300e0 JN |
4538 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
4539 | kfree(intel_connector->edid); | |
4540 | ||
acd8db10 PZ |
4541 | /* Can't call is_edp() since the encoder may have been destroyed |
4542 | * already. */ | |
4543 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
1d508706 | 4544 | intel_panel_fini(&intel_connector->panel); |
aaa6fd2a | 4545 | |
a4fc5ed6 | 4546 | drm_connector_cleanup(connector); |
55f78c43 | 4547 | kfree(connector); |
a4fc5ed6 KP |
4548 | } |
4549 | ||
00c09d70 | 4550 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
24d05927 | 4551 | { |
da63a9f2 PZ |
4552 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
4553 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
24d05927 | 4554 | |
0e32b39c | 4555 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
bd943159 KP |
4556 | if (is_edp(intel_dp)) { |
4557 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
951468f3 VS |
4558 | /* |
4559 | * vdd might still be enabled do to the delayed vdd off. | |
4560 | * Make sure vdd is actually turned off here. | |
4561 | */ | |
773538e8 | 4562 | pps_lock(intel_dp); |
4be73780 | 4563 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 VS |
4564 | pps_unlock(intel_dp); |
4565 | ||
01527b31 CT |
4566 | if (intel_dp->edp_notifier.notifier_call) { |
4567 | unregister_reboot_notifier(&intel_dp->edp_notifier); | |
4568 | intel_dp->edp_notifier.notifier_call = NULL; | |
4569 | } | |
bd943159 | 4570 | } |
c8bd0e49 | 4571 | drm_encoder_cleanup(encoder); |
da63a9f2 | 4572 | kfree(intel_dig_port); |
24d05927 DV |
4573 | } |
4574 | ||
bf93ba67 | 4575 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
07f9cd0b ID |
4576 | { |
4577 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
4578 | ||
4579 | if (!is_edp(intel_dp)) | |
4580 | return; | |
4581 | ||
951468f3 VS |
4582 | /* |
4583 | * vdd might still be enabled do to the delayed vdd off. | |
4584 | * Make sure vdd is actually turned off here. | |
4585 | */ | |
afa4e53a | 4586 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
773538e8 | 4587 | pps_lock(intel_dp); |
07f9cd0b | 4588 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 | 4589 | pps_unlock(intel_dp); |
07f9cd0b ID |
4590 | } |
4591 | ||
49e6bc51 VS |
4592 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
4593 | { | |
4594 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4595 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
4596 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4597 | enum intel_display_power_domain power_domain; | |
4598 | ||
4599 | lockdep_assert_held(&dev_priv->pps_mutex); | |
4600 | ||
4601 | if (!edp_have_panel_vdd(intel_dp)) | |
4602 | return; | |
4603 | ||
4604 | /* | |
4605 | * The VDD bit needs a power domain reference, so if the bit is | |
4606 | * already enabled when we boot or resume, grab this reference and | |
4607 | * schedule a vdd off, so we don't hold on to the reference | |
4608 | * indefinitely. | |
4609 | */ | |
4610 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); | |
25f78f58 | 4611 | power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); |
49e6bc51 VS |
4612 | intel_display_power_get(dev_priv, power_domain); |
4613 | ||
4614 | edp_panel_vdd_schedule_off(intel_dp); | |
4615 | } | |
4616 | ||
bf93ba67 | 4617 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
6d93c0c4 | 4618 | { |
49e6bc51 VS |
4619 | struct intel_dp *intel_dp; |
4620 | ||
4621 | if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) | |
4622 | return; | |
4623 | ||
4624 | intel_dp = enc_to_intel_dp(encoder); | |
4625 | ||
4626 | pps_lock(intel_dp); | |
4627 | ||
4628 | /* | |
4629 | * Read out the current power sequencer assignment, | |
4630 | * in case the BIOS did something with it. | |
4631 | */ | |
666a4537 | 4632 | if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev)) |
49e6bc51 VS |
4633 | vlv_initial_power_sequencer_setup(intel_dp); |
4634 | ||
4635 | intel_edp_panel_vdd_sanitize(intel_dp); | |
4636 | ||
4637 | pps_unlock(intel_dp); | |
6d93c0c4 ID |
4638 | } |
4639 | ||
a4fc5ed6 | 4640 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
4d688a2a | 4641 | .dpms = drm_atomic_helper_connector_dpms, |
a4fc5ed6 | 4642 | .detect = intel_dp_detect, |
beb60608 | 4643 | .force = intel_dp_force, |
a4fc5ed6 | 4644 | .fill_modes = drm_helper_probe_single_connector_modes, |
f684960e | 4645 | .set_property = intel_dp_set_property, |
2545e4a6 | 4646 | .atomic_get_property = intel_connector_atomic_get_property, |
73845adf | 4647 | .destroy = intel_dp_connector_destroy, |
c6f95f27 | 4648 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 4649 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
a4fc5ed6 KP |
4650 | }; |
4651 | ||
4652 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
4653 | .get_modes = intel_dp_get_modes, | |
4654 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 4655 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
4656 | }; |
4657 | ||
a4fc5ed6 | 4658 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
6d93c0c4 | 4659 | .reset = intel_dp_encoder_reset, |
24d05927 | 4660 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
4661 | }; |
4662 | ||
b2c5c181 | 4663 | enum irqreturn |
13cf5504 DA |
4664 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
4665 | { | |
4666 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
1c767b33 | 4667 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
0e32b39c DA |
4668 | struct drm_device *dev = intel_dig_port->base.base.dev; |
4669 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1c767b33 | 4670 | enum intel_display_power_domain power_domain; |
b2c5c181 | 4671 | enum irqreturn ret = IRQ_NONE; |
1c767b33 | 4672 | |
2540058f TI |
4673 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
4674 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) | |
0e32b39c | 4675 | intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT; |
13cf5504 | 4676 | |
7a7f84cc VS |
4677 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
4678 | /* | |
4679 | * vdd off can generate a long pulse on eDP which | |
4680 | * would require vdd on to handle it, and thus we | |
4681 | * would end up in an endless cycle of | |
4682 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." | |
4683 | */ | |
4684 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", | |
4685 | port_name(intel_dig_port->port)); | |
a8b3d52f | 4686 | return IRQ_HANDLED; |
7a7f84cc VS |
4687 | } |
4688 | ||
26fbb774 VS |
4689 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
4690 | port_name(intel_dig_port->port), | |
0e32b39c | 4691 | long_hpd ? "long" : "short"); |
13cf5504 | 4692 | |
25f78f58 | 4693 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
1c767b33 ID |
4694 | intel_display_power_get(dev_priv, power_domain); |
4695 | ||
0e32b39c | 4696 | if (long_hpd) { |
5fa836a9 MK |
4697 | /* indicate that we need to restart link training */ |
4698 | intel_dp->train_set_valid = false; | |
2a592bec | 4699 | |
7d23e3c3 SS |
4700 | intel_dp_long_pulse(intel_dp->attached_connector); |
4701 | if (intel_dp->is_mst) | |
4702 | ret = IRQ_HANDLED; | |
4703 | goto put_power; | |
0e32b39c | 4704 | |
0e32b39c DA |
4705 | } else { |
4706 | if (intel_dp->is_mst) { | |
7d23e3c3 SS |
4707 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { |
4708 | /* | |
4709 | * If we were in MST mode, and device is not | |
4710 | * there, get out of MST mode | |
4711 | */ | |
4712 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
4713 | intel_dp->is_mst, intel_dp->mst_mgr.mst_state); | |
4714 | intel_dp->is_mst = false; | |
4715 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
4716 | intel_dp->is_mst); | |
4717 | goto put_power; | |
4718 | } | |
0e32b39c DA |
4719 | } |
4720 | ||
39ff747b SS |
4721 | if (!intel_dp->is_mst) { |
4722 | if (!intel_dp_short_pulse(intel_dp)) { | |
4723 | intel_dp_long_pulse(intel_dp->attached_connector); | |
4724 | goto put_power; | |
4725 | } | |
4726 | } | |
0e32b39c | 4727 | } |
b2c5c181 DV |
4728 | |
4729 | ret = IRQ_HANDLED; | |
4730 | ||
1c767b33 ID |
4731 | put_power: |
4732 | intel_display_power_put(dev_priv, power_domain); | |
4733 | ||
4734 | return ret; | |
13cf5504 DA |
4735 | } |
4736 | ||
477ec328 | 4737 | /* check the VBT to see whether the eDP is on another port */ |
5d8a7752 | 4738 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
36e83a18 ZY |
4739 | { |
4740 | struct drm_i915_private *dev_priv = dev->dev_private; | |
36e83a18 | 4741 | |
53ce81a7 VS |
4742 | /* |
4743 | * eDP not supported on g4x. so bail out early just | |
4744 | * for a bit extra safety in case the VBT is bonkers. | |
4745 | */ | |
4746 | if (INTEL_INFO(dev)->gen < 5) | |
4747 | return false; | |
4748 | ||
3b32a35b VS |
4749 | if (port == PORT_A) |
4750 | return true; | |
4751 | ||
951d9efe | 4752 | return intel_bios_is_port_edp(dev_priv, port); |
36e83a18 ZY |
4753 | } |
4754 | ||
0e32b39c | 4755 | void |
f684960e CW |
4756 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
4757 | { | |
53b41837 YN |
4758 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4759 | ||
3f43c48d | 4760 | intel_attach_force_audio_property(connector); |
e953fd7b | 4761 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 4762 | intel_dp->color_range_auto = true; |
53b41837 YN |
4763 | |
4764 | if (is_edp(intel_dp)) { | |
4765 | drm_mode_create_scaling_mode_property(connector->dev); | |
6de6d846 RC |
4766 | drm_object_attach_property( |
4767 | &connector->base, | |
53b41837 | 4768 | connector->dev->mode_config.scaling_mode_property, |
8e740cd1 YN |
4769 | DRM_MODE_SCALE_ASPECT); |
4770 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
53b41837 | 4771 | } |
f684960e CW |
4772 | } |
4773 | ||
dada1a9f ID |
4774 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
4775 | { | |
d28d4731 | 4776 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
dada1a9f ID |
4777 | intel_dp->last_power_on = jiffies; |
4778 | intel_dp->last_backlight_off = jiffies; | |
4779 | } | |
4780 | ||
67a54566 DV |
4781 | static void |
4782 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
36b5f425 | 4783 | struct intel_dp *intel_dp) |
67a54566 DV |
4784 | { |
4785 | struct drm_i915_private *dev_priv = dev->dev_private; | |
36b5f425 VS |
4786 | struct edp_power_seq cur, vbt, spec, |
4787 | *final = &intel_dp->pps_delays; | |
b0a08bec | 4788 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
f0f59a00 | 4789 | i915_reg_t pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
453c5420 | 4790 | |
e39b999a VS |
4791 | lockdep_assert_held(&dev_priv->pps_mutex); |
4792 | ||
81ddbc69 VS |
4793 | /* already initialized? */ |
4794 | if (final->t11_t12 != 0) | |
4795 | return; | |
4796 | ||
b0a08bec VK |
4797 | if (IS_BROXTON(dev)) { |
4798 | /* | |
4799 | * TODO: BXT has 2 sets of PPS registers. | |
4800 | * Correct Register for Broxton need to be identified | |
4801 | * using VBT. hardcoding for now | |
4802 | */ | |
4803 | pp_ctrl_reg = BXT_PP_CONTROL(0); | |
4804 | pp_on_reg = BXT_PP_ON_DELAYS(0); | |
4805 | pp_off_reg = BXT_PP_OFF_DELAYS(0); | |
4806 | } else if (HAS_PCH_SPLIT(dev)) { | |
bf13e81b | 4807 | pp_ctrl_reg = PCH_PP_CONTROL; |
453c5420 JB |
4808 | pp_on_reg = PCH_PP_ON_DELAYS; |
4809 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
4810 | pp_div_reg = PCH_PP_DIVISOR; | |
4811 | } else { | |
bf13e81b JN |
4812 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
4813 | ||
4814 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); | |
4815 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); | |
4816 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); | |
4817 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
453c5420 | 4818 | } |
67a54566 DV |
4819 | |
4820 | /* Workaround: Need to write PP_CONTROL with the unlock key as | |
4821 | * the very first thing. */ | |
b0a08bec | 4822 | pp_ctl = ironlake_get_pp_control(intel_dp); |
67a54566 | 4823 | |
453c5420 JB |
4824 | pp_on = I915_READ(pp_on_reg); |
4825 | pp_off = I915_READ(pp_off_reg); | |
b0a08bec VK |
4826 | if (!IS_BROXTON(dev)) { |
4827 | I915_WRITE(pp_ctrl_reg, pp_ctl); | |
4828 | pp_div = I915_READ(pp_div_reg); | |
4829 | } | |
67a54566 DV |
4830 | |
4831 | /* Pull timing values out of registers */ | |
4832 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> | |
4833 | PANEL_POWER_UP_DELAY_SHIFT; | |
4834 | ||
4835 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> | |
4836 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
4837 | ||
4838 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> | |
4839 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
4840 | ||
4841 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> | |
4842 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
4843 | ||
b0a08bec VK |
4844 | if (IS_BROXTON(dev)) { |
4845 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> | |
4846 | BXT_POWER_CYCLE_DELAY_SHIFT; | |
4847 | if (tmp > 0) | |
4848 | cur.t11_t12 = (tmp - 1) * 1000; | |
4849 | else | |
4850 | cur.t11_t12 = 0; | |
4851 | } else { | |
4852 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
67a54566 | 4853 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
b0a08bec | 4854 | } |
67a54566 DV |
4855 | |
4856 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
4857 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); | |
4858 | ||
6aa23e65 | 4859 | vbt = dev_priv->vbt.edp.pps; |
67a54566 DV |
4860 | |
4861 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
4862 | * our hw here, which are all in 100usec. */ | |
4863 | spec.t1_t3 = 210 * 10; | |
4864 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
4865 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
4866 | spec.t10 = 500 * 10; | |
4867 | /* This one is special and actually in units of 100ms, but zero | |
4868 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
4869 | * table multiplies it with 1000 to make it in units of 100usec, | |
4870 | * too. */ | |
4871 | spec.t11_t12 = (510 + 100) * 10; | |
4872 | ||
4873 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
4874 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); | |
4875 | ||
4876 | /* Use the max of the register settings and vbt. If both are | |
4877 | * unset, fall back to the spec limits. */ | |
36b5f425 | 4878 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
67a54566 DV |
4879 | spec.field : \ |
4880 | max(cur.field, vbt.field)) | |
4881 | assign_final(t1_t3); | |
4882 | assign_final(t8); | |
4883 | assign_final(t9); | |
4884 | assign_final(t10); | |
4885 | assign_final(t11_t12); | |
4886 | #undef assign_final | |
4887 | ||
36b5f425 | 4888 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
67a54566 DV |
4889 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
4890 | intel_dp->backlight_on_delay = get_delay(t8); | |
4891 | intel_dp->backlight_off_delay = get_delay(t9); | |
4892 | intel_dp->panel_power_down_delay = get_delay(t10); | |
4893 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
4894 | #undef get_delay | |
4895 | ||
f30d26e4 JN |
4896 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
4897 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
4898 | intel_dp->panel_power_cycle_delay); | |
4899 | ||
4900 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
4901 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
f30d26e4 JN |
4902 | } |
4903 | ||
4904 | static void | |
4905 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
36b5f425 | 4906 | struct intel_dp *intel_dp) |
f30d26e4 JN |
4907 | { |
4908 | struct drm_i915_private *dev_priv = dev->dev_private; | |
453c5420 | 4909 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
e7dc33f3 | 4910 | int div = dev_priv->rawclk_freq / 1000; |
f0f59a00 | 4911 | i915_reg_t pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg; |
ad933b56 | 4912 | enum port port = dp_to_dig_port(intel_dp)->port; |
36b5f425 | 4913 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
453c5420 | 4914 | |
e39b999a | 4915 | lockdep_assert_held(&dev_priv->pps_mutex); |
453c5420 | 4916 | |
b0a08bec VK |
4917 | if (IS_BROXTON(dev)) { |
4918 | /* | |
4919 | * TODO: BXT has 2 sets of PPS registers. | |
4920 | * Correct Register for Broxton need to be identified | |
4921 | * using VBT. hardcoding for now | |
4922 | */ | |
4923 | pp_ctrl_reg = BXT_PP_CONTROL(0); | |
4924 | pp_on_reg = BXT_PP_ON_DELAYS(0); | |
4925 | pp_off_reg = BXT_PP_OFF_DELAYS(0); | |
4926 | ||
4927 | } else if (HAS_PCH_SPLIT(dev)) { | |
453c5420 JB |
4928 | pp_on_reg = PCH_PP_ON_DELAYS; |
4929 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
4930 | pp_div_reg = PCH_PP_DIVISOR; | |
4931 | } else { | |
bf13e81b JN |
4932 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
4933 | ||
4934 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); | |
4935 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); | |
4936 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
453c5420 JB |
4937 | } |
4938 | ||
b2f19d1a PZ |
4939 | /* |
4940 | * And finally store the new values in the power sequencer. The | |
4941 | * backlight delays are set to 1 because we do manual waits on them. For | |
4942 | * T8, even BSpec recommends doing it. For T9, if we don't do this, | |
4943 | * we'll end up waiting for the backlight off delay twice: once when we | |
4944 | * do the manual sleep, and once when we disable the panel and wait for | |
4945 | * the PP_STATUS bit to become zero. | |
4946 | */ | |
f30d26e4 | 4947 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
b2f19d1a PZ |
4948 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
4949 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | | |
f30d26e4 | 4950 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
67a54566 DV |
4951 | /* Compute the divisor for the pp clock, simply match the Bspec |
4952 | * formula. */ | |
b0a08bec VK |
4953 | if (IS_BROXTON(dev)) { |
4954 | pp_div = I915_READ(pp_ctrl_reg); | |
4955 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; | |
4956 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) | |
4957 | << BXT_POWER_CYCLE_DELAY_SHIFT); | |
4958 | } else { | |
4959 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; | |
4960 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) | |
4961 | << PANEL_POWER_CYCLE_DELAY_SHIFT); | |
4962 | } | |
67a54566 DV |
4963 | |
4964 | /* Haswell doesn't have any port selection bits for the panel | |
4965 | * power sequencer any more. */ | |
666a4537 | 4966 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ad933b56 | 4967 | port_sel = PANEL_PORT_SELECT_VLV(port); |
bc7d38a4 | 4968 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
ad933b56 | 4969 | if (port == PORT_A) |
a24c144c | 4970 | port_sel = PANEL_PORT_SELECT_DPA; |
67a54566 | 4971 | else |
a24c144c | 4972 | port_sel = PANEL_PORT_SELECT_DPD; |
67a54566 DV |
4973 | } |
4974 | ||
453c5420 JB |
4975 | pp_on |= port_sel; |
4976 | ||
4977 | I915_WRITE(pp_on_reg, pp_on); | |
4978 | I915_WRITE(pp_off_reg, pp_off); | |
b0a08bec VK |
4979 | if (IS_BROXTON(dev)) |
4980 | I915_WRITE(pp_ctrl_reg, pp_div); | |
4981 | else | |
4982 | I915_WRITE(pp_div_reg, pp_div); | |
67a54566 | 4983 | |
67a54566 | 4984 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
453c5420 JB |
4985 | I915_READ(pp_on_reg), |
4986 | I915_READ(pp_off_reg), | |
b0a08bec VK |
4987 | IS_BROXTON(dev) ? |
4988 | (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) : | |
453c5420 | 4989 | I915_READ(pp_div_reg)); |
f684960e CW |
4990 | } |
4991 | ||
b33a2815 VK |
4992 | /** |
4993 | * intel_dp_set_drrs_state - program registers for RR switch to take effect | |
4994 | * @dev: DRM device | |
4995 | * @refresh_rate: RR to be programmed | |
4996 | * | |
4997 | * This function gets called when refresh rate (RR) has to be changed from | |
4998 | * one frequency to another. Switches can be between high and low RR | |
4999 | * supported by the panel or to any other RR based on media playback (in | |
5000 | * this case, RR value needs to be passed from user space). | |
5001 | * | |
5002 | * The caller of this function needs to take a lock on dev_priv->drrs. | |
5003 | */ | |
96178eeb | 5004 | static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
439d7ac0 PB |
5005 | { |
5006 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5007 | struct intel_encoder *encoder; | |
96178eeb VK |
5008 | struct intel_digital_port *dig_port = NULL; |
5009 | struct intel_dp *intel_dp = dev_priv->drrs.dp; | |
5cec258b | 5010 | struct intel_crtc_state *config = NULL; |
439d7ac0 | 5011 | struct intel_crtc *intel_crtc = NULL; |
96178eeb | 5012 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
439d7ac0 PB |
5013 | |
5014 | if (refresh_rate <= 0) { | |
5015 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); | |
5016 | return; | |
5017 | } | |
5018 | ||
96178eeb VK |
5019 | if (intel_dp == NULL) { |
5020 | DRM_DEBUG_KMS("DRRS not supported.\n"); | |
439d7ac0 PB |
5021 | return; |
5022 | } | |
5023 | ||
1fcc9d1c | 5024 | /* |
e4d59f6b RV |
5025 | * FIXME: This needs proper synchronization with psr state for some |
5026 | * platforms that cannot have PSR and DRRS enabled at the same time. | |
1fcc9d1c | 5027 | */ |
439d7ac0 | 5028 | |
96178eeb VK |
5029 | dig_port = dp_to_dig_port(intel_dp); |
5030 | encoder = &dig_port->base; | |
723f9aab | 5031 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
439d7ac0 PB |
5032 | |
5033 | if (!intel_crtc) { | |
5034 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); | |
5035 | return; | |
5036 | } | |
5037 | ||
6e3c9717 | 5038 | config = intel_crtc->config; |
439d7ac0 | 5039 | |
96178eeb | 5040 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
439d7ac0 PB |
5041 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
5042 | return; | |
5043 | } | |
5044 | ||
96178eeb VK |
5045 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
5046 | refresh_rate) | |
439d7ac0 PB |
5047 | index = DRRS_LOW_RR; |
5048 | ||
96178eeb | 5049 | if (index == dev_priv->drrs.refresh_rate_type) { |
439d7ac0 PB |
5050 | DRM_DEBUG_KMS( |
5051 | "DRRS requested for previously set RR...ignoring\n"); | |
5052 | return; | |
5053 | } | |
5054 | ||
5055 | if (!intel_crtc->active) { | |
5056 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); | |
5057 | return; | |
5058 | } | |
5059 | ||
44395bfe | 5060 | if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) { |
a4c30b1d VK |
5061 | switch (index) { |
5062 | case DRRS_HIGH_RR: | |
5063 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
5064 | break; | |
5065 | case DRRS_LOW_RR: | |
5066 | intel_dp_set_m_n(intel_crtc, M2_N2); | |
5067 | break; | |
5068 | case DRRS_MAX_RR: | |
5069 | default: | |
5070 | DRM_ERROR("Unsupported refreshrate type\n"); | |
5071 | } | |
5072 | } else if (INTEL_INFO(dev)->gen > 6) { | |
f0f59a00 | 5073 | i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder); |
649636ef | 5074 | u32 val; |
a4c30b1d | 5075 | |
649636ef | 5076 | val = I915_READ(reg); |
439d7ac0 | 5077 | if (index > DRRS_HIGH_RR) { |
666a4537 | 5078 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6fa7aec1 VK |
5079 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5080 | else | |
5081 | val |= PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 | 5082 | } else { |
666a4537 | 5083 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6fa7aec1 VK |
5084 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5085 | else | |
5086 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 PB |
5087 | } |
5088 | I915_WRITE(reg, val); | |
5089 | } | |
5090 | ||
4e9ac947 VK |
5091 | dev_priv->drrs.refresh_rate_type = index; |
5092 | ||
5093 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); | |
5094 | } | |
5095 | ||
b33a2815 VK |
5096 | /** |
5097 | * intel_edp_drrs_enable - init drrs struct if supported | |
5098 | * @intel_dp: DP struct | |
5099 | * | |
5100 | * Initializes frontbuffer_bits and drrs.dp | |
5101 | */ | |
c395578e VK |
5102 | void intel_edp_drrs_enable(struct intel_dp *intel_dp) |
5103 | { | |
5104 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
5105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5106 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
5107 | struct drm_crtc *crtc = dig_port->base.base.crtc; | |
5108 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5109 | ||
5110 | if (!intel_crtc->config->has_drrs) { | |
5111 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); | |
5112 | return; | |
5113 | } | |
5114 | ||
5115 | mutex_lock(&dev_priv->drrs.mutex); | |
5116 | if (WARN_ON(dev_priv->drrs.dp)) { | |
5117 | DRM_ERROR("DRRS already enabled\n"); | |
5118 | goto unlock; | |
5119 | } | |
5120 | ||
5121 | dev_priv->drrs.busy_frontbuffer_bits = 0; | |
5122 | ||
5123 | dev_priv->drrs.dp = intel_dp; | |
5124 | ||
5125 | unlock: | |
5126 | mutex_unlock(&dev_priv->drrs.mutex); | |
5127 | } | |
5128 | ||
b33a2815 VK |
5129 | /** |
5130 | * intel_edp_drrs_disable - Disable DRRS | |
5131 | * @intel_dp: DP struct | |
5132 | * | |
5133 | */ | |
c395578e VK |
5134 | void intel_edp_drrs_disable(struct intel_dp *intel_dp) |
5135 | { | |
5136 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
5137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5138 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
5139 | struct drm_crtc *crtc = dig_port->base.base.crtc; | |
5140 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5141 | ||
5142 | if (!intel_crtc->config->has_drrs) | |
5143 | return; | |
5144 | ||
5145 | mutex_lock(&dev_priv->drrs.mutex); | |
5146 | if (!dev_priv->drrs.dp) { | |
5147 | mutex_unlock(&dev_priv->drrs.mutex); | |
5148 | return; | |
5149 | } | |
5150 | ||
5151 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) | |
5152 | intel_dp_set_drrs_state(dev_priv->dev, | |
5153 | intel_dp->attached_connector->panel. | |
5154 | fixed_mode->vrefresh); | |
5155 | ||
5156 | dev_priv->drrs.dp = NULL; | |
5157 | mutex_unlock(&dev_priv->drrs.mutex); | |
5158 | ||
5159 | cancel_delayed_work_sync(&dev_priv->drrs.work); | |
5160 | } | |
5161 | ||
4e9ac947 VK |
5162 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
5163 | { | |
5164 | struct drm_i915_private *dev_priv = | |
5165 | container_of(work, typeof(*dev_priv), drrs.work.work); | |
5166 | struct intel_dp *intel_dp; | |
5167 | ||
5168 | mutex_lock(&dev_priv->drrs.mutex); | |
5169 | ||
5170 | intel_dp = dev_priv->drrs.dp; | |
5171 | ||
5172 | if (!intel_dp) | |
5173 | goto unlock; | |
5174 | ||
439d7ac0 | 5175 | /* |
4e9ac947 VK |
5176 | * The delayed work can race with an invalidate hence we need to |
5177 | * recheck. | |
439d7ac0 PB |
5178 | */ |
5179 | ||
4e9ac947 VK |
5180 | if (dev_priv->drrs.busy_frontbuffer_bits) |
5181 | goto unlock; | |
439d7ac0 | 5182 | |
4e9ac947 VK |
5183 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) |
5184 | intel_dp_set_drrs_state(dev_priv->dev, | |
5185 | intel_dp->attached_connector->panel. | |
5186 | downclock_mode->vrefresh); | |
439d7ac0 | 5187 | |
4e9ac947 | 5188 | unlock: |
4e9ac947 | 5189 | mutex_unlock(&dev_priv->drrs.mutex); |
439d7ac0 PB |
5190 | } |
5191 | ||
b33a2815 | 5192 | /** |
0ddfd203 | 5193 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
b33a2815 VK |
5194 | * @dev: DRM device |
5195 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
5196 | * | |
0ddfd203 R |
5197 | * This function gets called everytime rendering on the given planes start. |
5198 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). | |
b33a2815 VK |
5199 | * |
5200 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5201 | */ | |
a93fad0f VK |
5202 | void intel_edp_drrs_invalidate(struct drm_device *dev, |
5203 | unsigned frontbuffer_bits) | |
5204 | { | |
5205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5206 | struct drm_crtc *crtc; | |
5207 | enum pipe pipe; | |
5208 | ||
9da7d693 | 5209 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5210 | return; |
5211 | ||
88f933a8 | 5212 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5213 | |
a93fad0f | 5214 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5215 | if (!dev_priv->drrs.dp) { |
5216 | mutex_unlock(&dev_priv->drrs.mutex); | |
5217 | return; | |
5218 | } | |
5219 | ||
a93fad0f VK |
5220 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5221 | pipe = to_intel_crtc(crtc)->pipe; | |
5222 | ||
c1d038c6 DV |
5223 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5224 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; | |
5225 | ||
0ddfd203 | 5226 | /* invalidate means busy screen hence upclock */ |
c1d038c6 | 5227 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
a93fad0f VK |
5228 | intel_dp_set_drrs_state(dev_priv->dev, |
5229 | dev_priv->drrs.dp->attached_connector->panel. | |
5230 | fixed_mode->vrefresh); | |
a93fad0f | 5231 | |
a93fad0f VK |
5232 | mutex_unlock(&dev_priv->drrs.mutex); |
5233 | } | |
5234 | ||
b33a2815 | 5235 | /** |
0ddfd203 | 5236 | * intel_edp_drrs_flush - Restart Idleness DRRS |
b33a2815 VK |
5237 | * @dev: DRM device |
5238 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
5239 | * | |
0ddfd203 R |
5240 | * This function gets called every time rendering on the given planes has |
5241 | * completed or flip on a crtc is completed. So DRRS should be upclocked | |
5242 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, | |
5243 | * if no other planes are dirty. | |
b33a2815 VK |
5244 | * |
5245 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5246 | */ | |
a93fad0f VK |
5247 | void intel_edp_drrs_flush(struct drm_device *dev, |
5248 | unsigned frontbuffer_bits) | |
5249 | { | |
5250 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5251 | struct drm_crtc *crtc; | |
5252 | enum pipe pipe; | |
5253 | ||
9da7d693 | 5254 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5255 | return; |
5256 | ||
88f933a8 | 5257 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5258 | |
a93fad0f | 5259 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5260 | if (!dev_priv->drrs.dp) { |
5261 | mutex_unlock(&dev_priv->drrs.mutex); | |
5262 | return; | |
5263 | } | |
5264 | ||
a93fad0f VK |
5265 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5266 | pipe = to_intel_crtc(crtc)->pipe; | |
c1d038c6 DV |
5267 | |
5268 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
a93fad0f VK |
5269 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
5270 | ||
0ddfd203 | 5271 | /* flush means busy screen hence upclock */ |
c1d038c6 | 5272 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
0ddfd203 R |
5273 | intel_dp_set_drrs_state(dev_priv->dev, |
5274 | dev_priv->drrs.dp->attached_connector->panel. | |
5275 | fixed_mode->vrefresh); | |
5276 | ||
5277 | /* | |
5278 | * flush also means no more activity hence schedule downclock, if all | |
5279 | * other fbs are quiescent too | |
5280 | */ | |
5281 | if (!dev_priv->drrs.busy_frontbuffer_bits) | |
a93fad0f VK |
5282 | schedule_delayed_work(&dev_priv->drrs.work, |
5283 | msecs_to_jiffies(1000)); | |
5284 | mutex_unlock(&dev_priv->drrs.mutex); | |
5285 | } | |
5286 | ||
b33a2815 VK |
5287 | /** |
5288 | * DOC: Display Refresh Rate Switching (DRRS) | |
5289 | * | |
5290 | * Display Refresh Rate Switching (DRRS) is a power conservation feature | |
5291 | * which enables swtching between low and high refresh rates, | |
5292 | * dynamically, based on the usage scenario. This feature is applicable | |
5293 | * for internal panels. | |
5294 | * | |
5295 | * Indication that the panel supports DRRS is given by the panel EDID, which | |
5296 | * would list multiple refresh rates for one resolution. | |
5297 | * | |
5298 | * DRRS is of 2 types - static and seamless. | |
5299 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset | |
5300 | * (may appear as a blink on screen) and is used in dock-undock scenario. | |
5301 | * Seamless DRRS involves changing RR without any visual effect to the user | |
5302 | * and can be used during normal system usage. This is done by programming | |
5303 | * certain registers. | |
5304 | * | |
5305 | * Support for static/seamless DRRS may be indicated in the VBT based on | |
5306 | * inputs from the panel spec. | |
5307 | * | |
5308 | * DRRS saves power by switching to low RR based on usage scenarios. | |
5309 | * | |
5310 | * eDP DRRS:- | |
5311 | * The implementation is based on frontbuffer tracking implementation. | |
5312 | * When there is a disturbance on the screen triggered by user activity or a | |
5313 | * periodic system activity, DRRS is disabled (RR is changed to high RR). | |
5314 | * When there is no movement on screen, after a timeout of 1 second, a switch | |
5315 | * to low RR is made. | |
5316 | * For integration with frontbuffer tracking code, | |
5317 | * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called. | |
5318 | * | |
5319 | * DRRS can be further extended to support other internal panels and also | |
5320 | * the scenario of video playback wherein RR is set based on the rate | |
5321 | * requested by userspace. | |
5322 | */ | |
5323 | ||
5324 | /** | |
5325 | * intel_dp_drrs_init - Init basic DRRS work and mutex. | |
5326 | * @intel_connector: eDP connector | |
5327 | * @fixed_mode: preferred mode of panel | |
5328 | * | |
5329 | * This function is called only once at driver load to initialize basic | |
5330 | * DRRS stuff. | |
5331 | * | |
5332 | * Returns: | |
5333 | * Downclock mode if panel supports it, else return NULL. | |
5334 | * DRRS support is determined by the presence of downclock mode (apart | |
5335 | * from VBT setting). | |
5336 | */ | |
4f9db5b5 | 5337 | static struct drm_display_mode * |
96178eeb VK |
5338 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
5339 | struct drm_display_mode *fixed_mode) | |
4f9db5b5 PB |
5340 | { |
5341 | struct drm_connector *connector = &intel_connector->base; | |
96178eeb | 5342 | struct drm_device *dev = connector->dev; |
4f9db5b5 PB |
5343 | struct drm_i915_private *dev_priv = dev->dev_private; |
5344 | struct drm_display_mode *downclock_mode = NULL; | |
5345 | ||
9da7d693 DV |
5346 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
5347 | mutex_init(&dev_priv->drrs.mutex); | |
5348 | ||
4f9db5b5 PB |
5349 | if (INTEL_INFO(dev)->gen <= 6) { |
5350 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); | |
5351 | return NULL; | |
5352 | } | |
5353 | ||
5354 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { | |
4079b8d1 | 5355 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
4f9db5b5 PB |
5356 | return NULL; |
5357 | } | |
5358 | ||
5359 | downclock_mode = intel_find_panel_downclock | |
5360 | (dev, fixed_mode, connector); | |
5361 | ||
5362 | if (!downclock_mode) { | |
a1d26342 | 5363 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
4f9db5b5 PB |
5364 | return NULL; |
5365 | } | |
5366 | ||
96178eeb | 5367 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
4f9db5b5 | 5368 | |
96178eeb | 5369 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
4079b8d1 | 5370 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
4f9db5b5 PB |
5371 | return downclock_mode; |
5372 | } | |
5373 | ||
ed92f0b2 | 5374 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
36b5f425 | 5375 | struct intel_connector *intel_connector) |
ed92f0b2 PZ |
5376 | { |
5377 | struct drm_connector *connector = &intel_connector->base; | |
5378 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
63635217 PZ |
5379 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5380 | struct drm_device *dev = intel_encoder->base.dev; | |
ed92f0b2 PZ |
5381 | struct drm_i915_private *dev_priv = dev->dev_private; |
5382 | struct drm_display_mode *fixed_mode = NULL; | |
4f9db5b5 | 5383 | struct drm_display_mode *downclock_mode = NULL; |
ed92f0b2 PZ |
5384 | bool has_dpcd; |
5385 | struct drm_display_mode *scan; | |
5386 | struct edid *edid; | |
6517d273 | 5387 | enum pipe pipe = INVALID_PIPE; |
ed92f0b2 PZ |
5388 | |
5389 | if (!is_edp(intel_dp)) | |
5390 | return true; | |
5391 | ||
49e6bc51 VS |
5392 | pps_lock(intel_dp); |
5393 | intel_edp_panel_vdd_sanitize(intel_dp); | |
5394 | pps_unlock(intel_dp); | |
63635217 | 5395 | |
ed92f0b2 | 5396 | /* Cache DPCD and EDID for edp. */ |
ed92f0b2 | 5397 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
ed92f0b2 PZ |
5398 | |
5399 | if (has_dpcd) { | |
5400 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) | |
5401 | dev_priv->no_aux_handshake = | |
5402 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
5403 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; | |
5404 | } else { | |
5405 | /* if this fails, presume the device is a ghost */ | |
5406 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); | |
ed92f0b2 PZ |
5407 | return false; |
5408 | } | |
5409 | ||
5410 | /* We now know it's not a ghost, init power sequence regs. */ | |
773538e8 | 5411 | pps_lock(intel_dp); |
36b5f425 | 5412 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); |
773538e8 | 5413 | pps_unlock(intel_dp); |
ed92f0b2 | 5414 | |
060c8778 | 5415 | mutex_lock(&dev->mode_config.mutex); |
0b99836f | 5416 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
ed92f0b2 PZ |
5417 | if (edid) { |
5418 | if (drm_add_edid_modes(connector, edid)) { | |
5419 | drm_mode_connector_update_edid_property(connector, | |
5420 | edid); | |
5421 | drm_edid_to_eld(connector, edid); | |
5422 | } else { | |
5423 | kfree(edid); | |
5424 | edid = ERR_PTR(-EINVAL); | |
5425 | } | |
5426 | } else { | |
5427 | edid = ERR_PTR(-ENOENT); | |
5428 | } | |
5429 | intel_connector->edid = edid; | |
5430 | ||
5431 | /* prefer fixed mode from EDID if available */ | |
5432 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
5433 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
5434 | fixed_mode = drm_mode_duplicate(dev, scan); | |
4f9db5b5 | 5435 | downclock_mode = intel_dp_drrs_init( |
4f9db5b5 | 5436 | intel_connector, fixed_mode); |
ed92f0b2 PZ |
5437 | break; |
5438 | } | |
5439 | } | |
5440 | ||
5441 | /* fallback to VBT if available for eDP */ | |
5442 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { | |
5443 | fixed_mode = drm_mode_duplicate(dev, | |
5444 | dev_priv->vbt.lfp_lvds_vbt_mode); | |
5445 | if (fixed_mode) | |
5446 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
5447 | } | |
060c8778 | 5448 | mutex_unlock(&dev->mode_config.mutex); |
ed92f0b2 | 5449 | |
666a4537 | 5450 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
01527b31 CT |
5451 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
5452 | register_reboot_notifier(&intel_dp->edp_notifier); | |
6517d273 VS |
5453 | |
5454 | /* | |
5455 | * Figure out the current pipe for the initial backlight setup. | |
5456 | * If the current pipe isn't valid, try the PPS pipe, and if that | |
5457 | * fails just assume pipe A. | |
5458 | */ | |
5459 | if (IS_CHERRYVIEW(dev)) | |
5460 | pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); | |
5461 | else | |
5462 | pipe = PORT_TO_PIPE(intel_dp->DP); | |
5463 | ||
5464 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5465 | pipe = intel_dp->pps_pipe; | |
5466 | ||
5467 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5468 | pipe = PIPE_A; | |
5469 | ||
5470 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", | |
5471 | pipe_name(pipe)); | |
01527b31 CT |
5472 | } |
5473 | ||
4f9db5b5 | 5474 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
5507faeb | 5475 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
6517d273 | 5476 | intel_panel_setup_backlight(connector, pipe); |
ed92f0b2 PZ |
5477 | |
5478 | return true; | |
5479 | } | |
5480 | ||
16c25533 | 5481 | bool |
f0fec3f2 PZ |
5482 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
5483 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 5484 | { |
f0fec3f2 PZ |
5485 | struct drm_connector *connector = &intel_connector->base; |
5486 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
5487 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
5488 | struct drm_device *dev = intel_encoder->base.dev; | |
a4fc5ed6 | 5489 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 5490 | enum port port = intel_dig_port->port; |
a121f4e5 | 5491 | int type, ret; |
a4fc5ed6 | 5492 | |
ccb1a831 VS |
5493 | if (WARN(intel_dig_port->max_lanes < 1, |
5494 | "Not enough lanes (%d) for DP on port %c\n", | |
5495 | intel_dig_port->max_lanes, port_name(port))) | |
5496 | return false; | |
5497 | ||
a4a5d2f8 VS |
5498 | intel_dp->pps_pipe = INVALID_PIPE; |
5499 | ||
ec5b01dd | 5500 | /* intel_dp vfuncs */ |
b6b5e383 DL |
5501 | if (INTEL_INFO(dev)->gen >= 9) |
5502 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; | |
ec5b01dd DL |
5503 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
5504 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; | |
5505 | else if (HAS_PCH_SPLIT(dev)) | |
5506 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; | |
5507 | else | |
6ffb1be7 | 5508 | intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; |
ec5b01dd | 5509 | |
b9ca5fad DL |
5510 | if (INTEL_INFO(dev)->gen >= 9) |
5511 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; | |
5512 | else | |
6ffb1be7 | 5513 | intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; |
153b1100 | 5514 | |
ad64217b ACO |
5515 | if (HAS_DDI(dev)) |
5516 | intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; | |
5517 | ||
0767935e DV |
5518 | /* Preserve the current hw state. */ |
5519 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
dd06f90e | 5520 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 5521 | |
3b32a35b | 5522 | if (intel_dp_is_edp(dev, port)) |
b329530c | 5523 | type = DRM_MODE_CONNECTOR_eDP; |
3b32a35b VS |
5524 | else |
5525 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
b329530c | 5526 | |
f7d24902 ID |
5527 | /* |
5528 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
5529 | * for DP the encoder type can be set by the caller to | |
5530 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
5531 | */ | |
5532 | if (type == DRM_MODE_CONNECTOR_eDP) | |
5533 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
5534 | ||
c17ed5b5 | 5535 | /* eDP only on port B and/or C on vlv/chv */ |
666a4537 WB |
5536 | if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
5537 | is_edp(intel_dp) && port != PORT_B && port != PORT_C)) | |
c17ed5b5 VS |
5538 | return false; |
5539 | ||
e7281eab ID |
5540 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
5541 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
5542 | port_name(port)); | |
5543 | ||
b329530c | 5544 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
5545 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
5546 | ||
a4fc5ed6 KP |
5547 | connector->interlace_allowed = true; |
5548 | connector->doublescan_allowed = 0; | |
5549 | ||
f0fec3f2 | 5550 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
4be73780 | 5551 | edp_panel_vdd_work); |
a4fc5ed6 | 5552 | |
df0e9248 | 5553 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
34ea3d38 | 5554 | drm_connector_register(connector); |
a4fc5ed6 | 5555 | |
affa9354 | 5556 | if (HAS_DDI(dev)) |
bcbc889b PZ |
5557 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
5558 | else | |
5559 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
80f65de3 | 5560 | intel_connector->unregister = intel_dp_connector_unregister; |
bcbc889b | 5561 | |
0b99836f | 5562 | /* Set up the hotplug pin. */ |
ab9d7c30 PZ |
5563 | switch (port) { |
5564 | case PORT_A: | |
1d843f9d | 5565 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
5566 | break; |
5567 | case PORT_B: | |
1d843f9d | 5568 | intel_encoder->hpd_pin = HPD_PORT_B; |
e87a005d | 5569 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
cf1d5883 | 5570 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
5571 | break; |
5572 | case PORT_C: | |
1d843f9d | 5573 | intel_encoder->hpd_pin = HPD_PORT_C; |
ab9d7c30 PZ |
5574 | break; |
5575 | case PORT_D: | |
1d843f9d | 5576 | intel_encoder->hpd_pin = HPD_PORT_D; |
ab9d7c30 | 5577 | break; |
26951caf XZ |
5578 | case PORT_E: |
5579 | intel_encoder->hpd_pin = HPD_PORT_E; | |
5580 | break; | |
ab9d7c30 | 5581 | default: |
ad1c0b19 | 5582 | BUG(); |
5eb08b69 ZW |
5583 | } |
5584 | ||
dada1a9f | 5585 | if (is_edp(intel_dp)) { |
773538e8 | 5586 | pps_lock(intel_dp); |
1e74a324 | 5587 | intel_dp_init_panel_power_timestamps(intel_dp); |
666a4537 | 5588 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
a4a5d2f8 | 5589 | vlv_initial_power_sequencer_setup(intel_dp); |
1e74a324 | 5590 | else |
36b5f425 | 5591 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
773538e8 | 5592 | pps_unlock(intel_dp); |
dada1a9f | 5593 | } |
0095e6dc | 5594 | |
a121f4e5 VS |
5595 | ret = intel_dp_aux_init(intel_dp, intel_connector); |
5596 | if (ret) | |
5597 | goto fail; | |
c1f05264 | 5598 | |
0e32b39c | 5599 | /* init MST on ports that can support it */ |
0c9b3715 JN |
5600 | if (HAS_DP_MST(dev) && |
5601 | (port == PORT_B || port == PORT_C || port == PORT_D)) | |
5602 | intel_dp_mst_encoder_init(intel_dig_port, | |
5603 | intel_connector->base.base.id); | |
0e32b39c | 5604 | |
36b5f425 | 5605 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
a121f4e5 VS |
5606 | intel_dp_aux_fini(intel_dp); |
5607 | intel_dp_mst_encoder_cleanup(intel_dig_port); | |
5608 | goto fail; | |
b2f246a8 | 5609 | } |
32f9d658 | 5610 | |
f684960e CW |
5611 | intel_dp_add_properties(intel_dp, connector); |
5612 | ||
a4fc5ed6 KP |
5613 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
5614 | * 0xd. Failure to do so will result in spurious interrupts being | |
5615 | * generated on the port when a cable is not attached. | |
5616 | */ | |
5617 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
5618 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
5619 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
5620 | } | |
16c25533 | 5621 | |
aa7471d2 JN |
5622 | i915_debugfs_connector_add(connector); |
5623 | ||
16c25533 | 5624 | return true; |
a121f4e5 VS |
5625 | |
5626 | fail: | |
5627 | if (is_edp(intel_dp)) { | |
5628 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
5629 | /* | |
5630 | * vdd might still be enabled do to the delayed vdd off. | |
5631 | * Make sure vdd is actually turned off here. | |
5632 | */ | |
5633 | pps_lock(intel_dp); | |
5634 | edp_panel_vdd_off_sync(intel_dp); | |
5635 | pps_unlock(intel_dp); | |
5636 | } | |
5637 | drm_connector_unregister(connector); | |
5638 | drm_connector_cleanup(connector); | |
5639 | ||
5640 | return false; | |
a4fc5ed6 | 5641 | } |
f0fec3f2 PZ |
5642 | |
5643 | void | |
f0f59a00 VS |
5644 | intel_dp_init(struct drm_device *dev, |
5645 | i915_reg_t output_reg, enum port port) | |
f0fec3f2 | 5646 | { |
13cf5504 | 5647 | struct drm_i915_private *dev_priv = dev->dev_private; |
f0fec3f2 PZ |
5648 | struct intel_digital_port *intel_dig_port; |
5649 | struct intel_encoder *intel_encoder; | |
5650 | struct drm_encoder *encoder; | |
5651 | struct intel_connector *intel_connector; | |
5652 | ||
b14c5679 | 5653 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
f0fec3f2 PZ |
5654 | if (!intel_dig_port) |
5655 | return; | |
5656 | ||
08d9bc92 | 5657 | intel_connector = intel_connector_alloc(); |
11aee0f6 SM |
5658 | if (!intel_connector) |
5659 | goto err_connector_alloc; | |
f0fec3f2 PZ |
5660 | |
5661 | intel_encoder = &intel_dig_port->base; | |
5662 | encoder = &intel_encoder->base; | |
5663 | ||
893da0c9 | 5664 | if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
ade1ba73 | 5665 | DRM_MODE_ENCODER_TMDS, NULL)) |
893da0c9 | 5666 | goto err_encoder_init; |
f0fec3f2 | 5667 | |
5bfe2ac0 | 5668 | intel_encoder->compute_config = intel_dp_compute_config; |
00c09d70 | 5669 | intel_encoder->disable = intel_disable_dp; |
00c09d70 | 5670 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
045ac3b5 | 5671 | intel_encoder->get_config = intel_dp_get_config; |
07f9cd0b | 5672 | intel_encoder->suspend = intel_dp_encoder_suspend; |
e4a1d846 | 5673 | if (IS_CHERRYVIEW(dev)) { |
9197c88b | 5674 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
e4a1d846 CML |
5675 | intel_encoder->pre_enable = chv_pre_enable_dp; |
5676 | intel_encoder->enable = vlv_enable_dp; | |
580d3811 | 5677 | intel_encoder->post_disable = chv_post_disable_dp; |
d6db995f | 5678 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
e4a1d846 | 5679 | } else if (IS_VALLEYVIEW(dev)) { |
ecff4f3b | 5680 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
5681 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
5682 | intel_encoder->enable = vlv_enable_dp; | |
49277c31 | 5683 | intel_encoder->post_disable = vlv_post_disable_dp; |
ab1f90f9 | 5684 | } else { |
ecff4f3b JN |
5685 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
5686 | intel_encoder->enable = g4x_enable_dp; | |
08aff3fe VS |
5687 | if (INTEL_INFO(dev)->gen >= 5) |
5688 | intel_encoder->post_disable = ilk_post_disable_dp; | |
ab1f90f9 | 5689 | } |
f0fec3f2 | 5690 | |
174edf1f | 5691 | intel_dig_port->port = port; |
f0fec3f2 | 5692 | intel_dig_port->dp.output_reg = output_reg; |
ccb1a831 | 5693 | intel_dig_port->max_lanes = 4; |
f0fec3f2 | 5694 | |
00c09d70 | 5695 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
882ec384 VS |
5696 | if (IS_CHERRYVIEW(dev)) { |
5697 | if (port == PORT_D) | |
5698 | intel_encoder->crtc_mask = 1 << 2; | |
5699 | else | |
5700 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
5701 | } else { | |
5702 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
5703 | } | |
bc079e8b | 5704 | intel_encoder->cloneable = 0; |
f0fec3f2 | 5705 | |
13cf5504 | 5706 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
5fcece80 | 5707 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
13cf5504 | 5708 | |
11aee0f6 SM |
5709 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
5710 | goto err_init_connector; | |
5711 | ||
5712 | return; | |
5713 | ||
5714 | err_init_connector: | |
5715 | drm_encoder_cleanup(encoder); | |
893da0c9 | 5716 | err_encoder_init: |
11aee0f6 SM |
5717 | kfree(intel_connector); |
5718 | err_connector_alloc: | |
5719 | kfree(intel_dig_port); | |
5720 | ||
5721 | return; | |
f0fec3f2 | 5722 | } |
0e32b39c DA |
5723 | |
5724 | void intel_dp_mst_suspend(struct drm_device *dev) | |
5725 | { | |
5726 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5727 | int i; | |
5728 | ||
5729 | /* disable MST */ | |
5730 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 5731 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
0e32b39c DA |
5732 | if (!intel_dig_port) |
5733 | continue; | |
5734 | ||
5735 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { | |
5736 | if (!intel_dig_port->dp.can_mst) | |
5737 | continue; | |
5738 | if (intel_dig_port->dp.is_mst) | |
5739 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); | |
5740 | } | |
5741 | } | |
5742 | } | |
5743 | ||
5744 | void intel_dp_mst_resume(struct drm_device *dev) | |
5745 | { | |
5746 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5747 | int i; | |
5748 | ||
5749 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 5750 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
0e32b39c DA |
5751 | if (!intel_dig_port) |
5752 | continue; | |
5753 | if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) { | |
5754 | int ret; | |
5755 | ||
5756 | if (!intel_dig_port->dp.can_mst) | |
5757 | continue; | |
5758 | ||
5759 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); | |
5760 | if (ret != 0) { | |
5761 | intel_dp_check_mst_status(&intel_dig_port->dp); | |
5762 | } | |
5763 | } | |
5764 | } | |
5765 | } |