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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
a4fc5ed6 KP |
30 | #include "drmP.h" |
31 | #include "drm.h" | |
32 | #include "drm_crtc.h" | |
33 | #include "drm_crtc_helper.h" | |
34 | #include "intel_drv.h" | |
35 | #include "i915_drm.h" | |
36 | #include "i915_drv.h" | |
ab2c0672 | 37 | #include "drm_dp_helper.h" |
a4fc5ed6 | 38 | |
a2006cf5 | 39 | #define DP_RECEIVER_CAP_SIZE 0xf |
a4fc5ed6 KP |
40 | #define DP_LINK_STATUS_SIZE 6 |
41 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) | |
42 | ||
43 | #define DP_LINK_CONFIGURATION_SIZE 9 | |
44 | ||
ea5b213a CW |
45 | struct intel_dp { |
46 | struct intel_encoder base; | |
a4fc5ed6 KP |
47 | uint32_t output_reg; |
48 | uint32_t DP; | |
49 | uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; | |
a4fc5ed6 | 50 | bool has_audio; |
f684960e | 51 | int force_audio; |
e953fd7b | 52 | uint32_t color_range; |
d2b996ac | 53 | int dpms_mode; |
a4fc5ed6 KP |
54 | uint8_t link_bw; |
55 | uint8_t lane_count; | |
a2006cf5 | 56 | uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; |
a4fc5ed6 KP |
57 | struct i2c_adapter adapter; |
58 | struct i2c_algo_dp_aux_data algo; | |
f0917379 | 59 | bool is_pch_edp; |
33a34e4e | 60 | uint8_t train_set[4]; |
f01eca2e KP |
61 | int panel_power_up_delay; |
62 | int panel_power_down_delay; | |
63 | int panel_power_cycle_delay; | |
64 | int backlight_on_delay; | |
65 | int backlight_off_delay; | |
d15456de | 66 | struct drm_display_mode *panel_fixed_mode; /* for eDP */ |
bd943159 KP |
67 | struct delayed_work panel_vdd_work; |
68 | bool want_panel_vdd; | |
a4fc5ed6 KP |
69 | }; |
70 | ||
cfcb0fc9 JB |
71 | /** |
72 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
73 | * @intel_dp: DP struct | |
74 | * | |
75 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
76 | * will return true, and false otherwise. | |
77 | */ | |
78 | static bool is_edp(struct intel_dp *intel_dp) | |
79 | { | |
80 | return intel_dp->base.type == INTEL_OUTPUT_EDP; | |
81 | } | |
82 | ||
83 | /** | |
84 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? | |
85 | * @intel_dp: DP struct | |
86 | * | |
87 | * Returns true if the given DP struct corresponds to a PCH DP port attached | |
88 | * to an eDP panel, false otherwise. Helpful for determining whether we | |
89 | * may need FDI resources for a given DP output or not. | |
90 | */ | |
91 | static bool is_pch_edp(struct intel_dp *intel_dp) | |
92 | { | |
93 | return intel_dp->is_pch_edp; | |
94 | } | |
95 | ||
1c95822a AJ |
96 | /** |
97 | * is_cpu_edp - is the port on the CPU and attached to an eDP panel? | |
98 | * @intel_dp: DP struct | |
99 | * | |
100 | * Returns true if the given DP struct corresponds to a CPU eDP port. | |
101 | */ | |
102 | static bool is_cpu_edp(struct intel_dp *intel_dp) | |
103 | { | |
104 | return is_edp(intel_dp) && !is_pch_edp(intel_dp); | |
105 | } | |
106 | ||
ea5b213a CW |
107 | static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) |
108 | { | |
4ef69c7a | 109 | return container_of(encoder, struct intel_dp, base.base); |
ea5b213a | 110 | } |
a4fc5ed6 | 111 | |
df0e9248 CW |
112 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
113 | { | |
114 | return container_of(intel_attached_encoder(connector), | |
115 | struct intel_dp, base); | |
116 | } | |
117 | ||
814948ad JB |
118 | /** |
119 | * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? | |
120 | * @encoder: DRM encoder | |
121 | * | |
122 | * Return true if @encoder corresponds to a PCH attached eDP panel. Needed | |
123 | * by intel_display.c. | |
124 | */ | |
125 | bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) | |
126 | { | |
127 | struct intel_dp *intel_dp; | |
128 | ||
129 | if (!encoder) | |
130 | return false; | |
131 | ||
132 | intel_dp = enc_to_intel_dp(encoder); | |
133 | ||
134 | return is_pch_edp(intel_dp); | |
135 | } | |
136 | ||
33a34e4e JB |
137 | static void intel_dp_start_link_train(struct intel_dp *intel_dp); |
138 | static void intel_dp_complete_link_train(struct intel_dp *intel_dp); | |
ea5b213a | 139 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
a4fc5ed6 | 140 | |
32f9d658 | 141 | void |
0206e353 | 142 | intel_edp_link_config(struct intel_encoder *intel_encoder, |
ea5b213a | 143 | int *lane_num, int *link_bw) |
32f9d658 | 144 | { |
ea5b213a | 145 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
32f9d658 | 146 | |
ea5b213a CW |
147 | *lane_num = intel_dp->lane_count; |
148 | if (intel_dp->link_bw == DP_LINK_BW_1_62) | |
32f9d658 | 149 | *link_bw = 162000; |
ea5b213a | 150 | else if (intel_dp->link_bw == DP_LINK_BW_2_7) |
32f9d658 ZW |
151 | *link_bw = 270000; |
152 | } | |
153 | ||
a4fc5ed6 | 154 | static int |
ea5b213a | 155 | intel_dp_max_lane_count(struct intel_dp *intel_dp) |
a4fc5ed6 | 156 | { |
a4fc5ed6 KP |
157 | int max_lane_count = 4; |
158 | ||
7183dc29 JB |
159 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
160 | max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f; | |
a4fc5ed6 KP |
161 | switch (max_lane_count) { |
162 | case 1: case 2: case 4: | |
163 | break; | |
164 | default: | |
165 | max_lane_count = 4; | |
166 | } | |
167 | } | |
168 | return max_lane_count; | |
169 | } | |
170 | ||
171 | static int | |
ea5b213a | 172 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 173 | { |
7183dc29 | 174 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
175 | |
176 | switch (max_link_bw) { | |
177 | case DP_LINK_BW_1_62: | |
178 | case DP_LINK_BW_2_7: | |
179 | break; | |
180 | default: | |
181 | max_link_bw = DP_LINK_BW_1_62; | |
182 | break; | |
183 | } | |
184 | return max_link_bw; | |
185 | } | |
186 | ||
187 | static int | |
188 | intel_dp_link_clock(uint8_t link_bw) | |
189 | { | |
190 | if (link_bw == DP_LINK_BW_2_7) | |
191 | return 270000; | |
192 | else | |
193 | return 162000; | |
194 | } | |
195 | ||
cd9dde44 AJ |
196 | /* |
197 | * The units on the numbers in the next two are... bizarre. Examples will | |
198 | * make it clearer; this one parallels an example in the eDP spec. | |
199 | * | |
200 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: | |
201 | * | |
202 | * 270000 * 1 * 8 / 10 == 216000 | |
203 | * | |
204 | * The actual data capacity of that configuration is 2.16Gbit/s, so the | |
205 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - | |
206 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be | |
207 | * 119000. At 18bpp that's 2142000 kilobits per second. | |
208 | * | |
209 | * Thus the strange-looking division by 10 in intel_dp_link_required, to | |
210 | * get the result in decakilobits instead of kilobits. | |
211 | */ | |
212 | ||
a4fc5ed6 | 213 | static int |
cd9dde44 | 214 | intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock) |
a4fc5ed6 | 215 | { |
89c61432 JB |
216 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
217 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
218 | int bpp = 24; | |
885a5fb5 | 219 | |
89c61432 JB |
220 | if (intel_crtc) |
221 | bpp = intel_crtc->bpp; | |
222 | ||
cd9dde44 | 223 | return (pixel_clock * bpp + 9) / 10; |
a4fc5ed6 KP |
224 | } |
225 | ||
fe27d53e DA |
226 | static int |
227 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
228 | { | |
229 | return (max_link_clock * max_lanes * 8) / 10; | |
230 | } | |
231 | ||
a4fc5ed6 KP |
232 | static int |
233 | intel_dp_mode_valid(struct drm_connector *connector, | |
234 | struct drm_display_mode *mode) | |
235 | { | |
df0e9248 | 236 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
ea5b213a CW |
237 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
238 | int max_lanes = intel_dp_max_lane_count(intel_dp); | |
a4fc5ed6 | 239 | |
d15456de KP |
240 | if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
241 | if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay) | |
7de56f43 ZY |
242 | return MODE_PANEL; |
243 | ||
d15456de | 244 | if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay) |
7de56f43 ZY |
245 | return MODE_PANEL; |
246 | } | |
247 | ||
dc22ee6f AJ |
248 | if (intel_dp_link_required(intel_dp, mode->clock) |
249 | > intel_dp_max_data_rate(max_link_clock, max_lanes)) | |
a4fc5ed6 KP |
250 | return MODE_CLOCK_HIGH; |
251 | ||
252 | if (mode->clock < 10000) | |
253 | return MODE_CLOCK_LOW; | |
254 | ||
255 | return MODE_OK; | |
256 | } | |
257 | ||
258 | static uint32_t | |
259 | pack_aux(uint8_t *src, int src_bytes) | |
260 | { | |
261 | int i; | |
262 | uint32_t v = 0; | |
263 | ||
264 | if (src_bytes > 4) | |
265 | src_bytes = 4; | |
266 | for (i = 0; i < src_bytes; i++) | |
267 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
268 | return v; | |
269 | } | |
270 | ||
271 | static void | |
272 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
273 | { | |
274 | int i; | |
275 | if (dst_bytes > 4) | |
276 | dst_bytes = 4; | |
277 | for (i = 0; i < dst_bytes; i++) | |
278 | dst[i] = src >> ((3-i) * 8); | |
279 | } | |
280 | ||
fb0f8fbf KP |
281 | /* hrawclock is 1/4 the FSB frequency */ |
282 | static int | |
283 | intel_hrawclk(struct drm_device *dev) | |
284 | { | |
285 | struct drm_i915_private *dev_priv = dev->dev_private; | |
286 | uint32_t clkcfg; | |
287 | ||
288 | clkcfg = I915_READ(CLKCFG); | |
289 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
290 | case CLKCFG_FSB_400: | |
291 | return 100; | |
292 | case CLKCFG_FSB_533: | |
293 | return 133; | |
294 | case CLKCFG_FSB_667: | |
295 | return 166; | |
296 | case CLKCFG_FSB_800: | |
297 | return 200; | |
298 | case CLKCFG_FSB_1067: | |
299 | return 266; | |
300 | case CLKCFG_FSB_1333: | |
301 | return 333; | |
302 | /* these two are just a guess; one of them might be right */ | |
303 | case CLKCFG_FSB_1600: | |
304 | case CLKCFG_FSB_1600_ALT: | |
305 | return 400; | |
306 | default: | |
307 | return 133; | |
308 | } | |
309 | } | |
310 | ||
ebf33b18 KP |
311 | static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) |
312 | { | |
313 | struct drm_device *dev = intel_dp->base.base.dev; | |
314 | struct drm_i915_private *dev_priv = dev->dev_private; | |
315 | ||
316 | return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; | |
317 | } | |
318 | ||
319 | static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) | |
320 | { | |
321 | struct drm_device *dev = intel_dp->base.base.dev; | |
322 | struct drm_i915_private *dev_priv = dev->dev_private; | |
323 | ||
324 | return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0; | |
325 | } | |
326 | ||
9b984dae KP |
327 | static void |
328 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
329 | { | |
330 | struct drm_device *dev = intel_dp->base.base.dev; | |
331 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ebf33b18 | 332 | |
9b984dae KP |
333 | if (!is_edp(intel_dp)) |
334 | return; | |
ebf33b18 | 335 | if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
336 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
337 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
ebf33b18 | 338 | I915_READ(PCH_PP_STATUS), |
9b984dae KP |
339 | I915_READ(PCH_PP_CONTROL)); |
340 | } | |
341 | } | |
342 | ||
a4fc5ed6 | 343 | static int |
ea5b213a | 344 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
345 | uint8_t *send, int send_bytes, |
346 | uint8_t *recv, int recv_size) | |
347 | { | |
ea5b213a | 348 | uint32_t output_reg = intel_dp->output_reg; |
4ef69c7a | 349 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 KP |
350 | struct drm_i915_private *dev_priv = dev->dev_private; |
351 | uint32_t ch_ctl = output_reg + 0x10; | |
352 | uint32_t ch_data = ch_ctl + 4; | |
353 | int i; | |
354 | int recv_bytes; | |
a4fc5ed6 | 355 | uint32_t status; |
fb0f8fbf | 356 | uint32_t aux_clock_divider; |
e3421a18 | 357 | int try, precharge; |
a4fc5ed6 | 358 | |
9b984dae | 359 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 | 360 | /* The clock divider is based off the hrawclk, |
fb0f8fbf KP |
361 | * and would like to run at 2MHz. So, take the |
362 | * hrawclk value and divide by 2 and use that | |
6176b8f9 JB |
363 | * |
364 | * Note that PCH attached eDP panels should use a 125MHz input | |
365 | * clock divider. | |
a4fc5ed6 | 366 | */ |
1c95822a | 367 | if (is_cpu_edp(intel_dp)) { |
e3421a18 ZW |
368 | if (IS_GEN6(dev)) |
369 | aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */ | |
370 | else | |
371 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ | |
372 | } else if (HAS_PCH_SPLIT(dev)) | |
f2b115e6 | 373 | aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */ |
5eb08b69 ZW |
374 | else |
375 | aux_clock_divider = intel_hrawclk(dev) / 2; | |
376 | ||
e3421a18 ZW |
377 | if (IS_GEN6(dev)) |
378 | precharge = 3; | |
379 | else | |
380 | precharge = 5; | |
381 | ||
11bee43e JB |
382 | /* Try to wait for any previous AUX channel activity */ |
383 | for (try = 0; try < 3; try++) { | |
384 | status = I915_READ(ch_ctl); | |
385 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
386 | break; | |
387 | msleep(1); | |
388 | } | |
389 | ||
390 | if (try == 3) { | |
391 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
392 | I915_READ(ch_ctl)); | |
4f7f7b7e CW |
393 | return -EBUSY; |
394 | } | |
395 | ||
fb0f8fbf KP |
396 | /* Must try at least 3 times according to DP spec */ |
397 | for (try = 0; try < 5; try++) { | |
398 | /* Load the send data into the aux channel data registers */ | |
4f7f7b7e CW |
399 | for (i = 0; i < send_bytes; i += 4) |
400 | I915_WRITE(ch_data + i, | |
401 | pack_aux(send + i, send_bytes - i)); | |
0206e353 | 402 | |
fb0f8fbf | 403 | /* Send the command and wait for it to complete */ |
4f7f7b7e CW |
404 | I915_WRITE(ch_ctl, |
405 | DP_AUX_CH_CTL_SEND_BUSY | | |
406 | DP_AUX_CH_CTL_TIME_OUT_400us | | |
407 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
408 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
409 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | | |
410 | DP_AUX_CH_CTL_DONE | | |
411 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
412 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
fb0f8fbf | 413 | for (;;) { |
fb0f8fbf KP |
414 | status = I915_READ(ch_ctl); |
415 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) | |
416 | break; | |
4f7f7b7e | 417 | udelay(100); |
fb0f8fbf | 418 | } |
0206e353 | 419 | |
fb0f8fbf | 420 | /* Clear done status and any errors */ |
4f7f7b7e CW |
421 | I915_WRITE(ch_ctl, |
422 | status | | |
423 | DP_AUX_CH_CTL_DONE | | |
424 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
425 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
426 | if (status & DP_AUX_CH_CTL_DONE) | |
a4fc5ed6 KP |
427 | break; |
428 | } | |
429 | ||
a4fc5ed6 | 430 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 431 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
a5b3da54 | 432 | return -EBUSY; |
a4fc5ed6 KP |
433 | } |
434 | ||
435 | /* Check for timeout or receive error. | |
436 | * Timeouts occur when the sink is not connected | |
437 | */ | |
a5b3da54 | 438 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 439 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
a5b3da54 KP |
440 | return -EIO; |
441 | } | |
1ae8c0a5 KP |
442 | |
443 | /* Timeouts occur when the device isn't connected, so they're | |
444 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 445 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 446 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
a5b3da54 | 447 | return -ETIMEDOUT; |
a4fc5ed6 KP |
448 | } |
449 | ||
450 | /* Unload any bytes sent back from the other side */ | |
451 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
452 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
453 | if (recv_bytes > recv_size) |
454 | recv_bytes = recv_size; | |
0206e353 | 455 | |
4f7f7b7e CW |
456 | for (i = 0; i < recv_bytes; i += 4) |
457 | unpack_aux(I915_READ(ch_data + i), | |
458 | recv + i, recv_bytes - i); | |
a4fc5ed6 KP |
459 | |
460 | return recv_bytes; | |
461 | } | |
462 | ||
463 | /* Write data to the aux channel in native mode */ | |
464 | static int | |
ea5b213a | 465 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
466 | uint16_t address, uint8_t *send, int send_bytes) |
467 | { | |
468 | int ret; | |
469 | uint8_t msg[20]; | |
470 | int msg_bytes; | |
471 | uint8_t ack; | |
472 | ||
9b984dae | 473 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
474 | if (send_bytes > 16) |
475 | return -1; | |
476 | msg[0] = AUX_NATIVE_WRITE << 4; | |
477 | msg[1] = address >> 8; | |
eebc863e | 478 | msg[2] = address & 0xff; |
a4fc5ed6 KP |
479 | msg[3] = send_bytes - 1; |
480 | memcpy(&msg[4], send, send_bytes); | |
481 | msg_bytes = send_bytes + 4; | |
482 | for (;;) { | |
ea5b213a | 483 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
a4fc5ed6 KP |
484 | if (ret < 0) |
485 | return ret; | |
486 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
487 | break; | |
488 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
489 | udelay(100); | |
490 | else | |
a5b3da54 | 491 | return -EIO; |
a4fc5ed6 KP |
492 | } |
493 | return send_bytes; | |
494 | } | |
495 | ||
496 | /* Write a single byte to the aux channel in native mode */ | |
497 | static int | |
ea5b213a | 498 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
499 | uint16_t address, uint8_t byte) |
500 | { | |
ea5b213a | 501 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
a4fc5ed6 KP |
502 | } |
503 | ||
504 | /* read bytes from a native aux channel */ | |
505 | static int | |
ea5b213a | 506 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
507 | uint16_t address, uint8_t *recv, int recv_bytes) |
508 | { | |
509 | uint8_t msg[4]; | |
510 | int msg_bytes; | |
511 | uint8_t reply[20]; | |
512 | int reply_bytes; | |
513 | uint8_t ack; | |
514 | int ret; | |
515 | ||
9b984dae | 516 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
517 | msg[0] = AUX_NATIVE_READ << 4; |
518 | msg[1] = address >> 8; | |
519 | msg[2] = address & 0xff; | |
520 | msg[3] = recv_bytes - 1; | |
521 | ||
522 | msg_bytes = 4; | |
523 | reply_bytes = recv_bytes + 1; | |
524 | ||
525 | for (;;) { | |
ea5b213a | 526 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
a4fc5ed6 | 527 | reply, reply_bytes); |
a5b3da54 KP |
528 | if (ret == 0) |
529 | return -EPROTO; | |
530 | if (ret < 0) | |
a4fc5ed6 KP |
531 | return ret; |
532 | ack = reply[0]; | |
533 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { | |
534 | memcpy(recv, reply + 1, ret - 1); | |
535 | return ret - 1; | |
536 | } | |
537 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
538 | udelay(100); | |
539 | else | |
a5b3da54 | 540 | return -EIO; |
a4fc5ed6 KP |
541 | } |
542 | } | |
543 | ||
544 | static int | |
ab2c0672 DA |
545 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
546 | uint8_t write_byte, uint8_t *read_byte) | |
a4fc5ed6 | 547 | { |
ab2c0672 | 548 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
ea5b213a CW |
549 | struct intel_dp *intel_dp = container_of(adapter, |
550 | struct intel_dp, | |
551 | adapter); | |
ab2c0672 DA |
552 | uint16_t address = algo_data->address; |
553 | uint8_t msg[5]; | |
554 | uint8_t reply[2]; | |
8316f337 | 555 | unsigned retry; |
ab2c0672 DA |
556 | int msg_bytes; |
557 | int reply_bytes; | |
558 | int ret; | |
559 | ||
9b984dae | 560 | intel_dp_check_edp(intel_dp); |
ab2c0672 DA |
561 | /* Set up the command byte */ |
562 | if (mode & MODE_I2C_READ) | |
563 | msg[0] = AUX_I2C_READ << 4; | |
564 | else | |
565 | msg[0] = AUX_I2C_WRITE << 4; | |
566 | ||
567 | if (!(mode & MODE_I2C_STOP)) | |
568 | msg[0] |= AUX_I2C_MOT << 4; | |
a4fc5ed6 | 569 | |
ab2c0672 DA |
570 | msg[1] = address >> 8; |
571 | msg[2] = address; | |
572 | ||
573 | switch (mode) { | |
574 | case MODE_I2C_WRITE: | |
575 | msg[3] = 0; | |
576 | msg[4] = write_byte; | |
577 | msg_bytes = 5; | |
578 | reply_bytes = 1; | |
579 | break; | |
580 | case MODE_I2C_READ: | |
581 | msg[3] = 0; | |
582 | msg_bytes = 4; | |
583 | reply_bytes = 2; | |
584 | break; | |
585 | default: | |
586 | msg_bytes = 3; | |
587 | reply_bytes = 1; | |
588 | break; | |
589 | } | |
590 | ||
8316f337 DF |
591 | for (retry = 0; retry < 5; retry++) { |
592 | ret = intel_dp_aux_ch(intel_dp, | |
593 | msg, msg_bytes, | |
594 | reply, reply_bytes); | |
ab2c0672 | 595 | if (ret < 0) { |
3ff99164 | 596 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
ab2c0672 DA |
597 | return ret; |
598 | } | |
8316f337 DF |
599 | |
600 | switch (reply[0] & AUX_NATIVE_REPLY_MASK) { | |
601 | case AUX_NATIVE_REPLY_ACK: | |
602 | /* I2C-over-AUX Reply field is only valid | |
603 | * when paired with AUX ACK. | |
604 | */ | |
605 | break; | |
606 | case AUX_NATIVE_REPLY_NACK: | |
607 | DRM_DEBUG_KMS("aux_ch native nack\n"); | |
608 | return -EREMOTEIO; | |
609 | case AUX_NATIVE_REPLY_DEFER: | |
610 | udelay(100); | |
611 | continue; | |
612 | default: | |
613 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", | |
614 | reply[0]); | |
615 | return -EREMOTEIO; | |
616 | } | |
617 | ||
ab2c0672 DA |
618 | switch (reply[0] & AUX_I2C_REPLY_MASK) { |
619 | case AUX_I2C_REPLY_ACK: | |
620 | if (mode == MODE_I2C_READ) { | |
621 | *read_byte = reply[1]; | |
622 | } | |
623 | return reply_bytes - 1; | |
624 | case AUX_I2C_REPLY_NACK: | |
8316f337 | 625 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
ab2c0672 DA |
626 | return -EREMOTEIO; |
627 | case AUX_I2C_REPLY_DEFER: | |
8316f337 | 628 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
ab2c0672 DA |
629 | udelay(100); |
630 | break; | |
631 | default: | |
8316f337 | 632 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
ab2c0672 DA |
633 | return -EREMOTEIO; |
634 | } | |
635 | } | |
8316f337 DF |
636 | |
637 | DRM_ERROR("too many retries, giving up\n"); | |
638 | return -EREMOTEIO; | |
a4fc5ed6 KP |
639 | } |
640 | ||
0b5c541b | 641 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
bd943159 | 642 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
0b5c541b | 643 | |
a4fc5ed6 | 644 | static int |
ea5b213a | 645 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
55f78c43 | 646 | struct intel_connector *intel_connector, const char *name) |
a4fc5ed6 | 647 | { |
0b5c541b KP |
648 | int ret; |
649 | ||
d54e9d28 | 650 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
ea5b213a CW |
651 | intel_dp->algo.running = false; |
652 | intel_dp->algo.address = 0; | |
653 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | |
654 | ||
0206e353 | 655 | memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); |
ea5b213a CW |
656 | intel_dp->adapter.owner = THIS_MODULE; |
657 | intel_dp->adapter.class = I2C_CLASS_DDC; | |
0206e353 | 658 | strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); |
ea5b213a CW |
659 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; |
660 | intel_dp->adapter.algo_data = &intel_dp->algo; | |
661 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; | |
662 | ||
0b5c541b KP |
663 | ironlake_edp_panel_vdd_on(intel_dp); |
664 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); | |
bd943159 | 665 | ironlake_edp_panel_vdd_off(intel_dp, false); |
0b5c541b | 666 | return ret; |
a4fc5ed6 KP |
667 | } |
668 | ||
669 | static bool | |
670 | intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
671 | struct drm_display_mode *adjusted_mode) | |
672 | { | |
0d3a1bee | 673 | struct drm_device *dev = encoder->dev; |
ea5b213a | 674 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
a4fc5ed6 | 675 | int lane_count, clock; |
ea5b213a CW |
676 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
677 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; | |
a4fc5ed6 KP |
678 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
679 | ||
d15456de KP |
680 | if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) { |
681 | intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode); | |
1d8e1c75 CW |
682 | intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, |
683 | mode, adjusted_mode); | |
0d3a1bee ZY |
684 | /* |
685 | * the mode->clock is used to calculate the Data&Link M/N | |
686 | * of the pipe. For the eDP the fixed clock should be used. | |
687 | */ | |
d15456de | 688 | mode->clock = intel_dp->panel_fixed_mode->clock; |
0d3a1bee ZY |
689 | } |
690 | ||
a4fc5ed6 KP |
691 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
692 | for (clock = 0; clock <= max_clock; clock++) { | |
fe27d53e | 693 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
a4fc5ed6 | 694 | |
cd9dde44 | 695 | if (intel_dp_link_required(intel_dp, mode->clock) |
885a5fb5 | 696 | <= link_avail) { |
ea5b213a CW |
697 | intel_dp->link_bw = bws[clock]; |
698 | intel_dp->lane_count = lane_count; | |
699 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); | |
28c97730 ZY |
700 | DRM_DEBUG_KMS("Display port link bw %02x lane " |
701 | "count %d clock %d\n", | |
ea5b213a | 702 | intel_dp->link_bw, intel_dp->lane_count, |
a4fc5ed6 KP |
703 | adjusted_mode->clock); |
704 | return true; | |
705 | } | |
706 | } | |
707 | } | |
fe27d53e | 708 | |
a4fc5ed6 KP |
709 | return false; |
710 | } | |
711 | ||
712 | struct intel_dp_m_n { | |
713 | uint32_t tu; | |
714 | uint32_t gmch_m; | |
715 | uint32_t gmch_n; | |
716 | uint32_t link_m; | |
717 | uint32_t link_n; | |
718 | }; | |
719 | ||
720 | static void | |
721 | intel_reduce_ratio(uint32_t *num, uint32_t *den) | |
722 | { | |
723 | while (*num > 0xffffff || *den > 0xffffff) { | |
724 | *num >>= 1; | |
725 | *den >>= 1; | |
726 | } | |
727 | } | |
728 | ||
729 | static void | |
36e83a18 | 730 | intel_dp_compute_m_n(int bpp, |
a4fc5ed6 KP |
731 | int nlanes, |
732 | int pixel_clock, | |
733 | int link_clock, | |
734 | struct intel_dp_m_n *m_n) | |
735 | { | |
736 | m_n->tu = 64; | |
36e83a18 | 737 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
a4fc5ed6 KP |
738 | m_n->gmch_n = link_clock * nlanes; |
739 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); | |
740 | m_n->link_m = pixel_clock; | |
741 | m_n->link_n = link_clock; | |
742 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); | |
743 | } | |
744 | ||
745 | void | |
746 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, | |
747 | struct drm_display_mode *adjusted_mode) | |
748 | { | |
749 | struct drm_device *dev = crtc->dev; | |
750 | struct drm_mode_config *mode_config = &dev->mode_config; | |
55f78c43 | 751 | struct drm_encoder *encoder; |
a4fc5ed6 KP |
752 | struct drm_i915_private *dev_priv = dev->dev_private; |
753 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
858fa035 | 754 | int lane_count = 4; |
a4fc5ed6 | 755 | struct intel_dp_m_n m_n; |
9db4a9c7 | 756 | int pipe = intel_crtc->pipe; |
a4fc5ed6 KP |
757 | |
758 | /* | |
21d40d37 | 759 | * Find the lane count in the intel_encoder private |
a4fc5ed6 | 760 | */ |
55f78c43 | 761 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { |
ea5b213a | 762 | struct intel_dp *intel_dp; |
a4fc5ed6 | 763 | |
d8201ab6 | 764 | if (encoder->crtc != crtc) |
a4fc5ed6 KP |
765 | continue; |
766 | ||
ea5b213a | 767 | intel_dp = enc_to_intel_dp(encoder); |
417e822d | 768 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || is_pch_edp(intel_dp)) { |
ea5b213a | 769 | lane_count = intel_dp->lane_count; |
51190667 | 770 | break; |
417e822d | 771 | } else if (is_cpu_edp(intel_dp)) { |
51190667 | 772 | lane_count = dev_priv->edp.lanes; |
a4fc5ed6 KP |
773 | break; |
774 | } | |
775 | } | |
776 | ||
777 | /* | |
778 | * Compute the GMCH and Link ratios. The '3' here is | |
779 | * the number of bytes_per_pixel post-LUT, which we always | |
780 | * set up for 8-bits of R/G/B, or 3 bytes total. | |
781 | */ | |
858fa035 | 782 | intel_dp_compute_m_n(intel_crtc->bpp, lane_count, |
a4fc5ed6 KP |
783 | mode->clock, adjusted_mode->clock, &m_n); |
784 | ||
c619eed4 | 785 | if (HAS_PCH_SPLIT(dev)) { |
9db4a9c7 JB |
786 | I915_WRITE(TRANSDATA_M1(pipe), |
787 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
788 | m_n.gmch_m); | |
789 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); | |
790 | I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); | |
791 | I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); | |
a4fc5ed6 | 792 | } else { |
9db4a9c7 JB |
793 | I915_WRITE(PIPE_GMCH_DATA_M(pipe), |
794 | ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) | | |
795 | m_n.gmch_m); | |
796 | I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); | |
797 | I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); | |
798 | I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); | |
a4fc5ed6 KP |
799 | } |
800 | } | |
801 | ||
f01eca2e KP |
802 | static void ironlake_edp_pll_on(struct drm_encoder *encoder); |
803 | static void ironlake_edp_pll_off(struct drm_encoder *encoder); | |
804 | ||
a4fc5ed6 KP |
805 | static void |
806 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
807 | struct drm_display_mode *adjusted_mode) | |
808 | { | |
e3421a18 | 809 | struct drm_device *dev = encoder->dev; |
417e822d | 810 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 811 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
4ef69c7a | 812 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
a4fc5ed6 KP |
813 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
814 | ||
f01eca2e KP |
815 | /* Turn on the eDP PLL if needed */ |
816 | if (is_edp(intel_dp)) { | |
817 | if (!is_pch_edp(intel_dp)) | |
818 | ironlake_edp_pll_on(encoder); | |
819 | else | |
820 | ironlake_edp_pll_off(encoder); | |
821 | } | |
822 | ||
417e822d KP |
823 | /* |
824 | * There are three kinds of DP registers: | |
825 | * | |
826 | * IBX PCH | |
827 | * CPU | |
828 | * CPT PCH | |
829 | * | |
830 | * IBX PCH and CPU are the same for almost everything, | |
831 | * except that the CPU DP PLL is configured in this | |
832 | * register | |
833 | * | |
834 | * CPT PCH is quite different, having many bits moved | |
835 | * to the TRANS_DP_CTL register instead. That | |
836 | * configuration happens (oddly) in ironlake_pch_enable | |
837 | */ | |
9c9e7927 | 838 | |
417e822d KP |
839 | /* Preserve the BIOS-computed detected bit. This is |
840 | * supposed to be read-only. | |
841 | */ | |
842 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
843 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
a4fc5ed6 | 844 | |
417e822d KP |
845 | /* Handle DP bits in common between all three register formats */ |
846 | ||
847 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
a4fc5ed6 | 848 | |
ea5b213a | 849 | switch (intel_dp->lane_count) { |
a4fc5ed6 | 850 | case 1: |
ea5b213a | 851 | intel_dp->DP |= DP_PORT_WIDTH_1; |
a4fc5ed6 KP |
852 | break; |
853 | case 2: | |
ea5b213a | 854 | intel_dp->DP |= DP_PORT_WIDTH_2; |
a4fc5ed6 KP |
855 | break; |
856 | case 4: | |
ea5b213a | 857 | intel_dp->DP |= DP_PORT_WIDTH_4; |
a4fc5ed6 KP |
858 | break; |
859 | } | |
e0dac65e WF |
860 | if (intel_dp->has_audio) { |
861 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", | |
862 | pipe_name(intel_crtc->pipe)); | |
ea5b213a | 863 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
e0dac65e WF |
864 | intel_write_eld(encoder, adjusted_mode); |
865 | } | |
ea5b213a CW |
866 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
867 | intel_dp->link_configuration[0] = intel_dp->link_bw; | |
868 | intel_dp->link_configuration[1] = intel_dp->lane_count; | |
a2cab1b2 | 869 | intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; |
a4fc5ed6 | 870 | /* |
9962c925 | 871 | * Check for DPCD version > 1.1 and enhanced framing support |
a4fc5ed6 | 872 | */ |
7183dc29 JB |
873 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
874 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { | |
ea5b213a | 875 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
a4fc5ed6 KP |
876 | } |
877 | ||
417e822d | 878 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 879 | |
417e822d KP |
880 | if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { |
881 | intel_dp->DP |= intel_dp->color_range; | |
882 | ||
883 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
884 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
885 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
886 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
887 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
888 | ||
889 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) | |
890 | intel_dp->DP |= DP_ENHANCED_FRAMING; | |
891 | ||
892 | if (intel_crtc->pipe == 1) | |
893 | intel_dp->DP |= DP_PIPEB_SELECT; | |
894 | ||
895 | if (is_cpu_edp(intel_dp)) { | |
896 | /* don't miss out required setting for eDP */ | |
897 | intel_dp->DP |= DP_PLL_ENABLE; | |
898 | if (adjusted_mode->clock < 200000) | |
899 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; | |
900 | else | |
901 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
902 | } | |
903 | } else { | |
904 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
32f9d658 | 905 | } |
a4fc5ed6 KP |
906 | } |
907 | ||
99ea7127 KP |
908 | #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
909 | #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
910 | ||
911 | #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) | |
912 | #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
913 | ||
914 | #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) | |
915 | #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
916 | ||
917 | static void ironlake_wait_panel_status(struct intel_dp *intel_dp, | |
918 | u32 mask, | |
919 | u32 value) | |
bd943159 | 920 | { |
99ea7127 KP |
921 | struct drm_device *dev = intel_dp->base.base.dev; |
922 | struct drm_i915_private *dev_priv = dev->dev_private; | |
32ce697c | 923 | |
99ea7127 KP |
924 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
925 | mask, value, | |
926 | I915_READ(PCH_PP_STATUS), | |
927 | I915_READ(PCH_PP_CONTROL)); | |
32ce697c | 928 | |
99ea7127 KP |
929 | if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) { |
930 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", | |
931 | I915_READ(PCH_PP_STATUS), | |
932 | I915_READ(PCH_PP_CONTROL)); | |
32ce697c | 933 | } |
99ea7127 | 934 | } |
32ce697c | 935 | |
99ea7127 KP |
936 | static void ironlake_wait_panel_on(struct intel_dp *intel_dp) |
937 | { | |
938 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
939 | ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); | |
bd943159 KP |
940 | } |
941 | ||
99ea7127 KP |
942 | static void ironlake_wait_panel_off(struct intel_dp *intel_dp) |
943 | { | |
944 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
945 | ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); | |
946 | } | |
947 | ||
948 | static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp) | |
949 | { | |
950 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); | |
951 | ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); | |
952 | } | |
953 | ||
954 | ||
832dd3c1 KP |
955 | /* Read the current pp_control value, unlocking the register if it |
956 | * is locked | |
957 | */ | |
958 | ||
959 | static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv) | |
960 | { | |
961 | u32 control = I915_READ(PCH_PP_CONTROL); | |
962 | ||
963 | control &= ~PANEL_UNLOCK_MASK; | |
964 | control |= PANEL_UNLOCK_REGS; | |
965 | return control; | |
966 | } | |
967 | ||
5d613501 JB |
968 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
969 | { | |
970 | struct drm_device *dev = intel_dp->base.base.dev; | |
971 | struct drm_i915_private *dev_priv = dev->dev_private; | |
972 | u32 pp; | |
973 | ||
97af61f5 KP |
974 | if (!is_edp(intel_dp)) |
975 | return; | |
f01eca2e | 976 | DRM_DEBUG_KMS("Turn eDP VDD on\n"); |
5d613501 | 977 | |
bd943159 KP |
978 | WARN(intel_dp->want_panel_vdd, |
979 | "eDP VDD already requested on\n"); | |
980 | ||
981 | intel_dp->want_panel_vdd = true; | |
99ea7127 | 982 | |
bd943159 KP |
983 | if (ironlake_edp_have_panel_vdd(intel_dp)) { |
984 | DRM_DEBUG_KMS("eDP VDD already on\n"); | |
985 | return; | |
986 | } | |
987 | ||
99ea7127 KP |
988 | if (!ironlake_edp_have_panel_power(intel_dp)) |
989 | ironlake_wait_panel_power_cycle(intel_dp); | |
990 | ||
832dd3c1 | 991 | pp = ironlake_get_pp_control(dev_priv); |
5d613501 JB |
992 | pp |= EDP_FORCE_VDD; |
993 | I915_WRITE(PCH_PP_CONTROL, pp); | |
994 | POSTING_READ(PCH_PP_CONTROL); | |
f01eca2e KP |
995 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", |
996 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); | |
ebf33b18 KP |
997 | |
998 | /* | |
999 | * If the panel wasn't on, delay before accessing aux channel | |
1000 | */ | |
1001 | if (!ironlake_edp_have_panel_power(intel_dp)) { | |
bd943159 | 1002 | DRM_DEBUG_KMS("eDP was not running\n"); |
f01eca2e | 1003 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 1004 | } |
5d613501 JB |
1005 | } |
1006 | ||
bd943159 | 1007 | static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 JB |
1008 | { |
1009 | struct drm_device *dev = intel_dp->base.base.dev; | |
1010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1011 | u32 pp; | |
1012 | ||
bd943159 | 1013 | if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { |
832dd3c1 | 1014 | pp = ironlake_get_pp_control(dev_priv); |
bd943159 KP |
1015 | pp &= ~EDP_FORCE_VDD; |
1016 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1017 | POSTING_READ(PCH_PP_CONTROL); | |
1018 | ||
1019 | /* Make sure sequencer is idle before allowing subsequent activity */ | |
1020 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", | |
1021 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); | |
99ea7127 KP |
1022 | |
1023 | msleep(intel_dp->panel_power_down_delay); | |
bd943159 KP |
1024 | } |
1025 | } | |
5d613501 | 1026 | |
bd943159 KP |
1027 | static void ironlake_panel_vdd_work(struct work_struct *__work) |
1028 | { | |
1029 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
1030 | struct intel_dp, panel_vdd_work); | |
1031 | struct drm_device *dev = intel_dp->base.base.dev; | |
1032 | ||
627f7675 | 1033 | mutex_lock(&dev->mode_config.mutex); |
bd943159 | 1034 | ironlake_panel_vdd_off_sync(intel_dp); |
627f7675 | 1035 | mutex_unlock(&dev->mode_config.mutex); |
bd943159 KP |
1036 | } |
1037 | ||
1038 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) | |
1039 | { | |
97af61f5 KP |
1040 | if (!is_edp(intel_dp)) |
1041 | return; | |
5d613501 | 1042 | |
bd943159 KP |
1043 | DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd); |
1044 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); | |
1045 | ||
1046 | intel_dp->want_panel_vdd = false; | |
1047 | ||
1048 | if (sync) { | |
1049 | ironlake_panel_vdd_off_sync(intel_dp); | |
1050 | } else { | |
1051 | /* | |
1052 | * Queue the timer to fire a long | |
1053 | * time from now (relative to the power down delay) | |
1054 | * to keep the panel power up across a sequence of operations | |
1055 | */ | |
1056 | schedule_delayed_work(&intel_dp->panel_vdd_work, | |
1057 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); | |
1058 | } | |
5d613501 JB |
1059 | } |
1060 | ||
86a3073e | 1061 | static void ironlake_edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 1062 | { |
01cb9ea6 | 1063 | struct drm_device *dev = intel_dp->base.base.dev; |
9934c132 | 1064 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1065 | u32 pp; |
9934c132 | 1066 | |
97af61f5 | 1067 | if (!is_edp(intel_dp)) |
bd943159 | 1068 | return; |
99ea7127 KP |
1069 | |
1070 | DRM_DEBUG_KMS("Turn eDP power on\n"); | |
1071 | ||
1072 | if (ironlake_edp_have_panel_power(intel_dp)) { | |
1073 | DRM_DEBUG_KMS("eDP power already on\n"); | |
7d639f35 | 1074 | return; |
99ea7127 | 1075 | } |
9934c132 | 1076 | |
99ea7127 | 1077 | ironlake_wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 1078 | |
99ea7127 | 1079 | pp = ironlake_get_pp_control(dev_priv); |
05ce1a49 KP |
1080 | if (IS_GEN5(dev)) { |
1081 | /* ILK workaround: disable reset around power sequence */ | |
1082 | pp &= ~PANEL_POWER_RESET; | |
1083 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1084 | POSTING_READ(PCH_PP_CONTROL); | |
1085 | } | |
37c6c9b0 | 1086 | |
1c0ae80a | 1087 | pp |= POWER_TARGET_ON; |
99ea7127 KP |
1088 | if (!IS_GEN5(dev)) |
1089 | pp |= PANEL_POWER_RESET; | |
1090 | ||
9934c132 | 1091 | I915_WRITE(PCH_PP_CONTROL, pp); |
01cb9ea6 | 1092 | POSTING_READ(PCH_PP_CONTROL); |
9934c132 | 1093 | |
99ea7127 | 1094 | ironlake_wait_panel_on(intel_dp); |
9934c132 | 1095 | |
05ce1a49 KP |
1096 | if (IS_GEN5(dev)) { |
1097 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ | |
1098 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1099 | POSTING_READ(PCH_PP_CONTROL); | |
1100 | } | |
9934c132 JB |
1101 | } |
1102 | ||
99ea7127 | 1103 | static void ironlake_edp_panel_off(struct intel_dp *intel_dp) |
9934c132 | 1104 | { |
99ea7127 | 1105 | struct drm_device *dev = intel_dp->base.base.dev; |
9934c132 | 1106 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1107 | u32 pp; |
9934c132 | 1108 | |
97af61f5 KP |
1109 | if (!is_edp(intel_dp)) |
1110 | return; | |
37c6c9b0 | 1111 | |
99ea7127 | 1112 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
37c6c9b0 | 1113 | |
99ea7127 | 1114 | WARN(intel_dp->want_panel_vdd, "Cannot turn power off while VDD is on\n"); |
9934c132 | 1115 | |
99ea7127 KP |
1116 | pp = ironlake_get_pp_control(dev_priv); |
1117 | pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE); | |
1118 | I915_WRITE(PCH_PP_CONTROL, pp); | |
1119 | POSTING_READ(PCH_PP_CONTROL); | |
9934c132 | 1120 | |
99ea7127 | 1121 | ironlake_wait_panel_off(intel_dp); |
9934c132 JB |
1122 | } |
1123 | ||
86a3073e | 1124 | static void ironlake_edp_backlight_on(struct intel_dp *intel_dp) |
32f9d658 | 1125 | { |
f01eca2e | 1126 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1127 | struct drm_i915_private *dev_priv = dev->dev_private; |
1128 | u32 pp; | |
1129 | ||
f01eca2e KP |
1130 | if (!is_edp(intel_dp)) |
1131 | return; | |
1132 | ||
28c97730 | 1133 | DRM_DEBUG_KMS("\n"); |
01cb9ea6 JB |
1134 | /* |
1135 | * If we enable the backlight right away following a panel power | |
1136 | * on, we may see slight flicker as the panel syncs with the eDP | |
1137 | * link. So delay a bit to make sure the image is solid before | |
1138 | * allowing it to appear. | |
1139 | */ | |
f01eca2e | 1140 | msleep(intel_dp->backlight_on_delay); |
832dd3c1 | 1141 | pp = ironlake_get_pp_control(dev_priv); |
32f9d658 ZW |
1142 | pp |= EDP_BLC_ENABLE; |
1143 | I915_WRITE(PCH_PP_CONTROL, pp); | |
f01eca2e | 1144 | POSTING_READ(PCH_PP_CONTROL); |
32f9d658 ZW |
1145 | } |
1146 | ||
86a3073e | 1147 | static void ironlake_edp_backlight_off(struct intel_dp *intel_dp) |
32f9d658 | 1148 | { |
f01eca2e | 1149 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
1150 | struct drm_i915_private *dev_priv = dev->dev_private; |
1151 | u32 pp; | |
1152 | ||
f01eca2e KP |
1153 | if (!is_edp(intel_dp)) |
1154 | return; | |
1155 | ||
28c97730 | 1156 | DRM_DEBUG_KMS("\n"); |
832dd3c1 | 1157 | pp = ironlake_get_pp_control(dev_priv); |
32f9d658 ZW |
1158 | pp &= ~EDP_BLC_ENABLE; |
1159 | I915_WRITE(PCH_PP_CONTROL, pp); | |
f01eca2e KP |
1160 | POSTING_READ(PCH_PP_CONTROL); |
1161 | msleep(intel_dp->backlight_off_delay); | |
32f9d658 | 1162 | } |
a4fc5ed6 | 1163 | |
d240f20f JB |
1164 | static void ironlake_edp_pll_on(struct drm_encoder *encoder) |
1165 | { | |
1166 | struct drm_device *dev = encoder->dev; | |
1167 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1168 | u32 dpa_ctl; | |
1169 | ||
1170 | DRM_DEBUG_KMS("\n"); | |
1171 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 1172 | dpa_ctl |= DP_PLL_ENABLE; |
d240f20f | 1173 | I915_WRITE(DP_A, dpa_ctl); |
298b0b39 JB |
1174 | POSTING_READ(DP_A); |
1175 | udelay(200); | |
d240f20f JB |
1176 | } |
1177 | ||
1178 | static void ironlake_edp_pll_off(struct drm_encoder *encoder) | |
1179 | { | |
1180 | struct drm_device *dev = encoder->dev; | |
1181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1182 | u32 dpa_ctl; | |
1183 | ||
1184 | dpa_ctl = I915_READ(DP_A); | |
298b0b39 | 1185 | dpa_ctl &= ~DP_PLL_ENABLE; |
d240f20f | 1186 | I915_WRITE(DP_A, dpa_ctl); |
1af5fa1b | 1187 | POSTING_READ(DP_A); |
d240f20f JB |
1188 | udelay(200); |
1189 | } | |
1190 | ||
c7ad3810 JB |
1191 | /* If the sink supports it, try to set the power state appropriately */ |
1192 | static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) | |
1193 | { | |
1194 | int ret, i; | |
1195 | ||
1196 | /* Should have a valid DPCD by this point */ | |
1197 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
1198 | return; | |
1199 | ||
1200 | if (mode != DRM_MODE_DPMS_ON) { | |
1201 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, | |
1202 | DP_SET_POWER_D3); | |
1203 | if (ret != 1) | |
1204 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); | |
1205 | } else { | |
1206 | /* | |
1207 | * When turning on, we need to retry for 1ms to give the sink | |
1208 | * time to wake up. | |
1209 | */ | |
1210 | for (i = 0; i < 3; i++) { | |
1211 | ret = intel_dp_aux_native_write_1(intel_dp, | |
1212 | DP_SET_POWER, | |
1213 | DP_SET_POWER_D0); | |
1214 | if (ret == 1) | |
1215 | break; | |
1216 | msleep(1); | |
1217 | } | |
1218 | } | |
1219 | } | |
1220 | ||
d240f20f JB |
1221 | static void intel_dp_prepare(struct drm_encoder *encoder) |
1222 | { | |
1223 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
d240f20f | 1224 | |
21264c63 KP |
1225 | ironlake_edp_backlight_off(intel_dp); |
1226 | ironlake_edp_panel_off(intel_dp); | |
1227 | ||
c7ad3810 | 1228 | /* Wake up the sink first */ |
f58ff854 | 1229 | ironlake_edp_panel_vdd_on(intel_dp); |
c7ad3810 | 1230 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
21264c63 | 1231 | intel_dp_link_down(intel_dp); |
bd943159 | 1232 | ironlake_edp_panel_vdd_off(intel_dp, false); |
c7ad3810 | 1233 | |
f01eca2e KP |
1234 | /* Make sure the panel is off before trying to |
1235 | * change the mode | |
1236 | */ | |
d240f20f JB |
1237 | } |
1238 | ||
1239 | static void intel_dp_commit(struct drm_encoder *encoder) | |
1240 | { | |
1241 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
d4270e57 JB |
1242 | struct drm_device *dev = encoder->dev; |
1243 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); | |
5d613501 | 1244 | |
97af61f5 | 1245 | ironlake_edp_panel_vdd_on(intel_dp); |
f01eca2e | 1246 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 1247 | intel_dp_start_link_train(intel_dp); |
97af61f5 | 1248 | ironlake_edp_panel_on(intel_dp); |
bd943159 | 1249 | ironlake_edp_panel_vdd_off(intel_dp, true); |
33a34e4e | 1250 | intel_dp_complete_link_train(intel_dp); |
f01eca2e | 1251 | ironlake_edp_backlight_on(intel_dp); |
d2b996ac KP |
1252 | |
1253 | intel_dp->dpms_mode = DRM_MODE_DPMS_ON; | |
d4270e57 JB |
1254 | |
1255 | if (HAS_PCH_CPT(dev)) | |
1256 | intel_cpt_verify_modeset(dev, intel_crtc->pipe); | |
d240f20f JB |
1257 | } |
1258 | ||
a4fc5ed6 KP |
1259 | static void |
1260 | intel_dp_dpms(struct drm_encoder *encoder, int mode) | |
1261 | { | |
ea5b213a | 1262 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
55f78c43 | 1263 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 | 1264 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1265 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
a4fc5ed6 KP |
1266 | |
1267 | if (mode != DRM_MODE_DPMS_ON) { | |
21264c63 KP |
1268 | ironlake_edp_backlight_off(intel_dp); |
1269 | ironlake_edp_panel_off(intel_dp); | |
1270 | ||
245e2708 | 1271 | ironlake_edp_panel_vdd_on(intel_dp); |
c7ad3810 | 1272 | intel_dp_sink_dpms(intel_dp, mode); |
736085bc | 1273 | intel_dp_link_down(intel_dp); |
bd943159 | 1274 | ironlake_edp_panel_vdd_off(intel_dp, false); |
21264c63 KP |
1275 | |
1276 | if (is_cpu_edp(intel_dp)) | |
1277 | ironlake_edp_pll_off(encoder); | |
a4fc5ed6 | 1278 | } else { |
21264c63 KP |
1279 | if (is_cpu_edp(intel_dp)) |
1280 | ironlake_edp_pll_on(encoder); | |
1281 | ||
97af61f5 | 1282 | ironlake_edp_panel_vdd_on(intel_dp); |
c7ad3810 | 1283 | intel_dp_sink_dpms(intel_dp, mode); |
32f9d658 | 1284 | if (!(dp_reg & DP_PORT_EN)) { |
01cb9ea6 | 1285 | intel_dp_start_link_train(intel_dp); |
97af61f5 | 1286 | ironlake_edp_panel_on(intel_dp); |
bd943159 | 1287 | ironlake_edp_panel_vdd_off(intel_dp, true); |
33a34e4e | 1288 | intel_dp_complete_link_train(intel_dp); |
bee7eb2d | 1289 | } else |
bd943159 KP |
1290 | ironlake_edp_panel_vdd_off(intel_dp, false); |
1291 | ironlake_edp_backlight_on(intel_dp); | |
a4fc5ed6 | 1292 | } |
d2b996ac | 1293 | intel_dp->dpms_mode = mode; |
a4fc5ed6 KP |
1294 | } |
1295 | ||
1296 | /* | |
df0c237d JB |
1297 | * Native read with retry for link status and receiver capability reads for |
1298 | * cases where the sink may still be asleep. | |
a4fc5ed6 KP |
1299 | */ |
1300 | static bool | |
df0c237d JB |
1301 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
1302 | uint8_t *recv, int recv_bytes) | |
a4fc5ed6 | 1303 | { |
61da5fab JB |
1304 | int ret, i; |
1305 | ||
df0c237d JB |
1306 | /* |
1307 | * Sinks are *supposed* to come up within 1ms from an off state, | |
1308 | * but we're also supposed to retry 3 times per the spec. | |
1309 | */ | |
61da5fab | 1310 | for (i = 0; i < 3; i++) { |
df0c237d JB |
1311 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
1312 | recv_bytes); | |
1313 | if (ret == recv_bytes) | |
61da5fab JB |
1314 | return true; |
1315 | msleep(1); | |
1316 | } | |
a4fc5ed6 | 1317 | |
61da5fab | 1318 | return false; |
a4fc5ed6 KP |
1319 | } |
1320 | ||
1321 | /* | |
1322 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
1323 | * link status information | |
1324 | */ | |
1325 | static bool | |
93f62dad | 1326 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 1327 | { |
df0c237d JB |
1328 | return intel_dp_aux_native_read_retry(intel_dp, |
1329 | DP_LANE0_1_STATUS, | |
93f62dad | 1330 | link_status, |
df0c237d | 1331 | DP_LINK_STATUS_SIZE); |
a4fc5ed6 KP |
1332 | } |
1333 | ||
1334 | static uint8_t | |
1335 | intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1336 | int r) | |
1337 | { | |
1338 | return link_status[r - DP_LANE0_1_STATUS]; | |
1339 | } | |
1340 | ||
a4fc5ed6 | 1341 | static uint8_t |
93f62dad | 1342 | intel_get_adjust_request_voltage(uint8_t adjust_request[2], |
a4fc5ed6 KP |
1343 | int lane) |
1344 | { | |
a4fc5ed6 KP |
1345 | int s = ((lane & 1) ? |
1346 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : | |
1347 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); | |
93f62dad | 1348 | uint8_t l = adjust_request[lane>>1]; |
a4fc5ed6 KP |
1349 | |
1350 | return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; | |
1351 | } | |
1352 | ||
1353 | static uint8_t | |
93f62dad | 1354 | intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2], |
a4fc5ed6 KP |
1355 | int lane) |
1356 | { | |
a4fc5ed6 KP |
1357 | int s = ((lane & 1) ? |
1358 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : | |
1359 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); | |
93f62dad | 1360 | uint8_t l = adjust_request[lane>>1]; |
a4fc5ed6 KP |
1361 | |
1362 | return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; | |
1363 | } | |
1364 | ||
1365 | ||
1366 | #if 0 | |
1367 | static char *voltage_names[] = { | |
1368 | "0.4V", "0.6V", "0.8V", "1.2V" | |
1369 | }; | |
1370 | static char *pre_emph_names[] = { | |
1371 | "0dB", "3.5dB", "6dB", "9.5dB" | |
1372 | }; | |
1373 | static char *link_train_names[] = { | |
1374 | "pattern 1", "pattern 2", "idle", "off" | |
1375 | }; | |
1376 | #endif | |
1377 | ||
1378 | /* | |
1379 | * These are source-specific values; current Intel hardware supports | |
1380 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
1381 | */ | |
1382 | #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800 | |
417e822d | 1383 | #define I830_DP_VOLTAGE_MAX_CPT DP_TRAIN_VOLTAGE_SWING_1200 |
a4fc5ed6 KP |
1384 | |
1385 | static uint8_t | |
1386 | intel_dp_pre_emphasis_max(uint8_t voltage_swing) | |
1387 | { | |
1388 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1389 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1390 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1391 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1392 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1393 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1394 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1395 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1396 | default: | |
1397 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1398 | } | |
1399 | } | |
1400 | ||
1401 | static void | |
93f62dad | 1402 | intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 1403 | { |
93f62dad | 1404 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 KP |
1405 | uint8_t v = 0; |
1406 | uint8_t p = 0; | |
1407 | int lane; | |
93f62dad KP |
1408 | uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS); |
1409 | int voltage_max; | |
a4fc5ed6 | 1410 | |
33a34e4e | 1411 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
93f62dad KP |
1412 | uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane); |
1413 | uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane); | |
a4fc5ed6 KP |
1414 | |
1415 | if (this_v > v) | |
1416 | v = this_v; | |
1417 | if (this_p > p) | |
1418 | p = this_p; | |
1419 | } | |
1420 | ||
417e822d KP |
1421 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
1422 | voltage_max = I830_DP_VOLTAGE_MAX_CPT; | |
1423 | else | |
1424 | voltage_max = I830_DP_VOLTAGE_MAX; | |
1425 | if (v >= voltage_max) | |
1426 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; | |
a4fc5ed6 KP |
1427 | |
1428 | if (p >= intel_dp_pre_emphasis_max(v)) | |
1429 | p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
1430 | ||
1431 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 1432 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
1433 | } |
1434 | ||
1435 | static uint32_t | |
93f62dad | 1436 | intel_dp_signal_levels(uint8_t train_set) |
a4fc5ed6 | 1437 | { |
3cf2efb1 | 1438 | uint32_t signal_levels = 0; |
a4fc5ed6 | 1439 | |
3cf2efb1 | 1440 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
a4fc5ed6 KP |
1441 | case DP_TRAIN_VOLTAGE_SWING_400: |
1442 | default: | |
1443 | signal_levels |= DP_VOLTAGE_0_4; | |
1444 | break; | |
1445 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1446 | signal_levels |= DP_VOLTAGE_0_6; | |
1447 | break; | |
1448 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1449 | signal_levels |= DP_VOLTAGE_0_8; | |
1450 | break; | |
1451 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1452 | signal_levels |= DP_VOLTAGE_1_2; | |
1453 | break; | |
1454 | } | |
3cf2efb1 | 1455 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
a4fc5ed6 KP |
1456 | case DP_TRAIN_PRE_EMPHASIS_0: |
1457 | default: | |
1458 | signal_levels |= DP_PRE_EMPHASIS_0; | |
1459 | break; | |
1460 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
1461 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
1462 | break; | |
1463 | case DP_TRAIN_PRE_EMPHASIS_6: | |
1464 | signal_levels |= DP_PRE_EMPHASIS_6; | |
1465 | break; | |
1466 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
1467 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
1468 | break; | |
1469 | } | |
1470 | return signal_levels; | |
1471 | } | |
1472 | ||
e3421a18 ZW |
1473 | /* Gen6's DP voltage swing and pre-emphasis control */ |
1474 | static uint32_t | |
1475 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
1476 | { | |
3c5a62b5 YL |
1477 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
1478 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
1479 | switch (signal_levels) { | |
e3421a18 | 1480 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1481 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
1482 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
1483 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
1484 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; | |
e3421a18 | 1485 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
3c5a62b5 YL |
1486 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
1487 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; | |
e3421a18 | 1488 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3c5a62b5 YL |
1489 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
1490 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; | |
e3421a18 | 1491 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
1492 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
1493 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; | |
e3421a18 | 1494 | default: |
3c5a62b5 YL |
1495 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
1496 | "0x%x\n", signal_levels); | |
1497 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
1498 | } |
1499 | } | |
1500 | ||
a4fc5ed6 KP |
1501 | static uint8_t |
1502 | intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], | |
1503 | int lane) | |
1504 | { | |
a4fc5ed6 | 1505 | int s = (lane & 1) * 4; |
93f62dad | 1506 | uint8_t l = link_status[lane>>1]; |
a4fc5ed6 KP |
1507 | |
1508 | return (l >> s) & 0xf; | |
1509 | } | |
1510 | ||
1511 | /* Check for clock recovery is done on all channels */ | |
1512 | static bool | |
1513 | intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) | |
1514 | { | |
1515 | int lane; | |
1516 | uint8_t lane_status; | |
1517 | ||
1518 | for (lane = 0; lane < lane_count; lane++) { | |
1519 | lane_status = intel_get_lane_status(link_status, lane); | |
1520 | if ((lane_status & DP_LANE_CR_DONE) == 0) | |
1521 | return false; | |
1522 | } | |
1523 | return true; | |
1524 | } | |
1525 | ||
1526 | /* Check to see if channel eq is done on all channels */ | |
1527 | #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\ | |
1528 | DP_LANE_CHANNEL_EQ_DONE|\ | |
1529 | DP_LANE_SYMBOL_LOCKED) | |
1530 | static bool | |
93f62dad | 1531 | intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 KP |
1532 | { |
1533 | uint8_t lane_align; | |
1534 | uint8_t lane_status; | |
1535 | int lane; | |
1536 | ||
93f62dad | 1537 | lane_align = intel_dp_link_status(link_status, |
a4fc5ed6 KP |
1538 | DP_LANE_ALIGN_STATUS_UPDATED); |
1539 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) | |
1540 | return false; | |
33a34e4e | 1541 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
93f62dad | 1542 | lane_status = intel_get_lane_status(link_status, lane); |
a4fc5ed6 KP |
1543 | if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS) |
1544 | return false; | |
1545 | } | |
1546 | return true; | |
1547 | } | |
1548 | ||
1549 | static bool | |
ea5b213a | 1550 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
a4fc5ed6 | 1551 | uint32_t dp_reg_value, |
58e10eb9 | 1552 | uint8_t dp_train_pat) |
a4fc5ed6 | 1553 | { |
4ef69c7a | 1554 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1555 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4fc5ed6 KP |
1556 | int ret; |
1557 | ||
ea5b213a CW |
1558 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
1559 | POSTING_READ(intel_dp->output_reg); | |
a4fc5ed6 | 1560 | |
ea5b213a | 1561 | intel_dp_aux_native_write_1(intel_dp, |
a4fc5ed6 KP |
1562 | DP_TRAINING_PATTERN_SET, |
1563 | dp_train_pat); | |
1564 | ||
ea5b213a | 1565 | ret = intel_dp_aux_native_write(intel_dp, |
58e10eb9 CW |
1566 | DP_TRAINING_LANE0_SET, |
1567 | intel_dp->train_set, 4); | |
a4fc5ed6 KP |
1568 | if (ret != 4) |
1569 | return false; | |
1570 | ||
1571 | return true; | |
1572 | } | |
1573 | ||
33a34e4e | 1574 | /* Enable corresponding port and start training pattern 1 */ |
a4fc5ed6 | 1575 | static void |
33a34e4e | 1576 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 1577 | { |
4ef69c7a | 1578 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1579 | struct drm_i915_private *dev_priv = dev->dev_private; |
58e10eb9 | 1580 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc); |
a4fc5ed6 KP |
1581 | int i; |
1582 | uint8_t voltage; | |
1583 | bool clock_recovery = false; | |
a4fc5ed6 | 1584 | int tries; |
e3421a18 | 1585 | u32 reg; |
ea5b213a | 1586 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1587 | |
e8519464 AJ |
1588 | /* |
1589 | * On CPT we have to enable the port in training pattern 1, which | |
1590 | * will happen below in intel_dp_set_link_train. Otherwise, enable | |
1591 | * the port and wait for it to become active. | |
1592 | */ | |
1593 | if (!HAS_PCH_CPT(dev)) { | |
1594 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
1595 | POSTING_READ(intel_dp->output_reg); | |
1596 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1597 | } | |
a4fc5ed6 | 1598 | |
3cf2efb1 CW |
1599 | /* Write the link configuration data */ |
1600 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, | |
1601 | intel_dp->link_configuration, | |
1602 | DP_LINK_CONFIGURATION_SIZE); | |
a4fc5ed6 KP |
1603 | |
1604 | DP |= DP_PORT_EN; | |
82d16555 | 1605 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
e3421a18 ZW |
1606 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1607 | else | |
1608 | DP &= ~DP_LINK_TRAIN_MASK; | |
33a34e4e | 1609 | memset(intel_dp->train_set, 0, 4); |
a4fc5ed6 KP |
1610 | voltage = 0xff; |
1611 | tries = 0; | |
1612 | clock_recovery = false; | |
1613 | for (;;) { | |
33a34e4e | 1614 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
93f62dad | 1615 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
e3421a18 | 1616 | uint32_t signal_levels; |
417e822d KP |
1617 | |
1618 | if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { | |
33a34e4e | 1619 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1620 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1621 | } else { | |
93f62dad KP |
1622 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); |
1623 | DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels); | |
e3421a18 ZW |
1624 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1625 | } | |
a4fc5ed6 | 1626 | |
82d16555 | 1627 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
e3421a18 ZW |
1628 | reg = DP | DP_LINK_TRAIN_PAT_1_CPT; |
1629 | else | |
1630 | reg = DP | DP_LINK_TRAIN_PAT_1; | |
1631 | ||
ea5b213a | 1632 | if (!intel_dp_set_link_train(intel_dp, reg, |
81055854 AJ |
1633 | DP_TRAINING_PATTERN_1 | |
1634 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 | 1635 | break; |
a4fc5ed6 KP |
1636 | /* Set training pattern 1 */ |
1637 | ||
3cf2efb1 | 1638 | udelay(100); |
93f62dad KP |
1639 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
1640 | DRM_ERROR("failed to get link status\n"); | |
a4fc5ed6 | 1641 | break; |
93f62dad | 1642 | } |
a4fc5ed6 | 1643 | |
93f62dad KP |
1644 | if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
1645 | DRM_DEBUG_KMS("clock recovery OK\n"); | |
3cf2efb1 CW |
1646 | clock_recovery = true; |
1647 | break; | |
1648 | } | |
1649 | ||
1650 | /* Check to see if we've tried the max voltage */ | |
1651 | for (i = 0; i < intel_dp->lane_count; i++) | |
1652 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
a4fc5ed6 | 1653 | break; |
3cf2efb1 CW |
1654 | if (i == intel_dp->lane_count) |
1655 | break; | |
a4fc5ed6 | 1656 | |
3cf2efb1 CW |
1657 | /* Check to see if we've tried the same voltage 5 times */ |
1658 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { | |
1659 | ++tries; | |
1660 | if (tries == 5) | |
a4fc5ed6 | 1661 | break; |
3cf2efb1 CW |
1662 | } else |
1663 | tries = 0; | |
1664 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
a4fc5ed6 | 1665 | |
3cf2efb1 | 1666 | /* Compute new intel_dp->train_set as requested by target */ |
93f62dad | 1667 | intel_get_adjust_train(intel_dp, link_status); |
a4fc5ed6 KP |
1668 | } |
1669 | ||
33a34e4e JB |
1670 | intel_dp->DP = DP; |
1671 | } | |
1672 | ||
1673 | static void | |
1674 | intel_dp_complete_link_train(struct intel_dp *intel_dp) | |
1675 | { | |
4ef69c7a | 1676 | struct drm_device *dev = intel_dp->base.base.dev; |
33a34e4e JB |
1677 | struct drm_i915_private *dev_priv = dev->dev_private; |
1678 | bool channel_eq = false; | |
37f80975 | 1679 | int tries, cr_tries; |
33a34e4e JB |
1680 | u32 reg; |
1681 | uint32_t DP = intel_dp->DP; | |
1682 | ||
a4fc5ed6 KP |
1683 | /* channel equalization */ |
1684 | tries = 0; | |
37f80975 | 1685 | cr_tries = 0; |
a4fc5ed6 KP |
1686 | channel_eq = false; |
1687 | for (;;) { | |
33a34e4e | 1688 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
e3421a18 | 1689 | uint32_t signal_levels; |
93f62dad | 1690 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
e3421a18 | 1691 | |
37f80975 JB |
1692 | if (cr_tries > 5) { |
1693 | DRM_ERROR("failed to train DP, aborting\n"); | |
1694 | intel_dp_link_down(intel_dp); | |
1695 | break; | |
1696 | } | |
1697 | ||
417e822d | 1698 | if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { |
33a34e4e | 1699 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1700 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
1701 | } else { | |
93f62dad | 1702 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); |
e3421a18 ZW |
1703 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
1704 | } | |
1705 | ||
82d16555 | 1706 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
e3421a18 ZW |
1707 | reg = DP | DP_LINK_TRAIN_PAT_2_CPT; |
1708 | else | |
1709 | reg = DP | DP_LINK_TRAIN_PAT_2; | |
a4fc5ed6 KP |
1710 | |
1711 | /* channel eq pattern */ | |
ea5b213a | 1712 | if (!intel_dp_set_link_train(intel_dp, reg, |
81055854 AJ |
1713 | DP_TRAINING_PATTERN_2 | |
1714 | DP_LINK_SCRAMBLING_DISABLE)) | |
a4fc5ed6 KP |
1715 | break; |
1716 | ||
3cf2efb1 | 1717 | udelay(400); |
93f62dad | 1718 | if (!intel_dp_get_link_status(intel_dp, link_status)) |
a4fc5ed6 | 1719 | break; |
a4fc5ed6 | 1720 | |
37f80975 | 1721 | /* Make sure clock is still ok */ |
93f62dad | 1722 | if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
37f80975 JB |
1723 | intel_dp_start_link_train(intel_dp); |
1724 | cr_tries++; | |
1725 | continue; | |
1726 | } | |
1727 | ||
93f62dad | 1728 | if (intel_channel_eq_ok(intel_dp, link_status)) { |
3cf2efb1 CW |
1729 | channel_eq = true; |
1730 | break; | |
1731 | } | |
a4fc5ed6 | 1732 | |
37f80975 JB |
1733 | /* Try 5 times, then try clock recovery if that fails */ |
1734 | if (tries > 5) { | |
1735 | intel_dp_link_down(intel_dp); | |
1736 | intel_dp_start_link_train(intel_dp); | |
1737 | tries = 0; | |
1738 | cr_tries++; | |
1739 | continue; | |
1740 | } | |
a4fc5ed6 | 1741 | |
3cf2efb1 | 1742 | /* Compute new intel_dp->train_set as requested by target */ |
93f62dad | 1743 | intel_get_adjust_train(intel_dp, link_status); |
3cf2efb1 | 1744 | ++tries; |
869184a6 | 1745 | } |
3cf2efb1 | 1746 | |
82d16555 | 1747 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
e3421a18 ZW |
1748 | reg = DP | DP_LINK_TRAIN_OFF_CPT; |
1749 | else | |
1750 | reg = DP | DP_LINK_TRAIN_OFF; | |
1751 | ||
ea5b213a CW |
1752 | I915_WRITE(intel_dp->output_reg, reg); |
1753 | POSTING_READ(intel_dp->output_reg); | |
1754 | intel_dp_aux_native_write_1(intel_dp, | |
a4fc5ed6 KP |
1755 | DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE); |
1756 | } | |
1757 | ||
1758 | static void | |
ea5b213a | 1759 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 1760 | { |
4ef69c7a | 1761 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1762 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea5b213a | 1763 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 1764 | |
1b39d6f3 CW |
1765 | if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) |
1766 | return; | |
1767 | ||
28c97730 | 1768 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 1769 | |
cfcb0fc9 | 1770 | if (is_edp(intel_dp)) { |
32f9d658 | 1771 | DP &= ~DP_PLL_ENABLE; |
ea5b213a CW |
1772 | I915_WRITE(intel_dp->output_reg, DP); |
1773 | POSTING_READ(intel_dp->output_reg); | |
32f9d658 ZW |
1774 | udelay(100); |
1775 | } | |
1776 | ||
82d16555 | 1777 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) { |
e3421a18 | 1778 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a | 1779 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
e3421a18 ZW |
1780 | } else { |
1781 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a | 1782 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
e3421a18 | 1783 | } |
fe255d00 | 1784 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 1785 | |
fe255d00 | 1786 | msleep(17); |
5eb08b69 | 1787 | |
417e822d KP |
1788 | if (is_edp(intel_dp)) { |
1789 | if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) | |
1790 | DP |= DP_LINK_TRAIN_OFF_CPT; | |
1791 | else | |
1792 | DP |= DP_LINK_TRAIN_OFF; | |
1793 | } | |
5bddd17f | 1794 | |
1b39d6f3 CW |
1795 | if (!HAS_PCH_CPT(dev) && |
1796 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { | |
31acbcc4 CW |
1797 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
1798 | ||
5bddd17f EA |
1799 | /* Hardware workaround: leaving our transcoder select |
1800 | * set to transcoder B while it's off will prevent the | |
1801 | * corresponding HDMI output on transcoder A. | |
1802 | * | |
1803 | * Combine this with another hardware workaround: | |
1804 | * transcoder select bit can only be cleared while the | |
1805 | * port is enabled. | |
1806 | */ | |
1807 | DP &= ~DP_PIPEB_SELECT; | |
1808 | I915_WRITE(intel_dp->output_reg, DP); | |
1809 | ||
1810 | /* Changes to enable or select take place the vblank | |
1811 | * after being written. | |
1812 | */ | |
31acbcc4 CW |
1813 | if (crtc == NULL) { |
1814 | /* We can arrive here never having been attached | |
1815 | * to a CRTC, for instance, due to inheriting | |
1816 | * random state from the BIOS. | |
1817 | * | |
1818 | * If the pipe is not running, play safe and | |
1819 | * wait for the clocks to stabilise before | |
1820 | * continuing. | |
1821 | */ | |
1822 | POSTING_READ(intel_dp->output_reg); | |
1823 | msleep(50); | |
1824 | } else | |
1825 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); | |
5bddd17f EA |
1826 | } |
1827 | ||
ea5b213a CW |
1828 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
1829 | POSTING_READ(intel_dp->output_reg); | |
f01eca2e | 1830 | msleep(intel_dp->panel_power_down_delay); |
a4fc5ed6 KP |
1831 | } |
1832 | ||
26d61aad KP |
1833 | static bool |
1834 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
92fd8fd1 | 1835 | { |
92fd8fd1 | 1836 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
0206e353 | 1837 | sizeof(intel_dp->dpcd)) && |
92fd8fd1 | 1838 | (intel_dp->dpcd[DP_DPCD_REV] != 0)) { |
26d61aad | 1839 | return true; |
92fd8fd1 KP |
1840 | } |
1841 | ||
26d61aad | 1842 | return false; |
92fd8fd1 KP |
1843 | } |
1844 | ||
a60f0e38 JB |
1845 | static bool |
1846 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
1847 | { | |
1848 | int ret; | |
1849 | ||
1850 | ret = intel_dp_aux_native_read_retry(intel_dp, | |
1851 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
1852 | sink_irq_vector, 1); | |
1853 | if (!ret) | |
1854 | return false; | |
1855 | ||
1856 | return true; | |
1857 | } | |
1858 | ||
1859 | static void | |
1860 | intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
1861 | { | |
1862 | /* NAK by default */ | |
1863 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK); | |
1864 | } | |
1865 | ||
a4fc5ed6 KP |
1866 | /* |
1867 | * According to DP spec | |
1868 | * 5.1.2: | |
1869 | * 1. Read DPCD | |
1870 | * 2. Configure link according to Receiver Capabilities | |
1871 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
1872 | * 4. Check link status on receipt of hot-plug interrupt | |
1873 | */ | |
1874 | ||
1875 | static void | |
ea5b213a | 1876 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 1877 | { |
a60f0e38 | 1878 | u8 sink_irq_vector; |
93f62dad | 1879 | u8 link_status[DP_LINK_STATUS_SIZE]; |
a60f0e38 | 1880 | |
d2b996ac KP |
1881 | if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON) |
1882 | return; | |
59cd09e1 | 1883 | |
4ef69c7a | 1884 | if (!intel_dp->base.base.crtc) |
a4fc5ed6 KP |
1885 | return; |
1886 | ||
92fd8fd1 | 1887 | /* Try to read receiver status if the link appears to be up */ |
93f62dad | 1888 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
ea5b213a | 1889 | intel_dp_link_down(intel_dp); |
a4fc5ed6 KP |
1890 | return; |
1891 | } | |
1892 | ||
92fd8fd1 | 1893 | /* Now read the DPCD to see if it's actually running */ |
26d61aad | 1894 | if (!intel_dp_get_dpcd(intel_dp)) { |
59cd09e1 JB |
1895 | intel_dp_link_down(intel_dp); |
1896 | return; | |
1897 | } | |
1898 | ||
a60f0e38 JB |
1899 | /* Try to read the source of the interrupt */ |
1900 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
1901 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { | |
1902 | /* Clear interrupt source */ | |
1903 | intel_dp_aux_native_write_1(intel_dp, | |
1904 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
1905 | sink_irq_vector); | |
1906 | ||
1907 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
1908 | intel_dp_handle_test_request(intel_dp); | |
1909 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
1910 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
1911 | } | |
1912 | ||
93f62dad | 1913 | if (!intel_channel_eq_ok(intel_dp, link_status)) { |
92fd8fd1 KP |
1914 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
1915 | drm_get_encoder_name(&intel_dp->base.base)); | |
33a34e4e JB |
1916 | intel_dp_start_link_train(intel_dp); |
1917 | intel_dp_complete_link_train(intel_dp); | |
1918 | } | |
a4fc5ed6 | 1919 | } |
a4fc5ed6 | 1920 | |
71ba9000 | 1921 | static enum drm_connector_status |
26d61aad | 1922 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 1923 | { |
26d61aad KP |
1924 | if (intel_dp_get_dpcd(intel_dp)) |
1925 | return connector_status_connected; | |
1926 | return connector_status_disconnected; | |
71ba9000 AJ |
1927 | } |
1928 | ||
5eb08b69 | 1929 | static enum drm_connector_status |
a9756bb5 | 1930 | ironlake_dp_detect(struct intel_dp *intel_dp) |
5eb08b69 | 1931 | { |
5eb08b69 ZW |
1932 | enum drm_connector_status status; |
1933 | ||
fe16d949 CW |
1934 | /* Can't disconnect eDP, but you can close the lid... */ |
1935 | if (is_edp(intel_dp)) { | |
1936 | status = intel_panel_detect(intel_dp->base.base.dev); | |
1937 | if (status == connector_status_unknown) | |
1938 | status = connector_status_connected; | |
1939 | return status; | |
1940 | } | |
01cb9ea6 | 1941 | |
26d61aad | 1942 | return intel_dp_detect_dpcd(intel_dp); |
5eb08b69 ZW |
1943 | } |
1944 | ||
a4fc5ed6 | 1945 | static enum drm_connector_status |
a9756bb5 | 1946 | g4x_dp_detect(struct intel_dp *intel_dp) |
a4fc5ed6 | 1947 | { |
4ef69c7a | 1948 | struct drm_device *dev = intel_dp->base.base.dev; |
a4fc5ed6 | 1949 | struct drm_i915_private *dev_priv = dev->dev_private; |
a9756bb5 | 1950 | uint32_t temp, bit; |
5eb08b69 | 1951 | |
ea5b213a | 1952 | switch (intel_dp->output_reg) { |
a4fc5ed6 KP |
1953 | case DP_B: |
1954 | bit = DPB_HOTPLUG_INT_STATUS; | |
1955 | break; | |
1956 | case DP_C: | |
1957 | bit = DPC_HOTPLUG_INT_STATUS; | |
1958 | break; | |
1959 | case DP_D: | |
1960 | bit = DPD_HOTPLUG_INT_STATUS; | |
1961 | break; | |
1962 | default: | |
1963 | return connector_status_unknown; | |
1964 | } | |
1965 | ||
1966 | temp = I915_READ(PORT_HOTPLUG_STAT); | |
1967 | ||
1968 | if ((temp & bit) == 0) | |
1969 | return connector_status_disconnected; | |
1970 | ||
26d61aad | 1971 | return intel_dp_detect_dpcd(intel_dp); |
a9756bb5 ZW |
1972 | } |
1973 | ||
8c241fef KP |
1974 | static struct edid * |
1975 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) | |
1976 | { | |
1977 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1978 | struct edid *edid; | |
1979 | ||
1980 | ironlake_edp_panel_vdd_on(intel_dp); | |
1981 | edid = drm_get_edid(connector, adapter); | |
bd943159 | 1982 | ironlake_edp_panel_vdd_off(intel_dp, false); |
8c241fef KP |
1983 | return edid; |
1984 | } | |
1985 | ||
1986 | static int | |
1987 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) | |
1988 | { | |
1989 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1990 | int ret; | |
1991 | ||
1992 | ironlake_edp_panel_vdd_on(intel_dp); | |
1993 | ret = intel_ddc_get_modes(connector, adapter); | |
bd943159 | 1994 | ironlake_edp_panel_vdd_off(intel_dp, false); |
8c241fef KP |
1995 | return ret; |
1996 | } | |
1997 | ||
1998 | ||
a9756bb5 ZW |
1999 | /** |
2000 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. | |
2001 | * | |
2002 | * \return true if DP port is connected. | |
2003 | * \return false if DP port is disconnected. | |
2004 | */ | |
2005 | static enum drm_connector_status | |
2006 | intel_dp_detect(struct drm_connector *connector, bool force) | |
2007 | { | |
2008 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
2009 | struct drm_device *dev = intel_dp->base.base.dev; | |
2010 | enum drm_connector_status status; | |
2011 | struct edid *edid = NULL; | |
2012 | ||
2013 | intel_dp->has_audio = false; | |
2014 | ||
2015 | if (HAS_PCH_SPLIT(dev)) | |
2016 | status = ironlake_dp_detect(intel_dp); | |
2017 | else | |
2018 | status = g4x_dp_detect(intel_dp); | |
1b9be9d0 | 2019 | |
ac66ae83 AJ |
2020 | DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n", |
2021 | intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2], | |
2022 | intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5], | |
2023 | intel_dp->dpcd[6], intel_dp->dpcd[7]); | |
1b9be9d0 | 2024 | |
a9756bb5 ZW |
2025 | if (status != connector_status_connected) |
2026 | return status; | |
2027 | ||
f684960e CW |
2028 | if (intel_dp->force_audio) { |
2029 | intel_dp->has_audio = intel_dp->force_audio > 0; | |
2030 | } else { | |
8c241fef | 2031 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
f684960e CW |
2032 | if (edid) { |
2033 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
2034 | connector->display_info.raw_edid = NULL; | |
2035 | kfree(edid); | |
2036 | } | |
a9756bb5 ZW |
2037 | } |
2038 | ||
2039 | return connector_status_connected; | |
a4fc5ed6 KP |
2040 | } |
2041 | ||
2042 | static int intel_dp_get_modes(struct drm_connector *connector) | |
2043 | { | |
df0e9248 | 2044 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
4ef69c7a | 2045 | struct drm_device *dev = intel_dp->base.base.dev; |
32f9d658 ZW |
2046 | struct drm_i915_private *dev_priv = dev->dev_private; |
2047 | int ret; | |
a4fc5ed6 KP |
2048 | |
2049 | /* We should parse the EDID data and find out if it has an audio sink | |
2050 | */ | |
2051 | ||
8c241fef | 2052 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
b9efc480 | 2053 | if (ret) { |
d15456de | 2054 | if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) { |
b9efc480 ZY |
2055 | struct drm_display_mode *newmode; |
2056 | list_for_each_entry(newmode, &connector->probed_modes, | |
2057 | head) { | |
d15456de KP |
2058 | if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) { |
2059 | intel_dp->panel_fixed_mode = | |
b9efc480 ZY |
2060 | drm_mode_duplicate(dev, newmode); |
2061 | break; | |
2062 | } | |
2063 | } | |
2064 | } | |
32f9d658 | 2065 | return ret; |
b9efc480 | 2066 | } |
32f9d658 ZW |
2067 | |
2068 | /* if eDP has no EDID, try to use fixed panel mode from VBT */ | |
4d926461 | 2069 | if (is_edp(intel_dp)) { |
47f0eb22 | 2070 | /* initialize panel mode from VBT if available for eDP */ |
d15456de KP |
2071 | if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) { |
2072 | intel_dp->panel_fixed_mode = | |
47f0eb22 | 2073 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
d15456de KP |
2074 | if (intel_dp->panel_fixed_mode) { |
2075 | intel_dp->panel_fixed_mode->type |= | |
47f0eb22 KP |
2076 | DRM_MODE_TYPE_PREFERRED; |
2077 | } | |
2078 | } | |
d15456de | 2079 | if (intel_dp->panel_fixed_mode) { |
32f9d658 | 2080 | struct drm_display_mode *mode; |
d15456de | 2081 | mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode); |
32f9d658 ZW |
2082 | drm_mode_probed_add(connector, mode); |
2083 | return 1; | |
2084 | } | |
2085 | } | |
2086 | return 0; | |
a4fc5ed6 KP |
2087 | } |
2088 | ||
1aad7ac0 CW |
2089 | static bool |
2090 | intel_dp_detect_audio(struct drm_connector *connector) | |
2091 | { | |
2092 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
2093 | struct edid *edid; | |
2094 | bool has_audio = false; | |
2095 | ||
8c241fef | 2096 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
1aad7ac0 CW |
2097 | if (edid) { |
2098 | has_audio = drm_detect_monitor_audio(edid); | |
2099 | ||
2100 | connector->display_info.raw_edid = NULL; | |
2101 | kfree(edid); | |
2102 | } | |
2103 | ||
2104 | return has_audio; | |
2105 | } | |
2106 | ||
f684960e CW |
2107 | static int |
2108 | intel_dp_set_property(struct drm_connector *connector, | |
2109 | struct drm_property *property, | |
2110 | uint64_t val) | |
2111 | { | |
e953fd7b | 2112 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
f684960e CW |
2113 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
2114 | int ret; | |
2115 | ||
2116 | ret = drm_connector_property_set_value(connector, property, val); | |
2117 | if (ret) | |
2118 | return ret; | |
2119 | ||
3f43c48d | 2120 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
2121 | int i = val; |
2122 | bool has_audio; | |
2123 | ||
2124 | if (i == intel_dp->force_audio) | |
f684960e CW |
2125 | return 0; |
2126 | ||
1aad7ac0 | 2127 | intel_dp->force_audio = i; |
f684960e | 2128 | |
1aad7ac0 CW |
2129 | if (i == 0) |
2130 | has_audio = intel_dp_detect_audio(connector); | |
2131 | else | |
2132 | has_audio = i > 0; | |
2133 | ||
2134 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
2135 | return 0; |
2136 | ||
1aad7ac0 | 2137 | intel_dp->has_audio = has_audio; |
f684960e CW |
2138 | goto done; |
2139 | } | |
2140 | ||
e953fd7b CW |
2141 | if (property == dev_priv->broadcast_rgb_property) { |
2142 | if (val == !!intel_dp->color_range) | |
2143 | return 0; | |
2144 | ||
2145 | intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; | |
2146 | goto done; | |
2147 | } | |
2148 | ||
f684960e CW |
2149 | return -EINVAL; |
2150 | ||
2151 | done: | |
2152 | if (intel_dp->base.base.crtc) { | |
2153 | struct drm_crtc *crtc = intel_dp->base.base.crtc; | |
2154 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
2155 | crtc->x, crtc->y, | |
2156 | crtc->fb); | |
2157 | } | |
2158 | ||
2159 | return 0; | |
2160 | } | |
2161 | ||
a4fc5ed6 | 2162 | static void |
0206e353 | 2163 | intel_dp_destroy(struct drm_connector *connector) |
a4fc5ed6 | 2164 | { |
aaa6fd2a MG |
2165 | struct drm_device *dev = connector->dev; |
2166 | ||
2167 | if (intel_dpd_is_edp(dev)) | |
2168 | intel_panel_destroy_backlight(dev); | |
2169 | ||
a4fc5ed6 KP |
2170 | drm_sysfs_connector_remove(connector); |
2171 | drm_connector_cleanup(connector); | |
55f78c43 | 2172 | kfree(connector); |
a4fc5ed6 KP |
2173 | } |
2174 | ||
24d05927 DV |
2175 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
2176 | { | |
2177 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
2178 | ||
2179 | i2c_del_adapter(&intel_dp->adapter); | |
2180 | drm_encoder_cleanup(encoder); | |
bd943159 KP |
2181 | if (is_edp(intel_dp)) { |
2182 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
2183 | ironlake_panel_vdd_off_sync(intel_dp); | |
2184 | } | |
24d05927 DV |
2185 | kfree(intel_dp); |
2186 | } | |
2187 | ||
a4fc5ed6 KP |
2188 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
2189 | .dpms = intel_dp_dpms, | |
2190 | .mode_fixup = intel_dp_mode_fixup, | |
d240f20f | 2191 | .prepare = intel_dp_prepare, |
a4fc5ed6 | 2192 | .mode_set = intel_dp_mode_set, |
d240f20f | 2193 | .commit = intel_dp_commit, |
a4fc5ed6 KP |
2194 | }; |
2195 | ||
2196 | static const struct drm_connector_funcs intel_dp_connector_funcs = { | |
2197 | .dpms = drm_helper_connector_dpms, | |
a4fc5ed6 KP |
2198 | .detect = intel_dp_detect, |
2199 | .fill_modes = drm_helper_probe_single_connector_modes, | |
f684960e | 2200 | .set_property = intel_dp_set_property, |
a4fc5ed6 KP |
2201 | .destroy = intel_dp_destroy, |
2202 | }; | |
2203 | ||
2204 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
2205 | .get_modes = intel_dp_get_modes, | |
2206 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 2207 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
2208 | }; |
2209 | ||
a4fc5ed6 | 2210 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
24d05927 | 2211 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
2212 | }; |
2213 | ||
995b6762 | 2214 | static void |
21d40d37 | 2215 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 2216 | { |
ea5b213a | 2217 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
c8110e52 | 2218 | |
885a5014 | 2219 | intel_dp_check_link_status(intel_dp); |
c8110e52 | 2220 | } |
6207937d | 2221 | |
e3421a18 ZW |
2222 | /* Return which DP Port should be selected for Transcoder DP control */ |
2223 | int | |
0206e353 | 2224 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
e3421a18 ZW |
2225 | { |
2226 | struct drm_device *dev = crtc->dev; | |
2227 | struct drm_mode_config *mode_config = &dev->mode_config; | |
2228 | struct drm_encoder *encoder; | |
e3421a18 ZW |
2229 | |
2230 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
ea5b213a CW |
2231 | struct intel_dp *intel_dp; |
2232 | ||
d8201ab6 | 2233 | if (encoder->crtc != crtc) |
e3421a18 ZW |
2234 | continue; |
2235 | ||
ea5b213a | 2236 | intel_dp = enc_to_intel_dp(encoder); |
417e822d KP |
2237 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || |
2238 | intel_dp->base.type == INTEL_OUTPUT_EDP) | |
ea5b213a | 2239 | return intel_dp->output_reg; |
e3421a18 | 2240 | } |
ea5b213a | 2241 | |
e3421a18 ZW |
2242 | return -1; |
2243 | } | |
2244 | ||
36e83a18 | 2245 | /* check the VBT to see whether the eDP is on DP-D port */ |
cb0953d7 | 2246 | bool intel_dpd_is_edp(struct drm_device *dev) |
36e83a18 ZY |
2247 | { |
2248 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2249 | struct child_device_config *p_child; | |
2250 | int i; | |
2251 | ||
2252 | if (!dev_priv->child_dev_num) | |
2253 | return false; | |
2254 | ||
2255 | for (i = 0; i < dev_priv->child_dev_num; i++) { | |
2256 | p_child = dev_priv->child_dev + i; | |
2257 | ||
2258 | if (p_child->dvo_port == PORT_IDPD && | |
2259 | p_child->device_type == DEVICE_TYPE_eDP) | |
2260 | return true; | |
2261 | } | |
2262 | return false; | |
2263 | } | |
2264 | ||
f684960e CW |
2265 | static void |
2266 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) | |
2267 | { | |
3f43c48d | 2268 | intel_attach_force_audio_property(connector); |
e953fd7b | 2269 | intel_attach_broadcast_rgb_property(connector); |
f684960e CW |
2270 | } |
2271 | ||
a4fc5ed6 KP |
2272 | void |
2273 | intel_dp_init(struct drm_device *dev, int output_reg) | |
2274 | { | |
2275 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2276 | struct drm_connector *connector; | |
ea5b213a | 2277 | struct intel_dp *intel_dp; |
21d40d37 | 2278 | struct intel_encoder *intel_encoder; |
55f78c43 | 2279 | struct intel_connector *intel_connector; |
5eb08b69 | 2280 | const char *name = NULL; |
b329530c | 2281 | int type; |
a4fc5ed6 | 2282 | |
ea5b213a CW |
2283 | intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); |
2284 | if (!intel_dp) | |
a4fc5ed6 KP |
2285 | return; |
2286 | ||
3d3dc149 | 2287 | intel_dp->output_reg = output_reg; |
d2b996ac | 2288 | intel_dp->dpms_mode = -1; |
3d3dc149 | 2289 | |
55f78c43 ZW |
2290 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
2291 | if (!intel_connector) { | |
ea5b213a | 2292 | kfree(intel_dp); |
55f78c43 ZW |
2293 | return; |
2294 | } | |
ea5b213a | 2295 | intel_encoder = &intel_dp->base; |
55f78c43 | 2296 | |
ea5b213a | 2297 | if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) |
b329530c | 2298 | if (intel_dpd_is_edp(dev)) |
ea5b213a | 2299 | intel_dp->is_pch_edp = true; |
b329530c | 2300 | |
cfcb0fc9 | 2301 | if (output_reg == DP_A || is_pch_edp(intel_dp)) { |
b329530c AJ |
2302 | type = DRM_MODE_CONNECTOR_eDP; |
2303 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
2304 | } else { | |
2305 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
2306 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
2307 | } | |
2308 | ||
55f78c43 | 2309 | connector = &intel_connector->base; |
b329530c | 2310 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
2311 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
2312 | ||
eb1f8e4f DA |
2313 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
2314 | ||
652af9d7 | 2315 | if (output_reg == DP_B || output_reg == PCH_DP_B) |
21d40d37 | 2316 | intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT); |
652af9d7 | 2317 | else if (output_reg == DP_C || output_reg == PCH_DP_C) |
21d40d37 | 2318 | intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT); |
652af9d7 | 2319 | else if (output_reg == DP_D || output_reg == PCH_DP_D) |
21d40d37 | 2320 | intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT); |
f8aed700 | 2321 | |
bd943159 | 2322 | if (is_edp(intel_dp)) { |
21d40d37 | 2323 | intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT); |
bd943159 KP |
2324 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
2325 | ironlake_panel_vdd_work); | |
2326 | } | |
6251ec0a | 2327 | |
27f8227b | 2328 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
a4fc5ed6 KP |
2329 | connector->interlace_allowed = true; |
2330 | connector->doublescan_allowed = 0; | |
2331 | ||
4ef69c7a | 2332 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
a4fc5ed6 | 2333 | DRM_MODE_ENCODER_TMDS); |
4ef69c7a | 2334 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
a4fc5ed6 | 2335 | |
df0e9248 | 2336 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 KP |
2337 | drm_sysfs_connector_add(connector); |
2338 | ||
2339 | /* Set up the DDC bus. */ | |
5eb08b69 | 2340 | switch (output_reg) { |
32f9d658 ZW |
2341 | case DP_A: |
2342 | name = "DPDDC-A"; | |
2343 | break; | |
5eb08b69 ZW |
2344 | case DP_B: |
2345 | case PCH_DP_B: | |
b01f2c3a JB |
2346 | dev_priv->hotplug_supported_mask |= |
2347 | HDMIB_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2348 | name = "DPDDC-B"; |
2349 | break; | |
2350 | case DP_C: | |
2351 | case PCH_DP_C: | |
b01f2c3a JB |
2352 | dev_priv->hotplug_supported_mask |= |
2353 | HDMIC_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2354 | name = "DPDDC-C"; |
2355 | break; | |
2356 | case DP_D: | |
2357 | case PCH_DP_D: | |
b01f2c3a JB |
2358 | dev_priv->hotplug_supported_mask |= |
2359 | HDMID_HOTPLUG_INT_STATUS; | |
5eb08b69 ZW |
2360 | name = "DPDDC-D"; |
2361 | break; | |
2362 | } | |
2363 | ||
89667383 JB |
2364 | /* Cache some DPCD data in the eDP case */ |
2365 | if (is_edp(intel_dp)) { | |
59f3e272 | 2366 | bool ret; |
f01eca2e KP |
2367 | struct edp_power_seq cur, vbt; |
2368 | u32 pp_on, pp_off, pp_div; | |
5d613501 JB |
2369 | |
2370 | pp_on = I915_READ(PCH_PP_ON_DELAYS); | |
f01eca2e | 2371 | pp_off = I915_READ(PCH_PP_OFF_DELAYS); |
5d613501 | 2372 | pp_div = I915_READ(PCH_PP_DIVISOR); |
89667383 | 2373 | |
f01eca2e KP |
2374 | /* Pull timing values out of registers */ |
2375 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> | |
2376 | PANEL_POWER_UP_DELAY_SHIFT; | |
2377 | ||
2378 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> | |
2379 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
2380 | ||
2381 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> | |
2382 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
2383 | ||
2384 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> | |
2385 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
2386 | ||
2387 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
2388 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; | |
2389 | ||
2390 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
2391 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); | |
2392 | ||
2393 | vbt = dev_priv->edp.pps; | |
2394 | ||
2395 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
2396 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); | |
2397 | ||
2398 | #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10) | |
2399 | ||
2400 | intel_dp->panel_power_up_delay = get_delay(t1_t3); | |
2401 | intel_dp->backlight_on_delay = get_delay(t8); | |
2402 | intel_dp->backlight_off_delay = get_delay(t9); | |
2403 | intel_dp->panel_power_down_delay = get_delay(t10); | |
2404 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
2405 | ||
2406 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", | |
2407 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
2408 | intel_dp->panel_power_cycle_delay); | |
2409 | ||
2410 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
2411 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
5d613501 JB |
2412 | |
2413 | ironlake_edp_panel_vdd_on(intel_dp); | |
59f3e272 | 2414 | ret = intel_dp_get_dpcd(intel_dp); |
bd943159 | 2415 | ironlake_edp_panel_vdd_off(intel_dp, false); |
99ea7127 | 2416 | |
59f3e272 | 2417 | if (ret) { |
7183dc29 JB |
2418 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
2419 | dev_priv->no_aux_handshake = | |
2420 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
89667383 JB |
2421 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
2422 | } else { | |
3d3dc149 | 2423 | /* if this fails, presume the device is a ghost */ |
48898b03 | 2424 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
3d3dc149 | 2425 | intel_dp_encoder_destroy(&intel_dp->base.base); |
48898b03 | 2426 | intel_dp_destroy(&intel_connector->base); |
3d3dc149 | 2427 | return; |
89667383 | 2428 | } |
89667383 JB |
2429 | } |
2430 | ||
552fb0b7 KP |
2431 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
2432 | ||
21d40d37 | 2433 | intel_encoder->hot_plug = intel_dp_hot_plug; |
a4fc5ed6 | 2434 | |
4d926461 | 2435 | if (is_edp(intel_dp)) { |
aaa6fd2a MG |
2436 | dev_priv->int_edp_connector = connector; |
2437 | intel_panel_setup_backlight(dev); | |
32f9d658 ZW |
2438 | } |
2439 | ||
f684960e CW |
2440 | intel_dp_add_properties(intel_dp, connector); |
2441 | ||
a4fc5ed6 KP |
2442 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
2443 | * 0xd. Failure to do so will result in spurious interrupts being | |
2444 | * generated on the port when a cable is not attached. | |
2445 | */ | |
2446 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
2447 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
2448 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
2449 | } | |
2450 | } |