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drm/i915: Rename similar plane functions to avoid confusion
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
4be73780 94static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 95
a4fc5ed6 96static int
ea5b213a 97intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 98{
7183dc29 99 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 100 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 101
102 switch (max_link_bw) {
103 case DP_LINK_BW_1_62:
104 case DP_LINK_BW_2_7:
105 break;
d4eead50 106 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
06ea66b6
TP		 107 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
108 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
109 max_link_bw = DP_LINK_BW_5_4;
110 else
111 max_link_bw = DP_LINK_BW_2_7;
d4eead50 112 break;
a4fc5ed6 113 default:
d4eead50
ID		 114 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
115 max_link_bw);
a4fc5ed6
KP		 116 max_link_bw = DP_LINK_BW_1_62;
117 break;
118 }
119 return max_link_bw;
120}
121
cd9dde44
AJ		 122/*
123 * The units on the numbers in the next two are... bizarre. Examples will
124 * make it clearer; this one parallels an example in the eDP spec.
125 *
126 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
127 *
128 * 270000 * 1 * 8 / 10 == 216000
129 *
130 * The actual data capacity of that configuration is 2.16Gbit/s, so the
131 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
132 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
133 * 119000. At 18bpp that's 2142000 kilobits per second.
134 *
135 * Thus the strange-looking division by 10 in intel_dp_link_required, to
136 * get the result in decakilobits instead of kilobits.
137 */
138
a4fc5ed6 139static int
c898261c 140intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 141{
cd9dde44 142 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 143}
144
fe27d53e
DA		 145static int
146intel_dp_max_data_rate(int max_link_clock, int max_lanes)
147{
148 return (max_link_clock * max_lanes * 8) / 10;
149}
150
c19de8eb 151static enum drm_mode_status
a4fc5ed6
KP		 152intel_dp_mode_valid(struct drm_connector *connector,
153 struct drm_display_mode *mode)
154{
df0e9248 155 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 156 struct intel_connector *intel_connector = to_intel_connector(connector);
157 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 158 int target_clock = mode->clock;
159 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 160
dd06f90e
JN		 161 if (is_edp(intel_dp) && fixed_mode) {
162 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 163 return MODE_PANEL;
164
dd06f90e 165 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 166 return MODE_PANEL;
03afc4a2
DV		 167
168 target_clock = fixed_mode->clock;
7de56f43
ZY		 169 }
170
36008365
DV		 171 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
172 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
173
174 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
175 mode_rate = intel_dp_link_required(target_clock, 18);
176
177 if (mode_rate > max_rate)
c4867936 178 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 179
180 if (mode->clock < 10000)
181 return MODE_CLOCK_LOW;
182
0af78a2b
DV		 183 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
184 return MODE_H_ILLEGAL;
185
a4fc5ed6
KP		 186 return MODE_OK;
187}
188
189static uint32_t
190pack_aux(uint8_t *src, int src_bytes)
191{
192 int i;
193 uint32_t v = 0;
194
195 if (src_bytes > 4)
196 src_bytes = 4;
197 for (i = 0; i < src_bytes; i++)
198 v |= ((uint32_t) src[i]) << ((3-i) * 8);
199 return v;
200}
201
202static void
203unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
204{
205 int i;
206 if (dst_bytes > 4)
207 dst_bytes = 4;
208 for (i = 0; i < dst_bytes; i++)
209 dst[i] = src >> ((3-i) * 8);
210}
211
fb0f8fbf
KP		 212/* hrawclock is 1/4 the FSB frequency */
213static int
214intel_hrawclk(struct drm_device *dev)
215{
216 struct drm_i915_private *dev_priv = dev->dev_private;
217 uint32_t clkcfg;
218
9473c8f4
VP		 219 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
220 if (IS_VALLEYVIEW(dev))
221 return 200;
222
fb0f8fbf
KP		 223 clkcfg = I915_READ(CLKCFG);
224 switch (clkcfg & CLKCFG_FSB_MASK) {
225 case CLKCFG_FSB_400:
226 return 100;
227 case CLKCFG_FSB_533:
228 return 133;
229 case CLKCFG_FSB_667:
230 return 166;
231 case CLKCFG_FSB_800:
232 return 200;
233 case CLKCFG_FSB_1067:
234 return 266;
235 case CLKCFG_FSB_1333:
236 return 333;
237 /* these two are just a guess; one of them might be right */
238 case CLKCFG_FSB_1600:
239 case CLKCFG_FSB_1600_ALT:
240 return 400;
241 default:
242 return 133;
243 }
244}
245
bf13e81b
JN		 246static void
247intel_dp_init_panel_power_sequencer(struct drm_device *dev,
248 struct intel_dp *intel_dp,
249 struct edp_power_seq *out);
250static void
251intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
252 struct intel_dp *intel_dp,
253 struct edp_power_seq *out);
254
255static enum pipe
256vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
257{
258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
259 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
260 struct drm_device *dev = intel_dig_port->base.base.dev;
261 struct drm_i915_private *dev_priv = dev->dev_private;
262 enum port port = intel_dig_port->port;
263 enum pipe pipe;
264
265 /* modeset should have pipe */
266 if (crtc)
267 return to_intel_crtc(crtc)->pipe;
268
269 /* init time, try to find a pipe with this port selected */
270 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
271 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
272 PANEL_PORT_SELECT_MASK;
273 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
274 return pipe;
275 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
276 return pipe;
277 }
278
279 /* shrug */
280 return PIPE_A;
281}
282
283static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
284{
285 struct drm_device *dev = intel_dp_to_dev(intel_dp);
286
287 if (HAS_PCH_SPLIT(dev))
288 return PCH_PP_CONTROL;
289 else
290 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
291}
292
293static u32 _pp_stat_reg(struct intel_dp *intel_dp)
294{
295 struct drm_device *dev = intel_dp_to_dev(intel_dp);
296
297 if (HAS_PCH_SPLIT(dev))
298 return PCH_PP_STATUS;
299 else
300 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
301}
302
4be73780 303static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 304{
30add22d 305 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 306 struct drm_i915_private *dev_priv = dev->dev_private;
307
bf13e81b 308 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 309}
310
4be73780 311static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 312{
30add22d 313 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 314 struct drm_i915_private *dev_priv = dev->dev_private;
315
bf13e81b 316 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 317}
318
9b984dae
KP		 319static void
320intel_dp_check_edp(struct intel_dp *intel_dp)
321{
30add22d 322 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 323 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 324
9b984dae
KP		 325 if (!is_edp(intel_dp))
326 return;
453c5420 327
4be73780 328 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 329 WARN(1, "eDP powered off while attempting aux channel communication.\n");
330 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 331 I915_READ(_pp_stat_reg(intel_dp)),
332 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 333 }
334}
335
9ee32fea
DV		 336static uint32_t
337intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
338{
339 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
340 struct drm_device *dev = intel_dig_port->base.base.dev;
341 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 342 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 343 uint32_t status;
344 bool done;
345
ef04f00d 346#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 347 if (has_aux_irq)
b18ac466 348 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 349 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 350 else
351 done = wait_for_atomic(C, 10) == 0;
352 if (!done)
353 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
354 has_aux_irq);
355#undef C
356
357 return status;
358}
359
ec5b01dd 360static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 361{
174edf1f
PZ		 362 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
363 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 364
ec5b01dd
DL		 365 /*
366 * The clock divider is based off the hrawclk, and would like to run at
367 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 368 */
ec5b01dd
DL		 369 return index ? 0 : intel_hrawclk(dev) / 2;
370}
371
372static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
373{
374 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
375 struct drm_device *dev = intel_dig_port->base.base.dev;
376
377 if (index)
378 return 0;
379
380 if (intel_dig_port->port == PORT_A) {
381 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 382 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 383 else
b84a1cf8 384 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 385 } else {
386 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
387 }
388}
389
390static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
391{
392 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
393 struct drm_device *dev = intel_dig_port->base.base.dev;
394 struct drm_i915_private *dev_priv = dev->dev_private;
395
396 if (intel_dig_port->port == PORT_A) {
397 if (index)
398 return 0;
399 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 400 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
401 /* Workaround for non-ULT HSW */
bc86625a
CW		 402 switch (index) {
403 case 0: return 63;
404 case 1: return 72;
405 default: return 0;
406 }
ec5b01dd 407 } else {
bc86625a 408 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 409 }
b84a1cf8
RV		 410}
411
ec5b01dd
DL		 412static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
413{
414 return index ? 0 : 100;
415}
416
5ed12a19
DL		 417static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
418 bool has_aux_irq,
419 int send_bytes,
420 uint32_t aux_clock_divider)
421{
422 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
423 struct drm_device *dev = intel_dig_port->base.base.dev;
424 uint32_t precharge, timeout;
425
426 if (IS_GEN6(dev))
427 precharge = 3;
428 else
429 precharge = 5;
430
431 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
432 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
433 else
434 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
435
436 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 437 DP_AUX_CH_CTL_DONE |
5ed12a19 438 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 439 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 440 timeout |
788d4433 441 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 442 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
443 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 444 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 445}
446
b84a1cf8
RV		 447static int
448intel_dp_aux_ch(struct intel_dp *intel_dp,
449 uint8_t *send, int send_bytes,
450 uint8_t *recv, int recv_size)
451{
452 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
453 struct drm_device *dev = intel_dig_port->base.base.dev;
454 struct drm_i915_private *dev_priv = dev->dev_private;
455 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
456 uint32_t ch_data = ch_ctl + 4;
bc86625a 457 uint32_t aux_clock_divider;
b84a1cf8
RV		 458 int i, ret, recv_bytes;
459 uint32_t status;
5ed12a19 460 int try, clock = 0;
4e6b788c 461 bool has_aux_irq = HAS_AUX_IRQ(dev);
b84a1cf8
RV		 462
463 /* dp aux is extremely sensitive to irq latency, hence request the
464 * lowest possible wakeup latency and so prevent the cpu from going into
465 * deep sleep states.
466 */
467 pm_qos_update_request(&dev_priv->pm_qos, 0);
468
469 intel_dp_check_edp(intel_dp);
5eb08b69 470
c67a470b
PZ		 471 intel_aux_display_runtime_get(dev_priv);
472
11bee43e
JB		 473 /* Try to wait for any previous AUX channel activity */
474 for (try = 0; try < 3; try++) {
ef04f00d 475 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 476 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
477 break;
478 msleep(1);
479 }
480
481 if (try == 3) {
482 WARN(1, "dp_aux_ch not started status 0x%08x\n",
483 I915_READ(ch_ctl));
9ee32fea
DV		 484 ret = -EBUSY;
485 goto out;
4f7f7b7e
CW		 486 }
487
46a5ae9f
PZ		 488 /* Only 5 data registers! */
489 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
490 ret = -E2BIG;
491 goto out;
492 }
493
ec5b01dd 494 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 495 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
496 has_aux_irq,
497 send_bytes,
498 aux_clock_divider);
5ed12a19 499
bc86625a
CW		 500 /* Must try at least 3 times according to DP spec */
501 for (try = 0; try < 5; try++) {
502 /* Load the send data into the aux channel data registers */
503 for (i = 0; i < send_bytes; i += 4)
504 I915_WRITE(ch_data + i,
505 pack_aux(send + i, send_bytes - i));
506
507 /* Send the command and wait for it to complete */
5ed12a19 508 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 509
510 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
511
512 /* Clear done status and any errors */
513 I915_WRITE(ch_ctl,
514 status |
515 DP_AUX_CH_CTL_DONE |
516 DP_AUX_CH_CTL_TIME_OUT_ERROR |
517 DP_AUX_CH_CTL_RECEIVE_ERROR);
518
519 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
520 DP_AUX_CH_CTL_RECEIVE_ERROR))
521 continue;
522 if (status & DP_AUX_CH_CTL_DONE)
523 break;
524 }
4f7f7b7e 525 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 526 break;
527 }
528
a4fc5ed6 529 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 530 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 531 ret = -EBUSY;
532 goto out;
a4fc5ed6
KP		 533 }
534
535 /* Check for timeout or receive error.
536 * Timeouts occur when the sink is not connected
537 */
a5b3da54 538 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 539 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 540 ret = -EIO;
541 goto out;
a5b3da54 542 }
1ae8c0a5
KP		 543
544 /* Timeouts occur when the device isn't connected, so they're
545 * "normal" -- don't fill the kernel log with these */
a5b3da54 546 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 547 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 548 ret = -ETIMEDOUT;
549 goto out;
a4fc5ed6
KP		 550 }
551
552 /* Unload any bytes sent back from the other side */
553 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
554 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 555 if (recv_bytes > recv_size)
556 recv_bytes = recv_size;
0206e353 557
4f7f7b7e
CW		 558 for (i = 0; i < recv_bytes; i += 4)
559 unpack_aux(I915_READ(ch_data + i),
560 recv + i, recv_bytes - i);
a4fc5ed6 561
9ee32fea
DV		 562 ret = recv_bytes;
563out:
564 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 565 intel_aux_display_runtime_put(dev_priv);
9ee32fea
DV		 566
567 return ret;
a4fc5ed6
KP		 568}
569
570/* Write data to the aux channel in native mode */
571static int
ea5b213a 572intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 573 uint16_t address, uint8_t *send, int send_bytes)
574{
575 int ret;
576 uint8_t msg[20];
577 int msg_bytes;
578 uint8_t ack;
f51a44b9 579 int retry;
a4fc5ed6 580
46a5ae9f
PZ		 581 if (WARN_ON(send_bytes > 16))
582 return -E2BIG;
583
9b984dae 584 intel_dp_check_edp(intel_dp);
6b27f7f0 585 msg[0] = DP_AUX_NATIVE_WRITE << 4;
a4fc5ed6 586 msg[1] = address >> 8;
eebc863e 587 msg[2] = address & 0xff;
a4fc5ed6
KP		 588 msg[3] = send_bytes - 1;
589 memcpy(&msg[4], send, send_bytes);
590 msg_bytes = send_bytes + 4;
f51a44b9 591 for (retry = 0; retry < 7; retry++) {
ea5b213a 592 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 593 if (ret < 0)
594 return ret;
6b27f7f0
TR		 595 ack >>= 4;
596 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
f51a44b9 597 return send_bytes;
6b27f7f0 598 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
04eada25 599 usleep_range(400, 500);
a4fc5ed6 600 else
a5b3da54 601 return -EIO;
a4fc5ed6 602 }
f51a44b9
JN		 603
604 DRM_ERROR("too many retries, giving up\n");
605 return -EIO;
a4fc5ed6
KP		 606}
607
608/* Write a single byte to the aux channel in native mode */
609static int
ea5b213a 610intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 611 uint16_t address, uint8_t byte)
612{
ea5b213a 613 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 614}
615
616/* read bytes from a native aux channel */
617static int
ea5b213a 618intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 619 uint16_t address, uint8_t *recv, int recv_bytes)
620{
621 uint8_t msg[4];
622 int msg_bytes;
623 uint8_t reply[20];
624 int reply_bytes;
625 uint8_t ack;
626 int ret;
f51a44b9 627 int retry;
a4fc5ed6 628
46a5ae9f
PZ		 629 if (WARN_ON(recv_bytes > 19))
630 return -E2BIG;
631
9b984dae 632 intel_dp_check_edp(intel_dp);
6b27f7f0 633 msg[0] = DP_AUX_NATIVE_READ << 4;
a4fc5ed6
KP		 634 msg[1] = address >> 8;
635 msg[2] = address & 0xff;
636 msg[3] = recv_bytes - 1;
637
638 msg_bytes = 4;
639 reply_bytes = recv_bytes + 1;
640
f51a44b9 641 for (retry = 0; retry < 7; retry++) {
ea5b213a 642 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 643 reply, reply_bytes);
a5b3da54
KP		 644 if (ret == 0)
645 return -EPROTO;
646 if (ret < 0)
a4fc5ed6 647 return ret;
6b27f7f0
TR		 648 ack = reply[0] >> 4;
649 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
a4fc5ed6
KP		 650 memcpy(recv, reply + 1, ret - 1);
651 return ret - 1;
652 }
6b27f7f0 653 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
04eada25 654 usleep_range(400, 500);
a4fc5ed6 655 else
a5b3da54 656 return -EIO;
a4fc5ed6 657 }
f51a44b9
JN		 658
659 DRM_ERROR("too many retries, giving up\n");
660 return -EIO;
a4fc5ed6
KP		 661}
662
663static int
ab2c0672
DA		 664intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
665 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 666{
ab2c0672 667 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 668 struct intel_dp *intel_dp = container_of(adapter,
669 struct intel_dp,
670 adapter);
ab2c0672
DA		 671 uint16_t address = algo_data->address;
672 uint8_t msg[5];
673 uint8_t reply[2];
8316f337 674 unsigned retry;
ab2c0672
DA		 675 int msg_bytes;
676 int reply_bytes;
677 int ret;
678
24f3e092 679 intel_edp_panel_vdd_on(intel_dp);
9b984dae 680 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 681 /* Set up the command byte */
682 if (mode & MODE_I2C_READ)
6b27f7f0 683 msg[0] = DP_AUX_I2C_READ << 4;
ab2c0672 684 else
6b27f7f0 685 msg[0] = DP_AUX_I2C_WRITE << 4;
ab2c0672
DA		 686
687 if (!(mode & MODE_I2C_STOP))
6b27f7f0 688 msg[0] |= DP_AUX_I2C_MOT << 4;
a4fc5ed6 689
ab2c0672
DA		 690 msg[1] = address >> 8;
691 msg[2] = address;
692
693 switch (mode) {
694 case MODE_I2C_WRITE:
695 msg[3] = 0;
696 msg[4] = write_byte;
697 msg_bytes = 5;
698 reply_bytes = 1;
699 break;
700 case MODE_I2C_READ:
701 msg[3] = 0;
702 msg_bytes = 4;
703 reply_bytes = 2;
704 break;
705 default:
706 msg_bytes = 3;
707 reply_bytes = 1;
708 break;
709 }
710
58c67ce9
JN		 711 /*
712 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
713 * required to retry at least seven times upon receiving AUX_DEFER
714 * before giving up the AUX transaction.
715 */
716 for (retry = 0; retry < 7; retry++) {
8316f337
DF		 717 ret = intel_dp_aux_ch(intel_dp,
718 msg, msg_bytes,
719 reply, reply_bytes);
ab2c0672 720 if (ret < 0) {
3ff99164 721 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
8a5e6aeb 722 goto out;
ab2c0672 723 }
8316f337 724
6b27f7f0
TR		 725 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
726 case DP_AUX_NATIVE_REPLY_ACK:
8316f337
DF		 727 /* I2C-over-AUX Reply field is only valid
728 * when paired with AUX ACK.
729 */
730 break;
6b27f7f0 731 case DP_AUX_NATIVE_REPLY_NACK:
8316f337 732 DRM_DEBUG_KMS("aux_ch native nack\n");
8a5e6aeb
PZ		 733 ret = -EREMOTEIO;
734 goto out;
6b27f7f0 735 case DP_AUX_NATIVE_REPLY_DEFER:
8d16f258
JN		 736 /*
737 * For now, just give more slack to branch devices. We
738 * could check the DPCD for I2C bit rate capabilities,
739 * and if available, adjust the interval. We could also
740 * be more careful with DP-to-Legacy adapters where a
741 * long legacy cable may force very low I2C bit rates.
742 */
743 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
744 DP_DWN_STRM_PORT_PRESENT)
745 usleep_range(500, 600);
746 else
747 usleep_range(300, 400);
8316f337
DF		 748 continue;
749 default:
750 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
751 reply[0]);
8a5e6aeb
PZ		 752 ret = -EREMOTEIO;
753 goto out;
8316f337
DF		 754 }
755
6b27f7f0
TR		 756 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
757 case DP_AUX_I2C_REPLY_ACK:
ab2c0672
DA		 758 if (mode == MODE_I2C_READ) {
759 *read_byte = reply[1];
760 }
8a5e6aeb
PZ		 761 ret = reply_bytes - 1;
762 goto out;
6b27f7f0 763 case DP_AUX_I2C_REPLY_NACK:
8316f337 764 DRM_DEBUG_KMS("aux_i2c nack\n");
8a5e6aeb
PZ		 765 ret = -EREMOTEIO;
766 goto out;
6b27f7f0 767 case DP_AUX_I2C_REPLY_DEFER:
8316f337 768 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 769 udelay(100);
770 break;
771 default:
8316f337 772 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
8a5e6aeb
PZ		 773 ret = -EREMOTEIO;
774 goto out;
ab2c0672
DA		 775 }
776 }
8316f337
DF		 777
778 DRM_ERROR("too many retries, giving up\n");
8a5e6aeb
PZ		 779 ret = -EREMOTEIO;
780
781out:
4be73780 782 edp_panel_vdd_off(intel_dp, false);
8a5e6aeb 783 return ret;
a4fc5ed6
KP		 784}
785
80f65de3
ID		 786static void
787intel_dp_connector_unregister(struct intel_connector *intel_connector)
788{
789 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
790
791 sysfs_remove_link(&intel_connector->base.kdev->kobj,
792 intel_dp->adapter.dev.kobj.name);
793 intel_connector_unregister(intel_connector);
794}
795
a4fc5ed6 796static int
ea5b213a 797intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 798 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 799{
0b5c541b
KP		 800 int ret;
801
d54e9d28 802 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 803 intel_dp->algo.running = false;
804 intel_dp->algo.address = 0;
805 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
806
0206e353 807 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 808 intel_dp->adapter.owner = THIS_MODULE;
809 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 810 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 811 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
812 intel_dp->adapter.algo_data = &intel_dp->algo;
80f65de3 813 intel_dp->adapter.dev.parent = intel_connector->base.dev->dev;
ea5b213a 814
0b5c541b 815 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
80f65de3
ID		 816 if (ret < 0)
817 return ret;
818
819 ret = sysfs_create_link(&intel_connector->base.kdev->kobj,
820 &intel_dp->adapter.dev.kobj,
821 intel_dp->adapter.dev.kobj.name);
822
823 if (ret < 0)
824 i2c_del_adapter(&intel_dp->adapter);
825
0b5c541b 826 return ret;
a4fc5ed6
KP		 827}
828
c6bb3538
DV		 829static void
830intel_dp_set_clock(struct intel_encoder *encoder,
831 struct intel_crtc_config *pipe_config, int link_bw)
832{
833 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 834 const struct dp_link_dpll *divisor = NULL;
835 int i, count = 0;
c6bb3538
DV		 836
837 if (IS_G4X(dev)) {
9dd4ffdf
CML		 838 divisor = gen4_dpll;
839 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 840 } else if (IS_HASWELL(dev)) {
841 /* Haswell has special-purpose DP DDI clocks. */
842 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 843 divisor = pch_dpll;
844 count = ARRAY_SIZE(pch_dpll);
c6bb3538 845 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 846 divisor = vlv_dpll;
847 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 848 }
9dd4ffdf
CML		 849
850 if (divisor && count) {
851 for (i = 0; i < count; i++) {
852 if (link_bw == divisor[i].link_bw) {
853 pipe_config->dpll = divisor[i].dpll;
854 pipe_config->clock_set = true;
855 break;
856 }
857 }
c6bb3538
DV		 858 }
859}
860
00c09d70 861bool
5bfe2ac0
DV		 862intel_dp_compute_config(struct intel_encoder *encoder,
863 struct intel_crtc_config *pipe_config)
a4fc5ed6 864{
5bfe2ac0 865 struct drm_device *dev = encoder->base.dev;
36008365 866 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 867 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 868 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 869 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 870 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 871 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 872 int lane_count, clock;
397fe157 873 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
06ea66b6
TP		 874 /* Conveniently, the link BW constants become indices with a shift...*/
875 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 876 int bpp, mode_rate;
06ea66b6 877 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 878 int link_avail, link_clock;
a4fc5ed6 879
bc7d38a4 880 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 881 pipe_config->has_pch_encoder = true;
882
03afc4a2 883 pipe_config->has_dp_encoder = true;
a4fc5ed6 884
dd06f90e
JN		 885 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
886 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
887 adjusted_mode);
2dd24552
JB		 888 if (!HAS_PCH_SPLIT(dev))
889 intel_gmch_panel_fitting(intel_crtc, pipe_config,
890 intel_connector->panel.fitting_mode);
891 else
b074cec8
JB		 892 intel_pch_panel_fitting(intel_crtc, pipe_config,
893 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 894 }
895
cb1793ce 896 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 897 return false;
898
083f9560
DV		 899 DRM_DEBUG_KMS("DP link computation with max lane count %i "
900 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 901 max_lane_count, bws[max_clock],
902 adjusted_mode->crtc_clock);
083f9560 903
36008365
DV		 904 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
905 * bpc in between. */
3e7ca985 906 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 907 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
908 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 909 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
910 dev_priv->vbt.edp_bpp);
6da7f10d 911 bpp = dev_priv->vbt.edp_bpp;
7984211e 912 }
657445fe 913
36008365 914 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 915 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
916 bpp);
36008365 917
38aecea0
DV		 918 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
919 for (clock = 0; clock <= max_clock; clock++) {
36008365
DV		 920 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
921 link_avail = intel_dp_max_data_rate(link_clock,
922 lane_count);
923
924 if (mode_rate <= link_avail) {
925 goto found;
926 }
927 }
928 }
929 }
c4867936 930
36008365 931 return false;
3685a8f3 932
36008365 933found:
55bc60db
VS		 934 if (intel_dp->color_range_auto) {
935 /*
936 * See:
937 * CEA-861-E - 5.1 Default Encoding Parameters
938 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
939 */
18316c8c 940 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 941 intel_dp->color_range = DP_COLOR_RANGE_16_235;
942 else
943 intel_dp->color_range = 0;
944 }
945
3685a8f3 946 if (intel_dp->color_range)
50f3b016 947 pipe_config->limited_color_range = true;
a4fc5ed6 948
36008365
DV		 949 intel_dp->link_bw = bws[clock];
950 intel_dp->lane_count = lane_count;
657445fe 951 pipe_config->pipe_bpp = bpp;
ff9a6750 952 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 953
36008365
DV		 954 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
955 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 956 pipe_config->port_clock, bpp);
36008365
DV		 957 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
958 mode_rate, link_avail);
a4fc5ed6 959
03afc4a2 960 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 961 adjusted_mode->crtc_clock,
962 pipe_config->port_clock,
03afc4a2 963 &pipe_config->dp_m_n);
9d1a455b 964
c6bb3538
DV		 965 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
966
03afc4a2 967 return true;
a4fc5ed6
KP		 968}
969
7c62a164 970static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 971{
7c62a164
DV		 972 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
973 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
974 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 975 struct drm_i915_private *dev_priv = dev->dev_private;
976 u32 dpa_ctl;
977
ff9a6750 978 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 979 dpa_ctl = I915_READ(DP_A);
980 dpa_ctl &= ~DP_PLL_FREQ_MASK;
981
ff9a6750 982 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 983 /* For a long time we've carried around a ILK-DevA w/a for the
984 * 160MHz clock. If we're really unlucky, it's still required.
985 */
986 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 987 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 988 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 989 } else {
990 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 991 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 992 }
1ce17038 993
ea9b6006
DV		 994 I915_WRITE(DP_A, dpa_ctl);
995
996 POSTING_READ(DP_A);
997 udelay(500);
998}
999
b934223d 1000static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 1001{
b934223d 1002 struct drm_device *dev = encoder->base.dev;
417e822d 1003 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1004 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1005 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1006 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1007 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1008
417e822d 1009 /*
1a2eb460 1010 * There are four kinds of DP registers:
417e822d
KP		 1011 *
1012 * IBX PCH
1a2eb460
KP		 1013 * SNB CPU
1014 * IVB CPU
417e822d
KP		 1015 * CPT PCH
1016 *
1017 * IBX PCH and CPU are the same for almost everything,
1018 * except that the CPU DP PLL is configured in this
1019 * register
1020 *
1021 * CPT PCH is quite different, having many bits moved
1022 * to the TRANS_DP_CTL register instead. That
1023 * configuration happens (oddly) in ironlake_pch_enable
1024 */
9c9e7927 1025
417e822d
KP		 1026 /* Preserve the BIOS-computed detected bit. This is
1027 * supposed to be read-only.
1028 */
1029 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1030
417e822d 1031 /* Handle DP bits in common between all three register formats */
417e822d 1032 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1033 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1034
e0dac65e
WF		 1035 if (intel_dp->has_audio) {
1036 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1037 pipe_name(crtc->pipe));
ea5b213a 1038 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1039 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1040 }
247d89f6 1041
417e822d 1042 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1043
bc7d38a4 1044 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1045 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1046 intel_dp->DP |= DP_SYNC_HS_HIGH;
1047 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1048 intel_dp->DP |= DP_SYNC_VS_HIGH;
1049 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1050
6aba5b6c 1051 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1052 intel_dp->DP |= DP_ENHANCED_FRAMING;
1053
7c62a164 1054 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1055 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1056 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1057 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1058
1059 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1060 intel_dp->DP |= DP_SYNC_HS_HIGH;
1061 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1062 intel_dp->DP |= DP_SYNC_VS_HIGH;
1063 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1064
6aba5b6c 1065 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1066 intel_dp->DP |= DP_ENHANCED_FRAMING;
1067
7c62a164 1068 if (crtc->pipe == 1)
417e822d 1069 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 1070 } else {
1071 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1072 }
ea9b6006 1073
bc7d38a4 1074 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 1075 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 1076}
1077
ffd6749d
PZ		 1078#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1079#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1080
1a5ef5b7
PZ		 1081#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1082#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1083
ffd6749d
PZ		 1084#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1085#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1086
4be73780 1087static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1088 u32 mask,
1089 u32 value)
bd943159 1090{
30add22d 1091 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1092 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1093 u32 pp_stat_reg, pp_ctrl_reg;
1094
bf13e81b
JN		 1095 pp_stat_reg = _pp_stat_reg(intel_dp);
1096 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1097
99ea7127 1098 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1099 mask, value,
1100 I915_READ(pp_stat_reg),
1101 I915_READ(pp_ctrl_reg));
32ce697c 1102
453c5420 1103 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1104 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1105 I915_READ(pp_stat_reg),
1106 I915_READ(pp_ctrl_reg));
32ce697c 1107 }
54c136d4
CW		 1108
1109 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1110}
32ce697c 1111
4be73780 1112static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1113{
1114 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1115 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1116}
1117
4be73780 1118static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1119{
1120 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1121 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1122}
1123
4be73780 1124static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1125{
1126 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1127
1128 /* When we disable the VDD override bit last we have to do the manual
1129 * wait. */
1130 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1131 intel_dp->panel_power_cycle_delay);
1132
4be73780 1133 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1134}
1135
4be73780 1136static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1137{
1138 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1139 intel_dp->backlight_on_delay);
1140}
1141
4be73780 1142static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1143{
1144 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1145 intel_dp->backlight_off_delay);
1146}
99ea7127 1147
832dd3c1
KP		 1148/* Read the current pp_control value, unlocking the register if it
1149 * is locked
1150 */
1151
453c5420 1152static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1153{
453c5420
JB		 1154 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1155 struct drm_i915_private *dev_priv = dev->dev_private;
1156 u32 control;
832dd3c1 1157
bf13e81b 1158 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1159 control &= ~PANEL_UNLOCK_MASK;
1160 control |= PANEL_UNLOCK_REGS;
1161 return control;
bd943159
KP		 1162}
1163
24f3e092 1164void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1165{
30add22d 1166 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1167 struct drm_i915_private *dev_priv = dev->dev_private;
1168 u32 pp;
453c5420 1169 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1170
97af61f5
KP		 1171 if (!is_edp(intel_dp))
1172 return;
5d613501 1173
bd943159
KP		 1174 WARN(intel_dp->want_panel_vdd,
1175 "eDP VDD already requested on\n");
1176
1177 intel_dp->want_panel_vdd = true;
99ea7127 1178
4be73780 1179 if (edp_have_panel_vdd(intel_dp))
bd943159 1180 return;
b0665d57 1181
e9cb81a2
PZ		 1182 intel_runtime_pm_get(dev_priv);
1183
b0665d57 1184 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1185
4be73780
DV		 1186 if (!edp_have_panel_power(intel_dp))
1187 wait_panel_power_cycle(intel_dp);
99ea7127 1188
453c5420 1189 pp = ironlake_get_pp_control(intel_dp);
5d613501 1190 pp |= EDP_FORCE_VDD;
ebf33b18 1191
bf13e81b
JN		 1192 pp_stat_reg = _pp_stat_reg(intel_dp);
1193 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1194
1195 I915_WRITE(pp_ctrl_reg, pp);
1196 POSTING_READ(pp_ctrl_reg);
1197 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1198 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1199 /*
1200 * If the panel wasn't on, delay before accessing aux channel
1201 */
4be73780 1202 if (!edp_have_panel_power(intel_dp)) {
bd943159 1203 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1204 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1205 }
5d613501
JB		 1206}
1207
4be73780 1208static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1209{
30add22d 1210 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1211 struct drm_i915_private *dev_priv = dev->dev_private;
1212 u32 pp;
453c5420 1213 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1214
a0e99e68
DV		 1215 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1216
4be73780 1217 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
b0665d57
PZ		 1218 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1219
453c5420 1220 pp = ironlake_get_pp_control(intel_dp);
bd943159 1221 pp &= ~EDP_FORCE_VDD;
bd943159 1222
9f08ef59
PZ		 1223 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1224 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1225
1226 I915_WRITE(pp_ctrl_reg, pp);
1227 POSTING_READ(pp_ctrl_reg);
99ea7127 1228
453c5420
JB		 1229 /* Make sure sequencer is idle before allowing subsequent activity */
1230 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1231 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1232
1233 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1234 intel_dp->last_power_cycle = jiffies;
e9cb81a2
PZ		 1235
1236 intel_runtime_pm_put(dev_priv);
bd943159
KP		 1237 }
1238}
5d613501 1239
4be73780 1240static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1241{
1242 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1243 struct intel_dp, panel_vdd_work);
30add22d 1244 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1245
627f7675 1246 mutex_lock(&dev->mode_config.mutex);
4be73780 1247 edp_panel_vdd_off_sync(intel_dp);
627f7675 1248 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1249}
1250
4be73780 1251static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1252{
97af61f5
KP		 1253 if (!is_edp(intel_dp))
1254 return;
5d613501 1255
bd943159 1256 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1257
bd943159
KP		 1258 intel_dp->want_panel_vdd = false;
1259
1260 if (sync) {
4be73780 1261 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1262 } else {
1263 /*
1264 * Queue the timer to fire a long
1265 * time from now (relative to the power down delay)
1266 * to keep the panel power up across a sequence of operations
1267 */
1268 schedule_delayed_work(&intel_dp->panel_vdd_work,
1269 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1270 }
5d613501
JB		 1271}
1272
4be73780 1273void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1274{
30add22d 1275 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1276 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1277 u32 pp;
453c5420 1278 u32 pp_ctrl_reg;
9934c132 1279
97af61f5 1280 if (!is_edp(intel_dp))
bd943159 1281 return;
99ea7127
KP		 1282
1283 DRM_DEBUG_KMS("Turn eDP power on\n");
1284
4be73780 1285 if (edp_have_panel_power(intel_dp)) {
99ea7127 1286 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1287 return;
99ea7127 1288 }
9934c132 1289
4be73780 1290 wait_panel_power_cycle(intel_dp);
37c6c9b0 1291
bf13e81b 1292 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1293 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1294 if (IS_GEN5(dev)) {
1295 /* ILK workaround: disable reset around power sequence */
1296 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1297 I915_WRITE(pp_ctrl_reg, pp);
1298 POSTING_READ(pp_ctrl_reg);
05ce1a49 1299 }
37c6c9b0 1300
1c0ae80a 1301 pp |= POWER_TARGET_ON;
99ea7127
KP		 1302 if (!IS_GEN5(dev))
1303 pp |= PANEL_POWER_RESET;
1304
453c5420
JB		 1305 I915_WRITE(pp_ctrl_reg, pp);
1306 POSTING_READ(pp_ctrl_reg);
9934c132 1307
4be73780 1308 wait_panel_on(intel_dp);
dce56b3c 1309 intel_dp->last_power_on = jiffies;
9934c132 1310
05ce1a49
KP		 1311 if (IS_GEN5(dev)) {
1312 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1313 I915_WRITE(pp_ctrl_reg, pp);
1314 POSTING_READ(pp_ctrl_reg);
05ce1a49 1315 }
9934c132
JB		 1316}
1317
4be73780 1318void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1319{
30add22d 1320 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1321 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1322 u32 pp;
453c5420 1323 u32 pp_ctrl_reg;
9934c132 1324
97af61f5
KP		 1325 if (!is_edp(intel_dp))
1326 return;
37c6c9b0 1327
99ea7127 1328 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1329
4be73780 1330 edp_wait_backlight_off(intel_dp);
dce56b3c 1331
24f3e092
JN		 1332 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1333
453c5420 1334 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1335 /* We need to switch off panel power _and_ force vdd, for otherwise some
1336 * panels get very unhappy and cease to work. */
b3064154
PJ		 1337 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1338 EDP_BLC_ENABLE);
453c5420 1339
bf13e81b 1340 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1341
849e39f5
PZ		 1342 intel_dp->want_panel_vdd = false;
1343
453c5420
JB		 1344 I915_WRITE(pp_ctrl_reg, pp);
1345 POSTING_READ(pp_ctrl_reg);
9934c132 1346
dce56b3c 1347 intel_dp->last_power_cycle = jiffies;
4be73780 1348 wait_panel_off(intel_dp);
849e39f5
PZ		 1349
1350 /* We got a reference when we enabled the VDD. */
1351 intel_runtime_pm_put(dev_priv);
9934c132
JB		 1352}
1353
4be73780 1354void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1355{
da63a9f2
PZ		 1356 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1357 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1358 struct drm_i915_private *dev_priv = dev->dev_private;
1359 u32 pp;
453c5420 1360 u32 pp_ctrl_reg;
32f9d658 1361
f01eca2e
KP		 1362 if (!is_edp(intel_dp))
1363 return;
1364
28c97730 1365 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1366 /*
1367 * If we enable the backlight right away following a panel power
1368 * on, we may see slight flicker as the panel syncs with the eDP
1369 * link. So delay a bit to make sure the image is solid before
1370 * allowing it to appear.
1371 */
4be73780 1372 wait_backlight_on(intel_dp);
453c5420 1373 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1374 pp |= EDP_BLC_ENABLE;
453c5420 1375
bf13e81b 1376 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1377
1378 I915_WRITE(pp_ctrl_reg, pp);
1379 POSTING_READ(pp_ctrl_reg);
035aa3de 1380
752aa88a 1381 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1382}
1383
4be73780 1384void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1385{
30add22d 1386 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1387 struct drm_i915_private *dev_priv = dev->dev_private;
1388 u32 pp;
453c5420 1389 u32 pp_ctrl_reg;
32f9d658 1390
f01eca2e
KP		 1391 if (!is_edp(intel_dp))
1392 return;
1393
752aa88a 1394 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1395
28c97730 1396 DRM_DEBUG_KMS("\n");
453c5420 1397 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1398 pp &= ~EDP_BLC_ENABLE;
453c5420 1399
bf13e81b 1400 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1401
1402 I915_WRITE(pp_ctrl_reg, pp);
1403 POSTING_READ(pp_ctrl_reg);
dce56b3c 1404 intel_dp->last_backlight_off = jiffies;
32f9d658 1405}
a4fc5ed6 1406
2bd2ad64 1407static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1408{
da63a9f2
PZ		 1409 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1410 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1411 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1412 struct drm_i915_private *dev_priv = dev->dev_private;
1413 u32 dpa_ctl;
1414
2bd2ad64
DV		 1415 assert_pipe_disabled(dev_priv,
1416 to_intel_crtc(crtc)->pipe);
1417
d240f20f
JB		 1418 DRM_DEBUG_KMS("\n");
1419 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1420 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1421 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1422
1423 /* We don't adjust intel_dp->DP while tearing down the link, to
1424 * facilitate link retraining (e.g. after hotplug). Hence clear all
1425 * enable bits here to ensure that we don't enable too much. */
1426 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1427 intel_dp->DP |= DP_PLL_ENABLE;
1428 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1429 POSTING_READ(DP_A);
1430 udelay(200);
d240f20f
JB		 1431}
1432
2bd2ad64 1433static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1434{
da63a9f2
PZ		 1435 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1436 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1437 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1438 struct drm_i915_private *dev_priv = dev->dev_private;
1439 u32 dpa_ctl;
1440
2bd2ad64
DV		 1441 assert_pipe_disabled(dev_priv,
1442 to_intel_crtc(crtc)->pipe);
1443
d240f20f 1444 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1445 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1446 "dp pll off, should be on\n");
1447 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1448
1449 /* We can't rely on the value tracked for the DP register in
1450 * intel_dp->DP because link_down must not change that (otherwise link
1451 * re-training will fail. */
298b0b39 1452 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1453 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1454 POSTING_READ(DP_A);
d240f20f
JB		 1455 udelay(200);
1456}
1457
c7ad3810 1458/* If the sink supports it, try to set the power state appropriately */
c19b0669 1459void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1460{
1461 int ret, i;
1462
1463 /* Should have a valid DPCD by this point */
1464 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1465 return;
1466
1467 if (mode != DRM_MODE_DPMS_ON) {
1468 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1469 DP_SET_POWER_D3);
1470 if (ret != 1)
1471 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1472 } else {
1473 /*
1474 * When turning on, we need to retry for 1ms to give the sink
1475 * time to wake up.
1476 */
1477 for (i = 0; i < 3; i++) {
1478 ret = intel_dp_aux_native_write_1(intel_dp,
1479 DP_SET_POWER,
1480 DP_SET_POWER_D0);
1481 if (ret == 1)
1482 break;
1483 msleep(1);
1484 }
1485 }
1486}
1487
19d8fe15
DV		 1488static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1489 enum pipe *pipe)
d240f20f 1490{
19d8fe15 1491 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1492 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1493 struct drm_device *dev = encoder->base.dev;
1494 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1495 enum intel_display_power_domain power_domain;
1496 u32 tmp;
1497
1498 power_domain = intel_display_port_power_domain(encoder);
1499 if (!intel_display_power_enabled(dev_priv, power_domain))
1500 return false;
1501
1502 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1503
1504 if (!(tmp & DP_PORT_EN))
1505 return false;
1506
bc7d38a4 1507 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1508 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1509 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1510 *pipe = PORT_TO_PIPE(tmp);
1511 } else {
1512 u32 trans_sel;
1513 u32 trans_dp;
1514 int i;
1515
1516 switch (intel_dp->output_reg) {
1517 case PCH_DP_B:
1518 trans_sel = TRANS_DP_PORT_SEL_B;
1519 break;
1520 case PCH_DP_C:
1521 trans_sel = TRANS_DP_PORT_SEL_C;
1522 break;
1523 case PCH_DP_D:
1524 trans_sel = TRANS_DP_PORT_SEL_D;
1525 break;
1526 default:
1527 return true;
1528 }
1529
1530 for_each_pipe(i) {
1531 trans_dp = I915_READ(TRANS_DP_CTL(i));
1532 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1533 *pipe = i;
1534 return true;
1535 }
1536 }
19d8fe15 1537
4a0833ec
DV		 1538 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1539 intel_dp->output_reg);
1540 }
d240f20f 1541
19d8fe15
DV		 1542 return true;
1543}
d240f20f 1544
045ac3b5
JB		 1545static void intel_dp_get_config(struct intel_encoder *encoder,
1546 struct intel_crtc_config *pipe_config)
1547{
1548 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1549 u32 tmp, flags = 0;
63000ef6
XZ		 1550 struct drm_device *dev = encoder->base.dev;
1551 struct drm_i915_private *dev_priv = dev->dev_private;
1552 enum port port = dp_to_dig_port(intel_dp)->port;
1553 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1554 int dotclock;
045ac3b5 1555
63000ef6
XZ		 1556 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1557 tmp = I915_READ(intel_dp->output_reg);
1558 if (tmp & DP_SYNC_HS_HIGH)
1559 flags |= DRM_MODE_FLAG_PHSYNC;
1560 else
1561 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1562
63000ef6
XZ		 1563 if (tmp & DP_SYNC_VS_HIGH)
1564 flags |= DRM_MODE_FLAG_PVSYNC;
1565 else
1566 flags |= DRM_MODE_FLAG_NVSYNC;
1567 } else {
1568 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1569 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1570 flags |= DRM_MODE_FLAG_PHSYNC;
1571 else
1572 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1573
63000ef6
XZ		 1574 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1575 flags |= DRM_MODE_FLAG_PVSYNC;
1576 else
1577 flags |= DRM_MODE_FLAG_NVSYNC;
1578 }
045ac3b5
JB		 1579
1580 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1581
eb14cb74
VS		 1582 pipe_config->has_dp_encoder = true;
1583
1584 intel_dp_get_m_n(crtc, pipe_config);
1585
18442d08 1586 if (port == PORT_A) {
f1f644dc
JB		 1587 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1588 pipe_config->port_clock = 162000;
1589 else
1590 pipe_config->port_clock = 270000;
1591 }
18442d08
VS		 1592
1593 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1594 &pipe_config->dp_m_n);
1595
1596 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1597 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1598
241bfc38 1599 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1600
c6cd2ee2
JN		 1601 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1602 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1603 /*
1604 * This is a big fat ugly hack.
1605 *
1606 * Some machines in UEFI boot mode provide us a VBT that has 18
1607 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1608 * unknown we fail to light up. Yet the same BIOS boots up with
1609 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1610 * max, not what it tells us to use.
1611 *
1612 * Note: This will still be broken if the eDP panel is not lit
1613 * up by the BIOS, and thus we can't get the mode at module
1614 * load.
1615 */
1616 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1617 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1618 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1619 }
045ac3b5
JB		 1620}
1621
a031d709 1622static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1623{
a031d709
RV		 1624 struct drm_i915_private *dev_priv = dev->dev_private;
1625
1626 return dev_priv->psr.sink_support;
2293bb5c
SK		 1627}
1628
2b28bb1b
RV		 1629static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1630{
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632
18b5992c 1633 if (!HAS_PSR(dev))
2b28bb1b
RV		 1634 return false;
1635
18b5992c 1636 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1637}
1638
1639static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1640 struct edp_vsc_psr *vsc_psr)
1641{
1642 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1643 struct drm_device *dev = dig_port->base.base.dev;
1644 struct drm_i915_private *dev_priv = dev->dev_private;
1645 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1646 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1647 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1648 uint32_t *data = (uint32_t *) vsc_psr;
1649 unsigned int i;
1650
1651 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1652 the video DIP being updated before program video DIP data buffer
1653 registers for DIP being updated. */
1654 I915_WRITE(ctl_reg, 0);
1655 POSTING_READ(ctl_reg);
1656
1657 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1658 if (i < sizeof(struct edp_vsc_psr))
1659 I915_WRITE(data_reg + i, *data++);
1660 else
1661 I915_WRITE(data_reg + i, 0);
1662 }
1663
1664 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1665 POSTING_READ(ctl_reg);
1666}
1667
1668static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1669{
1670 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1671 struct drm_i915_private *dev_priv = dev->dev_private;
1672 struct edp_vsc_psr psr_vsc;
1673
1674 if (intel_dp->psr_setup_done)
1675 return;
1676
1677 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1678 memset(&psr_vsc, 0, sizeof(psr_vsc));
1679 psr_vsc.sdp_header.HB0 = 0;
1680 psr_vsc.sdp_header.HB1 = 0x7;
1681 psr_vsc.sdp_header.HB2 = 0x2;
1682 psr_vsc.sdp_header.HB3 = 0x8;
1683 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1684
1685 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1686 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1687 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1688
1689 intel_dp->psr_setup_done = true;
1690}
1691
1692static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1693{
1694 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1695 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1696 uint32_t aux_clock_divider;
2b28bb1b
RV		 1697 int precharge = 0x3;
1698 int msg_size = 5; /* Header(4) + Message(1) */
1699
ec5b01dd
DL		 1700 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1701
2b28bb1b
RV		 1702 /* Enable PSR in sink */
1703 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1704 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1705 DP_PSR_ENABLE &
1706 ~DP_PSR_MAIN_LINK_ACTIVE);
1707 else
1708 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1709 DP_PSR_ENABLE |
1710 DP_PSR_MAIN_LINK_ACTIVE);
1711
1712 /* Setup AUX registers */
18b5992c
BW		 1713 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1714 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1715 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1716 DP_AUX_CH_CTL_TIME_OUT_400us |
1717 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1718 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1719 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1720}
1721
1722static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1723{
1724 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1725 struct drm_i915_private *dev_priv = dev->dev_private;
1726 uint32_t max_sleep_time = 0x1f;
1727 uint32_t idle_frames = 1;
1728 uint32_t val = 0x0;
ed8546ac 1729 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1730
1731 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1732 val |= EDP_PSR_LINK_STANDBY;
1733 val |= EDP_PSR_TP2_TP3_TIME_0us;
1734 val |= EDP_PSR_TP1_TIME_0us;
1735 val |= EDP_PSR_SKIP_AUX_EXIT;
1736 } else
1737 val |= EDP_PSR_LINK_DISABLE;
1738
18b5992c 1739 I915_WRITE(EDP_PSR_CTL(dev), val |
ed8546ac 1740 IS_BROADWELL(dev) ? 0 : link_entry_time |
2b28bb1b
RV		 1741 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1742 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1743 EDP_PSR_ENABLE);
1744}
1745
3f51e471
RV		 1746static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1747{
1748 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1749 struct drm_device *dev = dig_port->base.base.dev;
1750 struct drm_i915_private *dev_priv = dev->dev_private;
1751 struct drm_crtc *crtc = dig_port->base.base.crtc;
1752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1753 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1754 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1755
a031d709
RV		 1756 dev_priv->psr.source_ok = false;
1757
18b5992c 1758 if (!HAS_PSR(dev)) {
3f51e471 1759 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1760 return false;
1761 }
1762
1763 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1764 (dig_port->port != PORT_A)) {
1765 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1766 return false;
1767 }
1768
d330a953 1769 if (!i915.enable_psr) {
105b7c11 1770 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1771 return false;
1772 }
1773
cd234b0b
CW		 1774 crtc = dig_port->base.base.crtc;
1775 if (crtc == NULL) {
1776 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1777 return false;
1778 }
1779
1780 intel_crtc = to_intel_crtc(crtc);
20ddf665 1781 if (!intel_crtc_active(crtc)) {
3f51e471 1782 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1783 return false;
1784 }
1785
cd234b0b 1786 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1787 if (obj->tiling_mode != I915_TILING_X ||
1788 obj->fence_reg == I915_FENCE_REG_NONE) {
1789 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1790 return false;
1791 }
1792
1793 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1794 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1795 return false;
1796 }
1797
1798 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1799 S3D_ENABLE) {
1800 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1801 return false;
1802 }
1803
ca73b4f0 1804 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1805 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1806 return false;
1807 }
1808
a031d709 1809 dev_priv->psr.source_ok = true;
3f51e471
RV		 1810 return true;
1811}
1812
3d739d92 1813static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1814{
1815 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1816
3f51e471
RV		 1817 if (!intel_edp_psr_match_conditions(intel_dp) ||
1818 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1819 return;
1820
1821 /* Setup PSR once */
1822 intel_edp_psr_setup(intel_dp);
1823
1824 /* Enable PSR on the panel */
1825 intel_edp_psr_enable_sink(intel_dp);
1826
1827 /* Enable PSR on the host */
1828 intel_edp_psr_enable_source(intel_dp);
1829}
1830
3d739d92
RV		 1831void intel_edp_psr_enable(struct intel_dp *intel_dp)
1832{
1833 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1834
1835 if (intel_edp_psr_match_conditions(intel_dp) &&
1836 !intel_edp_is_psr_enabled(dev))
1837 intel_edp_psr_do_enable(intel_dp);
1838}
1839
2b28bb1b
RV		 1840void intel_edp_psr_disable(struct intel_dp *intel_dp)
1841{
1842 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1843 struct drm_i915_private *dev_priv = dev->dev_private;
1844
1845 if (!intel_edp_is_psr_enabled(dev))
1846 return;
1847
18b5992c
BW		 1848 I915_WRITE(EDP_PSR_CTL(dev),
1849 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1850
1851 /* Wait till PSR is idle */
18b5992c 1852 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1853 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1854 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1855}
1856
3d739d92
RV		 1857void intel_edp_psr_update(struct drm_device *dev)
1858{
1859 struct intel_encoder *encoder;
1860 struct intel_dp *intel_dp = NULL;
1861
1862 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1863 if (encoder->type == INTEL_OUTPUT_EDP) {
1864 intel_dp = enc_to_intel_dp(&encoder->base);
1865
a031d709 1866 if (!is_edp_psr(dev))
3d739d92
RV		 1867 return;
1868
1869 if (!intel_edp_psr_match_conditions(intel_dp))
1870 intel_edp_psr_disable(intel_dp);
1871 else
1872 if (!intel_edp_is_psr_enabled(dev))
1873 intel_edp_psr_do_enable(intel_dp);
1874 }
1875}
1876
e8cb4558 1877static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1878{
e8cb4558 1879 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1880 enum port port = dp_to_dig_port(intel_dp)->port;
1881 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1882
1883 /* Make sure the panel is off before trying to change the mode. But also
1884 * ensure that we have vdd while we switch off the panel. */
24f3e092 1885 intel_edp_panel_vdd_on(intel_dp);
4be73780 1886 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1887 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1888 intel_edp_panel_off(intel_dp);
3739850b
DV		 1889
1890 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1891 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1892 intel_dp_link_down(intel_dp);
d240f20f
JB		 1893}
1894
2bd2ad64 1895static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1896{
2bd2ad64 1897 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1898 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1899 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1900
982a3866 1901 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1902 intel_dp_link_down(intel_dp);
b2634017
JB		 1903 if (!IS_VALLEYVIEW(dev))
1904 ironlake_edp_pll_off(intel_dp);
3739850b 1905 }
2bd2ad64
DV		 1906}
1907
e8cb4558 1908static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1909{
e8cb4558
DV		 1910 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1911 struct drm_device *dev = encoder->base.dev;
1912 struct drm_i915_private *dev_priv = dev->dev_private;
1913 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1914
0c33d8d7
DV		 1915 if (WARN_ON(dp_reg & DP_PORT_EN))
1916 return;
5d613501 1917
24f3e092 1918 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 1919 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1920 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1921 intel_edp_panel_on(intel_dp);
1922 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1923 intel_dp_complete_link_train(intel_dp);
3ab9c637 1924 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1925}
89b667f8 1926
ecff4f3b
JN		 1927static void g4x_enable_dp(struct intel_encoder *encoder)
1928{
828f5c6e
JN		 1929 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1930
ecff4f3b 1931 intel_enable_dp(encoder);
4be73780 1932 intel_edp_backlight_on(intel_dp);
ab1f90f9 1933}
89b667f8 1934
ab1f90f9
JN		 1935static void vlv_enable_dp(struct intel_encoder *encoder)
1936{
828f5c6e
JN		 1937 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1938
4be73780 1939 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1940}
1941
ecff4f3b 1942static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1943{
1944 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1945 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1946
1947 if (dport->port == PORT_A)
1948 ironlake_edp_pll_on(intel_dp);
1949}
1950
1951static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1952{
2bd2ad64 1953 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1954 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1955 struct drm_device *dev = encoder->base.dev;
89b667f8 1956 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1957 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1958 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1959 int pipe = intel_crtc->pipe;
bf13e81b 1960 struct edp_power_seq power_seq;
ab1f90f9 1961 u32 val;
a4fc5ed6 1962
ab1f90f9 1963 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1964
ab3c759a 1965 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1966 val = 0;
1967 if (pipe)
1968 val |= (1<<21);
1969 else
1970 val &= ~(1<<21);
1971 val |= 0x001000c4;
ab3c759a
CML		 1972 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1973 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1974 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1975
ab1f90f9
JN		 1976 mutex_unlock(&dev_priv->dpio_lock);
1977
2cac613b
ID		 1978 if (is_edp(intel_dp)) {
1979 /* init power sequencer on this pipe and port */
1980 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1981 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1982 &power_seq);
1983 }
bf13e81b 1984
ab1f90f9
JN		 1985 intel_enable_dp(encoder);
1986
e4607fcf 1987 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1988}
1989
ecff4f3b 1990static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1991{
1992 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1993 struct drm_device *dev = encoder->base.dev;
1994 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1995 struct intel_crtc *intel_crtc =
1996 to_intel_crtc(encoder->base.crtc);
e4607fcf 1997 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1998 int pipe = intel_crtc->pipe;
89b667f8 1999
89b667f8 2000 /* Program Tx lane resets to default */
0980a60f 2001 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2002 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2003 DPIO_PCS_TX_LANE2_RESET |
2004 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2005 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2006 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2007 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2008 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2009 DPIO_PCS_CLK_SOFT_RESET);
2010
2011 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2012 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2013 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2014 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2015 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2016}
2017
2018/*
df0c237d
JB		 2019 * Native read with retry for link status and receiver capability reads for
2020 * cases where the sink may still be asleep.
a4fc5ed6
KP		 2021 */
2022static bool
df0c237d
JB		 2023intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
2024 uint8_t *recv, int recv_bytes)
a4fc5ed6 2025{
61da5fab
JB		 2026 int ret, i;
2027
df0c237d
JB		 2028 /*
2029 * Sinks are *supposed* to come up within 1ms from an off state,
2030 * but we're also supposed to retry 3 times per the spec.
2031 */
61da5fab 2032 for (i = 0; i < 3; i++) {
df0c237d
JB		 2033 ret = intel_dp_aux_native_read(intel_dp, address, recv,
2034 recv_bytes);
2035 if (ret == recv_bytes)
61da5fab
JB		 2036 return true;
2037 msleep(1);
2038 }
a4fc5ed6 2039
61da5fab 2040 return false;
a4fc5ed6
KP		 2041}
2042
2043/*
2044 * Fetch AUX CH registers 0x202 - 0x207 which contain
2045 * link status information
2046 */
2047static bool
93f62dad 2048intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2049{
df0c237d
JB		 2050 return intel_dp_aux_native_read_retry(intel_dp,
2051 DP_LANE0_1_STATUS,
93f62dad 2052 link_status,
df0c237d 2053 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 2054}
2055
a4fc5ed6
KP		 2056/*
2057 * These are source-specific values; current Intel hardware supports
2058 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2059 */
a4fc5ed6
KP		 2060
2061static uint8_t
1a2eb460 2062intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2063{
30add22d 2064 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2065 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2066
8f93f4f1 2067 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 2068 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2069 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2070 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2071 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2072 return DP_TRAIN_VOLTAGE_SWING_1200;
2073 else
2074 return DP_TRAIN_VOLTAGE_SWING_800;
2075}
2076
2077static uint8_t
2078intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2079{
30add22d 2080 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2081 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2082
8f93f4f1
PZ		 2083 if (IS_BROADWELL(dev)) {
2084 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2085 case DP_TRAIN_VOLTAGE_SWING_400:
2086 case DP_TRAIN_VOLTAGE_SWING_600:
2087 return DP_TRAIN_PRE_EMPHASIS_6;
2088 case DP_TRAIN_VOLTAGE_SWING_800:
2089 return DP_TRAIN_PRE_EMPHASIS_3_5;
2090 case DP_TRAIN_VOLTAGE_SWING_1200:
2091 default:
2092 return DP_TRAIN_PRE_EMPHASIS_0;
2093 }
2094 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 2095 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2096 case DP_TRAIN_VOLTAGE_SWING_400:
2097 return DP_TRAIN_PRE_EMPHASIS_9_5;
2098 case DP_TRAIN_VOLTAGE_SWING_600:
2099 return DP_TRAIN_PRE_EMPHASIS_6;
2100 case DP_TRAIN_VOLTAGE_SWING_800:
2101 return DP_TRAIN_PRE_EMPHASIS_3_5;
2102 case DP_TRAIN_VOLTAGE_SWING_1200:
2103 default:
2104 return DP_TRAIN_PRE_EMPHASIS_0;
2105 }
e2fa6fba
P		 2106 } else if (IS_VALLEYVIEW(dev)) {
2107 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2108 case DP_TRAIN_VOLTAGE_SWING_400:
2109 return DP_TRAIN_PRE_EMPHASIS_9_5;
2110 case DP_TRAIN_VOLTAGE_SWING_600:
2111 return DP_TRAIN_PRE_EMPHASIS_6;
2112 case DP_TRAIN_VOLTAGE_SWING_800:
2113 return DP_TRAIN_PRE_EMPHASIS_3_5;
2114 case DP_TRAIN_VOLTAGE_SWING_1200:
2115 default:
2116 return DP_TRAIN_PRE_EMPHASIS_0;
2117 }
bc7d38a4 2118 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2119 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2120 case DP_TRAIN_VOLTAGE_SWING_400:
2121 return DP_TRAIN_PRE_EMPHASIS_6;
2122 case DP_TRAIN_VOLTAGE_SWING_600:
2123 case DP_TRAIN_VOLTAGE_SWING_800:
2124 return DP_TRAIN_PRE_EMPHASIS_3_5;
2125 default:
2126 return DP_TRAIN_PRE_EMPHASIS_0;
2127 }
2128 } else {
2129 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2130 case DP_TRAIN_VOLTAGE_SWING_400:
2131 return DP_TRAIN_PRE_EMPHASIS_6;
2132 case DP_TRAIN_VOLTAGE_SWING_600:
2133 return DP_TRAIN_PRE_EMPHASIS_6;
2134 case DP_TRAIN_VOLTAGE_SWING_800:
2135 return DP_TRAIN_PRE_EMPHASIS_3_5;
2136 case DP_TRAIN_VOLTAGE_SWING_1200:
2137 default:
2138 return DP_TRAIN_PRE_EMPHASIS_0;
2139 }
a4fc5ed6
KP		 2140 }
2141}
2142
e2fa6fba
P		 2143static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2144{
2145 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2146 struct drm_i915_private *dev_priv = dev->dev_private;
2147 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2148 struct intel_crtc *intel_crtc =
2149 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2150 unsigned long demph_reg_value, preemph_reg_value,
2151 uniqtranscale_reg_value;
2152 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2153 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2154 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2155
2156 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2157 case DP_TRAIN_PRE_EMPHASIS_0:
2158 preemph_reg_value = 0x0004000;
2159 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2160 case DP_TRAIN_VOLTAGE_SWING_400:
2161 demph_reg_value = 0x2B405555;
2162 uniqtranscale_reg_value = 0x552AB83A;
2163 break;
2164 case DP_TRAIN_VOLTAGE_SWING_600:
2165 demph_reg_value = 0x2B404040;
2166 uniqtranscale_reg_value = 0x5548B83A;
2167 break;
2168 case DP_TRAIN_VOLTAGE_SWING_800:
2169 demph_reg_value = 0x2B245555;
2170 uniqtranscale_reg_value = 0x5560B83A;
2171 break;
2172 case DP_TRAIN_VOLTAGE_SWING_1200:
2173 demph_reg_value = 0x2B405555;
2174 uniqtranscale_reg_value = 0x5598DA3A;
2175 break;
2176 default:
2177 return 0;
2178 }
2179 break;
2180 case DP_TRAIN_PRE_EMPHASIS_3_5:
2181 preemph_reg_value = 0x0002000;
2182 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2183 case DP_TRAIN_VOLTAGE_SWING_400:
2184 demph_reg_value = 0x2B404040;
2185 uniqtranscale_reg_value = 0x5552B83A;
2186 break;
2187 case DP_TRAIN_VOLTAGE_SWING_600:
2188 demph_reg_value = 0x2B404848;
2189 uniqtranscale_reg_value = 0x5580B83A;
2190 break;
2191 case DP_TRAIN_VOLTAGE_SWING_800:
2192 demph_reg_value = 0x2B404040;
2193 uniqtranscale_reg_value = 0x55ADDA3A;
2194 break;
2195 default:
2196 return 0;
2197 }
2198 break;
2199 case DP_TRAIN_PRE_EMPHASIS_6:
2200 preemph_reg_value = 0x0000000;
2201 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2202 case DP_TRAIN_VOLTAGE_SWING_400:
2203 demph_reg_value = 0x2B305555;
2204 uniqtranscale_reg_value = 0x5570B83A;
2205 break;
2206 case DP_TRAIN_VOLTAGE_SWING_600:
2207 demph_reg_value = 0x2B2B4040;
2208 uniqtranscale_reg_value = 0x55ADDA3A;
2209 break;
2210 default:
2211 return 0;
2212 }
2213 break;
2214 case DP_TRAIN_PRE_EMPHASIS_9_5:
2215 preemph_reg_value = 0x0006000;
2216 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2217 case DP_TRAIN_VOLTAGE_SWING_400:
2218 demph_reg_value = 0x1B405555;
2219 uniqtranscale_reg_value = 0x55ADDA3A;
2220 break;
2221 default:
2222 return 0;
2223 }
2224 break;
2225 default:
2226 return 0;
2227 }
2228
0980a60f 2229 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2230 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2231 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2232 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2233 uniqtranscale_reg_value);
ab3c759a
CML		 2234 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2235 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2236 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2237 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2238 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2239
2240 return 0;
2241}
2242
a4fc5ed6 2243static void
0301b3ac
JN		 2244intel_get_adjust_train(struct intel_dp *intel_dp,
2245 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2246{
2247 uint8_t v = 0;
2248 uint8_t p = 0;
2249 int lane;
1a2eb460
KP		 2250 uint8_t voltage_max;
2251 uint8_t preemph_max;
a4fc5ed6 2252
33a34e4e 2253 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2254 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2255 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2256
2257 if (this_v > v)
2258 v = this_v;
2259 if (this_p > p)
2260 p = this_p;
2261 }
2262
1a2eb460 2263 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2264 if (v >= voltage_max)
2265 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2266
1a2eb460
KP		 2267 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2268 if (p >= preemph_max)
2269 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2270
2271 for (lane = 0; lane < 4; lane++)
33a34e4e 2272 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2273}
2274
2275static uint32_t
f0a3424e 2276intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2277{
3cf2efb1 2278 uint32_t signal_levels = 0;
a4fc5ed6 2279
3cf2efb1 2280 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2281 case DP_TRAIN_VOLTAGE_SWING_400:
2282 default:
2283 signal_levels |= DP_VOLTAGE_0_4;
2284 break;
2285 case DP_TRAIN_VOLTAGE_SWING_600:
2286 signal_levels |= DP_VOLTAGE_0_6;
2287 break;
2288 case DP_TRAIN_VOLTAGE_SWING_800:
2289 signal_levels |= DP_VOLTAGE_0_8;
2290 break;
2291 case DP_TRAIN_VOLTAGE_SWING_1200:
2292 signal_levels |= DP_VOLTAGE_1_2;
2293 break;
2294 }
3cf2efb1 2295 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2296 case DP_TRAIN_PRE_EMPHASIS_0:
2297 default:
2298 signal_levels |= DP_PRE_EMPHASIS_0;
2299 break;
2300 case DP_TRAIN_PRE_EMPHASIS_3_5:
2301 signal_levels |= DP_PRE_EMPHASIS_3_5;
2302 break;
2303 case DP_TRAIN_PRE_EMPHASIS_6:
2304 signal_levels |= DP_PRE_EMPHASIS_6;
2305 break;
2306 case DP_TRAIN_PRE_EMPHASIS_9_5:
2307 signal_levels |= DP_PRE_EMPHASIS_9_5;
2308 break;
2309 }
2310 return signal_levels;
2311}
2312
e3421a18
ZW		 2313/* Gen6's DP voltage swing and pre-emphasis control */
2314static uint32_t
2315intel_gen6_edp_signal_levels(uint8_t train_set)
2316{
3c5a62b5
YL		 2317 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2318 DP_TRAIN_PRE_EMPHASIS_MASK);
2319 switch (signal_levels) {
e3421a18 2320 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2321 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2322 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2323 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2324 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2325 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2326 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2327 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2328 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2329 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2330 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2331 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2332 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2333 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2334 default:
3c5a62b5
YL		 2335 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2336 "0x%x\n", signal_levels);
2337 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2338 }
2339}
2340
1a2eb460
KP		 2341/* Gen7's DP voltage swing and pre-emphasis control */
2342static uint32_t
2343intel_gen7_edp_signal_levels(uint8_t train_set)
2344{
2345 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2346 DP_TRAIN_PRE_EMPHASIS_MASK);
2347 switch (signal_levels) {
2348 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2349 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2350 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2351 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2352 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2353 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2354
2355 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2356 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2357 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2358 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2359
2360 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2361 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2362 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2363 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2364
2365 default:
2366 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2367 "0x%x\n", signal_levels);
2368 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2369 }
2370}
2371
d6c0d722
PZ		 2372/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2373static uint32_t
f0a3424e 2374intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2375{
d6c0d722
PZ		 2376 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2377 DP_TRAIN_PRE_EMPHASIS_MASK);
2378 switch (signal_levels) {
2379 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2380 return DDI_BUF_EMP_400MV_0DB_HSW;
2381 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2382 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2383 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2384 return DDI_BUF_EMP_400MV_6DB_HSW;
2385 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2386 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2387
d6c0d722
PZ		 2388 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2389 return DDI_BUF_EMP_600MV_0DB_HSW;
2390 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2391 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2392 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2393 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2394
d6c0d722
PZ		 2395 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2396 return DDI_BUF_EMP_800MV_0DB_HSW;
2397 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2398 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2399 default:
2400 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2401 "0x%x\n", signal_levels);
2402 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2403 }
a4fc5ed6
KP		 2404}
2405
8f93f4f1
PZ		 2406static uint32_t
2407intel_bdw_signal_levels(uint8_t train_set)
2408{
2409 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2410 DP_TRAIN_PRE_EMPHASIS_MASK);
2411 switch (signal_levels) {
2412 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2413 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2414 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2415 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2416 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2417 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2418
2419 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2420 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2421 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2422 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2423 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2424 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2425
2426 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2427 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2428 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2429 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2430
2431 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2432 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2433
2434 default:
2435 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2436 "0x%x\n", signal_levels);
2437 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2438 }
2439}
2440
f0a3424e
PZ		 2441/* Properly updates "DP" with the correct signal levels. */
2442static void
2443intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2444{
2445 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2446 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2447 struct drm_device *dev = intel_dig_port->base.base.dev;
2448 uint32_t signal_levels, mask;
2449 uint8_t train_set = intel_dp->train_set[0];
2450
8f93f4f1
PZ		 2451 if (IS_BROADWELL(dev)) {
2452 signal_levels = intel_bdw_signal_levels(train_set);
2453 mask = DDI_BUF_EMP_MASK;
2454 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2455 signal_levels = intel_hsw_signal_levels(train_set);
2456 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2457 } else if (IS_VALLEYVIEW(dev)) {
2458 signal_levels = intel_vlv_signal_levels(intel_dp);
2459 mask = 0;
bc7d38a4 2460 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2461 signal_levels = intel_gen7_edp_signal_levels(train_set);
2462 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2463 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2464 signal_levels = intel_gen6_edp_signal_levels(train_set);
2465 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2466 } else {
2467 signal_levels = intel_gen4_signal_levels(train_set);
2468 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2469 }
2470
2471 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2472
2473 *DP = (*DP & ~mask) | signal_levels;
2474}
2475
a4fc5ed6 2476static bool
ea5b213a 2477intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2478 uint32_t *DP,
58e10eb9 2479 uint8_t dp_train_pat)
a4fc5ed6 2480{
174edf1f
PZ		 2481 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2482 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2483 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2484 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2485 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2486 int ret, len;
a4fc5ed6 2487
22b8bf17 2488 if (HAS_DDI(dev)) {
3ab9c637 2489 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2490
2491 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2492 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2493 else
2494 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2495
2496 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2497 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2498 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2499 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2500
2501 break;
2502 case DP_TRAINING_PATTERN_1:
2503 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2504 break;
2505 case DP_TRAINING_PATTERN_2:
2506 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2507 break;
2508 case DP_TRAINING_PATTERN_3:
2509 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2510 break;
2511 }
174edf1f 2512 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2513
bc7d38a4 2514 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2515 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2516
2517 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2518 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2519 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2520 break;
2521 case DP_TRAINING_PATTERN_1:
70aff66c 2522 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2523 break;
2524 case DP_TRAINING_PATTERN_2:
70aff66c 2525 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2526 break;
2527 case DP_TRAINING_PATTERN_3:
2528 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2529 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2530 break;
2531 }
2532
2533 } else {
70aff66c 2534 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2535
2536 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2537 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2538 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2539 break;
2540 case DP_TRAINING_PATTERN_1:
70aff66c 2541 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2542 break;
2543 case DP_TRAINING_PATTERN_2:
70aff66c 2544 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2545 break;
2546 case DP_TRAINING_PATTERN_3:
2547 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2548 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2549 break;
2550 }
2551 }
2552
70aff66c 2553 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2554 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2555
2cdfe6c8
JN		 2556 buf[0] = dp_train_pat;
2557 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2558 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2559 /* don't write DP_TRAINING_LANEx_SET on disable */
2560 len = 1;
2561 } else {
2562 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2563 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2564 len = intel_dp->lane_count + 1;
47ea7542 2565 }
a4fc5ed6 2566
2cdfe6c8
JN		 2567 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2568 buf, len);
2569
2570 return ret == len;
a4fc5ed6
KP		 2571}
2572
70aff66c
JN		 2573static bool
2574intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2575 uint8_t dp_train_pat)
2576{
953d22e8 2577 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2578 intel_dp_set_signal_levels(intel_dp, DP);
2579 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2580}
2581
2582static bool
2583intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2584 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2585{
2586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2587 struct drm_device *dev = intel_dig_port->base.base.dev;
2588 struct drm_i915_private *dev_priv = dev->dev_private;
2589 int ret;
2590
2591 intel_get_adjust_train(intel_dp, link_status);
2592 intel_dp_set_signal_levels(intel_dp, DP);
2593
2594 I915_WRITE(intel_dp->output_reg, *DP);
2595 POSTING_READ(intel_dp->output_reg);
2596
2597 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2598 intel_dp->train_set,
2599 intel_dp->lane_count);
2600
2601 return ret == intel_dp->lane_count;
2602}
2603
3ab9c637
ID		 2604static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2605{
2606 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2607 struct drm_device *dev = intel_dig_port->base.base.dev;
2608 struct drm_i915_private *dev_priv = dev->dev_private;
2609 enum port port = intel_dig_port->port;
2610 uint32_t val;
2611
2612 if (!HAS_DDI(dev))
2613 return;
2614
2615 val = I915_READ(DP_TP_CTL(port));
2616 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2617 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2618 I915_WRITE(DP_TP_CTL(port), val);
2619
2620 /*
2621 * On PORT_A we can have only eDP in SST mode. There the only reason
2622 * we need to set idle transmission mode is to work around a HW issue
2623 * where we enable the pipe while not in idle link-training mode.
2624 * In this case there is requirement to wait for a minimum number of
2625 * idle patterns to be sent.
2626 */
2627 if (port == PORT_A)
2628 return;
2629
2630 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2631 1))
2632 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2633}
2634
33a34e4e 2635/* Enable corresponding port and start training pattern 1 */
c19b0669 2636void
33a34e4e 2637intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2638{
da63a9f2 2639 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2640 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2641 int i;
2642 uint8_t voltage;
cdb0e95b 2643 int voltage_tries, loop_tries;
ea5b213a 2644 uint32_t DP = intel_dp->DP;
6aba5b6c 2645 uint8_t link_config[2];
a4fc5ed6 2646
affa9354 2647 if (HAS_DDI(dev))
c19b0669
PZ		 2648 intel_ddi_prepare_link_retrain(encoder);
2649
3cf2efb1 2650 /* Write the link configuration data */
6aba5b6c
JN		 2651 link_config[0] = intel_dp->link_bw;
2652 link_config[1] = intel_dp->lane_count;
2653 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2654 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2655 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2656
2657 link_config[0] = 0;
2658 link_config[1] = DP_SET_ANSI_8B10B;
2659 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2660
2661 DP |= DP_PORT_EN;
1a2eb460 2662
70aff66c
JN		 2663 /* clock recovery */
2664 if (!intel_dp_reset_link_train(intel_dp, &DP,
2665 DP_TRAINING_PATTERN_1 |
2666 DP_LINK_SCRAMBLING_DISABLE)) {
2667 DRM_ERROR("failed to enable link training\n");
2668 return;
2669 }
2670
a4fc5ed6 2671 voltage = 0xff;
cdb0e95b
KP		 2672 voltage_tries = 0;
2673 loop_tries = 0;
a4fc5ed6 2674 for (;;) {
70aff66c 2675 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2676
a7c9655f 2677 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2678 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2679 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2680 break;
93f62dad 2681 }
a4fc5ed6 2682
01916270 2683 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2684 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2685 break;
2686 }
2687
2688 /* Check to see if we've tried the max voltage */
2689 for (i = 0; i < intel_dp->lane_count; i++)
2690 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2691 break;
3b4f819d 2692 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2693 ++loop_tries;
2694 if (loop_tries == 5) {
3def84b3 2695 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2696 break;
2697 }
70aff66c
JN		 2698 intel_dp_reset_link_train(intel_dp, &DP,
2699 DP_TRAINING_PATTERN_1 |
2700 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2701 voltage_tries = 0;
2702 continue;
2703 }
a4fc5ed6 2704
3cf2efb1 2705 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2706 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2707 ++voltage_tries;
b06fbda3 2708 if (voltage_tries == 5) {
3def84b3 2709 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2710 break;
2711 }
2712 } else
2713 voltage_tries = 0;
2714 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2715
70aff66c
JN		 2716 /* Update training set as requested by target */
2717 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2718 DRM_ERROR("failed to update link training\n");
2719 break;
2720 }
a4fc5ed6
KP		 2721 }
2722
33a34e4e
JB		 2723 intel_dp->DP = DP;
2724}
2725
c19b0669 2726void
33a34e4e
JB		 2727intel_dp_complete_link_train(struct intel_dp *intel_dp)
2728{
33a34e4e 2729 bool channel_eq = false;
37f80975 2730 int tries, cr_tries;
33a34e4e 2731 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 2732 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2733
2734 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2735 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2736 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 2737
a4fc5ed6 2738 /* channel equalization */
70aff66c 2739 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2740 training_pattern |
70aff66c
JN		 2741 DP_LINK_SCRAMBLING_DISABLE)) {
2742 DRM_ERROR("failed to start channel equalization\n");
2743 return;
2744 }
2745
a4fc5ed6 2746 tries = 0;
37f80975 2747 cr_tries = 0;
a4fc5ed6
KP		 2748 channel_eq = false;
2749 for (;;) {
70aff66c 2750 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2751
37f80975
JB		 2752 if (cr_tries > 5) {
2753 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2754 break;
2755 }
2756
a7c9655f 2757 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2758 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2759 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2760 break;
70aff66c 2761 }
a4fc5ed6 2762
37f80975 2763 /* Make sure clock is still ok */
01916270 2764 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2765 intel_dp_start_link_train(intel_dp);
70aff66c 2766 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2767 training_pattern |
70aff66c 2768 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2769 cr_tries++;
2770 continue;
2771 }
2772
1ffdff13 2773 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2774 channel_eq = true;
2775 break;
2776 }
a4fc5ed6 2777
37f80975
JB		 2778 /* Try 5 times, then try clock recovery if that fails */
2779 if (tries > 5) {
2780 intel_dp_link_down(intel_dp);
2781 intel_dp_start_link_train(intel_dp);
70aff66c 2782 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2783 training_pattern |
70aff66c 2784 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2785 tries = 0;
2786 cr_tries++;
2787 continue;
2788 }
a4fc5ed6 2789
70aff66c
JN		 2790 /* Update training set as requested by target */
2791 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2792 DRM_ERROR("failed to update link training\n");
2793 break;
2794 }
3cf2efb1 2795 ++tries;
869184a6 2796 }
3cf2efb1 2797
3ab9c637
ID		 2798 intel_dp_set_idle_link_train(intel_dp);
2799
2800 intel_dp->DP = DP;
2801
d6c0d722 2802 if (channel_eq)
07f42258 2803 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2804
3ab9c637
ID		 2805}
2806
2807void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2808{
70aff66c 2809 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2810 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2811}
2812
2813static void
ea5b213a 2814intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2815{
da63a9f2 2816 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2817 enum port port = intel_dig_port->port;
da63a9f2 2818 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2819 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2820 struct intel_crtc *intel_crtc =
2821 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2822 uint32_t DP = intel_dp->DP;
a4fc5ed6 2823
c19b0669
PZ		 2824 /*
2825 * DDI code has a strict mode set sequence and we should try to respect
2826 * it, otherwise we might hang the machine in many different ways. So we
2827 * really should be disabling the port only on a complete crtc_disable
2828 * sequence. This function is just called under two conditions on DDI
2829 * code:
2830 * - Link train failed while doing crtc_enable, and on this case we
2831 * really should respect the mode set sequence and wait for a
2832 * crtc_disable.
2833 * - Someone turned the monitor off and intel_dp_check_link_status
2834 * called us. We don't need to disable the whole port on this case, so
2835 * when someone turns the monitor on again,
2836 * intel_ddi_prepare_link_retrain will take care of redoing the link
2837 * train.
2838 */
affa9354 2839 if (HAS_DDI(dev))
c19b0669
PZ		 2840 return;
2841
0c33d8d7 2842 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2843 return;
2844
28c97730 2845 DRM_DEBUG_KMS("\n");
32f9d658 2846
bc7d38a4 2847 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2848 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2849 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2850 } else {
2851 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2852 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2853 }
fe255d00 2854 POSTING_READ(intel_dp->output_reg);
5eb08b69 2855
ab527efc
DV		 2856 /* We don't really know why we're doing this */
2857 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2858
493a7081 2859 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2860 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2861 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2862
5bddd17f
EA		 2863 /* Hardware workaround: leaving our transcoder select
2864 * set to transcoder B while it's off will prevent the
2865 * corresponding HDMI output on transcoder A.
2866 *
2867 * Combine this with another hardware workaround:
2868 * transcoder select bit can only be cleared while the
2869 * port is enabled.
2870 */
2871 DP &= ~DP_PIPEB_SELECT;
2872 I915_WRITE(intel_dp->output_reg, DP);
2873
2874 /* Changes to enable or select take place the vblank
2875 * after being written.
2876 */
ff50afe9
DV		 2877 if (WARN_ON(crtc == NULL)) {
2878 /* We should never try to disable a port without a crtc
2879 * attached. For paranoia keep the code around for a
2880 * bit. */
31acbcc4
CW		 2881 POSTING_READ(intel_dp->output_reg);
2882 msleep(50);
2883 } else
ab527efc 2884 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2885 }
2886
832afda6 2887 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2888 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2889 POSTING_READ(intel_dp->output_reg);
f01eca2e 2890 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2891}
2892
26d61aad
KP		 2893static bool
2894intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2895{
a031d709
RV		 2896 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2897 struct drm_device *dev = dig_port->base.base.dev;
2898 struct drm_i915_private *dev_priv = dev->dev_private;
2899
577c7a50
DL		 2900 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2901
92fd8fd1 2902 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2903 sizeof(intel_dp->dpcd)) == 0)
2904 return false; /* aux transfer failed */
92fd8fd1 2905
577c7a50
DL		 2906 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2907 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2908 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2909
edb39244
AJ		 2910 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2911 return false; /* DPCD not present */
2912
2293bb5c
SK		 2913 /* Check if the panel supports PSR */
2914 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939
JN		 2915 if (is_edp(intel_dp)) {
2916 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2917 intel_dp->psr_dpcd,
2918 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2919 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2920 dev_priv->psr.sink_support = true;
50003939 2921 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2922 }
50003939
JN		 2923 }
2924
06ea66b6
TP		 2925 /* Training Pattern 3 support */
2926 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2927 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2928 intel_dp->use_tps3 = true;
2929 DRM_DEBUG_KMS("Displayport TPS3 supported");
2930 } else
2931 intel_dp->use_tps3 = false;
2932
edb39244
AJ		 2933 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2934 DP_DWN_STRM_PORT_PRESENT))
2935 return true; /* native DP sink */
2936
2937 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2938 return true; /* no per-port downstream info */
2939
2940 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2941 intel_dp->downstream_ports,
2942 DP_MAX_DOWNSTREAM_PORTS) == 0)
2943 return false; /* downstream port status fetch failed */
2944
2945 return true;
92fd8fd1
KP		 2946}
2947
0d198328
AJ		 2948static void
2949intel_dp_probe_oui(struct intel_dp *intel_dp)
2950{
2951 u8 buf[3];
2952
2953 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2954 return;
2955
24f3e092 2956 intel_edp_panel_vdd_on(intel_dp);
351cfc34 2957
0d198328
AJ		 2958 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2959 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2960 buf[0], buf[1], buf[2]);
2961
2962 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2963 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2964 buf[0], buf[1], buf[2]);
351cfc34 2965
4be73780 2966 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2967}
2968
d2e216d0
RV		 2969int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2970{
2971 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2972 struct drm_device *dev = intel_dig_port->base.base.dev;
2973 struct intel_crtc *intel_crtc =
2974 to_intel_crtc(intel_dig_port->base.base.crtc);
2975 u8 buf[1];
2976
2977 if (!intel_dp_aux_native_read(intel_dp, DP_TEST_SINK_MISC, buf, 1))
2978 return -EAGAIN;
2979
2980 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2981 return -ENOTTY;
2982
2983 if (!intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK,
2984 DP_TEST_SINK_START))
2985 return -EAGAIN;
2986
2987 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2988 intel_wait_for_vblank(dev, intel_crtc->pipe);
2989 intel_wait_for_vblank(dev, intel_crtc->pipe);
2990
2991 if (!intel_dp_aux_native_read(intel_dp, DP_TEST_CRC_R_CR, crc, 6))
2992 return -EAGAIN;
2993
2994 intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK, 0);
2995 return 0;
2996}
2997
a60f0e38
JB		 2998static bool
2999intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3000{
3001 int ret;
3002
3003 ret = intel_dp_aux_native_read_retry(intel_dp,
3004 DP_DEVICE_SERVICE_IRQ_VECTOR,
3005 sink_irq_vector, 1);
3006 if (!ret)
3007 return false;
3008
3009 return true;
3010}
3011
3012static void
3013intel_dp_handle_test_request(struct intel_dp *intel_dp)
3014{
3015 /* NAK by default */
9324cf7f 3016 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3017}
3018
a4fc5ed6
KP		 3019/*
3020 * According to DP spec
3021 * 5.1.2:
3022 * 1. Read DPCD
3023 * 2. Configure link according to Receiver Capabilities
3024 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3025 * 4. Check link status on receipt of hot-plug interrupt
3026 */
3027
00c09d70 3028void
ea5b213a 3029intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3030{
da63a9f2 3031 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3032 u8 sink_irq_vector;
93f62dad 3033 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3034
da63a9f2 3035 if (!intel_encoder->connectors_active)
d2b996ac 3036 return;
59cd09e1 3037
da63a9f2 3038 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3039 return;
3040
92fd8fd1 3041 /* Try to read receiver status if the link appears to be up */
93f62dad 3042 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3043 return;
3044 }
3045
92fd8fd1 3046 /* Now read the DPCD to see if it's actually running */
26d61aad 3047 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3048 return;
3049 }
3050
a60f0e38
JB		 3051 /* Try to read the source of the interrupt */
3052 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3053 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3054 /* Clear interrupt source */
3055 intel_dp_aux_native_write_1(intel_dp,
3056 DP_DEVICE_SERVICE_IRQ_VECTOR,
3057 sink_irq_vector);
3058
3059 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3060 intel_dp_handle_test_request(intel_dp);
3061 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3062 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3063 }
3064
1ffdff13 3065 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3066 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 3067 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 3068 intel_dp_start_link_train(intel_dp);
3069 intel_dp_complete_link_train(intel_dp);
3ab9c637 3070 intel_dp_stop_link_train(intel_dp);
33a34e4e 3071 }
a4fc5ed6 3072}
a4fc5ed6 3073
caf9ab24 3074/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3075static enum drm_connector_status
26d61aad 3076intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3077{
caf9ab24 3078 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3079 uint8_t type;
3080
3081 if (!intel_dp_get_dpcd(intel_dp))
3082 return connector_status_disconnected;
3083
3084 /* if there's no downstream port, we're done */
3085 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3086 return connector_status_connected;
caf9ab24
AJ		 3087
3088 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3089 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3090 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3091 uint8_t reg;
caf9ab24 3092 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 3093 &reg, 1))
caf9ab24 3094 return connector_status_unknown;
23235177
AJ		 3095 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3096 : connector_status_disconnected;
caf9ab24
AJ		 3097 }
3098
3099 /* If no HPD, poke DDC gently */
3100 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 3101 return connector_status_connected;
caf9ab24
AJ		 3102
3103 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3104 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3105 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3106 if (type == DP_DS_PORT_TYPE_VGA ||
3107 type == DP_DS_PORT_TYPE_NON_EDID)
3108 return connector_status_unknown;
3109 } else {
3110 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3111 DP_DWN_STRM_PORT_TYPE_MASK;
3112 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3113 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3114 return connector_status_unknown;
3115 }
caf9ab24
AJ		 3116
3117 /* Anything else is out of spec, warn and ignore */
3118 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3119 return connector_status_disconnected;
71ba9000
AJ		 3120}
3121
5eb08b69 3122static enum drm_connector_status
a9756bb5 3123ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3124{
30add22d 3125 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3126 struct drm_i915_private *dev_priv = dev->dev_private;
3127 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3128 enum drm_connector_status status;
3129
fe16d949
CW		 3130 /* Can't disconnect eDP, but you can close the lid... */
3131 if (is_edp(intel_dp)) {
30add22d 3132 status = intel_panel_detect(dev);
fe16d949
CW		 3133 if (status == connector_status_unknown)
3134 status = connector_status_connected;
3135 return status;
3136 }
01cb9ea6 3137
1b469639
DL		 3138 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3139 return connector_status_disconnected;
3140
26d61aad 3141 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3142}
3143
a4fc5ed6 3144static enum drm_connector_status
a9756bb5 3145g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3146{
30add22d 3147 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3148 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3149 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3150 uint32_t bit;
5eb08b69 3151
35aad75f
JB		 3152 /* Can't disconnect eDP, but you can close the lid... */
3153 if (is_edp(intel_dp)) {
3154 enum drm_connector_status status;
3155
3156 status = intel_panel_detect(dev);
3157 if (status == connector_status_unknown)
3158 status = connector_status_connected;
3159 return status;
3160 }
3161
232a6ee9
TP		 3162 if (IS_VALLEYVIEW(dev)) {
3163 switch (intel_dig_port->port) {
3164 case PORT_B:
3165 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3166 break;
3167 case PORT_C:
3168 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3169 break;
3170 case PORT_D:
3171 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3172 break;
3173 default:
3174 return connector_status_unknown;
3175 }
3176 } else {
3177 switch (intel_dig_port->port) {
3178 case PORT_B:
3179 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3180 break;
3181 case PORT_C:
3182 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3183 break;
3184 case PORT_D:
3185 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3186 break;
3187 default:
3188 return connector_status_unknown;
3189 }
a4fc5ed6
KP		 3190 }
3191
10f76a38 3192 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3193 return connector_status_disconnected;
3194
26d61aad 3195 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3196}
3197
8c241fef
KP		 3198static struct edid *
3199intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3200{
9cd300e0 3201 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3202
9cd300e0
JN		 3203 /* use cached edid if we have one */
3204 if (intel_connector->edid) {
9cd300e0
JN		 3205 /* invalid edid */
3206 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3207 return NULL;
3208
55e9edeb 3209 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3210 }
8c241fef 3211
9cd300e0 3212 return drm_get_edid(connector, adapter);
8c241fef
KP		 3213}
3214
3215static int
3216intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3217{
9cd300e0 3218 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3219
9cd300e0
JN		 3220 /* use cached edid if we have one */
3221 if (intel_connector->edid) {
3222 /* invalid edid */
3223 if (IS_ERR(intel_connector->edid))
3224 return 0;
3225
3226 return intel_connector_update_modes(connector,
3227 intel_connector->edid);
d6f24d0f
JB		 3228 }
3229
9cd300e0 3230 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3231}
3232
a9756bb5
ZW		 3233static enum drm_connector_status
3234intel_dp_detect(struct drm_connector *connector, bool force)
3235{
3236 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3237 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3238 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3239 struct drm_device *dev = connector->dev;
c8c8fb33 3240 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3241 enum drm_connector_status status;
671dedd2 3242 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3243 struct edid *edid = NULL;
3244
c8c8fb33
PZ		 3245 intel_runtime_pm_get(dev_priv);
3246
671dedd2
ID		 3247 power_domain = intel_display_port_power_domain(intel_encoder);
3248 intel_display_power_get(dev_priv, power_domain);
3249
164c8598
CW		 3250 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3251 connector->base.id, drm_get_connector_name(connector));
3252
a9756bb5
ZW		 3253 intel_dp->has_audio = false;
3254
3255 if (HAS_PCH_SPLIT(dev))
3256 status = ironlake_dp_detect(intel_dp);
3257 else
3258 status = g4x_dp_detect(intel_dp);
1b9be9d0 3259
a9756bb5 3260 if (status != connector_status_connected)
c8c8fb33 3261 goto out;
a9756bb5 3262
0d198328
AJ		 3263 intel_dp_probe_oui(intel_dp);
3264
c3e5f67b
DV		 3265 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3266 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3267 } else {
8c241fef 3268 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 3269 if (edid) {
3270 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3271 kfree(edid);
3272 }
a9756bb5
ZW		 3273 }
3274
d63885da
PZ		 3275 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3276 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3277 status = connector_status_connected;
3278
3279out:
671dedd2
ID		 3280 intel_display_power_put(dev_priv, power_domain);
3281
c8c8fb33 3282 intel_runtime_pm_put(dev_priv);
671dedd2 3283
c8c8fb33 3284 return status;
a4fc5ed6
KP		 3285}
3286
3287static int intel_dp_get_modes(struct drm_connector *connector)
3288{
df0e9248 3289 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3290 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3291 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3292 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3293 struct drm_device *dev = connector->dev;
671dedd2
ID		 3294 struct drm_i915_private *dev_priv = dev->dev_private;
3295 enum intel_display_power_domain power_domain;
32f9d658 3296 int ret;
a4fc5ed6
KP		 3297
3298 /* We should parse the EDID data and find out if it has an audio sink
3299 */
3300
671dedd2
ID		 3301 power_domain = intel_display_port_power_domain(intel_encoder);
3302 intel_display_power_get(dev_priv, power_domain);
3303
8c241fef 3304 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
671dedd2 3305 intel_display_power_put(dev_priv, power_domain);
f8779fda 3306 if (ret)
32f9d658
ZW		 3307 return ret;
3308
f8779fda 3309 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3310 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3311 struct drm_display_mode *mode;
dd06f90e
JN		 3312 mode = drm_mode_duplicate(dev,
3313 intel_connector->panel.fixed_mode);
f8779fda 3314 if (mode) {
32f9d658
ZW		 3315 drm_mode_probed_add(connector, mode);
3316 return 1;
3317 }
3318 }
3319 return 0;
a4fc5ed6
KP		 3320}
3321
1aad7ac0
CW		 3322static bool
3323intel_dp_detect_audio(struct drm_connector *connector)
3324{
3325 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3326 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3327 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3328 struct drm_device *dev = connector->dev;
3329 struct drm_i915_private *dev_priv = dev->dev_private;
3330 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3331 struct edid *edid;
3332 bool has_audio = false;
3333
671dedd2
ID		 3334 power_domain = intel_display_port_power_domain(intel_encoder);
3335 intel_display_power_get(dev_priv, power_domain);
3336
8c241fef 3337 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 3338 if (edid) {
3339 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3340 kfree(edid);
3341 }
3342
671dedd2
ID		 3343 intel_display_power_put(dev_priv, power_domain);
3344
1aad7ac0
CW		 3345 return has_audio;
3346}
3347
f684960e
CW		 3348static int
3349intel_dp_set_property(struct drm_connector *connector,
3350 struct drm_property *property,
3351 uint64_t val)
3352{
e953fd7b 3353 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3354 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3355 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3356 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3357 int ret;
3358
662595df 3359 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3360 if (ret)
3361 return ret;
3362
3f43c48d 3363 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3364 int i = val;
3365 bool has_audio;
3366
3367 if (i == intel_dp->force_audio)
f684960e
CW		 3368 return 0;
3369
1aad7ac0 3370 intel_dp->force_audio = i;
f684960e 3371
c3e5f67b 3372 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3373 has_audio = intel_dp_detect_audio(connector);
3374 else
c3e5f67b 3375 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3376
3377 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3378 return 0;
3379
1aad7ac0 3380 intel_dp->has_audio = has_audio;
f684960e
CW		 3381 goto done;
3382 }
3383
e953fd7b 3384 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3385 bool old_auto = intel_dp->color_range_auto;
3386 uint32_t old_range = intel_dp->color_range;
3387
55bc60db
VS		 3388 switch (val) {
3389 case INTEL_BROADCAST_RGB_AUTO:
3390 intel_dp->color_range_auto = true;
3391 break;
3392 case INTEL_BROADCAST_RGB_FULL:
3393 intel_dp->color_range_auto = false;
3394 intel_dp->color_range = 0;
3395 break;
3396 case INTEL_BROADCAST_RGB_LIMITED:
3397 intel_dp->color_range_auto = false;
3398 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3399 break;
3400 default:
3401 return -EINVAL;
3402 }
ae4edb80
DV		 3403
3404 if (old_auto == intel_dp->color_range_auto &&
3405 old_range == intel_dp->color_range)
3406 return 0;
3407
e953fd7b
CW		 3408 goto done;
3409 }
3410
53b41837
YN		 3411 if (is_edp(intel_dp) &&
3412 property == connector->dev->mode_config.scaling_mode_property) {
3413 if (val == DRM_MODE_SCALE_NONE) {
3414 DRM_DEBUG_KMS("no scaling not supported\n");
3415 return -EINVAL;
3416 }
3417
3418 if (intel_connector->panel.fitting_mode == val) {
3419 /* the eDP scaling property is not changed */
3420 return 0;
3421 }
3422 intel_connector->panel.fitting_mode = val;
3423
3424 goto done;
3425 }
3426
f684960e
CW		 3427 return -EINVAL;
3428
3429done:
c0c36b94
CW		 3430 if (intel_encoder->base.crtc)
3431 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3432
3433 return 0;
3434}
3435
a4fc5ed6 3436static void
73845adf 3437intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3438{
1d508706 3439 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3440
9cd300e0
JN		 3441 if (!IS_ERR_OR_NULL(intel_connector->edid))
3442 kfree(intel_connector->edid);
3443
acd8db10
PZ		 3444 /* Can't call is_edp() since the encoder may have been destroyed
3445 * already. */
3446 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3447 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3448
a4fc5ed6 3449 drm_connector_cleanup(connector);
55f78c43 3450 kfree(connector);
a4fc5ed6
KP		 3451}
3452
00c09d70 3453void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3454{
da63a9f2
PZ		 3455 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3456 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3457 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 3458
3459 i2c_del_adapter(&intel_dp->adapter);
3460 drm_encoder_cleanup(encoder);
bd943159
KP		 3461 if (is_edp(intel_dp)) {
3462 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3463 mutex_lock(&dev->mode_config.mutex);
4be73780 3464 edp_panel_vdd_off_sync(intel_dp);
bd173813 3465 mutex_unlock(&dev->mode_config.mutex);
bd943159 3466 }
da63a9f2 3467 kfree(intel_dig_port);
24d05927
DV		 3468}
3469
a4fc5ed6 3470static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3471 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3472 .detect = intel_dp_detect,
3473 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3474 .set_property = intel_dp_set_property,
73845adf 3475 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3476};
3477
3478static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3479 .get_modes = intel_dp_get_modes,
3480 .mode_valid = intel_dp_mode_valid,
df0e9248 3481 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3482};
3483
a4fc5ed6 3484static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3485 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3486};
3487
995b6762 3488static void
21d40d37 3489intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3490{
fa90ecef 3491 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3492
885a5014 3493 intel_dp_check_link_status(intel_dp);
c8110e52 3494}
6207937d 3495
e3421a18
ZW		 3496/* Return which DP Port should be selected for Transcoder DP control */
3497int
0206e353 3498intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3499{
3500 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3501 struct intel_encoder *intel_encoder;
3502 struct intel_dp *intel_dp;
e3421a18 3503
fa90ecef
PZ		 3504 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3505 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3506
fa90ecef
PZ		 3507 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3508 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3509 return intel_dp->output_reg;
e3421a18 3510 }
ea5b213a 3511
e3421a18
ZW		 3512 return -1;
3513}
3514
36e83a18 3515/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3516bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3517{
3518 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3519 union child_device_config *p_child;
36e83a18 3520 int i;
5d8a7752
VS		 3521 static const short port_mapping[] = {
3522 [PORT_B] = PORT_IDPB,
3523 [PORT_C] = PORT_IDPC,
3524 [PORT_D] = PORT_IDPD,
3525 };
36e83a18 3526
3b32a35b
VS		 3527 if (port == PORT_A)
3528 return true;
3529
41aa3448 3530 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3531 return false;
3532
41aa3448
RV		 3533 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3534 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3535
5d8a7752 3536 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3537 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3538 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3539 return true;
3540 }
3541 return false;
3542}
3543
f684960e
CW		 3544static void
3545intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3546{
53b41837
YN		 3547 struct intel_connector *intel_connector = to_intel_connector(connector);
3548
3f43c48d 3549 intel_attach_force_audio_property(connector);
e953fd7b 3550 intel_attach_broadcast_rgb_property(connector);
55bc60db 3551 intel_dp->color_range_auto = true;
53b41837
YN		 3552
3553 if (is_edp(intel_dp)) {
3554 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3555 drm_object_attach_property(
3556 &connector->base,
53b41837 3557 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3558 DRM_MODE_SCALE_ASPECT);
3559 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3560 }
f684960e
CW		 3561}
3562
dada1a9f
ID		 3563static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3564{
3565 intel_dp->last_power_cycle = jiffies;
3566 intel_dp->last_power_on = jiffies;
3567 intel_dp->last_backlight_off = jiffies;
3568}
3569
67a54566
DV		 3570static void
3571intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3572 struct intel_dp *intel_dp,
3573 struct edp_power_seq *out)
67a54566
DV		 3574{
3575 struct drm_i915_private *dev_priv = dev->dev_private;
3576 struct edp_power_seq cur, vbt, spec, final;
3577 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3578 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3579
3580 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3581 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3582 pp_on_reg = PCH_PP_ON_DELAYS;
3583 pp_off_reg = PCH_PP_OFF_DELAYS;
3584 pp_div_reg = PCH_PP_DIVISOR;
3585 } else {
bf13e81b
JN		 3586 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3587
3588 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3589 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3590 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3591 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3592 }
67a54566
DV		 3593
3594 /* Workaround: Need to write PP_CONTROL with the unlock key as
3595 * the very first thing. */
453c5420 3596 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3597 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3598
453c5420
JB		 3599 pp_on = I915_READ(pp_on_reg);
3600 pp_off = I915_READ(pp_off_reg);
3601 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3602
3603 /* Pull timing values out of registers */
3604 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3605 PANEL_POWER_UP_DELAY_SHIFT;
3606
3607 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3608 PANEL_LIGHT_ON_DELAY_SHIFT;
3609
3610 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3611 PANEL_LIGHT_OFF_DELAY_SHIFT;
3612
3613 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3614 PANEL_POWER_DOWN_DELAY_SHIFT;
3615
3616 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3617 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3618
3619 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3620 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3621
41aa3448 3622 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3623
3624 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3625 * our hw here, which are all in 100usec. */
3626 spec.t1_t3 = 210 * 10;
3627 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3628 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3629 spec.t10 = 500 * 10;
3630 /* This one is special and actually in units of 100ms, but zero
3631 * based in the hw (so we need to add 100 ms). But the sw vbt
3632 * table multiplies it with 1000 to make it in units of 100usec,
3633 * too. */
3634 spec.t11_t12 = (510 + 100) * 10;
3635
3636 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3637 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3638
3639 /* Use the max of the register settings and vbt. If both are
3640 * unset, fall back to the spec limits. */
3641#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3642 spec.field : \
3643 max(cur.field, vbt.field))
3644 assign_final(t1_t3);
3645 assign_final(t8);
3646 assign_final(t9);
3647 assign_final(t10);
3648 assign_final(t11_t12);
3649#undef assign_final
3650
3651#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3652 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3653 intel_dp->backlight_on_delay = get_delay(t8);
3654 intel_dp->backlight_off_delay = get_delay(t9);
3655 intel_dp->panel_power_down_delay = get_delay(t10);
3656 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3657#undef get_delay
3658
f30d26e4
JN		 3659 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3660 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3661 intel_dp->panel_power_cycle_delay);
3662
3663 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3664 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3665
3666 if (out)
3667 *out = final;
3668}
3669
3670static void
3671intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3672 struct intel_dp *intel_dp,
3673 struct edp_power_seq *seq)
3674{
3675 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3676 u32 pp_on, pp_off, pp_div, port_sel = 0;
3677 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3678 int pp_on_reg, pp_off_reg, pp_div_reg;
3679
3680 if (HAS_PCH_SPLIT(dev)) {
3681 pp_on_reg = PCH_PP_ON_DELAYS;
3682 pp_off_reg = PCH_PP_OFF_DELAYS;
3683 pp_div_reg = PCH_PP_DIVISOR;
3684 } else {
bf13e81b
JN		 3685 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3686
3687 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3688 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3689 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3690 }
3691
b2f19d1a
PZ		 3692 /*
3693 * And finally store the new values in the power sequencer. The
3694 * backlight delays are set to 1 because we do manual waits on them. For
3695 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3696 * we'll end up waiting for the backlight off delay twice: once when we
3697 * do the manual sleep, and once when we disable the panel and wait for
3698 * the PP_STATUS bit to become zero.
3699 */
f30d26e4 3700 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 3701 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3702 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 3703 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3704 /* Compute the divisor for the pp clock, simply match the Bspec
3705 * formula. */
453c5420 3706 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3707 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3708 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3709
3710 /* Haswell doesn't have any port selection bits for the panel
3711 * power sequencer any more. */
bc7d38a4 3712 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3713 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3714 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3715 else
3716 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3717 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3718 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3719 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3720 else
a24c144c 3721 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3722 }
3723
453c5420
JB		 3724 pp_on |= port_sel;
3725
3726 I915_WRITE(pp_on_reg, pp_on);
3727 I915_WRITE(pp_off_reg, pp_off);
3728 I915_WRITE(pp_div_reg, pp_div);
67a54566 3729
67a54566 3730 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3731 I915_READ(pp_on_reg),
3732 I915_READ(pp_off_reg),
3733 I915_READ(pp_div_reg));
f684960e
CW		 3734}
3735
ed92f0b2 3736static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 3737 struct intel_connector *intel_connector,
3738 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 3739{
3740 struct drm_connector *connector = &intel_connector->base;
3741 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3742 struct drm_device *dev = intel_dig_port->base.base.dev;
3743 struct drm_i915_private *dev_priv = dev->dev_private;
3744 struct drm_display_mode *fixed_mode = NULL;
ed92f0b2
PZ		 3745 bool has_dpcd;
3746 struct drm_display_mode *scan;
3747 struct edid *edid;
3748
3749 if (!is_edp(intel_dp))
3750 return true;
3751
ed92f0b2 3752 /* Cache DPCD and EDID for edp. */
24f3e092 3753 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 3754 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 3755 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 3756
3757 if (has_dpcd) {
3758 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3759 dev_priv->no_aux_handshake =
3760 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3761 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3762 } else {
3763 /* if this fails, presume the device is a ghost */
3764 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3765 return false;
3766 }
3767
3768 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 3769 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 3770
ed92f0b2
PZ		 3771 edid = drm_get_edid(connector, &intel_dp->adapter);
3772 if (edid) {
3773 if (drm_add_edid_modes(connector, edid)) {
3774 drm_mode_connector_update_edid_property(connector,
3775 edid);
3776 drm_edid_to_eld(connector, edid);
3777 } else {
3778 kfree(edid);
3779 edid = ERR_PTR(-EINVAL);
3780 }
3781 } else {
3782 edid = ERR_PTR(-ENOENT);
3783 }
3784 intel_connector->edid = edid;
3785
3786 /* prefer fixed mode from EDID if available */
3787 list_for_each_entry(scan, &connector->probed_modes, head) {
3788 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3789 fixed_mode = drm_mode_duplicate(dev, scan);
3790 break;
3791 }
3792 }
3793
3794 /* fallback to VBT if available for eDP */
3795 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3796 fixed_mode = drm_mode_duplicate(dev,
3797 dev_priv->vbt.lfp_lvds_vbt_mode);
3798 if (fixed_mode)
3799 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3800 }
3801
4b6ed685 3802 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
ed92f0b2
PZ		 3803 intel_panel_setup_backlight(connector);
3804
3805 return true;
3806}
3807
16c25533 3808bool
f0fec3f2
PZ		 3809intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3810 struct intel_connector *intel_connector)
a4fc5ed6 3811{
f0fec3f2
PZ		 3812 struct drm_connector *connector = &intel_connector->base;
3813 struct intel_dp *intel_dp = &intel_dig_port->dp;
3814 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3815 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3816 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3817 enum port port = intel_dig_port->port;
0095e6dc 3818 struct edp_power_seq power_seq = { 0 };
5eb08b69 3819 const char *name = NULL;
b2a14755 3820 int type, error;
a4fc5ed6 3821
ec5b01dd
DL		 3822 /* intel_dp vfuncs */
3823 if (IS_VALLEYVIEW(dev))
3824 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3825 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3826 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3827 else if (HAS_PCH_SPLIT(dev))
3828 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3829 else
3830 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3831
153b1100
DL		 3832 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3833
0767935e
DV		 3834 /* Preserve the current hw state. */
3835 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3836 intel_dp->attached_connector = intel_connector;
3d3dc149 3837
3b32a35b 3838 if (intel_dp_is_edp(dev, port))
b329530c 3839 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 3840 else
3841 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 3842
f7d24902
ID		 3843 /*
3844 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3845 * for DP the encoder type can be set by the caller to
3846 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3847 */
3848 if (type == DRM_MODE_CONNECTOR_eDP)
3849 intel_encoder->type = INTEL_OUTPUT_EDP;
3850
e7281eab
ID		 3851 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3852 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3853 port_name(port));
3854
b329530c 3855 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3856 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3857
a4fc5ed6
KP		 3858 connector->interlace_allowed = true;
3859 connector->doublescan_allowed = 0;
3860
f0fec3f2 3861 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 3862 edp_panel_vdd_work);
a4fc5ed6 3863
df0e9248 3864 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3865 drm_sysfs_connector_add(connector);
3866
affa9354 3867 if (HAS_DDI(dev))
bcbc889b
PZ		 3868 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3869 else
3870 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 3871 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 3872
9ed35ab1
PZ		 3873 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3874 if (HAS_DDI(dev)) {
3875 switch (intel_dig_port->port) {
3876 case PORT_A:
3877 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3878 break;
3879 case PORT_B:
3880 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3881 break;
3882 case PORT_C:
3883 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3884 break;
3885 case PORT_D:
3886 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3887 break;
3888 default:
3889 BUG();
3890 }
3891 }
e8cb4558 3892
a4fc5ed6 3893 /* Set up the DDC bus. */
ab9d7c30
PZ		 3894 switch (port) {
3895 case PORT_A:
1d843f9d 3896 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3897 name = "DPDDC-A";
3898 break;
3899 case PORT_B:
1d843f9d 3900 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3901 name = "DPDDC-B";
3902 break;
3903 case PORT_C:
1d843f9d 3904 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3905 name = "DPDDC-C";
3906 break;
3907 case PORT_D:
1d843f9d 3908 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3909 name = "DPDDC-D";
3910 break;
3911 default:
ad1c0b19 3912 BUG();
5eb08b69
ZW		 3913 }
3914
dada1a9f
ID		 3915 if (is_edp(intel_dp)) {
3916 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 3917 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 3918 }
0095e6dc 3919
b2a14755
PZ		 3920 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3921 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3922 error, port_name(port));
c1f05264 3923
2b28bb1b
RV		 3924 intel_dp->psr_setup_done = false;
3925
0095e6dc 3926 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
15b1d171
PZ		 3927 i2c_del_adapter(&intel_dp->adapter);
3928 if (is_edp(intel_dp)) {
3929 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3930 mutex_lock(&dev->mode_config.mutex);
4be73780 3931 edp_panel_vdd_off_sync(intel_dp);
15b1d171
PZ		 3932 mutex_unlock(&dev->mode_config.mutex);
3933 }
b2f246a8
PZ		 3934 drm_sysfs_connector_remove(connector);
3935 drm_connector_cleanup(connector);
16c25533 3936 return false;
b2f246a8 3937 }
32f9d658 3938
f684960e
CW		 3939 intel_dp_add_properties(intel_dp, connector);
3940
a4fc5ed6
KP		 3941 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3942 * 0xd. Failure to do so will result in spurious interrupts being
3943 * generated on the port when a cable is not attached.
3944 */
3945 if (IS_G4X(dev) && !IS_GM45(dev)) {
3946 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3947 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3948 }
16c25533
PZ		 3949
3950 return true;
a4fc5ed6 3951}
f0fec3f2
PZ		 3952
3953void
3954intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3955{
3956 struct intel_digital_port *intel_dig_port;
3957 struct intel_encoder *intel_encoder;
3958 struct drm_encoder *encoder;
3959 struct intel_connector *intel_connector;
3960
b14c5679 3961 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3962 if (!intel_dig_port)
3963 return;
3964
b14c5679 3965 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3966 if (!intel_connector) {
3967 kfree(intel_dig_port);
3968 return;
3969 }
3970
3971 intel_encoder = &intel_dig_port->base;
3972 encoder = &intel_encoder->base;
3973
3974 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3975 DRM_MODE_ENCODER_TMDS);
3976
5bfe2ac0 3977 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3978 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3979 intel_encoder->disable = intel_disable_dp;
3980 intel_encoder->post_disable = intel_post_disable_dp;
3981 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3982 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3983 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3984 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3985 intel_encoder->pre_enable = vlv_pre_enable_dp;
3986 intel_encoder->enable = vlv_enable_dp;
3987 } else {
ecff4f3b
JN		 3988 intel_encoder->pre_enable = g4x_pre_enable_dp;
3989 intel_encoder->enable = g4x_enable_dp;
ab1f90f9 3990 }
f0fec3f2 3991
174edf1f 3992 intel_dig_port->port = port;
f0fec3f2
PZ		 3993 intel_dig_port->dp.output_reg = output_reg;
3994
00c09d70 3995 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2 3996 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 3997 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 3998 intel_encoder->hot_plug = intel_dp_hot_plug;
3999
15b1d171
PZ		 4000 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4001 drm_encoder_cleanup(encoder);
4002 kfree(intel_dig_port);
b2f246a8 4003 kfree(intel_connector);
15b1d171 4004 }
f0fec3f2 4005}
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