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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/drm_crtc.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_edid.h> | |
a4fc5ed6 | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
a4fc5ed6 | 37 | #include "i915_drv.h" |
a4fc5ed6 | 38 | |
a4fc5ed6 KP |
39 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
40 | ||
9dd4ffdf CML |
41 | struct dp_link_dpll { |
42 | int link_bw; | |
43 | struct dpll dpll; | |
44 | }; | |
45 | ||
46 | static const struct dp_link_dpll gen4_dpll[] = { | |
47 | { DP_LINK_BW_1_62, | |
48 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, | |
49 | { DP_LINK_BW_2_7, | |
50 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } | |
51 | }; | |
52 | ||
53 | static const struct dp_link_dpll pch_dpll[] = { | |
54 | { DP_LINK_BW_1_62, | |
55 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, | |
56 | { DP_LINK_BW_2_7, | |
57 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } | |
58 | }; | |
59 | ||
65ce4bf5 CML |
60 | static const struct dp_link_dpll vlv_dpll[] = { |
61 | { DP_LINK_BW_1_62, | |
58f6e632 | 62 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
65ce4bf5 CML |
63 | { DP_LINK_BW_2_7, |
64 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } | |
65 | }; | |
66 | ||
cfcb0fc9 JB |
67 | /** |
68 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
69 | * @intel_dp: DP struct | |
70 | * | |
71 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
72 | * will return true, and false otherwise. | |
73 | */ | |
74 | static bool is_edp(struct intel_dp *intel_dp) | |
75 | { | |
da63a9f2 PZ |
76 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
77 | ||
78 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
79 | } |
80 | ||
68b4d824 | 81 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
cfcb0fc9 | 82 | { |
68b4d824 ID |
83 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
84 | ||
85 | return intel_dig_port->base.base.dev; | |
cfcb0fc9 JB |
86 | } |
87 | ||
df0e9248 CW |
88 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
89 | { | |
fa90ecef | 90 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
91 | } |
92 | ||
ea5b213a | 93 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
4be73780 DV |
94 | static void edp_panel_vdd_on(struct intel_dp *intel_dp); |
95 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); | |
a4fc5ed6 | 96 | |
a4fc5ed6 | 97 | static int |
ea5b213a | 98 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 99 | { |
7183dc29 | 100 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
06ea66b6 | 101 | struct drm_device *dev = intel_dp->attached_connector->base.dev; |
a4fc5ed6 KP |
102 | |
103 | switch (max_link_bw) { | |
104 | case DP_LINK_BW_1_62: | |
105 | case DP_LINK_BW_2_7: | |
106 | break; | |
d4eead50 | 107 | case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ |
06ea66b6 TP |
108 | if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) && |
109 | intel_dp->dpcd[DP_DPCD_REV] >= 0x12) | |
110 | max_link_bw = DP_LINK_BW_5_4; | |
111 | else | |
112 | max_link_bw = DP_LINK_BW_2_7; | |
d4eead50 | 113 | break; |
a4fc5ed6 | 114 | default: |
d4eead50 ID |
115 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
116 | max_link_bw); | |
a4fc5ed6 KP |
117 | max_link_bw = DP_LINK_BW_1_62; |
118 | break; | |
119 | } | |
120 | return max_link_bw; | |
121 | } | |
122 | ||
cd9dde44 AJ |
123 | /* |
124 | * The units on the numbers in the next two are... bizarre. Examples will | |
125 | * make it clearer; this one parallels an example in the eDP spec. | |
126 | * | |
127 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: | |
128 | * | |
129 | * 270000 * 1 * 8 / 10 == 216000 | |
130 | * | |
131 | * The actual data capacity of that configuration is 2.16Gbit/s, so the | |
132 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - | |
133 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be | |
134 | * 119000. At 18bpp that's 2142000 kilobits per second. | |
135 | * | |
136 | * Thus the strange-looking division by 10 in intel_dp_link_required, to | |
137 | * get the result in decakilobits instead of kilobits. | |
138 | */ | |
139 | ||
a4fc5ed6 | 140 | static int |
c898261c | 141 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 142 | { |
cd9dde44 | 143 | return (pixel_clock * bpp + 9) / 10; |
a4fc5ed6 KP |
144 | } |
145 | ||
fe27d53e DA |
146 | static int |
147 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
148 | { | |
149 | return (max_link_clock * max_lanes * 8) / 10; | |
150 | } | |
151 | ||
c19de8eb | 152 | static enum drm_mode_status |
a4fc5ed6 KP |
153 | intel_dp_mode_valid(struct drm_connector *connector, |
154 | struct drm_display_mode *mode) | |
155 | { | |
df0e9248 | 156 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e JN |
157 | struct intel_connector *intel_connector = to_intel_connector(connector); |
158 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
36008365 DV |
159 | int target_clock = mode->clock; |
160 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
a4fc5ed6 | 161 | |
dd06f90e JN |
162 | if (is_edp(intel_dp) && fixed_mode) { |
163 | if (mode->hdisplay > fixed_mode->hdisplay) | |
7de56f43 ZY |
164 | return MODE_PANEL; |
165 | ||
dd06f90e | 166 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 167 | return MODE_PANEL; |
03afc4a2 DV |
168 | |
169 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
170 | } |
171 | ||
36008365 DV |
172 | max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); |
173 | max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); | |
174 | ||
175 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
176 | mode_rate = intel_dp_link_required(target_clock, 18); | |
177 | ||
178 | if (mode_rate > max_rate) | |
c4867936 | 179 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
180 | |
181 | if (mode->clock < 10000) | |
182 | return MODE_CLOCK_LOW; | |
183 | ||
0af78a2b DV |
184 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
185 | return MODE_H_ILLEGAL; | |
186 | ||
a4fc5ed6 KP |
187 | return MODE_OK; |
188 | } | |
189 | ||
190 | static uint32_t | |
191 | pack_aux(uint8_t *src, int src_bytes) | |
192 | { | |
193 | int i; | |
194 | uint32_t v = 0; | |
195 | ||
196 | if (src_bytes > 4) | |
197 | src_bytes = 4; | |
198 | for (i = 0; i < src_bytes; i++) | |
199 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
200 | return v; | |
201 | } | |
202 | ||
203 | static void | |
204 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
205 | { | |
206 | int i; | |
207 | if (dst_bytes > 4) | |
208 | dst_bytes = 4; | |
209 | for (i = 0; i < dst_bytes; i++) | |
210 | dst[i] = src >> ((3-i) * 8); | |
211 | } | |
212 | ||
fb0f8fbf KP |
213 | /* hrawclock is 1/4 the FSB frequency */ |
214 | static int | |
215 | intel_hrawclk(struct drm_device *dev) | |
216 | { | |
217 | struct drm_i915_private *dev_priv = dev->dev_private; | |
218 | uint32_t clkcfg; | |
219 | ||
9473c8f4 VP |
220 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
221 | if (IS_VALLEYVIEW(dev)) | |
222 | return 200; | |
223 | ||
fb0f8fbf KP |
224 | clkcfg = I915_READ(CLKCFG); |
225 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
226 | case CLKCFG_FSB_400: | |
227 | return 100; | |
228 | case CLKCFG_FSB_533: | |
229 | return 133; | |
230 | case CLKCFG_FSB_667: | |
231 | return 166; | |
232 | case CLKCFG_FSB_800: | |
233 | return 200; | |
234 | case CLKCFG_FSB_1067: | |
235 | return 266; | |
236 | case CLKCFG_FSB_1333: | |
237 | return 333; | |
238 | /* these two are just a guess; one of them might be right */ | |
239 | case CLKCFG_FSB_1600: | |
240 | case CLKCFG_FSB_1600_ALT: | |
241 | return 400; | |
242 | default: | |
243 | return 133; | |
244 | } | |
245 | } | |
246 | ||
bf13e81b JN |
247 | static void |
248 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
249 | struct intel_dp *intel_dp, | |
250 | struct edp_power_seq *out); | |
251 | static void | |
252 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
253 | struct intel_dp *intel_dp, | |
254 | struct edp_power_seq *out); | |
255 | ||
256 | static enum pipe | |
257 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
258 | { | |
259 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
260 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
261 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
262 | struct drm_i915_private *dev_priv = dev->dev_private; | |
263 | enum port port = intel_dig_port->port; | |
264 | enum pipe pipe; | |
265 | ||
266 | /* modeset should have pipe */ | |
267 | if (crtc) | |
268 | return to_intel_crtc(crtc)->pipe; | |
269 | ||
270 | /* init time, try to find a pipe with this port selected */ | |
271 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { | |
272 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & | |
273 | PANEL_PORT_SELECT_MASK; | |
274 | if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) | |
275 | return pipe; | |
276 | if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) | |
277 | return pipe; | |
278 | } | |
279 | ||
280 | /* shrug */ | |
281 | return PIPE_A; | |
282 | } | |
283 | ||
284 | static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) | |
285 | { | |
286 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
287 | ||
288 | if (HAS_PCH_SPLIT(dev)) | |
289 | return PCH_PP_CONTROL; | |
290 | else | |
291 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); | |
292 | } | |
293 | ||
294 | static u32 _pp_stat_reg(struct intel_dp *intel_dp) | |
295 | { | |
296 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
297 | ||
298 | if (HAS_PCH_SPLIT(dev)) | |
299 | return PCH_PP_STATUS; | |
300 | else | |
301 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); | |
302 | } | |
303 | ||
4be73780 | 304 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
ebf33b18 | 305 | { |
30add22d | 306 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
ebf33b18 KP |
307 | struct drm_i915_private *dev_priv = dev->dev_private; |
308 | ||
bf13e81b | 309 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
310 | } |
311 | ||
4be73780 | 312 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
ebf33b18 | 313 | { |
30add22d | 314 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
ebf33b18 KP |
315 | struct drm_i915_private *dev_priv = dev->dev_private; |
316 | ||
bf13e81b | 317 | return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; |
ebf33b18 KP |
318 | } |
319 | ||
9b984dae KP |
320 | static void |
321 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
322 | { | |
30add22d | 323 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9b984dae | 324 | struct drm_i915_private *dev_priv = dev->dev_private; |
ebf33b18 | 325 | |
9b984dae KP |
326 | if (!is_edp(intel_dp)) |
327 | return; | |
453c5420 | 328 | |
4be73780 | 329 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
330 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
331 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
bf13e81b JN |
332 | I915_READ(_pp_stat_reg(intel_dp)), |
333 | I915_READ(_pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
334 | } |
335 | } | |
336 | ||
9ee32fea DV |
337 | static uint32_t |
338 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) | |
339 | { | |
340 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
341 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
342 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9ed35ab1 | 343 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
9ee32fea DV |
344 | uint32_t status; |
345 | bool done; | |
346 | ||
ef04f00d | 347 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
9ee32fea | 348 | if (has_aux_irq) |
b18ac466 | 349 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
3598706b | 350 | msecs_to_jiffies_timeout(10)); |
9ee32fea DV |
351 | else |
352 | done = wait_for_atomic(C, 10) == 0; | |
353 | if (!done) | |
354 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", | |
355 | has_aux_irq); | |
356 | #undef C | |
357 | ||
358 | return status; | |
359 | } | |
360 | ||
ec5b01dd | 361 | static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
a4fc5ed6 | 362 | { |
174edf1f PZ |
363 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
364 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
9ee32fea | 365 | |
ec5b01dd DL |
366 | /* |
367 | * The clock divider is based off the hrawclk, and would like to run at | |
368 | * 2MHz. So, take the hrawclk value and divide by 2 and use that | |
a4fc5ed6 | 369 | */ |
ec5b01dd DL |
370 | return index ? 0 : intel_hrawclk(dev) / 2; |
371 | } | |
372 | ||
373 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
374 | { | |
375 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
376 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
377 | ||
378 | if (index) | |
379 | return 0; | |
380 | ||
381 | if (intel_dig_port->port == PORT_A) { | |
382 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
b84a1cf8 | 383 | return 200; /* SNB & IVB eDP input clock at 400Mhz */ |
e3421a18 | 384 | else |
b84a1cf8 | 385 | return 225; /* eDP input clock at 450Mhz */ |
ec5b01dd DL |
386 | } else { |
387 | return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); | |
388 | } | |
389 | } | |
390 | ||
391 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
392 | { | |
393 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
394 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
395 | struct drm_i915_private *dev_priv = dev->dev_private; | |
396 | ||
397 | if (intel_dig_port->port == PORT_A) { | |
398 | if (index) | |
399 | return 0; | |
400 | return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); | |
2c55c336 JN |
401 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
402 | /* Workaround for non-ULT HSW */ | |
bc86625a CW |
403 | switch (index) { |
404 | case 0: return 63; | |
405 | case 1: return 72; | |
406 | default: return 0; | |
407 | } | |
ec5b01dd | 408 | } else { |
bc86625a | 409 | return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
2c55c336 | 410 | } |
b84a1cf8 RV |
411 | } |
412 | ||
ec5b01dd DL |
413 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
414 | { | |
415 | return index ? 0 : 100; | |
416 | } | |
417 | ||
5ed12a19 DL |
418 | static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, |
419 | bool has_aux_irq, | |
420 | int send_bytes, | |
421 | uint32_t aux_clock_divider) | |
422 | { | |
423 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
424 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
425 | uint32_t precharge, timeout; | |
426 | ||
427 | if (IS_GEN6(dev)) | |
428 | precharge = 3; | |
429 | else | |
430 | precharge = 5; | |
431 | ||
432 | if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) | |
433 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; | |
434 | else | |
435 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; | |
436 | ||
437 | return DP_AUX_CH_CTL_SEND_BUSY | | |
788d4433 | 438 | DP_AUX_CH_CTL_DONE | |
5ed12a19 | 439 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
788d4433 | 440 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
5ed12a19 | 441 | timeout | |
788d4433 | 442 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
5ed12a19 DL |
443 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
444 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
788d4433 | 445 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
5ed12a19 DL |
446 | } |
447 | ||
b84a1cf8 RV |
448 | static int |
449 | intel_dp_aux_ch(struct intel_dp *intel_dp, | |
450 | uint8_t *send, int send_bytes, | |
451 | uint8_t *recv, int recv_size) | |
452 | { | |
453 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
454 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
456 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; | |
457 | uint32_t ch_data = ch_ctl + 4; | |
bc86625a | 458 | uint32_t aux_clock_divider; |
b84a1cf8 RV |
459 | int i, ret, recv_bytes; |
460 | uint32_t status; | |
5ed12a19 | 461 | int try, clock = 0; |
4e6b788c | 462 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
b84a1cf8 RV |
463 | |
464 | /* dp aux is extremely sensitive to irq latency, hence request the | |
465 | * lowest possible wakeup latency and so prevent the cpu from going into | |
466 | * deep sleep states. | |
467 | */ | |
468 | pm_qos_update_request(&dev_priv->pm_qos, 0); | |
469 | ||
470 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 471 | |
c67a470b PZ |
472 | intel_aux_display_runtime_get(dev_priv); |
473 | ||
11bee43e JB |
474 | /* Try to wait for any previous AUX channel activity */ |
475 | for (try = 0; try < 3; try++) { | |
ef04f00d | 476 | status = I915_READ_NOTRACE(ch_ctl); |
11bee43e JB |
477 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
478 | break; | |
479 | msleep(1); | |
480 | } | |
481 | ||
482 | if (try == 3) { | |
483 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
484 | I915_READ(ch_ctl)); | |
9ee32fea DV |
485 | ret = -EBUSY; |
486 | goto out; | |
4f7f7b7e CW |
487 | } |
488 | ||
46a5ae9f PZ |
489 | /* Only 5 data registers! */ |
490 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { | |
491 | ret = -E2BIG; | |
492 | goto out; | |
493 | } | |
494 | ||
ec5b01dd | 495 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
153b1100 DL |
496 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
497 | has_aux_irq, | |
498 | send_bytes, | |
499 | aux_clock_divider); | |
5ed12a19 | 500 | |
bc86625a CW |
501 | /* Must try at least 3 times according to DP spec */ |
502 | for (try = 0; try < 5; try++) { | |
503 | /* Load the send data into the aux channel data registers */ | |
504 | for (i = 0; i < send_bytes; i += 4) | |
505 | I915_WRITE(ch_data + i, | |
506 | pack_aux(send + i, send_bytes - i)); | |
507 | ||
508 | /* Send the command and wait for it to complete */ | |
5ed12a19 | 509 | I915_WRITE(ch_ctl, send_ctl); |
bc86625a CW |
510 | |
511 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); | |
512 | ||
513 | /* Clear done status and any errors */ | |
514 | I915_WRITE(ch_ctl, | |
515 | status | | |
516 | DP_AUX_CH_CTL_DONE | | |
517 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
518 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
519 | ||
520 | if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
521 | DP_AUX_CH_CTL_RECEIVE_ERROR)) | |
522 | continue; | |
523 | if (status & DP_AUX_CH_CTL_DONE) | |
524 | break; | |
525 | } | |
4f7f7b7e | 526 | if (status & DP_AUX_CH_CTL_DONE) |
a4fc5ed6 KP |
527 | break; |
528 | } | |
529 | ||
a4fc5ed6 | 530 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 531 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
9ee32fea DV |
532 | ret = -EBUSY; |
533 | goto out; | |
a4fc5ed6 KP |
534 | } |
535 | ||
536 | /* Check for timeout or receive error. | |
537 | * Timeouts occur when the sink is not connected | |
538 | */ | |
a5b3da54 | 539 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 540 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
9ee32fea DV |
541 | ret = -EIO; |
542 | goto out; | |
a5b3da54 | 543 | } |
1ae8c0a5 KP |
544 | |
545 | /* Timeouts occur when the device isn't connected, so they're | |
546 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 547 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 548 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
9ee32fea DV |
549 | ret = -ETIMEDOUT; |
550 | goto out; | |
a4fc5ed6 KP |
551 | } |
552 | ||
553 | /* Unload any bytes sent back from the other side */ | |
554 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
555 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
556 | if (recv_bytes > recv_size) |
557 | recv_bytes = recv_size; | |
0206e353 | 558 | |
4f7f7b7e CW |
559 | for (i = 0; i < recv_bytes; i += 4) |
560 | unpack_aux(I915_READ(ch_data + i), | |
561 | recv + i, recv_bytes - i); | |
a4fc5ed6 | 562 | |
9ee32fea DV |
563 | ret = recv_bytes; |
564 | out: | |
565 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); | |
c67a470b | 566 | intel_aux_display_runtime_put(dev_priv); |
9ee32fea DV |
567 | |
568 | return ret; | |
a4fc5ed6 KP |
569 | } |
570 | ||
571 | /* Write data to the aux channel in native mode */ | |
572 | static int | |
ea5b213a | 573 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
574 | uint16_t address, uint8_t *send, int send_bytes) |
575 | { | |
576 | int ret; | |
577 | uint8_t msg[20]; | |
578 | int msg_bytes; | |
579 | uint8_t ack; | |
f51a44b9 | 580 | int retry; |
a4fc5ed6 | 581 | |
46a5ae9f PZ |
582 | if (WARN_ON(send_bytes > 16)) |
583 | return -E2BIG; | |
584 | ||
9b984dae | 585 | intel_dp_check_edp(intel_dp); |
6b27f7f0 | 586 | msg[0] = DP_AUX_NATIVE_WRITE << 4; |
a4fc5ed6 | 587 | msg[1] = address >> 8; |
eebc863e | 588 | msg[2] = address & 0xff; |
a4fc5ed6 KP |
589 | msg[3] = send_bytes - 1; |
590 | memcpy(&msg[4], send, send_bytes); | |
591 | msg_bytes = send_bytes + 4; | |
f51a44b9 | 592 | for (retry = 0; retry < 7; retry++) { |
ea5b213a | 593 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
a4fc5ed6 KP |
594 | if (ret < 0) |
595 | return ret; | |
6b27f7f0 TR |
596 | ack >>= 4; |
597 | if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) | |
f51a44b9 | 598 | return send_bytes; |
6b27f7f0 | 599 | else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) |
04eada25 | 600 | usleep_range(400, 500); |
a4fc5ed6 | 601 | else |
a5b3da54 | 602 | return -EIO; |
a4fc5ed6 | 603 | } |
f51a44b9 JN |
604 | |
605 | DRM_ERROR("too many retries, giving up\n"); | |
606 | return -EIO; | |
a4fc5ed6 KP |
607 | } |
608 | ||
609 | /* Write a single byte to the aux channel in native mode */ | |
610 | static int | |
ea5b213a | 611 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
612 | uint16_t address, uint8_t byte) |
613 | { | |
ea5b213a | 614 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
a4fc5ed6 KP |
615 | } |
616 | ||
617 | /* read bytes from a native aux channel */ | |
618 | static int | |
ea5b213a | 619 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
620 | uint16_t address, uint8_t *recv, int recv_bytes) |
621 | { | |
622 | uint8_t msg[4]; | |
623 | int msg_bytes; | |
624 | uint8_t reply[20]; | |
625 | int reply_bytes; | |
626 | uint8_t ack; | |
627 | int ret; | |
f51a44b9 | 628 | int retry; |
a4fc5ed6 | 629 | |
46a5ae9f PZ |
630 | if (WARN_ON(recv_bytes > 19)) |
631 | return -E2BIG; | |
632 | ||
9b984dae | 633 | intel_dp_check_edp(intel_dp); |
6b27f7f0 | 634 | msg[0] = DP_AUX_NATIVE_READ << 4; |
a4fc5ed6 KP |
635 | msg[1] = address >> 8; |
636 | msg[2] = address & 0xff; | |
637 | msg[3] = recv_bytes - 1; | |
638 | ||
639 | msg_bytes = 4; | |
640 | reply_bytes = recv_bytes + 1; | |
641 | ||
f51a44b9 | 642 | for (retry = 0; retry < 7; retry++) { |
ea5b213a | 643 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
a4fc5ed6 | 644 | reply, reply_bytes); |
a5b3da54 KP |
645 | if (ret == 0) |
646 | return -EPROTO; | |
647 | if (ret < 0) | |
a4fc5ed6 | 648 | return ret; |
6b27f7f0 TR |
649 | ack = reply[0] >> 4; |
650 | if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) { | |
a4fc5ed6 KP |
651 | memcpy(recv, reply + 1, ret - 1); |
652 | return ret - 1; | |
653 | } | |
6b27f7f0 | 654 | else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) |
04eada25 | 655 | usleep_range(400, 500); |
a4fc5ed6 | 656 | else |
a5b3da54 | 657 | return -EIO; |
a4fc5ed6 | 658 | } |
f51a44b9 JN |
659 | |
660 | DRM_ERROR("too many retries, giving up\n"); | |
661 | return -EIO; | |
a4fc5ed6 KP |
662 | } |
663 | ||
664 | static int | |
ab2c0672 DA |
665 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
666 | uint8_t write_byte, uint8_t *read_byte) | |
a4fc5ed6 | 667 | { |
ab2c0672 | 668 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
ea5b213a CW |
669 | struct intel_dp *intel_dp = container_of(adapter, |
670 | struct intel_dp, | |
671 | adapter); | |
ab2c0672 DA |
672 | uint16_t address = algo_data->address; |
673 | uint8_t msg[5]; | |
674 | uint8_t reply[2]; | |
8316f337 | 675 | unsigned retry; |
ab2c0672 DA |
676 | int msg_bytes; |
677 | int reply_bytes; | |
678 | int ret; | |
679 | ||
4be73780 | 680 | edp_panel_vdd_on(intel_dp); |
9b984dae | 681 | intel_dp_check_edp(intel_dp); |
ab2c0672 DA |
682 | /* Set up the command byte */ |
683 | if (mode & MODE_I2C_READ) | |
6b27f7f0 | 684 | msg[0] = DP_AUX_I2C_READ << 4; |
ab2c0672 | 685 | else |
6b27f7f0 | 686 | msg[0] = DP_AUX_I2C_WRITE << 4; |
ab2c0672 DA |
687 | |
688 | if (!(mode & MODE_I2C_STOP)) | |
6b27f7f0 | 689 | msg[0] |= DP_AUX_I2C_MOT << 4; |
a4fc5ed6 | 690 | |
ab2c0672 DA |
691 | msg[1] = address >> 8; |
692 | msg[2] = address; | |
693 | ||
694 | switch (mode) { | |
695 | case MODE_I2C_WRITE: | |
696 | msg[3] = 0; | |
697 | msg[4] = write_byte; | |
698 | msg_bytes = 5; | |
699 | reply_bytes = 1; | |
700 | break; | |
701 | case MODE_I2C_READ: | |
702 | msg[3] = 0; | |
703 | msg_bytes = 4; | |
704 | reply_bytes = 2; | |
705 | break; | |
706 | default: | |
707 | msg_bytes = 3; | |
708 | reply_bytes = 1; | |
709 | break; | |
710 | } | |
711 | ||
58c67ce9 JN |
712 | /* |
713 | * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is | |
714 | * required to retry at least seven times upon receiving AUX_DEFER | |
715 | * before giving up the AUX transaction. | |
716 | */ | |
717 | for (retry = 0; retry < 7; retry++) { | |
8316f337 DF |
718 | ret = intel_dp_aux_ch(intel_dp, |
719 | msg, msg_bytes, | |
720 | reply, reply_bytes); | |
ab2c0672 | 721 | if (ret < 0) { |
3ff99164 | 722 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
8a5e6aeb | 723 | goto out; |
ab2c0672 | 724 | } |
8316f337 | 725 | |
6b27f7f0 TR |
726 | switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) { |
727 | case DP_AUX_NATIVE_REPLY_ACK: | |
8316f337 DF |
728 | /* I2C-over-AUX Reply field is only valid |
729 | * when paired with AUX ACK. | |
730 | */ | |
731 | break; | |
6b27f7f0 | 732 | case DP_AUX_NATIVE_REPLY_NACK: |
8316f337 | 733 | DRM_DEBUG_KMS("aux_ch native nack\n"); |
8a5e6aeb PZ |
734 | ret = -EREMOTEIO; |
735 | goto out; | |
6b27f7f0 | 736 | case DP_AUX_NATIVE_REPLY_DEFER: |
8d16f258 JN |
737 | /* |
738 | * For now, just give more slack to branch devices. We | |
739 | * could check the DPCD for I2C bit rate capabilities, | |
740 | * and if available, adjust the interval. We could also | |
741 | * be more careful with DP-to-Legacy adapters where a | |
742 | * long legacy cable may force very low I2C bit rates. | |
743 | */ | |
744 | if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
745 | DP_DWN_STRM_PORT_PRESENT) | |
746 | usleep_range(500, 600); | |
747 | else | |
748 | usleep_range(300, 400); | |
8316f337 DF |
749 | continue; |
750 | default: | |
751 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", | |
752 | reply[0]); | |
8a5e6aeb PZ |
753 | ret = -EREMOTEIO; |
754 | goto out; | |
8316f337 DF |
755 | } |
756 | ||
6b27f7f0 TR |
757 | switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) { |
758 | case DP_AUX_I2C_REPLY_ACK: | |
ab2c0672 DA |
759 | if (mode == MODE_I2C_READ) { |
760 | *read_byte = reply[1]; | |
761 | } | |
8a5e6aeb PZ |
762 | ret = reply_bytes - 1; |
763 | goto out; | |
6b27f7f0 | 764 | case DP_AUX_I2C_REPLY_NACK: |
8316f337 | 765 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
8a5e6aeb PZ |
766 | ret = -EREMOTEIO; |
767 | goto out; | |
6b27f7f0 | 768 | case DP_AUX_I2C_REPLY_DEFER: |
8316f337 | 769 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
ab2c0672 DA |
770 | udelay(100); |
771 | break; | |
772 | default: | |
8316f337 | 773 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
8a5e6aeb PZ |
774 | ret = -EREMOTEIO; |
775 | goto out; | |
ab2c0672 DA |
776 | } |
777 | } | |
8316f337 DF |
778 | |
779 | DRM_ERROR("too many retries, giving up\n"); | |
8a5e6aeb PZ |
780 | ret = -EREMOTEIO; |
781 | ||
782 | out: | |
4be73780 | 783 | edp_panel_vdd_off(intel_dp, false); |
8a5e6aeb | 784 | return ret; |
a4fc5ed6 KP |
785 | } |
786 | ||
80f65de3 ID |
787 | static void |
788 | intel_dp_connector_unregister(struct intel_connector *intel_connector) | |
789 | { | |
790 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); | |
791 | ||
792 | sysfs_remove_link(&intel_connector->base.kdev->kobj, | |
793 | intel_dp->adapter.dev.kobj.name); | |
794 | intel_connector_unregister(intel_connector); | |
795 | } | |
796 | ||
a4fc5ed6 | 797 | static int |
ea5b213a | 798 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
55f78c43 | 799 | struct intel_connector *intel_connector, const char *name) |
a4fc5ed6 | 800 | { |
0b5c541b KP |
801 | int ret; |
802 | ||
d54e9d28 | 803 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
ea5b213a CW |
804 | intel_dp->algo.running = false; |
805 | intel_dp->algo.address = 0; | |
806 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | |
807 | ||
0206e353 | 808 | memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); |
ea5b213a CW |
809 | intel_dp->adapter.owner = THIS_MODULE; |
810 | intel_dp->adapter.class = I2C_CLASS_DDC; | |
0206e353 | 811 | strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); |
ea5b213a CW |
812 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; |
813 | intel_dp->adapter.algo_data = &intel_dp->algo; | |
80f65de3 | 814 | intel_dp->adapter.dev.parent = intel_connector->base.dev->dev; |
ea5b213a | 815 | |
0b5c541b | 816 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); |
80f65de3 ID |
817 | if (ret < 0) |
818 | return ret; | |
819 | ||
820 | ret = sysfs_create_link(&intel_connector->base.kdev->kobj, | |
821 | &intel_dp->adapter.dev.kobj, | |
822 | intel_dp->adapter.dev.kobj.name); | |
823 | ||
824 | if (ret < 0) | |
825 | i2c_del_adapter(&intel_dp->adapter); | |
826 | ||
0b5c541b | 827 | return ret; |
a4fc5ed6 KP |
828 | } |
829 | ||
c6bb3538 DV |
830 | static void |
831 | intel_dp_set_clock(struct intel_encoder *encoder, | |
832 | struct intel_crtc_config *pipe_config, int link_bw) | |
833 | { | |
834 | struct drm_device *dev = encoder->base.dev; | |
9dd4ffdf CML |
835 | const struct dp_link_dpll *divisor = NULL; |
836 | int i, count = 0; | |
c6bb3538 DV |
837 | |
838 | if (IS_G4X(dev)) { | |
9dd4ffdf CML |
839 | divisor = gen4_dpll; |
840 | count = ARRAY_SIZE(gen4_dpll); | |
c6bb3538 DV |
841 | } else if (IS_HASWELL(dev)) { |
842 | /* Haswell has special-purpose DP DDI clocks. */ | |
843 | } else if (HAS_PCH_SPLIT(dev)) { | |
9dd4ffdf CML |
844 | divisor = pch_dpll; |
845 | count = ARRAY_SIZE(pch_dpll); | |
c6bb3538 | 846 | } else if (IS_VALLEYVIEW(dev)) { |
65ce4bf5 CML |
847 | divisor = vlv_dpll; |
848 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 849 | } |
9dd4ffdf CML |
850 | |
851 | if (divisor && count) { | |
852 | for (i = 0; i < count; i++) { | |
853 | if (link_bw == divisor[i].link_bw) { | |
854 | pipe_config->dpll = divisor[i].dpll; | |
855 | pipe_config->clock_set = true; | |
856 | break; | |
857 | } | |
858 | } | |
c6bb3538 DV |
859 | } |
860 | } | |
861 | ||
00c09d70 | 862 | bool |
5bfe2ac0 DV |
863 | intel_dp_compute_config(struct intel_encoder *encoder, |
864 | struct intel_crtc_config *pipe_config) | |
a4fc5ed6 | 865 | { |
5bfe2ac0 | 866 | struct drm_device *dev = encoder->base.dev; |
36008365 | 867 | struct drm_i915_private *dev_priv = dev->dev_private; |
5bfe2ac0 | 868 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
5bfe2ac0 | 869 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 870 | enum port port = dp_to_dig_port(intel_dp)->port; |
2dd24552 | 871 | struct intel_crtc *intel_crtc = encoder->new_crtc; |
dd06f90e | 872 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
a4fc5ed6 | 873 | int lane_count, clock; |
397fe157 | 874 | int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); |
06ea66b6 TP |
875 | /* Conveniently, the link BW constants become indices with a shift...*/ |
876 | int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; | |
083f9560 | 877 | int bpp, mode_rate; |
06ea66b6 | 878 | static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; |
ff9a6750 | 879 | int link_avail, link_clock; |
a4fc5ed6 | 880 | |
bc7d38a4 | 881 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
5bfe2ac0 DV |
882 | pipe_config->has_pch_encoder = true; |
883 | ||
03afc4a2 | 884 | pipe_config->has_dp_encoder = true; |
a4fc5ed6 | 885 | |
dd06f90e JN |
886 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
887 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, | |
888 | adjusted_mode); | |
2dd24552 JB |
889 | if (!HAS_PCH_SPLIT(dev)) |
890 | intel_gmch_panel_fitting(intel_crtc, pipe_config, | |
891 | intel_connector->panel.fitting_mode); | |
892 | else | |
b074cec8 JB |
893 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
894 | intel_connector->panel.fitting_mode); | |
0d3a1bee ZY |
895 | } |
896 | ||
cb1793ce | 897 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
0af78a2b DV |
898 | return false; |
899 | ||
083f9560 DV |
900 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
901 | "max bw %02x pixel clock %iKHz\n", | |
241bfc38 DL |
902 | max_lane_count, bws[max_clock], |
903 | adjusted_mode->crtc_clock); | |
083f9560 | 904 | |
36008365 DV |
905 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
906 | * bpc in between. */ | |
3e7ca985 | 907 | bpp = pipe_config->pipe_bpp; |
6da7f10d JN |
908 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
909 | dev_priv->vbt.edp_bpp < bpp) { | |
7984211e ID |
910 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
911 | dev_priv->vbt.edp_bpp); | |
6da7f10d | 912 | bpp = dev_priv->vbt.edp_bpp; |
7984211e | 913 | } |
657445fe | 914 | |
36008365 | 915 | for (; bpp >= 6*3; bpp -= 2*3) { |
241bfc38 DL |
916 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
917 | bpp); | |
36008365 | 918 | |
38aecea0 DV |
919 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
920 | for (clock = 0; clock <= max_clock; clock++) { | |
36008365 DV |
921 | link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); |
922 | link_avail = intel_dp_max_data_rate(link_clock, | |
923 | lane_count); | |
924 | ||
925 | if (mode_rate <= link_avail) { | |
926 | goto found; | |
927 | } | |
928 | } | |
929 | } | |
930 | } | |
c4867936 | 931 | |
36008365 | 932 | return false; |
3685a8f3 | 933 | |
36008365 | 934 | found: |
55bc60db VS |
935 | if (intel_dp->color_range_auto) { |
936 | /* | |
937 | * See: | |
938 | * CEA-861-E - 5.1 Default Encoding Parameters | |
939 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
940 | */ | |
18316c8c | 941 | if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) |
55bc60db VS |
942 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
943 | else | |
944 | intel_dp->color_range = 0; | |
945 | } | |
946 | ||
3685a8f3 | 947 | if (intel_dp->color_range) |
50f3b016 | 948 | pipe_config->limited_color_range = true; |
a4fc5ed6 | 949 | |
36008365 DV |
950 | intel_dp->link_bw = bws[clock]; |
951 | intel_dp->lane_count = lane_count; | |
657445fe | 952 | pipe_config->pipe_bpp = bpp; |
ff9a6750 | 953 | pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); |
a4fc5ed6 | 954 | |
36008365 DV |
955 | DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", |
956 | intel_dp->link_bw, intel_dp->lane_count, | |
ff9a6750 | 957 | pipe_config->port_clock, bpp); |
36008365 DV |
958 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
959 | mode_rate, link_avail); | |
a4fc5ed6 | 960 | |
03afc4a2 | 961 | intel_link_compute_m_n(bpp, lane_count, |
241bfc38 DL |
962 | adjusted_mode->crtc_clock, |
963 | pipe_config->port_clock, | |
03afc4a2 | 964 | &pipe_config->dp_m_n); |
9d1a455b | 965 | |
c6bb3538 DV |
966 | intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); |
967 | ||
03afc4a2 | 968 | return true; |
a4fc5ed6 KP |
969 | } |
970 | ||
7c62a164 | 971 | static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) |
ea9b6006 | 972 | { |
7c62a164 DV |
973 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
974 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); | |
975 | struct drm_device *dev = crtc->base.dev; | |
ea9b6006 DV |
976 | struct drm_i915_private *dev_priv = dev->dev_private; |
977 | u32 dpa_ctl; | |
978 | ||
ff9a6750 | 979 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); |
ea9b6006 DV |
980 | dpa_ctl = I915_READ(DP_A); |
981 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
982 | ||
ff9a6750 | 983 | if (crtc->config.port_clock == 162000) { |
1ce17038 DV |
984 | /* For a long time we've carried around a ILK-DevA w/a for the |
985 | * 160MHz clock. If we're really unlucky, it's still required. | |
986 | */ | |
987 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); | |
ea9b6006 | 988 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
7c62a164 | 989 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
ea9b6006 DV |
990 | } else { |
991 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
7c62a164 | 992 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
ea9b6006 | 993 | } |
1ce17038 | 994 | |
ea9b6006 DV |
995 | I915_WRITE(DP_A, dpa_ctl); |
996 | ||
997 | POSTING_READ(DP_A); | |
998 | udelay(500); | |
999 | } | |
1000 | ||
b934223d | 1001 | static void intel_dp_mode_set(struct intel_encoder *encoder) |
a4fc5ed6 | 1002 | { |
b934223d | 1003 | struct drm_device *dev = encoder->base.dev; |
417e822d | 1004 | struct drm_i915_private *dev_priv = dev->dev_private; |
b934223d | 1005 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1006 | enum port port = dp_to_dig_port(intel_dp)->port; |
b934223d DV |
1007 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
1008 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
a4fc5ed6 | 1009 | |
417e822d | 1010 | /* |
1a2eb460 | 1011 | * There are four kinds of DP registers: |
417e822d KP |
1012 | * |
1013 | * IBX PCH | |
1a2eb460 KP |
1014 | * SNB CPU |
1015 | * IVB CPU | |
417e822d KP |
1016 | * CPT PCH |
1017 | * | |
1018 | * IBX PCH and CPU are the same for almost everything, | |
1019 | * except that the CPU DP PLL is configured in this | |
1020 | * register | |
1021 | * | |
1022 | * CPT PCH is quite different, having many bits moved | |
1023 | * to the TRANS_DP_CTL register instead. That | |
1024 | * configuration happens (oddly) in ironlake_pch_enable | |
1025 | */ | |
9c9e7927 | 1026 | |
417e822d KP |
1027 | /* Preserve the BIOS-computed detected bit. This is |
1028 | * supposed to be read-only. | |
1029 | */ | |
1030 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
a4fc5ed6 | 1031 | |
417e822d | 1032 | /* Handle DP bits in common between all three register formats */ |
417e822d | 1033 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
17aa6be9 | 1034 | intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); |
a4fc5ed6 | 1035 | |
e0dac65e WF |
1036 | if (intel_dp->has_audio) { |
1037 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", | |
7c62a164 | 1038 | pipe_name(crtc->pipe)); |
ea5b213a | 1039 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
b934223d | 1040 | intel_write_eld(&encoder->base, adjusted_mode); |
e0dac65e | 1041 | } |
247d89f6 | 1042 | |
417e822d | 1043 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 1044 | |
bc7d38a4 | 1045 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
1a2eb460 KP |
1046 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1047 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1048 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1049 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1050 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
1051 | ||
6aba5b6c | 1052 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
1053 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1054 | ||
7c62a164 | 1055 | intel_dp->DP |= crtc->pipe << 29; |
bc7d38a4 | 1056 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
b2634017 | 1057 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) |
3685a8f3 | 1058 | intel_dp->DP |= intel_dp->color_range; |
417e822d KP |
1059 | |
1060 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
1061 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1062 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1063 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1064 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
1065 | ||
6aba5b6c | 1066 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
1067 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1068 | ||
7c62a164 | 1069 | if (crtc->pipe == 1) |
417e822d | 1070 | intel_dp->DP |= DP_PIPEB_SELECT; |
417e822d KP |
1071 | } else { |
1072 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
32f9d658 | 1073 | } |
ea9b6006 | 1074 | |
bc7d38a4 | 1075 | if (port == PORT_A && !IS_VALLEYVIEW(dev)) |
7c62a164 | 1076 | ironlake_set_pll_cpu_edp(intel_dp); |
a4fc5ed6 KP |
1077 | } |
1078 | ||
ffd6749d PZ |
1079 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1080 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
99ea7127 | 1081 | |
1a5ef5b7 PZ |
1082 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1083 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) | |
99ea7127 | 1084 | |
ffd6749d PZ |
1085 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1086 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
99ea7127 | 1087 | |
4be73780 | 1088 | static void wait_panel_status(struct intel_dp *intel_dp, |
99ea7127 KP |
1089 | u32 mask, |
1090 | u32 value) | |
bd943159 | 1091 | { |
30add22d | 1092 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
99ea7127 | 1093 | struct drm_i915_private *dev_priv = dev->dev_private; |
453c5420 JB |
1094 | u32 pp_stat_reg, pp_ctrl_reg; |
1095 | ||
bf13e81b JN |
1096 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1097 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 1098 | |
99ea7127 | 1099 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
453c5420 JB |
1100 | mask, value, |
1101 | I915_READ(pp_stat_reg), | |
1102 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1103 | |
453c5420 | 1104 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
99ea7127 | 1105 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
453c5420 JB |
1106 | I915_READ(pp_stat_reg), |
1107 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1108 | } |
54c136d4 CW |
1109 | |
1110 | DRM_DEBUG_KMS("Wait complete\n"); | |
99ea7127 | 1111 | } |
32ce697c | 1112 | |
4be73780 | 1113 | static void wait_panel_on(struct intel_dp *intel_dp) |
99ea7127 KP |
1114 | { |
1115 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
4be73780 | 1116 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
bd943159 KP |
1117 | } |
1118 | ||
4be73780 | 1119 | static void wait_panel_off(struct intel_dp *intel_dp) |
99ea7127 KP |
1120 | { |
1121 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
4be73780 | 1122 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
99ea7127 KP |
1123 | } |
1124 | ||
4be73780 | 1125 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
99ea7127 KP |
1126 | { |
1127 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); | |
dce56b3c PZ |
1128 | |
1129 | /* When we disable the VDD override bit last we have to do the manual | |
1130 | * wait. */ | |
1131 | wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, | |
1132 | intel_dp->panel_power_cycle_delay); | |
1133 | ||
4be73780 | 1134 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
99ea7127 KP |
1135 | } |
1136 | ||
4be73780 | 1137 | static void wait_backlight_on(struct intel_dp *intel_dp) |
dce56b3c PZ |
1138 | { |
1139 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, | |
1140 | intel_dp->backlight_on_delay); | |
1141 | } | |
1142 | ||
4be73780 | 1143 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
dce56b3c PZ |
1144 | { |
1145 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, | |
1146 | intel_dp->backlight_off_delay); | |
1147 | } | |
99ea7127 | 1148 | |
832dd3c1 KP |
1149 | /* Read the current pp_control value, unlocking the register if it |
1150 | * is locked | |
1151 | */ | |
1152 | ||
453c5420 | 1153 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 1154 | { |
453c5420 JB |
1155 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1156 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1157 | u32 control; | |
832dd3c1 | 1158 | |
bf13e81b | 1159 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
832dd3c1 KP |
1160 | control &= ~PANEL_UNLOCK_MASK; |
1161 | control |= PANEL_UNLOCK_REGS; | |
1162 | return control; | |
bd943159 KP |
1163 | } |
1164 | ||
4be73780 | 1165 | static void edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 1166 | { |
30add22d | 1167 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5d613501 JB |
1168 | struct drm_i915_private *dev_priv = dev->dev_private; |
1169 | u32 pp; | |
453c5420 | 1170 | u32 pp_stat_reg, pp_ctrl_reg; |
5d613501 | 1171 | |
97af61f5 KP |
1172 | if (!is_edp(intel_dp)) |
1173 | return; | |
5d613501 | 1174 | |
bd943159 KP |
1175 | WARN(intel_dp->want_panel_vdd, |
1176 | "eDP VDD already requested on\n"); | |
1177 | ||
1178 | intel_dp->want_panel_vdd = true; | |
99ea7127 | 1179 | |
4be73780 | 1180 | if (edp_have_panel_vdd(intel_dp)) |
bd943159 | 1181 | return; |
b0665d57 | 1182 | |
e9cb81a2 PZ |
1183 | intel_runtime_pm_get(dev_priv); |
1184 | ||
b0665d57 | 1185 | DRM_DEBUG_KMS("Turning eDP VDD on\n"); |
bd943159 | 1186 | |
4be73780 DV |
1187 | if (!edp_have_panel_power(intel_dp)) |
1188 | wait_panel_power_cycle(intel_dp); | |
99ea7127 | 1189 | |
453c5420 | 1190 | pp = ironlake_get_pp_control(intel_dp); |
5d613501 | 1191 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 1192 | |
bf13e81b JN |
1193 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1194 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 JB |
1195 | |
1196 | I915_WRITE(pp_ctrl_reg, pp); | |
1197 | POSTING_READ(pp_ctrl_reg); | |
1198 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1199 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
ebf33b18 KP |
1200 | /* |
1201 | * If the panel wasn't on, delay before accessing aux channel | |
1202 | */ | |
4be73780 | 1203 | if (!edp_have_panel_power(intel_dp)) { |
bd943159 | 1204 | DRM_DEBUG_KMS("eDP was not running\n"); |
f01eca2e | 1205 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 1206 | } |
5d613501 JB |
1207 | } |
1208 | ||
4be73780 | 1209 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 1210 | { |
30add22d | 1211 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5d613501 JB |
1212 | struct drm_i915_private *dev_priv = dev->dev_private; |
1213 | u32 pp; | |
453c5420 | 1214 | u32 pp_stat_reg, pp_ctrl_reg; |
5d613501 | 1215 | |
a0e99e68 DV |
1216 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); |
1217 | ||
4be73780 | 1218 | if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) { |
b0665d57 PZ |
1219 | DRM_DEBUG_KMS("Turning eDP VDD off\n"); |
1220 | ||
453c5420 | 1221 | pp = ironlake_get_pp_control(intel_dp); |
bd943159 | 1222 | pp &= ~EDP_FORCE_VDD; |
bd943159 | 1223 | |
9f08ef59 PZ |
1224 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1225 | pp_stat_reg = _pp_stat_reg(intel_dp); | |
453c5420 JB |
1226 | |
1227 | I915_WRITE(pp_ctrl_reg, pp); | |
1228 | POSTING_READ(pp_ctrl_reg); | |
99ea7127 | 1229 | |
453c5420 JB |
1230 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1231 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1232 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
90791a5c PZ |
1233 | |
1234 | if ((pp & POWER_TARGET_ON) == 0) | |
dce56b3c | 1235 | intel_dp->last_power_cycle = jiffies; |
e9cb81a2 PZ |
1236 | |
1237 | intel_runtime_pm_put(dev_priv); | |
bd943159 KP |
1238 | } |
1239 | } | |
5d613501 | 1240 | |
4be73780 | 1241 | static void edp_panel_vdd_work(struct work_struct *__work) |
bd943159 KP |
1242 | { |
1243 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
1244 | struct intel_dp, panel_vdd_work); | |
30add22d | 1245 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bd943159 | 1246 | |
627f7675 | 1247 | mutex_lock(&dev->mode_config.mutex); |
4be73780 | 1248 | edp_panel_vdd_off_sync(intel_dp); |
627f7675 | 1249 | mutex_unlock(&dev->mode_config.mutex); |
bd943159 KP |
1250 | } |
1251 | ||
4be73780 | 1252 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 1253 | { |
97af61f5 KP |
1254 | if (!is_edp(intel_dp)) |
1255 | return; | |
5d613501 | 1256 | |
bd943159 | 1257 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); |
f2e8b18a | 1258 | |
bd943159 KP |
1259 | intel_dp->want_panel_vdd = false; |
1260 | ||
1261 | if (sync) { | |
4be73780 | 1262 | edp_panel_vdd_off_sync(intel_dp); |
bd943159 KP |
1263 | } else { |
1264 | /* | |
1265 | * Queue the timer to fire a long | |
1266 | * time from now (relative to the power down delay) | |
1267 | * to keep the panel power up across a sequence of operations | |
1268 | */ | |
1269 | schedule_delayed_work(&intel_dp->panel_vdd_work, | |
1270 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); | |
1271 | } | |
5d613501 JB |
1272 | } |
1273 | ||
4be73780 | 1274 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 1275 | { |
30add22d | 1276 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9934c132 | 1277 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1278 | u32 pp; |
453c5420 | 1279 | u32 pp_ctrl_reg; |
9934c132 | 1280 | |
97af61f5 | 1281 | if (!is_edp(intel_dp)) |
bd943159 | 1282 | return; |
99ea7127 KP |
1283 | |
1284 | DRM_DEBUG_KMS("Turn eDP power on\n"); | |
1285 | ||
4be73780 | 1286 | if (edp_have_panel_power(intel_dp)) { |
99ea7127 | 1287 | DRM_DEBUG_KMS("eDP power already on\n"); |
7d639f35 | 1288 | return; |
99ea7127 | 1289 | } |
9934c132 | 1290 | |
4be73780 | 1291 | wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 1292 | |
bf13e81b | 1293 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 1294 | pp = ironlake_get_pp_control(intel_dp); |
05ce1a49 KP |
1295 | if (IS_GEN5(dev)) { |
1296 | /* ILK workaround: disable reset around power sequence */ | |
1297 | pp &= ~PANEL_POWER_RESET; | |
bf13e81b JN |
1298 | I915_WRITE(pp_ctrl_reg, pp); |
1299 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 1300 | } |
37c6c9b0 | 1301 | |
1c0ae80a | 1302 | pp |= POWER_TARGET_ON; |
99ea7127 KP |
1303 | if (!IS_GEN5(dev)) |
1304 | pp |= PANEL_POWER_RESET; | |
1305 | ||
453c5420 JB |
1306 | I915_WRITE(pp_ctrl_reg, pp); |
1307 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 1308 | |
4be73780 | 1309 | wait_panel_on(intel_dp); |
dce56b3c | 1310 | intel_dp->last_power_on = jiffies; |
9934c132 | 1311 | |
05ce1a49 KP |
1312 | if (IS_GEN5(dev)) { |
1313 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ | |
bf13e81b JN |
1314 | I915_WRITE(pp_ctrl_reg, pp); |
1315 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 1316 | } |
9934c132 JB |
1317 | } |
1318 | ||
4be73780 | 1319 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
9934c132 | 1320 | { |
30add22d | 1321 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9934c132 | 1322 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1323 | u32 pp; |
453c5420 | 1324 | u32 pp_ctrl_reg; |
9934c132 | 1325 | |
97af61f5 KP |
1326 | if (!is_edp(intel_dp)) |
1327 | return; | |
37c6c9b0 | 1328 | |
99ea7127 | 1329 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
37c6c9b0 | 1330 | |
4be73780 | 1331 | edp_wait_backlight_off(intel_dp); |
dce56b3c | 1332 | |
453c5420 | 1333 | pp = ironlake_get_pp_control(intel_dp); |
35a38556 DV |
1334 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
1335 | * panels get very unhappy and cease to work. */ | |
b3064154 PJ |
1336 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
1337 | EDP_BLC_ENABLE); | |
453c5420 | 1338 | |
bf13e81b | 1339 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
1340 | |
1341 | I915_WRITE(pp_ctrl_reg, pp); | |
1342 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 1343 | |
dce56b3c | 1344 | intel_dp->last_power_cycle = jiffies; |
4be73780 | 1345 | wait_panel_off(intel_dp); |
9934c132 JB |
1346 | } |
1347 | ||
4be73780 | 1348 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
32f9d658 | 1349 | { |
da63a9f2 PZ |
1350 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1351 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
32f9d658 ZW |
1352 | struct drm_i915_private *dev_priv = dev->dev_private; |
1353 | u32 pp; | |
453c5420 | 1354 | u32 pp_ctrl_reg; |
32f9d658 | 1355 | |
f01eca2e KP |
1356 | if (!is_edp(intel_dp)) |
1357 | return; | |
1358 | ||
28c97730 | 1359 | DRM_DEBUG_KMS("\n"); |
01cb9ea6 JB |
1360 | /* |
1361 | * If we enable the backlight right away following a panel power | |
1362 | * on, we may see slight flicker as the panel syncs with the eDP | |
1363 | * link. So delay a bit to make sure the image is solid before | |
1364 | * allowing it to appear. | |
1365 | */ | |
4be73780 | 1366 | wait_backlight_on(intel_dp); |
453c5420 | 1367 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 1368 | pp |= EDP_BLC_ENABLE; |
453c5420 | 1369 | |
bf13e81b | 1370 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
1371 | |
1372 | I915_WRITE(pp_ctrl_reg, pp); | |
1373 | POSTING_READ(pp_ctrl_reg); | |
035aa3de | 1374 | |
752aa88a | 1375 | intel_panel_enable_backlight(intel_dp->attached_connector); |
32f9d658 ZW |
1376 | } |
1377 | ||
4be73780 | 1378 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
32f9d658 | 1379 | { |
30add22d | 1380 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
32f9d658 ZW |
1381 | struct drm_i915_private *dev_priv = dev->dev_private; |
1382 | u32 pp; | |
453c5420 | 1383 | u32 pp_ctrl_reg; |
32f9d658 | 1384 | |
f01eca2e KP |
1385 | if (!is_edp(intel_dp)) |
1386 | return; | |
1387 | ||
752aa88a | 1388 | intel_panel_disable_backlight(intel_dp->attached_connector); |
035aa3de | 1389 | |
28c97730 | 1390 | DRM_DEBUG_KMS("\n"); |
453c5420 | 1391 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 1392 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 1393 | |
bf13e81b | 1394 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
1395 | |
1396 | I915_WRITE(pp_ctrl_reg, pp); | |
1397 | POSTING_READ(pp_ctrl_reg); | |
dce56b3c | 1398 | intel_dp->last_backlight_off = jiffies; |
32f9d658 | 1399 | } |
a4fc5ed6 | 1400 | |
2bd2ad64 | 1401 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
d240f20f | 1402 | { |
da63a9f2 PZ |
1403 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1404 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
1405 | struct drm_device *dev = crtc->dev; | |
d240f20f JB |
1406 | struct drm_i915_private *dev_priv = dev->dev_private; |
1407 | u32 dpa_ctl; | |
1408 | ||
2bd2ad64 DV |
1409 | assert_pipe_disabled(dev_priv, |
1410 | to_intel_crtc(crtc)->pipe); | |
1411 | ||
d240f20f JB |
1412 | DRM_DEBUG_KMS("\n"); |
1413 | dpa_ctl = I915_READ(DP_A); | |
0767935e DV |
1414 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
1415 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); | |
1416 | ||
1417 | /* We don't adjust intel_dp->DP while tearing down the link, to | |
1418 | * facilitate link retraining (e.g. after hotplug). Hence clear all | |
1419 | * enable bits here to ensure that we don't enable too much. */ | |
1420 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); | |
1421 | intel_dp->DP |= DP_PLL_ENABLE; | |
1422 | I915_WRITE(DP_A, intel_dp->DP); | |
298b0b39 JB |
1423 | POSTING_READ(DP_A); |
1424 | udelay(200); | |
d240f20f JB |
1425 | } |
1426 | ||
2bd2ad64 | 1427 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
d240f20f | 1428 | { |
da63a9f2 PZ |
1429 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1430 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
1431 | struct drm_device *dev = crtc->dev; | |
d240f20f JB |
1432 | struct drm_i915_private *dev_priv = dev->dev_private; |
1433 | u32 dpa_ctl; | |
1434 | ||
2bd2ad64 DV |
1435 | assert_pipe_disabled(dev_priv, |
1436 | to_intel_crtc(crtc)->pipe); | |
1437 | ||
d240f20f | 1438 | dpa_ctl = I915_READ(DP_A); |
0767935e DV |
1439 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
1440 | "dp pll off, should be on\n"); | |
1441 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); | |
1442 | ||
1443 | /* We can't rely on the value tracked for the DP register in | |
1444 | * intel_dp->DP because link_down must not change that (otherwise link | |
1445 | * re-training will fail. */ | |
298b0b39 | 1446 | dpa_ctl &= ~DP_PLL_ENABLE; |
d240f20f | 1447 | I915_WRITE(DP_A, dpa_ctl); |
1af5fa1b | 1448 | POSTING_READ(DP_A); |
d240f20f JB |
1449 | udelay(200); |
1450 | } | |
1451 | ||
c7ad3810 | 1452 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 1453 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 JB |
1454 | { |
1455 | int ret, i; | |
1456 | ||
1457 | /* Should have a valid DPCD by this point */ | |
1458 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
1459 | return; | |
1460 | ||
1461 | if (mode != DRM_MODE_DPMS_ON) { | |
1462 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, | |
1463 | DP_SET_POWER_D3); | |
1464 | if (ret != 1) | |
1465 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); | |
1466 | } else { | |
1467 | /* | |
1468 | * When turning on, we need to retry for 1ms to give the sink | |
1469 | * time to wake up. | |
1470 | */ | |
1471 | for (i = 0; i < 3; i++) { | |
1472 | ret = intel_dp_aux_native_write_1(intel_dp, | |
1473 | DP_SET_POWER, | |
1474 | DP_SET_POWER_D0); | |
1475 | if (ret == 1) | |
1476 | break; | |
1477 | msleep(1); | |
1478 | } | |
1479 | } | |
1480 | } | |
1481 | ||
19d8fe15 DV |
1482 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
1483 | enum pipe *pipe) | |
d240f20f | 1484 | { |
19d8fe15 | 1485 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1486 | enum port port = dp_to_dig_port(intel_dp)->port; |
19d8fe15 DV |
1487 | struct drm_device *dev = encoder->base.dev; |
1488 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d129bea ID |
1489 | enum intel_display_power_domain power_domain; |
1490 | u32 tmp; | |
1491 | ||
1492 | power_domain = intel_display_port_power_domain(encoder); | |
1493 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
1494 | return false; | |
1495 | ||
1496 | tmp = I915_READ(intel_dp->output_reg); | |
19d8fe15 DV |
1497 | |
1498 | if (!(tmp & DP_PORT_EN)) | |
1499 | return false; | |
1500 | ||
bc7d38a4 | 1501 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
19d8fe15 | 1502 | *pipe = PORT_TO_PIPE_CPT(tmp); |
bc7d38a4 | 1503 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
19d8fe15 DV |
1504 | *pipe = PORT_TO_PIPE(tmp); |
1505 | } else { | |
1506 | u32 trans_sel; | |
1507 | u32 trans_dp; | |
1508 | int i; | |
1509 | ||
1510 | switch (intel_dp->output_reg) { | |
1511 | case PCH_DP_B: | |
1512 | trans_sel = TRANS_DP_PORT_SEL_B; | |
1513 | break; | |
1514 | case PCH_DP_C: | |
1515 | trans_sel = TRANS_DP_PORT_SEL_C; | |
1516 | break; | |
1517 | case PCH_DP_D: | |
1518 | trans_sel = TRANS_DP_PORT_SEL_D; | |
1519 | break; | |
1520 | default: | |
1521 | return true; | |
1522 | } | |
1523 | ||
1524 | for_each_pipe(i) { | |
1525 | trans_dp = I915_READ(TRANS_DP_CTL(i)); | |
1526 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { | |
1527 | *pipe = i; | |
1528 | return true; | |
1529 | } | |
1530 | } | |
19d8fe15 | 1531 | |
4a0833ec DV |
1532 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
1533 | intel_dp->output_reg); | |
1534 | } | |
d240f20f | 1535 | |
19d8fe15 DV |
1536 | return true; |
1537 | } | |
d240f20f | 1538 | |
045ac3b5 JB |
1539 | static void intel_dp_get_config(struct intel_encoder *encoder, |
1540 | struct intel_crtc_config *pipe_config) | |
1541 | { | |
1542 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
045ac3b5 | 1543 | u32 tmp, flags = 0; |
63000ef6 XZ |
1544 | struct drm_device *dev = encoder->base.dev; |
1545 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1546 | enum port port = dp_to_dig_port(intel_dp)->port; | |
1547 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
18442d08 | 1548 | int dotclock; |
045ac3b5 | 1549 | |
63000ef6 XZ |
1550 | if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { |
1551 | tmp = I915_READ(intel_dp->output_reg); | |
1552 | if (tmp & DP_SYNC_HS_HIGH) | |
1553 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1554 | else | |
1555 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 1556 | |
63000ef6 XZ |
1557 | if (tmp & DP_SYNC_VS_HIGH) |
1558 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1559 | else | |
1560 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1561 | } else { | |
1562 | tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); | |
1563 | if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
1564 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1565 | else | |
1566 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 1567 | |
63000ef6 XZ |
1568 | if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
1569 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1570 | else | |
1571 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1572 | } | |
045ac3b5 JB |
1573 | |
1574 | pipe_config->adjusted_mode.flags |= flags; | |
f1f644dc | 1575 | |
eb14cb74 VS |
1576 | pipe_config->has_dp_encoder = true; |
1577 | ||
1578 | intel_dp_get_m_n(crtc, pipe_config); | |
1579 | ||
18442d08 | 1580 | if (port == PORT_A) { |
f1f644dc JB |
1581 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) |
1582 | pipe_config->port_clock = 162000; | |
1583 | else | |
1584 | pipe_config->port_clock = 270000; | |
1585 | } | |
18442d08 VS |
1586 | |
1587 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, | |
1588 | &pipe_config->dp_m_n); | |
1589 | ||
1590 | if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) | |
1591 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
1592 | ||
241bfc38 | 1593 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
7f16e5c1 | 1594 | |
c6cd2ee2 JN |
1595 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
1596 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { | |
1597 | /* | |
1598 | * This is a big fat ugly hack. | |
1599 | * | |
1600 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
1601 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
1602 | * unknown we fail to light up. Yet the same BIOS boots up with | |
1603 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
1604 | * max, not what it tells us to use. | |
1605 | * | |
1606 | * Note: This will still be broken if the eDP panel is not lit | |
1607 | * up by the BIOS, and thus we can't get the mode at module | |
1608 | * load. | |
1609 | */ | |
1610 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
1611 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); | |
1612 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; | |
1613 | } | |
045ac3b5 JB |
1614 | } |
1615 | ||
a031d709 | 1616 | static bool is_edp_psr(struct drm_device *dev) |
2293bb5c | 1617 | { |
a031d709 RV |
1618 | struct drm_i915_private *dev_priv = dev->dev_private; |
1619 | ||
1620 | return dev_priv->psr.sink_support; | |
2293bb5c SK |
1621 | } |
1622 | ||
2b28bb1b RV |
1623 | static bool intel_edp_is_psr_enabled(struct drm_device *dev) |
1624 | { | |
1625 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1626 | ||
18b5992c | 1627 | if (!HAS_PSR(dev)) |
2b28bb1b RV |
1628 | return false; |
1629 | ||
18b5992c | 1630 | return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; |
2b28bb1b RV |
1631 | } |
1632 | ||
1633 | static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, | |
1634 | struct edp_vsc_psr *vsc_psr) | |
1635 | { | |
1636 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
1637 | struct drm_device *dev = dig_port->base.base.dev; | |
1638 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1639 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); | |
1640 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); | |
1641 | u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); | |
1642 | uint32_t *data = (uint32_t *) vsc_psr; | |
1643 | unsigned int i; | |
1644 | ||
1645 | /* As per BSPec (Pipe Video Data Island Packet), we need to disable | |
1646 | the video DIP being updated before program video DIP data buffer | |
1647 | registers for DIP being updated. */ | |
1648 | I915_WRITE(ctl_reg, 0); | |
1649 | POSTING_READ(ctl_reg); | |
1650 | ||
1651 | for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { | |
1652 | if (i < sizeof(struct edp_vsc_psr)) | |
1653 | I915_WRITE(data_reg + i, *data++); | |
1654 | else | |
1655 | I915_WRITE(data_reg + i, 0); | |
1656 | } | |
1657 | ||
1658 | I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); | |
1659 | POSTING_READ(ctl_reg); | |
1660 | } | |
1661 | ||
1662 | static void intel_edp_psr_setup(struct intel_dp *intel_dp) | |
1663 | { | |
1664 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1665 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1666 | struct edp_vsc_psr psr_vsc; | |
1667 | ||
1668 | if (intel_dp->psr_setup_done) | |
1669 | return; | |
1670 | ||
1671 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ | |
1672 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
1673 | psr_vsc.sdp_header.HB0 = 0; | |
1674 | psr_vsc.sdp_header.HB1 = 0x7; | |
1675 | psr_vsc.sdp_header.HB2 = 0x2; | |
1676 | psr_vsc.sdp_header.HB3 = 0x8; | |
1677 | intel_edp_psr_write_vsc(intel_dp, &psr_vsc); | |
1678 | ||
1679 | /* Avoid continuous PSR exit by masking memup and hpd */ | |
18b5992c | 1680 | I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | |
0cc4b699 | 1681 | EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); |
2b28bb1b RV |
1682 | |
1683 | intel_dp->psr_setup_done = true; | |
1684 | } | |
1685 | ||
1686 | static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) | |
1687 | { | |
1688 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1689 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ec5b01dd | 1690 | uint32_t aux_clock_divider; |
2b28bb1b RV |
1691 | int precharge = 0x3; |
1692 | int msg_size = 5; /* Header(4) + Message(1) */ | |
1693 | ||
ec5b01dd DL |
1694 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); |
1695 | ||
2b28bb1b RV |
1696 | /* Enable PSR in sink */ |
1697 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) | |
1698 | intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, | |
1699 | DP_PSR_ENABLE & | |
1700 | ~DP_PSR_MAIN_LINK_ACTIVE); | |
1701 | else | |
1702 | intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, | |
1703 | DP_PSR_ENABLE | | |
1704 | DP_PSR_MAIN_LINK_ACTIVE); | |
1705 | ||
1706 | /* Setup AUX registers */ | |
18b5992c BW |
1707 | I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); |
1708 | I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); | |
1709 | I915_WRITE(EDP_PSR_AUX_CTL(dev), | |
2b28bb1b RV |
1710 | DP_AUX_CH_CTL_TIME_OUT_400us | |
1711 | (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
1712 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
1713 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); | |
1714 | } | |
1715 | ||
1716 | static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) | |
1717 | { | |
1718 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1719 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1720 | uint32_t max_sleep_time = 0x1f; | |
1721 | uint32_t idle_frames = 1; | |
1722 | uint32_t val = 0x0; | |
ed8546ac | 1723 | const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
2b28bb1b RV |
1724 | |
1725 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { | |
1726 | val |= EDP_PSR_LINK_STANDBY; | |
1727 | val |= EDP_PSR_TP2_TP3_TIME_0us; | |
1728 | val |= EDP_PSR_TP1_TIME_0us; | |
1729 | val |= EDP_PSR_SKIP_AUX_EXIT; | |
1730 | } else | |
1731 | val |= EDP_PSR_LINK_DISABLE; | |
1732 | ||
18b5992c | 1733 | I915_WRITE(EDP_PSR_CTL(dev), val | |
ed8546ac | 1734 | IS_BROADWELL(dev) ? 0 : link_entry_time | |
2b28bb1b RV |
1735 | max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | |
1736 | idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | | |
1737 | EDP_PSR_ENABLE); | |
1738 | } | |
1739 | ||
3f51e471 RV |
1740 | static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) |
1741 | { | |
1742 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
1743 | struct drm_device *dev = dig_port->base.base.dev; | |
1744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1745 | struct drm_crtc *crtc = dig_port->base.base.crtc; | |
1746 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1747 | struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj; | |
1748 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; | |
1749 | ||
a031d709 RV |
1750 | dev_priv->psr.source_ok = false; |
1751 | ||
18b5992c | 1752 | if (!HAS_PSR(dev)) { |
3f51e471 | 1753 | DRM_DEBUG_KMS("PSR not supported on this platform\n"); |
3f51e471 RV |
1754 | return false; |
1755 | } | |
1756 | ||
1757 | if ((intel_encoder->type != INTEL_OUTPUT_EDP) || | |
1758 | (dig_port->port != PORT_A)) { | |
1759 | DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); | |
3f51e471 RV |
1760 | return false; |
1761 | } | |
1762 | ||
d330a953 | 1763 | if (!i915.enable_psr) { |
105b7c11 | 1764 | DRM_DEBUG_KMS("PSR disable by flag\n"); |
105b7c11 RV |
1765 | return false; |
1766 | } | |
1767 | ||
cd234b0b CW |
1768 | crtc = dig_port->base.base.crtc; |
1769 | if (crtc == NULL) { | |
1770 | DRM_DEBUG_KMS("crtc not active for PSR\n"); | |
cd234b0b CW |
1771 | return false; |
1772 | } | |
1773 | ||
1774 | intel_crtc = to_intel_crtc(crtc); | |
20ddf665 | 1775 | if (!intel_crtc_active(crtc)) { |
3f51e471 | 1776 | DRM_DEBUG_KMS("crtc not active for PSR\n"); |
3f51e471 RV |
1777 | return false; |
1778 | } | |
1779 | ||
cd234b0b | 1780 | obj = to_intel_framebuffer(crtc->fb)->obj; |
3f51e471 RV |
1781 | if (obj->tiling_mode != I915_TILING_X || |
1782 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
1783 | DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n"); | |
3f51e471 RV |
1784 | return false; |
1785 | } | |
1786 | ||
1787 | if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) { | |
1788 | DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n"); | |
3f51e471 RV |
1789 | return false; |
1790 | } | |
1791 | ||
1792 | if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & | |
1793 | S3D_ENABLE) { | |
1794 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); | |
3f51e471 RV |
1795 | return false; |
1796 | } | |
1797 | ||
ca73b4f0 | 1798 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
3f51e471 | 1799 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
3f51e471 RV |
1800 | return false; |
1801 | } | |
1802 | ||
a031d709 | 1803 | dev_priv->psr.source_ok = true; |
3f51e471 RV |
1804 | return true; |
1805 | } | |
1806 | ||
3d739d92 | 1807 | static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) |
2b28bb1b RV |
1808 | { |
1809 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1810 | ||
3f51e471 RV |
1811 | if (!intel_edp_psr_match_conditions(intel_dp) || |
1812 | intel_edp_is_psr_enabled(dev)) | |
2b28bb1b RV |
1813 | return; |
1814 | ||
1815 | /* Setup PSR once */ | |
1816 | intel_edp_psr_setup(intel_dp); | |
1817 | ||
1818 | /* Enable PSR on the panel */ | |
1819 | intel_edp_psr_enable_sink(intel_dp); | |
1820 | ||
1821 | /* Enable PSR on the host */ | |
1822 | intel_edp_psr_enable_source(intel_dp); | |
1823 | } | |
1824 | ||
3d739d92 RV |
1825 | void intel_edp_psr_enable(struct intel_dp *intel_dp) |
1826 | { | |
1827 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1828 | ||
1829 | if (intel_edp_psr_match_conditions(intel_dp) && | |
1830 | !intel_edp_is_psr_enabled(dev)) | |
1831 | intel_edp_psr_do_enable(intel_dp); | |
1832 | } | |
1833 | ||
2b28bb1b RV |
1834 | void intel_edp_psr_disable(struct intel_dp *intel_dp) |
1835 | { | |
1836 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1837 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1838 | ||
1839 | if (!intel_edp_is_psr_enabled(dev)) | |
1840 | return; | |
1841 | ||
18b5992c BW |
1842 | I915_WRITE(EDP_PSR_CTL(dev), |
1843 | I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); | |
2b28bb1b RV |
1844 | |
1845 | /* Wait till PSR is idle */ | |
18b5992c | 1846 | if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & |
2b28bb1b RV |
1847 | EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) |
1848 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); | |
1849 | } | |
1850 | ||
3d739d92 RV |
1851 | void intel_edp_psr_update(struct drm_device *dev) |
1852 | { | |
1853 | struct intel_encoder *encoder; | |
1854 | struct intel_dp *intel_dp = NULL; | |
1855 | ||
1856 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) | |
1857 | if (encoder->type == INTEL_OUTPUT_EDP) { | |
1858 | intel_dp = enc_to_intel_dp(&encoder->base); | |
1859 | ||
a031d709 | 1860 | if (!is_edp_psr(dev)) |
3d739d92 RV |
1861 | return; |
1862 | ||
1863 | if (!intel_edp_psr_match_conditions(intel_dp)) | |
1864 | intel_edp_psr_disable(intel_dp); | |
1865 | else | |
1866 | if (!intel_edp_is_psr_enabled(dev)) | |
1867 | intel_edp_psr_do_enable(intel_dp); | |
1868 | } | |
1869 | } | |
1870 | ||
e8cb4558 | 1871 | static void intel_disable_dp(struct intel_encoder *encoder) |
d240f20f | 1872 | { |
e8cb4558 | 1873 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 ID |
1874 | enum port port = dp_to_dig_port(intel_dp)->port; |
1875 | struct drm_device *dev = encoder->base.dev; | |
6cb49835 DV |
1876 | |
1877 | /* Make sure the panel is off before trying to change the mode. But also | |
1878 | * ensure that we have vdd while we switch off the panel. */ | |
b3064154 | 1879 | edp_panel_vdd_on(intel_dp); |
4be73780 | 1880 | intel_edp_backlight_off(intel_dp); |
fdbc3b1f | 1881 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
4be73780 | 1882 | intel_edp_panel_off(intel_dp); |
b3064154 | 1883 | edp_panel_vdd_off(intel_dp, true); |
3739850b DV |
1884 | |
1885 | /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ | |
982a3866 | 1886 | if (!(port == PORT_A || IS_VALLEYVIEW(dev))) |
3739850b | 1887 | intel_dp_link_down(intel_dp); |
d240f20f JB |
1888 | } |
1889 | ||
2bd2ad64 | 1890 | static void intel_post_disable_dp(struct intel_encoder *encoder) |
d240f20f | 1891 | { |
2bd2ad64 | 1892 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 1893 | enum port port = dp_to_dig_port(intel_dp)->port; |
b2634017 | 1894 | struct drm_device *dev = encoder->base.dev; |
2bd2ad64 | 1895 | |
982a3866 | 1896 | if (port == PORT_A || IS_VALLEYVIEW(dev)) { |
3739850b | 1897 | intel_dp_link_down(intel_dp); |
b2634017 JB |
1898 | if (!IS_VALLEYVIEW(dev)) |
1899 | ironlake_edp_pll_off(intel_dp); | |
3739850b | 1900 | } |
2bd2ad64 DV |
1901 | } |
1902 | ||
e8cb4558 | 1903 | static void intel_enable_dp(struct intel_encoder *encoder) |
d240f20f | 1904 | { |
e8cb4558 DV |
1905 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1906 | struct drm_device *dev = encoder->base.dev; | |
1907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1908 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); | |
5d613501 | 1909 | |
0c33d8d7 DV |
1910 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
1911 | return; | |
5d613501 | 1912 | |
4be73780 | 1913 | edp_panel_vdd_on(intel_dp); |
f01eca2e | 1914 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 1915 | intel_dp_start_link_train(intel_dp); |
4be73780 DV |
1916 | intel_edp_panel_on(intel_dp); |
1917 | edp_panel_vdd_off(intel_dp, true); | |
33a34e4e | 1918 | intel_dp_complete_link_train(intel_dp); |
3ab9c637 | 1919 | intel_dp_stop_link_train(intel_dp); |
ab1f90f9 | 1920 | } |
89b667f8 | 1921 | |
ecff4f3b JN |
1922 | static void g4x_enable_dp(struct intel_encoder *encoder) |
1923 | { | |
828f5c6e JN |
1924 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1925 | ||
ecff4f3b | 1926 | intel_enable_dp(encoder); |
4be73780 | 1927 | intel_edp_backlight_on(intel_dp); |
ab1f90f9 | 1928 | } |
89b667f8 | 1929 | |
ab1f90f9 JN |
1930 | static void vlv_enable_dp(struct intel_encoder *encoder) |
1931 | { | |
828f5c6e JN |
1932 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1933 | ||
4be73780 | 1934 | intel_edp_backlight_on(intel_dp); |
d240f20f JB |
1935 | } |
1936 | ||
ecff4f3b | 1937 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
ab1f90f9 JN |
1938 | { |
1939 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
1940 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
1941 | ||
1942 | if (dport->port == PORT_A) | |
1943 | ironlake_edp_pll_on(intel_dp); | |
1944 | } | |
1945 | ||
1946 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) | |
a4fc5ed6 | 1947 | { |
2bd2ad64 | 1948 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1949 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
b2634017 | 1950 | struct drm_device *dev = encoder->base.dev; |
89b667f8 | 1951 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab1f90f9 | 1952 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
e4607fcf | 1953 | enum dpio_channel port = vlv_dport_to_channel(dport); |
ab1f90f9 | 1954 | int pipe = intel_crtc->pipe; |
bf13e81b | 1955 | struct edp_power_seq power_seq; |
ab1f90f9 | 1956 | u32 val; |
a4fc5ed6 | 1957 | |
ab1f90f9 | 1958 | mutex_lock(&dev_priv->dpio_lock); |
89b667f8 | 1959 | |
ab3c759a | 1960 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
ab1f90f9 JN |
1961 | val = 0; |
1962 | if (pipe) | |
1963 | val |= (1<<21); | |
1964 | else | |
1965 | val &= ~(1<<21); | |
1966 | val |= 0x001000c4; | |
ab3c759a CML |
1967 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
1968 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); | |
1969 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
89b667f8 | 1970 | |
ab1f90f9 JN |
1971 | mutex_unlock(&dev_priv->dpio_lock); |
1972 | ||
2cac613b ID |
1973 | if (is_edp(intel_dp)) { |
1974 | /* init power sequencer on this pipe and port */ | |
1975 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); | |
1976 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, | |
1977 | &power_seq); | |
1978 | } | |
bf13e81b | 1979 | |
ab1f90f9 JN |
1980 | intel_enable_dp(encoder); |
1981 | ||
e4607fcf | 1982 | vlv_wait_port_ready(dev_priv, dport); |
89b667f8 JB |
1983 | } |
1984 | ||
ecff4f3b | 1985 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1986 | { |
1987 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1988 | struct drm_device *dev = encoder->base.dev; | |
1989 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
1990 | struct intel_crtc *intel_crtc = |
1991 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1992 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1993 | int pipe = intel_crtc->pipe; |
89b667f8 | 1994 | |
89b667f8 | 1995 | /* Program Tx lane resets to default */ |
0980a60f | 1996 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 1997 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
89b667f8 JB |
1998 | DPIO_PCS_TX_LANE2_RESET | |
1999 | DPIO_PCS_TX_LANE1_RESET); | |
ab3c759a | 2000 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
89b667f8 JB |
2001 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
2002 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
2003 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
2004 | DPIO_PCS_CLK_SOFT_RESET); | |
2005 | ||
2006 | /* Fix up inter-pair skew failure */ | |
ab3c759a CML |
2007 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
2008 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
2009 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
0980a60f | 2010 | mutex_unlock(&dev_priv->dpio_lock); |
a4fc5ed6 KP |
2011 | } |
2012 | ||
2013 | /* | |
df0c237d JB |
2014 | * Native read with retry for link status and receiver capability reads for |
2015 | * cases where the sink may still be asleep. | |
a4fc5ed6 KP |
2016 | */ |
2017 | static bool | |
df0c237d JB |
2018 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
2019 | uint8_t *recv, int recv_bytes) | |
a4fc5ed6 | 2020 | { |
61da5fab JB |
2021 | int ret, i; |
2022 | ||
df0c237d JB |
2023 | /* |
2024 | * Sinks are *supposed* to come up within 1ms from an off state, | |
2025 | * but we're also supposed to retry 3 times per the spec. | |
2026 | */ | |
61da5fab | 2027 | for (i = 0; i < 3; i++) { |
df0c237d JB |
2028 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
2029 | recv_bytes); | |
2030 | if (ret == recv_bytes) | |
61da5fab JB |
2031 | return true; |
2032 | msleep(1); | |
2033 | } | |
a4fc5ed6 | 2034 | |
61da5fab | 2035 | return false; |
a4fc5ed6 KP |
2036 | } |
2037 | ||
2038 | /* | |
2039 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
2040 | * link status information | |
2041 | */ | |
2042 | static bool | |
93f62dad | 2043 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 2044 | { |
df0c237d JB |
2045 | return intel_dp_aux_native_read_retry(intel_dp, |
2046 | DP_LANE0_1_STATUS, | |
93f62dad | 2047 | link_status, |
df0c237d | 2048 | DP_LINK_STATUS_SIZE); |
a4fc5ed6 KP |
2049 | } |
2050 | ||
a4fc5ed6 KP |
2051 | /* |
2052 | * These are source-specific values; current Intel hardware supports | |
2053 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
2054 | */ | |
a4fc5ed6 KP |
2055 | |
2056 | static uint8_t | |
1a2eb460 | 2057 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 2058 | { |
30add22d | 2059 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bc7d38a4 | 2060 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 2061 | |
8f93f4f1 | 2062 | if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev)) |
e2fa6fba | 2063 | return DP_TRAIN_VOLTAGE_SWING_1200; |
bc7d38a4 | 2064 | else if (IS_GEN7(dev) && port == PORT_A) |
1a2eb460 | 2065 | return DP_TRAIN_VOLTAGE_SWING_800; |
bc7d38a4 | 2066 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
1a2eb460 KP |
2067 | return DP_TRAIN_VOLTAGE_SWING_1200; |
2068 | else | |
2069 | return DP_TRAIN_VOLTAGE_SWING_800; | |
2070 | } | |
2071 | ||
2072 | static uint8_t | |
2073 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) | |
2074 | { | |
30add22d | 2075 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bc7d38a4 | 2076 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 2077 | |
8f93f4f1 PZ |
2078 | if (IS_BROADWELL(dev)) { |
2079 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2080 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2081 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2082 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2083 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2084 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
2085 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2086 | default: | |
2087 | return DP_TRAIN_PRE_EMPHASIS_0; | |
2088 | } | |
2089 | } else if (IS_HASWELL(dev)) { | |
d6c0d722 PZ |
2090 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2091 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2092 | return DP_TRAIN_PRE_EMPHASIS_9_5; | |
2093 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2094 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2095 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2096 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
2097 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2098 | default: | |
2099 | return DP_TRAIN_PRE_EMPHASIS_0; | |
2100 | } | |
e2fa6fba P |
2101 | } else if (IS_VALLEYVIEW(dev)) { |
2102 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2103 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2104 | return DP_TRAIN_PRE_EMPHASIS_9_5; | |
2105 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2106 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2107 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2108 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
2109 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2110 | default: | |
2111 | return DP_TRAIN_PRE_EMPHASIS_0; | |
2112 | } | |
bc7d38a4 | 2113 | } else if (IS_GEN7(dev) && port == PORT_A) { |
1a2eb460 KP |
2114 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
2115 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2116 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2117 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2118 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2119 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
2120 | default: | |
2121 | return DP_TRAIN_PRE_EMPHASIS_0; | |
2122 | } | |
2123 | } else { | |
2124 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2125 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2126 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2127 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2128 | return DP_TRAIN_PRE_EMPHASIS_6; | |
2129 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2130 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
2131 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2132 | default: | |
2133 | return DP_TRAIN_PRE_EMPHASIS_0; | |
2134 | } | |
a4fc5ed6 KP |
2135 | } |
2136 | } | |
2137 | ||
e2fa6fba P |
2138 | static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) |
2139 | { | |
2140 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
2141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2142 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
5e69f97f CML |
2143 | struct intel_crtc *intel_crtc = |
2144 | to_intel_crtc(dport->base.base.crtc); | |
e2fa6fba P |
2145 | unsigned long demph_reg_value, preemph_reg_value, |
2146 | uniqtranscale_reg_value; | |
2147 | uint8_t train_set = intel_dp->train_set[0]; | |
e4607fcf | 2148 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 2149 | int pipe = intel_crtc->pipe; |
e2fa6fba P |
2150 | |
2151 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
2152 | case DP_TRAIN_PRE_EMPHASIS_0: | |
2153 | preemph_reg_value = 0x0004000; | |
2154 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2155 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2156 | demph_reg_value = 0x2B405555; | |
2157 | uniqtranscale_reg_value = 0x552AB83A; | |
2158 | break; | |
2159 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2160 | demph_reg_value = 0x2B404040; | |
2161 | uniqtranscale_reg_value = 0x5548B83A; | |
2162 | break; | |
2163 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2164 | demph_reg_value = 0x2B245555; | |
2165 | uniqtranscale_reg_value = 0x5560B83A; | |
2166 | break; | |
2167 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2168 | demph_reg_value = 0x2B405555; | |
2169 | uniqtranscale_reg_value = 0x5598DA3A; | |
2170 | break; | |
2171 | default: | |
2172 | return 0; | |
2173 | } | |
2174 | break; | |
2175 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
2176 | preemph_reg_value = 0x0002000; | |
2177 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2178 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2179 | demph_reg_value = 0x2B404040; | |
2180 | uniqtranscale_reg_value = 0x5552B83A; | |
2181 | break; | |
2182 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2183 | demph_reg_value = 0x2B404848; | |
2184 | uniqtranscale_reg_value = 0x5580B83A; | |
2185 | break; | |
2186 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2187 | demph_reg_value = 0x2B404040; | |
2188 | uniqtranscale_reg_value = 0x55ADDA3A; | |
2189 | break; | |
2190 | default: | |
2191 | return 0; | |
2192 | } | |
2193 | break; | |
2194 | case DP_TRAIN_PRE_EMPHASIS_6: | |
2195 | preemph_reg_value = 0x0000000; | |
2196 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2197 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2198 | demph_reg_value = 0x2B305555; | |
2199 | uniqtranscale_reg_value = 0x5570B83A; | |
2200 | break; | |
2201 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2202 | demph_reg_value = 0x2B2B4040; | |
2203 | uniqtranscale_reg_value = 0x55ADDA3A; | |
2204 | break; | |
2205 | default: | |
2206 | return 0; | |
2207 | } | |
2208 | break; | |
2209 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
2210 | preemph_reg_value = 0x0006000; | |
2211 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2212 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2213 | demph_reg_value = 0x1B405555; | |
2214 | uniqtranscale_reg_value = 0x55ADDA3A; | |
2215 | break; | |
2216 | default: | |
2217 | return 0; | |
2218 | } | |
2219 | break; | |
2220 | default: | |
2221 | return 0; | |
2222 | } | |
2223 | ||
0980a60f | 2224 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a CML |
2225 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
2226 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); | |
2227 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), | |
e2fa6fba | 2228 | uniqtranscale_reg_value); |
ab3c759a CML |
2229 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
2230 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
2231 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); | |
2232 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); | |
0980a60f | 2233 | mutex_unlock(&dev_priv->dpio_lock); |
e2fa6fba P |
2234 | |
2235 | return 0; | |
2236 | } | |
2237 | ||
a4fc5ed6 | 2238 | static void |
0301b3ac JN |
2239 | intel_get_adjust_train(struct intel_dp *intel_dp, |
2240 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) | |
a4fc5ed6 KP |
2241 | { |
2242 | uint8_t v = 0; | |
2243 | uint8_t p = 0; | |
2244 | int lane; | |
1a2eb460 KP |
2245 | uint8_t voltage_max; |
2246 | uint8_t preemph_max; | |
a4fc5ed6 | 2247 | |
33a34e4e | 2248 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
0f037bde DV |
2249 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
2250 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); | |
a4fc5ed6 KP |
2251 | |
2252 | if (this_v > v) | |
2253 | v = this_v; | |
2254 | if (this_p > p) | |
2255 | p = this_p; | |
2256 | } | |
2257 | ||
1a2eb460 | 2258 | voltage_max = intel_dp_voltage_max(intel_dp); |
417e822d KP |
2259 | if (v >= voltage_max) |
2260 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; | |
a4fc5ed6 | 2261 | |
1a2eb460 KP |
2262 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
2263 | if (p >= preemph_max) | |
2264 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
a4fc5ed6 KP |
2265 | |
2266 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 2267 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
2268 | } |
2269 | ||
2270 | static uint32_t | |
f0a3424e | 2271 | intel_gen4_signal_levels(uint8_t train_set) |
a4fc5ed6 | 2272 | { |
3cf2efb1 | 2273 | uint32_t signal_levels = 0; |
a4fc5ed6 | 2274 | |
3cf2efb1 | 2275 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
a4fc5ed6 KP |
2276 | case DP_TRAIN_VOLTAGE_SWING_400: |
2277 | default: | |
2278 | signal_levels |= DP_VOLTAGE_0_4; | |
2279 | break; | |
2280 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2281 | signal_levels |= DP_VOLTAGE_0_6; | |
2282 | break; | |
2283 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2284 | signal_levels |= DP_VOLTAGE_0_8; | |
2285 | break; | |
2286 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2287 | signal_levels |= DP_VOLTAGE_1_2; | |
2288 | break; | |
2289 | } | |
3cf2efb1 | 2290 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
a4fc5ed6 KP |
2291 | case DP_TRAIN_PRE_EMPHASIS_0: |
2292 | default: | |
2293 | signal_levels |= DP_PRE_EMPHASIS_0; | |
2294 | break; | |
2295 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
2296 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
2297 | break; | |
2298 | case DP_TRAIN_PRE_EMPHASIS_6: | |
2299 | signal_levels |= DP_PRE_EMPHASIS_6; | |
2300 | break; | |
2301 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
2302 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
2303 | break; | |
2304 | } | |
2305 | return signal_levels; | |
2306 | } | |
2307 | ||
e3421a18 ZW |
2308 | /* Gen6's DP voltage swing and pre-emphasis control */ |
2309 | static uint32_t | |
2310 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
2311 | { | |
3c5a62b5 YL |
2312 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2313 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2314 | switch (signal_levels) { | |
e3421a18 | 2315 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
2316 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
2317 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
2318 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2319 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; | |
e3421a18 | 2320 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
3c5a62b5 YL |
2321 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
2322 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; | |
e3421a18 | 2323 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3c5a62b5 YL |
2324 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2325 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; | |
e3421a18 | 2326 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
2327 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
2328 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; | |
e3421a18 | 2329 | default: |
3c5a62b5 YL |
2330 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
2331 | "0x%x\n", signal_levels); | |
2332 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
2333 | } |
2334 | } | |
2335 | ||
1a2eb460 KP |
2336 | /* Gen7's DP voltage swing and pre-emphasis control */ |
2337 | static uint32_t | |
2338 | intel_gen7_edp_signal_levels(uint8_t train_set) | |
2339 | { | |
2340 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
2341 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2342 | switch (signal_levels) { | |
2343 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
2344 | return EDP_LINK_TRAIN_400MV_0DB_IVB; | |
2345 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2346 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; | |
2347 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
2348 | return EDP_LINK_TRAIN_400MV_6DB_IVB; | |
2349 | ||
2350 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: | |
2351 | return EDP_LINK_TRAIN_600MV_0DB_IVB; | |
2352 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2353 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; | |
2354 | ||
2355 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: | |
2356 | return EDP_LINK_TRAIN_800MV_0DB_IVB; | |
2357 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2358 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; | |
2359 | ||
2360 | default: | |
2361 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
2362 | "0x%x\n", signal_levels); | |
2363 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
2364 | } | |
2365 | } | |
2366 | ||
d6c0d722 PZ |
2367 | /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ |
2368 | static uint32_t | |
f0a3424e | 2369 | intel_hsw_signal_levels(uint8_t train_set) |
a4fc5ed6 | 2370 | { |
d6c0d722 PZ |
2371 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2372 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2373 | switch (signal_levels) { | |
2374 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
2375 | return DDI_BUF_EMP_400MV_0DB_HSW; | |
2376 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2377 | return DDI_BUF_EMP_400MV_3_5DB_HSW; | |
2378 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
2379 | return DDI_BUF_EMP_400MV_6DB_HSW; | |
2380 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: | |
2381 | return DDI_BUF_EMP_400MV_9_5DB_HSW; | |
a4fc5ed6 | 2382 | |
d6c0d722 PZ |
2383 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
2384 | return DDI_BUF_EMP_600MV_0DB_HSW; | |
2385 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2386 | return DDI_BUF_EMP_600MV_3_5DB_HSW; | |
2387 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: | |
2388 | return DDI_BUF_EMP_600MV_6DB_HSW; | |
a4fc5ed6 | 2389 | |
d6c0d722 PZ |
2390 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
2391 | return DDI_BUF_EMP_800MV_0DB_HSW; | |
2392 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2393 | return DDI_BUF_EMP_800MV_3_5DB_HSW; | |
2394 | default: | |
2395 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
2396 | "0x%x\n", signal_levels); | |
2397 | return DDI_BUF_EMP_400MV_0DB_HSW; | |
a4fc5ed6 | 2398 | } |
a4fc5ed6 KP |
2399 | } |
2400 | ||
8f93f4f1 PZ |
2401 | static uint32_t |
2402 | intel_bdw_signal_levels(uint8_t train_set) | |
2403 | { | |
2404 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
2405 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2406 | switch (signal_levels) { | |
2407 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
2408 | return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ | |
2409 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2410 | return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */ | |
2411 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
2412 | return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */ | |
2413 | ||
2414 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: | |
2415 | return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */ | |
2416 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2417 | return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */ | |
2418 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: | |
2419 | return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */ | |
2420 | ||
2421 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: | |
2422 | return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */ | |
2423 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2424 | return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */ | |
2425 | ||
2426 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: | |
2427 | return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */ | |
2428 | ||
2429 | default: | |
2430 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
2431 | "0x%x\n", signal_levels); | |
2432 | return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ | |
2433 | } | |
2434 | } | |
2435 | ||
f0a3424e PZ |
2436 | /* Properly updates "DP" with the correct signal levels. */ |
2437 | static void | |
2438 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) | |
2439 | { | |
2440 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bc7d38a4 | 2441 | enum port port = intel_dig_port->port; |
f0a3424e PZ |
2442 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2443 | uint32_t signal_levels, mask; | |
2444 | uint8_t train_set = intel_dp->train_set[0]; | |
2445 | ||
8f93f4f1 PZ |
2446 | if (IS_BROADWELL(dev)) { |
2447 | signal_levels = intel_bdw_signal_levels(train_set); | |
2448 | mask = DDI_BUF_EMP_MASK; | |
2449 | } else if (IS_HASWELL(dev)) { | |
f0a3424e PZ |
2450 | signal_levels = intel_hsw_signal_levels(train_set); |
2451 | mask = DDI_BUF_EMP_MASK; | |
e2fa6fba P |
2452 | } else if (IS_VALLEYVIEW(dev)) { |
2453 | signal_levels = intel_vlv_signal_levels(intel_dp); | |
2454 | mask = 0; | |
bc7d38a4 | 2455 | } else if (IS_GEN7(dev) && port == PORT_A) { |
f0a3424e PZ |
2456 | signal_levels = intel_gen7_edp_signal_levels(train_set); |
2457 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; | |
bc7d38a4 | 2458 | } else if (IS_GEN6(dev) && port == PORT_A) { |
f0a3424e PZ |
2459 | signal_levels = intel_gen6_edp_signal_levels(train_set); |
2460 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; | |
2461 | } else { | |
2462 | signal_levels = intel_gen4_signal_levels(train_set); | |
2463 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; | |
2464 | } | |
2465 | ||
2466 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); | |
2467 | ||
2468 | *DP = (*DP & ~mask) | signal_levels; | |
2469 | } | |
2470 | ||
a4fc5ed6 | 2471 | static bool |
ea5b213a | 2472 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
70aff66c | 2473 | uint32_t *DP, |
58e10eb9 | 2474 | uint8_t dp_train_pat) |
a4fc5ed6 | 2475 | { |
174edf1f PZ |
2476 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2477 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
a4fc5ed6 | 2478 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 2479 | enum port port = intel_dig_port->port; |
2cdfe6c8 JN |
2480 | uint8_t buf[sizeof(intel_dp->train_set) + 1]; |
2481 | int ret, len; | |
a4fc5ed6 | 2482 | |
22b8bf17 | 2483 | if (HAS_DDI(dev)) { |
3ab9c637 | 2484 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
d6c0d722 PZ |
2485 | |
2486 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
2487 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
2488 | else | |
2489 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
2490 | ||
2491 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2492 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2493 | case DP_TRAINING_PATTERN_DISABLE: | |
d6c0d722 PZ |
2494 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
2495 | ||
2496 | break; | |
2497 | case DP_TRAINING_PATTERN_1: | |
2498 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2499 | break; | |
2500 | case DP_TRAINING_PATTERN_2: | |
2501 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
2502 | break; | |
2503 | case DP_TRAINING_PATTERN_3: | |
2504 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
2505 | break; | |
2506 | } | |
174edf1f | 2507 | I915_WRITE(DP_TP_CTL(port), temp); |
d6c0d722 | 2508 | |
bc7d38a4 | 2509 | } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
70aff66c | 2510 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
47ea7542 PZ |
2511 | |
2512 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2513 | case DP_TRAINING_PATTERN_DISABLE: | |
70aff66c | 2514 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
47ea7542 PZ |
2515 | break; |
2516 | case DP_TRAINING_PATTERN_1: | |
70aff66c | 2517 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
47ea7542 PZ |
2518 | break; |
2519 | case DP_TRAINING_PATTERN_2: | |
70aff66c | 2520 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
47ea7542 PZ |
2521 | break; |
2522 | case DP_TRAINING_PATTERN_3: | |
2523 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
70aff66c | 2524 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
47ea7542 PZ |
2525 | break; |
2526 | } | |
2527 | ||
2528 | } else { | |
70aff66c | 2529 | *DP &= ~DP_LINK_TRAIN_MASK; |
47ea7542 PZ |
2530 | |
2531 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2532 | case DP_TRAINING_PATTERN_DISABLE: | |
70aff66c | 2533 | *DP |= DP_LINK_TRAIN_OFF; |
47ea7542 PZ |
2534 | break; |
2535 | case DP_TRAINING_PATTERN_1: | |
70aff66c | 2536 | *DP |= DP_LINK_TRAIN_PAT_1; |
47ea7542 PZ |
2537 | break; |
2538 | case DP_TRAINING_PATTERN_2: | |
70aff66c | 2539 | *DP |= DP_LINK_TRAIN_PAT_2; |
47ea7542 PZ |
2540 | break; |
2541 | case DP_TRAINING_PATTERN_3: | |
2542 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
70aff66c | 2543 | *DP |= DP_LINK_TRAIN_PAT_2; |
47ea7542 PZ |
2544 | break; |
2545 | } | |
2546 | } | |
2547 | ||
70aff66c | 2548 | I915_WRITE(intel_dp->output_reg, *DP); |
ea5b213a | 2549 | POSTING_READ(intel_dp->output_reg); |
a4fc5ed6 | 2550 | |
2cdfe6c8 JN |
2551 | buf[0] = dp_train_pat; |
2552 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == | |
47ea7542 | 2553 | DP_TRAINING_PATTERN_DISABLE) { |
2cdfe6c8 JN |
2554 | /* don't write DP_TRAINING_LANEx_SET on disable */ |
2555 | len = 1; | |
2556 | } else { | |
2557 | /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ | |
2558 | memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); | |
2559 | len = intel_dp->lane_count + 1; | |
47ea7542 | 2560 | } |
a4fc5ed6 | 2561 | |
2cdfe6c8 JN |
2562 | ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET, |
2563 | buf, len); | |
2564 | ||
2565 | return ret == len; | |
a4fc5ed6 KP |
2566 | } |
2567 | ||
70aff66c JN |
2568 | static bool |
2569 | intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, | |
2570 | uint8_t dp_train_pat) | |
2571 | { | |
953d22e8 | 2572 | memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); |
70aff66c JN |
2573 | intel_dp_set_signal_levels(intel_dp, DP); |
2574 | return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); | |
2575 | } | |
2576 | ||
2577 | static bool | |
2578 | intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, | |
0301b3ac | 2579 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
70aff66c JN |
2580 | { |
2581 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2582 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
2583 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2584 | int ret; | |
2585 | ||
2586 | intel_get_adjust_train(intel_dp, link_status); | |
2587 | intel_dp_set_signal_levels(intel_dp, DP); | |
2588 | ||
2589 | I915_WRITE(intel_dp->output_reg, *DP); | |
2590 | POSTING_READ(intel_dp->output_reg); | |
2591 | ||
2592 | ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET, | |
2593 | intel_dp->train_set, | |
2594 | intel_dp->lane_count); | |
2595 | ||
2596 | return ret == intel_dp->lane_count; | |
2597 | } | |
2598 | ||
3ab9c637 ID |
2599 | static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
2600 | { | |
2601 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2602 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
2603 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2604 | enum port port = intel_dig_port->port; | |
2605 | uint32_t val; | |
2606 | ||
2607 | if (!HAS_DDI(dev)) | |
2608 | return; | |
2609 | ||
2610 | val = I915_READ(DP_TP_CTL(port)); | |
2611 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2612 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
2613 | I915_WRITE(DP_TP_CTL(port), val); | |
2614 | ||
2615 | /* | |
2616 | * On PORT_A we can have only eDP in SST mode. There the only reason | |
2617 | * we need to set idle transmission mode is to work around a HW issue | |
2618 | * where we enable the pipe while not in idle link-training mode. | |
2619 | * In this case there is requirement to wait for a minimum number of | |
2620 | * idle patterns to be sent. | |
2621 | */ | |
2622 | if (port == PORT_A) | |
2623 | return; | |
2624 | ||
2625 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), | |
2626 | 1)) | |
2627 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); | |
2628 | } | |
2629 | ||
33a34e4e | 2630 | /* Enable corresponding port and start training pattern 1 */ |
c19b0669 | 2631 | void |
33a34e4e | 2632 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 2633 | { |
da63a9f2 | 2634 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
c19b0669 | 2635 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 KP |
2636 | int i; |
2637 | uint8_t voltage; | |
cdb0e95b | 2638 | int voltage_tries, loop_tries; |
ea5b213a | 2639 | uint32_t DP = intel_dp->DP; |
6aba5b6c | 2640 | uint8_t link_config[2]; |
a4fc5ed6 | 2641 | |
affa9354 | 2642 | if (HAS_DDI(dev)) |
c19b0669 PZ |
2643 | intel_ddi_prepare_link_retrain(encoder); |
2644 | ||
3cf2efb1 | 2645 | /* Write the link configuration data */ |
6aba5b6c JN |
2646 | link_config[0] = intel_dp->link_bw; |
2647 | link_config[1] = intel_dp->lane_count; | |
2648 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
2649 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; | |
2650 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2); | |
2651 | ||
2652 | link_config[0] = 0; | |
2653 | link_config[1] = DP_SET_ANSI_8B10B; | |
2654 | intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2); | |
a4fc5ed6 KP |
2655 | |
2656 | DP |= DP_PORT_EN; | |
1a2eb460 | 2657 | |
70aff66c JN |
2658 | /* clock recovery */ |
2659 | if (!intel_dp_reset_link_train(intel_dp, &DP, | |
2660 | DP_TRAINING_PATTERN_1 | | |
2661 | DP_LINK_SCRAMBLING_DISABLE)) { | |
2662 | DRM_ERROR("failed to enable link training\n"); | |
2663 | return; | |
2664 | } | |
2665 | ||
a4fc5ed6 | 2666 | voltage = 0xff; |
cdb0e95b KP |
2667 | voltage_tries = 0; |
2668 | loop_tries = 0; | |
a4fc5ed6 | 2669 | for (;;) { |
70aff66c | 2670 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
a4fc5ed6 | 2671 | |
a7c9655f | 2672 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
93f62dad KP |
2673 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
2674 | DRM_ERROR("failed to get link status\n"); | |
a4fc5ed6 | 2675 | break; |
93f62dad | 2676 | } |
a4fc5ed6 | 2677 | |
01916270 | 2678 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
93f62dad | 2679 | DRM_DEBUG_KMS("clock recovery OK\n"); |
3cf2efb1 CW |
2680 | break; |
2681 | } | |
2682 | ||
2683 | /* Check to see if we've tried the max voltage */ | |
2684 | for (i = 0; i < intel_dp->lane_count; i++) | |
2685 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
a4fc5ed6 | 2686 | break; |
3b4f819d | 2687 | if (i == intel_dp->lane_count) { |
b06fbda3 DV |
2688 | ++loop_tries; |
2689 | if (loop_tries == 5) { | |
3def84b3 | 2690 | DRM_ERROR("too many full retries, give up\n"); |
cdb0e95b KP |
2691 | break; |
2692 | } | |
70aff66c JN |
2693 | intel_dp_reset_link_train(intel_dp, &DP, |
2694 | DP_TRAINING_PATTERN_1 | | |
2695 | DP_LINK_SCRAMBLING_DISABLE); | |
cdb0e95b KP |
2696 | voltage_tries = 0; |
2697 | continue; | |
2698 | } | |
a4fc5ed6 | 2699 | |
3cf2efb1 | 2700 | /* Check to see if we've tried the same voltage 5 times */ |
b06fbda3 | 2701 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
24773670 | 2702 | ++voltage_tries; |
b06fbda3 | 2703 | if (voltage_tries == 5) { |
3def84b3 | 2704 | DRM_ERROR("too many voltage retries, give up\n"); |
b06fbda3 DV |
2705 | break; |
2706 | } | |
2707 | } else | |
2708 | voltage_tries = 0; | |
2709 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
a4fc5ed6 | 2710 | |
70aff66c JN |
2711 | /* Update training set as requested by target */ |
2712 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { | |
2713 | DRM_ERROR("failed to update link training\n"); | |
2714 | break; | |
2715 | } | |
a4fc5ed6 KP |
2716 | } |
2717 | ||
33a34e4e JB |
2718 | intel_dp->DP = DP; |
2719 | } | |
2720 | ||
c19b0669 | 2721 | void |
33a34e4e JB |
2722 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
2723 | { | |
33a34e4e | 2724 | bool channel_eq = false; |
37f80975 | 2725 | int tries, cr_tries; |
33a34e4e | 2726 | uint32_t DP = intel_dp->DP; |
06ea66b6 TP |
2727 | uint32_t training_pattern = DP_TRAINING_PATTERN_2; |
2728 | ||
2729 | /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ | |
2730 | if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) | |
2731 | training_pattern = DP_TRAINING_PATTERN_3; | |
33a34e4e | 2732 | |
a4fc5ed6 | 2733 | /* channel equalization */ |
70aff66c | 2734 | if (!intel_dp_set_link_train(intel_dp, &DP, |
06ea66b6 | 2735 | training_pattern | |
70aff66c JN |
2736 | DP_LINK_SCRAMBLING_DISABLE)) { |
2737 | DRM_ERROR("failed to start channel equalization\n"); | |
2738 | return; | |
2739 | } | |
2740 | ||
a4fc5ed6 | 2741 | tries = 0; |
37f80975 | 2742 | cr_tries = 0; |
a4fc5ed6 KP |
2743 | channel_eq = false; |
2744 | for (;;) { | |
70aff66c | 2745 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
e3421a18 | 2746 | |
37f80975 JB |
2747 | if (cr_tries > 5) { |
2748 | DRM_ERROR("failed to train DP, aborting\n"); | |
37f80975 JB |
2749 | break; |
2750 | } | |
2751 | ||
a7c9655f | 2752 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
70aff66c JN |
2753 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
2754 | DRM_ERROR("failed to get link status\n"); | |
a4fc5ed6 | 2755 | break; |
70aff66c | 2756 | } |
a4fc5ed6 | 2757 | |
37f80975 | 2758 | /* Make sure clock is still ok */ |
01916270 | 2759 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
37f80975 | 2760 | intel_dp_start_link_train(intel_dp); |
70aff66c | 2761 | intel_dp_set_link_train(intel_dp, &DP, |
06ea66b6 | 2762 | training_pattern | |
70aff66c | 2763 | DP_LINK_SCRAMBLING_DISABLE); |
37f80975 JB |
2764 | cr_tries++; |
2765 | continue; | |
2766 | } | |
2767 | ||
1ffdff13 | 2768 | if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
3cf2efb1 CW |
2769 | channel_eq = true; |
2770 | break; | |
2771 | } | |
a4fc5ed6 | 2772 | |
37f80975 JB |
2773 | /* Try 5 times, then try clock recovery if that fails */ |
2774 | if (tries > 5) { | |
2775 | intel_dp_link_down(intel_dp); | |
2776 | intel_dp_start_link_train(intel_dp); | |
70aff66c | 2777 | intel_dp_set_link_train(intel_dp, &DP, |
06ea66b6 | 2778 | training_pattern | |
70aff66c | 2779 | DP_LINK_SCRAMBLING_DISABLE); |
37f80975 JB |
2780 | tries = 0; |
2781 | cr_tries++; | |
2782 | continue; | |
2783 | } | |
a4fc5ed6 | 2784 | |
70aff66c JN |
2785 | /* Update training set as requested by target */ |
2786 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { | |
2787 | DRM_ERROR("failed to update link training\n"); | |
2788 | break; | |
2789 | } | |
3cf2efb1 | 2790 | ++tries; |
869184a6 | 2791 | } |
3cf2efb1 | 2792 | |
3ab9c637 ID |
2793 | intel_dp_set_idle_link_train(intel_dp); |
2794 | ||
2795 | intel_dp->DP = DP; | |
2796 | ||
d6c0d722 | 2797 | if (channel_eq) |
07f42258 | 2798 | DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); |
d6c0d722 | 2799 | |
3ab9c637 ID |
2800 | } |
2801 | ||
2802 | void intel_dp_stop_link_train(struct intel_dp *intel_dp) | |
2803 | { | |
70aff66c | 2804 | intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
3ab9c637 | 2805 | DP_TRAINING_PATTERN_DISABLE); |
a4fc5ed6 KP |
2806 | } |
2807 | ||
2808 | static void | |
ea5b213a | 2809 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 2810 | { |
da63a9f2 | 2811 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
bc7d38a4 | 2812 | enum port port = intel_dig_port->port; |
da63a9f2 | 2813 | struct drm_device *dev = intel_dig_port->base.base.dev; |
a4fc5ed6 | 2814 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab527efc DV |
2815 | struct intel_crtc *intel_crtc = |
2816 | to_intel_crtc(intel_dig_port->base.base.crtc); | |
ea5b213a | 2817 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 2818 | |
c19b0669 PZ |
2819 | /* |
2820 | * DDI code has a strict mode set sequence and we should try to respect | |
2821 | * it, otherwise we might hang the machine in many different ways. So we | |
2822 | * really should be disabling the port only on a complete crtc_disable | |
2823 | * sequence. This function is just called under two conditions on DDI | |
2824 | * code: | |
2825 | * - Link train failed while doing crtc_enable, and on this case we | |
2826 | * really should respect the mode set sequence and wait for a | |
2827 | * crtc_disable. | |
2828 | * - Someone turned the monitor off and intel_dp_check_link_status | |
2829 | * called us. We don't need to disable the whole port on this case, so | |
2830 | * when someone turns the monitor on again, | |
2831 | * intel_ddi_prepare_link_retrain will take care of redoing the link | |
2832 | * train. | |
2833 | */ | |
affa9354 | 2834 | if (HAS_DDI(dev)) |
c19b0669 PZ |
2835 | return; |
2836 | ||
0c33d8d7 | 2837 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
1b39d6f3 CW |
2838 | return; |
2839 | ||
28c97730 | 2840 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 2841 | |
bc7d38a4 | 2842 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
e3421a18 | 2843 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a | 2844 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
e3421a18 ZW |
2845 | } else { |
2846 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a | 2847 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
e3421a18 | 2848 | } |
fe255d00 | 2849 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 2850 | |
ab527efc DV |
2851 | /* We don't really know why we're doing this */ |
2852 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
5eb08b69 | 2853 | |
493a7081 | 2854 | if (HAS_PCH_IBX(dev) && |
1b39d6f3 | 2855 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
da63a9f2 | 2856 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
31acbcc4 | 2857 | |
5bddd17f EA |
2858 | /* Hardware workaround: leaving our transcoder select |
2859 | * set to transcoder B while it's off will prevent the | |
2860 | * corresponding HDMI output on transcoder A. | |
2861 | * | |
2862 | * Combine this with another hardware workaround: | |
2863 | * transcoder select bit can only be cleared while the | |
2864 | * port is enabled. | |
2865 | */ | |
2866 | DP &= ~DP_PIPEB_SELECT; | |
2867 | I915_WRITE(intel_dp->output_reg, DP); | |
2868 | ||
2869 | /* Changes to enable or select take place the vblank | |
2870 | * after being written. | |
2871 | */ | |
ff50afe9 DV |
2872 | if (WARN_ON(crtc == NULL)) { |
2873 | /* We should never try to disable a port without a crtc | |
2874 | * attached. For paranoia keep the code around for a | |
2875 | * bit. */ | |
31acbcc4 CW |
2876 | POSTING_READ(intel_dp->output_reg); |
2877 | msleep(50); | |
2878 | } else | |
ab527efc | 2879 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
5bddd17f EA |
2880 | } |
2881 | ||
832afda6 | 2882 | DP &= ~DP_AUDIO_OUTPUT_ENABLE; |
ea5b213a CW |
2883 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
2884 | POSTING_READ(intel_dp->output_reg); | |
f01eca2e | 2885 | msleep(intel_dp->panel_power_down_delay); |
a4fc5ed6 KP |
2886 | } |
2887 | ||
26d61aad KP |
2888 | static bool |
2889 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
92fd8fd1 | 2890 | { |
a031d709 RV |
2891 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
2892 | struct drm_device *dev = dig_port->base.base.dev; | |
2893 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2894 | ||
577c7a50 DL |
2895 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
2896 | ||
92fd8fd1 | 2897 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
edb39244 AJ |
2898 | sizeof(intel_dp->dpcd)) == 0) |
2899 | return false; /* aux transfer failed */ | |
92fd8fd1 | 2900 | |
577c7a50 DL |
2901 | hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), |
2902 | 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); | |
2903 | DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); | |
2904 | ||
edb39244 AJ |
2905 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
2906 | return false; /* DPCD not present */ | |
2907 | ||
2293bb5c SK |
2908 | /* Check if the panel supports PSR */ |
2909 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); | |
50003939 JN |
2910 | if (is_edp(intel_dp)) { |
2911 | intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT, | |
2912 | intel_dp->psr_dpcd, | |
2913 | sizeof(intel_dp->psr_dpcd)); | |
a031d709 RV |
2914 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
2915 | dev_priv->psr.sink_support = true; | |
50003939 | 2916 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
a031d709 | 2917 | } |
50003939 JN |
2918 | } |
2919 | ||
06ea66b6 TP |
2920 | /* Training Pattern 3 support */ |
2921 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && | |
2922 | intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { | |
2923 | intel_dp->use_tps3 = true; | |
2924 | DRM_DEBUG_KMS("Displayport TPS3 supported"); | |
2925 | } else | |
2926 | intel_dp->use_tps3 = false; | |
2927 | ||
edb39244 AJ |
2928 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
2929 | DP_DWN_STRM_PORT_PRESENT)) | |
2930 | return true; /* native DP sink */ | |
2931 | ||
2932 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
2933 | return true; /* no per-port downstream info */ | |
2934 | ||
2935 | if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0, | |
2936 | intel_dp->downstream_ports, | |
2937 | DP_MAX_DOWNSTREAM_PORTS) == 0) | |
2938 | return false; /* downstream port status fetch failed */ | |
2939 | ||
2940 | return true; | |
92fd8fd1 KP |
2941 | } |
2942 | ||
0d198328 AJ |
2943 | static void |
2944 | intel_dp_probe_oui(struct intel_dp *intel_dp) | |
2945 | { | |
2946 | u8 buf[3]; | |
2947 | ||
2948 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) | |
2949 | return; | |
2950 | ||
4be73780 | 2951 | edp_panel_vdd_on(intel_dp); |
351cfc34 | 2952 | |
0d198328 AJ |
2953 | if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) |
2954 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", | |
2955 | buf[0], buf[1], buf[2]); | |
2956 | ||
2957 | if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) | |
2958 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", | |
2959 | buf[0], buf[1], buf[2]); | |
351cfc34 | 2960 | |
4be73780 | 2961 | edp_panel_vdd_off(intel_dp, false); |
0d198328 AJ |
2962 | } |
2963 | ||
d2e216d0 RV |
2964 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
2965 | { | |
2966 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2967 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
2968 | struct intel_crtc *intel_crtc = | |
2969 | to_intel_crtc(intel_dig_port->base.base.crtc); | |
2970 | u8 buf[1]; | |
2971 | ||
2972 | if (!intel_dp_aux_native_read(intel_dp, DP_TEST_SINK_MISC, buf, 1)) | |
2973 | return -EAGAIN; | |
2974 | ||
2975 | if (!(buf[0] & DP_TEST_CRC_SUPPORTED)) | |
2976 | return -ENOTTY; | |
2977 | ||
2978 | if (!intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK, | |
2979 | DP_TEST_SINK_START)) | |
2980 | return -EAGAIN; | |
2981 | ||
2982 | /* Wait 2 vblanks to be sure we will have the correct CRC value */ | |
2983 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
2984 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
2985 | ||
2986 | if (!intel_dp_aux_native_read(intel_dp, DP_TEST_CRC_R_CR, crc, 6)) | |
2987 | return -EAGAIN; | |
2988 | ||
2989 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK, 0); | |
2990 | return 0; | |
2991 | } | |
2992 | ||
a60f0e38 JB |
2993 | static bool |
2994 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
2995 | { | |
2996 | int ret; | |
2997 | ||
2998 | ret = intel_dp_aux_native_read_retry(intel_dp, | |
2999 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
3000 | sink_irq_vector, 1); | |
3001 | if (!ret) | |
3002 | return false; | |
3003 | ||
3004 | return true; | |
3005 | } | |
3006 | ||
3007 | static void | |
3008 | intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
3009 | { | |
3010 | /* NAK by default */ | |
9324cf7f | 3011 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK); |
a60f0e38 JB |
3012 | } |
3013 | ||
a4fc5ed6 KP |
3014 | /* |
3015 | * According to DP spec | |
3016 | * 5.1.2: | |
3017 | * 1. Read DPCD | |
3018 | * 2. Configure link according to Receiver Capabilities | |
3019 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
3020 | * 4. Check link status on receipt of hot-plug interrupt | |
3021 | */ | |
3022 | ||
00c09d70 | 3023 | void |
ea5b213a | 3024 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 3025 | { |
da63a9f2 | 3026 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
a60f0e38 | 3027 | u8 sink_irq_vector; |
93f62dad | 3028 | u8 link_status[DP_LINK_STATUS_SIZE]; |
a60f0e38 | 3029 | |
da63a9f2 | 3030 | if (!intel_encoder->connectors_active) |
d2b996ac | 3031 | return; |
59cd09e1 | 3032 | |
da63a9f2 | 3033 | if (WARN_ON(!intel_encoder->base.crtc)) |
a4fc5ed6 KP |
3034 | return; |
3035 | ||
92fd8fd1 | 3036 | /* Try to read receiver status if the link appears to be up */ |
93f62dad | 3037 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
a4fc5ed6 KP |
3038 | return; |
3039 | } | |
3040 | ||
92fd8fd1 | 3041 | /* Now read the DPCD to see if it's actually running */ |
26d61aad | 3042 | if (!intel_dp_get_dpcd(intel_dp)) { |
59cd09e1 JB |
3043 | return; |
3044 | } | |
3045 | ||
a60f0e38 JB |
3046 | /* Try to read the source of the interrupt */ |
3047 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
3048 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { | |
3049 | /* Clear interrupt source */ | |
3050 | intel_dp_aux_native_write_1(intel_dp, | |
3051 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
3052 | sink_irq_vector); | |
3053 | ||
3054 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
3055 | intel_dp_handle_test_request(intel_dp); | |
3056 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
3057 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
3058 | } | |
3059 | ||
1ffdff13 | 3060 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
92fd8fd1 | 3061 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
da63a9f2 | 3062 | drm_get_encoder_name(&intel_encoder->base)); |
33a34e4e JB |
3063 | intel_dp_start_link_train(intel_dp); |
3064 | intel_dp_complete_link_train(intel_dp); | |
3ab9c637 | 3065 | intel_dp_stop_link_train(intel_dp); |
33a34e4e | 3066 | } |
a4fc5ed6 | 3067 | } |
a4fc5ed6 | 3068 | |
caf9ab24 | 3069 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 3070 | static enum drm_connector_status |
26d61aad | 3071 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 3072 | { |
caf9ab24 | 3073 | uint8_t *dpcd = intel_dp->dpcd; |
caf9ab24 AJ |
3074 | uint8_t type; |
3075 | ||
3076 | if (!intel_dp_get_dpcd(intel_dp)) | |
3077 | return connector_status_disconnected; | |
3078 | ||
3079 | /* if there's no downstream port, we're done */ | |
3080 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) | |
26d61aad | 3081 | return connector_status_connected; |
caf9ab24 AJ |
3082 | |
3083 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
c9ff160b JN |
3084 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
3085 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | |
23235177 | 3086 | uint8_t reg; |
caf9ab24 | 3087 | if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT, |
23235177 | 3088 | ®, 1)) |
caf9ab24 | 3089 | return connector_status_unknown; |
23235177 AJ |
3090 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
3091 | : connector_status_disconnected; | |
caf9ab24 AJ |
3092 | } |
3093 | ||
3094 | /* If no HPD, poke DDC gently */ | |
3095 | if (drm_probe_ddc(&intel_dp->adapter)) | |
26d61aad | 3096 | return connector_status_connected; |
caf9ab24 AJ |
3097 | |
3098 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
3099 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
3100 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
3101 | if (type == DP_DS_PORT_TYPE_VGA || | |
3102 | type == DP_DS_PORT_TYPE_NON_EDID) | |
3103 | return connector_status_unknown; | |
3104 | } else { | |
3105 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
3106 | DP_DWN_STRM_PORT_TYPE_MASK; | |
3107 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
3108 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
3109 | return connector_status_unknown; | |
3110 | } | |
caf9ab24 AJ |
3111 | |
3112 | /* Anything else is out of spec, warn and ignore */ | |
3113 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); | |
26d61aad | 3114 | return connector_status_disconnected; |
71ba9000 AJ |
3115 | } |
3116 | ||
5eb08b69 | 3117 | static enum drm_connector_status |
a9756bb5 | 3118 | ironlake_dp_detect(struct intel_dp *intel_dp) |
5eb08b69 | 3119 | { |
30add22d | 3120 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1b469639 DL |
3121 | struct drm_i915_private *dev_priv = dev->dev_private; |
3122 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
5eb08b69 ZW |
3123 | enum drm_connector_status status; |
3124 | ||
fe16d949 CW |
3125 | /* Can't disconnect eDP, but you can close the lid... */ |
3126 | if (is_edp(intel_dp)) { | |
30add22d | 3127 | status = intel_panel_detect(dev); |
fe16d949 CW |
3128 | if (status == connector_status_unknown) |
3129 | status = connector_status_connected; | |
3130 | return status; | |
3131 | } | |
01cb9ea6 | 3132 | |
1b469639 DL |
3133 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
3134 | return connector_status_disconnected; | |
3135 | ||
26d61aad | 3136 | return intel_dp_detect_dpcd(intel_dp); |
5eb08b69 ZW |
3137 | } |
3138 | ||
a4fc5ed6 | 3139 | static enum drm_connector_status |
a9756bb5 | 3140 | g4x_dp_detect(struct intel_dp *intel_dp) |
a4fc5ed6 | 3141 | { |
30add22d | 3142 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
a4fc5ed6 | 3143 | struct drm_i915_private *dev_priv = dev->dev_private; |
34f2be46 | 3144 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
10f76a38 | 3145 | uint32_t bit; |
5eb08b69 | 3146 | |
35aad75f JB |
3147 | /* Can't disconnect eDP, but you can close the lid... */ |
3148 | if (is_edp(intel_dp)) { | |
3149 | enum drm_connector_status status; | |
3150 | ||
3151 | status = intel_panel_detect(dev); | |
3152 | if (status == connector_status_unknown) | |
3153 | status = connector_status_connected; | |
3154 | return status; | |
3155 | } | |
3156 | ||
232a6ee9 TP |
3157 | if (IS_VALLEYVIEW(dev)) { |
3158 | switch (intel_dig_port->port) { | |
3159 | case PORT_B: | |
3160 | bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; | |
3161 | break; | |
3162 | case PORT_C: | |
3163 | bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; | |
3164 | break; | |
3165 | case PORT_D: | |
3166 | bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; | |
3167 | break; | |
3168 | default: | |
3169 | return connector_status_unknown; | |
3170 | } | |
3171 | } else { | |
3172 | switch (intel_dig_port->port) { | |
3173 | case PORT_B: | |
3174 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; | |
3175 | break; | |
3176 | case PORT_C: | |
3177 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; | |
3178 | break; | |
3179 | case PORT_D: | |
3180 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; | |
3181 | break; | |
3182 | default: | |
3183 | return connector_status_unknown; | |
3184 | } | |
a4fc5ed6 KP |
3185 | } |
3186 | ||
10f76a38 | 3187 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
a4fc5ed6 KP |
3188 | return connector_status_disconnected; |
3189 | ||
26d61aad | 3190 | return intel_dp_detect_dpcd(intel_dp); |
a9756bb5 ZW |
3191 | } |
3192 | ||
8c241fef KP |
3193 | static struct edid * |
3194 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) | |
3195 | { | |
9cd300e0 | 3196 | struct intel_connector *intel_connector = to_intel_connector(connector); |
d6f24d0f | 3197 | |
9cd300e0 JN |
3198 | /* use cached edid if we have one */ |
3199 | if (intel_connector->edid) { | |
9cd300e0 JN |
3200 | /* invalid edid */ |
3201 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
3202 | return NULL; |
3203 | ||
55e9edeb | 3204 | return drm_edid_duplicate(intel_connector->edid); |
d6f24d0f | 3205 | } |
8c241fef | 3206 | |
9cd300e0 | 3207 | return drm_get_edid(connector, adapter); |
8c241fef KP |
3208 | } |
3209 | ||
3210 | static int | |
3211 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) | |
3212 | { | |
9cd300e0 | 3213 | struct intel_connector *intel_connector = to_intel_connector(connector); |
8c241fef | 3214 | |
9cd300e0 JN |
3215 | /* use cached edid if we have one */ |
3216 | if (intel_connector->edid) { | |
3217 | /* invalid edid */ | |
3218 | if (IS_ERR(intel_connector->edid)) | |
3219 | return 0; | |
3220 | ||
3221 | return intel_connector_update_modes(connector, | |
3222 | intel_connector->edid); | |
d6f24d0f JB |
3223 | } |
3224 | ||
9cd300e0 | 3225 | return intel_ddc_get_modes(connector, adapter); |
8c241fef KP |
3226 | } |
3227 | ||
a9756bb5 ZW |
3228 | static enum drm_connector_status |
3229 | intel_dp_detect(struct drm_connector *connector, bool force) | |
3230 | { | |
3231 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
d63885da PZ |
3232 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3233 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fa90ecef | 3234 | struct drm_device *dev = connector->dev; |
c8c8fb33 | 3235 | struct drm_i915_private *dev_priv = dev->dev_private; |
a9756bb5 | 3236 | enum drm_connector_status status; |
671dedd2 | 3237 | enum intel_display_power_domain power_domain; |
a9756bb5 ZW |
3238 | struct edid *edid = NULL; |
3239 | ||
c8c8fb33 PZ |
3240 | intel_runtime_pm_get(dev_priv); |
3241 | ||
671dedd2 ID |
3242 | power_domain = intel_display_port_power_domain(intel_encoder); |
3243 | intel_display_power_get(dev_priv, power_domain); | |
3244 | ||
164c8598 CW |
3245 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
3246 | connector->base.id, drm_get_connector_name(connector)); | |
3247 | ||
a9756bb5 ZW |
3248 | intel_dp->has_audio = false; |
3249 | ||
3250 | if (HAS_PCH_SPLIT(dev)) | |
3251 | status = ironlake_dp_detect(intel_dp); | |
3252 | else | |
3253 | status = g4x_dp_detect(intel_dp); | |
1b9be9d0 | 3254 | |
a9756bb5 | 3255 | if (status != connector_status_connected) |
c8c8fb33 | 3256 | goto out; |
a9756bb5 | 3257 | |
0d198328 AJ |
3258 | intel_dp_probe_oui(intel_dp); |
3259 | ||
c3e5f67b DV |
3260 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
3261 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); | |
f684960e | 3262 | } else { |
8c241fef | 3263 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
f684960e CW |
3264 | if (edid) { |
3265 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
f684960e CW |
3266 | kfree(edid); |
3267 | } | |
a9756bb5 ZW |
3268 | } |
3269 | ||
d63885da PZ |
3270 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
3271 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
c8c8fb33 PZ |
3272 | status = connector_status_connected; |
3273 | ||
3274 | out: | |
671dedd2 ID |
3275 | intel_display_power_put(dev_priv, power_domain); |
3276 | ||
c8c8fb33 | 3277 | intel_runtime_pm_put(dev_priv); |
671dedd2 | 3278 | |
c8c8fb33 | 3279 | return status; |
a4fc5ed6 KP |
3280 | } |
3281 | ||
3282 | static int intel_dp_get_modes(struct drm_connector *connector) | |
3283 | { | |
df0e9248 | 3284 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
671dedd2 ID |
3285 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3286 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
dd06f90e | 3287 | struct intel_connector *intel_connector = to_intel_connector(connector); |
fa90ecef | 3288 | struct drm_device *dev = connector->dev; |
671dedd2 ID |
3289 | struct drm_i915_private *dev_priv = dev->dev_private; |
3290 | enum intel_display_power_domain power_domain; | |
32f9d658 | 3291 | int ret; |
a4fc5ed6 KP |
3292 | |
3293 | /* We should parse the EDID data and find out if it has an audio sink | |
3294 | */ | |
3295 | ||
671dedd2 ID |
3296 | power_domain = intel_display_port_power_domain(intel_encoder); |
3297 | intel_display_power_get(dev_priv, power_domain); | |
3298 | ||
8c241fef | 3299 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
671dedd2 | 3300 | intel_display_power_put(dev_priv, power_domain); |
f8779fda | 3301 | if (ret) |
32f9d658 ZW |
3302 | return ret; |
3303 | ||
f8779fda | 3304 | /* if eDP has no EDID, fall back to fixed mode */ |
dd06f90e | 3305 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
f8779fda | 3306 | struct drm_display_mode *mode; |
dd06f90e JN |
3307 | mode = drm_mode_duplicate(dev, |
3308 | intel_connector->panel.fixed_mode); | |
f8779fda | 3309 | if (mode) { |
32f9d658 ZW |
3310 | drm_mode_probed_add(connector, mode); |
3311 | return 1; | |
3312 | } | |
3313 | } | |
3314 | return 0; | |
a4fc5ed6 KP |
3315 | } |
3316 | ||
1aad7ac0 CW |
3317 | static bool |
3318 | intel_dp_detect_audio(struct drm_connector *connector) | |
3319 | { | |
3320 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
671dedd2 ID |
3321 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3322 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
3323 | struct drm_device *dev = connector->dev; | |
3324 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3325 | enum intel_display_power_domain power_domain; | |
1aad7ac0 CW |
3326 | struct edid *edid; |
3327 | bool has_audio = false; | |
3328 | ||
671dedd2 ID |
3329 | power_domain = intel_display_port_power_domain(intel_encoder); |
3330 | intel_display_power_get(dev_priv, power_domain); | |
3331 | ||
8c241fef | 3332 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
1aad7ac0 CW |
3333 | if (edid) { |
3334 | has_audio = drm_detect_monitor_audio(edid); | |
1aad7ac0 CW |
3335 | kfree(edid); |
3336 | } | |
3337 | ||
671dedd2 ID |
3338 | intel_display_power_put(dev_priv, power_domain); |
3339 | ||
1aad7ac0 CW |
3340 | return has_audio; |
3341 | } | |
3342 | ||
f684960e CW |
3343 | static int |
3344 | intel_dp_set_property(struct drm_connector *connector, | |
3345 | struct drm_property *property, | |
3346 | uint64_t val) | |
3347 | { | |
e953fd7b | 3348 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
53b41837 | 3349 | struct intel_connector *intel_connector = to_intel_connector(connector); |
da63a9f2 PZ |
3350 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
3351 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
f684960e CW |
3352 | int ret; |
3353 | ||
662595df | 3354 | ret = drm_object_property_set_value(&connector->base, property, val); |
f684960e CW |
3355 | if (ret) |
3356 | return ret; | |
3357 | ||
3f43c48d | 3358 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
3359 | int i = val; |
3360 | bool has_audio; | |
3361 | ||
3362 | if (i == intel_dp->force_audio) | |
f684960e CW |
3363 | return 0; |
3364 | ||
1aad7ac0 | 3365 | intel_dp->force_audio = i; |
f684960e | 3366 | |
c3e5f67b | 3367 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
3368 | has_audio = intel_dp_detect_audio(connector); |
3369 | else | |
c3e5f67b | 3370 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 CW |
3371 | |
3372 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
3373 | return 0; |
3374 | ||
1aad7ac0 | 3375 | intel_dp->has_audio = has_audio; |
f684960e CW |
3376 | goto done; |
3377 | } | |
3378 | ||
e953fd7b | 3379 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
3380 | bool old_auto = intel_dp->color_range_auto; |
3381 | uint32_t old_range = intel_dp->color_range; | |
3382 | ||
55bc60db VS |
3383 | switch (val) { |
3384 | case INTEL_BROADCAST_RGB_AUTO: | |
3385 | intel_dp->color_range_auto = true; | |
3386 | break; | |
3387 | case INTEL_BROADCAST_RGB_FULL: | |
3388 | intel_dp->color_range_auto = false; | |
3389 | intel_dp->color_range = 0; | |
3390 | break; | |
3391 | case INTEL_BROADCAST_RGB_LIMITED: | |
3392 | intel_dp->color_range_auto = false; | |
3393 | intel_dp->color_range = DP_COLOR_RANGE_16_235; | |
3394 | break; | |
3395 | default: | |
3396 | return -EINVAL; | |
3397 | } | |
ae4edb80 DV |
3398 | |
3399 | if (old_auto == intel_dp->color_range_auto && | |
3400 | old_range == intel_dp->color_range) | |
3401 | return 0; | |
3402 | ||
e953fd7b CW |
3403 | goto done; |
3404 | } | |
3405 | ||
53b41837 YN |
3406 | if (is_edp(intel_dp) && |
3407 | property == connector->dev->mode_config.scaling_mode_property) { | |
3408 | if (val == DRM_MODE_SCALE_NONE) { | |
3409 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
3410 | return -EINVAL; | |
3411 | } | |
3412 | ||
3413 | if (intel_connector->panel.fitting_mode == val) { | |
3414 | /* the eDP scaling property is not changed */ | |
3415 | return 0; | |
3416 | } | |
3417 | intel_connector->panel.fitting_mode = val; | |
3418 | ||
3419 | goto done; | |
3420 | } | |
3421 | ||
f684960e CW |
3422 | return -EINVAL; |
3423 | ||
3424 | done: | |
c0c36b94 CW |
3425 | if (intel_encoder->base.crtc) |
3426 | intel_crtc_restore_mode(intel_encoder->base.crtc); | |
f684960e CW |
3427 | |
3428 | return 0; | |
3429 | } | |
3430 | ||
a4fc5ed6 | 3431 | static void |
73845adf | 3432 | intel_dp_connector_destroy(struct drm_connector *connector) |
a4fc5ed6 | 3433 | { |
1d508706 | 3434 | struct intel_connector *intel_connector = to_intel_connector(connector); |
aaa6fd2a | 3435 | |
9cd300e0 JN |
3436 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
3437 | kfree(intel_connector->edid); | |
3438 | ||
acd8db10 PZ |
3439 | /* Can't call is_edp() since the encoder may have been destroyed |
3440 | * already. */ | |
3441 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
1d508706 | 3442 | intel_panel_fini(&intel_connector->panel); |
aaa6fd2a | 3443 | |
a4fc5ed6 | 3444 | drm_connector_cleanup(connector); |
55f78c43 | 3445 | kfree(connector); |
a4fc5ed6 KP |
3446 | } |
3447 | ||
00c09d70 | 3448 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
24d05927 | 3449 | { |
da63a9f2 PZ |
3450 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
3451 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
bd173813 | 3452 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
24d05927 DV |
3453 | |
3454 | i2c_del_adapter(&intel_dp->adapter); | |
3455 | drm_encoder_cleanup(encoder); | |
bd943159 KP |
3456 | if (is_edp(intel_dp)) { |
3457 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
bd173813 | 3458 | mutex_lock(&dev->mode_config.mutex); |
4be73780 | 3459 | edp_panel_vdd_off_sync(intel_dp); |
bd173813 | 3460 | mutex_unlock(&dev->mode_config.mutex); |
bd943159 | 3461 | } |
da63a9f2 | 3462 | kfree(intel_dig_port); |
24d05927 DV |
3463 | } |
3464 | ||
a4fc5ed6 | 3465 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
2bd2ad64 | 3466 | .dpms = intel_connector_dpms, |
a4fc5ed6 KP |
3467 | .detect = intel_dp_detect, |
3468 | .fill_modes = drm_helper_probe_single_connector_modes, | |
f684960e | 3469 | .set_property = intel_dp_set_property, |
73845adf | 3470 | .destroy = intel_dp_connector_destroy, |
a4fc5ed6 KP |
3471 | }; |
3472 | ||
3473 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
3474 | .get_modes = intel_dp_get_modes, | |
3475 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 3476 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
3477 | }; |
3478 | ||
a4fc5ed6 | 3479 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
24d05927 | 3480 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
3481 | }; |
3482 | ||
995b6762 | 3483 | static void |
21d40d37 | 3484 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 3485 | { |
fa90ecef | 3486 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
c8110e52 | 3487 | |
885a5014 | 3488 | intel_dp_check_link_status(intel_dp); |
c8110e52 | 3489 | } |
6207937d | 3490 | |
e3421a18 ZW |
3491 | /* Return which DP Port should be selected for Transcoder DP control */ |
3492 | int | |
0206e353 | 3493 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
e3421a18 ZW |
3494 | { |
3495 | struct drm_device *dev = crtc->dev; | |
fa90ecef PZ |
3496 | struct intel_encoder *intel_encoder; |
3497 | struct intel_dp *intel_dp; | |
e3421a18 | 3498 | |
fa90ecef PZ |
3499 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
3500 | intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
e3421a18 | 3501 | |
fa90ecef PZ |
3502 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
3503 | intel_encoder->type == INTEL_OUTPUT_EDP) | |
ea5b213a | 3504 | return intel_dp->output_reg; |
e3421a18 | 3505 | } |
ea5b213a | 3506 | |
e3421a18 ZW |
3507 | return -1; |
3508 | } | |
3509 | ||
36e83a18 | 3510 | /* check the VBT to see whether the eDP is on DP-D port */ |
5d8a7752 | 3511 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
36e83a18 ZY |
3512 | { |
3513 | struct drm_i915_private *dev_priv = dev->dev_private; | |
768f69c9 | 3514 | union child_device_config *p_child; |
36e83a18 | 3515 | int i; |
5d8a7752 VS |
3516 | static const short port_mapping[] = { |
3517 | [PORT_B] = PORT_IDPB, | |
3518 | [PORT_C] = PORT_IDPC, | |
3519 | [PORT_D] = PORT_IDPD, | |
3520 | }; | |
36e83a18 | 3521 | |
3b32a35b VS |
3522 | if (port == PORT_A) |
3523 | return true; | |
3524 | ||
41aa3448 | 3525 | if (!dev_priv->vbt.child_dev_num) |
36e83a18 ZY |
3526 | return false; |
3527 | ||
41aa3448 RV |
3528 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
3529 | p_child = dev_priv->vbt.child_dev + i; | |
36e83a18 | 3530 | |
5d8a7752 | 3531 | if (p_child->common.dvo_port == port_mapping[port] && |
f02586df VS |
3532 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == |
3533 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) | |
36e83a18 ZY |
3534 | return true; |
3535 | } | |
3536 | return false; | |
3537 | } | |
3538 | ||
f684960e CW |
3539 | static void |
3540 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) | |
3541 | { | |
53b41837 YN |
3542 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3543 | ||
3f43c48d | 3544 | intel_attach_force_audio_property(connector); |
e953fd7b | 3545 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 3546 | intel_dp->color_range_auto = true; |
53b41837 YN |
3547 | |
3548 | if (is_edp(intel_dp)) { | |
3549 | drm_mode_create_scaling_mode_property(connector->dev); | |
6de6d846 RC |
3550 | drm_object_attach_property( |
3551 | &connector->base, | |
53b41837 | 3552 | connector->dev->mode_config.scaling_mode_property, |
8e740cd1 YN |
3553 | DRM_MODE_SCALE_ASPECT); |
3554 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
53b41837 | 3555 | } |
f684960e CW |
3556 | } |
3557 | ||
dada1a9f ID |
3558 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
3559 | { | |
3560 | intel_dp->last_power_cycle = jiffies; | |
3561 | intel_dp->last_power_on = jiffies; | |
3562 | intel_dp->last_backlight_off = jiffies; | |
3563 | } | |
3564 | ||
67a54566 DV |
3565 | static void |
3566 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
f30d26e4 JN |
3567 | struct intel_dp *intel_dp, |
3568 | struct edp_power_seq *out) | |
67a54566 DV |
3569 | { |
3570 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3571 | struct edp_power_seq cur, vbt, spec, final; | |
3572 | u32 pp_on, pp_off, pp_div, pp; | |
bf13e81b | 3573 | int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
453c5420 JB |
3574 | |
3575 | if (HAS_PCH_SPLIT(dev)) { | |
bf13e81b | 3576 | pp_ctrl_reg = PCH_PP_CONTROL; |
453c5420 JB |
3577 | pp_on_reg = PCH_PP_ON_DELAYS; |
3578 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
3579 | pp_div_reg = PCH_PP_DIVISOR; | |
3580 | } else { | |
bf13e81b JN |
3581 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
3582 | ||
3583 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); | |
3584 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); | |
3585 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); | |
3586 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
453c5420 | 3587 | } |
67a54566 DV |
3588 | |
3589 | /* Workaround: Need to write PP_CONTROL with the unlock key as | |
3590 | * the very first thing. */ | |
453c5420 | 3591 | pp = ironlake_get_pp_control(intel_dp); |
bf13e81b | 3592 | I915_WRITE(pp_ctrl_reg, pp); |
67a54566 | 3593 | |
453c5420 JB |
3594 | pp_on = I915_READ(pp_on_reg); |
3595 | pp_off = I915_READ(pp_off_reg); | |
3596 | pp_div = I915_READ(pp_div_reg); | |
67a54566 DV |
3597 | |
3598 | /* Pull timing values out of registers */ | |
3599 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> | |
3600 | PANEL_POWER_UP_DELAY_SHIFT; | |
3601 | ||
3602 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> | |
3603 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
3604 | ||
3605 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> | |
3606 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
3607 | ||
3608 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> | |
3609 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
3610 | ||
3611 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
3612 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; | |
3613 | ||
3614 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
3615 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); | |
3616 | ||
41aa3448 | 3617 | vbt = dev_priv->vbt.edp_pps; |
67a54566 DV |
3618 | |
3619 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
3620 | * our hw here, which are all in 100usec. */ | |
3621 | spec.t1_t3 = 210 * 10; | |
3622 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
3623 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
3624 | spec.t10 = 500 * 10; | |
3625 | /* This one is special and actually in units of 100ms, but zero | |
3626 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
3627 | * table multiplies it with 1000 to make it in units of 100usec, | |
3628 | * too. */ | |
3629 | spec.t11_t12 = (510 + 100) * 10; | |
3630 | ||
3631 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
3632 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); | |
3633 | ||
3634 | /* Use the max of the register settings and vbt. If both are | |
3635 | * unset, fall back to the spec limits. */ | |
3636 | #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ | |
3637 | spec.field : \ | |
3638 | max(cur.field, vbt.field)) | |
3639 | assign_final(t1_t3); | |
3640 | assign_final(t8); | |
3641 | assign_final(t9); | |
3642 | assign_final(t10); | |
3643 | assign_final(t11_t12); | |
3644 | #undef assign_final | |
3645 | ||
3646 | #define get_delay(field) (DIV_ROUND_UP(final.field, 10)) | |
3647 | intel_dp->panel_power_up_delay = get_delay(t1_t3); | |
3648 | intel_dp->backlight_on_delay = get_delay(t8); | |
3649 | intel_dp->backlight_off_delay = get_delay(t9); | |
3650 | intel_dp->panel_power_down_delay = get_delay(t10); | |
3651 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
3652 | #undef get_delay | |
3653 | ||
f30d26e4 JN |
3654 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
3655 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
3656 | intel_dp->panel_power_cycle_delay); | |
3657 | ||
3658 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
3659 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
3660 | ||
3661 | if (out) | |
3662 | *out = final; | |
3663 | } | |
3664 | ||
3665 | static void | |
3666 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
3667 | struct intel_dp *intel_dp, | |
3668 | struct edp_power_seq *seq) | |
3669 | { | |
3670 | struct drm_i915_private *dev_priv = dev->dev_private; | |
453c5420 JB |
3671 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
3672 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); | |
3673 | int pp_on_reg, pp_off_reg, pp_div_reg; | |
3674 | ||
3675 | if (HAS_PCH_SPLIT(dev)) { | |
3676 | pp_on_reg = PCH_PP_ON_DELAYS; | |
3677 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
3678 | pp_div_reg = PCH_PP_DIVISOR; | |
3679 | } else { | |
bf13e81b JN |
3680 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
3681 | ||
3682 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); | |
3683 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); | |
3684 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
453c5420 JB |
3685 | } |
3686 | ||
b2f19d1a PZ |
3687 | /* |
3688 | * And finally store the new values in the power sequencer. The | |
3689 | * backlight delays are set to 1 because we do manual waits on them. For | |
3690 | * T8, even BSpec recommends doing it. For T9, if we don't do this, | |
3691 | * we'll end up waiting for the backlight off delay twice: once when we | |
3692 | * do the manual sleep, and once when we disable the panel and wait for | |
3693 | * the PP_STATUS bit to become zero. | |
3694 | */ | |
f30d26e4 | 3695 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
b2f19d1a PZ |
3696 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
3697 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | | |
f30d26e4 | 3698 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
67a54566 DV |
3699 | /* Compute the divisor for the pp clock, simply match the Bspec |
3700 | * formula. */ | |
453c5420 | 3701 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
f30d26e4 | 3702 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
67a54566 DV |
3703 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
3704 | ||
3705 | /* Haswell doesn't have any port selection bits for the panel | |
3706 | * power sequencer any more. */ | |
bc7d38a4 | 3707 | if (IS_VALLEYVIEW(dev)) { |
bf13e81b JN |
3708 | if (dp_to_dig_port(intel_dp)->port == PORT_B) |
3709 | port_sel = PANEL_PORT_SELECT_DPB_VLV; | |
3710 | else | |
3711 | port_sel = PANEL_PORT_SELECT_DPC_VLV; | |
bc7d38a4 ID |
3712 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
3713 | if (dp_to_dig_port(intel_dp)->port == PORT_A) | |
a24c144c | 3714 | port_sel = PANEL_PORT_SELECT_DPA; |
67a54566 | 3715 | else |
a24c144c | 3716 | port_sel = PANEL_PORT_SELECT_DPD; |
67a54566 DV |
3717 | } |
3718 | ||
453c5420 JB |
3719 | pp_on |= port_sel; |
3720 | ||
3721 | I915_WRITE(pp_on_reg, pp_on); | |
3722 | I915_WRITE(pp_off_reg, pp_off); | |
3723 | I915_WRITE(pp_div_reg, pp_div); | |
67a54566 | 3724 | |
67a54566 | 3725 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
453c5420 JB |
3726 | I915_READ(pp_on_reg), |
3727 | I915_READ(pp_off_reg), | |
3728 | I915_READ(pp_div_reg)); | |
f684960e CW |
3729 | } |
3730 | ||
ed92f0b2 | 3731 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
0095e6dc PZ |
3732 | struct intel_connector *intel_connector, |
3733 | struct edp_power_seq *power_seq) | |
ed92f0b2 PZ |
3734 | { |
3735 | struct drm_connector *connector = &intel_connector->base; | |
3736 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3737 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
3738 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3739 | struct drm_display_mode *fixed_mode = NULL; | |
ed92f0b2 PZ |
3740 | bool has_dpcd; |
3741 | struct drm_display_mode *scan; | |
3742 | struct edid *edid; | |
3743 | ||
3744 | if (!is_edp(intel_dp)) | |
3745 | return true; | |
3746 | ||
ed92f0b2 | 3747 | /* Cache DPCD and EDID for edp. */ |
4be73780 | 3748 | edp_panel_vdd_on(intel_dp); |
ed92f0b2 | 3749 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
4be73780 | 3750 | edp_panel_vdd_off(intel_dp, false); |
ed92f0b2 PZ |
3751 | |
3752 | if (has_dpcd) { | |
3753 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) | |
3754 | dev_priv->no_aux_handshake = | |
3755 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
3756 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; | |
3757 | } else { | |
3758 | /* if this fails, presume the device is a ghost */ | |
3759 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); | |
ed92f0b2 PZ |
3760 | return false; |
3761 | } | |
3762 | ||
3763 | /* We now know it's not a ghost, init power sequence regs. */ | |
0095e6dc | 3764 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); |
ed92f0b2 | 3765 | |
060c8778 | 3766 | mutex_lock(&dev->mode_config.mutex); |
ed92f0b2 PZ |
3767 | edid = drm_get_edid(connector, &intel_dp->adapter); |
3768 | if (edid) { | |
3769 | if (drm_add_edid_modes(connector, edid)) { | |
3770 | drm_mode_connector_update_edid_property(connector, | |
3771 | edid); | |
3772 | drm_edid_to_eld(connector, edid); | |
3773 | } else { | |
3774 | kfree(edid); | |
3775 | edid = ERR_PTR(-EINVAL); | |
3776 | } | |
3777 | } else { | |
3778 | edid = ERR_PTR(-ENOENT); | |
3779 | } | |
3780 | intel_connector->edid = edid; | |
3781 | ||
3782 | /* prefer fixed mode from EDID if available */ | |
3783 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
3784 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
3785 | fixed_mode = drm_mode_duplicate(dev, scan); | |
3786 | break; | |
3787 | } | |
3788 | } | |
3789 | ||
3790 | /* fallback to VBT if available for eDP */ | |
3791 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { | |
3792 | fixed_mode = drm_mode_duplicate(dev, | |
3793 | dev_priv->vbt.lfp_lvds_vbt_mode); | |
3794 | if (fixed_mode) | |
3795 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
3796 | } | |
060c8778 | 3797 | mutex_unlock(&dev->mode_config.mutex); |
ed92f0b2 | 3798 | |
4b6ed685 | 3799 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
ed92f0b2 PZ |
3800 | intel_panel_setup_backlight(connector); |
3801 | ||
3802 | return true; | |
3803 | } | |
3804 | ||
16c25533 | 3805 | bool |
f0fec3f2 PZ |
3806 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
3807 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 3808 | { |
f0fec3f2 PZ |
3809 | struct drm_connector *connector = &intel_connector->base; |
3810 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
3811 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
3812 | struct drm_device *dev = intel_encoder->base.dev; | |
a4fc5ed6 | 3813 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 3814 | enum port port = intel_dig_port->port; |
0095e6dc | 3815 | struct edp_power_seq power_seq = { 0 }; |
5eb08b69 | 3816 | const char *name = NULL; |
b2a14755 | 3817 | int type, error; |
a4fc5ed6 | 3818 | |
ec5b01dd DL |
3819 | /* intel_dp vfuncs */ |
3820 | if (IS_VALLEYVIEW(dev)) | |
3821 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; | |
3822 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
3823 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; | |
3824 | else if (HAS_PCH_SPLIT(dev)) | |
3825 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; | |
3826 | else | |
3827 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; | |
3828 | ||
153b1100 DL |
3829 | intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; |
3830 | ||
0767935e DV |
3831 | /* Preserve the current hw state. */ |
3832 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
dd06f90e | 3833 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 3834 | |
3b32a35b | 3835 | if (intel_dp_is_edp(dev, port)) |
b329530c | 3836 | type = DRM_MODE_CONNECTOR_eDP; |
3b32a35b VS |
3837 | else |
3838 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
b329530c | 3839 | |
f7d24902 ID |
3840 | /* |
3841 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
3842 | * for DP the encoder type can be set by the caller to | |
3843 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
3844 | */ | |
3845 | if (type == DRM_MODE_CONNECTOR_eDP) | |
3846 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
3847 | ||
e7281eab ID |
3848 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
3849 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
3850 | port_name(port)); | |
3851 | ||
b329530c | 3852 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
3853 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
3854 | ||
a4fc5ed6 KP |
3855 | connector->interlace_allowed = true; |
3856 | connector->doublescan_allowed = 0; | |
3857 | ||
f0fec3f2 | 3858 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
4be73780 | 3859 | edp_panel_vdd_work); |
a4fc5ed6 | 3860 | |
df0e9248 | 3861 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 KP |
3862 | drm_sysfs_connector_add(connector); |
3863 | ||
affa9354 | 3864 | if (HAS_DDI(dev)) |
bcbc889b PZ |
3865 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
3866 | else | |
3867 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
80f65de3 | 3868 | intel_connector->unregister = intel_dp_connector_unregister; |
bcbc889b | 3869 | |
9ed35ab1 PZ |
3870 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
3871 | if (HAS_DDI(dev)) { | |
3872 | switch (intel_dig_port->port) { | |
3873 | case PORT_A: | |
3874 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; | |
3875 | break; | |
3876 | case PORT_B: | |
3877 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; | |
3878 | break; | |
3879 | case PORT_C: | |
3880 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; | |
3881 | break; | |
3882 | case PORT_D: | |
3883 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; | |
3884 | break; | |
3885 | default: | |
3886 | BUG(); | |
3887 | } | |
3888 | } | |
e8cb4558 | 3889 | |
a4fc5ed6 | 3890 | /* Set up the DDC bus. */ |
ab9d7c30 PZ |
3891 | switch (port) { |
3892 | case PORT_A: | |
1d843f9d | 3893 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
3894 | name = "DPDDC-A"; |
3895 | break; | |
3896 | case PORT_B: | |
1d843f9d | 3897 | intel_encoder->hpd_pin = HPD_PORT_B; |
ab9d7c30 PZ |
3898 | name = "DPDDC-B"; |
3899 | break; | |
3900 | case PORT_C: | |
1d843f9d | 3901 | intel_encoder->hpd_pin = HPD_PORT_C; |
ab9d7c30 PZ |
3902 | name = "DPDDC-C"; |
3903 | break; | |
3904 | case PORT_D: | |
1d843f9d | 3905 | intel_encoder->hpd_pin = HPD_PORT_D; |
ab9d7c30 PZ |
3906 | name = "DPDDC-D"; |
3907 | break; | |
3908 | default: | |
ad1c0b19 | 3909 | BUG(); |
5eb08b69 ZW |
3910 | } |
3911 | ||
dada1a9f ID |
3912 | if (is_edp(intel_dp)) { |
3913 | intel_dp_init_panel_power_timestamps(intel_dp); | |
0095e6dc | 3914 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
dada1a9f | 3915 | } |
0095e6dc | 3916 | |
b2a14755 PZ |
3917 | error = intel_dp_i2c_init(intel_dp, intel_connector, name); |
3918 | WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n", | |
3919 | error, port_name(port)); | |
c1f05264 | 3920 | |
2b28bb1b RV |
3921 | intel_dp->psr_setup_done = false; |
3922 | ||
0095e6dc | 3923 | if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { |
15b1d171 PZ |
3924 | i2c_del_adapter(&intel_dp->adapter); |
3925 | if (is_edp(intel_dp)) { | |
3926 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
3927 | mutex_lock(&dev->mode_config.mutex); | |
4be73780 | 3928 | edp_panel_vdd_off_sync(intel_dp); |
15b1d171 PZ |
3929 | mutex_unlock(&dev->mode_config.mutex); |
3930 | } | |
b2f246a8 PZ |
3931 | drm_sysfs_connector_remove(connector); |
3932 | drm_connector_cleanup(connector); | |
16c25533 | 3933 | return false; |
b2f246a8 | 3934 | } |
32f9d658 | 3935 | |
f684960e CW |
3936 | intel_dp_add_properties(intel_dp, connector); |
3937 | ||
a4fc5ed6 KP |
3938 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
3939 | * 0xd. Failure to do so will result in spurious interrupts being | |
3940 | * generated on the port when a cable is not attached. | |
3941 | */ | |
3942 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
3943 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
3944 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
3945 | } | |
16c25533 PZ |
3946 | |
3947 | return true; | |
a4fc5ed6 | 3948 | } |
f0fec3f2 PZ |
3949 | |
3950 | void | |
3951 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) | |
3952 | { | |
3953 | struct intel_digital_port *intel_dig_port; | |
3954 | struct intel_encoder *intel_encoder; | |
3955 | struct drm_encoder *encoder; | |
3956 | struct intel_connector *intel_connector; | |
3957 | ||
b14c5679 | 3958 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
f0fec3f2 PZ |
3959 | if (!intel_dig_port) |
3960 | return; | |
3961 | ||
b14c5679 | 3962 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
f0fec3f2 PZ |
3963 | if (!intel_connector) { |
3964 | kfree(intel_dig_port); | |
3965 | return; | |
3966 | } | |
3967 | ||
3968 | intel_encoder = &intel_dig_port->base; | |
3969 | encoder = &intel_encoder->base; | |
3970 | ||
3971 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, | |
3972 | DRM_MODE_ENCODER_TMDS); | |
3973 | ||
5bfe2ac0 | 3974 | intel_encoder->compute_config = intel_dp_compute_config; |
b934223d | 3975 | intel_encoder->mode_set = intel_dp_mode_set; |
00c09d70 PZ |
3976 | intel_encoder->disable = intel_disable_dp; |
3977 | intel_encoder->post_disable = intel_post_disable_dp; | |
3978 | intel_encoder->get_hw_state = intel_dp_get_hw_state; | |
045ac3b5 | 3979 | intel_encoder->get_config = intel_dp_get_config; |
ab1f90f9 | 3980 | if (IS_VALLEYVIEW(dev)) { |
ecff4f3b | 3981 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
3982 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
3983 | intel_encoder->enable = vlv_enable_dp; | |
3984 | } else { | |
ecff4f3b JN |
3985 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
3986 | intel_encoder->enable = g4x_enable_dp; | |
ab1f90f9 | 3987 | } |
f0fec3f2 | 3988 | |
174edf1f | 3989 | intel_dig_port->port = port; |
f0fec3f2 PZ |
3990 | intel_dig_port->dp.output_reg = output_reg; |
3991 | ||
00c09d70 | 3992 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
f0fec3f2 PZ |
3993 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
3994 | intel_encoder->cloneable = false; | |
3995 | intel_encoder->hot_plug = intel_dp_hot_plug; | |
3996 | ||
15b1d171 PZ |
3997 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { |
3998 | drm_encoder_cleanup(encoder); | |
3999 | kfree(intel_dig_port); | |
b2f246a8 | 4000 | kfree(intel_connector); |
15b1d171 | 4001 | } |
f0fec3f2 | 4002 | } |