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drm/i915/dp: move dp aux ch register init to aux init
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 94static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780
DV		 95static void edp_panel_vdd_on(struct intel_dp *intel_dp);
96static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 97
a4fc5ed6 98static int
ea5b213a 99intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 100{
7183dc29 101 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 102 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 103
104 switch (max_link_bw) {
105 case DP_LINK_BW_1_62:
106 case DP_LINK_BW_2_7:
107 break;
d4eead50 108 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
06ea66b6
TP		 109 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
110 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
111 max_link_bw = DP_LINK_BW_5_4;
112 else
113 max_link_bw = DP_LINK_BW_2_7;
d4eead50 114 break;
a4fc5ed6 115 default:
d4eead50
ID		 116 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
117 max_link_bw);
a4fc5ed6
KP		 118 max_link_bw = DP_LINK_BW_1_62;
119 break;
120 }
121 return max_link_bw;
122}
123
cd9dde44
AJ		 124/*
125 * The units on the numbers in the next two are... bizarre. Examples will
126 * make it clearer; this one parallels an example in the eDP spec.
127 *
128 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
129 *
130 * 270000 * 1 * 8 / 10 == 216000
131 *
132 * The actual data capacity of that configuration is 2.16Gbit/s, so the
133 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
134 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
135 * 119000. At 18bpp that's 2142000 kilobits per second.
136 *
137 * Thus the strange-looking division by 10 in intel_dp_link_required, to
138 * get the result in decakilobits instead of kilobits.
139 */
140
a4fc5ed6 141static int
c898261c 142intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 143{
cd9dde44 144 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 145}
146
fe27d53e
DA		 147static int
148intel_dp_max_data_rate(int max_link_clock, int max_lanes)
149{
150 return (max_link_clock * max_lanes * 8) / 10;
151}
152
c19de8eb 153static enum drm_mode_status
a4fc5ed6
KP		 154intel_dp_mode_valid(struct drm_connector *connector,
155 struct drm_display_mode *mode)
156{
df0e9248 157 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 158 struct intel_connector *intel_connector = to_intel_connector(connector);
159 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 160 int target_clock = mode->clock;
161 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 162
dd06f90e
JN		 163 if (is_edp(intel_dp) && fixed_mode) {
164 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 165 return MODE_PANEL;
166
dd06f90e 167 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 168 return MODE_PANEL;
03afc4a2
DV		 169
170 target_clock = fixed_mode->clock;
7de56f43
ZY		 171 }
172
36008365
DV		 173 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
174 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
175
176 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
177 mode_rate = intel_dp_link_required(target_clock, 18);
178
179 if (mode_rate > max_rate)
c4867936 180 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 181
182 if (mode->clock < 10000)
183 return MODE_CLOCK_LOW;
184
0af78a2b
DV		 185 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
186 return MODE_H_ILLEGAL;
187
a4fc5ed6
KP		 188 return MODE_OK;
189}
190
191static uint32_t
192pack_aux(uint8_t *src, int src_bytes)
193{
194 int i;
195 uint32_t v = 0;
196
197 if (src_bytes > 4)
198 src_bytes = 4;
199 for (i = 0; i < src_bytes; i++)
200 v |= ((uint32_t) src[i]) << ((3-i) * 8);
201 return v;
202}
203
204static void
205unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
206{
207 int i;
208 if (dst_bytes > 4)
209 dst_bytes = 4;
210 for (i = 0; i < dst_bytes; i++)
211 dst[i] = src >> ((3-i) * 8);
212}
213
fb0f8fbf
KP		 214/* hrawclock is 1/4 the FSB frequency */
215static int
216intel_hrawclk(struct drm_device *dev)
217{
218 struct drm_i915_private *dev_priv = dev->dev_private;
219 uint32_t clkcfg;
220
9473c8f4
VP		 221 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
222 if (IS_VALLEYVIEW(dev))
223 return 200;
224
fb0f8fbf
KP		 225 clkcfg = I915_READ(CLKCFG);
226 switch (clkcfg & CLKCFG_FSB_MASK) {
227 case CLKCFG_FSB_400:
228 return 100;
229 case CLKCFG_FSB_533:
230 return 133;
231 case CLKCFG_FSB_667:
232 return 166;
233 case CLKCFG_FSB_800:
234 return 200;
235 case CLKCFG_FSB_1067:
236 return 266;
237 case CLKCFG_FSB_1333:
238 return 333;
239 /* these two are just a guess; one of them might be right */
240 case CLKCFG_FSB_1600:
241 case CLKCFG_FSB_1600_ALT:
242 return 400;
243 default:
244 return 133;
245 }
246}
247
bf13e81b
JN		 248static void
249intel_dp_init_panel_power_sequencer(struct drm_device *dev,
250 struct intel_dp *intel_dp,
251 struct edp_power_seq *out);
252static void
253intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
254 struct intel_dp *intel_dp,
255 struct edp_power_seq *out);
256
257static enum pipe
258vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
259{
260 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
261 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
262 struct drm_device *dev = intel_dig_port->base.base.dev;
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 enum port port = intel_dig_port->port;
265 enum pipe pipe;
266
267 /* modeset should have pipe */
268 if (crtc)
269 return to_intel_crtc(crtc)->pipe;
270
271 /* init time, try to find a pipe with this port selected */
272 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
273 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
274 PANEL_PORT_SELECT_MASK;
275 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
276 return pipe;
277 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
278 return pipe;
279 }
280
281 /* shrug */
282 return PIPE_A;
283}
284
285static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
286{
287 struct drm_device *dev = intel_dp_to_dev(intel_dp);
288
289 if (HAS_PCH_SPLIT(dev))
290 return PCH_PP_CONTROL;
291 else
292 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
293}
294
295static u32 _pp_stat_reg(struct intel_dp *intel_dp)
296{
297 struct drm_device *dev = intel_dp_to_dev(intel_dp);
298
299 if (HAS_PCH_SPLIT(dev))
300 return PCH_PP_STATUS;
301 else
302 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
303}
304
4be73780 305static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 306{
30add22d 307 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 308 struct drm_i915_private *dev_priv = dev->dev_private;
309
bf13e81b 310 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 311}
312
4be73780 313static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 314{
30add22d 315 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 316 struct drm_i915_private *dev_priv = dev->dev_private;
317
bf13e81b 318 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 319}
320
9b984dae
KP		 321static void
322intel_dp_check_edp(struct intel_dp *intel_dp)
323{
30add22d 324 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 325 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 326
9b984dae
KP		 327 if (!is_edp(intel_dp))
328 return;
453c5420 329
4be73780 330 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 331 WARN(1, "eDP powered off while attempting aux channel communication.\n");
332 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 333 I915_READ(_pp_stat_reg(intel_dp)),
334 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 335 }
336}
337
9ee32fea
DV		 338static uint32_t
339intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
340{
341 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
342 struct drm_device *dev = intel_dig_port->base.base.dev;
343 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 344 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 345 uint32_t status;
346 bool done;
347
ef04f00d 348#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 349 if (has_aux_irq)
b18ac466 350 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 351 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 352 else
353 done = wait_for_atomic(C, 10) == 0;
354 if (!done)
355 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
356 has_aux_irq);
357#undef C
358
359 return status;
360}
361
ec5b01dd 362static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 363{
174edf1f
PZ		 364 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
365 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 366
ec5b01dd
DL		 367 /*
368 * The clock divider is based off the hrawclk, and would like to run at
369 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 370 */
ec5b01dd
DL		 371 return index ? 0 : intel_hrawclk(dev) / 2;
372}
373
374static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
375{
376 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
377 struct drm_device *dev = intel_dig_port->base.base.dev;
378
379 if (index)
380 return 0;
381
382 if (intel_dig_port->port == PORT_A) {
383 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 384 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 385 else
b84a1cf8 386 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 387 } else {
388 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
389 }
390}
391
392static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
393{
394 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
395 struct drm_device *dev = intel_dig_port->base.base.dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397
398 if (intel_dig_port->port == PORT_A) {
399 if (index)
400 return 0;
401 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 402 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
403 /* Workaround for non-ULT HSW */
bc86625a
CW		 404 switch (index) {
405 case 0: return 63;
406 case 1: return 72;
407 default: return 0;
408 }
ec5b01dd 409 } else {
bc86625a 410 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 411 }
b84a1cf8
RV		 412}
413
ec5b01dd
DL		 414static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
415{
416 return index ? 0 : 100;
417}
418
5ed12a19
DL		 419static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
420 bool has_aux_irq,
421 int send_bytes,
422 uint32_t aux_clock_divider)
423{
424 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
425 struct drm_device *dev = intel_dig_port->base.base.dev;
426 uint32_t precharge, timeout;
427
428 if (IS_GEN6(dev))
429 precharge = 3;
430 else
431 precharge = 5;
432
433 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
434 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
435 else
436 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
437
438 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 439 DP_AUX_CH_CTL_DONE |
5ed12a19 440 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 441 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 442 timeout |
788d4433 443 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 444 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
445 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 446 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 447}
448
b84a1cf8
RV		 449static int
450intel_dp_aux_ch(struct intel_dp *intel_dp,
451 uint8_t *send, int send_bytes,
452 uint8_t *recv, int recv_size)
453{
454 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
455 struct drm_device *dev = intel_dig_port->base.base.dev;
456 struct drm_i915_private *dev_priv = dev->dev_private;
457 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
458 uint32_t ch_data = ch_ctl + 4;
bc86625a 459 uint32_t aux_clock_divider;
b84a1cf8
RV		 460 int i, ret, recv_bytes;
461 uint32_t status;
5ed12a19 462 int try, clock = 0;
4e6b788c 463 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 464 bool vdd;
465
466 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 467
468 /* dp aux is extremely sensitive to irq latency, hence request the
469 * lowest possible wakeup latency and so prevent the cpu from going into
470 * deep sleep states.
471 */
472 pm_qos_update_request(&dev_priv->pm_qos, 0);
473
474 intel_dp_check_edp(intel_dp);
5eb08b69 475
c67a470b
PZ		 476 intel_aux_display_runtime_get(dev_priv);
477
11bee43e
JB		 478 /* Try to wait for any previous AUX channel activity */
479 for (try = 0; try < 3; try++) {
ef04f00d 480 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 481 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
482 break;
483 msleep(1);
484 }
485
486 if (try == 3) {
487 WARN(1, "dp_aux_ch not started status 0x%08x\n",
488 I915_READ(ch_ctl));
9ee32fea
DV		 489 ret = -EBUSY;
490 goto out;
4f7f7b7e
CW		 491 }
492
46a5ae9f
PZ		 493 /* Only 5 data registers! */
494 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
495 ret = -E2BIG;
496 goto out;
497 }
498
ec5b01dd 499 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 500 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
501 has_aux_irq,
502 send_bytes,
503 aux_clock_divider);
5ed12a19 504
bc86625a
CW		 505 /* Must try at least 3 times according to DP spec */
506 for (try = 0; try < 5; try++) {
507 /* Load the send data into the aux channel data registers */
508 for (i = 0; i < send_bytes; i += 4)
509 I915_WRITE(ch_data + i,
510 pack_aux(send + i, send_bytes - i));
511
512 /* Send the command and wait for it to complete */
5ed12a19 513 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 514
515 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
516
517 /* Clear done status and any errors */
518 I915_WRITE(ch_ctl,
519 status |
520 DP_AUX_CH_CTL_DONE |
521 DP_AUX_CH_CTL_TIME_OUT_ERROR |
522 DP_AUX_CH_CTL_RECEIVE_ERROR);
523
524 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
525 DP_AUX_CH_CTL_RECEIVE_ERROR))
526 continue;
527 if (status & DP_AUX_CH_CTL_DONE)
528 break;
529 }
4f7f7b7e 530 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 531 break;
532 }
533
a4fc5ed6 534 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 535 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 536 ret = -EBUSY;
537 goto out;
a4fc5ed6
KP		 538 }
539
540 /* Check for timeout or receive error.
541 * Timeouts occur when the sink is not connected
542 */
a5b3da54 543 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 544 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 545 ret = -EIO;
546 goto out;
a5b3da54 547 }
1ae8c0a5
KP		 548
549 /* Timeouts occur when the device isn't connected, so they're
550 * "normal" -- don't fill the kernel log with these */
a5b3da54 551 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 552 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 553 ret = -ETIMEDOUT;
554 goto out;
a4fc5ed6
KP		 555 }
556
557 /* Unload any bytes sent back from the other side */
558 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
559 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 560 if (recv_bytes > recv_size)
561 recv_bytes = recv_size;
0206e353 562
4f7f7b7e
CW		 563 for (i = 0; i < recv_bytes; i += 4)
564 unpack_aux(I915_READ(ch_data + i),
565 recv + i, recv_bytes - i);
a4fc5ed6 566
9ee32fea
DV		 567 ret = recv_bytes;
568out:
569 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 570 intel_aux_display_runtime_put(dev_priv);
9ee32fea 571
884f19e9
JN		 572 if (vdd)
573 edp_panel_vdd_off(intel_dp, false);
574
9ee32fea 575 return ret;
a4fc5ed6
KP		 576}
577
9d1a1031
JN		 578#define HEADER_SIZE 4
579static ssize_t
580intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 581{
9d1a1031
JN		 582 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
583 uint8_t txbuf[20], rxbuf[20];
584 size_t txsize, rxsize;
a4fc5ed6 585 int ret;
a4fc5ed6 586
9d1a1031
JN		 587 txbuf[0] = msg->request << 4;
588 txbuf[1] = msg->address >> 8;
589 txbuf[2] = msg->address & 0xff;
590 txbuf[3] = msg->size - 1;
46a5ae9f 591
9d1a1031
JN		 592 switch (msg->request & ~DP_AUX_I2C_MOT) {
593 case DP_AUX_NATIVE_WRITE:
594 case DP_AUX_I2C_WRITE:
595 txsize = HEADER_SIZE + msg->size;
596 rxsize = 1;
f51a44b9 597
9d1a1031
JN		 598 if (WARN_ON(txsize > 20))
599 return -E2BIG;
a4fc5ed6 600
9d1a1031 601 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 602
9d1a1031
JN		 603 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
604 if (ret > 0) {
605 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 606
9d1a1031
JN		 607 /* Return payload size. */
608 ret = msg->size;
609 }
610 break;
46a5ae9f 611
9d1a1031
JN		 612 case DP_AUX_NATIVE_READ:
613 case DP_AUX_I2C_READ:
614 txsize = HEADER_SIZE;
615 rxsize = msg->size + 1;
a4fc5ed6 616
9d1a1031
JN		 617 if (WARN_ON(rxsize > 20))
618 return -E2BIG;
a4fc5ed6 619
9d1a1031
JN		 620 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
621 if (ret > 0) {
622 msg->reply = rxbuf[0] >> 4;
623 /*
624 * Assume happy day, and copy the data. The caller is
625 * expected to check msg->reply before touching it.
626 *
627 * Return payload size.
628 */
629 ret--;
630 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 631 }
9d1a1031
JN		 632 break;
633
634 default:
635 ret = -EINVAL;
636 break;
a4fc5ed6 637 }
f51a44b9 638
9d1a1031
JN		 639 return ret;
640}
641
642static void
643intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
644{
645 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 646 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
647 enum port port = intel_dig_port->port;
648
649 switch (port) {
650 case PORT_A:
651 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
652 break;
653 case PORT_B:
654 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
655 break;
656 case PORT_C:
657 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
658 break;
659 case PORT_D:
660 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
661 break;
662 default:
663 BUG();
664 }
665
666 if (!HAS_DDI(dev))
667 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
9d1a1031
JN		 668
669 intel_dp->aux.dev = dev->dev;
670 intel_dp->aux.transfer = intel_dp_aux_transfer;
a4fc5ed6
KP		 671}
672
673static int
ab2c0672
DA		 674intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
675 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 676{
ab2c0672 677 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 678 struct intel_dp *intel_dp = container_of(adapter,
679 struct intel_dp,
680 adapter);
ab2c0672
DA		 681 uint16_t address = algo_data->address;
682 uint8_t msg[5];
683 uint8_t reply[2];
8316f337 684 unsigned retry;
ab2c0672
DA		 685 int msg_bytes;
686 int reply_bytes;
687 int ret;
688
689 /* Set up the command byte */
690 if (mode & MODE_I2C_READ)
6b27f7f0 691 msg[0] = DP_AUX_I2C_READ << 4;
ab2c0672 692 else
6b27f7f0 693 msg[0] = DP_AUX_I2C_WRITE << 4;
ab2c0672
DA		 694
695 if (!(mode & MODE_I2C_STOP))
6b27f7f0 696 msg[0] |= DP_AUX_I2C_MOT << 4;
a4fc5ed6 697
ab2c0672
DA		 698 msg[1] = address >> 8;
699 msg[2] = address;
700
701 switch (mode) {
702 case MODE_I2C_WRITE:
703 msg[3] = 0;
704 msg[4] = write_byte;
705 msg_bytes = 5;
706 reply_bytes = 1;
707 break;
708 case MODE_I2C_READ:
709 msg[3] = 0;
710 msg_bytes = 4;
711 reply_bytes = 2;
712 break;
713 default:
714 msg_bytes = 3;
715 reply_bytes = 1;
716 break;
717 }
718
58c67ce9
JN		 719 /*
720 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
721 * required to retry at least seven times upon receiving AUX_DEFER
722 * before giving up the AUX transaction.
723 */
724 for (retry = 0; retry < 7; retry++) {
8316f337
DF		 725 ret = intel_dp_aux_ch(intel_dp,
726 msg, msg_bytes,
727 reply, reply_bytes);
ab2c0672 728 if (ret < 0) {
3ff99164 729 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
8a5e6aeb 730 goto out;
ab2c0672 731 }
8316f337 732
6b27f7f0
TR		 733 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
734 case DP_AUX_NATIVE_REPLY_ACK:
8316f337
DF		 735 /* I2C-over-AUX Reply field is only valid
736 * when paired with AUX ACK.
737 */
738 break;
6b27f7f0 739 case DP_AUX_NATIVE_REPLY_NACK:
8316f337 740 DRM_DEBUG_KMS("aux_ch native nack\n");
8a5e6aeb
PZ		 741 ret = -EREMOTEIO;
742 goto out;
6b27f7f0 743 case DP_AUX_NATIVE_REPLY_DEFER:
8d16f258
JN		 744 /*
745 * For now, just give more slack to branch devices. We
746 * could check the DPCD for I2C bit rate capabilities,
747 * and if available, adjust the interval. We could also
748 * be more careful with DP-to-Legacy adapters where a
749 * long legacy cable may force very low I2C bit rates.
750 */
751 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
752 DP_DWN_STRM_PORT_PRESENT)
753 usleep_range(500, 600);
754 else
755 usleep_range(300, 400);
8316f337
DF		 756 continue;
757 default:
758 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
759 reply[0]);
8a5e6aeb
PZ		 760 ret = -EREMOTEIO;
761 goto out;
8316f337
DF		 762 }
763
6b27f7f0
TR		 764 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
765 case DP_AUX_I2C_REPLY_ACK:
ab2c0672
DA		 766 if (mode == MODE_I2C_READ) {
767 *read_byte = reply[1];
768 }
8a5e6aeb
PZ		 769 ret = reply_bytes - 1;
770 goto out;
6b27f7f0 771 case DP_AUX_I2C_REPLY_NACK:
8316f337 772 DRM_DEBUG_KMS("aux_i2c nack\n");
8a5e6aeb
PZ		 773 ret = -EREMOTEIO;
774 goto out;
6b27f7f0 775 case DP_AUX_I2C_REPLY_DEFER:
8316f337 776 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 777 udelay(100);
778 break;
779 default:
8316f337 780 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
8a5e6aeb
PZ		 781 ret = -EREMOTEIO;
782 goto out;
ab2c0672
DA		 783 }
784 }
8316f337
DF		 785
786 DRM_ERROR("too many retries, giving up\n");
8a5e6aeb
PZ		 787 ret = -EREMOTEIO;
788
789out:
8a5e6aeb 790 return ret;
a4fc5ed6
KP		 791}
792
80f65de3
ID		 793static void
794intel_dp_connector_unregister(struct intel_connector *intel_connector)
795{
796 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
797
798 sysfs_remove_link(&intel_connector->base.kdev->kobj,
799 intel_dp->adapter.dev.kobj.name);
800 intel_connector_unregister(intel_connector);
801}
802
a4fc5ed6 803static int
ea5b213a 804intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 805 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 806{
0b5c541b
KP		 807 int ret;
808
d54e9d28 809 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 810 intel_dp->algo.running = false;
811 intel_dp->algo.address = 0;
812 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
813
0206e353 814 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 815 intel_dp->adapter.owner = THIS_MODULE;
816 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 817 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 818 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
819 intel_dp->adapter.algo_data = &intel_dp->algo;
80f65de3 820 intel_dp->adapter.dev.parent = intel_connector->base.dev->dev;
ea5b213a 821
0b5c541b 822 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
80f65de3
ID		 823 if (ret < 0)
824 return ret;
825
826 ret = sysfs_create_link(&intel_connector->base.kdev->kobj,
827 &intel_dp->adapter.dev.kobj,
828 intel_dp->adapter.dev.kobj.name);
829
830 if (ret < 0)
831 i2c_del_adapter(&intel_dp->adapter);
832
0b5c541b 833 return ret;
a4fc5ed6
KP		 834}
835
c6bb3538
DV		 836static void
837intel_dp_set_clock(struct intel_encoder *encoder,
838 struct intel_crtc_config *pipe_config, int link_bw)
839{
840 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 841 const struct dp_link_dpll *divisor = NULL;
842 int i, count = 0;
c6bb3538
DV		 843
844 if (IS_G4X(dev)) {
9dd4ffdf
CML		 845 divisor = gen4_dpll;
846 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 847 } else if (IS_HASWELL(dev)) {
848 /* Haswell has special-purpose DP DDI clocks. */
849 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 850 divisor = pch_dpll;
851 count = ARRAY_SIZE(pch_dpll);
c6bb3538 852 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 853 divisor = vlv_dpll;
854 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 855 }
9dd4ffdf
CML		 856
857 if (divisor && count) {
858 for (i = 0; i < count; i++) {
859 if (link_bw == divisor[i].link_bw) {
860 pipe_config->dpll = divisor[i].dpll;
861 pipe_config->clock_set = true;
862 break;
863 }
864 }
c6bb3538
DV		 865 }
866}
867
00c09d70 868bool
5bfe2ac0
DV		 869intel_dp_compute_config(struct intel_encoder *encoder,
870 struct intel_crtc_config *pipe_config)
a4fc5ed6 871{
5bfe2ac0 872 struct drm_device *dev = encoder->base.dev;
36008365 873 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 874 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 875 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 876 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 877 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 878 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 879 int lane_count, clock;
397fe157 880 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
06ea66b6
TP		 881 /* Conveniently, the link BW constants become indices with a shift...*/
882 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 883 int bpp, mode_rate;
06ea66b6 884 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 885 int link_avail, link_clock;
a4fc5ed6 886
bc7d38a4 887 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 888 pipe_config->has_pch_encoder = true;
889
03afc4a2 890 pipe_config->has_dp_encoder = true;
a4fc5ed6 891
dd06f90e
JN		 892 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
893 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
894 adjusted_mode);
2dd24552
JB		 895 if (!HAS_PCH_SPLIT(dev))
896 intel_gmch_panel_fitting(intel_crtc, pipe_config,
897 intel_connector->panel.fitting_mode);
898 else
b074cec8
JB		 899 intel_pch_panel_fitting(intel_crtc, pipe_config,
900 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 901 }
902
cb1793ce 903 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 904 return false;
905
083f9560
DV		 906 DRM_DEBUG_KMS("DP link computation with max lane count %i "
907 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 908 max_lane_count, bws[max_clock],
909 adjusted_mode->crtc_clock);
083f9560 910
36008365
DV		 911 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
912 * bpc in between. */
3e7ca985 913 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 914 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
915 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 916 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
917 dev_priv->vbt.edp_bpp);
6da7f10d 918 bpp = dev_priv->vbt.edp_bpp;
7984211e 919 }
657445fe 920
36008365 921 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 922 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
923 bpp);
36008365 924
38aecea0
DV		 925 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
926 for (clock = 0; clock <= max_clock; clock++) {
36008365
DV		 927 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
928 link_avail = intel_dp_max_data_rate(link_clock,
929 lane_count);
930
931 if (mode_rate <= link_avail) {
932 goto found;
933 }
934 }
935 }
936 }
c4867936 937
36008365 938 return false;
3685a8f3 939
36008365 940found:
55bc60db
VS		 941 if (intel_dp->color_range_auto) {
942 /*
943 * See:
944 * CEA-861-E - 5.1 Default Encoding Parameters
945 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
946 */
18316c8c 947 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 948 intel_dp->color_range = DP_COLOR_RANGE_16_235;
949 else
950 intel_dp->color_range = 0;
951 }
952
3685a8f3 953 if (intel_dp->color_range)
50f3b016 954 pipe_config->limited_color_range = true;
a4fc5ed6 955
36008365
DV		 956 intel_dp->link_bw = bws[clock];
957 intel_dp->lane_count = lane_count;
657445fe 958 pipe_config->pipe_bpp = bpp;
ff9a6750 959 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 960
36008365
DV		 961 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
962 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 963 pipe_config->port_clock, bpp);
36008365
DV		 964 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
965 mode_rate, link_avail);
a4fc5ed6 966
03afc4a2 967 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 968 adjusted_mode->crtc_clock,
969 pipe_config->port_clock,
03afc4a2 970 &pipe_config->dp_m_n);
9d1a455b 971
c6bb3538
DV		 972 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
973
03afc4a2 974 return true;
a4fc5ed6
KP		 975}
976
7c62a164 977static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 978{
7c62a164
DV		 979 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
980 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
981 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 982 struct drm_i915_private *dev_priv = dev->dev_private;
983 u32 dpa_ctl;
984
ff9a6750 985 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 986 dpa_ctl = I915_READ(DP_A);
987 dpa_ctl &= ~DP_PLL_FREQ_MASK;
988
ff9a6750 989 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 990 /* For a long time we've carried around a ILK-DevA w/a for the
991 * 160MHz clock. If we're really unlucky, it's still required.
992 */
993 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 994 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 995 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 996 } else {
997 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 998 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 999 }
1ce17038 1000
ea9b6006
DV		 1001 I915_WRITE(DP_A, dpa_ctl);
1002
1003 POSTING_READ(DP_A);
1004 udelay(500);
1005}
1006
b934223d 1007static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 1008{
b934223d 1009 struct drm_device *dev = encoder->base.dev;
417e822d 1010 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1011 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1012 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1013 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1014 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1015
417e822d 1016 /*
1a2eb460 1017 * There are four kinds of DP registers:
417e822d
KP		 1018 *
1019 * IBX PCH
1a2eb460
KP		 1020 * SNB CPU
1021 * IVB CPU
417e822d
KP		 1022 * CPT PCH
1023 *
1024 * IBX PCH and CPU are the same for almost everything,
1025 * except that the CPU DP PLL is configured in this
1026 * register
1027 *
1028 * CPT PCH is quite different, having many bits moved
1029 * to the TRANS_DP_CTL register instead. That
1030 * configuration happens (oddly) in ironlake_pch_enable
1031 */
9c9e7927 1032
417e822d
KP		 1033 /* Preserve the BIOS-computed detected bit. This is
1034 * supposed to be read-only.
1035 */
1036 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1037
417e822d 1038 /* Handle DP bits in common between all three register formats */
417e822d 1039 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1040 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1041
e0dac65e
WF		 1042 if (intel_dp->has_audio) {
1043 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1044 pipe_name(crtc->pipe));
ea5b213a 1045 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1046 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1047 }
247d89f6 1048
417e822d 1049 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1050
bc7d38a4 1051 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1052 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1053 intel_dp->DP |= DP_SYNC_HS_HIGH;
1054 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1055 intel_dp->DP |= DP_SYNC_VS_HIGH;
1056 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1057
6aba5b6c 1058 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1059 intel_dp->DP |= DP_ENHANCED_FRAMING;
1060
7c62a164 1061 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1062 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1063 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1064 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1065
1066 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1067 intel_dp->DP |= DP_SYNC_HS_HIGH;
1068 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1069 intel_dp->DP |= DP_SYNC_VS_HIGH;
1070 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1071
6aba5b6c 1072 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1073 intel_dp->DP |= DP_ENHANCED_FRAMING;
1074
7c62a164 1075 if (crtc->pipe == 1)
417e822d 1076 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 1077 } else {
1078 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1079 }
ea9b6006 1080
bc7d38a4 1081 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 1082 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 1083}
1084
ffd6749d
PZ		 1085#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1086#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1087
1a5ef5b7
PZ		 1088#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1089#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1090
ffd6749d
PZ		 1091#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1092#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1093
4be73780 1094static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1095 u32 mask,
1096 u32 value)
bd943159 1097{
30add22d 1098 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1099 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1100 u32 pp_stat_reg, pp_ctrl_reg;
1101
bf13e81b
JN		 1102 pp_stat_reg = _pp_stat_reg(intel_dp);
1103 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1104
99ea7127 1105 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1106 mask, value,
1107 I915_READ(pp_stat_reg),
1108 I915_READ(pp_ctrl_reg));
32ce697c 1109
453c5420 1110 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1111 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1112 I915_READ(pp_stat_reg),
1113 I915_READ(pp_ctrl_reg));
32ce697c 1114 }
54c136d4
CW		 1115
1116 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1117}
32ce697c 1118
4be73780 1119static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1120{
1121 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1122 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1123}
1124
4be73780 1125static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1126{
1127 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1128 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1129}
1130
4be73780 1131static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1132{
1133 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1134
1135 /* When we disable the VDD override bit last we have to do the manual
1136 * wait. */
1137 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1138 intel_dp->panel_power_cycle_delay);
1139
4be73780 1140 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1141}
1142
4be73780 1143static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1144{
1145 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1146 intel_dp->backlight_on_delay);
1147}
1148
4be73780 1149static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1150{
1151 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1152 intel_dp->backlight_off_delay);
1153}
99ea7127 1154
832dd3c1
KP		 1155/* Read the current pp_control value, unlocking the register if it
1156 * is locked
1157 */
1158
453c5420 1159static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1160{
453c5420
JB		 1161 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1162 struct drm_i915_private *dev_priv = dev->dev_private;
1163 u32 control;
832dd3c1 1164
bf13e81b 1165 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1166 control &= ~PANEL_UNLOCK_MASK;
1167 control |= PANEL_UNLOCK_REGS;
1168 return control;
bd943159
KP		 1169}
1170
adddaaf4 1171static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1172{
30add22d 1173 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1174 struct drm_i915_private *dev_priv = dev->dev_private;
1175 u32 pp;
453c5420 1176 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1177 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1178
97af61f5 1179 if (!is_edp(intel_dp))
adddaaf4 1180 return false;
bd943159
KP		 1181
1182 intel_dp->want_panel_vdd = true;
99ea7127 1183
4be73780 1184 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1185 return need_to_disable;
b0665d57 1186
e9cb81a2
PZ		 1187 intel_runtime_pm_get(dev_priv);
1188
b0665d57 1189 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1190
4be73780
DV		 1191 if (!edp_have_panel_power(intel_dp))
1192 wait_panel_power_cycle(intel_dp);
99ea7127 1193
453c5420 1194 pp = ironlake_get_pp_control(intel_dp);
5d613501 1195 pp |= EDP_FORCE_VDD;
ebf33b18 1196
bf13e81b
JN		 1197 pp_stat_reg = _pp_stat_reg(intel_dp);
1198 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1199
1200 I915_WRITE(pp_ctrl_reg, pp);
1201 POSTING_READ(pp_ctrl_reg);
1202 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1203 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1204 /*
1205 * If the panel wasn't on, delay before accessing aux channel
1206 */
4be73780 1207 if (!edp_have_panel_power(intel_dp)) {
bd943159 1208 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1209 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1210 }
adddaaf4
JN		 1211
1212 return need_to_disable;
1213}
1214
1215static void edp_panel_vdd_on(struct intel_dp *intel_dp)
1216{
1217 if (is_edp(intel_dp)) {
1218 bool vdd = _edp_panel_vdd_on(intel_dp);
1219
1220 WARN(!vdd, "eDP VDD already requested on\n");
1221 }
5d613501
JB		 1222}
1223
4be73780 1224static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1225{
30add22d 1226 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1227 struct drm_i915_private *dev_priv = dev->dev_private;
1228 u32 pp;
453c5420 1229 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1230
a0e99e68
DV		 1231 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1232
4be73780 1233 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
b0665d57
PZ		 1234 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1235
453c5420 1236 pp = ironlake_get_pp_control(intel_dp);
bd943159 1237 pp &= ~EDP_FORCE_VDD;
bd943159 1238
9f08ef59
PZ		 1239 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1240 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1241
1242 I915_WRITE(pp_ctrl_reg, pp);
1243 POSTING_READ(pp_ctrl_reg);
99ea7127 1244
453c5420
JB		 1245 /* Make sure sequencer is idle before allowing subsequent activity */
1246 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1247 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1248
1249 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1250 intel_dp->last_power_cycle = jiffies;
e9cb81a2
PZ		 1251
1252 intel_runtime_pm_put(dev_priv);
bd943159
KP		 1253 }
1254}
5d613501 1255
4be73780 1256static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1257{
1258 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1259 struct intel_dp, panel_vdd_work);
30add22d 1260 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1261
627f7675 1262 mutex_lock(&dev->mode_config.mutex);
4be73780 1263 edp_panel_vdd_off_sync(intel_dp);
627f7675 1264 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1265}
1266
4be73780 1267static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1268{
97af61f5
KP		 1269 if (!is_edp(intel_dp))
1270 return;
5d613501 1271
bd943159 1272 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1273
bd943159
KP		 1274 intel_dp->want_panel_vdd = false;
1275
1276 if (sync) {
4be73780 1277 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1278 } else {
1279 /*
1280 * Queue the timer to fire a long
1281 * time from now (relative to the power down delay)
1282 * to keep the panel power up across a sequence of operations
1283 */
1284 schedule_delayed_work(&intel_dp->panel_vdd_work,
1285 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1286 }
5d613501
JB		 1287}
1288
4be73780 1289void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1290{
30add22d 1291 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1292 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1293 u32 pp;
453c5420 1294 u32 pp_ctrl_reg;
9934c132 1295
97af61f5 1296 if (!is_edp(intel_dp))
bd943159 1297 return;
99ea7127
KP		 1298
1299 DRM_DEBUG_KMS("Turn eDP power on\n");
1300
4be73780 1301 if (edp_have_panel_power(intel_dp)) {
99ea7127 1302 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1303 return;
99ea7127 1304 }
9934c132 1305
4be73780 1306 wait_panel_power_cycle(intel_dp);
37c6c9b0 1307
bf13e81b 1308 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1309 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1310 if (IS_GEN5(dev)) {
1311 /* ILK workaround: disable reset around power sequence */
1312 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1313 I915_WRITE(pp_ctrl_reg, pp);
1314 POSTING_READ(pp_ctrl_reg);
05ce1a49 1315 }
37c6c9b0 1316
1c0ae80a 1317 pp |= POWER_TARGET_ON;
99ea7127
KP		 1318 if (!IS_GEN5(dev))
1319 pp |= PANEL_POWER_RESET;
1320
453c5420
JB		 1321 I915_WRITE(pp_ctrl_reg, pp);
1322 POSTING_READ(pp_ctrl_reg);
9934c132 1323
4be73780 1324 wait_panel_on(intel_dp);
dce56b3c 1325 intel_dp->last_power_on = jiffies;
9934c132 1326
05ce1a49
KP		 1327 if (IS_GEN5(dev)) {
1328 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1329 I915_WRITE(pp_ctrl_reg, pp);
1330 POSTING_READ(pp_ctrl_reg);
05ce1a49 1331 }
9934c132
JB		 1332}
1333
4be73780 1334void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1335{
30add22d 1336 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1337 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1338 u32 pp;
453c5420 1339 u32 pp_ctrl_reg;
9934c132 1340
97af61f5
KP		 1341 if (!is_edp(intel_dp))
1342 return;
37c6c9b0 1343
99ea7127 1344 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1345
4be73780 1346 edp_wait_backlight_off(intel_dp);
dce56b3c 1347
453c5420 1348 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1349 /* We need to switch off panel power _and_ force vdd, for otherwise some
1350 * panels get very unhappy and cease to work. */
b3064154
PJ		 1351 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1352 EDP_BLC_ENABLE);
453c5420 1353
bf13e81b 1354 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1355
1356 I915_WRITE(pp_ctrl_reg, pp);
1357 POSTING_READ(pp_ctrl_reg);
9934c132 1358
dce56b3c 1359 intel_dp->last_power_cycle = jiffies;
4be73780 1360 wait_panel_off(intel_dp);
9934c132
JB		 1361}
1362
4be73780 1363void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1364{
da63a9f2
PZ		 1365 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1366 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 u32 pp;
453c5420 1369 u32 pp_ctrl_reg;
32f9d658 1370
f01eca2e
KP		 1371 if (!is_edp(intel_dp))
1372 return;
1373
28c97730 1374 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1375 /*
1376 * If we enable the backlight right away following a panel power
1377 * on, we may see slight flicker as the panel syncs with the eDP
1378 * link. So delay a bit to make sure the image is solid before
1379 * allowing it to appear.
1380 */
4be73780 1381 wait_backlight_on(intel_dp);
453c5420 1382 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1383 pp |= EDP_BLC_ENABLE;
453c5420 1384
bf13e81b 1385 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1386
1387 I915_WRITE(pp_ctrl_reg, pp);
1388 POSTING_READ(pp_ctrl_reg);
035aa3de 1389
752aa88a 1390 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1391}
1392
4be73780 1393void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1394{
30add22d 1395 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1396 struct drm_i915_private *dev_priv = dev->dev_private;
1397 u32 pp;
453c5420 1398 u32 pp_ctrl_reg;
32f9d658 1399
f01eca2e
KP		 1400 if (!is_edp(intel_dp))
1401 return;
1402
752aa88a 1403 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1404
28c97730 1405 DRM_DEBUG_KMS("\n");
453c5420 1406 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1407 pp &= ~EDP_BLC_ENABLE;
453c5420 1408
bf13e81b 1409 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1410
1411 I915_WRITE(pp_ctrl_reg, pp);
1412 POSTING_READ(pp_ctrl_reg);
dce56b3c 1413 intel_dp->last_backlight_off = jiffies;
32f9d658 1414}
a4fc5ed6 1415
2bd2ad64 1416static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1417{
da63a9f2
PZ		 1418 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1419 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1420 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1421 struct drm_i915_private *dev_priv = dev->dev_private;
1422 u32 dpa_ctl;
1423
2bd2ad64
DV		 1424 assert_pipe_disabled(dev_priv,
1425 to_intel_crtc(crtc)->pipe);
1426
d240f20f
JB		 1427 DRM_DEBUG_KMS("\n");
1428 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1429 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1430 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1431
1432 /* We don't adjust intel_dp->DP while tearing down the link, to
1433 * facilitate link retraining (e.g. after hotplug). Hence clear all
1434 * enable bits here to ensure that we don't enable too much. */
1435 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1436 intel_dp->DP |= DP_PLL_ENABLE;
1437 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1438 POSTING_READ(DP_A);
1439 udelay(200);
d240f20f
JB		 1440}
1441
2bd2ad64 1442static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1443{
da63a9f2
PZ		 1444 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1445 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1446 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1447 struct drm_i915_private *dev_priv = dev->dev_private;
1448 u32 dpa_ctl;
1449
2bd2ad64
DV		 1450 assert_pipe_disabled(dev_priv,
1451 to_intel_crtc(crtc)->pipe);
1452
d240f20f 1453 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1454 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1455 "dp pll off, should be on\n");
1456 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1457
1458 /* We can't rely on the value tracked for the DP register in
1459 * intel_dp->DP because link_down must not change that (otherwise link
1460 * re-training will fail. */
298b0b39 1461 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1462 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1463 POSTING_READ(DP_A);
d240f20f
JB		 1464 udelay(200);
1465}
1466
c7ad3810 1467/* If the sink supports it, try to set the power state appropriately */
c19b0669 1468void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1469{
1470 int ret, i;
1471
1472 /* Should have a valid DPCD by this point */
1473 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1474 return;
1475
1476 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1477 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1478 DP_SET_POWER_D3);
c7ad3810
JB		 1479 if (ret != 1)
1480 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1481 } else {
1482 /*
1483 * When turning on, we need to retry for 1ms to give the sink
1484 * time to wake up.
1485 */
1486 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1487 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1488 DP_SET_POWER_D0);
c7ad3810
JB		 1489 if (ret == 1)
1490 break;
1491 msleep(1);
1492 }
1493 }
1494}
1495
19d8fe15
DV		 1496static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1497 enum pipe *pipe)
d240f20f 1498{
19d8fe15 1499 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1500 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1501 struct drm_device *dev = encoder->base.dev;
1502 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1503 enum intel_display_power_domain power_domain;
1504 u32 tmp;
1505
1506 power_domain = intel_display_port_power_domain(encoder);
1507 if (!intel_display_power_enabled(dev_priv, power_domain))
1508 return false;
1509
1510 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1511
1512 if (!(tmp & DP_PORT_EN))
1513 return false;
1514
bc7d38a4 1515 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1516 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1517 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1518 *pipe = PORT_TO_PIPE(tmp);
1519 } else {
1520 u32 trans_sel;
1521 u32 trans_dp;
1522 int i;
1523
1524 switch (intel_dp->output_reg) {
1525 case PCH_DP_B:
1526 trans_sel = TRANS_DP_PORT_SEL_B;
1527 break;
1528 case PCH_DP_C:
1529 trans_sel = TRANS_DP_PORT_SEL_C;
1530 break;
1531 case PCH_DP_D:
1532 trans_sel = TRANS_DP_PORT_SEL_D;
1533 break;
1534 default:
1535 return true;
1536 }
1537
1538 for_each_pipe(i) {
1539 trans_dp = I915_READ(TRANS_DP_CTL(i));
1540 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1541 *pipe = i;
1542 return true;
1543 }
1544 }
19d8fe15 1545
4a0833ec
DV		 1546 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1547 intel_dp->output_reg);
1548 }
d240f20f 1549
19d8fe15
DV		 1550 return true;
1551}
d240f20f 1552
045ac3b5
JB		 1553static void intel_dp_get_config(struct intel_encoder *encoder,
1554 struct intel_crtc_config *pipe_config)
1555{
1556 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1557 u32 tmp, flags = 0;
63000ef6
XZ		 1558 struct drm_device *dev = encoder->base.dev;
1559 struct drm_i915_private *dev_priv = dev->dev_private;
1560 enum port port = dp_to_dig_port(intel_dp)->port;
1561 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1562 int dotclock;
045ac3b5 1563
63000ef6
XZ		 1564 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1565 tmp = I915_READ(intel_dp->output_reg);
1566 if (tmp & DP_SYNC_HS_HIGH)
1567 flags |= DRM_MODE_FLAG_PHSYNC;
1568 else
1569 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1570
63000ef6
XZ		 1571 if (tmp & DP_SYNC_VS_HIGH)
1572 flags |= DRM_MODE_FLAG_PVSYNC;
1573 else
1574 flags |= DRM_MODE_FLAG_NVSYNC;
1575 } else {
1576 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1577 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1578 flags |= DRM_MODE_FLAG_PHSYNC;
1579 else
1580 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1581
63000ef6
XZ		 1582 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1583 flags |= DRM_MODE_FLAG_PVSYNC;
1584 else
1585 flags |= DRM_MODE_FLAG_NVSYNC;
1586 }
045ac3b5
JB		 1587
1588 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1589
eb14cb74
VS		 1590 pipe_config->has_dp_encoder = true;
1591
1592 intel_dp_get_m_n(crtc, pipe_config);
1593
18442d08 1594 if (port == PORT_A) {
f1f644dc
JB		 1595 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1596 pipe_config->port_clock = 162000;
1597 else
1598 pipe_config->port_clock = 270000;
1599 }
18442d08
VS		 1600
1601 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1602 &pipe_config->dp_m_n);
1603
1604 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1605 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1606
241bfc38 1607 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1608
c6cd2ee2
JN		 1609 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1610 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1611 /*
1612 * This is a big fat ugly hack.
1613 *
1614 * Some machines in UEFI boot mode provide us a VBT that has 18
1615 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1616 * unknown we fail to light up. Yet the same BIOS boots up with
1617 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1618 * max, not what it tells us to use.
1619 *
1620 * Note: This will still be broken if the eDP panel is not lit
1621 * up by the BIOS, and thus we can't get the mode at module
1622 * load.
1623 */
1624 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1625 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1626 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1627 }
045ac3b5
JB		 1628}
1629
a031d709 1630static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1631{
a031d709
RV		 1632 struct drm_i915_private *dev_priv = dev->dev_private;
1633
1634 return dev_priv->psr.sink_support;
2293bb5c
SK		 1635}
1636
2b28bb1b
RV		 1637static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1638{
1639 struct drm_i915_private *dev_priv = dev->dev_private;
1640
18b5992c 1641 if (!HAS_PSR(dev))
2b28bb1b
RV		 1642 return false;
1643
18b5992c 1644 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1645}
1646
1647static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1648 struct edp_vsc_psr *vsc_psr)
1649{
1650 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1651 struct drm_device *dev = dig_port->base.base.dev;
1652 struct drm_i915_private *dev_priv = dev->dev_private;
1653 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1654 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1655 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1656 uint32_t *data = (uint32_t *) vsc_psr;
1657 unsigned int i;
1658
1659 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1660 the video DIP being updated before program video DIP data buffer
1661 registers for DIP being updated. */
1662 I915_WRITE(ctl_reg, 0);
1663 POSTING_READ(ctl_reg);
1664
1665 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1666 if (i < sizeof(struct edp_vsc_psr))
1667 I915_WRITE(data_reg + i, *data++);
1668 else
1669 I915_WRITE(data_reg + i, 0);
1670 }
1671
1672 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1673 POSTING_READ(ctl_reg);
1674}
1675
1676static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1677{
1678 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1679 struct drm_i915_private *dev_priv = dev->dev_private;
1680 struct edp_vsc_psr psr_vsc;
1681
1682 if (intel_dp->psr_setup_done)
1683 return;
1684
1685 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1686 memset(&psr_vsc, 0, sizeof(psr_vsc));
1687 psr_vsc.sdp_header.HB0 = 0;
1688 psr_vsc.sdp_header.HB1 = 0x7;
1689 psr_vsc.sdp_header.HB2 = 0x2;
1690 psr_vsc.sdp_header.HB3 = 0x8;
1691 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1692
1693 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1694 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1695 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1696
1697 intel_dp->psr_setup_done = true;
1698}
1699
1700static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1701{
1702 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1703 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1704 uint32_t aux_clock_divider;
2b28bb1b
RV		 1705 int precharge = 0x3;
1706 int msg_size = 5; /* Header(4) + Message(1) */
1707
ec5b01dd
DL		 1708 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1709
2b28bb1b
RV		 1710 /* Enable PSR in sink */
1711 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
9d1a1031
JN		 1712 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1713 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1714 else
9d1a1031
JN		 1715 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1716 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1717
1718 /* Setup AUX registers */
18b5992c
BW		 1719 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1720 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1721 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1722 DP_AUX_CH_CTL_TIME_OUT_400us |
1723 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1724 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1725 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1726}
1727
1728static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1729{
1730 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1731 struct drm_i915_private *dev_priv = dev->dev_private;
1732 uint32_t max_sleep_time = 0x1f;
1733 uint32_t idle_frames = 1;
1734 uint32_t val = 0x0;
ed8546ac 1735 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1736
1737 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1738 val |= EDP_PSR_LINK_STANDBY;
1739 val |= EDP_PSR_TP2_TP3_TIME_0us;
1740 val |= EDP_PSR_TP1_TIME_0us;
1741 val |= EDP_PSR_SKIP_AUX_EXIT;
1742 } else
1743 val |= EDP_PSR_LINK_DISABLE;
1744
18b5992c 1745 I915_WRITE(EDP_PSR_CTL(dev), val |
ed8546ac 1746 IS_BROADWELL(dev) ? 0 : link_entry_time |
2b28bb1b
RV		 1747 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1748 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1749 EDP_PSR_ENABLE);
1750}
1751
3f51e471
RV		 1752static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1753{
1754 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1755 struct drm_device *dev = dig_port->base.base.dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 struct drm_crtc *crtc = dig_port->base.base.crtc;
1758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1759 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1760 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1761
a031d709
RV		 1762 dev_priv->psr.source_ok = false;
1763
18b5992c 1764 if (!HAS_PSR(dev)) {
3f51e471 1765 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1766 return false;
1767 }
1768
1769 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1770 (dig_port->port != PORT_A)) {
1771 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1772 return false;
1773 }
1774
d330a953 1775 if (!i915.enable_psr) {
105b7c11 1776 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1777 return false;
1778 }
1779
cd234b0b
CW		 1780 crtc = dig_port->base.base.crtc;
1781 if (crtc == NULL) {
1782 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1783 return false;
1784 }
1785
1786 intel_crtc = to_intel_crtc(crtc);
20ddf665 1787 if (!intel_crtc_active(crtc)) {
3f51e471 1788 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1789 return false;
1790 }
1791
cd234b0b 1792 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1793 if (obj->tiling_mode != I915_TILING_X ||
1794 obj->fence_reg == I915_FENCE_REG_NONE) {
1795 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1796 return false;
1797 }
1798
1799 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1800 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1801 return false;
1802 }
1803
1804 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1805 S3D_ENABLE) {
1806 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1807 return false;
1808 }
1809
ca73b4f0 1810 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1811 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1812 return false;
1813 }
1814
a031d709 1815 dev_priv->psr.source_ok = true;
3f51e471
RV		 1816 return true;
1817}
1818
3d739d92 1819static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1820{
1821 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1822
3f51e471
RV		 1823 if (!intel_edp_psr_match_conditions(intel_dp) ||
1824 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1825 return;
1826
1827 /* Setup PSR once */
1828 intel_edp_psr_setup(intel_dp);
1829
1830 /* Enable PSR on the panel */
1831 intel_edp_psr_enable_sink(intel_dp);
1832
1833 /* Enable PSR on the host */
1834 intel_edp_psr_enable_source(intel_dp);
1835}
1836
3d739d92
RV		 1837void intel_edp_psr_enable(struct intel_dp *intel_dp)
1838{
1839 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1840
1841 if (intel_edp_psr_match_conditions(intel_dp) &&
1842 !intel_edp_is_psr_enabled(dev))
1843 intel_edp_psr_do_enable(intel_dp);
1844}
1845
2b28bb1b
RV		 1846void intel_edp_psr_disable(struct intel_dp *intel_dp)
1847{
1848 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1849 struct drm_i915_private *dev_priv = dev->dev_private;
1850
1851 if (!intel_edp_is_psr_enabled(dev))
1852 return;
1853
18b5992c
BW		 1854 I915_WRITE(EDP_PSR_CTL(dev),
1855 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1856
1857 /* Wait till PSR is idle */
18b5992c 1858 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1859 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1860 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1861}
1862
3d739d92
RV		 1863void intel_edp_psr_update(struct drm_device *dev)
1864{
1865 struct intel_encoder *encoder;
1866 struct intel_dp *intel_dp = NULL;
1867
1868 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1869 if (encoder->type == INTEL_OUTPUT_EDP) {
1870 intel_dp = enc_to_intel_dp(&encoder->base);
1871
a031d709 1872 if (!is_edp_psr(dev))
3d739d92
RV		 1873 return;
1874
1875 if (!intel_edp_psr_match_conditions(intel_dp))
1876 intel_edp_psr_disable(intel_dp);
1877 else
1878 if (!intel_edp_is_psr_enabled(dev))
1879 intel_edp_psr_do_enable(intel_dp);
1880 }
1881}
1882
e8cb4558 1883static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1884{
e8cb4558 1885 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1886 enum port port = dp_to_dig_port(intel_dp)->port;
1887 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1888
1889 /* Make sure the panel is off before trying to change the mode. But also
1890 * ensure that we have vdd while we switch off the panel. */
b3064154 1891 edp_panel_vdd_on(intel_dp);
4be73780 1892 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1893 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1894 intel_edp_panel_off(intel_dp);
b3064154 1895 edp_panel_vdd_off(intel_dp, true);
3739850b
DV		 1896
1897 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1898 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1899 intel_dp_link_down(intel_dp);
d240f20f
JB		 1900}
1901
2bd2ad64 1902static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1903{
2bd2ad64 1904 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1905 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1906 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1907
982a3866 1908 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1909 intel_dp_link_down(intel_dp);
b2634017
JB		 1910 if (!IS_VALLEYVIEW(dev))
1911 ironlake_edp_pll_off(intel_dp);
3739850b 1912 }
2bd2ad64
DV		 1913}
1914
e8cb4558 1915static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1916{
e8cb4558
DV		 1917 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1918 struct drm_device *dev = encoder->base.dev;
1919 struct drm_i915_private *dev_priv = dev->dev_private;
1920 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1921
0c33d8d7
DV		 1922 if (WARN_ON(dp_reg & DP_PORT_EN))
1923 return;
5d613501 1924
4be73780 1925 edp_panel_vdd_on(intel_dp);
f01eca2e 1926 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1927 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1928 intel_edp_panel_on(intel_dp);
1929 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1930 intel_dp_complete_link_train(intel_dp);
3ab9c637 1931 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1932}
89b667f8 1933
ecff4f3b
JN		 1934static void g4x_enable_dp(struct intel_encoder *encoder)
1935{
828f5c6e
JN		 1936 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1937
ecff4f3b 1938 intel_enable_dp(encoder);
4be73780 1939 intel_edp_backlight_on(intel_dp);
ab1f90f9 1940}
89b667f8 1941
ab1f90f9
JN		 1942static void vlv_enable_dp(struct intel_encoder *encoder)
1943{
828f5c6e
JN		 1944 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1945
4be73780 1946 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1947}
1948
ecff4f3b 1949static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1950{
1951 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1952 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1953
1954 if (dport->port == PORT_A)
1955 ironlake_edp_pll_on(intel_dp);
1956}
1957
1958static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1959{
2bd2ad64 1960 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1961 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1962 struct drm_device *dev = encoder->base.dev;
89b667f8 1963 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1964 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1965 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1966 int pipe = intel_crtc->pipe;
bf13e81b 1967 struct edp_power_seq power_seq;
ab1f90f9 1968 u32 val;
a4fc5ed6 1969
ab1f90f9 1970 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1971
ab3c759a 1972 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1973 val = 0;
1974 if (pipe)
1975 val |= (1<<21);
1976 else
1977 val &= ~(1<<21);
1978 val |= 0x001000c4;
ab3c759a
CML		 1979 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1980 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1981 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1982
ab1f90f9
JN		 1983 mutex_unlock(&dev_priv->dpio_lock);
1984
2cac613b
ID		 1985 if (is_edp(intel_dp)) {
1986 /* init power sequencer on this pipe and port */
1987 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1988 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1989 &power_seq);
1990 }
bf13e81b 1991
ab1f90f9
JN		 1992 intel_enable_dp(encoder);
1993
e4607fcf 1994 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1995}
1996
ecff4f3b 1997static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1998{
1999 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2000 struct drm_device *dev = encoder->base.dev;
2001 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2002 struct intel_crtc *intel_crtc =
2003 to_intel_crtc(encoder->base.crtc);
e4607fcf 2004 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2005 int pipe = intel_crtc->pipe;
89b667f8 2006
89b667f8 2007 /* Program Tx lane resets to default */
0980a60f 2008 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2009 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2010 DPIO_PCS_TX_LANE2_RESET |
2011 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2012 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2013 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2014 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2015 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2016 DPIO_PCS_CLK_SOFT_RESET);
2017
2018 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2019 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2020 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2021 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2022 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2023}
2024
2025/*
df0c237d
JB		 2026 * Native read with retry for link status and receiver capability reads for
2027 * cases where the sink may still be asleep.
9d1a1031
JN		 2028 *
2029 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2030 * supposed to retry 3 times per the spec.
a4fc5ed6 2031 */
9d1a1031
JN		 2032static ssize_t
2033intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2034 void *buffer, size_t size)
a4fc5ed6 2035{
9d1a1031
JN		 2036 ssize_t ret;
2037 int i;
61da5fab 2038
61da5fab 2039 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2040 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2041 if (ret == size)
2042 return ret;
61da5fab
JB		 2043 msleep(1);
2044 }
a4fc5ed6 2045
9d1a1031 2046 return ret;
a4fc5ed6
KP		 2047}
2048
2049/*
2050 * Fetch AUX CH registers 0x202 - 0x207 which contain
2051 * link status information
2052 */
2053static bool
93f62dad 2054intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2055{
9d1a1031
JN		 2056 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2057 DP_LANE0_1_STATUS,
2058 link_status,
2059 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2060}
2061
a4fc5ed6
KP		 2062/*
2063 * These are source-specific values; current Intel hardware supports
2064 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2065 */
a4fc5ed6
KP		 2066
2067static uint8_t
1a2eb460 2068intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2069{
30add22d 2070 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2071 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2072
8f93f4f1 2073 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 2074 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2075 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2076 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2077 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2078 return DP_TRAIN_VOLTAGE_SWING_1200;
2079 else
2080 return DP_TRAIN_VOLTAGE_SWING_800;
2081}
2082
2083static uint8_t
2084intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2085{
30add22d 2086 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2087 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2088
8f93f4f1
PZ		 2089 if (IS_BROADWELL(dev)) {
2090 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2091 case DP_TRAIN_VOLTAGE_SWING_400:
2092 case DP_TRAIN_VOLTAGE_SWING_600:
2093 return DP_TRAIN_PRE_EMPHASIS_6;
2094 case DP_TRAIN_VOLTAGE_SWING_800:
2095 return DP_TRAIN_PRE_EMPHASIS_3_5;
2096 case DP_TRAIN_VOLTAGE_SWING_1200:
2097 default:
2098 return DP_TRAIN_PRE_EMPHASIS_0;
2099 }
2100 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 2101 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2102 case DP_TRAIN_VOLTAGE_SWING_400:
2103 return DP_TRAIN_PRE_EMPHASIS_9_5;
2104 case DP_TRAIN_VOLTAGE_SWING_600:
2105 return DP_TRAIN_PRE_EMPHASIS_6;
2106 case DP_TRAIN_VOLTAGE_SWING_800:
2107 return DP_TRAIN_PRE_EMPHASIS_3_5;
2108 case DP_TRAIN_VOLTAGE_SWING_1200:
2109 default:
2110 return DP_TRAIN_PRE_EMPHASIS_0;
2111 }
e2fa6fba
P		 2112 } else if (IS_VALLEYVIEW(dev)) {
2113 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2114 case DP_TRAIN_VOLTAGE_SWING_400:
2115 return DP_TRAIN_PRE_EMPHASIS_9_5;
2116 case DP_TRAIN_VOLTAGE_SWING_600:
2117 return DP_TRAIN_PRE_EMPHASIS_6;
2118 case DP_TRAIN_VOLTAGE_SWING_800:
2119 return DP_TRAIN_PRE_EMPHASIS_3_5;
2120 case DP_TRAIN_VOLTAGE_SWING_1200:
2121 default:
2122 return DP_TRAIN_PRE_EMPHASIS_0;
2123 }
bc7d38a4 2124 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2125 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2126 case DP_TRAIN_VOLTAGE_SWING_400:
2127 return DP_TRAIN_PRE_EMPHASIS_6;
2128 case DP_TRAIN_VOLTAGE_SWING_600:
2129 case DP_TRAIN_VOLTAGE_SWING_800:
2130 return DP_TRAIN_PRE_EMPHASIS_3_5;
2131 default:
2132 return DP_TRAIN_PRE_EMPHASIS_0;
2133 }
2134 } else {
2135 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2136 case DP_TRAIN_VOLTAGE_SWING_400:
2137 return DP_TRAIN_PRE_EMPHASIS_6;
2138 case DP_TRAIN_VOLTAGE_SWING_600:
2139 return DP_TRAIN_PRE_EMPHASIS_6;
2140 case DP_TRAIN_VOLTAGE_SWING_800:
2141 return DP_TRAIN_PRE_EMPHASIS_3_5;
2142 case DP_TRAIN_VOLTAGE_SWING_1200:
2143 default:
2144 return DP_TRAIN_PRE_EMPHASIS_0;
2145 }
a4fc5ed6
KP		 2146 }
2147}
2148
e2fa6fba
P		 2149static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2150{
2151 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2152 struct drm_i915_private *dev_priv = dev->dev_private;
2153 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2154 struct intel_crtc *intel_crtc =
2155 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2156 unsigned long demph_reg_value, preemph_reg_value,
2157 uniqtranscale_reg_value;
2158 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2159 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2160 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2161
2162 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2163 case DP_TRAIN_PRE_EMPHASIS_0:
2164 preemph_reg_value = 0x0004000;
2165 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2166 case DP_TRAIN_VOLTAGE_SWING_400:
2167 demph_reg_value = 0x2B405555;
2168 uniqtranscale_reg_value = 0x552AB83A;
2169 break;
2170 case DP_TRAIN_VOLTAGE_SWING_600:
2171 demph_reg_value = 0x2B404040;
2172 uniqtranscale_reg_value = 0x5548B83A;
2173 break;
2174 case DP_TRAIN_VOLTAGE_SWING_800:
2175 demph_reg_value = 0x2B245555;
2176 uniqtranscale_reg_value = 0x5560B83A;
2177 break;
2178 case DP_TRAIN_VOLTAGE_SWING_1200:
2179 demph_reg_value = 0x2B405555;
2180 uniqtranscale_reg_value = 0x5598DA3A;
2181 break;
2182 default:
2183 return 0;
2184 }
2185 break;
2186 case DP_TRAIN_PRE_EMPHASIS_3_5:
2187 preemph_reg_value = 0x0002000;
2188 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2189 case DP_TRAIN_VOLTAGE_SWING_400:
2190 demph_reg_value = 0x2B404040;
2191 uniqtranscale_reg_value = 0x5552B83A;
2192 break;
2193 case DP_TRAIN_VOLTAGE_SWING_600:
2194 demph_reg_value = 0x2B404848;
2195 uniqtranscale_reg_value = 0x5580B83A;
2196 break;
2197 case DP_TRAIN_VOLTAGE_SWING_800:
2198 demph_reg_value = 0x2B404040;
2199 uniqtranscale_reg_value = 0x55ADDA3A;
2200 break;
2201 default:
2202 return 0;
2203 }
2204 break;
2205 case DP_TRAIN_PRE_EMPHASIS_6:
2206 preemph_reg_value = 0x0000000;
2207 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2208 case DP_TRAIN_VOLTAGE_SWING_400:
2209 demph_reg_value = 0x2B305555;
2210 uniqtranscale_reg_value = 0x5570B83A;
2211 break;
2212 case DP_TRAIN_VOLTAGE_SWING_600:
2213 demph_reg_value = 0x2B2B4040;
2214 uniqtranscale_reg_value = 0x55ADDA3A;
2215 break;
2216 default:
2217 return 0;
2218 }
2219 break;
2220 case DP_TRAIN_PRE_EMPHASIS_9_5:
2221 preemph_reg_value = 0x0006000;
2222 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2223 case DP_TRAIN_VOLTAGE_SWING_400:
2224 demph_reg_value = 0x1B405555;
2225 uniqtranscale_reg_value = 0x55ADDA3A;
2226 break;
2227 default:
2228 return 0;
2229 }
2230 break;
2231 default:
2232 return 0;
2233 }
2234
0980a60f 2235 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2236 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2237 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2238 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2239 uniqtranscale_reg_value);
ab3c759a
CML		 2240 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2241 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2242 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2243 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2244 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2245
2246 return 0;
2247}
2248
a4fc5ed6 2249static void
0301b3ac
JN		 2250intel_get_adjust_train(struct intel_dp *intel_dp,
2251 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2252{
2253 uint8_t v = 0;
2254 uint8_t p = 0;
2255 int lane;
1a2eb460
KP		 2256 uint8_t voltage_max;
2257 uint8_t preemph_max;
a4fc5ed6 2258
33a34e4e 2259 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2260 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2261 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2262
2263 if (this_v > v)
2264 v = this_v;
2265 if (this_p > p)
2266 p = this_p;
2267 }
2268
1a2eb460 2269 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2270 if (v >= voltage_max)
2271 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2272
1a2eb460
KP		 2273 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2274 if (p >= preemph_max)
2275 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2276
2277 for (lane = 0; lane < 4; lane++)
33a34e4e 2278 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2279}
2280
2281static uint32_t
f0a3424e 2282intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2283{
3cf2efb1 2284 uint32_t signal_levels = 0;
a4fc5ed6 2285
3cf2efb1 2286 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2287 case DP_TRAIN_VOLTAGE_SWING_400:
2288 default:
2289 signal_levels |= DP_VOLTAGE_0_4;
2290 break;
2291 case DP_TRAIN_VOLTAGE_SWING_600:
2292 signal_levels |= DP_VOLTAGE_0_6;
2293 break;
2294 case DP_TRAIN_VOLTAGE_SWING_800:
2295 signal_levels |= DP_VOLTAGE_0_8;
2296 break;
2297 case DP_TRAIN_VOLTAGE_SWING_1200:
2298 signal_levels |= DP_VOLTAGE_1_2;
2299 break;
2300 }
3cf2efb1 2301 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2302 case DP_TRAIN_PRE_EMPHASIS_0:
2303 default:
2304 signal_levels |= DP_PRE_EMPHASIS_0;
2305 break;
2306 case DP_TRAIN_PRE_EMPHASIS_3_5:
2307 signal_levels |= DP_PRE_EMPHASIS_3_5;
2308 break;
2309 case DP_TRAIN_PRE_EMPHASIS_6:
2310 signal_levels |= DP_PRE_EMPHASIS_6;
2311 break;
2312 case DP_TRAIN_PRE_EMPHASIS_9_5:
2313 signal_levels |= DP_PRE_EMPHASIS_9_5;
2314 break;
2315 }
2316 return signal_levels;
2317}
2318
e3421a18
ZW		 2319/* Gen6's DP voltage swing and pre-emphasis control */
2320static uint32_t
2321intel_gen6_edp_signal_levels(uint8_t train_set)
2322{
3c5a62b5
YL		 2323 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2324 DP_TRAIN_PRE_EMPHASIS_MASK);
2325 switch (signal_levels) {
e3421a18 2326 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2327 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2328 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2329 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2330 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2331 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2332 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2333 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2334 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2335 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2336 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2337 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2338 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2339 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2340 default:
3c5a62b5
YL		 2341 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2342 "0x%x\n", signal_levels);
2343 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2344 }
2345}
2346
1a2eb460
KP		 2347/* Gen7's DP voltage swing and pre-emphasis control */
2348static uint32_t
2349intel_gen7_edp_signal_levels(uint8_t train_set)
2350{
2351 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2352 DP_TRAIN_PRE_EMPHASIS_MASK);
2353 switch (signal_levels) {
2354 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2355 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2356 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2357 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2358 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2359 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2360
2361 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2362 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2363 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2364 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2365
2366 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2367 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2368 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2369 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2370
2371 default:
2372 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2373 "0x%x\n", signal_levels);
2374 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2375 }
2376}
2377
d6c0d722
PZ		 2378/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2379static uint32_t
f0a3424e 2380intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2381{
d6c0d722
PZ		 2382 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2383 DP_TRAIN_PRE_EMPHASIS_MASK);
2384 switch (signal_levels) {
2385 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2386 return DDI_BUF_EMP_400MV_0DB_HSW;
2387 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2388 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2389 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2390 return DDI_BUF_EMP_400MV_6DB_HSW;
2391 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2392 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2393
d6c0d722
PZ		 2394 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2395 return DDI_BUF_EMP_600MV_0DB_HSW;
2396 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2397 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2398 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2399 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2400
d6c0d722
PZ		 2401 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2402 return DDI_BUF_EMP_800MV_0DB_HSW;
2403 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2404 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2405 default:
2406 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2407 "0x%x\n", signal_levels);
2408 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2409 }
a4fc5ed6
KP		 2410}
2411
8f93f4f1
PZ		 2412static uint32_t
2413intel_bdw_signal_levels(uint8_t train_set)
2414{
2415 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2416 DP_TRAIN_PRE_EMPHASIS_MASK);
2417 switch (signal_levels) {
2418 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2419 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2420 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2421 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2422 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2423 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2424
2425 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2426 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2427 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2428 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2429 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2430 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2431
2432 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2433 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2434 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2435 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2436
2437 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2438 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2439
2440 default:
2441 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2442 "0x%x\n", signal_levels);
2443 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2444 }
2445}
2446
f0a3424e
PZ		 2447/* Properly updates "DP" with the correct signal levels. */
2448static void
2449intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2450{
2451 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2452 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2453 struct drm_device *dev = intel_dig_port->base.base.dev;
2454 uint32_t signal_levels, mask;
2455 uint8_t train_set = intel_dp->train_set[0];
2456
8f93f4f1
PZ		 2457 if (IS_BROADWELL(dev)) {
2458 signal_levels = intel_bdw_signal_levels(train_set);
2459 mask = DDI_BUF_EMP_MASK;
2460 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2461 signal_levels = intel_hsw_signal_levels(train_set);
2462 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2463 } else if (IS_VALLEYVIEW(dev)) {
2464 signal_levels = intel_vlv_signal_levels(intel_dp);
2465 mask = 0;
bc7d38a4 2466 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2467 signal_levels = intel_gen7_edp_signal_levels(train_set);
2468 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2469 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2470 signal_levels = intel_gen6_edp_signal_levels(train_set);
2471 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2472 } else {
2473 signal_levels = intel_gen4_signal_levels(train_set);
2474 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2475 }
2476
2477 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2478
2479 *DP = (*DP & ~mask) | signal_levels;
2480}
2481
a4fc5ed6 2482static bool
ea5b213a 2483intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2484 uint32_t *DP,
58e10eb9 2485 uint8_t dp_train_pat)
a4fc5ed6 2486{
174edf1f
PZ		 2487 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2488 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2489 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2490 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2491 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2492 int ret, len;
a4fc5ed6 2493
22b8bf17 2494 if (HAS_DDI(dev)) {
3ab9c637 2495 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2496
2497 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2498 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2499 else
2500 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2501
2502 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2503 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2504 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2505 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2506
2507 break;
2508 case DP_TRAINING_PATTERN_1:
2509 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2510 break;
2511 case DP_TRAINING_PATTERN_2:
2512 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2513 break;
2514 case DP_TRAINING_PATTERN_3:
2515 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2516 break;
2517 }
174edf1f 2518 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2519
bc7d38a4 2520 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2521 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2522
2523 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2524 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2525 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2526 break;
2527 case DP_TRAINING_PATTERN_1:
70aff66c 2528 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2529 break;
2530 case DP_TRAINING_PATTERN_2:
70aff66c 2531 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2532 break;
2533 case DP_TRAINING_PATTERN_3:
2534 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2535 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2536 break;
2537 }
2538
2539 } else {
70aff66c 2540 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2541
2542 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2543 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2544 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2545 break;
2546 case DP_TRAINING_PATTERN_1:
70aff66c 2547 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2548 break;
2549 case DP_TRAINING_PATTERN_2:
70aff66c 2550 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2551 break;
2552 case DP_TRAINING_PATTERN_3:
2553 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2554 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2555 break;
2556 }
2557 }
2558
70aff66c 2559 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2560 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2561
2cdfe6c8
JN		 2562 buf[0] = dp_train_pat;
2563 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2564 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2565 /* don't write DP_TRAINING_LANEx_SET on disable */
2566 len = 1;
2567 } else {
2568 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2569 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2570 len = intel_dp->lane_count + 1;
47ea7542 2571 }
a4fc5ed6 2572
9d1a1031
JN		 2573 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2574 buf, len);
2cdfe6c8
JN		 2575
2576 return ret == len;
a4fc5ed6
KP		 2577}
2578
70aff66c
JN		 2579static bool
2580intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2581 uint8_t dp_train_pat)
2582{
953d22e8 2583 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2584 intel_dp_set_signal_levels(intel_dp, DP);
2585 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2586}
2587
2588static bool
2589intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2590 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2591{
2592 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2593 struct drm_device *dev = intel_dig_port->base.base.dev;
2594 struct drm_i915_private *dev_priv = dev->dev_private;
2595 int ret;
2596
2597 intel_get_adjust_train(intel_dp, link_status);
2598 intel_dp_set_signal_levels(intel_dp, DP);
2599
2600 I915_WRITE(intel_dp->output_reg, *DP);
2601 POSTING_READ(intel_dp->output_reg);
2602
9d1a1031
JN		 2603 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2604 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 2605
2606 return ret == intel_dp->lane_count;
2607}
2608
3ab9c637
ID		 2609static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2610{
2611 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2612 struct drm_device *dev = intel_dig_port->base.base.dev;
2613 struct drm_i915_private *dev_priv = dev->dev_private;
2614 enum port port = intel_dig_port->port;
2615 uint32_t val;
2616
2617 if (!HAS_DDI(dev))
2618 return;
2619
2620 val = I915_READ(DP_TP_CTL(port));
2621 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2622 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2623 I915_WRITE(DP_TP_CTL(port), val);
2624
2625 /*
2626 * On PORT_A we can have only eDP in SST mode. There the only reason
2627 * we need to set idle transmission mode is to work around a HW issue
2628 * where we enable the pipe while not in idle link-training mode.
2629 * In this case there is requirement to wait for a minimum number of
2630 * idle patterns to be sent.
2631 */
2632 if (port == PORT_A)
2633 return;
2634
2635 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2636 1))
2637 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2638}
2639
33a34e4e 2640/* Enable corresponding port and start training pattern 1 */
c19b0669 2641void
33a34e4e 2642intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2643{
da63a9f2 2644 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2645 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2646 int i;
2647 uint8_t voltage;
cdb0e95b 2648 int voltage_tries, loop_tries;
ea5b213a 2649 uint32_t DP = intel_dp->DP;
6aba5b6c 2650 uint8_t link_config[2];
a4fc5ed6 2651
affa9354 2652 if (HAS_DDI(dev))
c19b0669
PZ		 2653 intel_ddi_prepare_link_retrain(encoder);
2654
3cf2efb1 2655 /* Write the link configuration data */
6aba5b6c
JN		 2656 link_config[0] = intel_dp->link_bw;
2657 link_config[1] = intel_dp->lane_count;
2658 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2659 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 2660 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 2661
2662 link_config[0] = 0;
2663 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 2664 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2665
2666 DP |= DP_PORT_EN;
1a2eb460 2667
70aff66c
JN		 2668 /* clock recovery */
2669 if (!intel_dp_reset_link_train(intel_dp, &DP,
2670 DP_TRAINING_PATTERN_1 |
2671 DP_LINK_SCRAMBLING_DISABLE)) {
2672 DRM_ERROR("failed to enable link training\n");
2673 return;
2674 }
2675
a4fc5ed6 2676 voltage = 0xff;
cdb0e95b
KP		 2677 voltage_tries = 0;
2678 loop_tries = 0;
a4fc5ed6 2679 for (;;) {
70aff66c 2680 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2681
a7c9655f 2682 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2683 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2684 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2685 break;
93f62dad 2686 }
a4fc5ed6 2687
01916270 2688 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2689 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2690 break;
2691 }
2692
2693 /* Check to see if we've tried the max voltage */
2694 for (i = 0; i < intel_dp->lane_count; i++)
2695 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2696 break;
3b4f819d 2697 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2698 ++loop_tries;
2699 if (loop_tries == 5) {
3def84b3 2700 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2701 break;
2702 }
70aff66c
JN		 2703 intel_dp_reset_link_train(intel_dp, &DP,
2704 DP_TRAINING_PATTERN_1 |
2705 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2706 voltage_tries = 0;
2707 continue;
2708 }
a4fc5ed6 2709
3cf2efb1 2710 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2711 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2712 ++voltage_tries;
b06fbda3 2713 if (voltage_tries == 5) {
3def84b3 2714 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2715 break;
2716 }
2717 } else
2718 voltage_tries = 0;
2719 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2720
70aff66c
JN		 2721 /* Update training set as requested by target */
2722 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2723 DRM_ERROR("failed to update link training\n");
2724 break;
2725 }
a4fc5ed6
KP		 2726 }
2727
33a34e4e
JB		 2728 intel_dp->DP = DP;
2729}
2730
c19b0669 2731void
33a34e4e
JB		 2732intel_dp_complete_link_train(struct intel_dp *intel_dp)
2733{
33a34e4e 2734 bool channel_eq = false;
37f80975 2735 int tries, cr_tries;
33a34e4e 2736 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 2737 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2738
2739 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2740 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2741 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 2742
a4fc5ed6 2743 /* channel equalization */
70aff66c 2744 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2745 training_pattern |
70aff66c
JN		 2746 DP_LINK_SCRAMBLING_DISABLE)) {
2747 DRM_ERROR("failed to start channel equalization\n");
2748 return;
2749 }
2750
a4fc5ed6 2751 tries = 0;
37f80975 2752 cr_tries = 0;
a4fc5ed6
KP		 2753 channel_eq = false;
2754 for (;;) {
70aff66c 2755 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2756
37f80975
JB		 2757 if (cr_tries > 5) {
2758 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2759 break;
2760 }
2761
a7c9655f 2762 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2763 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2764 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2765 break;
70aff66c 2766 }
a4fc5ed6 2767
37f80975 2768 /* Make sure clock is still ok */
01916270 2769 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2770 intel_dp_start_link_train(intel_dp);
70aff66c 2771 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2772 training_pattern |
70aff66c 2773 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2774 cr_tries++;
2775 continue;
2776 }
2777
1ffdff13 2778 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2779 channel_eq = true;
2780 break;
2781 }
a4fc5ed6 2782
37f80975
JB		 2783 /* Try 5 times, then try clock recovery if that fails */
2784 if (tries > 5) {
2785 intel_dp_link_down(intel_dp);
2786 intel_dp_start_link_train(intel_dp);
70aff66c 2787 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2788 training_pattern |
70aff66c 2789 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2790 tries = 0;
2791 cr_tries++;
2792 continue;
2793 }
a4fc5ed6 2794
70aff66c
JN		 2795 /* Update training set as requested by target */
2796 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2797 DRM_ERROR("failed to update link training\n");
2798 break;
2799 }
3cf2efb1 2800 ++tries;
869184a6 2801 }
3cf2efb1 2802
3ab9c637
ID		 2803 intel_dp_set_idle_link_train(intel_dp);
2804
2805 intel_dp->DP = DP;
2806
d6c0d722 2807 if (channel_eq)
07f42258 2808 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2809
3ab9c637
ID		 2810}
2811
2812void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2813{
70aff66c 2814 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2815 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2816}
2817
2818static void
ea5b213a 2819intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2820{
da63a9f2 2821 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2822 enum port port = intel_dig_port->port;
da63a9f2 2823 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2824 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2825 struct intel_crtc *intel_crtc =
2826 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2827 uint32_t DP = intel_dp->DP;
a4fc5ed6 2828
c19b0669
PZ		 2829 /*
2830 * DDI code has a strict mode set sequence and we should try to respect
2831 * it, otherwise we might hang the machine in many different ways. So we
2832 * really should be disabling the port only on a complete crtc_disable
2833 * sequence. This function is just called under two conditions on DDI
2834 * code:
2835 * - Link train failed while doing crtc_enable, and on this case we
2836 * really should respect the mode set sequence and wait for a
2837 * crtc_disable.
2838 * - Someone turned the monitor off and intel_dp_check_link_status
2839 * called us. We don't need to disable the whole port on this case, so
2840 * when someone turns the monitor on again,
2841 * intel_ddi_prepare_link_retrain will take care of redoing the link
2842 * train.
2843 */
affa9354 2844 if (HAS_DDI(dev))
c19b0669
PZ		 2845 return;
2846
0c33d8d7 2847 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2848 return;
2849
28c97730 2850 DRM_DEBUG_KMS("\n");
32f9d658 2851
bc7d38a4 2852 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2853 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2854 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2855 } else {
2856 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2857 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2858 }
fe255d00 2859 POSTING_READ(intel_dp->output_reg);
5eb08b69 2860
ab527efc
DV		 2861 /* We don't really know why we're doing this */
2862 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2863
493a7081 2864 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2865 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2866 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2867
5bddd17f
EA		 2868 /* Hardware workaround: leaving our transcoder select
2869 * set to transcoder B while it's off will prevent the
2870 * corresponding HDMI output on transcoder A.
2871 *
2872 * Combine this with another hardware workaround:
2873 * transcoder select bit can only be cleared while the
2874 * port is enabled.
2875 */
2876 DP &= ~DP_PIPEB_SELECT;
2877 I915_WRITE(intel_dp->output_reg, DP);
2878
2879 /* Changes to enable or select take place the vblank
2880 * after being written.
2881 */
ff50afe9
DV		 2882 if (WARN_ON(crtc == NULL)) {
2883 /* We should never try to disable a port without a crtc
2884 * attached. For paranoia keep the code around for a
2885 * bit. */
31acbcc4
CW		 2886 POSTING_READ(intel_dp->output_reg);
2887 msleep(50);
2888 } else
ab527efc 2889 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2890 }
2891
832afda6 2892 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2893 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2894 POSTING_READ(intel_dp->output_reg);
f01eca2e 2895 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2896}
2897
26d61aad
KP		 2898static bool
2899intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2900{
a031d709
RV		 2901 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2902 struct drm_device *dev = dig_port->base.base.dev;
2903 struct drm_i915_private *dev_priv = dev->dev_private;
2904
577c7a50
DL		 2905 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2906
9d1a1031
JN		 2907 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
2908 sizeof(intel_dp->dpcd)) < 0)
edb39244 2909 return false; /* aux transfer failed */
92fd8fd1 2910
577c7a50
DL		 2911 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2912 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2913 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2914
edb39244
AJ		 2915 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2916 return false; /* DPCD not present */
2917
2293bb5c
SK		 2918 /* Check if the panel supports PSR */
2919 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 2920 if (is_edp(intel_dp)) {
9d1a1031
JN		 2921 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
2922 intel_dp->psr_dpcd,
2923 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2924 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2925 dev_priv->psr.sink_support = true;
50003939 2926 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2927 }
50003939
JN		 2928 }
2929
06ea66b6
TP		 2930 /* Training Pattern 3 support */
2931 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2932 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2933 intel_dp->use_tps3 = true;
2934 DRM_DEBUG_KMS("Displayport TPS3 supported");
2935 } else
2936 intel_dp->use_tps3 = false;
2937
edb39244
AJ		 2938 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2939 DP_DWN_STRM_PORT_PRESENT))
2940 return true; /* native DP sink */
2941
2942 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2943 return true; /* no per-port downstream info */
2944
9d1a1031
JN		 2945 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
2946 intel_dp->downstream_ports,
2947 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 2948 return false; /* downstream port status fetch failed */
2949
2950 return true;
92fd8fd1
KP		 2951}
2952
0d198328
AJ		 2953static void
2954intel_dp_probe_oui(struct intel_dp *intel_dp)
2955{
2956 u8 buf[3];
2957
2958 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2959 return;
2960
4be73780 2961 edp_panel_vdd_on(intel_dp);
351cfc34 2962
9d1a1031 2963 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 2964 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2965 buf[0], buf[1], buf[2]);
2966
9d1a1031 2967 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 2968 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2969 buf[0], buf[1], buf[2]);
351cfc34 2970
4be73780 2971 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2972}
2973
d2e216d0
RV		 2974int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2975{
2976 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2977 struct drm_device *dev = intel_dig_port->base.base.dev;
2978 struct intel_crtc *intel_crtc =
2979 to_intel_crtc(intel_dig_port->base.base.crtc);
2980 u8 buf[1];
2981
9d1a1031 2982 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 2983 return -EAGAIN;
2984
2985 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2986 return -ENOTTY;
2987
9d1a1031
JN		 2988 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
2989 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 2990 return -EAGAIN;
2991
2992 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2993 intel_wait_for_vblank(dev, intel_crtc->pipe);
2994 intel_wait_for_vblank(dev, intel_crtc->pipe);
2995
9d1a1031 2996 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 2997 return -EAGAIN;
2998
9d1a1031 2999 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3000 return 0;
3001}
3002
a60f0e38
JB		 3003static bool
3004intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3005{
9d1a1031
JN		 3006 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3007 DP_DEVICE_SERVICE_IRQ_VECTOR,
3008 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3009}
3010
3011static void
3012intel_dp_handle_test_request(struct intel_dp *intel_dp)
3013{
3014 /* NAK by default */
9d1a1031 3015 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3016}
3017
a4fc5ed6
KP		 3018/*
3019 * According to DP spec
3020 * 5.1.2:
3021 * 1. Read DPCD
3022 * 2. Configure link according to Receiver Capabilities
3023 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3024 * 4. Check link status on receipt of hot-plug interrupt
3025 */
3026
00c09d70 3027void
ea5b213a 3028intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3029{
da63a9f2 3030 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3031 u8 sink_irq_vector;
93f62dad 3032 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3033
da63a9f2 3034 if (!intel_encoder->connectors_active)
d2b996ac 3035 return;
59cd09e1 3036
da63a9f2 3037 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3038 return;
3039
92fd8fd1 3040 /* Try to read receiver status if the link appears to be up */
93f62dad 3041 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3042 return;
3043 }
3044
92fd8fd1 3045 /* Now read the DPCD to see if it's actually running */
26d61aad 3046 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3047 return;
3048 }
3049
a60f0e38
JB		 3050 /* Try to read the source of the interrupt */
3051 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3052 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3053 /* Clear interrupt source */
9d1a1031
JN		 3054 drm_dp_dpcd_writeb(&intel_dp->aux,
3055 DP_DEVICE_SERVICE_IRQ_VECTOR,
3056 sink_irq_vector);
a60f0e38
JB		 3057
3058 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3059 intel_dp_handle_test_request(intel_dp);
3060 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3061 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3062 }
3063
1ffdff13 3064 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3065 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 3066 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 3067 intel_dp_start_link_train(intel_dp);
3068 intel_dp_complete_link_train(intel_dp);
3ab9c637 3069 intel_dp_stop_link_train(intel_dp);
33a34e4e 3070 }
a4fc5ed6 3071}
a4fc5ed6 3072
caf9ab24 3073/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3074static enum drm_connector_status
26d61aad 3075intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3076{
caf9ab24 3077 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3078 uint8_t type;
3079
3080 if (!intel_dp_get_dpcd(intel_dp))
3081 return connector_status_disconnected;
3082
3083 /* if there's no downstream port, we're done */
3084 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3085 return connector_status_connected;
caf9ab24
AJ		 3086
3087 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3088 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3089 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3090 uint8_t reg;
9d1a1031
JN		 3091
3092 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3093 &reg, 1) < 0)
caf9ab24 3094 return connector_status_unknown;
9d1a1031 3095
23235177
AJ		 3096 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3097 : connector_status_disconnected;
caf9ab24
AJ		 3098 }
3099
3100 /* If no HPD, poke DDC gently */
3101 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 3102 return connector_status_connected;
caf9ab24
AJ		 3103
3104 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3105 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3106 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3107 if (type == DP_DS_PORT_TYPE_VGA ||
3108 type == DP_DS_PORT_TYPE_NON_EDID)
3109 return connector_status_unknown;
3110 } else {
3111 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3112 DP_DWN_STRM_PORT_TYPE_MASK;
3113 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3114 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3115 return connector_status_unknown;
3116 }
caf9ab24
AJ		 3117
3118 /* Anything else is out of spec, warn and ignore */
3119 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3120 return connector_status_disconnected;
71ba9000
AJ		 3121}
3122
5eb08b69 3123static enum drm_connector_status
a9756bb5 3124ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3125{
30add22d 3126 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3127 struct drm_i915_private *dev_priv = dev->dev_private;
3128 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3129 enum drm_connector_status status;
3130
fe16d949
CW		 3131 /* Can't disconnect eDP, but you can close the lid... */
3132 if (is_edp(intel_dp)) {
30add22d 3133 status = intel_panel_detect(dev);
fe16d949
CW		 3134 if (status == connector_status_unknown)
3135 status = connector_status_connected;
3136 return status;
3137 }
01cb9ea6 3138
1b469639
DL		 3139 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3140 return connector_status_disconnected;
3141
26d61aad 3142 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3143}
3144
a4fc5ed6 3145static enum drm_connector_status
a9756bb5 3146g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3147{
30add22d 3148 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3149 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3150 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3151 uint32_t bit;
5eb08b69 3152
35aad75f
JB		 3153 /* Can't disconnect eDP, but you can close the lid... */
3154 if (is_edp(intel_dp)) {
3155 enum drm_connector_status status;
3156
3157 status = intel_panel_detect(dev);
3158 if (status == connector_status_unknown)
3159 status = connector_status_connected;
3160 return status;
3161 }
3162
232a6ee9
TP		 3163 if (IS_VALLEYVIEW(dev)) {
3164 switch (intel_dig_port->port) {
3165 case PORT_B:
3166 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3167 break;
3168 case PORT_C:
3169 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3170 break;
3171 case PORT_D:
3172 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3173 break;
3174 default:
3175 return connector_status_unknown;
3176 }
3177 } else {
3178 switch (intel_dig_port->port) {
3179 case PORT_B:
3180 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3181 break;
3182 case PORT_C:
3183 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3184 break;
3185 case PORT_D:
3186 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3187 break;
3188 default:
3189 return connector_status_unknown;
3190 }
a4fc5ed6
KP		 3191 }
3192
10f76a38 3193 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3194 return connector_status_disconnected;
3195
26d61aad 3196 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3197}
3198
8c241fef
KP		 3199static struct edid *
3200intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3201{
9cd300e0 3202 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3203
9cd300e0
JN		 3204 /* use cached edid if we have one */
3205 if (intel_connector->edid) {
9cd300e0
JN		 3206 /* invalid edid */
3207 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3208 return NULL;
3209
55e9edeb 3210 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3211 }
8c241fef 3212
9cd300e0 3213 return drm_get_edid(connector, adapter);
8c241fef
KP		 3214}
3215
3216static int
3217intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3218{
9cd300e0 3219 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3220
9cd300e0
JN		 3221 /* use cached edid if we have one */
3222 if (intel_connector->edid) {
3223 /* invalid edid */
3224 if (IS_ERR(intel_connector->edid))
3225 return 0;
3226
3227 return intel_connector_update_modes(connector,
3228 intel_connector->edid);
d6f24d0f
JB		 3229 }
3230
9cd300e0 3231 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3232}
3233
a9756bb5
ZW		 3234static enum drm_connector_status
3235intel_dp_detect(struct drm_connector *connector, bool force)
3236{
3237 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3238 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3239 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3240 struct drm_device *dev = connector->dev;
c8c8fb33 3241 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3242 enum drm_connector_status status;
671dedd2 3243 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3244 struct edid *edid = NULL;
3245
c8c8fb33
PZ		 3246 intel_runtime_pm_get(dev_priv);
3247
671dedd2
ID		 3248 power_domain = intel_display_port_power_domain(intel_encoder);
3249 intel_display_power_get(dev_priv, power_domain);
3250
164c8598
CW		 3251 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3252 connector->base.id, drm_get_connector_name(connector));
3253
a9756bb5
ZW		 3254 intel_dp->has_audio = false;
3255
3256 if (HAS_PCH_SPLIT(dev))
3257 status = ironlake_dp_detect(intel_dp);
3258 else
3259 status = g4x_dp_detect(intel_dp);
1b9be9d0 3260
a9756bb5 3261 if (status != connector_status_connected)
c8c8fb33 3262 goto out;
a9756bb5 3263
0d198328
AJ		 3264 intel_dp_probe_oui(intel_dp);
3265
c3e5f67b
DV		 3266 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3267 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3268 } else {
8c241fef 3269 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 3270 if (edid) {
3271 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3272 kfree(edid);
3273 }
a9756bb5
ZW		 3274 }
3275
d63885da
PZ		 3276 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3277 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3278 status = connector_status_connected;
3279
3280out:
671dedd2
ID		 3281 intel_display_power_put(dev_priv, power_domain);
3282
c8c8fb33 3283 intel_runtime_pm_put(dev_priv);
671dedd2 3284
c8c8fb33 3285 return status;
a4fc5ed6
KP		 3286}
3287
3288static int intel_dp_get_modes(struct drm_connector *connector)
3289{
df0e9248 3290 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3291 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3292 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3293 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3294 struct drm_device *dev = connector->dev;
671dedd2
ID		 3295 struct drm_i915_private *dev_priv = dev->dev_private;
3296 enum intel_display_power_domain power_domain;
32f9d658 3297 int ret;
a4fc5ed6
KP		 3298
3299 /* We should parse the EDID data and find out if it has an audio sink
3300 */
3301
671dedd2
ID		 3302 power_domain = intel_display_port_power_domain(intel_encoder);
3303 intel_display_power_get(dev_priv, power_domain);
3304
8c241fef 3305 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
671dedd2 3306 intel_display_power_put(dev_priv, power_domain);
f8779fda 3307 if (ret)
32f9d658
ZW		 3308 return ret;
3309
f8779fda 3310 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3311 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3312 struct drm_display_mode *mode;
dd06f90e
JN		 3313 mode = drm_mode_duplicate(dev,
3314 intel_connector->panel.fixed_mode);
f8779fda 3315 if (mode) {
32f9d658
ZW		 3316 drm_mode_probed_add(connector, mode);
3317 return 1;
3318 }
3319 }
3320 return 0;
a4fc5ed6
KP		 3321}
3322
1aad7ac0
CW		 3323static bool
3324intel_dp_detect_audio(struct drm_connector *connector)
3325{
3326 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3327 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3328 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3329 struct drm_device *dev = connector->dev;
3330 struct drm_i915_private *dev_priv = dev->dev_private;
3331 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3332 struct edid *edid;
3333 bool has_audio = false;
3334
671dedd2
ID		 3335 power_domain = intel_display_port_power_domain(intel_encoder);
3336 intel_display_power_get(dev_priv, power_domain);
3337
8c241fef 3338 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 3339 if (edid) {
3340 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3341 kfree(edid);
3342 }
3343
671dedd2
ID		 3344 intel_display_power_put(dev_priv, power_domain);
3345
1aad7ac0
CW		 3346 return has_audio;
3347}
3348
f684960e
CW		 3349static int
3350intel_dp_set_property(struct drm_connector *connector,
3351 struct drm_property *property,
3352 uint64_t val)
3353{
e953fd7b 3354 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3355 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3356 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3357 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3358 int ret;
3359
662595df 3360 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3361 if (ret)
3362 return ret;
3363
3f43c48d 3364 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3365 int i = val;
3366 bool has_audio;
3367
3368 if (i == intel_dp->force_audio)
f684960e
CW		 3369 return 0;
3370
1aad7ac0 3371 intel_dp->force_audio = i;
f684960e 3372
c3e5f67b 3373 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3374 has_audio = intel_dp_detect_audio(connector);
3375 else
c3e5f67b 3376 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3377
3378 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3379 return 0;
3380
1aad7ac0 3381 intel_dp->has_audio = has_audio;
f684960e
CW		 3382 goto done;
3383 }
3384
e953fd7b 3385 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3386 bool old_auto = intel_dp->color_range_auto;
3387 uint32_t old_range = intel_dp->color_range;
3388
55bc60db
VS		 3389 switch (val) {
3390 case INTEL_BROADCAST_RGB_AUTO:
3391 intel_dp->color_range_auto = true;
3392 break;
3393 case INTEL_BROADCAST_RGB_FULL:
3394 intel_dp->color_range_auto = false;
3395 intel_dp->color_range = 0;
3396 break;
3397 case INTEL_BROADCAST_RGB_LIMITED:
3398 intel_dp->color_range_auto = false;
3399 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3400 break;
3401 default:
3402 return -EINVAL;
3403 }
ae4edb80
DV		 3404
3405 if (old_auto == intel_dp->color_range_auto &&
3406 old_range == intel_dp->color_range)
3407 return 0;
3408
e953fd7b
CW		 3409 goto done;
3410 }
3411
53b41837
YN		 3412 if (is_edp(intel_dp) &&
3413 property == connector->dev->mode_config.scaling_mode_property) {
3414 if (val == DRM_MODE_SCALE_NONE) {
3415 DRM_DEBUG_KMS("no scaling not supported\n");
3416 return -EINVAL;
3417 }
3418
3419 if (intel_connector->panel.fitting_mode == val) {
3420 /* the eDP scaling property is not changed */
3421 return 0;
3422 }
3423 intel_connector->panel.fitting_mode = val;
3424
3425 goto done;
3426 }
3427
f684960e
CW		 3428 return -EINVAL;
3429
3430done:
c0c36b94
CW		 3431 if (intel_encoder->base.crtc)
3432 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3433
3434 return 0;
3435}
3436
a4fc5ed6 3437static void
73845adf 3438intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3439{
1d508706 3440 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3441
9cd300e0
JN		 3442 if (!IS_ERR_OR_NULL(intel_connector->edid))
3443 kfree(intel_connector->edid);
3444
acd8db10
PZ		 3445 /* Can't call is_edp() since the encoder may have been destroyed
3446 * already. */
3447 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3448 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3449
a4fc5ed6 3450 drm_connector_cleanup(connector);
55f78c43 3451 kfree(connector);
a4fc5ed6
KP		 3452}
3453
00c09d70 3454void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3455{
da63a9f2
PZ		 3456 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3457 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3458 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 3459
3460 i2c_del_adapter(&intel_dp->adapter);
3461 drm_encoder_cleanup(encoder);
bd943159
KP		 3462 if (is_edp(intel_dp)) {
3463 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3464 mutex_lock(&dev->mode_config.mutex);
4be73780 3465 edp_panel_vdd_off_sync(intel_dp);
bd173813 3466 mutex_unlock(&dev->mode_config.mutex);
bd943159 3467 }
da63a9f2 3468 kfree(intel_dig_port);
24d05927
DV		 3469}
3470
a4fc5ed6 3471static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3472 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3473 .detect = intel_dp_detect,
3474 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3475 .set_property = intel_dp_set_property,
73845adf 3476 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3477};
3478
3479static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3480 .get_modes = intel_dp_get_modes,
3481 .mode_valid = intel_dp_mode_valid,
df0e9248 3482 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3483};
3484
a4fc5ed6 3485static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3486 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3487};
3488
995b6762 3489static void
21d40d37 3490intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3491{
fa90ecef 3492 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3493
885a5014 3494 intel_dp_check_link_status(intel_dp);
c8110e52 3495}
6207937d 3496
e3421a18
ZW		 3497/* Return which DP Port should be selected for Transcoder DP control */
3498int
0206e353 3499intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3500{
3501 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3502 struct intel_encoder *intel_encoder;
3503 struct intel_dp *intel_dp;
e3421a18 3504
fa90ecef
PZ		 3505 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3506 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3507
fa90ecef
PZ		 3508 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3509 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3510 return intel_dp->output_reg;
e3421a18 3511 }
ea5b213a 3512
e3421a18
ZW		 3513 return -1;
3514}
3515
36e83a18 3516/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3517bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3518{
3519 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3520 union child_device_config *p_child;
36e83a18 3521 int i;
5d8a7752
VS		 3522 static const short port_mapping[] = {
3523 [PORT_B] = PORT_IDPB,
3524 [PORT_C] = PORT_IDPC,
3525 [PORT_D] = PORT_IDPD,
3526 };
36e83a18 3527
3b32a35b
VS		 3528 if (port == PORT_A)
3529 return true;
3530
41aa3448 3531 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3532 return false;
3533
41aa3448
RV		 3534 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3535 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3536
5d8a7752 3537 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3538 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3539 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3540 return true;
3541 }
3542 return false;
3543}
3544
f684960e
CW		 3545static void
3546intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3547{
53b41837
YN		 3548 struct intel_connector *intel_connector = to_intel_connector(connector);
3549
3f43c48d 3550 intel_attach_force_audio_property(connector);
e953fd7b 3551 intel_attach_broadcast_rgb_property(connector);
55bc60db 3552 intel_dp->color_range_auto = true;
53b41837
YN		 3553
3554 if (is_edp(intel_dp)) {
3555 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3556 drm_object_attach_property(
3557 &connector->base,
53b41837 3558 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3559 DRM_MODE_SCALE_ASPECT);
3560 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3561 }
f684960e
CW		 3562}
3563
dada1a9f
ID		 3564static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3565{
3566 intel_dp->last_power_cycle = jiffies;
3567 intel_dp->last_power_on = jiffies;
3568 intel_dp->last_backlight_off = jiffies;
3569}
3570
67a54566
DV		 3571static void
3572intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3573 struct intel_dp *intel_dp,
3574 struct edp_power_seq *out)
67a54566
DV		 3575{
3576 struct drm_i915_private *dev_priv = dev->dev_private;
3577 struct edp_power_seq cur, vbt, spec, final;
3578 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3579 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3580
3581 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3582 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3583 pp_on_reg = PCH_PP_ON_DELAYS;
3584 pp_off_reg = PCH_PP_OFF_DELAYS;
3585 pp_div_reg = PCH_PP_DIVISOR;
3586 } else {
bf13e81b
JN		 3587 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3588
3589 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3590 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3591 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3592 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3593 }
67a54566
DV		 3594
3595 /* Workaround: Need to write PP_CONTROL with the unlock key as
3596 * the very first thing. */
453c5420 3597 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3598 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3599
453c5420
JB		 3600 pp_on = I915_READ(pp_on_reg);
3601 pp_off = I915_READ(pp_off_reg);
3602 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3603
3604 /* Pull timing values out of registers */
3605 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3606 PANEL_POWER_UP_DELAY_SHIFT;
3607
3608 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3609 PANEL_LIGHT_ON_DELAY_SHIFT;
3610
3611 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3612 PANEL_LIGHT_OFF_DELAY_SHIFT;
3613
3614 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3615 PANEL_POWER_DOWN_DELAY_SHIFT;
3616
3617 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3618 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3619
3620 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3621 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3622
41aa3448 3623 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3624
3625 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3626 * our hw here, which are all in 100usec. */
3627 spec.t1_t3 = 210 * 10;
3628 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3629 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3630 spec.t10 = 500 * 10;
3631 /* This one is special and actually in units of 100ms, but zero
3632 * based in the hw (so we need to add 100 ms). But the sw vbt
3633 * table multiplies it with 1000 to make it in units of 100usec,
3634 * too. */
3635 spec.t11_t12 = (510 + 100) * 10;
3636
3637 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3638 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3639
3640 /* Use the max of the register settings and vbt. If both are
3641 * unset, fall back to the spec limits. */
3642#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3643 spec.field : \
3644 max(cur.field, vbt.field))
3645 assign_final(t1_t3);
3646 assign_final(t8);
3647 assign_final(t9);
3648 assign_final(t10);
3649 assign_final(t11_t12);
3650#undef assign_final
3651
3652#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3653 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3654 intel_dp->backlight_on_delay = get_delay(t8);
3655 intel_dp->backlight_off_delay = get_delay(t9);
3656 intel_dp->panel_power_down_delay = get_delay(t10);
3657 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3658#undef get_delay
3659
f30d26e4
JN		 3660 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3661 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3662 intel_dp->panel_power_cycle_delay);
3663
3664 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3665 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3666
3667 if (out)
3668 *out = final;
3669}
3670
3671static void
3672intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3673 struct intel_dp *intel_dp,
3674 struct edp_power_seq *seq)
3675{
3676 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3677 u32 pp_on, pp_off, pp_div, port_sel = 0;
3678 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3679 int pp_on_reg, pp_off_reg, pp_div_reg;
3680
3681 if (HAS_PCH_SPLIT(dev)) {
3682 pp_on_reg = PCH_PP_ON_DELAYS;
3683 pp_off_reg = PCH_PP_OFF_DELAYS;
3684 pp_div_reg = PCH_PP_DIVISOR;
3685 } else {
bf13e81b
JN		 3686 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3687
3688 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3689 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3690 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3691 }
3692
b2f19d1a
PZ		 3693 /*
3694 * And finally store the new values in the power sequencer. The
3695 * backlight delays are set to 1 because we do manual waits on them. For
3696 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3697 * we'll end up waiting for the backlight off delay twice: once when we
3698 * do the manual sleep, and once when we disable the panel and wait for
3699 * the PP_STATUS bit to become zero.
3700 */
f30d26e4 3701 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 3702 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3703 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 3704 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3705 /* Compute the divisor for the pp clock, simply match the Bspec
3706 * formula. */
453c5420 3707 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3708 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3709 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3710
3711 /* Haswell doesn't have any port selection bits for the panel
3712 * power sequencer any more. */
bc7d38a4 3713 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3714 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3715 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3716 else
3717 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3718 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3719 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3720 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3721 else
a24c144c 3722 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3723 }
3724
453c5420
JB		 3725 pp_on |= port_sel;
3726
3727 I915_WRITE(pp_on_reg, pp_on);
3728 I915_WRITE(pp_off_reg, pp_off);
3729 I915_WRITE(pp_div_reg, pp_div);
67a54566 3730
67a54566 3731 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3732 I915_READ(pp_on_reg),
3733 I915_READ(pp_off_reg),
3734 I915_READ(pp_div_reg));
f684960e
CW		 3735}
3736
ed92f0b2 3737static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 3738 struct intel_connector *intel_connector,
3739 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 3740{
3741 struct drm_connector *connector = &intel_connector->base;
3742 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3743 struct drm_device *dev = intel_dig_port->base.base.dev;
3744 struct drm_i915_private *dev_priv = dev->dev_private;
3745 struct drm_display_mode *fixed_mode = NULL;
ed92f0b2
PZ		 3746 bool has_dpcd;
3747 struct drm_display_mode *scan;
3748 struct edid *edid;
3749
3750 if (!is_edp(intel_dp))
3751 return true;
3752
ed92f0b2 3753 /* Cache DPCD and EDID for edp. */
4be73780 3754 edp_panel_vdd_on(intel_dp);
ed92f0b2 3755 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 3756 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 3757
3758 if (has_dpcd) {
3759 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3760 dev_priv->no_aux_handshake =
3761 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3762 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3763 } else {
3764 /* if this fails, presume the device is a ghost */
3765 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3766 return false;
3767 }
3768
3769 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 3770 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 3771
ed92f0b2
PZ		 3772 edid = drm_get_edid(connector, &intel_dp->adapter);
3773 if (edid) {
3774 if (drm_add_edid_modes(connector, edid)) {
3775 drm_mode_connector_update_edid_property(connector,
3776 edid);
3777 drm_edid_to_eld(connector, edid);
3778 } else {
3779 kfree(edid);
3780 edid = ERR_PTR(-EINVAL);
3781 }
3782 } else {
3783 edid = ERR_PTR(-ENOENT);
3784 }
3785 intel_connector->edid = edid;
3786
3787 /* prefer fixed mode from EDID if available */
3788 list_for_each_entry(scan, &connector->probed_modes, head) {
3789 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3790 fixed_mode = drm_mode_duplicate(dev, scan);
3791 break;
3792 }
3793 }
3794
3795 /* fallback to VBT if available for eDP */
3796 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3797 fixed_mode = drm_mode_duplicate(dev,
3798 dev_priv->vbt.lfp_lvds_vbt_mode);
3799 if (fixed_mode)
3800 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3801 }
3802
4b6ed685 3803 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
ed92f0b2
PZ		 3804 intel_panel_setup_backlight(connector);
3805
3806 return true;
3807}
3808
16c25533 3809bool
f0fec3f2
PZ		 3810intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3811 struct intel_connector *intel_connector)
a4fc5ed6 3812{
f0fec3f2
PZ		 3813 struct drm_connector *connector = &intel_connector->base;
3814 struct intel_dp *intel_dp = &intel_dig_port->dp;
3815 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3816 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3817 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3818 enum port port = intel_dig_port->port;
0095e6dc 3819 struct edp_power_seq power_seq = { 0 };
5eb08b69 3820 const char *name = NULL;
b2a14755 3821 int type, error;
a4fc5ed6 3822
ec5b01dd
DL		 3823 /* intel_dp vfuncs */
3824 if (IS_VALLEYVIEW(dev))
3825 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3826 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3827 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3828 else if (HAS_PCH_SPLIT(dev))
3829 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3830 else
3831 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3832
153b1100
DL		 3833 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3834
0767935e
DV		 3835 /* Preserve the current hw state. */
3836 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3837 intel_dp->attached_connector = intel_connector;
3d3dc149 3838
3b32a35b 3839 if (intel_dp_is_edp(dev, port))
b329530c 3840 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 3841 else
3842 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 3843
f7d24902
ID		 3844 /*
3845 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3846 * for DP the encoder type can be set by the caller to
3847 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3848 */
3849 if (type == DRM_MODE_CONNECTOR_eDP)
3850 intel_encoder->type = INTEL_OUTPUT_EDP;
3851
e7281eab
ID		 3852 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3853 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3854 port_name(port));
3855
b329530c 3856 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3857 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3858
a4fc5ed6
KP		 3859 connector->interlace_allowed = true;
3860 connector->doublescan_allowed = 0;
3861
f0fec3f2 3862 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 3863 edp_panel_vdd_work);
a4fc5ed6 3864
df0e9248 3865 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3866 drm_sysfs_connector_add(connector);
3867
affa9354 3868 if (HAS_DDI(dev))
bcbc889b
PZ		 3869 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3870 else
3871 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 3872 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 3873
a4fc5ed6 3874 /* Set up the DDC bus. */
ab9d7c30
PZ		 3875 switch (port) {
3876 case PORT_A:
1d843f9d 3877 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3878 name = "DPDDC-A";
3879 break;
3880 case PORT_B:
1d843f9d 3881 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3882 name = "DPDDC-B";
3883 break;
3884 case PORT_C:
1d843f9d 3885 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3886 name = "DPDDC-C";
3887 break;
3888 case PORT_D:
1d843f9d 3889 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3890 name = "DPDDC-D";
3891 break;
3892 default:
ad1c0b19 3893 BUG();
5eb08b69
ZW		 3894 }
3895
dada1a9f
ID		 3896 if (is_edp(intel_dp)) {
3897 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 3898 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 3899 }
0095e6dc 3900
9d1a1031
JN		 3901 intel_dp_aux_init(intel_dp, intel_connector);
3902
b2a14755
PZ		 3903 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3904 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3905 error, port_name(port));
c1f05264 3906
2b28bb1b
RV		 3907 intel_dp->psr_setup_done = false;
3908
0095e6dc 3909 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
15b1d171
PZ		 3910 i2c_del_adapter(&intel_dp->adapter);
3911 if (is_edp(intel_dp)) {
3912 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3913 mutex_lock(&dev->mode_config.mutex);
4be73780 3914 edp_panel_vdd_off_sync(intel_dp);
15b1d171
PZ		 3915 mutex_unlock(&dev->mode_config.mutex);
3916 }
b2f246a8
PZ		 3917 drm_sysfs_connector_remove(connector);
3918 drm_connector_cleanup(connector);
16c25533 3919 return false;
b2f246a8 3920 }
32f9d658 3921
f684960e
CW		 3922 intel_dp_add_properties(intel_dp, connector);
3923
a4fc5ed6
KP		 3924 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3925 * 0xd. Failure to do so will result in spurious interrupts being
3926 * generated on the port when a cable is not attached.
3927 */
3928 if (IS_G4X(dev) && !IS_GM45(dev)) {
3929 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3930 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3931 }
16c25533
PZ		 3932
3933 return true;
a4fc5ed6 3934}
f0fec3f2
PZ		 3935
3936void
3937intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3938{
3939 struct intel_digital_port *intel_dig_port;
3940 struct intel_encoder *intel_encoder;
3941 struct drm_encoder *encoder;
3942 struct intel_connector *intel_connector;
3943
b14c5679 3944 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3945 if (!intel_dig_port)
3946 return;
3947
b14c5679 3948 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3949 if (!intel_connector) {
3950 kfree(intel_dig_port);
3951 return;
3952 }
3953
3954 intel_encoder = &intel_dig_port->base;
3955 encoder = &intel_encoder->base;
3956
3957 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3958 DRM_MODE_ENCODER_TMDS);
3959
5bfe2ac0 3960 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3961 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3962 intel_encoder->disable = intel_disable_dp;
3963 intel_encoder->post_disable = intel_post_disable_dp;
3964 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3965 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3966 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3967 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3968 intel_encoder->pre_enable = vlv_pre_enable_dp;
3969 intel_encoder->enable = vlv_enable_dp;
3970 } else {
ecff4f3b
JN		 3971 intel_encoder->pre_enable = g4x_pre_enable_dp;
3972 intel_encoder->enable = g4x_enable_dp;
ab1f90f9 3973 }
f0fec3f2 3974
174edf1f 3975 intel_dig_port->port = port;
f0fec3f2
PZ		 3976 intel_dig_port->dp.output_reg = output_reg;
3977
00c09d70 3978 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3979 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3980 intel_encoder->cloneable = false;
3981 intel_encoder->hot_plug = intel_dp_hot_plug;
3982
15b1d171
PZ		 3983 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3984 drm_encoder_cleanup(encoder);
3985 kfree(intel_dig_port);
b2f246a8 3986 kfree(intel_connector);
15b1d171 3987 }
f0fec3f2 3988}
Ubuntu Artful kernel mirror