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drm/i915: Fix RGB color range property for PCH platforms
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
55/**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63static bool is_pch_edp(struct intel_dp *intel_dp)
64{
65 return intel_dp->is_pch_edp;
66}
67
1c95822a
AJ		 68/**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74static bool is_cpu_edp(struct intel_dp *intel_dp)
75{
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77}
78
30add22d 79static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
ea5b213a 80{
da63a9f2
PZ		 81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
82
83 return intel_dig_port->base.base.dev;
ea5b213a 84}
a4fc5ed6 85
df0e9248
CW		 86static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
87{
fa90ecef 88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 89}
90
814948ad
JB		 91/**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99{
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108}
109
ea5b213a 110static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 111
32f9d658 112void
0206e353 113intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 114 int *lane_num, int *link_bw)
32f9d658 115{
fa90ecef 116 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
32f9d658 117
ea5b213a 118 *lane_num = intel_dp->lane_count;
3b5c662e 119 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
32f9d658
ZW		 120}
121
94bf2ced
DV		 122int
123intel_edp_target_clock(struct intel_encoder *intel_encoder,
124 struct drm_display_mode *mode)
125{
fa90ecef 126 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
dd06f90e 127 struct intel_connector *intel_connector = intel_dp->attached_connector;
94bf2ced 128
dd06f90e
JN		 129 if (intel_connector->panel.fixed_mode)
130 return intel_connector->panel.fixed_mode->clock;
94bf2ced
DV		 131 else
132 return mode->clock;
133}
134
a4fc5ed6 135static int
ea5b213a 136intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 137{
7183dc29 138 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 139
140 switch (max_link_bw) {
141 case DP_LINK_BW_1_62:
142 case DP_LINK_BW_2_7:
143 break;
144 default:
145 max_link_bw = DP_LINK_BW_1_62;
146 break;
147 }
148 return max_link_bw;
149}
150
cd9dde44
AJ		 151/*
152 * The units on the numbers in the next two are... bizarre. Examples will
153 * make it clearer; this one parallels an example in the eDP spec.
154 *
155 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
156 *
157 * 270000 * 1 * 8 / 10 == 216000
158 *
159 * The actual data capacity of that configuration is 2.16Gbit/s, so the
160 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
161 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
162 * 119000. At 18bpp that's 2142000 kilobits per second.
163 *
164 * Thus the strange-looking division by 10 in intel_dp_link_required, to
165 * get the result in decakilobits instead of kilobits.
166 */
167
a4fc5ed6 168static int
c898261c 169intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 170{
cd9dde44 171 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 172}
173
fe27d53e
DA		 174static int
175intel_dp_max_data_rate(int max_link_clock, int max_lanes)
176{
177 return (max_link_clock * max_lanes * 8) / 10;
178}
179
c4867936
DV		 180static bool
181intel_dp_adjust_dithering(struct intel_dp *intel_dp,
182 struct drm_display_mode *mode,
cb1793ce 183 bool adjust_mode)
c4867936 184{
9fa5f652
PZ		 185 int max_link_clock =
186 drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
397fe157 187 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
c4867936
DV		 188 int max_rate, mode_rate;
189
190 mode_rate = intel_dp_link_required(mode->clock, 24);
191 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
192
193 if (mode_rate > max_rate) {
194 mode_rate = intel_dp_link_required(mode->clock, 18);
195 if (mode_rate > max_rate)
196 return false;
197
cb1793ce
DV		 198 if (adjust_mode)
199 mode->private_flags
c4867936
DV		 200 |= INTEL_MODE_DP_FORCE_6BPC;
201
202 return true;
203 }
204
205 return true;
206}
207
a4fc5ed6
KP		 208static int
209intel_dp_mode_valid(struct drm_connector *connector,
210 struct drm_display_mode *mode)
211{
df0e9248 212 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 213 struct intel_connector *intel_connector = to_intel_connector(connector);
214 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
a4fc5ed6 215
dd06f90e
JN		 216 if (is_edp(intel_dp) && fixed_mode) {
217 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 218 return MODE_PANEL;
219
dd06f90e 220 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43
ZY		 221 return MODE_PANEL;
222 }
223
cb1793ce 224 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 225 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 226
227 if (mode->clock < 10000)
228 return MODE_CLOCK_LOW;
229
0af78a2b
DV		 230 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
231 return MODE_H_ILLEGAL;
232
a4fc5ed6
KP		 233 return MODE_OK;
234}
235
236static uint32_t
237pack_aux(uint8_t *src, int src_bytes)
238{
239 int i;
240 uint32_t v = 0;
241
242 if (src_bytes > 4)
243 src_bytes = 4;
244 for (i = 0; i < src_bytes; i++)
245 v |= ((uint32_t) src[i]) << ((3-i) * 8);
246 return v;
247}
248
249static void
250unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
251{
252 int i;
253 if (dst_bytes > 4)
254 dst_bytes = 4;
255 for (i = 0; i < dst_bytes; i++)
256 dst[i] = src >> ((3-i) * 8);
257}
258
fb0f8fbf
KP		 259/* hrawclock is 1/4 the FSB frequency */
260static int
261intel_hrawclk(struct drm_device *dev)
262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 uint32_t clkcfg;
265
9473c8f4
VP		 266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev))
268 return 200;
269
fb0f8fbf
KP		 270 clkcfg = I915_READ(CLKCFG);
271 switch (clkcfg & CLKCFG_FSB_MASK) {
272 case CLKCFG_FSB_400:
273 return 100;
274 case CLKCFG_FSB_533:
275 return 133;
276 case CLKCFG_FSB_667:
277 return 166;
278 case CLKCFG_FSB_800:
279 return 200;
280 case CLKCFG_FSB_1067:
281 return 266;
282 case CLKCFG_FSB_1333:
283 return 333;
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600:
286 case CLKCFG_FSB_1600_ALT:
287 return 400;
288 default:
289 return 133;
290 }
291}
292
ebf33b18
KP		 293static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
294{
30add22d 295 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 296 struct drm_i915_private *dev_priv = dev->dev_private;
297
298 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
299}
300
301static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
302{
30add22d 303 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 304 struct drm_i915_private *dev_priv = dev->dev_private;
305
306 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
307}
308
9b984dae
KP		 309static void
310intel_dp_check_edp(struct intel_dp *intel_dp)
311{
30add22d 312 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 313 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 314
9b984dae
KP		 315 if (!is_edp(intel_dp))
316 return;
ebf33b18 317 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 318 WARN(1, "eDP powered off while attempting aux channel communication.\n");
319 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 320 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 321 I915_READ(PCH_PP_CONTROL));
322 }
323}
324
9ee32fea
DV		 325static uint32_t
326intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
327{
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
331 uint32_t ch_ctl = intel_dp->output_reg + 0x10;
332 uint32_t status;
333 bool done;
334
335 if (IS_HASWELL(dev)) {
336 switch (intel_dig_port->port) {
337 case PORT_A:
338 ch_ctl = DPA_AUX_CH_CTL;
339 break;
340 case PORT_B:
341 ch_ctl = PCH_DPB_AUX_CH_CTL;
342 break;
343 case PORT_C:
344 ch_ctl = PCH_DPC_AUX_CH_CTL;
345 break;
346 case PORT_D:
347 ch_ctl = PCH_DPD_AUX_CH_CTL;
348 break;
349 default:
350 BUG();
351 }
352 }
353
ef04f00d 354#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea
DV		 355 if (has_aux_irq)
356 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10);
357 else
358 done = wait_for_atomic(C, 10) == 0;
359 if (!done)
360 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
361 has_aux_irq);
362#undef C
363
364 return status;
365}
366
a4fc5ed6 367static int
ea5b213a 368intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 369 uint8_t *send, int send_bytes,
370 uint8_t *recv, int recv_size)
371{
ea5b213a 372 uint32_t output_reg = intel_dp->output_reg;
174edf1f
PZ		 373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
374 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6
KP		 375 struct drm_i915_private *dev_priv = dev->dev_private;
376 uint32_t ch_ctl = output_reg + 0x10;
377 uint32_t ch_data = ch_ctl + 4;
9ee32fea 378 int i, ret, recv_bytes;
a4fc5ed6 379 uint32_t status;
fb0f8fbf 380 uint32_t aux_clock_divider;
6b4e0a93 381 int try, precharge;
9ee32fea
DV		 382 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
383
384 /* dp aux is extremely sensitive to irq latency, hence request the
385 * lowest possible wakeup latency and so prevent the cpu from going into
386 * deep sleep states.
387 */
388 pm_qos_update_request(&dev_priv->pm_qos, 0);
a4fc5ed6 389
750eb99e 390 if (IS_HASWELL(dev)) {
174edf1f 391 switch (intel_dig_port->port) {
750eb99e
PZ		 392 case PORT_A:
393 ch_ctl = DPA_AUX_CH_CTL;
394 ch_data = DPA_AUX_CH_DATA1;
395 break;
396 case PORT_B:
397 ch_ctl = PCH_DPB_AUX_CH_CTL;
398 ch_data = PCH_DPB_AUX_CH_DATA1;
399 break;
400 case PORT_C:
401 ch_ctl = PCH_DPC_AUX_CH_CTL;
402 ch_data = PCH_DPC_AUX_CH_DATA1;
403 break;
404 case PORT_D:
405 ch_ctl = PCH_DPD_AUX_CH_CTL;
406 ch_data = PCH_DPD_AUX_CH_DATA1;
407 break;
408 default:
409 BUG();
410 }
411 }
412
9b984dae 413 intel_dp_check_edp(intel_dp);
a4fc5ed6 414 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 415 * and would like to run at 2MHz. So, take the
416 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 417 *
418 * Note that PCH attached eDP panels should use a 125MHz input
419 * clock divider.
a4fc5ed6 420 */
1c95822a 421 if (is_cpu_edp(intel_dp)) {
affa9354 422 if (HAS_DDI(dev))
b8fc2f6a
PZ		 423 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
424 else if (IS_VALLEYVIEW(dev))
9473c8f4
VP		 425 aux_clock_divider = 100;
426 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 427 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 428 else
429 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
430 } else if (HAS_PCH_SPLIT(dev))
6b3ec1c9 431 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
5eb08b69
ZW		 432 else
433 aux_clock_divider = intel_hrawclk(dev) / 2;
434
6b4e0a93
DV		 435 if (IS_GEN6(dev))
436 precharge = 3;
437 else
438 precharge = 5;
439
11bee43e
JB		 440 /* Try to wait for any previous AUX channel activity */
441 for (try = 0; try < 3; try++) {
ef04f00d 442 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 443 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
444 break;
445 msleep(1);
446 }
447
448 if (try == 3) {
449 WARN(1, "dp_aux_ch not started status 0x%08x\n",
450 I915_READ(ch_ctl));
9ee32fea
DV		 451 ret = -EBUSY;
452 goto out;
4f7f7b7e
CW		 453 }
454
fb0f8fbf
KP		 455 /* Must try at least 3 times according to DP spec */
456 for (try = 0; try < 5; try++) {
457 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 458 for (i = 0; i < send_bytes; i += 4)
459 I915_WRITE(ch_data + i,
460 pack_aux(send + i, send_bytes - i));
0206e353 461
fb0f8fbf 462 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 463 I915_WRITE(ch_ctl,
464 DP_AUX_CH_CTL_SEND_BUSY |
9ee32fea 465 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
4f7f7b7e
CW		 466 DP_AUX_CH_CTL_TIME_OUT_400us |
467 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
468 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
469 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
470 DP_AUX_CH_CTL_DONE |
471 DP_AUX_CH_CTL_TIME_OUT_ERROR |
472 DP_AUX_CH_CTL_RECEIVE_ERROR);
9ee32fea
DV		 473
474 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
0206e353 475
fb0f8fbf 476 /* Clear done status and any errors */
4f7f7b7e
CW		 477 I915_WRITE(ch_ctl,
478 status |
479 DP_AUX_CH_CTL_DONE |
480 DP_AUX_CH_CTL_TIME_OUT_ERROR |
481 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 482
483 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
484 DP_AUX_CH_CTL_RECEIVE_ERROR))
485 continue;
4f7f7b7e 486 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 487 break;
488 }
489
a4fc5ed6 490 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 491 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 492 ret = -EBUSY;
493 goto out;
a4fc5ed6
KP		 494 }
495
496 /* Check for timeout or receive error.
497 * Timeouts occur when the sink is not connected
498 */
a5b3da54 499 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 500 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 501 ret = -EIO;
502 goto out;
a5b3da54 503 }
1ae8c0a5
KP		 504
505 /* Timeouts occur when the device isn't connected, so they're
506 * "normal" -- don't fill the kernel log with these */
a5b3da54 507 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 508 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 509 ret = -ETIMEDOUT;
510 goto out;
a4fc5ed6
KP		 511 }
512
513 /* Unload any bytes sent back from the other side */
514 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
515 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 516 if (recv_bytes > recv_size)
517 recv_bytes = recv_size;
0206e353 518
4f7f7b7e
CW		 519 for (i = 0; i < recv_bytes; i += 4)
520 unpack_aux(I915_READ(ch_data + i),
521 recv + i, recv_bytes - i);
a4fc5ed6 522
9ee32fea
DV		 523 ret = recv_bytes;
524out:
525 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
526
527 return ret;
a4fc5ed6
KP		 528}
529
530/* Write data to the aux channel in native mode */
531static int
ea5b213a 532intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 533 uint16_t address, uint8_t *send, int send_bytes)
534{
535 int ret;
536 uint8_t msg[20];
537 int msg_bytes;
538 uint8_t ack;
539
9b984dae 540 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 541 if (send_bytes > 16)
542 return -1;
543 msg[0] = AUX_NATIVE_WRITE << 4;
544 msg[1] = address >> 8;
eebc863e 545 msg[2] = address & 0xff;
a4fc5ed6
KP		 546 msg[3] = send_bytes - 1;
547 memcpy(&msg[4], send, send_bytes);
548 msg_bytes = send_bytes + 4;
549 for (;;) {
ea5b213a 550 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 551 if (ret < 0)
552 return ret;
553 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
554 break;
555 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
556 udelay(100);
557 else
a5b3da54 558 return -EIO;
a4fc5ed6
KP		 559 }
560 return send_bytes;
561}
562
563/* Write a single byte to the aux channel in native mode */
564static int
ea5b213a 565intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 566 uint16_t address, uint8_t byte)
567{
ea5b213a 568 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 569}
570
571/* read bytes from a native aux channel */
572static int
ea5b213a 573intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 574 uint16_t address, uint8_t *recv, int recv_bytes)
575{
576 uint8_t msg[4];
577 int msg_bytes;
578 uint8_t reply[20];
579 int reply_bytes;
580 uint8_t ack;
581 int ret;
582
9b984dae 583 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 584 msg[0] = AUX_NATIVE_READ << 4;
585 msg[1] = address >> 8;
586 msg[2] = address & 0xff;
587 msg[3] = recv_bytes - 1;
588
589 msg_bytes = 4;
590 reply_bytes = recv_bytes + 1;
591
592 for (;;) {
ea5b213a 593 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 594 reply, reply_bytes);
a5b3da54
KP		 595 if (ret == 0)
596 return -EPROTO;
597 if (ret < 0)
a4fc5ed6
KP		 598 return ret;
599 ack = reply[0];
600 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
601 memcpy(recv, reply + 1, ret - 1);
602 return ret - 1;
603 }
604 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
605 udelay(100);
606 else
a5b3da54 607 return -EIO;
a4fc5ed6
KP		 608 }
609}
610
611static int
ab2c0672
DA		 612intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
613 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 614{
ab2c0672 615 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 616 struct intel_dp *intel_dp = container_of(adapter,
617 struct intel_dp,
618 adapter);
ab2c0672
DA		 619 uint16_t address = algo_data->address;
620 uint8_t msg[5];
621 uint8_t reply[2];
8316f337 622 unsigned retry;
ab2c0672
DA		 623 int msg_bytes;
624 int reply_bytes;
625 int ret;
626
9b984dae 627 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 628 /* Set up the command byte */
629 if (mode & MODE_I2C_READ)
630 msg[0] = AUX_I2C_READ << 4;
631 else
632 msg[0] = AUX_I2C_WRITE << 4;
633
634 if (!(mode & MODE_I2C_STOP))
635 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 636
ab2c0672
DA		 637 msg[1] = address >> 8;
638 msg[2] = address;
639
640 switch (mode) {
641 case MODE_I2C_WRITE:
642 msg[3] = 0;
643 msg[4] = write_byte;
644 msg_bytes = 5;
645 reply_bytes = 1;
646 break;
647 case MODE_I2C_READ:
648 msg[3] = 0;
649 msg_bytes = 4;
650 reply_bytes = 2;
651 break;
652 default:
653 msg_bytes = 3;
654 reply_bytes = 1;
655 break;
656 }
657
8316f337
DF		 658 for (retry = 0; retry < 5; retry++) {
659 ret = intel_dp_aux_ch(intel_dp,
660 msg, msg_bytes,
661 reply, reply_bytes);
ab2c0672 662 if (ret < 0) {
3ff99164 663 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 664 return ret;
665 }
8316f337
DF		 666
667 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
668 case AUX_NATIVE_REPLY_ACK:
669 /* I2C-over-AUX Reply field is only valid
670 * when paired with AUX ACK.
671 */
672 break;
673 case AUX_NATIVE_REPLY_NACK:
674 DRM_DEBUG_KMS("aux_ch native nack\n");
675 return -EREMOTEIO;
676 case AUX_NATIVE_REPLY_DEFER:
677 udelay(100);
678 continue;
679 default:
680 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
681 reply[0]);
682 return -EREMOTEIO;
683 }
684
ab2c0672
DA		 685 switch (reply[0] & AUX_I2C_REPLY_MASK) {
686 case AUX_I2C_REPLY_ACK:
687 if (mode == MODE_I2C_READ) {
688 *read_byte = reply[1];
689 }
690 return reply_bytes - 1;
691 case AUX_I2C_REPLY_NACK:
8316f337 692 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 693 return -EREMOTEIO;
694 case AUX_I2C_REPLY_DEFER:
8316f337 695 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 696 udelay(100);
697 break;
698 default:
8316f337 699 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 700 return -EREMOTEIO;
701 }
702 }
8316f337
DF		 703
704 DRM_ERROR("too many retries, giving up\n");
705 return -EREMOTEIO;
a4fc5ed6
KP		 706}
707
708static int
ea5b213a 709intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 710 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 711{
0b5c541b
KP		 712 int ret;
713
d54e9d28 714 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 715 intel_dp->algo.running = false;
716 intel_dp->algo.address = 0;
717 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
718
0206e353 719 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 720 intel_dp->adapter.owner = THIS_MODULE;
721 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 722 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 723 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
724 intel_dp->adapter.algo_data = &intel_dp->algo;
725 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
726
0b5c541b
KP		 727 ironlake_edp_panel_vdd_on(intel_dp);
728 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 729 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 730 return ret;
a4fc5ed6
KP		 731}
732
00c09d70 733bool
e811f5ae
LP		 734intel_dp_mode_fixup(struct drm_encoder *encoder,
735 const struct drm_display_mode *mode,
a4fc5ed6
KP		 736 struct drm_display_mode *adjusted_mode)
737{
0d3a1bee 738 struct drm_device *dev = encoder->dev;
ea5b213a 739 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
dd06f90e 740 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 741 int lane_count, clock;
397fe157 742 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 743 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 744 int bpp, mode_rate;
a4fc5ed6
KP		 745 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
746
dd06f90e
JN		 747 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
748 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
749 adjusted_mode);
53b41837
YN		 750 intel_pch_panel_fitting(dev,
751 intel_connector->panel.fitting_mode,
1d8e1c75 752 mode, adjusted_mode);
0d3a1bee
ZY		 753 }
754
cb1793ce 755 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 756 return false;
757
083f9560
DV		 758 DRM_DEBUG_KMS("DP link computation with max lane count %i "
759 "max bw %02x pixel clock %iKHz\n",
71244653 760 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 761
cb1793ce 762 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 763 return false;
764
765 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
3685a8f3
VS		 766
767 if (intel_dp->color_range)
768 adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE;
769
71244653 770 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 771
2514bc51
JB		 772 for (clock = 0; clock <= max_clock; clock++) {
773 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
9fa5f652
PZ		 774 int link_bw_clock =
775 drm_dp_bw_code_to_link_rate(bws[clock]);
776 int link_avail = intel_dp_max_data_rate(link_bw_clock,
777 lane_count);
a4fc5ed6 778
083f9560 779 if (mode_rate <= link_avail) {
ea5b213a
CW		 780 intel_dp->link_bw = bws[clock];
781 intel_dp->lane_count = lane_count;
9fa5f652 782 adjusted_mode->clock = link_bw_clock;
083f9560
DV		 783 DRM_DEBUG_KMS("DP link bw %02x lane "
784 "count %d clock %d bpp %d\n",
ea5b213a 785 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 786 adjusted_mode->clock, bpp);
787 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
788 mode_rate, link_avail);
a4fc5ed6
KP		 789 return true;
790 }
791 }
792 }
fe27d53e 793
a4fc5ed6
KP		 794 return false;
795}
796
a4fc5ed6
KP		 797void
798intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
799 struct drm_display_mode *adjusted_mode)
800{
801 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 802 struct intel_encoder *intel_encoder;
803 struct intel_dp *intel_dp;
a4fc5ed6
KP		 804 struct drm_i915_private *dev_priv = dev->dev_private;
805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 806 int lane_count = 4;
e69d0bc1 807 struct intel_link_m_n m_n;
9db4a9c7 808 int pipe = intel_crtc->pipe;
afe2fcf5 809 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
a4fc5ed6
KP		 810
811 /*
21d40d37 812 * Find the lane count in the intel_encoder private
a4fc5ed6 813 */
fa90ecef
PZ		 814 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
815 intel_dp = enc_to_intel_dp(&intel_encoder->base);
a4fc5ed6 816
fa90ecef
PZ		 817 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
818 intel_encoder->type == INTEL_OUTPUT_EDP)
9a10f401 819 {
ea5b213a 820 lane_count = intel_dp->lane_count;
51190667 821 break;
a4fc5ed6
KP		 822 }
823 }
824
825 /*
826 * Compute the GMCH and Link ratios. The '3' here is
827 * the number of bytes_per_pixel post-LUT, which we always
828 * set up for 8-bits of R/G/B, or 3 bytes total.
829 */
e69d0bc1
DV		 830 intel_link_compute_m_n(intel_crtc->bpp, lane_count,
831 mode->clock, adjusted_mode->clock, &m_n);
a4fc5ed6 832
1eb8dfec 833 if (IS_HASWELL(dev)) {
afe2fcf5
PZ		 834 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
835 TU_SIZE(m_n.tu) | m_n.gmch_m);
836 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
837 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
838 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
1eb8dfec 839 } else if (HAS_PCH_SPLIT(dev)) {
7346bfa0 840 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 841 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
842 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
843 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
74a4dd2e
VP		 844 } else if (IS_VALLEYVIEW(dev)) {
845 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
846 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
847 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
848 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
a4fc5ed6 849 } else {
9db4a9c7 850 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
7346bfa0 851 TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 852 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
853 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
854 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 855 }
856}
857
247d89f6
PZ		 858void intel_dp_init_link_config(struct intel_dp *intel_dp)
859{
860 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
861 intel_dp->link_configuration[0] = intel_dp->link_bw;
862 intel_dp->link_configuration[1] = intel_dp->lane_count;
863 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
864 /*
865 * Check for DPCD version > 1.1 and enhanced framing support
866 */
867 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
868 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
869 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
870 }
871}
872
ea9b6006
DV		 873static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
874{
875 struct drm_device *dev = crtc->dev;
876 struct drm_i915_private *dev_priv = dev->dev_private;
877 u32 dpa_ctl;
878
879 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
880 dpa_ctl = I915_READ(DP_A);
881 dpa_ctl &= ~DP_PLL_FREQ_MASK;
882
883 if (clock < 200000) {
1ce17038
DV		 884 /* For a long time we've carried around a ILK-DevA w/a for the
885 * 160MHz clock. If we're really unlucky, it's still required.
886 */
887 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 888 dpa_ctl |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 889 } else {
890 dpa_ctl |= DP_PLL_FREQ_270MHZ;
891 }
1ce17038 892
ea9b6006
DV		 893 I915_WRITE(DP_A, dpa_ctl);
894
895 POSTING_READ(DP_A);
896 udelay(500);
897}
898
a4fc5ed6
KP		 899static void
900intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
901 struct drm_display_mode *adjusted_mode)
902{
e3421a18 903 struct drm_device *dev = encoder->dev;
417e822d 904 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 905 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
fa90ecef 906 struct drm_crtc *crtc = encoder->crtc;
a4fc5ed6
KP		 907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
908
417e822d 909 /*
1a2eb460 910 * There are four kinds of DP registers:
417e822d
KP		 911 *
912 * IBX PCH
1a2eb460
KP		 913 * SNB CPU
914 * IVB CPU
417e822d
KP		 915 * CPT PCH
916 *
917 * IBX PCH and CPU are the same for almost everything,
918 * except that the CPU DP PLL is configured in this
919 * register
920 *
921 * CPT PCH is quite different, having many bits moved
922 * to the TRANS_DP_CTL register instead. That
923 * configuration happens (oddly) in ironlake_pch_enable
924 */
9c9e7927 925
417e822d
KP		 926 /* Preserve the BIOS-computed detected bit. This is
927 * supposed to be read-only.
928 */
929 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 930
417e822d 931 /* Handle DP bits in common between all three register formats */
417e822d 932 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 933
ea5b213a 934 switch (intel_dp->lane_count) {
a4fc5ed6 935 case 1:
ea5b213a 936 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 937 break;
938 case 2:
ea5b213a 939 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 940 break;
941 case 4:
ea5b213a 942 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 943 break;
944 }
e0dac65e
WF		 945 if (intel_dp->has_audio) {
946 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
947 pipe_name(intel_crtc->pipe));
ea5b213a 948 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 949 intel_write_eld(encoder, adjusted_mode);
950 }
247d89f6
PZ		 951
952 intel_dp_init_link_config(intel_dp);
a4fc5ed6 953
417e822d 954 /* Split out the IBX/CPU vs CPT settings */
32f9d658 955
19c03924 956 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 957 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
958 intel_dp->DP |= DP_SYNC_HS_HIGH;
959 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
960 intel_dp->DP |= DP_SYNC_VS_HIGH;
961 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
962
963 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
964 intel_dp->DP |= DP_ENHANCED_FRAMING;
965
966 intel_dp->DP |= intel_crtc->pipe << 29;
967
968 /* don't miss out required setting for eDP */
1a2eb460
KP		 969 if (adjusted_mode->clock < 200000)
970 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
971 else
972 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
973 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
3685a8f3
VS		 974 if (!HAS_PCH_SPLIT(dev))
975 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 976
977 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
978 intel_dp->DP |= DP_SYNC_HS_HIGH;
979 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
980 intel_dp->DP |= DP_SYNC_VS_HIGH;
981 intel_dp->DP |= DP_LINK_TRAIN_OFF;
982
983 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
984 intel_dp->DP |= DP_ENHANCED_FRAMING;
985
986 if (intel_crtc->pipe == 1)
987 intel_dp->DP |= DP_PIPEB_SELECT;
988
989 if (is_cpu_edp(intel_dp)) {
990 /* don't miss out required setting for eDP */
417e822d
KP		 991 if (adjusted_mode->clock < 200000)
992 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
993 else
994 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
995 }
996 } else {
997 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 998 }
ea9b6006
DV		 999
1000 if (is_cpu_edp(intel_dp))
1001 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
a4fc5ed6
KP		 1002}
1003
99ea7127
KP		 1004#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1005#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1006
1007#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1008#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1009
1010#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1011#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1012
1013static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1014 u32 mask,
1015 u32 value)
bd943159 1016{
30add22d 1017 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1018 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 1019
99ea7127
KP		 1020 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1021 mask, value,
1022 I915_READ(PCH_PP_STATUS),
1023 I915_READ(PCH_PP_CONTROL));
32ce697c 1024
99ea7127
KP		 1025 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
1026 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1027 I915_READ(PCH_PP_STATUS),
1028 I915_READ(PCH_PP_CONTROL));
32ce697c 1029 }
99ea7127 1030}
32ce697c 1031
99ea7127
KP		 1032static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1033{
1034 DRM_DEBUG_KMS("Wait for panel power on\n");
1035 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1036}
1037
99ea7127
KP		 1038static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1039{
1040 DRM_DEBUG_KMS("Wait for panel power off time\n");
1041 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1042}
1043
1044static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1045{
1046 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1047 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1048}
1049
1050
832dd3c1
KP		 1051/* Read the current pp_control value, unlocking the register if it
1052 * is locked
1053 */
1054
1055static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1056{
1057 u32 control = I915_READ(PCH_PP_CONTROL);
1058
1059 control &= ~PANEL_UNLOCK_MASK;
1060 control |= PANEL_UNLOCK_REGS;
1061 return control;
bd943159
KP		 1062}
1063
82a4d9c0 1064void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1065{
30add22d 1066 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1067 struct drm_i915_private *dev_priv = dev->dev_private;
1068 u32 pp;
1069
97af61f5
KP		 1070 if (!is_edp(intel_dp))
1071 return;
f01eca2e 1072 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1073
bd943159
KP		 1074 WARN(intel_dp->want_panel_vdd,
1075 "eDP VDD already requested on\n");
1076
1077 intel_dp->want_panel_vdd = true;
99ea7127 1078
bd943159
KP		 1079 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1080 DRM_DEBUG_KMS("eDP VDD already on\n");
1081 return;
1082 }
1083
99ea7127
KP		 1084 if (!ironlake_edp_have_panel_power(intel_dp))
1085 ironlake_wait_panel_power_cycle(intel_dp);
1086
832dd3c1 1087 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1088 pp |= EDP_FORCE_VDD;
1089 I915_WRITE(PCH_PP_CONTROL, pp);
1090 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1091 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1092 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1093
1094 /*
1095 * If the panel wasn't on, delay before accessing aux channel
1096 */
1097 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1098 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1099 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1100 }
5d613501
JB		 1101}
1102
bd943159 1103static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1104{
30add22d 1105 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1106 struct drm_i915_private *dev_priv = dev->dev_private;
1107 u32 pp;
1108
bd943159 1109 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1110 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1111 pp &= ~EDP_FORCE_VDD;
1112 I915_WRITE(PCH_PP_CONTROL, pp);
1113 POSTING_READ(PCH_PP_CONTROL);
1114
1115 /* Make sure sequencer is idle before allowing subsequent activity */
1116 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1117 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1118
1119 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1120 }
1121}
5d613501 1122
bd943159
KP		 1123static void ironlake_panel_vdd_work(struct work_struct *__work)
1124{
1125 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1126 struct intel_dp, panel_vdd_work);
30add22d 1127 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1128
627f7675 1129 mutex_lock(&dev->mode_config.mutex);
bd943159 1130 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1131 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1132}
1133
82a4d9c0 1134void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1135{
97af61f5
KP		 1136 if (!is_edp(intel_dp))
1137 return;
5d613501 1138
bd943159
KP		 1139 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1140 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1141
bd943159
KP		 1142 intel_dp->want_panel_vdd = false;
1143
1144 if (sync) {
1145 ironlake_panel_vdd_off_sync(intel_dp);
1146 } else {
1147 /*
1148 * Queue the timer to fire a long
1149 * time from now (relative to the power down delay)
1150 * to keep the panel power up across a sequence of operations
1151 */
1152 schedule_delayed_work(&intel_dp->panel_vdd_work,
1153 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1154 }
5d613501
JB		 1155}
1156
82a4d9c0 1157void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1158{
30add22d 1159 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1160 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1161 u32 pp;
9934c132 1162
97af61f5 1163 if (!is_edp(intel_dp))
bd943159 1164 return;
99ea7127
KP		 1165
1166 DRM_DEBUG_KMS("Turn eDP power on\n");
1167
1168 if (ironlake_edp_have_panel_power(intel_dp)) {
1169 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1170 return;
99ea7127 1171 }
9934c132 1172
99ea7127 1173 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1174
99ea7127 1175 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1176 if (IS_GEN5(dev)) {
1177 /* ILK workaround: disable reset around power sequence */
1178 pp &= ~PANEL_POWER_RESET;
1179 I915_WRITE(PCH_PP_CONTROL, pp);
1180 POSTING_READ(PCH_PP_CONTROL);
1181 }
37c6c9b0 1182
1c0ae80a 1183 pp |= POWER_TARGET_ON;
99ea7127
KP		 1184 if (!IS_GEN5(dev))
1185 pp |= PANEL_POWER_RESET;
1186
9934c132 1187 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1188 POSTING_READ(PCH_PP_CONTROL);
9934c132 1189
99ea7127 1190 ironlake_wait_panel_on(intel_dp);
9934c132 1191
05ce1a49
KP		 1192 if (IS_GEN5(dev)) {
1193 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1194 I915_WRITE(PCH_PP_CONTROL, pp);
1195 POSTING_READ(PCH_PP_CONTROL);
1196 }
9934c132
JB		 1197}
1198
82a4d9c0 1199void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1200{
30add22d 1201 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1202 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1203 u32 pp;
9934c132 1204
97af61f5
KP		 1205 if (!is_edp(intel_dp))
1206 return;
37c6c9b0 1207
99ea7127 1208 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1209
6cb49835 1210 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1211
99ea7127 1212 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1213 /* We need to switch off panel power _and_ force vdd, for otherwise some
1214 * panels get very unhappy and cease to work. */
1215 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1216 I915_WRITE(PCH_PP_CONTROL, pp);
1217 POSTING_READ(PCH_PP_CONTROL);
9934c132 1218
35a38556
DV		 1219 intel_dp->want_panel_vdd = false;
1220
99ea7127 1221 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1222}
1223
d6c50ff8 1224void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1225{
da63a9f2
PZ		 1226 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1227 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1228 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1229 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658
ZW		 1230 u32 pp;
1231
f01eca2e
KP		 1232 if (!is_edp(intel_dp))
1233 return;
1234
28c97730 1235 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1236 /*
1237 * If we enable the backlight right away following a panel power
1238 * on, we may see slight flicker as the panel syncs with the eDP
1239 * link. So delay a bit to make sure the image is solid before
1240 * allowing it to appear.
1241 */
f01eca2e 1242 msleep(intel_dp->backlight_on_delay);
832dd3c1 1243 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1244 pp |= EDP_BLC_ENABLE;
1245 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1246 POSTING_READ(PCH_PP_CONTROL);
035aa3de
DV		 1247
1248 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1249}
1250
d6c50ff8 1251void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1252{
30add22d 1253 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1254 struct drm_i915_private *dev_priv = dev->dev_private;
1255 u32 pp;
1256
f01eca2e
KP		 1257 if (!is_edp(intel_dp))
1258 return;
1259
035aa3de
DV		 1260 intel_panel_disable_backlight(dev);
1261
28c97730 1262 DRM_DEBUG_KMS("\n");
832dd3c1 1263 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1264 pp &= ~EDP_BLC_ENABLE;
1265 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1266 POSTING_READ(PCH_PP_CONTROL);
1267 msleep(intel_dp->backlight_off_delay);
32f9d658 1268}
a4fc5ed6 1269
2bd2ad64 1270static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1271{
da63a9f2
PZ		 1272 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1273 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1274 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1275 struct drm_i915_private *dev_priv = dev->dev_private;
1276 u32 dpa_ctl;
1277
2bd2ad64
DV		 1278 assert_pipe_disabled(dev_priv,
1279 to_intel_crtc(crtc)->pipe);
1280
d240f20f
JB		 1281 DRM_DEBUG_KMS("\n");
1282 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1283 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1284 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1285
1286 /* We don't adjust intel_dp->DP while tearing down the link, to
1287 * facilitate link retraining (e.g. after hotplug). Hence clear all
1288 * enable bits here to ensure that we don't enable too much. */
1289 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1290 intel_dp->DP |= DP_PLL_ENABLE;
1291 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1292 POSTING_READ(DP_A);
1293 udelay(200);
d240f20f
JB		 1294}
1295
2bd2ad64 1296static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1297{
da63a9f2
PZ		 1298 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1299 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1300 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1301 struct drm_i915_private *dev_priv = dev->dev_private;
1302 u32 dpa_ctl;
1303
2bd2ad64
DV		 1304 assert_pipe_disabled(dev_priv,
1305 to_intel_crtc(crtc)->pipe);
1306
d240f20f 1307 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1308 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1309 "dp pll off, should be on\n");
1310 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1311
1312 /* We can't rely on the value tracked for the DP register in
1313 * intel_dp->DP because link_down must not change that (otherwise link
1314 * re-training will fail. */
298b0b39 1315 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1316 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1317 POSTING_READ(DP_A);
d240f20f
JB		 1318 udelay(200);
1319}
1320
c7ad3810 1321/* If the sink supports it, try to set the power state appropriately */
c19b0669 1322void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1323{
1324 int ret, i;
1325
1326 /* Should have a valid DPCD by this point */
1327 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1328 return;
1329
1330 if (mode != DRM_MODE_DPMS_ON) {
1331 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1332 DP_SET_POWER_D3);
1333 if (ret != 1)
1334 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1335 } else {
1336 /*
1337 * When turning on, we need to retry for 1ms to give the sink
1338 * time to wake up.
1339 */
1340 for (i = 0; i < 3; i++) {
1341 ret = intel_dp_aux_native_write_1(intel_dp,
1342 DP_SET_POWER,
1343 DP_SET_POWER_D0);
1344 if (ret == 1)
1345 break;
1346 msleep(1);
1347 }
1348 }
1349}
1350
19d8fe15
DV		 1351static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1352 enum pipe *pipe)
d240f20f 1353{
19d8fe15
DV		 1354 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1355 struct drm_device *dev = encoder->base.dev;
1356 struct drm_i915_private *dev_priv = dev->dev_private;
1357 u32 tmp = I915_READ(intel_dp->output_reg);
1358
1359 if (!(tmp & DP_PORT_EN))
1360 return false;
1361
1362 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1363 *pipe = PORT_TO_PIPE_CPT(tmp);
1364 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1365 *pipe = PORT_TO_PIPE(tmp);
1366 } else {
1367 u32 trans_sel;
1368 u32 trans_dp;
1369 int i;
1370
1371 switch (intel_dp->output_reg) {
1372 case PCH_DP_B:
1373 trans_sel = TRANS_DP_PORT_SEL_B;
1374 break;
1375 case PCH_DP_C:
1376 trans_sel = TRANS_DP_PORT_SEL_C;
1377 break;
1378 case PCH_DP_D:
1379 trans_sel = TRANS_DP_PORT_SEL_D;
1380 break;
1381 default:
1382 return true;
1383 }
1384
1385 for_each_pipe(i) {
1386 trans_dp = I915_READ(TRANS_DP_CTL(i));
1387 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1388 *pipe = i;
1389 return true;
1390 }
1391 }
19d8fe15 1392
4a0833ec
DV		 1393 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1394 intel_dp->output_reg);
1395 }
d240f20f 1396
19d8fe15
DV		 1397 return true;
1398}
d240f20f 1399
e8cb4558 1400static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1401{
e8cb4558 1402 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1403
1404 /* Make sure the panel is off before trying to change the mode. But also
1405 * ensure that we have vdd while we switch off the panel. */
1406 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1407 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1408 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1409 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1410
1411 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1412 if (!is_cpu_edp(intel_dp))
1413 intel_dp_link_down(intel_dp);
d240f20f
JB		 1414}
1415
2bd2ad64 1416static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1417{
2bd2ad64
DV		 1418 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1419
3739850b
DV		 1420 if (is_cpu_edp(intel_dp)) {
1421 intel_dp_link_down(intel_dp);
2bd2ad64 1422 ironlake_edp_pll_off(intel_dp);
3739850b 1423 }
2bd2ad64
DV		 1424}
1425
e8cb4558 1426static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1427{
e8cb4558
DV		 1428 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1429 struct drm_device *dev = encoder->base.dev;
1430 struct drm_i915_private *dev_priv = dev->dev_private;
1431 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1432
0c33d8d7
DV		 1433 if (WARN_ON(dp_reg & DP_PORT_EN))
1434 return;
5d613501 1435
97af61f5 1436 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1437 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1438 intel_dp_start_link_train(intel_dp);
97af61f5 1439 ironlake_edp_panel_on(intel_dp);
bd943159 1440 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1441 intel_dp_complete_link_train(intel_dp);
f01eca2e 1442 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1443}
1444
2bd2ad64 1445static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1446{
2bd2ad64 1447 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 1448
2bd2ad64
DV		 1449 if (is_cpu_edp(intel_dp))
1450 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1451}
1452
1453/*
df0c237d
JB		 1454 * Native read with retry for link status and receiver capability reads for
1455 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1456 */
1457static bool
df0c237d
JB		 1458intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1459 uint8_t *recv, int recv_bytes)
a4fc5ed6 1460{
61da5fab
JB		 1461 int ret, i;
1462
df0c237d
JB		 1463 /*
1464 * Sinks are *supposed* to come up within 1ms from an off state,
1465 * but we're also supposed to retry 3 times per the spec.
1466 */
61da5fab 1467 for (i = 0; i < 3; i++) {
df0c237d
JB		 1468 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1469 recv_bytes);
1470 if (ret == recv_bytes)
61da5fab
JB		 1471 return true;
1472 msleep(1);
1473 }
a4fc5ed6 1474
61da5fab 1475 return false;
a4fc5ed6
KP		 1476}
1477
1478/*
1479 * Fetch AUX CH registers 0x202 - 0x207 which contain
1480 * link status information
1481 */
1482static bool
93f62dad 1483intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1484{
df0c237d
JB		 1485 return intel_dp_aux_native_read_retry(intel_dp,
1486 DP_LANE0_1_STATUS,
93f62dad 1487 link_status,
df0c237d 1488 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1489}
1490
a4fc5ed6
KP		 1491#if 0
1492static char *voltage_names[] = {
1493 "0.4V", "0.6V", "0.8V", "1.2V"
1494};
1495static char *pre_emph_names[] = {
1496 "0dB", "3.5dB", "6dB", "9.5dB"
1497};
1498static char *link_train_names[] = {
1499 "pattern 1", "pattern 2", "idle", "off"
1500};
1501#endif
1502
1503/*
1504 * These are source-specific values; current Intel hardware supports
1505 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1506 */
a4fc5ed6
KP		 1507
1508static uint8_t
1a2eb460 1509intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1510{
30add22d 1511 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460
KP		 1512
1513 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1514 return DP_TRAIN_VOLTAGE_SWING_800;
1515 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1516 return DP_TRAIN_VOLTAGE_SWING_1200;
1517 else
1518 return DP_TRAIN_VOLTAGE_SWING_800;
1519}
1520
1521static uint8_t
1522intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1523{
30add22d 1524 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1525
d6c0d722
PZ		 1526 if (IS_HASWELL(dev)) {
1527 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1528 case DP_TRAIN_VOLTAGE_SWING_400:
1529 return DP_TRAIN_PRE_EMPHASIS_9_5;
1530 case DP_TRAIN_VOLTAGE_SWING_600:
1531 return DP_TRAIN_PRE_EMPHASIS_6;
1532 case DP_TRAIN_VOLTAGE_SWING_800:
1533 return DP_TRAIN_PRE_EMPHASIS_3_5;
1534 case DP_TRAIN_VOLTAGE_SWING_1200:
1535 default:
1536 return DP_TRAIN_PRE_EMPHASIS_0;
1537 }
1538 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1539 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1540 case DP_TRAIN_VOLTAGE_SWING_400:
1541 return DP_TRAIN_PRE_EMPHASIS_6;
1542 case DP_TRAIN_VOLTAGE_SWING_600:
1543 case DP_TRAIN_VOLTAGE_SWING_800:
1544 return DP_TRAIN_PRE_EMPHASIS_3_5;
1545 default:
1546 return DP_TRAIN_PRE_EMPHASIS_0;
1547 }
1548 } else {
1549 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1550 case DP_TRAIN_VOLTAGE_SWING_400:
1551 return DP_TRAIN_PRE_EMPHASIS_6;
1552 case DP_TRAIN_VOLTAGE_SWING_600:
1553 return DP_TRAIN_PRE_EMPHASIS_6;
1554 case DP_TRAIN_VOLTAGE_SWING_800:
1555 return DP_TRAIN_PRE_EMPHASIS_3_5;
1556 case DP_TRAIN_VOLTAGE_SWING_1200:
1557 default:
1558 return DP_TRAIN_PRE_EMPHASIS_0;
1559 }
a4fc5ed6
KP		 1560 }
1561}
1562
1563static void
93f62dad 1564intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1565{
1566 uint8_t v = 0;
1567 uint8_t p = 0;
1568 int lane;
1a2eb460
KP		 1569 uint8_t voltage_max;
1570 uint8_t preemph_max;
a4fc5ed6 1571
33a34e4e 1572 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1573 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1574 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1575
1576 if (this_v > v)
1577 v = this_v;
1578 if (this_p > p)
1579 p = this_p;
1580 }
1581
1a2eb460 1582 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1583 if (v >= voltage_max)
1584 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1585
1a2eb460
KP		 1586 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1587 if (p >= preemph_max)
1588 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1589
1590 for (lane = 0; lane < 4; lane++)
33a34e4e 1591 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1592}
1593
1594static uint32_t
f0a3424e 1595intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 1596{
3cf2efb1 1597 uint32_t signal_levels = 0;
a4fc5ed6 1598
3cf2efb1 1599 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1600 case DP_TRAIN_VOLTAGE_SWING_400:
1601 default:
1602 signal_levels |= DP_VOLTAGE_0_4;
1603 break;
1604 case DP_TRAIN_VOLTAGE_SWING_600:
1605 signal_levels |= DP_VOLTAGE_0_6;
1606 break;
1607 case DP_TRAIN_VOLTAGE_SWING_800:
1608 signal_levels |= DP_VOLTAGE_0_8;
1609 break;
1610 case DP_TRAIN_VOLTAGE_SWING_1200:
1611 signal_levels |= DP_VOLTAGE_1_2;
1612 break;
1613 }
3cf2efb1 1614 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1615 case DP_TRAIN_PRE_EMPHASIS_0:
1616 default:
1617 signal_levels |= DP_PRE_EMPHASIS_0;
1618 break;
1619 case DP_TRAIN_PRE_EMPHASIS_3_5:
1620 signal_levels |= DP_PRE_EMPHASIS_3_5;
1621 break;
1622 case DP_TRAIN_PRE_EMPHASIS_6:
1623 signal_levels |= DP_PRE_EMPHASIS_6;
1624 break;
1625 case DP_TRAIN_PRE_EMPHASIS_9_5:
1626 signal_levels |= DP_PRE_EMPHASIS_9_5;
1627 break;
1628 }
1629 return signal_levels;
1630}
1631
e3421a18
ZW		 1632/* Gen6's DP voltage swing and pre-emphasis control */
1633static uint32_t
1634intel_gen6_edp_signal_levels(uint8_t train_set)
1635{
3c5a62b5
YL		 1636 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1637 DP_TRAIN_PRE_EMPHASIS_MASK);
1638 switch (signal_levels) {
e3421a18 1639 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1640 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1641 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1642 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1643 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1644 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1645 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1646 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1647 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1648 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1649 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1650 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1651 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1652 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1653 default:
3c5a62b5
YL		 1654 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1655 "0x%x\n", signal_levels);
1656 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1657 }
1658}
1659
1a2eb460
KP		 1660/* Gen7's DP voltage swing and pre-emphasis control */
1661static uint32_t
1662intel_gen7_edp_signal_levels(uint8_t train_set)
1663{
1664 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1665 DP_TRAIN_PRE_EMPHASIS_MASK);
1666 switch (signal_levels) {
1667 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1668 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1669 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1670 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1671 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1672 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1673
1674 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1675 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1676 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1677 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1678
1679 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1680 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1681 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1682 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1683
1684 default:
1685 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1686 "0x%x\n", signal_levels);
1687 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1688 }
1689}
1690
d6c0d722
PZ		 1691/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1692static uint32_t
f0a3424e 1693intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 1694{
d6c0d722
PZ		 1695 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1696 DP_TRAIN_PRE_EMPHASIS_MASK);
1697 switch (signal_levels) {
1698 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1699 return DDI_BUF_EMP_400MV_0DB_HSW;
1700 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1701 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1702 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1703 return DDI_BUF_EMP_400MV_6DB_HSW;
1704 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1705 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 1706
d6c0d722
PZ		 1707 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1708 return DDI_BUF_EMP_600MV_0DB_HSW;
1709 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1710 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1711 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1712 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 1713
d6c0d722
PZ		 1714 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1715 return DDI_BUF_EMP_800MV_0DB_HSW;
1716 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1717 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1718 default:
1719 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1720 "0x%x\n", signal_levels);
1721 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 1722 }
a4fc5ed6
KP		 1723}
1724
f0a3424e
PZ		 1725/* Properly updates "DP" with the correct signal levels. */
1726static void
1727intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1728{
1729 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1730 struct drm_device *dev = intel_dig_port->base.base.dev;
1731 uint32_t signal_levels, mask;
1732 uint8_t train_set = intel_dp->train_set[0];
1733
1734 if (IS_HASWELL(dev)) {
1735 signal_levels = intel_hsw_signal_levels(train_set);
1736 mask = DDI_BUF_EMP_MASK;
1737 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1738 signal_levels = intel_gen7_edp_signal_levels(train_set);
1739 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1740 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1741 signal_levels = intel_gen6_edp_signal_levels(train_set);
1742 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1743 } else {
1744 signal_levels = intel_gen4_signal_levels(train_set);
1745 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1746 }
1747
1748 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1749
1750 *DP = (*DP & ~mask) | signal_levels;
1751}
1752
a4fc5ed6 1753static bool
ea5b213a 1754intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1755 uint32_t dp_reg_value,
58e10eb9 1756 uint8_t dp_train_pat)
a4fc5ed6 1757{
174edf1f
PZ		 1758 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1759 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1760 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 1761 enum port port = intel_dig_port->port;
a4fc5ed6 1762 int ret;
d6c0d722 1763 uint32_t temp;
a4fc5ed6 1764
d6c0d722 1765 if (IS_HASWELL(dev)) {
174edf1f 1766 temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 1767
1768 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1769 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1770 else
1771 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1772
1773 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1774 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1775 case DP_TRAINING_PATTERN_DISABLE:
1776 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
174edf1f 1777 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 1778
174edf1f 1779 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
d6c0d722
PZ		 1780 DP_TP_STATUS_IDLE_DONE), 1))
1781 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1782
1783 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1784 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1785
1786 break;
1787 case DP_TRAINING_PATTERN_1:
1788 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1789 break;
1790 case DP_TRAINING_PATTERN_2:
1791 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1792 break;
1793 case DP_TRAINING_PATTERN_3:
1794 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1795 break;
1796 }
174edf1f 1797 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722
PZ		 1798
1799 } else if (HAS_PCH_CPT(dev) &&
1800 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1801 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1802
1803 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1804 case DP_TRAINING_PATTERN_DISABLE:
1805 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1806 break;
1807 case DP_TRAINING_PATTERN_1:
1808 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1809 break;
1810 case DP_TRAINING_PATTERN_2:
1811 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1812 break;
1813 case DP_TRAINING_PATTERN_3:
1814 DRM_ERROR("DP training pattern 3 not supported\n");
1815 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1816 break;
1817 }
1818
1819 } else {
1820 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1821
1822 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1823 case DP_TRAINING_PATTERN_DISABLE:
1824 dp_reg_value |= DP_LINK_TRAIN_OFF;
1825 break;
1826 case DP_TRAINING_PATTERN_1:
1827 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1828 break;
1829 case DP_TRAINING_PATTERN_2:
1830 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1831 break;
1832 case DP_TRAINING_PATTERN_3:
1833 DRM_ERROR("DP training pattern 3 not supported\n");
1834 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1835 break;
1836 }
1837 }
1838
ea5b213a
CW		 1839 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1840 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1841
ea5b213a 1842 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1843 DP_TRAINING_PATTERN_SET,
1844 dp_train_pat);
1845
47ea7542
PZ		 1846 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1847 DP_TRAINING_PATTERN_DISABLE) {
1848 ret = intel_dp_aux_native_write(intel_dp,
1849 DP_TRAINING_LANE0_SET,
1850 intel_dp->train_set,
1851 intel_dp->lane_count);
1852 if (ret != intel_dp->lane_count)
1853 return false;
1854 }
a4fc5ed6
KP		 1855
1856 return true;
1857}
1858
33a34e4e 1859/* Enable corresponding port and start training pattern 1 */
c19b0669 1860void
33a34e4e 1861intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1862{
da63a9f2 1863 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 1864 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 1865 int i;
1866 uint8_t voltage;
1867 bool clock_recovery = false;
cdb0e95b 1868 int voltage_tries, loop_tries;
ea5b213a 1869 uint32_t DP = intel_dp->DP;
a4fc5ed6 1870
affa9354 1871 if (HAS_DDI(dev))
c19b0669
PZ		 1872 intel_ddi_prepare_link_retrain(encoder);
1873
3cf2efb1
CW		 1874 /* Write the link configuration data */
1875 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1876 intel_dp->link_configuration,
1877 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1878
1879 DP |= DP_PORT_EN;
1a2eb460 1880
33a34e4e 1881 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1882 voltage = 0xff;
cdb0e95b
KP		 1883 voltage_tries = 0;
1884 loop_tries = 0;
a4fc5ed6
KP		 1885 clock_recovery = false;
1886 for (;;) {
33a34e4e 1887 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1888 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 1889
1890 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 1891
a7c9655f 1892 /* Set training pattern 1 */
47ea7542 1893 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1894 DP_TRAINING_PATTERN_1 |
1895 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1896 break;
a4fc5ed6 1897
a7c9655f 1898 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 1899 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1900 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1901 break;
93f62dad 1902 }
a4fc5ed6 1903
01916270 1904 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 1905 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1906 clock_recovery = true;
1907 break;
1908 }
1909
1910 /* Check to see if we've tried the max voltage */
1911 for (i = 0; i < intel_dp->lane_count; i++)
1912 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1913 break;
0d710688 1914 if (i == intel_dp->lane_count && voltage_tries == 5) {
b06fbda3
DV		 1915 ++loop_tries;
1916 if (loop_tries == 5) {
cdb0e95b
KP		 1917 DRM_DEBUG_KMS("too many full retries, give up\n");
1918 break;
1919 }
1920 memset(intel_dp->train_set, 0, 4);
1921 voltage_tries = 0;
1922 continue;
1923 }
a4fc5ed6 1924
3cf2efb1 1925 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 1926 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 1927 ++voltage_tries;
b06fbda3
DV		 1928 if (voltage_tries == 5) {
1929 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1930 break;
1931 }
1932 } else
1933 voltage_tries = 0;
1934 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1935
3cf2efb1 1936 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1937 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1938 }
1939
33a34e4e
JB		 1940 intel_dp->DP = DP;
1941}
1942
c19b0669 1943void
33a34e4e
JB		 1944intel_dp_complete_link_train(struct intel_dp *intel_dp)
1945{
33a34e4e 1946 bool channel_eq = false;
37f80975 1947 int tries, cr_tries;
33a34e4e
JB		 1948 uint32_t DP = intel_dp->DP;
1949
a4fc5ed6
KP		 1950 /* channel equalization */
1951 tries = 0;
37f80975 1952 cr_tries = 0;
a4fc5ed6
KP		 1953 channel_eq = false;
1954 for (;;) {
93f62dad 1955 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1956
37f80975
JB		 1957 if (cr_tries > 5) {
1958 DRM_ERROR("failed to train DP, aborting\n");
1959 intel_dp_link_down(intel_dp);
1960 break;
1961 }
1962
f0a3424e 1963 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 1964
a4fc5ed6 1965 /* channel eq pattern */
47ea7542 1966 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1967 DP_TRAINING_PATTERN_2 |
1968 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1969 break;
1970
a7c9655f 1971 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 1972 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1973 break;
a4fc5ed6 1974
37f80975 1975 /* Make sure clock is still ok */
01916270 1976 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1977 intel_dp_start_link_train(intel_dp);
1978 cr_tries++;
1979 continue;
1980 }
1981
1ffdff13 1982 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 1983 channel_eq = true;
1984 break;
1985 }
a4fc5ed6 1986
37f80975
JB		 1987 /* Try 5 times, then try clock recovery if that fails */
1988 if (tries > 5) {
1989 intel_dp_link_down(intel_dp);
1990 intel_dp_start_link_train(intel_dp);
1991 tries = 0;
1992 cr_tries++;
1993 continue;
1994 }
a4fc5ed6 1995
3cf2efb1 1996 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1997 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1998 ++tries;
869184a6 1999 }
3cf2efb1 2000
d6c0d722
PZ		 2001 if (channel_eq)
2002 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2003
47ea7542 2004 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2005}
2006
2007static void
ea5b213a 2008intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2009{
da63a9f2
PZ		 2010 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2011 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2012 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2013 struct intel_crtc *intel_crtc =
2014 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2015 uint32_t DP = intel_dp->DP;
a4fc5ed6 2016
c19b0669
PZ		 2017 /*
2018 * DDI code has a strict mode set sequence and we should try to respect
2019 * it, otherwise we might hang the machine in many different ways. So we
2020 * really should be disabling the port only on a complete crtc_disable
2021 * sequence. This function is just called under two conditions on DDI
2022 * code:
2023 * - Link train failed while doing crtc_enable, and on this case we
2024 * really should respect the mode set sequence and wait for a
2025 * crtc_disable.
2026 * - Someone turned the monitor off and intel_dp_check_link_status
2027 * called us. We don't need to disable the whole port on this case, so
2028 * when someone turns the monitor on again,
2029 * intel_ddi_prepare_link_retrain will take care of redoing the link
2030 * train.
2031 */
affa9354 2032 if (HAS_DDI(dev))
c19b0669
PZ		 2033 return;
2034
0c33d8d7 2035 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2036 return;
2037
28c97730 2038 DRM_DEBUG_KMS("\n");
32f9d658 2039
1a2eb460 2040 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 2041 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2042 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2043 } else {
2044 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2045 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2046 }
fe255d00 2047 POSTING_READ(intel_dp->output_reg);
5eb08b69 2048
ab527efc
DV		 2049 /* We don't really know why we're doing this */
2050 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2051
493a7081 2052 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2053 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2054 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2055
5bddd17f
EA		 2056 /* Hardware workaround: leaving our transcoder select
2057 * set to transcoder B while it's off will prevent the
2058 * corresponding HDMI output on transcoder A.
2059 *
2060 * Combine this with another hardware workaround:
2061 * transcoder select bit can only be cleared while the
2062 * port is enabled.
2063 */
2064 DP &= ~DP_PIPEB_SELECT;
2065 I915_WRITE(intel_dp->output_reg, DP);
2066
2067 /* Changes to enable or select take place the vblank
2068 * after being written.
2069 */
ff50afe9
DV		 2070 if (WARN_ON(crtc == NULL)) {
2071 /* We should never try to disable a port without a crtc
2072 * attached. For paranoia keep the code around for a
2073 * bit. */
31acbcc4
CW		 2074 POSTING_READ(intel_dp->output_reg);
2075 msleep(50);
2076 } else
ab527efc 2077 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2078 }
2079
832afda6 2080 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2081 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2082 POSTING_READ(intel_dp->output_reg);
f01eca2e 2083 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2084}
2085
26d61aad
KP		 2086static bool
2087intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2088{
577c7a50
DL		 2089 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2090
92fd8fd1 2091 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2092 sizeof(intel_dp->dpcd)) == 0)
2093 return false; /* aux transfer failed */
92fd8fd1 2094
577c7a50
DL		 2095 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2096 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2097 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2098
edb39244
AJ		 2099 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2100 return false; /* DPCD not present */
2101
2102 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2103 DP_DWN_STRM_PORT_PRESENT))
2104 return true; /* native DP sink */
2105
2106 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2107 return true; /* no per-port downstream info */
2108
2109 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2110 intel_dp->downstream_ports,
2111 DP_MAX_DOWNSTREAM_PORTS) == 0)
2112 return false; /* downstream port status fetch failed */
2113
2114 return true;
92fd8fd1
KP		 2115}
2116
0d198328
AJ		 2117static void
2118intel_dp_probe_oui(struct intel_dp *intel_dp)
2119{
2120 u8 buf[3];
2121
2122 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2123 return;
2124
351cfc34
DV		 2125 ironlake_edp_panel_vdd_on(intel_dp);
2126
0d198328
AJ		 2127 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2128 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2129 buf[0], buf[1], buf[2]);
2130
2131 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2132 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2133 buf[0], buf[1], buf[2]);
351cfc34
DV		 2134
2135 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2136}
2137
a60f0e38
JB		 2138static bool
2139intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2140{
2141 int ret;
2142
2143 ret = intel_dp_aux_native_read_retry(intel_dp,
2144 DP_DEVICE_SERVICE_IRQ_VECTOR,
2145 sink_irq_vector, 1);
2146 if (!ret)
2147 return false;
2148
2149 return true;
2150}
2151
2152static void
2153intel_dp_handle_test_request(struct intel_dp *intel_dp)
2154{
2155 /* NAK by default */
9324cf7f 2156 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2157}
2158
a4fc5ed6
KP		 2159/*
2160 * According to DP spec
2161 * 5.1.2:
2162 * 1. Read DPCD
2163 * 2. Configure link according to Receiver Capabilities
2164 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2165 * 4. Check link status on receipt of hot-plug interrupt
2166 */
2167
00c09d70 2168void
ea5b213a 2169intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2170{
da63a9f2 2171 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2172 u8 sink_irq_vector;
93f62dad 2173 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2174
da63a9f2 2175 if (!intel_encoder->connectors_active)
d2b996ac 2176 return;
59cd09e1 2177
da63a9f2 2178 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2179 return;
2180
92fd8fd1 2181 /* Try to read receiver status if the link appears to be up */
93f62dad 2182 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2183 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2184 return;
2185 }
2186
92fd8fd1 2187 /* Now read the DPCD to see if it's actually running */
26d61aad 2188 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2189 intel_dp_link_down(intel_dp);
2190 return;
2191 }
2192
a60f0e38
JB		 2193 /* Try to read the source of the interrupt */
2194 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2195 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2196 /* Clear interrupt source */
2197 intel_dp_aux_native_write_1(intel_dp,
2198 DP_DEVICE_SERVICE_IRQ_VECTOR,
2199 sink_irq_vector);
2200
2201 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2202 intel_dp_handle_test_request(intel_dp);
2203 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2204 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2205 }
2206
1ffdff13 2207 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2208 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2209 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2210 intel_dp_start_link_train(intel_dp);
2211 intel_dp_complete_link_train(intel_dp);
2212 }
a4fc5ed6 2213}
a4fc5ed6 2214
caf9ab24 2215/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2216static enum drm_connector_status
26d61aad 2217intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2218{
caf9ab24
AJ		 2219 uint8_t *dpcd = intel_dp->dpcd;
2220 bool hpd;
2221 uint8_t type;
2222
2223 if (!intel_dp_get_dpcd(intel_dp))
2224 return connector_status_disconnected;
2225
2226 /* if there's no downstream port, we're done */
2227 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2228 return connector_status_connected;
caf9ab24
AJ		 2229
2230 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2231 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2232 if (hpd) {
23235177 2233 uint8_t reg;
caf9ab24 2234 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2235 &reg, 1))
caf9ab24 2236 return connector_status_unknown;
23235177
AJ		 2237 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2238 : connector_status_disconnected;
caf9ab24
AJ		 2239 }
2240
2241 /* If no HPD, poke DDC gently */
2242 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2243 return connector_status_connected;
caf9ab24
AJ		 2244
2245 /* Well we tried, say unknown for unreliable port types */
2246 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2247 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2248 return connector_status_unknown;
2249
2250 /* Anything else is out of spec, warn and ignore */
2251 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2252 return connector_status_disconnected;
71ba9000
AJ		 2253}
2254
5eb08b69 2255static enum drm_connector_status
a9756bb5 2256ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2257{
30add22d 2258 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2259 struct drm_i915_private *dev_priv = dev->dev_private;
2260 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2261 enum drm_connector_status status;
2262
fe16d949
CW		 2263 /* Can't disconnect eDP, but you can close the lid... */
2264 if (is_edp(intel_dp)) {
30add22d 2265 status = intel_panel_detect(dev);
fe16d949
CW		 2266 if (status == connector_status_unknown)
2267 status = connector_status_connected;
2268 return status;
2269 }
01cb9ea6 2270
1b469639
DL		 2271 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2272 return connector_status_disconnected;
2273
26d61aad 2274 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2275}
2276
a4fc5ed6 2277static enum drm_connector_status
a9756bb5 2278g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2279{
30add22d 2280 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2281 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 2282 uint32_t bit;
5eb08b69 2283
ea5b213a 2284 switch (intel_dp->output_reg) {
a4fc5ed6 2285 case DP_B:
10f76a38 2286 bit = DPB_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2287 break;
2288 case DP_C:
10f76a38 2289 bit = DPC_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2290 break;
2291 case DP_D:
10f76a38 2292 bit = DPD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2293 break;
2294 default:
2295 return connector_status_unknown;
2296 }
2297
10f76a38 2298 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2299 return connector_status_disconnected;
2300
26d61aad 2301 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2302}
2303
8c241fef
KP		 2304static struct edid *
2305intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2306{
9cd300e0 2307 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2308
9cd300e0
JN		 2309 /* use cached edid if we have one */
2310 if (intel_connector->edid) {
2311 struct edid *edid;
2312 int size;
2313
2314 /* invalid edid */
2315 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2316 return NULL;
2317
9cd300e0 2318 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
d6f24d0f
JB		 2319 edid = kmalloc(size, GFP_KERNEL);
2320 if (!edid)
2321 return NULL;
2322
9cd300e0 2323 memcpy(edid, intel_connector->edid, size);
d6f24d0f
JB		 2324 return edid;
2325 }
8c241fef 2326
9cd300e0 2327 return drm_get_edid(connector, adapter);
8c241fef
KP		 2328}
2329
2330static int
2331intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2332{
9cd300e0 2333 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2334
9cd300e0
JN		 2335 /* use cached edid if we have one */
2336 if (intel_connector->edid) {
2337 /* invalid edid */
2338 if (IS_ERR(intel_connector->edid))
2339 return 0;
2340
2341 return intel_connector_update_modes(connector,
2342 intel_connector->edid);
d6f24d0f
JB		 2343 }
2344
9cd300e0 2345 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2346}
2347
a9756bb5
ZW		 2348static enum drm_connector_status
2349intel_dp_detect(struct drm_connector *connector, bool force)
2350{
2351 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2352 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2353 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2354 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2355 enum drm_connector_status status;
2356 struct edid *edid = NULL;
2357
2358 intel_dp->has_audio = false;
2359
2360 if (HAS_PCH_SPLIT(dev))
2361 status = ironlake_dp_detect(intel_dp);
2362 else
2363 status = g4x_dp_detect(intel_dp);
1b9be9d0 2364
a9756bb5
ZW		 2365 if (status != connector_status_connected)
2366 return status;
2367
0d198328
AJ		 2368 intel_dp_probe_oui(intel_dp);
2369
c3e5f67b
DV		 2370 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2371 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2372 } else {
8c241fef 2373 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2374 if (edid) {
2375 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2376 kfree(edid);
2377 }
a9756bb5
ZW		 2378 }
2379
d63885da
PZ		 2380 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2381 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2382 return connector_status_connected;
a4fc5ed6
KP		 2383}
2384
2385static int intel_dp_get_modes(struct drm_connector *connector)
2386{
df0e9248 2387 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2388 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2389 struct drm_device *dev = connector->dev;
32f9d658 2390 int ret;
a4fc5ed6
KP		 2391
2392 /* We should parse the EDID data and find out if it has an audio sink
2393 */
2394
8c241fef 2395 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2396 if (ret)
32f9d658
ZW		 2397 return ret;
2398
f8779fda 2399 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2400 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2401 struct drm_display_mode *mode;
dd06f90e
JN		 2402 mode = drm_mode_duplicate(dev,
2403 intel_connector->panel.fixed_mode);
f8779fda 2404 if (mode) {
32f9d658
ZW		 2405 drm_mode_probed_add(connector, mode);
2406 return 1;
2407 }
2408 }
2409 return 0;
a4fc5ed6
KP		 2410}
2411
1aad7ac0
CW		 2412static bool
2413intel_dp_detect_audio(struct drm_connector *connector)
2414{
2415 struct intel_dp *intel_dp = intel_attached_dp(connector);
2416 struct edid *edid;
2417 bool has_audio = false;
2418
8c241fef 2419 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2420 if (edid) {
2421 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2422 kfree(edid);
2423 }
2424
2425 return has_audio;
2426}
2427
f684960e
CW		 2428static int
2429intel_dp_set_property(struct drm_connector *connector,
2430 struct drm_property *property,
2431 uint64_t val)
2432{
e953fd7b 2433 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2434 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2435 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2436 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2437 int ret;
2438
662595df 2439 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2440 if (ret)
2441 return ret;
2442
3f43c48d 2443 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2444 int i = val;
2445 bool has_audio;
2446
2447 if (i == intel_dp->force_audio)
f684960e
CW		 2448 return 0;
2449
1aad7ac0 2450 intel_dp->force_audio = i;
f684960e 2451
c3e5f67b 2452 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2453 has_audio = intel_dp_detect_audio(connector);
2454 else
c3e5f67b 2455 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2456
2457 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2458 return 0;
2459
1aad7ac0 2460 intel_dp->has_audio = has_audio;
f684960e
CW		 2461 goto done;
2462 }
2463
e953fd7b
CW		 2464 if (property == dev_priv->broadcast_rgb_property) {
2465 if (val == !!intel_dp->color_range)
2466 return 0;
2467
2468 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2469 goto done;
2470 }
2471
53b41837
YN		 2472 if (is_edp(intel_dp) &&
2473 property == connector->dev->mode_config.scaling_mode_property) {
2474 if (val == DRM_MODE_SCALE_NONE) {
2475 DRM_DEBUG_KMS("no scaling not supported\n");
2476 return -EINVAL;
2477 }
2478
2479 if (intel_connector->panel.fitting_mode == val) {
2480 /* the eDP scaling property is not changed */
2481 return 0;
2482 }
2483 intel_connector->panel.fitting_mode = val;
2484
2485 goto done;
2486 }
2487
f684960e
CW		 2488 return -EINVAL;
2489
2490done:
c0c36b94
CW		 2491 if (intel_encoder->base.crtc)
2492 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 2493
2494 return 0;
2495}
2496
a4fc5ed6 2497static void
0206e353 2498intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2499{
aaa6fd2a 2500 struct drm_device *dev = connector->dev;
be3cd5e3 2501 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2502 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2503
9cd300e0
JN		 2504 if (!IS_ERR_OR_NULL(intel_connector->edid))
2505 kfree(intel_connector->edid);
2506
1d508706 2507 if (is_edp(intel_dp)) {
aaa6fd2a 2508 intel_panel_destroy_backlight(dev);
1d508706
JN		 2509 intel_panel_fini(&intel_connector->panel);
2510 }
aaa6fd2a 2511
a4fc5ed6
KP		 2512 drm_sysfs_connector_remove(connector);
2513 drm_connector_cleanup(connector);
55f78c43 2514 kfree(connector);
a4fc5ed6
KP		 2515}
2516
00c09d70 2517void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 2518{
da63a9f2
PZ		 2519 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2520 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927
DV		 2521
2522 i2c_del_adapter(&intel_dp->adapter);
2523 drm_encoder_cleanup(encoder);
bd943159
KP		 2524 if (is_edp(intel_dp)) {
2525 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2526 ironlake_panel_vdd_off_sync(intel_dp);
2527 }
da63a9f2 2528 kfree(intel_dig_port);
24d05927
DV		 2529}
2530
a4fc5ed6 2531static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2532 .mode_fixup = intel_dp_mode_fixup,
a4fc5ed6 2533 .mode_set = intel_dp_mode_set,
1f703855 2534 .disable = intel_encoder_noop,
a4fc5ed6
KP		 2535};
2536
2537static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2538 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2539 .detect = intel_dp_detect,
2540 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2541 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2542 .destroy = intel_dp_destroy,
2543};
2544
2545static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2546 .get_modes = intel_dp_get_modes,
2547 .mode_valid = intel_dp_mode_valid,
df0e9248 2548 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2549};
2550
a4fc5ed6 2551static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2552 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2553};
2554
995b6762 2555static void
21d40d37 2556intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2557{
fa90ecef 2558 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 2559
885a5014 2560 intel_dp_check_link_status(intel_dp);
c8110e52 2561}
6207937d 2562
e3421a18
ZW		 2563/* Return which DP Port should be selected for Transcoder DP control */
2564int
0206e353 2565intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2566{
2567 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 2568 struct intel_encoder *intel_encoder;
2569 struct intel_dp *intel_dp;
e3421a18 2570
fa90ecef
PZ		 2571 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2572 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 2573
fa90ecef
PZ		 2574 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2575 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 2576 return intel_dp->output_reg;
e3421a18 2577 }
ea5b213a 2578
e3421a18
ZW		 2579 return -1;
2580}
2581
36e83a18 2582/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2583bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2584{
2585 struct drm_i915_private *dev_priv = dev->dev_private;
2586 struct child_device_config *p_child;
2587 int i;
2588
2589 if (!dev_priv->child_dev_num)
2590 return false;
2591
2592 for (i = 0; i < dev_priv->child_dev_num; i++) {
2593 p_child = dev_priv->child_dev + i;
2594
2595 if (p_child->dvo_port == PORT_IDPD &&
2596 p_child->device_type == DEVICE_TYPE_eDP)
2597 return true;
2598 }
2599 return false;
2600}
2601
f684960e
CW		 2602static void
2603intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2604{
53b41837
YN		 2605 struct intel_connector *intel_connector = to_intel_connector(connector);
2606
3f43c48d 2607 intel_attach_force_audio_property(connector);
e953fd7b 2608 intel_attach_broadcast_rgb_property(connector);
53b41837
YN		 2609
2610 if (is_edp(intel_dp)) {
2611 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 2612 drm_object_attach_property(
2613 &connector->base,
53b41837 2614 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 2615 DRM_MODE_SCALE_ASPECT);
2616 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 2617 }
f684960e
CW		 2618}
2619
67a54566
DV		 2620static void
2621intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2622 struct intel_dp *intel_dp)
2623{
2624 struct drm_i915_private *dev_priv = dev->dev_private;
2625 struct edp_power_seq cur, vbt, spec, final;
2626 u32 pp_on, pp_off, pp_div, pp;
2627
2628 /* Workaround: Need to write PP_CONTROL with the unlock key as
2629 * the very first thing. */
2630 pp = ironlake_get_pp_control(dev_priv);
2631 I915_WRITE(PCH_PP_CONTROL, pp);
2632
2633 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2634 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2635 pp_div = I915_READ(PCH_PP_DIVISOR);
2636
2637 /* Pull timing values out of registers */
2638 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2639 PANEL_POWER_UP_DELAY_SHIFT;
2640
2641 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2642 PANEL_LIGHT_ON_DELAY_SHIFT;
2643
2644 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2645 PANEL_LIGHT_OFF_DELAY_SHIFT;
2646
2647 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2648 PANEL_POWER_DOWN_DELAY_SHIFT;
2649
2650 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2651 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2652
2653 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2654 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2655
2656 vbt = dev_priv->edp.pps;
2657
2658 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2659 * our hw here, which are all in 100usec. */
2660 spec.t1_t3 = 210 * 10;
2661 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2662 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2663 spec.t10 = 500 * 10;
2664 /* This one is special and actually in units of 100ms, but zero
2665 * based in the hw (so we need to add 100 ms). But the sw vbt
2666 * table multiplies it with 1000 to make it in units of 100usec,
2667 * too. */
2668 spec.t11_t12 = (510 + 100) * 10;
2669
2670 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2671 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2672
2673 /* Use the max of the register settings and vbt. If both are
2674 * unset, fall back to the spec limits. */
2675#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2676 spec.field : \
2677 max(cur.field, vbt.field))
2678 assign_final(t1_t3);
2679 assign_final(t8);
2680 assign_final(t9);
2681 assign_final(t10);
2682 assign_final(t11_t12);
2683#undef assign_final
2684
2685#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2686 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2687 intel_dp->backlight_on_delay = get_delay(t8);
2688 intel_dp->backlight_off_delay = get_delay(t9);
2689 intel_dp->panel_power_down_delay = get_delay(t10);
2690 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2691#undef get_delay
2692
2693 /* And finally store the new values in the power sequencer. */
2694 pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2695 (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2696 pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2697 (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2698 /* Compute the divisor for the pp clock, simply match the Bspec
2699 * formula. */
2700 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2701 << PP_REFERENCE_DIVIDER_SHIFT;
2702 pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
2703 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2704
2705 /* Haswell doesn't have any port selection bits for the panel
2706 * power sequencer any more. */
2707 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2708 if (is_cpu_edp(intel_dp))
2709 pp_on |= PANEL_POWER_PORT_DP_A;
2710 else
2711 pp_on |= PANEL_POWER_PORT_DP_D;
2712 }
2713
2714 I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2715 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2716 I915_WRITE(PCH_PP_DIVISOR, pp_div);
2717
2718
2719 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2720 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2721 intel_dp->panel_power_cycle_delay);
2722
2723 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2724 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2725
2726 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2727 I915_READ(PCH_PP_ON_DELAYS),
2728 I915_READ(PCH_PP_OFF_DELAYS),
2729 I915_READ(PCH_PP_DIVISOR));
f684960e
CW		 2730}
2731
a4fc5ed6 2732void
f0fec3f2
PZ		 2733intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2734 struct intel_connector *intel_connector)
a4fc5ed6 2735{
f0fec3f2
PZ		 2736 struct drm_connector *connector = &intel_connector->base;
2737 struct intel_dp *intel_dp = &intel_dig_port->dp;
2738 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2739 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 2740 struct drm_i915_private *dev_priv = dev->dev_private;
f8779fda 2741 struct drm_display_mode *fixed_mode = NULL;
174edf1f 2742 enum port port = intel_dig_port->port;
5eb08b69 2743 const char *name = NULL;
b329530c 2744 int type;
a4fc5ed6 2745
0767935e
DV		 2746 /* Preserve the current hw state. */
2747 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 2748 intel_dp->attached_connector = intel_connector;
3d3dc149 2749
f0fec3f2 2750 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
b329530c 2751 if (intel_dpd_is_edp(dev))
ea5b213a 2752 intel_dp->is_pch_edp = true;
b329530c 2753
19c03924
GB		 2754 /*
2755 * FIXME : We need to initialize built-in panels before external panels.
2756 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2757 */
f0fec3f2 2758 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
19c03924
GB		 2759 type = DRM_MODE_CONNECTOR_eDP;
2760 intel_encoder->type = INTEL_OUTPUT_EDP;
f0fec3f2 2761 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2762 type = DRM_MODE_CONNECTOR_eDP;
2763 intel_encoder->type = INTEL_OUTPUT_EDP;
2764 } else {
00c09d70
PZ		 2765 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2766 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2767 * rewrite it.
2768 */
b329530c 2769 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c
AJ		 2770 }
2771
b329530c 2772 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2773 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2774
eb1f8e4f 2775 connector->polled = DRM_CONNECTOR_POLL_HPD;
a4fc5ed6
KP		 2776 connector->interlace_allowed = true;
2777 connector->doublescan_allowed = 0;
2778
f0fec3f2
PZ		 2779 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2780 ironlake_panel_vdd_work);
a4fc5ed6 2781
df0e9248 2782 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2783 drm_sysfs_connector_add(connector);
2784
affa9354 2785 if (HAS_DDI(dev))
bcbc889b
PZ		 2786 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2787 else
2788 intel_connector->get_hw_state = intel_connector_get_hw_state;
2789
e8cb4558 2790
a4fc5ed6 2791 /* Set up the DDC bus. */
ab9d7c30
PZ		 2792 switch (port) {
2793 case PORT_A:
2794 name = "DPDDC-A";
2795 break;
2796 case PORT_B:
2797 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2798 name = "DPDDC-B";
2799 break;
2800 case PORT_C:
2801 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2802 name = "DPDDC-C";
2803 break;
2804 case PORT_D:
2805 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2806 name = "DPDDC-D";
2807 break;
2808 default:
2809 WARN(1, "Invalid port %c\n", port_name(port));
2810 break;
5eb08b69
ZW		 2811 }
2812
67a54566
DV		 2813 if (is_edp(intel_dp))
2814 intel_dp_init_panel_power_sequencer(dev, intel_dp);
c1f05264
DA		 2815
2816 intel_dp_i2c_init(intel_dp, intel_connector, name);
2817
67a54566 2818 /* Cache DPCD and EDID for edp. */
c1f05264
DA		 2819 if (is_edp(intel_dp)) {
2820 bool ret;
f8779fda 2821 struct drm_display_mode *scan;
c1f05264 2822 struct edid *edid;
5d613501
JB		 2823
2824 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2825 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2826 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2827
59f3e272 2828 if (ret) {
7183dc29
JB		 2829 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2830 dev_priv->no_aux_handshake =
2831 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2832 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2833 } else {
3d3dc149 2834 /* if this fails, presume the device is a ghost */
48898b03 2835 DRM_INFO("failed to retrieve link info, disabling eDP\n");
fa90ecef
PZ		 2836 intel_dp_encoder_destroy(&intel_encoder->base);
2837 intel_dp_destroy(connector);
3d3dc149 2838 return;
89667383 2839 }
89667383 2840
d6f24d0f
JB		 2841 ironlake_edp_panel_vdd_on(intel_dp);
2842 edid = drm_get_edid(connector, &intel_dp->adapter);
2843 if (edid) {
9cd300e0
JN		 2844 if (drm_add_edid_modes(connector, edid)) {
2845 drm_mode_connector_update_edid_property(connector, edid);
2846 drm_edid_to_eld(connector, edid);
2847 } else {
2848 kfree(edid);
2849 edid = ERR_PTR(-EINVAL);
2850 }
2851 } else {
2852 edid = ERR_PTR(-ENOENT);
d6f24d0f 2853 }
9cd300e0 2854 intel_connector->edid = edid;
f8779fda
JN		 2855
2856 /* prefer fixed mode from EDID if available */
2857 list_for_each_entry(scan, &connector->probed_modes, head) {
2858 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2859 fixed_mode = drm_mode_duplicate(dev, scan);
2860 break;
2861 }
d6f24d0f 2862 }
f8779fda
JN		 2863
2864 /* fallback to VBT if available for eDP */
2865 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2866 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2867 if (fixed_mode)
2868 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2869 }
f8779fda 2870
d6f24d0f
JB		 2871 ironlake_edp_panel_vdd_off(intel_dp, false);
2872 }
552fb0b7 2873
4d926461 2874 if (is_edp(intel_dp)) {
dd06f90e 2875 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 2876 intel_panel_setup_backlight(connector);
32f9d658
ZW		 2877 }
2878
f684960e
CW		 2879 intel_dp_add_properties(intel_dp, connector);
2880
a4fc5ed6
KP		 2881 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2882 * 0xd. Failure to do so will result in spurious interrupts being
2883 * generated on the port when a cable is not attached.
2884 */
2885 if (IS_G4X(dev) && !IS_GM45(dev)) {
2886 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2887 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2888 }
2889}
f0fec3f2
PZ		 2890
2891void
2892intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2893{
2894 struct intel_digital_port *intel_dig_port;
2895 struct intel_encoder *intel_encoder;
2896 struct drm_encoder *encoder;
2897 struct intel_connector *intel_connector;
2898
2899 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2900 if (!intel_dig_port)
2901 return;
2902
2903 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2904 if (!intel_connector) {
2905 kfree(intel_dig_port);
2906 return;
2907 }
2908
2909 intel_encoder = &intel_dig_port->base;
2910 encoder = &intel_encoder->base;
2911
2912 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2913 DRM_MODE_ENCODER_TMDS);
00c09d70 2914 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
f0fec3f2 2915
00c09d70
PZ		 2916 intel_encoder->enable = intel_enable_dp;
2917 intel_encoder->pre_enable = intel_pre_enable_dp;
2918 intel_encoder->disable = intel_disable_dp;
2919 intel_encoder->post_disable = intel_post_disable_dp;
2920 intel_encoder->get_hw_state = intel_dp_get_hw_state;
f0fec3f2 2921
174edf1f 2922 intel_dig_port->port = port;
f0fec3f2
PZ		 2923 intel_dig_port->dp.output_reg = output_reg;
2924
00c09d70 2925 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 2926 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2927 intel_encoder->cloneable = false;
2928 intel_encoder->hot_plug = intel_dp_hot_plug;
2929
2930 intel_dp_init_connector(intel_dig_port, intel_connector);
2931}
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