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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
760285e7 DH |
31 | #include <drm/drmP.h> |
32 | #include <drm/drm_crtc.h> | |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_edid.h> | |
a4fc5ed6 | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
a4fc5ed6 | 37 | #include "i915_drv.h" |
a4fc5ed6 | 38 | |
a4fc5ed6 KP |
39 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
40 | ||
9dd4ffdf CML |
41 | struct dp_link_dpll { |
42 | int link_bw; | |
43 | struct dpll dpll; | |
44 | }; | |
45 | ||
46 | static const struct dp_link_dpll gen4_dpll[] = { | |
47 | { DP_LINK_BW_1_62, | |
48 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, | |
49 | { DP_LINK_BW_2_7, | |
50 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } | |
51 | }; | |
52 | ||
53 | static const struct dp_link_dpll pch_dpll[] = { | |
54 | { DP_LINK_BW_1_62, | |
55 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, | |
56 | { DP_LINK_BW_2_7, | |
57 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } | |
58 | }; | |
59 | ||
65ce4bf5 CML |
60 | static const struct dp_link_dpll vlv_dpll[] = { |
61 | { DP_LINK_BW_1_62, | |
58f6e632 | 62 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
65ce4bf5 CML |
63 | { DP_LINK_BW_2_7, |
64 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } | |
65 | }; | |
66 | ||
cfcb0fc9 JB |
67 | /** |
68 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
69 | * @intel_dp: DP struct | |
70 | * | |
71 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
72 | * will return true, and false otherwise. | |
73 | */ | |
74 | static bool is_edp(struct intel_dp *intel_dp) | |
75 | { | |
da63a9f2 PZ |
76 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
77 | ||
78 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
79 | } |
80 | ||
68b4d824 | 81 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
cfcb0fc9 | 82 | { |
68b4d824 ID |
83 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
84 | ||
85 | return intel_dig_port->base.base.dev; | |
cfcb0fc9 JB |
86 | } |
87 | ||
df0e9248 CW |
88 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
89 | { | |
fa90ecef | 90 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
91 | } |
92 | ||
ea5b213a | 93 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
a4fc5ed6 | 94 | |
a4fc5ed6 | 95 | static int |
ea5b213a | 96 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
a4fc5ed6 | 97 | { |
7183dc29 | 98 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
99 | |
100 | switch (max_link_bw) { | |
101 | case DP_LINK_BW_1_62: | |
102 | case DP_LINK_BW_2_7: | |
103 | break; | |
d4eead50 ID |
104 | case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ |
105 | max_link_bw = DP_LINK_BW_2_7; | |
106 | break; | |
a4fc5ed6 | 107 | default: |
d4eead50 ID |
108 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
109 | max_link_bw); | |
a4fc5ed6 KP |
110 | max_link_bw = DP_LINK_BW_1_62; |
111 | break; | |
112 | } | |
113 | return max_link_bw; | |
114 | } | |
115 | ||
cd9dde44 AJ |
116 | /* |
117 | * The units on the numbers in the next two are... bizarre. Examples will | |
118 | * make it clearer; this one parallels an example in the eDP spec. | |
119 | * | |
120 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: | |
121 | * | |
122 | * 270000 * 1 * 8 / 10 == 216000 | |
123 | * | |
124 | * The actual data capacity of that configuration is 2.16Gbit/s, so the | |
125 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - | |
126 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be | |
127 | * 119000. At 18bpp that's 2142000 kilobits per second. | |
128 | * | |
129 | * Thus the strange-looking division by 10 in intel_dp_link_required, to | |
130 | * get the result in decakilobits instead of kilobits. | |
131 | */ | |
132 | ||
a4fc5ed6 | 133 | static int |
c898261c | 134 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 135 | { |
cd9dde44 | 136 | return (pixel_clock * bpp + 9) / 10; |
a4fc5ed6 KP |
137 | } |
138 | ||
fe27d53e DA |
139 | static int |
140 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
141 | { | |
142 | return (max_link_clock * max_lanes * 8) / 10; | |
143 | } | |
144 | ||
a4fc5ed6 KP |
145 | static int |
146 | intel_dp_mode_valid(struct drm_connector *connector, | |
147 | struct drm_display_mode *mode) | |
148 | { | |
df0e9248 | 149 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e JN |
150 | struct intel_connector *intel_connector = to_intel_connector(connector); |
151 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
36008365 DV |
152 | int target_clock = mode->clock; |
153 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
a4fc5ed6 | 154 | |
dd06f90e JN |
155 | if (is_edp(intel_dp) && fixed_mode) { |
156 | if (mode->hdisplay > fixed_mode->hdisplay) | |
7de56f43 ZY |
157 | return MODE_PANEL; |
158 | ||
dd06f90e | 159 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 160 | return MODE_PANEL; |
03afc4a2 DV |
161 | |
162 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
163 | } |
164 | ||
36008365 DV |
165 | max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); |
166 | max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); | |
167 | ||
168 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
169 | mode_rate = intel_dp_link_required(target_clock, 18); | |
170 | ||
171 | if (mode_rate > max_rate) | |
c4867936 | 172 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
173 | |
174 | if (mode->clock < 10000) | |
175 | return MODE_CLOCK_LOW; | |
176 | ||
0af78a2b DV |
177 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
178 | return MODE_H_ILLEGAL; | |
179 | ||
a4fc5ed6 KP |
180 | return MODE_OK; |
181 | } | |
182 | ||
183 | static uint32_t | |
184 | pack_aux(uint8_t *src, int src_bytes) | |
185 | { | |
186 | int i; | |
187 | uint32_t v = 0; | |
188 | ||
189 | if (src_bytes > 4) | |
190 | src_bytes = 4; | |
191 | for (i = 0; i < src_bytes; i++) | |
192 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
193 | return v; | |
194 | } | |
195 | ||
196 | static void | |
197 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) | |
198 | { | |
199 | int i; | |
200 | if (dst_bytes > 4) | |
201 | dst_bytes = 4; | |
202 | for (i = 0; i < dst_bytes; i++) | |
203 | dst[i] = src >> ((3-i) * 8); | |
204 | } | |
205 | ||
fb0f8fbf KP |
206 | /* hrawclock is 1/4 the FSB frequency */ |
207 | static int | |
208 | intel_hrawclk(struct drm_device *dev) | |
209 | { | |
210 | struct drm_i915_private *dev_priv = dev->dev_private; | |
211 | uint32_t clkcfg; | |
212 | ||
9473c8f4 VP |
213 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
214 | if (IS_VALLEYVIEW(dev)) | |
215 | return 200; | |
216 | ||
fb0f8fbf KP |
217 | clkcfg = I915_READ(CLKCFG); |
218 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
219 | case CLKCFG_FSB_400: | |
220 | return 100; | |
221 | case CLKCFG_FSB_533: | |
222 | return 133; | |
223 | case CLKCFG_FSB_667: | |
224 | return 166; | |
225 | case CLKCFG_FSB_800: | |
226 | return 200; | |
227 | case CLKCFG_FSB_1067: | |
228 | return 266; | |
229 | case CLKCFG_FSB_1333: | |
230 | return 333; | |
231 | /* these two are just a guess; one of them might be right */ | |
232 | case CLKCFG_FSB_1600: | |
233 | case CLKCFG_FSB_1600_ALT: | |
234 | return 400; | |
235 | default: | |
236 | return 133; | |
237 | } | |
238 | } | |
239 | ||
bf13e81b JN |
240 | static void |
241 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
242 | struct intel_dp *intel_dp, | |
243 | struct edp_power_seq *out); | |
244 | static void | |
245 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
246 | struct intel_dp *intel_dp, | |
247 | struct edp_power_seq *out); | |
248 | ||
249 | static enum pipe | |
250 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
251 | { | |
252 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
253 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
254 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
255 | struct drm_i915_private *dev_priv = dev->dev_private; | |
256 | enum port port = intel_dig_port->port; | |
257 | enum pipe pipe; | |
258 | ||
259 | /* modeset should have pipe */ | |
260 | if (crtc) | |
261 | return to_intel_crtc(crtc)->pipe; | |
262 | ||
263 | /* init time, try to find a pipe with this port selected */ | |
264 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { | |
265 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & | |
266 | PANEL_PORT_SELECT_MASK; | |
267 | if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) | |
268 | return pipe; | |
269 | if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) | |
270 | return pipe; | |
271 | } | |
272 | ||
273 | /* shrug */ | |
274 | return PIPE_A; | |
275 | } | |
276 | ||
277 | static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) | |
278 | { | |
279 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
280 | ||
281 | if (HAS_PCH_SPLIT(dev)) | |
282 | return PCH_PP_CONTROL; | |
283 | else | |
284 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); | |
285 | } | |
286 | ||
287 | static u32 _pp_stat_reg(struct intel_dp *intel_dp) | |
288 | { | |
289 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
290 | ||
291 | if (HAS_PCH_SPLIT(dev)) | |
292 | return PCH_PP_STATUS; | |
293 | else | |
294 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); | |
295 | } | |
296 | ||
ebf33b18 KP |
297 | static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) |
298 | { | |
30add22d | 299 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
ebf33b18 KP |
300 | struct drm_i915_private *dev_priv = dev->dev_private; |
301 | ||
bf13e81b | 302 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
303 | } |
304 | ||
305 | static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) | |
306 | { | |
30add22d | 307 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
ebf33b18 KP |
308 | struct drm_i915_private *dev_priv = dev->dev_private; |
309 | ||
bf13e81b | 310 | return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; |
ebf33b18 KP |
311 | } |
312 | ||
9b984dae KP |
313 | static void |
314 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
315 | { | |
30add22d | 316 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9b984dae | 317 | struct drm_i915_private *dev_priv = dev->dev_private; |
ebf33b18 | 318 | |
9b984dae KP |
319 | if (!is_edp(intel_dp)) |
320 | return; | |
453c5420 | 321 | |
ebf33b18 | 322 | if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
323 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
324 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
bf13e81b JN |
325 | I915_READ(_pp_stat_reg(intel_dp)), |
326 | I915_READ(_pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
327 | } |
328 | } | |
329 | ||
9ee32fea DV |
330 | static uint32_t |
331 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) | |
332 | { | |
333 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
334 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
335 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9ed35ab1 | 336 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
9ee32fea DV |
337 | uint32_t status; |
338 | bool done; | |
339 | ||
ef04f00d | 340 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
9ee32fea | 341 | if (has_aux_irq) |
b18ac466 | 342 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
3598706b | 343 | msecs_to_jiffies_timeout(10)); |
9ee32fea DV |
344 | else |
345 | done = wait_for_atomic(C, 10) == 0; | |
346 | if (!done) | |
347 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", | |
348 | has_aux_irq); | |
349 | #undef C | |
350 | ||
351 | return status; | |
352 | } | |
353 | ||
bc86625a CW |
354 | static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp, |
355 | int index) | |
a4fc5ed6 | 356 | { |
174edf1f PZ |
357 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
358 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
a4fc5ed6 | 359 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ee32fea | 360 | |
a4fc5ed6 | 361 | /* The clock divider is based off the hrawclk, |
fb0f8fbf KP |
362 | * and would like to run at 2MHz. So, take the |
363 | * hrawclk value and divide by 2 and use that | |
6176b8f9 JB |
364 | * |
365 | * Note that PCH attached eDP panels should use a 125MHz input | |
366 | * clock divider. | |
a4fc5ed6 | 367 | */ |
a62d0834 | 368 | if (IS_VALLEYVIEW(dev)) { |
bc86625a | 369 | return index ? 0 : 100; |
a62d0834 | 370 | } else if (intel_dig_port->port == PORT_A) { |
bc86625a CW |
371 | if (index) |
372 | return 0; | |
affa9354 | 373 | if (HAS_DDI(dev)) |
bc86625a | 374 | return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); |
9473c8f4 | 375 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
b84a1cf8 | 376 | return 200; /* SNB & IVB eDP input clock at 400Mhz */ |
e3421a18 | 377 | else |
b84a1cf8 | 378 | return 225; /* eDP input clock at 450Mhz */ |
2c55c336 JN |
379 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
380 | /* Workaround for non-ULT HSW */ | |
bc86625a CW |
381 | switch (index) { |
382 | case 0: return 63; | |
383 | case 1: return 72; | |
384 | default: return 0; | |
385 | } | |
2c55c336 | 386 | } else if (HAS_PCH_SPLIT(dev)) { |
bc86625a | 387 | return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
2c55c336 | 388 | } else { |
bc86625a | 389 | return index ? 0 :intel_hrawclk(dev) / 2; |
2c55c336 | 390 | } |
b84a1cf8 RV |
391 | } |
392 | ||
393 | static int | |
394 | intel_dp_aux_ch(struct intel_dp *intel_dp, | |
395 | uint8_t *send, int send_bytes, | |
396 | uint8_t *recv, int recv_size) | |
397 | { | |
398 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
399 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
400 | struct drm_i915_private *dev_priv = dev->dev_private; | |
401 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; | |
402 | uint32_t ch_data = ch_ctl + 4; | |
bc86625a | 403 | uint32_t aux_clock_divider; |
b84a1cf8 RV |
404 | int i, ret, recv_bytes; |
405 | uint32_t status; | |
bc86625a | 406 | int try, precharge, clock = 0; |
b84a1cf8 RV |
407 | bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev); |
408 | ||
409 | /* dp aux is extremely sensitive to irq latency, hence request the | |
410 | * lowest possible wakeup latency and so prevent the cpu from going into | |
411 | * deep sleep states. | |
412 | */ | |
413 | pm_qos_update_request(&dev_priv->pm_qos, 0); | |
414 | ||
415 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 416 | |
6b4e0a93 DV |
417 | if (IS_GEN6(dev)) |
418 | precharge = 3; | |
419 | else | |
420 | precharge = 5; | |
421 | ||
c67a470b PZ |
422 | intel_aux_display_runtime_get(dev_priv); |
423 | ||
11bee43e JB |
424 | /* Try to wait for any previous AUX channel activity */ |
425 | for (try = 0; try < 3; try++) { | |
ef04f00d | 426 | status = I915_READ_NOTRACE(ch_ctl); |
11bee43e JB |
427 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
428 | break; | |
429 | msleep(1); | |
430 | } | |
431 | ||
432 | if (try == 3) { | |
433 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
434 | I915_READ(ch_ctl)); | |
9ee32fea DV |
435 | ret = -EBUSY; |
436 | goto out; | |
4f7f7b7e CW |
437 | } |
438 | ||
46a5ae9f PZ |
439 | /* Only 5 data registers! */ |
440 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { | |
441 | ret = -E2BIG; | |
442 | goto out; | |
443 | } | |
444 | ||
bc86625a CW |
445 | while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) { |
446 | /* Must try at least 3 times according to DP spec */ | |
447 | for (try = 0; try < 5; try++) { | |
448 | /* Load the send data into the aux channel data registers */ | |
449 | for (i = 0; i < send_bytes; i += 4) | |
450 | I915_WRITE(ch_data + i, | |
451 | pack_aux(send + i, send_bytes - i)); | |
452 | ||
453 | /* Send the command and wait for it to complete */ | |
454 | I915_WRITE(ch_ctl, | |
455 | DP_AUX_CH_CTL_SEND_BUSY | | |
456 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | | |
457 | DP_AUX_CH_CTL_TIME_OUT_400us | | |
458 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
459 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
460 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | | |
461 | DP_AUX_CH_CTL_DONE | | |
462 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
463 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
464 | ||
465 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); | |
466 | ||
467 | /* Clear done status and any errors */ | |
468 | I915_WRITE(ch_ctl, | |
469 | status | | |
470 | DP_AUX_CH_CTL_DONE | | |
471 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
472 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
473 | ||
474 | if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
475 | DP_AUX_CH_CTL_RECEIVE_ERROR)) | |
476 | continue; | |
477 | if (status & DP_AUX_CH_CTL_DONE) | |
478 | break; | |
479 | } | |
4f7f7b7e | 480 | if (status & DP_AUX_CH_CTL_DONE) |
a4fc5ed6 KP |
481 | break; |
482 | } | |
483 | ||
a4fc5ed6 | 484 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 485 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
9ee32fea DV |
486 | ret = -EBUSY; |
487 | goto out; | |
a4fc5ed6 KP |
488 | } |
489 | ||
490 | /* Check for timeout or receive error. | |
491 | * Timeouts occur when the sink is not connected | |
492 | */ | |
a5b3da54 | 493 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 494 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
9ee32fea DV |
495 | ret = -EIO; |
496 | goto out; | |
a5b3da54 | 497 | } |
1ae8c0a5 KP |
498 | |
499 | /* Timeouts occur when the device isn't connected, so they're | |
500 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 501 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 502 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
9ee32fea DV |
503 | ret = -ETIMEDOUT; |
504 | goto out; | |
a4fc5ed6 KP |
505 | } |
506 | ||
507 | /* Unload any bytes sent back from the other side */ | |
508 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
509 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
a4fc5ed6 KP |
510 | if (recv_bytes > recv_size) |
511 | recv_bytes = recv_size; | |
0206e353 | 512 | |
4f7f7b7e CW |
513 | for (i = 0; i < recv_bytes; i += 4) |
514 | unpack_aux(I915_READ(ch_data + i), | |
515 | recv + i, recv_bytes - i); | |
a4fc5ed6 | 516 | |
9ee32fea DV |
517 | ret = recv_bytes; |
518 | out: | |
519 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); | |
c67a470b | 520 | intel_aux_display_runtime_put(dev_priv); |
9ee32fea DV |
521 | |
522 | return ret; | |
a4fc5ed6 KP |
523 | } |
524 | ||
525 | /* Write data to the aux channel in native mode */ | |
526 | static int | |
ea5b213a | 527 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
528 | uint16_t address, uint8_t *send, int send_bytes) |
529 | { | |
530 | int ret; | |
531 | uint8_t msg[20]; | |
532 | int msg_bytes; | |
533 | uint8_t ack; | |
534 | ||
46a5ae9f PZ |
535 | if (WARN_ON(send_bytes > 16)) |
536 | return -E2BIG; | |
537 | ||
9b984dae | 538 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
539 | msg[0] = AUX_NATIVE_WRITE << 4; |
540 | msg[1] = address >> 8; | |
eebc863e | 541 | msg[2] = address & 0xff; |
a4fc5ed6 KP |
542 | msg[3] = send_bytes - 1; |
543 | memcpy(&msg[4], send, send_bytes); | |
544 | msg_bytes = send_bytes + 4; | |
545 | for (;;) { | |
ea5b213a | 546 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
a4fc5ed6 KP |
547 | if (ret < 0) |
548 | return ret; | |
549 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) | |
550 | break; | |
551 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
552 | udelay(100); | |
553 | else | |
a5b3da54 | 554 | return -EIO; |
a4fc5ed6 KP |
555 | } |
556 | return send_bytes; | |
557 | } | |
558 | ||
559 | /* Write a single byte to the aux channel in native mode */ | |
560 | static int | |
ea5b213a | 561 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
562 | uint16_t address, uint8_t byte) |
563 | { | |
ea5b213a | 564 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
a4fc5ed6 KP |
565 | } |
566 | ||
567 | /* read bytes from a native aux channel */ | |
568 | static int | |
ea5b213a | 569 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
a4fc5ed6 KP |
570 | uint16_t address, uint8_t *recv, int recv_bytes) |
571 | { | |
572 | uint8_t msg[4]; | |
573 | int msg_bytes; | |
574 | uint8_t reply[20]; | |
575 | int reply_bytes; | |
576 | uint8_t ack; | |
577 | int ret; | |
578 | ||
46a5ae9f PZ |
579 | if (WARN_ON(recv_bytes > 19)) |
580 | return -E2BIG; | |
581 | ||
9b984dae | 582 | intel_dp_check_edp(intel_dp); |
a4fc5ed6 KP |
583 | msg[0] = AUX_NATIVE_READ << 4; |
584 | msg[1] = address >> 8; | |
585 | msg[2] = address & 0xff; | |
586 | msg[3] = recv_bytes - 1; | |
587 | ||
588 | msg_bytes = 4; | |
589 | reply_bytes = recv_bytes + 1; | |
590 | ||
591 | for (;;) { | |
ea5b213a | 592 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
a4fc5ed6 | 593 | reply, reply_bytes); |
a5b3da54 KP |
594 | if (ret == 0) |
595 | return -EPROTO; | |
596 | if (ret < 0) | |
a4fc5ed6 KP |
597 | return ret; |
598 | ack = reply[0]; | |
599 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { | |
600 | memcpy(recv, reply + 1, ret - 1); | |
601 | return ret - 1; | |
602 | } | |
603 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) | |
604 | udelay(100); | |
605 | else | |
a5b3da54 | 606 | return -EIO; |
a4fc5ed6 KP |
607 | } |
608 | } | |
609 | ||
610 | static int | |
ab2c0672 DA |
611 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
612 | uint8_t write_byte, uint8_t *read_byte) | |
a4fc5ed6 | 613 | { |
ab2c0672 | 614 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
ea5b213a CW |
615 | struct intel_dp *intel_dp = container_of(adapter, |
616 | struct intel_dp, | |
617 | adapter); | |
ab2c0672 DA |
618 | uint16_t address = algo_data->address; |
619 | uint8_t msg[5]; | |
620 | uint8_t reply[2]; | |
8316f337 | 621 | unsigned retry; |
ab2c0672 DA |
622 | int msg_bytes; |
623 | int reply_bytes; | |
624 | int ret; | |
625 | ||
9b984dae | 626 | intel_dp_check_edp(intel_dp); |
ab2c0672 DA |
627 | /* Set up the command byte */ |
628 | if (mode & MODE_I2C_READ) | |
629 | msg[0] = AUX_I2C_READ << 4; | |
630 | else | |
631 | msg[0] = AUX_I2C_WRITE << 4; | |
632 | ||
633 | if (!(mode & MODE_I2C_STOP)) | |
634 | msg[0] |= AUX_I2C_MOT << 4; | |
a4fc5ed6 | 635 | |
ab2c0672 DA |
636 | msg[1] = address >> 8; |
637 | msg[2] = address; | |
638 | ||
639 | switch (mode) { | |
640 | case MODE_I2C_WRITE: | |
641 | msg[3] = 0; | |
642 | msg[4] = write_byte; | |
643 | msg_bytes = 5; | |
644 | reply_bytes = 1; | |
645 | break; | |
646 | case MODE_I2C_READ: | |
647 | msg[3] = 0; | |
648 | msg_bytes = 4; | |
649 | reply_bytes = 2; | |
650 | break; | |
651 | default: | |
652 | msg_bytes = 3; | |
653 | reply_bytes = 1; | |
654 | break; | |
655 | } | |
656 | ||
58c67ce9 JN |
657 | /* |
658 | * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is | |
659 | * required to retry at least seven times upon receiving AUX_DEFER | |
660 | * before giving up the AUX transaction. | |
661 | */ | |
662 | for (retry = 0; retry < 7; retry++) { | |
8316f337 DF |
663 | ret = intel_dp_aux_ch(intel_dp, |
664 | msg, msg_bytes, | |
665 | reply, reply_bytes); | |
ab2c0672 | 666 | if (ret < 0) { |
3ff99164 | 667 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
ab2c0672 DA |
668 | return ret; |
669 | } | |
8316f337 DF |
670 | |
671 | switch (reply[0] & AUX_NATIVE_REPLY_MASK) { | |
672 | case AUX_NATIVE_REPLY_ACK: | |
673 | /* I2C-over-AUX Reply field is only valid | |
674 | * when paired with AUX ACK. | |
675 | */ | |
676 | break; | |
677 | case AUX_NATIVE_REPLY_NACK: | |
678 | DRM_DEBUG_KMS("aux_ch native nack\n"); | |
679 | return -EREMOTEIO; | |
680 | case AUX_NATIVE_REPLY_DEFER: | |
8d16f258 JN |
681 | /* |
682 | * For now, just give more slack to branch devices. We | |
683 | * could check the DPCD for I2C bit rate capabilities, | |
684 | * and if available, adjust the interval. We could also | |
685 | * be more careful with DP-to-Legacy adapters where a | |
686 | * long legacy cable may force very low I2C bit rates. | |
687 | */ | |
688 | if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
689 | DP_DWN_STRM_PORT_PRESENT) | |
690 | usleep_range(500, 600); | |
691 | else | |
692 | usleep_range(300, 400); | |
8316f337 DF |
693 | continue; |
694 | default: | |
695 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", | |
696 | reply[0]); | |
697 | return -EREMOTEIO; | |
698 | } | |
699 | ||
ab2c0672 DA |
700 | switch (reply[0] & AUX_I2C_REPLY_MASK) { |
701 | case AUX_I2C_REPLY_ACK: | |
702 | if (mode == MODE_I2C_READ) { | |
703 | *read_byte = reply[1]; | |
704 | } | |
705 | return reply_bytes - 1; | |
706 | case AUX_I2C_REPLY_NACK: | |
8316f337 | 707 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
ab2c0672 DA |
708 | return -EREMOTEIO; |
709 | case AUX_I2C_REPLY_DEFER: | |
8316f337 | 710 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
ab2c0672 DA |
711 | udelay(100); |
712 | break; | |
713 | default: | |
8316f337 | 714 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
ab2c0672 DA |
715 | return -EREMOTEIO; |
716 | } | |
717 | } | |
8316f337 DF |
718 | |
719 | DRM_ERROR("too many retries, giving up\n"); | |
720 | return -EREMOTEIO; | |
a4fc5ed6 KP |
721 | } |
722 | ||
723 | static int | |
ea5b213a | 724 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
55f78c43 | 725 | struct intel_connector *intel_connector, const char *name) |
a4fc5ed6 | 726 | { |
0b5c541b KP |
727 | int ret; |
728 | ||
d54e9d28 | 729 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
ea5b213a CW |
730 | intel_dp->algo.running = false; |
731 | intel_dp->algo.address = 0; | |
732 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; | |
733 | ||
0206e353 | 734 | memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); |
ea5b213a CW |
735 | intel_dp->adapter.owner = THIS_MODULE; |
736 | intel_dp->adapter.class = I2C_CLASS_DDC; | |
0206e353 | 737 | strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); |
ea5b213a CW |
738 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; |
739 | intel_dp->adapter.algo_data = &intel_dp->algo; | |
740 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; | |
741 | ||
0b5c541b KP |
742 | ironlake_edp_panel_vdd_on(intel_dp); |
743 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); | |
bd943159 | 744 | ironlake_edp_panel_vdd_off(intel_dp, false); |
0b5c541b | 745 | return ret; |
a4fc5ed6 KP |
746 | } |
747 | ||
c6bb3538 DV |
748 | static void |
749 | intel_dp_set_clock(struct intel_encoder *encoder, | |
750 | struct intel_crtc_config *pipe_config, int link_bw) | |
751 | { | |
752 | struct drm_device *dev = encoder->base.dev; | |
9dd4ffdf CML |
753 | const struct dp_link_dpll *divisor = NULL; |
754 | int i, count = 0; | |
c6bb3538 DV |
755 | |
756 | if (IS_G4X(dev)) { | |
9dd4ffdf CML |
757 | divisor = gen4_dpll; |
758 | count = ARRAY_SIZE(gen4_dpll); | |
c6bb3538 DV |
759 | } else if (IS_HASWELL(dev)) { |
760 | /* Haswell has special-purpose DP DDI clocks. */ | |
761 | } else if (HAS_PCH_SPLIT(dev)) { | |
9dd4ffdf CML |
762 | divisor = pch_dpll; |
763 | count = ARRAY_SIZE(pch_dpll); | |
c6bb3538 | 764 | } else if (IS_VALLEYVIEW(dev)) { |
65ce4bf5 CML |
765 | divisor = vlv_dpll; |
766 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 767 | } |
9dd4ffdf CML |
768 | |
769 | if (divisor && count) { | |
770 | for (i = 0; i < count; i++) { | |
771 | if (link_bw == divisor[i].link_bw) { | |
772 | pipe_config->dpll = divisor[i].dpll; | |
773 | pipe_config->clock_set = true; | |
774 | break; | |
775 | } | |
776 | } | |
c6bb3538 DV |
777 | } |
778 | } | |
779 | ||
00c09d70 | 780 | bool |
5bfe2ac0 DV |
781 | intel_dp_compute_config(struct intel_encoder *encoder, |
782 | struct intel_crtc_config *pipe_config) | |
a4fc5ed6 | 783 | { |
5bfe2ac0 | 784 | struct drm_device *dev = encoder->base.dev; |
36008365 | 785 | struct drm_i915_private *dev_priv = dev->dev_private; |
5bfe2ac0 | 786 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
5bfe2ac0 | 787 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 788 | enum port port = dp_to_dig_port(intel_dp)->port; |
2dd24552 | 789 | struct intel_crtc *intel_crtc = encoder->new_crtc; |
dd06f90e | 790 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
a4fc5ed6 | 791 | int lane_count, clock; |
397fe157 | 792 | int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); |
ea5b213a | 793 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; |
083f9560 | 794 | int bpp, mode_rate; |
a4fc5ed6 | 795 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
ff9a6750 | 796 | int link_avail, link_clock; |
a4fc5ed6 | 797 | |
bc7d38a4 | 798 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
5bfe2ac0 DV |
799 | pipe_config->has_pch_encoder = true; |
800 | ||
03afc4a2 | 801 | pipe_config->has_dp_encoder = true; |
a4fc5ed6 | 802 | |
dd06f90e JN |
803 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
804 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, | |
805 | adjusted_mode); | |
2dd24552 JB |
806 | if (!HAS_PCH_SPLIT(dev)) |
807 | intel_gmch_panel_fitting(intel_crtc, pipe_config, | |
808 | intel_connector->panel.fitting_mode); | |
809 | else | |
b074cec8 JB |
810 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
811 | intel_connector->panel.fitting_mode); | |
0d3a1bee ZY |
812 | } |
813 | ||
cb1793ce | 814 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
0af78a2b DV |
815 | return false; |
816 | ||
083f9560 DV |
817 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
818 | "max bw %02x pixel clock %iKHz\n", | |
241bfc38 DL |
819 | max_lane_count, bws[max_clock], |
820 | adjusted_mode->crtc_clock); | |
083f9560 | 821 | |
36008365 DV |
822 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
823 | * bpc in between. */ | |
3e7ca985 | 824 | bpp = pipe_config->pipe_bpp; |
7984211e ID |
825 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) { |
826 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", | |
827 | dev_priv->vbt.edp_bpp); | |
e1b73cba | 828 | bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp); |
7984211e | 829 | } |
657445fe | 830 | |
36008365 | 831 | for (; bpp >= 6*3; bpp -= 2*3) { |
241bfc38 DL |
832 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
833 | bpp); | |
36008365 DV |
834 | |
835 | for (clock = 0; clock <= max_clock; clock++) { | |
836 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { | |
837 | link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); | |
838 | link_avail = intel_dp_max_data_rate(link_clock, | |
839 | lane_count); | |
840 | ||
841 | if (mode_rate <= link_avail) { | |
842 | goto found; | |
843 | } | |
844 | } | |
845 | } | |
846 | } | |
c4867936 | 847 | |
36008365 | 848 | return false; |
3685a8f3 | 849 | |
36008365 | 850 | found: |
55bc60db VS |
851 | if (intel_dp->color_range_auto) { |
852 | /* | |
853 | * See: | |
854 | * CEA-861-E - 5.1 Default Encoding Parameters | |
855 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
856 | */ | |
18316c8c | 857 | if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) |
55bc60db VS |
858 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
859 | else | |
860 | intel_dp->color_range = 0; | |
861 | } | |
862 | ||
3685a8f3 | 863 | if (intel_dp->color_range) |
50f3b016 | 864 | pipe_config->limited_color_range = true; |
a4fc5ed6 | 865 | |
36008365 DV |
866 | intel_dp->link_bw = bws[clock]; |
867 | intel_dp->lane_count = lane_count; | |
657445fe | 868 | pipe_config->pipe_bpp = bpp; |
ff9a6750 | 869 | pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); |
a4fc5ed6 | 870 | |
36008365 DV |
871 | DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", |
872 | intel_dp->link_bw, intel_dp->lane_count, | |
ff9a6750 | 873 | pipe_config->port_clock, bpp); |
36008365 DV |
874 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
875 | mode_rate, link_avail); | |
a4fc5ed6 | 876 | |
03afc4a2 | 877 | intel_link_compute_m_n(bpp, lane_count, |
241bfc38 DL |
878 | adjusted_mode->crtc_clock, |
879 | pipe_config->port_clock, | |
03afc4a2 | 880 | &pipe_config->dp_m_n); |
9d1a455b | 881 | |
c6bb3538 DV |
882 | intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); |
883 | ||
03afc4a2 | 884 | return true; |
a4fc5ed6 KP |
885 | } |
886 | ||
7c62a164 | 887 | static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) |
ea9b6006 | 888 | { |
7c62a164 DV |
889 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
890 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); | |
891 | struct drm_device *dev = crtc->base.dev; | |
ea9b6006 DV |
892 | struct drm_i915_private *dev_priv = dev->dev_private; |
893 | u32 dpa_ctl; | |
894 | ||
ff9a6750 | 895 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); |
ea9b6006 DV |
896 | dpa_ctl = I915_READ(DP_A); |
897 | dpa_ctl &= ~DP_PLL_FREQ_MASK; | |
898 | ||
ff9a6750 | 899 | if (crtc->config.port_clock == 162000) { |
1ce17038 DV |
900 | /* For a long time we've carried around a ILK-DevA w/a for the |
901 | * 160MHz clock. If we're really unlucky, it's still required. | |
902 | */ | |
903 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); | |
ea9b6006 | 904 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
7c62a164 | 905 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
ea9b6006 DV |
906 | } else { |
907 | dpa_ctl |= DP_PLL_FREQ_270MHZ; | |
7c62a164 | 908 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
ea9b6006 | 909 | } |
1ce17038 | 910 | |
ea9b6006 DV |
911 | I915_WRITE(DP_A, dpa_ctl); |
912 | ||
913 | POSTING_READ(DP_A); | |
914 | udelay(500); | |
915 | } | |
916 | ||
b934223d | 917 | static void intel_dp_mode_set(struct intel_encoder *encoder) |
a4fc5ed6 | 918 | { |
b934223d | 919 | struct drm_device *dev = encoder->base.dev; |
417e822d | 920 | struct drm_i915_private *dev_priv = dev->dev_private; |
b934223d | 921 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 922 | enum port port = dp_to_dig_port(intel_dp)->port; |
b934223d DV |
923 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
924 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
a4fc5ed6 | 925 | |
417e822d | 926 | /* |
1a2eb460 | 927 | * There are four kinds of DP registers: |
417e822d KP |
928 | * |
929 | * IBX PCH | |
1a2eb460 KP |
930 | * SNB CPU |
931 | * IVB CPU | |
417e822d KP |
932 | * CPT PCH |
933 | * | |
934 | * IBX PCH and CPU are the same for almost everything, | |
935 | * except that the CPU DP PLL is configured in this | |
936 | * register | |
937 | * | |
938 | * CPT PCH is quite different, having many bits moved | |
939 | * to the TRANS_DP_CTL register instead. That | |
940 | * configuration happens (oddly) in ironlake_pch_enable | |
941 | */ | |
9c9e7927 | 942 | |
417e822d KP |
943 | /* Preserve the BIOS-computed detected bit. This is |
944 | * supposed to be read-only. | |
945 | */ | |
946 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
a4fc5ed6 | 947 | |
417e822d | 948 | /* Handle DP bits in common between all three register formats */ |
417e822d | 949 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
17aa6be9 | 950 | intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); |
a4fc5ed6 | 951 | |
e0dac65e WF |
952 | if (intel_dp->has_audio) { |
953 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", | |
7c62a164 | 954 | pipe_name(crtc->pipe)); |
ea5b213a | 955 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
b934223d | 956 | intel_write_eld(&encoder->base, adjusted_mode); |
e0dac65e | 957 | } |
247d89f6 | 958 | |
417e822d | 959 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 960 | |
bc7d38a4 | 961 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
1a2eb460 KP |
962 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
963 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
964 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
965 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
966 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
967 | ||
6aba5b6c | 968 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
969 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
970 | ||
7c62a164 | 971 | intel_dp->DP |= crtc->pipe << 29; |
bc7d38a4 | 972 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
b2634017 | 973 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) |
3685a8f3 | 974 | intel_dp->DP |= intel_dp->color_range; |
417e822d KP |
975 | |
976 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
977 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
978 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
979 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
980 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
981 | ||
6aba5b6c | 982 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
983 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
984 | ||
7c62a164 | 985 | if (crtc->pipe == 1) |
417e822d | 986 | intel_dp->DP |= DP_PIPEB_SELECT; |
417e822d KP |
987 | } else { |
988 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
32f9d658 | 989 | } |
ea9b6006 | 990 | |
bc7d38a4 | 991 | if (port == PORT_A && !IS_VALLEYVIEW(dev)) |
7c62a164 | 992 | ironlake_set_pll_cpu_edp(intel_dp); |
a4fc5ed6 KP |
993 | } |
994 | ||
99ea7127 KP |
995 | #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
996 | #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
997 | ||
998 | #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) | |
999 | #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
1000 | ||
1001 | #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) | |
1002 | #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
1003 | ||
1004 | static void ironlake_wait_panel_status(struct intel_dp *intel_dp, | |
1005 | u32 mask, | |
1006 | u32 value) | |
bd943159 | 1007 | { |
30add22d | 1008 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
99ea7127 | 1009 | struct drm_i915_private *dev_priv = dev->dev_private; |
453c5420 JB |
1010 | u32 pp_stat_reg, pp_ctrl_reg; |
1011 | ||
bf13e81b JN |
1012 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1013 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 1014 | |
99ea7127 | 1015 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
453c5420 JB |
1016 | mask, value, |
1017 | I915_READ(pp_stat_reg), | |
1018 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1019 | |
453c5420 | 1020 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
99ea7127 | 1021 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
453c5420 JB |
1022 | I915_READ(pp_stat_reg), |
1023 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1024 | } |
99ea7127 | 1025 | } |
32ce697c | 1026 | |
99ea7127 KP |
1027 | static void ironlake_wait_panel_on(struct intel_dp *intel_dp) |
1028 | { | |
1029 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
1030 | ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); | |
bd943159 KP |
1031 | } |
1032 | ||
99ea7127 KP |
1033 | static void ironlake_wait_panel_off(struct intel_dp *intel_dp) |
1034 | { | |
1035 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
1036 | ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); | |
1037 | } | |
1038 | ||
1039 | static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp) | |
1040 | { | |
1041 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); | |
1042 | ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); | |
1043 | } | |
1044 | ||
1045 | ||
832dd3c1 KP |
1046 | /* Read the current pp_control value, unlocking the register if it |
1047 | * is locked | |
1048 | */ | |
1049 | ||
453c5420 | 1050 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 1051 | { |
453c5420 JB |
1052 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1053 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1054 | u32 control; | |
832dd3c1 | 1055 | |
bf13e81b | 1056 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
832dd3c1 KP |
1057 | control &= ~PANEL_UNLOCK_MASK; |
1058 | control |= PANEL_UNLOCK_REGS; | |
1059 | return control; | |
bd943159 KP |
1060 | } |
1061 | ||
82a4d9c0 | 1062 | void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 1063 | { |
30add22d | 1064 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5d613501 JB |
1065 | struct drm_i915_private *dev_priv = dev->dev_private; |
1066 | u32 pp; | |
453c5420 | 1067 | u32 pp_stat_reg, pp_ctrl_reg; |
5d613501 | 1068 | |
97af61f5 KP |
1069 | if (!is_edp(intel_dp)) |
1070 | return; | |
f01eca2e | 1071 | DRM_DEBUG_KMS("Turn eDP VDD on\n"); |
5d613501 | 1072 | |
bd943159 KP |
1073 | WARN(intel_dp->want_panel_vdd, |
1074 | "eDP VDD already requested on\n"); | |
1075 | ||
1076 | intel_dp->want_panel_vdd = true; | |
99ea7127 | 1077 | |
bd943159 KP |
1078 | if (ironlake_edp_have_panel_vdd(intel_dp)) { |
1079 | DRM_DEBUG_KMS("eDP VDD already on\n"); | |
1080 | return; | |
1081 | } | |
1082 | ||
99ea7127 KP |
1083 | if (!ironlake_edp_have_panel_power(intel_dp)) |
1084 | ironlake_wait_panel_power_cycle(intel_dp); | |
1085 | ||
453c5420 | 1086 | pp = ironlake_get_pp_control(intel_dp); |
5d613501 | 1087 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 1088 | |
bf13e81b JN |
1089 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1090 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 JB |
1091 | |
1092 | I915_WRITE(pp_ctrl_reg, pp); | |
1093 | POSTING_READ(pp_ctrl_reg); | |
1094 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1095 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
ebf33b18 KP |
1096 | /* |
1097 | * If the panel wasn't on, delay before accessing aux channel | |
1098 | */ | |
1099 | if (!ironlake_edp_have_panel_power(intel_dp)) { | |
bd943159 | 1100 | DRM_DEBUG_KMS("eDP was not running\n"); |
f01eca2e | 1101 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 1102 | } |
5d613501 JB |
1103 | } |
1104 | ||
bd943159 | 1105 | static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 1106 | { |
30add22d | 1107 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
5d613501 JB |
1108 | struct drm_i915_private *dev_priv = dev->dev_private; |
1109 | u32 pp; | |
453c5420 | 1110 | u32 pp_stat_reg, pp_ctrl_reg; |
5d613501 | 1111 | |
a0e99e68 DV |
1112 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); |
1113 | ||
bd943159 | 1114 | if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { |
453c5420 | 1115 | pp = ironlake_get_pp_control(intel_dp); |
bd943159 | 1116 | pp &= ~EDP_FORCE_VDD; |
bd943159 | 1117 | |
bf13e81b JN |
1118 | pp_stat_reg = _pp_ctrl_reg(intel_dp); |
1119 | pp_ctrl_reg = _pp_stat_reg(intel_dp); | |
453c5420 JB |
1120 | |
1121 | I915_WRITE(pp_ctrl_reg, pp); | |
1122 | POSTING_READ(pp_ctrl_reg); | |
99ea7127 | 1123 | |
453c5420 JB |
1124 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1125 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1126 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
99ea7127 | 1127 | msleep(intel_dp->panel_power_down_delay); |
bd943159 KP |
1128 | } |
1129 | } | |
5d613501 | 1130 | |
bd943159 KP |
1131 | static void ironlake_panel_vdd_work(struct work_struct *__work) |
1132 | { | |
1133 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
1134 | struct intel_dp, panel_vdd_work); | |
30add22d | 1135 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bd943159 | 1136 | |
627f7675 | 1137 | mutex_lock(&dev->mode_config.mutex); |
bd943159 | 1138 | ironlake_panel_vdd_off_sync(intel_dp); |
627f7675 | 1139 | mutex_unlock(&dev->mode_config.mutex); |
bd943159 KP |
1140 | } |
1141 | ||
82a4d9c0 | 1142 | void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 1143 | { |
97af61f5 KP |
1144 | if (!is_edp(intel_dp)) |
1145 | return; | |
5d613501 | 1146 | |
bd943159 KP |
1147 | DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd); |
1148 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); | |
f2e8b18a | 1149 | |
bd943159 KP |
1150 | intel_dp->want_panel_vdd = false; |
1151 | ||
1152 | if (sync) { | |
1153 | ironlake_panel_vdd_off_sync(intel_dp); | |
1154 | } else { | |
1155 | /* | |
1156 | * Queue the timer to fire a long | |
1157 | * time from now (relative to the power down delay) | |
1158 | * to keep the panel power up across a sequence of operations | |
1159 | */ | |
1160 | schedule_delayed_work(&intel_dp->panel_vdd_work, | |
1161 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); | |
1162 | } | |
5d613501 JB |
1163 | } |
1164 | ||
82a4d9c0 | 1165 | void ironlake_edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 1166 | { |
30add22d | 1167 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9934c132 | 1168 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1169 | u32 pp; |
453c5420 | 1170 | u32 pp_ctrl_reg; |
9934c132 | 1171 | |
97af61f5 | 1172 | if (!is_edp(intel_dp)) |
bd943159 | 1173 | return; |
99ea7127 KP |
1174 | |
1175 | DRM_DEBUG_KMS("Turn eDP power on\n"); | |
1176 | ||
1177 | if (ironlake_edp_have_panel_power(intel_dp)) { | |
1178 | DRM_DEBUG_KMS("eDP power already on\n"); | |
7d639f35 | 1179 | return; |
99ea7127 | 1180 | } |
9934c132 | 1181 | |
99ea7127 | 1182 | ironlake_wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 1183 | |
bf13e81b | 1184 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 1185 | pp = ironlake_get_pp_control(intel_dp); |
05ce1a49 KP |
1186 | if (IS_GEN5(dev)) { |
1187 | /* ILK workaround: disable reset around power sequence */ | |
1188 | pp &= ~PANEL_POWER_RESET; | |
bf13e81b JN |
1189 | I915_WRITE(pp_ctrl_reg, pp); |
1190 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 1191 | } |
37c6c9b0 | 1192 | |
1c0ae80a | 1193 | pp |= POWER_TARGET_ON; |
99ea7127 KP |
1194 | if (!IS_GEN5(dev)) |
1195 | pp |= PANEL_POWER_RESET; | |
1196 | ||
453c5420 JB |
1197 | I915_WRITE(pp_ctrl_reg, pp); |
1198 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 1199 | |
99ea7127 | 1200 | ironlake_wait_panel_on(intel_dp); |
9934c132 | 1201 | |
05ce1a49 KP |
1202 | if (IS_GEN5(dev)) { |
1203 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ | |
bf13e81b JN |
1204 | I915_WRITE(pp_ctrl_reg, pp); |
1205 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 1206 | } |
9934c132 JB |
1207 | } |
1208 | ||
82a4d9c0 | 1209 | void ironlake_edp_panel_off(struct intel_dp *intel_dp) |
9934c132 | 1210 | { |
30add22d | 1211 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
9934c132 | 1212 | struct drm_i915_private *dev_priv = dev->dev_private; |
99ea7127 | 1213 | u32 pp; |
453c5420 | 1214 | u32 pp_ctrl_reg; |
9934c132 | 1215 | |
97af61f5 KP |
1216 | if (!is_edp(intel_dp)) |
1217 | return; | |
37c6c9b0 | 1218 | |
99ea7127 | 1219 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
37c6c9b0 | 1220 | |
6cb49835 | 1221 | WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); |
37c6c9b0 | 1222 | |
453c5420 | 1223 | pp = ironlake_get_pp_control(intel_dp); |
35a38556 DV |
1224 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
1225 | * panels get very unhappy and cease to work. */ | |
1226 | pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE); | |
453c5420 | 1227 | |
bf13e81b | 1228 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
1229 | |
1230 | I915_WRITE(pp_ctrl_reg, pp); | |
1231 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 1232 | |
35a38556 DV |
1233 | intel_dp->want_panel_vdd = false; |
1234 | ||
99ea7127 | 1235 | ironlake_wait_panel_off(intel_dp); |
9934c132 JB |
1236 | } |
1237 | ||
d6c50ff8 | 1238 | void ironlake_edp_backlight_on(struct intel_dp *intel_dp) |
32f9d658 | 1239 | { |
da63a9f2 PZ |
1240 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1241 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
32f9d658 | 1242 | struct drm_i915_private *dev_priv = dev->dev_private; |
da63a9f2 | 1243 | int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe; |
32f9d658 | 1244 | u32 pp; |
453c5420 | 1245 | u32 pp_ctrl_reg; |
32f9d658 | 1246 | |
f01eca2e KP |
1247 | if (!is_edp(intel_dp)) |
1248 | return; | |
1249 | ||
28c97730 | 1250 | DRM_DEBUG_KMS("\n"); |
01cb9ea6 JB |
1251 | /* |
1252 | * If we enable the backlight right away following a panel power | |
1253 | * on, we may see slight flicker as the panel syncs with the eDP | |
1254 | * link. So delay a bit to make sure the image is solid before | |
1255 | * allowing it to appear. | |
1256 | */ | |
f01eca2e | 1257 | msleep(intel_dp->backlight_on_delay); |
453c5420 | 1258 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 1259 | pp |= EDP_BLC_ENABLE; |
453c5420 | 1260 | |
bf13e81b | 1261 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
1262 | |
1263 | I915_WRITE(pp_ctrl_reg, pp); | |
1264 | POSTING_READ(pp_ctrl_reg); | |
035aa3de DV |
1265 | |
1266 | intel_panel_enable_backlight(dev, pipe); | |
32f9d658 ZW |
1267 | } |
1268 | ||
d6c50ff8 | 1269 | void ironlake_edp_backlight_off(struct intel_dp *intel_dp) |
32f9d658 | 1270 | { |
30add22d | 1271 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
32f9d658 ZW |
1272 | struct drm_i915_private *dev_priv = dev->dev_private; |
1273 | u32 pp; | |
453c5420 | 1274 | u32 pp_ctrl_reg; |
32f9d658 | 1275 | |
f01eca2e KP |
1276 | if (!is_edp(intel_dp)) |
1277 | return; | |
1278 | ||
035aa3de DV |
1279 | intel_panel_disable_backlight(dev); |
1280 | ||
28c97730 | 1281 | DRM_DEBUG_KMS("\n"); |
453c5420 | 1282 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 1283 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 1284 | |
bf13e81b | 1285 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
1286 | |
1287 | I915_WRITE(pp_ctrl_reg, pp); | |
1288 | POSTING_READ(pp_ctrl_reg); | |
f01eca2e | 1289 | msleep(intel_dp->backlight_off_delay); |
32f9d658 | 1290 | } |
a4fc5ed6 | 1291 | |
2bd2ad64 | 1292 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
d240f20f | 1293 | { |
da63a9f2 PZ |
1294 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1295 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
1296 | struct drm_device *dev = crtc->dev; | |
d240f20f JB |
1297 | struct drm_i915_private *dev_priv = dev->dev_private; |
1298 | u32 dpa_ctl; | |
1299 | ||
2bd2ad64 DV |
1300 | assert_pipe_disabled(dev_priv, |
1301 | to_intel_crtc(crtc)->pipe); | |
1302 | ||
d240f20f JB |
1303 | DRM_DEBUG_KMS("\n"); |
1304 | dpa_ctl = I915_READ(DP_A); | |
0767935e DV |
1305 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
1306 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); | |
1307 | ||
1308 | /* We don't adjust intel_dp->DP while tearing down the link, to | |
1309 | * facilitate link retraining (e.g. after hotplug). Hence clear all | |
1310 | * enable bits here to ensure that we don't enable too much. */ | |
1311 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); | |
1312 | intel_dp->DP |= DP_PLL_ENABLE; | |
1313 | I915_WRITE(DP_A, intel_dp->DP); | |
298b0b39 JB |
1314 | POSTING_READ(DP_A); |
1315 | udelay(200); | |
d240f20f JB |
1316 | } |
1317 | ||
2bd2ad64 | 1318 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
d240f20f | 1319 | { |
da63a9f2 PZ |
1320 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1321 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; | |
1322 | struct drm_device *dev = crtc->dev; | |
d240f20f JB |
1323 | struct drm_i915_private *dev_priv = dev->dev_private; |
1324 | u32 dpa_ctl; | |
1325 | ||
2bd2ad64 DV |
1326 | assert_pipe_disabled(dev_priv, |
1327 | to_intel_crtc(crtc)->pipe); | |
1328 | ||
d240f20f | 1329 | dpa_ctl = I915_READ(DP_A); |
0767935e DV |
1330 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
1331 | "dp pll off, should be on\n"); | |
1332 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); | |
1333 | ||
1334 | /* We can't rely on the value tracked for the DP register in | |
1335 | * intel_dp->DP because link_down must not change that (otherwise link | |
1336 | * re-training will fail. */ | |
298b0b39 | 1337 | dpa_ctl &= ~DP_PLL_ENABLE; |
d240f20f | 1338 | I915_WRITE(DP_A, dpa_ctl); |
1af5fa1b | 1339 | POSTING_READ(DP_A); |
d240f20f JB |
1340 | udelay(200); |
1341 | } | |
1342 | ||
c7ad3810 | 1343 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 1344 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 JB |
1345 | { |
1346 | int ret, i; | |
1347 | ||
1348 | /* Should have a valid DPCD by this point */ | |
1349 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
1350 | return; | |
1351 | ||
1352 | if (mode != DRM_MODE_DPMS_ON) { | |
1353 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, | |
1354 | DP_SET_POWER_D3); | |
1355 | if (ret != 1) | |
1356 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); | |
1357 | } else { | |
1358 | /* | |
1359 | * When turning on, we need to retry for 1ms to give the sink | |
1360 | * time to wake up. | |
1361 | */ | |
1362 | for (i = 0; i < 3; i++) { | |
1363 | ret = intel_dp_aux_native_write_1(intel_dp, | |
1364 | DP_SET_POWER, | |
1365 | DP_SET_POWER_D0); | |
1366 | if (ret == 1) | |
1367 | break; | |
1368 | msleep(1); | |
1369 | } | |
1370 | } | |
1371 | } | |
1372 | ||
19d8fe15 DV |
1373 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
1374 | enum pipe *pipe) | |
d240f20f | 1375 | { |
19d8fe15 | 1376 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1377 | enum port port = dp_to_dig_port(intel_dp)->port; |
19d8fe15 DV |
1378 | struct drm_device *dev = encoder->base.dev; |
1379 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1380 | u32 tmp = I915_READ(intel_dp->output_reg); | |
1381 | ||
1382 | if (!(tmp & DP_PORT_EN)) | |
1383 | return false; | |
1384 | ||
bc7d38a4 | 1385 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
19d8fe15 | 1386 | *pipe = PORT_TO_PIPE_CPT(tmp); |
bc7d38a4 | 1387 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
19d8fe15 DV |
1388 | *pipe = PORT_TO_PIPE(tmp); |
1389 | } else { | |
1390 | u32 trans_sel; | |
1391 | u32 trans_dp; | |
1392 | int i; | |
1393 | ||
1394 | switch (intel_dp->output_reg) { | |
1395 | case PCH_DP_B: | |
1396 | trans_sel = TRANS_DP_PORT_SEL_B; | |
1397 | break; | |
1398 | case PCH_DP_C: | |
1399 | trans_sel = TRANS_DP_PORT_SEL_C; | |
1400 | break; | |
1401 | case PCH_DP_D: | |
1402 | trans_sel = TRANS_DP_PORT_SEL_D; | |
1403 | break; | |
1404 | default: | |
1405 | return true; | |
1406 | } | |
1407 | ||
1408 | for_each_pipe(i) { | |
1409 | trans_dp = I915_READ(TRANS_DP_CTL(i)); | |
1410 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { | |
1411 | *pipe = i; | |
1412 | return true; | |
1413 | } | |
1414 | } | |
19d8fe15 | 1415 | |
4a0833ec DV |
1416 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
1417 | intel_dp->output_reg); | |
1418 | } | |
d240f20f | 1419 | |
19d8fe15 DV |
1420 | return true; |
1421 | } | |
d240f20f | 1422 | |
045ac3b5 JB |
1423 | static void intel_dp_get_config(struct intel_encoder *encoder, |
1424 | struct intel_crtc_config *pipe_config) | |
1425 | { | |
1426 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
045ac3b5 | 1427 | u32 tmp, flags = 0; |
63000ef6 XZ |
1428 | struct drm_device *dev = encoder->base.dev; |
1429 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1430 | enum port port = dp_to_dig_port(intel_dp)->port; | |
1431 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
18442d08 | 1432 | int dotclock; |
045ac3b5 | 1433 | |
63000ef6 XZ |
1434 | if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { |
1435 | tmp = I915_READ(intel_dp->output_reg); | |
1436 | if (tmp & DP_SYNC_HS_HIGH) | |
1437 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1438 | else | |
1439 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 1440 | |
63000ef6 XZ |
1441 | if (tmp & DP_SYNC_VS_HIGH) |
1442 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1443 | else | |
1444 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1445 | } else { | |
1446 | tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); | |
1447 | if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
1448 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1449 | else | |
1450 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 1451 | |
63000ef6 XZ |
1452 | if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
1453 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1454 | else | |
1455 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1456 | } | |
045ac3b5 JB |
1457 | |
1458 | pipe_config->adjusted_mode.flags |= flags; | |
f1f644dc | 1459 | |
eb14cb74 VS |
1460 | pipe_config->has_dp_encoder = true; |
1461 | ||
1462 | intel_dp_get_m_n(crtc, pipe_config); | |
1463 | ||
18442d08 | 1464 | if (port == PORT_A) { |
f1f644dc JB |
1465 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) |
1466 | pipe_config->port_clock = 162000; | |
1467 | else | |
1468 | pipe_config->port_clock = 270000; | |
1469 | } | |
18442d08 VS |
1470 | |
1471 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, | |
1472 | &pipe_config->dp_m_n); | |
1473 | ||
1474 | if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) | |
1475 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
1476 | ||
241bfc38 | 1477 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
1478 | } |
1479 | ||
a031d709 | 1480 | static bool is_edp_psr(struct drm_device *dev) |
2293bb5c | 1481 | { |
a031d709 RV |
1482 | struct drm_i915_private *dev_priv = dev->dev_private; |
1483 | ||
1484 | return dev_priv->psr.sink_support; | |
2293bb5c SK |
1485 | } |
1486 | ||
2b28bb1b RV |
1487 | static bool intel_edp_is_psr_enabled(struct drm_device *dev) |
1488 | { | |
1489 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1490 | ||
18b5992c | 1491 | if (!HAS_PSR(dev)) |
2b28bb1b RV |
1492 | return false; |
1493 | ||
18b5992c | 1494 | return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; |
2b28bb1b RV |
1495 | } |
1496 | ||
1497 | static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, | |
1498 | struct edp_vsc_psr *vsc_psr) | |
1499 | { | |
1500 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
1501 | struct drm_device *dev = dig_port->base.base.dev; | |
1502 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1503 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); | |
1504 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); | |
1505 | u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); | |
1506 | uint32_t *data = (uint32_t *) vsc_psr; | |
1507 | unsigned int i; | |
1508 | ||
1509 | /* As per BSPec (Pipe Video Data Island Packet), we need to disable | |
1510 | the video DIP being updated before program video DIP data buffer | |
1511 | registers for DIP being updated. */ | |
1512 | I915_WRITE(ctl_reg, 0); | |
1513 | POSTING_READ(ctl_reg); | |
1514 | ||
1515 | for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { | |
1516 | if (i < sizeof(struct edp_vsc_psr)) | |
1517 | I915_WRITE(data_reg + i, *data++); | |
1518 | else | |
1519 | I915_WRITE(data_reg + i, 0); | |
1520 | } | |
1521 | ||
1522 | I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); | |
1523 | POSTING_READ(ctl_reg); | |
1524 | } | |
1525 | ||
1526 | static void intel_edp_psr_setup(struct intel_dp *intel_dp) | |
1527 | { | |
1528 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1529 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1530 | struct edp_vsc_psr psr_vsc; | |
1531 | ||
1532 | if (intel_dp->psr_setup_done) | |
1533 | return; | |
1534 | ||
1535 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ | |
1536 | memset(&psr_vsc, 0, sizeof(psr_vsc)); | |
1537 | psr_vsc.sdp_header.HB0 = 0; | |
1538 | psr_vsc.sdp_header.HB1 = 0x7; | |
1539 | psr_vsc.sdp_header.HB2 = 0x2; | |
1540 | psr_vsc.sdp_header.HB3 = 0x8; | |
1541 | intel_edp_psr_write_vsc(intel_dp, &psr_vsc); | |
1542 | ||
1543 | /* Avoid continuous PSR exit by masking memup and hpd */ | |
18b5992c | 1544 | I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | |
2b28bb1b RV |
1545 | EDP_PSR_DEBUG_MASK_HPD); |
1546 | ||
1547 | intel_dp->psr_setup_done = true; | |
1548 | } | |
1549 | ||
1550 | static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) | |
1551 | { | |
1552 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bc86625a | 1554 | uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0); |
2b28bb1b RV |
1555 | int precharge = 0x3; |
1556 | int msg_size = 5; /* Header(4) + Message(1) */ | |
1557 | ||
1558 | /* Enable PSR in sink */ | |
1559 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) | |
1560 | intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, | |
1561 | DP_PSR_ENABLE & | |
1562 | ~DP_PSR_MAIN_LINK_ACTIVE); | |
1563 | else | |
1564 | intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG, | |
1565 | DP_PSR_ENABLE | | |
1566 | DP_PSR_MAIN_LINK_ACTIVE); | |
1567 | ||
1568 | /* Setup AUX registers */ | |
18b5992c BW |
1569 | I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); |
1570 | I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); | |
1571 | I915_WRITE(EDP_PSR_AUX_CTL(dev), | |
2b28bb1b RV |
1572 | DP_AUX_CH_CTL_TIME_OUT_400us | |
1573 | (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
1574 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
1575 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); | |
1576 | } | |
1577 | ||
1578 | static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) | |
1579 | { | |
1580 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1581 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1582 | uint32_t max_sleep_time = 0x1f; | |
1583 | uint32_t idle_frames = 1; | |
1584 | uint32_t val = 0x0; | |
1585 | ||
1586 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { | |
1587 | val |= EDP_PSR_LINK_STANDBY; | |
1588 | val |= EDP_PSR_TP2_TP3_TIME_0us; | |
1589 | val |= EDP_PSR_TP1_TIME_0us; | |
1590 | val |= EDP_PSR_SKIP_AUX_EXIT; | |
1591 | } else | |
1592 | val |= EDP_PSR_LINK_DISABLE; | |
1593 | ||
18b5992c | 1594 | I915_WRITE(EDP_PSR_CTL(dev), val | |
2b28bb1b RV |
1595 | EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES | |
1596 | max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | | |
1597 | idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | | |
1598 | EDP_PSR_ENABLE); | |
1599 | } | |
1600 | ||
3f51e471 RV |
1601 | static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) |
1602 | { | |
1603 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
1604 | struct drm_device *dev = dig_port->base.base.dev; | |
1605 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1606 | struct drm_crtc *crtc = dig_port->base.base.crtc; | |
1607 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1608 | struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj; | |
1609 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; | |
1610 | ||
a031d709 RV |
1611 | dev_priv->psr.source_ok = false; |
1612 | ||
18b5992c | 1613 | if (!HAS_PSR(dev)) { |
3f51e471 | 1614 | DRM_DEBUG_KMS("PSR not supported on this platform\n"); |
3f51e471 RV |
1615 | return false; |
1616 | } | |
1617 | ||
1618 | if ((intel_encoder->type != INTEL_OUTPUT_EDP) || | |
1619 | (dig_port->port != PORT_A)) { | |
1620 | DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); | |
3f51e471 RV |
1621 | return false; |
1622 | } | |
1623 | ||
105b7c11 RV |
1624 | if (!i915_enable_psr) { |
1625 | DRM_DEBUG_KMS("PSR disable by flag\n"); | |
105b7c11 RV |
1626 | return false; |
1627 | } | |
1628 | ||
cd234b0b CW |
1629 | crtc = dig_port->base.base.crtc; |
1630 | if (crtc == NULL) { | |
1631 | DRM_DEBUG_KMS("crtc not active for PSR\n"); | |
cd234b0b CW |
1632 | return false; |
1633 | } | |
1634 | ||
1635 | intel_crtc = to_intel_crtc(crtc); | |
20ddf665 | 1636 | if (!intel_crtc_active(crtc)) { |
3f51e471 | 1637 | DRM_DEBUG_KMS("crtc not active for PSR\n"); |
3f51e471 RV |
1638 | return false; |
1639 | } | |
1640 | ||
cd234b0b | 1641 | obj = to_intel_framebuffer(crtc->fb)->obj; |
3f51e471 RV |
1642 | if (obj->tiling_mode != I915_TILING_X || |
1643 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
1644 | DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n"); | |
3f51e471 RV |
1645 | return false; |
1646 | } | |
1647 | ||
1648 | if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) { | |
1649 | DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n"); | |
3f51e471 RV |
1650 | return false; |
1651 | } | |
1652 | ||
1653 | if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & | |
1654 | S3D_ENABLE) { | |
1655 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); | |
3f51e471 RV |
1656 | return false; |
1657 | } | |
1658 | ||
ca73b4f0 | 1659 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
3f51e471 | 1660 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
3f51e471 RV |
1661 | return false; |
1662 | } | |
1663 | ||
a031d709 | 1664 | dev_priv->psr.source_ok = true; |
3f51e471 RV |
1665 | return true; |
1666 | } | |
1667 | ||
3d739d92 | 1668 | static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) |
2b28bb1b RV |
1669 | { |
1670 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1671 | ||
3f51e471 RV |
1672 | if (!intel_edp_psr_match_conditions(intel_dp) || |
1673 | intel_edp_is_psr_enabled(dev)) | |
2b28bb1b RV |
1674 | return; |
1675 | ||
1676 | /* Setup PSR once */ | |
1677 | intel_edp_psr_setup(intel_dp); | |
1678 | ||
1679 | /* Enable PSR on the panel */ | |
1680 | intel_edp_psr_enable_sink(intel_dp); | |
1681 | ||
1682 | /* Enable PSR on the host */ | |
1683 | intel_edp_psr_enable_source(intel_dp); | |
1684 | } | |
1685 | ||
3d739d92 RV |
1686 | void intel_edp_psr_enable(struct intel_dp *intel_dp) |
1687 | { | |
1688 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1689 | ||
1690 | if (intel_edp_psr_match_conditions(intel_dp) && | |
1691 | !intel_edp_is_psr_enabled(dev)) | |
1692 | intel_edp_psr_do_enable(intel_dp); | |
1693 | } | |
1694 | ||
2b28bb1b RV |
1695 | void intel_edp_psr_disable(struct intel_dp *intel_dp) |
1696 | { | |
1697 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1698 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1699 | ||
1700 | if (!intel_edp_is_psr_enabled(dev)) | |
1701 | return; | |
1702 | ||
18b5992c BW |
1703 | I915_WRITE(EDP_PSR_CTL(dev), |
1704 | I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); | |
2b28bb1b RV |
1705 | |
1706 | /* Wait till PSR is idle */ | |
18b5992c | 1707 | if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & |
2b28bb1b RV |
1708 | EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) |
1709 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); | |
1710 | } | |
1711 | ||
3d739d92 RV |
1712 | void intel_edp_psr_update(struct drm_device *dev) |
1713 | { | |
1714 | struct intel_encoder *encoder; | |
1715 | struct intel_dp *intel_dp = NULL; | |
1716 | ||
1717 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) | |
1718 | if (encoder->type == INTEL_OUTPUT_EDP) { | |
1719 | intel_dp = enc_to_intel_dp(&encoder->base); | |
1720 | ||
a031d709 | 1721 | if (!is_edp_psr(dev)) |
3d739d92 RV |
1722 | return; |
1723 | ||
1724 | if (!intel_edp_psr_match_conditions(intel_dp)) | |
1725 | intel_edp_psr_disable(intel_dp); | |
1726 | else | |
1727 | if (!intel_edp_is_psr_enabled(dev)) | |
1728 | intel_edp_psr_do_enable(intel_dp); | |
1729 | } | |
1730 | } | |
1731 | ||
e8cb4558 | 1732 | static void intel_disable_dp(struct intel_encoder *encoder) |
d240f20f | 1733 | { |
e8cb4558 | 1734 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 ID |
1735 | enum port port = dp_to_dig_port(intel_dp)->port; |
1736 | struct drm_device *dev = encoder->base.dev; | |
6cb49835 DV |
1737 | |
1738 | /* Make sure the panel is off before trying to change the mode. But also | |
1739 | * ensure that we have vdd while we switch off the panel. */ | |
1740 | ironlake_edp_panel_vdd_on(intel_dp); | |
21264c63 | 1741 | ironlake_edp_backlight_off(intel_dp); |
c7ad3810 | 1742 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
35a38556 | 1743 | ironlake_edp_panel_off(intel_dp); |
3739850b DV |
1744 | |
1745 | /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ | |
982a3866 | 1746 | if (!(port == PORT_A || IS_VALLEYVIEW(dev))) |
3739850b | 1747 | intel_dp_link_down(intel_dp); |
d240f20f JB |
1748 | } |
1749 | ||
2bd2ad64 | 1750 | static void intel_post_disable_dp(struct intel_encoder *encoder) |
d240f20f | 1751 | { |
2bd2ad64 | 1752 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 1753 | enum port port = dp_to_dig_port(intel_dp)->port; |
b2634017 | 1754 | struct drm_device *dev = encoder->base.dev; |
2bd2ad64 | 1755 | |
982a3866 | 1756 | if (port == PORT_A || IS_VALLEYVIEW(dev)) { |
3739850b | 1757 | intel_dp_link_down(intel_dp); |
b2634017 JB |
1758 | if (!IS_VALLEYVIEW(dev)) |
1759 | ironlake_edp_pll_off(intel_dp); | |
3739850b | 1760 | } |
2bd2ad64 DV |
1761 | } |
1762 | ||
e8cb4558 | 1763 | static void intel_enable_dp(struct intel_encoder *encoder) |
d240f20f | 1764 | { |
e8cb4558 DV |
1765 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1766 | struct drm_device *dev = encoder->base.dev; | |
1767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1768 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); | |
5d613501 | 1769 | |
0c33d8d7 DV |
1770 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
1771 | return; | |
5d613501 | 1772 | |
97af61f5 | 1773 | ironlake_edp_panel_vdd_on(intel_dp); |
f01eca2e | 1774 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 1775 | intel_dp_start_link_train(intel_dp); |
97af61f5 | 1776 | ironlake_edp_panel_on(intel_dp); |
bd943159 | 1777 | ironlake_edp_panel_vdd_off(intel_dp, true); |
33a34e4e | 1778 | intel_dp_complete_link_train(intel_dp); |
3ab9c637 | 1779 | intel_dp_stop_link_train(intel_dp); |
ab1f90f9 | 1780 | } |
89b667f8 | 1781 | |
ecff4f3b JN |
1782 | static void g4x_enable_dp(struct intel_encoder *encoder) |
1783 | { | |
828f5c6e JN |
1784 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1785 | ||
ecff4f3b | 1786 | intel_enable_dp(encoder); |
f01eca2e | 1787 | ironlake_edp_backlight_on(intel_dp); |
ab1f90f9 | 1788 | } |
89b667f8 | 1789 | |
ab1f90f9 JN |
1790 | static void vlv_enable_dp(struct intel_encoder *encoder) |
1791 | { | |
828f5c6e JN |
1792 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1793 | ||
1794 | ironlake_edp_backlight_on(intel_dp); | |
d240f20f JB |
1795 | } |
1796 | ||
ecff4f3b | 1797 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
ab1f90f9 JN |
1798 | { |
1799 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
1800 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
1801 | ||
1802 | if (dport->port == PORT_A) | |
1803 | ironlake_edp_pll_on(intel_dp); | |
1804 | } | |
1805 | ||
1806 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) | |
a4fc5ed6 | 1807 | { |
2bd2ad64 | 1808 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1809 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
b2634017 | 1810 | struct drm_device *dev = encoder->base.dev; |
89b667f8 | 1811 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab1f90f9 JN |
1812 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
1813 | int port = vlv_dport_to_channel(dport); | |
1814 | int pipe = intel_crtc->pipe; | |
bf13e81b | 1815 | struct edp_power_seq power_seq; |
ab1f90f9 | 1816 | u32 val; |
a4fc5ed6 | 1817 | |
ab1f90f9 | 1818 | mutex_lock(&dev_priv->dpio_lock); |
89b667f8 | 1819 | |
5e69f97f | 1820 | val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port)); |
ab1f90f9 JN |
1821 | val = 0; |
1822 | if (pipe) | |
1823 | val |= (1<<21); | |
1824 | else | |
1825 | val &= ~(1<<21); | |
1826 | val |= 0x001000c4; | |
5e69f97f CML |
1827 | vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val); |
1828 | vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018); | |
1829 | vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888); | |
89b667f8 | 1830 | |
ab1f90f9 JN |
1831 | mutex_unlock(&dev_priv->dpio_lock); |
1832 | ||
bf13e81b JN |
1833 | /* init power sequencer on this pipe and port */ |
1834 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); | |
1835 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, | |
1836 | &power_seq); | |
1837 | ||
ab1f90f9 JN |
1838 | intel_enable_dp(encoder); |
1839 | ||
1840 | vlv_wait_port_ready(dev_priv, port); | |
89b667f8 JB |
1841 | } |
1842 | ||
ecff4f3b | 1843 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1844 | { |
1845 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1846 | struct drm_device *dev = encoder->base.dev; | |
1847 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
1848 | struct intel_crtc *intel_crtc = |
1849 | to_intel_crtc(encoder->base.crtc); | |
89b667f8 | 1850 | int port = vlv_dport_to_channel(dport); |
5e69f97f | 1851 | int pipe = intel_crtc->pipe; |
89b667f8 | 1852 | |
89b667f8 | 1853 | /* Program Tx lane resets to default */ |
0980a60f | 1854 | mutex_lock(&dev_priv->dpio_lock); |
5e69f97f | 1855 | vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port), |
89b667f8 JB |
1856 | DPIO_PCS_TX_LANE2_RESET | |
1857 | DPIO_PCS_TX_LANE1_RESET); | |
5e69f97f | 1858 | vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port), |
89b667f8 JB |
1859 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1860 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1861 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1862 | DPIO_PCS_CLK_SOFT_RESET); | |
1863 | ||
1864 | /* Fix up inter-pair skew failure */ | |
5e69f97f CML |
1865 | vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00); |
1866 | vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500); | |
1867 | vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000); | |
0980a60f | 1868 | mutex_unlock(&dev_priv->dpio_lock); |
a4fc5ed6 KP |
1869 | } |
1870 | ||
1871 | /* | |
df0c237d JB |
1872 | * Native read with retry for link status and receiver capability reads for |
1873 | * cases where the sink may still be asleep. | |
a4fc5ed6 KP |
1874 | */ |
1875 | static bool | |
df0c237d JB |
1876 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
1877 | uint8_t *recv, int recv_bytes) | |
a4fc5ed6 | 1878 | { |
61da5fab JB |
1879 | int ret, i; |
1880 | ||
df0c237d JB |
1881 | /* |
1882 | * Sinks are *supposed* to come up within 1ms from an off state, | |
1883 | * but we're also supposed to retry 3 times per the spec. | |
1884 | */ | |
61da5fab | 1885 | for (i = 0; i < 3; i++) { |
df0c237d JB |
1886 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
1887 | recv_bytes); | |
1888 | if (ret == recv_bytes) | |
61da5fab JB |
1889 | return true; |
1890 | msleep(1); | |
1891 | } | |
a4fc5ed6 | 1892 | |
61da5fab | 1893 | return false; |
a4fc5ed6 KP |
1894 | } |
1895 | ||
1896 | /* | |
1897 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
1898 | * link status information | |
1899 | */ | |
1900 | static bool | |
93f62dad | 1901 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 1902 | { |
df0c237d JB |
1903 | return intel_dp_aux_native_read_retry(intel_dp, |
1904 | DP_LANE0_1_STATUS, | |
93f62dad | 1905 | link_status, |
df0c237d | 1906 | DP_LINK_STATUS_SIZE); |
a4fc5ed6 KP |
1907 | } |
1908 | ||
a4fc5ed6 KP |
1909 | #if 0 |
1910 | static char *voltage_names[] = { | |
1911 | "0.4V", "0.6V", "0.8V", "1.2V" | |
1912 | }; | |
1913 | static char *pre_emph_names[] = { | |
1914 | "0dB", "3.5dB", "6dB", "9.5dB" | |
1915 | }; | |
1916 | static char *link_train_names[] = { | |
1917 | "pattern 1", "pattern 2", "idle", "off" | |
1918 | }; | |
1919 | #endif | |
1920 | ||
1921 | /* | |
1922 | * These are source-specific values; current Intel hardware supports | |
1923 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB | |
1924 | */ | |
a4fc5ed6 KP |
1925 | |
1926 | static uint8_t | |
1a2eb460 | 1927 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 1928 | { |
30add22d | 1929 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bc7d38a4 | 1930 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 1931 | |
e2fa6fba P |
1932 | if (IS_VALLEYVIEW(dev)) |
1933 | return DP_TRAIN_VOLTAGE_SWING_1200; | |
bc7d38a4 | 1934 | else if (IS_GEN7(dev) && port == PORT_A) |
1a2eb460 | 1935 | return DP_TRAIN_VOLTAGE_SWING_800; |
bc7d38a4 | 1936 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
1a2eb460 KP |
1937 | return DP_TRAIN_VOLTAGE_SWING_1200; |
1938 | else | |
1939 | return DP_TRAIN_VOLTAGE_SWING_800; | |
1940 | } | |
1941 | ||
1942 | static uint8_t | |
1943 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) | |
1944 | { | |
30add22d | 1945 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bc7d38a4 | 1946 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 1947 | |
22b8bf17 | 1948 | if (HAS_DDI(dev)) { |
d6c0d722 PZ |
1949 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
1950 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1951 | return DP_TRAIN_PRE_EMPHASIS_9_5; | |
1952 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1953 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1954 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1955 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1956 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1957 | default: | |
1958 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1959 | } | |
e2fa6fba P |
1960 | } else if (IS_VALLEYVIEW(dev)) { |
1961 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1962 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1963 | return DP_TRAIN_PRE_EMPHASIS_9_5; | |
1964 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1965 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1966 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1967 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1968 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1969 | default: | |
1970 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1971 | } | |
bc7d38a4 | 1972 | } else if (IS_GEN7(dev) && port == PORT_A) { |
1a2eb460 KP |
1973 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
1974 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1975 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1976 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1977 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1978 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1979 | default: | |
1980 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1981 | } | |
1982 | } else { | |
1983 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
1984 | case DP_TRAIN_VOLTAGE_SWING_400: | |
1985 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1986 | case DP_TRAIN_VOLTAGE_SWING_600: | |
1987 | return DP_TRAIN_PRE_EMPHASIS_6; | |
1988 | case DP_TRAIN_VOLTAGE_SWING_800: | |
1989 | return DP_TRAIN_PRE_EMPHASIS_3_5; | |
1990 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
1991 | default: | |
1992 | return DP_TRAIN_PRE_EMPHASIS_0; | |
1993 | } | |
a4fc5ed6 KP |
1994 | } |
1995 | } | |
1996 | ||
e2fa6fba P |
1997 | static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) |
1998 | { | |
1999 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
2000 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2001 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); | |
5e69f97f CML |
2002 | struct intel_crtc *intel_crtc = |
2003 | to_intel_crtc(dport->base.base.crtc); | |
e2fa6fba P |
2004 | unsigned long demph_reg_value, preemph_reg_value, |
2005 | uniqtranscale_reg_value; | |
2006 | uint8_t train_set = intel_dp->train_set[0]; | |
cece5d58 | 2007 | int port = vlv_dport_to_channel(dport); |
5e69f97f | 2008 | int pipe = intel_crtc->pipe; |
e2fa6fba P |
2009 | |
2010 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
2011 | case DP_TRAIN_PRE_EMPHASIS_0: | |
2012 | preemph_reg_value = 0x0004000; | |
2013 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2014 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2015 | demph_reg_value = 0x2B405555; | |
2016 | uniqtranscale_reg_value = 0x552AB83A; | |
2017 | break; | |
2018 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2019 | demph_reg_value = 0x2B404040; | |
2020 | uniqtranscale_reg_value = 0x5548B83A; | |
2021 | break; | |
2022 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2023 | demph_reg_value = 0x2B245555; | |
2024 | uniqtranscale_reg_value = 0x5560B83A; | |
2025 | break; | |
2026 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2027 | demph_reg_value = 0x2B405555; | |
2028 | uniqtranscale_reg_value = 0x5598DA3A; | |
2029 | break; | |
2030 | default: | |
2031 | return 0; | |
2032 | } | |
2033 | break; | |
2034 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
2035 | preemph_reg_value = 0x0002000; | |
2036 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2037 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2038 | demph_reg_value = 0x2B404040; | |
2039 | uniqtranscale_reg_value = 0x5552B83A; | |
2040 | break; | |
2041 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2042 | demph_reg_value = 0x2B404848; | |
2043 | uniqtranscale_reg_value = 0x5580B83A; | |
2044 | break; | |
2045 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2046 | demph_reg_value = 0x2B404040; | |
2047 | uniqtranscale_reg_value = 0x55ADDA3A; | |
2048 | break; | |
2049 | default: | |
2050 | return 0; | |
2051 | } | |
2052 | break; | |
2053 | case DP_TRAIN_PRE_EMPHASIS_6: | |
2054 | preemph_reg_value = 0x0000000; | |
2055 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2056 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2057 | demph_reg_value = 0x2B305555; | |
2058 | uniqtranscale_reg_value = 0x5570B83A; | |
2059 | break; | |
2060 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2061 | demph_reg_value = 0x2B2B4040; | |
2062 | uniqtranscale_reg_value = 0x55ADDA3A; | |
2063 | break; | |
2064 | default: | |
2065 | return 0; | |
2066 | } | |
2067 | break; | |
2068 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
2069 | preemph_reg_value = 0x0006000; | |
2070 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2071 | case DP_TRAIN_VOLTAGE_SWING_400: | |
2072 | demph_reg_value = 0x1B405555; | |
2073 | uniqtranscale_reg_value = 0x55ADDA3A; | |
2074 | break; | |
2075 | default: | |
2076 | return 0; | |
2077 | } | |
2078 | break; | |
2079 | default: | |
2080 | return 0; | |
2081 | } | |
2082 | ||
0980a60f | 2083 | mutex_lock(&dev_priv->dpio_lock); |
5e69f97f CML |
2084 | vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000); |
2085 | vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value); | |
2086 | vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port), | |
e2fa6fba | 2087 | uniqtranscale_reg_value); |
5e69f97f CML |
2088 | vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040); |
2089 | vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000); | |
2090 | vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value); | |
2091 | vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000); | |
0980a60f | 2092 | mutex_unlock(&dev_priv->dpio_lock); |
e2fa6fba P |
2093 | |
2094 | return 0; | |
2095 | } | |
2096 | ||
a4fc5ed6 | 2097 | static void |
93f62dad | 2098 | intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 KP |
2099 | { |
2100 | uint8_t v = 0; | |
2101 | uint8_t p = 0; | |
2102 | int lane; | |
1a2eb460 KP |
2103 | uint8_t voltage_max; |
2104 | uint8_t preemph_max; | |
a4fc5ed6 | 2105 | |
33a34e4e | 2106 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
0f037bde DV |
2107 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
2108 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); | |
a4fc5ed6 KP |
2109 | |
2110 | if (this_v > v) | |
2111 | v = this_v; | |
2112 | if (this_p > p) | |
2113 | p = this_p; | |
2114 | } | |
2115 | ||
1a2eb460 | 2116 | voltage_max = intel_dp_voltage_max(intel_dp); |
417e822d KP |
2117 | if (v >= voltage_max) |
2118 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; | |
a4fc5ed6 | 2119 | |
1a2eb460 KP |
2120 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
2121 | if (p >= preemph_max) | |
2122 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; | |
a4fc5ed6 KP |
2123 | |
2124 | for (lane = 0; lane < 4; lane++) | |
33a34e4e | 2125 | intel_dp->train_set[lane] = v | p; |
a4fc5ed6 KP |
2126 | } |
2127 | ||
2128 | static uint32_t | |
f0a3424e | 2129 | intel_gen4_signal_levels(uint8_t train_set) |
a4fc5ed6 | 2130 | { |
3cf2efb1 | 2131 | uint32_t signal_levels = 0; |
a4fc5ed6 | 2132 | |
3cf2efb1 | 2133 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
a4fc5ed6 KP |
2134 | case DP_TRAIN_VOLTAGE_SWING_400: |
2135 | default: | |
2136 | signal_levels |= DP_VOLTAGE_0_4; | |
2137 | break; | |
2138 | case DP_TRAIN_VOLTAGE_SWING_600: | |
2139 | signal_levels |= DP_VOLTAGE_0_6; | |
2140 | break; | |
2141 | case DP_TRAIN_VOLTAGE_SWING_800: | |
2142 | signal_levels |= DP_VOLTAGE_0_8; | |
2143 | break; | |
2144 | case DP_TRAIN_VOLTAGE_SWING_1200: | |
2145 | signal_levels |= DP_VOLTAGE_1_2; | |
2146 | break; | |
2147 | } | |
3cf2efb1 | 2148 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
a4fc5ed6 KP |
2149 | case DP_TRAIN_PRE_EMPHASIS_0: |
2150 | default: | |
2151 | signal_levels |= DP_PRE_EMPHASIS_0; | |
2152 | break; | |
2153 | case DP_TRAIN_PRE_EMPHASIS_3_5: | |
2154 | signal_levels |= DP_PRE_EMPHASIS_3_5; | |
2155 | break; | |
2156 | case DP_TRAIN_PRE_EMPHASIS_6: | |
2157 | signal_levels |= DP_PRE_EMPHASIS_6; | |
2158 | break; | |
2159 | case DP_TRAIN_PRE_EMPHASIS_9_5: | |
2160 | signal_levels |= DP_PRE_EMPHASIS_9_5; | |
2161 | break; | |
2162 | } | |
2163 | return signal_levels; | |
2164 | } | |
2165 | ||
e3421a18 ZW |
2166 | /* Gen6's DP voltage swing and pre-emphasis control */ |
2167 | static uint32_t | |
2168 | intel_gen6_edp_signal_levels(uint8_t train_set) | |
2169 | { | |
3c5a62b5 YL |
2170 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2171 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2172 | switch (signal_levels) { | |
e3421a18 | 2173 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
2174 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
2175 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
2176 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2177 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; | |
e3421a18 | 2178 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
3c5a62b5 YL |
2179 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
2180 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; | |
e3421a18 | 2181 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
3c5a62b5 YL |
2182 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
2183 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; | |
e3421a18 | 2184 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
3c5a62b5 YL |
2185 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
2186 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; | |
e3421a18 | 2187 | default: |
3c5a62b5 YL |
2188 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
2189 | "0x%x\n", signal_levels); | |
2190 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
2191 | } |
2192 | } | |
2193 | ||
1a2eb460 KP |
2194 | /* Gen7's DP voltage swing and pre-emphasis control */ |
2195 | static uint32_t | |
2196 | intel_gen7_edp_signal_levels(uint8_t train_set) | |
2197 | { | |
2198 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
2199 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2200 | switch (signal_levels) { | |
2201 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
2202 | return EDP_LINK_TRAIN_400MV_0DB_IVB; | |
2203 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2204 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; | |
2205 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
2206 | return EDP_LINK_TRAIN_400MV_6DB_IVB; | |
2207 | ||
2208 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: | |
2209 | return EDP_LINK_TRAIN_600MV_0DB_IVB; | |
2210 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2211 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; | |
2212 | ||
2213 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: | |
2214 | return EDP_LINK_TRAIN_800MV_0DB_IVB; | |
2215 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2216 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; | |
2217 | ||
2218 | default: | |
2219 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
2220 | "0x%x\n", signal_levels); | |
2221 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
2222 | } | |
2223 | } | |
2224 | ||
d6c0d722 PZ |
2225 | /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ |
2226 | static uint32_t | |
f0a3424e | 2227 | intel_hsw_signal_levels(uint8_t train_set) |
a4fc5ed6 | 2228 | { |
d6c0d722 PZ |
2229 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
2230 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
2231 | switch (signal_levels) { | |
2232 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: | |
2233 | return DDI_BUF_EMP_400MV_0DB_HSW; | |
2234 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2235 | return DDI_BUF_EMP_400MV_3_5DB_HSW; | |
2236 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: | |
2237 | return DDI_BUF_EMP_400MV_6DB_HSW; | |
2238 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: | |
2239 | return DDI_BUF_EMP_400MV_9_5DB_HSW; | |
a4fc5ed6 | 2240 | |
d6c0d722 PZ |
2241 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
2242 | return DDI_BUF_EMP_600MV_0DB_HSW; | |
2243 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2244 | return DDI_BUF_EMP_600MV_3_5DB_HSW; | |
2245 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: | |
2246 | return DDI_BUF_EMP_600MV_6DB_HSW; | |
a4fc5ed6 | 2247 | |
d6c0d722 PZ |
2248 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
2249 | return DDI_BUF_EMP_800MV_0DB_HSW; | |
2250 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: | |
2251 | return DDI_BUF_EMP_800MV_3_5DB_HSW; | |
2252 | default: | |
2253 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
2254 | "0x%x\n", signal_levels); | |
2255 | return DDI_BUF_EMP_400MV_0DB_HSW; | |
a4fc5ed6 | 2256 | } |
a4fc5ed6 KP |
2257 | } |
2258 | ||
f0a3424e PZ |
2259 | /* Properly updates "DP" with the correct signal levels. */ |
2260 | static void | |
2261 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) | |
2262 | { | |
2263 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bc7d38a4 | 2264 | enum port port = intel_dig_port->port; |
f0a3424e PZ |
2265 | struct drm_device *dev = intel_dig_port->base.base.dev; |
2266 | uint32_t signal_levels, mask; | |
2267 | uint8_t train_set = intel_dp->train_set[0]; | |
2268 | ||
22b8bf17 | 2269 | if (HAS_DDI(dev)) { |
f0a3424e PZ |
2270 | signal_levels = intel_hsw_signal_levels(train_set); |
2271 | mask = DDI_BUF_EMP_MASK; | |
e2fa6fba P |
2272 | } else if (IS_VALLEYVIEW(dev)) { |
2273 | signal_levels = intel_vlv_signal_levels(intel_dp); | |
2274 | mask = 0; | |
bc7d38a4 | 2275 | } else if (IS_GEN7(dev) && port == PORT_A) { |
f0a3424e PZ |
2276 | signal_levels = intel_gen7_edp_signal_levels(train_set); |
2277 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; | |
bc7d38a4 | 2278 | } else if (IS_GEN6(dev) && port == PORT_A) { |
f0a3424e PZ |
2279 | signal_levels = intel_gen6_edp_signal_levels(train_set); |
2280 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; | |
2281 | } else { | |
2282 | signal_levels = intel_gen4_signal_levels(train_set); | |
2283 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; | |
2284 | } | |
2285 | ||
2286 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); | |
2287 | ||
2288 | *DP = (*DP & ~mask) | signal_levels; | |
2289 | } | |
2290 | ||
a4fc5ed6 | 2291 | static bool |
ea5b213a | 2292 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
70aff66c | 2293 | uint32_t *DP, |
58e10eb9 | 2294 | uint8_t dp_train_pat) |
a4fc5ed6 | 2295 | { |
174edf1f PZ |
2296 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2297 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
a4fc5ed6 | 2298 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 2299 | enum port port = intel_dig_port->port; |
a4fc5ed6 KP |
2300 | int ret; |
2301 | ||
22b8bf17 | 2302 | if (HAS_DDI(dev)) { |
3ab9c637 | 2303 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
d6c0d722 PZ |
2304 | |
2305 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
2306 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
2307 | else | |
2308 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
2309 | ||
2310 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2311 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2312 | case DP_TRAINING_PATTERN_DISABLE: | |
d6c0d722 PZ |
2313 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
2314 | ||
2315 | break; | |
2316 | case DP_TRAINING_PATTERN_1: | |
2317 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2318 | break; | |
2319 | case DP_TRAINING_PATTERN_2: | |
2320 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
2321 | break; | |
2322 | case DP_TRAINING_PATTERN_3: | |
2323 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
2324 | break; | |
2325 | } | |
174edf1f | 2326 | I915_WRITE(DP_TP_CTL(port), temp); |
d6c0d722 | 2327 | |
bc7d38a4 | 2328 | } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
70aff66c | 2329 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
47ea7542 PZ |
2330 | |
2331 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2332 | case DP_TRAINING_PATTERN_DISABLE: | |
70aff66c | 2333 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
47ea7542 PZ |
2334 | break; |
2335 | case DP_TRAINING_PATTERN_1: | |
70aff66c | 2336 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
47ea7542 PZ |
2337 | break; |
2338 | case DP_TRAINING_PATTERN_2: | |
70aff66c | 2339 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
47ea7542 PZ |
2340 | break; |
2341 | case DP_TRAINING_PATTERN_3: | |
2342 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
70aff66c | 2343 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
47ea7542 PZ |
2344 | break; |
2345 | } | |
2346 | ||
2347 | } else { | |
70aff66c | 2348 | *DP &= ~DP_LINK_TRAIN_MASK; |
47ea7542 PZ |
2349 | |
2350 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2351 | case DP_TRAINING_PATTERN_DISABLE: | |
70aff66c | 2352 | *DP |= DP_LINK_TRAIN_OFF; |
47ea7542 PZ |
2353 | break; |
2354 | case DP_TRAINING_PATTERN_1: | |
70aff66c | 2355 | *DP |= DP_LINK_TRAIN_PAT_1; |
47ea7542 PZ |
2356 | break; |
2357 | case DP_TRAINING_PATTERN_2: | |
70aff66c | 2358 | *DP |= DP_LINK_TRAIN_PAT_2; |
47ea7542 PZ |
2359 | break; |
2360 | case DP_TRAINING_PATTERN_3: | |
2361 | DRM_ERROR("DP training pattern 3 not supported\n"); | |
70aff66c | 2362 | *DP |= DP_LINK_TRAIN_PAT_2; |
47ea7542 PZ |
2363 | break; |
2364 | } | |
2365 | } | |
2366 | ||
70aff66c | 2367 | I915_WRITE(intel_dp->output_reg, *DP); |
ea5b213a | 2368 | POSTING_READ(intel_dp->output_reg); |
a4fc5ed6 | 2369 | |
70aff66c JN |
2370 | ret = intel_dp_aux_native_write_1(intel_dp, DP_TRAINING_PATTERN_SET, |
2371 | dp_train_pat); | |
2372 | if (ret != 1) | |
2373 | return false; | |
a4fc5ed6 | 2374 | |
47ea7542 PZ |
2375 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) != |
2376 | DP_TRAINING_PATTERN_DISABLE) { | |
2377 | ret = intel_dp_aux_native_write(intel_dp, | |
2378 | DP_TRAINING_LANE0_SET, | |
2379 | intel_dp->train_set, | |
2380 | intel_dp->lane_count); | |
2381 | if (ret != intel_dp->lane_count) | |
2382 | return false; | |
2383 | } | |
a4fc5ed6 KP |
2384 | |
2385 | return true; | |
2386 | } | |
2387 | ||
70aff66c JN |
2388 | static bool |
2389 | intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, | |
2390 | uint8_t dp_train_pat) | |
2391 | { | |
2392 | memset(intel_dp->train_set, 0, 4); | |
2393 | intel_dp_set_signal_levels(intel_dp, DP); | |
2394 | return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); | |
2395 | } | |
2396 | ||
2397 | static bool | |
2398 | intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, | |
2399 | uint8_t link_status[DP_LINK_STATUS_SIZE]) | |
2400 | { | |
2401 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2402 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
2403 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2404 | int ret; | |
2405 | ||
2406 | intel_get_adjust_train(intel_dp, link_status); | |
2407 | intel_dp_set_signal_levels(intel_dp, DP); | |
2408 | ||
2409 | I915_WRITE(intel_dp->output_reg, *DP); | |
2410 | POSTING_READ(intel_dp->output_reg); | |
2411 | ||
2412 | ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET, | |
2413 | intel_dp->train_set, | |
2414 | intel_dp->lane_count); | |
2415 | ||
2416 | return ret == intel_dp->lane_count; | |
2417 | } | |
2418 | ||
3ab9c637 ID |
2419 | static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
2420 | { | |
2421 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2422 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
2423 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2424 | enum port port = intel_dig_port->port; | |
2425 | uint32_t val; | |
2426 | ||
2427 | if (!HAS_DDI(dev)) | |
2428 | return; | |
2429 | ||
2430 | val = I915_READ(DP_TP_CTL(port)); | |
2431 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2432 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
2433 | I915_WRITE(DP_TP_CTL(port), val); | |
2434 | ||
2435 | /* | |
2436 | * On PORT_A we can have only eDP in SST mode. There the only reason | |
2437 | * we need to set idle transmission mode is to work around a HW issue | |
2438 | * where we enable the pipe while not in idle link-training mode. | |
2439 | * In this case there is requirement to wait for a minimum number of | |
2440 | * idle patterns to be sent. | |
2441 | */ | |
2442 | if (port == PORT_A) | |
2443 | return; | |
2444 | ||
2445 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), | |
2446 | 1)) | |
2447 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); | |
2448 | } | |
2449 | ||
33a34e4e | 2450 | /* Enable corresponding port and start training pattern 1 */ |
c19b0669 | 2451 | void |
33a34e4e | 2452 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
a4fc5ed6 | 2453 | { |
da63a9f2 | 2454 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
c19b0669 | 2455 | struct drm_device *dev = encoder->dev; |
a4fc5ed6 KP |
2456 | int i; |
2457 | uint8_t voltage; | |
cdb0e95b | 2458 | int voltage_tries, loop_tries; |
ea5b213a | 2459 | uint32_t DP = intel_dp->DP; |
6aba5b6c | 2460 | uint8_t link_config[2]; |
a4fc5ed6 | 2461 | |
affa9354 | 2462 | if (HAS_DDI(dev)) |
c19b0669 PZ |
2463 | intel_ddi_prepare_link_retrain(encoder); |
2464 | ||
3cf2efb1 | 2465 | /* Write the link configuration data */ |
6aba5b6c JN |
2466 | link_config[0] = intel_dp->link_bw; |
2467 | link_config[1] = intel_dp->lane_count; | |
2468 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
2469 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; | |
2470 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2); | |
2471 | ||
2472 | link_config[0] = 0; | |
2473 | link_config[1] = DP_SET_ANSI_8B10B; | |
2474 | intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2); | |
a4fc5ed6 KP |
2475 | |
2476 | DP |= DP_PORT_EN; | |
1a2eb460 | 2477 | |
70aff66c JN |
2478 | /* clock recovery */ |
2479 | if (!intel_dp_reset_link_train(intel_dp, &DP, | |
2480 | DP_TRAINING_PATTERN_1 | | |
2481 | DP_LINK_SCRAMBLING_DISABLE)) { | |
2482 | DRM_ERROR("failed to enable link training\n"); | |
2483 | return; | |
2484 | } | |
2485 | ||
a4fc5ed6 | 2486 | voltage = 0xff; |
cdb0e95b KP |
2487 | voltage_tries = 0; |
2488 | loop_tries = 0; | |
a4fc5ed6 | 2489 | for (;;) { |
70aff66c | 2490 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
a4fc5ed6 | 2491 | |
a7c9655f | 2492 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
93f62dad KP |
2493 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
2494 | DRM_ERROR("failed to get link status\n"); | |
a4fc5ed6 | 2495 | break; |
93f62dad | 2496 | } |
a4fc5ed6 | 2497 | |
01916270 | 2498 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
93f62dad | 2499 | DRM_DEBUG_KMS("clock recovery OK\n"); |
3cf2efb1 CW |
2500 | break; |
2501 | } | |
2502 | ||
2503 | /* Check to see if we've tried the max voltage */ | |
2504 | for (i = 0; i < intel_dp->lane_count; i++) | |
2505 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) | |
a4fc5ed6 | 2506 | break; |
3b4f819d | 2507 | if (i == intel_dp->lane_count) { |
b06fbda3 DV |
2508 | ++loop_tries; |
2509 | if (loop_tries == 5) { | |
cdb0e95b KP |
2510 | DRM_DEBUG_KMS("too many full retries, give up\n"); |
2511 | break; | |
2512 | } | |
70aff66c JN |
2513 | intel_dp_reset_link_train(intel_dp, &DP, |
2514 | DP_TRAINING_PATTERN_1 | | |
2515 | DP_LINK_SCRAMBLING_DISABLE); | |
cdb0e95b KP |
2516 | voltage_tries = 0; |
2517 | continue; | |
2518 | } | |
a4fc5ed6 | 2519 | |
3cf2efb1 | 2520 | /* Check to see if we've tried the same voltage 5 times */ |
b06fbda3 | 2521 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
24773670 | 2522 | ++voltage_tries; |
b06fbda3 DV |
2523 | if (voltage_tries == 5) { |
2524 | DRM_DEBUG_KMS("too many voltage retries, give up\n"); | |
2525 | break; | |
2526 | } | |
2527 | } else | |
2528 | voltage_tries = 0; | |
2529 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; | |
a4fc5ed6 | 2530 | |
70aff66c JN |
2531 | /* Update training set as requested by target */ |
2532 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { | |
2533 | DRM_ERROR("failed to update link training\n"); | |
2534 | break; | |
2535 | } | |
a4fc5ed6 KP |
2536 | } |
2537 | ||
33a34e4e JB |
2538 | intel_dp->DP = DP; |
2539 | } | |
2540 | ||
c19b0669 | 2541 | void |
33a34e4e JB |
2542 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
2543 | { | |
33a34e4e | 2544 | bool channel_eq = false; |
37f80975 | 2545 | int tries, cr_tries; |
33a34e4e JB |
2546 | uint32_t DP = intel_dp->DP; |
2547 | ||
a4fc5ed6 | 2548 | /* channel equalization */ |
70aff66c JN |
2549 | if (!intel_dp_set_link_train(intel_dp, &DP, |
2550 | DP_TRAINING_PATTERN_2 | | |
2551 | DP_LINK_SCRAMBLING_DISABLE)) { | |
2552 | DRM_ERROR("failed to start channel equalization\n"); | |
2553 | return; | |
2554 | } | |
2555 | ||
a4fc5ed6 | 2556 | tries = 0; |
37f80975 | 2557 | cr_tries = 0; |
a4fc5ed6 KP |
2558 | channel_eq = false; |
2559 | for (;;) { | |
70aff66c | 2560 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
e3421a18 | 2561 | |
37f80975 JB |
2562 | if (cr_tries > 5) { |
2563 | DRM_ERROR("failed to train DP, aborting\n"); | |
2564 | intel_dp_link_down(intel_dp); | |
2565 | break; | |
2566 | } | |
2567 | ||
a7c9655f | 2568 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
70aff66c JN |
2569 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
2570 | DRM_ERROR("failed to get link status\n"); | |
a4fc5ed6 | 2571 | break; |
70aff66c | 2572 | } |
a4fc5ed6 | 2573 | |
37f80975 | 2574 | /* Make sure clock is still ok */ |
01916270 | 2575 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
37f80975 | 2576 | intel_dp_start_link_train(intel_dp); |
70aff66c JN |
2577 | intel_dp_set_link_train(intel_dp, &DP, |
2578 | DP_TRAINING_PATTERN_2 | | |
2579 | DP_LINK_SCRAMBLING_DISABLE); | |
37f80975 JB |
2580 | cr_tries++; |
2581 | continue; | |
2582 | } | |
2583 | ||
1ffdff13 | 2584 | if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
3cf2efb1 CW |
2585 | channel_eq = true; |
2586 | break; | |
2587 | } | |
a4fc5ed6 | 2588 | |
37f80975 JB |
2589 | /* Try 5 times, then try clock recovery if that fails */ |
2590 | if (tries > 5) { | |
2591 | intel_dp_link_down(intel_dp); | |
2592 | intel_dp_start_link_train(intel_dp); | |
70aff66c JN |
2593 | intel_dp_set_link_train(intel_dp, &DP, |
2594 | DP_TRAINING_PATTERN_2 | | |
2595 | DP_LINK_SCRAMBLING_DISABLE); | |
37f80975 JB |
2596 | tries = 0; |
2597 | cr_tries++; | |
2598 | continue; | |
2599 | } | |
a4fc5ed6 | 2600 | |
70aff66c JN |
2601 | /* Update training set as requested by target */ |
2602 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { | |
2603 | DRM_ERROR("failed to update link training\n"); | |
2604 | break; | |
2605 | } | |
3cf2efb1 | 2606 | ++tries; |
869184a6 | 2607 | } |
3cf2efb1 | 2608 | |
3ab9c637 ID |
2609 | intel_dp_set_idle_link_train(intel_dp); |
2610 | ||
2611 | intel_dp->DP = DP; | |
2612 | ||
d6c0d722 | 2613 | if (channel_eq) |
07f42258 | 2614 | DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); |
d6c0d722 | 2615 | |
3ab9c637 ID |
2616 | } |
2617 | ||
2618 | void intel_dp_stop_link_train(struct intel_dp *intel_dp) | |
2619 | { | |
70aff66c | 2620 | intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
3ab9c637 | 2621 | DP_TRAINING_PATTERN_DISABLE); |
a4fc5ed6 KP |
2622 | } |
2623 | ||
2624 | static void | |
ea5b213a | 2625 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 2626 | { |
da63a9f2 | 2627 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
bc7d38a4 | 2628 | enum port port = intel_dig_port->port; |
da63a9f2 | 2629 | struct drm_device *dev = intel_dig_port->base.base.dev; |
a4fc5ed6 | 2630 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab527efc DV |
2631 | struct intel_crtc *intel_crtc = |
2632 | to_intel_crtc(intel_dig_port->base.base.crtc); | |
ea5b213a | 2633 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 2634 | |
c19b0669 PZ |
2635 | /* |
2636 | * DDI code has a strict mode set sequence and we should try to respect | |
2637 | * it, otherwise we might hang the machine in many different ways. So we | |
2638 | * really should be disabling the port only on a complete crtc_disable | |
2639 | * sequence. This function is just called under two conditions on DDI | |
2640 | * code: | |
2641 | * - Link train failed while doing crtc_enable, and on this case we | |
2642 | * really should respect the mode set sequence and wait for a | |
2643 | * crtc_disable. | |
2644 | * - Someone turned the monitor off and intel_dp_check_link_status | |
2645 | * called us. We don't need to disable the whole port on this case, so | |
2646 | * when someone turns the monitor on again, | |
2647 | * intel_ddi_prepare_link_retrain will take care of redoing the link | |
2648 | * train. | |
2649 | */ | |
affa9354 | 2650 | if (HAS_DDI(dev)) |
c19b0669 PZ |
2651 | return; |
2652 | ||
0c33d8d7 | 2653 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
1b39d6f3 CW |
2654 | return; |
2655 | ||
28c97730 | 2656 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 2657 | |
bc7d38a4 | 2658 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
e3421a18 | 2659 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
ea5b213a | 2660 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
e3421a18 ZW |
2661 | } else { |
2662 | DP &= ~DP_LINK_TRAIN_MASK; | |
ea5b213a | 2663 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
e3421a18 | 2664 | } |
fe255d00 | 2665 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 2666 | |
ab527efc DV |
2667 | /* We don't really know why we're doing this */ |
2668 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
5eb08b69 | 2669 | |
493a7081 | 2670 | if (HAS_PCH_IBX(dev) && |
1b39d6f3 | 2671 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
da63a9f2 | 2672 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
31acbcc4 | 2673 | |
5bddd17f EA |
2674 | /* Hardware workaround: leaving our transcoder select |
2675 | * set to transcoder B while it's off will prevent the | |
2676 | * corresponding HDMI output on transcoder A. | |
2677 | * | |
2678 | * Combine this with another hardware workaround: | |
2679 | * transcoder select bit can only be cleared while the | |
2680 | * port is enabled. | |
2681 | */ | |
2682 | DP &= ~DP_PIPEB_SELECT; | |
2683 | I915_WRITE(intel_dp->output_reg, DP); | |
2684 | ||
2685 | /* Changes to enable or select take place the vblank | |
2686 | * after being written. | |
2687 | */ | |
ff50afe9 DV |
2688 | if (WARN_ON(crtc == NULL)) { |
2689 | /* We should never try to disable a port without a crtc | |
2690 | * attached. For paranoia keep the code around for a | |
2691 | * bit. */ | |
31acbcc4 CW |
2692 | POSTING_READ(intel_dp->output_reg); |
2693 | msleep(50); | |
2694 | } else | |
ab527efc | 2695 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
5bddd17f EA |
2696 | } |
2697 | ||
832afda6 | 2698 | DP &= ~DP_AUDIO_OUTPUT_ENABLE; |
ea5b213a CW |
2699 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
2700 | POSTING_READ(intel_dp->output_reg); | |
f01eca2e | 2701 | msleep(intel_dp->panel_power_down_delay); |
a4fc5ed6 KP |
2702 | } |
2703 | ||
26d61aad KP |
2704 | static bool |
2705 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
92fd8fd1 | 2706 | { |
a031d709 RV |
2707 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
2708 | struct drm_device *dev = dig_port->base.base.dev; | |
2709 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2710 | ||
577c7a50 DL |
2711 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
2712 | ||
92fd8fd1 | 2713 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
edb39244 AJ |
2714 | sizeof(intel_dp->dpcd)) == 0) |
2715 | return false; /* aux transfer failed */ | |
92fd8fd1 | 2716 | |
577c7a50 DL |
2717 | hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), |
2718 | 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); | |
2719 | DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); | |
2720 | ||
edb39244 AJ |
2721 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
2722 | return false; /* DPCD not present */ | |
2723 | ||
2293bb5c SK |
2724 | /* Check if the panel supports PSR */ |
2725 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); | |
50003939 JN |
2726 | if (is_edp(intel_dp)) { |
2727 | intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT, | |
2728 | intel_dp->psr_dpcd, | |
2729 | sizeof(intel_dp->psr_dpcd)); | |
a031d709 RV |
2730 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
2731 | dev_priv->psr.sink_support = true; | |
50003939 | 2732 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
a031d709 | 2733 | } |
50003939 JN |
2734 | } |
2735 | ||
edb39244 AJ |
2736 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
2737 | DP_DWN_STRM_PORT_PRESENT)) | |
2738 | return true; /* native DP sink */ | |
2739 | ||
2740 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
2741 | return true; /* no per-port downstream info */ | |
2742 | ||
2743 | if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0, | |
2744 | intel_dp->downstream_ports, | |
2745 | DP_MAX_DOWNSTREAM_PORTS) == 0) | |
2746 | return false; /* downstream port status fetch failed */ | |
2747 | ||
2748 | return true; | |
92fd8fd1 KP |
2749 | } |
2750 | ||
0d198328 AJ |
2751 | static void |
2752 | intel_dp_probe_oui(struct intel_dp *intel_dp) | |
2753 | { | |
2754 | u8 buf[3]; | |
2755 | ||
2756 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) | |
2757 | return; | |
2758 | ||
351cfc34 DV |
2759 | ironlake_edp_panel_vdd_on(intel_dp); |
2760 | ||
0d198328 AJ |
2761 | if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) |
2762 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", | |
2763 | buf[0], buf[1], buf[2]); | |
2764 | ||
2765 | if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) | |
2766 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", | |
2767 | buf[0], buf[1], buf[2]); | |
351cfc34 DV |
2768 | |
2769 | ironlake_edp_panel_vdd_off(intel_dp, false); | |
0d198328 AJ |
2770 | } |
2771 | ||
a60f0e38 JB |
2772 | static bool |
2773 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
2774 | { | |
2775 | int ret; | |
2776 | ||
2777 | ret = intel_dp_aux_native_read_retry(intel_dp, | |
2778 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
2779 | sink_irq_vector, 1); | |
2780 | if (!ret) | |
2781 | return false; | |
2782 | ||
2783 | return true; | |
2784 | } | |
2785 | ||
2786 | static void | |
2787 | intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
2788 | { | |
2789 | /* NAK by default */ | |
9324cf7f | 2790 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK); |
a60f0e38 JB |
2791 | } |
2792 | ||
a4fc5ed6 KP |
2793 | /* |
2794 | * According to DP spec | |
2795 | * 5.1.2: | |
2796 | * 1. Read DPCD | |
2797 | * 2. Configure link according to Receiver Capabilities | |
2798 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
2799 | * 4. Check link status on receipt of hot-plug interrupt | |
2800 | */ | |
2801 | ||
00c09d70 | 2802 | void |
ea5b213a | 2803 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
a4fc5ed6 | 2804 | { |
da63a9f2 | 2805 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
a60f0e38 | 2806 | u8 sink_irq_vector; |
93f62dad | 2807 | u8 link_status[DP_LINK_STATUS_SIZE]; |
a60f0e38 | 2808 | |
da63a9f2 | 2809 | if (!intel_encoder->connectors_active) |
d2b996ac | 2810 | return; |
59cd09e1 | 2811 | |
da63a9f2 | 2812 | if (WARN_ON(!intel_encoder->base.crtc)) |
a4fc5ed6 KP |
2813 | return; |
2814 | ||
92fd8fd1 | 2815 | /* Try to read receiver status if the link appears to be up */ |
93f62dad | 2816 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
ea5b213a | 2817 | intel_dp_link_down(intel_dp); |
a4fc5ed6 KP |
2818 | return; |
2819 | } | |
2820 | ||
92fd8fd1 | 2821 | /* Now read the DPCD to see if it's actually running */ |
26d61aad | 2822 | if (!intel_dp_get_dpcd(intel_dp)) { |
59cd09e1 JB |
2823 | intel_dp_link_down(intel_dp); |
2824 | return; | |
2825 | } | |
2826 | ||
a60f0e38 JB |
2827 | /* Try to read the source of the interrupt */ |
2828 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
2829 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { | |
2830 | /* Clear interrupt source */ | |
2831 | intel_dp_aux_native_write_1(intel_dp, | |
2832 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
2833 | sink_irq_vector); | |
2834 | ||
2835 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
2836 | intel_dp_handle_test_request(intel_dp); | |
2837 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
2838 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
2839 | } | |
2840 | ||
1ffdff13 | 2841 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
92fd8fd1 | 2842 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
da63a9f2 | 2843 | drm_get_encoder_name(&intel_encoder->base)); |
33a34e4e JB |
2844 | intel_dp_start_link_train(intel_dp); |
2845 | intel_dp_complete_link_train(intel_dp); | |
3ab9c637 | 2846 | intel_dp_stop_link_train(intel_dp); |
33a34e4e | 2847 | } |
a4fc5ed6 | 2848 | } |
a4fc5ed6 | 2849 | |
caf9ab24 | 2850 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 2851 | static enum drm_connector_status |
26d61aad | 2852 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 2853 | { |
caf9ab24 | 2854 | uint8_t *dpcd = intel_dp->dpcd; |
caf9ab24 AJ |
2855 | uint8_t type; |
2856 | ||
2857 | if (!intel_dp_get_dpcd(intel_dp)) | |
2858 | return connector_status_disconnected; | |
2859 | ||
2860 | /* if there's no downstream port, we're done */ | |
2861 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) | |
26d61aad | 2862 | return connector_status_connected; |
caf9ab24 AJ |
2863 | |
2864 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
c9ff160b JN |
2865 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
2866 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | |
23235177 | 2867 | uint8_t reg; |
caf9ab24 | 2868 | if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT, |
23235177 | 2869 | ®, 1)) |
caf9ab24 | 2870 | return connector_status_unknown; |
23235177 AJ |
2871 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
2872 | : connector_status_disconnected; | |
caf9ab24 AJ |
2873 | } |
2874 | ||
2875 | /* If no HPD, poke DDC gently */ | |
2876 | if (drm_probe_ddc(&intel_dp->adapter)) | |
26d61aad | 2877 | return connector_status_connected; |
caf9ab24 AJ |
2878 | |
2879 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
2880 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
2881 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
2882 | if (type == DP_DS_PORT_TYPE_VGA || | |
2883 | type == DP_DS_PORT_TYPE_NON_EDID) | |
2884 | return connector_status_unknown; | |
2885 | } else { | |
2886 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
2887 | DP_DWN_STRM_PORT_TYPE_MASK; | |
2888 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
2889 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
2890 | return connector_status_unknown; | |
2891 | } | |
caf9ab24 AJ |
2892 | |
2893 | /* Anything else is out of spec, warn and ignore */ | |
2894 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); | |
26d61aad | 2895 | return connector_status_disconnected; |
71ba9000 AJ |
2896 | } |
2897 | ||
5eb08b69 | 2898 | static enum drm_connector_status |
a9756bb5 | 2899 | ironlake_dp_detect(struct intel_dp *intel_dp) |
5eb08b69 | 2900 | { |
30add22d | 2901 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
1b469639 DL |
2902 | struct drm_i915_private *dev_priv = dev->dev_private; |
2903 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
5eb08b69 ZW |
2904 | enum drm_connector_status status; |
2905 | ||
fe16d949 CW |
2906 | /* Can't disconnect eDP, but you can close the lid... */ |
2907 | if (is_edp(intel_dp)) { | |
30add22d | 2908 | status = intel_panel_detect(dev); |
fe16d949 CW |
2909 | if (status == connector_status_unknown) |
2910 | status = connector_status_connected; | |
2911 | return status; | |
2912 | } | |
01cb9ea6 | 2913 | |
1b469639 DL |
2914 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
2915 | return connector_status_disconnected; | |
2916 | ||
26d61aad | 2917 | return intel_dp_detect_dpcd(intel_dp); |
5eb08b69 ZW |
2918 | } |
2919 | ||
a4fc5ed6 | 2920 | static enum drm_connector_status |
a9756bb5 | 2921 | g4x_dp_detect(struct intel_dp *intel_dp) |
a4fc5ed6 | 2922 | { |
30add22d | 2923 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
a4fc5ed6 | 2924 | struct drm_i915_private *dev_priv = dev->dev_private; |
34f2be46 | 2925 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
10f76a38 | 2926 | uint32_t bit; |
5eb08b69 | 2927 | |
35aad75f JB |
2928 | /* Can't disconnect eDP, but you can close the lid... */ |
2929 | if (is_edp(intel_dp)) { | |
2930 | enum drm_connector_status status; | |
2931 | ||
2932 | status = intel_panel_detect(dev); | |
2933 | if (status == connector_status_unknown) | |
2934 | status = connector_status_connected; | |
2935 | return status; | |
2936 | } | |
2937 | ||
34f2be46 VS |
2938 | switch (intel_dig_port->port) { |
2939 | case PORT_B: | |
26739f12 | 2940 | bit = PORTB_HOTPLUG_LIVE_STATUS; |
a4fc5ed6 | 2941 | break; |
34f2be46 | 2942 | case PORT_C: |
26739f12 | 2943 | bit = PORTC_HOTPLUG_LIVE_STATUS; |
a4fc5ed6 | 2944 | break; |
34f2be46 | 2945 | case PORT_D: |
26739f12 | 2946 | bit = PORTD_HOTPLUG_LIVE_STATUS; |
a4fc5ed6 KP |
2947 | break; |
2948 | default: | |
2949 | return connector_status_unknown; | |
2950 | } | |
2951 | ||
10f76a38 | 2952 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
a4fc5ed6 KP |
2953 | return connector_status_disconnected; |
2954 | ||
26d61aad | 2955 | return intel_dp_detect_dpcd(intel_dp); |
a9756bb5 ZW |
2956 | } |
2957 | ||
8c241fef KP |
2958 | static struct edid * |
2959 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) | |
2960 | { | |
9cd300e0 | 2961 | struct intel_connector *intel_connector = to_intel_connector(connector); |
d6f24d0f | 2962 | |
9cd300e0 JN |
2963 | /* use cached edid if we have one */ |
2964 | if (intel_connector->edid) { | |
9cd300e0 JN |
2965 | /* invalid edid */ |
2966 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
2967 | return NULL; |
2968 | ||
55e9edeb | 2969 | return drm_edid_duplicate(intel_connector->edid); |
d6f24d0f | 2970 | } |
8c241fef | 2971 | |
9cd300e0 | 2972 | return drm_get_edid(connector, adapter); |
8c241fef KP |
2973 | } |
2974 | ||
2975 | static int | |
2976 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) | |
2977 | { | |
9cd300e0 | 2978 | struct intel_connector *intel_connector = to_intel_connector(connector); |
8c241fef | 2979 | |
9cd300e0 JN |
2980 | /* use cached edid if we have one */ |
2981 | if (intel_connector->edid) { | |
2982 | /* invalid edid */ | |
2983 | if (IS_ERR(intel_connector->edid)) | |
2984 | return 0; | |
2985 | ||
2986 | return intel_connector_update_modes(connector, | |
2987 | intel_connector->edid); | |
d6f24d0f JB |
2988 | } |
2989 | ||
9cd300e0 | 2990 | return intel_ddc_get_modes(connector, adapter); |
8c241fef KP |
2991 | } |
2992 | ||
a9756bb5 ZW |
2993 | static enum drm_connector_status |
2994 | intel_dp_detect(struct drm_connector *connector, bool force) | |
2995 | { | |
2996 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
d63885da PZ |
2997 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2998 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fa90ecef | 2999 | struct drm_device *dev = connector->dev; |
a9756bb5 ZW |
3000 | enum drm_connector_status status; |
3001 | struct edid *edid = NULL; | |
3002 | ||
164c8598 CW |
3003 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
3004 | connector->base.id, drm_get_connector_name(connector)); | |
3005 | ||
a9756bb5 ZW |
3006 | intel_dp->has_audio = false; |
3007 | ||
3008 | if (HAS_PCH_SPLIT(dev)) | |
3009 | status = ironlake_dp_detect(intel_dp); | |
3010 | else | |
3011 | status = g4x_dp_detect(intel_dp); | |
1b9be9d0 | 3012 | |
a9756bb5 ZW |
3013 | if (status != connector_status_connected) |
3014 | return status; | |
3015 | ||
0d198328 AJ |
3016 | intel_dp_probe_oui(intel_dp); |
3017 | ||
c3e5f67b DV |
3018 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
3019 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); | |
f684960e | 3020 | } else { |
8c241fef | 3021 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
f684960e CW |
3022 | if (edid) { |
3023 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
f684960e CW |
3024 | kfree(edid); |
3025 | } | |
a9756bb5 ZW |
3026 | } |
3027 | ||
d63885da PZ |
3028 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
3029 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; | |
a9756bb5 | 3030 | return connector_status_connected; |
a4fc5ed6 KP |
3031 | } |
3032 | ||
3033 | static int intel_dp_get_modes(struct drm_connector *connector) | |
3034 | { | |
df0e9248 | 3035 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e | 3036 | struct intel_connector *intel_connector = to_intel_connector(connector); |
fa90ecef | 3037 | struct drm_device *dev = connector->dev; |
32f9d658 | 3038 | int ret; |
a4fc5ed6 KP |
3039 | |
3040 | /* We should parse the EDID data and find out if it has an audio sink | |
3041 | */ | |
3042 | ||
8c241fef | 3043 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
f8779fda | 3044 | if (ret) |
32f9d658 ZW |
3045 | return ret; |
3046 | ||
f8779fda | 3047 | /* if eDP has no EDID, fall back to fixed mode */ |
dd06f90e | 3048 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
f8779fda | 3049 | struct drm_display_mode *mode; |
dd06f90e JN |
3050 | mode = drm_mode_duplicate(dev, |
3051 | intel_connector->panel.fixed_mode); | |
f8779fda | 3052 | if (mode) { |
32f9d658 ZW |
3053 | drm_mode_probed_add(connector, mode); |
3054 | return 1; | |
3055 | } | |
3056 | } | |
3057 | return 0; | |
a4fc5ed6 KP |
3058 | } |
3059 | ||
1aad7ac0 CW |
3060 | static bool |
3061 | intel_dp_detect_audio(struct drm_connector *connector) | |
3062 | { | |
3063 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
3064 | struct edid *edid; | |
3065 | bool has_audio = false; | |
3066 | ||
8c241fef | 3067 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
1aad7ac0 CW |
3068 | if (edid) { |
3069 | has_audio = drm_detect_monitor_audio(edid); | |
1aad7ac0 CW |
3070 | kfree(edid); |
3071 | } | |
3072 | ||
3073 | return has_audio; | |
3074 | } | |
3075 | ||
f684960e CW |
3076 | static int |
3077 | intel_dp_set_property(struct drm_connector *connector, | |
3078 | struct drm_property *property, | |
3079 | uint64_t val) | |
3080 | { | |
e953fd7b | 3081 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
53b41837 | 3082 | struct intel_connector *intel_connector = to_intel_connector(connector); |
da63a9f2 PZ |
3083 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
3084 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
f684960e CW |
3085 | int ret; |
3086 | ||
662595df | 3087 | ret = drm_object_property_set_value(&connector->base, property, val); |
f684960e CW |
3088 | if (ret) |
3089 | return ret; | |
3090 | ||
3f43c48d | 3091 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
3092 | int i = val; |
3093 | bool has_audio; | |
3094 | ||
3095 | if (i == intel_dp->force_audio) | |
f684960e CW |
3096 | return 0; |
3097 | ||
1aad7ac0 | 3098 | intel_dp->force_audio = i; |
f684960e | 3099 | |
c3e5f67b | 3100 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
3101 | has_audio = intel_dp_detect_audio(connector); |
3102 | else | |
c3e5f67b | 3103 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 CW |
3104 | |
3105 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
3106 | return 0; |
3107 | ||
1aad7ac0 | 3108 | intel_dp->has_audio = has_audio; |
f684960e CW |
3109 | goto done; |
3110 | } | |
3111 | ||
e953fd7b | 3112 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
3113 | bool old_auto = intel_dp->color_range_auto; |
3114 | uint32_t old_range = intel_dp->color_range; | |
3115 | ||
55bc60db VS |
3116 | switch (val) { |
3117 | case INTEL_BROADCAST_RGB_AUTO: | |
3118 | intel_dp->color_range_auto = true; | |
3119 | break; | |
3120 | case INTEL_BROADCAST_RGB_FULL: | |
3121 | intel_dp->color_range_auto = false; | |
3122 | intel_dp->color_range = 0; | |
3123 | break; | |
3124 | case INTEL_BROADCAST_RGB_LIMITED: | |
3125 | intel_dp->color_range_auto = false; | |
3126 | intel_dp->color_range = DP_COLOR_RANGE_16_235; | |
3127 | break; | |
3128 | default: | |
3129 | return -EINVAL; | |
3130 | } | |
ae4edb80 DV |
3131 | |
3132 | if (old_auto == intel_dp->color_range_auto && | |
3133 | old_range == intel_dp->color_range) | |
3134 | return 0; | |
3135 | ||
e953fd7b CW |
3136 | goto done; |
3137 | } | |
3138 | ||
53b41837 YN |
3139 | if (is_edp(intel_dp) && |
3140 | property == connector->dev->mode_config.scaling_mode_property) { | |
3141 | if (val == DRM_MODE_SCALE_NONE) { | |
3142 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
3143 | return -EINVAL; | |
3144 | } | |
3145 | ||
3146 | if (intel_connector->panel.fitting_mode == val) { | |
3147 | /* the eDP scaling property is not changed */ | |
3148 | return 0; | |
3149 | } | |
3150 | intel_connector->panel.fitting_mode = val; | |
3151 | ||
3152 | goto done; | |
3153 | } | |
3154 | ||
f684960e CW |
3155 | return -EINVAL; |
3156 | ||
3157 | done: | |
c0c36b94 CW |
3158 | if (intel_encoder->base.crtc) |
3159 | intel_crtc_restore_mode(intel_encoder->base.crtc); | |
f684960e CW |
3160 | |
3161 | return 0; | |
3162 | } | |
3163 | ||
a4fc5ed6 | 3164 | static void |
73845adf | 3165 | intel_dp_connector_destroy(struct drm_connector *connector) |
a4fc5ed6 | 3166 | { |
1d508706 | 3167 | struct intel_connector *intel_connector = to_intel_connector(connector); |
aaa6fd2a | 3168 | |
9cd300e0 JN |
3169 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
3170 | kfree(intel_connector->edid); | |
3171 | ||
acd8db10 PZ |
3172 | /* Can't call is_edp() since the encoder may have been destroyed |
3173 | * already. */ | |
3174 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
1d508706 | 3175 | intel_panel_fini(&intel_connector->panel); |
aaa6fd2a | 3176 | |
a4fc5ed6 | 3177 | drm_connector_cleanup(connector); |
55f78c43 | 3178 | kfree(connector); |
a4fc5ed6 KP |
3179 | } |
3180 | ||
00c09d70 | 3181 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
24d05927 | 3182 | { |
da63a9f2 PZ |
3183 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
3184 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
bd173813 | 3185 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
24d05927 DV |
3186 | |
3187 | i2c_del_adapter(&intel_dp->adapter); | |
3188 | drm_encoder_cleanup(encoder); | |
bd943159 KP |
3189 | if (is_edp(intel_dp)) { |
3190 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
bd173813 | 3191 | mutex_lock(&dev->mode_config.mutex); |
bd943159 | 3192 | ironlake_panel_vdd_off_sync(intel_dp); |
bd173813 | 3193 | mutex_unlock(&dev->mode_config.mutex); |
bd943159 | 3194 | } |
da63a9f2 | 3195 | kfree(intel_dig_port); |
24d05927 DV |
3196 | } |
3197 | ||
a4fc5ed6 | 3198 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
2bd2ad64 | 3199 | .dpms = intel_connector_dpms, |
a4fc5ed6 KP |
3200 | .detect = intel_dp_detect, |
3201 | .fill_modes = drm_helper_probe_single_connector_modes, | |
f684960e | 3202 | .set_property = intel_dp_set_property, |
73845adf | 3203 | .destroy = intel_dp_connector_destroy, |
a4fc5ed6 KP |
3204 | }; |
3205 | ||
3206 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
3207 | .get_modes = intel_dp_get_modes, | |
3208 | .mode_valid = intel_dp_mode_valid, | |
df0e9248 | 3209 | .best_encoder = intel_best_encoder, |
a4fc5ed6 KP |
3210 | }; |
3211 | ||
a4fc5ed6 | 3212 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
24d05927 | 3213 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
3214 | }; |
3215 | ||
995b6762 | 3216 | static void |
21d40d37 | 3217 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
c8110e52 | 3218 | { |
fa90ecef | 3219 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
c8110e52 | 3220 | |
885a5014 | 3221 | intel_dp_check_link_status(intel_dp); |
c8110e52 | 3222 | } |
6207937d | 3223 | |
e3421a18 ZW |
3224 | /* Return which DP Port should be selected for Transcoder DP control */ |
3225 | int | |
0206e353 | 3226 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
e3421a18 ZW |
3227 | { |
3228 | struct drm_device *dev = crtc->dev; | |
fa90ecef PZ |
3229 | struct intel_encoder *intel_encoder; |
3230 | struct intel_dp *intel_dp; | |
e3421a18 | 3231 | |
fa90ecef PZ |
3232 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
3233 | intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
e3421a18 | 3234 | |
fa90ecef PZ |
3235 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
3236 | intel_encoder->type == INTEL_OUTPUT_EDP) | |
ea5b213a | 3237 | return intel_dp->output_reg; |
e3421a18 | 3238 | } |
ea5b213a | 3239 | |
e3421a18 ZW |
3240 | return -1; |
3241 | } | |
3242 | ||
36e83a18 | 3243 | /* check the VBT to see whether the eDP is on DP-D port */ |
cb0953d7 | 3244 | bool intel_dpd_is_edp(struct drm_device *dev) |
36e83a18 ZY |
3245 | { |
3246 | struct drm_i915_private *dev_priv = dev->dev_private; | |
768f69c9 | 3247 | union child_device_config *p_child; |
36e83a18 ZY |
3248 | int i; |
3249 | ||
41aa3448 | 3250 | if (!dev_priv->vbt.child_dev_num) |
36e83a18 ZY |
3251 | return false; |
3252 | ||
41aa3448 RV |
3253 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
3254 | p_child = dev_priv->vbt.child_dev + i; | |
36e83a18 | 3255 | |
768f69c9 PZ |
3256 | if (p_child->common.dvo_port == PORT_IDPD && |
3257 | p_child->common.device_type == DEVICE_TYPE_eDP) | |
36e83a18 ZY |
3258 | return true; |
3259 | } | |
3260 | return false; | |
3261 | } | |
3262 | ||
f684960e CW |
3263 | static void |
3264 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) | |
3265 | { | |
53b41837 YN |
3266 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3267 | ||
3f43c48d | 3268 | intel_attach_force_audio_property(connector); |
e953fd7b | 3269 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 3270 | intel_dp->color_range_auto = true; |
53b41837 YN |
3271 | |
3272 | if (is_edp(intel_dp)) { | |
3273 | drm_mode_create_scaling_mode_property(connector->dev); | |
6de6d846 RC |
3274 | drm_object_attach_property( |
3275 | &connector->base, | |
53b41837 | 3276 | connector->dev->mode_config.scaling_mode_property, |
8e740cd1 YN |
3277 | DRM_MODE_SCALE_ASPECT); |
3278 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
53b41837 | 3279 | } |
f684960e CW |
3280 | } |
3281 | ||
67a54566 DV |
3282 | static void |
3283 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
f30d26e4 JN |
3284 | struct intel_dp *intel_dp, |
3285 | struct edp_power_seq *out) | |
67a54566 DV |
3286 | { |
3287 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3288 | struct edp_power_seq cur, vbt, spec, final; | |
3289 | u32 pp_on, pp_off, pp_div, pp; | |
bf13e81b | 3290 | int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
453c5420 JB |
3291 | |
3292 | if (HAS_PCH_SPLIT(dev)) { | |
bf13e81b | 3293 | pp_ctrl_reg = PCH_PP_CONTROL; |
453c5420 JB |
3294 | pp_on_reg = PCH_PP_ON_DELAYS; |
3295 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
3296 | pp_div_reg = PCH_PP_DIVISOR; | |
3297 | } else { | |
bf13e81b JN |
3298 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
3299 | ||
3300 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); | |
3301 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); | |
3302 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); | |
3303 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
453c5420 | 3304 | } |
67a54566 DV |
3305 | |
3306 | /* Workaround: Need to write PP_CONTROL with the unlock key as | |
3307 | * the very first thing. */ | |
453c5420 | 3308 | pp = ironlake_get_pp_control(intel_dp); |
bf13e81b | 3309 | I915_WRITE(pp_ctrl_reg, pp); |
67a54566 | 3310 | |
453c5420 JB |
3311 | pp_on = I915_READ(pp_on_reg); |
3312 | pp_off = I915_READ(pp_off_reg); | |
3313 | pp_div = I915_READ(pp_div_reg); | |
67a54566 DV |
3314 | |
3315 | /* Pull timing values out of registers */ | |
3316 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> | |
3317 | PANEL_POWER_UP_DELAY_SHIFT; | |
3318 | ||
3319 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> | |
3320 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
3321 | ||
3322 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> | |
3323 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
3324 | ||
3325 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> | |
3326 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
3327 | ||
3328 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
3329 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; | |
3330 | ||
3331 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
3332 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); | |
3333 | ||
41aa3448 | 3334 | vbt = dev_priv->vbt.edp_pps; |
67a54566 DV |
3335 | |
3336 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
3337 | * our hw here, which are all in 100usec. */ | |
3338 | spec.t1_t3 = 210 * 10; | |
3339 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
3340 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
3341 | spec.t10 = 500 * 10; | |
3342 | /* This one is special and actually in units of 100ms, but zero | |
3343 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
3344 | * table multiplies it with 1000 to make it in units of 100usec, | |
3345 | * too. */ | |
3346 | spec.t11_t12 = (510 + 100) * 10; | |
3347 | ||
3348 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
3349 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); | |
3350 | ||
3351 | /* Use the max of the register settings and vbt. If both are | |
3352 | * unset, fall back to the spec limits. */ | |
3353 | #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ | |
3354 | spec.field : \ | |
3355 | max(cur.field, vbt.field)) | |
3356 | assign_final(t1_t3); | |
3357 | assign_final(t8); | |
3358 | assign_final(t9); | |
3359 | assign_final(t10); | |
3360 | assign_final(t11_t12); | |
3361 | #undef assign_final | |
3362 | ||
3363 | #define get_delay(field) (DIV_ROUND_UP(final.field, 10)) | |
3364 | intel_dp->panel_power_up_delay = get_delay(t1_t3); | |
3365 | intel_dp->backlight_on_delay = get_delay(t8); | |
3366 | intel_dp->backlight_off_delay = get_delay(t9); | |
3367 | intel_dp->panel_power_down_delay = get_delay(t10); | |
3368 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
3369 | #undef get_delay | |
3370 | ||
f30d26e4 JN |
3371 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
3372 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
3373 | intel_dp->panel_power_cycle_delay); | |
3374 | ||
3375 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
3376 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
3377 | ||
3378 | if (out) | |
3379 | *out = final; | |
3380 | } | |
3381 | ||
3382 | static void | |
3383 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
3384 | struct intel_dp *intel_dp, | |
3385 | struct edp_power_seq *seq) | |
3386 | { | |
3387 | struct drm_i915_private *dev_priv = dev->dev_private; | |
453c5420 JB |
3388 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
3389 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); | |
3390 | int pp_on_reg, pp_off_reg, pp_div_reg; | |
3391 | ||
3392 | if (HAS_PCH_SPLIT(dev)) { | |
3393 | pp_on_reg = PCH_PP_ON_DELAYS; | |
3394 | pp_off_reg = PCH_PP_OFF_DELAYS; | |
3395 | pp_div_reg = PCH_PP_DIVISOR; | |
3396 | } else { | |
bf13e81b JN |
3397 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
3398 | ||
3399 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); | |
3400 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); | |
3401 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); | |
453c5420 JB |
3402 | } |
3403 | ||
67a54566 | 3404 | /* And finally store the new values in the power sequencer. */ |
f30d26e4 JN |
3405 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
3406 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); | |
3407 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | | |
3408 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); | |
67a54566 DV |
3409 | /* Compute the divisor for the pp clock, simply match the Bspec |
3410 | * formula. */ | |
453c5420 | 3411 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
f30d26e4 | 3412 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
67a54566 DV |
3413 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
3414 | ||
3415 | /* Haswell doesn't have any port selection bits for the panel | |
3416 | * power sequencer any more. */ | |
bc7d38a4 | 3417 | if (IS_VALLEYVIEW(dev)) { |
bf13e81b JN |
3418 | if (dp_to_dig_port(intel_dp)->port == PORT_B) |
3419 | port_sel = PANEL_PORT_SELECT_DPB_VLV; | |
3420 | else | |
3421 | port_sel = PANEL_PORT_SELECT_DPC_VLV; | |
bc7d38a4 ID |
3422 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
3423 | if (dp_to_dig_port(intel_dp)->port == PORT_A) | |
a24c144c | 3424 | port_sel = PANEL_PORT_SELECT_DPA; |
67a54566 | 3425 | else |
a24c144c | 3426 | port_sel = PANEL_PORT_SELECT_DPD; |
67a54566 DV |
3427 | } |
3428 | ||
453c5420 JB |
3429 | pp_on |= port_sel; |
3430 | ||
3431 | I915_WRITE(pp_on_reg, pp_on); | |
3432 | I915_WRITE(pp_off_reg, pp_off); | |
3433 | I915_WRITE(pp_div_reg, pp_div); | |
67a54566 | 3434 | |
67a54566 | 3435 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
453c5420 JB |
3436 | I915_READ(pp_on_reg), |
3437 | I915_READ(pp_off_reg), | |
3438 | I915_READ(pp_div_reg)); | |
f684960e CW |
3439 | } |
3440 | ||
ed92f0b2 PZ |
3441 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
3442 | struct intel_connector *intel_connector) | |
3443 | { | |
3444 | struct drm_connector *connector = &intel_connector->base; | |
3445 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3446 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
3447 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3448 | struct drm_display_mode *fixed_mode = NULL; | |
3449 | struct edp_power_seq power_seq = { 0 }; | |
3450 | bool has_dpcd; | |
3451 | struct drm_display_mode *scan; | |
3452 | struct edid *edid; | |
3453 | ||
3454 | if (!is_edp(intel_dp)) | |
3455 | return true; | |
3456 | ||
3457 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); | |
3458 | ||
3459 | /* Cache DPCD and EDID for edp. */ | |
3460 | ironlake_edp_panel_vdd_on(intel_dp); | |
3461 | has_dpcd = intel_dp_get_dpcd(intel_dp); | |
3462 | ironlake_edp_panel_vdd_off(intel_dp, false); | |
3463 | ||
3464 | if (has_dpcd) { | |
3465 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) | |
3466 | dev_priv->no_aux_handshake = | |
3467 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
3468 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; | |
3469 | } else { | |
3470 | /* if this fails, presume the device is a ghost */ | |
3471 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); | |
ed92f0b2 PZ |
3472 | return false; |
3473 | } | |
3474 | ||
3475 | /* We now know it's not a ghost, init power sequence regs. */ | |
3476 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, | |
3477 | &power_seq); | |
3478 | ||
3479 | ironlake_edp_panel_vdd_on(intel_dp); | |
3480 | edid = drm_get_edid(connector, &intel_dp->adapter); | |
3481 | if (edid) { | |
3482 | if (drm_add_edid_modes(connector, edid)) { | |
3483 | drm_mode_connector_update_edid_property(connector, | |
3484 | edid); | |
3485 | drm_edid_to_eld(connector, edid); | |
3486 | } else { | |
3487 | kfree(edid); | |
3488 | edid = ERR_PTR(-EINVAL); | |
3489 | } | |
3490 | } else { | |
3491 | edid = ERR_PTR(-ENOENT); | |
3492 | } | |
3493 | intel_connector->edid = edid; | |
3494 | ||
3495 | /* prefer fixed mode from EDID if available */ | |
3496 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
3497 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
3498 | fixed_mode = drm_mode_duplicate(dev, scan); | |
3499 | break; | |
3500 | } | |
3501 | } | |
3502 | ||
3503 | /* fallback to VBT if available for eDP */ | |
3504 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { | |
3505 | fixed_mode = drm_mode_duplicate(dev, | |
3506 | dev_priv->vbt.lfp_lvds_vbt_mode); | |
3507 | if (fixed_mode) | |
3508 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
3509 | } | |
3510 | ||
3511 | ironlake_edp_panel_vdd_off(intel_dp, false); | |
3512 | ||
3513 | intel_panel_init(&intel_connector->panel, fixed_mode); | |
3514 | intel_panel_setup_backlight(connector); | |
3515 | ||
3516 | return true; | |
3517 | } | |
3518 | ||
16c25533 | 3519 | bool |
f0fec3f2 PZ |
3520 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
3521 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 3522 | { |
f0fec3f2 PZ |
3523 | struct drm_connector *connector = &intel_connector->base; |
3524 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
3525 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
3526 | struct drm_device *dev = intel_encoder->base.dev; | |
a4fc5ed6 | 3527 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 3528 | enum port port = intel_dig_port->port; |
5eb08b69 | 3529 | const char *name = NULL; |
b2a14755 | 3530 | int type, error; |
a4fc5ed6 | 3531 | |
0767935e DV |
3532 | /* Preserve the current hw state. */ |
3533 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
dd06f90e | 3534 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 3535 | |
f7d24902 | 3536 | type = DRM_MODE_CONNECTOR_DisplayPort; |
19c03924 GB |
3537 | /* |
3538 | * FIXME : We need to initialize built-in panels before external panels. | |
3539 | * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup | |
3540 | */ | |
f7d24902 ID |
3541 | switch (port) { |
3542 | case PORT_A: | |
b329530c | 3543 | type = DRM_MODE_CONNECTOR_eDP; |
f7d24902 ID |
3544 | break; |
3545 | case PORT_C: | |
3546 | if (IS_VALLEYVIEW(dev)) | |
3547 | type = DRM_MODE_CONNECTOR_eDP; | |
3548 | break; | |
3549 | case PORT_D: | |
3550 | if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev)) | |
3551 | type = DRM_MODE_CONNECTOR_eDP; | |
3552 | break; | |
3553 | default: /* silence GCC warning */ | |
3554 | break; | |
b329530c AJ |
3555 | } |
3556 | ||
f7d24902 ID |
3557 | /* |
3558 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
3559 | * for DP the encoder type can be set by the caller to | |
3560 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
3561 | */ | |
3562 | if (type == DRM_MODE_CONNECTOR_eDP) | |
3563 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
3564 | ||
e7281eab ID |
3565 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
3566 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
3567 | port_name(port)); | |
3568 | ||
b329530c | 3569 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
3570 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
3571 | ||
a4fc5ed6 KP |
3572 | connector->interlace_allowed = true; |
3573 | connector->doublescan_allowed = 0; | |
3574 | ||
f0fec3f2 PZ |
3575 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
3576 | ironlake_panel_vdd_work); | |
a4fc5ed6 | 3577 | |
df0e9248 | 3578 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 KP |
3579 | drm_sysfs_connector_add(connector); |
3580 | ||
affa9354 | 3581 | if (HAS_DDI(dev)) |
bcbc889b PZ |
3582 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
3583 | else | |
3584 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
3585 | ||
9ed35ab1 PZ |
3586 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
3587 | if (HAS_DDI(dev)) { | |
3588 | switch (intel_dig_port->port) { | |
3589 | case PORT_A: | |
3590 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; | |
3591 | break; | |
3592 | case PORT_B: | |
3593 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; | |
3594 | break; | |
3595 | case PORT_C: | |
3596 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; | |
3597 | break; | |
3598 | case PORT_D: | |
3599 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; | |
3600 | break; | |
3601 | default: | |
3602 | BUG(); | |
3603 | } | |
3604 | } | |
e8cb4558 | 3605 | |
a4fc5ed6 | 3606 | /* Set up the DDC bus. */ |
ab9d7c30 PZ |
3607 | switch (port) { |
3608 | case PORT_A: | |
1d843f9d | 3609 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
3610 | name = "DPDDC-A"; |
3611 | break; | |
3612 | case PORT_B: | |
1d843f9d | 3613 | intel_encoder->hpd_pin = HPD_PORT_B; |
ab9d7c30 PZ |
3614 | name = "DPDDC-B"; |
3615 | break; | |
3616 | case PORT_C: | |
1d843f9d | 3617 | intel_encoder->hpd_pin = HPD_PORT_C; |
ab9d7c30 PZ |
3618 | name = "DPDDC-C"; |
3619 | break; | |
3620 | case PORT_D: | |
1d843f9d | 3621 | intel_encoder->hpd_pin = HPD_PORT_D; |
ab9d7c30 PZ |
3622 | name = "DPDDC-D"; |
3623 | break; | |
3624 | default: | |
ad1c0b19 | 3625 | BUG(); |
5eb08b69 ZW |
3626 | } |
3627 | ||
b2a14755 PZ |
3628 | error = intel_dp_i2c_init(intel_dp, intel_connector, name); |
3629 | WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n", | |
3630 | error, port_name(port)); | |
c1f05264 | 3631 | |
2b28bb1b RV |
3632 | intel_dp->psr_setup_done = false; |
3633 | ||
b2f246a8 | 3634 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
15b1d171 PZ |
3635 | i2c_del_adapter(&intel_dp->adapter); |
3636 | if (is_edp(intel_dp)) { | |
3637 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
3638 | mutex_lock(&dev->mode_config.mutex); | |
3639 | ironlake_panel_vdd_off_sync(intel_dp); | |
3640 | mutex_unlock(&dev->mode_config.mutex); | |
3641 | } | |
b2f246a8 PZ |
3642 | drm_sysfs_connector_remove(connector); |
3643 | drm_connector_cleanup(connector); | |
16c25533 | 3644 | return false; |
b2f246a8 | 3645 | } |
32f9d658 | 3646 | |
f684960e CW |
3647 | intel_dp_add_properties(intel_dp, connector); |
3648 | ||
a4fc5ed6 KP |
3649 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
3650 | * 0xd. Failure to do so will result in spurious interrupts being | |
3651 | * generated on the port when a cable is not attached. | |
3652 | */ | |
3653 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
3654 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
3655 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
3656 | } | |
16c25533 PZ |
3657 | |
3658 | return true; | |
a4fc5ed6 | 3659 | } |
f0fec3f2 PZ |
3660 | |
3661 | void | |
3662 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) | |
3663 | { | |
3664 | struct intel_digital_port *intel_dig_port; | |
3665 | struct intel_encoder *intel_encoder; | |
3666 | struct drm_encoder *encoder; | |
3667 | struct intel_connector *intel_connector; | |
3668 | ||
b14c5679 | 3669 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
f0fec3f2 PZ |
3670 | if (!intel_dig_port) |
3671 | return; | |
3672 | ||
b14c5679 | 3673 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
f0fec3f2 PZ |
3674 | if (!intel_connector) { |
3675 | kfree(intel_dig_port); | |
3676 | return; | |
3677 | } | |
3678 | ||
3679 | intel_encoder = &intel_dig_port->base; | |
3680 | encoder = &intel_encoder->base; | |
3681 | ||
3682 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, | |
3683 | DRM_MODE_ENCODER_TMDS); | |
3684 | ||
5bfe2ac0 | 3685 | intel_encoder->compute_config = intel_dp_compute_config; |
b934223d | 3686 | intel_encoder->mode_set = intel_dp_mode_set; |
00c09d70 PZ |
3687 | intel_encoder->disable = intel_disable_dp; |
3688 | intel_encoder->post_disable = intel_post_disable_dp; | |
3689 | intel_encoder->get_hw_state = intel_dp_get_hw_state; | |
045ac3b5 | 3690 | intel_encoder->get_config = intel_dp_get_config; |
ab1f90f9 | 3691 | if (IS_VALLEYVIEW(dev)) { |
ecff4f3b | 3692 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
3693 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
3694 | intel_encoder->enable = vlv_enable_dp; | |
3695 | } else { | |
ecff4f3b JN |
3696 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
3697 | intel_encoder->enable = g4x_enable_dp; | |
ab1f90f9 | 3698 | } |
f0fec3f2 | 3699 | |
174edf1f | 3700 | intel_dig_port->port = port; |
f0fec3f2 PZ |
3701 | intel_dig_port->dp.output_reg = output_reg; |
3702 | ||
00c09d70 | 3703 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
f0fec3f2 PZ |
3704 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
3705 | intel_encoder->cloneable = false; | |
3706 | intel_encoder->hot_plug = intel_dp_hot_plug; | |
3707 | ||
15b1d171 PZ |
3708 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { |
3709 | drm_encoder_cleanup(encoder); | |
3710 | kfree(intel_dig_port); | |
b2f246a8 | 3711 | kfree(intel_connector); |
15b1d171 | 3712 | } |
f0fec3f2 | 3713 | } |