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UAPI: (Scripted) Remove redundant DRM UAPI header #inclusions from drivers/gpu/.
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
a4fc5ed6 31#include "drmP.h"
a4fc5ed6
KP		 32#include "drm_crtc.h"
33#include "drm_crtc_helper.h"
d6f24d0f 34#include "drm_edid.h"
a4fc5ed6
KP		 35#include "intel_drv.h"
36#include "i915_drm.h"
37#include "i915_drv.h"
ab2c0672 38#include "drm_dp_helper.h"
a4fc5ed6 39
a2006cf5 40#define DP_RECEIVER_CAP_SIZE 0xf
a4fc5ed6
KP		 41#define DP_LINK_STATUS_SIZE 6
42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
44#define DP_LINK_CONFIGURATION_SIZE 9
45
ea5b213a
CW		 46struct intel_dp {
47 struct intel_encoder base;
a4fc5ed6
KP		 48 uint32_t output_reg;
49 uint32_t DP;
50 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
a4fc5ed6 51 bool has_audio;
c3e5f67b 52 enum hdmi_force_audio force_audio;
e953fd7b 53 uint32_t color_range;
d2b996ac 54 int dpms_mode;
a4fc5ed6
KP		 55 uint8_t link_bw;
56 uint8_t lane_count;
a2006cf5 57 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
a4fc5ed6
KP		 58 struct i2c_adapter adapter;
59 struct i2c_algo_dp_aux_data algo;
f0917379 60 bool is_pch_edp;
33a34e4e 61 uint8_t train_set[4];
f01eca2e
KP		 62 int panel_power_up_delay;
63 int panel_power_down_delay;
64 int panel_power_cycle_delay;
65 int backlight_on_delay;
66 int backlight_off_delay;
d15456de 67 struct drm_display_mode *panel_fixed_mode; /* for eDP */
bd943159
KP		 68 struct delayed_work panel_vdd_work;
69 bool want_panel_vdd;
d6f24d0f
JB		 70 struct edid *edid; /* cached EDID for eDP */
71 int edid_mode_count;
a4fc5ed6
KP		 72};
73
cfcb0fc9
JB		 74/**
75 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
76 * @intel_dp: DP struct
77 *
78 * If a CPU or PCH DP output is attached to an eDP panel, this function
79 * will return true, and false otherwise.
80 */
81static bool is_edp(struct intel_dp *intel_dp)
82{
83 return intel_dp->base.type == INTEL_OUTPUT_EDP;
84}
85
86/**
87 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
88 * @intel_dp: DP struct
89 *
90 * Returns true if the given DP struct corresponds to a PCH DP port attached
91 * to an eDP panel, false otherwise. Helpful for determining whether we
92 * may need FDI resources for a given DP output or not.
93 */
94static bool is_pch_edp(struct intel_dp *intel_dp)
95{
96 return intel_dp->is_pch_edp;
97}
98
1c95822a
AJ		 99/**
100 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
101 * @intel_dp: DP struct
102 *
103 * Returns true if the given DP struct corresponds to a CPU eDP port.
104 */
105static bool is_cpu_edp(struct intel_dp *intel_dp)
106{
107 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
108}
109
ea5b213a
CW		 110static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
111{
4ef69c7a 112 return container_of(encoder, struct intel_dp, base.base);
ea5b213a 113}
a4fc5ed6 114
df0e9248
CW		 115static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
116{
117 return container_of(intel_attached_encoder(connector),
118 struct intel_dp, base);
119}
120
814948ad
JB		 121/**
122 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
123 * @encoder: DRM encoder
124 *
125 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
126 * by intel_display.c.
127 */
128bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
129{
130 struct intel_dp *intel_dp;
131
132 if (!encoder)
133 return false;
134
135 intel_dp = enc_to_intel_dp(encoder);
136
137 return is_pch_edp(intel_dp);
138}
139
33a34e4e
JB		 140static void intel_dp_start_link_train(struct intel_dp *intel_dp);
141static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
ea5b213a 142static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 143
32f9d658 144void
0206e353 145intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 146 int *lane_num, int *link_bw)
32f9d658 147{
ea5b213a 148 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 149
ea5b213a
CW		 150 *lane_num = intel_dp->lane_count;
151 if (intel_dp->link_bw == DP_LINK_BW_1_62)
32f9d658 152 *link_bw = 162000;
ea5b213a 153 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
32f9d658
ZW		 154 *link_bw = 270000;
155}
156
94bf2ced
DV		 157int
158intel_edp_target_clock(struct intel_encoder *intel_encoder,
159 struct drm_display_mode *mode)
160{
161 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
162
163 if (intel_dp->panel_fixed_mode)
164 return intel_dp->panel_fixed_mode->clock;
165 else
166 return mode->clock;
167}
168
a4fc5ed6 169static int
ea5b213a 170intel_dp_max_lane_count(struct intel_dp *intel_dp)
a4fc5ed6 171{
9a10f401
KP		 172 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
173 switch (max_lane_count) {
174 case 1: case 2: case 4:
175 break;
176 default:
177 max_lane_count = 4;
a4fc5ed6
KP		 178 }
179 return max_lane_count;
180}
181
182static int
ea5b213a 183intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 184{
7183dc29 185 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 186
187 switch (max_link_bw) {
188 case DP_LINK_BW_1_62:
189 case DP_LINK_BW_2_7:
190 break;
191 default:
192 max_link_bw = DP_LINK_BW_1_62;
193 break;
194 }
195 return max_link_bw;
196}
197
198static int
199intel_dp_link_clock(uint8_t link_bw)
200{
201 if (link_bw == DP_LINK_BW_2_7)
202 return 270000;
203 else
204 return 162000;
205}
206
cd9dde44
AJ		 207/*
208 * The units on the numbers in the next two are... bizarre. Examples will
209 * make it clearer; this one parallels an example in the eDP spec.
210 *
211 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
212 *
213 * 270000 * 1 * 8 / 10 == 216000
214 *
215 * The actual data capacity of that configuration is 2.16Gbit/s, so the
216 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
217 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
218 * 119000. At 18bpp that's 2142000 kilobits per second.
219 *
220 * Thus the strange-looking division by 10 in intel_dp_link_required, to
221 * get the result in decakilobits instead of kilobits.
222 */
223
a4fc5ed6 224static int
c898261c 225intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 226{
cd9dde44 227 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 228}
229
fe27d53e
DA		 230static int
231intel_dp_max_data_rate(int max_link_clock, int max_lanes)
232{
233 return (max_link_clock * max_lanes * 8) / 10;
234}
235
c4867936
DV		 236static bool
237intel_dp_adjust_dithering(struct intel_dp *intel_dp,
238 struct drm_display_mode *mode,
cb1793ce 239 bool adjust_mode)
c4867936
DV		 240{
241 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
242 int max_lanes = intel_dp_max_lane_count(intel_dp);
243 int max_rate, mode_rate;
244
245 mode_rate = intel_dp_link_required(mode->clock, 24);
246 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
247
248 if (mode_rate > max_rate) {
249 mode_rate = intel_dp_link_required(mode->clock, 18);
250 if (mode_rate > max_rate)
251 return false;
252
cb1793ce
DV		 253 if (adjust_mode)
254 mode->private_flags
c4867936
DV		 255 |= INTEL_MODE_DP_FORCE_6BPC;
256
257 return true;
258 }
259
260 return true;
261}
262
a4fc5ed6
KP		 263static int
264intel_dp_mode_valid(struct drm_connector *connector,
265 struct drm_display_mode *mode)
266{
df0e9248 267 struct intel_dp *intel_dp = intel_attached_dp(connector);
a4fc5ed6 268
d15456de
KP		 269 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
270 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
7de56f43
ZY		 271 return MODE_PANEL;
272
d15456de 273 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
7de56f43
ZY		 274 return MODE_PANEL;
275 }
276
cb1793ce 277 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 278 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 279
280 if (mode->clock < 10000)
281 return MODE_CLOCK_LOW;
282
0af78a2b
DV		 283 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
284 return MODE_H_ILLEGAL;
285
a4fc5ed6
KP		 286 return MODE_OK;
287}
288
289static uint32_t
290pack_aux(uint8_t *src, int src_bytes)
291{
292 int i;
293 uint32_t v = 0;
294
295 if (src_bytes > 4)
296 src_bytes = 4;
297 for (i = 0; i < src_bytes; i++)
298 v |= ((uint32_t) src[i]) << ((3-i) * 8);
299 return v;
300}
301
302static void
303unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
304{
305 int i;
306 if (dst_bytes > 4)
307 dst_bytes = 4;
308 for (i = 0; i < dst_bytes; i++)
309 dst[i] = src >> ((3-i) * 8);
310}
311
fb0f8fbf
KP		 312/* hrawclock is 1/4 the FSB frequency */
313static int
314intel_hrawclk(struct drm_device *dev)
315{
316 struct drm_i915_private *dev_priv = dev->dev_private;
317 uint32_t clkcfg;
318
319 clkcfg = I915_READ(CLKCFG);
320 switch (clkcfg & CLKCFG_FSB_MASK) {
321 case CLKCFG_FSB_400:
322 return 100;
323 case CLKCFG_FSB_533:
324 return 133;
325 case CLKCFG_FSB_667:
326 return 166;
327 case CLKCFG_FSB_800:
328 return 200;
329 case CLKCFG_FSB_1067:
330 return 266;
331 case CLKCFG_FSB_1333:
332 return 333;
333 /* these two are just a guess; one of them might be right */
334 case CLKCFG_FSB_1600:
335 case CLKCFG_FSB_1600_ALT:
336 return 400;
337 default:
338 return 133;
339 }
340}
341
ebf33b18
KP		 342static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
343{
344 struct drm_device *dev = intel_dp->base.base.dev;
345 struct drm_i915_private *dev_priv = dev->dev_private;
346
347 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
348}
349
350static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
351{
352 struct drm_device *dev = intel_dp->base.base.dev;
353 struct drm_i915_private *dev_priv = dev->dev_private;
354
355 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
356}
357
9b984dae
KP		 358static void
359intel_dp_check_edp(struct intel_dp *intel_dp)
360{
361 struct drm_device *dev = intel_dp->base.base.dev;
362 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 363
9b984dae
KP		 364 if (!is_edp(intel_dp))
365 return;
ebf33b18 366 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 367 WARN(1, "eDP powered off while attempting aux channel communication.\n");
368 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 369 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 370 I915_READ(PCH_PP_CONTROL));
371 }
372}
373
a4fc5ed6 374static int
ea5b213a 375intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 376 uint8_t *send, int send_bytes,
377 uint8_t *recv, int recv_size)
378{
ea5b213a 379 uint32_t output_reg = intel_dp->output_reg;
4ef69c7a 380 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 381 struct drm_i915_private *dev_priv = dev->dev_private;
382 uint32_t ch_ctl = output_reg + 0x10;
383 uint32_t ch_data = ch_ctl + 4;
384 int i;
385 int recv_bytes;
a4fc5ed6 386 uint32_t status;
fb0f8fbf 387 uint32_t aux_clock_divider;
6b4e0a93 388 int try, precharge;
a4fc5ed6 389
9b984dae 390 intel_dp_check_edp(intel_dp);
a4fc5ed6 391 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 392 * and would like to run at 2MHz. So, take the
393 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 394 *
395 * Note that PCH attached eDP panels should use a 125MHz input
396 * clock divider.
a4fc5ed6 397 */
1c95822a 398 if (is_cpu_edp(intel_dp)) {
1a2eb460
KP		 399 if (IS_GEN6(dev) || IS_GEN7(dev))
400 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 401 else
402 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
403 } else if (HAS_PCH_SPLIT(dev))
6919132e 404 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 405 else
406 aux_clock_divider = intel_hrawclk(dev) / 2;
407
6b4e0a93
DV		 408 if (IS_GEN6(dev))
409 precharge = 3;
410 else
411 precharge = 5;
412
11bee43e
JB		 413 /* Try to wait for any previous AUX channel activity */
414 for (try = 0; try < 3; try++) {
415 status = I915_READ(ch_ctl);
416 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
417 break;
418 msleep(1);
419 }
420
421 if (try == 3) {
422 WARN(1, "dp_aux_ch not started status 0x%08x\n",
423 I915_READ(ch_ctl));
4f7f7b7e
CW		 424 return -EBUSY;
425 }
426
fb0f8fbf
KP		 427 /* Must try at least 3 times according to DP spec */
428 for (try = 0; try < 5; try++) {
429 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 430 for (i = 0; i < send_bytes; i += 4)
431 I915_WRITE(ch_data + i,
432 pack_aux(send + i, send_bytes - i));
0206e353 433
fb0f8fbf 434 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 435 I915_WRITE(ch_ctl,
436 DP_AUX_CH_CTL_SEND_BUSY |
437 DP_AUX_CH_CTL_TIME_OUT_400us |
438 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
439 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
440 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
441 DP_AUX_CH_CTL_DONE |
442 DP_AUX_CH_CTL_TIME_OUT_ERROR |
443 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 444 for (;;) {
fb0f8fbf
KP		 445 status = I915_READ(ch_ctl);
446 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
447 break;
4f7f7b7e 448 udelay(100);
fb0f8fbf 449 }
0206e353 450
fb0f8fbf 451 /* Clear done status and any errors */
4f7f7b7e
CW		 452 I915_WRITE(ch_ctl,
453 status |
454 DP_AUX_CH_CTL_DONE |
455 DP_AUX_CH_CTL_TIME_OUT_ERROR |
456 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 457
458 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
459 DP_AUX_CH_CTL_RECEIVE_ERROR))
460 continue;
4f7f7b7e 461 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 462 break;
463 }
464
a4fc5ed6 465 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 466 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 467 return -EBUSY;
a4fc5ed6
KP		 468 }
469
470 /* Check for timeout or receive error.
471 * Timeouts occur when the sink is not connected
472 */
a5b3da54 473 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 474 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 475 return -EIO;
476 }
1ae8c0a5
KP		 477
478 /* Timeouts occur when the device isn't connected, so they're
479 * "normal" -- don't fill the kernel log with these */
a5b3da54 480 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 481 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 482 return -ETIMEDOUT;
a4fc5ed6
KP		 483 }
484
485 /* Unload any bytes sent back from the other side */
486 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
487 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 488 if (recv_bytes > recv_size)
489 recv_bytes = recv_size;
0206e353 490
4f7f7b7e
CW		 491 for (i = 0; i < recv_bytes; i += 4)
492 unpack_aux(I915_READ(ch_data + i),
493 recv + i, recv_bytes - i);
a4fc5ed6
KP		 494
495 return recv_bytes;
496}
497
498/* Write data to the aux channel in native mode */
499static int
ea5b213a 500intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 501 uint16_t address, uint8_t *send, int send_bytes)
502{
503 int ret;
504 uint8_t msg[20];
505 int msg_bytes;
506 uint8_t ack;
507
9b984dae 508 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 509 if (send_bytes > 16)
510 return -1;
511 msg[0] = AUX_NATIVE_WRITE << 4;
512 msg[1] = address >> 8;
eebc863e 513 msg[2] = address & 0xff;
a4fc5ed6
KP		 514 msg[3] = send_bytes - 1;
515 memcpy(&msg[4], send, send_bytes);
516 msg_bytes = send_bytes + 4;
517 for (;;) {
ea5b213a 518 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 519 if (ret < 0)
520 return ret;
521 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
522 break;
523 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
524 udelay(100);
525 else
a5b3da54 526 return -EIO;
a4fc5ed6
KP		 527 }
528 return send_bytes;
529}
530
531/* Write a single byte to the aux channel in native mode */
532static int
ea5b213a 533intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 534 uint16_t address, uint8_t byte)
535{
ea5b213a 536 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 537}
538
539/* read bytes from a native aux channel */
540static int
ea5b213a 541intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 542 uint16_t address, uint8_t *recv, int recv_bytes)
543{
544 uint8_t msg[4];
545 int msg_bytes;
546 uint8_t reply[20];
547 int reply_bytes;
548 uint8_t ack;
549 int ret;
550
9b984dae 551 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 552 msg[0] = AUX_NATIVE_READ << 4;
553 msg[1] = address >> 8;
554 msg[2] = address & 0xff;
555 msg[3] = recv_bytes - 1;
556
557 msg_bytes = 4;
558 reply_bytes = recv_bytes + 1;
559
560 for (;;) {
ea5b213a 561 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 562 reply, reply_bytes);
a5b3da54
KP		 563 if (ret == 0)
564 return -EPROTO;
565 if (ret < 0)
a4fc5ed6
KP		 566 return ret;
567 ack = reply[0];
568 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
569 memcpy(recv, reply + 1, ret - 1);
570 return ret - 1;
571 }
572 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
573 udelay(100);
574 else
a5b3da54 575 return -EIO;
a4fc5ed6
KP		 576 }
577}
578
579static int
ab2c0672
DA		 580intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
581 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 582{
ab2c0672 583 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 584 struct intel_dp *intel_dp = container_of(adapter,
585 struct intel_dp,
586 adapter);
ab2c0672
DA		 587 uint16_t address = algo_data->address;
588 uint8_t msg[5];
589 uint8_t reply[2];
8316f337 590 unsigned retry;
ab2c0672
DA		 591 int msg_bytes;
592 int reply_bytes;
593 int ret;
594
9b984dae 595 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 596 /* Set up the command byte */
597 if (mode & MODE_I2C_READ)
598 msg[0] = AUX_I2C_READ << 4;
599 else
600 msg[0] = AUX_I2C_WRITE << 4;
601
602 if (!(mode & MODE_I2C_STOP))
603 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 604
ab2c0672
DA		 605 msg[1] = address >> 8;
606 msg[2] = address;
607
608 switch (mode) {
609 case MODE_I2C_WRITE:
610 msg[3] = 0;
611 msg[4] = write_byte;
612 msg_bytes = 5;
613 reply_bytes = 1;
614 break;
615 case MODE_I2C_READ:
616 msg[3] = 0;
617 msg_bytes = 4;
618 reply_bytes = 2;
619 break;
620 default:
621 msg_bytes = 3;
622 reply_bytes = 1;
623 break;
624 }
625
8316f337
DF		 626 for (retry = 0; retry < 5; retry++) {
627 ret = intel_dp_aux_ch(intel_dp,
628 msg, msg_bytes,
629 reply, reply_bytes);
ab2c0672 630 if (ret < 0) {
3ff99164 631 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 632 return ret;
633 }
8316f337
DF		 634
635 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
636 case AUX_NATIVE_REPLY_ACK:
637 /* I2C-over-AUX Reply field is only valid
638 * when paired with AUX ACK.
639 */
640 break;
641 case AUX_NATIVE_REPLY_NACK:
642 DRM_DEBUG_KMS("aux_ch native nack\n");
643 return -EREMOTEIO;
644 case AUX_NATIVE_REPLY_DEFER:
645 udelay(100);
646 continue;
647 default:
648 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
649 reply[0]);
650 return -EREMOTEIO;
651 }
652
ab2c0672
DA		 653 switch (reply[0] & AUX_I2C_REPLY_MASK) {
654 case AUX_I2C_REPLY_ACK:
655 if (mode == MODE_I2C_READ) {
656 *read_byte = reply[1];
657 }
658 return reply_bytes - 1;
659 case AUX_I2C_REPLY_NACK:
8316f337 660 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 661 return -EREMOTEIO;
662 case AUX_I2C_REPLY_DEFER:
8316f337 663 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 664 udelay(100);
665 break;
666 default:
8316f337 667 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 668 return -EREMOTEIO;
669 }
670 }
8316f337
DF		 671
672 DRM_ERROR("too many retries, giving up\n");
673 return -EREMOTEIO;
a4fc5ed6
KP		 674}
675
0b5c541b 676static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
bd943159 677static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0b5c541b 678
a4fc5ed6 679static int
ea5b213a 680intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 681 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 682{
0b5c541b
KP		 683 int ret;
684
d54e9d28 685 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 686 intel_dp->algo.running = false;
687 intel_dp->algo.address = 0;
688 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
689
0206e353 690 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 691 intel_dp->adapter.owner = THIS_MODULE;
692 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 693 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 694 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
695 intel_dp->adapter.algo_data = &intel_dp->algo;
696 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
697
0b5c541b
KP		 698 ironlake_edp_panel_vdd_on(intel_dp);
699 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 700 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 701 return ret;
a4fc5ed6
KP		 702}
703
704static bool
e811f5ae
LP		 705intel_dp_mode_fixup(struct drm_encoder *encoder,
706 const struct drm_display_mode *mode,
a4fc5ed6
KP		 707 struct drm_display_mode *adjusted_mode)
708{
0d3a1bee 709 struct drm_device *dev = encoder->dev;
ea5b213a 710 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
a4fc5ed6 711 int lane_count, clock;
ea5b213a
CW		 712 int max_lane_count = intel_dp_max_lane_count(intel_dp);
713 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 714 int bpp, mode_rate;
a4fc5ed6
KP		 715 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
716
d15456de
KP		 717 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
718 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
1d8e1c75
CW		 719 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
720 mode, adjusted_mode);
0d3a1bee
ZY		 721 }
722
cb1793ce 723 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 724 return false;
725
083f9560
DV		 726 DRM_DEBUG_KMS("DP link computation with max lane count %i "
727 "max bw %02x pixel clock %iKHz\n",
71244653 728 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 729
cb1793ce 730 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 731 return false;
732
733 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
71244653 734 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 735
2514bc51
JB		 736 for (clock = 0; clock <= max_clock; clock++) {
737 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
fe27d53e 738 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 739
083f9560 740 if (mode_rate <= link_avail) {
ea5b213a
CW		 741 intel_dp->link_bw = bws[clock];
742 intel_dp->lane_count = lane_count;
743 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
083f9560
DV		 744 DRM_DEBUG_KMS("DP link bw %02x lane "
745 "count %d clock %d bpp %d\n",
ea5b213a 746 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 747 adjusted_mode->clock, bpp);
748 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
749 mode_rate, link_avail);
a4fc5ed6
KP		 750 return true;
751 }
752 }
753 }
fe27d53e 754
a4fc5ed6
KP		 755 return false;
756}
757
758struct intel_dp_m_n {
759 uint32_t tu;
760 uint32_t gmch_m;
761 uint32_t gmch_n;
762 uint32_t link_m;
763 uint32_t link_n;
764};
765
766static void
767intel_reduce_ratio(uint32_t *num, uint32_t *den)
768{
769 while (*num > 0xffffff || *den > 0xffffff) {
770 *num >>= 1;
771 *den >>= 1;
772 }
773}
774
775static void
36e83a18 776intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 777 int nlanes,
778 int pixel_clock,
779 int link_clock,
780 struct intel_dp_m_n *m_n)
781{
782 m_n->tu = 64;
36e83a18 783 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 784 m_n->gmch_n = link_clock * nlanes;
785 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
786 m_n->link_m = pixel_clock;
787 m_n->link_n = link_clock;
788 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
789}
790
791void
792intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
793 struct drm_display_mode *adjusted_mode)
794{
795 struct drm_device *dev = crtc->dev;
6c2b7c12 796 struct intel_encoder *encoder;
a4fc5ed6
KP		 797 struct drm_i915_private *dev_priv = dev->dev_private;
798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 799 int lane_count = 4;
a4fc5ed6 800 struct intel_dp_m_n m_n;
9db4a9c7 801 int pipe = intel_crtc->pipe;
a4fc5ed6
KP		 802
803 /*
21d40d37 804 * Find the lane count in the intel_encoder private
a4fc5ed6 805 */
6c2b7c12
DV		 806 for_each_encoder_on_crtc(dev, crtc, encoder) {
807 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 808
9a10f401
KP		 809 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
810 intel_dp->base.type == INTEL_OUTPUT_EDP)
811 {
ea5b213a 812 lane_count = intel_dp->lane_count;
51190667 813 break;
a4fc5ed6
KP		 814 }
815 }
816
817 /*
818 * Compute the GMCH and Link ratios. The '3' here is
819 * the number of bytes_per_pixel post-LUT, which we always
820 * set up for 8-bits of R/G/B, or 3 bytes total.
821 */
858fa035 822 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 823 mode->clock, adjusted_mode->clock, &m_n);
824
c619eed4 825 if (HAS_PCH_SPLIT(dev)) {
9db4a9c7
JB		 826 I915_WRITE(TRANSDATA_M1(pipe),
827 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
828 m_n.gmch_m);
829 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
830 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
831 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
a4fc5ed6 832 } else {
9db4a9c7
JB		 833 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
834 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
835 m_n.gmch_m);
836 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
837 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
838 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 839 }
840}
841
f01eca2e
KP		 842static void ironlake_edp_pll_on(struct drm_encoder *encoder);
843static void ironlake_edp_pll_off(struct drm_encoder *encoder);
844
a4fc5ed6
KP		 845static void
846intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
847 struct drm_display_mode *adjusted_mode)
848{
e3421a18 849 struct drm_device *dev = encoder->dev;
417e822d 850 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 851 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4ef69c7a 852 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a4fc5ed6
KP		 853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
854
f01eca2e
KP		 855 /* Turn on the eDP PLL if needed */
856 if (is_edp(intel_dp)) {
857 if (!is_pch_edp(intel_dp))
858 ironlake_edp_pll_on(encoder);
859 else
860 ironlake_edp_pll_off(encoder);
861 }
862
417e822d 863 /*
1a2eb460 864 * There are four kinds of DP registers:
417e822d
KP		 865 *
866 * IBX PCH
1a2eb460
KP		 867 * SNB CPU
868 * IVB CPU
417e822d
KP		 869 * CPT PCH
870 *
871 * IBX PCH and CPU are the same for almost everything,
872 * except that the CPU DP PLL is configured in this
873 * register
874 *
875 * CPT PCH is quite different, having many bits moved
876 * to the TRANS_DP_CTL register instead. That
877 * configuration happens (oddly) in ironlake_pch_enable
878 */
9c9e7927 879
417e822d
KP		 880 /* Preserve the BIOS-computed detected bit. This is
881 * supposed to be read-only.
882 */
883 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
884 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 885
417e822d
KP		 886 /* Handle DP bits in common between all three register formats */
887
888 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 889
ea5b213a 890 switch (intel_dp->lane_count) {
a4fc5ed6 891 case 1:
ea5b213a 892 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 893 break;
894 case 2:
ea5b213a 895 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 896 break;
897 case 4:
ea5b213a 898 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 899 break;
900 }
e0dac65e
WF		 901 if (intel_dp->has_audio) {
902 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
903 pipe_name(intel_crtc->pipe));
ea5b213a 904 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 905 intel_write_eld(encoder, adjusted_mode);
906 }
ea5b213a
CW		 907 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
908 intel_dp->link_configuration[0] = intel_dp->link_bw;
909 intel_dp->link_configuration[1] = intel_dp->lane_count;
a2cab1b2 910 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
a4fc5ed6 911 /*
9962c925 912 * Check for DPCD version > 1.1 and enhanced framing support
a4fc5ed6 913 */
7183dc29
JB		 914 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
915 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
ea5b213a 916 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
a4fc5ed6
KP		 917 }
918
417e822d 919 /* Split out the IBX/CPU vs CPT settings */
32f9d658 920
1a2eb460
KP		 921 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
922 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
923 intel_dp->DP |= DP_SYNC_HS_HIGH;
924 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
925 intel_dp->DP |= DP_SYNC_VS_HIGH;
926 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
927
928 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
929 intel_dp->DP |= DP_ENHANCED_FRAMING;
930
931 intel_dp->DP |= intel_crtc->pipe << 29;
932
933 /* don't miss out required setting for eDP */
934 intel_dp->DP |= DP_PLL_ENABLE;
935 if (adjusted_mode->clock < 200000)
936 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
937 else
938 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
939 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 940 intel_dp->DP |= intel_dp->color_range;
941
942 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
943 intel_dp->DP |= DP_SYNC_HS_HIGH;
944 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
945 intel_dp->DP |= DP_SYNC_VS_HIGH;
946 intel_dp->DP |= DP_LINK_TRAIN_OFF;
947
948 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
949 intel_dp->DP |= DP_ENHANCED_FRAMING;
950
951 if (intel_crtc->pipe == 1)
952 intel_dp->DP |= DP_PIPEB_SELECT;
953
954 if (is_cpu_edp(intel_dp)) {
955 /* don't miss out required setting for eDP */
956 intel_dp->DP |= DP_PLL_ENABLE;
957 if (adjusted_mode->clock < 200000)
958 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
959 else
960 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
961 }
962 } else {
963 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 964 }
a4fc5ed6
KP		 965}
966
99ea7127
KP		 967#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
968#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
969
970#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
971#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
972
973#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
974#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
975
976static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
977 u32 mask,
978 u32 value)
bd943159 979{
99ea7127
KP		 980 struct drm_device *dev = intel_dp->base.base.dev;
981 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 982
99ea7127
KP		 983 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
984 mask, value,
985 I915_READ(PCH_PP_STATUS),
986 I915_READ(PCH_PP_CONTROL));
32ce697c 987
99ea7127
KP		 988 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
989 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
990 I915_READ(PCH_PP_STATUS),
991 I915_READ(PCH_PP_CONTROL));
32ce697c 992 }
99ea7127 993}
32ce697c 994
99ea7127
KP		 995static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
996{
997 DRM_DEBUG_KMS("Wait for panel power on\n");
998 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 999}
1000
99ea7127
KP		 1001static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1002{
1003 DRM_DEBUG_KMS("Wait for panel power off time\n");
1004 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1005}
1006
1007static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1008{
1009 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1010 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1011}
1012
1013
832dd3c1
KP		 1014/* Read the current pp_control value, unlocking the register if it
1015 * is locked
1016 */
1017
1018static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1019{
1020 u32 control = I915_READ(PCH_PP_CONTROL);
1021
1022 control &= ~PANEL_UNLOCK_MASK;
1023 control |= PANEL_UNLOCK_REGS;
1024 return control;
bd943159
KP		 1025}
1026
5d613501
JB		 1027static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1028{
1029 struct drm_device *dev = intel_dp->base.base.dev;
1030 struct drm_i915_private *dev_priv = dev->dev_private;
1031 u32 pp;
1032
97af61f5
KP		 1033 if (!is_edp(intel_dp))
1034 return;
f01eca2e 1035 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1036
bd943159
KP		 1037 WARN(intel_dp->want_panel_vdd,
1038 "eDP VDD already requested on\n");
1039
1040 intel_dp->want_panel_vdd = true;
99ea7127 1041
bd943159
KP		 1042 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1043 DRM_DEBUG_KMS("eDP VDD already on\n");
1044 return;
1045 }
1046
99ea7127
KP		 1047 if (!ironlake_edp_have_panel_power(intel_dp))
1048 ironlake_wait_panel_power_cycle(intel_dp);
1049
832dd3c1 1050 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1051 pp |= EDP_FORCE_VDD;
1052 I915_WRITE(PCH_PP_CONTROL, pp);
1053 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1054 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1055 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1056
1057 /*
1058 * If the panel wasn't on, delay before accessing aux channel
1059 */
1060 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1061 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1062 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1063 }
5d613501
JB		 1064}
1065
bd943159 1066static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501
JB		 1067{
1068 struct drm_device *dev = intel_dp->base.base.dev;
1069 struct drm_i915_private *dev_priv = dev->dev_private;
1070 u32 pp;
1071
bd943159 1072 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1073 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1074 pp &= ~EDP_FORCE_VDD;
1075 I915_WRITE(PCH_PP_CONTROL, pp);
1076 POSTING_READ(PCH_PP_CONTROL);
1077
1078 /* Make sure sequencer is idle before allowing subsequent activity */
1079 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1080 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1081
1082 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1083 }
1084}
5d613501 1085
bd943159
KP		 1086static void ironlake_panel_vdd_work(struct work_struct *__work)
1087{
1088 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1089 struct intel_dp, panel_vdd_work);
1090 struct drm_device *dev = intel_dp->base.base.dev;
1091
627f7675 1092 mutex_lock(&dev->mode_config.mutex);
bd943159 1093 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1094 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1095}
1096
1097static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1098{
97af61f5
KP		 1099 if (!is_edp(intel_dp))
1100 return;
5d613501 1101
bd943159
KP		 1102 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1103 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1104
bd943159
KP		 1105 intel_dp->want_panel_vdd = false;
1106
1107 if (sync) {
1108 ironlake_panel_vdd_off_sync(intel_dp);
1109 } else {
1110 /*
1111 * Queue the timer to fire a long
1112 * time from now (relative to the power down delay)
1113 * to keep the panel power up across a sequence of operations
1114 */
1115 schedule_delayed_work(&intel_dp->panel_vdd_work,
1116 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1117 }
5d613501
JB		 1118}
1119
86a3073e 1120static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1121{
01cb9ea6 1122 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1123 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1124 u32 pp;
9934c132 1125
97af61f5 1126 if (!is_edp(intel_dp))
bd943159 1127 return;
99ea7127
KP		 1128
1129 DRM_DEBUG_KMS("Turn eDP power on\n");
1130
1131 if (ironlake_edp_have_panel_power(intel_dp)) {
1132 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1133 return;
99ea7127 1134 }
9934c132 1135
99ea7127 1136 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1137
99ea7127 1138 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1139 if (IS_GEN5(dev)) {
1140 /* ILK workaround: disable reset around power sequence */
1141 pp &= ~PANEL_POWER_RESET;
1142 I915_WRITE(PCH_PP_CONTROL, pp);
1143 POSTING_READ(PCH_PP_CONTROL);
1144 }
37c6c9b0 1145
1c0ae80a 1146 pp |= POWER_TARGET_ON;
99ea7127
KP		 1147 if (!IS_GEN5(dev))
1148 pp |= PANEL_POWER_RESET;
1149
9934c132 1150 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1151 POSTING_READ(PCH_PP_CONTROL);
9934c132 1152
99ea7127 1153 ironlake_wait_panel_on(intel_dp);
9934c132 1154
05ce1a49
KP		 1155 if (IS_GEN5(dev)) {
1156 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1157 I915_WRITE(PCH_PP_CONTROL, pp);
1158 POSTING_READ(PCH_PP_CONTROL);
1159 }
9934c132
JB		 1160}
1161
99ea7127 1162static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1163{
99ea7127 1164 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1165 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1166 u32 pp;
9934c132 1167
97af61f5
KP		 1168 if (!is_edp(intel_dp))
1169 return;
37c6c9b0 1170
99ea7127 1171 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1172
6cb49835 1173 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1174
99ea7127 1175 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1176 /* We need to switch off panel power _and_ force vdd, for otherwise some
1177 * panels get very unhappy and cease to work. */
1178 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1179 I915_WRITE(PCH_PP_CONTROL, pp);
1180 POSTING_READ(PCH_PP_CONTROL);
9934c132 1181
35a38556
DV		 1182 intel_dp->want_panel_vdd = false;
1183
99ea7127 1184 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1185}
1186
86a3073e 1187static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1188{
f01eca2e 1189 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1190 struct drm_i915_private *dev_priv = dev->dev_private;
1191 u32 pp;
1192
f01eca2e
KP		 1193 if (!is_edp(intel_dp))
1194 return;
1195
28c97730 1196 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1197 /*
1198 * If we enable the backlight right away following a panel power
1199 * on, we may see slight flicker as the panel syncs with the eDP
1200 * link. So delay a bit to make sure the image is solid before
1201 * allowing it to appear.
1202 */
f01eca2e 1203 msleep(intel_dp->backlight_on_delay);
832dd3c1 1204 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1205 pp |= EDP_BLC_ENABLE;
1206 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1207 POSTING_READ(PCH_PP_CONTROL);
32f9d658
ZW		 1208}
1209
86a3073e 1210static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1211{
f01eca2e 1212 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1213 struct drm_i915_private *dev_priv = dev->dev_private;
1214 u32 pp;
1215
f01eca2e
KP		 1216 if (!is_edp(intel_dp))
1217 return;
1218
28c97730 1219 DRM_DEBUG_KMS("\n");
832dd3c1 1220 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1221 pp &= ~EDP_BLC_ENABLE;
1222 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1223 POSTING_READ(PCH_PP_CONTROL);
1224 msleep(intel_dp->backlight_off_delay);
32f9d658 1225}
a4fc5ed6 1226
d240f20f
JB		 1227static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1228{
1229 struct drm_device *dev = encoder->dev;
1230 struct drm_i915_private *dev_priv = dev->dev_private;
1231 u32 dpa_ctl;
1232
1233 DRM_DEBUG_KMS("\n");
1234 dpa_ctl = I915_READ(DP_A);
298b0b39 1235 dpa_ctl |= DP_PLL_ENABLE;
d240f20f 1236 I915_WRITE(DP_A, dpa_ctl);
298b0b39
JB		 1237 POSTING_READ(DP_A);
1238 udelay(200);
d240f20f
JB		 1239}
1240
1241static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1242{
1243 struct drm_device *dev = encoder->dev;
1244 struct drm_i915_private *dev_priv = dev->dev_private;
1245 u32 dpa_ctl;
1246
1247 dpa_ctl = I915_READ(DP_A);
298b0b39 1248 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1249 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1250 POSTING_READ(DP_A);
d240f20f
JB		 1251 udelay(200);
1252}
1253
c7ad3810
JB		 1254/* If the sink supports it, try to set the power state appropriately */
1255static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1256{
1257 int ret, i;
1258
1259 /* Should have a valid DPCD by this point */
1260 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1261 return;
1262
1263 if (mode != DRM_MODE_DPMS_ON) {
1264 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1265 DP_SET_POWER_D3);
1266 if (ret != 1)
1267 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1268 } else {
1269 /*
1270 * When turning on, we need to retry for 1ms to give the sink
1271 * time to wake up.
1272 */
1273 for (i = 0; i < 3; i++) {
1274 ret = intel_dp_aux_native_write_1(intel_dp,
1275 DP_SET_POWER,
1276 DP_SET_POWER_D0);
1277 if (ret == 1)
1278 break;
1279 msleep(1);
1280 }
1281 }
1282}
1283
d240f20f
JB		 1284static void intel_dp_prepare(struct drm_encoder *encoder)
1285{
1286 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
d240f20f 1287
6cb49835
DV		 1288
1289 /* Make sure the panel is off before trying to change the mode. But also
1290 * ensure that we have vdd while we switch off the panel. */
1291 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1292 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1293 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1294 ironlake_edp_panel_off(intel_dp);
21264c63 1295 intel_dp_link_down(intel_dp);
d240f20f
JB		 1296}
1297
1298static void intel_dp_commit(struct drm_encoder *encoder)
1299{
1300 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
d4270e57
JB		 1301 struct drm_device *dev = encoder->dev;
1302 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
5d613501 1303
97af61f5 1304 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1305 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1306 intel_dp_start_link_train(intel_dp);
97af61f5 1307 ironlake_edp_panel_on(intel_dp);
bd943159 1308 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1309 intel_dp_complete_link_train(intel_dp);
f01eca2e 1310 ironlake_edp_backlight_on(intel_dp);
d2b996ac
KP		 1311
1312 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
d4270e57
JB		 1313
1314 if (HAS_PCH_CPT(dev))
1315 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
d240f20f
JB		 1316}
1317
a4fc5ed6
KP		 1318static void
1319intel_dp_dpms(struct drm_encoder *encoder, int mode)
1320{
ea5b213a 1321 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
55f78c43 1322 struct drm_device *dev = encoder->dev;
a4fc5ed6 1323 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1324 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
a4fc5ed6
KP		 1325
1326 if (mode != DRM_MODE_DPMS_ON) {
6cb49835
DV		 1327 /* Switching the panel off requires vdd. */
1328 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1329 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1330 intel_dp_sink_dpms(intel_dp, mode);
35a38556 1331 ironlake_edp_panel_off(intel_dp);
736085bc 1332 intel_dp_link_down(intel_dp);
21264c63
KP		 1333
1334 if (is_cpu_edp(intel_dp))
1335 ironlake_edp_pll_off(encoder);
a4fc5ed6 1336 } else {
21264c63
KP		 1337 if (is_cpu_edp(intel_dp))
1338 ironlake_edp_pll_on(encoder);
1339
97af61f5 1340 ironlake_edp_panel_vdd_on(intel_dp);
c7ad3810 1341 intel_dp_sink_dpms(intel_dp, mode);
32f9d658 1342 if (!(dp_reg & DP_PORT_EN)) {
01cb9ea6 1343 intel_dp_start_link_train(intel_dp);
97af61f5 1344 ironlake_edp_panel_on(intel_dp);
bd943159 1345 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1346 intel_dp_complete_link_train(intel_dp);
bee7eb2d 1347 } else
bd943159
KP		 1348 ironlake_edp_panel_vdd_off(intel_dp, false);
1349 ironlake_edp_backlight_on(intel_dp);
a4fc5ed6 1350 }
d2b996ac 1351 intel_dp->dpms_mode = mode;
a4fc5ed6
KP		 1352}
1353
1354/*
df0c237d
JB		 1355 * Native read with retry for link status and receiver capability reads for
1356 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1357 */
1358static bool
df0c237d
JB		 1359intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1360 uint8_t *recv, int recv_bytes)
a4fc5ed6 1361{
61da5fab
JB		 1362 int ret, i;
1363
df0c237d
JB		 1364 /*
1365 * Sinks are *supposed* to come up within 1ms from an off state,
1366 * but we're also supposed to retry 3 times per the spec.
1367 */
61da5fab 1368 for (i = 0; i < 3; i++) {
df0c237d
JB		 1369 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1370 recv_bytes);
1371 if (ret == recv_bytes)
61da5fab
JB		 1372 return true;
1373 msleep(1);
1374 }
a4fc5ed6 1375
61da5fab 1376 return false;
a4fc5ed6
KP		 1377}
1378
1379/*
1380 * Fetch AUX CH registers 0x202 - 0x207 which contain
1381 * link status information
1382 */
1383static bool
93f62dad 1384intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1385{
df0c237d
JB		 1386 return intel_dp_aux_native_read_retry(intel_dp,
1387 DP_LANE0_1_STATUS,
93f62dad 1388 link_status,
df0c237d 1389 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1390}
1391
1392static uint8_t
1393intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1394 int r)
1395{
1396 return link_status[r - DP_LANE0_1_STATUS];
1397}
1398
a4fc5ed6 1399static uint8_t
93f62dad 1400intel_get_adjust_request_voltage(uint8_t adjust_request[2],
a4fc5ed6
KP		 1401 int lane)
1402{
a4fc5ed6
KP		 1403 int s = ((lane & 1) ?
1404 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1405 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
93f62dad 1406 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1407
1408 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1409}
1410
1411static uint8_t
93f62dad 1412intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
a4fc5ed6
KP		 1413 int lane)
1414{
a4fc5ed6
KP		 1415 int s = ((lane & 1) ?
1416 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1417 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
93f62dad 1418 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1419
1420 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1421}
1422
1423
1424#if 0
1425static char *voltage_names[] = {
1426 "0.4V", "0.6V", "0.8V", "1.2V"
1427};
1428static char *pre_emph_names[] = {
1429 "0dB", "3.5dB", "6dB", "9.5dB"
1430};
1431static char *link_train_names[] = {
1432 "pattern 1", "pattern 2", "idle", "off"
1433};
1434#endif
1435
1436/*
1437 * These are source-specific values; current Intel hardware supports
1438 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1439 */
a4fc5ed6
KP		 1440
1441static uint8_t
1a2eb460 1442intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1443{
1a2eb460
KP		 1444 struct drm_device *dev = intel_dp->base.base.dev;
1445
1446 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1447 return DP_TRAIN_VOLTAGE_SWING_800;
1448 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1449 return DP_TRAIN_VOLTAGE_SWING_1200;
1450 else
1451 return DP_TRAIN_VOLTAGE_SWING_800;
1452}
1453
1454static uint8_t
1455intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1456{
1457 struct drm_device *dev = intel_dp->base.base.dev;
1458
1459 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1460 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1461 case DP_TRAIN_VOLTAGE_SWING_400:
1462 return DP_TRAIN_PRE_EMPHASIS_6;
1463 case DP_TRAIN_VOLTAGE_SWING_600:
1464 case DP_TRAIN_VOLTAGE_SWING_800:
1465 return DP_TRAIN_PRE_EMPHASIS_3_5;
1466 default:
1467 return DP_TRAIN_PRE_EMPHASIS_0;
1468 }
1469 } else {
1470 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1471 case DP_TRAIN_VOLTAGE_SWING_400:
1472 return DP_TRAIN_PRE_EMPHASIS_6;
1473 case DP_TRAIN_VOLTAGE_SWING_600:
1474 return DP_TRAIN_PRE_EMPHASIS_6;
1475 case DP_TRAIN_VOLTAGE_SWING_800:
1476 return DP_TRAIN_PRE_EMPHASIS_3_5;
1477 case DP_TRAIN_VOLTAGE_SWING_1200:
1478 default:
1479 return DP_TRAIN_PRE_EMPHASIS_0;
1480 }
a4fc5ed6
KP		 1481 }
1482}
1483
1484static void
93f62dad 1485intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1486{
1487 uint8_t v = 0;
1488 uint8_t p = 0;
1489 int lane;
93f62dad 1490 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1a2eb460
KP		 1491 uint8_t voltage_max;
1492 uint8_t preemph_max;
a4fc5ed6 1493
33a34e4e 1494 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad
KP		 1495 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1496 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
a4fc5ed6
KP		 1497
1498 if (this_v > v)
1499 v = this_v;
1500 if (this_p > p)
1501 p = this_p;
1502 }
1503
1a2eb460 1504 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1505 if (v >= voltage_max)
1506 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1507
1a2eb460
KP		 1508 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1509 if (p >= preemph_max)
1510 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1511
1512 for (lane = 0; lane < 4; lane++)
33a34e4e 1513 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1514}
1515
1516static uint32_t
93f62dad 1517intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1518{
3cf2efb1 1519 uint32_t signal_levels = 0;
a4fc5ed6 1520
3cf2efb1 1521 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1522 case DP_TRAIN_VOLTAGE_SWING_400:
1523 default:
1524 signal_levels |= DP_VOLTAGE_0_4;
1525 break;
1526 case DP_TRAIN_VOLTAGE_SWING_600:
1527 signal_levels |= DP_VOLTAGE_0_6;
1528 break;
1529 case DP_TRAIN_VOLTAGE_SWING_800:
1530 signal_levels |= DP_VOLTAGE_0_8;
1531 break;
1532 case DP_TRAIN_VOLTAGE_SWING_1200:
1533 signal_levels |= DP_VOLTAGE_1_2;
1534 break;
1535 }
3cf2efb1 1536 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1537 case DP_TRAIN_PRE_EMPHASIS_0:
1538 default:
1539 signal_levels |= DP_PRE_EMPHASIS_0;
1540 break;
1541 case DP_TRAIN_PRE_EMPHASIS_3_5:
1542 signal_levels |= DP_PRE_EMPHASIS_3_5;
1543 break;
1544 case DP_TRAIN_PRE_EMPHASIS_6:
1545 signal_levels |= DP_PRE_EMPHASIS_6;
1546 break;
1547 case DP_TRAIN_PRE_EMPHASIS_9_5:
1548 signal_levels |= DP_PRE_EMPHASIS_9_5;
1549 break;
1550 }
1551 return signal_levels;
1552}
1553
e3421a18
ZW		 1554/* Gen6's DP voltage swing and pre-emphasis control */
1555static uint32_t
1556intel_gen6_edp_signal_levels(uint8_t train_set)
1557{
3c5a62b5
YL		 1558 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1559 DP_TRAIN_PRE_EMPHASIS_MASK);
1560 switch (signal_levels) {
e3421a18 1561 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1562 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1563 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1564 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1565 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1566 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1567 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1568 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1569 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1570 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1571 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1572 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1573 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1574 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1575 default:
3c5a62b5
YL		 1576 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1577 "0x%x\n", signal_levels);
1578 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1579 }
1580}
1581
1a2eb460
KP		 1582/* Gen7's DP voltage swing and pre-emphasis control */
1583static uint32_t
1584intel_gen7_edp_signal_levels(uint8_t train_set)
1585{
1586 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1587 DP_TRAIN_PRE_EMPHASIS_MASK);
1588 switch (signal_levels) {
1589 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1590 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1591 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1592 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1593 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1594 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1595
1596 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1597 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1598 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1599 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1600
1601 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1602 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1603 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1604 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1605
1606 default:
1607 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1608 "0x%x\n", signal_levels);
1609 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1610 }
1611}
1612
a4fc5ed6
KP		 1613static uint8_t
1614intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1615 int lane)
1616{
a4fc5ed6 1617 int s = (lane & 1) * 4;
93f62dad 1618 uint8_t l = link_status[lane>>1];
a4fc5ed6
KP		 1619
1620 return (l >> s) & 0xf;
1621}
1622
1623/* Check for clock recovery is done on all channels */
1624static bool
1625intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1626{
1627 int lane;
1628 uint8_t lane_status;
1629
1630 for (lane = 0; lane < lane_count; lane++) {
1631 lane_status = intel_get_lane_status(link_status, lane);
1632 if ((lane_status & DP_LANE_CR_DONE) == 0)
1633 return false;
1634 }
1635 return true;
1636}
1637
1638/* Check to see if channel eq is done on all channels */
1639#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1640 DP_LANE_CHANNEL_EQ_DONE|\
1641 DP_LANE_SYMBOL_LOCKED)
1642static bool
93f62dad 1643intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1644{
1645 uint8_t lane_align;
1646 uint8_t lane_status;
1647 int lane;
1648
93f62dad 1649 lane_align = intel_dp_link_status(link_status,
a4fc5ed6
KP		 1650 DP_LANE_ALIGN_STATUS_UPDATED);
1651 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1652 return false;
33a34e4e 1653 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad 1654 lane_status = intel_get_lane_status(link_status, lane);
a4fc5ed6
KP		 1655 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1656 return false;
1657 }
1658 return true;
1659}
1660
1661static bool
ea5b213a 1662intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1663 uint32_t dp_reg_value,
58e10eb9 1664 uint8_t dp_train_pat)
a4fc5ed6 1665{
4ef69c7a 1666 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1667 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6
KP		 1668 int ret;
1669
ea5b213a
CW		 1670 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1671 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1672
ea5b213a 1673 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1674 DP_TRAINING_PATTERN_SET,
1675 dp_train_pat);
1676
ea5b213a 1677 ret = intel_dp_aux_native_write(intel_dp,
58e10eb9 1678 DP_TRAINING_LANE0_SET,
b34f1f09
KP		 1679 intel_dp->train_set,
1680 intel_dp->lane_count);
1681 if (ret != intel_dp->lane_count)
a4fc5ed6
KP		 1682 return false;
1683
1684 return true;
1685}
1686
33a34e4e 1687/* Enable corresponding port and start training pattern 1 */
a4fc5ed6 1688static void
33a34e4e 1689intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1690{
4ef69c7a 1691 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1692 struct drm_i915_private *dev_priv = dev->dev_private;
58e10eb9 1693 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
a4fc5ed6
KP		 1694 int i;
1695 uint8_t voltage;
1696 bool clock_recovery = false;
cdb0e95b 1697 int voltage_tries, loop_tries;
e3421a18 1698 u32 reg;
ea5b213a 1699 uint32_t DP = intel_dp->DP;
a4fc5ed6 1700
e8519464
AJ		 1701 /*
1702 * On CPT we have to enable the port in training pattern 1, which
1703 * will happen below in intel_dp_set_link_train. Otherwise, enable
1704 * the port and wait for it to become active.
1705 */
1706 if (!HAS_PCH_CPT(dev)) {
1707 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1708 POSTING_READ(intel_dp->output_reg);
1709 intel_wait_for_vblank(dev, intel_crtc->pipe);
1710 }
a4fc5ed6 1711
3cf2efb1
CW		 1712 /* Write the link configuration data */
1713 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1714 intel_dp->link_configuration,
1715 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1716
1717 DP |= DP_PORT_EN;
1a2eb460
KP		 1718
1719 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
e3421a18
ZW		 1720 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1721 else
1722 DP &= ~DP_LINK_TRAIN_MASK;
33a34e4e 1723 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1724 voltage = 0xff;
cdb0e95b
KP		 1725 voltage_tries = 0;
1726 loop_tries = 0;
a4fc5ed6
KP		 1727 clock_recovery = false;
1728 for (;;) {
33a34e4e 1729 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1730 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1731 uint32_t signal_levels;
417e822d 1732
1a2eb460
KP		 1733
1734 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1735 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1736 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1737 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1738 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1739 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1740 } else {
93f62dad
KP		 1741 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1742 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
e3421a18
ZW		 1743 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1744 }
a4fc5ed6 1745
1a2eb460 1746 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
e3421a18
ZW		 1747 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1748 else
1749 reg = DP | DP_LINK_TRAIN_PAT_1;
1750
ea5b213a 1751 if (!intel_dp_set_link_train(intel_dp, reg,
81055854
AJ		 1752 DP_TRAINING_PATTERN_1 |
1753 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1754 break;
a4fc5ed6
KP		 1755 /* Set training pattern 1 */
1756
3cf2efb1 1757 udelay(100);
93f62dad
KP		 1758 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1759 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1760 break;
93f62dad 1761 }
a4fc5ed6 1762
93f62dad
KP		 1763 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1764 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1765 clock_recovery = true;
1766 break;
1767 }
1768
1769 /* Check to see if we've tried the max voltage */
1770 for (i = 0; i < intel_dp->lane_count; i++)
1771 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1772 break;
0d710688 1773 if (i == intel_dp->lane_count && voltage_tries == 5) {
cdb0e95b
KP		 1774 ++loop_tries;
1775 if (loop_tries == 5) {
1776 DRM_DEBUG_KMS("too many full retries, give up\n");
1777 break;
1778 }
1779 memset(intel_dp->train_set, 0, 4);
1780 voltage_tries = 0;
1781 continue;
1782 }
a4fc5ed6 1783
3cf2efb1
CW		 1784 /* Check to see if we've tried the same voltage 5 times */
1785 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
cdb0e95b
KP		 1786 ++voltage_tries;
1787 if (voltage_tries == 5) {
1788 DRM_DEBUG_KMS("too many voltage retries, give up\n");
a4fc5ed6 1789 break;
cdb0e95b 1790 }
3cf2efb1 1791 } else
cdb0e95b 1792 voltage_tries = 0;
3cf2efb1 1793 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1794
3cf2efb1 1795 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1796 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1797 }
1798
33a34e4e
JB		 1799 intel_dp->DP = DP;
1800}
1801
1802static void
1803intel_dp_complete_link_train(struct intel_dp *intel_dp)
1804{
4ef69c7a 1805 struct drm_device *dev = intel_dp->base.base.dev;
33a34e4e
JB		 1806 struct drm_i915_private *dev_priv = dev->dev_private;
1807 bool channel_eq = false;
37f80975 1808 int tries, cr_tries;
33a34e4e
JB		 1809 u32 reg;
1810 uint32_t DP = intel_dp->DP;
1811
a4fc5ed6
KP		 1812 /* channel equalization */
1813 tries = 0;
37f80975 1814 cr_tries = 0;
a4fc5ed6
KP		 1815 channel_eq = false;
1816 for (;;) {
33a34e4e 1817 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1818 uint32_t signal_levels;
93f62dad 1819 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1820
37f80975
JB		 1821 if (cr_tries > 5) {
1822 DRM_ERROR("failed to train DP, aborting\n");
1823 intel_dp_link_down(intel_dp);
1824 break;
1825 }
1826
1a2eb460
KP		 1827 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1828 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1829 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1830 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1831 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1832 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1833 } else {
93f62dad 1834 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1835 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1836 }
1837
1a2eb460 1838 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
e3421a18
ZW		 1839 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1840 else
1841 reg = DP | DP_LINK_TRAIN_PAT_2;
a4fc5ed6
KP		 1842
1843 /* channel eq pattern */
ea5b213a 1844 if (!intel_dp_set_link_train(intel_dp, reg,
81055854
AJ		 1845 DP_TRAINING_PATTERN_2 |
1846 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1847 break;
1848
3cf2efb1 1849 udelay(400);
93f62dad 1850 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1851 break;
a4fc5ed6 1852
37f80975 1853 /* Make sure clock is still ok */
93f62dad 1854 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1855 intel_dp_start_link_train(intel_dp);
1856 cr_tries++;
1857 continue;
1858 }
1859
93f62dad 1860 if (intel_channel_eq_ok(intel_dp, link_status)) {
3cf2efb1
CW		 1861 channel_eq = true;
1862 break;
1863 }
a4fc5ed6 1864
37f80975
JB		 1865 /* Try 5 times, then try clock recovery if that fails */
1866 if (tries > 5) {
1867 intel_dp_link_down(intel_dp);
1868 intel_dp_start_link_train(intel_dp);
1869 tries = 0;
1870 cr_tries++;
1871 continue;
1872 }
a4fc5ed6 1873
3cf2efb1 1874 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1875 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1876 ++tries;
869184a6 1877 }
3cf2efb1 1878
1a2eb460 1879 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
e3421a18
ZW		 1880 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1881 else
1882 reg = DP | DP_LINK_TRAIN_OFF;
1883
ea5b213a
CW		 1884 I915_WRITE(intel_dp->output_reg, reg);
1885 POSTING_READ(intel_dp->output_reg);
1886 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1887 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1888}
1889
1890static void
ea5b213a 1891intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1892{
4ef69c7a 1893 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1894 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1895 uint32_t DP = intel_dp->DP;
a4fc5ed6 1896
1b39d6f3
CW		 1897 if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1898 return;
1899
28c97730 1900 DRM_DEBUG_KMS("\n");
32f9d658 1901
cfcb0fc9 1902 if (is_edp(intel_dp)) {
32f9d658 1903 DP &= ~DP_PLL_ENABLE;
ea5b213a
CW		 1904 I915_WRITE(intel_dp->output_reg, DP);
1905 POSTING_READ(intel_dp->output_reg);
32f9d658
ZW		 1906 udelay(100);
1907 }
1908
1a2eb460 1909 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 1910 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 1911 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 1912 } else {
1913 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 1914 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 1915 }
fe255d00 1916 POSTING_READ(intel_dp->output_reg);
5eb08b69 1917
fe255d00 1918 msleep(17);
5eb08b69 1919
417e822d 1920 if (is_edp(intel_dp)) {
1a2eb460 1921 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
417e822d
KP		 1922 DP |= DP_LINK_TRAIN_OFF_CPT;
1923 else
1924 DP |= DP_LINK_TRAIN_OFF;
1925 }
5bddd17f 1926
493a7081 1927 if (HAS_PCH_IBX(dev) &&
1b39d6f3 1928 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
31acbcc4
CW		 1929 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1930
5bddd17f
EA		 1931 /* Hardware workaround: leaving our transcoder select
1932 * set to transcoder B while it's off will prevent the
1933 * corresponding HDMI output on transcoder A.
1934 *
1935 * Combine this with another hardware workaround:
1936 * transcoder select bit can only be cleared while the
1937 * port is enabled.
1938 */
1939 DP &= ~DP_PIPEB_SELECT;
1940 I915_WRITE(intel_dp->output_reg, DP);
1941
1942 /* Changes to enable or select take place the vblank
1943 * after being written.
1944 */
31acbcc4
CW		 1945 if (crtc == NULL) {
1946 /* We can arrive here never having been attached
1947 * to a CRTC, for instance, due to inheriting
1948 * random state from the BIOS.
1949 *
1950 * If the pipe is not running, play safe and
1951 * wait for the clocks to stabilise before
1952 * continuing.
1953 */
1954 POSTING_READ(intel_dp->output_reg);
1955 msleep(50);
1956 } else
1957 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 1958 }
1959
832afda6 1960 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 1961 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1962 POSTING_READ(intel_dp->output_reg);
f01eca2e 1963 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 1964}
1965
26d61aad
KP		 1966static bool
1967intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 1968{
92fd8fd1 1969 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
0206e353 1970 sizeof(intel_dp->dpcd)) &&
92fd8fd1 1971 (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
26d61aad 1972 return true;
92fd8fd1
KP		 1973 }
1974
26d61aad 1975 return false;
92fd8fd1
KP		 1976}
1977
0d198328
AJ		 1978static void
1979intel_dp_probe_oui(struct intel_dp *intel_dp)
1980{
1981 u8 buf[3];
1982
1983 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
1984 return;
1985
351cfc34
DV		 1986 ironlake_edp_panel_vdd_on(intel_dp);
1987
0d198328
AJ		 1988 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
1989 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
1990 buf[0], buf[1], buf[2]);
1991
1992 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
1993 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
1994 buf[0], buf[1], buf[2]);
351cfc34
DV		 1995
1996 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 1997}
1998
a60f0e38
JB		 1999static bool
2000intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2001{
2002 int ret;
2003
2004 ret = intel_dp_aux_native_read_retry(intel_dp,
2005 DP_DEVICE_SERVICE_IRQ_VECTOR,
2006 sink_irq_vector, 1);
2007 if (!ret)
2008 return false;
2009
2010 return true;
2011}
2012
2013static void
2014intel_dp_handle_test_request(struct intel_dp *intel_dp)
2015{
2016 /* NAK by default */
2017 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2018}
2019
a4fc5ed6
KP		 2020/*
2021 * According to DP spec
2022 * 5.1.2:
2023 * 1. Read DPCD
2024 * 2. Configure link according to Receiver Capabilities
2025 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2026 * 4. Check link status on receipt of hot-plug interrupt
2027 */
2028
2029static void
ea5b213a 2030intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2031{
a60f0e38 2032 u8 sink_irq_vector;
93f62dad 2033 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2034
d2b996ac
KP		 2035 if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
2036 return;
59cd09e1 2037
4ef69c7a 2038 if (!intel_dp->base.base.crtc)
a4fc5ed6
KP		 2039 return;
2040
92fd8fd1 2041 /* Try to read receiver status if the link appears to be up */
93f62dad 2042 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2043 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2044 return;
2045 }
2046
92fd8fd1 2047 /* Now read the DPCD to see if it's actually running */
26d61aad 2048 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2049 intel_dp_link_down(intel_dp);
2050 return;
2051 }
2052
a60f0e38
JB		 2053 /* Try to read the source of the interrupt */
2054 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2055 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2056 /* Clear interrupt source */
2057 intel_dp_aux_native_write_1(intel_dp,
2058 DP_DEVICE_SERVICE_IRQ_VECTOR,
2059 sink_irq_vector);
2060
2061 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2062 intel_dp_handle_test_request(intel_dp);
2063 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2064 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2065 }
2066
93f62dad 2067 if (!intel_channel_eq_ok(intel_dp, link_status)) {
92fd8fd1
KP		 2068 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2069 drm_get_encoder_name(&intel_dp->base.base));
33a34e4e
JB		 2070 intel_dp_start_link_train(intel_dp);
2071 intel_dp_complete_link_train(intel_dp);
2072 }
a4fc5ed6 2073}
a4fc5ed6 2074
71ba9000 2075static enum drm_connector_status
26d61aad 2076intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2077{
26d61aad
KP		 2078 if (intel_dp_get_dpcd(intel_dp))
2079 return connector_status_connected;
2080 return connector_status_disconnected;
71ba9000
AJ		 2081}
2082
5eb08b69 2083static enum drm_connector_status
a9756bb5 2084ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2085{
5eb08b69
ZW		 2086 enum drm_connector_status status;
2087
fe16d949
CW		 2088 /* Can't disconnect eDP, but you can close the lid... */
2089 if (is_edp(intel_dp)) {
2090 status = intel_panel_detect(intel_dp->base.base.dev);
2091 if (status == connector_status_unknown)
2092 status = connector_status_connected;
2093 return status;
2094 }
01cb9ea6 2095
26d61aad 2096 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2097}
2098
a4fc5ed6 2099static enum drm_connector_status
a9756bb5 2100g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2101{
4ef69c7a 2102 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2103 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 2104 uint32_t bit;
5eb08b69 2105
ea5b213a 2106 switch (intel_dp->output_reg) {
a4fc5ed6 2107 case DP_B:
10f76a38 2108 bit = DPB_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2109 break;
2110 case DP_C:
10f76a38 2111 bit = DPC_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2112 break;
2113 case DP_D:
10f76a38 2114 bit = DPD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2115 break;
2116 default:
2117 return connector_status_unknown;
2118 }
2119
10f76a38 2120 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2121 return connector_status_disconnected;
2122
26d61aad 2123 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2124}
2125
8c241fef
KP		 2126static struct edid *
2127intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2128{
2129 struct intel_dp *intel_dp = intel_attached_dp(connector);
2130 struct edid *edid;
d6f24d0f
JB		 2131 int size;
2132
2133 if (is_edp(intel_dp)) {
2134 if (!intel_dp->edid)
2135 return NULL;
2136
2137 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2138 edid = kmalloc(size, GFP_KERNEL);
2139 if (!edid)
2140 return NULL;
2141
2142 memcpy(edid, intel_dp->edid, size);
2143 return edid;
2144 }
8c241fef 2145
8c241fef 2146 edid = drm_get_edid(connector, adapter);
8c241fef
KP		 2147 return edid;
2148}
2149
2150static int
2151intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2152{
2153 struct intel_dp *intel_dp = intel_attached_dp(connector);
2154 int ret;
2155
d6f24d0f
JB		 2156 if (is_edp(intel_dp)) {
2157 drm_mode_connector_update_edid_property(connector,
2158 intel_dp->edid);
2159 ret = drm_add_edid_modes(connector, intel_dp->edid);
2160 drm_edid_to_eld(connector,
2161 intel_dp->edid);
2162 connector->display_info.raw_edid = NULL;
2163 return intel_dp->edid_mode_count;
2164 }
2165
8c241fef 2166 ret = intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2167 return ret;
2168}
2169
2170
a9756bb5
ZW		 2171/**
2172 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2173 *
2174 * \return true if DP port is connected.
2175 * \return false if DP port is disconnected.
2176 */
2177static enum drm_connector_status
2178intel_dp_detect(struct drm_connector *connector, bool force)
2179{
2180 struct intel_dp *intel_dp = intel_attached_dp(connector);
2181 struct drm_device *dev = intel_dp->base.base.dev;
2182 enum drm_connector_status status;
2183 struct edid *edid = NULL;
2184
2185 intel_dp->has_audio = false;
2186
2187 if (HAS_PCH_SPLIT(dev))
2188 status = ironlake_dp_detect(intel_dp);
2189 else
2190 status = g4x_dp_detect(intel_dp);
1b9be9d0 2191
ac66ae83
AJ		 2192 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2193 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2194 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2195 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1b9be9d0 2196
a9756bb5
ZW		 2197 if (status != connector_status_connected)
2198 return status;
2199
0d198328
AJ		 2200 intel_dp_probe_oui(intel_dp);
2201
c3e5f67b
DV		 2202 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2203 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2204 } else {
8c241fef 2205 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2206 if (edid) {
2207 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2208 connector->display_info.raw_edid = NULL;
2209 kfree(edid);
2210 }
a9756bb5
ZW		 2211 }
2212
2213 return connector_status_connected;
a4fc5ed6
KP		 2214}
2215
2216static int intel_dp_get_modes(struct drm_connector *connector)
2217{
df0e9248 2218 struct intel_dp *intel_dp = intel_attached_dp(connector);
4ef69c7a 2219 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 2220 struct drm_i915_private *dev_priv = dev->dev_private;
2221 int ret;
a4fc5ed6
KP		 2222
2223 /* We should parse the EDID data and find out if it has an audio sink
2224 */
2225
8c241fef 2226 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
b9efc480 2227 if (ret) {
d15456de 2228 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
b9efc480
ZY		 2229 struct drm_display_mode *newmode;
2230 list_for_each_entry(newmode, &connector->probed_modes,
2231 head) {
d15456de
KP		 2232 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2233 intel_dp->panel_fixed_mode =
b9efc480
ZY		 2234 drm_mode_duplicate(dev, newmode);
2235 break;
2236 }
2237 }
2238 }
32f9d658 2239 return ret;
b9efc480 2240 }
32f9d658
ZW		 2241
2242 /* if eDP has no EDID, try to use fixed panel mode from VBT */
4d926461 2243 if (is_edp(intel_dp)) {
47f0eb22 2244 /* initialize panel mode from VBT if available for eDP */
d15456de
KP		 2245 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2246 intel_dp->panel_fixed_mode =
47f0eb22 2247 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
d15456de
KP		 2248 if (intel_dp->panel_fixed_mode) {
2249 intel_dp->panel_fixed_mode->type |=
47f0eb22
KP		 2250 DRM_MODE_TYPE_PREFERRED;
2251 }
2252 }
d15456de 2253 if (intel_dp->panel_fixed_mode) {
32f9d658 2254 struct drm_display_mode *mode;
d15456de 2255 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
32f9d658
ZW		 2256 drm_mode_probed_add(connector, mode);
2257 return 1;
2258 }
2259 }
2260 return 0;
a4fc5ed6
KP		 2261}
2262
1aad7ac0
CW		 2263static bool
2264intel_dp_detect_audio(struct drm_connector *connector)
2265{
2266 struct intel_dp *intel_dp = intel_attached_dp(connector);
2267 struct edid *edid;
2268 bool has_audio = false;
2269
8c241fef 2270 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2271 if (edid) {
2272 has_audio = drm_detect_monitor_audio(edid);
2273
2274 connector->display_info.raw_edid = NULL;
2275 kfree(edid);
2276 }
2277
2278 return has_audio;
2279}
2280
f684960e
CW		 2281static int
2282intel_dp_set_property(struct drm_connector *connector,
2283 struct drm_property *property,
2284 uint64_t val)
2285{
e953fd7b 2286 struct drm_i915_private *dev_priv = connector->dev->dev_private;
f684960e
CW		 2287 struct intel_dp *intel_dp = intel_attached_dp(connector);
2288 int ret;
2289
2290 ret = drm_connector_property_set_value(connector, property, val);
2291 if (ret)
2292 return ret;
2293
3f43c48d 2294 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2295 int i = val;
2296 bool has_audio;
2297
2298 if (i == intel_dp->force_audio)
f684960e
CW		 2299 return 0;
2300
1aad7ac0 2301 intel_dp->force_audio = i;
f684960e 2302
c3e5f67b 2303 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2304 has_audio = intel_dp_detect_audio(connector);
2305 else
c3e5f67b 2306 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2307
2308 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2309 return 0;
2310
1aad7ac0 2311 intel_dp->has_audio = has_audio;
f684960e
CW		 2312 goto done;
2313 }
2314
e953fd7b
CW		 2315 if (property == dev_priv->broadcast_rgb_property) {
2316 if (val == !!intel_dp->color_range)
2317 return 0;
2318
2319 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2320 goto done;
2321 }
2322
f684960e
CW		 2323 return -EINVAL;
2324
2325done:
2326 if (intel_dp->base.base.crtc) {
2327 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2328 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2329 crtc->x, crtc->y,
2330 crtc->fb);
2331 }
2332
2333 return 0;
2334}
2335
a4fc5ed6 2336static void
0206e353 2337intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2338{
aaa6fd2a
MG		 2339 struct drm_device *dev = connector->dev;
2340
2341 if (intel_dpd_is_edp(dev))
2342 intel_panel_destroy_backlight(dev);
2343
a4fc5ed6
KP		 2344 drm_sysfs_connector_remove(connector);
2345 drm_connector_cleanup(connector);
55f78c43 2346 kfree(connector);
a4fc5ed6
KP		 2347}
2348
24d05927
DV		 2349static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2350{
2351 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2352
2353 i2c_del_adapter(&intel_dp->adapter);
2354 drm_encoder_cleanup(encoder);
bd943159 2355 if (is_edp(intel_dp)) {
d6f24d0f 2356 kfree(intel_dp->edid);
bd943159
KP		 2357 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2358 ironlake_panel_vdd_off_sync(intel_dp);
2359 }
24d05927
DV		 2360 kfree(intel_dp);
2361}
2362
a4fc5ed6
KP		 2363static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2364 .dpms = intel_dp_dpms,
2365 .mode_fixup = intel_dp_mode_fixup,
d240f20f 2366 .prepare = intel_dp_prepare,
a4fc5ed6 2367 .mode_set = intel_dp_mode_set,
d240f20f 2368 .commit = intel_dp_commit,
a4fc5ed6
KP		 2369};
2370
2371static const struct drm_connector_funcs intel_dp_connector_funcs = {
2372 .dpms = drm_helper_connector_dpms,
a4fc5ed6
KP		 2373 .detect = intel_dp_detect,
2374 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2375 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2376 .destroy = intel_dp_destroy,
2377};
2378
2379static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2380 .get_modes = intel_dp_get_modes,
2381 .mode_valid = intel_dp_mode_valid,
df0e9248 2382 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2383};
2384
a4fc5ed6 2385static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2386 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2387};
2388
995b6762 2389static void
21d40d37 2390intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2391{
ea5b213a 2392 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 2393
885a5014 2394 intel_dp_check_link_status(intel_dp);
c8110e52 2395}
6207937d 2396
e3421a18
ZW		 2397/* Return which DP Port should be selected for Transcoder DP control */
2398int
0206e353 2399intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2400{
2401 struct drm_device *dev = crtc->dev;
6c2b7c12 2402 struct intel_encoder *encoder;
e3421a18 2403
6c2b7c12
DV		 2404 for_each_encoder_on_crtc(dev, crtc, encoder) {
2405 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
e3421a18 2406
417e822d
KP		 2407 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2408 intel_dp->base.type == INTEL_OUTPUT_EDP)
ea5b213a 2409 return intel_dp->output_reg;
e3421a18 2410 }
ea5b213a 2411
e3421a18
ZW		 2412 return -1;
2413}
2414
36e83a18 2415/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2416bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2417{
2418 struct drm_i915_private *dev_priv = dev->dev_private;
2419 struct child_device_config *p_child;
2420 int i;
2421
2422 if (!dev_priv->child_dev_num)
2423 return false;
2424
2425 for (i = 0; i < dev_priv->child_dev_num; i++) {
2426 p_child = dev_priv->child_dev + i;
2427
2428 if (p_child->dvo_port == PORT_IDPD &&
2429 p_child->device_type == DEVICE_TYPE_eDP)
2430 return true;
2431 }
2432 return false;
2433}
2434
f684960e
CW		 2435static void
2436intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2437{
3f43c48d 2438 intel_attach_force_audio_property(connector);
e953fd7b 2439 intel_attach_broadcast_rgb_property(connector);
f684960e
CW		 2440}
2441
a4fc5ed6
KP		 2442void
2443intel_dp_init(struct drm_device *dev, int output_reg)
2444{
2445 struct drm_i915_private *dev_priv = dev->dev_private;
2446 struct drm_connector *connector;
ea5b213a 2447 struct intel_dp *intel_dp;
21d40d37 2448 struct intel_encoder *intel_encoder;
55f78c43 2449 struct intel_connector *intel_connector;
5eb08b69 2450 const char *name = NULL;
b329530c 2451 int type;
a4fc5ed6 2452
ea5b213a
CW		 2453 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2454 if (!intel_dp)
a4fc5ed6
KP		 2455 return;
2456
3d3dc149 2457 intel_dp->output_reg = output_reg;
d2b996ac 2458 intel_dp->dpms_mode = -1;
3d3dc149 2459
55f78c43
ZW		 2460 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2461 if (!intel_connector) {
ea5b213a 2462 kfree(intel_dp);
55f78c43
ZW		 2463 return;
2464 }
ea5b213a 2465 intel_encoder = &intel_dp->base;
55f78c43 2466
ea5b213a 2467 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 2468 if (intel_dpd_is_edp(dev))
ea5b213a 2469 intel_dp->is_pch_edp = true;
b329530c 2470
cfcb0fc9 2471 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2472 type = DRM_MODE_CONNECTOR_eDP;
2473 intel_encoder->type = INTEL_OUTPUT_EDP;
2474 } else {
2475 type = DRM_MODE_CONNECTOR_DisplayPort;
2476 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2477 }
2478
55f78c43 2479 connector = &intel_connector->base;
b329530c 2480 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2481 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2482
eb1f8e4f
DA		 2483 connector->polled = DRM_CONNECTOR_POLL_HPD;
2484
652af9d7 2485 if (output_reg == DP_B || output_reg == PCH_DP_B)
21d40d37 2486 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
652af9d7 2487 else if (output_reg == DP_C || output_reg == PCH_DP_C)
21d40d37 2488 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
652af9d7 2489 else if (output_reg == DP_D || output_reg == PCH_DP_D)
21d40d37 2490 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
f8aed700 2491
bd943159 2492 if (is_edp(intel_dp)) {
21d40d37 2493 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
bd943159
KP		 2494 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2495 ironlake_panel_vdd_work);
2496 }
6251ec0a 2497
27f8227b 2498 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
ee7b9f93 2499
a4fc5ed6
KP		 2500 connector->interlace_allowed = true;
2501 connector->doublescan_allowed = 0;
2502
4ef69c7a 2503 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
a4fc5ed6 2504 DRM_MODE_ENCODER_TMDS);
4ef69c7a 2505 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
a4fc5ed6 2506
df0e9248 2507 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2508 drm_sysfs_connector_add(connector);
2509
2510 /* Set up the DDC bus. */
5eb08b69 2511 switch (output_reg) {
32f9d658
ZW		 2512 case DP_A:
2513 name = "DPDDC-A";
2514 break;
5eb08b69
ZW		 2515 case DP_B:
2516 case PCH_DP_B:
b01f2c3a 2517 dev_priv->hotplug_supported_mask |=
78d56d78 2518 DPB_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 2519 name = "DPDDC-B";
2520 break;
2521 case DP_C:
2522 case PCH_DP_C:
b01f2c3a 2523 dev_priv->hotplug_supported_mask |=
78d56d78 2524 DPC_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 2525 name = "DPDDC-C";
2526 break;
2527 case DP_D:
2528 case PCH_DP_D:
b01f2c3a 2529 dev_priv->hotplug_supported_mask |=
78d56d78 2530 DPD_HOTPLUG_INT_STATUS;
5eb08b69
ZW		 2531 name = "DPDDC-D";
2532 break;
2533 }
2534
89667383
JB		 2535 /* Cache some DPCD data in the eDP case */
2536 if (is_edp(intel_dp)) {
f01eca2e
KP		 2537 struct edp_power_seq cur, vbt;
2538 u32 pp_on, pp_off, pp_div;
5d613501
JB		 2539
2540 pp_on = I915_READ(PCH_PP_ON_DELAYS);
f01eca2e 2541 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
5d613501 2542 pp_div = I915_READ(PCH_PP_DIVISOR);
89667383 2543
bfa3384a
JB		 2544 if (!pp_on || !pp_off || !pp_div) {
2545 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2546 intel_dp_encoder_destroy(&intel_dp->base.base);
2547 intel_dp_destroy(&intel_connector->base);
2548 return;
2549 }
2550
f01eca2e
KP		 2551 /* Pull timing values out of registers */
2552 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2553 PANEL_POWER_UP_DELAY_SHIFT;
2554
2555 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2556 PANEL_LIGHT_ON_DELAY_SHIFT;
f2e8b18a 2557
f01eca2e
KP		 2558 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2559 PANEL_LIGHT_OFF_DELAY_SHIFT;
2560
2561 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2562 PANEL_POWER_DOWN_DELAY_SHIFT;
2563
2564 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2565 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2566
2567 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2568 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2569
2570 vbt = dev_priv->edp.pps;
2571
2572 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2573 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2574
2575#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2576
2577 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2578 intel_dp->backlight_on_delay = get_delay(t8);
2579 intel_dp->backlight_off_delay = get_delay(t9);
2580 intel_dp->panel_power_down_delay = get_delay(t10);
2581 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2582
2583 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2584 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2585 intel_dp->panel_power_cycle_delay);
2586
2587 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2588 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
c1f05264
DA		 2589 }
2590
2591 intel_dp_i2c_init(intel_dp, intel_connector, name);
2592
2593 if (is_edp(intel_dp)) {
2594 bool ret;
2595 struct edid *edid;
5d613501
JB		 2596
2597 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2598 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2599 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2600
59f3e272 2601 if (ret) {
7183dc29
JB		 2602 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2603 dev_priv->no_aux_handshake =
2604 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2605 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2606 } else {
3d3dc149 2607 /* if this fails, presume the device is a ghost */
48898b03 2608 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3d3dc149 2609 intel_dp_encoder_destroy(&intel_dp->base.base);
48898b03 2610 intel_dp_destroy(&intel_connector->base);
3d3dc149 2611 return;
89667383 2612 }
89667383 2613
d6f24d0f
JB		 2614 ironlake_edp_panel_vdd_on(intel_dp);
2615 edid = drm_get_edid(connector, &intel_dp->adapter);
2616 if (edid) {
2617 drm_mode_connector_update_edid_property(connector,
2618 edid);
2619 intel_dp->edid_mode_count =
2620 drm_add_edid_modes(connector, edid);
2621 drm_edid_to_eld(connector, edid);
2622 intel_dp->edid = edid;
2623 }
2624 ironlake_edp_panel_vdd_off(intel_dp, false);
2625 }
552fb0b7 2626
21d40d37 2627 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 2628
4d926461 2629 if (is_edp(intel_dp)) {
aaa6fd2a
MG		 2630 dev_priv->int_edp_connector = connector;
2631 intel_panel_setup_backlight(dev);
32f9d658
ZW		 2632 }
2633
f684960e
CW		 2634 intel_dp_add_properties(intel_dp, connector);
2635
a4fc5ed6
KP		 2636 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2637 * 0xd. Failure to do so will result in spurious interrupts being
2638 * generated on the port when a cable is not attached.
2639 */
2640 if (IS_G4X(dev) && !IS_GM45(dev)) {
2641 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2642 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2643 }
2644}
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