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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
01527b31 CT |
31 | #include <linux/notifier.h> |
32 | #include <linux/reboot.h> | |
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_crtc_helper.h> | |
37 | #include <drm/drm_edid.h> | |
a4fc5ed6 | 38 | #include "intel_drv.h" |
760285e7 | 39 | #include <drm/i915_drm.h> |
a4fc5ed6 | 40 | #include "i915_drv.h" |
a4fc5ed6 | 41 | |
a4fc5ed6 KP |
42 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
43 | ||
559be30c TP |
44 | /* Compliance test status bits */ |
45 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 | |
46 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
47 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
48 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
49 | ||
9dd4ffdf | 50 | struct dp_link_dpll { |
840b32b7 | 51 | int clock; |
9dd4ffdf CML |
52 | struct dpll dpll; |
53 | }; | |
54 | ||
55 | static const struct dp_link_dpll gen4_dpll[] = { | |
840b32b7 | 56 | { 162000, |
9dd4ffdf | 57 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
840b32b7 | 58 | { 270000, |
9dd4ffdf CML |
59 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
60 | }; | |
61 | ||
62 | static const struct dp_link_dpll pch_dpll[] = { | |
840b32b7 | 63 | { 162000, |
9dd4ffdf | 64 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
840b32b7 | 65 | { 270000, |
9dd4ffdf CML |
66 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
67 | }; | |
68 | ||
65ce4bf5 | 69 | static const struct dp_link_dpll vlv_dpll[] = { |
840b32b7 | 70 | { 162000, |
58f6e632 | 71 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
840b32b7 | 72 | { 270000, |
65ce4bf5 CML |
73 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
74 | }; | |
75 | ||
ef9348c8 CML |
76 | /* |
77 | * CHV supports eDP 1.4 that have more link rates. | |
78 | * Below only provides the fixed rate but exclude variable rate. | |
79 | */ | |
80 | static const struct dp_link_dpll chv_dpll[] = { | |
81 | /* | |
82 | * CHV requires to program fractional division for m2. | |
83 | * m2 is stored in fixed point format using formula below | |
84 | * (m2_int << 22) | m2_fraction | |
85 | */ | |
840b32b7 | 86 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
ef9348c8 | 87 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
840b32b7 | 88 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 | 89 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
840b32b7 | 90 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 CML |
91 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
92 | }; | |
637a9c63 | 93 | |
64987fc5 SJ |
94 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
95 | 324000, 432000, 540000 }; | |
637a9c63 | 96 | static const int skl_rates[] = { 162000, 216000, 270000, |
f4896f15 VS |
97 | 324000, 432000, 540000 }; |
98 | static const int default_rates[] = { 162000, 270000, 540000 }; | |
ef9348c8 | 99 | |
cfcb0fc9 JB |
100 | /** |
101 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) | |
102 | * @intel_dp: DP struct | |
103 | * | |
104 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
105 | * will return true, and false otherwise. | |
106 | */ | |
107 | static bool is_edp(struct intel_dp *intel_dp) | |
108 | { | |
da63a9f2 PZ |
109 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
110 | ||
111 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
112 | } |
113 | ||
68b4d824 | 114 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
cfcb0fc9 | 115 | { |
68b4d824 ID |
116 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
117 | ||
118 | return intel_dig_port->base.base.dev; | |
cfcb0fc9 JB |
119 | } |
120 | ||
df0e9248 CW |
121 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
122 | { | |
fa90ecef | 123 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
124 | } |
125 | ||
ea5b213a | 126 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
1e0560e0 | 127 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 | 128 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
093e3f13 | 129 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
a8c3344e VS |
130 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
131 | enum pipe pipe); | |
f21a2198 | 132 | static void intel_dp_unset_edid(struct intel_dp *intel_dp); |
a4fc5ed6 | 133 | |
ed4e9c1d VS |
134 | static int |
135 | intel_dp_max_link_bw(struct intel_dp *intel_dp) | |
a4fc5ed6 | 136 | { |
7183dc29 | 137 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
a4fc5ed6 KP |
138 | |
139 | switch (max_link_bw) { | |
140 | case DP_LINK_BW_1_62: | |
141 | case DP_LINK_BW_2_7: | |
1db10e28 | 142 | case DP_LINK_BW_5_4: |
d4eead50 | 143 | break; |
a4fc5ed6 | 144 | default: |
d4eead50 ID |
145 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
146 | max_link_bw); | |
a4fc5ed6 KP |
147 | max_link_bw = DP_LINK_BW_1_62; |
148 | break; | |
149 | } | |
150 | return max_link_bw; | |
151 | } | |
152 | ||
eeb6324d PZ |
153 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) |
154 | { | |
155 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
eeb6324d PZ |
156 | u8 source_max, sink_max; |
157 | ||
ccb1a831 | 158 | source_max = intel_dig_port->max_lanes; |
eeb6324d PZ |
159 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); |
160 | ||
161 | return min(source_max, sink_max); | |
162 | } | |
163 | ||
cd9dde44 AJ |
164 | /* |
165 | * The units on the numbers in the next two are... bizarre. Examples will | |
166 | * make it clearer; this one parallels an example in the eDP spec. | |
167 | * | |
168 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: | |
169 | * | |
170 | * 270000 * 1 * 8 / 10 == 216000 | |
171 | * | |
172 | * The actual data capacity of that configuration is 2.16Gbit/s, so the | |
173 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - | |
174 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be | |
175 | * 119000. At 18bpp that's 2142000 kilobits per second. | |
176 | * | |
177 | * Thus the strange-looking division by 10 in intel_dp_link_required, to | |
178 | * get the result in decakilobits instead of kilobits. | |
179 | */ | |
180 | ||
a4fc5ed6 | 181 | static int |
c898261c | 182 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 183 | { |
cd9dde44 | 184 | return (pixel_clock * bpp + 9) / 10; |
a4fc5ed6 KP |
185 | } |
186 | ||
fe27d53e DA |
187 | static int |
188 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) | |
189 | { | |
190 | return (max_link_clock * max_lanes * 8) / 10; | |
191 | } | |
192 | ||
c19de8eb | 193 | static enum drm_mode_status |
a4fc5ed6 KP |
194 | intel_dp_mode_valid(struct drm_connector *connector, |
195 | struct drm_display_mode *mode) | |
196 | { | |
df0e9248 | 197 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e JN |
198 | struct intel_connector *intel_connector = to_intel_connector(connector); |
199 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
36008365 DV |
200 | int target_clock = mode->clock; |
201 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
799487f5 | 202 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
a4fc5ed6 | 203 | |
dd06f90e JN |
204 | if (is_edp(intel_dp) && fixed_mode) { |
205 | if (mode->hdisplay > fixed_mode->hdisplay) | |
7de56f43 ZY |
206 | return MODE_PANEL; |
207 | ||
dd06f90e | 208 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 209 | return MODE_PANEL; |
03afc4a2 DV |
210 | |
211 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
212 | } |
213 | ||
50fec21a | 214 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
eeb6324d | 215 | max_lanes = intel_dp_max_lane_count(intel_dp); |
36008365 DV |
216 | |
217 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
218 | mode_rate = intel_dp_link_required(target_clock, 18); | |
219 | ||
799487f5 | 220 | if (mode_rate > max_rate || target_clock > max_dotclk) |
c4867936 | 221 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
222 | |
223 | if (mode->clock < 10000) | |
224 | return MODE_CLOCK_LOW; | |
225 | ||
0af78a2b DV |
226 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
227 | return MODE_H_ILLEGAL; | |
228 | ||
a4fc5ed6 KP |
229 | return MODE_OK; |
230 | } | |
231 | ||
a4f1289e | 232 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
a4fc5ed6 KP |
233 | { |
234 | int i; | |
235 | uint32_t v = 0; | |
236 | ||
237 | if (src_bytes > 4) | |
238 | src_bytes = 4; | |
239 | for (i = 0; i < src_bytes; i++) | |
240 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
241 | return v; | |
242 | } | |
243 | ||
c2af70e2 | 244 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
a4fc5ed6 KP |
245 | { |
246 | int i; | |
247 | if (dst_bytes > 4) | |
248 | dst_bytes = 4; | |
249 | for (i = 0; i < dst_bytes; i++) | |
250 | dst[i] = src >> ((3-i) * 8); | |
251 | } | |
252 | ||
bf13e81b JN |
253 | static void |
254 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
36b5f425 | 255 | struct intel_dp *intel_dp); |
bf13e81b JN |
256 | static void |
257 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
36b5f425 | 258 | struct intel_dp *intel_dp); |
335f752b ID |
259 | static void |
260 | intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp); | |
bf13e81b | 261 | |
773538e8 VS |
262 | static void pps_lock(struct intel_dp *intel_dp) |
263 | { | |
264 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
265 | struct intel_encoder *encoder = &intel_dig_port->base; | |
266 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 267 | struct drm_i915_private *dev_priv = to_i915(dev); |
773538e8 VS |
268 | enum intel_display_power_domain power_domain; |
269 | ||
270 | /* | |
271 | * See vlv_power_sequencer_reset() why we need | |
272 | * a power domain reference here. | |
273 | */ | |
25f78f58 | 274 | power_domain = intel_display_port_aux_power_domain(encoder); |
773538e8 VS |
275 | intel_display_power_get(dev_priv, power_domain); |
276 | ||
277 | mutex_lock(&dev_priv->pps_mutex); | |
278 | } | |
279 | ||
280 | static void pps_unlock(struct intel_dp *intel_dp) | |
281 | { | |
282 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
283 | struct intel_encoder *encoder = &intel_dig_port->base; | |
284 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 285 | struct drm_i915_private *dev_priv = to_i915(dev); |
773538e8 VS |
286 | enum intel_display_power_domain power_domain; |
287 | ||
288 | mutex_unlock(&dev_priv->pps_mutex); | |
289 | ||
25f78f58 | 290 | power_domain = intel_display_port_aux_power_domain(encoder); |
773538e8 VS |
291 | intel_display_power_put(dev_priv, power_domain); |
292 | } | |
293 | ||
961a0db0 VS |
294 | static void |
295 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) | |
296 | { | |
297 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
298 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 299 | struct drm_i915_private *dev_priv = to_i915(dev); |
961a0db0 | 300 | enum pipe pipe = intel_dp->pps_pipe; |
0047eedc VS |
301 | bool pll_enabled, release_cl_override = false; |
302 | enum dpio_phy phy = DPIO_PHY(pipe); | |
303 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); | |
961a0db0 VS |
304 | uint32_t DP; |
305 | ||
306 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, | |
307 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", | |
308 | pipe_name(pipe), port_name(intel_dig_port->port))) | |
309 | return; | |
310 | ||
311 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", | |
312 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
313 | ||
314 | /* Preserve the BIOS-computed detected bit. This is | |
315 | * supposed to be read-only. | |
316 | */ | |
317 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
318 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
319 | DP |= DP_PORT_WIDTH(1); | |
320 | DP |= DP_LINK_TRAIN_PAT_1; | |
321 | ||
322 | if (IS_CHERRYVIEW(dev)) | |
323 | DP |= DP_PIPE_SELECT_CHV(pipe); | |
324 | else if (pipe == PIPE_B) | |
325 | DP |= DP_PIPEB_SELECT; | |
326 | ||
d288f65f VS |
327 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
328 | ||
329 | /* | |
330 | * The DPLL for the pipe must be enabled for this to work. | |
331 | * So enable temporarily it if it's not already enabled. | |
332 | */ | |
0047eedc VS |
333 | if (!pll_enabled) { |
334 | release_cl_override = IS_CHERRYVIEW(dev) && | |
335 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); | |
336 | ||
3f36b937 TU |
337 | if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ? |
338 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { | |
339 | DRM_ERROR("Failed to force on pll for pipe %c!\n", | |
340 | pipe_name(pipe)); | |
341 | return; | |
342 | } | |
0047eedc | 343 | } |
d288f65f | 344 | |
961a0db0 VS |
345 | /* |
346 | * Similar magic as in intel_dp_enable_port(). | |
347 | * We _must_ do this port enable + disable trick | |
348 | * to make this power seqeuencer lock onto the port. | |
349 | * Otherwise even VDD force bit won't work. | |
350 | */ | |
351 | I915_WRITE(intel_dp->output_reg, DP); | |
352 | POSTING_READ(intel_dp->output_reg); | |
353 | ||
354 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); | |
355 | POSTING_READ(intel_dp->output_reg); | |
356 | ||
357 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); | |
358 | POSTING_READ(intel_dp->output_reg); | |
d288f65f | 359 | |
0047eedc | 360 | if (!pll_enabled) { |
d288f65f | 361 | vlv_force_pll_off(dev, pipe); |
0047eedc VS |
362 | |
363 | if (release_cl_override) | |
364 | chv_phy_powergate_ch(dev_priv, phy, ch, false); | |
365 | } | |
961a0db0 VS |
366 | } |
367 | ||
bf13e81b JN |
368 | static enum pipe |
369 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
370 | { | |
371 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bf13e81b | 372 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 373 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 VS |
374 | struct intel_encoder *encoder; |
375 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); | |
a8c3344e | 376 | enum pipe pipe; |
bf13e81b | 377 | |
e39b999a | 378 | lockdep_assert_held(&dev_priv->pps_mutex); |
bf13e81b | 379 | |
a8c3344e VS |
380 | /* We should never land here with regular DP ports */ |
381 | WARN_ON(!is_edp(intel_dp)); | |
382 | ||
a4a5d2f8 VS |
383 | if (intel_dp->pps_pipe != INVALID_PIPE) |
384 | return intel_dp->pps_pipe; | |
385 | ||
386 | /* | |
387 | * We don't have power sequencer currently. | |
388 | * Pick one that's not used by other ports. | |
389 | */ | |
19c8054c | 390 | for_each_intel_encoder(dev, encoder) { |
a4a5d2f8 VS |
391 | struct intel_dp *tmp; |
392 | ||
393 | if (encoder->type != INTEL_OUTPUT_EDP) | |
394 | continue; | |
395 | ||
396 | tmp = enc_to_intel_dp(&encoder->base); | |
397 | ||
398 | if (tmp->pps_pipe != INVALID_PIPE) | |
399 | pipes &= ~(1 << tmp->pps_pipe); | |
400 | } | |
401 | ||
402 | /* | |
403 | * Didn't find one. This should not happen since there | |
404 | * are two power sequencers and up to two eDP ports. | |
405 | */ | |
406 | if (WARN_ON(pipes == 0)) | |
a8c3344e VS |
407 | pipe = PIPE_A; |
408 | else | |
409 | pipe = ffs(pipes) - 1; | |
a4a5d2f8 | 410 | |
a8c3344e VS |
411 | vlv_steal_power_sequencer(dev, pipe); |
412 | intel_dp->pps_pipe = pipe; | |
a4a5d2f8 VS |
413 | |
414 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", | |
415 | pipe_name(intel_dp->pps_pipe), | |
416 | port_name(intel_dig_port->port)); | |
417 | ||
418 | /* init power sequencer on this pipe and port */ | |
36b5f425 VS |
419 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
420 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
a4a5d2f8 | 421 | |
961a0db0 VS |
422 | /* |
423 | * Even vdd force doesn't work until we've made | |
424 | * the power sequencer lock in on the port. | |
425 | */ | |
426 | vlv_power_sequencer_kick(intel_dp); | |
a4a5d2f8 VS |
427 | |
428 | return intel_dp->pps_pipe; | |
429 | } | |
430 | ||
78597996 ID |
431 | static int |
432 | bxt_power_sequencer_idx(struct intel_dp *intel_dp) | |
433 | { | |
434 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
435 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 436 | struct drm_i915_private *dev_priv = to_i915(dev); |
78597996 ID |
437 | |
438 | lockdep_assert_held(&dev_priv->pps_mutex); | |
439 | ||
440 | /* We should never land here with regular DP ports */ | |
441 | WARN_ON(!is_edp(intel_dp)); | |
442 | ||
443 | /* | |
444 | * TODO: BXT has 2 PPS instances. The correct port->PPS instance | |
445 | * mapping needs to be retrieved from VBT, for now just hard-code to | |
446 | * use instance #0 always. | |
447 | */ | |
448 | if (!intel_dp->pps_reset) | |
449 | return 0; | |
450 | ||
451 | intel_dp->pps_reset = false; | |
452 | ||
453 | /* | |
454 | * Only the HW needs to be reprogrammed, the SW state is fixed and | |
455 | * has been setup during connector init. | |
456 | */ | |
457 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
458 | ||
459 | return 0; | |
460 | } | |
461 | ||
6491ab27 VS |
462 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
463 | enum pipe pipe); | |
464 | ||
465 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, | |
466 | enum pipe pipe) | |
467 | { | |
44cb734c | 468 | return I915_READ(PP_STATUS(pipe)) & PP_ON; |
6491ab27 VS |
469 | } |
470 | ||
471 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, | |
472 | enum pipe pipe) | |
473 | { | |
44cb734c | 474 | return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
6491ab27 VS |
475 | } |
476 | ||
477 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, | |
478 | enum pipe pipe) | |
479 | { | |
480 | return true; | |
481 | } | |
bf13e81b | 482 | |
a4a5d2f8 | 483 | static enum pipe |
6491ab27 VS |
484 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
485 | enum port port, | |
486 | vlv_pipe_check pipe_check) | |
a4a5d2f8 VS |
487 | { |
488 | enum pipe pipe; | |
bf13e81b | 489 | |
bf13e81b | 490 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
44cb734c | 491 | u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) & |
bf13e81b | 492 | PANEL_PORT_SELECT_MASK; |
a4a5d2f8 VS |
493 | |
494 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) | |
495 | continue; | |
496 | ||
6491ab27 VS |
497 | if (!pipe_check(dev_priv, pipe)) |
498 | continue; | |
499 | ||
a4a5d2f8 | 500 | return pipe; |
bf13e81b JN |
501 | } |
502 | ||
a4a5d2f8 VS |
503 | return INVALID_PIPE; |
504 | } | |
505 | ||
506 | static void | |
507 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) | |
508 | { | |
509 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
510 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 511 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 VS |
512 | enum port port = intel_dig_port->port; |
513 | ||
514 | lockdep_assert_held(&dev_priv->pps_mutex); | |
515 | ||
516 | /* try to find a pipe with this port selected */ | |
6491ab27 VS |
517 | /* first pick one where the panel is on */ |
518 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
519 | vlv_pipe_has_pp_on); | |
520 | /* didn't find one? pick one where vdd is on */ | |
521 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
522 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
523 | vlv_pipe_has_vdd_on); | |
524 | /* didn't find one? pick one with just the correct port */ | |
525 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
526 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
527 | vlv_pipe_any); | |
a4a5d2f8 VS |
528 | |
529 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ | |
530 | if (intel_dp->pps_pipe == INVALID_PIPE) { | |
531 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", | |
532 | port_name(port)); | |
533 | return; | |
bf13e81b JN |
534 | } |
535 | ||
a4a5d2f8 VS |
536 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
537 | port_name(port), pipe_name(intel_dp->pps_pipe)); | |
538 | ||
36b5f425 VS |
539 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
540 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
bf13e81b JN |
541 | } |
542 | ||
78597996 | 543 | void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) |
773538e8 | 544 | { |
91c8a326 | 545 | struct drm_device *dev = &dev_priv->drm; |
773538e8 VS |
546 | struct intel_encoder *encoder; |
547 | ||
78597996 ID |
548 | if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
549 | !IS_BROXTON(dev))) | |
773538e8 VS |
550 | return; |
551 | ||
552 | /* | |
553 | * We can't grab pps_mutex here due to deadlock with power_domain | |
554 | * mutex when power_domain functions are called while holding pps_mutex. | |
555 | * That also means that in order to use pps_pipe the code needs to | |
556 | * hold both a power domain reference and pps_mutex, and the power domain | |
557 | * reference get/put must be done while _not_ holding pps_mutex. | |
558 | * pps_{lock,unlock}() do these steps in the correct order, so one | |
559 | * should use them always. | |
560 | */ | |
561 | ||
19c8054c | 562 | for_each_intel_encoder(dev, encoder) { |
773538e8 VS |
563 | struct intel_dp *intel_dp; |
564 | ||
565 | if (encoder->type != INTEL_OUTPUT_EDP) | |
566 | continue; | |
567 | ||
568 | intel_dp = enc_to_intel_dp(&encoder->base); | |
78597996 ID |
569 | if (IS_BROXTON(dev)) |
570 | intel_dp->pps_reset = true; | |
571 | else | |
572 | intel_dp->pps_pipe = INVALID_PIPE; | |
773538e8 | 573 | } |
bf13e81b JN |
574 | } |
575 | ||
8e8232d5 ID |
576 | struct pps_registers { |
577 | i915_reg_t pp_ctrl; | |
578 | i915_reg_t pp_stat; | |
579 | i915_reg_t pp_on; | |
580 | i915_reg_t pp_off; | |
581 | i915_reg_t pp_div; | |
582 | }; | |
583 | ||
584 | static void intel_pps_get_registers(struct drm_i915_private *dev_priv, | |
585 | struct intel_dp *intel_dp, | |
586 | struct pps_registers *regs) | |
587 | { | |
44cb734c ID |
588 | int pps_idx = 0; |
589 | ||
8e8232d5 ID |
590 | memset(regs, 0, sizeof(*regs)); |
591 | ||
44cb734c ID |
592 | if (IS_BROXTON(dev_priv)) |
593 | pps_idx = bxt_power_sequencer_idx(intel_dp); | |
594 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
595 | pps_idx = vlv_power_sequencer_pipe(intel_dp); | |
8e8232d5 | 596 | |
44cb734c ID |
597 | regs->pp_ctrl = PP_CONTROL(pps_idx); |
598 | regs->pp_stat = PP_STATUS(pps_idx); | |
599 | regs->pp_on = PP_ON_DELAYS(pps_idx); | |
600 | regs->pp_off = PP_OFF_DELAYS(pps_idx); | |
601 | if (!IS_BROXTON(dev_priv)) | |
602 | regs->pp_div = PP_DIVISOR(pps_idx); | |
8e8232d5 ID |
603 | } |
604 | ||
f0f59a00 VS |
605 | static i915_reg_t |
606 | _pp_ctrl_reg(struct intel_dp *intel_dp) | |
bf13e81b | 607 | { |
8e8232d5 | 608 | struct pps_registers regs; |
bf13e81b | 609 | |
8e8232d5 ID |
610 | intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, |
611 | ®s); | |
612 | ||
613 | return regs.pp_ctrl; | |
bf13e81b JN |
614 | } |
615 | ||
f0f59a00 VS |
616 | static i915_reg_t |
617 | _pp_stat_reg(struct intel_dp *intel_dp) | |
bf13e81b | 618 | { |
8e8232d5 | 619 | struct pps_registers regs; |
bf13e81b | 620 | |
8e8232d5 ID |
621 | intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, |
622 | ®s); | |
623 | ||
624 | return regs.pp_stat; | |
bf13e81b JN |
625 | } |
626 | ||
01527b31 CT |
627 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
628 | This function only applicable when panel PM state is not to be tracked */ | |
629 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, | |
630 | void *unused) | |
631 | { | |
632 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), | |
633 | edp_notifier); | |
634 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 635 | struct drm_i915_private *dev_priv = to_i915(dev); |
01527b31 CT |
636 | |
637 | if (!is_edp(intel_dp) || code != SYS_RESTART) | |
638 | return 0; | |
639 | ||
773538e8 | 640 | pps_lock(intel_dp); |
e39b999a | 641 | |
666a4537 | 642 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e39b999a | 643 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
f0f59a00 | 644 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
649636ef | 645 | u32 pp_div; |
e39b999a | 646 | |
44cb734c ID |
647 | pp_ctrl_reg = PP_CONTROL(pipe); |
648 | pp_div_reg = PP_DIVISOR(pipe); | |
01527b31 CT |
649 | pp_div = I915_READ(pp_div_reg); |
650 | pp_div &= PP_REFERENCE_DIVIDER_MASK; | |
651 | ||
652 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ | |
653 | I915_WRITE(pp_div_reg, pp_div | 0x1F); | |
654 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); | |
655 | msleep(intel_dp->panel_power_cycle_delay); | |
656 | } | |
657 | ||
773538e8 | 658 | pps_unlock(intel_dp); |
e39b999a | 659 | |
01527b31 CT |
660 | return 0; |
661 | } | |
662 | ||
4be73780 | 663 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
ebf33b18 | 664 | { |
30add22d | 665 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 666 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 667 | |
e39b999a VS |
668 | lockdep_assert_held(&dev_priv->pps_mutex); |
669 | ||
666a4537 | 670 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
9a42356b VS |
671 | intel_dp->pps_pipe == INVALID_PIPE) |
672 | return false; | |
673 | ||
bf13e81b | 674 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
675 | } |
676 | ||
4be73780 | 677 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
ebf33b18 | 678 | { |
30add22d | 679 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 680 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 681 | |
e39b999a VS |
682 | lockdep_assert_held(&dev_priv->pps_mutex); |
683 | ||
666a4537 | 684 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
9a42356b VS |
685 | intel_dp->pps_pipe == INVALID_PIPE) |
686 | return false; | |
687 | ||
773538e8 | 688 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
ebf33b18 KP |
689 | } |
690 | ||
9b984dae KP |
691 | static void |
692 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
693 | { | |
30add22d | 694 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 695 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 696 | |
9b984dae KP |
697 | if (!is_edp(intel_dp)) |
698 | return; | |
453c5420 | 699 | |
4be73780 | 700 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
701 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
702 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
bf13e81b JN |
703 | I915_READ(_pp_stat_reg(intel_dp)), |
704 | I915_READ(_pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
705 | } |
706 | } | |
707 | ||
9ee32fea DV |
708 | static uint32_t |
709 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) | |
710 | { | |
711 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
712 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 713 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 714 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
9ee32fea DV |
715 | uint32_t status; |
716 | bool done; | |
717 | ||
ef04f00d | 718 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
9ee32fea | 719 | if (has_aux_irq) |
b18ac466 | 720 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
3598706b | 721 | msecs_to_jiffies_timeout(10)); |
9ee32fea | 722 | else |
713a6b66 | 723 | done = wait_for(C, 10) == 0; |
9ee32fea DV |
724 | if (!done) |
725 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", | |
726 | has_aux_irq); | |
727 | #undef C | |
728 | ||
729 | return status; | |
730 | } | |
731 | ||
6ffb1be7 | 732 | static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
a4fc5ed6 | 733 | { |
174edf1f | 734 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
e7dc33f3 | 735 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
9ee32fea | 736 | |
a457f54b VS |
737 | if (index) |
738 | return 0; | |
739 | ||
ec5b01dd DL |
740 | /* |
741 | * The clock divider is based off the hrawclk, and would like to run at | |
a457f54b | 742 | * 2MHz. So, take the hrawclk value and divide by 2000 and use that |
a4fc5ed6 | 743 | */ |
a457f54b | 744 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
ec5b01dd DL |
745 | } |
746 | ||
747 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
748 | { | |
749 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
a457f54b | 750 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
ec5b01dd DL |
751 | |
752 | if (index) | |
753 | return 0; | |
754 | ||
a457f54b VS |
755 | /* |
756 | * The clock divider is based off the cdclk or PCH rawclk, and would | |
757 | * like to run at 2MHz. So, take the cdclk or PCH rawclk value and | |
758 | * divide by 2000 and use that | |
759 | */ | |
e7dc33f3 | 760 | if (intel_dig_port->port == PORT_A) |
fce18c4c | 761 | return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000); |
e7dc33f3 VS |
762 | else |
763 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); | |
ec5b01dd DL |
764 | } |
765 | ||
766 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
767 | { | |
768 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
a457f54b | 769 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
ec5b01dd | 770 | |
a457f54b | 771 | if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) { |
2c55c336 | 772 | /* Workaround for non-ULT HSW */ |
bc86625a CW |
773 | switch (index) { |
774 | case 0: return 63; | |
775 | case 1: return 72; | |
776 | default: return 0; | |
777 | } | |
2c55c336 | 778 | } |
a457f54b VS |
779 | |
780 | return ilk_get_aux_clock_divider(intel_dp, index); | |
b84a1cf8 RV |
781 | } |
782 | ||
b6b5e383 DL |
783 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
784 | { | |
785 | /* | |
786 | * SKL doesn't need us to program the AUX clock divider (Hardware will | |
787 | * derive the clock from CDCLK automatically). We still implement the | |
788 | * get_aux_clock_divider vfunc to plug-in into the existing code. | |
789 | */ | |
790 | return index ? 0 : 1; | |
791 | } | |
792 | ||
6ffb1be7 VS |
793 | static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, |
794 | bool has_aux_irq, | |
795 | int send_bytes, | |
796 | uint32_t aux_clock_divider) | |
5ed12a19 DL |
797 | { |
798 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
799 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
800 | uint32_t precharge, timeout; | |
801 | ||
802 | if (IS_GEN6(dev)) | |
803 | precharge = 3; | |
804 | else | |
805 | precharge = 5; | |
806 | ||
f3c6a3a7 | 807 | if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A) |
5ed12a19 DL |
808 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
809 | else | |
810 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; | |
811 | ||
812 | return DP_AUX_CH_CTL_SEND_BUSY | | |
788d4433 | 813 | DP_AUX_CH_CTL_DONE | |
5ed12a19 | 814 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
788d4433 | 815 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
5ed12a19 | 816 | timeout | |
788d4433 | 817 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
5ed12a19 DL |
818 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
819 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
788d4433 | 820 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
5ed12a19 DL |
821 | } |
822 | ||
b9ca5fad DL |
823 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
824 | bool has_aux_irq, | |
825 | int send_bytes, | |
826 | uint32_t unused) | |
827 | { | |
828 | return DP_AUX_CH_CTL_SEND_BUSY | | |
829 | DP_AUX_CH_CTL_DONE | | |
830 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | | |
831 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
832 | DP_AUX_CH_CTL_TIME_OUT_1600us | | |
833 | DP_AUX_CH_CTL_RECEIVE_ERROR | | |
834 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
d4dcbdce | 835 | DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | |
b9ca5fad DL |
836 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
837 | } | |
838 | ||
b84a1cf8 RV |
839 | static int |
840 | intel_dp_aux_ch(struct intel_dp *intel_dp, | |
bd9f74a5 | 841 | const uint8_t *send, int send_bytes, |
b84a1cf8 RV |
842 | uint8_t *recv, int recv_size) |
843 | { | |
844 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
845 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 846 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 847 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
bc86625a | 848 | uint32_t aux_clock_divider; |
b84a1cf8 RV |
849 | int i, ret, recv_bytes; |
850 | uint32_t status; | |
5ed12a19 | 851 | int try, clock = 0; |
4e6b788c | 852 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
884f19e9 JN |
853 | bool vdd; |
854 | ||
773538e8 | 855 | pps_lock(intel_dp); |
e39b999a | 856 | |
72c3500a VS |
857 | /* |
858 | * We will be called with VDD already enabled for dpcd/edid/oui reads. | |
859 | * In such cases we want to leave VDD enabled and it's up to upper layers | |
860 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off | |
861 | * ourselves. | |
862 | */ | |
1e0560e0 | 863 | vdd = edp_panel_vdd_on(intel_dp); |
b84a1cf8 RV |
864 | |
865 | /* dp aux is extremely sensitive to irq latency, hence request the | |
866 | * lowest possible wakeup latency and so prevent the cpu from going into | |
867 | * deep sleep states. | |
868 | */ | |
869 | pm_qos_update_request(&dev_priv->pm_qos, 0); | |
870 | ||
871 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 872 | |
11bee43e JB |
873 | /* Try to wait for any previous AUX channel activity */ |
874 | for (try = 0; try < 3; try++) { | |
ef04f00d | 875 | status = I915_READ_NOTRACE(ch_ctl); |
11bee43e JB |
876 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
877 | break; | |
878 | msleep(1); | |
879 | } | |
880 | ||
881 | if (try == 3) { | |
02196c77 MK |
882 | static u32 last_status = -1; |
883 | const u32 status = I915_READ(ch_ctl); | |
884 | ||
885 | if (status != last_status) { | |
886 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
887 | status); | |
888 | last_status = status; | |
889 | } | |
890 | ||
9ee32fea DV |
891 | ret = -EBUSY; |
892 | goto out; | |
4f7f7b7e CW |
893 | } |
894 | ||
46a5ae9f PZ |
895 | /* Only 5 data registers! */ |
896 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { | |
897 | ret = -E2BIG; | |
898 | goto out; | |
899 | } | |
900 | ||
ec5b01dd | 901 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
153b1100 DL |
902 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
903 | has_aux_irq, | |
904 | send_bytes, | |
905 | aux_clock_divider); | |
5ed12a19 | 906 | |
bc86625a CW |
907 | /* Must try at least 3 times according to DP spec */ |
908 | for (try = 0; try < 5; try++) { | |
909 | /* Load the send data into the aux channel data registers */ | |
910 | for (i = 0; i < send_bytes; i += 4) | |
330e20ec | 911 | I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], |
a4f1289e RV |
912 | intel_dp_pack_aux(send + i, |
913 | send_bytes - i)); | |
bc86625a CW |
914 | |
915 | /* Send the command and wait for it to complete */ | |
5ed12a19 | 916 | I915_WRITE(ch_ctl, send_ctl); |
bc86625a CW |
917 | |
918 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); | |
919 | ||
920 | /* Clear done status and any errors */ | |
921 | I915_WRITE(ch_ctl, | |
922 | status | | |
923 | DP_AUX_CH_CTL_DONE | | |
924 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
925 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
926 | ||
74ebf294 | 927 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
bc86625a | 928 | continue; |
74ebf294 TP |
929 | |
930 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 | |
931 | * 400us delay required for errors and timeouts | |
932 | * Timeout errors from the HW already meet this | |
933 | * requirement so skip to next iteration | |
934 | */ | |
935 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { | |
936 | usleep_range(400, 500); | |
bc86625a | 937 | continue; |
74ebf294 | 938 | } |
bc86625a | 939 | if (status & DP_AUX_CH_CTL_DONE) |
e058c945 | 940 | goto done; |
bc86625a | 941 | } |
a4fc5ed6 KP |
942 | } |
943 | ||
a4fc5ed6 | 944 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 945 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
9ee32fea DV |
946 | ret = -EBUSY; |
947 | goto out; | |
a4fc5ed6 KP |
948 | } |
949 | ||
e058c945 | 950 | done: |
a4fc5ed6 KP |
951 | /* Check for timeout or receive error. |
952 | * Timeouts occur when the sink is not connected | |
953 | */ | |
a5b3da54 | 954 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 955 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
9ee32fea DV |
956 | ret = -EIO; |
957 | goto out; | |
a5b3da54 | 958 | } |
1ae8c0a5 KP |
959 | |
960 | /* Timeouts occur when the device isn't connected, so they're | |
961 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 962 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
28c97730 | 963 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
9ee32fea DV |
964 | ret = -ETIMEDOUT; |
965 | goto out; | |
a4fc5ed6 KP |
966 | } |
967 | ||
968 | /* Unload any bytes sent back from the other side */ | |
969 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
970 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
14e01889 RV |
971 | |
972 | /* | |
973 | * By BSpec: "Message sizes of 0 or >20 are not allowed." | |
974 | * We have no idea of what happened so we return -EBUSY so | |
975 | * drm layer takes care for the necessary retries. | |
976 | */ | |
977 | if (recv_bytes == 0 || recv_bytes > 20) { | |
978 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", | |
979 | recv_bytes); | |
980 | /* | |
981 | * FIXME: This patch was created on top of a series that | |
982 | * organize the retries at drm level. There EBUSY should | |
983 | * also take care for 1ms wait before retrying. | |
984 | * That aux retries re-org is still needed and after that is | |
985 | * merged we remove this sleep from here. | |
986 | */ | |
987 | usleep_range(1000, 1500); | |
988 | ret = -EBUSY; | |
989 | goto out; | |
990 | } | |
991 | ||
a4fc5ed6 KP |
992 | if (recv_bytes > recv_size) |
993 | recv_bytes = recv_size; | |
0206e353 | 994 | |
4f7f7b7e | 995 | for (i = 0; i < recv_bytes; i += 4) |
330e20ec | 996 | intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), |
a4f1289e | 997 | recv + i, recv_bytes - i); |
a4fc5ed6 | 998 | |
9ee32fea DV |
999 | ret = recv_bytes; |
1000 | out: | |
1001 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); | |
1002 | ||
884f19e9 JN |
1003 | if (vdd) |
1004 | edp_panel_vdd_off(intel_dp, false); | |
1005 | ||
773538e8 | 1006 | pps_unlock(intel_dp); |
e39b999a | 1007 | |
9ee32fea | 1008 | return ret; |
a4fc5ed6 KP |
1009 | } |
1010 | ||
a6c8aff0 JN |
1011 | #define BARE_ADDRESS_SIZE 3 |
1012 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) | |
9d1a1031 JN |
1013 | static ssize_t |
1014 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
a4fc5ed6 | 1015 | { |
9d1a1031 JN |
1016 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
1017 | uint8_t txbuf[20], rxbuf[20]; | |
1018 | size_t txsize, rxsize; | |
a4fc5ed6 | 1019 | int ret; |
a4fc5ed6 | 1020 | |
d2d9cbbd VS |
1021 | txbuf[0] = (msg->request << 4) | |
1022 | ((msg->address >> 16) & 0xf); | |
1023 | txbuf[1] = (msg->address >> 8) & 0xff; | |
9d1a1031 JN |
1024 | txbuf[2] = msg->address & 0xff; |
1025 | txbuf[3] = msg->size - 1; | |
46a5ae9f | 1026 | |
9d1a1031 JN |
1027 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
1028 | case DP_AUX_NATIVE_WRITE: | |
1029 | case DP_AUX_I2C_WRITE: | |
c1e74122 | 1030 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
a6c8aff0 | 1031 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
a1ddefd8 | 1032 | rxsize = 2; /* 0 or 1 data bytes */ |
f51a44b9 | 1033 | |
9d1a1031 JN |
1034 | if (WARN_ON(txsize > 20)) |
1035 | return -E2BIG; | |
a4fc5ed6 | 1036 | |
dd788090 VS |
1037 | WARN_ON(!msg->buffer != !msg->size); |
1038 | ||
d81a67cc ID |
1039 | if (msg->buffer) |
1040 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); | |
a4fc5ed6 | 1041 | |
9d1a1031 JN |
1042 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1043 | if (ret > 0) { | |
1044 | msg->reply = rxbuf[0] >> 4; | |
a4fc5ed6 | 1045 | |
a1ddefd8 JN |
1046 | if (ret > 1) { |
1047 | /* Number of bytes written in a short write. */ | |
1048 | ret = clamp_t(int, rxbuf[1], 0, msg->size); | |
1049 | } else { | |
1050 | /* Return payload size. */ | |
1051 | ret = msg->size; | |
1052 | } | |
9d1a1031 JN |
1053 | } |
1054 | break; | |
46a5ae9f | 1055 | |
9d1a1031 JN |
1056 | case DP_AUX_NATIVE_READ: |
1057 | case DP_AUX_I2C_READ: | |
a6c8aff0 | 1058 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
9d1a1031 | 1059 | rxsize = msg->size + 1; |
a4fc5ed6 | 1060 | |
9d1a1031 JN |
1061 | if (WARN_ON(rxsize > 20)) |
1062 | return -E2BIG; | |
a4fc5ed6 | 1063 | |
9d1a1031 JN |
1064 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1065 | if (ret > 0) { | |
1066 | msg->reply = rxbuf[0] >> 4; | |
1067 | /* | |
1068 | * Assume happy day, and copy the data. The caller is | |
1069 | * expected to check msg->reply before touching it. | |
1070 | * | |
1071 | * Return payload size. | |
1072 | */ | |
1073 | ret--; | |
1074 | memcpy(msg->buffer, rxbuf + 1, ret); | |
a4fc5ed6 | 1075 | } |
9d1a1031 JN |
1076 | break; |
1077 | ||
1078 | default: | |
1079 | ret = -EINVAL; | |
1080 | break; | |
a4fc5ed6 | 1081 | } |
f51a44b9 | 1082 | |
9d1a1031 | 1083 | return ret; |
a4fc5ed6 KP |
1084 | } |
1085 | ||
f0f59a00 VS |
1086 | static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1087 | enum port port) | |
da00bdcf VS |
1088 | { |
1089 | switch (port) { | |
1090 | case PORT_B: | |
1091 | case PORT_C: | |
1092 | case PORT_D: | |
1093 | return DP_AUX_CH_CTL(port); | |
1094 | default: | |
1095 | MISSING_CASE(port); | |
1096 | return DP_AUX_CH_CTL(PORT_B); | |
1097 | } | |
1098 | } | |
1099 | ||
f0f59a00 VS |
1100 | static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, |
1101 | enum port port, int index) | |
330e20ec VS |
1102 | { |
1103 | switch (port) { | |
1104 | case PORT_B: | |
1105 | case PORT_C: | |
1106 | case PORT_D: | |
1107 | return DP_AUX_CH_DATA(port, index); | |
1108 | default: | |
1109 | MISSING_CASE(port); | |
1110 | return DP_AUX_CH_DATA(PORT_B, index); | |
1111 | } | |
1112 | } | |
1113 | ||
f0f59a00 VS |
1114 | static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1115 | enum port port) | |
da00bdcf VS |
1116 | { |
1117 | switch (port) { | |
1118 | case PORT_A: | |
1119 | return DP_AUX_CH_CTL(port); | |
1120 | case PORT_B: | |
1121 | case PORT_C: | |
1122 | case PORT_D: | |
1123 | return PCH_DP_AUX_CH_CTL(port); | |
1124 | default: | |
1125 | MISSING_CASE(port); | |
1126 | return DP_AUX_CH_CTL(PORT_A); | |
1127 | } | |
1128 | } | |
1129 | ||
f0f59a00 VS |
1130 | static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, |
1131 | enum port port, int index) | |
330e20ec VS |
1132 | { |
1133 | switch (port) { | |
1134 | case PORT_A: | |
1135 | return DP_AUX_CH_DATA(port, index); | |
1136 | case PORT_B: | |
1137 | case PORT_C: | |
1138 | case PORT_D: | |
1139 | return PCH_DP_AUX_CH_DATA(port, index); | |
1140 | default: | |
1141 | MISSING_CASE(port); | |
1142 | return DP_AUX_CH_DATA(PORT_A, index); | |
1143 | } | |
1144 | } | |
1145 | ||
da00bdcf VS |
1146 | /* |
1147 | * On SKL we don't have Aux for port E so we rely | |
1148 | * on VBT to set a proper alternate aux channel. | |
1149 | */ | |
1150 | static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv) | |
1151 | { | |
1152 | const struct ddi_vbt_port_info *info = | |
1153 | &dev_priv->vbt.ddi_port_info[PORT_E]; | |
1154 | ||
1155 | switch (info->alternate_aux_channel) { | |
1156 | case DP_AUX_A: | |
1157 | return PORT_A; | |
1158 | case DP_AUX_B: | |
1159 | return PORT_B; | |
1160 | case DP_AUX_C: | |
1161 | return PORT_C; | |
1162 | case DP_AUX_D: | |
1163 | return PORT_D; | |
1164 | default: | |
1165 | MISSING_CASE(info->alternate_aux_channel); | |
1166 | return PORT_A; | |
1167 | } | |
1168 | } | |
1169 | ||
f0f59a00 VS |
1170 | static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1171 | enum port port) | |
da00bdcf VS |
1172 | { |
1173 | if (port == PORT_E) | |
1174 | port = skl_porte_aux_port(dev_priv); | |
1175 | ||
1176 | switch (port) { | |
1177 | case PORT_A: | |
1178 | case PORT_B: | |
1179 | case PORT_C: | |
1180 | case PORT_D: | |
1181 | return DP_AUX_CH_CTL(port); | |
1182 | default: | |
1183 | MISSING_CASE(port); | |
1184 | return DP_AUX_CH_CTL(PORT_A); | |
1185 | } | |
1186 | } | |
1187 | ||
f0f59a00 VS |
1188 | static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, |
1189 | enum port port, int index) | |
330e20ec VS |
1190 | { |
1191 | if (port == PORT_E) | |
1192 | port = skl_porte_aux_port(dev_priv); | |
1193 | ||
1194 | switch (port) { | |
1195 | case PORT_A: | |
1196 | case PORT_B: | |
1197 | case PORT_C: | |
1198 | case PORT_D: | |
1199 | return DP_AUX_CH_DATA(port, index); | |
1200 | default: | |
1201 | MISSING_CASE(port); | |
1202 | return DP_AUX_CH_DATA(PORT_A, index); | |
1203 | } | |
1204 | } | |
1205 | ||
f0f59a00 VS |
1206 | static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, |
1207 | enum port port) | |
330e20ec VS |
1208 | { |
1209 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
1210 | return skl_aux_ctl_reg(dev_priv, port); | |
1211 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1212 | return ilk_aux_ctl_reg(dev_priv, port); | |
1213 | else | |
1214 | return g4x_aux_ctl_reg(dev_priv, port); | |
1215 | } | |
1216 | ||
f0f59a00 VS |
1217 | static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, |
1218 | enum port port, int index) | |
330e20ec VS |
1219 | { |
1220 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
1221 | return skl_aux_data_reg(dev_priv, port, index); | |
1222 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1223 | return ilk_aux_data_reg(dev_priv, port, index); | |
1224 | else | |
1225 | return g4x_aux_data_reg(dev_priv, port, index); | |
1226 | } | |
1227 | ||
1228 | static void intel_aux_reg_init(struct intel_dp *intel_dp) | |
1229 | { | |
1230 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); | |
1231 | enum port port = dp_to_dig_port(intel_dp)->port; | |
1232 | int i; | |
1233 | ||
1234 | intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); | |
1235 | for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) | |
1236 | intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); | |
1237 | } | |
1238 | ||
9d1a1031 | 1239 | static void |
a121f4e5 VS |
1240 | intel_dp_aux_fini(struct intel_dp *intel_dp) |
1241 | { | |
a121f4e5 VS |
1242 | kfree(intel_dp->aux.name); |
1243 | } | |
1244 | ||
7a418e34 | 1245 | static void |
9d1a1031 JN |
1246 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) |
1247 | { | |
33ad6626 JN |
1248 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1249 | enum port port = intel_dig_port->port; | |
ab2c0672 | 1250 | |
330e20ec | 1251 | intel_aux_reg_init(intel_dp); |
7a418e34 | 1252 | drm_dp_aux_init(&intel_dp->aux); |
8316f337 | 1253 | |
7a418e34 | 1254 | /* Failure to allocate our preferred name is not critical */ |
a121f4e5 | 1255 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); |
9d1a1031 | 1256 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
a4fc5ed6 KP |
1257 | } |
1258 | ||
fc0f8e25 | 1259 | static int |
12f6a2e2 | 1260 | intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates) |
fc0f8e25 | 1261 | { |
94ca719e VS |
1262 | if (intel_dp->num_sink_rates) { |
1263 | *sink_rates = intel_dp->sink_rates; | |
1264 | return intel_dp->num_sink_rates; | |
fc0f8e25 | 1265 | } |
12f6a2e2 VS |
1266 | |
1267 | *sink_rates = default_rates; | |
1268 | ||
1269 | return (intel_dp_max_link_bw(intel_dp) >> 3) + 1; | |
fc0f8e25 SJ |
1270 | } |
1271 | ||
e588fa18 | 1272 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
ed63baaf | 1273 | { |
e588fa18 ACO |
1274 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1275 | struct drm_device *dev = dig_port->base.base.dev; | |
1276 | ||
ed63baaf | 1277 | /* WaDisableHBR2:skl */ |
e87a005d | 1278 | if (IS_SKL_REVID(dev, 0, SKL_REVID_B0)) |
ed63baaf TS |
1279 | return false; |
1280 | ||
1281 | if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) || | |
1282 | (INTEL_INFO(dev)->gen >= 9)) | |
1283 | return true; | |
1284 | else | |
1285 | return false; | |
1286 | } | |
1287 | ||
a8f3ef61 | 1288 | static int |
e588fa18 | 1289 | intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates) |
a8f3ef61 | 1290 | { |
e588fa18 ACO |
1291 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
1292 | struct drm_device *dev = dig_port->base.base.dev; | |
af7080f5 TS |
1293 | int size; |
1294 | ||
64987fc5 SJ |
1295 | if (IS_BROXTON(dev)) { |
1296 | *source_rates = bxt_rates; | |
af7080f5 | 1297 | size = ARRAY_SIZE(bxt_rates); |
ef11bdb3 | 1298 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
637a9c63 | 1299 | *source_rates = skl_rates; |
af7080f5 TS |
1300 | size = ARRAY_SIZE(skl_rates); |
1301 | } else { | |
1302 | *source_rates = default_rates; | |
1303 | size = ARRAY_SIZE(default_rates); | |
a8f3ef61 | 1304 | } |
636280ba | 1305 | |
ed63baaf | 1306 | /* This depends on the fact that 5.4 is last value in the array */ |
e588fa18 | 1307 | if (!intel_dp_source_supports_hbr2(intel_dp)) |
af7080f5 | 1308 | size--; |
636280ba | 1309 | |
af7080f5 | 1310 | return size; |
a8f3ef61 SJ |
1311 | } |
1312 | ||
c6bb3538 DV |
1313 | static void |
1314 | intel_dp_set_clock(struct intel_encoder *encoder, | |
840b32b7 | 1315 | struct intel_crtc_state *pipe_config) |
c6bb3538 DV |
1316 | { |
1317 | struct drm_device *dev = encoder->base.dev; | |
9dd4ffdf CML |
1318 | const struct dp_link_dpll *divisor = NULL; |
1319 | int i, count = 0; | |
c6bb3538 DV |
1320 | |
1321 | if (IS_G4X(dev)) { | |
9dd4ffdf CML |
1322 | divisor = gen4_dpll; |
1323 | count = ARRAY_SIZE(gen4_dpll); | |
c6bb3538 | 1324 | } else if (HAS_PCH_SPLIT(dev)) { |
9dd4ffdf CML |
1325 | divisor = pch_dpll; |
1326 | count = ARRAY_SIZE(pch_dpll); | |
ef9348c8 CML |
1327 | } else if (IS_CHERRYVIEW(dev)) { |
1328 | divisor = chv_dpll; | |
1329 | count = ARRAY_SIZE(chv_dpll); | |
c6bb3538 | 1330 | } else if (IS_VALLEYVIEW(dev)) { |
65ce4bf5 CML |
1331 | divisor = vlv_dpll; |
1332 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 1333 | } |
9dd4ffdf CML |
1334 | |
1335 | if (divisor && count) { | |
1336 | for (i = 0; i < count; i++) { | |
840b32b7 | 1337 | if (pipe_config->port_clock == divisor[i].clock) { |
9dd4ffdf CML |
1338 | pipe_config->dpll = divisor[i].dpll; |
1339 | pipe_config->clock_set = true; | |
1340 | break; | |
1341 | } | |
1342 | } | |
c6bb3538 DV |
1343 | } |
1344 | } | |
1345 | ||
2ecae76a VS |
1346 | static int intersect_rates(const int *source_rates, int source_len, |
1347 | const int *sink_rates, int sink_len, | |
94ca719e | 1348 | int *common_rates) |
a8f3ef61 SJ |
1349 | { |
1350 | int i = 0, j = 0, k = 0; | |
1351 | ||
a8f3ef61 SJ |
1352 | while (i < source_len && j < sink_len) { |
1353 | if (source_rates[i] == sink_rates[j]) { | |
e6bda3e4 VS |
1354 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) |
1355 | return k; | |
94ca719e | 1356 | common_rates[k] = source_rates[i]; |
a8f3ef61 SJ |
1357 | ++k; |
1358 | ++i; | |
1359 | ++j; | |
1360 | } else if (source_rates[i] < sink_rates[j]) { | |
1361 | ++i; | |
1362 | } else { | |
1363 | ++j; | |
1364 | } | |
1365 | } | |
1366 | return k; | |
1367 | } | |
1368 | ||
94ca719e VS |
1369 | static int intel_dp_common_rates(struct intel_dp *intel_dp, |
1370 | int *common_rates) | |
2ecae76a | 1371 | { |
2ecae76a VS |
1372 | const int *source_rates, *sink_rates; |
1373 | int source_len, sink_len; | |
1374 | ||
1375 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); | |
e588fa18 | 1376 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
2ecae76a VS |
1377 | |
1378 | return intersect_rates(source_rates, source_len, | |
1379 | sink_rates, sink_len, | |
94ca719e | 1380 | common_rates); |
2ecae76a VS |
1381 | } |
1382 | ||
0336400e VS |
1383 | static void snprintf_int_array(char *str, size_t len, |
1384 | const int *array, int nelem) | |
1385 | { | |
1386 | int i; | |
1387 | ||
1388 | str[0] = '\0'; | |
1389 | ||
1390 | for (i = 0; i < nelem; i++) { | |
b2f505be | 1391 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
0336400e VS |
1392 | if (r >= len) |
1393 | return; | |
1394 | str += r; | |
1395 | len -= r; | |
1396 | } | |
1397 | } | |
1398 | ||
1399 | static void intel_dp_print_rates(struct intel_dp *intel_dp) | |
1400 | { | |
0336400e | 1401 | const int *source_rates, *sink_rates; |
94ca719e VS |
1402 | int source_len, sink_len, common_len; |
1403 | int common_rates[DP_MAX_SUPPORTED_RATES]; | |
0336400e VS |
1404 | char str[128]; /* FIXME: too big for stack? */ |
1405 | ||
1406 | if ((drm_debug & DRM_UT_KMS) == 0) | |
1407 | return; | |
1408 | ||
e588fa18 | 1409 | source_len = intel_dp_source_rates(intel_dp, &source_rates); |
0336400e VS |
1410 | snprintf_int_array(str, sizeof(str), source_rates, source_len); |
1411 | DRM_DEBUG_KMS("source rates: %s\n", str); | |
1412 | ||
1413 | sink_len = intel_dp_sink_rates(intel_dp, &sink_rates); | |
1414 | snprintf_int_array(str, sizeof(str), sink_rates, sink_len); | |
1415 | DRM_DEBUG_KMS("sink rates: %s\n", str); | |
1416 | ||
94ca719e VS |
1417 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
1418 | snprintf_int_array(str, sizeof(str), common_rates, common_len); | |
1419 | DRM_DEBUG_KMS("common rates: %s\n", str); | |
0336400e VS |
1420 | } |
1421 | ||
f4896f15 | 1422 | static int rate_to_index(int find, const int *rates) |
a8f3ef61 SJ |
1423 | { |
1424 | int i = 0; | |
1425 | ||
1426 | for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) | |
1427 | if (find == rates[i]) | |
1428 | break; | |
1429 | ||
1430 | return i; | |
1431 | } | |
1432 | ||
50fec21a VS |
1433 | int |
1434 | intel_dp_max_link_rate(struct intel_dp *intel_dp) | |
1435 | { | |
1436 | int rates[DP_MAX_SUPPORTED_RATES] = {}; | |
1437 | int len; | |
1438 | ||
94ca719e | 1439 | len = intel_dp_common_rates(intel_dp, rates); |
50fec21a VS |
1440 | if (WARN_ON(len <= 0)) |
1441 | return 162000; | |
1442 | ||
1354f734 | 1443 | return rates[len - 1]; |
50fec21a VS |
1444 | } |
1445 | ||
ed4e9c1d VS |
1446 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1447 | { | |
94ca719e | 1448 | return rate_to_index(rate, intel_dp->sink_rates); |
ed4e9c1d VS |
1449 | } |
1450 | ||
94223d04 ACO |
1451 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
1452 | uint8_t *link_bw, uint8_t *rate_select) | |
04a60f9f VS |
1453 | { |
1454 | if (intel_dp->num_sink_rates) { | |
1455 | *link_bw = 0; | |
1456 | *rate_select = | |
1457 | intel_dp_rate_select(intel_dp, port_clock); | |
1458 | } else { | |
1459 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); | |
1460 | *rate_select = 0; | |
1461 | } | |
1462 | } | |
1463 | ||
00c09d70 | 1464 | bool |
5bfe2ac0 | 1465 | intel_dp_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
1466 | struct intel_crtc_state *pipe_config, |
1467 | struct drm_connector_state *conn_state) | |
a4fc5ed6 | 1468 | { |
5bfe2ac0 | 1469 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1470 | struct drm_i915_private *dev_priv = to_i915(dev); |
2d112de7 | 1471 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
5bfe2ac0 | 1472 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1473 | enum port port = dp_to_dig_port(intel_dp)->port; |
84556d58 | 1474 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
dd06f90e | 1475 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
a4fc5ed6 | 1476 | int lane_count, clock; |
56071a20 | 1477 | int min_lane_count = 1; |
eeb6324d | 1478 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
06ea66b6 | 1479 | /* Conveniently, the link BW constants become indices with a shift...*/ |
56071a20 | 1480 | int min_clock = 0; |
a8f3ef61 | 1481 | int max_clock; |
083f9560 | 1482 | int bpp, mode_rate; |
ff9a6750 | 1483 | int link_avail, link_clock; |
94ca719e VS |
1484 | int common_rates[DP_MAX_SUPPORTED_RATES] = {}; |
1485 | int common_len; | |
04a60f9f | 1486 | uint8_t link_bw, rate_select; |
a8f3ef61 | 1487 | |
94ca719e | 1488 | common_len = intel_dp_common_rates(intel_dp, common_rates); |
a8f3ef61 SJ |
1489 | |
1490 | /* No common link rates between source and sink */ | |
94ca719e | 1491 | WARN_ON(common_len <= 0); |
a8f3ef61 | 1492 | |
94ca719e | 1493 | max_clock = common_len - 1; |
a4fc5ed6 | 1494 | |
bc7d38a4 | 1495 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
5bfe2ac0 DV |
1496 | pipe_config->has_pch_encoder = true; |
1497 | ||
f769cd24 | 1498 | pipe_config->has_drrs = false; |
9fcb1704 | 1499 | pipe_config->has_audio = intel_dp->has_audio && port != PORT_A; |
a4fc5ed6 | 1500 | |
dd06f90e JN |
1501 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
1502 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, | |
1503 | adjusted_mode); | |
a1b2278e CK |
1504 | |
1505 | if (INTEL_INFO(dev)->gen >= 9) { | |
1506 | int ret; | |
e435d6e5 | 1507 | ret = skl_update_scaler_crtc(pipe_config); |
a1b2278e CK |
1508 | if (ret) |
1509 | return ret; | |
1510 | } | |
1511 | ||
b5667627 | 1512 | if (HAS_GMCH_DISPLAY(dev)) |
2dd24552 JB |
1513 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
1514 | intel_connector->panel.fitting_mode); | |
1515 | else | |
b074cec8 JB |
1516 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
1517 | intel_connector->panel.fitting_mode); | |
0d3a1bee ZY |
1518 | } |
1519 | ||
cb1793ce | 1520 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
0af78a2b DV |
1521 | return false; |
1522 | ||
083f9560 | 1523 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
a8f3ef61 | 1524 | "max bw %d pixel clock %iKHz\n", |
94ca719e | 1525 | max_lane_count, common_rates[max_clock], |
241bfc38 | 1526 | adjusted_mode->crtc_clock); |
083f9560 | 1527 | |
36008365 DV |
1528 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
1529 | * bpc in between. */ | |
3e7ca985 | 1530 | bpp = pipe_config->pipe_bpp; |
56071a20 | 1531 | if (is_edp(intel_dp)) { |
22ce5628 TS |
1532 | |
1533 | /* Get bpp from vbt only for panels that dont have bpp in edid */ | |
1534 | if (intel_connector->base.display_info.bpc == 0 && | |
6aa23e65 | 1535 | (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) { |
56071a20 | 1536 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
6aa23e65 JN |
1537 | dev_priv->vbt.edp.bpp); |
1538 | bpp = dev_priv->vbt.edp.bpp; | |
56071a20 JN |
1539 | } |
1540 | ||
344c5bbc JN |
1541 | /* |
1542 | * Use the maximum clock and number of lanes the eDP panel | |
1543 | * advertizes being capable of. The panels are generally | |
1544 | * designed to support only a single clock and lane | |
1545 | * configuration, and typically these values correspond to the | |
1546 | * native resolution of the panel. | |
1547 | */ | |
1548 | min_lane_count = max_lane_count; | |
1549 | min_clock = max_clock; | |
7984211e | 1550 | } |
657445fe | 1551 | |
36008365 | 1552 | for (; bpp >= 6*3; bpp -= 2*3) { |
241bfc38 DL |
1553 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
1554 | bpp); | |
36008365 | 1555 | |
c6930992 | 1556 | for (clock = min_clock; clock <= max_clock; clock++) { |
a8f3ef61 SJ |
1557 | for (lane_count = min_lane_count; |
1558 | lane_count <= max_lane_count; | |
1559 | lane_count <<= 1) { | |
1560 | ||
94ca719e | 1561 | link_clock = common_rates[clock]; |
36008365 DV |
1562 | link_avail = intel_dp_max_data_rate(link_clock, |
1563 | lane_count); | |
1564 | ||
1565 | if (mode_rate <= link_avail) { | |
1566 | goto found; | |
1567 | } | |
1568 | } | |
1569 | } | |
1570 | } | |
c4867936 | 1571 | |
36008365 | 1572 | return false; |
3685a8f3 | 1573 | |
36008365 | 1574 | found: |
55bc60db VS |
1575 | if (intel_dp->color_range_auto) { |
1576 | /* | |
1577 | * See: | |
1578 | * CEA-861-E - 5.1 Default Encoding Parameters | |
1579 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
1580 | */ | |
0f2a2a75 VS |
1581 | pipe_config->limited_color_range = |
1582 | bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1; | |
1583 | } else { | |
1584 | pipe_config->limited_color_range = | |
1585 | intel_dp->limited_color_range; | |
55bc60db VS |
1586 | } |
1587 | ||
90a6b7b0 | 1588 | pipe_config->lane_count = lane_count; |
a8f3ef61 | 1589 | |
657445fe | 1590 | pipe_config->pipe_bpp = bpp; |
94ca719e | 1591 | pipe_config->port_clock = common_rates[clock]; |
a4fc5ed6 | 1592 | |
04a60f9f VS |
1593 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
1594 | &link_bw, &rate_select); | |
1595 | ||
1596 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", | |
1597 | link_bw, rate_select, pipe_config->lane_count, | |
ff9a6750 | 1598 | pipe_config->port_clock, bpp); |
36008365 DV |
1599 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
1600 | mode_rate, link_avail); | |
a4fc5ed6 | 1601 | |
03afc4a2 | 1602 | intel_link_compute_m_n(bpp, lane_count, |
241bfc38 DL |
1603 | adjusted_mode->crtc_clock, |
1604 | pipe_config->port_clock, | |
03afc4a2 | 1605 | &pipe_config->dp_m_n); |
9d1a455b | 1606 | |
439d7ac0 | 1607 | if (intel_connector->panel.downclock_mode != NULL && |
96178eeb | 1608 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
f769cd24 | 1609 | pipe_config->has_drrs = true; |
439d7ac0 PB |
1610 | intel_link_compute_m_n(bpp, lane_count, |
1611 | intel_connector->panel.downclock_mode->clock, | |
1612 | pipe_config->port_clock, | |
1613 | &pipe_config->dp_m2_n2); | |
1614 | } | |
1615 | ||
14d41b3b VS |
1616 | /* |
1617 | * DPLL0 VCO may need to be adjusted to get the correct | |
1618 | * clock for eDP. This will affect cdclk as well. | |
1619 | */ | |
1620 | if (is_edp(intel_dp) && | |
1621 | (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) { | |
1622 | int vco; | |
1623 | ||
1624 | switch (pipe_config->port_clock / 2) { | |
1625 | case 108000: | |
1626 | case 216000: | |
63911d72 | 1627 | vco = 8640000; |
14d41b3b VS |
1628 | break; |
1629 | default: | |
63911d72 | 1630 | vco = 8100000; |
14d41b3b VS |
1631 | break; |
1632 | } | |
1633 | ||
1634 | to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco; | |
1635 | } | |
1636 | ||
a3c988ea | 1637 | if (!HAS_DDI(dev)) |
840b32b7 | 1638 | intel_dp_set_clock(encoder, pipe_config); |
c6bb3538 | 1639 | |
03afc4a2 | 1640 | return true; |
a4fc5ed6 KP |
1641 | } |
1642 | ||
901c2daf VS |
1643 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
1644 | const struct intel_crtc_state *pipe_config) | |
1645 | { | |
1646 | intel_dp->link_rate = pipe_config->port_clock; | |
1647 | intel_dp->lane_count = pipe_config->lane_count; | |
64ee2fd2 | 1648 | intel_dp->link_mst = intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST); |
901c2daf VS |
1649 | } |
1650 | ||
85cb48a1 ML |
1651 | static void intel_dp_prepare(struct intel_encoder *encoder, |
1652 | struct intel_crtc_state *pipe_config) | |
a4fc5ed6 | 1653 | { |
b934223d | 1654 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1655 | struct drm_i915_private *dev_priv = to_i915(dev); |
b934223d | 1656 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1657 | enum port port = dp_to_dig_port(intel_dp)->port; |
b934223d | 1658 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
85cb48a1 | 1659 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
a4fc5ed6 | 1660 | |
85cb48a1 | 1661 | intel_dp_set_link_params(intel_dp, pipe_config); |
901c2daf | 1662 | |
417e822d | 1663 | /* |
1a2eb460 | 1664 | * There are four kinds of DP registers: |
417e822d KP |
1665 | * |
1666 | * IBX PCH | |
1a2eb460 KP |
1667 | * SNB CPU |
1668 | * IVB CPU | |
417e822d KP |
1669 | * CPT PCH |
1670 | * | |
1671 | * IBX PCH and CPU are the same for almost everything, | |
1672 | * except that the CPU DP PLL is configured in this | |
1673 | * register | |
1674 | * | |
1675 | * CPT PCH is quite different, having many bits moved | |
1676 | * to the TRANS_DP_CTL register instead. That | |
1677 | * configuration happens (oddly) in ironlake_pch_enable | |
1678 | */ | |
9c9e7927 | 1679 | |
417e822d KP |
1680 | /* Preserve the BIOS-computed detected bit. This is |
1681 | * supposed to be read-only. | |
1682 | */ | |
1683 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
a4fc5ed6 | 1684 | |
417e822d | 1685 | /* Handle DP bits in common between all three register formats */ |
417e822d | 1686 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
85cb48a1 | 1687 | intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); |
a4fc5ed6 | 1688 | |
417e822d | 1689 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 1690 | |
39e5fa88 | 1691 | if (IS_GEN7(dev) && port == PORT_A) { |
1a2eb460 KP |
1692 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1693 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1694 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1695 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1696 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
1697 | ||
6aba5b6c | 1698 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
1699 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1700 | ||
7c62a164 | 1701 | intel_dp->DP |= crtc->pipe << 29; |
39e5fa88 | 1702 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
e3ef4479 VS |
1703 | u32 trans_dp; |
1704 | ||
39e5fa88 | 1705 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3ef4479 VS |
1706 | |
1707 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); | |
1708 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
1709 | trans_dp |= TRANS_DP_ENH_FRAMING; | |
1710 | else | |
1711 | trans_dp &= ~TRANS_DP_ENH_FRAMING; | |
1712 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); | |
39e5fa88 | 1713 | } else { |
0f2a2a75 | 1714 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
85cb48a1 | 1715 | !IS_CHERRYVIEW(dev) && pipe_config->limited_color_range) |
0f2a2a75 | 1716 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
417e822d KP |
1717 | |
1718 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
1719 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1720 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1721 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1722 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
1723 | ||
6aba5b6c | 1724 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
1725 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1726 | ||
39e5fa88 | 1727 | if (IS_CHERRYVIEW(dev)) |
44f37d1f | 1728 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
39e5fa88 VS |
1729 | else if (crtc->pipe == PIPE_B) |
1730 | intel_dp->DP |= DP_PIPEB_SELECT; | |
32f9d658 | 1731 | } |
a4fc5ed6 KP |
1732 | } |
1733 | ||
ffd6749d PZ |
1734 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1735 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
99ea7127 | 1736 | |
1a5ef5b7 PZ |
1737 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1738 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) | |
99ea7127 | 1739 | |
ffd6749d PZ |
1740 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1741 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
99ea7127 | 1742 | |
de9c1b6b ID |
1743 | static void intel_pps_verify_state(struct drm_i915_private *dev_priv, |
1744 | struct intel_dp *intel_dp); | |
1745 | ||
4be73780 | 1746 | static void wait_panel_status(struct intel_dp *intel_dp, |
99ea7127 KP |
1747 | u32 mask, |
1748 | u32 value) | |
bd943159 | 1749 | { |
30add22d | 1750 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 1751 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1752 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
453c5420 | 1753 | |
e39b999a VS |
1754 | lockdep_assert_held(&dev_priv->pps_mutex); |
1755 | ||
de9c1b6b ID |
1756 | intel_pps_verify_state(dev_priv, intel_dp); |
1757 | ||
bf13e81b JN |
1758 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1759 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 1760 | |
99ea7127 | 1761 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
453c5420 JB |
1762 | mask, value, |
1763 | I915_READ(pp_stat_reg), | |
1764 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1765 | |
9036ff06 CW |
1766 | if (intel_wait_for_register(dev_priv, |
1767 | pp_stat_reg, mask, value, | |
1768 | 5000)) | |
99ea7127 | 1769 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
453c5420 JB |
1770 | I915_READ(pp_stat_reg), |
1771 | I915_READ(pp_ctrl_reg)); | |
54c136d4 CW |
1772 | |
1773 | DRM_DEBUG_KMS("Wait complete\n"); | |
99ea7127 | 1774 | } |
32ce697c | 1775 | |
4be73780 | 1776 | static void wait_panel_on(struct intel_dp *intel_dp) |
99ea7127 KP |
1777 | { |
1778 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
4be73780 | 1779 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
bd943159 KP |
1780 | } |
1781 | ||
4be73780 | 1782 | static void wait_panel_off(struct intel_dp *intel_dp) |
99ea7127 KP |
1783 | { |
1784 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
4be73780 | 1785 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
99ea7127 KP |
1786 | } |
1787 | ||
4be73780 | 1788 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
99ea7127 | 1789 | { |
d28d4731 AK |
1790 | ktime_t panel_power_on_time; |
1791 | s64 panel_power_off_duration; | |
1792 | ||
99ea7127 | 1793 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
dce56b3c | 1794 | |
d28d4731 AK |
1795 | /* take the difference of currrent time and panel power off time |
1796 | * and then make panel wait for t11_t12 if needed. */ | |
1797 | panel_power_on_time = ktime_get_boottime(); | |
1798 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); | |
1799 | ||
dce56b3c PZ |
1800 | /* When we disable the VDD override bit last we have to do the manual |
1801 | * wait. */ | |
d28d4731 AK |
1802 | if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
1803 | wait_remaining_ms_from_jiffies(jiffies, | |
1804 | intel_dp->panel_power_cycle_delay - panel_power_off_duration); | |
dce56b3c | 1805 | |
4be73780 | 1806 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
99ea7127 KP |
1807 | } |
1808 | ||
4be73780 | 1809 | static void wait_backlight_on(struct intel_dp *intel_dp) |
dce56b3c PZ |
1810 | { |
1811 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, | |
1812 | intel_dp->backlight_on_delay); | |
1813 | } | |
1814 | ||
4be73780 | 1815 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
dce56b3c PZ |
1816 | { |
1817 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, | |
1818 | intel_dp->backlight_off_delay); | |
1819 | } | |
99ea7127 | 1820 | |
832dd3c1 KP |
1821 | /* Read the current pp_control value, unlocking the register if it |
1822 | * is locked | |
1823 | */ | |
1824 | ||
453c5420 | 1825 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 1826 | { |
453c5420 | 1827 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 1828 | struct drm_i915_private *dev_priv = to_i915(dev); |
453c5420 | 1829 | u32 control; |
832dd3c1 | 1830 | |
e39b999a VS |
1831 | lockdep_assert_held(&dev_priv->pps_mutex); |
1832 | ||
bf13e81b | 1833 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
8090ba8c ID |
1834 | if (WARN_ON(!HAS_DDI(dev_priv) && |
1835 | (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { | |
b0a08bec VK |
1836 | control &= ~PANEL_UNLOCK_MASK; |
1837 | control |= PANEL_UNLOCK_REGS; | |
1838 | } | |
832dd3c1 | 1839 | return control; |
bd943159 KP |
1840 | } |
1841 | ||
951468f3 VS |
1842 | /* |
1843 | * Must be paired with edp_panel_vdd_off(). | |
1844 | * Must hold pps_mutex around the whole on/off sequence. | |
1845 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
1846 | */ | |
1e0560e0 | 1847 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 1848 | { |
30add22d | 1849 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4e6e1a54 ID |
1850 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1851 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fac5e23e | 1852 | struct drm_i915_private *dev_priv = to_i915(dev); |
4e6e1a54 | 1853 | enum intel_display_power_domain power_domain; |
5d613501 | 1854 | u32 pp; |
f0f59a00 | 1855 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
adddaaf4 | 1856 | bool need_to_disable = !intel_dp->want_panel_vdd; |
5d613501 | 1857 | |
e39b999a VS |
1858 | lockdep_assert_held(&dev_priv->pps_mutex); |
1859 | ||
97af61f5 | 1860 | if (!is_edp(intel_dp)) |
adddaaf4 | 1861 | return false; |
bd943159 | 1862 | |
2c623c11 | 1863 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
bd943159 | 1864 | intel_dp->want_panel_vdd = true; |
99ea7127 | 1865 | |
4be73780 | 1866 | if (edp_have_panel_vdd(intel_dp)) |
adddaaf4 | 1867 | return need_to_disable; |
b0665d57 | 1868 | |
25f78f58 | 1869 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4e6e1a54 | 1870 | intel_display_power_get(dev_priv, power_domain); |
e9cb81a2 | 1871 | |
3936fcf4 VS |
1872 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
1873 | port_name(intel_dig_port->port)); | |
bd943159 | 1874 | |
4be73780 DV |
1875 | if (!edp_have_panel_power(intel_dp)) |
1876 | wait_panel_power_cycle(intel_dp); | |
99ea7127 | 1877 | |
453c5420 | 1878 | pp = ironlake_get_pp_control(intel_dp); |
5d613501 | 1879 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 1880 | |
bf13e81b JN |
1881 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1882 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 JB |
1883 | |
1884 | I915_WRITE(pp_ctrl_reg, pp); | |
1885 | POSTING_READ(pp_ctrl_reg); | |
1886 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1887 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
ebf33b18 KP |
1888 | /* |
1889 | * If the panel wasn't on, delay before accessing aux channel | |
1890 | */ | |
4be73780 | 1891 | if (!edp_have_panel_power(intel_dp)) { |
3936fcf4 VS |
1892 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
1893 | port_name(intel_dig_port->port)); | |
f01eca2e | 1894 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 1895 | } |
adddaaf4 JN |
1896 | |
1897 | return need_to_disable; | |
1898 | } | |
1899 | ||
951468f3 VS |
1900 | /* |
1901 | * Must be paired with intel_edp_panel_vdd_off() or | |
1902 | * intel_edp_panel_off(). | |
1903 | * Nested calls to these functions are not allowed since | |
1904 | * we drop the lock. Caller must use some higher level | |
1905 | * locking to prevent nested calls from other threads. | |
1906 | */ | |
b80d6c78 | 1907 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
adddaaf4 | 1908 | { |
c695b6b6 | 1909 | bool vdd; |
adddaaf4 | 1910 | |
c695b6b6 VS |
1911 | if (!is_edp(intel_dp)) |
1912 | return; | |
1913 | ||
773538e8 | 1914 | pps_lock(intel_dp); |
c695b6b6 | 1915 | vdd = edp_panel_vdd_on(intel_dp); |
773538e8 | 1916 | pps_unlock(intel_dp); |
c695b6b6 | 1917 | |
e2c719b7 | 1918 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
3936fcf4 | 1919 | port_name(dp_to_dig_port(intel_dp)->port)); |
5d613501 JB |
1920 | } |
1921 | ||
4be73780 | 1922 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 1923 | { |
30add22d | 1924 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 1925 | struct drm_i915_private *dev_priv = to_i915(dev); |
be2c9196 VS |
1926 | struct intel_digital_port *intel_dig_port = |
1927 | dp_to_dig_port(intel_dp); | |
1928 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1929 | enum intel_display_power_domain power_domain; | |
5d613501 | 1930 | u32 pp; |
f0f59a00 | 1931 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
5d613501 | 1932 | |
e39b999a | 1933 | lockdep_assert_held(&dev_priv->pps_mutex); |
a0e99e68 | 1934 | |
15e899a0 | 1935 | WARN_ON(intel_dp->want_panel_vdd); |
4e6e1a54 | 1936 | |
15e899a0 | 1937 | if (!edp_have_panel_vdd(intel_dp)) |
be2c9196 | 1938 | return; |
b0665d57 | 1939 | |
3936fcf4 VS |
1940 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
1941 | port_name(intel_dig_port->port)); | |
bd943159 | 1942 | |
be2c9196 VS |
1943 | pp = ironlake_get_pp_control(intel_dp); |
1944 | pp &= ~EDP_FORCE_VDD; | |
453c5420 | 1945 | |
be2c9196 VS |
1946 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
1947 | pp_stat_reg = _pp_stat_reg(intel_dp); | |
99ea7127 | 1948 | |
be2c9196 VS |
1949 | I915_WRITE(pp_ctrl_reg, pp); |
1950 | POSTING_READ(pp_ctrl_reg); | |
90791a5c | 1951 | |
be2c9196 VS |
1952 | /* Make sure sequencer is idle before allowing subsequent activity */ |
1953 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
1954 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
e9cb81a2 | 1955 | |
5a162e22 | 1956 | if ((pp & PANEL_POWER_ON) == 0) |
d28d4731 | 1957 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
e9cb81a2 | 1958 | |
25f78f58 | 1959 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
be2c9196 | 1960 | intel_display_power_put(dev_priv, power_domain); |
bd943159 | 1961 | } |
5d613501 | 1962 | |
4be73780 | 1963 | static void edp_panel_vdd_work(struct work_struct *__work) |
bd943159 KP |
1964 | { |
1965 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
1966 | struct intel_dp, panel_vdd_work); | |
bd943159 | 1967 | |
773538e8 | 1968 | pps_lock(intel_dp); |
15e899a0 VS |
1969 | if (!intel_dp->want_panel_vdd) |
1970 | edp_panel_vdd_off_sync(intel_dp); | |
773538e8 | 1971 | pps_unlock(intel_dp); |
bd943159 KP |
1972 | } |
1973 | ||
aba86890 ID |
1974 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
1975 | { | |
1976 | unsigned long delay; | |
1977 | ||
1978 | /* | |
1979 | * Queue the timer to fire a long time from now (relative to the power | |
1980 | * down delay) to keep the panel power up across a sequence of | |
1981 | * operations. | |
1982 | */ | |
1983 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); | |
1984 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); | |
1985 | } | |
1986 | ||
951468f3 VS |
1987 | /* |
1988 | * Must be paired with edp_panel_vdd_on(). | |
1989 | * Must hold pps_mutex around the whole on/off sequence. | |
1990 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
1991 | */ | |
4be73780 | 1992 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 1993 | { |
fac5e23e | 1994 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
e39b999a VS |
1995 | |
1996 | lockdep_assert_held(&dev_priv->pps_mutex); | |
1997 | ||
97af61f5 KP |
1998 | if (!is_edp(intel_dp)) |
1999 | return; | |
5d613501 | 2000 | |
e2c719b7 | 2001 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
3936fcf4 | 2002 | port_name(dp_to_dig_port(intel_dp)->port)); |
f2e8b18a | 2003 | |
bd943159 KP |
2004 | intel_dp->want_panel_vdd = false; |
2005 | ||
aba86890 | 2006 | if (sync) |
4be73780 | 2007 | edp_panel_vdd_off_sync(intel_dp); |
aba86890 ID |
2008 | else |
2009 | edp_panel_vdd_schedule_off(intel_dp); | |
5d613501 JB |
2010 | } |
2011 | ||
9f0fb5be | 2012 | static void edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 2013 | { |
30add22d | 2014 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2015 | struct drm_i915_private *dev_priv = to_i915(dev); |
99ea7127 | 2016 | u32 pp; |
f0f59a00 | 2017 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2018 | |
9f0fb5be VS |
2019 | lockdep_assert_held(&dev_priv->pps_mutex); |
2020 | ||
97af61f5 | 2021 | if (!is_edp(intel_dp)) |
bd943159 | 2022 | return; |
99ea7127 | 2023 | |
3936fcf4 VS |
2024 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
2025 | port_name(dp_to_dig_port(intel_dp)->port)); | |
e39b999a | 2026 | |
e7a89ace VS |
2027 | if (WARN(edp_have_panel_power(intel_dp), |
2028 | "eDP port %c panel power already on\n", | |
2029 | port_name(dp_to_dig_port(intel_dp)->port))) | |
9f0fb5be | 2030 | return; |
9934c132 | 2031 | |
4be73780 | 2032 | wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 2033 | |
bf13e81b | 2034 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2035 | pp = ironlake_get_pp_control(intel_dp); |
05ce1a49 KP |
2036 | if (IS_GEN5(dev)) { |
2037 | /* ILK workaround: disable reset around power sequence */ | |
2038 | pp &= ~PANEL_POWER_RESET; | |
bf13e81b JN |
2039 | I915_WRITE(pp_ctrl_reg, pp); |
2040 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2041 | } |
37c6c9b0 | 2042 | |
5a162e22 | 2043 | pp |= PANEL_POWER_ON; |
99ea7127 KP |
2044 | if (!IS_GEN5(dev)) |
2045 | pp |= PANEL_POWER_RESET; | |
2046 | ||
453c5420 JB |
2047 | I915_WRITE(pp_ctrl_reg, pp); |
2048 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2049 | |
4be73780 | 2050 | wait_panel_on(intel_dp); |
dce56b3c | 2051 | intel_dp->last_power_on = jiffies; |
9934c132 | 2052 | |
05ce1a49 KP |
2053 | if (IS_GEN5(dev)) { |
2054 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ | |
bf13e81b JN |
2055 | I915_WRITE(pp_ctrl_reg, pp); |
2056 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2057 | } |
9f0fb5be | 2058 | } |
e39b999a | 2059 | |
9f0fb5be VS |
2060 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
2061 | { | |
2062 | if (!is_edp(intel_dp)) | |
2063 | return; | |
2064 | ||
2065 | pps_lock(intel_dp); | |
2066 | edp_panel_on(intel_dp); | |
773538e8 | 2067 | pps_unlock(intel_dp); |
9934c132 JB |
2068 | } |
2069 | ||
9f0fb5be VS |
2070 | |
2071 | static void edp_panel_off(struct intel_dp *intel_dp) | |
9934c132 | 2072 | { |
4e6e1a54 ID |
2073 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2074 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
30add22d | 2075 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2076 | struct drm_i915_private *dev_priv = to_i915(dev); |
4e6e1a54 | 2077 | enum intel_display_power_domain power_domain; |
99ea7127 | 2078 | u32 pp; |
f0f59a00 | 2079 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2080 | |
9f0fb5be VS |
2081 | lockdep_assert_held(&dev_priv->pps_mutex); |
2082 | ||
97af61f5 KP |
2083 | if (!is_edp(intel_dp)) |
2084 | return; | |
37c6c9b0 | 2085 | |
3936fcf4 VS |
2086 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
2087 | port_name(dp_to_dig_port(intel_dp)->port)); | |
37c6c9b0 | 2088 | |
3936fcf4 VS |
2089 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
2090 | port_name(dp_to_dig_port(intel_dp)->port)); | |
24f3e092 | 2091 | |
453c5420 | 2092 | pp = ironlake_get_pp_control(intel_dp); |
35a38556 DV |
2093 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
2094 | * panels get very unhappy and cease to work. */ | |
5a162e22 | 2095 | pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
b3064154 | 2096 | EDP_BLC_ENABLE); |
453c5420 | 2097 | |
bf13e81b | 2098 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2099 | |
849e39f5 PZ |
2100 | intel_dp->want_panel_vdd = false; |
2101 | ||
453c5420 JB |
2102 | I915_WRITE(pp_ctrl_reg, pp); |
2103 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2104 | |
d28d4731 | 2105 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
4be73780 | 2106 | wait_panel_off(intel_dp); |
849e39f5 PZ |
2107 | |
2108 | /* We got a reference when we enabled the VDD. */ | |
25f78f58 | 2109 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4e6e1a54 | 2110 | intel_display_power_put(dev_priv, power_domain); |
9f0fb5be | 2111 | } |
e39b999a | 2112 | |
9f0fb5be VS |
2113 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
2114 | { | |
2115 | if (!is_edp(intel_dp)) | |
2116 | return; | |
e39b999a | 2117 | |
9f0fb5be VS |
2118 | pps_lock(intel_dp); |
2119 | edp_panel_off(intel_dp); | |
773538e8 | 2120 | pps_unlock(intel_dp); |
9934c132 JB |
2121 | } |
2122 | ||
1250d107 JN |
2123 | /* Enable backlight in the panel power control. */ |
2124 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) | |
32f9d658 | 2125 | { |
da63a9f2 PZ |
2126 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2127 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 2128 | struct drm_i915_private *dev_priv = to_i915(dev); |
32f9d658 | 2129 | u32 pp; |
f0f59a00 | 2130 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2131 | |
01cb9ea6 JB |
2132 | /* |
2133 | * If we enable the backlight right away following a panel power | |
2134 | * on, we may see slight flicker as the panel syncs with the eDP | |
2135 | * link. So delay a bit to make sure the image is solid before | |
2136 | * allowing it to appear. | |
2137 | */ | |
4be73780 | 2138 | wait_backlight_on(intel_dp); |
e39b999a | 2139 | |
773538e8 | 2140 | pps_lock(intel_dp); |
e39b999a | 2141 | |
453c5420 | 2142 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2143 | pp |= EDP_BLC_ENABLE; |
453c5420 | 2144 | |
bf13e81b | 2145 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2146 | |
2147 | I915_WRITE(pp_ctrl_reg, pp); | |
2148 | POSTING_READ(pp_ctrl_reg); | |
e39b999a | 2149 | |
773538e8 | 2150 | pps_unlock(intel_dp); |
32f9d658 ZW |
2151 | } |
2152 | ||
1250d107 JN |
2153 | /* Enable backlight PWM and backlight PP control. */ |
2154 | void intel_edp_backlight_on(struct intel_dp *intel_dp) | |
2155 | { | |
2156 | if (!is_edp(intel_dp)) | |
2157 | return; | |
2158 | ||
2159 | DRM_DEBUG_KMS("\n"); | |
2160 | ||
2161 | intel_panel_enable_backlight(intel_dp->attached_connector); | |
2162 | _intel_edp_backlight_on(intel_dp); | |
2163 | } | |
2164 | ||
2165 | /* Disable backlight in the panel power control. */ | |
2166 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) | |
32f9d658 | 2167 | { |
30add22d | 2168 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2169 | struct drm_i915_private *dev_priv = to_i915(dev); |
32f9d658 | 2170 | u32 pp; |
f0f59a00 | 2171 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2172 | |
f01eca2e KP |
2173 | if (!is_edp(intel_dp)) |
2174 | return; | |
2175 | ||
773538e8 | 2176 | pps_lock(intel_dp); |
e39b999a | 2177 | |
453c5420 | 2178 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2179 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 2180 | |
bf13e81b | 2181 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2182 | |
2183 | I915_WRITE(pp_ctrl_reg, pp); | |
2184 | POSTING_READ(pp_ctrl_reg); | |
f7d2323c | 2185 | |
773538e8 | 2186 | pps_unlock(intel_dp); |
e39b999a VS |
2187 | |
2188 | intel_dp->last_backlight_off = jiffies; | |
f7d2323c | 2189 | edp_wait_backlight_off(intel_dp); |
1250d107 | 2190 | } |
f7d2323c | 2191 | |
1250d107 JN |
2192 | /* Disable backlight PP control and backlight PWM. */ |
2193 | void intel_edp_backlight_off(struct intel_dp *intel_dp) | |
2194 | { | |
2195 | if (!is_edp(intel_dp)) | |
2196 | return; | |
2197 | ||
2198 | DRM_DEBUG_KMS("\n"); | |
f7d2323c | 2199 | |
1250d107 | 2200 | _intel_edp_backlight_off(intel_dp); |
f7d2323c | 2201 | intel_panel_disable_backlight(intel_dp->attached_connector); |
32f9d658 | 2202 | } |
a4fc5ed6 | 2203 | |
73580fb7 JN |
2204 | /* |
2205 | * Hook for controlling the panel power control backlight through the bl_power | |
2206 | * sysfs attribute. Take care to handle multiple calls. | |
2207 | */ | |
2208 | static void intel_edp_backlight_power(struct intel_connector *connector, | |
2209 | bool enable) | |
2210 | { | |
2211 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); | |
e39b999a VS |
2212 | bool is_enabled; |
2213 | ||
773538e8 | 2214 | pps_lock(intel_dp); |
e39b999a | 2215 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
773538e8 | 2216 | pps_unlock(intel_dp); |
73580fb7 JN |
2217 | |
2218 | if (is_enabled == enable) | |
2219 | return; | |
2220 | ||
23ba9373 JN |
2221 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
2222 | enable ? "enable" : "disable"); | |
73580fb7 JN |
2223 | |
2224 | if (enable) | |
2225 | _intel_edp_backlight_on(intel_dp); | |
2226 | else | |
2227 | _intel_edp_backlight_off(intel_dp); | |
2228 | } | |
2229 | ||
64e1077a VS |
2230 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
2231 | { | |
2232 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
2233 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
2234 | bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; | |
2235 | ||
2236 | I915_STATE_WARN(cur_state != state, | |
2237 | "DP port %c state assertion failure (expected %s, current %s)\n", | |
2238 | port_name(dig_port->port), | |
87ad3212 | 2239 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2240 | } |
2241 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) | |
2242 | ||
2243 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) | |
2244 | { | |
2245 | bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; | |
2246 | ||
2247 | I915_STATE_WARN(cur_state != state, | |
2248 | "eDP PLL state assertion failure (expected %s, current %s)\n", | |
87ad3212 | 2249 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2250 | } |
2251 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) | |
2252 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) | |
2253 | ||
85cb48a1 ML |
2254 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp, |
2255 | struct intel_crtc_state *pipe_config) | |
d240f20f | 2256 | { |
85cb48a1 | 2257 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
64e1077a | 2258 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d240f20f | 2259 | |
64e1077a VS |
2260 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2261 | assert_dp_port_disabled(intel_dp); | |
2262 | assert_edp_pll_disabled(dev_priv); | |
2bd2ad64 | 2263 | |
abfce949 | 2264 | DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", |
85cb48a1 | 2265 | pipe_config->port_clock); |
abfce949 VS |
2266 | |
2267 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; | |
2268 | ||
85cb48a1 | 2269 | if (pipe_config->port_clock == 162000) |
abfce949 VS |
2270 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; |
2271 | else | |
2272 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
2273 | ||
2274 | I915_WRITE(DP_A, intel_dp->DP); | |
2275 | POSTING_READ(DP_A); | |
2276 | udelay(500); | |
2277 | ||
6b23f3e8 VS |
2278 | /* |
2279 | * [DevILK] Work around required when enabling DP PLL | |
2280 | * while a pipe is enabled going to FDI: | |
2281 | * 1. Wait for the start of vertical blank on the enabled pipe going to FDI | |
2282 | * 2. Program DP PLL enable | |
2283 | */ | |
2284 | if (IS_GEN5(dev_priv)) | |
91c8a326 | 2285 | intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe); |
6b23f3e8 | 2286 | |
0767935e | 2287 | intel_dp->DP |= DP_PLL_ENABLE; |
6fec7662 | 2288 | |
0767935e | 2289 | I915_WRITE(DP_A, intel_dp->DP); |
298b0b39 JB |
2290 | POSTING_READ(DP_A); |
2291 | udelay(200); | |
d240f20f JB |
2292 | } |
2293 | ||
2bd2ad64 | 2294 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
d240f20f | 2295 | { |
da63a9f2 | 2296 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
64e1077a VS |
2297 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
2298 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
d240f20f | 2299 | |
64e1077a VS |
2300 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2301 | assert_dp_port_disabled(intel_dp); | |
2302 | assert_edp_pll_enabled(dev_priv); | |
2bd2ad64 | 2303 | |
abfce949 VS |
2304 | DRM_DEBUG_KMS("disabling eDP PLL\n"); |
2305 | ||
6fec7662 | 2306 | intel_dp->DP &= ~DP_PLL_ENABLE; |
0767935e | 2307 | |
6fec7662 | 2308 | I915_WRITE(DP_A, intel_dp->DP); |
1af5fa1b | 2309 | POSTING_READ(DP_A); |
d240f20f JB |
2310 | udelay(200); |
2311 | } | |
2312 | ||
c7ad3810 | 2313 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 2314 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 JB |
2315 | { |
2316 | int ret, i; | |
2317 | ||
2318 | /* Should have a valid DPCD by this point */ | |
2319 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
2320 | return; | |
2321 | ||
2322 | if (mode != DRM_MODE_DPMS_ON) { | |
9d1a1031 JN |
2323 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2324 | DP_SET_POWER_D3); | |
c7ad3810 JB |
2325 | } else { |
2326 | /* | |
2327 | * When turning on, we need to retry for 1ms to give the sink | |
2328 | * time to wake up. | |
2329 | */ | |
2330 | for (i = 0; i < 3; i++) { | |
9d1a1031 JN |
2331 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2332 | DP_SET_POWER_D0); | |
c7ad3810 JB |
2333 | if (ret == 1) |
2334 | break; | |
2335 | msleep(1); | |
2336 | } | |
2337 | } | |
f9cac721 JN |
2338 | |
2339 | if (ret != 1) | |
2340 | DRM_DEBUG_KMS("failed to %s sink power state\n", | |
2341 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); | |
c7ad3810 JB |
2342 | } |
2343 | ||
19d8fe15 DV |
2344 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
2345 | enum pipe *pipe) | |
d240f20f | 2346 | { |
19d8fe15 | 2347 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 2348 | enum port port = dp_to_dig_port(intel_dp)->port; |
19d8fe15 | 2349 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2350 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d129bea ID |
2351 | enum intel_display_power_domain power_domain; |
2352 | u32 tmp; | |
6fa9a5ec | 2353 | bool ret; |
6d129bea ID |
2354 | |
2355 | power_domain = intel_display_port_power_domain(encoder); | |
6fa9a5ec | 2356 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
6d129bea ID |
2357 | return false; |
2358 | ||
6fa9a5ec ID |
2359 | ret = false; |
2360 | ||
6d129bea | 2361 | tmp = I915_READ(intel_dp->output_reg); |
19d8fe15 DV |
2362 | |
2363 | if (!(tmp & DP_PORT_EN)) | |
6fa9a5ec | 2364 | goto out; |
19d8fe15 | 2365 | |
39e5fa88 | 2366 | if (IS_GEN7(dev) && port == PORT_A) { |
19d8fe15 | 2367 | *pipe = PORT_TO_PIPE_CPT(tmp); |
39e5fa88 | 2368 | } else if (HAS_PCH_CPT(dev) && port != PORT_A) { |
adc289d7 | 2369 | enum pipe p; |
19d8fe15 | 2370 | |
adc289d7 VS |
2371 | for_each_pipe(dev_priv, p) { |
2372 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); | |
2373 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { | |
2374 | *pipe = p; | |
6fa9a5ec ID |
2375 | ret = true; |
2376 | ||
2377 | goto out; | |
19d8fe15 DV |
2378 | } |
2379 | } | |
19d8fe15 | 2380 | |
4a0833ec | 2381 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
f0f59a00 | 2382 | i915_mmio_reg_offset(intel_dp->output_reg)); |
39e5fa88 VS |
2383 | } else if (IS_CHERRYVIEW(dev)) { |
2384 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); | |
2385 | } else { | |
2386 | *pipe = PORT_TO_PIPE(tmp); | |
4a0833ec | 2387 | } |
d240f20f | 2388 | |
6fa9a5ec ID |
2389 | ret = true; |
2390 | ||
2391 | out: | |
2392 | intel_display_power_put(dev_priv, power_domain); | |
2393 | ||
2394 | return ret; | |
19d8fe15 | 2395 | } |
d240f20f | 2396 | |
045ac3b5 | 2397 | static void intel_dp_get_config(struct intel_encoder *encoder, |
5cec258b | 2398 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
2399 | { |
2400 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
045ac3b5 | 2401 | u32 tmp, flags = 0; |
63000ef6 | 2402 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2403 | struct drm_i915_private *dev_priv = to_i915(dev); |
63000ef6 XZ |
2404 | enum port port = dp_to_dig_port(intel_dp)->port; |
2405 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
045ac3b5 | 2406 | |
9ed109a7 | 2407 | tmp = I915_READ(intel_dp->output_reg); |
9fcb1704 JN |
2408 | |
2409 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; | |
9ed109a7 | 2410 | |
39e5fa88 | 2411 | if (HAS_PCH_CPT(dev) && port != PORT_A) { |
b81e34c2 VS |
2412 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
2413 | ||
2414 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
63000ef6 XZ |
2415 | flags |= DRM_MODE_FLAG_PHSYNC; |
2416 | else | |
2417 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2418 | |
b81e34c2 | 2419 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
63000ef6 XZ |
2420 | flags |= DRM_MODE_FLAG_PVSYNC; |
2421 | else | |
2422 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2423 | } else { | |
39e5fa88 | 2424 | if (tmp & DP_SYNC_HS_HIGH) |
63000ef6 XZ |
2425 | flags |= DRM_MODE_FLAG_PHSYNC; |
2426 | else | |
2427 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2428 | |
39e5fa88 | 2429 | if (tmp & DP_SYNC_VS_HIGH) |
63000ef6 XZ |
2430 | flags |= DRM_MODE_FLAG_PVSYNC; |
2431 | else | |
2432 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2433 | } | |
045ac3b5 | 2434 | |
2d112de7 | 2435 | pipe_config->base.adjusted_mode.flags |= flags; |
f1f644dc | 2436 | |
8c875fca | 2437 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) && |
666a4537 | 2438 | !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235) |
8c875fca VS |
2439 | pipe_config->limited_color_range = true; |
2440 | ||
90a6b7b0 VS |
2441 | pipe_config->lane_count = |
2442 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; | |
2443 | ||
eb14cb74 VS |
2444 | intel_dp_get_m_n(crtc, pipe_config); |
2445 | ||
18442d08 | 2446 | if (port == PORT_A) { |
b377e0df | 2447 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
f1f644dc JB |
2448 | pipe_config->port_clock = 162000; |
2449 | else | |
2450 | pipe_config->port_clock = 270000; | |
2451 | } | |
18442d08 | 2452 | |
e3b247da VS |
2453 | pipe_config->base.adjusted_mode.crtc_clock = |
2454 | intel_dotclock_calculate(pipe_config->port_clock, | |
2455 | &pipe_config->dp_m_n); | |
7f16e5c1 | 2456 | |
6aa23e65 JN |
2457 | if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp && |
2458 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { | |
c6cd2ee2 JN |
2459 | /* |
2460 | * This is a big fat ugly hack. | |
2461 | * | |
2462 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
2463 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
2464 | * unknown we fail to light up. Yet the same BIOS boots up with | |
2465 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
2466 | * max, not what it tells us to use. | |
2467 | * | |
2468 | * Note: This will still be broken if the eDP panel is not lit | |
2469 | * up by the BIOS, and thus we can't get the mode at module | |
2470 | * load. | |
2471 | */ | |
2472 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
6aa23e65 JN |
2473 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
2474 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; | |
c6cd2ee2 | 2475 | } |
045ac3b5 JB |
2476 | } |
2477 | ||
fd6bbda9 ML |
2478 | static void intel_disable_dp(struct intel_encoder *encoder, |
2479 | struct intel_crtc_state *old_crtc_state, | |
2480 | struct drm_connector_state *old_conn_state) | |
d240f20f | 2481 | { |
e8cb4558 | 2482 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
85cb48a1 | 2483 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
495a5bb8 | 2484 | |
85cb48a1 | 2485 | if (old_crtc_state->has_audio) |
495a5bb8 | 2486 | intel_audio_codec_disable(encoder); |
6cb49835 | 2487 | |
85cb48a1 | 2488 | if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv)) |
b32c6f48 RV |
2489 | intel_psr_disable(intel_dp); |
2490 | ||
6cb49835 DV |
2491 | /* Make sure the panel is off before trying to change the mode. But also |
2492 | * ensure that we have vdd while we switch off the panel. */ | |
24f3e092 | 2493 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 2494 | intel_edp_backlight_off(intel_dp); |
fdbc3b1f | 2495 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
4be73780 | 2496 | intel_edp_panel_off(intel_dp); |
3739850b | 2497 | |
08aff3fe | 2498 | /* disable the port before the pipe on g4x */ |
85cb48a1 | 2499 | if (INTEL_GEN(dev_priv) < 5) |
3739850b | 2500 | intel_dp_link_down(intel_dp); |
d240f20f JB |
2501 | } |
2502 | ||
fd6bbda9 ML |
2503 | static void ilk_post_disable_dp(struct intel_encoder *encoder, |
2504 | struct intel_crtc_state *old_crtc_state, | |
2505 | struct drm_connector_state *old_conn_state) | |
d240f20f | 2506 | { |
2bd2ad64 | 2507 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 2508 | enum port port = dp_to_dig_port(intel_dp)->port; |
2bd2ad64 | 2509 | |
49277c31 | 2510 | intel_dp_link_down(intel_dp); |
abfce949 VS |
2511 | |
2512 | /* Only ilk+ has port A */ | |
08aff3fe VS |
2513 | if (port == PORT_A) |
2514 | ironlake_edp_pll_off(intel_dp); | |
49277c31 VS |
2515 | } |
2516 | ||
fd6bbda9 ML |
2517 | static void vlv_post_disable_dp(struct intel_encoder *encoder, |
2518 | struct intel_crtc_state *old_crtc_state, | |
2519 | struct drm_connector_state *old_conn_state) | |
49277c31 VS |
2520 | { |
2521 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2522 | ||
2523 | intel_dp_link_down(intel_dp); | |
2bd2ad64 DV |
2524 | } |
2525 | ||
fd6bbda9 ML |
2526 | static void chv_post_disable_dp(struct intel_encoder *encoder, |
2527 | struct intel_crtc_state *old_crtc_state, | |
2528 | struct drm_connector_state *old_conn_state) | |
a8f327fb VS |
2529 | { |
2530 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2531 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2532 | struct drm_i915_private *dev_priv = to_i915(dev); |
97fd4d5c | 2533 | |
a8f327fb VS |
2534 | intel_dp_link_down(intel_dp); |
2535 | ||
2536 | mutex_lock(&dev_priv->sb_lock); | |
2537 | ||
2538 | /* Assert data lane reset */ | |
2539 | chv_data_lane_soft_reset(encoder, true); | |
580d3811 | 2540 | |
a580516d | 2541 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
2542 | } |
2543 | ||
7b13b58a VS |
2544 | static void |
2545 | _intel_dp_set_link_train(struct intel_dp *intel_dp, | |
2546 | uint32_t *DP, | |
2547 | uint8_t dp_train_pat) | |
2548 | { | |
2549 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2550 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 2551 | struct drm_i915_private *dev_priv = to_i915(dev); |
7b13b58a VS |
2552 | enum port port = intel_dig_port->port; |
2553 | ||
8b0878a0 PD |
2554 | if (dp_train_pat & DP_TRAINING_PATTERN_MASK) |
2555 | DRM_DEBUG_KMS("Using DP training pattern TPS%d\n", | |
2556 | dp_train_pat & DP_TRAINING_PATTERN_MASK); | |
2557 | ||
7b13b58a VS |
2558 | if (HAS_DDI(dev)) { |
2559 | uint32_t temp = I915_READ(DP_TP_CTL(port)); | |
2560 | ||
2561 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
2562 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
2563 | else | |
2564 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
2565 | ||
2566 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2567 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2568 | case DP_TRAINING_PATTERN_DISABLE: | |
2569 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; | |
2570 | ||
2571 | break; | |
2572 | case DP_TRAINING_PATTERN_1: | |
2573 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2574 | break; | |
2575 | case DP_TRAINING_PATTERN_2: | |
2576 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
2577 | break; | |
2578 | case DP_TRAINING_PATTERN_3: | |
2579 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
2580 | break; | |
2581 | } | |
2582 | I915_WRITE(DP_TP_CTL(port), temp); | |
2583 | ||
39e5fa88 VS |
2584 | } else if ((IS_GEN7(dev) && port == PORT_A) || |
2585 | (HAS_PCH_CPT(dev) && port != PORT_A)) { | |
7b13b58a VS |
2586 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2587 | ||
2588 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2589 | case DP_TRAINING_PATTERN_DISABLE: | |
2590 | *DP |= DP_LINK_TRAIN_OFF_CPT; | |
2591 | break; | |
2592 | case DP_TRAINING_PATTERN_1: | |
2593 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; | |
2594 | break; | |
2595 | case DP_TRAINING_PATTERN_2: | |
2596 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
2597 | break; | |
2598 | case DP_TRAINING_PATTERN_3: | |
8b0878a0 | 2599 | DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); |
7b13b58a VS |
2600 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2601 | break; | |
2602 | } | |
2603 | ||
2604 | } else { | |
2605 | if (IS_CHERRYVIEW(dev)) | |
2606 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; | |
2607 | else | |
2608 | *DP &= ~DP_LINK_TRAIN_MASK; | |
2609 | ||
2610 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2611 | case DP_TRAINING_PATTERN_DISABLE: | |
2612 | *DP |= DP_LINK_TRAIN_OFF; | |
2613 | break; | |
2614 | case DP_TRAINING_PATTERN_1: | |
2615 | *DP |= DP_LINK_TRAIN_PAT_1; | |
2616 | break; | |
2617 | case DP_TRAINING_PATTERN_2: | |
2618 | *DP |= DP_LINK_TRAIN_PAT_2; | |
2619 | break; | |
2620 | case DP_TRAINING_PATTERN_3: | |
2621 | if (IS_CHERRYVIEW(dev)) { | |
2622 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; | |
2623 | } else { | |
8b0878a0 | 2624 | DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); |
7b13b58a VS |
2625 | *DP |= DP_LINK_TRAIN_PAT_2; |
2626 | } | |
2627 | break; | |
2628 | } | |
2629 | } | |
2630 | } | |
2631 | ||
85cb48a1 ML |
2632 | static void intel_dp_enable_port(struct intel_dp *intel_dp, |
2633 | struct intel_crtc_state *old_crtc_state) | |
7b13b58a VS |
2634 | { |
2635 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 2636 | struct drm_i915_private *dev_priv = to_i915(dev); |
7b13b58a | 2637 | |
7b13b58a | 2638 | /* enable with pattern 1 (as per spec) */ |
7b13b58a | 2639 | |
8b0878a0 | 2640 | intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1); |
7b713f50 VS |
2641 | |
2642 | /* | |
2643 | * Magic for VLV/CHV. We _must_ first set up the register | |
2644 | * without actually enabling the port, and then do another | |
2645 | * write to enable the port. Otherwise link training will | |
2646 | * fail when the power sequencer is freshly used for this port. | |
2647 | */ | |
2648 | intel_dp->DP |= DP_PORT_EN; | |
85cb48a1 | 2649 | if (old_crtc_state->has_audio) |
6fec7662 | 2650 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
7b713f50 VS |
2651 | |
2652 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
2653 | POSTING_READ(intel_dp->output_reg); | |
580d3811 VS |
2654 | } |
2655 | ||
85cb48a1 ML |
2656 | static void intel_enable_dp(struct intel_encoder *encoder, |
2657 | struct intel_crtc_state *pipe_config) | |
d240f20f | 2658 | { |
e8cb4558 DV |
2659 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2660 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2661 | struct drm_i915_private *dev_priv = to_i915(dev); |
c1dec79a | 2662 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
e8cb4558 | 2663 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
d6fbdd15 | 2664 | enum pipe pipe = crtc->pipe; |
5d613501 | 2665 | |
0c33d8d7 DV |
2666 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2667 | return; | |
5d613501 | 2668 | |
093e3f13 VS |
2669 | pps_lock(intel_dp); |
2670 | ||
666a4537 | 2671 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
093e3f13 VS |
2672 | vlv_init_panel_power_sequencer(intel_dp); |
2673 | ||
85cb48a1 | 2674 | intel_dp_enable_port(intel_dp, pipe_config); |
093e3f13 VS |
2675 | |
2676 | edp_panel_vdd_on(intel_dp); | |
2677 | edp_panel_on(intel_dp); | |
2678 | edp_panel_vdd_off(intel_dp, true); | |
2679 | ||
2680 | pps_unlock(intel_dp); | |
2681 | ||
666a4537 | 2682 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e0fce78f VS |
2683 | unsigned int lane_mask = 0x0; |
2684 | ||
2685 | if (IS_CHERRYVIEW(dev)) | |
85cb48a1 | 2686 | lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); |
e0fce78f | 2687 | |
9b6de0a1 VS |
2688 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
2689 | lane_mask); | |
e0fce78f | 2690 | } |
61234fa5 | 2691 | |
f01eca2e | 2692 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 2693 | intel_dp_start_link_train(intel_dp); |
3ab9c637 | 2694 | intel_dp_stop_link_train(intel_dp); |
c1dec79a | 2695 | |
85cb48a1 | 2696 | if (pipe_config->has_audio) { |
c1dec79a | 2697 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
d6fbdd15 | 2698 | pipe_name(pipe)); |
c1dec79a JN |
2699 | intel_audio_codec_enable(encoder); |
2700 | } | |
ab1f90f9 | 2701 | } |
89b667f8 | 2702 | |
fd6bbda9 ML |
2703 | static void g4x_enable_dp(struct intel_encoder *encoder, |
2704 | struct intel_crtc_state *pipe_config, | |
2705 | struct drm_connector_state *conn_state) | |
ecff4f3b | 2706 | { |
828f5c6e JN |
2707 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2708 | ||
85cb48a1 | 2709 | intel_enable_dp(encoder, pipe_config); |
4be73780 | 2710 | intel_edp_backlight_on(intel_dp); |
ab1f90f9 | 2711 | } |
89b667f8 | 2712 | |
fd6bbda9 ML |
2713 | static void vlv_enable_dp(struct intel_encoder *encoder, |
2714 | struct intel_crtc_state *pipe_config, | |
2715 | struct drm_connector_state *conn_state) | |
ab1f90f9 | 2716 | { |
828f5c6e JN |
2717 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2718 | ||
4be73780 | 2719 | intel_edp_backlight_on(intel_dp); |
b32c6f48 | 2720 | intel_psr_enable(intel_dp); |
d240f20f JB |
2721 | } |
2722 | ||
fd6bbda9 ML |
2723 | static void g4x_pre_enable_dp(struct intel_encoder *encoder, |
2724 | struct intel_crtc_state *pipe_config, | |
2725 | struct drm_connector_state *conn_state) | |
ab1f90f9 JN |
2726 | { |
2727 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
d6fbdd15 | 2728 | enum port port = dp_to_dig_port(intel_dp)->port; |
ab1f90f9 | 2729 | |
85cb48a1 | 2730 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 2731 | |
d41f1efb | 2732 | /* Only ilk+ has port A */ |
abfce949 | 2733 | if (port == PORT_A) |
85cb48a1 | 2734 | ironlake_edp_pll_on(intel_dp, pipe_config); |
ab1f90f9 JN |
2735 | } |
2736 | ||
83b84597 VS |
2737 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
2738 | { | |
2739 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
fac5e23e | 2740 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
83b84597 | 2741 | enum pipe pipe = intel_dp->pps_pipe; |
44cb734c | 2742 | i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); |
83b84597 VS |
2743 | |
2744 | edp_panel_vdd_off_sync(intel_dp); | |
2745 | ||
2746 | /* | |
2747 | * VLV seems to get confused when multiple power seqeuencers | |
2748 | * have the same port selected (even if only one has power/vdd | |
2749 | * enabled). The failure manifests as vlv_wait_port_ready() failing | |
2750 | * CHV on the other hand doesn't seem to mind having the same port | |
2751 | * selected in multiple power seqeuencers, but let's clear the | |
2752 | * port select always when logically disconnecting a power sequencer | |
2753 | * from a port. | |
2754 | */ | |
2755 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", | |
2756 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
2757 | I915_WRITE(pp_on_reg, 0); | |
2758 | POSTING_READ(pp_on_reg); | |
2759 | ||
2760 | intel_dp->pps_pipe = INVALID_PIPE; | |
2761 | } | |
2762 | ||
a4a5d2f8 VS |
2763 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
2764 | enum pipe pipe) | |
2765 | { | |
fac5e23e | 2766 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 VS |
2767 | struct intel_encoder *encoder; |
2768 | ||
2769 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2770 | ||
ac3c12e4 VS |
2771 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
2772 | return; | |
2773 | ||
19c8054c | 2774 | for_each_intel_encoder(dev, encoder) { |
a4a5d2f8 | 2775 | struct intel_dp *intel_dp; |
773538e8 | 2776 | enum port port; |
a4a5d2f8 VS |
2777 | |
2778 | if (encoder->type != INTEL_OUTPUT_EDP) | |
2779 | continue; | |
2780 | ||
2781 | intel_dp = enc_to_intel_dp(&encoder->base); | |
773538e8 | 2782 | port = dp_to_dig_port(intel_dp)->port; |
a4a5d2f8 VS |
2783 | |
2784 | if (intel_dp->pps_pipe != pipe) | |
2785 | continue; | |
2786 | ||
2787 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", | |
773538e8 | 2788 | pipe_name(pipe), port_name(port)); |
a4a5d2f8 | 2789 | |
e02f9a06 | 2790 | WARN(encoder->base.crtc, |
034e43c6 VS |
2791 | "stealing pipe %c power sequencer from active eDP port %c\n", |
2792 | pipe_name(pipe), port_name(port)); | |
a4a5d2f8 | 2793 | |
a4a5d2f8 | 2794 | /* make sure vdd is off before we steal it */ |
83b84597 | 2795 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
2796 | } |
2797 | } | |
2798 | ||
2799 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) | |
2800 | { | |
2801 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2802 | struct intel_encoder *encoder = &intel_dig_port->base; | |
2803 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2804 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 | 2805 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
a4a5d2f8 VS |
2806 | |
2807 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2808 | ||
093e3f13 VS |
2809 | if (!is_edp(intel_dp)) |
2810 | return; | |
2811 | ||
a4a5d2f8 VS |
2812 | if (intel_dp->pps_pipe == crtc->pipe) |
2813 | return; | |
2814 | ||
2815 | /* | |
2816 | * If another power sequencer was being used on this | |
2817 | * port previously make sure to turn off vdd there while | |
2818 | * we still have control of it. | |
2819 | */ | |
2820 | if (intel_dp->pps_pipe != INVALID_PIPE) | |
83b84597 | 2821 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
2822 | |
2823 | /* | |
2824 | * We may be stealing the power | |
2825 | * sequencer from another port. | |
2826 | */ | |
2827 | vlv_steal_power_sequencer(dev, crtc->pipe); | |
2828 | ||
2829 | /* now it's all ours */ | |
2830 | intel_dp->pps_pipe = crtc->pipe; | |
2831 | ||
2832 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", | |
2833 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); | |
2834 | ||
2835 | /* init power sequencer on this pipe and port */ | |
36b5f425 VS |
2836 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
2837 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
a4a5d2f8 VS |
2838 | } |
2839 | ||
fd6bbda9 ML |
2840 | static void vlv_pre_enable_dp(struct intel_encoder *encoder, |
2841 | struct intel_crtc_state *pipe_config, | |
2842 | struct drm_connector_state *conn_state) | |
a4fc5ed6 | 2843 | { |
5f68c275 | 2844 | vlv_phy_pre_encoder_enable(encoder); |
ab1f90f9 | 2845 | |
85cb48a1 | 2846 | intel_enable_dp(encoder, pipe_config); |
89b667f8 JB |
2847 | } |
2848 | ||
fd6bbda9 ML |
2849 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder, |
2850 | struct intel_crtc_state *pipe_config, | |
2851 | struct drm_connector_state *conn_state) | |
89b667f8 | 2852 | { |
85cb48a1 | 2853 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 2854 | |
6da2e616 | 2855 | vlv_phy_pre_pll_enable(encoder); |
a4fc5ed6 KP |
2856 | } |
2857 | ||
fd6bbda9 ML |
2858 | static void chv_pre_enable_dp(struct intel_encoder *encoder, |
2859 | struct intel_crtc_state *pipe_config, | |
2860 | struct drm_connector_state *conn_state) | |
e4a1d846 | 2861 | { |
e7d2a717 | 2862 | chv_phy_pre_encoder_enable(encoder); |
e4a1d846 | 2863 | |
85cb48a1 | 2864 | intel_enable_dp(encoder, pipe_config); |
b0b33846 VS |
2865 | |
2866 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 2867 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
2868 | } |
2869 | ||
fd6bbda9 ML |
2870 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder, |
2871 | struct intel_crtc_state *pipe_config, | |
2872 | struct drm_connector_state *conn_state) | |
9197c88b | 2873 | { |
85cb48a1 | 2874 | intel_dp_prepare(encoder, pipe_config); |
625695f8 | 2875 | |
419b1b7a | 2876 | chv_phy_pre_pll_enable(encoder); |
9197c88b VS |
2877 | } |
2878 | ||
fd6bbda9 ML |
2879 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder, |
2880 | struct intel_crtc_state *pipe_config, | |
2881 | struct drm_connector_state *conn_state) | |
d6db995f | 2882 | { |
204970b5 | 2883 | chv_phy_post_pll_disable(encoder); |
d6db995f VS |
2884 | } |
2885 | ||
a4fc5ed6 KP |
2886 | /* |
2887 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
2888 | * link status information | |
2889 | */ | |
94223d04 | 2890 | bool |
93f62dad | 2891 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 2892 | { |
9f085ebb L |
2893 | return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, |
2894 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; | |
a4fc5ed6 KP |
2895 | } |
2896 | ||
1100244e | 2897 | /* These are source-specific values. */ |
94223d04 | 2898 | uint8_t |
1a2eb460 | 2899 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 2900 | { |
30add22d | 2901 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2902 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc7d38a4 | 2903 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 2904 | |
9314726b VK |
2905 | if (IS_BROXTON(dev)) |
2906 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; | |
2907 | else if (INTEL_INFO(dev)->gen >= 9) { | |
06411f08 | 2908 | if (dev_priv->vbt.edp.low_vswing && port == PORT_A) |
7ad14a29 | 2909 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
5a9d1f1a | 2910 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
666a4537 | 2911 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
bd60018a | 2912 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
bc7d38a4 | 2913 | else if (IS_GEN7(dev) && port == PORT_A) |
bd60018a | 2914 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
bc7d38a4 | 2915 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
bd60018a | 2916 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
1a2eb460 | 2917 | else |
bd60018a | 2918 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
1a2eb460 KP |
2919 | } |
2920 | ||
94223d04 | 2921 | uint8_t |
1a2eb460 KP |
2922 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
2923 | { | |
30add22d | 2924 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
bc7d38a4 | 2925 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 2926 | |
5a9d1f1a DL |
2927 | if (INTEL_INFO(dev)->gen >= 9) { |
2928 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
2929 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: | |
2930 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
2931 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2932 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2933 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2934 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
7ad14a29 SJ |
2935 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
2936 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
5a9d1f1a DL |
2937 | default: |
2938 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
2939 | } | |
2940 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
d6c0d722 | 2941 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
2942 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2943 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
2944 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2945 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2946 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2947 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
2948 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
d6c0d722 | 2949 | default: |
bd60018a | 2950 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
d6c0d722 | 2951 | } |
666a4537 | 2952 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e2fa6fba | 2953 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
2954 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2955 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
2956 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2957 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2958 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2959 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
2960 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
e2fa6fba | 2961 | default: |
bd60018a | 2962 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
e2fa6fba | 2963 | } |
bc7d38a4 | 2964 | } else if (IS_GEN7(dev) && port == PORT_A) { |
1a2eb460 | 2965 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
2966 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2967 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2968 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2969 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2970 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
1a2eb460 | 2971 | default: |
bd60018a | 2972 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 KP |
2973 | } |
2974 | } else { | |
2975 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a SJ |
2976 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
2977 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2978 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
2979 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
2980 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
2981 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
2982 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
1a2eb460 | 2983 | default: |
bd60018a | 2984 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 | 2985 | } |
a4fc5ed6 KP |
2986 | } |
2987 | } | |
2988 | ||
5829975c | 2989 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
e2fa6fba | 2990 | { |
53d98725 | 2991 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
e2fa6fba P |
2992 | unsigned long demph_reg_value, preemph_reg_value, |
2993 | uniqtranscale_reg_value; | |
2994 | uint8_t train_set = intel_dp->train_set[0]; | |
e2fa6fba P |
2995 | |
2996 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 2997 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e2fa6fba P |
2998 | preemph_reg_value = 0x0004000; |
2999 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3000 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3001 | demph_reg_value = 0x2B405555; |
3002 | uniqtranscale_reg_value = 0x552AB83A; | |
3003 | break; | |
bd60018a | 3004 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3005 | demph_reg_value = 0x2B404040; |
3006 | uniqtranscale_reg_value = 0x5548B83A; | |
3007 | break; | |
bd60018a | 3008 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3009 | demph_reg_value = 0x2B245555; |
3010 | uniqtranscale_reg_value = 0x5560B83A; | |
3011 | break; | |
bd60018a | 3012 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e2fa6fba P |
3013 | demph_reg_value = 0x2B405555; |
3014 | uniqtranscale_reg_value = 0x5598DA3A; | |
3015 | break; | |
3016 | default: | |
3017 | return 0; | |
3018 | } | |
3019 | break; | |
bd60018a | 3020 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e2fa6fba P |
3021 | preemph_reg_value = 0x0002000; |
3022 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3023 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3024 | demph_reg_value = 0x2B404040; |
3025 | uniqtranscale_reg_value = 0x5552B83A; | |
3026 | break; | |
bd60018a | 3027 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3028 | demph_reg_value = 0x2B404848; |
3029 | uniqtranscale_reg_value = 0x5580B83A; | |
3030 | break; | |
bd60018a | 3031 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3032 | demph_reg_value = 0x2B404040; |
3033 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3034 | break; | |
3035 | default: | |
3036 | return 0; | |
3037 | } | |
3038 | break; | |
bd60018a | 3039 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e2fa6fba P |
3040 | preemph_reg_value = 0x0000000; |
3041 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3042 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3043 | demph_reg_value = 0x2B305555; |
3044 | uniqtranscale_reg_value = 0x5570B83A; | |
3045 | break; | |
bd60018a | 3046 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3047 | demph_reg_value = 0x2B2B4040; |
3048 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3049 | break; | |
3050 | default: | |
3051 | return 0; | |
3052 | } | |
3053 | break; | |
bd60018a | 3054 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e2fa6fba P |
3055 | preemph_reg_value = 0x0006000; |
3056 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3057 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3058 | demph_reg_value = 0x1B405555; |
3059 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3060 | break; | |
3061 | default: | |
3062 | return 0; | |
3063 | } | |
3064 | break; | |
3065 | default: | |
3066 | return 0; | |
3067 | } | |
3068 | ||
53d98725 ACO |
3069 | vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value, |
3070 | uniqtranscale_reg_value, 0); | |
e2fa6fba P |
3071 | |
3072 | return 0; | |
3073 | } | |
3074 | ||
5829975c | 3075 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
e4a1d846 | 3076 | { |
b7fa22d8 ACO |
3077 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3078 | u32 deemph_reg_value, margin_reg_value; | |
3079 | bool uniq_trans_scale = false; | |
e4a1d846 | 3080 | uint8_t train_set = intel_dp->train_set[0]; |
e4a1d846 CML |
3081 | |
3082 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3083 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e4a1d846 | 3084 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3085 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3086 | deemph_reg_value = 128; |
3087 | margin_reg_value = 52; | |
3088 | break; | |
bd60018a | 3089 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3090 | deemph_reg_value = 128; |
3091 | margin_reg_value = 77; | |
3092 | break; | |
bd60018a | 3093 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3094 | deemph_reg_value = 128; |
3095 | margin_reg_value = 102; | |
3096 | break; | |
bd60018a | 3097 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e4a1d846 CML |
3098 | deemph_reg_value = 128; |
3099 | margin_reg_value = 154; | |
b7fa22d8 | 3100 | uniq_trans_scale = true; |
e4a1d846 CML |
3101 | break; |
3102 | default: | |
3103 | return 0; | |
3104 | } | |
3105 | break; | |
bd60018a | 3106 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e4a1d846 | 3107 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3108 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3109 | deemph_reg_value = 85; |
3110 | margin_reg_value = 78; | |
3111 | break; | |
bd60018a | 3112 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3113 | deemph_reg_value = 85; |
3114 | margin_reg_value = 116; | |
3115 | break; | |
bd60018a | 3116 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3117 | deemph_reg_value = 85; |
3118 | margin_reg_value = 154; | |
3119 | break; | |
3120 | default: | |
3121 | return 0; | |
3122 | } | |
3123 | break; | |
bd60018a | 3124 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e4a1d846 | 3125 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3126 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3127 | deemph_reg_value = 64; |
3128 | margin_reg_value = 104; | |
3129 | break; | |
bd60018a | 3130 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3131 | deemph_reg_value = 64; |
3132 | margin_reg_value = 154; | |
3133 | break; | |
3134 | default: | |
3135 | return 0; | |
3136 | } | |
3137 | break; | |
bd60018a | 3138 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e4a1d846 | 3139 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3140 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3141 | deemph_reg_value = 43; |
3142 | margin_reg_value = 154; | |
3143 | break; | |
3144 | default: | |
3145 | return 0; | |
3146 | } | |
3147 | break; | |
3148 | default: | |
3149 | return 0; | |
3150 | } | |
3151 | ||
b7fa22d8 ACO |
3152 | chv_set_phy_signal_level(encoder, deemph_reg_value, |
3153 | margin_reg_value, uniq_trans_scale); | |
e4a1d846 CML |
3154 | |
3155 | return 0; | |
3156 | } | |
3157 | ||
a4fc5ed6 | 3158 | static uint32_t |
5829975c | 3159 | gen4_signal_levels(uint8_t train_set) |
a4fc5ed6 | 3160 | { |
3cf2efb1 | 3161 | uint32_t signal_levels = 0; |
a4fc5ed6 | 3162 | |
3cf2efb1 | 3163 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3164 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
a4fc5ed6 KP |
3165 | default: |
3166 | signal_levels |= DP_VOLTAGE_0_4; | |
3167 | break; | |
bd60018a | 3168 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
a4fc5ed6 KP |
3169 | signal_levels |= DP_VOLTAGE_0_6; |
3170 | break; | |
bd60018a | 3171 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
a4fc5ed6 KP |
3172 | signal_levels |= DP_VOLTAGE_0_8; |
3173 | break; | |
bd60018a | 3174 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
a4fc5ed6 KP |
3175 | signal_levels |= DP_VOLTAGE_1_2; |
3176 | break; | |
3177 | } | |
3cf2efb1 | 3178 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
bd60018a | 3179 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
a4fc5ed6 KP |
3180 | default: |
3181 | signal_levels |= DP_PRE_EMPHASIS_0; | |
3182 | break; | |
bd60018a | 3183 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
a4fc5ed6 KP |
3184 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
3185 | break; | |
bd60018a | 3186 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
a4fc5ed6 KP |
3187 | signal_levels |= DP_PRE_EMPHASIS_6; |
3188 | break; | |
bd60018a | 3189 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
a4fc5ed6 KP |
3190 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
3191 | break; | |
3192 | } | |
3193 | return signal_levels; | |
3194 | } | |
3195 | ||
e3421a18 ZW |
3196 | /* Gen6's DP voltage swing and pre-emphasis control */ |
3197 | static uint32_t | |
5829975c | 3198 | gen6_edp_signal_levels(uint8_t train_set) |
e3421a18 | 3199 | { |
3c5a62b5 YL |
3200 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3201 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3202 | switch (signal_levels) { | |
bd60018a SJ |
3203 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3204 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3205 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
bd60018a | 3206 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3c5a62b5 | 3207 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
bd60018a SJ |
3208 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3209 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
3c5a62b5 | 3210 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
bd60018a SJ |
3211 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3212 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
3c5a62b5 | 3213 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
bd60018a SJ |
3214 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3215 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3216 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
e3421a18 | 3217 | default: |
3c5a62b5 YL |
3218 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3219 | "0x%x\n", signal_levels); | |
3220 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
3221 | } |
3222 | } | |
3223 | ||
1a2eb460 KP |
3224 | /* Gen7's DP voltage swing and pre-emphasis control */ |
3225 | static uint32_t | |
5829975c | 3226 | gen7_edp_signal_levels(uint8_t train_set) |
1a2eb460 KP |
3227 | { |
3228 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
3229 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3230 | switch (signal_levels) { | |
bd60018a | 3231 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3232 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
bd60018a | 3233 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 | 3234 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
bd60018a | 3235 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
1a2eb460 KP |
3236 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
3237 | ||
bd60018a | 3238 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3239 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
bd60018a | 3240 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3241 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
3242 | ||
bd60018a | 3243 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3244 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
bd60018a | 3245 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3246 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
3247 | ||
3248 | default: | |
3249 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
3250 | "0x%x\n", signal_levels); | |
3251 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
3252 | } | |
3253 | } | |
3254 | ||
94223d04 | 3255 | void |
f4eb692e | 3256 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
f0a3424e PZ |
3257 | { |
3258 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bc7d38a4 | 3259 | enum port port = intel_dig_port->port; |
f0a3424e | 3260 | struct drm_device *dev = intel_dig_port->base.base.dev; |
b905a915 | 3261 | struct drm_i915_private *dev_priv = to_i915(dev); |
f8896f5d | 3262 | uint32_t signal_levels, mask = 0; |
f0a3424e PZ |
3263 | uint8_t train_set = intel_dp->train_set[0]; |
3264 | ||
f8896f5d DW |
3265 | if (HAS_DDI(dev)) { |
3266 | signal_levels = ddi_signal_levels(intel_dp); | |
3267 | ||
3268 | if (IS_BROXTON(dev)) | |
3269 | signal_levels = 0; | |
3270 | else | |
3271 | mask = DDI_BUF_EMP_MASK; | |
e4a1d846 | 3272 | } else if (IS_CHERRYVIEW(dev)) { |
5829975c | 3273 | signal_levels = chv_signal_levels(intel_dp); |
e2fa6fba | 3274 | } else if (IS_VALLEYVIEW(dev)) { |
5829975c | 3275 | signal_levels = vlv_signal_levels(intel_dp); |
bc7d38a4 | 3276 | } else if (IS_GEN7(dev) && port == PORT_A) { |
5829975c | 3277 | signal_levels = gen7_edp_signal_levels(train_set); |
f0a3424e | 3278 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
bc7d38a4 | 3279 | } else if (IS_GEN6(dev) && port == PORT_A) { |
5829975c | 3280 | signal_levels = gen6_edp_signal_levels(train_set); |
f0a3424e PZ |
3281 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
3282 | } else { | |
5829975c | 3283 | signal_levels = gen4_signal_levels(train_set); |
f0a3424e PZ |
3284 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
3285 | } | |
3286 | ||
96fb9f9b VK |
3287 | if (mask) |
3288 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); | |
3289 | ||
3290 | DRM_DEBUG_KMS("Using vswing level %d\n", | |
3291 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); | |
3292 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", | |
3293 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> | |
3294 | DP_TRAIN_PRE_EMPHASIS_SHIFT); | |
f0a3424e | 3295 | |
f4eb692e | 3296 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
b905a915 ACO |
3297 | |
3298 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
3299 | POSTING_READ(intel_dp->output_reg); | |
f0a3424e PZ |
3300 | } |
3301 | ||
94223d04 | 3302 | void |
e9c176d5 ACO |
3303 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
3304 | uint8_t dp_train_pat) | |
a4fc5ed6 | 3305 | { |
174edf1f | 3306 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
90a6b7b0 VS |
3307 | struct drm_i915_private *dev_priv = |
3308 | to_i915(intel_dig_port->base.base.dev); | |
a4fc5ed6 | 3309 | |
f4eb692e | 3310 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
47ea7542 | 3311 | |
f4eb692e | 3312 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
ea5b213a | 3313 | POSTING_READ(intel_dp->output_reg); |
e9c176d5 ACO |
3314 | } |
3315 | ||
94223d04 | 3316 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3ab9c637 ID |
3317 | { |
3318 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3319 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 3320 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ab9c637 ID |
3321 | enum port port = intel_dig_port->port; |
3322 | uint32_t val; | |
3323 | ||
3324 | if (!HAS_DDI(dev)) | |
3325 | return; | |
3326 | ||
3327 | val = I915_READ(DP_TP_CTL(port)); | |
3328 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
3329 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
3330 | I915_WRITE(DP_TP_CTL(port), val); | |
3331 | ||
3332 | /* | |
3333 | * On PORT_A we can have only eDP in SST mode. There the only reason | |
3334 | * we need to set idle transmission mode is to work around a HW issue | |
3335 | * where we enable the pipe while not in idle link-training mode. | |
3336 | * In this case there is requirement to wait for a minimum number of | |
3337 | * idle patterns to be sent. | |
3338 | */ | |
3339 | if (port == PORT_A) | |
3340 | return; | |
3341 | ||
a767017f CW |
3342 | if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port), |
3343 | DP_TP_STATUS_IDLE_DONE, | |
3344 | DP_TP_STATUS_IDLE_DONE, | |
3345 | 1)) | |
3ab9c637 ID |
3346 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
3347 | } | |
3348 | ||
a4fc5ed6 | 3349 | static void |
ea5b213a | 3350 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 3351 | { |
da63a9f2 | 3352 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1612c8bd | 3353 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
bc7d38a4 | 3354 | enum port port = intel_dig_port->port; |
da63a9f2 | 3355 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 3356 | struct drm_i915_private *dev_priv = to_i915(dev); |
ea5b213a | 3357 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 3358 | |
bc76e320 | 3359 | if (WARN_ON(HAS_DDI(dev))) |
c19b0669 PZ |
3360 | return; |
3361 | ||
0c33d8d7 | 3362 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
1b39d6f3 CW |
3363 | return; |
3364 | ||
28c97730 | 3365 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 3366 | |
39e5fa88 VS |
3367 | if ((IS_GEN7(dev) && port == PORT_A) || |
3368 | (HAS_PCH_CPT(dev) && port != PORT_A)) { | |
e3421a18 | 3369 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1612c8bd | 3370 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
e3421a18 | 3371 | } else { |
aad3d14d VS |
3372 | if (IS_CHERRYVIEW(dev)) |
3373 | DP &= ~DP_LINK_TRAIN_MASK_CHV; | |
3374 | else | |
3375 | DP &= ~DP_LINK_TRAIN_MASK; | |
1612c8bd | 3376 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
e3421a18 | 3377 | } |
1612c8bd | 3378 | I915_WRITE(intel_dp->output_reg, DP); |
fe255d00 | 3379 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 3380 | |
1612c8bd VS |
3381 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
3382 | I915_WRITE(intel_dp->output_reg, DP); | |
3383 | POSTING_READ(intel_dp->output_reg); | |
3384 | ||
3385 | /* | |
3386 | * HW workaround for IBX, we need to move the port | |
3387 | * to transcoder A after disabling it to allow the | |
3388 | * matching HDMI port to be enabled on transcoder A. | |
3389 | */ | |
3390 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) { | |
0c241d5b VS |
3391 | /* |
3392 | * We get CPU/PCH FIFO underruns on the other pipe when | |
3393 | * doing the workaround. Sweep them under the rug. | |
3394 | */ | |
3395 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3396 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3397 | ||
1612c8bd VS |
3398 | /* always enable with pattern 1 (as per spec) */ |
3399 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); | |
3400 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; | |
3401 | I915_WRITE(intel_dp->output_reg, DP); | |
3402 | POSTING_READ(intel_dp->output_reg); | |
3403 | ||
3404 | DP &= ~DP_PORT_EN; | |
5bddd17f | 3405 | I915_WRITE(intel_dp->output_reg, DP); |
0ca09685 | 3406 | POSTING_READ(intel_dp->output_reg); |
0c241d5b | 3407 | |
91c8a326 | 3408 | intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A); |
0c241d5b VS |
3409 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
3410 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
5bddd17f EA |
3411 | } |
3412 | ||
f01eca2e | 3413 | msleep(intel_dp->panel_power_down_delay); |
6fec7662 VS |
3414 | |
3415 | intel_dp->DP = DP; | |
a4fc5ed6 KP |
3416 | } |
3417 | ||
26d61aad | 3418 | static bool |
fe5a66f9 | 3419 | intel_dp_read_dpcd(struct intel_dp *intel_dp) |
92fd8fd1 | 3420 | { |
9f085ebb L |
3421 | if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3422 | sizeof(intel_dp->dpcd)) < 0) | |
edb39244 | 3423 | return false; /* aux transfer failed */ |
92fd8fd1 | 3424 | |
a8e98153 | 3425 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
577c7a50 | 3426 | |
fe5a66f9 VS |
3427 | return intel_dp->dpcd[DP_DPCD_REV] != 0; |
3428 | } | |
edb39244 | 3429 | |
fe5a66f9 VS |
3430 | static bool |
3431 | intel_edp_init_dpcd(struct intel_dp *intel_dp) | |
3432 | { | |
3433 | struct drm_i915_private *dev_priv = | |
3434 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
30d9aa42 | 3435 | |
fe5a66f9 VS |
3436 | /* this function is meant to be called only once */ |
3437 | WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0); | |
30d9aa42 | 3438 | |
fe5a66f9 | 3439 | if (!intel_dp_read_dpcd(intel_dp)) |
30d9aa42 SS |
3440 | return false; |
3441 | ||
fe5a66f9 VS |
3442 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
3443 | dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
3444 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; | |
474d1ec4 | 3445 | |
fe5a66f9 VS |
3446 | /* Check if the panel supports PSR */ |
3447 | drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, | |
3448 | intel_dp->psr_dpcd, | |
3449 | sizeof(intel_dp->psr_dpcd)); | |
3450 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { | |
3451 | dev_priv->psr.sink_support = true; | |
3452 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); | |
3453 | } | |
86ee27b5 | 3454 | |
fe5a66f9 VS |
3455 | if (INTEL_GEN(dev_priv) >= 9 && |
3456 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { | |
3457 | uint8_t frame_sync_cap; | |
3458 | ||
3459 | dev_priv->psr.sink_support = true; | |
3460 | drm_dp_dpcd_read(&intel_dp->aux, | |
3461 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, | |
3462 | &frame_sync_cap, 1); | |
3463 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; | |
3464 | /* PSR2 needs frame sync as well */ | |
3465 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; | |
3466 | DRM_DEBUG_KMS("PSR2 %s on sink", | |
3467 | dev_priv->psr.psr2_support ? "supported" : "not supported"); | |
50003939 JN |
3468 | } |
3469 | ||
fe5a66f9 VS |
3470 | /* Read the eDP Display control capabilities registers */ |
3471 | if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && | |
3472 | drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, | |
3473 | intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd) == | |
3474 | sizeof(intel_dp->edp_dpcd))) | |
3475 | DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd), | |
3476 | intel_dp->edp_dpcd); | |
06ea66b6 | 3477 | |
fc0f8e25 | 3478 | /* Intermediate frequency support */ |
fe5a66f9 | 3479 | if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */ |
94ca719e | 3480 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
ea2d8a42 VS |
3481 | int i; |
3482 | ||
9f085ebb L |
3483 | drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, |
3484 | sink_rates, sizeof(sink_rates)); | |
ea2d8a42 | 3485 | |
94ca719e VS |
3486 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
3487 | int val = le16_to_cpu(sink_rates[i]); | |
ea2d8a42 VS |
3488 | |
3489 | if (val == 0) | |
3490 | break; | |
3491 | ||
af77b974 SJ |
3492 | /* Value read is in kHz while drm clock is saved in deca-kHz */ |
3493 | intel_dp->sink_rates[i] = (val * 200) / 10; | |
ea2d8a42 | 3494 | } |
94ca719e | 3495 | intel_dp->num_sink_rates = i; |
fc0f8e25 | 3496 | } |
0336400e | 3497 | |
fe5a66f9 VS |
3498 | return true; |
3499 | } | |
3500 | ||
3501 | ||
3502 | static bool | |
3503 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
3504 | { | |
3505 | if (!intel_dp_read_dpcd(intel_dp)) | |
3506 | return false; | |
3507 | ||
3508 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT, | |
3509 | &intel_dp->sink_count, 1) < 0) | |
3510 | return false; | |
3511 | ||
3512 | /* | |
3513 | * Sink count can change between short pulse hpd hence | |
3514 | * a member variable in intel_dp will track any changes | |
3515 | * between short pulse interrupts. | |
3516 | */ | |
3517 | intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count); | |
3518 | ||
3519 | /* | |
3520 | * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that | |
3521 | * a dongle is present but no display. Unless we require to know | |
3522 | * if a dongle is present or not, we don't need to update | |
3523 | * downstream port information. So, an early return here saves | |
3524 | * time from performing other operations which are not required. | |
3525 | */ | |
3526 | if (!is_edp(intel_dp) && !intel_dp->sink_count) | |
3527 | return false; | |
0336400e | 3528 | |
edb39244 AJ |
3529 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
3530 | DP_DWN_STRM_PORT_PRESENT)) | |
3531 | return true; /* native DP sink */ | |
3532 | ||
3533 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
3534 | return true; /* no per-port downstream info */ | |
3535 | ||
9f085ebb L |
3536 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
3537 | intel_dp->downstream_ports, | |
3538 | DP_MAX_DOWNSTREAM_PORTS) < 0) | |
edb39244 AJ |
3539 | return false; /* downstream port status fetch failed */ |
3540 | ||
3541 | return true; | |
92fd8fd1 KP |
3542 | } |
3543 | ||
0d198328 AJ |
3544 | static void |
3545 | intel_dp_probe_oui(struct intel_dp *intel_dp) | |
3546 | { | |
3547 | u8 buf[3]; | |
3548 | ||
3549 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) | |
3550 | return; | |
3551 | ||
9f085ebb | 3552 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
0d198328 AJ |
3553 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
3554 | buf[0], buf[1], buf[2]); | |
3555 | ||
9f085ebb | 3556 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
0d198328 AJ |
3557 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
3558 | buf[0], buf[1], buf[2]); | |
3559 | } | |
3560 | ||
0e32b39c | 3561 | static bool |
c4e3170a | 3562 | intel_dp_can_mst(struct intel_dp *intel_dp) |
0e32b39c DA |
3563 | { |
3564 | u8 buf[1]; | |
3565 | ||
7cc96139 NS |
3566 | if (!i915.enable_dp_mst) |
3567 | return false; | |
3568 | ||
0e32b39c DA |
3569 | if (!intel_dp->can_mst) |
3570 | return false; | |
3571 | ||
3572 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) | |
3573 | return false; | |
3574 | ||
c4e3170a VS |
3575 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1) |
3576 | return false; | |
0e32b39c | 3577 | |
c4e3170a VS |
3578 | return buf[0] & DP_MST_CAP; |
3579 | } | |
3580 | ||
3581 | static void | |
3582 | intel_dp_configure_mst(struct intel_dp *intel_dp) | |
3583 | { | |
3584 | if (!i915.enable_dp_mst) | |
3585 | return; | |
3586 | ||
3587 | if (!intel_dp->can_mst) | |
3588 | return; | |
3589 | ||
3590 | intel_dp->is_mst = intel_dp_can_mst(intel_dp); | |
3591 | ||
3592 | if (intel_dp->is_mst) | |
3593 | DRM_DEBUG_KMS("Sink is MST capable\n"); | |
3594 | else | |
3595 | DRM_DEBUG_KMS("Sink is not MST capable\n"); | |
3596 | ||
3597 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
3598 | intel_dp->is_mst); | |
0e32b39c DA |
3599 | } |
3600 | ||
e5a1cab5 | 3601 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
d2e216d0 | 3602 | { |
082dcc7c | 3603 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
d72f9d91 | 3604 | struct drm_device *dev = dig_port->base.base.dev; |
082dcc7c | 3605 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
ad9dc91b | 3606 | u8 buf; |
e5a1cab5 | 3607 | int ret = 0; |
c6297843 RV |
3608 | int count = 0; |
3609 | int attempts = 10; | |
d2e216d0 | 3610 | |
082dcc7c RV |
3611 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
3612 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); | |
e5a1cab5 RV |
3613 | ret = -EIO; |
3614 | goto out; | |
4373f0f2 PZ |
3615 | } |
3616 | ||
082dcc7c | 3617 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
e5a1cab5 | 3618 | buf & ~DP_TEST_SINK_START) < 0) { |
082dcc7c | 3619 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
e5a1cab5 RV |
3620 | ret = -EIO; |
3621 | goto out; | |
3622 | } | |
d2e216d0 | 3623 | |
c6297843 RV |
3624 | do { |
3625 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
3626 | ||
3627 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
3628 | DP_TEST_SINK_MISC, &buf) < 0) { | |
3629 | ret = -EIO; | |
3630 | goto out; | |
3631 | } | |
3632 | count = buf & DP_TEST_COUNT_MASK; | |
3633 | } while (--attempts && count); | |
3634 | ||
3635 | if (attempts == 0) { | |
dc5a9037 | 3636 | DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); |
c6297843 RV |
3637 | ret = -ETIMEDOUT; |
3638 | } | |
3639 | ||
e5a1cab5 | 3640 | out: |
082dcc7c | 3641 | hsw_enable_ips(intel_crtc); |
e5a1cab5 | 3642 | return ret; |
082dcc7c RV |
3643 | } |
3644 | ||
3645 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) | |
3646 | { | |
3647 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
d72f9d91 | 3648 | struct drm_device *dev = dig_port->base.base.dev; |
082dcc7c RV |
3649 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
3650 | u8 buf; | |
e5a1cab5 RV |
3651 | int ret; |
3652 | ||
082dcc7c RV |
3653 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
3654 | return -EIO; | |
3655 | ||
3656 | if (!(buf & DP_TEST_CRC_SUPPORTED)) | |
3657 | return -ENOTTY; | |
3658 | ||
3659 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) | |
3660 | return -EIO; | |
3661 | ||
6d8175da RV |
3662 | if (buf & DP_TEST_SINK_START) { |
3663 | ret = intel_dp_sink_crc_stop(intel_dp); | |
3664 | if (ret) | |
3665 | return ret; | |
3666 | } | |
3667 | ||
082dcc7c | 3668 | hsw_disable_ips(intel_crtc); |
1dda5f93 | 3669 | |
9d1a1031 | 3670 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
082dcc7c RV |
3671 | buf | DP_TEST_SINK_START) < 0) { |
3672 | hsw_enable_ips(intel_crtc); | |
3673 | return -EIO; | |
4373f0f2 PZ |
3674 | } |
3675 | ||
d72f9d91 | 3676 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
082dcc7c RV |
3677 | return 0; |
3678 | } | |
3679 | ||
3680 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) | |
3681 | { | |
3682 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
3683 | struct drm_device *dev = dig_port->base.base.dev; | |
3684 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); | |
3685 | u8 buf; | |
621d4c76 | 3686 | int count, ret; |
082dcc7c | 3687 | int attempts = 6; |
082dcc7c RV |
3688 | |
3689 | ret = intel_dp_sink_crc_start(intel_dp); | |
3690 | if (ret) | |
3691 | return ret; | |
3692 | ||
ad9dc91b | 3693 | do { |
621d4c76 RV |
3694 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
3695 | ||
1dda5f93 | 3696 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4373f0f2 PZ |
3697 | DP_TEST_SINK_MISC, &buf) < 0) { |
3698 | ret = -EIO; | |
afe0d67e | 3699 | goto stop; |
4373f0f2 | 3700 | } |
621d4c76 | 3701 | count = buf & DP_TEST_COUNT_MASK; |
aabc95dc | 3702 | |
7e38eeff | 3703 | } while (--attempts && count == 0); |
ad9dc91b RV |
3704 | |
3705 | if (attempts == 0) { | |
7e38eeff RV |
3706 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
3707 | ret = -ETIMEDOUT; | |
3708 | goto stop; | |
3709 | } | |
3710 | ||
3711 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { | |
3712 | ret = -EIO; | |
3713 | goto stop; | |
ad9dc91b | 3714 | } |
d2e216d0 | 3715 | |
afe0d67e | 3716 | stop: |
082dcc7c | 3717 | intel_dp_sink_crc_stop(intel_dp); |
4373f0f2 | 3718 | return ret; |
d2e216d0 RV |
3719 | } |
3720 | ||
a60f0e38 JB |
3721 | static bool |
3722 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3723 | { | |
9f085ebb | 3724 | return drm_dp_dpcd_read(&intel_dp->aux, |
9d1a1031 JN |
3725 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
3726 | sink_irq_vector, 1) == 1; | |
a60f0e38 JB |
3727 | } |
3728 | ||
0e32b39c DA |
3729 | static bool |
3730 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3731 | { | |
3732 | int ret; | |
3733 | ||
9f085ebb | 3734 | ret = drm_dp_dpcd_read(&intel_dp->aux, |
0e32b39c DA |
3735 | DP_SINK_COUNT_ESI, |
3736 | sink_irq_vector, 14); | |
3737 | if (ret != 14) | |
3738 | return false; | |
3739 | ||
3740 | return true; | |
3741 | } | |
3742 | ||
c5d5ab7a TP |
3743 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
3744 | { | |
3745 | uint8_t test_result = DP_TEST_ACK; | |
3746 | return test_result; | |
3747 | } | |
3748 | ||
3749 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) | |
3750 | { | |
3751 | uint8_t test_result = DP_TEST_NAK; | |
3752 | return test_result; | |
3753 | } | |
3754 | ||
3755 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) | |
a60f0e38 | 3756 | { |
c5d5ab7a | 3757 | uint8_t test_result = DP_TEST_NAK; |
559be30c TP |
3758 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
3759 | struct drm_connector *connector = &intel_connector->base; | |
3760 | ||
3761 | if (intel_connector->detect_edid == NULL || | |
ac6f2e29 | 3762 | connector->edid_corrupt || |
559be30c TP |
3763 | intel_dp->aux.i2c_defer_count > 6) { |
3764 | /* Check EDID read for NACKs, DEFERs and corruption | |
3765 | * (DP CTS 1.2 Core r1.1) | |
3766 | * 4.2.2.4 : Failed EDID read, I2C_NAK | |
3767 | * 4.2.2.5 : Failed EDID read, I2C_DEFER | |
3768 | * 4.2.2.6 : EDID corruption detected | |
3769 | * Use failsafe mode for all cases | |
3770 | */ | |
3771 | if (intel_dp->aux.i2c_nack_count > 0 || | |
3772 | intel_dp->aux.i2c_defer_count > 0) | |
3773 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", | |
3774 | intel_dp->aux.i2c_nack_count, | |
3775 | intel_dp->aux.i2c_defer_count); | |
3776 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE; | |
3777 | } else { | |
f79b468e TS |
3778 | struct edid *block = intel_connector->detect_edid; |
3779 | ||
3780 | /* We have to write the checksum | |
3781 | * of the last block read | |
3782 | */ | |
3783 | block += intel_connector->detect_edid->extensions; | |
3784 | ||
559be30c TP |
3785 | if (!drm_dp_dpcd_write(&intel_dp->aux, |
3786 | DP_TEST_EDID_CHECKSUM, | |
f79b468e | 3787 | &block->checksum, |
5a1cc655 | 3788 | 1)) |
559be30c TP |
3789 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
3790 | ||
3791 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; | |
3792 | intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD; | |
3793 | } | |
3794 | ||
3795 | /* Set test active flag here so userspace doesn't interrupt things */ | |
3796 | intel_dp->compliance_test_active = 1; | |
3797 | ||
c5d5ab7a TP |
3798 | return test_result; |
3799 | } | |
3800 | ||
3801 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) | |
a60f0e38 | 3802 | { |
c5d5ab7a TP |
3803 | uint8_t test_result = DP_TEST_NAK; |
3804 | return test_result; | |
3805 | } | |
3806 | ||
3807 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
3808 | { | |
3809 | uint8_t response = DP_TEST_NAK; | |
3810 | uint8_t rxdata = 0; | |
3811 | int status = 0; | |
3812 | ||
c5d5ab7a TP |
3813 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1); |
3814 | if (status <= 0) { | |
3815 | DRM_DEBUG_KMS("Could not read test request from sink\n"); | |
3816 | goto update_status; | |
3817 | } | |
3818 | ||
3819 | switch (rxdata) { | |
3820 | case DP_TEST_LINK_TRAINING: | |
3821 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); | |
3822 | intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING; | |
3823 | response = intel_dp_autotest_link_training(intel_dp); | |
3824 | break; | |
3825 | case DP_TEST_LINK_VIDEO_PATTERN: | |
3826 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); | |
3827 | intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN; | |
3828 | response = intel_dp_autotest_video_pattern(intel_dp); | |
3829 | break; | |
3830 | case DP_TEST_LINK_EDID_READ: | |
3831 | DRM_DEBUG_KMS("EDID test requested\n"); | |
3832 | intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ; | |
3833 | response = intel_dp_autotest_edid(intel_dp); | |
3834 | break; | |
3835 | case DP_TEST_LINK_PHY_TEST_PATTERN: | |
3836 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); | |
3837 | intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN; | |
3838 | response = intel_dp_autotest_phy_pattern(intel_dp); | |
3839 | break; | |
3840 | default: | |
3841 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata); | |
3842 | break; | |
3843 | } | |
3844 | ||
3845 | update_status: | |
3846 | status = drm_dp_dpcd_write(&intel_dp->aux, | |
3847 | DP_TEST_RESPONSE, | |
3848 | &response, 1); | |
3849 | if (status <= 0) | |
3850 | DRM_DEBUG_KMS("Could not write test response to sink\n"); | |
a60f0e38 JB |
3851 | } |
3852 | ||
0e32b39c DA |
3853 | static int |
3854 | intel_dp_check_mst_status(struct intel_dp *intel_dp) | |
3855 | { | |
3856 | bool bret; | |
3857 | ||
3858 | if (intel_dp->is_mst) { | |
3859 | u8 esi[16] = { 0 }; | |
3860 | int ret = 0; | |
3861 | int retry; | |
3862 | bool handled; | |
3863 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
3864 | go_again: | |
3865 | if (bret == true) { | |
3866 | ||
3867 | /* check link status - esi[10] = 0x200c */ | |
19e0b4ca | 3868 | if (intel_dp->active_mst_links && |
901c2daf | 3869 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
0e32b39c DA |
3870 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
3871 | intel_dp_start_link_train(intel_dp); | |
0e32b39c DA |
3872 | intel_dp_stop_link_train(intel_dp); |
3873 | } | |
3874 | ||
6f34cc39 | 3875 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
0e32b39c DA |
3876 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
3877 | ||
3878 | if (handled) { | |
3879 | for (retry = 0; retry < 3; retry++) { | |
3880 | int wret; | |
3881 | wret = drm_dp_dpcd_write(&intel_dp->aux, | |
3882 | DP_SINK_COUNT_ESI+1, | |
3883 | &esi[1], 3); | |
3884 | if (wret == 3) { | |
3885 | break; | |
3886 | } | |
3887 | } | |
3888 | ||
3889 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
3890 | if (bret == true) { | |
6f34cc39 | 3891 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
0e32b39c DA |
3892 | goto go_again; |
3893 | } | |
3894 | } else | |
3895 | ret = 0; | |
3896 | ||
3897 | return ret; | |
3898 | } else { | |
3899 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3900 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); | |
3901 | intel_dp->is_mst = false; | |
3902 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | |
3903 | /* send a hotplug event */ | |
3904 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); | |
3905 | } | |
3906 | } | |
3907 | return -EINVAL; | |
3908 | } | |
3909 | ||
5c9114d0 SS |
3910 | static void |
3911 | intel_dp_check_link_status(struct intel_dp *intel_dp) | |
3912 | { | |
3913 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; | |
3914 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
3915 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
3916 | ||
3917 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); | |
3918 | ||
3919 | if (!intel_dp_get_link_status(intel_dp, link_status)) { | |
3920 | DRM_ERROR("Failed to get link status\n"); | |
3921 | return; | |
3922 | } | |
3923 | ||
3924 | if (!intel_encoder->base.crtc) | |
3925 | return; | |
3926 | ||
3927 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) | |
3928 | return; | |
3929 | ||
3930 | /* if link training is requested we should perform it always */ | |
3931 | if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) || | |
3932 | (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) { | |
3933 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", | |
3934 | intel_encoder->base.name); | |
3935 | intel_dp_start_link_train(intel_dp); | |
3936 | intel_dp_stop_link_train(intel_dp); | |
3937 | } | |
3938 | } | |
3939 | ||
a4fc5ed6 KP |
3940 | /* |
3941 | * According to DP spec | |
3942 | * 5.1.2: | |
3943 | * 1. Read DPCD | |
3944 | * 2. Configure link according to Receiver Capabilities | |
3945 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
3946 | * 4. Check link status on receipt of hot-plug interrupt | |
39ff747b SS |
3947 | * |
3948 | * intel_dp_short_pulse - handles short pulse interrupts | |
3949 | * when full detection is not required. | |
3950 | * Returns %true if short pulse is handled and full detection | |
3951 | * is NOT required and %false otherwise. | |
a4fc5ed6 | 3952 | */ |
39ff747b | 3953 | static bool |
5c9114d0 | 3954 | intel_dp_short_pulse(struct intel_dp *intel_dp) |
a4fc5ed6 | 3955 | { |
5b215bcf | 3956 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
65fbb4e7 | 3957 | u8 sink_irq_vector = 0; |
39ff747b SS |
3958 | u8 old_sink_count = intel_dp->sink_count; |
3959 | bool ret; | |
5b215bcf | 3960 | |
4df6960e SS |
3961 | /* |
3962 | * Clearing compliance test variables to allow capturing | |
3963 | * of values for next automated test request. | |
3964 | */ | |
3965 | intel_dp->compliance_test_active = 0; | |
3966 | intel_dp->compliance_test_type = 0; | |
3967 | intel_dp->compliance_test_data = 0; | |
3968 | ||
39ff747b SS |
3969 | /* |
3970 | * Now read the DPCD to see if it's actually running | |
3971 | * If the current value of sink count doesn't match with | |
3972 | * the value that was stored earlier or dpcd read failed | |
3973 | * we need to do full detection | |
3974 | */ | |
3975 | ret = intel_dp_get_dpcd(intel_dp); | |
3976 | ||
3977 | if ((old_sink_count != intel_dp->sink_count) || !ret) { | |
3978 | /* No need to proceed if we are going to do full detect */ | |
3979 | return false; | |
59cd09e1 JB |
3980 | } |
3981 | ||
a60f0e38 JB |
3982 | /* Try to read the source of the interrupt */ |
3983 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
65fbb4e7 VS |
3984 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
3985 | sink_irq_vector != 0) { | |
a60f0e38 | 3986 | /* Clear interrupt source */ |
9d1a1031 JN |
3987 | drm_dp_dpcd_writeb(&intel_dp->aux, |
3988 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
3989 | sink_irq_vector); | |
a60f0e38 JB |
3990 | |
3991 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
09b1eb13 | 3992 | DRM_DEBUG_DRIVER("Test request in short pulse not handled\n"); |
a60f0e38 JB |
3993 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
3994 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
3995 | } | |
3996 | ||
5c9114d0 SS |
3997 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
3998 | intel_dp_check_link_status(intel_dp); | |
3999 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
39ff747b SS |
4000 | |
4001 | return true; | |
a4fc5ed6 | 4002 | } |
a4fc5ed6 | 4003 | |
caf9ab24 | 4004 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 4005 | static enum drm_connector_status |
26d61aad | 4006 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 4007 | { |
caf9ab24 | 4008 | uint8_t *dpcd = intel_dp->dpcd; |
caf9ab24 AJ |
4009 | uint8_t type; |
4010 | ||
4011 | if (!intel_dp_get_dpcd(intel_dp)) | |
4012 | return connector_status_disconnected; | |
4013 | ||
1034ce70 SS |
4014 | if (is_edp(intel_dp)) |
4015 | return connector_status_connected; | |
4016 | ||
caf9ab24 AJ |
4017 | /* if there's no downstream port, we're done */ |
4018 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) | |
26d61aad | 4019 | return connector_status_connected; |
caf9ab24 AJ |
4020 | |
4021 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
c9ff160b JN |
4022 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4023 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | |
9d1a1031 | 4024 | |
30d9aa42 SS |
4025 | return intel_dp->sink_count ? |
4026 | connector_status_connected : connector_status_disconnected; | |
caf9ab24 AJ |
4027 | } |
4028 | ||
c4e3170a VS |
4029 | if (intel_dp_can_mst(intel_dp)) |
4030 | return connector_status_connected; | |
4031 | ||
caf9ab24 | 4032 | /* If no HPD, poke DDC gently */ |
0b99836f | 4033 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
26d61aad | 4034 | return connector_status_connected; |
caf9ab24 AJ |
4035 | |
4036 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
4037 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
4038 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
4039 | if (type == DP_DS_PORT_TYPE_VGA || | |
4040 | type == DP_DS_PORT_TYPE_NON_EDID) | |
4041 | return connector_status_unknown; | |
4042 | } else { | |
4043 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
4044 | DP_DWN_STRM_PORT_TYPE_MASK; | |
4045 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
4046 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
4047 | return connector_status_unknown; | |
4048 | } | |
caf9ab24 AJ |
4049 | |
4050 | /* Anything else is out of spec, warn and ignore */ | |
4051 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); | |
26d61aad | 4052 | return connector_status_disconnected; |
71ba9000 AJ |
4053 | } |
4054 | ||
d410b56d CW |
4055 | static enum drm_connector_status |
4056 | edp_detect(struct intel_dp *intel_dp) | |
4057 | { | |
4058 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
4059 | enum drm_connector_status status; | |
4060 | ||
4061 | status = intel_panel_detect(dev); | |
4062 | if (status == connector_status_unknown) | |
4063 | status = connector_status_connected; | |
4064 | ||
4065 | return status; | |
4066 | } | |
4067 | ||
b93433cc JN |
4068 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
4069 | struct intel_digital_port *port) | |
5eb08b69 | 4070 | { |
b93433cc | 4071 | u32 bit; |
01cb9ea6 | 4072 | |
0df53b77 JN |
4073 | switch (port->port) { |
4074 | case PORT_A: | |
4075 | return true; | |
4076 | case PORT_B: | |
4077 | bit = SDE_PORTB_HOTPLUG; | |
4078 | break; | |
4079 | case PORT_C: | |
4080 | bit = SDE_PORTC_HOTPLUG; | |
4081 | break; | |
4082 | case PORT_D: | |
4083 | bit = SDE_PORTD_HOTPLUG; | |
4084 | break; | |
4085 | default: | |
4086 | MISSING_CASE(port->port); | |
4087 | return false; | |
4088 | } | |
4089 | ||
4090 | return I915_READ(SDEISR) & bit; | |
4091 | } | |
4092 | ||
4093 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, | |
4094 | struct intel_digital_port *port) | |
4095 | { | |
4096 | u32 bit; | |
4097 | ||
4098 | switch (port->port) { | |
4099 | case PORT_A: | |
4100 | return true; | |
4101 | case PORT_B: | |
4102 | bit = SDE_PORTB_HOTPLUG_CPT; | |
4103 | break; | |
4104 | case PORT_C: | |
4105 | bit = SDE_PORTC_HOTPLUG_CPT; | |
4106 | break; | |
4107 | case PORT_D: | |
4108 | bit = SDE_PORTD_HOTPLUG_CPT; | |
4109 | break; | |
a78695d3 JN |
4110 | case PORT_E: |
4111 | bit = SDE_PORTE_HOTPLUG_SPT; | |
4112 | break; | |
0df53b77 JN |
4113 | default: |
4114 | MISSING_CASE(port->port); | |
4115 | return false; | |
b93433cc | 4116 | } |
1b469639 | 4117 | |
b93433cc | 4118 | return I915_READ(SDEISR) & bit; |
5eb08b69 ZW |
4119 | } |
4120 | ||
7e66bcf2 | 4121 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
1d245987 | 4122 | struct intel_digital_port *port) |
a4fc5ed6 | 4123 | { |
9642c81c | 4124 | u32 bit; |
5eb08b69 | 4125 | |
9642c81c JN |
4126 | switch (port->port) { |
4127 | case PORT_B: | |
4128 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; | |
4129 | break; | |
4130 | case PORT_C: | |
4131 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; | |
4132 | break; | |
4133 | case PORT_D: | |
4134 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; | |
4135 | break; | |
4136 | default: | |
4137 | MISSING_CASE(port->port); | |
4138 | return false; | |
4139 | } | |
4140 | ||
4141 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | |
4142 | } | |
4143 | ||
0780cd36 VS |
4144 | static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, |
4145 | struct intel_digital_port *port) | |
9642c81c JN |
4146 | { |
4147 | u32 bit; | |
4148 | ||
4149 | switch (port->port) { | |
4150 | case PORT_B: | |
0780cd36 | 4151 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4152 | break; |
4153 | case PORT_C: | |
0780cd36 | 4154 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4155 | break; |
4156 | case PORT_D: | |
0780cd36 | 4157 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4158 | break; |
4159 | default: | |
4160 | MISSING_CASE(port->port); | |
4161 | return false; | |
a4fc5ed6 KP |
4162 | } |
4163 | ||
1d245987 | 4164 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
2a592bec DA |
4165 | } |
4166 | ||
e464bfde | 4167 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
e2ec35a5 | 4168 | struct intel_digital_port *intel_dig_port) |
e464bfde | 4169 | { |
e2ec35a5 SJ |
4170 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4171 | enum port port; | |
e464bfde JN |
4172 | u32 bit; |
4173 | ||
e2ec35a5 SJ |
4174 | intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port); |
4175 | switch (port) { | |
e464bfde JN |
4176 | case PORT_A: |
4177 | bit = BXT_DE_PORT_HP_DDIA; | |
4178 | break; | |
4179 | case PORT_B: | |
4180 | bit = BXT_DE_PORT_HP_DDIB; | |
4181 | break; | |
4182 | case PORT_C: | |
4183 | bit = BXT_DE_PORT_HP_DDIC; | |
4184 | break; | |
4185 | default: | |
e2ec35a5 | 4186 | MISSING_CASE(port); |
e464bfde JN |
4187 | return false; |
4188 | } | |
4189 | ||
4190 | return I915_READ(GEN8_DE_PORT_ISR) & bit; | |
4191 | } | |
4192 | ||
7e66bcf2 JN |
4193 | /* |
4194 | * intel_digital_port_connected - is the specified port connected? | |
4195 | * @dev_priv: i915 private structure | |
4196 | * @port: the port to test | |
4197 | * | |
4198 | * Return %true if @port is connected, %false otherwise. | |
4199 | */ | |
237ed86c | 4200 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
7e66bcf2 JN |
4201 | struct intel_digital_port *port) |
4202 | { | |
0df53b77 | 4203 | if (HAS_PCH_IBX(dev_priv)) |
7e66bcf2 | 4204 | return ibx_digital_port_connected(dev_priv, port); |
22824fac | 4205 | else if (HAS_PCH_SPLIT(dev_priv)) |
0df53b77 | 4206 | return cpt_digital_port_connected(dev_priv, port); |
e464bfde JN |
4207 | else if (IS_BROXTON(dev_priv)) |
4208 | return bxt_digital_port_connected(dev_priv, port); | |
0780cd36 VS |
4209 | else if (IS_GM45(dev_priv)) |
4210 | return gm45_digital_port_connected(dev_priv, port); | |
7e66bcf2 JN |
4211 | else |
4212 | return g4x_digital_port_connected(dev_priv, port); | |
4213 | } | |
4214 | ||
8c241fef | 4215 | static struct edid * |
beb60608 | 4216 | intel_dp_get_edid(struct intel_dp *intel_dp) |
8c241fef | 4217 | { |
beb60608 | 4218 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
d6f24d0f | 4219 | |
9cd300e0 JN |
4220 | /* use cached edid if we have one */ |
4221 | if (intel_connector->edid) { | |
9cd300e0 JN |
4222 | /* invalid edid */ |
4223 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
4224 | return NULL; |
4225 | ||
55e9edeb | 4226 | return drm_edid_duplicate(intel_connector->edid); |
beb60608 CW |
4227 | } else |
4228 | return drm_get_edid(&intel_connector->base, | |
4229 | &intel_dp->aux.ddc); | |
4230 | } | |
8c241fef | 4231 | |
beb60608 CW |
4232 | static void |
4233 | intel_dp_set_edid(struct intel_dp *intel_dp) | |
4234 | { | |
4235 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
4236 | struct edid *edid; | |
8c241fef | 4237 | |
f21a2198 | 4238 | intel_dp_unset_edid(intel_dp); |
beb60608 CW |
4239 | edid = intel_dp_get_edid(intel_dp); |
4240 | intel_connector->detect_edid = edid; | |
4241 | ||
4242 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) | |
4243 | intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON; | |
4244 | else | |
4245 | intel_dp->has_audio = drm_detect_monitor_audio(edid); | |
8c241fef KP |
4246 | } |
4247 | ||
beb60608 CW |
4248 | static void |
4249 | intel_dp_unset_edid(struct intel_dp *intel_dp) | |
8c241fef | 4250 | { |
beb60608 | 4251 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
8c241fef | 4252 | |
beb60608 CW |
4253 | kfree(intel_connector->detect_edid); |
4254 | intel_connector->detect_edid = NULL; | |
9cd300e0 | 4255 | |
beb60608 CW |
4256 | intel_dp->has_audio = false; |
4257 | } | |
d6f24d0f | 4258 | |
f21a2198 SS |
4259 | static void |
4260 | intel_dp_long_pulse(struct intel_connector *intel_connector) | |
a9756bb5 | 4261 | { |
f21a2198 | 4262 | struct drm_connector *connector = &intel_connector->base; |
a9756bb5 | 4263 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
d63885da PZ |
4264 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4265 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fa90ecef | 4266 | struct drm_device *dev = connector->dev; |
a9756bb5 | 4267 | enum drm_connector_status status; |
671dedd2 | 4268 | enum intel_display_power_domain power_domain; |
65fbb4e7 | 4269 | u8 sink_irq_vector = 0; |
a9756bb5 | 4270 | |
25f78f58 VS |
4271 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4272 | intel_display_power_get(to_i915(dev), power_domain); | |
a9756bb5 | 4273 | |
d410b56d CW |
4274 | /* Can't disconnect eDP, but you can close the lid... */ |
4275 | if (is_edp(intel_dp)) | |
4276 | status = edp_detect(intel_dp); | |
c555a81d ACO |
4277 | else if (intel_digital_port_connected(to_i915(dev), |
4278 | dp_to_dig_port(intel_dp))) | |
4279 | status = intel_dp_detect_dpcd(intel_dp); | |
a9756bb5 | 4280 | else |
c555a81d ACO |
4281 | status = connector_status_disconnected; |
4282 | ||
4df6960e SS |
4283 | if (status != connector_status_connected) { |
4284 | intel_dp->compliance_test_active = 0; | |
4285 | intel_dp->compliance_test_type = 0; | |
4286 | intel_dp->compliance_test_data = 0; | |
4287 | ||
0e505a08 | 4288 | if (intel_dp->is_mst) { |
4289 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
4290 | intel_dp->is_mst, | |
4291 | intel_dp->mst_mgr.mst_state); | |
4292 | intel_dp->is_mst = false; | |
4293 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
4294 | intel_dp->is_mst); | |
4295 | } | |
4296 | ||
c8c8fb33 | 4297 | goto out; |
4df6960e | 4298 | } |
a9756bb5 | 4299 | |
f21a2198 | 4300 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
cca0502b | 4301 | intel_encoder->type = INTEL_OUTPUT_DP; |
f21a2198 | 4302 | |
fe5a66f9 VS |
4303 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
4304 | yesno(intel_dp_source_supports_hbr2(intel_dp)), | |
4305 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); | |
4306 | ||
4307 | intel_dp_print_rates(intel_dp); | |
4308 | ||
0d198328 AJ |
4309 | intel_dp_probe_oui(intel_dp); |
4310 | ||
c4e3170a VS |
4311 | intel_dp_configure_mst(intel_dp); |
4312 | ||
4313 | if (intel_dp->is_mst) { | |
f21a2198 SS |
4314 | /* |
4315 | * If we are in MST mode then this connector | |
4316 | * won't appear connected or have anything | |
4317 | * with EDID on it | |
4318 | */ | |
0e32b39c DA |
4319 | status = connector_status_disconnected; |
4320 | goto out; | |
7d23e3c3 SS |
4321 | } else if (connector->status == connector_status_connected) { |
4322 | /* | |
4323 | * If display was connected already and is still connected | |
4324 | * check links status, there has been known issues of | |
4325 | * link loss triggerring long pulse!!!! | |
4326 | */ | |
4327 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); | |
4328 | intel_dp_check_link_status(intel_dp); | |
4329 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
4330 | goto out; | |
0e32b39c DA |
4331 | } |
4332 | ||
4df6960e SS |
4333 | /* |
4334 | * Clearing NACK and defer counts to get their exact values | |
4335 | * while reading EDID which are required by Compliance tests | |
4336 | * 4.2.2.4 and 4.2.2.5 | |
4337 | */ | |
4338 | intel_dp->aux.i2c_nack_count = 0; | |
4339 | intel_dp->aux.i2c_defer_count = 0; | |
4340 | ||
beb60608 | 4341 | intel_dp_set_edid(intel_dp); |
a9756bb5 | 4342 | |
c8c8fb33 | 4343 | status = connector_status_connected; |
7d23e3c3 | 4344 | intel_dp->detect_done = true; |
c8c8fb33 | 4345 | |
09b1eb13 TP |
4346 | /* Try to read the source of the interrupt */ |
4347 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
65fbb4e7 VS |
4348 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
4349 | sink_irq_vector != 0) { | |
09b1eb13 TP |
4350 | /* Clear interrupt source */ |
4351 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
4352 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4353 | sink_irq_vector); | |
4354 | ||
4355 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
4356 | intel_dp_handle_test_request(intel_dp); | |
4357 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
4358 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4359 | } | |
4360 | ||
c8c8fb33 | 4361 | out: |
0e505a08 | 4362 | if ((status != connector_status_connected) && |
4363 | (intel_dp->is_mst == false)) | |
f21a2198 | 4364 | intel_dp_unset_edid(intel_dp); |
7d23e3c3 | 4365 | |
25f78f58 | 4366 | intel_display_power_put(to_i915(dev), power_domain); |
f21a2198 SS |
4367 | return; |
4368 | } | |
4369 | ||
4370 | static enum drm_connector_status | |
4371 | intel_dp_detect(struct drm_connector *connector, bool force) | |
4372 | { | |
4373 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
4374 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4375 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
4376 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4377 | ||
4378 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4379 | connector->base.id, connector->name); | |
4380 | ||
4381 | if (intel_dp->is_mst) { | |
4382 | /* MST devices are disconnected from a monitor POV */ | |
4383 | intel_dp_unset_edid(intel_dp); | |
4384 | if (intel_encoder->type != INTEL_OUTPUT_EDP) | |
cca0502b | 4385 | intel_encoder->type = INTEL_OUTPUT_DP; |
f21a2198 SS |
4386 | return connector_status_disconnected; |
4387 | } | |
4388 | ||
7d23e3c3 SS |
4389 | /* If full detect is not performed yet, do a full detect */ |
4390 | if (!intel_dp->detect_done) | |
4391 | intel_dp_long_pulse(intel_dp->attached_connector); | |
4392 | ||
4393 | intel_dp->detect_done = false; | |
f21a2198 | 4394 | |
1b7f2c8b | 4395 | if (is_edp(intel_dp) || intel_connector->detect_edid) |
f21a2198 SS |
4396 | return connector_status_connected; |
4397 | else | |
4398 | return connector_status_disconnected; | |
a4fc5ed6 KP |
4399 | } |
4400 | ||
beb60608 CW |
4401 | static void |
4402 | intel_dp_force(struct drm_connector *connector) | |
a4fc5ed6 | 4403 | { |
df0e9248 | 4404 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
beb60608 | 4405 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
25f78f58 | 4406 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
671dedd2 | 4407 | enum intel_display_power_domain power_domain; |
a4fc5ed6 | 4408 | |
beb60608 CW |
4409 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4410 | connector->base.id, connector->name); | |
4411 | intel_dp_unset_edid(intel_dp); | |
a4fc5ed6 | 4412 | |
beb60608 CW |
4413 | if (connector->status != connector_status_connected) |
4414 | return; | |
671dedd2 | 4415 | |
25f78f58 VS |
4416 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
4417 | intel_display_power_get(dev_priv, power_domain); | |
beb60608 CW |
4418 | |
4419 | intel_dp_set_edid(intel_dp); | |
4420 | ||
25f78f58 | 4421 | intel_display_power_put(dev_priv, power_domain); |
beb60608 CW |
4422 | |
4423 | if (intel_encoder->type != INTEL_OUTPUT_EDP) | |
cca0502b | 4424 | intel_encoder->type = INTEL_OUTPUT_DP; |
beb60608 CW |
4425 | } |
4426 | ||
4427 | static int intel_dp_get_modes(struct drm_connector *connector) | |
4428 | { | |
4429 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4430 | struct edid *edid; | |
4431 | ||
4432 | edid = intel_connector->detect_edid; | |
4433 | if (edid) { | |
4434 | int ret = intel_connector_update_modes(connector, edid); | |
4435 | if (ret) | |
4436 | return ret; | |
4437 | } | |
32f9d658 | 4438 | |
f8779fda | 4439 | /* if eDP has no EDID, fall back to fixed mode */ |
beb60608 CW |
4440 | if (is_edp(intel_attached_dp(connector)) && |
4441 | intel_connector->panel.fixed_mode) { | |
f8779fda | 4442 | struct drm_display_mode *mode; |
beb60608 CW |
4443 | |
4444 | mode = drm_mode_duplicate(connector->dev, | |
dd06f90e | 4445 | intel_connector->panel.fixed_mode); |
f8779fda | 4446 | if (mode) { |
32f9d658 ZW |
4447 | drm_mode_probed_add(connector, mode); |
4448 | return 1; | |
4449 | } | |
4450 | } | |
beb60608 | 4451 | |
32f9d658 | 4452 | return 0; |
a4fc5ed6 KP |
4453 | } |
4454 | ||
1aad7ac0 CW |
4455 | static bool |
4456 | intel_dp_detect_audio(struct drm_connector *connector) | |
4457 | { | |
1aad7ac0 | 4458 | bool has_audio = false; |
beb60608 | 4459 | struct edid *edid; |
1aad7ac0 | 4460 | |
beb60608 CW |
4461 | edid = to_intel_connector(connector)->detect_edid; |
4462 | if (edid) | |
1aad7ac0 | 4463 | has_audio = drm_detect_monitor_audio(edid); |
671dedd2 | 4464 | |
1aad7ac0 CW |
4465 | return has_audio; |
4466 | } | |
4467 | ||
f684960e CW |
4468 | static int |
4469 | intel_dp_set_property(struct drm_connector *connector, | |
4470 | struct drm_property *property, | |
4471 | uint64_t val) | |
4472 | { | |
fac5e23e | 4473 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
53b41837 | 4474 | struct intel_connector *intel_connector = to_intel_connector(connector); |
da63a9f2 PZ |
4475 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
4476 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
f684960e CW |
4477 | int ret; |
4478 | ||
662595df | 4479 | ret = drm_object_property_set_value(&connector->base, property, val); |
f684960e CW |
4480 | if (ret) |
4481 | return ret; | |
4482 | ||
3f43c48d | 4483 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
4484 | int i = val; |
4485 | bool has_audio; | |
4486 | ||
4487 | if (i == intel_dp->force_audio) | |
f684960e CW |
4488 | return 0; |
4489 | ||
1aad7ac0 | 4490 | intel_dp->force_audio = i; |
f684960e | 4491 | |
c3e5f67b | 4492 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
4493 | has_audio = intel_dp_detect_audio(connector); |
4494 | else | |
c3e5f67b | 4495 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 CW |
4496 | |
4497 | if (has_audio == intel_dp->has_audio) | |
f684960e CW |
4498 | return 0; |
4499 | ||
1aad7ac0 | 4500 | intel_dp->has_audio = has_audio; |
f684960e CW |
4501 | goto done; |
4502 | } | |
4503 | ||
e953fd7b | 4504 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 | 4505 | bool old_auto = intel_dp->color_range_auto; |
0f2a2a75 | 4506 | bool old_range = intel_dp->limited_color_range; |
ae4edb80 | 4507 | |
55bc60db VS |
4508 | switch (val) { |
4509 | case INTEL_BROADCAST_RGB_AUTO: | |
4510 | intel_dp->color_range_auto = true; | |
4511 | break; | |
4512 | case INTEL_BROADCAST_RGB_FULL: | |
4513 | intel_dp->color_range_auto = false; | |
0f2a2a75 | 4514 | intel_dp->limited_color_range = false; |
55bc60db VS |
4515 | break; |
4516 | case INTEL_BROADCAST_RGB_LIMITED: | |
4517 | intel_dp->color_range_auto = false; | |
0f2a2a75 | 4518 | intel_dp->limited_color_range = true; |
55bc60db VS |
4519 | break; |
4520 | default: | |
4521 | return -EINVAL; | |
4522 | } | |
ae4edb80 DV |
4523 | |
4524 | if (old_auto == intel_dp->color_range_auto && | |
0f2a2a75 | 4525 | old_range == intel_dp->limited_color_range) |
ae4edb80 DV |
4526 | return 0; |
4527 | ||
e953fd7b CW |
4528 | goto done; |
4529 | } | |
4530 | ||
53b41837 YN |
4531 | if (is_edp(intel_dp) && |
4532 | property == connector->dev->mode_config.scaling_mode_property) { | |
4533 | if (val == DRM_MODE_SCALE_NONE) { | |
4534 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
4535 | return -EINVAL; | |
4536 | } | |
234126c6 VS |
4537 | if (HAS_GMCH_DISPLAY(dev_priv) && |
4538 | val == DRM_MODE_SCALE_CENTER) { | |
4539 | DRM_DEBUG_KMS("centering not supported\n"); | |
4540 | return -EINVAL; | |
4541 | } | |
53b41837 YN |
4542 | |
4543 | if (intel_connector->panel.fitting_mode == val) { | |
4544 | /* the eDP scaling property is not changed */ | |
4545 | return 0; | |
4546 | } | |
4547 | intel_connector->panel.fitting_mode = val; | |
4548 | ||
4549 | goto done; | |
4550 | } | |
4551 | ||
f684960e CW |
4552 | return -EINVAL; |
4553 | ||
4554 | done: | |
c0c36b94 CW |
4555 | if (intel_encoder->base.crtc) |
4556 | intel_crtc_restore_mode(intel_encoder->base.crtc); | |
f684960e CW |
4557 | |
4558 | return 0; | |
4559 | } | |
4560 | ||
7a418e34 CW |
4561 | static int |
4562 | intel_dp_connector_register(struct drm_connector *connector) | |
4563 | { | |
4564 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1ebaa0b9 CW |
4565 | int ret; |
4566 | ||
4567 | ret = intel_connector_register(connector); | |
4568 | if (ret) | |
4569 | return ret; | |
7a418e34 CW |
4570 | |
4571 | i915_debugfs_connector_add(connector); | |
4572 | ||
4573 | DRM_DEBUG_KMS("registering %s bus for %s\n", | |
4574 | intel_dp->aux.name, connector->kdev->kobj.name); | |
4575 | ||
4576 | intel_dp->aux.dev = connector->kdev; | |
4577 | return drm_dp_aux_register(&intel_dp->aux); | |
4578 | } | |
4579 | ||
c191eca1 CW |
4580 | static void |
4581 | intel_dp_connector_unregister(struct drm_connector *connector) | |
4582 | { | |
4583 | drm_dp_aux_unregister(&intel_attached_dp(connector)->aux); | |
4584 | intel_connector_unregister(connector); | |
4585 | } | |
4586 | ||
a4fc5ed6 | 4587 | static void |
73845adf | 4588 | intel_dp_connector_destroy(struct drm_connector *connector) |
a4fc5ed6 | 4589 | { |
1d508706 | 4590 | struct intel_connector *intel_connector = to_intel_connector(connector); |
aaa6fd2a | 4591 | |
10e972d3 | 4592 | kfree(intel_connector->detect_edid); |
beb60608 | 4593 | |
9cd300e0 JN |
4594 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
4595 | kfree(intel_connector->edid); | |
4596 | ||
acd8db10 PZ |
4597 | /* Can't call is_edp() since the encoder may have been destroyed |
4598 | * already. */ | |
4599 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) | |
1d508706 | 4600 | intel_panel_fini(&intel_connector->panel); |
aaa6fd2a | 4601 | |
a4fc5ed6 | 4602 | drm_connector_cleanup(connector); |
55f78c43 | 4603 | kfree(connector); |
a4fc5ed6 KP |
4604 | } |
4605 | ||
00c09d70 | 4606 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
24d05927 | 4607 | { |
da63a9f2 PZ |
4608 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
4609 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
24d05927 | 4610 | |
0e32b39c | 4611 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
bd943159 KP |
4612 | if (is_edp(intel_dp)) { |
4613 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
951468f3 VS |
4614 | /* |
4615 | * vdd might still be enabled do to the delayed vdd off. | |
4616 | * Make sure vdd is actually turned off here. | |
4617 | */ | |
773538e8 | 4618 | pps_lock(intel_dp); |
4be73780 | 4619 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 VS |
4620 | pps_unlock(intel_dp); |
4621 | ||
01527b31 CT |
4622 | if (intel_dp->edp_notifier.notifier_call) { |
4623 | unregister_reboot_notifier(&intel_dp->edp_notifier); | |
4624 | intel_dp->edp_notifier.notifier_call = NULL; | |
4625 | } | |
bd943159 | 4626 | } |
99681886 CW |
4627 | |
4628 | intel_dp_aux_fini(intel_dp); | |
4629 | ||
c8bd0e49 | 4630 | drm_encoder_cleanup(encoder); |
da63a9f2 | 4631 | kfree(intel_dig_port); |
24d05927 DV |
4632 | } |
4633 | ||
bf93ba67 | 4634 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
07f9cd0b ID |
4635 | { |
4636 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
4637 | ||
4638 | if (!is_edp(intel_dp)) | |
4639 | return; | |
4640 | ||
951468f3 VS |
4641 | /* |
4642 | * vdd might still be enabled do to the delayed vdd off. | |
4643 | * Make sure vdd is actually turned off here. | |
4644 | */ | |
afa4e53a | 4645 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
773538e8 | 4646 | pps_lock(intel_dp); |
07f9cd0b | 4647 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 | 4648 | pps_unlock(intel_dp); |
07f9cd0b ID |
4649 | } |
4650 | ||
49e6bc51 VS |
4651 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
4652 | { | |
4653 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4654 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 4655 | struct drm_i915_private *dev_priv = to_i915(dev); |
49e6bc51 VS |
4656 | enum intel_display_power_domain power_domain; |
4657 | ||
4658 | lockdep_assert_held(&dev_priv->pps_mutex); | |
4659 | ||
4660 | if (!edp_have_panel_vdd(intel_dp)) | |
4661 | return; | |
4662 | ||
4663 | /* | |
4664 | * The VDD bit needs a power domain reference, so if the bit is | |
4665 | * already enabled when we boot or resume, grab this reference and | |
4666 | * schedule a vdd off, so we don't hold on to the reference | |
4667 | * indefinitely. | |
4668 | */ | |
4669 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); | |
25f78f58 | 4670 | power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base); |
49e6bc51 VS |
4671 | intel_display_power_get(dev_priv, power_domain); |
4672 | ||
4673 | edp_panel_vdd_schedule_off(intel_dp); | |
4674 | } | |
4675 | ||
bf93ba67 | 4676 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
6d93c0c4 | 4677 | { |
64989ca4 VS |
4678 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
4679 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
4680 | ||
4681 | if (!HAS_DDI(dev_priv)) | |
4682 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
49e6bc51 VS |
4683 | |
4684 | if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP) | |
4685 | return; | |
4686 | ||
49e6bc51 VS |
4687 | pps_lock(intel_dp); |
4688 | ||
335f752b ID |
4689 | /* Reinit the power sequencer, in case BIOS did something with it. */ |
4690 | intel_dp_pps_init(encoder->dev, intel_dp); | |
49e6bc51 VS |
4691 | intel_edp_panel_vdd_sanitize(intel_dp); |
4692 | ||
4693 | pps_unlock(intel_dp); | |
6d93c0c4 ID |
4694 | } |
4695 | ||
a4fc5ed6 | 4696 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
4d688a2a | 4697 | .dpms = drm_atomic_helper_connector_dpms, |
a4fc5ed6 | 4698 | .detect = intel_dp_detect, |
beb60608 | 4699 | .force = intel_dp_force, |
a4fc5ed6 | 4700 | .fill_modes = drm_helper_probe_single_connector_modes, |
f684960e | 4701 | .set_property = intel_dp_set_property, |
2545e4a6 | 4702 | .atomic_get_property = intel_connector_atomic_get_property, |
7a418e34 | 4703 | .late_register = intel_dp_connector_register, |
c191eca1 | 4704 | .early_unregister = intel_dp_connector_unregister, |
73845adf | 4705 | .destroy = intel_dp_connector_destroy, |
c6f95f27 | 4706 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 4707 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
a4fc5ed6 KP |
4708 | }; |
4709 | ||
4710 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
4711 | .get_modes = intel_dp_get_modes, | |
4712 | .mode_valid = intel_dp_mode_valid, | |
a4fc5ed6 KP |
4713 | }; |
4714 | ||
a4fc5ed6 | 4715 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
6d93c0c4 | 4716 | .reset = intel_dp_encoder_reset, |
24d05927 | 4717 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
4718 | }; |
4719 | ||
b2c5c181 | 4720 | enum irqreturn |
13cf5504 DA |
4721 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
4722 | { | |
4723 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
1c767b33 | 4724 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
0e32b39c | 4725 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 4726 | struct drm_i915_private *dev_priv = to_i915(dev); |
1c767b33 | 4727 | enum intel_display_power_domain power_domain; |
b2c5c181 | 4728 | enum irqreturn ret = IRQ_NONE; |
1c767b33 | 4729 | |
2540058f TI |
4730 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
4731 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) | |
cca0502b | 4732 | intel_dig_port->base.type = INTEL_OUTPUT_DP; |
13cf5504 | 4733 | |
7a7f84cc VS |
4734 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
4735 | /* | |
4736 | * vdd off can generate a long pulse on eDP which | |
4737 | * would require vdd on to handle it, and thus we | |
4738 | * would end up in an endless cycle of | |
4739 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." | |
4740 | */ | |
4741 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", | |
4742 | port_name(intel_dig_port->port)); | |
a8b3d52f | 4743 | return IRQ_HANDLED; |
7a7f84cc VS |
4744 | } |
4745 | ||
26fbb774 VS |
4746 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
4747 | port_name(intel_dig_port->port), | |
0e32b39c | 4748 | long_hpd ? "long" : "short"); |
13cf5504 | 4749 | |
25f78f58 | 4750 | power_domain = intel_display_port_aux_power_domain(intel_encoder); |
1c767b33 ID |
4751 | intel_display_power_get(dev_priv, power_domain); |
4752 | ||
0e32b39c | 4753 | if (long_hpd) { |
7d23e3c3 SS |
4754 | intel_dp_long_pulse(intel_dp->attached_connector); |
4755 | if (intel_dp->is_mst) | |
4756 | ret = IRQ_HANDLED; | |
4757 | goto put_power; | |
0e32b39c | 4758 | |
0e32b39c DA |
4759 | } else { |
4760 | if (intel_dp->is_mst) { | |
7d23e3c3 SS |
4761 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { |
4762 | /* | |
4763 | * If we were in MST mode, and device is not | |
4764 | * there, get out of MST mode | |
4765 | */ | |
4766 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
4767 | intel_dp->is_mst, intel_dp->mst_mgr.mst_state); | |
4768 | intel_dp->is_mst = false; | |
4769 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
4770 | intel_dp->is_mst); | |
4771 | goto put_power; | |
4772 | } | |
0e32b39c DA |
4773 | } |
4774 | ||
39ff747b SS |
4775 | if (!intel_dp->is_mst) { |
4776 | if (!intel_dp_short_pulse(intel_dp)) { | |
4777 | intel_dp_long_pulse(intel_dp->attached_connector); | |
4778 | goto put_power; | |
4779 | } | |
4780 | } | |
0e32b39c | 4781 | } |
b2c5c181 DV |
4782 | |
4783 | ret = IRQ_HANDLED; | |
4784 | ||
1c767b33 ID |
4785 | put_power: |
4786 | intel_display_power_put(dev_priv, power_domain); | |
4787 | ||
4788 | return ret; | |
13cf5504 DA |
4789 | } |
4790 | ||
477ec328 | 4791 | /* check the VBT to see whether the eDP is on another port */ |
5d8a7752 | 4792 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
36e83a18 | 4793 | { |
fac5e23e | 4794 | struct drm_i915_private *dev_priv = to_i915(dev); |
36e83a18 | 4795 | |
53ce81a7 VS |
4796 | /* |
4797 | * eDP not supported on g4x. so bail out early just | |
4798 | * for a bit extra safety in case the VBT is bonkers. | |
4799 | */ | |
4800 | if (INTEL_INFO(dev)->gen < 5) | |
4801 | return false; | |
4802 | ||
3b32a35b VS |
4803 | if (port == PORT_A) |
4804 | return true; | |
4805 | ||
951d9efe | 4806 | return intel_bios_is_port_edp(dev_priv, port); |
36e83a18 ZY |
4807 | } |
4808 | ||
0e32b39c | 4809 | void |
f684960e CW |
4810 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
4811 | { | |
53b41837 YN |
4812 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4813 | ||
3f43c48d | 4814 | intel_attach_force_audio_property(connector); |
e953fd7b | 4815 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 4816 | intel_dp->color_range_auto = true; |
53b41837 YN |
4817 | |
4818 | if (is_edp(intel_dp)) { | |
4819 | drm_mode_create_scaling_mode_property(connector->dev); | |
6de6d846 RC |
4820 | drm_object_attach_property( |
4821 | &connector->base, | |
53b41837 | 4822 | connector->dev->mode_config.scaling_mode_property, |
8e740cd1 YN |
4823 | DRM_MODE_SCALE_ASPECT); |
4824 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; | |
53b41837 | 4825 | } |
f684960e CW |
4826 | } |
4827 | ||
dada1a9f ID |
4828 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
4829 | { | |
d28d4731 | 4830 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
dada1a9f ID |
4831 | intel_dp->last_power_on = jiffies; |
4832 | intel_dp->last_backlight_off = jiffies; | |
4833 | } | |
4834 | ||
67a54566 | 4835 | static void |
54648618 ID |
4836 | intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, |
4837 | struct intel_dp *intel_dp, struct edp_power_seq *seq) | |
67a54566 | 4838 | { |
b0a08bec | 4839 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
8e8232d5 | 4840 | struct pps_registers regs; |
453c5420 | 4841 | |
8e8232d5 | 4842 | intel_pps_get_registers(dev_priv, intel_dp, ®s); |
67a54566 DV |
4843 | |
4844 | /* Workaround: Need to write PP_CONTROL with the unlock key as | |
4845 | * the very first thing. */ | |
b0a08bec | 4846 | pp_ctl = ironlake_get_pp_control(intel_dp); |
67a54566 | 4847 | |
8e8232d5 ID |
4848 | pp_on = I915_READ(regs.pp_on); |
4849 | pp_off = I915_READ(regs.pp_off); | |
54648618 | 4850 | if (!IS_BROXTON(dev_priv)) { |
8e8232d5 ID |
4851 | I915_WRITE(regs.pp_ctrl, pp_ctl); |
4852 | pp_div = I915_READ(regs.pp_div); | |
b0a08bec | 4853 | } |
67a54566 DV |
4854 | |
4855 | /* Pull timing values out of registers */ | |
54648618 ID |
4856 | seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
4857 | PANEL_POWER_UP_DELAY_SHIFT; | |
67a54566 | 4858 | |
54648618 ID |
4859 | seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
4860 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
67a54566 | 4861 | |
54648618 ID |
4862 | seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
4863 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
67a54566 | 4864 | |
54648618 ID |
4865 | seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
4866 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
67a54566 | 4867 | |
54648618 | 4868 | if (IS_BROXTON(dev_priv)) { |
b0a08bec VK |
4869 | u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> |
4870 | BXT_POWER_CYCLE_DELAY_SHIFT; | |
4871 | if (tmp > 0) | |
54648618 | 4872 | seq->t11_t12 = (tmp - 1) * 1000; |
b0a08bec | 4873 | else |
54648618 | 4874 | seq->t11_t12 = 0; |
b0a08bec | 4875 | } else { |
54648618 | 4876 | seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
67a54566 | 4877 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
b0a08bec | 4878 | } |
54648618 ID |
4879 | } |
4880 | ||
de9c1b6b ID |
4881 | static void |
4882 | intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) | |
4883 | { | |
4884 | DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
4885 | state_name, | |
4886 | seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); | |
4887 | } | |
4888 | ||
4889 | static void | |
4890 | intel_pps_verify_state(struct drm_i915_private *dev_priv, | |
4891 | struct intel_dp *intel_dp) | |
4892 | { | |
4893 | struct edp_power_seq hw; | |
4894 | struct edp_power_seq *sw = &intel_dp->pps_delays; | |
4895 | ||
4896 | intel_pps_readout_hw_state(dev_priv, intel_dp, &hw); | |
4897 | ||
4898 | if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || | |
4899 | hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { | |
4900 | DRM_ERROR("PPS state mismatch\n"); | |
4901 | intel_pps_dump_state("sw", sw); | |
4902 | intel_pps_dump_state("hw", &hw); | |
4903 | } | |
4904 | } | |
4905 | ||
54648618 ID |
4906 | static void |
4907 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
4908 | struct intel_dp *intel_dp) | |
4909 | { | |
fac5e23e | 4910 | struct drm_i915_private *dev_priv = to_i915(dev); |
54648618 ID |
4911 | struct edp_power_seq cur, vbt, spec, |
4912 | *final = &intel_dp->pps_delays; | |
4913 | ||
4914 | lockdep_assert_held(&dev_priv->pps_mutex); | |
4915 | ||
4916 | /* already initialized? */ | |
4917 | if (final->t11_t12 != 0) | |
4918 | return; | |
4919 | ||
4920 | intel_pps_readout_hw_state(dev_priv, intel_dp, &cur); | |
67a54566 | 4921 | |
de9c1b6b | 4922 | intel_pps_dump_state("cur", &cur); |
67a54566 | 4923 | |
6aa23e65 | 4924 | vbt = dev_priv->vbt.edp.pps; |
67a54566 DV |
4925 | |
4926 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
4927 | * our hw here, which are all in 100usec. */ | |
4928 | spec.t1_t3 = 210 * 10; | |
4929 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
4930 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
4931 | spec.t10 = 500 * 10; | |
4932 | /* This one is special and actually in units of 100ms, but zero | |
4933 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
4934 | * table multiplies it with 1000 to make it in units of 100usec, | |
4935 | * too. */ | |
4936 | spec.t11_t12 = (510 + 100) * 10; | |
4937 | ||
de9c1b6b | 4938 | intel_pps_dump_state("vbt", &vbt); |
67a54566 DV |
4939 | |
4940 | /* Use the max of the register settings and vbt. If both are | |
4941 | * unset, fall back to the spec limits. */ | |
36b5f425 | 4942 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
67a54566 DV |
4943 | spec.field : \ |
4944 | max(cur.field, vbt.field)) | |
4945 | assign_final(t1_t3); | |
4946 | assign_final(t8); | |
4947 | assign_final(t9); | |
4948 | assign_final(t10); | |
4949 | assign_final(t11_t12); | |
4950 | #undef assign_final | |
4951 | ||
36b5f425 | 4952 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
67a54566 DV |
4953 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
4954 | intel_dp->backlight_on_delay = get_delay(t8); | |
4955 | intel_dp->backlight_off_delay = get_delay(t9); | |
4956 | intel_dp->panel_power_down_delay = get_delay(t10); | |
4957 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
4958 | #undef get_delay | |
4959 | ||
f30d26e4 JN |
4960 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
4961 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
4962 | intel_dp->panel_power_cycle_delay); | |
4963 | ||
4964 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
4965 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
de9c1b6b ID |
4966 | |
4967 | /* | |
4968 | * We override the HW backlight delays to 1 because we do manual waits | |
4969 | * on them. For T8, even BSpec recommends doing it. For T9, if we | |
4970 | * don't do this, we'll end up waiting for the backlight off delay | |
4971 | * twice: once when we do the manual sleep, and once when we disable | |
4972 | * the panel and wait for the PP_STATUS bit to become zero. | |
4973 | */ | |
4974 | final->t8 = 1; | |
4975 | final->t9 = 1; | |
f30d26e4 JN |
4976 | } |
4977 | ||
4978 | static void | |
4979 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
36b5f425 | 4980 | struct intel_dp *intel_dp) |
f30d26e4 | 4981 | { |
fac5e23e | 4982 | struct drm_i915_private *dev_priv = to_i915(dev); |
453c5420 | 4983 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
e7dc33f3 | 4984 | int div = dev_priv->rawclk_freq / 1000; |
8e8232d5 | 4985 | struct pps_registers regs; |
ad933b56 | 4986 | enum port port = dp_to_dig_port(intel_dp)->port; |
36b5f425 | 4987 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
453c5420 | 4988 | |
e39b999a | 4989 | lockdep_assert_held(&dev_priv->pps_mutex); |
453c5420 | 4990 | |
8e8232d5 | 4991 | intel_pps_get_registers(dev_priv, intel_dp, ®s); |
453c5420 | 4992 | |
f30d26e4 | 4993 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
de9c1b6b ID |
4994 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); |
4995 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | | |
f30d26e4 | 4996 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
67a54566 DV |
4997 | /* Compute the divisor for the pp clock, simply match the Bspec |
4998 | * formula. */ | |
b0a08bec | 4999 | if (IS_BROXTON(dev)) { |
8e8232d5 | 5000 | pp_div = I915_READ(regs.pp_ctrl); |
b0a08bec VK |
5001 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; |
5002 | pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) | |
5003 | << BXT_POWER_CYCLE_DELAY_SHIFT); | |
5004 | } else { | |
5005 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; | |
5006 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) | |
5007 | << PANEL_POWER_CYCLE_DELAY_SHIFT); | |
5008 | } | |
67a54566 DV |
5009 | |
5010 | /* Haswell doesn't have any port selection bits for the panel | |
5011 | * power sequencer any more. */ | |
666a4537 | 5012 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ad933b56 | 5013 | port_sel = PANEL_PORT_SELECT_VLV(port); |
bc7d38a4 | 5014 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
ad933b56 | 5015 | if (port == PORT_A) |
a24c144c | 5016 | port_sel = PANEL_PORT_SELECT_DPA; |
67a54566 | 5017 | else |
a24c144c | 5018 | port_sel = PANEL_PORT_SELECT_DPD; |
67a54566 DV |
5019 | } |
5020 | ||
453c5420 JB |
5021 | pp_on |= port_sel; |
5022 | ||
8e8232d5 ID |
5023 | I915_WRITE(regs.pp_on, pp_on); |
5024 | I915_WRITE(regs.pp_off, pp_off); | |
b0a08bec | 5025 | if (IS_BROXTON(dev)) |
8e8232d5 | 5026 | I915_WRITE(regs.pp_ctrl, pp_div); |
b0a08bec | 5027 | else |
8e8232d5 | 5028 | I915_WRITE(regs.pp_div, pp_div); |
67a54566 | 5029 | |
67a54566 | 5030 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
8e8232d5 ID |
5031 | I915_READ(regs.pp_on), |
5032 | I915_READ(regs.pp_off), | |
b0a08bec | 5033 | IS_BROXTON(dev) ? |
8e8232d5 ID |
5034 | (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : |
5035 | I915_READ(regs.pp_div)); | |
f684960e CW |
5036 | } |
5037 | ||
335f752b ID |
5038 | static void intel_dp_pps_init(struct drm_device *dev, |
5039 | struct intel_dp *intel_dp) | |
5040 | { | |
5041 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { | |
5042 | vlv_initial_power_sequencer_setup(intel_dp); | |
5043 | } else { | |
5044 | intel_dp_init_panel_power_sequencer(dev, intel_dp); | |
5045 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp); | |
5046 | } | |
5047 | } | |
5048 | ||
b33a2815 VK |
5049 | /** |
5050 | * intel_dp_set_drrs_state - program registers for RR switch to take effect | |
5051 | * @dev: DRM device | |
e896402c | 5052 | * @crtc_state: a pointer to the active intel_crtc_state |
b33a2815 VK |
5053 | * @refresh_rate: RR to be programmed |
5054 | * | |
5055 | * This function gets called when refresh rate (RR) has to be changed from | |
5056 | * one frequency to another. Switches can be between high and low RR | |
5057 | * supported by the panel or to any other RR based on media playback (in | |
5058 | * this case, RR value needs to be passed from user space). | |
5059 | * | |
5060 | * The caller of this function needs to take a lock on dev_priv->drrs. | |
5061 | */ | |
85cb48a1 ML |
5062 | static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, |
5063 | struct intel_crtc_state *crtc_state, | |
5064 | int refresh_rate) | |
439d7ac0 | 5065 | { |
439d7ac0 | 5066 | struct intel_encoder *encoder; |
96178eeb VK |
5067 | struct intel_digital_port *dig_port = NULL; |
5068 | struct intel_dp *intel_dp = dev_priv->drrs.dp; | |
85cb48a1 | 5069 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
96178eeb | 5070 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
439d7ac0 PB |
5071 | |
5072 | if (refresh_rate <= 0) { | |
5073 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); | |
5074 | return; | |
5075 | } | |
5076 | ||
96178eeb VK |
5077 | if (intel_dp == NULL) { |
5078 | DRM_DEBUG_KMS("DRRS not supported.\n"); | |
439d7ac0 PB |
5079 | return; |
5080 | } | |
5081 | ||
1fcc9d1c | 5082 | /* |
e4d59f6b RV |
5083 | * FIXME: This needs proper synchronization with psr state for some |
5084 | * platforms that cannot have PSR and DRRS enabled at the same time. | |
1fcc9d1c | 5085 | */ |
439d7ac0 | 5086 | |
96178eeb VK |
5087 | dig_port = dp_to_dig_port(intel_dp); |
5088 | encoder = &dig_port->base; | |
723f9aab | 5089 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
439d7ac0 PB |
5090 | |
5091 | if (!intel_crtc) { | |
5092 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); | |
5093 | return; | |
5094 | } | |
5095 | ||
96178eeb | 5096 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
439d7ac0 PB |
5097 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
5098 | return; | |
5099 | } | |
5100 | ||
96178eeb VK |
5101 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
5102 | refresh_rate) | |
439d7ac0 PB |
5103 | index = DRRS_LOW_RR; |
5104 | ||
96178eeb | 5105 | if (index == dev_priv->drrs.refresh_rate_type) { |
439d7ac0 PB |
5106 | DRM_DEBUG_KMS( |
5107 | "DRRS requested for previously set RR...ignoring\n"); | |
5108 | return; | |
5109 | } | |
5110 | ||
85cb48a1 | 5111 | if (!crtc_state->base.active) { |
439d7ac0 PB |
5112 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
5113 | return; | |
5114 | } | |
5115 | ||
85cb48a1 | 5116 | if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { |
a4c30b1d VK |
5117 | switch (index) { |
5118 | case DRRS_HIGH_RR: | |
5119 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
5120 | break; | |
5121 | case DRRS_LOW_RR: | |
5122 | intel_dp_set_m_n(intel_crtc, M2_N2); | |
5123 | break; | |
5124 | case DRRS_MAX_RR: | |
5125 | default: | |
5126 | DRM_ERROR("Unsupported refreshrate type\n"); | |
5127 | } | |
85cb48a1 ML |
5128 | } else if (INTEL_GEN(dev_priv) > 6) { |
5129 | i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); | |
649636ef | 5130 | u32 val; |
a4c30b1d | 5131 | |
649636ef | 5132 | val = I915_READ(reg); |
439d7ac0 | 5133 | if (index > DRRS_HIGH_RR) { |
85cb48a1 | 5134 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
5135 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5136 | else | |
5137 | val |= PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 | 5138 | } else { |
85cb48a1 | 5139 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
5140 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5141 | else | |
5142 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 PB |
5143 | } |
5144 | I915_WRITE(reg, val); | |
5145 | } | |
5146 | ||
4e9ac947 VK |
5147 | dev_priv->drrs.refresh_rate_type = index; |
5148 | ||
5149 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); | |
5150 | } | |
5151 | ||
b33a2815 VK |
5152 | /** |
5153 | * intel_edp_drrs_enable - init drrs struct if supported | |
5154 | * @intel_dp: DP struct | |
5155 | * | |
5156 | * Initializes frontbuffer_bits and drrs.dp | |
5157 | */ | |
85cb48a1 ML |
5158 | void intel_edp_drrs_enable(struct intel_dp *intel_dp, |
5159 | struct intel_crtc_state *crtc_state) | |
c395578e VK |
5160 | { |
5161 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 5162 | struct drm_i915_private *dev_priv = to_i915(dev); |
c395578e | 5163 | |
85cb48a1 | 5164 | if (!crtc_state->has_drrs) { |
c395578e VK |
5165 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); |
5166 | return; | |
5167 | } | |
5168 | ||
5169 | mutex_lock(&dev_priv->drrs.mutex); | |
5170 | if (WARN_ON(dev_priv->drrs.dp)) { | |
5171 | DRM_ERROR("DRRS already enabled\n"); | |
5172 | goto unlock; | |
5173 | } | |
5174 | ||
5175 | dev_priv->drrs.busy_frontbuffer_bits = 0; | |
5176 | ||
5177 | dev_priv->drrs.dp = intel_dp; | |
5178 | ||
5179 | unlock: | |
5180 | mutex_unlock(&dev_priv->drrs.mutex); | |
5181 | } | |
5182 | ||
b33a2815 VK |
5183 | /** |
5184 | * intel_edp_drrs_disable - Disable DRRS | |
5185 | * @intel_dp: DP struct | |
5186 | * | |
5187 | */ | |
85cb48a1 ML |
5188 | void intel_edp_drrs_disable(struct intel_dp *intel_dp, |
5189 | struct intel_crtc_state *old_crtc_state) | |
c395578e VK |
5190 | { |
5191 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 5192 | struct drm_i915_private *dev_priv = to_i915(dev); |
c395578e | 5193 | |
85cb48a1 | 5194 | if (!old_crtc_state->has_drrs) |
c395578e VK |
5195 | return; |
5196 | ||
5197 | mutex_lock(&dev_priv->drrs.mutex); | |
5198 | if (!dev_priv->drrs.dp) { | |
5199 | mutex_unlock(&dev_priv->drrs.mutex); | |
5200 | return; | |
5201 | } | |
5202 | ||
5203 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) | |
85cb48a1 ML |
5204 | intel_dp_set_drrs_state(dev_priv, old_crtc_state, |
5205 | intel_dp->attached_connector->panel.fixed_mode->vrefresh); | |
c395578e VK |
5206 | |
5207 | dev_priv->drrs.dp = NULL; | |
5208 | mutex_unlock(&dev_priv->drrs.mutex); | |
5209 | ||
5210 | cancel_delayed_work_sync(&dev_priv->drrs.work); | |
5211 | } | |
5212 | ||
4e9ac947 VK |
5213 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
5214 | { | |
5215 | struct drm_i915_private *dev_priv = | |
5216 | container_of(work, typeof(*dev_priv), drrs.work.work); | |
5217 | struct intel_dp *intel_dp; | |
5218 | ||
5219 | mutex_lock(&dev_priv->drrs.mutex); | |
5220 | ||
5221 | intel_dp = dev_priv->drrs.dp; | |
5222 | ||
5223 | if (!intel_dp) | |
5224 | goto unlock; | |
5225 | ||
439d7ac0 | 5226 | /* |
4e9ac947 VK |
5227 | * The delayed work can race with an invalidate hence we need to |
5228 | * recheck. | |
439d7ac0 PB |
5229 | */ |
5230 | ||
4e9ac947 VK |
5231 | if (dev_priv->drrs.busy_frontbuffer_bits) |
5232 | goto unlock; | |
439d7ac0 | 5233 | |
85cb48a1 ML |
5234 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) { |
5235 | struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; | |
5236 | ||
5237 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, | |
5238 | intel_dp->attached_connector->panel.downclock_mode->vrefresh); | |
5239 | } | |
439d7ac0 | 5240 | |
4e9ac947 | 5241 | unlock: |
4e9ac947 | 5242 | mutex_unlock(&dev_priv->drrs.mutex); |
439d7ac0 PB |
5243 | } |
5244 | ||
b33a2815 | 5245 | /** |
0ddfd203 | 5246 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
5748b6a1 | 5247 | * @dev_priv: i915 device |
b33a2815 VK |
5248 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5249 | * | |
0ddfd203 R |
5250 | * This function gets called everytime rendering on the given planes start. |
5251 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). | |
b33a2815 VK |
5252 | * |
5253 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5254 | */ | |
5748b6a1 CW |
5255 | void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, |
5256 | unsigned int frontbuffer_bits) | |
a93fad0f | 5257 | { |
a93fad0f VK |
5258 | struct drm_crtc *crtc; |
5259 | enum pipe pipe; | |
5260 | ||
9da7d693 | 5261 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5262 | return; |
5263 | ||
88f933a8 | 5264 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5265 | |
a93fad0f | 5266 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5267 | if (!dev_priv->drrs.dp) { |
5268 | mutex_unlock(&dev_priv->drrs.mutex); | |
5269 | return; | |
5270 | } | |
5271 | ||
a93fad0f VK |
5272 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5273 | pipe = to_intel_crtc(crtc)->pipe; | |
5274 | ||
c1d038c6 DV |
5275 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5276 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; | |
5277 | ||
0ddfd203 | 5278 | /* invalidate means busy screen hence upclock */ |
c1d038c6 | 5279 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 ML |
5280 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
5281 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); | |
a93fad0f | 5282 | |
a93fad0f VK |
5283 | mutex_unlock(&dev_priv->drrs.mutex); |
5284 | } | |
5285 | ||
b33a2815 | 5286 | /** |
0ddfd203 | 5287 | * intel_edp_drrs_flush - Restart Idleness DRRS |
5748b6a1 | 5288 | * @dev_priv: i915 device |
b33a2815 VK |
5289 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5290 | * | |
0ddfd203 R |
5291 | * This function gets called every time rendering on the given planes has |
5292 | * completed or flip on a crtc is completed. So DRRS should be upclocked | |
5293 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, | |
5294 | * if no other planes are dirty. | |
b33a2815 VK |
5295 | * |
5296 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5297 | */ | |
5748b6a1 CW |
5298 | void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, |
5299 | unsigned int frontbuffer_bits) | |
a93fad0f | 5300 | { |
a93fad0f VK |
5301 | struct drm_crtc *crtc; |
5302 | enum pipe pipe; | |
5303 | ||
9da7d693 | 5304 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5305 | return; |
5306 | ||
88f933a8 | 5307 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5308 | |
a93fad0f | 5309 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5310 | if (!dev_priv->drrs.dp) { |
5311 | mutex_unlock(&dev_priv->drrs.mutex); | |
5312 | return; | |
5313 | } | |
5314 | ||
a93fad0f VK |
5315 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5316 | pipe = to_intel_crtc(crtc)->pipe; | |
c1d038c6 DV |
5317 | |
5318 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
a93fad0f VK |
5319 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
5320 | ||
0ddfd203 | 5321 | /* flush means busy screen hence upclock */ |
c1d038c6 | 5322 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 ML |
5323 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
5324 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); | |
0ddfd203 R |
5325 | |
5326 | /* | |
5327 | * flush also means no more activity hence schedule downclock, if all | |
5328 | * other fbs are quiescent too | |
5329 | */ | |
5330 | if (!dev_priv->drrs.busy_frontbuffer_bits) | |
a93fad0f VK |
5331 | schedule_delayed_work(&dev_priv->drrs.work, |
5332 | msecs_to_jiffies(1000)); | |
5333 | mutex_unlock(&dev_priv->drrs.mutex); | |
5334 | } | |
5335 | ||
b33a2815 VK |
5336 | /** |
5337 | * DOC: Display Refresh Rate Switching (DRRS) | |
5338 | * | |
5339 | * Display Refresh Rate Switching (DRRS) is a power conservation feature | |
5340 | * which enables swtching between low and high refresh rates, | |
5341 | * dynamically, based on the usage scenario. This feature is applicable | |
5342 | * for internal panels. | |
5343 | * | |
5344 | * Indication that the panel supports DRRS is given by the panel EDID, which | |
5345 | * would list multiple refresh rates for one resolution. | |
5346 | * | |
5347 | * DRRS is of 2 types - static and seamless. | |
5348 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset | |
5349 | * (may appear as a blink on screen) and is used in dock-undock scenario. | |
5350 | * Seamless DRRS involves changing RR without any visual effect to the user | |
5351 | * and can be used during normal system usage. This is done by programming | |
5352 | * certain registers. | |
5353 | * | |
5354 | * Support for static/seamless DRRS may be indicated in the VBT based on | |
5355 | * inputs from the panel spec. | |
5356 | * | |
5357 | * DRRS saves power by switching to low RR based on usage scenarios. | |
5358 | * | |
2e7a5701 DV |
5359 | * The implementation is based on frontbuffer tracking implementation. When |
5360 | * there is a disturbance on the screen triggered by user activity or a periodic | |
5361 | * system activity, DRRS is disabled (RR is changed to high RR). When there is | |
5362 | * no movement on screen, after a timeout of 1 second, a switch to low RR is | |
5363 | * made. | |
5364 | * | |
5365 | * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() | |
5366 | * and intel_edp_drrs_flush() are called. | |
b33a2815 VK |
5367 | * |
5368 | * DRRS can be further extended to support other internal panels and also | |
5369 | * the scenario of video playback wherein RR is set based on the rate | |
5370 | * requested by userspace. | |
5371 | */ | |
5372 | ||
5373 | /** | |
5374 | * intel_dp_drrs_init - Init basic DRRS work and mutex. | |
5375 | * @intel_connector: eDP connector | |
5376 | * @fixed_mode: preferred mode of panel | |
5377 | * | |
5378 | * This function is called only once at driver load to initialize basic | |
5379 | * DRRS stuff. | |
5380 | * | |
5381 | * Returns: | |
5382 | * Downclock mode if panel supports it, else return NULL. | |
5383 | * DRRS support is determined by the presence of downclock mode (apart | |
5384 | * from VBT setting). | |
5385 | */ | |
4f9db5b5 | 5386 | static struct drm_display_mode * |
96178eeb VK |
5387 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
5388 | struct drm_display_mode *fixed_mode) | |
4f9db5b5 PB |
5389 | { |
5390 | struct drm_connector *connector = &intel_connector->base; | |
96178eeb | 5391 | struct drm_device *dev = connector->dev; |
fac5e23e | 5392 | struct drm_i915_private *dev_priv = to_i915(dev); |
4f9db5b5 PB |
5393 | struct drm_display_mode *downclock_mode = NULL; |
5394 | ||
9da7d693 DV |
5395 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
5396 | mutex_init(&dev_priv->drrs.mutex); | |
5397 | ||
4f9db5b5 PB |
5398 | if (INTEL_INFO(dev)->gen <= 6) { |
5399 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); | |
5400 | return NULL; | |
5401 | } | |
5402 | ||
5403 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { | |
4079b8d1 | 5404 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
4f9db5b5 PB |
5405 | return NULL; |
5406 | } | |
5407 | ||
5408 | downclock_mode = intel_find_panel_downclock | |
5409 | (dev, fixed_mode, connector); | |
5410 | ||
5411 | if (!downclock_mode) { | |
a1d26342 | 5412 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
4f9db5b5 PB |
5413 | return NULL; |
5414 | } | |
5415 | ||
96178eeb | 5416 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
4f9db5b5 | 5417 | |
96178eeb | 5418 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
4079b8d1 | 5419 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
4f9db5b5 PB |
5420 | return downclock_mode; |
5421 | } | |
5422 | ||
ed92f0b2 | 5423 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
36b5f425 | 5424 | struct intel_connector *intel_connector) |
ed92f0b2 PZ |
5425 | { |
5426 | struct drm_connector *connector = &intel_connector->base; | |
5427 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
63635217 PZ |
5428 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5429 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 5430 | struct drm_i915_private *dev_priv = to_i915(dev); |
ed92f0b2 | 5431 | struct drm_display_mode *fixed_mode = NULL; |
4f9db5b5 | 5432 | struct drm_display_mode *downclock_mode = NULL; |
ed92f0b2 PZ |
5433 | bool has_dpcd; |
5434 | struct drm_display_mode *scan; | |
5435 | struct edid *edid; | |
6517d273 | 5436 | enum pipe pipe = INVALID_PIPE; |
ed92f0b2 PZ |
5437 | |
5438 | if (!is_edp(intel_dp)) | |
5439 | return true; | |
5440 | ||
97a824e1 ID |
5441 | /* |
5442 | * On IBX/CPT we may get here with LVDS already registered. Since the | |
5443 | * driver uses the only internal power sequencer available for both | |
5444 | * eDP and LVDS bail out early in this case to prevent interfering | |
5445 | * with an already powered-on LVDS power sequencer. | |
5446 | */ | |
5447 | if (intel_get_lvds_encoder(dev)) { | |
5448 | WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); | |
5449 | DRM_INFO("LVDS was detected, not registering eDP\n"); | |
5450 | ||
5451 | return false; | |
5452 | } | |
5453 | ||
49e6bc51 | 5454 | pps_lock(intel_dp); |
b4d06ede ID |
5455 | |
5456 | intel_dp_init_panel_power_timestamps(intel_dp); | |
335f752b | 5457 | intel_dp_pps_init(dev, intel_dp); |
49e6bc51 | 5458 | intel_edp_panel_vdd_sanitize(intel_dp); |
b4d06ede | 5459 | |
49e6bc51 | 5460 | pps_unlock(intel_dp); |
63635217 | 5461 | |
ed92f0b2 | 5462 | /* Cache DPCD and EDID for edp. */ |
fe5a66f9 | 5463 | has_dpcd = intel_edp_init_dpcd(intel_dp); |
ed92f0b2 | 5464 | |
fe5a66f9 | 5465 | if (!has_dpcd) { |
ed92f0b2 PZ |
5466 | /* if this fails, presume the device is a ghost */ |
5467 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); | |
b4d06ede | 5468 | goto out_vdd_off; |
ed92f0b2 PZ |
5469 | } |
5470 | ||
060c8778 | 5471 | mutex_lock(&dev->mode_config.mutex); |
0b99836f | 5472 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
ed92f0b2 PZ |
5473 | if (edid) { |
5474 | if (drm_add_edid_modes(connector, edid)) { | |
5475 | drm_mode_connector_update_edid_property(connector, | |
5476 | edid); | |
5477 | drm_edid_to_eld(connector, edid); | |
5478 | } else { | |
5479 | kfree(edid); | |
5480 | edid = ERR_PTR(-EINVAL); | |
5481 | } | |
5482 | } else { | |
5483 | edid = ERR_PTR(-ENOENT); | |
5484 | } | |
5485 | intel_connector->edid = edid; | |
5486 | ||
5487 | /* prefer fixed mode from EDID if available */ | |
5488 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
5489 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
5490 | fixed_mode = drm_mode_duplicate(dev, scan); | |
4f9db5b5 | 5491 | downclock_mode = intel_dp_drrs_init( |
4f9db5b5 | 5492 | intel_connector, fixed_mode); |
ed92f0b2 PZ |
5493 | break; |
5494 | } | |
5495 | } | |
5496 | ||
5497 | /* fallback to VBT if available for eDP */ | |
5498 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { | |
5499 | fixed_mode = drm_mode_duplicate(dev, | |
5500 | dev_priv->vbt.lfp_lvds_vbt_mode); | |
df457245 | 5501 | if (fixed_mode) { |
ed92f0b2 | 5502 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
df457245 VS |
5503 | connector->display_info.width_mm = fixed_mode->width_mm; |
5504 | connector->display_info.height_mm = fixed_mode->height_mm; | |
5505 | } | |
ed92f0b2 | 5506 | } |
060c8778 | 5507 | mutex_unlock(&dev->mode_config.mutex); |
ed92f0b2 | 5508 | |
666a4537 | 5509 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
01527b31 CT |
5510 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
5511 | register_reboot_notifier(&intel_dp->edp_notifier); | |
6517d273 VS |
5512 | |
5513 | /* | |
5514 | * Figure out the current pipe for the initial backlight setup. | |
5515 | * If the current pipe isn't valid, try the PPS pipe, and if that | |
5516 | * fails just assume pipe A. | |
5517 | */ | |
5518 | if (IS_CHERRYVIEW(dev)) | |
5519 | pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP); | |
5520 | else | |
5521 | pipe = PORT_TO_PIPE(intel_dp->DP); | |
5522 | ||
5523 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5524 | pipe = intel_dp->pps_pipe; | |
5525 | ||
5526 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5527 | pipe = PIPE_A; | |
5528 | ||
5529 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", | |
5530 | pipe_name(pipe)); | |
01527b31 CT |
5531 | } |
5532 | ||
4f9db5b5 | 5533 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
5507faeb | 5534 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
6517d273 | 5535 | intel_panel_setup_backlight(connector, pipe); |
ed92f0b2 PZ |
5536 | |
5537 | return true; | |
b4d06ede ID |
5538 | |
5539 | out_vdd_off: | |
5540 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
5541 | /* | |
5542 | * vdd might still be enabled do to the delayed vdd off. | |
5543 | * Make sure vdd is actually turned off here. | |
5544 | */ | |
5545 | pps_lock(intel_dp); | |
5546 | edp_panel_vdd_off_sync(intel_dp); | |
5547 | pps_unlock(intel_dp); | |
5548 | ||
5549 | return false; | |
ed92f0b2 PZ |
5550 | } |
5551 | ||
16c25533 | 5552 | bool |
f0fec3f2 PZ |
5553 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
5554 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 5555 | { |
f0fec3f2 PZ |
5556 | struct drm_connector *connector = &intel_connector->base; |
5557 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
5558 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
5559 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 5560 | struct drm_i915_private *dev_priv = to_i915(dev); |
174edf1f | 5561 | enum port port = intel_dig_port->port; |
7a418e34 | 5562 | int type; |
a4fc5ed6 | 5563 | |
ccb1a831 VS |
5564 | if (WARN(intel_dig_port->max_lanes < 1, |
5565 | "Not enough lanes (%d) for DP on port %c\n", | |
5566 | intel_dig_port->max_lanes, port_name(port))) | |
5567 | return false; | |
5568 | ||
a4a5d2f8 VS |
5569 | intel_dp->pps_pipe = INVALID_PIPE; |
5570 | ||
ec5b01dd | 5571 | /* intel_dp vfuncs */ |
b6b5e383 DL |
5572 | if (INTEL_INFO(dev)->gen >= 9) |
5573 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; | |
ec5b01dd DL |
5574 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
5575 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; | |
5576 | else if (HAS_PCH_SPLIT(dev)) | |
5577 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; | |
5578 | else | |
6ffb1be7 | 5579 | intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; |
ec5b01dd | 5580 | |
b9ca5fad DL |
5581 | if (INTEL_INFO(dev)->gen >= 9) |
5582 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; | |
5583 | else | |
6ffb1be7 | 5584 | intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; |
153b1100 | 5585 | |
ad64217b ACO |
5586 | if (HAS_DDI(dev)) |
5587 | intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; | |
5588 | ||
0767935e DV |
5589 | /* Preserve the current hw state. */ |
5590 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
dd06f90e | 5591 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 5592 | |
3b32a35b | 5593 | if (intel_dp_is_edp(dev, port)) |
b329530c | 5594 | type = DRM_MODE_CONNECTOR_eDP; |
3b32a35b VS |
5595 | else |
5596 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
b329530c | 5597 | |
f7d24902 ID |
5598 | /* |
5599 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
5600 | * for DP the encoder type can be set by the caller to | |
5601 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
5602 | */ | |
5603 | if (type == DRM_MODE_CONNECTOR_eDP) | |
5604 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
5605 | ||
c17ed5b5 | 5606 | /* eDP only on port B and/or C on vlv/chv */ |
666a4537 WB |
5607 | if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
5608 | is_edp(intel_dp) && port != PORT_B && port != PORT_C)) | |
c17ed5b5 VS |
5609 | return false; |
5610 | ||
e7281eab ID |
5611 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
5612 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
5613 | port_name(port)); | |
5614 | ||
b329530c | 5615 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
5616 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
5617 | ||
a4fc5ed6 KP |
5618 | connector->interlace_allowed = true; |
5619 | connector->doublescan_allowed = 0; | |
5620 | ||
7a418e34 CW |
5621 | intel_dp_aux_init(intel_dp, intel_connector); |
5622 | ||
f0fec3f2 | 5623 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
4be73780 | 5624 | edp_panel_vdd_work); |
a4fc5ed6 | 5625 | |
df0e9248 | 5626 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 | 5627 | |
affa9354 | 5628 | if (HAS_DDI(dev)) |
bcbc889b PZ |
5629 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
5630 | else | |
5631 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
5632 | ||
0b99836f | 5633 | /* Set up the hotplug pin. */ |
ab9d7c30 PZ |
5634 | switch (port) { |
5635 | case PORT_A: | |
1d843f9d | 5636 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
5637 | break; |
5638 | case PORT_B: | |
1d843f9d | 5639 | intel_encoder->hpd_pin = HPD_PORT_B; |
e87a005d | 5640 | if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) |
cf1d5883 | 5641 | intel_encoder->hpd_pin = HPD_PORT_A; |
ab9d7c30 PZ |
5642 | break; |
5643 | case PORT_C: | |
1d843f9d | 5644 | intel_encoder->hpd_pin = HPD_PORT_C; |
ab9d7c30 PZ |
5645 | break; |
5646 | case PORT_D: | |
1d843f9d | 5647 | intel_encoder->hpd_pin = HPD_PORT_D; |
ab9d7c30 | 5648 | break; |
26951caf XZ |
5649 | case PORT_E: |
5650 | intel_encoder->hpd_pin = HPD_PORT_E; | |
5651 | break; | |
ab9d7c30 | 5652 | default: |
ad1c0b19 | 5653 | BUG(); |
5eb08b69 ZW |
5654 | } |
5655 | ||
0e32b39c | 5656 | /* init MST on ports that can support it */ |
f8e58ddf | 5657 | if (HAS_DP_MST(dev) && !is_edp(intel_dp) && |
0c9b3715 JN |
5658 | (port == PORT_B || port == PORT_C || port == PORT_D)) |
5659 | intel_dp_mst_encoder_init(intel_dig_port, | |
5660 | intel_connector->base.base.id); | |
0e32b39c | 5661 | |
36b5f425 | 5662 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
a121f4e5 VS |
5663 | intel_dp_aux_fini(intel_dp); |
5664 | intel_dp_mst_encoder_cleanup(intel_dig_port); | |
5665 | goto fail; | |
b2f246a8 | 5666 | } |
32f9d658 | 5667 | |
f684960e CW |
5668 | intel_dp_add_properties(intel_dp, connector); |
5669 | ||
a4fc5ed6 KP |
5670 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
5671 | * 0xd. Failure to do so will result in spurious interrupts being | |
5672 | * generated on the port when a cable is not attached. | |
5673 | */ | |
5674 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
5675 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
5676 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
5677 | } | |
16c25533 PZ |
5678 | |
5679 | return true; | |
a121f4e5 VS |
5680 | |
5681 | fail: | |
a121f4e5 VS |
5682 | drm_connector_cleanup(connector); |
5683 | ||
5684 | return false; | |
a4fc5ed6 | 5685 | } |
f0fec3f2 | 5686 | |
457c52d8 CW |
5687 | bool intel_dp_init(struct drm_device *dev, |
5688 | i915_reg_t output_reg, | |
5689 | enum port port) | |
f0fec3f2 | 5690 | { |
fac5e23e | 5691 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0fec3f2 PZ |
5692 | struct intel_digital_port *intel_dig_port; |
5693 | struct intel_encoder *intel_encoder; | |
5694 | struct drm_encoder *encoder; | |
5695 | struct intel_connector *intel_connector; | |
5696 | ||
b14c5679 | 5697 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
f0fec3f2 | 5698 | if (!intel_dig_port) |
457c52d8 | 5699 | return false; |
f0fec3f2 | 5700 | |
08d9bc92 | 5701 | intel_connector = intel_connector_alloc(); |
11aee0f6 SM |
5702 | if (!intel_connector) |
5703 | goto err_connector_alloc; | |
f0fec3f2 PZ |
5704 | |
5705 | intel_encoder = &intel_dig_port->base; | |
5706 | encoder = &intel_encoder->base; | |
5707 | ||
893da0c9 | 5708 | if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
580d8ed5 | 5709 | DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port))) |
893da0c9 | 5710 | goto err_encoder_init; |
f0fec3f2 | 5711 | |
5bfe2ac0 | 5712 | intel_encoder->compute_config = intel_dp_compute_config; |
00c09d70 | 5713 | intel_encoder->disable = intel_disable_dp; |
00c09d70 | 5714 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
045ac3b5 | 5715 | intel_encoder->get_config = intel_dp_get_config; |
07f9cd0b | 5716 | intel_encoder->suspend = intel_dp_encoder_suspend; |
e4a1d846 | 5717 | if (IS_CHERRYVIEW(dev)) { |
9197c88b | 5718 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
e4a1d846 CML |
5719 | intel_encoder->pre_enable = chv_pre_enable_dp; |
5720 | intel_encoder->enable = vlv_enable_dp; | |
580d3811 | 5721 | intel_encoder->post_disable = chv_post_disable_dp; |
d6db995f | 5722 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
e4a1d846 | 5723 | } else if (IS_VALLEYVIEW(dev)) { |
ecff4f3b | 5724 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
5725 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
5726 | intel_encoder->enable = vlv_enable_dp; | |
49277c31 | 5727 | intel_encoder->post_disable = vlv_post_disable_dp; |
ab1f90f9 | 5728 | } else { |
ecff4f3b JN |
5729 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
5730 | intel_encoder->enable = g4x_enable_dp; | |
08aff3fe VS |
5731 | if (INTEL_INFO(dev)->gen >= 5) |
5732 | intel_encoder->post_disable = ilk_post_disable_dp; | |
ab1f90f9 | 5733 | } |
f0fec3f2 | 5734 | |
174edf1f | 5735 | intel_dig_port->port = port; |
f0fec3f2 | 5736 | intel_dig_port->dp.output_reg = output_reg; |
ccb1a831 | 5737 | intel_dig_port->max_lanes = 4; |
f0fec3f2 | 5738 | |
cca0502b | 5739 | intel_encoder->type = INTEL_OUTPUT_DP; |
882ec384 VS |
5740 | if (IS_CHERRYVIEW(dev)) { |
5741 | if (port == PORT_D) | |
5742 | intel_encoder->crtc_mask = 1 << 2; | |
5743 | else | |
5744 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
5745 | } else { | |
5746 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
5747 | } | |
bc079e8b | 5748 | intel_encoder->cloneable = 0; |
f0fec3f2 | 5749 | |
13cf5504 | 5750 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
5fcece80 | 5751 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
13cf5504 | 5752 | |
11aee0f6 SM |
5753 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
5754 | goto err_init_connector; | |
5755 | ||
457c52d8 | 5756 | return true; |
11aee0f6 SM |
5757 | |
5758 | err_init_connector: | |
5759 | drm_encoder_cleanup(encoder); | |
893da0c9 | 5760 | err_encoder_init: |
11aee0f6 SM |
5761 | kfree(intel_connector); |
5762 | err_connector_alloc: | |
5763 | kfree(intel_dig_port); | |
457c52d8 | 5764 | return false; |
f0fec3f2 | 5765 | } |
0e32b39c DA |
5766 | |
5767 | void intel_dp_mst_suspend(struct drm_device *dev) | |
5768 | { | |
fac5e23e | 5769 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e32b39c DA |
5770 | int i; |
5771 | ||
5772 | /* disable MST */ | |
5773 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 5774 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
5aa56969 VS |
5775 | |
5776 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) | |
0e32b39c DA |
5777 | continue; |
5778 | ||
5aa56969 VS |
5779 | if (intel_dig_port->dp.is_mst) |
5780 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); | |
0e32b39c DA |
5781 | } |
5782 | } | |
5783 | ||
5784 | void intel_dp_mst_resume(struct drm_device *dev) | |
5785 | { | |
fac5e23e | 5786 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e32b39c DA |
5787 | int i; |
5788 | ||
5789 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 5790 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
5aa56969 | 5791 | int ret; |
0e32b39c | 5792 | |
5aa56969 VS |
5793 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) |
5794 | continue; | |
0e32b39c | 5795 | |
5aa56969 VS |
5796 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
5797 | if (ret) | |
5798 | intel_dp_check_mst_status(&intel_dig_port->dp); | |
0e32b39c DA |
5799 | } |
5800 | } |