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drm/i915: Make INTEL_DEVID only take dev_priv
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_crtc_helper.h>
37#include <drm/drm_edid.h>
a4fc5ed6 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
a4fc5ed6 40#include "i915_drv.h"
a4fc5ed6 41
a4fc5ed6
KP		 42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
559be30c
TP		 44/* Compliance test status bits */
45#define INTEL_DP_RESOLUTION_SHIFT_MASK 0
46#define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
47#define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
48#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
49
9dd4ffdf 50struct dp_link_dpll {
840b32b7 51 int clock;
9dd4ffdf
CML		 52 struct dpll dpll;
53};
54
55static const struct dp_link_dpll gen4_dpll[] = {
840b32b7 56 { 162000,
9dd4ffdf 57 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
840b32b7 58 { 270000,
9dd4ffdf
CML		 59 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
60};
61
62static const struct dp_link_dpll pch_dpll[] = {
840b32b7 63 { 162000,
9dd4ffdf 64 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
840b32b7 65 { 270000,
9dd4ffdf
CML		 66 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
67};
68
65ce4bf5 69static const struct dp_link_dpll vlv_dpll[] = {
840b32b7 70 { 162000,
58f6e632 71 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
840b32b7 72 { 270000,
65ce4bf5
CML		 73 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
74};
75
ef9348c8
CML		 76/*
77 * CHV supports eDP 1.4 that have more link rates.
78 * Below only provides the fixed rate but exclude variable rate.
79 */
80static const struct dp_link_dpll chv_dpll[] = {
81 /*
82 * CHV requires to program fractional division for m2.
83 * m2 is stored in fixed point format using formula below
84 * (m2_int << 22) | m2_fraction
85 */
840b32b7 86 { 162000, /* m2_int = 32, m2_fraction = 1677722 */
ef9348c8 87 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
840b32b7 88 { 270000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8 89 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
840b32b7 90 { 540000, /* m2_int = 27, m2_fraction = 0 */
ef9348c8
CML		 91 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
92};
637a9c63 93
64987fc5
SJ		 94static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
95 324000, 432000, 540000 };
637a9c63 96static const int skl_rates[] = { 162000, 216000, 270000,
f4896f15
VS		 97 324000, 432000, 540000 };
98static const int default_rates[] = { 162000, 270000, 540000 };
ef9348c8 99
cfcb0fc9
JB		 100/**
101 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
102 * @intel_dp: DP struct
103 *
104 * If a CPU or PCH DP output is attached to an eDP panel, this function
105 * will return true, and false otherwise.
106 */
107static bool is_edp(struct intel_dp *intel_dp)
108{
da63a9f2
PZ		 109 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
110
111 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 112}
113
68b4d824 114static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 115{
68b4d824
ID		 116 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
117
118 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 119}
120
df0e9248
CW		 121static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
122{
fa90ecef 123 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 124}
125
ea5b213a 126static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 127static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 128static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 129static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a8c3344e
VS		 130static void vlv_steal_power_sequencer(struct drm_device *dev,
131 enum pipe pipe);
f21a2198 132static void intel_dp_unset_edid(struct intel_dp *intel_dp);
a4fc5ed6 133
ed4e9c1d
VS		 134static int
135intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 136{
7183dc29 137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 138
139 switch (max_link_bw) {
140 case DP_LINK_BW_1_62:
141 case DP_LINK_BW_2_7:
1db10e28 142 case DP_LINK_BW_5_4:
d4eead50 143 break;
a4fc5ed6 144 default:
d4eead50
ID		 145 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
146 max_link_bw);
a4fc5ed6
KP		 147 max_link_bw = DP_LINK_BW_1_62;
148 break;
149 }
150 return max_link_bw;
151}
152
eeb6324d
PZ		 153static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
154{
155 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
eeb6324d
PZ		 156 u8 source_max, sink_max;
157
ccb1a831 158 source_max = intel_dig_port->max_lanes;
eeb6324d
PZ		 159 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
160
161 return min(source_max, sink_max);
162}
163
cd9dde44
AJ		 164/*
165 * The units on the numbers in the next two are... bizarre. Examples will
166 * make it clearer; this one parallels an example in the eDP spec.
167 *
168 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
169 *
170 * 270000 * 1 * 8 / 10 == 216000
171 *
172 * The actual data capacity of that configuration is 2.16Gbit/s, so the
173 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
174 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
175 * 119000. At 18bpp that's 2142000 kilobits per second.
176 *
177 * Thus the strange-looking division by 10 in intel_dp_link_required, to
178 * get the result in decakilobits instead of kilobits.
179 */
180
a4fc5ed6 181static int
c898261c 182intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 183{
cd9dde44 184 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 185}
186
fe27d53e
DA		 187static int
188intel_dp_max_data_rate(int max_link_clock, int max_lanes)
189{
190 return (max_link_clock * max_lanes * 8) / 10;
191}
192
70ec0645
MK		 193static int
194intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
195{
196 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
197 struct intel_encoder *encoder = &intel_dig_port->base;
198 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
199 int max_dotclk = dev_priv->max_dotclk_freq;
200 int ds_max_dotclk;
201
202 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
203
204 if (type != DP_DS_PORT_TYPE_VGA)
205 return max_dotclk;
206
207 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
208 intel_dp->downstream_ports);
209
210 if (ds_max_dotclk != 0)
211 max_dotclk = min(max_dotclk, ds_max_dotclk);
212
213 return max_dotclk;
214}
215
c19de8eb 216static enum drm_mode_status
a4fc5ed6
KP		 217intel_dp_mode_valid(struct drm_connector *connector,
218 struct drm_display_mode *mode)
219{
df0e9248 220 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 221 struct intel_connector *intel_connector = to_intel_connector(connector);
222 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 223 int target_clock = mode->clock;
224 int max_rate, mode_rate, max_lanes, max_link_clock;
70ec0645
MK		 225 int max_dotclk;
226
227 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
a4fc5ed6 228
dd06f90e
JN		 229 if (is_edp(intel_dp) && fixed_mode) {
230 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 231 return MODE_PANEL;
232
dd06f90e 233 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 234 return MODE_PANEL;
03afc4a2
DV		 235
236 target_clock = fixed_mode->clock;
7de56f43
ZY		 237 }
238
50fec21a 239 max_link_clock = intel_dp_max_link_rate(intel_dp);
eeb6324d 240 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 241
242 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
243 mode_rate = intel_dp_link_required(target_clock, 18);
244
799487f5 245 if (mode_rate > max_rate || target_clock > max_dotclk)
c4867936 246 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 247
248 if (mode->clock < 10000)
249 return MODE_CLOCK_LOW;
250
0af78a2b
DV		 251 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
252 return MODE_H_ILLEGAL;
253
a4fc5ed6
KP		 254 return MODE_OK;
255}
256
a4f1289e 257uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 258{
259 int i;
260 uint32_t v = 0;
261
262 if (src_bytes > 4)
263 src_bytes = 4;
264 for (i = 0; i < src_bytes; i++)
265 v |= ((uint32_t) src[i]) << ((3-i) * 8);
266 return v;
267}
268
c2af70e2 269static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
a4fc5ed6
KP		 270{
271 int i;
272 if (dst_bytes > 4)
273 dst_bytes = 4;
274 for (i = 0; i < dst_bytes; i++)
275 dst[i] = src >> ((3-i) * 8);
276}
277
bf13e81b
JN		 278static void
279intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 280 struct intel_dp *intel_dp);
bf13e81b
JN		 281static void
282intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 283 struct intel_dp *intel_dp);
335f752b
ID		 284static void
285intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
bf13e81b 286
773538e8
VS		 287static void pps_lock(struct intel_dp *intel_dp)
288{
289 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
290 struct intel_encoder *encoder = &intel_dig_port->base;
291 struct drm_device *dev = encoder->base.dev;
fac5e23e 292 struct drm_i915_private *dev_priv = to_i915(dev);
773538e8
VS		 293 enum intel_display_power_domain power_domain;
294
295 /*
296 * See vlv_power_sequencer_reset() why we need
297 * a power domain reference here.
298 */
25f78f58 299 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 300 intel_display_power_get(dev_priv, power_domain);
301
302 mutex_lock(&dev_priv->pps_mutex);
303}
304
305static void pps_unlock(struct intel_dp *intel_dp)
306{
307 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
308 struct intel_encoder *encoder = &intel_dig_port->base;
309 struct drm_device *dev = encoder->base.dev;
fac5e23e 310 struct drm_i915_private *dev_priv = to_i915(dev);
773538e8
VS		 311 enum intel_display_power_domain power_domain;
312
313 mutex_unlock(&dev_priv->pps_mutex);
314
25f78f58 315 power_domain = intel_display_port_aux_power_domain(encoder);
773538e8
VS		 316 intel_display_power_put(dev_priv, power_domain);
317}
318
961a0db0
VS		 319static void
320vlv_power_sequencer_kick(struct intel_dp *intel_dp)
321{
322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
323 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 324 struct drm_i915_private *dev_priv = to_i915(dev);
961a0db0 325 enum pipe pipe = intel_dp->pps_pipe;
0047eedc
VS		 326 bool pll_enabled, release_cl_override = false;
327 enum dpio_phy phy = DPIO_PHY(pipe);
328 enum dpio_channel ch = vlv_pipe_to_channel(pipe);
961a0db0
VS		 329 uint32_t DP;
330
331 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
332 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
333 pipe_name(pipe), port_name(intel_dig_port->port)))
334 return;
335
336 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
337 pipe_name(pipe), port_name(intel_dig_port->port));
338
339 /* Preserve the BIOS-computed detected bit. This is
340 * supposed to be read-only.
341 */
342 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
343 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
344 DP |= DP_PORT_WIDTH(1);
345 DP |= DP_LINK_TRAIN_PAT_1;
346
347 if (IS_CHERRYVIEW(dev))
348 DP |= DP_PIPE_SELECT_CHV(pipe);
349 else if (pipe == PIPE_B)
350 DP |= DP_PIPEB_SELECT;
351
d288f65f
VS		 352 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
353
354 /*
355 * The DPLL for the pipe must be enabled for this to work.
356 * So enable temporarily it if it's not already enabled.
357 */
0047eedc
VS		 358 if (!pll_enabled) {
359 release_cl_override = IS_CHERRYVIEW(dev) &&
360 !chv_phy_powergate_ch(dev_priv, phy, ch, true);
361
3f36b937
TU		 362 if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
363 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
364 DRM_ERROR("Failed to force on pll for pipe %c!\n",
365 pipe_name(pipe));
366 return;
367 }
0047eedc 368 }
d288f65f 369
961a0db0
VS		 370 /*
371 * Similar magic as in intel_dp_enable_port().
372 * We _must_ do this port enable + disable trick
373 * to make this power seqeuencer lock onto the port.
374 * Otherwise even VDD force bit won't work.
375 */
376 I915_WRITE(intel_dp->output_reg, DP);
377 POSTING_READ(intel_dp->output_reg);
378
379 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
380 POSTING_READ(intel_dp->output_reg);
381
382 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
383 POSTING_READ(intel_dp->output_reg);
d288f65f 384
0047eedc 385 if (!pll_enabled) {
d288f65f 386 vlv_force_pll_off(dev, pipe);
0047eedc
VS		 387
388 if (release_cl_override)
389 chv_phy_powergate_ch(dev_priv, phy, ch, false);
390 }
961a0db0
VS		 391}
392
bf13e81b
JN		 393static enum pipe
394vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
395{
396 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b 397 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 398 struct drm_i915_private *dev_priv = to_i915(dev);
a4a5d2f8
VS		 399 struct intel_encoder *encoder;
400 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
a8c3344e 401 enum pipe pipe;
bf13e81b 402
e39b999a 403 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 404
a8c3344e
VS		 405 /* We should never land here with regular DP ports */
406 WARN_ON(!is_edp(intel_dp));
407
a4a5d2f8
VS		 408 if (intel_dp->pps_pipe != INVALID_PIPE)
409 return intel_dp->pps_pipe;
410
411 /*
412 * We don't have power sequencer currently.
413 * Pick one that's not used by other ports.
414 */
19c8054c 415 for_each_intel_encoder(dev, encoder) {
a4a5d2f8
VS		 416 struct intel_dp *tmp;
417
418 if (encoder->type != INTEL_OUTPUT_EDP)
419 continue;
420
421 tmp = enc_to_intel_dp(&encoder->base);
422
423 if (tmp->pps_pipe != INVALID_PIPE)
424 pipes &= ~(1 << tmp->pps_pipe);
425 }
426
427 /*
428 * Didn't find one. This should not happen since there
429 * are two power sequencers and up to two eDP ports.
430 */
431 if (WARN_ON(pipes == 0))
a8c3344e
VS		 432 pipe = PIPE_A;
433 else
434 pipe = ffs(pipes) - 1;
a4a5d2f8 435
a8c3344e
VS		 436 vlv_steal_power_sequencer(dev, pipe);
437 intel_dp->pps_pipe = pipe;
a4a5d2f8
VS		 438
439 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
440 pipe_name(intel_dp->pps_pipe),
441 port_name(intel_dig_port->port));
442
443 /* init power sequencer on this pipe and port */
36b5f425
VS		 444 intel_dp_init_panel_power_sequencer(dev, intel_dp);
445 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8 446
961a0db0
VS		 447 /*
448 * Even vdd force doesn't work until we've made
449 * the power sequencer lock in on the port.
450 */
451 vlv_power_sequencer_kick(intel_dp);
a4a5d2f8
VS		 452
453 return intel_dp->pps_pipe;
454}
455
78597996
ID		 456static int
457bxt_power_sequencer_idx(struct intel_dp *intel_dp)
458{
459 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
460 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 461 struct drm_i915_private *dev_priv = to_i915(dev);
78597996
ID		 462
463 lockdep_assert_held(&dev_priv->pps_mutex);
464
465 /* We should never land here with regular DP ports */
466 WARN_ON(!is_edp(intel_dp));
467
468 /*
469 * TODO: BXT has 2 PPS instances. The correct port->PPS instance
470 * mapping needs to be retrieved from VBT, for now just hard-code to
471 * use instance #0 always.
472 */
473 if (!intel_dp->pps_reset)
474 return 0;
475
476 intel_dp->pps_reset = false;
477
478 /*
479 * Only the HW needs to be reprogrammed, the SW state is fixed and
480 * has been setup during connector init.
481 */
482 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
483
484 return 0;
485}
486
6491ab27
VS		 487typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
488 enum pipe pipe);
489
490static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
491 enum pipe pipe)
492{
44cb734c 493 return I915_READ(PP_STATUS(pipe)) & PP_ON;
6491ab27
VS		 494}
495
496static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
497 enum pipe pipe)
498{
44cb734c 499 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
6491ab27
VS		 500}
501
502static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
503 enum pipe pipe)
504{
505 return true;
506}
bf13e81b 507
a4a5d2f8 508static enum pipe
6491ab27
VS		 509vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
510 enum port port,
511 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 512{
513 enum pipe pipe;
bf13e81b 514
bf13e81b 515 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
44cb734c 516 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
bf13e81b 517 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 518
519 if (port_sel != PANEL_PORT_SELECT_VLV(port))
520 continue;
521
6491ab27
VS		 522 if (!pipe_check(dev_priv, pipe))
523 continue;
524
a4a5d2f8 525 return pipe;
bf13e81b
JN		 526 }
527
a4a5d2f8
VS		 528 return INVALID_PIPE;
529}
530
531static void
532vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
533{
534 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
535 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 536 struct drm_i915_private *dev_priv = to_i915(dev);
a4a5d2f8
VS		 537 enum port port = intel_dig_port->port;
538
539 lockdep_assert_held(&dev_priv->pps_mutex);
540
541 /* try to find a pipe with this port selected */
6491ab27
VS		 542 /* first pick one where the panel is on */
543 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
544 vlv_pipe_has_pp_on);
545 /* didn't find one? pick one where vdd is on */
546 if (intel_dp->pps_pipe == INVALID_PIPE)
547 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
548 vlv_pipe_has_vdd_on);
549 /* didn't find one? pick one with just the correct port */
550 if (intel_dp->pps_pipe == INVALID_PIPE)
551 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
552 vlv_pipe_any);
a4a5d2f8
VS		 553
554 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
555 if (intel_dp->pps_pipe == INVALID_PIPE) {
556 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
557 port_name(port));
558 return;
bf13e81b
JN		 559 }
560
a4a5d2f8
VS		 561 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
562 port_name(port), pipe_name(intel_dp->pps_pipe));
563
36b5f425
VS		 564 intel_dp_init_panel_power_sequencer(dev, intel_dp);
565 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 566}
567
78597996 568void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
773538e8 569{
91c8a326 570 struct drm_device *dev = &dev_priv->drm;
773538e8
VS		 571 struct intel_encoder *encoder;
572
78597996
ID		 573 if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
574 !IS_BROXTON(dev)))
773538e8
VS		 575 return;
576
577 /*
578 * We can't grab pps_mutex here due to deadlock with power_domain
579 * mutex when power_domain functions are called while holding pps_mutex.
580 * That also means that in order to use pps_pipe the code needs to
581 * hold both a power domain reference and pps_mutex, and the power domain
582 * reference get/put must be done while _not_ holding pps_mutex.
583 * pps_{lock,unlock}() do these steps in the correct order, so one
584 * should use them always.
585 */
586
19c8054c 587 for_each_intel_encoder(dev, encoder) {
773538e8
VS		 588 struct intel_dp *intel_dp;
589
590 if (encoder->type != INTEL_OUTPUT_EDP)
591 continue;
592
593 intel_dp = enc_to_intel_dp(&encoder->base);
78597996
ID		 594 if (IS_BROXTON(dev))
595 intel_dp->pps_reset = true;
596 else
597 intel_dp->pps_pipe = INVALID_PIPE;
773538e8 598 }
bf13e81b
JN		 599}
600
8e8232d5
ID		 601struct pps_registers {
602 i915_reg_t pp_ctrl;
603 i915_reg_t pp_stat;
604 i915_reg_t pp_on;
605 i915_reg_t pp_off;
606 i915_reg_t pp_div;
607};
608
609static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
610 struct intel_dp *intel_dp,
611 struct pps_registers *regs)
612{
44cb734c
ID		 613 int pps_idx = 0;
614
8e8232d5
ID		 615 memset(regs, 0, sizeof(*regs));
616
44cb734c
ID		 617 if (IS_BROXTON(dev_priv))
618 pps_idx = bxt_power_sequencer_idx(intel_dp);
619 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
620 pps_idx = vlv_power_sequencer_pipe(intel_dp);
8e8232d5 621
44cb734c
ID		 622 regs->pp_ctrl = PP_CONTROL(pps_idx);
623 regs->pp_stat = PP_STATUS(pps_idx);
624 regs->pp_on = PP_ON_DELAYS(pps_idx);
625 regs->pp_off = PP_OFF_DELAYS(pps_idx);
626 if (!IS_BROXTON(dev_priv))
627 regs->pp_div = PP_DIVISOR(pps_idx);
8e8232d5
ID		 628}
629
f0f59a00
VS		 630static i915_reg_t
631_pp_ctrl_reg(struct intel_dp *intel_dp)
bf13e81b 632{
8e8232d5 633 struct pps_registers regs;
bf13e81b 634
8e8232d5
ID		 635 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
636 &regs);
637
638 return regs.pp_ctrl;
bf13e81b
JN		 639}
640
f0f59a00
VS		 641static i915_reg_t
642_pp_stat_reg(struct intel_dp *intel_dp)
bf13e81b 643{
8e8232d5 644 struct pps_registers regs;
bf13e81b 645
8e8232d5
ID		 646 intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
647 &regs);
648
649 return regs.pp_stat;
bf13e81b
JN		 650}
651
01527b31
CT		 652/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
653 This function only applicable when panel PM state is not to be tracked */
654static int edp_notify_handler(struct notifier_block *this, unsigned long code,
655 void *unused)
656{
657 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
658 edp_notifier);
659 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 660 struct drm_i915_private *dev_priv = to_i915(dev);
01527b31
CT		 661
662 if (!is_edp(intel_dp) || code != SYS_RESTART)
663 return 0;
664
773538e8 665 pps_lock(intel_dp);
e39b999a 666
666a4537 667 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e39b999a 668 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
f0f59a00 669 i915_reg_t pp_ctrl_reg, pp_div_reg;
649636ef 670 u32 pp_div;
e39b999a 671
44cb734c
ID		 672 pp_ctrl_reg = PP_CONTROL(pipe);
673 pp_div_reg = PP_DIVISOR(pipe);
01527b31
CT		 674 pp_div = I915_READ(pp_div_reg);
675 pp_div &= PP_REFERENCE_DIVIDER_MASK;
676
677 /* 0x1F write to PP_DIV_REG sets max cycle delay */
678 I915_WRITE(pp_div_reg, pp_div | 0x1F);
679 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
680 msleep(intel_dp->panel_power_cycle_delay);
681 }
682
773538e8 683 pps_unlock(intel_dp);
e39b999a 684
01527b31
CT		 685 return 0;
686}
687
4be73780 688static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 689{
30add22d 690 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 691 struct drm_i915_private *dev_priv = to_i915(dev);
ebf33b18 692
e39b999a
VS		 693 lockdep_assert_held(&dev_priv->pps_mutex);
694
666a4537 695 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 696 intel_dp->pps_pipe == INVALID_PIPE)
697 return false;
698
bf13e81b 699 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 700}
701
4be73780 702static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 703{
30add22d 704 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 705 struct drm_i915_private *dev_priv = to_i915(dev);
ebf33b18 706
e39b999a
VS		 707 lockdep_assert_held(&dev_priv->pps_mutex);
708
666a4537 709 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
9a42356b
VS		 710 intel_dp->pps_pipe == INVALID_PIPE)
711 return false;
712
773538e8 713 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 714}
715
9b984dae
KP		 716static void
717intel_dp_check_edp(struct intel_dp *intel_dp)
718{
30add22d 719 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 720 struct drm_i915_private *dev_priv = to_i915(dev);
ebf33b18 721
9b984dae
KP		 722 if (!is_edp(intel_dp))
723 return;
453c5420 724
4be73780 725 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 726 WARN(1, "eDP powered off while attempting aux channel communication.\n");
727 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 728 I915_READ(_pp_stat_reg(intel_dp)),
729 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 730 }
731}
732
9ee32fea
DV		 733static uint32_t
734intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
735{
736 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
737 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 738 struct drm_i915_private *dev_priv = to_i915(dev);
f0f59a00 739 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 740 uint32_t status;
741 bool done;
742
ef04f00d 743#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 744 if (has_aux_irq)
b18ac466 745 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 746 msecs_to_jiffies_timeout(10));
9ee32fea 747 else
713a6b66 748 done = wait_for(C, 10) == 0;
9ee32fea
DV		 749 if (!done)
750 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
751 has_aux_irq);
752#undef C
753
754 return status;
755}
756
6ffb1be7 757static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 758{
174edf1f 759 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
e7dc33f3 760 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
9ee32fea 761
a457f54b
VS		 762 if (index)
763 return 0;
764
ec5b01dd
DL		 765 /*
766 * The clock divider is based off the hrawclk, and would like to run at
a457f54b 767 * 2MHz. So, take the hrawclk value and divide by 2000 and use that
a4fc5ed6 768 */
a457f54b 769 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 770}
771
772static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
773{
774 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 775 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd
DL		 776
777 if (index)
778 return 0;
779
a457f54b
VS		 780 /*
781 * The clock divider is based off the cdclk or PCH rawclk, and would
782 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and
783 * divide by 2000 and use that
784 */
e7dc33f3 785 if (intel_dig_port->port == PORT_A)
fce18c4c 786 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
e7dc33f3
VS		 787 else
788 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
ec5b01dd
DL		 789}
790
791static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
792{
793 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
a457f54b 794 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
ec5b01dd 795
a457f54b 796 if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
2c55c336 797 /* Workaround for non-ULT HSW */
bc86625a
CW		 798 switch (index) {
799 case 0: return 63;
800 case 1: return 72;
801 default: return 0;
802 }
2c55c336 803 }
a457f54b
VS		 804
805 return ilk_get_aux_clock_divider(intel_dp, index);
b84a1cf8
RV		 806}
807
b6b5e383
DL		 808static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
809{
810 /*
811 * SKL doesn't need us to program the AUX clock divider (Hardware will
812 * derive the clock from CDCLK automatically). We still implement the
813 * get_aux_clock_divider vfunc to plug-in into the existing code.
814 */
815 return index ? 0 : 1;
816}
817
6ffb1be7
VS		 818static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
819 bool has_aux_irq,
820 int send_bytes,
821 uint32_t aux_clock_divider)
5ed12a19
DL		 822{
823 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
824 struct drm_device *dev = intel_dig_port->base.base.dev;
825 uint32_t precharge, timeout;
826
827 if (IS_GEN6(dev))
828 precharge = 3;
829 else
830 precharge = 5;
831
f3c6a3a7 832 if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
5ed12a19
DL		 833 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
834 else
835 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
836
837 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 838 DP_AUX_CH_CTL_DONE |
5ed12a19 839 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 840 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 841 timeout |
788d4433 842 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 843 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
844 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 845 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 846}
847
b9ca5fad
DL		 848static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
849 bool has_aux_irq,
850 int send_bytes,
851 uint32_t unused)
852{
853 return DP_AUX_CH_CTL_SEND_BUSY |
854 DP_AUX_CH_CTL_DONE |
855 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
856 DP_AUX_CH_CTL_TIME_OUT_ERROR |
857 DP_AUX_CH_CTL_TIME_OUT_1600us |
858 DP_AUX_CH_CTL_RECEIVE_ERROR |
859 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
d4dcbdce 860 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
b9ca5fad
DL		 861 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
862}
863
b84a1cf8
RV		 864static int
865intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 866 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 867 uint8_t *recv, int recv_size)
868{
869 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
870 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 871 struct drm_i915_private *dev_priv = to_i915(dev);
f0f59a00 872 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
bc86625a 873 uint32_t aux_clock_divider;
b84a1cf8
RV		 874 int i, ret, recv_bytes;
875 uint32_t status;
5ed12a19 876 int try, clock = 0;
4e6b788c 877 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 878 bool vdd;
879
773538e8 880 pps_lock(intel_dp);
e39b999a 881
72c3500a
VS		 882 /*
883 * We will be called with VDD already enabled for dpcd/edid/oui reads.
884 * In such cases we want to leave VDD enabled and it's up to upper layers
885 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
886 * ourselves.
887 */
1e0560e0 888 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 889
890 /* dp aux is extremely sensitive to irq latency, hence request the
891 * lowest possible wakeup latency and so prevent the cpu from going into
892 * deep sleep states.
893 */
894 pm_qos_update_request(&dev_priv->pm_qos, 0);
895
896 intel_dp_check_edp(intel_dp);
5eb08b69 897
11bee43e
JB		 898 /* Try to wait for any previous AUX channel activity */
899 for (try = 0; try < 3; try++) {
ef04f00d 900 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 901 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
902 break;
903 msleep(1);
904 }
905
906 if (try == 3) {
02196c77
MK		 907 static u32 last_status = -1;
908 const u32 status = I915_READ(ch_ctl);
909
910 if (status != last_status) {
911 WARN(1, "dp_aux_ch not started status 0x%08x\n",
912 status);
913 last_status = status;
914 }
915
9ee32fea
DV		 916 ret = -EBUSY;
917 goto out;
4f7f7b7e
CW		 918 }
919
46a5ae9f
PZ		 920 /* Only 5 data registers! */
921 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
922 ret = -E2BIG;
923 goto out;
924 }
925
ec5b01dd 926 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 927 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
928 has_aux_irq,
929 send_bytes,
930 aux_clock_divider);
5ed12a19 931
bc86625a
CW		 932 /* Must try at least 3 times according to DP spec */
933 for (try = 0; try < 5; try++) {
934 /* Load the send data into the aux channel data registers */
935 for (i = 0; i < send_bytes; i += 4)
330e20ec 936 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
a4f1289e
RV		 937 intel_dp_pack_aux(send + i,
938 send_bytes - i));
bc86625a
CW		 939
940 /* Send the command and wait for it to complete */
5ed12a19 941 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 942
943 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
944
945 /* Clear done status and any errors */
946 I915_WRITE(ch_ctl,
947 status |
948 DP_AUX_CH_CTL_DONE |
949 DP_AUX_CH_CTL_TIME_OUT_ERROR |
950 DP_AUX_CH_CTL_RECEIVE_ERROR);
951
74ebf294 952 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
bc86625a 953 continue;
74ebf294
TP		 954
955 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
956 * 400us delay required for errors and timeouts
957 * Timeout errors from the HW already meet this
958 * requirement so skip to next iteration
959 */
960 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
961 usleep_range(400, 500);
bc86625a 962 continue;
74ebf294 963 }
bc86625a 964 if (status & DP_AUX_CH_CTL_DONE)
e058c945 965 goto done;
bc86625a 966 }
a4fc5ed6
KP		 967 }
968
a4fc5ed6 969 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 970 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 971 ret = -EBUSY;
972 goto out;
a4fc5ed6
KP		 973 }
974
e058c945 975done:
a4fc5ed6
KP		 976 /* Check for timeout or receive error.
977 * Timeouts occur when the sink is not connected
978 */
a5b3da54 979 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 980 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 981 ret = -EIO;
982 goto out;
a5b3da54 983 }
1ae8c0a5
KP		 984
985 /* Timeouts occur when the device isn't connected, so they're
986 * "normal" -- don't fill the kernel log with these */
a5b3da54 987 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 988 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 989 ret = -ETIMEDOUT;
990 goto out;
a4fc5ed6
KP		 991 }
992
993 /* Unload any bytes sent back from the other side */
994 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
995 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
14e01889
RV		 996
997 /*
998 * By BSpec: "Message sizes of 0 or >20 are not allowed."
999 * We have no idea of what happened so we return -EBUSY so
1000 * drm layer takes care for the necessary retries.
1001 */
1002 if (recv_bytes == 0 || recv_bytes > 20) {
1003 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1004 recv_bytes);
1005 /*
1006 * FIXME: This patch was created on top of a series that
1007 * organize the retries at drm level. There EBUSY should
1008 * also take care for 1ms wait before retrying.
1009 * That aux retries re-org is still needed and after that is
1010 * merged we remove this sleep from here.
1011 */
1012 usleep_range(1000, 1500);
1013 ret = -EBUSY;
1014 goto out;
1015 }
1016
a4fc5ed6
KP		 1017 if (recv_bytes > recv_size)
1018 recv_bytes = recv_size;
0206e353 1019
4f7f7b7e 1020 for (i = 0; i < recv_bytes; i += 4)
330e20ec 1021 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
a4f1289e 1022 recv + i, recv_bytes - i);
a4fc5ed6 1023
9ee32fea
DV		 1024 ret = recv_bytes;
1025out:
1026 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1027
884f19e9
JN		 1028 if (vdd)
1029 edp_panel_vdd_off(intel_dp, false);
1030
773538e8 1031 pps_unlock(intel_dp);
e39b999a 1032
9ee32fea 1033 return ret;
a4fc5ed6
KP		 1034}
1035
a6c8aff0
JN		 1036#define BARE_ADDRESS_SIZE 3
1037#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 1038static ssize_t
1039intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 1040{
9d1a1031
JN		 1041 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1042 uint8_t txbuf[20], rxbuf[20];
1043 size_t txsize, rxsize;
a4fc5ed6 1044 int ret;
a4fc5ed6 1045
d2d9cbbd
VS		 1046 txbuf[0] = (msg->request << 4) |
1047 ((msg->address >> 16) & 0xf);
1048 txbuf[1] = (msg->address >> 8) & 0xff;
9d1a1031
JN		 1049 txbuf[2] = msg->address & 0xff;
1050 txbuf[3] = msg->size - 1;
46a5ae9f 1051
9d1a1031
JN		 1052 switch (msg->request & ~DP_AUX_I2C_MOT) {
1053 case DP_AUX_NATIVE_WRITE:
1054 case DP_AUX_I2C_WRITE:
c1e74122 1055 case DP_AUX_I2C_WRITE_STATUS_UPDATE:
a6c8aff0 1056 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
a1ddefd8 1057 rxsize = 2; /* 0 or 1 data bytes */
f51a44b9 1058
9d1a1031
JN		 1059 if (WARN_ON(txsize > 20))
1060 return -E2BIG;
a4fc5ed6 1061
dd788090
VS		 1062 WARN_ON(!msg->buffer != !msg->size);
1063
d81a67cc
ID		 1064 if (msg->buffer)
1065 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 1066
9d1a1031
JN		 1067 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1068 if (ret > 0) {
1069 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 1070
a1ddefd8
JN		 1071 if (ret > 1) {
1072 /* Number of bytes written in a short write. */
1073 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1074 } else {
1075 /* Return payload size. */
1076 ret = msg->size;
1077 }
9d1a1031
JN		 1078 }
1079 break;
46a5ae9f 1080
9d1a1031
JN		 1081 case DP_AUX_NATIVE_READ:
1082 case DP_AUX_I2C_READ:
a6c8aff0 1083 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 1084 rxsize = msg->size + 1;
a4fc5ed6 1085
9d1a1031
JN		 1086 if (WARN_ON(rxsize > 20))
1087 return -E2BIG;
a4fc5ed6 1088
9d1a1031
JN		 1089 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1090 if (ret > 0) {
1091 msg->reply = rxbuf[0] >> 4;
1092 /*
1093 * Assume happy day, and copy the data. The caller is
1094 * expected to check msg->reply before touching it.
1095 *
1096 * Return payload size.
1097 */
1098 ret--;
1099 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 1100 }
9d1a1031
JN		 1101 break;
1102
1103 default:
1104 ret = -EINVAL;
1105 break;
a4fc5ed6 1106 }
f51a44b9 1107
9d1a1031 1108 return ret;
a4fc5ed6
KP		 1109}
1110
f0f59a00
VS		 1111static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1112 enum port port)
da00bdcf
VS		 1113{
1114 switch (port) {
1115 case PORT_B:
1116 case PORT_C:
1117 case PORT_D:
1118 return DP_AUX_CH_CTL(port);
1119 default:
1120 MISSING_CASE(port);
1121 return DP_AUX_CH_CTL(PORT_B);
1122 }
1123}
1124
f0f59a00
VS		 1125static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1126 enum port port, int index)
330e20ec
VS		 1127{
1128 switch (port) {
1129 case PORT_B:
1130 case PORT_C:
1131 case PORT_D:
1132 return DP_AUX_CH_DATA(port, index);
1133 default:
1134 MISSING_CASE(port);
1135 return DP_AUX_CH_DATA(PORT_B, index);
1136 }
1137}
1138
f0f59a00
VS		 1139static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1140 enum port port)
da00bdcf
VS		 1141{
1142 switch (port) {
1143 case PORT_A:
1144 return DP_AUX_CH_CTL(port);
1145 case PORT_B:
1146 case PORT_C:
1147 case PORT_D:
1148 return PCH_DP_AUX_CH_CTL(port);
1149 default:
1150 MISSING_CASE(port);
1151 return DP_AUX_CH_CTL(PORT_A);
1152 }
1153}
1154
f0f59a00
VS		 1155static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1156 enum port port, int index)
330e20ec
VS		 1157{
1158 switch (port) {
1159 case PORT_A:
1160 return DP_AUX_CH_DATA(port, index);
1161 case PORT_B:
1162 case PORT_C:
1163 case PORT_D:
1164 return PCH_DP_AUX_CH_DATA(port, index);
1165 default:
1166 MISSING_CASE(port);
1167 return DP_AUX_CH_DATA(PORT_A, index);
1168 }
1169}
1170
da00bdcf
VS		 1171/*
1172 * On SKL we don't have Aux for port E so we rely
1173 * on VBT to set a proper alternate aux channel.
1174 */
1175static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1176{
1177 const struct ddi_vbt_port_info *info =
1178 &dev_priv->vbt.ddi_port_info[PORT_E];
1179
1180 switch (info->alternate_aux_channel) {
1181 case DP_AUX_A:
1182 return PORT_A;
1183 case DP_AUX_B:
1184 return PORT_B;
1185 case DP_AUX_C:
1186 return PORT_C;
1187 case DP_AUX_D:
1188 return PORT_D;
1189 default:
1190 MISSING_CASE(info->alternate_aux_channel);
1191 return PORT_A;
1192 }
1193}
1194
f0f59a00
VS		 1195static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1196 enum port port)
da00bdcf
VS		 1197{
1198 if (port == PORT_E)
1199 port = skl_porte_aux_port(dev_priv);
1200
1201 switch (port) {
1202 case PORT_A:
1203 case PORT_B:
1204 case PORT_C:
1205 case PORT_D:
1206 return DP_AUX_CH_CTL(port);
1207 default:
1208 MISSING_CASE(port);
1209 return DP_AUX_CH_CTL(PORT_A);
1210 }
1211}
1212
f0f59a00
VS		 1213static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1214 enum port port, int index)
330e20ec
VS		 1215{
1216 if (port == PORT_E)
1217 port = skl_porte_aux_port(dev_priv);
1218
1219 switch (port) {
1220 case PORT_A:
1221 case PORT_B:
1222 case PORT_C:
1223 case PORT_D:
1224 return DP_AUX_CH_DATA(port, index);
1225 default:
1226 MISSING_CASE(port);
1227 return DP_AUX_CH_DATA(PORT_A, index);
1228 }
1229}
1230
f0f59a00
VS		 1231static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1232 enum port port)
330e20ec
VS		 1233{
1234 if (INTEL_INFO(dev_priv)->gen >= 9)
1235 return skl_aux_ctl_reg(dev_priv, port);
1236 else if (HAS_PCH_SPLIT(dev_priv))
1237 return ilk_aux_ctl_reg(dev_priv, port);
1238 else
1239 return g4x_aux_ctl_reg(dev_priv, port);
1240}
1241
f0f59a00
VS		 1242static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1243 enum port port, int index)
330e20ec
VS		 1244{
1245 if (INTEL_INFO(dev_priv)->gen >= 9)
1246 return skl_aux_data_reg(dev_priv, port, index);
1247 else if (HAS_PCH_SPLIT(dev_priv))
1248 return ilk_aux_data_reg(dev_priv, port, index);
1249 else
1250 return g4x_aux_data_reg(dev_priv, port, index);
1251}
1252
1253static void intel_aux_reg_init(struct intel_dp *intel_dp)
1254{
1255 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1256 enum port port = dp_to_dig_port(intel_dp)->port;
1257 int i;
1258
1259 intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1260 for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1261 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1262}
1263
9d1a1031 1264static void
a121f4e5
VS		 1265intel_dp_aux_fini(struct intel_dp *intel_dp)
1266{
a121f4e5
VS		 1267 kfree(intel_dp->aux.name);
1268}
1269
7a418e34 1270static void
b6339585 1271intel_dp_aux_init(struct intel_dp *intel_dp)
9d1a1031 1272{
33ad6626
JN		 1273 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1274 enum port port = intel_dig_port->port;
ab2c0672 1275
330e20ec 1276 intel_aux_reg_init(intel_dp);
7a418e34 1277 drm_dp_aux_init(&intel_dp->aux);
8316f337 1278
7a418e34 1279 /* Failure to allocate our preferred name is not critical */
a121f4e5 1280 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
9d1a1031 1281 intel_dp->aux.transfer = intel_dp_aux_transfer;
a4fc5ed6
KP		 1282}
1283
fc0f8e25 1284static int
12f6a2e2 1285intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
fc0f8e25 1286{
94ca719e
VS		 1287 if (intel_dp->num_sink_rates) {
1288 *sink_rates = intel_dp->sink_rates;
1289 return intel_dp->num_sink_rates;
fc0f8e25 1290 }
12f6a2e2
VS		 1291
1292 *sink_rates = default_rates;
1293
1294 return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
fc0f8e25
SJ		 1295}
1296
e588fa18 1297bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
ed63baaf 1298{
e588fa18 1299 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
577c5430 1300 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
e588fa18 1301
577c5430
NM		 1302 if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
1303 IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
ed63baaf
TS		 1304 return true;
1305 else
1306 return false;
1307}
1308
a8f3ef61 1309static int
e588fa18 1310intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
a8f3ef61 1311{
e588fa18 1312 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
577c5430 1313 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
af7080f5
TS		 1314 int size;
1315
577c5430 1316 if (IS_BROXTON(dev_priv)) {
64987fc5 1317 *source_rates = bxt_rates;
af7080f5 1318 size = ARRAY_SIZE(bxt_rates);
577c5430 1319 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
637a9c63 1320 *source_rates = skl_rates;
af7080f5
TS		 1321 size = ARRAY_SIZE(skl_rates);
1322 } else {
1323 *source_rates = default_rates;
1324 size = ARRAY_SIZE(default_rates);
a8f3ef61 1325 }
636280ba 1326
ed63baaf 1327 /* This depends on the fact that 5.4 is last value in the array */
e588fa18 1328 if (!intel_dp_source_supports_hbr2(intel_dp))
af7080f5 1329 size--;
636280ba 1330
af7080f5 1331 return size;
a8f3ef61
SJ		 1332}
1333
c6bb3538
DV		 1334static void
1335intel_dp_set_clock(struct intel_encoder *encoder,
840b32b7 1336 struct intel_crtc_state *pipe_config)
c6bb3538
DV		 1337{
1338 struct drm_device *dev = encoder->base.dev;
6e266956 1339 struct drm_i915_private *dev_priv = to_i915(dev);
9dd4ffdf
CML		 1340 const struct dp_link_dpll *divisor = NULL;
1341 int i, count = 0;
c6bb3538
DV		 1342
1343 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1344 divisor = gen4_dpll;
1345 count = ARRAY_SIZE(gen4_dpll);
6e266956 1346 } else if (HAS_PCH_SPLIT(dev_priv)) {
9dd4ffdf
CML		 1347 divisor = pch_dpll;
1348 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1349 } else if (IS_CHERRYVIEW(dev)) {
1350 divisor = chv_dpll;
1351 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1352 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1353 divisor = vlv_dpll;
1354 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1355 }
9dd4ffdf
CML		 1356
1357 if (divisor && count) {
1358 for (i = 0; i < count; i++) {
840b32b7 1359 if (pipe_config->port_clock == divisor[i].clock) {
9dd4ffdf
CML		 1360 pipe_config->dpll = divisor[i].dpll;
1361 pipe_config->clock_set = true;
1362 break;
1363 }
1364 }
c6bb3538
DV		 1365 }
1366}
1367
2ecae76a
VS		 1368static int intersect_rates(const int *source_rates, int source_len,
1369 const int *sink_rates, int sink_len,
94ca719e 1370 int *common_rates)
a8f3ef61
SJ		 1371{
1372 int i = 0, j = 0, k = 0;
1373
a8f3ef61
SJ		 1374 while (i < source_len && j < sink_len) {
1375 if (source_rates[i] == sink_rates[j]) {
e6bda3e4
VS		 1376 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1377 return k;
94ca719e 1378 common_rates[k] = source_rates[i];
a8f3ef61
SJ		 1379 ++k;
1380 ++i;
1381 ++j;
1382 } else if (source_rates[i] < sink_rates[j]) {
1383 ++i;
1384 } else {
1385 ++j;
1386 }
1387 }
1388 return k;
1389}
1390
94ca719e
VS		 1391static int intel_dp_common_rates(struct intel_dp *intel_dp,
1392 int *common_rates)
2ecae76a 1393{
2ecae76a
VS		 1394 const int *source_rates, *sink_rates;
1395 int source_len, sink_len;
1396
1397 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
e588fa18 1398 source_len = intel_dp_source_rates(intel_dp, &source_rates);
2ecae76a
VS		 1399
1400 return intersect_rates(source_rates, source_len,
1401 sink_rates, sink_len,
94ca719e 1402 common_rates);
2ecae76a
VS		 1403}
1404
0336400e
VS		 1405static void snprintf_int_array(char *str, size_t len,
1406 const int *array, int nelem)
1407{
1408 int i;
1409
1410 str[0] = '\0';
1411
1412 for (i = 0; i < nelem; i++) {
b2f505be 1413 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
0336400e
VS		 1414 if (r >= len)
1415 return;
1416 str += r;
1417 len -= r;
1418 }
1419}
1420
1421static void intel_dp_print_rates(struct intel_dp *intel_dp)
1422{
0336400e 1423 const int *source_rates, *sink_rates;
94ca719e
VS		 1424 int source_len, sink_len, common_len;
1425 int common_rates[DP_MAX_SUPPORTED_RATES];
0336400e
VS		 1426 char str[128]; /* FIXME: too big for stack? */
1427
1428 if ((drm_debug & DRM_UT_KMS) == 0)
1429 return;
1430
e588fa18 1431 source_len = intel_dp_source_rates(intel_dp, &source_rates);
0336400e
VS		 1432 snprintf_int_array(str, sizeof(str), source_rates, source_len);
1433 DRM_DEBUG_KMS("source rates: %s\n", str);
1434
1435 sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1436 snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1437 DRM_DEBUG_KMS("sink rates: %s\n", str);
1438
94ca719e
VS		 1439 common_len = intel_dp_common_rates(intel_dp, common_rates);
1440 snprintf_int_array(str, sizeof(str), common_rates, common_len);
1441 DRM_DEBUG_KMS("common rates: %s\n", str);
0336400e
VS		 1442}
1443
0e390a33
MK		 1444static void intel_dp_print_hw_revision(struct intel_dp *intel_dp)
1445{
1446 uint8_t rev;
1447 int len;
1448
1449 if ((drm_debug & DRM_UT_KMS) == 0)
1450 return;
1451
1452 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1453 DP_DWN_STRM_PORT_PRESENT))
1454 return;
1455
1456 len = drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_HW_REV, &rev, 1);
1457 if (len < 0)
1458 return;
1459
1460 DRM_DEBUG_KMS("sink hw revision: %d.%d\n", (rev & 0xf0) >> 4, rev & 0xf);
1461}
1462
1a2724fa
MK		 1463static void intel_dp_print_sw_revision(struct intel_dp *intel_dp)
1464{
1465 uint8_t rev[2];
1466 int len;
1467
1468 if ((drm_debug & DRM_UT_KMS) == 0)
1469 return;
1470
1471 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1472 DP_DWN_STRM_PORT_PRESENT))
1473 return;
1474
1475 len = drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_SW_REV, &rev, 2);
1476 if (len < 0)
1477 return;
1478
1479 DRM_DEBUG_KMS("sink sw revision: %d.%d\n", rev[0], rev[1]);
1480}
1481
f4896f15 1482static int rate_to_index(int find, const int *rates)
a8f3ef61
SJ		 1483{
1484 int i = 0;
1485
1486 for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1487 if (find == rates[i])
1488 break;
1489
1490 return i;
1491}
1492
50fec21a
VS		 1493int
1494intel_dp_max_link_rate(struct intel_dp *intel_dp)
1495{
1496 int rates[DP_MAX_SUPPORTED_RATES] = {};
1497 int len;
1498
94ca719e 1499 len = intel_dp_common_rates(intel_dp, rates);
50fec21a
VS		 1500 if (WARN_ON(len <= 0))
1501 return 162000;
1502
1354f734 1503 return rates[len - 1];
50fec21a
VS		 1504}
1505
ed4e9c1d
VS		 1506int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1507{
94ca719e 1508 return rate_to_index(rate, intel_dp->sink_rates);
ed4e9c1d
VS		 1509}
1510
94223d04
ACO		 1511void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1512 uint8_t *link_bw, uint8_t *rate_select)
04a60f9f
VS		 1513{
1514 if (intel_dp->num_sink_rates) {
1515 *link_bw = 0;
1516 *rate_select =
1517 intel_dp_rate_select(intel_dp, port_clock);
1518 } else {
1519 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1520 *rate_select = 0;
1521 }
1522}
1523
f580bea9
JN		 1524static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1525 struct intel_crtc_state *pipe_config)
f9bb705e
MK		 1526{
1527 int bpp, bpc;
1528
1529 bpp = pipe_config->pipe_bpp;
1530 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1531
1532 if (bpc > 0)
1533 bpp = min(bpp, 3*bpc);
1534
1535 return bpp;
1536}
1537
00c09d70 1538bool
5bfe2ac0 1539intel_dp_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 1540 struct intel_crtc_state *pipe_config,
1541 struct drm_connector_state *conn_state)
a4fc5ed6 1542{
5bfe2ac0 1543 struct drm_device *dev = encoder->base.dev;
fac5e23e 1544 struct drm_i915_private *dev_priv = to_i915(dev);
2d112de7 1545 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5bfe2ac0 1546 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1547 enum port port = dp_to_dig_port(intel_dp)->port;
84556d58 1548 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
dd06f90e 1549 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1550 int lane_count, clock;
56071a20 1551 int min_lane_count = 1;
eeb6324d 1552 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1553 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1554 int min_clock = 0;
a8f3ef61 1555 int max_clock;
083f9560 1556 int bpp, mode_rate;
ff9a6750 1557 int link_avail, link_clock;
94ca719e
VS		 1558 int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1559 int common_len;
04a60f9f 1560 uint8_t link_bw, rate_select;
a8f3ef61 1561
94ca719e 1562 common_len = intel_dp_common_rates(intel_dp, common_rates);
a8f3ef61
SJ		 1563
1564 /* No common link rates between source and sink */
94ca719e 1565 WARN_ON(common_len <= 0);
a8f3ef61 1566
94ca719e 1567 max_clock = common_len - 1;
a4fc5ed6 1568
4f8036a2 1569 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
5bfe2ac0
DV		 1570 pipe_config->has_pch_encoder = true;
1571
f769cd24 1572 pipe_config->has_drrs = false;
9fcb1704 1573 pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
a4fc5ed6 1574
dd06f90e
JN		 1575 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1576 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1577 adjusted_mode);
a1b2278e
CK		 1578
1579 if (INTEL_INFO(dev)->gen >= 9) {
1580 int ret;
e435d6e5 1581 ret = skl_update_scaler_crtc(pipe_config);
a1b2278e
CK		 1582 if (ret)
1583 return ret;
1584 }
1585
49cff963 1586 if (HAS_GMCH_DISPLAY(dev_priv))
2dd24552
JB		 1587 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1588 intel_connector->panel.fitting_mode);
1589 else
b074cec8
JB		 1590 intel_pch_panel_fitting(intel_crtc, pipe_config,
1591 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1592 }
1593
cb1793ce 1594 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1595 return false;
1596
083f9560 1597 DRM_DEBUG_KMS("DP link computation with max lane count %i "
a8f3ef61 1598 "max bw %d pixel clock %iKHz\n",
94ca719e 1599 max_lane_count, common_rates[max_clock],
241bfc38 1600 adjusted_mode->crtc_clock);
083f9560 1601
36008365
DV		 1602 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1603 * bpc in between. */
f9bb705e 1604 bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
56071a20 1605 if (is_edp(intel_dp)) {
22ce5628
TS		 1606
1607 /* Get bpp from vbt only for panels that dont have bpp in edid */
1608 if (intel_connector->base.display_info.bpc == 0 &&
6aa23e65 1609 (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
56071a20 1610 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
6aa23e65
JN		 1611 dev_priv->vbt.edp.bpp);
1612 bpp = dev_priv->vbt.edp.bpp;
56071a20
JN		 1613 }
1614
344c5bbc
JN		 1615 /*
1616 * Use the maximum clock and number of lanes the eDP panel
1617 * advertizes being capable of. The panels are generally
1618 * designed to support only a single clock and lane
1619 * configuration, and typically these values correspond to the
1620 * native resolution of the panel.
1621 */
1622 min_lane_count = max_lane_count;
1623 min_clock = max_clock;
7984211e 1624 }
657445fe 1625
36008365 1626 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1627 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1628 bpp);
36008365 1629
c6930992 1630 for (clock = min_clock; clock <= max_clock; clock++) {
a8f3ef61
SJ		 1631 for (lane_count = min_lane_count;
1632 lane_count <= max_lane_count;
1633 lane_count <<= 1) {
1634
94ca719e 1635 link_clock = common_rates[clock];
36008365
DV		 1636 link_avail = intel_dp_max_data_rate(link_clock,
1637 lane_count);
1638
1639 if (mode_rate <= link_avail) {
1640 goto found;
1641 }
1642 }
1643 }
1644 }
c4867936 1645
36008365 1646 return false;
3685a8f3 1647
36008365 1648found:
55bc60db
VS		 1649 if (intel_dp->color_range_auto) {
1650 /*
1651 * See:
1652 * CEA-861-E - 5.1 Default Encoding Parameters
1653 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1654 */
0f2a2a75
VS		 1655 pipe_config->limited_color_range =
1656 bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1657 } else {
1658 pipe_config->limited_color_range =
1659 intel_dp->limited_color_range;
55bc60db
VS		 1660 }
1661
90a6b7b0 1662 pipe_config->lane_count = lane_count;
a8f3ef61 1663
657445fe 1664 pipe_config->pipe_bpp = bpp;
94ca719e 1665 pipe_config->port_clock = common_rates[clock];
a4fc5ed6 1666
04a60f9f
VS		 1667 intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1668 &link_bw, &rate_select);
1669
1670 DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1671 link_bw, rate_select, pipe_config->lane_count,
ff9a6750 1672 pipe_config->port_clock, bpp);
36008365
DV		 1673 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1674 mode_rate, link_avail);
a4fc5ed6 1675
03afc4a2 1676 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1677 adjusted_mode->crtc_clock,
1678 pipe_config->port_clock,
03afc4a2 1679 &pipe_config->dp_m_n);
9d1a455b 1680
439d7ac0 1681 if (intel_connector->panel.downclock_mode != NULL &&
96178eeb 1682 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1683 pipe_config->has_drrs = true;
439d7ac0
PB		 1684 intel_link_compute_m_n(bpp, lane_count,
1685 intel_connector->panel.downclock_mode->clock,
1686 pipe_config->port_clock,
1687 &pipe_config->dp_m2_n2);
1688 }
1689
14d41b3b
VS		 1690 /*
1691 * DPLL0 VCO may need to be adjusted to get the correct
1692 * clock for eDP. This will affect cdclk as well.
1693 */
1694 if (is_edp(intel_dp) &&
1695 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) {
1696 int vco;
1697
1698 switch (pipe_config->port_clock / 2) {
1699 case 108000:
1700 case 216000:
63911d72 1701 vco = 8640000;
14d41b3b
VS		 1702 break;
1703 default:
63911d72 1704 vco = 8100000;
14d41b3b
VS		 1705 break;
1706 }
1707
1708 to_intel_atomic_state(pipe_config->base.state)->cdclk_pll_vco = vco;
1709 }
1710
4f8036a2 1711 if (!HAS_DDI(dev_priv))
840b32b7 1712 intel_dp_set_clock(encoder, pipe_config);
c6bb3538 1713
03afc4a2 1714 return true;
a4fc5ed6
KP		 1715}
1716
901c2daf 1717void intel_dp_set_link_params(struct intel_dp *intel_dp,
dfa10480
ACO		 1718 int link_rate, uint8_t lane_count,
1719 bool link_mst)
901c2daf 1720{
dfa10480
ACO		 1721 intel_dp->link_rate = link_rate;
1722 intel_dp->lane_count = lane_count;
1723 intel_dp->link_mst = link_mst;
901c2daf
VS		 1724}
1725
85cb48a1
ML		 1726static void intel_dp_prepare(struct intel_encoder *encoder,
1727 struct intel_crtc_state *pipe_config)
a4fc5ed6 1728{
b934223d 1729 struct drm_device *dev = encoder->base.dev;
fac5e23e 1730 struct drm_i915_private *dev_priv = to_i915(dev);
b934223d 1731 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1732 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d 1733 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
85cb48a1 1734 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
a4fc5ed6 1735
dfa10480
ACO		 1736 intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1737 pipe_config->lane_count,
1738 intel_crtc_has_type(pipe_config,
1739 INTEL_OUTPUT_DP_MST));
901c2daf 1740
417e822d 1741 /*
1a2eb460 1742 * There are four kinds of DP registers:
417e822d
KP		 1743 *
1744 * IBX PCH
1a2eb460
KP		 1745 * SNB CPU
1746 * IVB CPU
417e822d
KP		 1747 * CPT PCH
1748 *
1749 * IBX PCH and CPU are the same for almost everything,
1750 * except that the CPU DP PLL is configured in this
1751 * register
1752 *
1753 * CPT PCH is quite different, having many bits moved
1754 * to the TRANS_DP_CTL register instead. That
1755 * configuration happens (oddly) in ironlake_pch_enable
1756 */
9c9e7927 1757
417e822d
KP		 1758 /* Preserve the BIOS-computed detected bit. This is
1759 * supposed to be read-only.
1760 */
1761 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1762
417e822d 1763 /* Handle DP bits in common between all three register formats */
417e822d 1764 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
85cb48a1 1765 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
a4fc5ed6 1766
417e822d 1767 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1768
39e5fa88 1769 if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1770 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1771 intel_dp->DP |= DP_SYNC_HS_HIGH;
1772 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1773 intel_dp->DP |= DP_SYNC_VS_HIGH;
1774 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1775
6aba5b6c 1776 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1777 intel_dp->DP |= DP_ENHANCED_FRAMING;
1778
7c62a164 1779 intel_dp->DP |= crtc->pipe << 29;
6e266956 1780 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
e3ef4479
VS		 1781 u32 trans_dp;
1782
39e5fa88 1783 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
e3ef4479
VS		 1784
1785 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1786 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1787 trans_dp |= TRANS_DP_ENH_FRAMING;
1788 else
1789 trans_dp &= ~TRANS_DP_ENH_FRAMING;
1790 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
39e5fa88 1791 } else {
6e266956 1792 if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev) &&
85cb48a1 1793 !IS_CHERRYVIEW(dev) && pipe_config->limited_color_range)
0f2a2a75 1794 intel_dp->DP |= DP_COLOR_RANGE_16_235;
417e822d
KP		 1795
1796 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1797 intel_dp->DP |= DP_SYNC_HS_HIGH;
1798 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1799 intel_dp->DP |= DP_SYNC_VS_HIGH;
1800 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1801
6aba5b6c 1802 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1803 intel_dp->DP |= DP_ENHANCED_FRAMING;
1804
39e5fa88 1805 if (IS_CHERRYVIEW(dev))
44f37d1f 1806 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
39e5fa88
VS		 1807 else if (crtc->pipe == PIPE_B)
1808 intel_dp->DP |= DP_PIPEB_SELECT;
32f9d658 1809 }
a4fc5ed6
KP		 1810}
1811
ffd6749d
PZ		 1812#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1813#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1814
1a5ef5b7
PZ		 1815#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1816#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1817
ffd6749d
PZ		 1818#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1819#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1820
de9c1b6b
ID		 1821static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1822 struct intel_dp *intel_dp);
1823
4be73780 1824static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1825 u32 mask,
1826 u32 value)
bd943159 1827{
30add22d 1828 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 1829 struct drm_i915_private *dev_priv = to_i915(dev);
f0f59a00 1830 i915_reg_t pp_stat_reg, pp_ctrl_reg;
453c5420 1831
e39b999a
VS		 1832 lockdep_assert_held(&dev_priv->pps_mutex);
1833
de9c1b6b
ID		 1834 intel_pps_verify_state(dev_priv, intel_dp);
1835
bf13e81b
JN		 1836 pp_stat_reg = _pp_stat_reg(intel_dp);
1837 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1838
99ea7127 1839 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1840 mask, value,
1841 I915_READ(pp_stat_reg),
1842 I915_READ(pp_ctrl_reg));
32ce697c 1843
9036ff06
CW		 1844 if (intel_wait_for_register(dev_priv,
1845 pp_stat_reg, mask, value,
1846 5000))
99ea7127 1847 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1848 I915_READ(pp_stat_reg),
1849 I915_READ(pp_ctrl_reg));
54c136d4
CW		 1850
1851 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1852}
32ce697c 1853
4be73780 1854static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1855{
1856 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1857 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1858}
1859
4be73780 1860static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1861{
1862 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1863 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1864}
1865
4be73780 1866static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127 1867{
d28d4731
AK		 1868 ktime_t panel_power_on_time;
1869 s64 panel_power_off_duration;
1870
99ea7127 1871 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c 1872
d28d4731
AK		 1873 /* take the difference of currrent time and panel power off time
1874 * and then make panel wait for t11_t12 if needed. */
1875 panel_power_on_time = ktime_get_boottime();
1876 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1877
dce56b3c
PZ		 1878 /* When we disable the VDD override bit last we have to do the manual
1879 * wait. */
d28d4731
AK		 1880 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1881 wait_remaining_ms_from_jiffies(jiffies,
1882 intel_dp->panel_power_cycle_delay - panel_power_off_duration);
dce56b3c 1883
4be73780 1884 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1885}
1886
4be73780 1887static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1888{
1889 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1890 intel_dp->backlight_on_delay);
1891}
1892
4be73780 1893static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1894{
1895 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1896 intel_dp->backlight_off_delay);
1897}
99ea7127 1898
832dd3c1
KP		 1899/* Read the current pp_control value, unlocking the register if it
1900 * is locked
1901 */
1902
453c5420 1903static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1904{
453c5420 1905 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 1906 struct drm_i915_private *dev_priv = to_i915(dev);
453c5420 1907 u32 control;
832dd3c1 1908
e39b999a
VS		 1909 lockdep_assert_held(&dev_priv->pps_mutex);
1910
bf13e81b 1911 control = I915_READ(_pp_ctrl_reg(intel_dp));
8090ba8c
ID		 1912 if (WARN_ON(!HAS_DDI(dev_priv) &&
1913 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
b0a08bec
VK		 1914 control &= ~PANEL_UNLOCK_MASK;
1915 control |= PANEL_UNLOCK_REGS;
1916 }
832dd3c1 1917 return control;
bd943159
KP		 1918}
1919
951468f3
VS		 1920/*
1921 * Must be paired with edp_panel_vdd_off().
1922 * Must hold pps_mutex around the whole on/off sequence.
1923 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1924 */
1e0560e0 1925static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1926{
30add22d 1927 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1928 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1929 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fac5e23e 1930 struct drm_i915_private *dev_priv = to_i915(dev);
4e6e1a54 1931 enum intel_display_power_domain power_domain;
5d613501 1932 u32 pp;
f0f59a00 1933 i915_reg_t pp_stat_reg, pp_ctrl_reg;
adddaaf4 1934 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1935
e39b999a
VS		 1936 lockdep_assert_held(&dev_priv->pps_mutex);
1937
97af61f5 1938 if (!is_edp(intel_dp))
adddaaf4 1939 return false;
bd943159 1940
2c623c11 1941 cancel_delayed_work(&intel_dp->panel_vdd_work);
bd943159 1942 intel_dp->want_panel_vdd = true;
99ea7127 1943
4be73780 1944 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1945 return need_to_disable;
b0665d57 1946
25f78f58 1947 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 1948 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1949
3936fcf4
VS		 1950 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1951 port_name(intel_dig_port->port));
bd943159 1952
4be73780
DV		 1953 if (!edp_have_panel_power(intel_dp))
1954 wait_panel_power_cycle(intel_dp);
99ea7127 1955
453c5420 1956 pp = ironlake_get_pp_control(intel_dp);
5d613501 1957 pp |= EDP_FORCE_VDD;
ebf33b18 1958
bf13e81b
JN		 1959 pp_stat_reg = _pp_stat_reg(intel_dp);
1960 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1961
1962 I915_WRITE(pp_ctrl_reg, pp);
1963 POSTING_READ(pp_ctrl_reg);
1964 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1965 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1966 /*
1967 * If the panel wasn't on, delay before accessing aux channel
1968 */
4be73780 1969 if (!edp_have_panel_power(intel_dp)) {
3936fcf4
VS		 1970 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1971 port_name(intel_dig_port->port));
f01eca2e 1972 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1973 }
adddaaf4
JN		 1974
1975 return need_to_disable;
1976}
1977
951468f3
VS		 1978/*
1979 * Must be paired with intel_edp_panel_vdd_off() or
1980 * intel_edp_panel_off().
1981 * Nested calls to these functions are not allowed since
1982 * we drop the lock. Caller must use some higher level
1983 * locking to prevent nested calls from other threads.
1984 */
b80d6c78 1985void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1986{
c695b6b6 1987 bool vdd;
adddaaf4 1988
c695b6b6
VS		 1989 if (!is_edp(intel_dp))
1990 return;
1991
773538e8 1992 pps_lock(intel_dp);
c695b6b6 1993 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1994 pps_unlock(intel_dp);
c695b6b6 1995
e2c719b7 1996 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
3936fcf4 1997 port_name(dp_to_dig_port(intel_dp)->port));
5d613501
JB		 1998}
1999
4be73780 2000static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 2001{
30add22d 2002 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2003 struct drm_i915_private *dev_priv = to_i915(dev);
be2c9196
VS		 2004 struct intel_digital_port *intel_dig_port =
2005 dp_to_dig_port(intel_dp);
2006 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2007 enum intel_display_power_domain power_domain;
5d613501 2008 u32 pp;
f0f59a00 2009 i915_reg_t pp_stat_reg, pp_ctrl_reg;
5d613501 2010
e39b999a 2011 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 2012
15e899a0 2013 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 2014
15e899a0 2015 if (!edp_have_panel_vdd(intel_dp))
be2c9196 2016 return;
b0665d57 2017
3936fcf4
VS		 2018 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2019 port_name(intel_dig_port->port));
bd943159 2020
be2c9196
VS		 2021 pp = ironlake_get_pp_control(intel_dp);
2022 pp &= ~EDP_FORCE_VDD;
453c5420 2023
be2c9196
VS		 2024 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2025 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 2026
be2c9196
VS		 2027 I915_WRITE(pp_ctrl_reg, pp);
2028 POSTING_READ(pp_ctrl_reg);
90791a5c 2029
be2c9196
VS		 2030 /* Make sure sequencer is idle before allowing subsequent activity */
2031 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2032 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 2033
5a162e22 2034 if ((pp & PANEL_POWER_ON) == 0)
d28d4731 2035 intel_dp->panel_power_off_time = ktime_get_boottime();
e9cb81a2 2036
25f78f58 2037 power_domain = intel_display_port_aux_power_domain(intel_encoder);
be2c9196 2038 intel_display_power_put(dev_priv, power_domain);
bd943159 2039}
5d613501 2040
4be73780 2041static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 2042{
2043 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2044 struct intel_dp, panel_vdd_work);
bd943159 2045
773538e8 2046 pps_lock(intel_dp);
15e899a0
VS		 2047 if (!intel_dp->want_panel_vdd)
2048 edp_panel_vdd_off_sync(intel_dp);
773538e8 2049 pps_unlock(intel_dp);
bd943159
KP		 2050}
2051
aba86890
ID		 2052static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2053{
2054 unsigned long delay;
2055
2056 /*
2057 * Queue the timer to fire a long time from now (relative to the power
2058 * down delay) to keep the panel power up across a sequence of
2059 * operations.
2060 */
2061 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2062 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2063}
2064
951468f3
VS		 2065/*
2066 * Must be paired with edp_panel_vdd_on().
2067 * Must hold pps_mutex around the whole on/off sequence.
2068 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2069 */
4be73780 2070static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 2071{
fac5e23e 2072 struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
e39b999a
VS		 2073
2074 lockdep_assert_held(&dev_priv->pps_mutex);
2075
97af61f5
KP		 2076 if (!is_edp(intel_dp))
2077 return;
5d613501 2078
e2c719b7 2079 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
3936fcf4 2080 port_name(dp_to_dig_port(intel_dp)->port));
f2e8b18a 2081
bd943159
KP		 2082 intel_dp->want_panel_vdd = false;
2083
aba86890 2084 if (sync)
4be73780 2085 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 2086 else
2087 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 2088}
2089
9f0fb5be 2090static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 2091{
30add22d 2092 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2093 struct drm_i915_private *dev_priv = to_i915(dev);
99ea7127 2094 u32 pp;
f0f59a00 2095 i915_reg_t pp_ctrl_reg;
9934c132 2096
9f0fb5be
VS		 2097 lockdep_assert_held(&dev_priv->pps_mutex);
2098
97af61f5 2099 if (!is_edp(intel_dp))
bd943159 2100 return;
99ea7127 2101
3936fcf4
VS		 2102 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2103 port_name(dp_to_dig_port(intel_dp)->port));
e39b999a 2104
e7a89ace
VS		 2105 if (WARN(edp_have_panel_power(intel_dp),
2106 "eDP port %c panel power already on\n",
2107 port_name(dp_to_dig_port(intel_dp)->port)))
9f0fb5be 2108 return;
9934c132 2109
4be73780 2110 wait_panel_power_cycle(intel_dp);
37c6c9b0 2111
bf13e81b 2112 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2113 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 2114 if (IS_GEN5(dev)) {
2115 /* ILK workaround: disable reset around power sequence */
2116 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 2117 I915_WRITE(pp_ctrl_reg, pp);
2118 POSTING_READ(pp_ctrl_reg);
05ce1a49 2119 }
37c6c9b0 2120
5a162e22 2121 pp |= PANEL_POWER_ON;
99ea7127
KP		 2122 if (!IS_GEN5(dev))
2123 pp |= PANEL_POWER_RESET;
2124
453c5420
JB		 2125 I915_WRITE(pp_ctrl_reg, pp);
2126 POSTING_READ(pp_ctrl_reg);
9934c132 2127
4be73780 2128 wait_panel_on(intel_dp);
dce56b3c 2129 intel_dp->last_power_on = jiffies;
9934c132 2130
05ce1a49
KP		 2131 if (IS_GEN5(dev)) {
2132 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 2133 I915_WRITE(pp_ctrl_reg, pp);
2134 POSTING_READ(pp_ctrl_reg);
05ce1a49 2135 }
9f0fb5be 2136}
e39b999a 2137
9f0fb5be
VS		 2138void intel_edp_panel_on(struct intel_dp *intel_dp)
2139{
2140 if (!is_edp(intel_dp))
2141 return;
2142
2143 pps_lock(intel_dp);
2144 edp_panel_on(intel_dp);
773538e8 2145 pps_unlock(intel_dp);
9934c132
JB		 2146}
2147
9f0fb5be
VS		 2148
2149static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 2150{
4e6e1a54
ID		 2151 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2152 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 2153 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2154 struct drm_i915_private *dev_priv = to_i915(dev);
4e6e1a54 2155 enum intel_display_power_domain power_domain;
99ea7127 2156 u32 pp;
f0f59a00 2157 i915_reg_t pp_ctrl_reg;
9934c132 2158
9f0fb5be
VS		 2159 lockdep_assert_held(&dev_priv->pps_mutex);
2160
97af61f5
KP		 2161 if (!is_edp(intel_dp))
2162 return;
37c6c9b0 2163
3936fcf4
VS		 2164 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2165 port_name(dp_to_dig_port(intel_dp)->port));
37c6c9b0 2166
3936fcf4
VS		 2167 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2168 port_name(dp_to_dig_port(intel_dp)->port));
24f3e092 2169
453c5420 2170 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 2171 /* We need to switch off panel power _and_ force vdd, for otherwise some
2172 * panels get very unhappy and cease to work. */
5a162e22 2173 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
b3064154 2174 EDP_BLC_ENABLE);
453c5420 2175
bf13e81b 2176 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 2177
849e39f5
PZ		 2178 intel_dp->want_panel_vdd = false;
2179
453c5420
JB		 2180 I915_WRITE(pp_ctrl_reg, pp);
2181 POSTING_READ(pp_ctrl_reg);
9934c132 2182
d28d4731 2183 intel_dp->panel_power_off_time = ktime_get_boottime();
4be73780 2184 wait_panel_off(intel_dp);
849e39f5
PZ		 2185
2186 /* We got a reference when we enabled the VDD. */
25f78f58 2187 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4e6e1a54 2188 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 2189}
e39b999a 2190
9f0fb5be
VS		 2191void intel_edp_panel_off(struct intel_dp *intel_dp)
2192{
2193 if (!is_edp(intel_dp))
2194 return;
e39b999a 2195
9f0fb5be
VS		 2196 pps_lock(intel_dp);
2197 edp_panel_off(intel_dp);
773538e8 2198 pps_unlock(intel_dp);
9934c132
JB		 2199}
2200
1250d107
JN		 2201/* Enable backlight in the panel power control. */
2202static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 2203{
da63a9f2
PZ		 2204 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2205 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 2206 struct drm_i915_private *dev_priv = to_i915(dev);
32f9d658 2207 u32 pp;
f0f59a00 2208 i915_reg_t pp_ctrl_reg;
32f9d658 2209
01cb9ea6
JB		 2210 /*
2211 * If we enable the backlight right away following a panel power
2212 * on, we may see slight flicker as the panel syncs with the eDP
2213 * link. So delay a bit to make sure the image is solid before
2214 * allowing it to appear.
2215 */
4be73780 2216 wait_backlight_on(intel_dp);
e39b999a 2217
773538e8 2218 pps_lock(intel_dp);
e39b999a 2219
453c5420 2220 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2221 pp |= EDP_BLC_ENABLE;
453c5420 2222
bf13e81b 2223 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2224
2225 I915_WRITE(pp_ctrl_reg, pp);
2226 POSTING_READ(pp_ctrl_reg);
e39b999a 2227
773538e8 2228 pps_unlock(intel_dp);
32f9d658
ZW		 2229}
2230
1250d107
JN		 2231/* Enable backlight PWM and backlight PP control. */
2232void intel_edp_backlight_on(struct intel_dp *intel_dp)
2233{
2234 if (!is_edp(intel_dp))
2235 return;
2236
2237 DRM_DEBUG_KMS("\n");
2238
2239 intel_panel_enable_backlight(intel_dp->attached_connector);
2240 _intel_edp_backlight_on(intel_dp);
2241}
2242
2243/* Disable backlight in the panel power control. */
2244static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 2245{
30add22d 2246 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2247 struct drm_i915_private *dev_priv = to_i915(dev);
32f9d658 2248 u32 pp;
f0f59a00 2249 i915_reg_t pp_ctrl_reg;
32f9d658 2250
f01eca2e
KP		 2251 if (!is_edp(intel_dp))
2252 return;
2253
773538e8 2254 pps_lock(intel_dp);
e39b999a 2255
453c5420 2256 pp = ironlake_get_pp_control(intel_dp);
32f9d658 2257 pp &= ~EDP_BLC_ENABLE;
453c5420 2258
bf13e81b 2259 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 2260
2261 I915_WRITE(pp_ctrl_reg, pp);
2262 POSTING_READ(pp_ctrl_reg);
f7d2323c 2263
773538e8 2264 pps_unlock(intel_dp);
e39b999a
VS		 2265
2266 intel_dp->last_backlight_off = jiffies;
f7d2323c 2267 edp_wait_backlight_off(intel_dp);
1250d107 2268}
f7d2323c 2269
1250d107
JN		 2270/* Disable backlight PP control and backlight PWM. */
2271void intel_edp_backlight_off(struct intel_dp *intel_dp)
2272{
2273 if (!is_edp(intel_dp))
2274 return;
2275
2276 DRM_DEBUG_KMS("\n");
f7d2323c 2277
1250d107 2278 _intel_edp_backlight_off(intel_dp);
f7d2323c 2279 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 2280}
a4fc5ed6 2281
73580fb7
JN		 2282/*
2283 * Hook for controlling the panel power control backlight through the bl_power
2284 * sysfs attribute. Take care to handle multiple calls.
2285 */
2286static void intel_edp_backlight_power(struct intel_connector *connector,
2287 bool enable)
2288{
2289 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 2290 bool is_enabled;
2291
773538e8 2292 pps_lock(intel_dp);
e39b999a 2293 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 2294 pps_unlock(intel_dp);
73580fb7
JN		 2295
2296 if (is_enabled == enable)
2297 return;
2298
23ba9373
JN		 2299 DRM_DEBUG_KMS("panel power control backlight %s\n",
2300 enable ? "enable" : "disable");
73580fb7
JN		 2301
2302 if (enable)
2303 _intel_edp_backlight_on(intel_dp);
2304 else
2305 _intel_edp_backlight_off(intel_dp);
2306}
2307
64e1077a
VS		 2308static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2309{
2310 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2311 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2312 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2313
2314 I915_STATE_WARN(cur_state != state,
2315 "DP port %c state assertion failure (expected %s, current %s)\n",
2316 port_name(dig_port->port),
87ad3212 2317 onoff(state), onoff(cur_state));
64e1077a
VS		 2318}
2319#define assert_dp_port_disabled(d) assert_dp_port((d), false)
2320
2321static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2322{
2323 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2324
2325 I915_STATE_WARN(cur_state != state,
2326 "eDP PLL state assertion failure (expected %s, current %s)\n",
87ad3212 2327 onoff(state), onoff(cur_state));
64e1077a
VS		 2328}
2329#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2330#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2331
85cb48a1
ML		 2332static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2333 struct intel_crtc_state *pipe_config)
d240f20f 2334{
85cb48a1 2335 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
64e1077a 2336 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2337
64e1077a
VS		 2338 assert_pipe_disabled(dev_priv, crtc->pipe);
2339 assert_dp_port_disabled(intel_dp);
2340 assert_edp_pll_disabled(dev_priv);
2bd2ad64 2341
abfce949 2342 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
85cb48a1 2343 pipe_config->port_clock);
abfce949
VS		 2344
2345 intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2346
85cb48a1 2347 if (pipe_config->port_clock == 162000)
abfce949
VS		 2348 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2349 else
2350 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2351
2352 I915_WRITE(DP_A, intel_dp->DP);
2353 POSTING_READ(DP_A);
2354 udelay(500);
2355
6b23f3e8
VS		 2356 /*
2357 * [DevILK] Work around required when enabling DP PLL
2358 * while a pipe is enabled going to FDI:
2359 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2360 * 2. Program DP PLL enable
2361 */
2362 if (IS_GEN5(dev_priv))
91c8a326 2363 intel_wait_for_vblank_if_active(&dev_priv->drm, !crtc->pipe);
6b23f3e8 2364
0767935e 2365 intel_dp->DP |= DP_PLL_ENABLE;
6fec7662 2366
0767935e 2367 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 2368 POSTING_READ(DP_A);
2369 udelay(200);
d240f20f
JB		 2370}
2371
2bd2ad64 2372static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 2373{
da63a9f2 2374 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
64e1077a
VS		 2375 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2376 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d240f20f 2377
64e1077a
VS		 2378 assert_pipe_disabled(dev_priv, crtc->pipe);
2379 assert_dp_port_disabled(intel_dp);
2380 assert_edp_pll_enabled(dev_priv);
2bd2ad64 2381
abfce949
VS		 2382 DRM_DEBUG_KMS("disabling eDP PLL\n");
2383
6fec7662 2384 intel_dp->DP &= ~DP_PLL_ENABLE;
0767935e 2385
6fec7662 2386 I915_WRITE(DP_A, intel_dp->DP);
1af5fa1b 2387 POSTING_READ(DP_A);
d240f20f
JB		 2388 udelay(200);
2389}
2390
c7ad3810 2391/* If the sink supports it, try to set the power state appropriately */
c19b0669 2392void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 2393{
2394 int ret, i;
2395
2396 /* Should have a valid DPCD by this point */
2397 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2398 return;
2399
2400 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 2401 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2402 DP_SET_POWER_D3);
c7ad3810
JB		 2403 } else {
2404 /*
2405 * When turning on, we need to retry for 1ms to give the sink
2406 * time to wake up.
2407 */
2408 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2409 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2410 DP_SET_POWER_D0);
c7ad3810
JB		 2411 if (ret == 1)
2412 break;
2413 msleep(1);
2414 }
2415 }
f9cac721
JN		 2416
2417 if (ret != 1)
2418 DRM_DEBUG_KMS("failed to %s sink power state\n",
2419 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 2420}
2421
19d8fe15
DV		 2422static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2423 enum pipe *pipe)
d240f20f 2424{
19d8fe15 2425 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2426 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15 2427 struct drm_device *dev = encoder->base.dev;
fac5e23e 2428 struct drm_i915_private *dev_priv = to_i915(dev);
6d129bea
ID		 2429 enum intel_display_power_domain power_domain;
2430 u32 tmp;
6fa9a5ec 2431 bool ret;
6d129bea
ID		 2432
2433 power_domain = intel_display_port_power_domain(encoder);
6fa9a5ec 2434 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 2435 return false;
2436
6fa9a5ec
ID		 2437 ret = false;
2438
6d129bea 2439 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 2440
2441 if (!(tmp & DP_PORT_EN))
6fa9a5ec 2442 goto out;
19d8fe15 2443
39e5fa88 2444 if (IS_GEN7(dev) && port == PORT_A) {
19d8fe15 2445 *pipe = PORT_TO_PIPE_CPT(tmp);
6e266956 2446 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
adc289d7 2447 enum pipe p;
19d8fe15 2448
adc289d7
VS		 2449 for_each_pipe(dev_priv, p) {
2450 u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2451 if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2452 *pipe = p;
6fa9a5ec
ID		 2453 ret = true;
2454
2455 goto out;
19d8fe15
DV		 2456 }
2457 }
19d8fe15 2458
4a0833ec 2459 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
f0f59a00 2460 i915_mmio_reg_offset(intel_dp->output_reg));
39e5fa88
VS		 2461 } else if (IS_CHERRYVIEW(dev)) {
2462 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2463 } else {
2464 *pipe = PORT_TO_PIPE(tmp);
4a0833ec 2465 }
d240f20f 2466
6fa9a5ec
ID		 2467 ret = true;
2468
2469out:
2470 intel_display_power_put(dev_priv, power_domain);
2471
2472 return ret;
19d8fe15 2473}
d240f20f 2474
045ac3b5 2475static void intel_dp_get_config(struct intel_encoder *encoder,
5cec258b 2476 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2477{
2478 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 2479 u32 tmp, flags = 0;
63000ef6 2480 struct drm_device *dev = encoder->base.dev;
fac5e23e 2481 struct drm_i915_private *dev_priv = to_i915(dev);
63000ef6
XZ		 2482 enum port port = dp_to_dig_port(intel_dp)->port;
2483 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
045ac3b5 2484
9ed109a7 2485 tmp = I915_READ(intel_dp->output_reg);
9fcb1704
JN		 2486
2487 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
9ed109a7 2488
6e266956 2489 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
b81e34c2
VS		 2490 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2491
2492 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2493 flags |= DRM_MODE_FLAG_PHSYNC;
2494 else
2495 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2496
b81e34c2 2497 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
63000ef6
XZ		 2498 flags |= DRM_MODE_FLAG_PVSYNC;
2499 else
2500 flags |= DRM_MODE_FLAG_NVSYNC;
2501 } else {
39e5fa88 2502 if (tmp & DP_SYNC_HS_HIGH)
63000ef6
XZ		 2503 flags |= DRM_MODE_FLAG_PHSYNC;
2504 else
2505 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 2506
39e5fa88 2507 if (tmp & DP_SYNC_VS_HIGH)
63000ef6
XZ		 2508 flags |= DRM_MODE_FLAG_PVSYNC;
2509 else
2510 flags |= DRM_MODE_FLAG_NVSYNC;
2511 }
045ac3b5 2512
2d112de7 2513 pipe_config->base.adjusted_mode.flags |= flags;
f1f644dc 2514
6e266956
TU		 2515 if (!HAS_PCH_SPLIT(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
2516 !IS_CHERRYVIEW(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
8c875fca
VS		 2517 pipe_config->limited_color_range = true;
2518
90a6b7b0
VS		 2519 pipe_config->lane_count =
2520 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2521
eb14cb74
VS		 2522 intel_dp_get_m_n(crtc, pipe_config);
2523
18442d08 2524 if (port == PORT_A) {
b377e0df 2525 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
f1f644dc
JB		 2526 pipe_config->port_clock = 162000;
2527 else
2528 pipe_config->port_clock = 270000;
2529 }
18442d08 2530
e3b247da
VS		 2531 pipe_config->base.adjusted_mode.crtc_clock =
2532 intel_dotclock_calculate(pipe_config->port_clock,
2533 &pipe_config->dp_m_n);
7f16e5c1 2534
6aa23e65
JN		 2535 if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2536 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
c6cd2ee2
JN		 2537 /*
2538 * This is a big fat ugly hack.
2539 *
2540 * Some machines in UEFI boot mode provide us a VBT that has 18
2541 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2542 * unknown we fail to light up. Yet the same BIOS boots up with
2543 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2544 * max, not what it tells us to use.
2545 *
2546 * Note: This will still be broken if the eDP panel is not lit
2547 * up by the BIOS, and thus we can't get the mode at module
2548 * load.
2549 */
2550 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2551 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2552 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
c6cd2ee2 2553 }
045ac3b5
JB		 2554}
2555
fd6bbda9
ML		 2556static void intel_disable_dp(struct intel_encoder *encoder,
2557 struct intel_crtc_state *old_crtc_state,
2558 struct drm_connector_state *old_conn_state)
d240f20f 2559{
e8cb4558 2560 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
85cb48a1 2561 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
495a5bb8 2562
85cb48a1 2563 if (old_crtc_state->has_audio)
495a5bb8 2564 intel_audio_codec_disable(encoder);
6cb49835 2565
85cb48a1 2566 if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
b32c6f48
RV		 2567 intel_psr_disable(intel_dp);
2568
6cb49835
DV		 2569 /* Make sure the panel is off before trying to change the mode. But also
2570 * ensure that we have vdd while we switch off the panel. */
24f3e092 2571 intel_edp_panel_vdd_on(intel_dp);
4be73780 2572 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2573 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2574 intel_edp_panel_off(intel_dp);
3739850b 2575
08aff3fe 2576 /* disable the port before the pipe on g4x */
85cb48a1 2577 if (INTEL_GEN(dev_priv) < 5)
3739850b 2578 intel_dp_link_down(intel_dp);
d240f20f
JB		 2579}
2580
fd6bbda9
ML		 2581static void ilk_post_disable_dp(struct intel_encoder *encoder,
2582 struct intel_crtc_state *old_crtc_state,
2583 struct drm_connector_state *old_conn_state)
d240f20f 2584{
2bd2ad64 2585 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2586 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2587
49277c31 2588 intel_dp_link_down(intel_dp);
abfce949
VS		 2589
2590 /* Only ilk+ has port A */
08aff3fe
VS		 2591 if (port == PORT_A)
2592 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2593}
2594
fd6bbda9
ML		 2595static void vlv_post_disable_dp(struct intel_encoder *encoder,
2596 struct intel_crtc_state *old_crtc_state,
2597 struct drm_connector_state *old_conn_state)
49277c31
VS		 2598{
2599 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2600
2601 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2602}
2603
fd6bbda9
ML		 2604static void chv_post_disable_dp(struct intel_encoder *encoder,
2605 struct intel_crtc_state *old_crtc_state,
2606 struct drm_connector_state *old_conn_state)
a8f327fb
VS		 2607{
2608 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2609 struct drm_device *dev = encoder->base.dev;
fac5e23e 2610 struct drm_i915_private *dev_priv = to_i915(dev);
97fd4d5c 2611
a8f327fb
VS		 2612 intel_dp_link_down(intel_dp);
2613
2614 mutex_lock(&dev_priv->sb_lock);
2615
2616 /* Assert data lane reset */
2617 chv_data_lane_soft_reset(encoder, true);
580d3811 2618
a580516d 2619 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 2620}
2621
7b13b58a
VS		 2622static void
2623_intel_dp_set_link_train(struct intel_dp *intel_dp,
2624 uint32_t *DP,
2625 uint8_t dp_train_pat)
2626{
2627 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2628 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 2629 struct drm_i915_private *dev_priv = to_i915(dev);
7b13b58a
VS		 2630 enum port port = intel_dig_port->port;
2631
8b0878a0
PD		 2632 if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2633 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2634 dp_train_pat & DP_TRAINING_PATTERN_MASK);
2635
4f8036a2 2636 if (HAS_DDI(dev_priv)) {
7b13b58a
VS		 2637 uint32_t temp = I915_READ(DP_TP_CTL(port));
2638
2639 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2640 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2641 else
2642 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2643
2644 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2645 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2646 case DP_TRAINING_PATTERN_DISABLE:
2647 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2648
2649 break;
2650 case DP_TRAINING_PATTERN_1:
2651 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2652 break;
2653 case DP_TRAINING_PATTERN_2:
2654 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2655 break;
2656 case DP_TRAINING_PATTERN_3:
2657 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2658 break;
2659 }
2660 I915_WRITE(DP_TP_CTL(port), temp);
2661
39e5fa88 2662 } else if ((IS_GEN7(dev) && port == PORT_A) ||
6e266956 2663 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
7b13b58a
VS		 2664 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2665
2666 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2667 case DP_TRAINING_PATTERN_DISABLE:
2668 *DP |= DP_LINK_TRAIN_OFF_CPT;
2669 break;
2670 case DP_TRAINING_PATTERN_1:
2671 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2672 break;
2673 case DP_TRAINING_PATTERN_2:
2674 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2675 break;
2676 case DP_TRAINING_PATTERN_3:
8b0878a0 2677 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
7b13b58a
VS		 2678 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2679 break;
2680 }
2681
2682 } else {
2683 if (IS_CHERRYVIEW(dev))
2684 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2685 else
2686 *DP &= ~DP_LINK_TRAIN_MASK;
2687
2688 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2689 case DP_TRAINING_PATTERN_DISABLE:
2690 *DP |= DP_LINK_TRAIN_OFF;
2691 break;
2692 case DP_TRAINING_PATTERN_1:
2693 *DP |= DP_LINK_TRAIN_PAT_1;
2694 break;
2695 case DP_TRAINING_PATTERN_2:
2696 *DP |= DP_LINK_TRAIN_PAT_2;
2697 break;
2698 case DP_TRAINING_PATTERN_3:
2699 if (IS_CHERRYVIEW(dev)) {
2700 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2701 } else {
8b0878a0 2702 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
7b13b58a
VS		 2703 *DP |= DP_LINK_TRAIN_PAT_2;
2704 }
2705 break;
2706 }
2707 }
2708}
2709
85cb48a1
ML		 2710static void intel_dp_enable_port(struct intel_dp *intel_dp,
2711 struct intel_crtc_state *old_crtc_state)
7b13b58a
VS		 2712{
2713 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2714 struct drm_i915_private *dev_priv = to_i915(dev);
7b13b58a 2715
7b13b58a 2716 /* enable with pattern 1 (as per spec) */
7b13b58a 2717
8b0878a0 2718 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
7b713f50
VS		 2719
2720 /*
2721 * Magic for VLV/CHV. We _must_ first set up the register
2722 * without actually enabling the port, and then do another
2723 * write to enable the port. Otherwise link training will
2724 * fail when the power sequencer is freshly used for this port.
2725 */
2726 intel_dp->DP |= DP_PORT_EN;
85cb48a1 2727 if (old_crtc_state->has_audio)
6fec7662 2728 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
7b713f50
VS		 2729
2730 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2731 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2732}
2733
85cb48a1
ML		 2734static void intel_enable_dp(struct intel_encoder *encoder,
2735 struct intel_crtc_state *pipe_config)
d240f20f 2736{
e8cb4558
DV		 2737 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2738 struct drm_device *dev = encoder->base.dev;
fac5e23e 2739 struct drm_i915_private *dev_priv = to_i915(dev);
c1dec79a 2740 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
e8cb4558 2741 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
d6fbdd15 2742 enum pipe pipe = crtc->pipe;
5d613501 2743
0c33d8d7
DV		 2744 if (WARN_ON(dp_reg & DP_PORT_EN))
2745 return;
5d613501 2746
093e3f13
VS		 2747 pps_lock(intel_dp);
2748
666a4537 2749 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
093e3f13
VS		 2750 vlv_init_panel_power_sequencer(intel_dp);
2751
85cb48a1 2752 intel_dp_enable_port(intel_dp, pipe_config);
093e3f13
VS		 2753
2754 edp_panel_vdd_on(intel_dp);
2755 edp_panel_on(intel_dp);
2756 edp_panel_vdd_off(intel_dp, true);
2757
2758 pps_unlock(intel_dp);
2759
666a4537 2760 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e0fce78f
VS		 2761 unsigned int lane_mask = 0x0;
2762
2763 if (IS_CHERRYVIEW(dev))
85cb48a1 2764 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
e0fce78f 2765
9b6de0a1
VS		 2766 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2767 lane_mask);
e0fce78f 2768 }
61234fa5 2769
f01eca2e 2770 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2771 intel_dp_start_link_train(intel_dp);
3ab9c637 2772 intel_dp_stop_link_train(intel_dp);
c1dec79a 2773
85cb48a1 2774 if (pipe_config->has_audio) {
c1dec79a 2775 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
d6fbdd15 2776 pipe_name(pipe));
c1dec79a
JN		 2777 intel_audio_codec_enable(encoder);
2778 }
ab1f90f9 2779}
89b667f8 2780
fd6bbda9
ML		 2781static void g4x_enable_dp(struct intel_encoder *encoder,
2782 struct intel_crtc_state *pipe_config,
2783 struct drm_connector_state *conn_state)
ecff4f3b 2784{
828f5c6e
JN		 2785 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2786
85cb48a1 2787 intel_enable_dp(encoder, pipe_config);
4be73780 2788 intel_edp_backlight_on(intel_dp);
ab1f90f9 2789}
89b667f8 2790
fd6bbda9
ML		 2791static void vlv_enable_dp(struct intel_encoder *encoder,
2792 struct intel_crtc_state *pipe_config,
2793 struct drm_connector_state *conn_state)
ab1f90f9 2794{
828f5c6e
JN		 2795 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2796
4be73780 2797 intel_edp_backlight_on(intel_dp);
b32c6f48 2798 intel_psr_enable(intel_dp);
d240f20f
JB		 2799}
2800
fd6bbda9
ML		 2801static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2802 struct intel_crtc_state *pipe_config,
2803 struct drm_connector_state *conn_state)
ab1f90f9
JN		 2804{
2805 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
d6fbdd15 2806 enum port port = dp_to_dig_port(intel_dp)->port;
ab1f90f9 2807
85cb48a1 2808 intel_dp_prepare(encoder, pipe_config);
8ac33ed3 2809
d41f1efb 2810 /* Only ilk+ has port A */
abfce949 2811 if (port == PORT_A)
85cb48a1 2812 ironlake_edp_pll_on(intel_dp, pipe_config);
ab1f90f9
JN		 2813}
2814
83b84597
VS		 2815static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2816{
2817 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
fac5e23e 2818 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
83b84597 2819 enum pipe pipe = intel_dp->pps_pipe;
44cb734c 2820 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
83b84597
VS		 2821
2822 edp_panel_vdd_off_sync(intel_dp);
2823
2824 /*
2825 * VLV seems to get confused when multiple power seqeuencers
2826 * have the same port selected (even if only one has power/vdd
2827 * enabled). The failure manifests as vlv_wait_port_ready() failing
2828 * CHV on the other hand doesn't seem to mind having the same port
2829 * selected in multiple power seqeuencers, but let's clear the
2830 * port select always when logically disconnecting a power sequencer
2831 * from a port.
2832 */
2833 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2834 pipe_name(pipe), port_name(intel_dig_port->port));
2835 I915_WRITE(pp_on_reg, 0);
2836 POSTING_READ(pp_on_reg);
2837
2838 intel_dp->pps_pipe = INVALID_PIPE;
2839}
2840
a4a5d2f8
VS		 2841static void vlv_steal_power_sequencer(struct drm_device *dev,
2842 enum pipe pipe)
2843{
fac5e23e 2844 struct drm_i915_private *dev_priv = to_i915(dev);
a4a5d2f8
VS		 2845 struct intel_encoder *encoder;
2846
2847 lockdep_assert_held(&dev_priv->pps_mutex);
2848
ac3c12e4
VS		 2849 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2850 return;
2851
19c8054c 2852 for_each_intel_encoder(dev, encoder) {
a4a5d2f8 2853 struct intel_dp *intel_dp;
773538e8 2854 enum port port;
a4a5d2f8
VS		 2855
2856 if (encoder->type != INTEL_OUTPUT_EDP)
2857 continue;
2858
2859 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2860 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2861
2862 if (intel_dp->pps_pipe != pipe)
2863 continue;
2864
2865 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2866 pipe_name(pipe), port_name(port));
a4a5d2f8 2867
e02f9a06 2868 WARN(encoder->base.crtc,
034e43c6
VS		 2869 "stealing pipe %c power sequencer from active eDP port %c\n",
2870 pipe_name(pipe), port_name(port));
a4a5d2f8 2871
a4a5d2f8 2872 /* make sure vdd is off before we steal it */
83b84597 2873 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2874 }
2875}
2876
2877static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2878{
2879 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2880 struct intel_encoder *encoder = &intel_dig_port->base;
2881 struct drm_device *dev = encoder->base.dev;
fac5e23e 2882 struct drm_i915_private *dev_priv = to_i915(dev);
a4a5d2f8 2883 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2884
2885 lockdep_assert_held(&dev_priv->pps_mutex);
2886
093e3f13
VS		 2887 if (!is_edp(intel_dp))
2888 return;
2889
a4a5d2f8
VS		 2890 if (intel_dp->pps_pipe == crtc->pipe)
2891 return;
2892
2893 /*
2894 * If another power sequencer was being used on this
2895 * port previously make sure to turn off vdd there while
2896 * we still have control of it.
2897 */
2898 if (intel_dp->pps_pipe != INVALID_PIPE)
83b84597 2899 vlv_detach_power_sequencer(intel_dp);
a4a5d2f8
VS		 2900
2901 /*
2902 * We may be stealing the power
2903 * sequencer from another port.
2904 */
2905 vlv_steal_power_sequencer(dev, crtc->pipe);
2906
2907 /* now it's all ours */
2908 intel_dp->pps_pipe = crtc->pipe;
2909
2910 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2911 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2912
2913 /* init power sequencer on this pipe and port */
36b5f425
VS		 2914 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2915 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2916}
2917
fd6bbda9
ML		 2918static void vlv_pre_enable_dp(struct intel_encoder *encoder,
2919 struct intel_crtc_state *pipe_config,
2920 struct drm_connector_state *conn_state)
a4fc5ed6 2921{
5f68c275 2922 vlv_phy_pre_encoder_enable(encoder);
ab1f90f9 2923
85cb48a1 2924 intel_enable_dp(encoder, pipe_config);
89b667f8
JB		 2925}
2926
fd6bbda9
ML		 2927static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
2928 struct intel_crtc_state *pipe_config,
2929 struct drm_connector_state *conn_state)
89b667f8 2930{
85cb48a1 2931 intel_dp_prepare(encoder, pipe_config);
8ac33ed3 2932
6da2e616 2933 vlv_phy_pre_pll_enable(encoder);
a4fc5ed6
KP		 2934}
2935
fd6bbda9
ML		 2936static void chv_pre_enable_dp(struct intel_encoder *encoder,
2937 struct intel_crtc_state *pipe_config,
2938 struct drm_connector_state *conn_state)
e4a1d846 2939{
e7d2a717 2940 chv_phy_pre_encoder_enable(encoder);
e4a1d846 2941
85cb48a1 2942 intel_enable_dp(encoder, pipe_config);
b0b33846
VS		 2943
2944 /* Second common lane will stay alive on its own now */
e7d2a717 2945 chv_phy_release_cl2_override(encoder);
e4a1d846
CML		 2946}
2947
fd6bbda9
ML		 2948static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
2949 struct intel_crtc_state *pipe_config,
2950 struct drm_connector_state *conn_state)
9197c88b 2951{
85cb48a1 2952 intel_dp_prepare(encoder, pipe_config);
625695f8 2953
419b1b7a 2954 chv_phy_pre_pll_enable(encoder);
9197c88b
VS		 2955}
2956
fd6bbda9
ML		 2957static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
2958 struct intel_crtc_state *pipe_config,
2959 struct drm_connector_state *conn_state)
d6db995f 2960{
204970b5 2961 chv_phy_post_pll_disable(encoder);
d6db995f
VS		 2962}
2963
a4fc5ed6
KP		 2964/*
2965 * Fetch AUX CH registers 0x202 - 0x207 which contain
2966 * link status information
2967 */
94223d04 2968bool
93f62dad 2969intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2970{
9f085ebb
L		 2971 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
2972 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2973}
2974
1100244e 2975/* These are source-specific values. */
94223d04 2976uint8_t
1a2eb460 2977intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2978{
30add22d 2979 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 2980 struct drm_i915_private *dev_priv = to_i915(dev);
bc7d38a4 2981 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2982
9314726b
VK		 2983 if (IS_BROXTON(dev))
2984 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
2985 else if (INTEL_INFO(dev)->gen >= 9) {
06411f08 2986 if (dev_priv->vbt.edp.low_vswing && port == PORT_A)
7ad14a29 2987 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
5a9d1f1a 2988 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
666a4537 2989 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
bd60018a 2990 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2991 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2992 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
6e266956 2993 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
bd60018a 2994 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2995 else
bd60018a 2996 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2997}
2998
94223d04 2999uint8_t
1a2eb460
KP		 3000intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3001{
30add22d 3002 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 3003 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 3004
5a9d1f1a
DL		 3005 if (INTEL_INFO(dev)->gen >= 9) {
3006 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3007 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3008 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3009 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3010 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3011 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3012 return DP_TRAIN_PRE_EMPH_LEVEL_1;
7ad14a29
SJ		 3013 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3014 return DP_TRAIN_PRE_EMPH_LEVEL_0;
5a9d1f1a
DL		 3015 default:
3016 return DP_TRAIN_PRE_EMPH_LEVEL_0;
3017 }
3018 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 3019 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3020 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3021 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3022 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3023 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3024 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3025 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3026 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 3027 default:
bd60018a 3028 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 3029 }
666a4537 3030 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
e2fa6fba 3031 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3032 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3033 return DP_TRAIN_PRE_EMPH_LEVEL_3;
3034 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3035 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3036 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3037 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3038 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 3039 default:
bd60018a 3040 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 3041 }
bc7d38a4 3042 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 3043 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3044 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3045 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3046 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3047 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3048 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 3049 default:
bd60018a 3050 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 3051 }
3052 } else {
3053 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 3054 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3055 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3056 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3057 return DP_TRAIN_PRE_EMPH_LEVEL_2;
3058 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3059 return DP_TRAIN_PRE_EMPH_LEVEL_1;
3060 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 3061 default:
bd60018a 3062 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 3063 }
a4fc5ed6
KP		 3064 }
3065}
3066
5829975c 3067static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
e2fa6fba 3068{
53d98725 3069 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
e2fa6fba
P		 3070 unsigned long demph_reg_value, preemph_reg_value,
3071 uniqtranscale_reg_value;
3072 uint8_t train_set = intel_dp->train_set[0];
e2fa6fba
P		 3073
3074 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3075 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 3076 preemph_reg_value = 0x0004000;
3077 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3078 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3079 demph_reg_value = 0x2B405555;
3080 uniqtranscale_reg_value = 0x552AB83A;
3081 break;
bd60018a 3082 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3083 demph_reg_value = 0x2B404040;
3084 uniqtranscale_reg_value = 0x5548B83A;
3085 break;
bd60018a 3086 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3087 demph_reg_value = 0x2B245555;
3088 uniqtranscale_reg_value = 0x5560B83A;
3089 break;
bd60018a 3090 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3091 demph_reg_value = 0x2B405555;
3092 uniqtranscale_reg_value = 0x5598DA3A;
3093 break;
3094 default:
3095 return 0;
3096 }
3097 break;
bd60018a 3098 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3099 preemph_reg_value = 0x0002000;
3100 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3101 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3102 demph_reg_value = 0x2B404040;
3103 uniqtranscale_reg_value = 0x5552B83A;
3104 break;
bd60018a 3105 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3106 demph_reg_value = 0x2B404848;
3107 uniqtranscale_reg_value = 0x5580B83A;
3108 break;
bd60018a 3109 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3110 demph_reg_value = 0x2B404040;
3111 uniqtranscale_reg_value = 0x55ADDA3A;
3112 break;
3113 default:
3114 return 0;
3115 }
3116 break;
bd60018a 3117 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3118 preemph_reg_value = 0x0000000;
3119 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3120 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3121 demph_reg_value = 0x2B305555;
3122 uniqtranscale_reg_value = 0x5570B83A;
3123 break;
bd60018a 3124 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3125 demph_reg_value = 0x2B2B4040;
3126 uniqtranscale_reg_value = 0x55ADDA3A;
3127 break;
3128 default:
3129 return 0;
3130 }
3131 break;
bd60018a 3132 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3133 preemph_reg_value = 0x0006000;
3134 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3135 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3136 demph_reg_value = 0x1B405555;
3137 uniqtranscale_reg_value = 0x55ADDA3A;
3138 break;
3139 default:
3140 return 0;
3141 }
3142 break;
3143 default:
3144 return 0;
3145 }
3146
53d98725
ACO		 3147 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3148 uniqtranscale_reg_value, 0);
e2fa6fba
P		 3149
3150 return 0;
3151}
3152
5829975c 3153static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
e4a1d846 3154{
b7fa22d8
ACO		 3155 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3156 u32 deemph_reg_value, margin_reg_value;
3157 bool uniq_trans_scale = false;
e4a1d846 3158 uint8_t train_set = intel_dp->train_set[0];
e4a1d846
CML		 3159
3160 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3161 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3162 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3163 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3164 deemph_reg_value = 128;
3165 margin_reg_value = 52;
3166 break;
bd60018a 3167 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3168 deemph_reg_value = 128;
3169 margin_reg_value = 77;
3170 break;
bd60018a 3171 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3172 deemph_reg_value = 128;
3173 margin_reg_value = 102;
3174 break;
bd60018a 3175 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3176 deemph_reg_value = 128;
3177 margin_reg_value = 154;
b7fa22d8 3178 uniq_trans_scale = true;
e4a1d846
CML		 3179 break;
3180 default:
3181 return 0;
3182 }
3183 break;
bd60018a 3184 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3185 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3186 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3187 deemph_reg_value = 85;
3188 margin_reg_value = 78;
3189 break;
bd60018a 3190 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3191 deemph_reg_value = 85;
3192 margin_reg_value = 116;
3193 break;
bd60018a 3194 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3195 deemph_reg_value = 85;
3196 margin_reg_value = 154;
3197 break;
3198 default:
3199 return 0;
3200 }
3201 break;
bd60018a 3202 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3203 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3204 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3205 deemph_reg_value = 64;
3206 margin_reg_value = 104;
3207 break;
bd60018a 3208 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3209 deemph_reg_value = 64;
3210 margin_reg_value = 154;
3211 break;
3212 default:
3213 return 0;
3214 }
3215 break;
bd60018a 3216 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3217 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3218 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3219 deemph_reg_value = 43;
3220 margin_reg_value = 154;
3221 break;
3222 default:
3223 return 0;
3224 }
3225 break;
3226 default:
3227 return 0;
3228 }
3229
b7fa22d8
ACO		 3230 chv_set_phy_signal_level(encoder, deemph_reg_value,
3231 margin_reg_value, uniq_trans_scale);
e4a1d846
CML		 3232
3233 return 0;
3234}
3235
a4fc5ed6 3236static uint32_t
5829975c 3237gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3238{
3cf2efb1 3239 uint32_t signal_levels = 0;
a4fc5ed6 3240
3cf2efb1 3241 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3242 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3243 default:
3244 signal_levels |= DP_VOLTAGE_0_4;
3245 break;
bd60018a 3246 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3247 signal_levels |= DP_VOLTAGE_0_6;
3248 break;
bd60018a 3249 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3250 signal_levels |= DP_VOLTAGE_0_8;
3251 break;
bd60018a 3252 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3253 signal_levels |= DP_VOLTAGE_1_2;
3254 break;
3255 }
3cf2efb1 3256 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3257 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3258 default:
3259 signal_levels |= DP_PRE_EMPHASIS_0;
3260 break;
bd60018a 3261 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3262 signal_levels |= DP_PRE_EMPHASIS_3_5;
3263 break;
bd60018a 3264 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3265 signal_levels |= DP_PRE_EMPHASIS_6;
3266 break;
bd60018a 3267 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3268 signal_levels |= DP_PRE_EMPHASIS_9_5;
3269 break;
3270 }
3271 return signal_levels;
3272}
3273
e3421a18
ZW		 3274/* Gen6's DP voltage swing and pre-emphasis control */
3275static uint32_t
5829975c 3276gen6_edp_signal_levels(uint8_t train_set)
e3421a18 3277{
3c5a62b5
YL		 3278 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3279 DP_TRAIN_PRE_EMPHASIS_MASK);
3280 switch (signal_levels) {
bd60018a
SJ		 3281 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3282 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3283 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3284 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3285 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3286 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3287 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3288 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3289 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3290 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3291 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3292 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3293 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3294 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3295 default:
3c5a62b5
YL		 3296 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3297 "0x%x\n", signal_levels);
3298 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3299 }
3300}
3301
1a2eb460
KP		 3302/* Gen7's DP voltage swing and pre-emphasis control */
3303static uint32_t
5829975c 3304gen7_edp_signal_levels(uint8_t train_set)
1a2eb460
KP		 3305{
3306 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3307 DP_TRAIN_PRE_EMPHASIS_MASK);
3308 switch (signal_levels) {
bd60018a 3309 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3310 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3311 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3312 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3313 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3314 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3315
bd60018a 3316 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3317 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3318 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3319 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3320
bd60018a 3321 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3322 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3323 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3324 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3325
3326 default:
3327 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3328 "0x%x\n", signal_levels);
3329 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3330 }
3331}
3332
94223d04 3333void
f4eb692e 3334intel_dp_set_signal_levels(struct intel_dp *intel_dp)
f0a3424e
PZ		 3335{
3336 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3337 enum port port = intel_dig_port->port;
f0a3424e 3338 struct drm_device *dev = intel_dig_port->base.base.dev;
b905a915 3339 struct drm_i915_private *dev_priv = to_i915(dev);
f8896f5d 3340 uint32_t signal_levels, mask = 0;
f0a3424e
PZ		 3341 uint8_t train_set = intel_dp->train_set[0];
3342
4f8036a2 3343 if (HAS_DDI(dev_priv)) {
f8896f5d
DW		 3344 signal_levels = ddi_signal_levels(intel_dp);
3345
3346 if (IS_BROXTON(dev))
3347 signal_levels = 0;
3348 else
3349 mask = DDI_BUF_EMP_MASK;
e4a1d846 3350 } else if (IS_CHERRYVIEW(dev)) {
5829975c 3351 signal_levels = chv_signal_levels(intel_dp);
e2fa6fba 3352 } else if (IS_VALLEYVIEW(dev)) {
5829975c 3353 signal_levels = vlv_signal_levels(intel_dp);
bc7d38a4 3354 } else if (IS_GEN7(dev) && port == PORT_A) {
5829975c 3355 signal_levels = gen7_edp_signal_levels(train_set);
f0a3424e 3356 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3357 } else if (IS_GEN6(dev) && port == PORT_A) {
5829975c 3358 signal_levels = gen6_edp_signal_levels(train_set);
f0a3424e
PZ		 3359 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3360 } else {
5829975c 3361 signal_levels = gen4_signal_levels(train_set);
f0a3424e
PZ		 3362 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3363 }
3364
96fb9f9b
VK		 3365 if (mask)
3366 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3367
3368 DRM_DEBUG_KMS("Using vswing level %d\n",
3369 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3370 DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3371 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3372 DP_TRAIN_PRE_EMPHASIS_SHIFT);
f0a3424e 3373
f4eb692e 3374 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
b905a915
ACO		 3375
3376 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3377 POSTING_READ(intel_dp->output_reg);
f0a3424e
PZ		 3378}
3379
94223d04 3380void
e9c176d5
ACO		 3381intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3382 uint8_t dp_train_pat)
a4fc5ed6 3383{
174edf1f 3384 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
90a6b7b0
VS		 3385 struct drm_i915_private *dev_priv =
3386 to_i915(intel_dig_port->base.base.dev);
a4fc5ed6 3387
f4eb692e 3388 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
47ea7542 3389
f4eb692e 3390 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
ea5b213a 3391 POSTING_READ(intel_dp->output_reg);
e9c176d5
ACO		 3392}
3393
94223d04 3394void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3ab9c637
ID		 3395{
3396 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3397 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 3398 struct drm_i915_private *dev_priv = to_i915(dev);
3ab9c637
ID		 3399 enum port port = intel_dig_port->port;
3400 uint32_t val;
3401
4f8036a2 3402 if (!HAS_DDI(dev_priv))
3ab9c637
ID		 3403 return;
3404
3405 val = I915_READ(DP_TP_CTL(port));
3406 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3407 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3408 I915_WRITE(DP_TP_CTL(port), val);
3409
3410 /*
3411 * On PORT_A we can have only eDP in SST mode. There the only reason
3412 * we need to set idle transmission mode is to work around a HW issue
3413 * where we enable the pipe while not in idle link-training mode.
3414 * In this case there is requirement to wait for a minimum number of
3415 * idle patterns to be sent.
3416 */
3417 if (port == PORT_A)
3418 return;
3419
a767017f
CW		 3420 if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3421 DP_TP_STATUS_IDLE_DONE,
3422 DP_TP_STATUS_IDLE_DONE,
3423 1))
3ab9c637
ID		 3424 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3425}
3426
a4fc5ed6 3427static void
ea5b213a 3428intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3429{
da63a9f2 3430 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1612c8bd 3431 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
bc7d38a4 3432 enum port port = intel_dig_port->port;
da63a9f2 3433 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 3434 struct drm_i915_private *dev_priv = to_i915(dev);
ea5b213a 3435 uint32_t DP = intel_dp->DP;
a4fc5ed6 3436
4f8036a2 3437 if (WARN_ON(HAS_DDI(dev_priv)))
c19b0669
PZ		 3438 return;
3439
0c33d8d7 3440 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3441 return;
3442
28c97730 3443 DRM_DEBUG_KMS("\n");
32f9d658 3444
39e5fa88 3445 if ((IS_GEN7(dev) && port == PORT_A) ||
6e266956 3446 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
e3421a18 3447 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1612c8bd 3448 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
e3421a18 3449 } else {
aad3d14d
VS		 3450 if (IS_CHERRYVIEW(dev))
3451 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3452 else
3453 DP &= ~DP_LINK_TRAIN_MASK;
1612c8bd 3454 DP |= DP_LINK_TRAIN_PAT_IDLE;
e3421a18 3455 }
1612c8bd 3456 I915_WRITE(intel_dp->output_reg, DP);
fe255d00 3457 POSTING_READ(intel_dp->output_reg);
5eb08b69 3458
1612c8bd
VS		 3459 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3460 I915_WRITE(intel_dp->output_reg, DP);
3461 POSTING_READ(intel_dp->output_reg);
3462
3463 /*
3464 * HW workaround for IBX, we need to move the port
3465 * to transcoder A after disabling it to allow the
3466 * matching HDMI port to be enabled on transcoder A.
3467 */
6e266956 3468 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
0c241d5b
VS		 3469 /*
3470 * We get CPU/PCH FIFO underruns on the other pipe when
3471 * doing the workaround. Sweep them under the rug.
3472 */
3473 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3474 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3475
1612c8bd
VS		 3476 /* always enable with pattern 1 (as per spec) */
3477 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3478 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3479 I915_WRITE(intel_dp->output_reg, DP);
3480 POSTING_READ(intel_dp->output_reg);
3481
3482 DP &= ~DP_PORT_EN;
5bddd17f 3483 I915_WRITE(intel_dp->output_reg, DP);
0ca09685 3484 POSTING_READ(intel_dp->output_reg);
0c241d5b 3485
91c8a326 3486 intel_wait_for_vblank_if_active(&dev_priv->drm, PIPE_A);
0c241d5b
VS		 3487 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3488 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
5bddd17f
EA		 3489 }
3490
f01eca2e 3491 msleep(intel_dp->panel_power_down_delay);
6fec7662
VS		 3492
3493 intel_dp->DP = DP;
a4fc5ed6
KP		 3494}
3495
26d61aad 3496static bool
fe5a66f9 3497intel_dp_read_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3498{
9f085ebb
L		 3499 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3500 sizeof(intel_dp->dpcd)) < 0)
edb39244 3501 return false; /* aux transfer failed */
92fd8fd1 3502
a8e98153 3503 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3504
fe5a66f9
VS		 3505 return intel_dp->dpcd[DP_DPCD_REV] != 0;
3506}
edb39244 3507
fe5a66f9
VS		 3508static bool
3509intel_edp_init_dpcd(struct intel_dp *intel_dp)
3510{
3511 struct drm_i915_private *dev_priv =
3512 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
30d9aa42 3513
fe5a66f9
VS		 3514 /* this function is meant to be called only once */
3515 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
30d9aa42 3516
fe5a66f9 3517 if (!intel_dp_read_dpcd(intel_dp))
30d9aa42
SS		 3518 return false;
3519
fe5a66f9
VS		 3520 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3521 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3522 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
474d1ec4 3523
fe5a66f9
VS		 3524 /* Check if the panel supports PSR */
3525 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3526 intel_dp->psr_dpcd,
3527 sizeof(intel_dp->psr_dpcd));
3528 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3529 dev_priv->psr.sink_support = true;
3530 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3531 }
86ee27b5 3532
fe5a66f9
VS		 3533 if (INTEL_GEN(dev_priv) >= 9 &&
3534 (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3535 uint8_t frame_sync_cap;
3536
3537 dev_priv->psr.sink_support = true;
3538 drm_dp_dpcd_read(&intel_dp->aux,
3539 DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3540 &frame_sync_cap, 1);
3541 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3542 /* PSR2 needs frame sync as well */
3543 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3544 DRM_DEBUG_KMS("PSR2 %s on sink",
3545 dev_priv->psr.psr2_support ? "supported" : "not supported");
50003939
JN		 3546 }
3547
fe5a66f9
VS		 3548 /* Read the eDP Display control capabilities registers */
3549 if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3550 drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
f7170e2e
DC		 3551 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3552 sizeof(intel_dp->edp_dpcd))
fe5a66f9
VS		 3553 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3554 intel_dp->edp_dpcd);
06ea66b6 3555
fc0f8e25 3556 /* Intermediate frequency support */
fe5a66f9 3557 if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
94ca719e 3558 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
ea2d8a42
VS		 3559 int i;
3560
9f085ebb
L		 3561 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3562 sink_rates, sizeof(sink_rates));
ea2d8a42 3563
94ca719e
VS		 3564 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3565 int val = le16_to_cpu(sink_rates[i]);
ea2d8a42
VS		 3566
3567 if (val == 0)
3568 break;
3569
af77b974
SJ		 3570 /* Value read is in kHz while drm clock is saved in deca-kHz */
3571 intel_dp->sink_rates[i] = (val * 200) / 10;
ea2d8a42 3572 }
94ca719e 3573 intel_dp->num_sink_rates = i;
fc0f8e25 3574 }
0336400e 3575
fe5a66f9
VS		 3576 return true;
3577}
3578
3579
3580static bool
3581intel_dp_get_dpcd(struct intel_dp *intel_dp)
3582{
3583 if (!intel_dp_read_dpcd(intel_dp))
3584 return false;
3585
3586 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT,
3587 &intel_dp->sink_count, 1) < 0)
3588 return false;
3589
3590 /*
3591 * Sink count can change between short pulse hpd hence
3592 * a member variable in intel_dp will track any changes
3593 * between short pulse interrupts.
3594 */
3595 intel_dp->sink_count = DP_GET_SINK_COUNT(intel_dp->sink_count);
3596
3597 /*
3598 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3599 * a dongle is present but no display. Unless we require to know
3600 * if a dongle is present or not, we don't need to update
3601 * downstream port information. So, an early return here saves
3602 * time from performing other operations which are not required.
3603 */
3604 if (!is_edp(intel_dp) && !intel_dp->sink_count)
3605 return false;
0336400e 3606
edb39244
AJ		 3607 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3608 DP_DWN_STRM_PORT_PRESENT))
3609 return true; /* native DP sink */
3610
3611 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3612 return true; /* no per-port downstream info */
3613
9f085ebb
L		 3614 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3615 intel_dp->downstream_ports,
3616 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3617 return false; /* downstream port status fetch failed */
3618
3619 return true;
92fd8fd1
KP		 3620}
3621
0d198328
AJ		 3622static void
3623intel_dp_probe_oui(struct intel_dp *intel_dp)
3624{
3625 u8 buf[3];
3626
3627 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3628 return;
3629
9f085ebb 3630 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3631 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3632 buf[0], buf[1], buf[2]);
3633
9f085ebb 3634 if (drm_dp_dpcd_read(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3635 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3636 buf[0], buf[1], buf[2]);
3637}
3638
0e32b39c 3639static bool
c4e3170a 3640intel_dp_can_mst(struct intel_dp *intel_dp)
0e32b39c
DA		 3641{
3642 u8 buf[1];
3643
7cc96139
NS		 3644 if (!i915.enable_dp_mst)
3645 return false;
3646
0e32b39c
DA		 3647 if (!intel_dp->can_mst)
3648 return false;
3649
3650 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3651 return false;
3652
c4e3170a
VS		 3653 if (drm_dp_dpcd_read(&intel_dp->aux, DP_MSTM_CAP, buf, 1) != 1)
3654 return false;
0e32b39c 3655
c4e3170a
VS		 3656 return buf[0] & DP_MST_CAP;
3657}
3658
3659static void
3660intel_dp_configure_mst(struct intel_dp *intel_dp)
3661{
3662 if (!i915.enable_dp_mst)
3663 return;
3664
3665 if (!intel_dp->can_mst)
3666 return;
3667
3668 intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3669
3670 if (intel_dp->is_mst)
3671 DRM_DEBUG_KMS("Sink is MST capable\n");
3672 else
3673 DRM_DEBUG_KMS("Sink is not MST capable\n");
3674
3675 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3676 intel_dp->is_mst);
0e32b39c
DA		 3677}
3678
e5a1cab5 3679static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
d2e216d0 3680{
082dcc7c 3681 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3682 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c 3683 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
ad9dc91b 3684 u8 buf;
e5a1cab5 3685 int ret = 0;
c6297843
RV		 3686 int count = 0;
3687 int attempts = 10;
d2e216d0 3688
082dcc7c
RV		 3689 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3690 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3691 ret = -EIO;
3692 goto out;
4373f0f2
PZ		 3693 }
3694
082dcc7c 3695 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
e5a1cab5 3696 buf & ~DP_TEST_SINK_START) < 0) {
082dcc7c 3697 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
e5a1cab5
RV		 3698 ret = -EIO;
3699 goto out;
3700 }
d2e216d0 3701
c6297843
RV		 3702 do {
3703 intel_wait_for_vblank(dev, intel_crtc->pipe);
3704
3705 if (drm_dp_dpcd_readb(&intel_dp->aux,
3706 DP_TEST_SINK_MISC, &buf) < 0) {
3707 ret = -EIO;
3708 goto out;
3709 }
3710 count = buf & DP_TEST_COUNT_MASK;
3711 } while (--attempts && count);
3712
3713 if (attempts == 0) {
dc5a9037 3714 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
c6297843
RV		 3715 ret = -ETIMEDOUT;
3716 }
3717
e5a1cab5 3718 out:
082dcc7c 3719 hsw_enable_ips(intel_crtc);
e5a1cab5 3720 return ret;
082dcc7c
RV		 3721}
3722
3723static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3724{
3725 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
d72f9d91 3726 struct drm_device *dev = dig_port->base.base.dev;
082dcc7c
RV		 3727 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3728 u8 buf;
e5a1cab5
RV		 3729 int ret;
3730
082dcc7c
RV		 3731 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3732 return -EIO;
3733
3734 if (!(buf & DP_TEST_CRC_SUPPORTED))
3735 return -ENOTTY;
3736
3737 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3738 return -EIO;
3739
6d8175da
RV		 3740 if (buf & DP_TEST_SINK_START) {
3741 ret = intel_dp_sink_crc_stop(intel_dp);
3742 if (ret)
3743 return ret;
3744 }
3745
082dcc7c 3746 hsw_disable_ips(intel_crtc);
1dda5f93 3747
9d1a1031 3748 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
082dcc7c
RV		 3749 buf | DP_TEST_SINK_START) < 0) {
3750 hsw_enable_ips(intel_crtc);
3751 return -EIO;
4373f0f2
PZ		 3752 }
3753
d72f9d91 3754 intel_wait_for_vblank(dev, intel_crtc->pipe);
082dcc7c
RV		 3755 return 0;
3756}
3757
3758int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3759{
3760 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3761 struct drm_device *dev = dig_port->base.base.dev;
3762 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3763 u8 buf;
621d4c76 3764 int count, ret;
082dcc7c 3765 int attempts = 6;
082dcc7c
RV		 3766
3767 ret = intel_dp_sink_crc_start(intel_dp);
3768 if (ret)
3769 return ret;
3770
ad9dc91b 3771 do {
621d4c76
RV		 3772 intel_wait_for_vblank(dev, intel_crtc->pipe);
3773
1dda5f93 3774 if (drm_dp_dpcd_readb(&intel_dp->aux,
4373f0f2
PZ		 3775 DP_TEST_SINK_MISC, &buf) < 0) {
3776 ret = -EIO;
afe0d67e 3777 goto stop;
4373f0f2 3778 }
621d4c76 3779 count = buf & DP_TEST_COUNT_MASK;
aabc95dc 3780
7e38eeff 3781 } while (--attempts && count == 0);
ad9dc91b
RV		 3782
3783 if (attempts == 0) {
7e38eeff
RV		 3784 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3785 ret = -ETIMEDOUT;
3786 goto stop;
3787 }
3788
3789 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3790 ret = -EIO;
3791 goto stop;
ad9dc91b 3792 }
d2e216d0 3793
afe0d67e 3794stop:
082dcc7c 3795 intel_dp_sink_crc_stop(intel_dp);
4373f0f2 3796 return ret;
d2e216d0
RV		 3797}
3798
a60f0e38
JB		 3799static bool
3800intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3801{
9f085ebb 3802 return drm_dp_dpcd_read(&intel_dp->aux,
9d1a1031
JN		 3803 DP_DEVICE_SERVICE_IRQ_VECTOR,
3804 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3805}
3806
0e32b39c
DA		 3807static bool
3808intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3809{
3810 int ret;
3811
9f085ebb 3812 ret = drm_dp_dpcd_read(&intel_dp->aux,
0e32b39c
DA		 3813 DP_SINK_COUNT_ESI,
3814 sink_irq_vector, 14);
3815 if (ret != 14)
3816 return false;
3817
3818 return true;
3819}
3820
c5d5ab7a
TP		 3821static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3822{
3823 uint8_t test_result = DP_TEST_ACK;
3824 return test_result;
3825}
3826
3827static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3828{
3829 uint8_t test_result = DP_TEST_NAK;
3830 return test_result;
3831}
3832
3833static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
a60f0e38 3834{
c5d5ab7a 3835 uint8_t test_result = DP_TEST_NAK;
559be30c
TP		 3836 struct intel_connector *intel_connector = intel_dp->attached_connector;
3837 struct drm_connector *connector = &intel_connector->base;
3838
3839 if (intel_connector->detect_edid == NULL ||
ac6f2e29 3840 connector->edid_corrupt ||
559be30c
TP		 3841 intel_dp->aux.i2c_defer_count > 6) {
3842 /* Check EDID read for NACKs, DEFERs and corruption
3843 * (DP CTS 1.2 Core r1.1)
3844 * 4.2.2.4 : Failed EDID read, I2C_NAK
3845 * 4.2.2.5 : Failed EDID read, I2C_DEFER
3846 * 4.2.2.6 : EDID corruption detected
3847 * Use failsafe mode for all cases
3848 */
3849 if (intel_dp->aux.i2c_nack_count > 0 ||
3850 intel_dp->aux.i2c_defer_count > 0)
3851 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
3852 intel_dp->aux.i2c_nack_count,
3853 intel_dp->aux.i2c_defer_count);
3854 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
3855 } else {
f79b468e
TS		 3856 struct edid *block = intel_connector->detect_edid;
3857
3858 /* We have to write the checksum
3859 * of the last block read
3860 */
3861 block += intel_connector->detect_edid->extensions;
3862
559be30c
TP		 3863 if (!drm_dp_dpcd_write(&intel_dp->aux,
3864 DP_TEST_EDID_CHECKSUM,
f79b468e 3865 &block->checksum,
5a1cc655 3866 1))
559be30c
TP		 3867 DRM_DEBUG_KMS("Failed to write EDID checksum\n");
3868
3869 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
3870 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
3871 }
3872
3873 /* Set test active flag here so userspace doesn't interrupt things */
3874 intel_dp->compliance_test_active = 1;
3875
c5d5ab7a
TP		 3876 return test_result;
3877}
3878
3879static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
a60f0e38 3880{
c5d5ab7a
TP		 3881 uint8_t test_result = DP_TEST_NAK;
3882 return test_result;
3883}
3884
3885static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
3886{
3887 uint8_t response = DP_TEST_NAK;
3888 uint8_t rxdata = 0;
3889 int status = 0;
3890
c5d5ab7a
TP		 3891 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
3892 if (status <= 0) {
3893 DRM_DEBUG_KMS("Could not read test request from sink\n");
3894 goto update_status;
3895 }
3896
3897 switch (rxdata) {
3898 case DP_TEST_LINK_TRAINING:
3899 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
3900 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
3901 response = intel_dp_autotest_link_training(intel_dp);
3902 break;
3903 case DP_TEST_LINK_VIDEO_PATTERN:
3904 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
3905 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
3906 response = intel_dp_autotest_video_pattern(intel_dp);
3907 break;
3908 case DP_TEST_LINK_EDID_READ:
3909 DRM_DEBUG_KMS("EDID test requested\n");
3910 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
3911 response = intel_dp_autotest_edid(intel_dp);
3912 break;
3913 case DP_TEST_LINK_PHY_TEST_PATTERN:
3914 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
3915 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
3916 response = intel_dp_autotest_phy_pattern(intel_dp);
3917 break;
3918 default:
3919 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
3920 break;
3921 }
3922
3923update_status:
3924 status = drm_dp_dpcd_write(&intel_dp->aux,
3925 DP_TEST_RESPONSE,
3926 &response, 1);
3927 if (status <= 0)
3928 DRM_DEBUG_KMS("Could not write test response to sink\n");
a60f0e38
JB		 3929}
3930
0e32b39c
DA		 3931static int
3932intel_dp_check_mst_status(struct intel_dp *intel_dp)
3933{
3934 bool bret;
3935
3936 if (intel_dp->is_mst) {
3937 u8 esi[16] = { 0 };
3938 int ret = 0;
3939 int retry;
3940 bool handled;
3941 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3942go_again:
3943 if (bret == true) {
3944
3945 /* check link status - esi[10] = 0x200c */
19e0b4ca 3946 if (intel_dp->active_mst_links &&
901c2daf 3947 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
0e32b39c
DA		 3948 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3949 intel_dp_start_link_train(intel_dp);
0e32b39c
DA		 3950 intel_dp_stop_link_train(intel_dp);
3951 }
3952
6f34cc39 3953 DRM_DEBUG_KMS("got esi %3ph\n", esi);
0e32b39c
DA		 3954 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3955
3956 if (handled) {
3957 for (retry = 0; retry < 3; retry++) {
3958 int wret;
3959 wret = drm_dp_dpcd_write(&intel_dp->aux,
3960 DP_SINK_COUNT_ESI+1,
3961 &esi[1], 3);
3962 if (wret == 3) {
3963 break;
3964 }
3965 }
3966
3967 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3968 if (bret == true) {
6f34cc39 3969 DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
0e32b39c
DA		 3970 goto go_again;
3971 }
3972 } else
3973 ret = 0;
3974
3975 return ret;
3976 } else {
3977 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3978 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3979 intel_dp->is_mst = false;
3980 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3981 /* send a hotplug event */
3982 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3983 }
3984 }
3985 return -EINVAL;
3986}
3987
5c9114d0
SS		 3988static void
3989intel_dp_check_link_status(struct intel_dp *intel_dp)
3990{
3991 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3992 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3993 u8 link_status[DP_LINK_STATUS_SIZE];
3994
3995 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3996
3997 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3998 DRM_ERROR("Failed to get link status\n");
3999 return;
4000 }
4001
4002 if (!intel_encoder->base.crtc)
4003 return;
4004
4005 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4006 return;
4007
4008 /* if link training is requested we should perform it always */
4009 if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
4010 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
4011 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4012 intel_encoder->base.name);
4013 intel_dp_start_link_train(intel_dp);
4014 intel_dp_stop_link_train(intel_dp);
4015 }
4016}
4017
a4fc5ed6
KP		 4018/*
4019 * According to DP spec
4020 * 5.1.2:
4021 * 1. Read DPCD
4022 * 2. Configure link according to Receiver Capabilities
4023 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4024 * 4. Check link status on receipt of hot-plug interrupt
39ff747b
SS		 4025 *
4026 * intel_dp_short_pulse - handles short pulse interrupts
4027 * when full detection is not required.
4028 * Returns %true if short pulse is handled and full detection
4029 * is NOT required and %false otherwise.
a4fc5ed6 4030 */
39ff747b 4031static bool
5c9114d0 4032intel_dp_short_pulse(struct intel_dp *intel_dp)
a4fc5ed6 4033{
5b215bcf 4034 struct drm_device *dev = intel_dp_to_dev(intel_dp);
65fbb4e7 4035 u8 sink_irq_vector = 0;
39ff747b
SS		 4036 u8 old_sink_count = intel_dp->sink_count;
4037 bool ret;
5b215bcf 4038
4df6960e
SS		 4039 /*
4040 * Clearing compliance test variables to allow capturing
4041 * of values for next automated test request.
4042 */
4043 intel_dp->compliance_test_active = 0;
4044 intel_dp->compliance_test_type = 0;
4045 intel_dp->compliance_test_data = 0;
4046
39ff747b
SS		 4047 /*
4048 * Now read the DPCD to see if it's actually running
4049 * If the current value of sink count doesn't match with
4050 * the value that was stored earlier or dpcd read failed
4051 * we need to do full detection
4052 */
4053 ret = intel_dp_get_dpcd(intel_dp);
4054
4055 if ((old_sink_count != intel_dp->sink_count) || !ret) {
4056 /* No need to proceed if we are going to do full detect */
4057 return false;
59cd09e1
JB		 4058 }
4059
a60f0e38
JB		 4060 /* Try to read the source of the interrupt */
4061 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
65fbb4e7
VS		 4062 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4063 sink_irq_vector != 0) {
a60f0e38 4064 /* Clear interrupt source */
9d1a1031
JN		 4065 drm_dp_dpcd_writeb(&intel_dp->aux,
4066 DP_DEVICE_SERVICE_IRQ_VECTOR,
4067 sink_irq_vector);
a60f0e38
JB		 4068
4069 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
09b1eb13 4070 DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
a60f0e38
JB		 4071 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4072 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4073 }
4074
5c9114d0
SS		 4075 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4076 intel_dp_check_link_status(intel_dp);
4077 drm_modeset_unlock(&dev->mode_config.connection_mutex);
39ff747b
SS		 4078
4079 return true;
a4fc5ed6 4080}
a4fc5ed6 4081
caf9ab24 4082/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4083static enum drm_connector_status
26d61aad 4084intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4085{
caf9ab24 4086 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4087 uint8_t type;
4088
4089 if (!intel_dp_get_dpcd(intel_dp))
4090 return connector_status_disconnected;
4091
1034ce70
SS		 4092 if (is_edp(intel_dp))
4093 return connector_status_connected;
4094
caf9ab24
AJ		 4095 /* if there's no downstream port, we're done */
4096 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4097 return connector_status_connected;
caf9ab24
AJ		 4098
4099 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4100 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4101 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
9d1a1031 4102
30d9aa42
SS		 4103 return intel_dp->sink_count ?
4104 connector_status_connected : connector_status_disconnected;
caf9ab24
AJ		 4105 }
4106
c4e3170a
VS		 4107 if (intel_dp_can_mst(intel_dp))
4108 return connector_status_connected;
4109
caf9ab24 4110 /* If no HPD, poke DDC gently */
0b99836f 4111 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4112 return connector_status_connected;
caf9ab24
AJ		 4113
4114 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4115 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4116 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4117 if (type == DP_DS_PORT_TYPE_VGA ||
4118 type == DP_DS_PORT_TYPE_NON_EDID)
4119 return connector_status_unknown;
4120 } else {
4121 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4122 DP_DWN_STRM_PORT_TYPE_MASK;
4123 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4124 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4125 return connector_status_unknown;
4126 }
caf9ab24
AJ		 4127
4128 /* Anything else is out of spec, warn and ignore */
4129 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4130 return connector_status_disconnected;
71ba9000
AJ		 4131}
4132
d410b56d
CW		 4133static enum drm_connector_status
4134edp_detect(struct intel_dp *intel_dp)
4135{
4136 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4137 enum drm_connector_status status;
4138
4139 status = intel_panel_detect(dev);
4140 if (status == connector_status_unknown)
4141 status = connector_status_connected;
4142
4143 return status;
4144}
4145
b93433cc
JN		 4146static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4147 struct intel_digital_port *port)
5eb08b69 4148{
b93433cc 4149 u32 bit;
01cb9ea6 4150
0df53b77
JN		 4151 switch (port->port) {
4152 case PORT_A:
4153 return true;
4154 case PORT_B:
4155 bit = SDE_PORTB_HOTPLUG;
4156 break;
4157 case PORT_C:
4158 bit = SDE_PORTC_HOTPLUG;
4159 break;
4160 case PORT_D:
4161 bit = SDE_PORTD_HOTPLUG;
4162 break;
4163 default:
4164 MISSING_CASE(port->port);
4165 return false;
4166 }
4167
4168 return I915_READ(SDEISR) & bit;
4169}
4170
4171static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4172 struct intel_digital_port *port)
4173{
4174 u32 bit;
4175
4176 switch (port->port) {
4177 case PORT_A:
4178 return true;
4179 case PORT_B:
4180 bit = SDE_PORTB_HOTPLUG_CPT;
4181 break;
4182 case PORT_C:
4183 bit = SDE_PORTC_HOTPLUG_CPT;
4184 break;
4185 case PORT_D:
4186 bit = SDE_PORTD_HOTPLUG_CPT;
4187 break;
a78695d3
JN		 4188 case PORT_E:
4189 bit = SDE_PORTE_HOTPLUG_SPT;
4190 break;
0df53b77
JN		 4191 default:
4192 MISSING_CASE(port->port);
4193 return false;
b93433cc 4194 }
1b469639 4195
b93433cc 4196 return I915_READ(SDEISR) & bit;
5eb08b69
ZW		 4197}
4198
7e66bcf2 4199static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
1d245987 4200 struct intel_digital_port *port)
a4fc5ed6 4201{
9642c81c 4202 u32 bit;
5eb08b69 4203
9642c81c
JN		 4204 switch (port->port) {
4205 case PORT_B:
4206 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4207 break;
4208 case PORT_C:
4209 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4210 break;
4211 case PORT_D:
4212 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4213 break;
4214 default:
4215 MISSING_CASE(port->port);
4216 return false;
4217 }
4218
4219 return I915_READ(PORT_HOTPLUG_STAT) & bit;
4220}
4221
0780cd36
VS		 4222static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4223 struct intel_digital_port *port)
9642c81c
JN		 4224{
4225 u32 bit;
4226
4227 switch (port->port) {
4228 case PORT_B:
0780cd36 4229 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4230 break;
4231 case PORT_C:
0780cd36 4232 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4233 break;
4234 case PORT_D:
0780cd36 4235 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
9642c81c
JN		 4236 break;
4237 default:
4238 MISSING_CASE(port->port);
4239 return false;
a4fc5ed6
KP		 4240 }
4241
1d245987 4242 return I915_READ(PORT_HOTPLUG_STAT) & bit;
2a592bec
DA		 4243}
4244
e464bfde 4245static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
e2ec35a5 4246 struct intel_digital_port *intel_dig_port)
e464bfde 4247{
e2ec35a5
SJ		 4248 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4249 enum port port;
e464bfde
JN		 4250 u32 bit;
4251
e2ec35a5
SJ		 4252 intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4253 switch (port) {
e464bfde
JN		 4254 case PORT_A:
4255 bit = BXT_DE_PORT_HP_DDIA;
4256 break;
4257 case PORT_B:
4258 bit = BXT_DE_PORT_HP_DDIB;
4259 break;
4260 case PORT_C:
4261 bit = BXT_DE_PORT_HP_DDIC;
4262 break;
4263 default:
e2ec35a5 4264 MISSING_CASE(port);
e464bfde
JN		 4265 return false;
4266 }
4267
4268 return I915_READ(GEN8_DE_PORT_ISR) & bit;
4269}
4270
7e66bcf2
JN		 4271/*
4272 * intel_digital_port_connected - is the specified port connected?
4273 * @dev_priv: i915 private structure
4274 * @port: the port to test
4275 *
4276 * Return %true if @port is connected, %false otherwise.
4277 */
23f889bd 4278static bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
7e66bcf2
JN		 4279 struct intel_digital_port *port)
4280{
0df53b77 4281 if (HAS_PCH_IBX(dev_priv))
7e66bcf2 4282 return ibx_digital_port_connected(dev_priv, port);
22824fac 4283 else if (HAS_PCH_SPLIT(dev_priv))
0df53b77 4284 return cpt_digital_port_connected(dev_priv, port);
e464bfde
JN		 4285 else if (IS_BROXTON(dev_priv))
4286 return bxt_digital_port_connected(dev_priv, port);
0780cd36
VS		 4287 else if (IS_GM45(dev_priv))
4288 return gm45_digital_port_connected(dev_priv, port);
7e66bcf2
JN		 4289 else
4290 return g4x_digital_port_connected(dev_priv, port);
4291}
4292
8c241fef 4293static struct edid *
beb60608 4294intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4295{
beb60608 4296 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4297
9cd300e0
JN		 4298 /* use cached edid if we have one */
4299 if (intel_connector->edid) {
9cd300e0
JN		 4300 /* invalid edid */
4301 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4302 return NULL;
4303
55e9edeb 4304 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4305 } else
4306 return drm_get_edid(&intel_connector->base,
4307 &intel_dp->aux.ddc);
4308}
8c241fef 4309
beb60608
CW		 4310static void
4311intel_dp_set_edid(struct intel_dp *intel_dp)
4312{
4313 struct intel_connector *intel_connector = intel_dp->attached_connector;
4314 struct edid *edid;
8c241fef 4315
f21a2198 4316 intel_dp_unset_edid(intel_dp);
beb60608
CW		 4317 edid = intel_dp_get_edid(intel_dp);
4318 intel_connector->detect_edid = edid;
4319
4320 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4321 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4322 else
4323 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4324}
4325
beb60608
CW		 4326static void
4327intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4328{
beb60608 4329 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4330
beb60608
CW		 4331 kfree(intel_connector->detect_edid);
4332 intel_connector->detect_edid = NULL;
9cd300e0 4333
beb60608
CW		 4334 intel_dp->has_audio = false;
4335}
d6f24d0f 4336
5cb651a7 4337static enum drm_connector_status
f21a2198 4338intel_dp_long_pulse(struct intel_connector *intel_connector)
a9756bb5 4339{
f21a2198 4340 struct drm_connector *connector = &intel_connector->base;
a9756bb5 4341 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4342 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4343 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4344 struct drm_device *dev = connector->dev;
a9756bb5 4345 enum drm_connector_status status;
671dedd2 4346 enum intel_display_power_domain power_domain;
65fbb4e7 4347 u8 sink_irq_vector = 0;
a9756bb5 4348
25f78f58
VS		 4349 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4350 intel_display_power_get(to_i915(dev), power_domain);
a9756bb5 4351
d410b56d
CW		 4352 /* Can't disconnect eDP, but you can close the lid... */
4353 if (is_edp(intel_dp))
4354 status = edp_detect(intel_dp);
c555a81d
ACO		 4355 else if (intel_digital_port_connected(to_i915(dev),
4356 dp_to_dig_port(intel_dp)))
4357 status = intel_dp_detect_dpcd(intel_dp);
a9756bb5 4358 else
c555a81d
ACO		 4359 status = connector_status_disconnected;
4360
5cb651a7 4361 if (status == connector_status_disconnected) {
4df6960e
SS		 4362 intel_dp->compliance_test_active = 0;
4363 intel_dp->compliance_test_type = 0;
4364 intel_dp->compliance_test_data = 0;
4365
0e505a08 4366 if (intel_dp->is_mst) {
4367 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4368 intel_dp->is_mst,
4369 intel_dp->mst_mgr.mst_state);
4370 intel_dp->is_mst = false;
4371 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4372 intel_dp->is_mst);
4373 }
4374
c8c8fb33 4375 goto out;
4df6960e 4376 }
a9756bb5 4377
f21a2198 4378 if (intel_encoder->type != INTEL_OUTPUT_EDP)
cca0502b 4379 intel_encoder->type = INTEL_OUTPUT_DP;
f21a2198 4380
fe5a66f9
VS		 4381 DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4382 yesno(intel_dp_source_supports_hbr2(intel_dp)),
4383 yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4384
4385 intel_dp_print_rates(intel_dp);
4386
0d198328
AJ		 4387 intel_dp_probe_oui(intel_dp);
4388
0e390a33 4389 intel_dp_print_hw_revision(intel_dp);
1a2724fa 4390 intel_dp_print_sw_revision(intel_dp);
0e390a33 4391
c4e3170a
VS		 4392 intel_dp_configure_mst(intel_dp);
4393
4394 if (intel_dp->is_mst) {
f21a2198
SS		 4395 /*
4396 * If we are in MST mode then this connector
4397 * won't appear connected or have anything
4398 * with EDID on it
4399 */
0e32b39c
DA		 4400 status = connector_status_disconnected;
4401 goto out;
7d23e3c3
SS		 4402 } else if (connector->status == connector_status_connected) {
4403 /*
4404 * If display was connected already and is still connected
4405 * check links status, there has been known issues of
4406 * link loss triggerring long pulse!!!!
4407 */
4408 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4409 intel_dp_check_link_status(intel_dp);
4410 drm_modeset_unlock(&dev->mode_config.connection_mutex);
4411 goto out;
0e32b39c
DA		 4412 }
4413
4df6960e
SS		 4414 /*
4415 * Clearing NACK and defer counts to get their exact values
4416 * while reading EDID which are required by Compliance tests
4417 * 4.2.2.4 and 4.2.2.5
4418 */
4419 intel_dp->aux.i2c_nack_count = 0;
4420 intel_dp->aux.i2c_defer_count = 0;
4421
beb60608 4422 intel_dp_set_edid(intel_dp);
5cb651a7
VS		 4423 if (is_edp(intel_dp) || intel_connector->detect_edid)
4424 status = connector_status_connected;
7d23e3c3 4425 intel_dp->detect_done = true;
c8c8fb33 4426
09b1eb13
TP		 4427 /* Try to read the source of the interrupt */
4428 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
65fbb4e7
VS		 4429 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4430 sink_irq_vector != 0) {
09b1eb13
TP		 4431 /* Clear interrupt source */
4432 drm_dp_dpcd_writeb(&intel_dp->aux,
4433 DP_DEVICE_SERVICE_IRQ_VECTOR,
4434 sink_irq_vector);
4435
4436 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4437 intel_dp_handle_test_request(intel_dp);
4438 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4439 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4440 }
4441
c8c8fb33 4442out:
5cb651a7 4443 if (status != connector_status_connected && !intel_dp->is_mst)
f21a2198 4444 intel_dp_unset_edid(intel_dp);
7d23e3c3 4445
25f78f58 4446 intel_display_power_put(to_i915(dev), power_domain);
5cb651a7 4447 return status;
f21a2198
SS		 4448}
4449
4450static enum drm_connector_status
4451intel_dp_detect(struct drm_connector *connector, bool force)
4452{
4453 struct intel_dp *intel_dp = intel_attached_dp(connector);
4454 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4455 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5cb651a7 4456 enum drm_connector_status status = connector->status;
f21a2198
SS		 4457
4458 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4459 connector->base.id, connector->name);
4460
4461 if (intel_dp->is_mst) {
4462 /* MST devices are disconnected from a monitor POV */
4463 intel_dp_unset_edid(intel_dp);
4464 if (intel_encoder->type != INTEL_OUTPUT_EDP)
cca0502b 4465 intel_encoder->type = INTEL_OUTPUT_DP;
f21a2198
SS		 4466 return connector_status_disconnected;
4467 }
4468
7d23e3c3
SS		 4469 /* If full detect is not performed yet, do a full detect */
4470 if (!intel_dp->detect_done)
5cb651a7 4471 status = intel_dp_long_pulse(intel_dp->attached_connector);
7d23e3c3
SS		 4472
4473 intel_dp->detect_done = false;
f21a2198 4474
5cb651a7 4475 return status;
a4fc5ed6
KP		 4476}
4477
beb60608
CW		 4478static void
4479intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4480{
df0e9248 4481 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4482 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
25f78f58 4483 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
671dedd2 4484 enum intel_display_power_domain power_domain;
a4fc5ed6 4485
beb60608
CW		 4486 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4487 connector->base.id, connector->name);
4488 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4489
beb60608
CW		 4490 if (connector->status != connector_status_connected)
4491 return;
671dedd2 4492
25f78f58
VS		 4493 power_domain = intel_display_port_aux_power_domain(intel_encoder);
4494 intel_display_power_get(dev_priv, power_domain);
beb60608
CW		 4495
4496 intel_dp_set_edid(intel_dp);
4497
25f78f58 4498 intel_display_power_put(dev_priv, power_domain);
beb60608
CW		 4499
4500 if (intel_encoder->type != INTEL_OUTPUT_EDP)
cca0502b 4501 intel_encoder->type = INTEL_OUTPUT_DP;
beb60608
CW		 4502}
4503
4504static int intel_dp_get_modes(struct drm_connector *connector)
4505{
4506 struct intel_connector *intel_connector = to_intel_connector(connector);
4507 struct edid *edid;
4508
4509 edid = intel_connector->detect_edid;
4510 if (edid) {
4511 int ret = intel_connector_update_modes(connector, edid);
4512 if (ret)
4513 return ret;
4514 }
32f9d658 4515
f8779fda 4516 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4517 if (is_edp(intel_attached_dp(connector)) &&
4518 intel_connector->panel.fixed_mode) {
f8779fda 4519 struct drm_display_mode *mode;
beb60608
CW		 4520
4521 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4522 intel_connector->panel.fixed_mode);
f8779fda 4523 if (mode) {
32f9d658
ZW		 4524 drm_mode_probed_add(connector, mode);
4525 return 1;
4526 }
4527 }
beb60608 4528
32f9d658 4529 return 0;
a4fc5ed6
KP		 4530}
4531
1aad7ac0
CW		 4532static bool
4533intel_dp_detect_audio(struct drm_connector *connector)
4534{
1aad7ac0 4535 bool has_audio = false;
beb60608 4536 struct edid *edid;
1aad7ac0 4537
beb60608
CW		 4538 edid = to_intel_connector(connector)->detect_edid;
4539 if (edid)
1aad7ac0 4540 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4541
1aad7ac0
CW		 4542 return has_audio;
4543}
4544
f684960e
CW		 4545static int
4546intel_dp_set_property(struct drm_connector *connector,
4547 struct drm_property *property,
4548 uint64_t val)
4549{
fac5e23e 4550 struct drm_i915_private *dev_priv = to_i915(connector->dev);
53b41837 4551 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4552 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4553 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4554 int ret;
4555
662595df 4556 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4557 if (ret)
4558 return ret;
4559
3f43c48d 4560 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4561 int i = val;
4562 bool has_audio;
4563
4564 if (i == intel_dp->force_audio)
f684960e
CW		 4565 return 0;
4566
1aad7ac0 4567 intel_dp->force_audio = i;
f684960e 4568
c3e5f67b 4569 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4570 has_audio = intel_dp_detect_audio(connector);
4571 else
c3e5f67b 4572 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4573
4574 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4575 return 0;
4576
1aad7ac0 4577 intel_dp->has_audio = has_audio;
f684960e
CW		 4578 goto done;
4579 }
4580
e953fd7b 4581 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80 4582 bool old_auto = intel_dp->color_range_auto;
0f2a2a75 4583 bool old_range = intel_dp->limited_color_range;
ae4edb80 4584
55bc60db
VS		 4585 switch (val) {
4586 case INTEL_BROADCAST_RGB_AUTO:
4587 intel_dp->color_range_auto = true;
4588 break;
4589 case INTEL_BROADCAST_RGB_FULL:
4590 intel_dp->color_range_auto = false;
0f2a2a75 4591 intel_dp->limited_color_range = false;
55bc60db
VS		 4592 break;
4593 case INTEL_BROADCAST_RGB_LIMITED:
4594 intel_dp->color_range_auto = false;
0f2a2a75 4595 intel_dp->limited_color_range = true;
55bc60db
VS		 4596 break;
4597 default:
4598 return -EINVAL;
4599 }
ae4edb80
DV		 4600
4601 if (old_auto == intel_dp->color_range_auto &&
0f2a2a75 4602 old_range == intel_dp->limited_color_range)
ae4edb80
DV		 4603 return 0;
4604
e953fd7b
CW		 4605 goto done;
4606 }
4607
53b41837
YN		 4608 if (is_edp(intel_dp) &&
4609 property == connector->dev->mode_config.scaling_mode_property) {
4610 if (val == DRM_MODE_SCALE_NONE) {
4611 DRM_DEBUG_KMS("no scaling not supported\n");
4612 return -EINVAL;
4613 }
234126c6
VS		 4614 if (HAS_GMCH_DISPLAY(dev_priv) &&
4615 val == DRM_MODE_SCALE_CENTER) {
4616 DRM_DEBUG_KMS("centering not supported\n");
4617 return -EINVAL;
4618 }
53b41837
YN		 4619
4620 if (intel_connector->panel.fitting_mode == val) {
4621 /* the eDP scaling property is not changed */
4622 return 0;
4623 }
4624 intel_connector->panel.fitting_mode = val;
4625
4626 goto done;
4627 }
4628
f684960e
CW		 4629 return -EINVAL;
4630
4631done:
c0c36b94
CW		 4632 if (intel_encoder->base.crtc)
4633 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4634
4635 return 0;
4636}
4637
7a418e34
CW		 4638static int
4639intel_dp_connector_register(struct drm_connector *connector)
4640{
4641 struct intel_dp *intel_dp = intel_attached_dp(connector);
1ebaa0b9
CW		 4642 int ret;
4643
4644 ret = intel_connector_register(connector);
4645 if (ret)
4646 return ret;
7a418e34
CW		 4647
4648 i915_debugfs_connector_add(connector);
4649
4650 DRM_DEBUG_KMS("registering %s bus for %s\n",
4651 intel_dp->aux.name, connector->kdev->kobj.name);
4652
4653 intel_dp->aux.dev = connector->kdev;
4654 return drm_dp_aux_register(&intel_dp->aux);
4655}
4656
c191eca1
CW		 4657static void
4658intel_dp_connector_unregister(struct drm_connector *connector)
4659{
4660 drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4661 intel_connector_unregister(connector);
4662}
4663
a4fc5ed6 4664static void
73845adf 4665intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4666{
1d508706 4667 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4668
10e972d3 4669 kfree(intel_connector->detect_edid);
beb60608 4670
9cd300e0
JN		 4671 if (!IS_ERR_OR_NULL(intel_connector->edid))
4672 kfree(intel_connector->edid);
4673
acd8db10
PZ		 4674 /* Can't call is_edp() since the encoder may have been destroyed
4675 * already. */
4676 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4677 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4678
a4fc5ed6 4679 drm_connector_cleanup(connector);
55f78c43 4680 kfree(connector);
a4fc5ed6
KP		 4681}
4682
00c09d70 4683void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4684{
da63a9f2
PZ		 4685 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4686 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4687
0e32b39c 4688 intel_dp_mst_encoder_cleanup(intel_dig_port);
bd943159
KP		 4689 if (is_edp(intel_dp)) {
4690 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4691 /*
4692 * vdd might still be enabled do to the delayed vdd off.
4693 * Make sure vdd is actually turned off here.
4694 */
773538e8 4695 pps_lock(intel_dp);
4be73780 4696 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4697 pps_unlock(intel_dp);
4698
01527b31
CT		 4699 if (intel_dp->edp_notifier.notifier_call) {
4700 unregister_reboot_notifier(&intel_dp->edp_notifier);
4701 intel_dp->edp_notifier.notifier_call = NULL;
4702 }
bd943159 4703 }
99681886
CW		 4704
4705 intel_dp_aux_fini(intel_dp);
4706
c8bd0e49 4707 drm_encoder_cleanup(encoder);
da63a9f2 4708 kfree(intel_dig_port);
24d05927
DV		 4709}
4710
bf93ba67 4711void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
07f9cd0b
ID		 4712{
4713 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4714
4715 if (!is_edp(intel_dp))
4716 return;
4717
951468f3
VS		 4718 /*
4719 * vdd might still be enabled do to the delayed vdd off.
4720 * Make sure vdd is actually turned off here.
4721 */
afa4e53a 4722 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
773538e8 4723 pps_lock(intel_dp);
07f9cd0b 4724 edp_panel_vdd_off_sync(intel_dp);
773538e8 4725 pps_unlock(intel_dp);
07f9cd0b
ID		 4726}
4727
49e6bc51
VS		 4728static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4729{
4730 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4731 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 4732 struct drm_i915_private *dev_priv = to_i915(dev);
49e6bc51
VS		 4733 enum intel_display_power_domain power_domain;
4734
4735 lockdep_assert_held(&dev_priv->pps_mutex);
4736
4737 if (!edp_have_panel_vdd(intel_dp))
4738 return;
4739
4740 /*
4741 * The VDD bit needs a power domain reference, so if the bit is
4742 * already enabled when we boot or resume, grab this reference and
4743 * schedule a vdd off, so we don't hold on to the reference
4744 * indefinitely.
4745 */
4746 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
25f78f58 4747 power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
49e6bc51
VS		 4748 intel_display_power_get(dev_priv, power_domain);
4749
4750 edp_panel_vdd_schedule_off(intel_dp);
4751}
4752
bf93ba67 4753void intel_dp_encoder_reset(struct drm_encoder *encoder)
6d93c0c4 4754{
64989ca4
VS		 4755 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
4756 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4757
4758 if (!HAS_DDI(dev_priv))
4759 intel_dp->DP = I915_READ(intel_dp->output_reg);
49e6bc51
VS		 4760
4761 if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4762 return;
4763
49e6bc51
VS		 4764 pps_lock(intel_dp);
4765
335f752b
ID		 4766 /* Reinit the power sequencer, in case BIOS did something with it. */
4767 intel_dp_pps_init(encoder->dev, intel_dp);
49e6bc51
VS		 4768 intel_edp_panel_vdd_sanitize(intel_dp);
4769
4770 pps_unlock(intel_dp);
6d93c0c4
ID		 4771}
4772
a4fc5ed6 4773static const struct drm_connector_funcs intel_dp_connector_funcs = {
4d688a2a 4774 .dpms = drm_atomic_helper_connector_dpms,
a4fc5ed6 4775 .detect = intel_dp_detect,
beb60608 4776 .force = intel_dp_force,
a4fc5ed6 4777 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4778 .set_property = intel_dp_set_property,
2545e4a6 4779 .atomic_get_property = intel_connector_atomic_get_property,
7a418e34 4780 .late_register = intel_dp_connector_register,
c191eca1 4781 .early_unregister = intel_dp_connector_unregister,
73845adf 4782 .destroy = intel_dp_connector_destroy,
c6f95f27 4783 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 4784 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
a4fc5ed6
KP		 4785};
4786
4787static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4788 .get_modes = intel_dp_get_modes,
4789 .mode_valid = intel_dp_mode_valid,
a4fc5ed6
KP		 4790};
4791
a4fc5ed6 4792static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4793 .reset = intel_dp_encoder_reset,
24d05927 4794 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4795};
4796
b2c5c181 4797enum irqreturn
13cf5504
DA		 4798intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4799{
4800 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4801 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c 4802 struct drm_device *dev = intel_dig_port->base.base.dev;
fac5e23e 4803 struct drm_i915_private *dev_priv = to_i915(dev);
1c767b33 4804 enum intel_display_power_domain power_domain;
b2c5c181 4805 enum irqreturn ret = IRQ_NONE;
1c767b33 4806
2540058f
TI		 4807 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4808 intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
cca0502b 4809 intel_dig_port->base.type = INTEL_OUTPUT_DP;
13cf5504 4810
7a7f84cc
VS		 4811 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
4812 /*
4813 * vdd off can generate a long pulse on eDP which
4814 * would require vdd on to handle it, and thus we
4815 * would end up in an endless cycle of
4816 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
4817 */
4818 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
4819 port_name(intel_dig_port->port));
a8b3d52f 4820 return IRQ_HANDLED;
7a7f84cc
VS		 4821 }
4822
26fbb774
VS		 4823 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4824 port_name(intel_dig_port->port),
0e32b39c 4825 long_hpd ? "long" : "short");
13cf5504 4826
27d4efc5
VS		 4827 if (long_hpd) {
4828 intel_dp->detect_done = false;
4829 return IRQ_NONE;
4830 }
4831
25f78f58 4832 power_domain = intel_display_port_aux_power_domain(intel_encoder);
1c767b33
ID		 4833 intel_display_power_get(dev_priv, power_domain);
4834
27d4efc5
VS		 4835 if (intel_dp->is_mst) {
4836 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
4837 /*
4838 * If we were in MST mode, and device is not
4839 * there, get out of MST mode
4840 */
4841 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4842 intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4843 intel_dp->is_mst = false;
4844 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4845 intel_dp->is_mst);
4846 intel_dp->detect_done = false;
4847 goto put_power;
0e32b39c 4848 }
27d4efc5 4849 }
0e32b39c 4850
27d4efc5
VS		 4851 if (!intel_dp->is_mst) {
4852 if (!intel_dp_short_pulse(intel_dp)) {
4853 intel_dp->detect_done = false;
4854 goto put_power;
39ff747b 4855 }
0e32b39c 4856 }
b2c5c181
DV		 4857
4858 ret = IRQ_HANDLED;
4859
1c767b33
ID		 4860put_power:
4861 intel_display_power_put(dev_priv, power_domain);
4862
4863 return ret;
13cf5504
DA		 4864}
4865
477ec328 4866/* check the VBT to see whether the eDP is on another port */
5d8a7752 4867bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18 4868{
fac5e23e 4869 struct drm_i915_private *dev_priv = to_i915(dev);
36e83a18 4870
53ce81a7
VS		 4871 /*
4872 * eDP not supported on g4x. so bail out early just
4873 * for a bit extra safety in case the VBT is bonkers.
4874 */
4875 if (INTEL_INFO(dev)->gen < 5)
4876 return false;
4877
3b32a35b
VS		 4878 if (port == PORT_A)
4879 return true;
4880
951d9efe 4881 return intel_bios_is_port_edp(dev_priv, port);
36e83a18
ZY		 4882}
4883
0e32b39c 4884void
f684960e
CW		 4885intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4886{
53b41837
YN		 4887 struct intel_connector *intel_connector = to_intel_connector(connector);
4888
3f43c48d 4889 intel_attach_force_audio_property(connector);
e953fd7b 4890 intel_attach_broadcast_rgb_property(connector);
55bc60db 4891 intel_dp->color_range_auto = true;
53b41837
YN		 4892
4893 if (is_edp(intel_dp)) {
4894 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4895 drm_object_attach_property(
4896 &connector->base,
53b41837 4897 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4898 DRM_MODE_SCALE_ASPECT);
4899 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4900 }
f684960e
CW		 4901}
4902
dada1a9f
ID		 4903static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4904{
d28d4731 4905 intel_dp->panel_power_off_time = ktime_get_boottime();
dada1a9f
ID		 4906 intel_dp->last_power_on = jiffies;
4907 intel_dp->last_backlight_off = jiffies;
4908}
4909
67a54566 4910static void
54648618
ID		 4911intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
4912 struct intel_dp *intel_dp, struct edp_power_seq *seq)
67a54566 4913{
b0a08bec 4914 u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
8e8232d5 4915 struct pps_registers regs;
453c5420 4916
8e8232d5 4917 intel_pps_get_registers(dev_priv, intel_dp, &regs);
67a54566
DV		 4918
4919 /* Workaround: Need to write PP_CONTROL with the unlock key as
4920 * the very first thing. */
b0a08bec 4921 pp_ctl = ironlake_get_pp_control(intel_dp);
67a54566 4922
8e8232d5
ID		 4923 pp_on = I915_READ(regs.pp_on);
4924 pp_off = I915_READ(regs.pp_off);
54648618 4925 if (!IS_BROXTON(dev_priv)) {
8e8232d5
ID		 4926 I915_WRITE(regs.pp_ctrl, pp_ctl);
4927 pp_div = I915_READ(regs.pp_div);
b0a08bec 4928 }
67a54566
DV		 4929
4930 /* Pull timing values out of registers */
54648618
ID		 4931 seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4932 PANEL_POWER_UP_DELAY_SHIFT;
67a54566 4933
54648618
ID		 4934 seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4935 PANEL_LIGHT_ON_DELAY_SHIFT;
67a54566 4936
54648618
ID		 4937 seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4938 PANEL_LIGHT_OFF_DELAY_SHIFT;
67a54566 4939
54648618
ID		 4940 seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4941 PANEL_POWER_DOWN_DELAY_SHIFT;
67a54566 4942
54648618 4943 if (IS_BROXTON(dev_priv)) {
b0a08bec
VK		 4944 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
4945 BXT_POWER_CYCLE_DELAY_SHIFT;
4946 if (tmp > 0)
54648618 4947 seq->t11_t12 = (tmp - 1) * 1000;
b0a08bec 4948 else
54648618 4949 seq->t11_t12 = 0;
b0a08bec 4950 } else {
54648618 4951 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
67a54566 4952 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
b0a08bec 4953 }
54648618
ID		 4954}
4955
de9c1b6b
ID		 4956static void
4957intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
4958{
4959 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4960 state_name,
4961 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
4962}
4963
4964static void
4965intel_pps_verify_state(struct drm_i915_private *dev_priv,
4966 struct intel_dp *intel_dp)
4967{
4968 struct edp_power_seq hw;
4969 struct edp_power_seq *sw = &intel_dp->pps_delays;
4970
4971 intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
4972
4973 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
4974 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
4975 DRM_ERROR("PPS state mismatch\n");
4976 intel_pps_dump_state("sw", sw);
4977 intel_pps_dump_state("hw", &hw);
4978 }
4979}
4980
54648618
ID		 4981static void
4982intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4983 struct intel_dp *intel_dp)
4984{
fac5e23e 4985 struct drm_i915_private *dev_priv = to_i915(dev);
54648618
ID		 4986 struct edp_power_seq cur, vbt, spec,
4987 *final = &intel_dp->pps_delays;
4988
4989 lockdep_assert_held(&dev_priv->pps_mutex);
4990
4991 /* already initialized? */
4992 if (final->t11_t12 != 0)
4993 return;
4994
4995 intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
67a54566 4996
de9c1b6b 4997 intel_pps_dump_state("cur", &cur);
67a54566 4998
6aa23e65 4999 vbt = dev_priv->vbt.edp.pps;
67a54566
DV		 5000
5001 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5002 * our hw here, which are all in 100usec. */
5003 spec.t1_t3 = 210 * 10;
5004 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5005 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5006 spec.t10 = 500 * 10;
5007 /* This one is special and actually in units of 100ms, but zero
5008 * based in the hw (so we need to add 100 ms). But the sw vbt
5009 * table multiplies it with 1000 to make it in units of 100usec,
5010 * too. */
5011 spec.t11_t12 = (510 + 100) * 10;
5012
de9c1b6b 5013 intel_pps_dump_state("vbt", &vbt);
67a54566
DV		 5014
5015 /* Use the max of the register settings and vbt. If both are
5016 * unset, fall back to the spec limits. */
36b5f425 5017#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 5018 spec.field : \
5019 max(cur.field, vbt.field))
5020 assign_final(t1_t3);
5021 assign_final(t8);
5022 assign_final(t9);
5023 assign_final(t10);
5024 assign_final(t11_t12);
5025#undef assign_final
5026
36b5f425 5027#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 5028 intel_dp->panel_power_up_delay = get_delay(t1_t3);
5029 intel_dp->backlight_on_delay = get_delay(t8);
5030 intel_dp->backlight_off_delay = get_delay(t9);
5031 intel_dp->panel_power_down_delay = get_delay(t10);
5032 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5033#undef get_delay
5034
f30d26e4
JN		 5035 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5036 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5037 intel_dp->panel_power_cycle_delay);
5038
5039 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5040 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
de9c1b6b
ID		 5041
5042 /*
5043 * We override the HW backlight delays to 1 because we do manual waits
5044 * on them. For T8, even BSpec recommends doing it. For T9, if we
5045 * don't do this, we'll end up waiting for the backlight off delay
5046 * twice: once when we do the manual sleep, and once when we disable
5047 * the panel and wait for the PP_STATUS bit to become zero.
5048 */
5049 final->t8 = 1;
5050 final->t9 = 1;
f30d26e4
JN		 5051}
5052
5053static void
5054intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 5055 struct intel_dp *intel_dp)
f30d26e4 5056{
fac5e23e 5057 struct drm_i915_private *dev_priv = to_i915(dev);
453c5420 5058 u32 pp_on, pp_off, pp_div, port_sel = 0;
e7dc33f3 5059 int div = dev_priv->rawclk_freq / 1000;
8e8232d5 5060 struct pps_registers regs;
ad933b56 5061 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 5062 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 5063
e39b999a 5064 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420 5065
8e8232d5 5066 intel_pps_get_registers(dev_priv, intel_dp, &regs);
453c5420 5067
f30d26e4 5068 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
de9c1b6b
ID		 5069 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5070 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 5071 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 5072 /* Compute the divisor for the pp clock, simply match the Bspec
5073 * formula. */
b0a08bec 5074 if (IS_BROXTON(dev)) {
8e8232d5 5075 pp_div = I915_READ(regs.pp_ctrl);
b0a08bec
VK		 5076 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5077 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5078 << BXT_POWER_CYCLE_DELAY_SHIFT);
5079 } else {
5080 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5081 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5082 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5083 }
67a54566
DV		 5084
5085 /* Haswell doesn't have any port selection bits for the panel
5086 * power sequencer any more. */
666a4537 5087 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
ad933b56 5088 port_sel = PANEL_PORT_SELECT_VLV(port);
6e266956 5089 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
ad933b56 5090 if (port == PORT_A)
a24c144c 5091 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 5092 else
a24c144c 5093 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 5094 }
5095
453c5420
JB		 5096 pp_on |= port_sel;
5097
8e8232d5
ID		 5098 I915_WRITE(regs.pp_on, pp_on);
5099 I915_WRITE(regs.pp_off, pp_off);
b0a08bec 5100 if (IS_BROXTON(dev))
8e8232d5 5101 I915_WRITE(regs.pp_ctrl, pp_div);
b0a08bec 5102 else
8e8232d5 5103 I915_WRITE(regs.pp_div, pp_div);
67a54566 5104
67a54566 5105 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
8e8232d5
ID		 5106 I915_READ(regs.pp_on),
5107 I915_READ(regs.pp_off),
b0a08bec 5108 IS_BROXTON(dev) ?
8e8232d5
ID		 5109 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5110 I915_READ(regs.pp_div));
f684960e
CW		 5111}
5112
335f752b
ID		 5113static void intel_dp_pps_init(struct drm_device *dev,
5114 struct intel_dp *intel_dp)
5115{
5116 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5117 vlv_initial_power_sequencer_setup(intel_dp);
5118 } else {
5119 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5120 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5121 }
5122}
5123
b33a2815
VK		 5124/**
5125 * intel_dp_set_drrs_state - program registers for RR switch to take effect
5423adf1 5126 * @dev_priv: i915 device
e896402c 5127 * @crtc_state: a pointer to the active intel_crtc_state
b33a2815
VK		 5128 * @refresh_rate: RR to be programmed
5129 *
5130 * This function gets called when refresh rate (RR) has to be changed from
5131 * one frequency to another. Switches can be between high and low RR
5132 * supported by the panel or to any other RR based on media playback (in
5133 * this case, RR value needs to be passed from user space).
5134 *
5135 * The caller of this function needs to take a lock on dev_priv->drrs.
5136 */
85cb48a1
ML		 5137static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5138 struct intel_crtc_state *crtc_state,
5139 int refresh_rate)
439d7ac0 5140{
439d7ac0 5141 struct intel_encoder *encoder;
96178eeb
VK		 5142 struct intel_digital_port *dig_port = NULL;
5143 struct intel_dp *intel_dp = dev_priv->drrs.dp;
85cb48a1 5144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
96178eeb 5145 enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
439d7ac0
PB		 5146
5147 if (refresh_rate <= 0) {
5148 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5149 return;
5150 }
5151
96178eeb
VK		 5152 if (intel_dp == NULL) {
5153 DRM_DEBUG_KMS("DRRS not supported.\n");
439d7ac0
PB		 5154 return;
5155 }
5156
1fcc9d1c 5157 /*
e4d59f6b
RV		 5158 * FIXME: This needs proper synchronization with psr state for some
5159 * platforms that cannot have PSR and DRRS enabled at the same time.
1fcc9d1c 5160 */
439d7ac0 5161
96178eeb
VK		 5162 dig_port = dp_to_dig_port(intel_dp);
5163 encoder = &dig_port->base;
723f9aab 5164 intel_crtc = to_intel_crtc(encoder->base.crtc);
439d7ac0
PB		 5165
5166 if (!intel_crtc) {
5167 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5168 return;
5169 }
5170
96178eeb 5171 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
439d7ac0
PB		 5172 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5173 return;
5174 }
5175
96178eeb
VK		 5176 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5177 refresh_rate)
439d7ac0
PB		 5178 index = DRRS_LOW_RR;
5179
96178eeb 5180 if (index == dev_priv->drrs.refresh_rate_type) {
439d7ac0
PB		 5181 DRM_DEBUG_KMS(
5182 "DRRS requested for previously set RR...ignoring\n");
5183 return;
5184 }
5185
85cb48a1 5186 if (!crtc_state->base.active) {
439d7ac0
PB		 5187 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5188 return;
5189 }
5190
85cb48a1 5191 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
a4c30b1d
VK		 5192 switch (index) {
5193 case DRRS_HIGH_RR:
5194 intel_dp_set_m_n(intel_crtc, M1_N1);
5195 break;
5196 case DRRS_LOW_RR:
5197 intel_dp_set_m_n(intel_crtc, M2_N2);
5198 break;
5199 case DRRS_MAX_RR:
5200 default:
5201 DRM_ERROR("Unsupported refreshrate type\n");
5202 }
85cb48a1
ML		 5203 } else if (INTEL_GEN(dev_priv) > 6) {
5204 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
649636ef 5205 u32 val;
a4c30b1d 5206
649636ef 5207 val = I915_READ(reg);
439d7ac0 5208 if (index > DRRS_HIGH_RR) {
85cb48a1 5209 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6fa7aec1
VK		 5210 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5211 else
5212 val |= PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0 5213 } else {
85cb48a1 5214 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6fa7aec1
VK		 5215 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5216 else
5217 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
439d7ac0
PB		 5218 }
5219 I915_WRITE(reg, val);
5220 }
5221
4e9ac947
VK		 5222 dev_priv->drrs.refresh_rate_type = index;
5223
5224 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5225}
5226
b33a2815
VK		 5227/**
5228 * intel_edp_drrs_enable - init drrs struct if supported
5229 * @intel_dp: DP struct
5423adf1 5230 * @crtc_state: A pointer to the active crtc state.
b33a2815
VK		 5231 *
5232 * Initializes frontbuffer_bits and drrs.dp
5233 */
85cb48a1
ML		 5234void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5235 struct intel_crtc_state *crtc_state)
c395578e
VK		 5236{
5237 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 5238 struct drm_i915_private *dev_priv = to_i915(dev);
c395578e 5239
85cb48a1 5240 if (!crtc_state->has_drrs) {
c395578e
VK		 5241 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5242 return;
5243 }
5244
5245 mutex_lock(&dev_priv->drrs.mutex);
5246 if (WARN_ON(dev_priv->drrs.dp)) {
5247 DRM_ERROR("DRRS already enabled\n");
5248 goto unlock;
5249 }
5250
5251 dev_priv->drrs.busy_frontbuffer_bits = 0;
5252
5253 dev_priv->drrs.dp = intel_dp;
5254
5255unlock:
5256 mutex_unlock(&dev_priv->drrs.mutex);
5257}
5258
b33a2815
VK		 5259/**
5260 * intel_edp_drrs_disable - Disable DRRS
5261 * @intel_dp: DP struct
5423adf1 5262 * @old_crtc_state: Pointer to old crtc_state.
b33a2815
VK		 5263 *
5264 */
85cb48a1
ML		 5265void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5266 struct intel_crtc_state *old_crtc_state)
c395578e
VK		 5267{
5268 struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e 5269 struct drm_i915_private *dev_priv = to_i915(dev);
c395578e 5270
85cb48a1 5271 if (!old_crtc_state->has_drrs)
c395578e
VK		 5272 return;
5273
5274 mutex_lock(&dev_priv->drrs.mutex);
5275 if (!dev_priv->drrs.dp) {
5276 mutex_unlock(&dev_priv->drrs.mutex);
5277 return;
5278 }
5279
5280 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
85cb48a1
ML		 5281 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5282 intel_dp->attached_connector->panel.fixed_mode->vrefresh);
c395578e
VK		 5283
5284 dev_priv->drrs.dp = NULL;
5285 mutex_unlock(&dev_priv->drrs.mutex);
5286
5287 cancel_delayed_work_sync(&dev_priv->drrs.work);
5288}
5289
4e9ac947
VK		 5290static void intel_edp_drrs_downclock_work(struct work_struct *work)
5291{
5292 struct drm_i915_private *dev_priv =
5293 container_of(work, typeof(*dev_priv), drrs.work.work);
5294 struct intel_dp *intel_dp;
5295
5296 mutex_lock(&dev_priv->drrs.mutex);
5297
5298 intel_dp = dev_priv->drrs.dp;
5299
5300 if (!intel_dp)
5301 goto unlock;
5302
439d7ac0 5303 /*
4e9ac947
VK		 5304 * The delayed work can race with an invalidate hence we need to
5305 * recheck.
439d7ac0
PB		 5306 */
5307
4e9ac947
VK		 5308 if (dev_priv->drrs.busy_frontbuffer_bits)
5309 goto unlock;
439d7ac0 5310
85cb48a1
ML		 5311 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5312 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5313
5314 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5315 intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5316 }
439d7ac0 5317
4e9ac947 5318unlock:
4e9ac947 5319 mutex_unlock(&dev_priv->drrs.mutex);
439d7ac0
PB		 5320}
5321
b33a2815 5322/**
0ddfd203 5323 * intel_edp_drrs_invalidate - Disable Idleness DRRS
5748b6a1 5324 * @dev_priv: i915 device
b33a2815
VK		 5325 * @frontbuffer_bits: frontbuffer plane tracking bits
5326 *
0ddfd203
R		 5327 * This function gets called everytime rendering on the given planes start.
5328 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
b33a2815
VK		 5329 *
5330 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5331 */
5748b6a1
CW		 5332void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5333 unsigned int frontbuffer_bits)
a93fad0f 5334{
a93fad0f
VK		 5335 struct drm_crtc *crtc;
5336 enum pipe pipe;
5337
9da7d693 5338 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5339 return;
5340
88f933a8 5341 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5342
a93fad0f 5343 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5344 if (!dev_priv->drrs.dp) {
5345 mutex_unlock(&dev_priv->drrs.mutex);
5346 return;
5347 }
5348
a93fad0f
VK		 5349 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5350 pipe = to_intel_crtc(crtc)->pipe;
5351
c1d038c6
DV		 5352 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5353 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5354
0ddfd203 5355 /* invalidate means busy screen hence upclock */
c1d038c6 5356 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
85cb48a1
ML		 5357 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5358 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
a93fad0f 5359
a93fad0f
VK		 5360 mutex_unlock(&dev_priv->drrs.mutex);
5361}
5362
b33a2815 5363/**
0ddfd203 5364 * intel_edp_drrs_flush - Restart Idleness DRRS
5748b6a1 5365 * @dev_priv: i915 device
b33a2815
VK		 5366 * @frontbuffer_bits: frontbuffer plane tracking bits
5367 *
0ddfd203
R		 5368 * This function gets called every time rendering on the given planes has
5369 * completed or flip on a crtc is completed. So DRRS should be upclocked
5370 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5371 * if no other planes are dirty.
b33a2815
VK		 5372 *
5373 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5374 */
5748b6a1
CW		 5375void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5376 unsigned int frontbuffer_bits)
a93fad0f 5377{
a93fad0f
VK		 5378 struct drm_crtc *crtc;
5379 enum pipe pipe;
5380
9da7d693 5381 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
a93fad0f
VK		 5382 return;
5383
88f933a8 5384 cancel_delayed_work(&dev_priv->drrs.work);
3954e733 5385
a93fad0f 5386 mutex_lock(&dev_priv->drrs.mutex);
9da7d693
DV		 5387 if (!dev_priv->drrs.dp) {
5388 mutex_unlock(&dev_priv->drrs.mutex);
5389 return;
5390 }
5391
a93fad0f
VK		 5392 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5393 pipe = to_intel_crtc(crtc)->pipe;
c1d038c6
DV		 5394
5395 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
a93fad0f
VK		 5396 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5397
0ddfd203 5398 /* flush means busy screen hence upclock */
c1d038c6 5399 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
85cb48a1
ML		 5400 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5401 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
0ddfd203
R		 5402
5403 /*
5404 * flush also means no more activity hence schedule downclock, if all
5405 * other fbs are quiescent too
5406 */
5407 if (!dev_priv->drrs.busy_frontbuffer_bits)
a93fad0f
VK		 5408 schedule_delayed_work(&dev_priv->drrs.work,
5409 msecs_to_jiffies(1000));
5410 mutex_unlock(&dev_priv->drrs.mutex);
5411}
5412
b33a2815
VK		 5413/**
5414 * DOC: Display Refresh Rate Switching (DRRS)
5415 *
5416 * Display Refresh Rate Switching (DRRS) is a power conservation feature
5417 * which enables swtching between low and high refresh rates,
5418 * dynamically, based on the usage scenario. This feature is applicable
5419 * for internal panels.
5420 *
5421 * Indication that the panel supports DRRS is given by the panel EDID, which
5422 * would list multiple refresh rates for one resolution.
5423 *
5424 * DRRS is of 2 types - static and seamless.
5425 * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5426 * (may appear as a blink on screen) and is used in dock-undock scenario.
5427 * Seamless DRRS involves changing RR without any visual effect to the user
5428 * and can be used during normal system usage. This is done by programming
5429 * certain registers.
5430 *
5431 * Support for static/seamless DRRS may be indicated in the VBT based on
5432 * inputs from the panel spec.
5433 *
5434 * DRRS saves power by switching to low RR based on usage scenarios.
5435 *
2e7a5701
DV		 5436 * The implementation is based on frontbuffer tracking implementation. When
5437 * there is a disturbance on the screen triggered by user activity or a periodic
5438 * system activity, DRRS is disabled (RR is changed to high RR). When there is
5439 * no movement on screen, after a timeout of 1 second, a switch to low RR is
5440 * made.
5441 *
5442 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5443 * and intel_edp_drrs_flush() are called.
b33a2815
VK		 5444 *
5445 * DRRS can be further extended to support other internal panels and also
5446 * the scenario of video playback wherein RR is set based on the rate
5447 * requested by userspace.
5448 */
5449
5450/**
5451 * intel_dp_drrs_init - Init basic DRRS work and mutex.
5452 * @intel_connector: eDP connector
5453 * @fixed_mode: preferred mode of panel
5454 *
5455 * This function is called only once at driver load to initialize basic
5456 * DRRS stuff.
5457 *
5458 * Returns:
5459 * Downclock mode if panel supports it, else return NULL.
5460 * DRRS support is determined by the presence of downclock mode (apart
5461 * from VBT setting).
5462 */
4f9db5b5 5463static struct drm_display_mode *
96178eeb
VK		 5464intel_dp_drrs_init(struct intel_connector *intel_connector,
5465 struct drm_display_mode *fixed_mode)
4f9db5b5
PB		 5466{
5467 struct drm_connector *connector = &intel_connector->base;
96178eeb 5468 struct drm_device *dev = connector->dev;
fac5e23e 5469 struct drm_i915_private *dev_priv = to_i915(dev);
4f9db5b5
PB		 5470 struct drm_display_mode *downclock_mode = NULL;
5471
9da7d693
DV		 5472 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5473 mutex_init(&dev_priv->drrs.mutex);
5474
4f9db5b5
PB		 5475 if (INTEL_INFO(dev)->gen <= 6) {
5476 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5477 return NULL;
5478 }
5479
5480 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 5481 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5482 return NULL;
5483 }
5484
5485 downclock_mode = intel_find_panel_downclock
5486 (dev, fixed_mode, connector);
5487
5488 if (!downclock_mode) {
a1d26342 5489 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
4f9db5b5
PB		 5490 return NULL;
5491 }
5492
96178eeb 5493 dev_priv->drrs.type = dev_priv->vbt.drrs_type;
4f9db5b5 5494
96178eeb 5495 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5496 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5497 return downclock_mode;
5498}
5499
ed92f0b2 5500static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5501 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5502{
5503 struct drm_connector *connector = &intel_connector->base;
5504 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5505 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5506 struct drm_device *dev = intel_encoder->base.dev;
fac5e23e 5507 struct drm_i915_private *dev_priv = to_i915(dev);
ed92f0b2 5508 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5509 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5510 bool has_dpcd;
5511 struct drm_display_mode *scan;
5512 struct edid *edid;
6517d273 5513 enum pipe pipe = INVALID_PIPE;
ed92f0b2
PZ		 5514
5515 if (!is_edp(intel_dp))
5516 return true;
5517
97a824e1
ID		 5518 /*
5519 * On IBX/CPT we may get here with LVDS already registered. Since the
5520 * driver uses the only internal power sequencer available for both
5521 * eDP and LVDS bail out early in this case to prevent interfering
5522 * with an already powered-on LVDS power sequencer.
5523 */
5524 if (intel_get_lvds_encoder(dev)) {
5525 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5526 DRM_INFO("LVDS was detected, not registering eDP\n");
5527
5528 return false;
5529 }
5530
49e6bc51 5531 pps_lock(intel_dp);
b4d06ede
ID		 5532
5533 intel_dp_init_panel_power_timestamps(intel_dp);
335f752b 5534 intel_dp_pps_init(dev, intel_dp);
49e6bc51 5535 intel_edp_panel_vdd_sanitize(intel_dp);
b4d06ede 5536
49e6bc51 5537 pps_unlock(intel_dp);
63635217 5538
ed92f0b2 5539 /* Cache DPCD and EDID for edp. */
fe5a66f9 5540 has_dpcd = intel_edp_init_dpcd(intel_dp);
ed92f0b2 5541
fe5a66f9 5542 if (!has_dpcd) {
ed92f0b2
PZ		 5543 /* if this fails, presume the device is a ghost */
5544 DRM_INFO("failed to retrieve link info, disabling eDP\n");
b4d06ede 5545 goto out_vdd_off;
ed92f0b2
PZ		 5546 }
5547
060c8778 5548 mutex_lock(&dev->mode_config.mutex);
0b99836f 5549 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5550 if (edid) {
5551 if (drm_add_edid_modes(connector, edid)) {
5552 drm_mode_connector_update_edid_property(connector,
5553 edid);
5554 drm_edid_to_eld(connector, edid);
5555 } else {
5556 kfree(edid);
5557 edid = ERR_PTR(-EINVAL);
5558 }
5559 } else {
5560 edid = ERR_PTR(-ENOENT);
5561 }
5562 intel_connector->edid = edid;
5563
5564 /* prefer fixed mode from EDID if available */
5565 list_for_each_entry(scan, &connector->probed_modes, head) {
5566 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5567 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5 5568 downclock_mode = intel_dp_drrs_init(
4f9db5b5 5569 intel_connector, fixed_mode);
ed92f0b2
PZ		 5570 break;
5571 }
5572 }
5573
5574 /* fallback to VBT if available for eDP */
5575 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5576 fixed_mode = drm_mode_duplicate(dev,
5577 dev_priv->vbt.lfp_lvds_vbt_mode);
df457245 5578 if (fixed_mode) {
ed92f0b2 5579 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
df457245
VS		 5580 connector->display_info.width_mm = fixed_mode->width_mm;
5581 connector->display_info.height_mm = fixed_mode->height_mm;
5582 }
ed92f0b2 5583 }
060c8778 5584 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5585
666a4537 5586 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
01527b31
CT		 5587 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5588 register_reboot_notifier(&intel_dp->edp_notifier);
6517d273
VS		 5589
5590 /*
5591 * Figure out the current pipe for the initial backlight setup.
5592 * If the current pipe isn't valid, try the PPS pipe, and if that
5593 * fails just assume pipe A.
5594 */
5595 if (IS_CHERRYVIEW(dev))
5596 pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5597 else
5598 pipe = PORT_TO_PIPE(intel_dp->DP);
5599
5600 if (pipe != PIPE_A && pipe != PIPE_B)
5601 pipe = intel_dp->pps_pipe;
5602
5603 if (pipe != PIPE_A && pipe != PIPE_B)
5604 pipe = PIPE_A;
5605
5606 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5607 pipe_name(pipe));
01527b31
CT		 5608 }
5609
4f9db5b5 5610 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5507faeb 5611 intel_connector->panel.backlight.power = intel_edp_backlight_power;
6517d273 5612 intel_panel_setup_backlight(connector, pipe);
ed92f0b2
PZ		 5613
5614 return true;
b4d06ede
ID		 5615
5616out_vdd_off:
5617 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5618 /*
5619 * vdd might still be enabled do to the delayed vdd off.
5620 * Make sure vdd is actually turned off here.
5621 */
5622 pps_lock(intel_dp);
5623 edp_panel_vdd_off_sync(intel_dp);
5624 pps_unlock(intel_dp);
5625
5626 return false;
ed92f0b2
PZ		 5627}
5628
16c25533 5629bool
f0fec3f2
PZ		 5630intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5631 struct intel_connector *intel_connector)
a4fc5ed6 5632{
f0fec3f2
PZ		 5633 struct drm_connector *connector = &intel_connector->base;
5634 struct intel_dp *intel_dp = &intel_dig_port->dp;
5635 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5636 struct drm_device *dev = intel_encoder->base.dev;
fac5e23e 5637 struct drm_i915_private *dev_priv = to_i915(dev);
174edf1f 5638 enum port port = intel_dig_port->port;
7a418e34 5639 int type;
a4fc5ed6 5640
ccb1a831
VS		 5641 if (WARN(intel_dig_port->max_lanes < 1,
5642 "Not enough lanes (%d) for DP on port %c\n",
5643 intel_dig_port->max_lanes, port_name(port)))
5644 return false;
5645
a4a5d2f8
VS		 5646 intel_dp->pps_pipe = INVALID_PIPE;
5647
ec5b01dd 5648 /* intel_dp vfuncs */
b6b5e383
DL		 5649 if (INTEL_INFO(dev)->gen >= 9)
5650 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
ec5b01dd
DL		 5651 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5652 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
6e266956 5653 else if (HAS_PCH_SPLIT(dev_priv))
ec5b01dd
DL		 5654 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5655 else
6ffb1be7 5656 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
ec5b01dd 5657
b9ca5fad
DL		 5658 if (INTEL_INFO(dev)->gen >= 9)
5659 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5660 else
6ffb1be7 5661 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
153b1100 5662
4f8036a2 5663 if (HAS_DDI(dev_priv))
ad64217b
ACO		 5664 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5665
0767935e
DV		 5666 /* Preserve the current hw state. */
5667 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5668 intel_dp->attached_connector = intel_connector;
3d3dc149 5669
3b32a35b 5670 if (intel_dp_is_edp(dev, port))
b329530c 5671 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5672 else
5673 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5674
f7d24902
ID		 5675 /*
5676 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5677 * for DP the encoder type can be set by the caller to
5678 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5679 */
5680 if (type == DRM_MODE_CONNECTOR_eDP)
5681 intel_encoder->type = INTEL_OUTPUT_EDP;
5682
c17ed5b5 5683 /* eDP only on port B and/or C on vlv/chv */
666a4537
WB		 5684 if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5685 is_edp(intel_dp) && port != PORT_B && port != PORT_C))
c17ed5b5
VS		 5686 return false;
5687
e7281eab
ID		 5688 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5689 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5690 port_name(port));
5691
b329530c 5692 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5693 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5694
a4fc5ed6
KP		 5695 connector->interlace_allowed = true;
5696 connector->doublescan_allowed = 0;
5697
b6339585 5698 intel_dp_aux_init(intel_dp);
7a418e34 5699
f0fec3f2 5700 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5701 edp_panel_vdd_work);
a4fc5ed6 5702
df0e9248 5703 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6 5704
4f8036a2 5705 if (HAS_DDI(dev_priv))
bcbc889b
PZ		 5706 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5707 else
5708 intel_connector->get_hw_state = intel_connector_get_hw_state;
5709
0b99836f 5710 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5711 switch (port) {
5712 case PORT_A:
1d843f9d 5713 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5714 break;
5715 case PORT_B:
1d843f9d 5716 intel_encoder->hpd_pin = HPD_PORT_B;
e87a005d 5717 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
cf1d5883 5718 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5719 break;
5720 case PORT_C:
1d843f9d 5721 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5722 break;
5723 case PORT_D:
1d843f9d 5724 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30 5725 break;
26951caf
XZ		 5726 case PORT_E:
5727 intel_encoder->hpd_pin = HPD_PORT_E;
5728 break;
ab9d7c30 5729 default:
ad1c0b19 5730 BUG();
5eb08b69
ZW		 5731 }
5732
0e32b39c 5733 /* init MST on ports that can support it */
f8e58ddf 5734 if (HAS_DP_MST(dev) && !is_edp(intel_dp) &&
0c9b3715
JN		 5735 (port == PORT_B || port == PORT_C || port == PORT_D))
5736 intel_dp_mst_encoder_init(intel_dig_port,
5737 intel_connector->base.base.id);
0e32b39c 5738
36b5f425 5739 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
a121f4e5
VS		 5740 intel_dp_aux_fini(intel_dp);
5741 intel_dp_mst_encoder_cleanup(intel_dig_port);
5742 goto fail;
b2f246a8 5743 }
32f9d658 5744
f684960e
CW		 5745 intel_dp_add_properties(intel_dp, connector);
5746
a4fc5ed6
KP		 5747 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5748 * 0xd. Failure to do so will result in spurious interrupts being
5749 * generated on the port when a cable is not attached.
5750 */
50a0bc90 5751 if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
a4fc5ed6
KP		 5752 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5753 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5754 }
16c25533
PZ		 5755
5756 return true;
a121f4e5
VS		 5757
5758fail:
a121f4e5
VS		 5759 drm_connector_cleanup(connector);
5760
5761 return false;
a4fc5ed6 5762}
f0fec3f2 5763
457c52d8
CW		 5764bool intel_dp_init(struct drm_device *dev,
5765 i915_reg_t output_reg,
5766 enum port port)
f0fec3f2 5767{
fac5e23e 5768 struct drm_i915_private *dev_priv = to_i915(dev);
f0fec3f2
PZ		 5769 struct intel_digital_port *intel_dig_port;
5770 struct intel_encoder *intel_encoder;
5771 struct drm_encoder *encoder;
5772 struct intel_connector *intel_connector;
5773
b14c5679 5774 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2 5775 if (!intel_dig_port)
457c52d8 5776 return false;
f0fec3f2 5777
08d9bc92 5778 intel_connector = intel_connector_alloc();
11aee0f6
SM		 5779 if (!intel_connector)
5780 goto err_connector_alloc;
f0fec3f2
PZ		 5781
5782 intel_encoder = &intel_dig_port->base;
5783 encoder = &intel_encoder->base;
5784
893da0c9 5785 if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
580d8ed5 5786 DRM_MODE_ENCODER_TMDS, "DP %c", port_name(port)))
893da0c9 5787 goto err_encoder_init;
f0fec3f2 5788
5bfe2ac0 5789 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5790 intel_encoder->disable = intel_disable_dp;
00c09d70 5791 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5792 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5793 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5794 if (IS_CHERRYVIEW(dev)) {
9197c88b 5795 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5796 intel_encoder->pre_enable = chv_pre_enable_dp;
5797 intel_encoder->enable = vlv_enable_dp;
580d3811 5798 intel_encoder->post_disable = chv_post_disable_dp;
d6db995f 5799 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
e4a1d846 5800 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5801 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5802 intel_encoder->pre_enable = vlv_pre_enable_dp;
5803 intel_encoder->enable = vlv_enable_dp;
49277c31 5804 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5805 } else {
ecff4f3b
JN		 5806 intel_encoder->pre_enable = g4x_pre_enable_dp;
5807 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5808 if (INTEL_INFO(dev)->gen >= 5)
5809 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5810 }
f0fec3f2 5811
174edf1f 5812 intel_dig_port->port = port;
f0fec3f2 5813 intel_dig_port->dp.output_reg = output_reg;
ccb1a831 5814 intel_dig_port->max_lanes = 4;
f0fec3f2 5815
cca0502b 5816 intel_encoder->type = INTEL_OUTPUT_DP;
882ec384
VS		 5817 if (IS_CHERRYVIEW(dev)) {
5818 if (port == PORT_D)
5819 intel_encoder->crtc_mask = 1 << 2;
5820 else
5821 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5822 } else {
5823 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5824 }
bc079e8b 5825 intel_encoder->cloneable = 0;
03cdc1d4 5826 intel_encoder->port = port;
f0fec3f2 5827
13cf5504 5828 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 5829 dev_priv->hotplug.irq_port[port] = intel_dig_port;
13cf5504 5830
11aee0f6
SM		 5831 if (!intel_dp_init_connector(intel_dig_port, intel_connector))
5832 goto err_init_connector;
5833
457c52d8 5834 return true;
11aee0f6
SM		 5835
5836err_init_connector:
5837 drm_encoder_cleanup(encoder);
893da0c9 5838err_encoder_init:
11aee0f6
SM		 5839 kfree(intel_connector);
5840err_connector_alloc:
5841 kfree(intel_dig_port);
457c52d8 5842 return false;
f0fec3f2 5843}
0e32b39c
DA		 5844
5845void intel_dp_mst_suspend(struct drm_device *dev)
5846{
fac5e23e 5847 struct drm_i915_private *dev_priv = to_i915(dev);
0e32b39c
DA		 5848 int i;
5849
5850 /* disable MST */
5851 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5852 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5aa56969
VS		 5853
5854 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
0e32b39c
DA		 5855 continue;
5856
5aa56969
VS		 5857 if (intel_dig_port->dp.is_mst)
5858 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
0e32b39c
DA		 5859 }
5860}
5861
5862void intel_dp_mst_resume(struct drm_device *dev)
5863{
fac5e23e 5864 struct drm_i915_private *dev_priv = to_i915(dev);
0e32b39c
DA		 5865 int i;
5866
5867 for (i = 0; i < I915_MAX_PORTS; i++) {
5fcece80 5868 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
5aa56969 5869 int ret;
0e32b39c 5870
5aa56969
VS		 5871 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
5872 continue;
0e32b39c 5873
5aa56969
VS		 5874 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5875 if (ret)
5876 intel_dp_check_mst_status(&intel_dig_port->dp);
0e32b39c
DA		 5877 }
5878}
ubuntu-bionic-kernel mirror