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drm/i915: shuffle panel code
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
ef9348c8
CML		 67/*
68 * CHV supports eDP 1.4 that have more link rates.
69 * Below only provides the fixed rate but exclude variable rate.
70 */
71static const struct dp_link_dpll chv_dpll[] = {
72 /*
73 * CHV requires to program fractional division for m2.
74 * m2 is stored in fixed point format using formula below
75 * (m2_int << 22) | m2_fraction
76 */
77 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
78 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
79 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
80 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
81 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
83};
84
cfcb0fc9
JB		 85/**
86 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
87 * @intel_dp: DP struct
88 *
89 * If a CPU or PCH DP output is attached to an eDP panel, this function
90 * will return true, and false otherwise.
91 */
92static bool is_edp(struct intel_dp *intel_dp)
93{
da63a9f2
PZ		 94 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
95
96 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 97}
98
68b4d824 99static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 100{
68b4d824
ID		 101 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
102
103 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 104}
105
df0e9248
CW		 106static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
107{
fa90ecef 108 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 109}
110
ea5b213a 111static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 112static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 113static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 114
a4fc5ed6 115static int
ea5b213a 116intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 117{
7183dc29 118 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 119 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 120
121 switch (max_link_bw) {
122 case DP_LINK_BW_1_62:
123 case DP_LINK_BW_2_7:
124 break;
d4eead50 125 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
06ea66b6
TP		 126 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
127 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
128 max_link_bw = DP_LINK_BW_5_4;
129 else
130 max_link_bw = DP_LINK_BW_2_7;
d4eead50 131 break;
a4fc5ed6 132 default:
d4eead50
ID		 133 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
134 max_link_bw);
a4fc5ed6
KP		 135 max_link_bw = DP_LINK_BW_1_62;
136 break;
137 }
138 return max_link_bw;
139}
140
cd9dde44
AJ		 141/*
142 * The units on the numbers in the next two are... bizarre. Examples will
143 * make it clearer; this one parallels an example in the eDP spec.
144 *
145 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
146 *
147 * 270000 * 1 * 8 / 10 == 216000
148 *
149 * The actual data capacity of that configuration is 2.16Gbit/s, so the
150 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
151 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
152 * 119000. At 18bpp that's 2142000 kilobits per second.
153 *
154 * Thus the strange-looking division by 10 in intel_dp_link_required, to
155 * get the result in decakilobits instead of kilobits.
156 */
157
a4fc5ed6 158static int
c898261c 159intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 160{
cd9dde44 161 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 162}
163
fe27d53e
DA		 164static int
165intel_dp_max_data_rate(int max_link_clock, int max_lanes)
166{
167 return (max_link_clock * max_lanes * 8) / 10;
168}
169
c19de8eb 170static enum drm_mode_status
a4fc5ed6
KP		 171intel_dp_mode_valid(struct drm_connector *connector,
172 struct drm_display_mode *mode)
173{
df0e9248 174 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 175 struct intel_connector *intel_connector = to_intel_connector(connector);
176 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 177 int target_clock = mode->clock;
178 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 179
dd06f90e
JN		 180 if (is_edp(intel_dp) && fixed_mode) {
181 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 182 return MODE_PANEL;
183
dd06f90e 184 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 185 return MODE_PANEL;
03afc4a2
DV		 186
187 target_clock = fixed_mode->clock;
7de56f43
ZY		 188 }
189
36008365
DV		 190 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
191 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
192
193 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
194 mode_rate = intel_dp_link_required(target_clock, 18);
195
196 if (mode_rate > max_rate)
c4867936 197 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 198
199 if (mode->clock < 10000)
200 return MODE_CLOCK_LOW;
201
0af78a2b
DV		 202 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
203 return MODE_H_ILLEGAL;
204
a4fc5ed6
KP		 205 return MODE_OK;
206}
207
208static uint32_t
209pack_aux(uint8_t *src, int src_bytes)
210{
211 int i;
212 uint32_t v = 0;
213
214 if (src_bytes > 4)
215 src_bytes = 4;
216 for (i = 0; i < src_bytes; i++)
217 v |= ((uint32_t) src[i]) << ((3-i) * 8);
218 return v;
219}
220
221static void
222unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
223{
224 int i;
225 if (dst_bytes > 4)
226 dst_bytes = 4;
227 for (i = 0; i < dst_bytes; i++)
228 dst[i] = src >> ((3-i) * 8);
229}
230
fb0f8fbf
KP		 231/* hrawclock is 1/4 the FSB frequency */
232static int
233intel_hrawclk(struct drm_device *dev)
234{
235 struct drm_i915_private *dev_priv = dev->dev_private;
236 uint32_t clkcfg;
237
9473c8f4
VP		 238 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
239 if (IS_VALLEYVIEW(dev))
240 return 200;
241
fb0f8fbf
KP		 242 clkcfg = I915_READ(CLKCFG);
243 switch (clkcfg & CLKCFG_FSB_MASK) {
244 case CLKCFG_FSB_400:
245 return 100;
246 case CLKCFG_FSB_533:
247 return 133;
248 case CLKCFG_FSB_667:
249 return 166;
250 case CLKCFG_FSB_800:
251 return 200;
252 case CLKCFG_FSB_1067:
253 return 266;
254 case CLKCFG_FSB_1333:
255 return 333;
256 /* these two are just a guess; one of them might be right */
257 case CLKCFG_FSB_1600:
258 case CLKCFG_FSB_1600_ALT:
259 return 400;
260 default:
261 return 133;
262 }
263}
264
bf13e81b
JN		 265static void
266intel_dp_init_panel_power_sequencer(struct drm_device *dev,
267 struct intel_dp *intel_dp,
268 struct edp_power_seq *out);
269static void
270intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
271 struct intel_dp *intel_dp,
272 struct edp_power_seq *out);
273
274static enum pipe
275vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
276{
277 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
278 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
279 struct drm_device *dev = intel_dig_port->base.base.dev;
280 struct drm_i915_private *dev_priv = dev->dev_private;
281 enum port port = intel_dig_port->port;
282 enum pipe pipe;
283
284 /* modeset should have pipe */
285 if (crtc)
286 return to_intel_crtc(crtc)->pipe;
287
288 /* init time, try to find a pipe with this port selected */
289 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
290 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
291 PANEL_PORT_SELECT_MASK;
292 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
293 return pipe;
294 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
295 return pipe;
296 }
297
298 /* shrug */
299 return PIPE_A;
300}
301
302static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
303{
304 struct drm_device *dev = intel_dp_to_dev(intel_dp);
305
306 if (HAS_PCH_SPLIT(dev))
307 return PCH_PP_CONTROL;
308 else
309 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
310}
311
312static u32 _pp_stat_reg(struct intel_dp *intel_dp)
313{
314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
315
316 if (HAS_PCH_SPLIT(dev))
317 return PCH_PP_STATUS;
318 else
319 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
320}
321
4be73780 322static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 323{
30add22d 324 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 325 struct drm_i915_private *dev_priv = dev->dev_private;
326
bf13e81b 327 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 328}
329
4be73780 330static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 331{
30add22d 332 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 333 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 334 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
335 struct intel_encoder *intel_encoder = &intel_dig_port->base;
336 enum intel_display_power_domain power_domain;
ebf33b18 337
bb4932c4
ID		 338 power_domain = intel_display_port_power_domain(intel_encoder);
339 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 340 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 341}
342
9b984dae
KP		 343static void
344intel_dp_check_edp(struct intel_dp *intel_dp)
345{
30add22d 346 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 347 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 348
9b984dae
KP		 349 if (!is_edp(intel_dp))
350 return;
453c5420 351
4be73780 352 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 353 WARN(1, "eDP powered off while attempting aux channel communication.\n");
354 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 355 I915_READ(_pp_stat_reg(intel_dp)),
356 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 357 }
358}
359
9ee32fea
DV		 360static uint32_t
361intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
362{
363 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
364 struct drm_device *dev = intel_dig_port->base.base.dev;
365 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 366 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 367 uint32_t status;
368 bool done;
369
ef04f00d 370#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 371 if (has_aux_irq)
b18ac466 372 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 373 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 374 else
375 done = wait_for_atomic(C, 10) == 0;
376 if (!done)
377 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
378 has_aux_irq);
379#undef C
380
381 return status;
382}
383
ec5b01dd 384static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 385{
174edf1f
PZ		 386 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
387 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 388
ec5b01dd
DL		 389 /*
390 * The clock divider is based off the hrawclk, and would like to run at
391 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 392 */
ec5b01dd
DL		 393 return index ? 0 : intel_hrawclk(dev) / 2;
394}
395
396static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
397{
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
400
401 if (index)
402 return 0;
403
404 if (intel_dig_port->port == PORT_A) {
405 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 406 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 407 else
b84a1cf8 408 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 409 } else {
410 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
411 }
412}
413
414static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
415{
416 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
417 struct drm_device *dev = intel_dig_port->base.base.dev;
418 struct drm_i915_private *dev_priv = dev->dev_private;
419
420 if (intel_dig_port->port == PORT_A) {
421 if (index)
422 return 0;
423 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 424 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
425 /* Workaround for non-ULT HSW */
bc86625a
CW		 426 switch (index) {
427 case 0: return 63;
428 case 1: return 72;
429 default: return 0;
430 }
ec5b01dd 431 } else {
bc86625a 432 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 433 }
b84a1cf8
RV		 434}
435
ec5b01dd
DL		 436static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
437{
438 return index ? 0 : 100;
439}
440
5ed12a19
DL		 441static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
442 bool has_aux_irq,
443 int send_bytes,
444 uint32_t aux_clock_divider)
445{
446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
447 struct drm_device *dev = intel_dig_port->base.base.dev;
448 uint32_t precharge, timeout;
449
450 if (IS_GEN6(dev))
451 precharge = 3;
452 else
453 precharge = 5;
454
455 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
456 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
457 else
458 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
459
460 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 461 DP_AUX_CH_CTL_DONE |
5ed12a19 462 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 463 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 464 timeout |
788d4433 465 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 466 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
467 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 468 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 469}
470
b84a1cf8
RV		 471static int
472intel_dp_aux_ch(struct intel_dp *intel_dp,
473 uint8_t *send, int send_bytes,
474 uint8_t *recv, int recv_size)
475{
476 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
477 struct drm_device *dev = intel_dig_port->base.base.dev;
478 struct drm_i915_private *dev_priv = dev->dev_private;
479 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
480 uint32_t ch_data = ch_ctl + 4;
bc86625a 481 uint32_t aux_clock_divider;
b84a1cf8
RV		 482 int i, ret, recv_bytes;
483 uint32_t status;
5ed12a19 484 int try, clock = 0;
4e6b788c 485 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 486 bool vdd;
487
488 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 489
490 /* dp aux is extremely sensitive to irq latency, hence request the
491 * lowest possible wakeup latency and so prevent the cpu from going into
492 * deep sleep states.
493 */
494 pm_qos_update_request(&dev_priv->pm_qos, 0);
495
496 intel_dp_check_edp(intel_dp);
5eb08b69 497
c67a470b
PZ		 498 intel_aux_display_runtime_get(dev_priv);
499
11bee43e
JB		 500 /* Try to wait for any previous AUX channel activity */
501 for (try = 0; try < 3; try++) {
ef04f00d 502 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 503 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
504 break;
505 msleep(1);
506 }
507
508 if (try == 3) {
509 WARN(1, "dp_aux_ch not started status 0x%08x\n",
510 I915_READ(ch_ctl));
9ee32fea
DV		 511 ret = -EBUSY;
512 goto out;
4f7f7b7e
CW		 513 }
514
46a5ae9f
PZ		 515 /* Only 5 data registers! */
516 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
517 ret = -E2BIG;
518 goto out;
519 }
520
ec5b01dd 521 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 522 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
523 has_aux_irq,
524 send_bytes,
525 aux_clock_divider);
5ed12a19 526
bc86625a
CW		 527 /* Must try at least 3 times according to DP spec */
528 for (try = 0; try < 5; try++) {
529 /* Load the send data into the aux channel data registers */
530 for (i = 0; i < send_bytes; i += 4)
531 I915_WRITE(ch_data + i,
532 pack_aux(send + i, send_bytes - i));
533
534 /* Send the command and wait for it to complete */
5ed12a19 535 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 536
537 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
538
539 /* Clear done status and any errors */
540 I915_WRITE(ch_ctl,
541 status |
542 DP_AUX_CH_CTL_DONE |
543 DP_AUX_CH_CTL_TIME_OUT_ERROR |
544 DP_AUX_CH_CTL_RECEIVE_ERROR);
545
546 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
547 DP_AUX_CH_CTL_RECEIVE_ERROR))
548 continue;
549 if (status & DP_AUX_CH_CTL_DONE)
550 break;
551 }
4f7f7b7e 552 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 553 break;
554 }
555
a4fc5ed6 556 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 557 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 558 ret = -EBUSY;
559 goto out;
a4fc5ed6
KP		 560 }
561
562 /* Check for timeout or receive error.
563 * Timeouts occur when the sink is not connected
564 */
a5b3da54 565 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 566 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 567 ret = -EIO;
568 goto out;
a5b3da54 569 }
1ae8c0a5
KP		 570
571 /* Timeouts occur when the device isn't connected, so they're
572 * "normal" -- don't fill the kernel log with these */
a5b3da54 573 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 574 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 575 ret = -ETIMEDOUT;
576 goto out;
a4fc5ed6
KP		 577 }
578
579 /* Unload any bytes sent back from the other side */
580 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
581 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 582 if (recv_bytes > recv_size)
583 recv_bytes = recv_size;
0206e353 584
4f7f7b7e
CW		 585 for (i = 0; i < recv_bytes; i += 4)
586 unpack_aux(I915_READ(ch_data + i),
587 recv + i, recv_bytes - i);
a4fc5ed6 588
9ee32fea
DV		 589 ret = recv_bytes;
590out:
591 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 592 intel_aux_display_runtime_put(dev_priv);
9ee32fea 593
884f19e9
JN		 594 if (vdd)
595 edp_panel_vdd_off(intel_dp, false);
596
9ee32fea 597 return ret;
a4fc5ed6
KP		 598}
599
a6c8aff0
JN		 600#define BARE_ADDRESS_SIZE 3
601#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 602static ssize_t
603intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 604{
9d1a1031
JN		 605 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
606 uint8_t txbuf[20], rxbuf[20];
607 size_t txsize, rxsize;
a4fc5ed6 608 int ret;
a4fc5ed6 609
9d1a1031
JN		 610 txbuf[0] = msg->request << 4;
611 txbuf[1] = msg->address >> 8;
612 txbuf[2] = msg->address & 0xff;
613 txbuf[3] = msg->size - 1;
46a5ae9f 614
9d1a1031
JN		 615 switch (msg->request & ~DP_AUX_I2C_MOT) {
616 case DP_AUX_NATIVE_WRITE:
617 case DP_AUX_I2C_WRITE:
a6c8aff0 618 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 619 rxsize = 1;
f51a44b9 620
9d1a1031
JN		 621 if (WARN_ON(txsize > 20))
622 return -E2BIG;
a4fc5ed6 623
9d1a1031 624 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 625
9d1a1031
JN		 626 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
627 if (ret > 0) {
628 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 629
9d1a1031
JN		 630 /* Return payload size. */
631 ret = msg->size;
632 }
633 break;
46a5ae9f 634
9d1a1031
JN		 635 case DP_AUX_NATIVE_READ:
636 case DP_AUX_I2C_READ:
a6c8aff0 637 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 638 rxsize = msg->size + 1;
a4fc5ed6 639
9d1a1031
JN		 640 if (WARN_ON(rxsize > 20))
641 return -E2BIG;
a4fc5ed6 642
9d1a1031
JN		 643 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
644 if (ret > 0) {
645 msg->reply = rxbuf[0] >> 4;
646 /*
647 * Assume happy day, and copy the data. The caller is
648 * expected to check msg->reply before touching it.
649 *
650 * Return payload size.
651 */
652 ret--;
653 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 654 }
9d1a1031
JN		 655 break;
656
657 default:
658 ret = -EINVAL;
659 break;
a4fc5ed6 660 }
f51a44b9 661
9d1a1031 662 return ret;
a4fc5ed6
KP		 663}
664
9d1a1031
JN		 665static void
666intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
667{
668 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 669 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
670 enum port port = intel_dig_port->port;
0b99836f 671 const char *name = NULL;
ab2c0672
DA		 672 int ret;
673
33ad6626
JN		 674 switch (port) {
675 case PORT_A:
676 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 677 name = "DPDDC-A";
ab2c0672 678 break;
33ad6626
JN		 679 case PORT_B:
680 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 681 name = "DPDDC-B";
ab2c0672 682 break;
33ad6626
JN		 683 case PORT_C:
684 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 685 name = "DPDDC-C";
ab2c0672 686 break;
33ad6626
JN		 687 case PORT_D:
688 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 689 name = "DPDDC-D";
33ad6626
JN		 690 break;
691 default:
692 BUG();
ab2c0672
DA		 693 }
694
33ad6626
JN		 695 if (!HAS_DDI(dev))
696 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 697
0b99836f 698 intel_dp->aux.name = name;
9d1a1031
JN		 699 intel_dp->aux.dev = dev->dev;
700 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 701
0b99836f
JN		 702 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
703 connector->base.kdev->kobj.name);
8316f337 704
0b99836f
JN		 705 ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
706 if (ret < 0) {
707 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
708 name, ret);
709 return;
ab2c0672 710 }
8a5e6aeb 711
0b99836f
JN		 712 ret = sysfs_create_link(&connector->base.kdev->kobj,
713 &intel_dp->aux.ddc.dev.kobj,
714 intel_dp->aux.ddc.dev.kobj.name);
715 if (ret < 0) {
716 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
717 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
ab2c0672 718 }
a4fc5ed6
KP		 719}
720
80f65de3
ID		 721static void
722intel_dp_connector_unregister(struct intel_connector *intel_connector)
723{
724 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
725
726 sysfs_remove_link(&intel_connector->base.kdev->kobj,
0b99836f 727 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 728 intel_connector_unregister(intel_connector);
729}
730
c6bb3538
DV		 731static void
732intel_dp_set_clock(struct intel_encoder *encoder,
733 struct intel_crtc_config *pipe_config, int link_bw)
734{
735 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 736 const struct dp_link_dpll *divisor = NULL;
737 int i, count = 0;
c6bb3538
DV		 738
739 if (IS_G4X(dev)) {
9dd4ffdf
CML		 740 divisor = gen4_dpll;
741 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 742 } else if (IS_HASWELL(dev)) {
743 /* Haswell has special-purpose DP DDI clocks. */
744 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 745 divisor = pch_dpll;
746 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 747 } else if (IS_CHERRYVIEW(dev)) {
748 divisor = chv_dpll;
749 count = ARRAY_SIZE(chv_dpll);
c6bb3538 750 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 751 divisor = vlv_dpll;
752 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 753 }
9dd4ffdf
CML		 754
755 if (divisor && count) {
756 for (i = 0; i < count; i++) {
757 if (link_bw == divisor[i].link_bw) {
758 pipe_config->dpll = divisor[i].dpll;
759 pipe_config->clock_set = true;
760 break;
761 }
762 }
c6bb3538
DV		 763 }
764}
765
439d7ac0
PB		 766static void
767intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
768{
769 struct drm_device *dev = crtc->base.dev;
770 struct drm_i915_private *dev_priv = dev->dev_private;
771 enum transcoder transcoder = crtc->config.cpu_transcoder;
772
773 I915_WRITE(PIPE_DATA_M2(transcoder),
774 TU_SIZE(m_n->tu) | m_n->gmch_m);
775 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
776 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
777 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
778}
779
00c09d70 780bool
5bfe2ac0
DV		 781intel_dp_compute_config(struct intel_encoder *encoder,
782 struct intel_crtc_config *pipe_config)
a4fc5ed6 783{
5bfe2ac0 784 struct drm_device *dev = encoder->base.dev;
36008365 785 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 786 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 787 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 788 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 789 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 790 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 791 int lane_count, clock;
397fe157 792 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
06ea66b6
TP		 793 /* Conveniently, the link BW constants become indices with a shift...*/
794 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 795 int bpp, mode_rate;
06ea66b6 796 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 797 int link_avail, link_clock;
a4fc5ed6 798
bc7d38a4 799 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 800 pipe_config->has_pch_encoder = true;
801
03afc4a2 802 pipe_config->has_dp_encoder = true;
9ed109a7 803 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 804
dd06f90e
JN		 805 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
806 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
807 adjusted_mode);
2dd24552
JB		 808 if (!HAS_PCH_SPLIT(dev))
809 intel_gmch_panel_fitting(intel_crtc, pipe_config,
810 intel_connector->panel.fitting_mode);
811 else
b074cec8
JB		 812 intel_pch_panel_fitting(intel_crtc, pipe_config,
813 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 814 }
815
cb1793ce 816 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 817 return false;
818
083f9560
DV		 819 DRM_DEBUG_KMS("DP link computation with max lane count %i "
820 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 821 max_lane_count, bws[max_clock],
822 adjusted_mode->crtc_clock);
083f9560 823
36008365
DV		 824 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
825 * bpc in between. */
3e7ca985 826 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 827 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
828 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 829 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
830 dev_priv->vbt.edp_bpp);
6da7f10d 831 bpp = dev_priv->vbt.edp_bpp;
7984211e 832 }
657445fe 833
36008365 834 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 835 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
836 bpp);
36008365 837
38aecea0
DV		 838 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
839 for (clock = 0; clock <= max_clock; clock++) {
36008365
DV		 840 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
841 link_avail = intel_dp_max_data_rate(link_clock,
842 lane_count);
843
844 if (mode_rate <= link_avail) {
845 goto found;
846 }
847 }
848 }
849 }
c4867936 850
36008365 851 return false;
3685a8f3 852
36008365 853found:
55bc60db
VS		 854 if (intel_dp->color_range_auto) {
855 /*
856 * See:
857 * CEA-861-E - 5.1 Default Encoding Parameters
858 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
859 */
18316c8c 860 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 861 intel_dp->color_range = DP_COLOR_RANGE_16_235;
862 else
863 intel_dp->color_range = 0;
864 }
865
3685a8f3 866 if (intel_dp->color_range)
50f3b016 867 pipe_config->limited_color_range = true;
a4fc5ed6 868
36008365
DV		 869 intel_dp->link_bw = bws[clock];
870 intel_dp->lane_count = lane_count;
657445fe 871 pipe_config->pipe_bpp = bpp;
ff9a6750 872 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 873
36008365
DV		 874 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
875 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 876 pipe_config->port_clock, bpp);
36008365
DV		 877 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
878 mode_rate, link_avail);
a4fc5ed6 879
03afc4a2 880 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 881 adjusted_mode->crtc_clock,
882 pipe_config->port_clock,
03afc4a2 883 &pipe_config->dp_m_n);
9d1a455b 884
439d7ac0
PB		 885 if (intel_connector->panel.downclock_mode != NULL &&
886 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
887 intel_link_compute_m_n(bpp, lane_count,
888 intel_connector->panel.downclock_mode->clock,
889 pipe_config->port_clock,
890 &pipe_config->dp_m2_n2);
891 }
892
c6bb3538
DV		 893 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
894
03afc4a2 895 return true;
a4fc5ed6
KP		 896}
897
7c62a164 898static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 899{
7c62a164
DV		 900 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
901 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
902 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 903 struct drm_i915_private *dev_priv = dev->dev_private;
904 u32 dpa_ctl;
905
ff9a6750 906 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 907 dpa_ctl = I915_READ(DP_A);
908 dpa_ctl &= ~DP_PLL_FREQ_MASK;
909
ff9a6750 910 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 911 /* For a long time we've carried around a ILK-DevA w/a for the
912 * 160MHz clock. If we're really unlucky, it's still required.
913 */
914 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 915 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 916 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 917 } else {
918 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 919 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 920 }
1ce17038 921
ea9b6006
DV		 922 I915_WRITE(DP_A, dpa_ctl);
923
924 POSTING_READ(DP_A);
925 udelay(500);
926}
927
8ac33ed3 928static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 929{
b934223d 930 struct drm_device *dev = encoder->base.dev;
417e822d 931 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 932 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 933 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 934 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
935 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 936
417e822d 937 /*
1a2eb460 938 * There are four kinds of DP registers:
417e822d
KP		 939 *
940 * IBX PCH
1a2eb460
KP		 941 * SNB CPU
942 * IVB CPU
417e822d
KP		 943 * CPT PCH
944 *
945 * IBX PCH and CPU are the same for almost everything,
946 * except that the CPU DP PLL is configured in this
947 * register
948 *
949 * CPT PCH is quite different, having many bits moved
950 * to the TRANS_DP_CTL register instead. That
951 * configuration happens (oddly) in ironlake_pch_enable
952 */
9c9e7927 953
417e822d
KP		 954 /* Preserve the BIOS-computed detected bit. This is
955 * supposed to be read-only.
956 */
957 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 958
417e822d 959 /* Handle DP bits in common between all three register formats */
417e822d 960 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 961 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 962
9ed109a7 963 if (crtc->config.has_audio) {
e0dac65e 964 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 965 pipe_name(crtc->pipe));
ea5b213a 966 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 967 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 968 }
247d89f6 969
417e822d 970 /* Split out the IBX/CPU vs CPT settings */
32f9d658 971
bc7d38a4 972 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 973 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
974 intel_dp->DP |= DP_SYNC_HS_HIGH;
975 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
976 intel_dp->DP |= DP_SYNC_VS_HIGH;
977 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
978
6aba5b6c 979 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 980 intel_dp->DP |= DP_ENHANCED_FRAMING;
981
7c62a164 982 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 983 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 984 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 985 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 986
987 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
988 intel_dp->DP |= DP_SYNC_HS_HIGH;
989 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
990 intel_dp->DP |= DP_SYNC_VS_HIGH;
991 intel_dp->DP |= DP_LINK_TRAIN_OFF;
992
6aba5b6c 993 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 994 intel_dp->DP |= DP_ENHANCED_FRAMING;
995
44f37d1f
CML		 996 if (!IS_CHERRYVIEW(dev)) {
997 if (crtc->pipe == 1)
998 intel_dp->DP |= DP_PIPEB_SELECT;
999 } else {
1000 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1001 }
417e822d
KP		 1002 } else {
1003 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1004 }
a4fc5ed6
KP		 1005}
1006
ffd6749d
PZ		 1007#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1008#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1009
1a5ef5b7
PZ		 1010#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1011#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1012
ffd6749d
PZ		 1013#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1014#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1015
4be73780 1016static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1017 u32 mask,
1018 u32 value)
bd943159 1019{
30add22d 1020 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1021 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1022 u32 pp_stat_reg, pp_ctrl_reg;
1023
bf13e81b
JN		 1024 pp_stat_reg = _pp_stat_reg(intel_dp);
1025 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1026
99ea7127 1027 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1028 mask, value,
1029 I915_READ(pp_stat_reg),
1030 I915_READ(pp_ctrl_reg));
32ce697c 1031
453c5420 1032 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1033 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1034 I915_READ(pp_stat_reg),
1035 I915_READ(pp_ctrl_reg));
32ce697c 1036 }
54c136d4
CW		 1037
1038 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1039}
32ce697c 1040
4be73780 1041static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1042{
1043 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1044 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1045}
1046
4be73780 1047static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1048{
1049 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1050 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1051}
1052
4be73780 1053static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1054{
1055 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1056
1057 /* When we disable the VDD override bit last we have to do the manual
1058 * wait. */
1059 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1060 intel_dp->panel_power_cycle_delay);
1061
4be73780 1062 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1063}
1064
4be73780 1065static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1066{
1067 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1068 intel_dp->backlight_on_delay);
1069}
1070
4be73780 1071static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1072{
1073 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1074 intel_dp->backlight_off_delay);
1075}
99ea7127 1076
832dd3c1
KP		 1077/* Read the current pp_control value, unlocking the register if it
1078 * is locked
1079 */
1080
453c5420 1081static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1082{
453c5420
JB		 1083 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1084 struct drm_i915_private *dev_priv = dev->dev_private;
1085 u32 control;
832dd3c1 1086
bf13e81b 1087 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1088 control &= ~PANEL_UNLOCK_MASK;
1089 control |= PANEL_UNLOCK_REGS;
1090 return control;
bd943159
KP		 1091}
1092
adddaaf4 1093static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1094{
30add22d 1095 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1096 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1097 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1098 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1099 enum intel_display_power_domain power_domain;
5d613501 1100 u32 pp;
453c5420 1101 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1102 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1103
97af61f5 1104 if (!is_edp(intel_dp))
adddaaf4 1105 return false;
bd943159
KP		 1106
1107 intel_dp->want_panel_vdd = true;
99ea7127 1108
4be73780 1109 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1110 return need_to_disable;
b0665d57 1111
4e6e1a54
ID		 1112 power_domain = intel_display_port_power_domain(intel_encoder);
1113 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1114
b0665d57 1115 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1116
4be73780
DV		 1117 if (!edp_have_panel_power(intel_dp))
1118 wait_panel_power_cycle(intel_dp);
99ea7127 1119
453c5420 1120 pp = ironlake_get_pp_control(intel_dp);
5d613501 1121 pp |= EDP_FORCE_VDD;
ebf33b18 1122
bf13e81b
JN		 1123 pp_stat_reg = _pp_stat_reg(intel_dp);
1124 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1125
1126 I915_WRITE(pp_ctrl_reg, pp);
1127 POSTING_READ(pp_ctrl_reg);
1128 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1129 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1130 /*
1131 * If the panel wasn't on, delay before accessing aux channel
1132 */
4be73780 1133 if (!edp_have_panel_power(intel_dp)) {
bd943159 1134 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1135 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1136 }
adddaaf4
JN		 1137
1138 return need_to_disable;
1139}
1140
b80d6c78 1141void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1142{
1143 if (is_edp(intel_dp)) {
1144 bool vdd = _edp_panel_vdd_on(intel_dp);
1145
1146 WARN(!vdd, "eDP VDD already requested on\n");
1147 }
5d613501
JB		 1148}
1149
4be73780 1150static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1151{
30add22d 1152 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1153 struct drm_i915_private *dev_priv = dev->dev_private;
1154 u32 pp;
453c5420 1155 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1156
a0e99e68
DV		 1157 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1158
4be73780 1159 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
4e6e1a54
ID		 1160 struct intel_digital_port *intel_dig_port =
1161 dp_to_dig_port(intel_dp);
1162 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1163 enum intel_display_power_domain power_domain;
1164
b0665d57
PZ		 1165 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1166
453c5420 1167 pp = ironlake_get_pp_control(intel_dp);
bd943159 1168 pp &= ~EDP_FORCE_VDD;
bd943159 1169
9f08ef59
PZ		 1170 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1171 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1172
1173 I915_WRITE(pp_ctrl_reg, pp);
1174 POSTING_READ(pp_ctrl_reg);
99ea7127 1175
453c5420
JB		 1176 /* Make sure sequencer is idle before allowing subsequent activity */
1177 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1178 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1179
1180 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1181 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1182
4e6e1a54
ID		 1183 power_domain = intel_display_port_power_domain(intel_encoder);
1184 intel_display_power_put(dev_priv, power_domain);
bd943159
KP		 1185 }
1186}
5d613501 1187
4be73780 1188static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1189{
1190 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1191 struct intel_dp, panel_vdd_work);
30add22d 1192 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1193
627f7675 1194 mutex_lock(&dev->mode_config.mutex);
4be73780 1195 edp_panel_vdd_off_sync(intel_dp);
627f7675 1196 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1197}
1198
4be73780 1199static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1200{
97af61f5
KP		 1201 if (!is_edp(intel_dp))
1202 return;
5d613501 1203
bd943159 1204 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1205
bd943159
KP		 1206 intel_dp->want_panel_vdd = false;
1207
1208 if (sync) {
4be73780 1209 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1210 } else {
1211 /*
1212 * Queue the timer to fire a long
1213 * time from now (relative to the power down delay)
1214 * to keep the panel power up across a sequence of operations
1215 */
1216 schedule_delayed_work(&intel_dp->panel_vdd_work,
1217 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1218 }
5d613501
JB		 1219}
1220
4be73780 1221void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1222{
30add22d 1223 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1224 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1225 u32 pp;
453c5420 1226 u32 pp_ctrl_reg;
9934c132 1227
97af61f5 1228 if (!is_edp(intel_dp))
bd943159 1229 return;
99ea7127
KP		 1230
1231 DRM_DEBUG_KMS("Turn eDP power on\n");
1232
4be73780 1233 if (edp_have_panel_power(intel_dp)) {
99ea7127 1234 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1235 return;
99ea7127 1236 }
9934c132 1237
4be73780 1238 wait_panel_power_cycle(intel_dp);
37c6c9b0 1239
bf13e81b 1240 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1241 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1242 if (IS_GEN5(dev)) {
1243 /* ILK workaround: disable reset around power sequence */
1244 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1245 I915_WRITE(pp_ctrl_reg, pp);
1246 POSTING_READ(pp_ctrl_reg);
05ce1a49 1247 }
37c6c9b0 1248
1c0ae80a 1249 pp |= POWER_TARGET_ON;
99ea7127
KP		 1250 if (!IS_GEN5(dev))
1251 pp |= PANEL_POWER_RESET;
1252
453c5420
JB		 1253 I915_WRITE(pp_ctrl_reg, pp);
1254 POSTING_READ(pp_ctrl_reg);
9934c132 1255
4be73780 1256 wait_panel_on(intel_dp);
dce56b3c 1257 intel_dp->last_power_on = jiffies;
9934c132 1258
05ce1a49
KP		 1259 if (IS_GEN5(dev)) {
1260 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1261 I915_WRITE(pp_ctrl_reg, pp);
1262 POSTING_READ(pp_ctrl_reg);
05ce1a49 1263 }
9934c132
JB		 1264}
1265
4be73780 1266void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1267{
4e6e1a54
ID		 1268 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1269 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1270 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1271 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1272 enum intel_display_power_domain power_domain;
99ea7127 1273 u32 pp;
453c5420 1274 u32 pp_ctrl_reg;
9934c132 1275
97af61f5
KP		 1276 if (!is_edp(intel_dp))
1277 return;
37c6c9b0 1278
99ea7127 1279 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1280
4be73780 1281 edp_wait_backlight_off(intel_dp);
dce56b3c 1282
24f3e092
JN		 1283 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1284
453c5420 1285 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1286 /* We need to switch off panel power _and_ force vdd, for otherwise some
1287 * panels get very unhappy and cease to work. */
b3064154
PJ		 1288 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1289 EDP_BLC_ENABLE);
453c5420 1290
bf13e81b 1291 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1292
849e39f5
PZ		 1293 intel_dp->want_panel_vdd = false;
1294
453c5420
JB		 1295 I915_WRITE(pp_ctrl_reg, pp);
1296 POSTING_READ(pp_ctrl_reg);
9934c132 1297
dce56b3c 1298 intel_dp->last_power_cycle = jiffies;
4be73780 1299 wait_panel_off(intel_dp);
849e39f5
PZ		 1300
1301 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1302 power_domain = intel_display_port_power_domain(intel_encoder);
1303 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1304}
1305
4be73780 1306void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1307{
da63a9f2
PZ		 1308 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1309 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1310 struct drm_i915_private *dev_priv = dev->dev_private;
1311 u32 pp;
453c5420 1312 u32 pp_ctrl_reg;
32f9d658 1313
f01eca2e
KP		 1314 if (!is_edp(intel_dp))
1315 return;
1316
28c97730 1317 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1318 /*
1319 * If we enable the backlight right away following a panel power
1320 * on, we may see slight flicker as the panel syncs with the eDP
1321 * link. So delay a bit to make sure the image is solid before
1322 * allowing it to appear.
1323 */
4be73780 1324 wait_backlight_on(intel_dp);
453c5420 1325 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1326 pp |= EDP_BLC_ENABLE;
453c5420 1327
bf13e81b 1328 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1329
1330 I915_WRITE(pp_ctrl_reg, pp);
1331 POSTING_READ(pp_ctrl_reg);
035aa3de 1332
752aa88a 1333 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1334}
1335
4be73780 1336void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1337{
30add22d 1338 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1339 struct drm_i915_private *dev_priv = dev->dev_private;
1340 u32 pp;
453c5420 1341 u32 pp_ctrl_reg;
32f9d658 1342
f01eca2e
KP		 1343 if (!is_edp(intel_dp))
1344 return;
1345
752aa88a 1346 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1347
28c97730 1348 DRM_DEBUG_KMS("\n");
453c5420 1349 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1350 pp &= ~EDP_BLC_ENABLE;
453c5420 1351
bf13e81b 1352 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1353
1354 I915_WRITE(pp_ctrl_reg, pp);
1355 POSTING_READ(pp_ctrl_reg);
dce56b3c 1356 intel_dp->last_backlight_off = jiffies;
32f9d658 1357}
a4fc5ed6 1358
2bd2ad64 1359static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1360{
da63a9f2
PZ		 1361 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1362 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1363 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1364 struct drm_i915_private *dev_priv = dev->dev_private;
1365 u32 dpa_ctl;
1366
2bd2ad64
DV		 1367 assert_pipe_disabled(dev_priv,
1368 to_intel_crtc(crtc)->pipe);
1369
d240f20f
JB		 1370 DRM_DEBUG_KMS("\n");
1371 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1372 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1373 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1374
1375 /* We don't adjust intel_dp->DP while tearing down the link, to
1376 * facilitate link retraining (e.g. after hotplug). Hence clear all
1377 * enable bits here to ensure that we don't enable too much. */
1378 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1379 intel_dp->DP |= DP_PLL_ENABLE;
1380 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1381 POSTING_READ(DP_A);
1382 udelay(200);
d240f20f
JB		 1383}
1384
2bd2ad64 1385static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1386{
da63a9f2
PZ		 1387 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1388 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1389 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1390 struct drm_i915_private *dev_priv = dev->dev_private;
1391 u32 dpa_ctl;
1392
2bd2ad64
DV		 1393 assert_pipe_disabled(dev_priv,
1394 to_intel_crtc(crtc)->pipe);
1395
d240f20f 1396 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1397 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1398 "dp pll off, should be on\n");
1399 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1400
1401 /* We can't rely on the value tracked for the DP register in
1402 * intel_dp->DP because link_down must not change that (otherwise link
1403 * re-training will fail. */
298b0b39 1404 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1405 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1406 POSTING_READ(DP_A);
d240f20f
JB		 1407 udelay(200);
1408}
1409
c7ad3810 1410/* If the sink supports it, try to set the power state appropriately */
c19b0669 1411void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1412{
1413 int ret, i;
1414
1415 /* Should have a valid DPCD by this point */
1416 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1417 return;
1418
1419 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1420 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1421 DP_SET_POWER_D3);
c7ad3810
JB		 1422 if (ret != 1)
1423 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1424 } else {
1425 /*
1426 * When turning on, we need to retry for 1ms to give the sink
1427 * time to wake up.
1428 */
1429 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1430 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1431 DP_SET_POWER_D0);
c7ad3810
JB		 1432 if (ret == 1)
1433 break;
1434 msleep(1);
1435 }
1436 }
1437}
1438
19d8fe15
DV		 1439static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1440 enum pipe *pipe)
d240f20f 1441{
19d8fe15 1442 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1443 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1444 struct drm_device *dev = encoder->base.dev;
1445 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1446 enum intel_display_power_domain power_domain;
1447 u32 tmp;
1448
1449 power_domain = intel_display_port_power_domain(encoder);
1450 if (!intel_display_power_enabled(dev_priv, power_domain))
1451 return false;
1452
1453 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1454
1455 if (!(tmp & DP_PORT_EN))
1456 return false;
1457
bc7d38a4 1458 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1459 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1460 } else if (IS_CHERRYVIEW(dev)) {
1461 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1462 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1463 *pipe = PORT_TO_PIPE(tmp);
1464 } else {
1465 u32 trans_sel;
1466 u32 trans_dp;
1467 int i;
1468
1469 switch (intel_dp->output_reg) {
1470 case PCH_DP_B:
1471 trans_sel = TRANS_DP_PORT_SEL_B;
1472 break;
1473 case PCH_DP_C:
1474 trans_sel = TRANS_DP_PORT_SEL_C;
1475 break;
1476 case PCH_DP_D:
1477 trans_sel = TRANS_DP_PORT_SEL_D;
1478 break;
1479 default:
1480 return true;
1481 }
1482
1483 for_each_pipe(i) {
1484 trans_dp = I915_READ(TRANS_DP_CTL(i));
1485 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1486 *pipe = i;
1487 return true;
1488 }
1489 }
19d8fe15 1490
4a0833ec
DV		 1491 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1492 intel_dp->output_reg);
1493 }
d240f20f 1494
19d8fe15
DV		 1495 return true;
1496}
d240f20f 1497
045ac3b5
JB		 1498static void intel_dp_get_config(struct intel_encoder *encoder,
1499 struct intel_crtc_config *pipe_config)
1500{
1501 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1502 u32 tmp, flags = 0;
63000ef6
XZ		 1503 struct drm_device *dev = encoder->base.dev;
1504 struct drm_i915_private *dev_priv = dev->dev_private;
1505 enum port port = dp_to_dig_port(intel_dp)->port;
1506 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1507 int dotclock;
045ac3b5 1508
9ed109a7
DV		 1509 tmp = I915_READ(intel_dp->output_reg);
1510 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1511 pipe_config->has_audio = true;
1512
63000ef6 1513 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1514 if (tmp & DP_SYNC_HS_HIGH)
1515 flags |= DRM_MODE_FLAG_PHSYNC;
1516 else
1517 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1518
63000ef6
XZ		 1519 if (tmp & DP_SYNC_VS_HIGH)
1520 flags |= DRM_MODE_FLAG_PVSYNC;
1521 else
1522 flags |= DRM_MODE_FLAG_NVSYNC;
1523 } else {
1524 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1525 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1526 flags |= DRM_MODE_FLAG_PHSYNC;
1527 else
1528 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1529
63000ef6
XZ		 1530 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1531 flags |= DRM_MODE_FLAG_PVSYNC;
1532 else
1533 flags |= DRM_MODE_FLAG_NVSYNC;
1534 }
045ac3b5
JB		 1535
1536 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1537
eb14cb74
VS		 1538 pipe_config->has_dp_encoder = true;
1539
1540 intel_dp_get_m_n(crtc, pipe_config);
1541
18442d08 1542 if (port == PORT_A) {
f1f644dc
JB		 1543 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1544 pipe_config->port_clock = 162000;
1545 else
1546 pipe_config->port_clock = 270000;
1547 }
18442d08
VS		 1548
1549 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1550 &pipe_config->dp_m_n);
1551
1552 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1553 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1554
241bfc38 1555 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1556
c6cd2ee2
JN		 1557 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1558 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1559 /*
1560 * This is a big fat ugly hack.
1561 *
1562 * Some machines in UEFI boot mode provide us a VBT that has 18
1563 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1564 * unknown we fail to light up. Yet the same BIOS boots up with
1565 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1566 * max, not what it tells us to use.
1567 *
1568 * Note: This will still be broken if the eDP panel is not lit
1569 * up by the BIOS, and thus we can't get the mode at module
1570 * load.
1571 */
1572 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1573 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1574 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1575 }
045ac3b5
JB		 1576}
1577
a031d709 1578static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1579{
a031d709
RV		 1580 struct drm_i915_private *dev_priv = dev->dev_private;
1581
1582 return dev_priv->psr.sink_support;
2293bb5c
SK		 1583}
1584
2b28bb1b
RV		 1585static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1586{
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588
18b5992c 1589 if (!HAS_PSR(dev))
2b28bb1b
RV		 1590 return false;
1591
18b5992c 1592 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1593}
1594
1595static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1596 struct edp_vsc_psr *vsc_psr)
1597{
1598 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1599 struct drm_device *dev = dig_port->base.base.dev;
1600 struct drm_i915_private *dev_priv = dev->dev_private;
1601 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1602 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1603 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1604 uint32_t *data = (uint32_t *) vsc_psr;
1605 unsigned int i;
1606
1607 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1608 the video DIP being updated before program video DIP data buffer
1609 registers for DIP being updated. */
1610 I915_WRITE(ctl_reg, 0);
1611 POSTING_READ(ctl_reg);
1612
1613 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1614 if (i < sizeof(struct edp_vsc_psr))
1615 I915_WRITE(data_reg + i, *data++);
1616 else
1617 I915_WRITE(data_reg + i, 0);
1618 }
1619
1620 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1621 POSTING_READ(ctl_reg);
1622}
1623
1624static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1625{
1626 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1627 struct drm_i915_private *dev_priv = dev->dev_private;
1628 struct edp_vsc_psr psr_vsc;
1629
1630 if (intel_dp->psr_setup_done)
1631 return;
1632
1633 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1634 memset(&psr_vsc, 0, sizeof(psr_vsc));
1635 psr_vsc.sdp_header.HB0 = 0;
1636 psr_vsc.sdp_header.HB1 = 0x7;
1637 psr_vsc.sdp_header.HB2 = 0x2;
1638 psr_vsc.sdp_header.HB3 = 0x8;
1639 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1640
1641 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1642 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1643 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1644
1645 intel_dp->psr_setup_done = true;
1646}
1647
1648static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1649{
1650 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1651 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1652 uint32_t aux_clock_divider;
2b28bb1b
RV		 1653 int precharge = 0x3;
1654 int msg_size = 5; /* Header(4) + Message(1) */
1655
ec5b01dd
DL		 1656 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1657
2b28bb1b
RV		 1658 /* Enable PSR in sink */
1659 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
9d1a1031
JN		 1660 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1661 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1662 else
9d1a1031
JN		 1663 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1664 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1665
1666 /* Setup AUX registers */
18b5992c
BW		 1667 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1668 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1669 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1670 DP_AUX_CH_CTL_TIME_OUT_400us |
1671 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1672 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1673 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1674}
1675
1676static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1677{
1678 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1679 struct drm_i915_private *dev_priv = dev->dev_private;
1680 uint32_t max_sleep_time = 0x1f;
1681 uint32_t idle_frames = 1;
1682 uint32_t val = 0x0;
ed8546ac 1683 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1684
1685 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1686 val |= EDP_PSR_LINK_STANDBY;
1687 val |= EDP_PSR_TP2_TP3_TIME_0us;
1688 val |= EDP_PSR_TP1_TIME_0us;
1689 val |= EDP_PSR_SKIP_AUX_EXIT;
1690 } else
1691 val |= EDP_PSR_LINK_DISABLE;
1692
18b5992c 1693 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1694 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1695 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1696 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1697 EDP_PSR_ENABLE);
1698}
1699
3f51e471
RV		 1700static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1701{
1702 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1703 struct drm_device *dev = dig_port->base.base.dev;
1704 struct drm_i915_private *dev_priv = dev->dev_private;
1705 struct drm_crtc *crtc = dig_port->base.base.crtc;
1706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f4510a27 1707 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1708 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1709
a031d709
RV		 1710 dev_priv->psr.source_ok = false;
1711
18b5992c 1712 if (!HAS_PSR(dev)) {
3f51e471 1713 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1714 return false;
1715 }
1716
1717 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1718 (dig_port->port != PORT_A)) {
1719 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1720 return false;
1721 }
1722
d330a953 1723 if (!i915.enable_psr) {
105b7c11 1724 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1725 return false;
1726 }
1727
cd234b0b
CW		 1728 crtc = dig_port->base.base.crtc;
1729 if (crtc == NULL) {
1730 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1731 return false;
1732 }
1733
1734 intel_crtc = to_intel_crtc(crtc);
20ddf665 1735 if (!intel_crtc_active(crtc)) {
3f51e471 1736 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1737 return false;
1738 }
1739
f4510a27 1740 obj = to_intel_framebuffer(crtc->primary->fb)->obj;
3f51e471
RV		 1741 if (obj->tiling_mode != I915_TILING_X ||
1742 obj->fence_reg == I915_FENCE_REG_NONE) {
1743 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1744 return false;
1745 }
1746
1747 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1748 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1749 return false;
1750 }
1751
1752 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1753 S3D_ENABLE) {
1754 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1755 return false;
1756 }
1757
ca73b4f0 1758 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1759 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1760 return false;
1761 }
1762
a031d709 1763 dev_priv->psr.source_ok = true;
3f51e471
RV		 1764 return true;
1765}
1766
3d739d92 1767static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1768{
1769 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1770
3f51e471
RV		 1771 if (!intel_edp_psr_match_conditions(intel_dp) ||
1772 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1773 return;
1774
1775 /* Setup PSR once */
1776 intel_edp_psr_setup(intel_dp);
1777
1778 /* Enable PSR on the panel */
1779 intel_edp_psr_enable_sink(intel_dp);
1780
1781 /* Enable PSR on the host */
1782 intel_edp_psr_enable_source(intel_dp);
1783}
1784
3d739d92
RV		 1785void intel_edp_psr_enable(struct intel_dp *intel_dp)
1786{
1787 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1788
1789 if (intel_edp_psr_match_conditions(intel_dp) &&
1790 !intel_edp_is_psr_enabled(dev))
1791 intel_edp_psr_do_enable(intel_dp);
1792}
1793
2b28bb1b
RV		 1794void intel_edp_psr_disable(struct intel_dp *intel_dp)
1795{
1796 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1797 struct drm_i915_private *dev_priv = dev->dev_private;
1798
1799 if (!intel_edp_is_psr_enabled(dev))
1800 return;
1801
18b5992c
BW		 1802 I915_WRITE(EDP_PSR_CTL(dev),
1803 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1804
1805 /* Wait till PSR is idle */
18b5992c 1806 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1807 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1808 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1809}
1810
3d739d92
RV		 1811void intel_edp_psr_update(struct drm_device *dev)
1812{
1813 struct intel_encoder *encoder;
1814 struct intel_dp *intel_dp = NULL;
1815
1816 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1817 if (encoder->type == INTEL_OUTPUT_EDP) {
1818 intel_dp = enc_to_intel_dp(&encoder->base);
1819
a031d709 1820 if (!is_edp_psr(dev))
3d739d92
RV		 1821 return;
1822
1823 if (!intel_edp_psr_match_conditions(intel_dp))
1824 intel_edp_psr_disable(intel_dp);
1825 else
1826 if (!intel_edp_is_psr_enabled(dev))
1827 intel_edp_psr_do_enable(intel_dp);
1828 }
1829}
1830
e8cb4558 1831static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1832{
e8cb4558 1833 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1834 enum port port = dp_to_dig_port(intel_dp)->port;
1835 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1836
1837 /* Make sure the panel is off before trying to change the mode. But also
1838 * ensure that we have vdd while we switch off the panel. */
24f3e092 1839 intel_edp_panel_vdd_on(intel_dp);
4be73780 1840 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1841 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1842 intel_edp_panel_off(intel_dp);
3739850b
DV		 1843
1844 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1845 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1846 intel_dp_link_down(intel_dp);
d240f20f
JB		 1847}
1848
49277c31 1849static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1850{
2bd2ad64 1851 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1852 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 1853
49277c31
VS		 1854 if (port != PORT_A)
1855 return;
1856
1857 intel_dp_link_down(intel_dp);
1858 ironlake_edp_pll_off(intel_dp);
1859}
1860
1861static void vlv_post_disable_dp(struct intel_encoder *encoder)
1862{
1863 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1864
1865 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 1866}
1867
580d3811
VS		 1868static void chv_post_disable_dp(struct intel_encoder *encoder)
1869{
1870 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1871 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1872 struct drm_device *dev = encoder->base.dev;
1873 struct drm_i915_private *dev_priv = dev->dev_private;
1874 struct intel_crtc *intel_crtc =
1875 to_intel_crtc(encoder->base.crtc);
1876 enum dpio_channel ch = vlv_dport_to_channel(dport);
1877 enum pipe pipe = intel_crtc->pipe;
1878 u32 val;
1879
1880 intel_dp_link_down(intel_dp);
1881
1882 mutex_lock(&dev_priv->dpio_lock);
1883
1884 /* Propagate soft reset to data lane reset */
97fd4d5c 1885 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 1886 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 1887 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 1888
97fd4d5c
VS		 1889 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1890 val |= CHV_PCS_REQ_SOFTRESET_EN;
1891 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1892
1893 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1894 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1895 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1896
1897 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 1898 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 1899 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 1900
1901 mutex_unlock(&dev_priv->dpio_lock);
1902}
1903
e8cb4558 1904static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1905{
e8cb4558
DV		 1906 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1907 struct drm_device *dev = encoder->base.dev;
1908 struct drm_i915_private *dev_priv = dev->dev_private;
1909 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1910
0c33d8d7
DV		 1911 if (WARN_ON(dp_reg & DP_PORT_EN))
1912 return;
5d613501 1913
24f3e092 1914 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 1915 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1916 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1917 intel_edp_panel_on(intel_dp);
1918 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1919 intel_dp_complete_link_train(intel_dp);
3ab9c637 1920 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1921}
89b667f8 1922
ecff4f3b
JN		 1923static void g4x_enable_dp(struct intel_encoder *encoder)
1924{
828f5c6e
JN		 1925 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1926
ecff4f3b 1927 intel_enable_dp(encoder);
4be73780 1928 intel_edp_backlight_on(intel_dp);
ab1f90f9 1929}
89b667f8 1930
ab1f90f9
JN		 1931static void vlv_enable_dp(struct intel_encoder *encoder)
1932{
828f5c6e
JN		 1933 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1934
4be73780 1935 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1936}
1937
ecff4f3b 1938static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1939{
1940 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1941 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1942
8ac33ed3
DV		 1943 intel_dp_prepare(encoder);
1944
d41f1efb
DV		 1945 /* Only ilk+ has port A */
1946 if (dport->port == PORT_A) {
1947 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 1948 ironlake_edp_pll_on(intel_dp);
d41f1efb 1949 }
ab1f90f9
JN		 1950}
1951
1952static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1953{
2bd2ad64 1954 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1955 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1956 struct drm_device *dev = encoder->base.dev;
89b667f8 1957 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1958 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1959 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1960 int pipe = intel_crtc->pipe;
bf13e81b 1961 struct edp_power_seq power_seq;
ab1f90f9 1962 u32 val;
a4fc5ed6 1963
ab1f90f9 1964 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1965
ab3c759a 1966 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1967 val = 0;
1968 if (pipe)
1969 val |= (1<<21);
1970 else
1971 val &= ~(1<<21);
1972 val |= 0x001000c4;
ab3c759a
CML		 1973 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1974 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1975 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1976
ab1f90f9
JN		 1977 mutex_unlock(&dev_priv->dpio_lock);
1978
2cac613b
ID		 1979 if (is_edp(intel_dp)) {
1980 /* init power sequencer on this pipe and port */
1981 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1982 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1983 &power_seq);
1984 }
bf13e81b 1985
ab1f90f9
JN		 1986 intel_enable_dp(encoder);
1987
e4607fcf 1988 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1989}
1990
ecff4f3b 1991static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1992{
1993 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1994 struct drm_device *dev = encoder->base.dev;
1995 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1996 struct intel_crtc *intel_crtc =
1997 to_intel_crtc(encoder->base.crtc);
e4607fcf 1998 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1999 int pipe = intel_crtc->pipe;
89b667f8 2000
8ac33ed3
DV		 2001 intel_dp_prepare(encoder);
2002
89b667f8 2003 /* Program Tx lane resets to default */
0980a60f 2004 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2005 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2006 DPIO_PCS_TX_LANE2_RESET |
2007 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2008 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2009 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2010 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2011 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2012 DPIO_PCS_CLK_SOFT_RESET);
2013
2014 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2015 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2016 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2017 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2018 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2019}
2020
e4a1d846
CML		 2021static void chv_pre_enable_dp(struct intel_encoder *encoder)
2022{
2023 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2024 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2025 struct drm_device *dev = encoder->base.dev;
2026 struct drm_i915_private *dev_priv = dev->dev_private;
2027 struct edp_power_seq power_seq;
2028 struct intel_crtc *intel_crtc =
2029 to_intel_crtc(encoder->base.crtc);
2030 enum dpio_channel ch = vlv_dport_to_channel(dport);
2031 int pipe = intel_crtc->pipe;
2032 int data, i;
949c1d43 2033 u32 val;
e4a1d846 2034
e4a1d846 2035 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2036
2037 /* Deassert soft data lane reset*/
97fd4d5c 2038 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2039 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2040 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2041
2042 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2043 val |= CHV_PCS_REQ_SOFTRESET_EN;
2044 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2045
2046 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2047 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2048 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2049
97fd4d5c 2050 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2051 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2052 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2053
2054 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2055 for (i = 0; i < 4; i++) {
2056 /* Set the latency optimal bit */
2057 data = (i == 1) ? 0x0 : 0x6;
2058 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2059 data << DPIO_FRC_LATENCY_SHFIT);
2060
2061 /* Set the upar bit */
2062 data = (i == 1) ? 0x0 : 0x1;
2063 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2064 data << DPIO_UPAR_SHIFT);
2065 }
2066
2067 /* Data lane stagger programming */
2068 /* FIXME: Fix up value only after power analysis */
2069
2070 mutex_unlock(&dev_priv->dpio_lock);
2071
2072 if (is_edp(intel_dp)) {
2073 /* init power sequencer on this pipe and port */
2074 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2075 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2076 &power_seq);
2077 }
2078
2079 intel_enable_dp(encoder);
2080
2081 vlv_wait_port_ready(dev_priv, dport);
2082}
2083
a4fc5ed6 2084/*
df0c237d
JB		 2085 * Native read with retry for link status and receiver capability reads for
2086 * cases where the sink may still be asleep.
9d1a1031
JN		 2087 *
2088 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2089 * supposed to retry 3 times per the spec.
a4fc5ed6 2090 */
9d1a1031
JN		 2091static ssize_t
2092intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2093 void *buffer, size_t size)
a4fc5ed6 2094{
9d1a1031
JN		 2095 ssize_t ret;
2096 int i;
61da5fab 2097
61da5fab 2098 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2099 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2100 if (ret == size)
2101 return ret;
61da5fab
JB		 2102 msleep(1);
2103 }
a4fc5ed6 2104
9d1a1031 2105 return ret;
a4fc5ed6
KP		 2106}
2107
2108/*
2109 * Fetch AUX CH registers 0x202 - 0x207 which contain
2110 * link status information
2111 */
2112static bool
93f62dad 2113intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2114{
9d1a1031
JN		 2115 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2116 DP_LANE0_1_STATUS,
2117 link_status,
2118 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2119}
2120
a4fc5ed6
KP		 2121/*
2122 * These are source-specific values; current Intel hardware supports
2123 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2124 */
a4fc5ed6
KP		 2125
2126static uint8_t
1a2eb460 2127intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2128{
30add22d 2129 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2130 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2131
8f93f4f1 2132 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 2133 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2134 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2135 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2136 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2137 return DP_TRAIN_VOLTAGE_SWING_1200;
2138 else
2139 return DP_TRAIN_VOLTAGE_SWING_800;
2140}
2141
2142static uint8_t
2143intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2144{
30add22d 2145 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2146 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2147
8f93f4f1
PZ		 2148 if (IS_BROADWELL(dev)) {
2149 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2150 case DP_TRAIN_VOLTAGE_SWING_400:
2151 case DP_TRAIN_VOLTAGE_SWING_600:
2152 return DP_TRAIN_PRE_EMPHASIS_6;
2153 case DP_TRAIN_VOLTAGE_SWING_800:
2154 return DP_TRAIN_PRE_EMPHASIS_3_5;
2155 case DP_TRAIN_VOLTAGE_SWING_1200:
2156 default:
2157 return DP_TRAIN_PRE_EMPHASIS_0;
2158 }
2159 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 2160 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2161 case DP_TRAIN_VOLTAGE_SWING_400:
2162 return DP_TRAIN_PRE_EMPHASIS_9_5;
2163 case DP_TRAIN_VOLTAGE_SWING_600:
2164 return DP_TRAIN_PRE_EMPHASIS_6;
2165 case DP_TRAIN_VOLTAGE_SWING_800:
2166 return DP_TRAIN_PRE_EMPHASIS_3_5;
2167 case DP_TRAIN_VOLTAGE_SWING_1200:
2168 default:
2169 return DP_TRAIN_PRE_EMPHASIS_0;
2170 }
e2fa6fba
P		 2171 } else if (IS_VALLEYVIEW(dev)) {
2172 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2173 case DP_TRAIN_VOLTAGE_SWING_400:
2174 return DP_TRAIN_PRE_EMPHASIS_9_5;
2175 case DP_TRAIN_VOLTAGE_SWING_600:
2176 return DP_TRAIN_PRE_EMPHASIS_6;
2177 case DP_TRAIN_VOLTAGE_SWING_800:
2178 return DP_TRAIN_PRE_EMPHASIS_3_5;
2179 case DP_TRAIN_VOLTAGE_SWING_1200:
2180 default:
2181 return DP_TRAIN_PRE_EMPHASIS_0;
2182 }
bc7d38a4 2183 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2184 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2185 case DP_TRAIN_VOLTAGE_SWING_400:
2186 return DP_TRAIN_PRE_EMPHASIS_6;
2187 case DP_TRAIN_VOLTAGE_SWING_600:
2188 case DP_TRAIN_VOLTAGE_SWING_800:
2189 return DP_TRAIN_PRE_EMPHASIS_3_5;
2190 default:
2191 return DP_TRAIN_PRE_EMPHASIS_0;
2192 }
2193 } else {
2194 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2195 case DP_TRAIN_VOLTAGE_SWING_400:
2196 return DP_TRAIN_PRE_EMPHASIS_6;
2197 case DP_TRAIN_VOLTAGE_SWING_600:
2198 return DP_TRAIN_PRE_EMPHASIS_6;
2199 case DP_TRAIN_VOLTAGE_SWING_800:
2200 return DP_TRAIN_PRE_EMPHASIS_3_5;
2201 case DP_TRAIN_VOLTAGE_SWING_1200:
2202 default:
2203 return DP_TRAIN_PRE_EMPHASIS_0;
2204 }
a4fc5ed6
KP		 2205 }
2206}
2207
e2fa6fba
P		 2208static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2209{
2210 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2211 struct drm_i915_private *dev_priv = dev->dev_private;
2212 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2213 struct intel_crtc *intel_crtc =
2214 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2215 unsigned long demph_reg_value, preemph_reg_value,
2216 uniqtranscale_reg_value;
2217 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2218 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2219 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2220
2221 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2222 case DP_TRAIN_PRE_EMPHASIS_0:
2223 preemph_reg_value = 0x0004000;
2224 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2225 case DP_TRAIN_VOLTAGE_SWING_400:
2226 demph_reg_value = 0x2B405555;
2227 uniqtranscale_reg_value = 0x552AB83A;
2228 break;
2229 case DP_TRAIN_VOLTAGE_SWING_600:
2230 demph_reg_value = 0x2B404040;
2231 uniqtranscale_reg_value = 0x5548B83A;
2232 break;
2233 case DP_TRAIN_VOLTAGE_SWING_800:
2234 demph_reg_value = 0x2B245555;
2235 uniqtranscale_reg_value = 0x5560B83A;
2236 break;
2237 case DP_TRAIN_VOLTAGE_SWING_1200:
2238 demph_reg_value = 0x2B405555;
2239 uniqtranscale_reg_value = 0x5598DA3A;
2240 break;
2241 default:
2242 return 0;
2243 }
2244 break;
2245 case DP_TRAIN_PRE_EMPHASIS_3_5:
2246 preemph_reg_value = 0x0002000;
2247 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2248 case DP_TRAIN_VOLTAGE_SWING_400:
2249 demph_reg_value = 0x2B404040;
2250 uniqtranscale_reg_value = 0x5552B83A;
2251 break;
2252 case DP_TRAIN_VOLTAGE_SWING_600:
2253 demph_reg_value = 0x2B404848;
2254 uniqtranscale_reg_value = 0x5580B83A;
2255 break;
2256 case DP_TRAIN_VOLTAGE_SWING_800:
2257 demph_reg_value = 0x2B404040;
2258 uniqtranscale_reg_value = 0x55ADDA3A;
2259 break;
2260 default:
2261 return 0;
2262 }
2263 break;
2264 case DP_TRAIN_PRE_EMPHASIS_6:
2265 preemph_reg_value = 0x0000000;
2266 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2267 case DP_TRAIN_VOLTAGE_SWING_400:
2268 demph_reg_value = 0x2B305555;
2269 uniqtranscale_reg_value = 0x5570B83A;
2270 break;
2271 case DP_TRAIN_VOLTAGE_SWING_600:
2272 demph_reg_value = 0x2B2B4040;
2273 uniqtranscale_reg_value = 0x55ADDA3A;
2274 break;
2275 default:
2276 return 0;
2277 }
2278 break;
2279 case DP_TRAIN_PRE_EMPHASIS_9_5:
2280 preemph_reg_value = 0x0006000;
2281 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2282 case DP_TRAIN_VOLTAGE_SWING_400:
2283 demph_reg_value = 0x1B405555;
2284 uniqtranscale_reg_value = 0x55ADDA3A;
2285 break;
2286 default:
2287 return 0;
2288 }
2289 break;
2290 default:
2291 return 0;
2292 }
2293
0980a60f 2294 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2295 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2296 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2297 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2298 uniqtranscale_reg_value);
ab3c759a
CML		 2299 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2300 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2301 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2302 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2303 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2304
2305 return 0;
2306}
2307
e4a1d846
CML		 2308static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2309{
2310 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2311 struct drm_i915_private *dev_priv = dev->dev_private;
2312 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2313 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2314 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2315 uint8_t train_set = intel_dp->train_set[0];
2316 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2317 enum pipe pipe = intel_crtc->pipe;
2318 int i;
e4a1d846
CML		 2319
2320 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2321 case DP_TRAIN_PRE_EMPHASIS_0:
2322 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2323 case DP_TRAIN_VOLTAGE_SWING_400:
2324 deemph_reg_value = 128;
2325 margin_reg_value = 52;
2326 break;
2327 case DP_TRAIN_VOLTAGE_SWING_600:
2328 deemph_reg_value = 128;
2329 margin_reg_value = 77;
2330 break;
2331 case DP_TRAIN_VOLTAGE_SWING_800:
2332 deemph_reg_value = 128;
2333 margin_reg_value = 102;
2334 break;
2335 case DP_TRAIN_VOLTAGE_SWING_1200:
2336 deemph_reg_value = 128;
2337 margin_reg_value = 154;
2338 /* FIXME extra to set for 1200 */
2339 break;
2340 default:
2341 return 0;
2342 }
2343 break;
2344 case DP_TRAIN_PRE_EMPHASIS_3_5:
2345 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2346 case DP_TRAIN_VOLTAGE_SWING_400:
2347 deemph_reg_value = 85;
2348 margin_reg_value = 78;
2349 break;
2350 case DP_TRAIN_VOLTAGE_SWING_600:
2351 deemph_reg_value = 85;
2352 margin_reg_value = 116;
2353 break;
2354 case DP_TRAIN_VOLTAGE_SWING_800:
2355 deemph_reg_value = 85;
2356 margin_reg_value = 154;
2357 break;
2358 default:
2359 return 0;
2360 }
2361 break;
2362 case DP_TRAIN_PRE_EMPHASIS_6:
2363 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2364 case DP_TRAIN_VOLTAGE_SWING_400:
2365 deemph_reg_value = 64;
2366 margin_reg_value = 104;
2367 break;
2368 case DP_TRAIN_VOLTAGE_SWING_600:
2369 deemph_reg_value = 64;
2370 margin_reg_value = 154;
2371 break;
2372 default:
2373 return 0;
2374 }
2375 break;
2376 case DP_TRAIN_PRE_EMPHASIS_9_5:
2377 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2378 case DP_TRAIN_VOLTAGE_SWING_400:
2379 deemph_reg_value = 43;
2380 margin_reg_value = 154;
2381 break;
2382 default:
2383 return 0;
2384 }
2385 break;
2386 default:
2387 return 0;
2388 }
2389
2390 mutex_lock(&dev_priv->dpio_lock);
2391
2392 /* Clear calc init */
1966e59e
VS		 2393 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2394 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2395 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2396
2397 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2398 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2399 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2400
2401 /* Program swing deemph */
f72df8db
VS		 2402 for (i = 0; i < 4; i++) {
2403 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2404 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2405 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2406 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2407 }
e4a1d846
CML		 2408
2409 /* Program swing margin */
f72df8db
VS		 2410 for (i = 0; i < 4; i++) {
2411 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2412 val &= ~DPIO_SWING_MARGIN_MASK;
2413 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2414 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2415 }
e4a1d846
CML		 2416
2417 /* Disable unique transition scale */
f72df8db
VS		 2418 for (i = 0; i < 4; i++) {
2419 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2420 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2421 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2422 }
e4a1d846
CML		 2423
2424 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2425 == DP_TRAIN_PRE_EMPHASIS_0) &&
2426 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2427 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2428
2429 /*
2430 * The document said it needs to set bit 27 for ch0 and bit 26
2431 * for ch1. Might be a typo in the doc.
2432 * For now, for this unique transition scale selection, set bit
2433 * 27 for ch0 and ch1.
2434 */
f72df8db
VS		 2435 for (i = 0; i < 4; i++) {
2436 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2437 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2438 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2439 }
e4a1d846 2440
f72df8db
VS		 2441 for (i = 0; i < 4; i++) {
2442 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2443 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2444 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2445 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2446 }
e4a1d846
CML		 2447 }
2448
2449 /* Start swing calculation */
1966e59e
VS		 2450 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2451 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2452 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2453
2454 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2455 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2456 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2457
2458 /* LRC Bypass */
2459 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2460 val |= DPIO_LRC_BYPASS;
2461 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2462
2463 mutex_unlock(&dev_priv->dpio_lock);
2464
2465 return 0;
2466}
2467
a4fc5ed6 2468static void
0301b3ac
JN		 2469intel_get_adjust_train(struct intel_dp *intel_dp,
2470 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2471{
2472 uint8_t v = 0;
2473 uint8_t p = 0;
2474 int lane;
1a2eb460
KP		 2475 uint8_t voltage_max;
2476 uint8_t preemph_max;
a4fc5ed6 2477
33a34e4e 2478 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2479 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2480 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2481
2482 if (this_v > v)
2483 v = this_v;
2484 if (this_p > p)
2485 p = this_p;
2486 }
2487
1a2eb460 2488 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2489 if (v >= voltage_max)
2490 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2491
1a2eb460
KP		 2492 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2493 if (p >= preemph_max)
2494 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2495
2496 for (lane = 0; lane < 4; lane++)
33a34e4e 2497 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2498}
2499
2500static uint32_t
f0a3424e 2501intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2502{
3cf2efb1 2503 uint32_t signal_levels = 0;
a4fc5ed6 2504
3cf2efb1 2505 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2506 case DP_TRAIN_VOLTAGE_SWING_400:
2507 default:
2508 signal_levels |= DP_VOLTAGE_0_4;
2509 break;
2510 case DP_TRAIN_VOLTAGE_SWING_600:
2511 signal_levels |= DP_VOLTAGE_0_6;
2512 break;
2513 case DP_TRAIN_VOLTAGE_SWING_800:
2514 signal_levels |= DP_VOLTAGE_0_8;
2515 break;
2516 case DP_TRAIN_VOLTAGE_SWING_1200:
2517 signal_levels |= DP_VOLTAGE_1_2;
2518 break;
2519 }
3cf2efb1 2520 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2521 case DP_TRAIN_PRE_EMPHASIS_0:
2522 default:
2523 signal_levels |= DP_PRE_EMPHASIS_0;
2524 break;
2525 case DP_TRAIN_PRE_EMPHASIS_3_5:
2526 signal_levels |= DP_PRE_EMPHASIS_3_5;
2527 break;
2528 case DP_TRAIN_PRE_EMPHASIS_6:
2529 signal_levels |= DP_PRE_EMPHASIS_6;
2530 break;
2531 case DP_TRAIN_PRE_EMPHASIS_9_5:
2532 signal_levels |= DP_PRE_EMPHASIS_9_5;
2533 break;
2534 }
2535 return signal_levels;
2536}
2537
e3421a18
ZW		 2538/* Gen6's DP voltage swing and pre-emphasis control */
2539static uint32_t
2540intel_gen6_edp_signal_levels(uint8_t train_set)
2541{
3c5a62b5
YL		 2542 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2543 DP_TRAIN_PRE_EMPHASIS_MASK);
2544 switch (signal_levels) {
e3421a18 2545 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2546 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2547 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2548 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2549 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2550 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2551 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2552 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2553 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2554 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2555 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2556 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2557 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2558 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2559 default:
3c5a62b5
YL		 2560 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2561 "0x%x\n", signal_levels);
2562 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2563 }
2564}
2565
1a2eb460
KP		 2566/* Gen7's DP voltage swing and pre-emphasis control */
2567static uint32_t
2568intel_gen7_edp_signal_levels(uint8_t train_set)
2569{
2570 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2571 DP_TRAIN_PRE_EMPHASIS_MASK);
2572 switch (signal_levels) {
2573 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2574 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2575 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2576 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2577 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2578 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2579
2580 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2581 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2582 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2583 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2584
2585 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2586 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2587 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2588 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2589
2590 default:
2591 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2592 "0x%x\n", signal_levels);
2593 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2594 }
2595}
2596
d6c0d722
PZ		 2597/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2598static uint32_t
f0a3424e 2599intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2600{
d6c0d722
PZ		 2601 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2602 DP_TRAIN_PRE_EMPHASIS_MASK);
2603 switch (signal_levels) {
2604 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2605 return DDI_BUF_EMP_400MV_0DB_HSW;
2606 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2607 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2608 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2609 return DDI_BUF_EMP_400MV_6DB_HSW;
2610 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2611 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2612
d6c0d722
PZ		 2613 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2614 return DDI_BUF_EMP_600MV_0DB_HSW;
2615 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2616 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2617 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2618 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2619
d6c0d722
PZ		 2620 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2621 return DDI_BUF_EMP_800MV_0DB_HSW;
2622 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2623 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2624 default:
2625 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2626 "0x%x\n", signal_levels);
2627 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2628 }
a4fc5ed6
KP		 2629}
2630
8f93f4f1
PZ		 2631static uint32_t
2632intel_bdw_signal_levels(uint8_t train_set)
2633{
2634 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2635 DP_TRAIN_PRE_EMPHASIS_MASK);
2636 switch (signal_levels) {
2637 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2638 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2639 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2640 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2641 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2642 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2643
2644 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2645 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2646 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2647 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2648 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2649 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2650
2651 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2652 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2653 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2654 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2655
2656 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2657 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2658
2659 default:
2660 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2661 "0x%x\n", signal_levels);
2662 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2663 }
2664}
2665
f0a3424e
PZ		 2666/* Properly updates "DP" with the correct signal levels. */
2667static void
2668intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2669{
2670 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2671 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2672 struct drm_device *dev = intel_dig_port->base.base.dev;
2673 uint32_t signal_levels, mask;
2674 uint8_t train_set = intel_dp->train_set[0];
2675
8f93f4f1
PZ		 2676 if (IS_BROADWELL(dev)) {
2677 signal_levels = intel_bdw_signal_levels(train_set);
2678 mask = DDI_BUF_EMP_MASK;
2679 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2680 signal_levels = intel_hsw_signal_levels(train_set);
2681 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 2682 } else if (IS_CHERRYVIEW(dev)) {
2683 signal_levels = intel_chv_signal_levels(intel_dp);
2684 mask = 0;
e2fa6fba
P		 2685 } else if (IS_VALLEYVIEW(dev)) {
2686 signal_levels = intel_vlv_signal_levels(intel_dp);
2687 mask = 0;
bc7d38a4 2688 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2689 signal_levels = intel_gen7_edp_signal_levels(train_set);
2690 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2691 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2692 signal_levels = intel_gen6_edp_signal_levels(train_set);
2693 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2694 } else {
2695 signal_levels = intel_gen4_signal_levels(train_set);
2696 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2697 }
2698
2699 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2700
2701 *DP = (*DP & ~mask) | signal_levels;
2702}
2703
a4fc5ed6 2704static bool
ea5b213a 2705intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2706 uint32_t *DP,
58e10eb9 2707 uint8_t dp_train_pat)
a4fc5ed6 2708{
174edf1f
PZ		 2709 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2710 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2711 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2712 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2713 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2714 int ret, len;
a4fc5ed6 2715
22b8bf17 2716 if (HAS_DDI(dev)) {
3ab9c637 2717 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2718
2719 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2720 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2721 else
2722 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2723
2724 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2725 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2726 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2727 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2728
2729 break;
2730 case DP_TRAINING_PATTERN_1:
2731 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2732 break;
2733 case DP_TRAINING_PATTERN_2:
2734 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2735 break;
2736 case DP_TRAINING_PATTERN_3:
2737 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2738 break;
2739 }
174edf1f 2740 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2741
bc7d38a4 2742 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2743 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2744
2745 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2746 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2747 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2748 break;
2749 case DP_TRAINING_PATTERN_1:
70aff66c 2750 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2751 break;
2752 case DP_TRAINING_PATTERN_2:
70aff66c 2753 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2754 break;
2755 case DP_TRAINING_PATTERN_3:
2756 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2757 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2758 break;
2759 }
2760
2761 } else {
70aff66c 2762 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2763
2764 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2765 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2766 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2767 break;
2768 case DP_TRAINING_PATTERN_1:
70aff66c 2769 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2770 break;
2771 case DP_TRAINING_PATTERN_2:
70aff66c 2772 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2773 break;
2774 case DP_TRAINING_PATTERN_3:
2775 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2776 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2777 break;
2778 }
2779 }
2780
70aff66c 2781 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2782 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2783
2cdfe6c8
JN		 2784 buf[0] = dp_train_pat;
2785 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2786 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2787 /* don't write DP_TRAINING_LANEx_SET on disable */
2788 len = 1;
2789 } else {
2790 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2791 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2792 len = intel_dp->lane_count + 1;
47ea7542 2793 }
a4fc5ed6 2794
9d1a1031
JN		 2795 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2796 buf, len);
2cdfe6c8
JN		 2797
2798 return ret == len;
a4fc5ed6
KP		 2799}
2800
70aff66c
JN		 2801static bool
2802intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2803 uint8_t dp_train_pat)
2804{
953d22e8 2805 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2806 intel_dp_set_signal_levels(intel_dp, DP);
2807 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2808}
2809
2810static bool
2811intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2812 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2813{
2814 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2815 struct drm_device *dev = intel_dig_port->base.base.dev;
2816 struct drm_i915_private *dev_priv = dev->dev_private;
2817 int ret;
2818
2819 intel_get_adjust_train(intel_dp, link_status);
2820 intel_dp_set_signal_levels(intel_dp, DP);
2821
2822 I915_WRITE(intel_dp->output_reg, *DP);
2823 POSTING_READ(intel_dp->output_reg);
2824
9d1a1031
JN		 2825 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2826 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 2827
2828 return ret == intel_dp->lane_count;
2829}
2830
3ab9c637
ID		 2831static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2832{
2833 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2834 struct drm_device *dev = intel_dig_port->base.base.dev;
2835 struct drm_i915_private *dev_priv = dev->dev_private;
2836 enum port port = intel_dig_port->port;
2837 uint32_t val;
2838
2839 if (!HAS_DDI(dev))
2840 return;
2841
2842 val = I915_READ(DP_TP_CTL(port));
2843 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2844 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2845 I915_WRITE(DP_TP_CTL(port), val);
2846
2847 /*
2848 * On PORT_A we can have only eDP in SST mode. There the only reason
2849 * we need to set idle transmission mode is to work around a HW issue
2850 * where we enable the pipe while not in idle link-training mode.
2851 * In this case there is requirement to wait for a minimum number of
2852 * idle patterns to be sent.
2853 */
2854 if (port == PORT_A)
2855 return;
2856
2857 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2858 1))
2859 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2860}
2861
33a34e4e 2862/* Enable corresponding port and start training pattern 1 */
c19b0669 2863void
33a34e4e 2864intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2865{
da63a9f2 2866 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2867 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2868 int i;
2869 uint8_t voltage;
cdb0e95b 2870 int voltage_tries, loop_tries;
ea5b213a 2871 uint32_t DP = intel_dp->DP;
6aba5b6c 2872 uint8_t link_config[2];
a4fc5ed6 2873
affa9354 2874 if (HAS_DDI(dev))
c19b0669
PZ		 2875 intel_ddi_prepare_link_retrain(encoder);
2876
3cf2efb1 2877 /* Write the link configuration data */
6aba5b6c
JN		 2878 link_config[0] = intel_dp->link_bw;
2879 link_config[1] = intel_dp->lane_count;
2880 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2881 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 2882 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 2883
2884 link_config[0] = 0;
2885 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 2886 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2887
2888 DP |= DP_PORT_EN;
1a2eb460 2889
70aff66c
JN		 2890 /* clock recovery */
2891 if (!intel_dp_reset_link_train(intel_dp, &DP,
2892 DP_TRAINING_PATTERN_1 |
2893 DP_LINK_SCRAMBLING_DISABLE)) {
2894 DRM_ERROR("failed to enable link training\n");
2895 return;
2896 }
2897
a4fc5ed6 2898 voltage = 0xff;
cdb0e95b
KP		 2899 voltage_tries = 0;
2900 loop_tries = 0;
a4fc5ed6 2901 for (;;) {
70aff66c 2902 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2903
a7c9655f 2904 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2905 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2906 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2907 break;
93f62dad 2908 }
a4fc5ed6 2909
01916270 2910 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2911 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2912 break;
2913 }
2914
2915 /* Check to see if we've tried the max voltage */
2916 for (i = 0; i < intel_dp->lane_count; i++)
2917 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2918 break;
3b4f819d 2919 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2920 ++loop_tries;
2921 if (loop_tries == 5) {
3def84b3 2922 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2923 break;
2924 }
70aff66c
JN		 2925 intel_dp_reset_link_train(intel_dp, &DP,
2926 DP_TRAINING_PATTERN_1 |
2927 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2928 voltage_tries = 0;
2929 continue;
2930 }
a4fc5ed6 2931
3cf2efb1 2932 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2933 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2934 ++voltage_tries;
b06fbda3 2935 if (voltage_tries == 5) {
3def84b3 2936 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2937 break;
2938 }
2939 } else
2940 voltage_tries = 0;
2941 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2942
70aff66c
JN		 2943 /* Update training set as requested by target */
2944 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2945 DRM_ERROR("failed to update link training\n");
2946 break;
2947 }
a4fc5ed6
KP		 2948 }
2949
33a34e4e
JB		 2950 intel_dp->DP = DP;
2951}
2952
c19b0669 2953void
33a34e4e
JB		 2954intel_dp_complete_link_train(struct intel_dp *intel_dp)
2955{
33a34e4e 2956 bool channel_eq = false;
37f80975 2957 int tries, cr_tries;
33a34e4e 2958 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 2959 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2960
2961 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2962 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2963 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 2964
a4fc5ed6 2965 /* channel equalization */
70aff66c 2966 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2967 training_pattern |
70aff66c
JN		 2968 DP_LINK_SCRAMBLING_DISABLE)) {
2969 DRM_ERROR("failed to start channel equalization\n");
2970 return;
2971 }
2972
a4fc5ed6 2973 tries = 0;
37f80975 2974 cr_tries = 0;
a4fc5ed6
KP		 2975 channel_eq = false;
2976 for (;;) {
70aff66c 2977 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2978
37f80975
JB		 2979 if (cr_tries > 5) {
2980 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2981 break;
2982 }
2983
a7c9655f 2984 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2985 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2986 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2987 break;
70aff66c 2988 }
a4fc5ed6 2989
37f80975 2990 /* Make sure clock is still ok */
01916270 2991 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2992 intel_dp_start_link_train(intel_dp);
70aff66c 2993 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2994 training_pattern |
70aff66c 2995 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2996 cr_tries++;
2997 continue;
2998 }
2999
1ffdff13 3000 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3001 channel_eq = true;
3002 break;
3003 }
a4fc5ed6 3004
37f80975
JB		 3005 /* Try 5 times, then try clock recovery if that fails */
3006 if (tries > 5) {
3007 intel_dp_link_down(intel_dp);
3008 intel_dp_start_link_train(intel_dp);
70aff66c 3009 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3010 training_pattern |
70aff66c 3011 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3012 tries = 0;
3013 cr_tries++;
3014 continue;
3015 }
a4fc5ed6 3016
70aff66c
JN		 3017 /* Update training set as requested by target */
3018 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3019 DRM_ERROR("failed to update link training\n");
3020 break;
3021 }
3cf2efb1 3022 ++tries;
869184a6 3023 }
3cf2efb1 3024
3ab9c637
ID		 3025 intel_dp_set_idle_link_train(intel_dp);
3026
3027 intel_dp->DP = DP;
3028
d6c0d722 3029 if (channel_eq)
07f42258 3030 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3031
3ab9c637
ID		 3032}
3033
3034void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3035{
70aff66c 3036 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3037 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3038}
3039
3040static void
ea5b213a 3041intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3042{
da63a9f2 3043 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3044 enum port port = intel_dig_port->port;
da63a9f2 3045 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3046 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3047 struct intel_crtc *intel_crtc =
3048 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3049 uint32_t DP = intel_dp->DP;
a4fc5ed6 3050
c19b0669
PZ		 3051 /*
3052 * DDI code has a strict mode set sequence and we should try to respect
3053 * it, otherwise we might hang the machine in many different ways. So we
3054 * really should be disabling the port only on a complete crtc_disable
3055 * sequence. This function is just called under two conditions on DDI
3056 * code:
3057 * - Link train failed while doing crtc_enable, and on this case we
3058 * really should respect the mode set sequence and wait for a
3059 * crtc_disable.
3060 * - Someone turned the monitor off and intel_dp_check_link_status
3061 * called us. We don't need to disable the whole port on this case, so
3062 * when someone turns the monitor on again,
3063 * intel_ddi_prepare_link_retrain will take care of redoing the link
3064 * train.
3065 */
affa9354 3066 if (HAS_DDI(dev))
c19b0669
PZ		 3067 return;
3068
0c33d8d7 3069 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3070 return;
3071
28c97730 3072 DRM_DEBUG_KMS("\n");
32f9d658 3073
bc7d38a4 3074 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3075 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3076 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 3077 } else {
3078 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3079 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3080 }
fe255d00 3081 POSTING_READ(intel_dp->output_reg);
5eb08b69 3082
493a7081 3083 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3084 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3085 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3086
5bddd17f
EA		 3087 /* Hardware workaround: leaving our transcoder select
3088 * set to transcoder B while it's off will prevent the
3089 * corresponding HDMI output on transcoder A.
3090 *
3091 * Combine this with another hardware workaround:
3092 * transcoder select bit can only be cleared while the
3093 * port is enabled.
3094 */
3095 DP &= ~DP_PIPEB_SELECT;
3096 I915_WRITE(intel_dp->output_reg, DP);
3097
3098 /* Changes to enable or select take place the vblank
3099 * after being written.
3100 */
ff50afe9
DV		 3101 if (WARN_ON(crtc == NULL)) {
3102 /* We should never try to disable a port without a crtc
3103 * attached. For paranoia keep the code around for a
3104 * bit. */
31acbcc4
CW		 3105 POSTING_READ(intel_dp->output_reg);
3106 msleep(50);
3107 } else
ab527efc 3108 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3109 }
3110
832afda6 3111 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3112 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3113 POSTING_READ(intel_dp->output_reg);
f01eca2e 3114 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3115}
3116
26d61aad
KP		 3117static bool
3118intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3119{
a031d709
RV		 3120 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3121 struct drm_device *dev = dig_port->base.base.dev;
3122 struct drm_i915_private *dev_priv = dev->dev_private;
3123
577c7a50
DL		 3124 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3125
9d1a1031
JN		 3126 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3127 sizeof(intel_dp->dpcd)) < 0)
edb39244 3128 return false; /* aux transfer failed */
92fd8fd1 3129
577c7a50
DL		 3130 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3131 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3132 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3133
edb39244
AJ		 3134 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3135 return false; /* DPCD not present */
3136
2293bb5c
SK		 3137 /* Check if the panel supports PSR */
3138 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3139 if (is_edp(intel_dp)) {
9d1a1031
JN		 3140 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3141 intel_dp->psr_dpcd,
3142 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3143 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3144 dev_priv->psr.sink_support = true;
50003939 3145 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3146 }
50003939
JN		 3147 }
3148
06ea66b6
TP		 3149 /* Training Pattern 3 support */
3150 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3151 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3152 intel_dp->use_tps3 = true;
3153 DRM_DEBUG_KMS("Displayport TPS3 supported");
3154 } else
3155 intel_dp->use_tps3 = false;
3156
edb39244
AJ		 3157 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3158 DP_DWN_STRM_PORT_PRESENT))
3159 return true; /* native DP sink */
3160
3161 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3162 return true; /* no per-port downstream info */
3163
9d1a1031
JN		 3164 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3165 intel_dp->downstream_ports,
3166 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3167 return false; /* downstream port status fetch failed */
3168
3169 return true;
92fd8fd1
KP		 3170}
3171
0d198328
AJ		 3172static void
3173intel_dp_probe_oui(struct intel_dp *intel_dp)
3174{
3175 u8 buf[3];
3176
3177 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3178 return;
3179
24f3e092 3180 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3181
9d1a1031 3182 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3183 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3184 buf[0], buf[1], buf[2]);
3185
9d1a1031 3186 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3187 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3188 buf[0], buf[1], buf[2]);
351cfc34 3189
4be73780 3190 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3191}
3192
d2e216d0
RV		 3193int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3194{
3195 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3196 struct drm_device *dev = intel_dig_port->base.base.dev;
3197 struct intel_crtc *intel_crtc =
3198 to_intel_crtc(intel_dig_port->base.base.crtc);
3199 u8 buf[1];
3200
9d1a1031 3201 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3202 return -EAGAIN;
3203
3204 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3205 return -ENOTTY;
3206
9d1a1031
JN		 3207 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3208 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3209 return -EAGAIN;
3210
3211 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3212 intel_wait_for_vblank(dev, intel_crtc->pipe);
3213 intel_wait_for_vblank(dev, intel_crtc->pipe);
3214
9d1a1031 3215 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3216 return -EAGAIN;
3217
9d1a1031 3218 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3219 return 0;
3220}
3221
a60f0e38
JB		 3222static bool
3223intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3224{
9d1a1031
JN		 3225 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3226 DP_DEVICE_SERVICE_IRQ_VECTOR,
3227 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3228}
3229
3230static void
3231intel_dp_handle_test_request(struct intel_dp *intel_dp)
3232{
3233 /* NAK by default */
9d1a1031 3234 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3235}
3236
a4fc5ed6
KP		 3237/*
3238 * According to DP spec
3239 * 5.1.2:
3240 * 1. Read DPCD
3241 * 2. Configure link according to Receiver Capabilities
3242 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3243 * 4. Check link status on receipt of hot-plug interrupt
3244 */
3245
00c09d70 3246void
ea5b213a 3247intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3248{
da63a9f2 3249 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3250 u8 sink_irq_vector;
93f62dad 3251 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3252
da63a9f2 3253 if (!intel_encoder->connectors_active)
d2b996ac 3254 return;
59cd09e1 3255
da63a9f2 3256 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3257 return;
3258
92fd8fd1 3259 /* Try to read receiver status if the link appears to be up */
93f62dad 3260 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3261 return;
3262 }
3263
92fd8fd1 3264 /* Now read the DPCD to see if it's actually running */
26d61aad 3265 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3266 return;
3267 }
3268
a60f0e38
JB		 3269 /* Try to read the source of the interrupt */
3270 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3271 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3272 /* Clear interrupt source */
9d1a1031
JN		 3273 drm_dp_dpcd_writeb(&intel_dp->aux,
3274 DP_DEVICE_SERVICE_IRQ_VECTOR,
3275 sink_irq_vector);
a60f0e38
JB		 3276
3277 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3278 intel_dp_handle_test_request(intel_dp);
3279 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3280 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3281 }
3282
1ffdff13 3283 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3284 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 3285 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 3286 intel_dp_start_link_train(intel_dp);
3287 intel_dp_complete_link_train(intel_dp);
3ab9c637 3288 intel_dp_stop_link_train(intel_dp);
33a34e4e 3289 }
a4fc5ed6 3290}
a4fc5ed6 3291
caf9ab24 3292/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3293static enum drm_connector_status
26d61aad 3294intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3295{
caf9ab24 3296 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3297 uint8_t type;
3298
3299 if (!intel_dp_get_dpcd(intel_dp))
3300 return connector_status_disconnected;
3301
3302 /* if there's no downstream port, we're done */
3303 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3304 return connector_status_connected;
caf9ab24
AJ		 3305
3306 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3307 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3308 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3309 uint8_t reg;
9d1a1031
JN		 3310
3311 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3312 &reg, 1) < 0)
caf9ab24 3313 return connector_status_unknown;
9d1a1031 3314
23235177
AJ		 3315 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3316 : connector_status_disconnected;
caf9ab24
AJ		 3317 }
3318
3319 /* If no HPD, poke DDC gently */
0b99836f 3320 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3321 return connector_status_connected;
caf9ab24
AJ		 3322
3323 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3324 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3325 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3326 if (type == DP_DS_PORT_TYPE_VGA ||
3327 type == DP_DS_PORT_TYPE_NON_EDID)
3328 return connector_status_unknown;
3329 } else {
3330 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3331 DP_DWN_STRM_PORT_TYPE_MASK;
3332 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3333 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3334 return connector_status_unknown;
3335 }
caf9ab24
AJ		 3336
3337 /* Anything else is out of spec, warn and ignore */
3338 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3339 return connector_status_disconnected;
71ba9000
AJ		 3340}
3341
5eb08b69 3342static enum drm_connector_status
a9756bb5 3343ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3344{
30add22d 3345 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3346 struct drm_i915_private *dev_priv = dev->dev_private;
3347 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3348 enum drm_connector_status status;
3349
fe16d949
CW		 3350 /* Can't disconnect eDP, but you can close the lid... */
3351 if (is_edp(intel_dp)) {
30add22d 3352 status = intel_panel_detect(dev);
fe16d949
CW		 3353 if (status == connector_status_unknown)
3354 status = connector_status_connected;
3355 return status;
3356 }
01cb9ea6 3357
1b469639
DL		 3358 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3359 return connector_status_disconnected;
3360
26d61aad 3361 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3362}
3363
a4fc5ed6 3364static enum drm_connector_status
a9756bb5 3365g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3366{
30add22d 3367 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3368 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3369 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3370 uint32_t bit;
5eb08b69 3371
35aad75f
JB		 3372 /* Can't disconnect eDP, but you can close the lid... */
3373 if (is_edp(intel_dp)) {
3374 enum drm_connector_status status;
3375
3376 status = intel_panel_detect(dev);
3377 if (status == connector_status_unknown)
3378 status = connector_status_connected;
3379 return status;
3380 }
3381
232a6ee9
TP		 3382 if (IS_VALLEYVIEW(dev)) {
3383 switch (intel_dig_port->port) {
3384 case PORT_B:
3385 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3386 break;
3387 case PORT_C:
3388 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3389 break;
3390 case PORT_D:
3391 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3392 break;
3393 default:
3394 return connector_status_unknown;
3395 }
3396 } else {
3397 switch (intel_dig_port->port) {
3398 case PORT_B:
3399 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3400 break;
3401 case PORT_C:
3402 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3403 break;
3404 case PORT_D:
3405 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3406 break;
3407 default:
3408 return connector_status_unknown;
3409 }
a4fc5ed6
KP		 3410 }
3411
10f76a38 3412 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3413 return connector_status_disconnected;
3414
26d61aad 3415 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3416}
3417
8c241fef
KP		 3418static struct edid *
3419intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3420{
9cd300e0 3421 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3422
9cd300e0
JN		 3423 /* use cached edid if we have one */
3424 if (intel_connector->edid) {
9cd300e0
JN		 3425 /* invalid edid */
3426 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3427 return NULL;
3428
55e9edeb 3429 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3430 }
8c241fef 3431
9cd300e0 3432 return drm_get_edid(connector, adapter);
8c241fef
KP		 3433}
3434
3435static int
3436intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3437{
9cd300e0 3438 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3439
9cd300e0
JN		 3440 /* use cached edid if we have one */
3441 if (intel_connector->edid) {
3442 /* invalid edid */
3443 if (IS_ERR(intel_connector->edid))
3444 return 0;
3445
3446 return intel_connector_update_modes(connector,
3447 intel_connector->edid);
d6f24d0f
JB		 3448 }
3449
9cd300e0 3450 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3451}
3452
a9756bb5
ZW		 3453static enum drm_connector_status
3454intel_dp_detect(struct drm_connector *connector, bool force)
3455{
3456 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3457 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3458 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3459 struct drm_device *dev = connector->dev;
c8c8fb33 3460 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3461 enum drm_connector_status status;
671dedd2 3462 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3463 struct edid *edid = NULL;
3464
c8c8fb33
PZ		 3465 intel_runtime_pm_get(dev_priv);
3466
671dedd2
ID		 3467 power_domain = intel_display_port_power_domain(intel_encoder);
3468 intel_display_power_get(dev_priv, power_domain);
3469
164c8598
CW		 3470 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3471 connector->base.id, drm_get_connector_name(connector));
3472
a9756bb5
ZW		 3473 intel_dp->has_audio = false;
3474
3475 if (HAS_PCH_SPLIT(dev))
3476 status = ironlake_dp_detect(intel_dp);
3477 else
3478 status = g4x_dp_detect(intel_dp);
1b9be9d0 3479
a9756bb5 3480 if (status != connector_status_connected)
c8c8fb33 3481 goto out;
a9756bb5 3482
0d198328
AJ		 3483 intel_dp_probe_oui(intel_dp);
3484
c3e5f67b
DV		 3485 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3486 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3487 } else {
0b99836f 3488 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3489 if (edid) {
3490 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3491 kfree(edid);
3492 }
a9756bb5
ZW		 3493 }
3494
d63885da
PZ		 3495 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3496 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3497 status = connector_status_connected;
3498
3499out:
671dedd2
ID		 3500 intel_display_power_put(dev_priv, power_domain);
3501
c8c8fb33 3502 intel_runtime_pm_put(dev_priv);
671dedd2 3503
c8c8fb33 3504 return status;
a4fc5ed6
KP		 3505}
3506
3507static int intel_dp_get_modes(struct drm_connector *connector)
3508{
df0e9248 3509 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3510 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3511 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3512 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3513 struct drm_device *dev = connector->dev;
671dedd2
ID		 3514 struct drm_i915_private *dev_priv = dev->dev_private;
3515 enum intel_display_power_domain power_domain;
32f9d658 3516 int ret;
a4fc5ed6
KP		 3517
3518 /* We should parse the EDID data and find out if it has an audio sink
3519 */
3520
671dedd2
ID		 3521 power_domain = intel_display_port_power_domain(intel_encoder);
3522 intel_display_power_get(dev_priv, power_domain);
3523
0b99836f 3524 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3525 intel_display_power_put(dev_priv, power_domain);
f8779fda 3526 if (ret)
32f9d658
ZW		 3527 return ret;
3528
f8779fda 3529 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3530 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3531 struct drm_display_mode *mode;
dd06f90e
JN		 3532 mode = drm_mode_duplicate(dev,
3533 intel_connector->panel.fixed_mode);
f8779fda 3534 if (mode) {
32f9d658
ZW		 3535 drm_mode_probed_add(connector, mode);
3536 return 1;
3537 }
3538 }
3539 return 0;
a4fc5ed6
KP		 3540}
3541
1aad7ac0
CW		 3542static bool
3543intel_dp_detect_audio(struct drm_connector *connector)
3544{
3545 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3546 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3547 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3548 struct drm_device *dev = connector->dev;
3549 struct drm_i915_private *dev_priv = dev->dev_private;
3550 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3551 struct edid *edid;
3552 bool has_audio = false;
3553
671dedd2
ID		 3554 power_domain = intel_display_port_power_domain(intel_encoder);
3555 intel_display_power_get(dev_priv, power_domain);
3556
0b99836f 3557 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3558 if (edid) {
3559 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3560 kfree(edid);
3561 }
3562
671dedd2
ID		 3563 intel_display_power_put(dev_priv, power_domain);
3564
1aad7ac0
CW		 3565 return has_audio;
3566}
3567
f684960e
CW		 3568static int
3569intel_dp_set_property(struct drm_connector *connector,
3570 struct drm_property *property,
3571 uint64_t val)
3572{
e953fd7b 3573 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3574 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3575 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3576 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3577 int ret;
3578
662595df 3579 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3580 if (ret)
3581 return ret;
3582
3f43c48d 3583 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3584 int i = val;
3585 bool has_audio;
3586
3587 if (i == intel_dp->force_audio)
f684960e
CW		 3588 return 0;
3589
1aad7ac0 3590 intel_dp->force_audio = i;
f684960e 3591
c3e5f67b 3592 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3593 has_audio = intel_dp_detect_audio(connector);
3594 else
c3e5f67b 3595 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3596
3597 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3598 return 0;
3599
1aad7ac0 3600 intel_dp->has_audio = has_audio;
f684960e
CW		 3601 goto done;
3602 }
3603
e953fd7b 3604 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3605 bool old_auto = intel_dp->color_range_auto;
3606 uint32_t old_range = intel_dp->color_range;
3607
55bc60db
VS		 3608 switch (val) {
3609 case INTEL_BROADCAST_RGB_AUTO:
3610 intel_dp->color_range_auto = true;
3611 break;
3612 case INTEL_BROADCAST_RGB_FULL:
3613 intel_dp->color_range_auto = false;
3614 intel_dp->color_range = 0;
3615 break;
3616 case INTEL_BROADCAST_RGB_LIMITED:
3617 intel_dp->color_range_auto = false;
3618 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3619 break;
3620 default:
3621 return -EINVAL;
3622 }
ae4edb80
DV		 3623
3624 if (old_auto == intel_dp->color_range_auto &&
3625 old_range == intel_dp->color_range)
3626 return 0;
3627
e953fd7b
CW		 3628 goto done;
3629 }
3630
53b41837
YN		 3631 if (is_edp(intel_dp) &&
3632 property == connector->dev->mode_config.scaling_mode_property) {
3633 if (val == DRM_MODE_SCALE_NONE) {
3634 DRM_DEBUG_KMS("no scaling not supported\n");
3635 return -EINVAL;
3636 }
3637
3638 if (intel_connector->panel.fitting_mode == val) {
3639 /* the eDP scaling property is not changed */
3640 return 0;
3641 }
3642 intel_connector->panel.fitting_mode = val;
3643
3644 goto done;
3645 }
3646
f684960e
CW		 3647 return -EINVAL;
3648
3649done:
c0c36b94
CW		 3650 if (intel_encoder->base.crtc)
3651 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3652
3653 return 0;
3654}
3655
a4fc5ed6 3656static void
73845adf 3657intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3658{
1d508706 3659 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3660
9cd300e0
JN		 3661 if (!IS_ERR_OR_NULL(intel_connector->edid))
3662 kfree(intel_connector->edid);
3663
acd8db10
PZ		 3664 /* Can't call is_edp() since the encoder may have been destroyed
3665 * already. */
3666 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3667 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3668
a4fc5ed6 3669 drm_connector_cleanup(connector);
55f78c43 3670 kfree(connector);
a4fc5ed6
KP		 3671}
3672
00c09d70 3673void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3674{
da63a9f2
PZ		 3675 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3676 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3677 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 3678
0b99836f 3679 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
24d05927 3680 drm_encoder_cleanup(encoder);
bd943159
KP		 3681 if (is_edp(intel_dp)) {
3682 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3683 mutex_lock(&dev->mode_config.mutex);
4be73780 3684 edp_panel_vdd_off_sync(intel_dp);
bd173813 3685 mutex_unlock(&dev->mode_config.mutex);
bd943159 3686 }
da63a9f2 3687 kfree(intel_dig_port);
24d05927
DV		 3688}
3689
a4fc5ed6 3690static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3691 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3692 .detect = intel_dp_detect,
3693 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3694 .set_property = intel_dp_set_property,
73845adf 3695 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3696};
3697
3698static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3699 .get_modes = intel_dp_get_modes,
3700 .mode_valid = intel_dp_mode_valid,
df0e9248 3701 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3702};
3703
a4fc5ed6 3704static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3705 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3706};
3707
995b6762 3708static void
21d40d37 3709intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3710{
fa90ecef 3711 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3712
885a5014 3713 intel_dp_check_link_status(intel_dp);
c8110e52 3714}
6207937d 3715
e3421a18
ZW		 3716/* Return which DP Port should be selected for Transcoder DP control */
3717int
0206e353 3718intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3719{
3720 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3721 struct intel_encoder *intel_encoder;
3722 struct intel_dp *intel_dp;
e3421a18 3723
fa90ecef
PZ		 3724 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3725 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3726
fa90ecef
PZ		 3727 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3728 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3729 return intel_dp->output_reg;
e3421a18 3730 }
ea5b213a 3731
e3421a18
ZW		 3732 return -1;
3733}
3734
36e83a18 3735/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3736bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3737{
3738 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3739 union child_device_config *p_child;
36e83a18 3740 int i;
5d8a7752
VS		 3741 static const short port_mapping[] = {
3742 [PORT_B] = PORT_IDPB,
3743 [PORT_C] = PORT_IDPC,
3744 [PORT_D] = PORT_IDPD,
3745 };
36e83a18 3746
3b32a35b
VS		 3747 if (port == PORT_A)
3748 return true;
3749
41aa3448 3750 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3751 return false;
3752
41aa3448
RV		 3753 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3754 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3755
5d8a7752 3756 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3757 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3758 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3759 return true;
3760 }
3761 return false;
3762}
3763
f684960e
CW		 3764static void
3765intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3766{
53b41837
YN		 3767 struct intel_connector *intel_connector = to_intel_connector(connector);
3768
3f43c48d 3769 intel_attach_force_audio_property(connector);
e953fd7b 3770 intel_attach_broadcast_rgb_property(connector);
55bc60db 3771 intel_dp->color_range_auto = true;
53b41837
YN		 3772
3773 if (is_edp(intel_dp)) {
3774 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3775 drm_object_attach_property(
3776 &connector->base,
53b41837 3777 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3778 DRM_MODE_SCALE_ASPECT);
3779 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3780 }
f684960e
CW		 3781}
3782
dada1a9f
ID		 3783static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3784{
3785 intel_dp->last_power_cycle = jiffies;
3786 intel_dp->last_power_on = jiffies;
3787 intel_dp->last_backlight_off = jiffies;
3788}
3789
67a54566
DV		 3790static void
3791intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3792 struct intel_dp *intel_dp,
3793 struct edp_power_seq *out)
67a54566
DV		 3794{
3795 struct drm_i915_private *dev_priv = dev->dev_private;
3796 struct edp_power_seq cur, vbt, spec, final;
3797 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3798 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3799
3800 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3801 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3802 pp_on_reg = PCH_PP_ON_DELAYS;
3803 pp_off_reg = PCH_PP_OFF_DELAYS;
3804 pp_div_reg = PCH_PP_DIVISOR;
3805 } else {
bf13e81b
JN		 3806 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3807
3808 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3809 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3810 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3811 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3812 }
67a54566
DV		 3813
3814 /* Workaround: Need to write PP_CONTROL with the unlock key as
3815 * the very first thing. */
453c5420 3816 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3817 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3818
453c5420
JB		 3819 pp_on = I915_READ(pp_on_reg);
3820 pp_off = I915_READ(pp_off_reg);
3821 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3822
3823 /* Pull timing values out of registers */
3824 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3825 PANEL_POWER_UP_DELAY_SHIFT;
3826
3827 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3828 PANEL_LIGHT_ON_DELAY_SHIFT;
3829
3830 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3831 PANEL_LIGHT_OFF_DELAY_SHIFT;
3832
3833 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3834 PANEL_POWER_DOWN_DELAY_SHIFT;
3835
3836 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3837 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3838
3839 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3840 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3841
41aa3448 3842 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3843
3844 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3845 * our hw here, which are all in 100usec. */
3846 spec.t1_t3 = 210 * 10;
3847 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3848 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3849 spec.t10 = 500 * 10;
3850 /* This one is special and actually in units of 100ms, but zero
3851 * based in the hw (so we need to add 100 ms). But the sw vbt
3852 * table multiplies it with 1000 to make it in units of 100usec,
3853 * too. */
3854 spec.t11_t12 = (510 + 100) * 10;
3855
3856 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3857 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3858
3859 /* Use the max of the register settings and vbt. If both are
3860 * unset, fall back to the spec limits. */
3861#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3862 spec.field : \
3863 max(cur.field, vbt.field))
3864 assign_final(t1_t3);
3865 assign_final(t8);
3866 assign_final(t9);
3867 assign_final(t10);
3868 assign_final(t11_t12);
3869#undef assign_final
3870
3871#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3872 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3873 intel_dp->backlight_on_delay = get_delay(t8);
3874 intel_dp->backlight_off_delay = get_delay(t9);
3875 intel_dp->panel_power_down_delay = get_delay(t10);
3876 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3877#undef get_delay
3878
f30d26e4
JN		 3879 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3880 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3881 intel_dp->panel_power_cycle_delay);
3882
3883 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3884 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3885
3886 if (out)
3887 *out = final;
3888}
3889
3890static void
3891intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3892 struct intel_dp *intel_dp,
3893 struct edp_power_seq *seq)
3894{
3895 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3896 u32 pp_on, pp_off, pp_div, port_sel = 0;
3897 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3898 int pp_on_reg, pp_off_reg, pp_div_reg;
3899
3900 if (HAS_PCH_SPLIT(dev)) {
3901 pp_on_reg = PCH_PP_ON_DELAYS;
3902 pp_off_reg = PCH_PP_OFF_DELAYS;
3903 pp_div_reg = PCH_PP_DIVISOR;
3904 } else {
bf13e81b
JN		 3905 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3906
3907 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3908 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3909 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3910 }
3911
b2f19d1a
PZ		 3912 /*
3913 * And finally store the new values in the power sequencer. The
3914 * backlight delays are set to 1 because we do manual waits on them. For
3915 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3916 * we'll end up waiting for the backlight off delay twice: once when we
3917 * do the manual sleep, and once when we disable the panel and wait for
3918 * the PP_STATUS bit to become zero.
3919 */
f30d26e4 3920 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 3921 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3922 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 3923 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3924 /* Compute the divisor for the pp clock, simply match the Bspec
3925 * formula. */
453c5420 3926 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3927 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3928 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3929
3930 /* Haswell doesn't have any port selection bits for the panel
3931 * power sequencer any more. */
bc7d38a4 3932 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3933 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3934 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3935 else
3936 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3937 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3938 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3939 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3940 else
a24c144c 3941 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3942 }
3943
453c5420
JB		 3944 pp_on |= port_sel;
3945
3946 I915_WRITE(pp_on_reg, pp_on);
3947 I915_WRITE(pp_off_reg, pp_off);
3948 I915_WRITE(pp_div_reg, pp_div);
67a54566 3949
67a54566 3950 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3951 I915_READ(pp_on_reg),
3952 I915_READ(pp_off_reg),
3953 I915_READ(pp_div_reg));
f684960e
CW		 3954}
3955
439d7ac0
PB		 3956void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
3957{
3958 struct drm_i915_private *dev_priv = dev->dev_private;
3959 struct intel_encoder *encoder;
3960 struct intel_dp *intel_dp = NULL;
3961 struct intel_crtc_config *config = NULL;
3962 struct intel_crtc *intel_crtc = NULL;
3963 struct intel_connector *intel_connector = dev_priv->drrs.connector;
3964 u32 reg, val;
3965 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
3966
3967 if (refresh_rate <= 0) {
3968 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
3969 return;
3970 }
3971
3972 if (intel_connector == NULL) {
3973 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
3974 return;
3975 }
3976
3977 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
3978 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
3979 return;
3980 }
3981
3982 encoder = intel_attached_encoder(&intel_connector->base);
3983 intel_dp = enc_to_intel_dp(&encoder->base);
3984 intel_crtc = encoder->new_crtc;
3985
3986 if (!intel_crtc) {
3987 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
3988 return;
3989 }
3990
3991 config = &intel_crtc->config;
3992
3993 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
3994 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
3995 return;
3996 }
3997
3998 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
3999 index = DRRS_LOW_RR;
4000
4001 if (index == intel_dp->drrs_state.refresh_rate_type) {
4002 DRM_DEBUG_KMS(
4003 "DRRS requested for previously set RR...ignoring\n");
4004 return;
4005 }
4006
4007 if (!intel_crtc->active) {
4008 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4009 return;
4010 }
4011
4012 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4013 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4014 val = I915_READ(reg);
4015 if (index > DRRS_HIGH_RR) {
4016 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4017 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
4018 } else {
4019 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4020 }
4021 I915_WRITE(reg, val);
4022 }
4023
4024 /*
4025 * mutex taken to ensure that there is no race between differnt
4026 * drrs calls trying to update refresh rate. This scenario may occur
4027 * in future when idleness detection based DRRS in kernel and
4028 * possible calls from user space to set differnt RR are made.
4029 */
4030
4031 mutex_lock(&intel_dp->drrs_state.mutex);
4032
4033 intel_dp->drrs_state.refresh_rate_type = index;
4034
4035 mutex_unlock(&intel_dp->drrs_state.mutex);
4036
4037 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4038}
4039
4f9db5b5
PB		 4040static struct drm_display_mode *
4041intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4042 struct intel_connector *intel_connector,
4043 struct drm_display_mode *fixed_mode)
4044{
4045 struct drm_connector *connector = &intel_connector->base;
4046 struct intel_dp *intel_dp = &intel_dig_port->dp;
4047 struct drm_device *dev = intel_dig_port->base.base.dev;
4048 struct drm_i915_private *dev_priv = dev->dev_private;
4049 struct drm_display_mode *downclock_mode = NULL;
4050
4051 if (INTEL_INFO(dev)->gen <= 6) {
4052 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4053 return NULL;
4054 }
4055
4056 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4057 DRM_INFO("VBT doesn't support DRRS\n");
4058 return NULL;
4059 }
4060
4061 downclock_mode = intel_find_panel_downclock
4062 (dev, fixed_mode, connector);
4063
4064 if (!downclock_mode) {
4065 DRM_INFO("DRRS not supported\n");
4066 return NULL;
4067 }
4068
439d7ac0
PB		 4069 dev_priv->drrs.connector = intel_connector;
4070
4071 mutex_init(&intel_dp->drrs_state.mutex);
4072
4f9db5b5
PB		 4073 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4074
4075 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4076 DRM_INFO("seamless DRRS supported for eDP panel.\n");
4077 return downclock_mode;
4078}
4079
ed92f0b2 4080static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4081 struct intel_connector *intel_connector,
4082 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4083{
4084 struct drm_connector *connector = &intel_connector->base;
4085 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4086 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4087 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4088 struct drm_i915_private *dev_priv = dev->dev_private;
4089 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4090 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4091 bool has_dpcd;
4092 struct drm_display_mode *scan;
4093 struct edid *edid;
4094
4f9db5b5
PB		 4095 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4096
ed92f0b2
PZ		 4097 if (!is_edp(intel_dp))
4098 return true;
4099
63635217
PZ		 4100 /* The VDD bit needs a power domain reference, so if the bit is already
4101 * enabled when we boot, grab this reference. */
4102 if (edp_have_panel_vdd(intel_dp)) {
4103 enum intel_display_power_domain power_domain;
4104 power_domain = intel_display_port_power_domain(intel_encoder);
4105 intel_display_power_get(dev_priv, power_domain);
4106 }
4107
ed92f0b2 4108 /* Cache DPCD and EDID for edp. */
24f3e092 4109 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4110 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 4111 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4112
4113 if (has_dpcd) {
4114 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4115 dev_priv->no_aux_handshake =
4116 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4117 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4118 } else {
4119 /* if this fails, presume the device is a ghost */
4120 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4121 return false;
4122 }
4123
4124 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 4125 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 4126
060c8778 4127 mutex_lock(&dev->mode_config.mutex);
0b99836f 4128 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4129 if (edid) {
4130 if (drm_add_edid_modes(connector, edid)) {
4131 drm_mode_connector_update_edid_property(connector,
4132 edid);
4133 drm_edid_to_eld(connector, edid);
4134 } else {
4135 kfree(edid);
4136 edid = ERR_PTR(-EINVAL);
4137 }
4138 } else {
4139 edid = ERR_PTR(-ENOENT);
4140 }
4141 intel_connector->edid = edid;
4142
4143 /* prefer fixed mode from EDID if available */
4144 list_for_each_entry(scan, &connector->probed_modes, head) {
4145 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4146 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4147 downclock_mode = intel_dp_drrs_init(
4148 intel_dig_port,
4149 intel_connector, fixed_mode);
ed92f0b2
PZ		 4150 break;
4151 }
4152 }
4153
4154 /* fallback to VBT if available for eDP */
4155 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4156 fixed_mode = drm_mode_duplicate(dev,
4157 dev_priv->vbt.lfp_lvds_vbt_mode);
4158 if (fixed_mode)
4159 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4160 }
060c8778 4161 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4162
4f9db5b5 4163 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
ed92f0b2
PZ		 4164 intel_panel_setup_backlight(connector);
4165
4166 return true;
4167}
4168
16c25533 4169bool
f0fec3f2
PZ		 4170intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4171 struct intel_connector *intel_connector)
a4fc5ed6 4172{
f0fec3f2
PZ		 4173 struct drm_connector *connector = &intel_connector->base;
4174 struct intel_dp *intel_dp = &intel_dig_port->dp;
4175 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4176 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4177 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4178 enum port port = intel_dig_port->port;
0095e6dc 4179 struct edp_power_seq power_seq = { 0 };
0b99836f 4180 int type;
a4fc5ed6 4181
ec5b01dd
DL		 4182 /* intel_dp vfuncs */
4183 if (IS_VALLEYVIEW(dev))
4184 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4185 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4186 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4187 else if (HAS_PCH_SPLIT(dev))
4188 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4189 else
4190 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4191
153b1100
DL		 4192 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4193
0767935e
DV		 4194 /* Preserve the current hw state. */
4195 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4196 intel_dp->attached_connector = intel_connector;
3d3dc149 4197
3b32a35b 4198 if (intel_dp_is_edp(dev, port))
b329530c 4199 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4200 else
4201 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4202
f7d24902
ID		 4203 /*
4204 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4205 * for DP the encoder type can be set by the caller to
4206 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4207 */
4208 if (type == DRM_MODE_CONNECTOR_eDP)
4209 intel_encoder->type = INTEL_OUTPUT_EDP;
4210
e7281eab
ID		 4211 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4212 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4213 port_name(port));
4214
b329530c 4215 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4216 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4217
a4fc5ed6
KP		 4218 connector->interlace_allowed = true;
4219 connector->doublescan_allowed = 0;
4220
f0fec3f2 4221 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4222 edp_panel_vdd_work);
a4fc5ed6 4223
df0e9248 4224 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 4225 drm_sysfs_connector_add(connector);
4226
affa9354 4227 if (HAS_DDI(dev))
bcbc889b
PZ		 4228 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4229 else
4230 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 4231 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 4232
0b99836f 4233 /* Set up the hotplug pin. */
ab9d7c30
PZ		 4234 switch (port) {
4235 case PORT_A:
1d843f9d 4236 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 4237 break;
4238 case PORT_B:
1d843f9d 4239 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 4240 break;
4241 case PORT_C:
1d843f9d 4242 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 4243 break;
4244 case PORT_D:
1d843f9d 4245 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 4246 break;
4247 default:
ad1c0b19 4248 BUG();
5eb08b69
ZW		 4249 }
4250
dada1a9f
ID		 4251 if (is_edp(intel_dp)) {
4252 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 4253 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 4254 }
0095e6dc 4255
9d1a1031 4256 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 4257
2b28bb1b
RV		 4258 intel_dp->psr_setup_done = false;
4259
0095e6dc 4260 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
0b99836f 4261 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
15b1d171
PZ		 4262 if (is_edp(intel_dp)) {
4263 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4264 mutex_lock(&dev->mode_config.mutex);
4be73780 4265 edp_panel_vdd_off_sync(intel_dp);
15b1d171
PZ		 4266 mutex_unlock(&dev->mode_config.mutex);
4267 }
b2f246a8
PZ		 4268 drm_sysfs_connector_remove(connector);
4269 drm_connector_cleanup(connector);
16c25533 4270 return false;
b2f246a8 4271 }
32f9d658 4272
f684960e
CW		 4273 intel_dp_add_properties(intel_dp, connector);
4274
a4fc5ed6
KP		 4275 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4276 * 0xd. Failure to do so will result in spurious interrupts being
4277 * generated on the port when a cable is not attached.
4278 */
4279 if (IS_G4X(dev) && !IS_GM45(dev)) {
4280 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4281 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4282 }
16c25533
PZ		 4283
4284 return true;
a4fc5ed6 4285}
f0fec3f2
PZ		 4286
4287void
4288intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4289{
4290 struct intel_digital_port *intel_dig_port;
4291 struct intel_encoder *intel_encoder;
4292 struct drm_encoder *encoder;
4293 struct intel_connector *intel_connector;
4294
b14c5679 4295 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 4296 if (!intel_dig_port)
4297 return;
4298
b14c5679 4299 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 4300 if (!intel_connector) {
4301 kfree(intel_dig_port);
4302 return;
4303 }
4304
4305 intel_encoder = &intel_dig_port->base;
4306 encoder = &intel_encoder->base;
4307
4308 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4309 DRM_MODE_ENCODER_TMDS);
4310
5bfe2ac0 4311 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 4312 intel_encoder->disable = intel_disable_dp;
00c09d70 4313 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4314 intel_encoder->get_config = intel_dp_get_config;
e4a1d846
CML		 4315 if (IS_CHERRYVIEW(dev)) {
4316 intel_encoder->pre_enable = chv_pre_enable_dp;
4317 intel_encoder->enable = vlv_enable_dp;
580d3811 4318 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 4319 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4320 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4321 intel_encoder->pre_enable = vlv_pre_enable_dp;
4322 intel_encoder->enable = vlv_enable_dp;
49277c31 4323 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4324 } else {
ecff4f3b
JN		 4325 intel_encoder->pre_enable = g4x_pre_enable_dp;
4326 intel_encoder->enable = g4x_enable_dp;
49277c31 4327 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4328 }
f0fec3f2 4329
174edf1f 4330 intel_dig_port->port = port;
f0fec3f2
PZ		 4331 intel_dig_port->dp.output_reg = output_reg;
4332
00c09d70 4333 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 4334 if (IS_CHERRYVIEW(dev)) {
4335 if (port == PORT_D)
4336 intel_encoder->crtc_mask = 1 << 2;
4337 else
4338 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4339 } else {
4340 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4341 }
bc079e8b 4342 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4343 intel_encoder->hot_plug = intel_dp_hot_plug;
4344
15b1d171
PZ		 4345 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4346 drm_encoder_cleanup(encoder);
4347 kfree(intel_dig_port);
b2f246a8 4348 kfree(intel_connector);
15b1d171 4349 }
f0fec3f2 4350}
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