]>
Commit | Line | Data |
---|---|---|
a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Keith Packard <keithp@keithp.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
2d1a8a48 | 30 | #include <linux/export.h> |
611032bf | 31 | #include <linux/types.h> |
01527b31 CT |
32 | #include <linux/notifier.h> |
33 | #include <linux/reboot.h> | |
611032bf | 34 | #include <asm/byteorder.h> |
760285e7 | 35 | #include <drm/drmP.h> |
c6f95f27 | 36 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
37 | #include <drm/drm_crtc.h> |
38 | #include <drm/drm_crtc_helper.h> | |
39 | #include <drm/drm_edid.h> | |
a4fc5ed6 | 40 | #include "intel_drv.h" |
760285e7 | 41 | #include <drm/i915_drm.h> |
a4fc5ed6 | 42 | #include "i915_drv.h" |
a4fc5ed6 | 43 | |
a4fc5ed6 KP |
44 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
45 | ||
559be30c TP |
46 | /* Compliance test status bits */ |
47 | #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 | |
48 | #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
49 | #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
50 | #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) | |
51 | ||
9dd4ffdf | 52 | struct dp_link_dpll { |
840b32b7 | 53 | int clock; |
9dd4ffdf CML |
54 | struct dpll dpll; |
55 | }; | |
56 | ||
57 | static const struct dp_link_dpll gen4_dpll[] = { | |
840b32b7 | 58 | { 162000, |
9dd4ffdf | 59 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
840b32b7 | 60 | { 270000, |
9dd4ffdf CML |
61 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
62 | }; | |
63 | ||
64 | static const struct dp_link_dpll pch_dpll[] = { | |
840b32b7 | 65 | { 162000, |
9dd4ffdf | 66 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
840b32b7 | 67 | { 270000, |
9dd4ffdf CML |
68 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
69 | }; | |
70 | ||
65ce4bf5 | 71 | static const struct dp_link_dpll vlv_dpll[] = { |
840b32b7 | 72 | { 162000, |
58f6e632 | 73 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
840b32b7 | 74 | { 270000, |
65ce4bf5 CML |
75 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
76 | }; | |
77 | ||
ef9348c8 CML |
78 | /* |
79 | * CHV supports eDP 1.4 that have more link rates. | |
80 | * Below only provides the fixed rate but exclude variable rate. | |
81 | */ | |
82 | static const struct dp_link_dpll chv_dpll[] = { | |
83 | /* | |
84 | * CHV requires to program fractional division for m2. | |
85 | * m2 is stored in fixed point format using formula below | |
86 | * (m2_int << 22) | m2_fraction | |
87 | */ | |
840b32b7 | 88 | { 162000, /* m2_int = 32, m2_fraction = 1677722 */ |
ef9348c8 | 89 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
840b32b7 | 90 | { 270000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 | 91 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
840b32b7 | 92 | { 540000, /* m2_int = 27, m2_fraction = 0 */ |
ef9348c8 CML |
93 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
94 | }; | |
637a9c63 | 95 | |
64987fc5 SJ |
96 | static const int bxt_rates[] = { 162000, 216000, 243000, 270000, |
97 | 324000, 432000, 540000 }; | |
637a9c63 | 98 | static const int skl_rates[] = { 162000, 216000, 270000, |
f4896f15 | 99 | 324000, 432000, 540000 }; |
d907b665 RV |
100 | static const int cnl_rates[] = { 162000, 216000, 270000, |
101 | 324000, 432000, 540000, | |
102 | 648000, 810000 }; | |
f4896f15 | 103 | static const int default_rates[] = { 162000, 270000, 540000 }; |
ef9348c8 | 104 | |
cfcb0fc9 | 105 | /** |
1853a9da | 106 | * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
cfcb0fc9 JB |
107 | * @intel_dp: DP struct |
108 | * | |
109 | * If a CPU or PCH DP output is attached to an eDP panel, this function | |
110 | * will return true, and false otherwise. | |
111 | */ | |
1853a9da | 112 | bool intel_dp_is_edp(struct intel_dp *intel_dp) |
cfcb0fc9 | 113 | { |
da63a9f2 PZ |
114 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
115 | ||
116 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; | |
cfcb0fc9 JB |
117 | } |
118 | ||
68b4d824 | 119 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
cfcb0fc9 | 120 | { |
68b4d824 ID |
121 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
122 | ||
123 | return intel_dig_port->base.base.dev; | |
cfcb0fc9 JB |
124 | } |
125 | ||
df0e9248 CW |
126 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
127 | { | |
fa90ecef | 128 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
129 | } |
130 | ||
ea5b213a | 131 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
1e0560e0 | 132 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp); |
4be73780 | 133 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
093e3f13 | 134 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp); |
a8c3344e VS |
135 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
136 | enum pipe pipe); | |
f21a2198 | 137 | static void intel_dp_unset_edid(struct intel_dp *intel_dp); |
a4fc5ed6 | 138 | |
68f357cb JN |
139 | static int intel_dp_num_rates(u8 link_bw_code) |
140 | { | |
141 | switch (link_bw_code) { | |
142 | default: | |
143 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", | |
144 | link_bw_code); | |
145 | case DP_LINK_BW_1_62: | |
146 | return 1; | |
147 | case DP_LINK_BW_2_7: | |
148 | return 2; | |
149 | case DP_LINK_BW_5_4: | |
150 | return 3; | |
151 | } | |
152 | } | |
153 | ||
154 | /* update sink rates from dpcd */ | |
155 | static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) | |
156 | { | |
157 | int i, num_rates; | |
158 | ||
159 | num_rates = intel_dp_num_rates(intel_dp->dpcd[DP_MAX_LINK_RATE]); | |
160 | ||
161 | for (i = 0; i < num_rates; i++) | |
162 | intel_dp->sink_rates[i] = default_rates[i]; | |
163 | ||
164 | intel_dp->num_sink_rates = num_rates; | |
165 | } | |
166 | ||
540b0b7f JN |
167 | /* Theoretical max between source and sink */ |
168 | static int intel_dp_max_common_rate(struct intel_dp *intel_dp) | |
a4fc5ed6 | 169 | { |
540b0b7f | 170 | return intel_dp->common_rates[intel_dp->num_common_rates - 1]; |
a4fc5ed6 KP |
171 | } |
172 | ||
540b0b7f JN |
173 | /* Theoretical max between source and sink */ |
174 | static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) | |
eeb6324d PZ |
175 | { |
176 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
540b0b7f JN |
177 | int source_max = intel_dig_port->max_lanes; |
178 | int sink_max = drm_dp_max_lane_count(intel_dp->dpcd); | |
eeb6324d PZ |
179 | |
180 | return min(source_max, sink_max); | |
181 | } | |
182 | ||
3d65a735 | 183 | int intel_dp_max_lane_count(struct intel_dp *intel_dp) |
540b0b7f JN |
184 | { |
185 | return intel_dp->max_link_lane_count; | |
186 | } | |
187 | ||
22a2c8e0 | 188 | int |
c898261c | 189 | intel_dp_link_required(int pixel_clock, int bpp) |
a4fc5ed6 | 190 | { |
fd81c44e DP |
191 | /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ |
192 | return DIV_ROUND_UP(pixel_clock * bpp, 8); | |
a4fc5ed6 KP |
193 | } |
194 | ||
22a2c8e0 | 195 | int |
fe27d53e DA |
196 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
197 | { | |
fd81c44e DP |
198 | /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the |
199 | * link rate that is generally expressed in Gbps. Since, 8 bits of data | |
200 | * is transmitted every LS_Clk per lane, there is no need to account for | |
201 | * the channel encoding that is done in the PHY layer here. | |
202 | */ | |
203 | ||
204 | return max_link_clock * max_lanes; | |
fe27d53e DA |
205 | } |
206 | ||
70ec0645 MK |
207 | static int |
208 | intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) | |
209 | { | |
210 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
211 | struct intel_encoder *encoder = &intel_dig_port->base; | |
212 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
213 | int max_dotclk = dev_priv->max_dotclk_freq; | |
214 | int ds_max_dotclk; | |
215 | ||
216 | int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
217 | ||
218 | if (type != DP_DS_PORT_TYPE_VGA) | |
219 | return max_dotclk; | |
220 | ||
221 | ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd, | |
222 | intel_dp->downstream_ports); | |
223 | ||
224 | if (ds_max_dotclk != 0) | |
225 | max_dotclk = min(max_dotclk, ds_max_dotclk); | |
226 | ||
227 | return max_dotclk; | |
228 | } | |
229 | ||
55cfc580 JN |
230 | static void |
231 | intel_dp_set_source_rates(struct intel_dp *intel_dp) | |
40dba341 NM |
232 | { |
233 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
234 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
d907b665 | 235 | enum port port = dig_port->port; |
55cfc580 | 236 | const int *source_rates; |
40dba341 | 237 | int size; |
d907b665 | 238 | u32 voltage; |
40dba341 | 239 | |
55cfc580 JN |
240 | /* This should only be done once */ |
241 | WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates); | |
242 | ||
cc3f90f0 | 243 | if (IS_GEN9_LP(dev_priv)) { |
55cfc580 | 244 | source_rates = bxt_rates; |
40dba341 | 245 | size = ARRAY_SIZE(bxt_rates); |
d907b665 RV |
246 | } else if (IS_CANNONLAKE(dev_priv)) { |
247 | source_rates = cnl_rates; | |
248 | size = ARRAY_SIZE(cnl_rates); | |
249 | voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; | |
250 | if (port == PORT_A || port == PORT_D || | |
251 | voltage == VOLTAGE_INFO_0_85V) | |
252 | size -= 2; | |
b976dc53 | 253 | } else if (IS_GEN9_BC(dev_priv)) { |
55cfc580 | 254 | source_rates = skl_rates; |
40dba341 NM |
255 | size = ARRAY_SIZE(skl_rates); |
256 | } else { | |
55cfc580 | 257 | source_rates = default_rates; |
40dba341 NM |
258 | size = ARRAY_SIZE(default_rates); |
259 | } | |
260 | ||
261 | /* This depends on the fact that 5.4 is last value in the array */ | |
262 | if (!intel_dp_source_supports_hbr2(intel_dp)) | |
263 | size--; | |
264 | ||
55cfc580 JN |
265 | intel_dp->source_rates = source_rates; |
266 | intel_dp->num_source_rates = size; | |
40dba341 NM |
267 | } |
268 | ||
269 | static int intersect_rates(const int *source_rates, int source_len, | |
270 | const int *sink_rates, int sink_len, | |
271 | int *common_rates) | |
272 | { | |
273 | int i = 0, j = 0, k = 0; | |
274 | ||
275 | while (i < source_len && j < sink_len) { | |
276 | if (source_rates[i] == sink_rates[j]) { | |
277 | if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) | |
278 | return k; | |
279 | common_rates[k] = source_rates[i]; | |
280 | ++k; | |
281 | ++i; | |
282 | ++j; | |
283 | } else if (source_rates[i] < sink_rates[j]) { | |
284 | ++i; | |
285 | } else { | |
286 | ++j; | |
287 | } | |
288 | } | |
289 | return k; | |
290 | } | |
291 | ||
8001b754 JN |
292 | /* return index of rate in rates array, or -1 if not found */ |
293 | static int intel_dp_rate_index(const int *rates, int len, int rate) | |
294 | { | |
295 | int i; | |
296 | ||
297 | for (i = 0; i < len; i++) | |
298 | if (rate == rates[i]) | |
299 | return i; | |
300 | ||
301 | return -1; | |
302 | } | |
303 | ||
975ee5fc | 304 | static void intel_dp_set_common_rates(struct intel_dp *intel_dp) |
40dba341 | 305 | { |
975ee5fc | 306 | WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates); |
40dba341 | 307 | |
975ee5fc JN |
308 | intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, |
309 | intel_dp->num_source_rates, | |
310 | intel_dp->sink_rates, | |
311 | intel_dp->num_sink_rates, | |
312 | intel_dp->common_rates); | |
313 | ||
314 | /* Paranoia, there should always be something in common. */ | |
315 | if (WARN_ON(intel_dp->num_common_rates == 0)) { | |
316 | intel_dp->common_rates[0] = default_rates[0]; | |
317 | intel_dp->num_common_rates = 1; | |
318 | } | |
319 | } | |
320 | ||
321 | /* get length of common rates potentially limited by max_rate */ | |
322 | static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp, | |
323 | int max_rate) | |
324 | { | |
325 | const int *common_rates = intel_dp->common_rates; | |
326 | int i, common_len = intel_dp->num_common_rates; | |
68f357cb JN |
327 | |
328 | /* Limit results by potentially reduced max rate */ | |
329 | for (i = 0; i < common_len; i++) { | |
330 | if (common_rates[common_len - i - 1] <= max_rate) | |
331 | return common_len - i; | |
332 | } | |
40dba341 | 333 | |
68f357cb | 334 | return 0; |
40dba341 NM |
335 | } |
336 | ||
1a92c70e MN |
337 | static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, |
338 | uint8_t lane_count) | |
14c562c0 MN |
339 | { |
340 | /* | |
341 | * FIXME: we need to synchronize the current link parameters with | |
342 | * hardware readout. Currently fast link training doesn't work on | |
343 | * boot-up. | |
344 | */ | |
1a92c70e MN |
345 | if (link_rate == 0 || |
346 | link_rate > intel_dp->max_link_rate) | |
14c562c0 MN |
347 | return false; |
348 | ||
1a92c70e MN |
349 | if (lane_count == 0 || |
350 | lane_count > intel_dp_max_lane_count(intel_dp)) | |
14c562c0 MN |
351 | return false; |
352 | ||
353 | return true; | |
354 | } | |
355 | ||
fdb14d33 MN |
356 | int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, |
357 | int link_rate, uint8_t lane_count) | |
358 | { | |
b1810a74 | 359 | int index; |
fdb14d33 | 360 | |
b1810a74 JN |
361 | index = intel_dp_rate_index(intel_dp->common_rates, |
362 | intel_dp->num_common_rates, | |
363 | link_rate); | |
364 | if (index > 0) { | |
e6c0c64a JN |
365 | intel_dp->max_link_rate = intel_dp->common_rates[index - 1]; |
366 | intel_dp->max_link_lane_count = lane_count; | |
fdb14d33 | 367 | } else if (lane_count > 1) { |
540b0b7f | 368 | intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); |
e6c0c64a | 369 | intel_dp->max_link_lane_count = lane_count >> 1; |
fdb14d33 MN |
370 | } else { |
371 | DRM_ERROR("Link Training Unsuccessful\n"); | |
372 | return -1; | |
373 | } | |
374 | ||
375 | return 0; | |
376 | } | |
377 | ||
c19de8eb | 378 | static enum drm_mode_status |
a4fc5ed6 KP |
379 | intel_dp_mode_valid(struct drm_connector *connector, |
380 | struct drm_display_mode *mode) | |
381 | { | |
df0e9248 | 382 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
dd06f90e JN |
383 | struct intel_connector *intel_connector = to_intel_connector(connector); |
384 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
36008365 DV |
385 | int target_clock = mode->clock; |
386 | int max_rate, mode_rate, max_lanes, max_link_clock; | |
70ec0645 MK |
387 | int max_dotclk; |
388 | ||
389 | max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); | |
a4fc5ed6 | 390 | |
1853a9da | 391 | if (intel_dp_is_edp(intel_dp) && fixed_mode) { |
dd06f90e | 392 | if (mode->hdisplay > fixed_mode->hdisplay) |
7de56f43 ZY |
393 | return MODE_PANEL; |
394 | ||
dd06f90e | 395 | if (mode->vdisplay > fixed_mode->vdisplay) |
7de56f43 | 396 | return MODE_PANEL; |
03afc4a2 DV |
397 | |
398 | target_clock = fixed_mode->clock; | |
7de56f43 ZY |
399 | } |
400 | ||
50fec21a | 401 | max_link_clock = intel_dp_max_link_rate(intel_dp); |
eeb6324d | 402 | max_lanes = intel_dp_max_lane_count(intel_dp); |
36008365 DV |
403 | |
404 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | |
405 | mode_rate = intel_dp_link_required(target_clock, 18); | |
406 | ||
799487f5 | 407 | if (mode_rate > max_rate || target_clock > max_dotclk) |
c4867936 | 408 | return MODE_CLOCK_HIGH; |
a4fc5ed6 KP |
409 | |
410 | if (mode->clock < 10000) | |
411 | return MODE_CLOCK_LOW; | |
412 | ||
0af78a2b DV |
413 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
414 | return MODE_H_ILLEGAL; | |
415 | ||
a4fc5ed6 KP |
416 | return MODE_OK; |
417 | } | |
418 | ||
a4f1289e | 419 | uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes) |
a4fc5ed6 KP |
420 | { |
421 | int i; | |
422 | uint32_t v = 0; | |
423 | ||
424 | if (src_bytes > 4) | |
425 | src_bytes = 4; | |
426 | for (i = 0; i < src_bytes; i++) | |
427 | v |= ((uint32_t) src[i]) << ((3-i) * 8); | |
428 | return v; | |
429 | } | |
430 | ||
c2af70e2 | 431 | static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
a4fc5ed6 KP |
432 | { |
433 | int i; | |
434 | if (dst_bytes > 4) | |
435 | dst_bytes = 4; | |
436 | for (i = 0; i < dst_bytes; i++) | |
437 | dst[i] = src >> ((3-i) * 8); | |
438 | } | |
439 | ||
bf13e81b JN |
440 | static void |
441 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
36b5f425 | 442 | struct intel_dp *intel_dp); |
bf13e81b JN |
443 | static void |
444 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
5d5ab2d2 VS |
445 | struct intel_dp *intel_dp, |
446 | bool force_disable_vdd); | |
335f752b ID |
447 | static void |
448 | intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp); | |
bf13e81b | 449 | |
773538e8 VS |
450 | static void pps_lock(struct intel_dp *intel_dp) |
451 | { | |
452 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
453 | struct intel_encoder *encoder = &intel_dig_port->base; | |
454 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 455 | struct drm_i915_private *dev_priv = to_i915(dev); |
773538e8 VS |
456 | |
457 | /* | |
458 | * See vlv_power_sequencer_reset() why we need | |
459 | * a power domain reference here. | |
460 | */ | |
5432fcaf | 461 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
773538e8 VS |
462 | |
463 | mutex_lock(&dev_priv->pps_mutex); | |
464 | } | |
465 | ||
466 | static void pps_unlock(struct intel_dp *intel_dp) | |
467 | { | |
468 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
469 | struct intel_encoder *encoder = &intel_dig_port->base; | |
470 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 471 | struct drm_i915_private *dev_priv = to_i915(dev); |
773538e8 VS |
472 | |
473 | mutex_unlock(&dev_priv->pps_mutex); | |
474 | ||
5432fcaf | 475 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
773538e8 VS |
476 | } |
477 | ||
961a0db0 VS |
478 | static void |
479 | vlv_power_sequencer_kick(struct intel_dp *intel_dp) | |
480 | { | |
481 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
30ad9814 | 482 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
961a0db0 | 483 | enum pipe pipe = intel_dp->pps_pipe; |
0047eedc VS |
484 | bool pll_enabled, release_cl_override = false; |
485 | enum dpio_phy phy = DPIO_PHY(pipe); | |
486 | enum dpio_channel ch = vlv_pipe_to_channel(pipe); | |
961a0db0 VS |
487 | uint32_t DP; |
488 | ||
489 | if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, | |
490 | "skipping pipe %c power seqeuncer kick due to port %c being active\n", | |
491 | pipe_name(pipe), port_name(intel_dig_port->port))) | |
492 | return; | |
493 | ||
494 | DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", | |
495 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
496 | ||
497 | /* Preserve the BIOS-computed detected bit. This is | |
498 | * supposed to be read-only. | |
499 | */ | |
500 | DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
501 | DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; | |
502 | DP |= DP_PORT_WIDTH(1); | |
503 | DP |= DP_LINK_TRAIN_PAT_1; | |
504 | ||
920a14b2 | 505 | if (IS_CHERRYVIEW(dev_priv)) |
961a0db0 VS |
506 | DP |= DP_PIPE_SELECT_CHV(pipe); |
507 | else if (pipe == PIPE_B) | |
508 | DP |= DP_PIPEB_SELECT; | |
509 | ||
d288f65f VS |
510 | pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; |
511 | ||
512 | /* | |
513 | * The DPLL for the pipe must be enabled for this to work. | |
514 | * So enable temporarily it if it's not already enabled. | |
515 | */ | |
0047eedc | 516 | if (!pll_enabled) { |
920a14b2 | 517 | release_cl_override = IS_CHERRYVIEW(dev_priv) && |
0047eedc VS |
518 | !chv_phy_powergate_ch(dev_priv, phy, ch, true); |
519 | ||
30ad9814 | 520 | if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ? |
3f36b937 TU |
521 | &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { |
522 | DRM_ERROR("Failed to force on pll for pipe %c!\n", | |
523 | pipe_name(pipe)); | |
524 | return; | |
525 | } | |
0047eedc | 526 | } |
d288f65f | 527 | |
961a0db0 VS |
528 | /* |
529 | * Similar magic as in intel_dp_enable_port(). | |
530 | * We _must_ do this port enable + disable trick | |
531 | * to make this power seqeuencer lock onto the port. | |
532 | * Otherwise even VDD force bit won't work. | |
533 | */ | |
534 | I915_WRITE(intel_dp->output_reg, DP); | |
535 | POSTING_READ(intel_dp->output_reg); | |
536 | ||
537 | I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); | |
538 | POSTING_READ(intel_dp->output_reg); | |
539 | ||
540 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); | |
541 | POSTING_READ(intel_dp->output_reg); | |
d288f65f | 542 | |
0047eedc | 543 | if (!pll_enabled) { |
30ad9814 | 544 | vlv_force_pll_off(dev_priv, pipe); |
0047eedc VS |
545 | |
546 | if (release_cl_override) | |
547 | chv_phy_powergate_ch(dev_priv, phy, ch, false); | |
548 | } | |
961a0db0 VS |
549 | } |
550 | ||
9f2bdb00 VS |
551 | static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv) |
552 | { | |
553 | struct intel_encoder *encoder; | |
554 | unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); | |
555 | ||
556 | /* | |
557 | * We don't have power sequencer currently. | |
558 | * Pick one that's not used by other ports. | |
559 | */ | |
560 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
561 | struct intel_dp *intel_dp; | |
562 | ||
563 | if (encoder->type != INTEL_OUTPUT_DP && | |
564 | encoder->type != INTEL_OUTPUT_EDP) | |
565 | continue; | |
566 | ||
567 | intel_dp = enc_to_intel_dp(&encoder->base); | |
568 | ||
569 | if (encoder->type == INTEL_OUTPUT_EDP) { | |
570 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE && | |
571 | intel_dp->active_pipe != intel_dp->pps_pipe); | |
572 | ||
573 | if (intel_dp->pps_pipe != INVALID_PIPE) | |
574 | pipes &= ~(1 << intel_dp->pps_pipe); | |
575 | } else { | |
576 | WARN_ON(intel_dp->pps_pipe != INVALID_PIPE); | |
577 | ||
578 | if (intel_dp->active_pipe != INVALID_PIPE) | |
579 | pipes &= ~(1 << intel_dp->active_pipe); | |
580 | } | |
581 | } | |
582 | ||
583 | if (pipes == 0) | |
584 | return INVALID_PIPE; | |
585 | ||
586 | return ffs(pipes) - 1; | |
587 | } | |
588 | ||
bf13e81b JN |
589 | static enum pipe |
590 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) | |
591 | { | |
592 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bf13e81b | 593 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 594 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8c3344e | 595 | enum pipe pipe; |
bf13e81b | 596 | |
e39b999a | 597 | lockdep_assert_held(&dev_priv->pps_mutex); |
bf13e81b | 598 | |
a8c3344e | 599 | /* We should never land here with regular DP ports */ |
1853a9da | 600 | WARN_ON(!intel_dp_is_edp(intel_dp)); |
a8c3344e | 601 | |
9f2bdb00 VS |
602 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE && |
603 | intel_dp->active_pipe != intel_dp->pps_pipe); | |
604 | ||
a4a5d2f8 VS |
605 | if (intel_dp->pps_pipe != INVALID_PIPE) |
606 | return intel_dp->pps_pipe; | |
607 | ||
9f2bdb00 | 608 | pipe = vlv_find_free_pps(dev_priv); |
a4a5d2f8 VS |
609 | |
610 | /* | |
611 | * Didn't find one. This should not happen since there | |
612 | * are two power sequencers and up to two eDP ports. | |
613 | */ | |
9f2bdb00 | 614 | if (WARN_ON(pipe == INVALID_PIPE)) |
a8c3344e | 615 | pipe = PIPE_A; |
a4a5d2f8 | 616 | |
a8c3344e VS |
617 | vlv_steal_power_sequencer(dev, pipe); |
618 | intel_dp->pps_pipe = pipe; | |
a4a5d2f8 VS |
619 | |
620 | DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", | |
621 | pipe_name(intel_dp->pps_pipe), | |
622 | port_name(intel_dig_port->port)); | |
623 | ||
624 | /* init power sequencer on this pipe and port */ | |
36b5f425 | 625 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
5d5ab2d2 | 626 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true); |
a4a5d2f8 | 627 | |
961a0db0 VS |
628 | /* |
629 | * Even vdd force doesn't work until we've made | |
630 | * the power sequencer lock in on the port. | |
631 | */ | |
632 | vlv_power_sequencer_kick(intel_dp); | |
a4a5d2f8 VS |
633 | |
634 | return intel_dp->pps_pipe; | |
635 | } | |
636 | ||
78597996 ID |
637 | static int |
638 | bxt_power_sequencer_idx(struct intel_dp *intel_dp) | |
639 | { | |
640 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
641 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 642 | struct drm_i915_private *dev_priv = to_i915(dev); |
78597996 ID |
643 | |
644 | lockdep_assert_held(&dev_priv->pps_mutex); | |
645 | ||
646 | /* We should never land here with regular DP ports */ | |
1853a9da | 647 | WARN_ON(!intel_dp_is_edp(intel_dp)); |
78597996 ID |
648 | |
649 | /* | |
650 | * TODO: BXT has 2 PPS instances. The correct port->PPS instance | |
651 | * mapping needs to be retrieved from VBT, for now just hard-code to | |
652 | * use instance #0 always. | |
653 | */ | |
654 | if (!intel_dp->pps_reset) | |
655 | return 0; | |
656 | ||
657 | intel_dp->pps_reset = false; | |
658 | ||
659 | /* | |
660 | * Only the HW needs to be reprogrammed, the SW state is fixed and | |
661 | * has been setup during connector init. | |
662 | */ | |
5d5ab2d2 | 663 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false); |
78597996 ID |
664 | |
665 | return 0; | |
666 | } | |
667 | ||
6491ab27 VS |
668 | typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, |
669 | enum pipe pipe); | |
670 | ||
671 | static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, | |
672 | enum pipe pipe) | |
673 | { | |
44cb734c | 674 | return I915_READ(PP_STATUS(pipe)) & PP_ON; |
6491ab27 VS |
675 | } |
676 | ||
677 | static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, | |
678 | enum pipe pipe) | |
679 | { | |
44cb734c | 680 | return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD; |
6491ab27 VS |
681 | } |
682 | ||
683 | static bool vlv_pipe_any(struct drm_i915_private *dev_priv, | |
684 | enum pipe pipe) | |
685 | { | |
686 | return true; | |
687 | } | |
bf13e81b | 688 | |
a4a5d2f8 | 689 | static enum pipe |
6491ab27 VS |
690 | vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, |
691 | enum port port, | |
692 | vlv_pipe_check pipe_check) | |
a4a5d2f8 VS |
693 | { |
694 | enum pipe pipe; | |
bf13e81b | 695 | |
bf13e81b | 696 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
44cb734c | 697 | u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) & |
bf13e81b | 698 | PANEL_PORT_SELECT_MASK; |
a4a5d2f8 VS |
699 | |
700 | if (port_sel != PANEL_PORT_SELECT_VLV(port)) | |
701 | continue; | |
702 | ||
6491ab27 VS |
703 | if (!pipe_check(dev_priv, pipe)) |
704 | continue; | |
705 | ||
a4a5d2f8 | 706 | return pipe; |
bf13e81b JN |
707 | } |
708 | ||
a4a5d2f8 VS |
709 | return INVALID_PIPE; |
710 | } | |
711 | ||
712 | static void | |
713 | vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) | |
714 | { | |
715 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
716 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 717 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 VS |
718 | enum port port = intel_dig_port->port; |
719 | ||
720 | lockdep_assert_held(&dev_priv->pps_mutex); | |
721 | ||
722 | /* try to find a pipe with this port selected */ | |
6491ab27 VS |
723 | /* first pick one where the panel is on */ |
724 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
725 | vlv_pipe_has_pp_on); | |
726 | /* didn't find one? pick one where vdd is on */ | |
727 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
728 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
729 | vlv_pipe_has_vdd_on); | |
730 | /* didn't find one? pick one with just the correct port */ | |
731 | if (intel_dp->pps_pipe == INVALID_PIPE) | |
732 | intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, | |
733 | vlv_pipe_any); | |
a4a5d2f8 VS |
734 | |
735 | /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ | |
736 | if (intel_dp->pps_pipe == INVALID_PIPE) { | |
737 | DRM_DEBUG_KMS("no initial power sequencer for port %c\n", | |
738 | port_name(port)); | |
739 | return; | |
bf13e81b JN |
740 | } |
741 | ||
a4a5d2f8 VS |
742 | DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", |
743 | port_name(port), pipe_name(intel_dp->pps_pipe)); | |
744 | ||
36b5f425 | 745 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
5d5ab2d2 | 746 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false); |
bf13e81b JN |
747 | } |
748 | ||
78597996 | 749 | void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) |
773538e8 | 750 | { |
91c8a326 | 751 | struct drm_device *dev = &dev_priv->drm; |
773538e8 VS |
752 | struct intel_encoder *encoder; |
753 | ||
920a14b2 | 754 | if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 755 | !IS_GEN9_LP(dev_priv))) |
773538e8 VS |
756 | return; |
757 | ||
758 | /* | |
759 | * We can't grab pps_mutex here due to deadlock with power_domain | |
760 | * mutex when power_domain functions are called while holding pps_mutex. | |
761 | * That also means that in order to use pps_pipe the code needs to | |
762 | * hold both a power domain reference and pps_mutex, and the power domain | |
763 | * reference get/put must be done while _not_ holding pps_mutex. | |
764 | * pps_{lock,unlock}() do these steps in the correct order, so one | |
765 | * should use them always. | |
766 | */ | |
767 | ||
19c8054c | 768 | for_each_intel_encoder(dev, encoder) { |
773538e8 VS |
769 | struct intel_dp *intel_dp; |
770 | ||
9f2bdb00 VS |
771 | if (encoder->type != INTEL_OUTPUT_DP && |
772 | encoder->type != INTEL_OUTPUT_EDP) | |
773538e8 VS |
773 | continue; |
774 | ||
775 | intel_dp = enc_to_intel_dp(&encoder->base); | |
9f2bdb00 VS |
776 | |
777 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE); | |
778 | ||
779 | if (encoder->type != INTEL_OUTPUT_EDP) | |
780 | continue; | |
781 | ||
cc3f90f0 | 782 | if (IS_GEN9_LP(dev_priv)) |
78597996 ID |
783 | intel_dp->pps_reset = true; |
784 | else | |
785 | intel_dp->pps_pipe = INVALID_PIPE; | |
773538e8 | 786 | } |
bf13e81b JN |
787 | } |
788 | ||
8e8232d5 ID |
789 | struct pps_registers { |
790 | i915_reg_t pp_ctrl; | |
791 | i915_reg_t pp_stat; | |
792 | i915_reg_t pp_on; | |
793 | i915_reg_t pp_off; | |
794 | i915_reg_t pp_div; | |
795 | }; | |
796 | ||
797 | static void intel_pps_get_registers(struct drm_i915_private *dev_priv, | |
798 | struct intel_dp *intel_dp, | |
799 | struct pps_registers *regs) | |
800 | { | |
44cb734c ID |
801 | int pps_idx = 0; |
802 | ||
8e8232d5 ID |
803 | memset(regs, 0, sizeof(*regs)); |
804 | ||
cc3f90f0 | 805 | if (IS_GEN9_LP(dev_priv)) |
44cb734c ID |
806 | pps_idx = bxt_power_sequencer_idx(intel_dp); |
807 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
808 | pps_idx = vlv_power_sequencer_pipe(intel_dp); | |
8e8232d5 | 809 | |
44cb734c ID |
810 | regs->pp_ctrl = PP_CONTROL(pps_idx); |
811 | regs->pp_stat = PP_STATUS(pps_idx); | |
812 | regs->pp_on = PP_ON_DELAYS(pps_idx); | |
813 | regs->pp_off = PP_OFF_DELAYS(pps_idx); | |
938361e7 | 814 | if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) |
44cb734c | 815 | regs->pp_div = PP_DIVISOR(pps_idx); |
8e8232d5 ID |
816 | } |
817 | ||
f0f59a00 VS |
818 | static i915_reg_t |
819 | _pp_ctrl_reg(struct intel_dp *intel_dp) | |
bf13e81b | 820 | { |
8e8232d5 | 821 | struct pps_registers regs; |
bf13e81b | 822 | |
8e8232d5 ID |
823 | intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, |
824 | ®s); | |
825 | ||
826 | return regs.pp_ctrl; | |
bf13e81b JN |
827 | } |
828 | ||
f0f59a00 VS |
829 | static i915_reg_t |
830 | _pp_stat_reg(struct intel_dp *intel_dp) | |
bf13e81b | 831 | { |
8e8232d5 | 832 | struct pps_registers regs; |
bf13e81b | 833 | |
8e8232d5 ID |
834 | intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp, |
835 | ®s); | |
836 | ||
837 | return regs.pp_stat; | |
bf13e81b JN |
838 | } |
839 | ||
01527b31 CT |
840 | /* Reboot notifier handler to shutdown panel power to guarantee T12 timing |
841 | This function only applicable when panel PM state is not to be tracked */ | |
842 | static int edp_notify_handler(struct notifier_block *this, unsigned long code, | |
843 | void *unused) | |
844 | { | |
845 | struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), | |
846 | edp_notifier); | |
847 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 848 | struct drm_i915_private *dev_priv = to_i915(dev); |
01527b31 | 849 | |
1853a9da | 850 | if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART) |
01527b31 CT |
851 | return 0; |
852 | ||
773538e8 | 853 | pps_lock(intel_dp); |
e39b999a | 854 | |
920a14b2 | 855 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e39b999a | 856 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
f0f59a00 | 857 | i915_reg_t pp_ctrl_reg, pp_div_reg; |
649636ef | 858 | u32 pp_div; |
e39b999a | 859 | |
44cb734c ID |
860 | pp_ctrl_reg = PP_CONTROL(pipe); |
861 | pp_div_reg = PP_DIVISOR(pipe); | |
01527b31 CT |
862 | pp_div = I915_READ(pp_div_reg); |
863 | pp_div &= PP_REFERENCE_DIVIDER_MASK; | |
864 | ||
865 | /* 0x1F write to PP_DIV_REG sets max cycle delay */ | |
866 | I915_WRITE(pp_div_reg, pp_div | 0x1F); | |
867 | I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); | |
868 | msleep(intel_dp->panel_power_cycle_delay); | |
869 | } | |
870 | ||
773538e8 | 871 | pps_unlock(intel_dp); |
e39b999a | 872 | |
01527b31 CT |
873 | return 0; |
874 | } | |
875 | ||
4be73780 | 876 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
ebf33b18 | 877 | { |
30add22d | 878 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 879 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 880 | |
e39b999a VS |
881 | lockdep_assert_held(&dev_priv->pps_mutex); |
882 | ||
920a14b2 | 883 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
9a42356b VS |
884 | intel_dp->pps_pipe == INVALID_PIPE) |
885 | return false; | |
886 | ||
bf13e81b | 887 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
ebf33b18 KP |
888 | } |
889 | ||
4be73780 | 890 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
ebf33b18 | 891 | { |
30add22d | 892 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 893 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 894 | |
e39b999a VS |
895 | lockdep_assert_held(&dev_priv->pps_mutex); |
896 | ||
920a14b2 | 897 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
9a42356b VS |
898 | intel_dp->pps_pipe == INVALID_PIPE) |
899 | return false; | |
900 | ||
773538e8 | 901 | return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; |
ebf33b18 KP |
902 | } |
903 | ||
9b984dae KP |
904 | static void |
905 | intel_dp_check_edp(struct intel_dp *intel_dp) | |
906 | { | |
30add22d | 907 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 908 | struct drm_i915_private *dev_priv = to_i915(dev); |
ebf33b18 | 909 | |
1853a9da | 910 | if (!intel_dp_is_edp(intel_dp)) |
9b984dae | 911 | return; |
453c5420 | 912 | |
4be73780 | 913 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
9b984dae KP |
914 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
915 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", | |
bf13e81b JN |
916 | I915_READ(_pp_stat_reg(intel_dp)), |
917 | I915_READ(_pp_ctrl_reg(intel_dp))); | |
9b984dae KP |
918 | } |
919 | } | |
920 | ||
9ee32fea DV |
921 | static uint32_t |
922 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) | |
923 | { | |
924 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
925 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 926 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 927 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
9ee32fea DV |
928 | uint32_t status; |
929 | bool done; | |
930 | ||
ef04f00d | 931 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
9ee32fea | 932 | if (has_aux_irq) |
b18ac466 | 933 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
3598706b | 934 | msecs_to_jiffies_timeout(10)); |
9ee32fea | 935 | else |
713a6b66 | 936 | done = wait_for(C, 10) == 0; |
9ee32fea DV |
937 | if (!done) |
938 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", | |
939 | has_aux_irq); | |
940 | #undef C | |
941 | ||
942 | return status; | |
943 | } | |
944 | ||
6ffb1be7 | 945 | static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
a4fc5ed6 | 946 | { |
174edf1f | 947 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
e7dc33f3 | 948 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
9ee32fea | 949 | |
a457f54b VS |
950 | if (index) |
951 | return 0; | |
952 | ||
ec5b01dd DL |
953 | /* |
954 | * The clock divider is based off the hrawclk, and would like to run at | |
a457f54b | 955 | * 2MHz. So, take the hrawclk value and divide by 2000 and use that |
a4fc5ed6 | 956 | */ |
a457f54b | 957 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); |
ec5b01dd DL |
958 | } |
959 | ||
960 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
961 | { | |
962 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
a457f54b | 963 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
ec5b01dd DL |
964 | |
965 | if (index) | |
966 | return 0; | |
967 | ||
a457f54b VS |
968 | /* |
969 | * The clock divider is based off the cdclk or PCH rawclk, and would | |
970 | * like to run at 2MHz. So, take the cdclk or PCH rawclk value and | |
971 | * divide by 2000 and use that | |
972 | */ | |
e7dc33f3 | 973 | if (intel_dig_port->port == PORT_A) |
49cd97a3 | 974 | return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000); |
e7dc33f3 VS |
975 | else |
976 | return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); | |
ec5b01dd DL |
977 | } |
978 | ||
979 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) | |
980 | { | |
981 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
a457f54b | 982 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
ec5b01dd | 983 | |
a457f54b | 984 | if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) { |
2c55c336 | 985 | /* Workaround for non-ULT HSW */ |
bc86625a CW |
986 | switch (index) { |
987 | case 0: return 63; | |
988 | case 1: return 72; | |
989 | default: return 0; | |
990 | } | |
2c55c336 | 991 | } |
a457f54b VS |
992 | |
993 | return ilk_get_aux_clock_divider(intel_dp, index); | |
b84a1cf8 RV |
994 | } |
995 | ||
b6b5e383 DL |
996 | static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
997 | { | |
998 | /* | |
999 | * SKL doesn't need us to program the AUX clock divider (Hardware will | |
1000 | * derive the clock from CDCLK automatically). We still implement the | |
1001 | * get_aux_clock_divider vfunc to plug-in into the existing code. | |
1002 | */ | |
1003 | return index ? 0 : 1; | |
1004 | } | |
1005 | ||
6ffb1be7 VS |
1006 | static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, |
1007 | bool has_aux_irq, | |
1008 | int send_bytes, | |
1009 | uint32_t aux_clock_divider) | |
5ed12a19 DL |
1010 | { |
1011 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
8652744b TU |
1012 | struct drm_i915_private *dev_priv = |
1013 | to_i915(intel_dig_port->base.base.dev); | |
5ed12a19 DL |
1014 | uint32_t precharge, timeout; |
1015 | ||
8652744b | 1016 | if (IS_GEN6(dev_priv)) |
5ed12a19 DL |
1017 | precharge = 3; |
1018 | else | |
1019 | precharge = 5; | |
1020 | ||
8652744b | 1021 | if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A) |
5ed12a19 DL |
1022 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
1023 | else | |
1024 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; | |
1025 | ||
1026 | return DP_AUX_CH_CTL_SEND_BUSY | | |
788d4433 | 1027 | DP_AUX_CH_CTL_DONE | |
5ed12a19 | 1028 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
788d4433 | 1029 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
5ed12a19 | 1030 | timeout | |
788d4433 | 1031 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
5ed12a19 DL |
1032 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
1033 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | | |
788d4433 | 1034 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
5ed12a19 DL |
1035 | } |
1036 | ||
b9ca5fad DL |
1037 | static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, |
1038 | bool has_aux_irq, | |
1039 | int send_bytes, | |
1040 | uint32_t unused) | |
1041 | { | |
1042 | return DP_AUX_CH_CTL_SEND_BUSY | | |
1043 | DP_AUX_CH_CTL_DONE | | |
1044 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | | |
1045 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
1046 | DP_AUX_CH_CTL_TIME_OUT_1600us | | |
1047 | DP_AUX_CH_CTL_RECEIVE_ERROR | | |
1048 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | | |
d4dcbdce | 1049 | DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | |
b9ca5fad DL |
1050 | DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); |
1051 | } | |
1052 | ||
b84a1cf8 RV |
1053 | static int |
1054 | intel_dp_aux_ch(struct intel_dp *intel_dp, | |
bd9f74a5 | 1055 | const uint8_t *send, int send_bytes, |
b84a1cf8 RV |
1056 | uint8_t *recv, int recv_size) |
1057 | { | |
1058 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
0031fb96 TU |
1059 | struct drm_i915_private *dev_priv = |
1060 | to_i915(intel_dig_port->base.base.dev); | |
f0f59a00 | 1061 | i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
bc86625a | 1062 | uint32_t aux_clock_divider; |
b84a1cf8 RV |
1063 | int i, ret, recv_bytes; |
1064 | uint32_t status; | |
5ed12a19 | 1065 | int try, clock = 0; |
0031fb96 | 1066 | bool has_aux_irq = HAS_AUX_IRQ(dev_priv); |
884f19e9 JN |
1067 | bool vdd; |
1068 | ||
773538e8 | 1069 | pps_lock(intel_dp); |
e39b999a | 1070 | |
72c3500a VS |
1071 | /* |
1072 | * We will be called with VDD already enabled for dpcd/edid/oui reads. | |
1073 | * In such cases we want to leave VDD enabled and it's up to upper layers | |
1074 | * to turn it off. But for eg. i2c-dev access we need to turn it on/off | |
1075 | * ourselves. | |
1076 | */ | |
1e0560e0 | 1077 | vdd = edp_panel_vdd_on(intel_dp); |
b84a1cf8 RV |
1078 | |
1079 | /* dp aux is extremely sensitive to irq latency, hence request the | |
1080 | * lowest possible wakeup latency and so prevent the cpu from going into | |
1081 | * deep sleep states. | |
1082 | */ | |
1083 | pm_qos_update_request(&dev_priv->pm_qos, 0); | |
1084 | ||
1085 | intel_dp_check_edp(intel_dp); | |
5eb08b69 | 1086 | |
11bee43e JB |
1087 | /* Try to wait for any previous AUX channel activity */ |
1088 | for (try = 0; try < 3; try++) { | |
ef04f00d | 1089 | status = I915_READ_NOTRACE(ch_ctl); |
11bee43e JB |
1090 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
1091 | break; | |
1092 | msleep(1); | |
1093 | } | |
1094 | ||
1095 | if (try == 3) { | |
02196c77 MK |
1096 | static u32 last_status = -1; |
1097 | const u32 status = I915_READ(ch_ctl); | |
1098 | ||
1099 | if (status != last_status) { | |
1100 | WARN(1, "dp_aux_ch not started status 0x%08x\n", | |
1101 | status); | |
1102 | last_status = status; | |
1103 | } | |
1104 | ||
9ee32fea DV |
1105 | ret = -EBUSY; |
1106 | goto out; | |
4f7f7b7e CW |
1107 | } |
1108 | ||
46a5ae9f PZ |
1109 | /* Only 5 data registers! */ |
1110 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { | |
1111 | ret = -E2BIG; | |
1112 | goto out; | |
1113 | } | |
1114 | ||
ec5b01dd | 1115 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
153b1100 DL |
1116 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
1117 | has_aux_irq, | |
1118 | send_bytes, | |
1119 | aux_clock_divider); | |
5ed12a19 | 1120 | |
bc86625a CW |
1121 | /* Must try at least 3 times according to DP spec */ |
1122 | for (try = 0; try < 5; try++) { | |
1123 | /* Load the send data into the aux channel data registers */ | |
1124 | for (i = 0; i < send_bytes; i += 4) | |
330e20ec | 1125 | I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2], |
a4f1289e RV |
1126 | intel_dp_pack_aux(send + i, |
1127 | send_bytes - i)); | |
bc86625a CW |
1128 | |
1129 | /* Send the command and wait for it to complete */ | |
5ed12a19 | 1130 | I915_WRITE(ch_ctl, send_ctl); |
bc86625a CW |
1131 | |
1132 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); | |
1133 | ||
1134 | /* Clear done status and any errors */ | |
1135 | I915_WRITE(ch_ctl, | |
1136 | status | | |
1137 | DP_AUX_CH_CTL_DONE | | |
1138 | DP_AUX_CH_CTL_TIME_OUT_ERROR | | |
1139 | DP_AUX_CH_CTL_RECEIVE_ERROR); | |
1140 | ||
74ebf294 | 1141 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) |
bc86625a | 1142 | continue; |
74ebf294 TP |
1143 | |
1144 | /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 | |
1145 | * 400us delay required for errors and timeouts | |
1146 | * Timeout errors from the HW already meet this | |
1147 | * requirement so skip to next iteration | |
1148 | */ | |
1149 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { | |
1150 | usleep_range(400, 500); | |
bc86625a | 1151 | continue; |
74ebf294 | 1152 | } |
bc86625a | 1153 | if (status & DP_AUX_CH_CTL_DONE) |
e058c945 | 1154 | goto done; |
bc86625a | 1155 | } |
a4fc5ed6 KP |
1156 | } |
1157 | ||
a4fc5ed6 | 1158 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
1ae8c0a5 | 1159 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
9ee32fea DV |
1160 | ret = -EBUSY; |
1161 | goto out; | |
a4fc5ed6 KP |
1162 | } |
1163 | ||
e058c945 | 1164 | done: |
a4fc5ed6 KP |
1165 | /* Check for timeout or receive error. |
1166 | * Timeouts occur when the sink is not connected | |
1167 | */ | |
a5b3da54 | 1168 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
1ae8c0a5 | 1169 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
9ee32fea DV |
1170 | ret = -EIO; |
1171 | goto out; | |
a5b3da54 | 1172 | } |
1ae8c0a5 KP |
1173 | |
1174 | /* Timeouts occur when the device isn't connected, so they're | |
1175 | * "normal" -- don't fill the kernel log with these */ | |
a5b3da54 | 1176 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
a5570fe5 | 1177 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
9ee32fea DV |
1178 | ret = -ETIMEDOUT; |
1179 | goto out; | |
a4fc5ed6 KP |
1180 | } |
1181 | ||
1182 | /* Unload any bytes sent back from the other side */ | |
1183 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> | |
1184 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); | |
14e01889 RV |
1185 | |
1186 | /* | |
1187 | * By BSpec: "Message sizes of 0 or >20 are not allowed." | |
1188 | * We have no idea of what happened so we return -EBUSY so | |
1189 | * drm layer takes care for the necessary retries. | |
1190 | */ | |
1191 | if (recv_bytes == 0 || recv_bytes > 20) { | |
1192 | DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", | |
1193 | recv_bytes); | |
1194 | /* | |
1195 | * FIXME: This patch was created on top of a series that | |
1196 | * organize the retries at drm level. There EBUSY should | |
1197 | * also take care for 1ms wait before retrying. | |
1198 | * That aux retries re-org is still needed and after that is | |
1199 | * merged we remove this sleep from here. | |
1200 | */ | |
1201 | usleep_range(1000, 1500); | |
1202 | ret = -EBUSY; | |
1203 | goto out; | |
1204 | } | |
1205 | ||
a4fc5ed6 KP |
1206 | if (recv_bytes > recv_size) |
1207 | recv_bytes = recv_size; | |
0206e353 | 1208 | |
4f7f7b7e | 1209 | for (i = 0; i < recv_bytes; i += 4) |
330e20ec | 1210 | intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]), |
a4f1289e | 1211 | recv + i, recv_bytes - i); |
a4fc5ed6 | 1212 | |
9ee32fea DV |
1213 | ret = recv_bytes; |
1214 | out: | |
1215 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); | |
1216 | ||
884f19e9 JN |
1217 | if (vdd) |
1218 | edp_panel_vdd_off(intel_dp, false); | |
1219 | ||
773538e8 | 1220 | pps_unlock(intel_dp); |
e39b999a | 1221 | |
9ee32fea | 1222 | return ret; |
a4fc5ed6 KP |
1223 | } |
1224 | ||
a6c8aff0 JN |
1225 | #define BARE_ADDRESS_SIZE 3 |
1226 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) | |
9d1a1031 JN |
1227 | static ssize_t |
1228 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
a4fc5ed6 | 1229 | { |
9d1a1031 JN |
1230 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
1231 | uint8_t txbuf[20], rxbuf[20]; | |
1232 | size_t txsize, rxsize; | |
a4fc5ed6 | 1233 | int ret; |
a4fc5ed6 | 1234 | |
d2d9cbbd VS |
1235 | txbuf[0] = (msg->request << 4) | |
1236 | ((msg->address >> 16) & 0xf); | |
1237 | txbuf[1] = (msg->address >> 8) & 0xff; | |
9d1a1031 JN |
1238 | txbuf[2] = msg->address & 0xff; |
1239 | txbuf[3] = msg->size - 1; | |
46a5ae9f | 1240 | |
9d1a1031 JN |
1241 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
1242 | case DP_AUX_NATIVE_WRITE: | |
1243 | case DP_AUX_I2C_WRITE: | |
c1e74122 | 1244 | case DP_AUX_I2C_WRITE_STATUS_UPDATE: |
a6c8aff0 | 1245 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
a1ddefd8 | 1246 | rxsize = 2; /* 0 or 1 data bytes */ |
f51a44b9 | 1247 | |
9d1a1031 JN |
1248 | if (WARN_ON(txsize > 20)) |
1249 | return -E2BIG; | |
a4fc5ed6 | 1250 | |
dd788090 VS |
1251 | WARN_ON(!msg->buffer != !msg->size); |
1252 | ||
d81a67cc ID |
1253 | if (msg->buffer) |
1254 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); | |
a4fc5ed6 | 1255 | |
9d1a1031 JN |
1256 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1257 | if (ret > 0) { | |
1258 | msg->reply = rxbuf[0] >> 4; | |
a4fc5ed6 | 1259 | |
a1ddefd8 JN |
1260 | if (ret > 1) { |
1261 | /* Number of bytes written in a short write. */ | |
1262 | ret = clamp_t(int, rxbuf[1], 0, msg->size); | |
1263 | } else { | |
1264 | /* Return payload size. */ | |
1265 | ret = msg->size; | |
1266 | } | |
9d1a1031 JN |
1267 | } |
1268 | break; | |
46a5ae9f | 1269 | |
9d1a1031 JN |
1270 | case DP_AUX_NATIVE_READ: |
1271 | case DP_AUX_I2C_READ: | |
a6c8aff0 | 1272 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
9d1a1031 | 1273 | rxsize = msg->size + 1; |
a4fc5ed6 | 1274 | |
9d1a1031 JN |
1275 | if (WARN_ON(rxsize > 20)) |
1276 | return -E2BIG; | |
a4fc5ed6 | 1277 | |
9d1a1031 JN |
1278 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
1279 | if (ret > 0) { | |
1280 | msg->reply = rxbuf[0] >> 4; | |
1281 | /* | |
1282 | * Assume happy day, and copy the data. The caller is | |
1283 | * expected to check msg->reply before touching it. | |
1284 | * | |
1285 | * Return payload size. | |
1286 | */ | |
1287 | ret--; | |
1288 | memcpy(msg->buffer, rxbuf + 1, ret); | |
a4fc5ed6 | 1289 | } |
9d1a1031 JN |
1290 | break; |
1291 | ||
1292 | default: | |
1293 | ret = -EINVAL; | |
1294 | break; | |
a4fc5ed6 | 1295 | } |
f51a44b9 | 1296 | |
9d1a1031 | 1297 | return ret; |
a4fc5ed6 KP |
1298 | } |
1299 | ||
8f7ce038 VS |
1300 | static enum port intel_aux_port(struct drm_i915_private *dev_priv, |
1301 | enum port port) | |
1302 | { | |
1303 | const struct ddi_vbt_port_info *info = | |
1304 | &dev_priv->vbt.ddi_port_info[port]; | |
1305 | enum port aux_port; | |
1306 | ||
1307 | if (!info->alternate_aux_channel) { | |
1308 | DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n", | |
1309 | port_name(port), port_name(port)); | |
1310 | return port; | |
1311 | } | |
1312 | ||
1313 | switch (info->alternate_aux_channel) { | |
1314 | case DP_AUX_A: | |
1315 | aux_port = PORT_A; | |
1316 | break; | |
1317 | case DP_AUX_B: | |
1318 | aux_port = PORT_B; | |
1319 | break; | |
1320 | case DP_AUX_C: | |
1321 | aux_port = PORT_C; | |
1322 | break; | |
1323 | case DP_AUX_D: | |
1324 | aux_port = PORT_D; | |
1325 | break; | |
1326 | default: | |
1327 | MISSING_CASE(info->alternate_aux_channel); | |
1328 | aux_port = PORT_A; | |
1329 | break; | |
1330 | } | |
1331 | ||
1332 | DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n", | |
1333 | port_name(aux_port), port_name(port)); | |
1334 | ||
1335 | return aux_port; | |
1336 | } | |
1337 | ||
f0f59a00 | 1338 | static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1339 | enum port port) |
da00bdcf VS |
1340 | { |
1341 | switch (port) { | |
1342 | case PORT_B: | |
1343 | case PORT_C: | |
1344 | case PORT_D: | |
1345 | return DP_AUX_CH_CTL(port); | |
1346 | default: | |
1347 | MISSING_CASE(port); | |
1348 | return DP_AUX_CH_CTL(PORT_B); | |
1349 | } | |
1350 | } | |
1351 | ||
f0f59a00 | 1352 | static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1353 | enum port port, int index) |
330e20ec VS |
1354 | { |
1355 | switch (port) { | |
1356 | case PORT_B: | |
1357 | case PORT_C: | |
1358 | case PORT_D: | |
1359 | return DP_AUX_CH_DATA(port, index); | |
1360 | default: | |
1361 | MISSING_CASE(port); | |
1362 | return DP_AUX_CH_DATA(PORT_B, index); | |
1363 | } | |
1364 | } | |
1365 | ||
f0f59a00 | 1366 | static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1367 | enum port port) |
da00bdcf VS |
1368 | { |
1369 | switch (port) { | |
1370 | case PORT_A: | |
1371 | return DP_AUX_CH_CTL(port); | |
1372 | case PORT_B: | |
1373 | case PORT_C: | |
1374 | case PORT_D: | |
1375 | return PCH_DP_AUX_CH_CTL(port); | |
1376 | default: | |
1377 | MISSING_CASE(port); | |
1378 | return DP_AUX_CH_CTL(PORT_A); | |
1379 | } | |
1380 | } | |
1381 | ||
f0f59a00 | 1382 | static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1383 | enum port port, int index) |
330e20ec VS |
1384 | { |
1385 | switch (port) { | |
1386 | case PORT_A: | |
1387 | return DP_AUX_CH_DATA(port, index); | |
1388 | case PORT_B: | |
1389 | case PORT_C: | |
1390 | case PORT_D: | |
1391 | return PCH_DP_AUX_CH_DATA(port, index); | |
1392 | default: | |
1393 | MISSING_CASE(port); | |
1394 | return DP_AUX_CH_DATA(PORT_A, index); | |
1395 | } | |
1396 | } | |
1397 | ||
f0f59a00 | 1398 | static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1399 | enum port port) |
da00bdcf | 1400 | { |
da00bdcf VS |
1401 | switch (port) { |
1402 | case PORT_A: | |
1403 | case PORT_B: | |
1404 | case PORT_C: | |
1405 | case PORT_D: | |
1406 | return DP_AUX_CH_CTL(port); | |
1407 | default: | |
1408 | MISSING_CASE(port); | |
1409 | return DP_AUX_CH_CTL(PORT_A); | |
1410 | } | |
1411 | } | |
1412 | ||
f0f59a00 | 1413 | static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1414 | enum port port, int index) |
330e20ec | 1415 | { |
330e20ec VS |
1416 | switch (port) { |
1417 | case PORT_A: | |
1418 | case PORT_B: | |
1419 | case PORT_C: | |
1420 | case PORT_D: | |
1421 | return DP_AUX_CH_DATA(port, index); | |
1422 | default: | |
1423 | MISSING_CASE(port); | |
1424 | return DP_AUX_CH_DATA(PORT_A, index); | |
1425 | } | |
1426 | } | |
1427 | ||
f0f59a00 | 1428 | static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1429 | enum port port) |
330e20ec VS |
1430 | { |
1431 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
1432 | return skl_aux_ctl_reg(dev_priv, port); | |
1433 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1434 | return ilk_aux_ctl_reg(dev_priv, port); | |
1435 | else | |
1436 | return g4x_aux_ctl_reg(dev_priv, port); | |
1437 | } | |
1438 | ||
f0f59a00 | 1439 | static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv, |
c8a89b08 | 1440 | enum port port, int index) |
330e20ec VS |
1441 | { |
1442 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
1443 | return skl_aux_data_reg(dev_priv, port, index); | |
1444 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1445 | return ilk_aux_data_reg(dev_priv, port, index); | |
1446 | else | |
1447 | return g4x_aux_data_reg(dev_priv, port, index); | |
1448 | } | |
1449 | ||
1450 | static void intel_aux_reg_init(struct intel_dp *intel_dp) | |
1451 | { | |
1452 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); | |
8f7ce038 VS |
1453 | enum port port = intel_aux_port(dev_priv, |
1454 | dp_to_dig_port(intel_dp)->port); | |
330e20ec VS |
1455 | int i; |
1456 | ||
1457 | intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port); | |
1458 | for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++) | |
1459 | intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i); | |
1460 | } | |
1461 | ||
9d1a1031 | 1462 | static void |
a121f4e5 VS |
1463 | intel_dp_aux_fini(struct intel_dp *intel_dp) |
1464 | { | |
a121f4e5 VS |
1465 | kfree(intel_dp->aux.name); |
1466 | } | |
1467 | ||
7a418e34 | 1468 | static void |
b6339585 | 1469 | intel_dp_aux_init(struct intel_dp *intel_dp) |
9d1a1031 | 1470 | { |
33ad6626 JN |
1471 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1472 | enum port port = intel_dig_port->port; | |
ab2c0672 | 1473 | |
330e20ec | 1474 | intel_aux_reg_init(intel_dp); |
7a418e34 | 1475 | drm_dp_aux_init(&intel_dp->aux); |
8316f337 | 1476 | |
7a418e34 | 1477 | /* Failure to allocate our preferred name is not critical */ |
a121f4e5 | 1478 | intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port)); |
9d1a1031 | 1479 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
a4fc5ed6 KP |
1480 | } |
1481 | ||
e588fa18 | 1482 | bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) |
ed63baaf | 1483 | { |
e588fa18 | 1484 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
577c5430 | 1485 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
e588fa18 | 1486 | |
577c5430 NM |
1487 | if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) || |
1488 | IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9)) | |
ed63baaf TS |
1489 | return true; |
1490 | else | |
1491 | return false; | |
1492 | } | |
1493 | ||
c6bb3538 DV |
1494 | static void |
1495 | intel_dp_set_clock(struct intel_encoder *encoder, | |
840b32b7 | 1496 | struct intel_crtc_state *pipe_config) |
c6bb3538 DV |
1497 | { |
1498 | struct drm_device *dev = encoder->base.dev; | |
6e266956 | 1499 | struct drm_i915_private *dev_priv = to_i915(dev); |
9dd4ffdf CML |
1500 | const struct dp_link_dpll *divisor = NULL; |
1501 | int i, count = 0; | |
c6bb3538 | 1502 | |
9beb5fea | 1503 | if (IS_G4X(dev_priv)) { |
9dd4ffdf CML |
1504 | divisor = gen4_dpll; |
1505 | count = ARRAY_SIZE(gen4_dpll); | |
6e266956 | 1506 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
9dd4ffdf CML |
1507 | divisor = pch_dpll; |
1508 | count = ARRAY_SIZE(pch_dpll); | |
920a14b2 | 1509 | } else if (IS_CHERRYVIEW(dev_priv)) { |
ef9348c8 CML |
1510 | divisor = chv_dpll; |
1511 | count = ARRAY_SIZE(chv_dpll); | |
11a914c2 | 1512 | } else if (IS_VALLEYVIEW(dev_priv)) { |
65ce4bf5 CML |
1513 | divisor = vlv_dpll; |
1514 | count = ARRAY_SIZE(vlv_dpll); | |
c6bb3538 | 1515 | } |
9dd4ffdf CML |
1516 | |
1517 | if (divisor && count) { | |
1518 | for (i = 0; i < count; i++) { | |
840b32b7 | 1519 | if (pipe_config->port_clock == divisor[i].clock) { |
9dd4ffdf CML |
1520 | pipe_config->dpll = divisor[i].dpll; |
1521 | pipe_config->clock_set = true; | |
1522 | break; | |
1523 | } | |
1524 | } | |
c6bb3538 DV |
1525 | } |
1526 | } | |
1527 | ||
0336400e VS |
1528 | static void snprintf_int_array(char *str, size_t len, |
1529 | const int *array, int nelem) | |
1530 | { | |
1531 | int i; | |
1532 | ||
1533 | str[0] = '\0'; | |
1534 | ||
1535 | for (i = 0; i < nelem; i++) { | |
b2f505be | 1536 | int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); |
0336400e VS |
1537 | if (r >= len) |
1538 | return; | |
1539 | str += r; | |
1540 | len -= r; | |
1541 | } | |
1542 | } | |
1543 | ||
1544 | static void intel_dp_print_rates(struct intel_dp *intel_dp) | |
1545 | { | |
0336400e VS |
1546 | char str[128]; /* FIXME: too big for stack? */ |
1547 | ||
1548 | if ((drm_debug & DRM_UT_KMS) == 0) | |
1549 | return; | |
1550 | ||
55cfc580 JN |
1551 | snprintf_int_array(str, sizeof(str), |
1552 | intel_dp->source_rates, intel_dp->num_source_rates); | |
0336400e VS |
1553 | DRM_DEBUG_KMS("source rates: %s\n", str); |
1554 | ||
68f357cb JN |
1555 | snprintf_int_array(str, sizeof(str), |
1556 | intel_dp->sink_rates, intel_dp->num_sink_rates); | |
0336400e VS |
1557 | DRM_DEBUG_KMS("sink rates: %s\n", str); |
1558 | ||
975ee5fc JN |
1559 | snprintf_int_array(str, sizeof(str), |
1560 | intel_dp->common_rates, intel_dp->num_common_rates); | |
94ca719e | 1561 | DRM_DEBUG_KMS("common rates: %s\n", str); |
0336400e VS |
1562 | } |
1563 | ||
50fec21a VS |
1564 | int |
1565 | intel_dp_max_link_rate(struct intel_dp *intel_dp) | |
1566 | { | |
50fec21a VS |
1567 | int len; |
1568 | ||
e6c0c64a | 1569 | len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate); |
50fec21a VS |
1570 | if (WARN_ON(len <= 0)) |
1571 | return 162000; | |
1572 | ||
975ee5fc | 1573 | return intel_dp->common_rates[len - 1]; |
50fec21a VS |
1574 | } |
1575 | ||
ed4e9c1d VS |
1576 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) |
1577 | { | |
8001b754 JN |
1578 | int i = intel_dp_rate_index(intel_dp->sink_rates, |
1579 | intel_dp->num_sink_rates, rate); | |
b5c72b20 JN |
1580 | |
1581 | if (WARN_ON(i < 0)) | |
1582 | i = 0; | |
1583 | ||
1584 | return i; | |
ed4e9c1d VS |
1585 | } |
1586 | ||
94223d04 ACO |
1587 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
1588 | uint8_t *link_bw, uint8_t *rate_select) | |
04a60f9f | 1589 | { |
68f357cb JN |
1590 | /* eDP 1.4 rate select method. */ |
1591 | if (intel_dp->use_rate_select) { | |
04a60f9f VS |
1592 | *link_bw = 0; |
1593 | *rate_select = | |
1594 | intel_dp_rate_select(intel_dp, port_clock); | |
1595 | } else { | |
1596 | *link_bw = drm_dp_link_rate_to_bw_code(port_clock); | |
1597 | *rate_select = 0; | |
1598 | } | |
1599 | } | |
1600 | ||
f580bea9 JN |
1601 | static int intel_dp_compute_bpp(struct intel_dp *intel_dp, |
1602 | struct intel_crtc_state *pipe_config) | |
f9bb705e MK |
1603 | { |
1604 | int bpp, bpc; | |
1605 | ||
1606 | bpp = pipe_config->pipe_bpp; | |
1607 | bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports); | |
1608 | ||
1609 | if (bpc > 0) | |
1610 | bpp = min(bpp, 3*bpc); | |
1611 | ||
611032bf MN |
1612 | /* For DP Compliance we override the computed bpp for the pipe */ |
1613 | if (intel_dp->compliance.test_data.bpc != 0) { | |
1614 | pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc; | |
1615 | pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3; | |
1616 | DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", | |
1617 | pipe_config->pipe_bpp); | |
1618 | } | |
f9bb705e MK |
1619 | return bpp; |
1620 | } | |
1621 | ||
dc911f5b JB |
1622 | static bool intel_edp_compare_alt_mode(struct drm_display_mode *m1, |
1623 | struct drm_display_mode *m2) | |
1624 | { | |
1625 | bool bres = false; | |
1626 | ||
1627 | if (m1 && m2) | |
1628 | bres = (m1->hdisplay == m2->hdisplay && | |
1629 | m1->hsync_start == m2->hsync_start && | |
1630 | m1->hsync_end == m2->hsync_end && | |
1631 | m1->htotal == m2->htotal && | |
1632 | m1->vdisplay == m2->vdisplay && | |
1633 | m1->vsync_start == m2->vsync_start && | |
1634 | m1->vsync_end == m2->vsync_end && | |
1635 | m1->vtotal == m2->vtotal); | |
1636 | return bres; | |
1637 | } | |
1638 | ||
00c09d70 | 1639 | bool |
5bfe2ac0 | 1640 | intel_dp_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
1641 | struct intel_crtc_state *pipe_config, |
1642 | struct drm_connector_state *conn_state) | |
a4fc5ed6 | 1643 | { |
dd11bc10 | 1644 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2d112de7 | 1645 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
5bfe2ac0 | 1646 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1647 | enum port port = dp_to_dig_port(intel_dp)->port; |
84556d58 | 1648 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
dd06f90e | 1649 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
8f647a01 ML |
1650 | struct intel_digital_connector_state *intel_conn_state = |
1651 | to_intel_digital_connector_state(conn_state); | |
a4fc5ed6 | 1652 | int lane_count, clock; |
56071a20 | 1653 | int min_lane_count = 1; |
eeb6324d | 1654 | int max_lane_count = intel_dp_max_lane_count(intel_dp); |
06ea66b6 | 1655 | /* Conveniently, the link BW constants become indices with a shift...*/ |
56071a20 | 1656 | int min_clock = 0; |
a8f3ef61 | 1657 | int max_clock; |
083f9560 | 1658 | int bpp, mode_rate; |
ff9a6750 | 1659 | int link_avail, link_clock; |
94ca719e | 1660 | int common_len; |
04a60f9f | 1661 | uint8_t link_bw, rate_select; |
b31e85ed JN |
1662 | bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc, |
1663 | DP_DPCD_QUIRK_LIMITED_M_N); | |
a8f3ef61 | 1664 | |
975ee5fc | 1665 | common_len = intel_dp_common_len_rate_limit(intel_dp, |
e6c0c64a | 1666 | intel_dp->max_link_rate); |
a8f3ef61 SJ |
1667 | |
1668 | /* No common link rates between source and sink */ | |
94ca719e | 1669 | WARN_ON(common_len <= 0); |
a8f3ef61 | 1670 | |
94ca719e | 1671 | max_clock = common_len - 1; |
a4fc5ed6 | 1672 | |
4f8036a2 | 1673 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) |
5bfe2ac0 DV |
1674 | pipe_config->has_pch_encoder = true; |
1675 | ||
f769cd24 | 1676 | pipe_config->has_drrs = false; |
e6b72c94 ML |
1677 | if (port == PORT_A) |
1678 | pipe_config->has_audio = false; | |
8f647a01 | 1679 | else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) |
e6b72c94 ML |
1680 | pipe_config->has_audio = intel_dp->has_audio; |
1681 | else | |
8f647a01 | 1682 | pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; |
a4fc5ed6 | 1683 | |
1853a9da | 1684 | if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
dc911f5b JB |
1685 | struct drm_display_mode *panel_mode = |
1686 | intel_connector->panel.alt_fixed_mode; | |
1687 | struct drm_display_mode *req_mode = &pipe_config->base.mode; | |
1688 | ||
1689 | if (!intel_edp_compare_alt_mode(req_mode, panel_mode)) | |
1690 | panel_mode = intel_connector->panel.fixed_mode; | |
1691 | ||
1692 | drm_mode_debug_printmodeline(panel_mode); | |
1693 | ||
1694 | intel_fixed_panel_mode(panel_mode, adjusted_mode); | |
a1b2278e | 1695 | |
dd11bc10 | 1696 | if (INTEL_GEN(dev_priv) >= 9) { |
a1b2278e | 1697 | int ret; |
e435d6e5 | 1698 | ret = skl_update_scaler_crtc(pipe_config); |
a1b2278e CK |
1699 | if (ret) |
1700 | return ret; | |
1701 | } | |
1702 | ||
49cff963 | 1703 | if (HAS_GMCH_DISPLAY(dev_priv)) |
2dd24552 | 1704 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
eead06df | 1705 | conn_state->scaling_mode); |
2dd24552 | 1706 | else |
b074cec8 | 1707 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
eead06df | 1708 | conn_state->scaling_mode); |
0d3a1bee ZY |
1709 | } |
1710 | ||
cb1793ce | 1711 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
0af78a2b DV |
1712 | return false; |
1713 | ||
da15f7cb MN |
1714 | /* Use values requested by Compliance Test Request */ |
1715 | if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { | |
ec990e21 JN |
1716 | int index; |
1717 | ||
140ef138 MN |
1718 | /* Validate the compliance test data since max values |
1719 | * might have changed due to link train fallback. | |
1720 | */ | |
1721 | if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate, | |
1722 | intel_dp->compliance.test_lane_count)) { | |
1723 | index = intel_dp_rate_index(intel_dp->common_rates, | |
1724 | intel_dp->num_common_rates, | |
1725 | intel_dp->compliance.test_link_rate); | |
1726 | if (index >= 0) | |
1727 | min_clock = max_clock = index; | |
1728 | min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count; | |
1729 | } | |
da15f7cb | 1730 | } |
083f9560 | 1731 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
a8f3ef61 | 1732 | "max bw %d pixel clock %iKHz\n", |
975ee5fc | 1733 | max_lane_count, intel_dp->common_rates[max_clock], |
241bfc38 | 1734 | adjusted_mode->crtc_clock); |
083f9560 | 1735 | |
36008365 DV |
1736 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
1737 | * bpc in between. */ | |
f9bb705e | 1738 | bpp = intel_dp_compute_bpp(intel_dp, pipe_config); |
1853a9da | 1739 | if (intel_dp_is_edp(intel_dp)) { |
22ce5628 TS |
1740 | |
1741 | /* Get bpp from vbt only for panels that dont have bpp in edid */ | |
1742 | if (intel_connector->base.display_info.bpc == 0 && | |
6aa23e65 | 1743 | (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) { |
56071a20 | 1744 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
6aa23e65 JN |
1745 | dev_priv->vbt.edp.bpp); |
1746 | bpp = dev_priv->vbt.edp.bpp; | |
56071a20 JN |
1747 | } |
1748 | ||
344c5bbc JN |
1749 | /* |
1750 | * Use the maximum clock and number of lanes the eDP panel | |
1751 | * advertizes being capable of. The panels are generally | |
1752 | * designed to support only a single clock and lane | |
1753 | * configuration, and typically these values correspond to the | |
1754 | * native resolution of the panel. | |
1755 | */ | |
1756 | min_lane_count = max_lane_count; | |
1757 | min_clock = max_clock; | |
7984211e | 1758 | } |
657445fe | 1759 | |
36008365 | 1760 | for (; bpp >= 6*3; bpp -= 2*3) { |
241bfc38 DL |
1761 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
1762 | bpp); | |
36008365 | 1763 | |
c6930992 | 1764 | for (clock = min_clock; clock <= max_clock; clock++) { |
a8f3ef61 SJ |
1765 | for (lane_count = min_lane_count; |
1766 | lane_count <= max_lane_count; | |
1767 | lane_count <<= 1) { | |
1768 | ||
975ee5fc | 1769 | link_clock = intel_dp->common_rates[clock]; |
36008365 DV |
1770 | link_avail = intel_dp_max_data_rate(link_clock, |
1771 | lane_count); | |
1772 | ||
1773 | if (mode_rate <= link_avail) { | |
1774 | goto found; | |
1775 | } | |
1776 | } | |
1777 | } | |
1778 | } | |
c4867936 | 1779 | |
36008365 | 1780 | return false; |
3685a8f3 | 1781 | |
36008365 | 1782 | found: |
8f647a01 | 1783 | if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { |
55bc60db VS |
1784 | /* |
1785 | * See: | |
1786 | * CEA-861-E - 5.1 Default Encoding Parameters | |
1787 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry | |
1788 | */ | |
0f2a2a75 | 1789 | pipe_config->limited_color_range = |
c8127cf0 VS |
1790 | bpp != 18 && |
1791 | drm_default_rgb_quant_range(adjusted_mode) == | |
1792 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
0f2a2a75 VS |
1793 | } else { |
1794 | pipe_config->limited_color_range = | |
8f647a01 | 1795 | intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; |
55bc60db VS |
1796 | } |
1797 | ||
90a6b7b0 | 1798 | pipe_config->lane_count = lane_count; |
a8f3ef61 | 1799 | |
657445fe | 1800 | pipe_config->pipe_bpp = bpp; |
975ee5fc | 1801 | pipe_config->port_clock = intel_dp->common_rates[clock]; |
a4fc5ed6 | 1802 | |
04a60f9f VS |
1803 | intel_dp_compute_rate(intel_dp, pipe_config->port_clock, |
1804 | &link_bw, &rate_select); | |
1805 | ||
1806 | DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n", | |
1807 | link_bw, rate_select, pipe_config->lane_count, | |
ff9a6750 | 1808 | pipe_config->port_clock, bpp); |
36008365 DV |
1809 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
1810 | mode_rate, link_avail); | |
a4fc5ed6 | 1811 | |
03afc4a2 | 1812 | intel_link_compute_m_n(bpp, lane_count, |
241bfc38 DL |
1813 | adjusted_mode->crtc_clock, |
1814 | pipe_config->port_clock, | |
b31e85ed JN |
1815 | &pipe_config->dp_m_n, |
1816 | reduce_m_n); | |
9d1a455b | 1817 | |
439d7ac0 | 1818 | if (intel_connector->panel.downclock_mode != NULL && |
96178eeb | 1819 | dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { |
f769cd24 | 1820 | pipe_config->has_drrs = true; |
439d7ac0 PB |
1821 | intel_link_compute_m_n(bpp, lane_count, |
1822 | intel_connector->panel.downclock_mode->clock, | |
1823 | pipe_config->port_clock, | |
b31e85ed JN |
1824 | &pipe_config->dp_m2_n2, |
1825 | reduce_m_n); | |
439d7ac0 PB |
1826 | } |
1827 | ||
14d41b3b VS |
1828 | /* |
1829 | * DPLL0 VCO may need to be adjusted to get the correct | |
1830 | * clock for eDP. This will affect cdclk as well. | |
1831 | */ | |
1853a9da | 1832 | if (intel_dp_is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) { |
14d41b3b VS |
1833 | int vco; |
1834 | ||
1835 | switch (pipe_config->port_clock / 2) { | |
1836 | case 108000: | |
1837 | case 216000: | |
63911d72 | 1838 | vco = 8640000; |
14d41b3b VS |
1839 | break; |
1840 | default: | |
63911d72 | 1841 | vco = 8100000; |
14d41b3b VS |
1842 | break; |
1843 | } | |
1844 | ||
bb0f4aab | 1845 | to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco; |
14d41b3b VS |
1846 | } |
1847 | ||
4f8036a2 | 1848 | if (!HAS_DDI(dev_priv)) |
840b32b7 | 1849 | intel_dp_set_clock(encoder, pipe_config); |
c6bb3538 | 1850 | |
03afc4a2 | 1851 | return true; |
a4fc5ed6 KP |
1852 | } |
1853 | ||
901c2daf | 1854 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
dfa10480 ACO |
1855 | int link_rate, uint8_t lane_count, |
1856 | bool link_mst) | |
901c2daf | 1857 | { |
dfa10480 ACO |
1858 | intel_dp->link_rate = link_rate; |
1859 | intel_dp->lane_count = lane_count; | |
1860 | intel_dp->link_mst = link_mst; | |
901c2daf VS |
1861 | } |
1862 | ||
85cb48a1 | 1863 | static void intel_dp_prepare(struct intel_encoder *encoder, |
5f88a9c6 | 1864 | const struct intel_crtc_state *pipe_config) |
a4fc5ed6 | 1865 | { |
b934223d | 1866 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1867 | struct drm_i915_private *dev_priv = to_i915(dev); |
b934223d | 1868 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 1869 | enum port port = dp_to_dig_port(intel_dp)->port; |
b934223d | 1870 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
85cb48a1 | 1871 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
a4fc5ed6 | 1872 | |
dfa10480 ACO |
1873 | intel_dp_set_link_params(intel_dp, pipe_config->port_clock, |
1874 | pipe_config->lane_count, | |
1875 | intel_crtc_has_type(pipe_config, | |
1876 | INTEL_OUTPUT_DP_MST)); | |
901c2daf | 1877 | |
417e822d | 1878 | /* |
1a2eb460 | 1879 | * There are four kinds of DP registers: |
417e822d KP |
1880 | * |
1881 | * IBX PCH | |
1a2eb460 KP |
1882 | * SNB CPU |
1883 | * IVB CPU | |
417e822d KP |
1884 | * CPT PCH |
1885 | * | |
1886 | * IBX PCH and CPU are the same for almost everything, | |
1887 | * except that the CPU DP PLL is configured in this | |
1888 | * register | |
1889 | * | |
1890 | * CPT PCH is quite different, having many bits moved | |
1891 | * to the TRANS_DP_CTL register instead. That | |
1892 | * configuration happens (oddly) in ironlake_pch_enable | |
1893 | */ | |
9c9e7927 | 1894 | |
417e822d KP |
1895 | /* Preserve the BIOS-computed detected bit. This is |
1896 | * supposed to be read-only. | |
1897 | */ | |
1898 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; | |
a4fc5ed6 | 1899 | |
417e822d | 1900 | /* Handle DP bits in common between all three register formats */ |
417e822d | 1901 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
85cb48a1 | 1902 | intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); |
a4fc5ed6 | 1903 | |
417e822d | 1904 | /* Split out the IBX/CPU vs CPT settings */ |
32f9d658 | 1905 | |
5db94019 | 1906 | if (IS_GEN7(dev_priv) && port == PORT_A) { |
1a2eb460 KP |
1907 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
1908 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1909 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1910 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1911 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; | |
1912 | ||
6aba5b6c | 1913 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
1a2eb460 KP |
1914 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1915 | ||
7c62a164 | 1916 | intel_dp->DP |= crtc->pipe << 29; |
6e266956 | 1917 | } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
e3ef4479 VS |
1918 | u32 trans_dp; |
1919 | ||
39e5fa88 | 1920 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
e3ef4479 VS |
1921 | |
1922 | trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); | |
1923 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
1924 | trans_dp |= TRANS_DP_ENH_FRAMING; | |
1925 | else | |
1926 | trans_dp &= ~TRANS_DP_ENH_FRAMING; | |
1927 | I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); | |
39e5fa88 | 1928 | } else { |
c99f53f7 | 1929 | if (IS_G4X(dev_priv) && pipe_config->limited_color_range) |
0f2a2a75 | 1930 | intel_dp->DP |= DP_COLOR_RANGE_16_235; |
417e822d KP |
1931 | |
1932 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
1933 | intel_dp->DP |= DP_SYNC_HS_HIGH; | |
1934 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
1935 | intel_dp->DP |= DP_SYNC_VS_HIGH; | |
1936 | intel_dp->DP |= DP_LINK_TRAIN_OFF; | |
1937 | ||
6aba5b6c | 1938 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
417e822d KP |
1939 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
1940 | ||
920a14b2 | 1941 | if (IS_CHERRYVIEW(dev_priv)) |
44f37d1f | 1942 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
39e5fa88 VS |
1943 | else if (crtc->pipe == PIPE_B) |
1944 | intel_dp->DP |= DP_PIPEB_SELECT; | |
32f9d658 | 1945 | } |
a4fc5ed6 KP |
1946 | } |
1947 | ||
ffd6749d PZ |
1948 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1949 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) | |
99ea7127 | 1950 | |
1a5ef5b7 PZ |
1951 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
1952 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) | |
99ea7127 | 1953 | |
ffd6749d PZ |
1954 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
1955 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) | |
99ea7127 | 1956 | |
de9c1b6b ID |
1957 | static void intel_pps_verify_state(struct drm_i915_private *dev_priv, |
1958 | struct intel_dp *intel_dp); | |
1959 | ||
4be73780 | 1960 | static void wait_panel_status(struct intel_dp *intel_dp, |
99ea7127 KP |
1961 | u32 mask, |
1962 | u32 value) | |
bd943159 | 1963 | { |
30add22d | 1964 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 1965 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 1966 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
453c5420 | 1967 | |
e39b999a VS |
1968 | lockdep_assert_held(&dev_priv->pps_mutex); |
1969 | ||
de9c1b6b ID |
1970 | intel_pps_verify_state(dev_priv, intel_dp); |
1971 | ||
bf13e81b JN |
1972 | pp_stat_reg = _pp_stat_reg(intel_dp); |
1973 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
32ce697c | 1974 | |
99ea7127 | 1975 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
453c5420 JB |
1976 | mask, value, |
1977 | I915_READ(pp_stat_reg), | |
1978 | I915_READ(pp_ctrl_reg)); | |
32ce697c | 1979 | |
9036ff06 CW |
1980 | if (intel_wait_for_register(dev_priv, |
1981 | pp_stat_reg, mask, value, | |
1982 | 5000)) | |
99ea7127 | 1983 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
453c5420 JB |
1984 | I915_READ(pp_stat_reg), |
1985 | I915_READ(pp_ctrl_reg)); | |
54c136d4 CW |
1986 | |
1987 | DRM_DEBUG_KMS("Wait complete\n"); | |
99ea7127 | 1988 | } |
32ce697c | 1989 | |
4be73780 | 1990 | static void wait_panel_on(struct intel_dp *intel_dp) |
99ea7127 KP |
1991 | { |
1992 | DRM_DEBUG_KMS("Wait for panel power on\n"); | |
4be73780 | 1993 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
bd943159 KP |
1994 | } |
1995 | ||
4be73780 | 1996 | static void wait_panel_off(struct intel_dp *intel_dp) |
99ea7127 KP |
1997 | { |
1998 | DRM_DEBUG_KMS("Wait for panel power off time\n"); | |
4be73780 | 1999 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
99ea7127 KP |
2000 | } |
2001 | ||
4be73780 | 2002 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
99ea7127 | 2003 | { |
d28d4731 AK |
2004 | ktime_t panel_power_on_time; |
2005 | s64 panel_power_off_duration; | |
2006 | ||
99ea7127 | 2007 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
dce56b3c | 2008 | |
d28d4731 AK |
2009 | /* take the difference of currrent time and panel power off time |
2010 | * and then make panel wait for t11_t12 if needed. */ | |
2011 | panel_power_on_time = ktime_get_boottime(); | |
2012 | panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); | |
2013 | ||
dce56b3c PZ |
2014 | /* When we disable the VDD override bit last we have to do the manual |
2015 | * wait. */ | |
d28d4731 AK |
2016 | if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) |
2017 | wait_remaining_ms_from_jiffies(jiffies, | |
2018 | intel_dp->panel_power_cycle_delay - panel_power_off_duration); | |
dce56b3c | 2019 | |
4be73780 | 2020 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
99ea7127 KP |
2021 | } |
2022 | ||
4be73780 | 2023 | static void wait_backlight_on(struct intel_dp *intel_dp) |
dce56b3c PZ |
2024 | { |
2025 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, | |
2026 | intel_dp->backlight_on_delay); | |
2027 | } | |
2028 | ||
4be73780 | 2029 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
dce56b3c PZ |
2030 | { |
2031 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, | |
2032 | intel_dp->backlight_off_delay); | |
2033 | } | |
99ea7127 | 2034 | |
832dd3c1 KP |
2035 | /* Read the current pp_control value, unlocking the register if it |
2036 | * is locked | |
2037 | */ | |
2038 | ||
453c5420 | 2039 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
832dd3c1 | 2040 | { |
453c5420 | 2041 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2042 | struct drm_i915_private *dev_priv = to_i915(dev); |
453c5420 | 2043 | u32 control; |
832dd3c1 | 2044 | |
e39b999a VS |
2045 | lockdep_assert_held(&dev_priv->pps_mutex); |
2046 | ||
bf13e81b | 2047 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
8090ba8c ID |
2048 | if (WARN_ON(!HAS_DDI(dev_priv) && |
2049 | (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { | |
b0a08bec VK |
2050 | control &= ~PANEL_UNLOCK_MASK; |
2051 | control |= PANEL_UNLOCK_REGS; | |
2052 | } | |
832dd3c1 | 2053 | return control; |
bd943159 KP |
2054 | } |
2055 | ||
951468f3 VS |
2056 | /* |
2057 | * Must be paired with edp_panel_vdd_off(). | |
2058 | * Must hold pps_mutex around the whole on/off sequence. | |
2059 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
2060 | */ | |
1e0560e0 | 2061 | static bool edp_panel_vdd_on(struct intel_dp *intel_dp) |
5d613501 | 2062 | { |
30add22d | 2063 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
4e6e1a54 | 2064 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
fac5e23e | 2065 | struct drm_i915_private *dev_priv = to_i915(dev); |
5d613501 | 2066 | u32 pp; |
f0f59a00 | 2067 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
adddaaf4 | 2068 | bool need_to_disable = !intel_dp->want_panel_vdd; |
5d613501 | 2069 | |
e39b999a VS |
2070 | lockdep_assert_held(&dev_priv->pps_mutex); |
2071 | ||
1853a9da | 2072 | if (!intel_dp_is_edp(intel_dp)) |
adddaaf4 | 2073 | return false; |
bd943159 | 2074 | |
2c623c11 | 2075 | cancel_delayed_work(&intel_dp->panel_vdd_work); |
bd943159 | 2076 | intel_dp->want_panel_vdd = true; |
99ea7127 | 2077 | |
4be73780 | 2078 | if (edp_have_panel_vdd(intel_dp)) |
adddaaf4 | 2079 | return need_to_disable; |
b0665d57 | 2080 | |
5432fcaf | 2081 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
e9cb81a2 | 2082 | |
3936fcf4 VS |
2083 | DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", |
2084 | port_name(intel_dig_port->port)); | |
bd943159 | 2085 | |
4be73780 DV |
2086 | if (!edp_have_panel_power(intel_dp)) |
2087 | wait_panel_power_cycle(intel_dp); | |
99ea7127 | 2088 | |
453c5420 | 2089 | pp = ironlake_get_pp_control(intel_dp); |
5d613501 | 2090 | pp |= EDP_FORCE_VDD; |
ebf33b18 | 2091 | |
bf13e81b JN |
2092 | pp_stat_reg = _pp_stat_reg(intel_dp); |
2093 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); | |
453c5420 JB |
2094 | |
2095 | I915_WRITE(pp_ctrl_reg, pp); | |
2096 | POSTING_READ(pp_ctrl_reg); | |
2097 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
2098 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
ebf33b18 KP |
2099 | /* |
2100 | * If the panel wasn't on, delay before accessing aux channel | |
2101 | */ | |
4be73780 | 2102 | if (!edp_have_panel_power(intel_dp)) { |
3936fcf4 VS |
2103 | DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", |
2104 | port_name(intel_dig_port->port)); | |
f01eca2e | 2105 | msleep(intel_dp->panel_power_up_delay); |
f01eca2e | 2106 | } |
adddaaf4 JN |
2107 | |
2108 | return need_to_disable; | |
2109 | } | |
2110 | ||
951468f3 VS |
2111 | /* |
2112 | * Must be paired with intel_edp_panel_vdd_off() or | |
2113 | * intel_edp_panel_off(). | |
2114 | * Nested calls to these functions are not allowed since | |
2115 | * we drop the lock. Caller must use some higher level | |
2116 | * locking to prevent nested calls from other threads. | |
2117 | */ | |
b80d6c78 | 2118 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
adddaaf4 | 2119 | { |
c695b6b6 | 2120 | bool vdd; |
adddaaf4 | 2121 | |
1853a9da | 2122 | if (!intel_dp_is_edp(intel_dp)) |
c695b6b6 VS |
2123 | return; |
2124 | ||
773538e8 | 2125 | pps_lock(intel_dp); |
c695b6b6 | 2126 | vdd = edp_panel_vdd_on(intel_dp); |
773538e8 | 2127 | pps_unlock(intel_dp); |
c695b6b6 | 2128 | |
e2c719b7 | 2129 | I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", |
3936fcf4 | 2130 | port_name(dp_to_dig_port(intel_dp)->port)); |
5d613501 JB |
2131 | } |
2132 | ||
4be73780 | 2133 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
5d613501 | 2134 | { |
30add22d | 2135 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2136 | struct drm_i915_private *dev_priv = to_i915(dev); |
be2c9196 VS |
2137 | struct intel_digital_port *intel_dig_port = |
2138 | dp_to_dig_port(intel_dp); | |
5d613501 | 2139 | u32 pp; |
f0f59a00 | 2140 | i915_reg_t pp_stat_reg, pp_ctrl_reg; |
5d613501 | 2141 | |
e39b999a | 2142 | lockdep_assert_held(&dev_priv->pps_mutex); |
a0e99e68 | 2143 | |
15e899a0 | 2144 | WARN_ON(intel_dp->want_panel_vdd); |
4e6e1a54 | 2145 | |
15e899a0 | 2146 | if (!edp_have_panel_vdd(intel_dp)) |
be2c9196 | 2147 | return; |
b0665d57 | 2148 | |
3936fcf4 VS |
2149 | DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", |
2150 | port_name(intel_dig_port->port)); | |
bd943159 | 2151 | |
be2c9196 VS |
2152 | pp = ironlake_get_pp_control(intel_dp); |
2153 | pp &= ~EDP_FORCE_VDD; | |
453c5420 | 2154 | |
be2c9196 VS |
2155 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
2156 | pp_stat_reg = _pp_stat_reg(intel_dp); | |
99ea7127 | 2157 | |
be2c9196 VS |
2158 | I915_WRITE(pp_ctrl_reg, pp); |
2159 | POSTING_READ(pp_ctrl_reg); | |
90791a5c | 2160 | |
be2c9196 VS |
2161 | /* Make sure sequencer is idle before allowing subsequent activity */ |
2162 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", | |
2163 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); | |
e9cb81a2 | 2164 | |
5a162e22 | 2165 | if ((pp & PANEL_POWER_ON) == 0) |
d28d4731 | 2166 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
e9cb81a2 | 2167 | |
5432fcaf | 2168 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
bd943159 | 2169 | } |
5d613501 | 2170 | |
4be73780 | 2171 | static void edp_panel_vdd_work(struct work_struct *__work) |
bd943159 KP |
2172 | { |
2173 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), | |
2174 | struct intel_dp, panel_vdd_work); | |
bd943159 | 2175 | |
773538e8 | 2176 | pps_lock(intel_dp); |
15e899a0 VS |
2177 | if (!intel_dp->want_panel_vdd) |
2178 | edp_panel_vdd_off_sync(intel_dp); | |
773538e8 | 2179 | pps_unlock(intel_dp); |
bd943159 KP |
2180 | } |
2181 | ||
aba86890 ID |
2182 | static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) |
2183 | { | |
2184 | unsigned long delay; | |
2185 | ||
2186 | /* | |
2187 | * Queue the timer to fire a long time from now (relative to the power | |
2188 | * down delay) to keep the panel power up across a sequence of | |
2189 | * operations. | |
2190 | */ | |
2191 | delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); | |
2192 | schedule_delayed_work(&intel_dp->panel_vdd_work, delay); | |
2193 | } | |
2194 | ||
951468f3 VS |
2195 | /* |
2196 | * Must be paired with edp_panel_vdd_on(). | |
2197 | * Must hold pps_mutex around the whole on/off sequence. | |
2198 | * Can be nested with intel_edp_panel_vdd_{on,off}() calls. | |
2199 | */ | |
4be73780 | 2200 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
bd943159 | 2201 | { |
fac5e23e | 2202 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
e39b999a VS |
2203 | |
2204 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2205 | ||
1853a9da | 2206 | if (!intel_dp_is_edp(intel_dp)) |
97af61f5 | 2207 | return; |
5d613501 | 2208 | |
e2c719b7 | 2209 | I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", |
3936fcf4 | 2210 | port_name(dp_to_dig_port(intel_dp)->port)); |
f2e8b18a | 2211 | |
bd943159 KP |
2212 | intel_dp->want_panel_vdd = false; |
2213 | ||
aba86890 | 2214 | if (sync) |
4be73780 | 2215 | edp_panel_vdd_off_sync(intel_dp); |
aba86890 ID |
2216 | else |
2217 | edp_panel_vdd_schedule_off(intel_dp); | |
5d613501 JB |
2218 | } |
2219 | ||
9f0fb5be | 2220 | static void edp_panel_on(struct intel_dp *intel_dp) |
9934c132 | 2221 | { |
30add22d | 2222 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2223 | struct drm_i915_private *dev_priv = to_i915(dev); |
99ea7127 | 2224 | u32 pp; |
f0f59a00 | 2225 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2226 | |
9f0fb5be VS |
2227 | lockdep_assert_held(&dev_priv->pps_mutex); |
2228 | ||
1853a9da | 2229 | if (!intel_dp_is_edp(intel_dp)) |
bd943159 | 2230 | return; |
99ea7127 | 2231 | |
3936fcf4 VS |
2232 | DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", |
2233 | port_name(dp_to_dig_port(intel_dp)->port)); | |
e39b999a | 2234 | |
e7a89ace VS |
2235 | if (WARN(edp_have_panel_power(intel_dp), |
2236 | "eDP port %c panel power already on\n", | |
2237 | port_name(dp_to_dig_port(intel_dp)->port))) | |
9f0fb5be | 2238 | return; |
9934c132 | 2239 | |
4be73780 | 2240 | wait_panel_power_cycle(intel_dp); |
37c6c9b0 | 2241 | |
bf13e81b | 2242 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2243 | pp = ironlake_get_pp_control(intel_dp); |
5db94019 | 2244 | if (IS_GEN5(dev_priv)) { |
05ce1a49 KP |
2245 | /* ILK workaround: disable reset around power sequence */ |
2246 | pp &= ~PANEL_POWER_RESET; | |
bf13e81b JN |
2247 | I915_WRITE(pp_ctrl_reg, pp); |
2248 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2249 | } |
37c6c9b0 | 2250 | |
5a162e22 | 2251 | pp |= PANEL_POWER_ON; |
5db94019 | 2252 | if (!IS_GEN5(dev_priv)) |
99ea7127 KP |
2253 | pp |= PANEL_POWER_RESET; |
2254 | ||
453c5420 JB |
2255 | I915_WRITE(pp_ctrl_reg, pp); |
2256 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2257 | |
4be73780 | 2258 | wait_panel_on(intel_dp); |
dce56b3c | 2259 | intel_dp->last_power_on = jiffies; |
9934c132 | 2260 | |
5db94019 | 2261 | if (IS_GEN5(dev_priv)) { |
05ce1a49 | 2262 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
bf13e81b JN |
2263 | I915_WRITE(pp_ctrl_reg, pp); |
2264 | POSTING_READ(pp_ctrl_reg); | |
05ce1a49 | 2265 | } |
9f0fb5be | 2266 | } |
e39b999a | 2267 | |
9f0fb5be VS |
2268 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
2269 | { | |
1853a9da | 2270 | if (!intel_dp_is_edp(intel_dp)) |
9f0fb5be VS |
2271 | return; |
2272 | ||
2273 | pps_lock(intel_dp); | |
2274 | edp_panel_on(intel_dp); | |
773538e8 | 2275 | pps_unlock(intel_dp); |
9934c132 JB |
2276 | } |
2277 | ||
9f0fb5be VS |
2278 | |
2279 | static void edp_panel_off(struct intel_dp *intel_dp) | |
9934c132 | 2280 | { |
30add22d | 2281 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2282 | struct drm_i915_private *dev_priv = to_i915(dev); |
99ea7127 | 2283 | u32 pp; |
f0f59a00 | 2284 | i915_reg_t pp_ctrl_reg; |
9934c132 | 2285 | |
9f0fb5be VS |
2286 | lockdep_assert_held(&dev_priv->pps_mutex); |
2287 | ||
1853a9da | 2288 | if (!intel_dp_is_edp(intel_dp)) |
97af61f5 | 2289 | return; |
37c6c9b0 | 2290 | |
3936fcf4 VS |
2291 | DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", |
2292 | port_name(dp_to_dig_port(intel_dp)->port)); | |
37c6c9b0 | 2293 | |
3936fcf4 VS |
2294 | WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", |
2295 | port_name(dp_to_dig_port(intel_dp)->port)); | |
24f3e092 | 2296 | |
453c5420 | 2297 | pp = ironlake_get_pp_control(intel_dp); |
35a38556 DV |
2298 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
2299 | * panels get very unhappy and cease to work. */ | |
5a162e22 | 2300 | pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
b3064154 | 2301 | EDP_BLC_ENABLE); |
453c5420 | 2302 | |
bf13e81b | 2303 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 | 2304 | |
849e39f5 PZ |
2305 | intel_dp->want_panel_vdd = false; |
2306 | ||
453c5420 JB |
2307 | I915_WRITE(pp_ctrl_reg, pp); |
2308 | POSTING_READ(pp_ctrl_reg); | |
9934c132 | 2309 | |
d28d4731 | 2310 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
4be73780 | 2311 | wait_panel_off(intel_dp); |
849e39f5 PZ |
2312 | |
2313 | /* We got a reference when we enabled the VDD. */ | |
5432fcaf | 2314 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
9f0fb5be | 2315 | } |
e39b999a | 2316 | |
9f0fb5be VS |
2317 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
2318 | { | |
1853a9da | 2319 | if (!intel_dp_is_edp(intel_dp)) |
9f0fb5be | 2320 | return; |
e39b999a | 2321 | |
9f0fb5be VS |
2322 | pps_lock(intel_dp); |
2323 | edp_panel_off(intel_dp); | |
773538e8 | 2324 | pps_unlock(intel_dp); |
9934c132 JB |
2325 | } |
2326 | ||
1250d107 JN |
2327 | /* Enable backlight in the panel power control. */ |
2328 | static void _intel_edp_backlight_on(struct intel_dp *intel_dp) | |
32f9d658 | 2329 | { |
da63a9f2 PZ |
2330 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2331 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 2332 | struct drm_i915_private *dev_priv = to_i915(dev); |
32f9d658 | 2333 | u32 pp; |
f0f59a00 | 2334 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2335 | |
01cb9ea6 JB |
2336 | /* |
2337 | * If we enable the backlight right away following a panel power | |
2338 | * on, we may see slight flicker as the panel syncs with the eDP | |
2339 | * link. So delay a bit to make sure the image is solid before | |
2340 | * allowing it to appear. | |
2341 | */ | |
4be73780 | 2342 | wait_backlight_on(intel_dp); |
e39b999a | 2343 | |
773538e8 | 2344 | pps_lock(intel_dp); |
e39b999a | 2345 | |
453c5420 | 2346 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2347 | pp |= EDP_BLC_ENABLE; |
453c5420 | 2348 | |
bf13e81b | 2349 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2350 | |
2351 | I915_WRITE(pp_ctrl_reg, pp); | |
2352 | POSTING_READ(pp_ctrl_reg); | |
e39b999a | 2353 | |
773538e8 | 2354 | pps_unlock(intel_dp); |
32f9d658 ZW |
2355 | } |
2356 | ||
1250d107 | 2357 | /* Enable backlight PWM and backlight PP control. */ |
b037d58f ML |
2358 | void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, |
2359 | const struct drm_connector_state *conn_state) | |
1250d107 | 2360 | { |
b037d58f ML |
2361 | struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder); |
2362 | ||
1853a9da | 2363 | if (!intel_dp_is_edp(intel_dp)) |
1250d107 JN |
2364 | return; |
2365 | ||
2366 | DRM_DEBUG_KMS("\n"); | |
2367 | ||
b037d58f | 2368 | intel_panel_enable_backlight(crtc_state, conn_state); |
1250d107 JN |
2369 | _intel_edp_backlight_on(intel_dp); |
2370 | } | |
2371 | ||
2372 | /* Disable backlight in the panel power control. */ | |
2373 | static void _intel_edp_backlight_off(struct intel_dp *intel_dp) | |
32f9d658 | 2374 | { |
30add22d | 2375 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
fac5e23e | 2376 | struct drm_i915_private *dev_priv = to_i915(dev); |
32f9d658 | 2377 | u32 pp; |
f0f59a00 | 2378 | i915_reg_t pp_ctrl_reg; |
32f9d658 | 2379 | |
1853a9da | 2380 | if (!intel_dp_is_edp(intel_dp)) |
f01eca2e KP |
2381 | return; |
2382 | ||
773538e8 | 2383 | pps_lock(intel_dp); |
e39b999a | 2384 | |
453c5420 | 2385 | pp = ironlake_get_pp_control(intel_dp); |
32f9d658 | 2386 | pp &= ~EDP_BLC_ENABLE; |
453c5420 | 2387 | |
bf13e81b | 2388 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
453c5420 JB |
2389 | |
2390 | I915_WRITE(pp_ctrl_reg, pp); | |
2391 | POSTING_READ(pp_ctrl_reg); | |
f7d2323c | 2392 | |
773538e8 | 2393 | pps_unlock(intel_dp); |
e39b999a VS |
2394 | |
2395 | intel_dp->last_backlight_off = jiffies; | |
f7d2323c | 2396 | edp_wait_backlight_off(intel_dp); |
1250d107 | 2397 | } |
f7d2323c | 2398 | |
1250d107 | 2399 | /* Disable backlight PP control and backlight PWM. */ |
b037d58f | 2400 | void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) |
1250d107 | 2401 | { |
b037d58f ML |
2402 | struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder); |
2403 | ||
1853a9da | 2404 | if (!intel_dp_is_edp(intel_dp)) |
1250d107 JN |
2405 | return; |
2406 | ||
2407 | DRM_DEBUG_KMS("\n"); | |
f7d2323c | 2408 | |
1250d107 | 2409 | _intel_edp_backlight_off(intel_dp); |
b037d58f | 2410 | intel_panel_disable_backlight(old_conn_state); |
32f9d658 | 2411 | } |
a4fc5ed6 | 2412 | |
73580fb7 JN |
2413 | /* |
2414 | * Hook for controlling the panel power control backlight through the bl_power | |
2415 | * sysfs attribute. Take care to handle multiple calls. | |
2416 | */ | |
2417 | static void intel_edp_backlight_power(struct intel_connector *connector, | |
2418 | bool enable) | |
2419 | { | |
2420 | struct intel_dp *intel_dp = intel_attached_dp(&connector->base); | |
e39b999a VS |
2421 | bool is_enabled; |
2422 | ||
773538e8 | 2423 | pps_lock(intel_dp); |
e39b999a | 2424 | is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; |
773538e8 | 2425 | pps_unlock(intel_dp); |
73580fb7 JN |
2426 | |
2427 | if (is_enabled == enable) | |
2428 | return; | |
2429 | ||
23ba9373 JN |
2430 | DRM_DEBUG_KMS("panel power control backlight %s\n", |
2431 | enable ? "enable" : "disable"); | |
73580fb7 JN |
2432 | |
2433 | if (enable) | |
2434 | _intel_edp_backlight_on(intel_dp); | |
2435 | else | |
2436 | _intel_edp_backlight_off(intel_dp); | |
2437 | } | |
2438 | ||
64e1077a VS |
2439 | static void assert_dp_port(struct intel_dp *intel_dp, bool state) |
2440 | { | |
2441 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
2442 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); | |
2443 | bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; | |
2444 | ||
2445 | I915_STATE_WARN(cur_state != state, | |
2446 | "DP port %c state assertion failure (expected %s, current %s)\n", | |
2447 | port_name(dig_port->port), | |
87ad3212 | 2448 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2449 | } |
2450 | #define assert_dp_port_disabled(d) assert_dp_port((d), false) | |
2451 | ||
2452 | static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) | |
2453 | { | |
2454 | bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; | |
2455 | ||
2456 | I915_STATE_WARN(cur_state != state, | |
2457 | "eDP PLL state assertion failure (expected %s, current %s)\n", | |
87ad3212 | 2458 | onoff(state), onoff(cur_state)); |
64e1077a VS |
2459 | } |
2460 | #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) | |
2461 | #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) | |
2462 | ||
85cb48a1 | 2463 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp, |
5f88a9c6 | 2464 | const struct intel_crtc_state *pipe_config) |
d240f20f | 2465 | { |
85cb48a1 | 2466 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
64e1077a | 2467 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d240f20f | 2468 | |
64e1077a VS |
2469 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2470 | assert_dp_port_disabled(intel_dp); | |
2471 | assert_edp_pll_disabled(dev_priv); | |
2bd2ad64 | 2472 | |
abfce949 | 2473 | DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", |
85cb48a1 | 2474 | pipe_config->port_clock); |
abfce949 VS |
2475 | |
2476 | intel_dp->DP &= ~DP_PLL_FREQ_MASK; | |
2477 | ||
85cb48a1 | 2478 | if (pipe_config->port_clock == 162000) |
abfce949 VS |
2479 | intel_dp->DP |= DP_PLL_FREQ_162MHZ; |
2480 | else | |
2481 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; | |
2482 | ||
2483 | I915_WRITE(DP_A, intel_dp->DP); | |
2484 | POSTING_READ(DP_A); | |
2485 | udelay(500); | |
2486 | ||
6b23f3e8 VS |
2487 | /* |
2488 | * [DevILK] Work around required when enabling DP PLL | |
2489 | * while a pipe is enabled going to FDI: | |
2490 | * 1. Wait for the start of vertical blank on the enabled pipe going to FDI | |
2491 | * 2. Program DP PLL enable | |
2492 | */ | |
2493 | if (IS_GEN5(dev_priv)) | |
0f0f74bc | 2494 | intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); |
6b23f3e8 | 2495 | |
0767935e | 2496 | intel_dp->DP |= DP_PLL_ENABLE; |
6fec7662 | 2497 | |
0767935e | 2498 | I915_WRITE(DP_A, intel_dp->DP); |
298b0b39 JB |
2499 | POSTING_READ(DP_A); |
2500 | udelay(200); | |
d240f20f JB |
2501 | } |
2502 | ||
2bd2ad64 | 2503 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
d240f20f | 2504 | { |
da63a9f2 | 2505 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
64e1077a VS |
2506 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
2507 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
d240f20f | 2508 | |
64e1077a VS |
2509 | assert_pipe_disabled(dev_priv, crtc->pipe); |
2510 | assert_dp_port_disabled(intel_dp); | |
2511 | assert_edp_pll_enabled(dev_priv); | |
2bd2ad64 | 2512 | |
abfce949 VS |
2513 | DRM_DEBUG_KMS("disabling eDP PLL\n"); |
2514 | ||
6fec7662 | 2515 | intel_dp->DP &= ~DP_PLL_ENABLE; |
0767935e | 2516 | |
6fec7662 | 2517 | I915_WRITE(DP_A, intel_dp->DP); |
1af5fa1b | 2518 | POSTING_READ(DP_A); |
d240f20f JB |
2519 | udelay(200); |
2520 | } | |
2521 | ||
c7ad3810 | 2522 | /* If the sink supports it, try to set the power state appropriately */ |
c19b0669 | 2523 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
c7ad3810 JB |
2524 | { |
2525 | int ret, i; | |
2526 | ||
2527 | /* Should have a valid DPCD by this point */ | |
2528 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) | |
2529 | return; | |
2530 | ||
2531 | if (mode != DRM_MODE_DPMS_ON) { | |
9d1a1031 JN |
2532 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2533 | DP_SET_POWER_D3); | |
c7ad3810 | 2534 | } else { |
357c0ae9 ID |
2535 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); |
2536 | ||
c7ad3810 JB |
2537 | /* |
2538 | * When turning on, we need to retry for 1ms to give the sink | |
2539 | * time to wake up. | |
2540 | */ | |
2541 | for (i = 0; i < 3; i++) { | |
9d1a1031 JN |
2542 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
2543 | DP_SET_POWER_D0); | |
c7ad3810 JB |
2544 | if (ret == 1) |
2545 | break; | |
2546 | msleep(1); | |
2547 | } | |
357c0ae9 ID |
2548 | |
2549 | if (ret == 1 && lspcon->active) | |
2550 | lspcon_wait_pcon_mode(lspcon); | |
c7ad3810 | 2551 | } |
f9cac721 JN |
2552 | |
2553 | if (ret != 1) | |
2554 | DRM_DEBUG_KMS("failed to %s sink power state\n", | |
2555 | mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); | |
c7ad3810 JB |
2556 | } |
2557 | ||
19d8fe15 DV |
2558 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
2559 | enum pipe *pipe) | |
d240f20f | 2560 | { |
19d8fe15 | 2561 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
bc7d38a4 | 2562 | enum port port = dp_to_dig_port(intel_dp)->port; |
19d8fe15 | 2563 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2564 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d129bea | 2565 | u32 tmp; |
6fa9a5ec | 2566 | bool ret; |
6d129bea | 2567 | |
79f255a0 ACO |
2568 | if (!intel_display_power_get_if_enabled(dev_priv, |
2569 | encoder->power_domain)) | |
6d129bea ID |
2570 | return false; |
2571 | ||
6fa9a5ec ID |
2572 | ret = false; |
2573 | ||
6d129bea | 2574 | tmp = I915_READ(intel_dp->output_reg); |
19d8fe15 DV |
2575 | |
2576 | if (!(tmp & DP_PORT_EN)) | |
6fa9a5ec | 2577 | goto out; |
19d8fe15 | 2578 | |
5db94019 | 2579 | if (IS_GEN7(dev_priv) && port == PORT_A) { |
19d8fe15 | 2580 | *pipe = PORT_TO_PIPE_CPT(tmp); |
6e266956 | 2581 | } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
adc289d7 | 2582 | enum pipe p; |
19d8fe15 | 2583 | |
adc289d7 VS |
2584 | for_each_pipe(dev_priv, p) { |
2585 | u32 trans_dp = I915_READ(TRANS_DP_CTL(p)); | |
2586 | if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) { | |
2587 | *pipe = p; | |
6fa9a5ec ID |
2588 | ret = true; |
2589 | ||
2590 | goto out; | |
19d8fe15 DV |
2591 | } |
2592 | } | |
19d8fe15 | 2593 | |
4a0833ec | 2594 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
f0f59a00 | 2595 | i915_mmio_reg_offset(intel_dp->output_reg)); |
920a14b2 | 2596 | } else if (IS_CHERRYVIEW(dev_priv)) { |
39e5fa88 VS |
2597 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
2598 | } else { | |
2599 | *pipe = PORT_TO_PIPE(tmp); | |
4a0833ec | 2600 | } |
d240f20f | 2601 | |
6fa9a5ec ID |
2602 | ret = true; |
2603 | ||
2604 | out: | |
79f255a0 | 2605 | intel_display_power_put(dev_priv, encoder->power_domain); |
6fa9a5ec ID |
2606 | |
2607 | return ret; | |
19d8fe15 | 2608 | } |
d240f20f | 2609 | |
045ac3b5 | 2610 | static void intel_dp_get_config(struct intel_encoder *encoder, |
5cec258b | 2611 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
2612 | { |
2613 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
045ac3b5 | 2614 | u32 tmp, flags = 0; |
63000ef6 | 2615 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2616 | struct drm_i915_private *dev_priv = to_i915(dev); |
63000ef6 XZ |
2617 | enum port port = dp_to_dig_port(intel_dp)->port; |
2618 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
045ac3b5 | 2619 | |
9ed109a7 | 2620 | tmp = I915_READ(intel_dp->output_reg); |
9fcb1704 JN |
2621 | |
2622 | pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; | |
9ed109a7 | 2623 | |
6e266956 | 2624 | if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { |
b81e34c2 VS |
2625 | u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
2626 | ||
2627 | if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) | |
63000ef6 XZ |
2628 | flags |= DRM_MODE_FLAG_PHSYNC; |
2629 | else | |
2630 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2631 | |
b81e34c2 | 2632 | if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
63000ef6 XZ |
2633 | flags |= DRM_MODE_FLAG_PVSYNC; |
2634 | else | |
2635 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2636 | } else { | |
39e5fa88 | 2637 | if (tmp & DP_SYNC_HS_HIGH) |
63000ef6 XZ |
2638 | flags |= DRM_MODE_FLAG_PHSYNC; |
2639 | else | |
2640 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 2641 | |
39e5fa88 | 2642 | if (tmp & DP_SYNC_VS_HIGH) |
63000ef6 XZ |
2643 | flags |= DRM_MODE_FLAG_PVSYNC; |
2644 | else | |
2645 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2646 | } | |
045ac3b5 | 2647 | |
2d112de7 | 2648 | pipe_config->base.adjusted_mode.flags |= flags; |
f1f644dc | 2649 | |
c99f53f7 | 2650 | if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235) |
8c875fca VS |
2651 | pipe_config->limited_color_range = true; |
2652 | ||
90a6b7b0 VS |
2653 | pipe_config->lane_count = |
2654 | ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; | |
2655 | ||
eb14cb74 VS |
2656 | intel_dp_get_m_n(crtc, pipe_config); |
2657 | ||
18442d08 | 2658 | if (port == PORT_A) { |
b377e0df | 2659 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) |
f1f644dc JB |
2660 | pipe_config->port_clock = 162000; |
2661 | else | |
2662 | pipe_config->port_clock = 270000; | |
2663 | } | |
18442d08 | 2664 | |
e3b247da VS |
2665 | pipe_config->base.adjusted_mode.crtc_clock = |
2666 | intel_dotclock_calculate(pipe_config->port_clock, | |
2667 | &pipe_config->dp_m_n); | |
7f16e5c1 | 2668 | |
1853a9da | 2669 | if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp && |
6aa23e65 | 2670 | pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { |
c6cd2ee2 JN |
2671 | /* |
2672 | * This is a big fat ugly hack. | |
2673 | * | |
2674 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
2675 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
2676 | * unknown we fail to light up. Yet the same BIOS boots up with | |
2677 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
2678 | * max, not what it tells us to use. | |
2679 | * | |
2680 | * Note: This will still be broken if the eDP panel is not lit | |
2681 | * up by the BIOS, and thus we can't get the mode at module | |
2682 | * load. | |
2683 | */ | |
2684 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
6aa23e65 JN |
2685 | pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); |
2686 | dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; | |
c6cd2ee2 | 2687 | } |
045ac3b5 JB |
2688 | } |
2689 | ||
fd6bbda9 | 2690 | static void intel_disable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
2691 | const struct intel_crtc_state *old_crtc_state, |
2692 | const struct drm_connector_state *old_conn_state) | |
d240f20f | 2693 | { |
e8cb4558 | 2694 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
85cb48a1 | 2695 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
495a5bb8 | 2696 | |
85cb48a1 | 2697 | if (old_crtc_state->has_audio) |
495a5bb8 | 2698 | intel_audio_codec_disable(encoder); |
6cb49835 | 2699 | |
85cb48a1 | 2700 | if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv)) |
d2419ffc | 2701 | intel_psr_disable(intel_dp, old_crtc_state); |
b32c6f48 | 2702 | |
6cb49835 DV |
2703 | /* Make sure the panel is off before trying to change the mode. But also |
2704 | * ensure that we have vdd while we switch off the panel. */ | |
24f3e092 | 2705 | intel_edp_panel_vdd_on(intel_dp); |
b037d58f | 2706 | intel_edp_backlight_off(old_conn_state); |
fdbc3b1f | 2707 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
4be73780 | 2708 | intel_edp_panel_off(intel_dp); |
3739850b | 2709 | |
08aff3fe | 2710 | /* disable the port before the pipe on g4x */ |
85cb48a1 | 2711 | if (INTEL_GEN(dev_priv) < 5) |
3739850b | 2712 | intel_dp_link_down(intel_dp); |
d240f20f JB |
2713 | } |
2714 | ||
fd6bbda9 | 2715 | static void ilk_post_disable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
2716 | const struct intel_crtc_state *old_crtc_state, |
2717 | const struct drm_connector_state *old_conn_state) | |
d240f20f | 2718 | { |
2bd2ad64 | 2719 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
982a3866 | 2720 | enum port port = dp_to_dig_port(intel_dp)->port; |
2bd2ad64 | 2721 | |
49277c31 | 2722 | intel_dp_link_down(intel_dp); |
abfce949 VS |
2723 | |
2724 | /* Only ilk+ has port A */ | |
08aff3fe VS |
2725 | if (port == PORT_A) |
2726 | ironlake_edp_pll_off(intel_dp); | |
49277c31 VS |
2727 | } |
2728 | ||
fd6bbda9 | 2729 | static void vlv_post_disable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
2730 | const struct intel_crtc_state *old_crtc_state, |
2731 | const struct drm_connector_state *old_conn_state) | |
49277c31 VS |
2732 | { |
2733 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2734 | ||
2735 | intel_dp_link_down(intel_dp); | |
2bd2ad64 DV |
2736 | } |
2737 | ||
fd6bbda9 | 2738 | static void chv_post_disable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
2739 | const struct intel_crtc_state *old_crtc_state, |
2740 | const struct drm_connector_state *old_conn_state) | |
a8f327fb VS |
2741 | { |
2742 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
2743 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2744 | struct drm_i915_private *dev_priv = to_i915(dev); |
97fd4d5c | 2745 | |
a8f327fb VS |
2746 | intel_dp_link_down(intel_dp); |
2747 | ||
2748 | mutex_lock(&dev_priv->sb_lock); | |
2749 | ||
2750 | /* Assert data lane reset */ | |
2751 | chv_data_lane_soft_reset(encoder, true); | |
580d3811 | 2752 | |
a580516d | 2753 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
2754 | } |
2755 | ||
7b13b58a VS |
2756 | static void |
2757 | _intel_dp_set_link_train(struct intel_dp *intel_dp, | |
2758 | uint32_t *DP, | |
2759 | uint8_t dp_train_pat) | |
2760 | { | |
2761 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
2762 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 2763 | struct drm_i915_private *dev_priv = to_i915(dev); |
7b13b58a VS |
2764 | enum port port = intel_dig_port->port; |
2765 | ||
8b0878a0 PD |
2766 | if (dp_train_pat & DP_TRAINING_PATTERN_MASK) |
2767 | DRM_DEBUG_KMS("Using DP training pattern TPS%d\n", | |
2768 | dp_train_pat & DP_TRAINING_PATTERN_MASK); | |
2769 | ||
4f8036a2 | 2770 | if (HAS_DDI(dev_priv)) { |
7b13b58a VS |
2771 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
2772 | ||
2773 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) | |
2774 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; | |
2775 | else | |
2776 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; | |
2777 | ||
2778 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
2779 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2780 | case DP_TRAINING_PATTERN_DISABLE: | |
2781 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; | |
2782 | ||
2783 | break; | |
2784 | case DP_TRAINING_PATTERN_1: | |
2785 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2786 | break; | |
2787 | case DP_TRAINING_PATTERN_2: | |
2788 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; | |
2789 | break; | |
2790 | case DP_TRAINING_PATTERN_3: | |
2791 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; | |
2792 | break; | |
2793 | } | |
2794 | I915_WRITE(DP_TP_CTL(port), temp); | |
2795 | ||
5db94019 | 2796 | } else if ((IS_GEN7(dev_priv) && port == PORT_A) || |
6e266956 | 2797 | (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { |
7b13b58a VS |
2798 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2799 | ||
2800 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2801 | case DP_TRAINING_PATTERN_DISABLE: | |
2802 | *DP |= DP_LINK_TRAIN_OFF_CPT; | |
2803 | break; | |
2804 | case DP_TRAINING_PATTERN_1: | |
2805 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; | |
2806 | break; | |
2807 | case DP_TRAINING_PATTERN_2: | |
2808 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; | |
2809 | break; | |
2810 | case DP_TRAINING_PATTERN_3: | |
8b0878a0 | 2811 | DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); |
7b13b58a VS |
2812 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
2813 | break; | |
2814 | } | |
2815 | ||
2816 | } else { | |
920a14b2 | 2817 | if (IS_CHERRYVIEW(dev_priv)) |
7b13b58a VS |
2818 | *DP &= ~DP_LINK_TRAIN_MASK_CHV; |
2819 | else | |
2820 | *DP &= ~DP_LINK_TRAIN_MASK; | |
2821 | ||
2822 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { | |
2823 | case DP_TRAINING_PATTERN_DISABLE: | |
2824 | *DP |= DP_LINK_TRAIN_OFF; | |
2825 | break; | |
2826 | case DP_TRAINING_PATTERN_1: | |
2827 | *DP |= DP_LINK_TRAIN_PAT_1; | |
2828 | break; | |
2829 | case DP_TRAINING_PATTERN_2: | |
2830 | *DP |= DP_LINK_TRAIN_PAT_2; | |
2831 | break; | |
2832 | case DP_TRAINING_PATTERN_3: | |
920a14b2 | 2833 | if (IS_CHERRYVIEW(dev_priv)) { |
7b13b58a VS |
2834 | *DP |= DP_LINK_TRAIN_PAT_3_CHV; |
2835 | } else { | |
8b0878a0 | 2836 | DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); |
7b13b58a VS |
2837 | *DP |= DP_LINK_TRAIN_PAT_2; |
2838 | } | |
2839 | break; | |
2840 | } | |
2841 | } | |
2842 | } | |
2843 | ||
85cb48a1 | 2844 | static void intel_dp_enable_port(struct intel_dp *intel_dp, |
5f88a9c6 | 2845 | const struct intel_crtc_state *old_crtc_state) |
7b13b58a VS |
2846 | { |
2847 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 2848 | struct drm_i915_private *dev_priv = to_i915(dev); |
7b13b58a | 2849 | |
7b13b58a | 2850 | /* enable with pattern 1 (as per spec) */ |
7b13b58a | 2851 | |
8b0878a0 | 2852 | intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1); |
7b713f50 VS |
2853 | |
2854 | /* | |
2855 | * Magic for VLV/CHV. We _must_ first set up the register | |
2856 | * without actually enabling the port, and then do another | |
2857 | * write to enable the port. Otherwise link training will | |
2858 | * fail when the power sequencer is freshly used for this port. | |
2859 | */ | |
2860 | intel_dp->DP |= DP_PORT_EN; | |
85cb48a1 | 2861 | if (old_crtc_state->has_audio) |
6fec7662 | 2862 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
7b713f50 VS |
2863 | |
2864 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
2865 | POSTING_READ(intel_dp->output_reg); | |
580d3811 VS |
2866 | } |
2867 | ||
85cb48a1 | 2868 | static void intel_enable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
2869 | const struct intel_crtc_state *pipe_config, |
2870 | const struct drm_connector_state *conn_state) | |
d240f20f | 2871 | { |
e8cb4558 DV |
2872 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2873 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2874 | struct drm_i915_private *dev_priv = to_i915(dev); |
c1dec79a | 2875 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
e8cb4558 | 2876 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
d6fbdd15 | 2877 | enum pipe pipe = crtc->pipe; |
5d613501 | 2878 | |
0c33d8d7 DV |
2879 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
2880 | return; | |
5d613501 | 2881 | |
093e3f13 VS |
2882 | pps_lock(intel_dp); |
2883 | ||
920a14b2 | 2884 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
093e3f13 VS |
2885 | vlv_init_panel_power_sequencer(intel_dp); |
2886 | ||
85cb48a1 | 2887 | intel_dp_enable_port(intel_dp, pipe_config); |
093e3f13 VS |
2888 | |
2889 | edp_panel_vdd_on(intel_dp); | |
2890 | edp_panel_on(intel_dp); | |
2891 | edp_panel_vdd_off(intel_dp, true); | |
2892 | ||
2893 | pps_unlock(intel_dp); | |
2894 | ||
920a14b2 | 2895 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e0fce78f VS |
2896 | unsigned int lane_mask = 0x0; |
2897 | ||
920a14b2 | 2898 | if (IS_CHERRYVIEW(dev_priv)) |
85cb48a1 | 2899 | lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); |
e0fce78f | 2900 | |
9b6de0a1 VS |
2901 | vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), |
2902 | lane_mask); | |
e0fce78f | 2903 | } |
61234fa5 | 2904 | |
f01eca2e | 2905 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
33a34e4e | 2906 | intel_dp_start_link_train(intel_dp); |
3ab9c637 | 2907 | intel_dp_stop_link_train(intel_dp); |
c1dec79a | 2908 | |
85cb48a1 | 2909 | if (pipe_config->has_audio) { |
c1dec79a | 2910 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
d6fbdd15 | 2911 | pipe_name(pipe)); |
bbf35e9d | 2912 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
c1dec79a | 2913 | } |
ab1f90f9 | 2914 | } |
89b667f8 | 2915 | |
fd6bbda9 | 2916 | static void g4x_enable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
2917 | const struct intel_crtc_state *pipe_config, |
2918 | const struct drm_connector_state *conn_state) | |
ecff4f3b | 2919 | { |
bbf35e9d | 2920 | intel_enable_dp(encoder, pipe_config, conn_state); |
b037d58f | 2921 | intel_edp_backlight_on(pipe_config, conn_state); |
ab1f90f9 | 2922 | } |
89b667f8 | 2923 | |
fd6bbda9 | 2924 | static void vlv_enable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
2925 | const struct intel_crtc_state *pipe_config, |
2926 | const struct drm_connector_state *conn_state) | |
ab1f90f9 | 2927 | { |
828f5c6e JN |
2928 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2929 | ||
b037d58f | 2930 | intel_edp_backlight_on(pipe_config, conn_state); |
d2419ffc | 2931 | intel_psr_enable(intel_dp, pipe_config); |
d240f20f JB |
2932 | } |
2933 | ||
fd6bbda9 | 2934 | static void g4x_pre_enable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
2935 | const struct intel_crtc_state *pipe_config, |
2936 | const struct drm_connector_state *conn_state) | |
ab1f90f9 JN |
2937 | { |
2938 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
d6fbdd15 | 2939 | enum port port = dp_to_dig_port(intel_dp)->port; |
ab1f90f9 | 2940 | |
85cb48a1 | 2941 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 2942 | |
d41f1efb | 2943 | /* Only ilk+ has port A */ |
abfce949 | 2944 | if (port == PORT_A) |
85cb48a1 | 2945 | ironlake_edp_pll_on(intel_dp, pipe_config); |
ab1f90f9 JN |
2946 | } |
2947 | ||
83b84597 VS |
2948 | static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) |
2949 | { | |
2950 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
fac5e23e | 2951 | struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); |
83b84597 | 2952 | enum pipe pipe = intel_dp->pps_pipe; |
44cb734c | 2953 | i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); |
83b84597 | 2954 | |
9f2bdb00 VS |
2955 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE); |
2956 | ||
d158694f VS |
2957 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
2958 | return; | |
2959 | ||
83b84597 VS |
2960 | edp_panel_vdd_off_sync(intel_dp); |
2961 | ||
2962 | /* | |
2963 | * VLV seems to get confused when multiple power seqeuencers | |
2964 | * have the same port selected (even if only one has power/vdd | |
2965 | * enabled). The failure manifests as vlv_wait_port_ready() failing | |
2966 | * CHV on the other hand doesn't seem to mind having the same port | |
2967 | * selected in multiple power seqeuencers, but let's clear the | |
2968 | * port select always when logically disconnecting a power sequencer | |
2969 | * from a port. | |
2970 | */ | |
2971 | DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", | |
2972 | pipe_name(pipe), port_name(intel_dig_port->port)); | |
2973 | I915_WRITE(pp_on_reg, 0); | |
2974 | POSTING_READ(pp_on_reg); | |
2975 | ||
2976 | intel_dp->pps_pipe = INVALID_PIPE; | |
2977 | } | |
2978 | ||
a4a5d2f8 VS |
2979 | static void vlv_steal_power_sequencer(struct drm_device *dev, |
2980 | enum pipe pipe) | |
2981 | { | |
fac5e23e | 2982 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 VS |
2983 | struct intel_encoder *encoder; |
2984 | ||
2985 | lockdep_assert_held(&dev_priv->pps_mutex); | |
2986 | ||
19c8054c | 2987 | for_each_intel_encoder(dev, encoder) { |
a4a5d2f8 | 2988 | struct intel_dp *intel_dp; |
773538e8 | 2989 | enum port port; |
a4a5d2f8 | 2990 | |
9f2bdb00 VS |
2991 | if (encoder->type != INTEL_OUTPUT_DP && |
2992 | encoder->type != INTEL_OUTPUT_EDP) | |
a4a5d2f8 VS |
2993 | continue; |
2994 | ||
2995 | intel_dp = enc_to_intel_dp(&encoder->base); | |
773538e8 | 2996 | port = dp_to_dig_port(intel_dp)->port; |
a4a5d2f8 | 2997 | |
9f2bdb00 VS |
2998 | WARN(intel_dp->active_pipe == pipe, |
2999 | "stealing pipe %c power sequencer from active (e)DP port %c\n", | |
3000 | pipe_name(pipe), port_name(port)); | |
3001 | ||
a4a5d2f8 VS |
3002 | if (intel_dp->pps_pipe != pipe) |
3003 | continue; | |
3004 | ||
3005 | DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", | |
773538e8 | 3006 | pipe_name(pipe), port_name(port)); |
a4a5d2f8 VS |
3007 | |
3008 | /* make sure vdd is off before we steal it */ | |
83b84597 | 3009 | vlv_detach_power_sequencer(intel_dp); |
a4a5d2f8 VS |
3010 | } |
3011 | } | |
3012 | ||
3013 | static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp) | |
3014 | { | |
3015 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3016 | struct intel_encoder *encoder = &intel_dig_port->base; | |
3017 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 3018 | struct drm_i915_private *dev_priv = to_i915(dev); |
a4a5d2f8 | 3019 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
a4a5d2f8 VS |
3020 | |
3021 | lockdep_assert_held(&dev_priv->pps_mutex); | |
3022 | ||
9f2bdb00 | 3023 | WARN_ON(intel_dp->active_pipe != INVALID_PIPE); |
093e3f13 | 3024 | |
9f2bdb00 VS |
3025 | if (intel_dp->pps_pipe != INVALID_PIPE && |
3026 | intel_dp->pps_pipe != crtc->pipe) { | |
3027 | /* | |
3028 | * If another power sequencer was being used on this | |
3029 | * port previously make sure to turn off vdd there while | |
3030 | * we still have control of it. | |
3031 | */ | |
83b84597 | 3032 | vlv_detach_power_sequencer(intel_dp); |
9f2bdb00 | 3033 | } |
a4a5d2f8 VS |
3034 | |
3035 | /* | |
3036 | * We may be stealing the power | |
3037 | * sequencer from another port. | |
3038 | */ | |
3039 | vlv_steal_power_sequencer(dev, crtc->pipe); | |
3040 | ||
9f2bdb00 VS |
3041 | intel_dp->active_pipe = crtc->pipe; |
3042 | ||
1853a9da | 3043 | if (!intel_dp_is_edp(intel_dp)) |
9f2bdb00 VS |
3044 | return; |
3045 | ||
a4a5d2f8 VS |
3046 | /* now it's all ours */ |
3047 | intel_dp->pps_pipe = crtc->pipe; | |
3048 | ||
3049 | DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", | |
3050 | pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port)); | |
3051 | ||
3052 | /* init power sequencer on this pipe and port */ | |
36b5f425 | 3053 | intel_dp_init_panel_power_sequencer(dev, intel_dp); |
5d5ab2d2 | 3054 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true); |
a4a5d2f8 VS |
3055 | } |
3056 | ||
fd6bbda9 | 3057 | static void vlv_pre_enable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
3058 | const struct intel_crtc_state *pipe_config, |
3059 | const struct drm_connector_state *conn_state) | |
a4fc5ed6 | 3060 | { |
5f68c275 | 3061 | vlv_phy_pre_encoder_enable(encoder); |
ab1f90f9 | 3062 | |
bbf35e9d | 3063 | intel_enable_dp(encoder, pipe_config, conn_state); |
89b667f8 JB |
3064 | } |
3065 | ||
fd6bbda9 | 3066 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
3067 | const struct intel_crtc_state *pipe_config, |
3068 | const struct drm_connector_state *conn_state) | |
89b667f8 | 3069 | { |
85cb48a1 | 3070 | intel_dp_prepare(encoder, pipe_config); |
8ac33ed3 | 3071 | |
6da2e616 | 3072 | vlv_phy_pre_pll_enable(encoder); |
a4fc5ed6 KP |
3073 | } |
3074 | ||
fd6bbda9 | 3075 | static void chv_pre_enable_dp(struct intel_encoder *encoder, |
5f88a9c6 VS |
3076 | const struct intel_crtc_state *pipe_config, |
3077 | const struct drm_connector_state *conn_state) | |
e4a1d846 | 3078 | { |
e7d2a717 | 3079 | chv_phy_pre_encoder_enable(encoder); |
e4a1d846 | 3080 | |
bbf35e9d | 3081 | intel_enable_dp(encoder, pipe_config, conn_state); |
b0b33846 VS |
3082 | |
3083 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 3084 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
3085 | } |
3086 | ||
fd6bbda9 | 3087 | static void chv_dp_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
3088 | const struct intel_crtc_state *pipe_config, |
3089 | const struct drm_connector_state *conn_state) | |
9197c88b | 3090 | { |
85cb48a1 | 3091 | intel_dp_prepare(encoder, pipe_config); |
625695f8 | 3092 | |
419b1b7a | 3093 | chv_phy_pre_pll_enable(encoder); |
9197c88b VS |
3094 | } |
3095 | ||
fd6bbda9 | 3096 | static void chv_dp_post_pll_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
3097 | const struct intel_crtc_state *pipe_config, |
3098 | const struct drm_connector_state *conn_state) | |
d6db995f | 3099 | { |
204970b5 | 3100 | chv_phy_post_pll_disable(encoder); |
d6db995f VS |
3101 | } |
3102 | ||
a4fc5ed6 KP |
3103 | /* |
3104 | * Fetch AUX CH registers 0x202 - 0x207 which contain | |
3105 | * link status information | |
3106 | */ | |
94223d04 | 3107 | bool |
93f62dad | 3108 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
a4fc5ed6 | 3109 | { |
9f085ebb L |
3110 | return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, |
3111 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; | |
a4fc5ed6 KP |
3112 | } |
3113 | ||
97da2ef4 NV |
3114 | static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp) |
3115 | { | |
3116 | uint8_t psr_caps = 0; | |
3117 | ||
9bacd4b1 ID |
3118 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1) |
3119 | return false; | |
97da2ef4 NV |
3120 | return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED; |
3121 | } | |
3122 | ||
3123 | static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) | |
3124 | { | |
3125 | uint8_t dprx = 0; | |
3126 | ||
9bacd4b1 ID |
3127 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, |
3128 | &dprx) != 1) | |
3129 | return false; | |
97da2ef4 NV |
3130 | return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; |
3131 | } | |
3132 | ||
a76f73dc | 3133 | static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) |
340c93c0 NV |
3134 | { |
3135 | uint8_t alpm_caps = 0; | |
3136 | ||
9bacd4b1 ID |
3137 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, |
3138 | &alpm_caps) != 1) | |
3139 | return false; | |
340c93c0 NV |
3140 | return alpm_caps & DP_ALPM_CAP; |
3141 | } | |
3142 | ||
1100244e | 3143 | /* These are source-specific values. */ |
94223d04 | 3144 | uint8_t |
1a2eb460 | 3145 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
a4fc5ed6 | 3146 | { |
dd11bc10 | 3147 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
bc7d38a4 | 3148 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 3149 | |
cc3f90f0 | 3150 | if (IS_GEN9_LP(dev_priv)) |
9314726b | 3151 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
dd11bc10 | 3152 | else if (INTEL_GEN(dev_priv) >= 9) { |
ffe5111e VS |
3153 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3154 | return intel_ddi_dp_voltage_max(encoder); | |
920a14b2 | 3155 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
bd60018a | 3156 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
5db94019 | 3157 | else if (IS_GEN7(dev_priv) && port == PORT_A) |
bd60018a | 3158 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
6e266956 | 3159 | else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) |
bd60018a | 3160 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
1a2eb460 | 3161 | else |
bd60018a | 3162 | return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
1a2eb460 KP |
3163 | } |
3164 | ||
94223d04 | 3165 | uint8_t |
1a2eb460 KP |
3166 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
3167 | { | |
8652744b | 3168 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); |
bc7d38a4 | 3169 | enum port port = dp_to_dig_port(intel_dp)->port; |
1a2eb460 | 3170 | |
8652744b | 3171 | if (INTEL_GEN(dev_priv) >= 9) { |
5a9d1f1a DL |
3172 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
3173 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: | |
3174 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3175 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3176 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3177 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3178 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
7ad14a29 SJ |
3179 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
3180 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
5a9d1f1a DL |
3181 | default: |
3182 | return DP_TRAIN_PRE_EMPH_LEVEL_0; | |
3183 | } | |
8652744b | 3184 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
d6c0d722 | 3185 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3186 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3187 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3188 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3189 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3190 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3191 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3192 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
d6c0d722 | 3193 | default: |
bd60018a | 3194 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
d6c0d722 | 3195 | } |
8652744b | 3196 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
e2fa6fba | 3197 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3198 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3199 | return DP_TRAIN_PRE_EMPH_LEVEL_3; | |
3200 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3201 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3202 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3203 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3204 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
e2fa6fba | 3205 | default: |
bd60018a | 3206 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
e2fa6fba | 3207 | } |
8652744b | 3208 | } else if (IS_GEN7(dev_priv) && port == PORT_A) { |
1a2eb460 | 3209 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a SJ |
3210 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3211 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3212 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3213 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3214 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
1a2eb460 | 3215 | default: |
bd60018a | 3216 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 KP |
3217 | } |
3218 | } else { | |
3219 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a SJ |
3220 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
3221 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3222 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: | |
3223 | return DP_TRAIN_PRE_EMPH_LEVEL_2; | |
3224 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: | |
3225 | return DP_TRAIN_PRE_EMPH_LEVEL_1; | |
3226 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: | |
1a2eb460 | 3227 | default: |
bd60018a | 3228 | return DP_TRAIN_PRE_EMPH_LEVEL_0; |
1a2eb460 | 3229 | } |
a4fc5ed6 KP |
3230 | } |
3231 | } | |
3232 | ||
5829975c | 3233 | static uint32_t vlv_signal_levels(struct intel_dp *intel_dp) |
e2fa6fba | 3234 | { |
53d98725 | 3235 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
e2fa6fba P |
3236 | unsigned long demph_reg_value, preemph_reg_value, |
3237 | uniqtranscale_reg_value; | |
3238 | uint8_t train_set = intel_dp->train_set[0]; | |
e2fa6fba P |
3239 | |
3240 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3241 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e2fa6fba P |
3242 | preemph_reg_value = 0x0004000; |
3243 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3244 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3245 | demph_reg_value = 0x2B405555; |
3246 | uniqtranscale_reg_value = 0x552AB83A; | |
3247 | break; | |
bd60018a | 3248 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3249 | demph_reg_value = 0x2B404040; |
3250 | uniqtranscale_reg_value = 0x5548B83A; | |
3251 | break; | |
bd60018a | 3252 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3253 | demph_reg_value = 0x2B245555; |
3254 | uniqtranscale_reg_value = 0x5560B83A; | |
3255 | break; | |
bd60018a | 3256 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e2fa6fba P |
3257 | demph_reg_value = 0x2B405555; |
3258 | uniqtranscale_reg_value = 0x5598DA3A; | |
3259 | break; | |
3260 | default: | |
3261 | return 0; | |
3262 | } | |
3263 | break; | |
bd60018a | 3264 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e2fa6fba P |
3265 | preemph_reg_value = 0x0002000; |
3266 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3267 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3268 | demph_reg_value = 0x2B404040; |
3269 | uniqtranscale_reg_value = 0x5552B83A; | |
3270 | break; | |
bd60018a | 3271 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3272 | demph_reg_value = 0x2B404848; |
3273 | uniqtranscale_reg_value = 0x5580B83A; | |
3274 | break; | |
bd60018a | 3275 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e2fa6fba P |
3276 | demph_reg_value = 0x2B404040; |
3277 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3278 | break; | |
3279 | default: | |
3280 | return 0; | |
3281 | } | |
3282 | break; | |
bd60018a | 3283 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e2fa6fba P |
3284 | preemph_reg_value = 0x0000000; |
3285 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3286 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3287 | demph_reg_value = 0x2B305555; |
3288 | uniqtranscale_reg_value = 0x5570B83A; | |
3289 | break; | |
bd60018a | 3290 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e2fa6fba P |
3291 | demph_reg_value = 0x2B2B4040; |
3292 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3293 | break; | |
3294 | default: | |
3295 | return 0; | |
3296 | } | |
3297 | break; | |
bd60018a | 3298 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e2fa6fba P |
3299 | preemph_reg_value = 0x0006000; |
3300 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { | |
bd60018a | 3301 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e2fa6fba P |
3302 | demph_reg_value = 0x1B405555; |
3303 | uniqtranscale_reg_value = 0x55ADDA3A; | |
3304 | break; | |
3305 | default: | |
3306 | return 0; | |
3307 | } | |
3308 | break; | |
3309 | default: | |
3310 | return 0; | |
3311 | } | |
3312 | ||
53d98725 ACO |
3313 | vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value, |
3314 | uniqtranscale_reg_value, 0); | |
e2fa6fba P |
3315 | |
3316 | return 0; | |
3317 | } | |
3318 | ||
5829975c | 3319 | static uint32_t chv_signal_levels(struct intel_dp *intel_dp) |
e4a1d846 | 3320 | { |
b7fa22d8 ACO |
3321 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; |
3322 | u32 deemph_reg_value, margin_reg_value; | |
3323 | bool uniq_trans_scale = false; | |
e4a1d846 | 3324 | uint8_t train_set = intel_dp->train_set[0]; |
e4a1d846 CML |
3325 | |
3326 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { | |
bd60018a | 3327 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
e4a1d846 | 3328 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3329 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3330 | deemph_reg_value = 128; |
3331 | margin_reg_value = 52; | |
3332 | break; | |
bd60018a | 3333 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3334 | deemph_reg_value = 128; |
3335 | margin_reg_value = 77; | |
3336 | break; | |
bd60018a | 3337 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3338 | deemph_reg_value = 128; |
3339 | margin_reg_value = 102; | |
3340 | break; | |
bd60018a | 3341 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
e4a1d846 CML |
3342 | deemph_reg_value = 128; |
3343 | margin_reg_value = 154; | |
b7fa22d8 | 3344 | uniq_trans_scale = true; |
e4a1d846 CML |
3345 | break; |
3346 | default: | |
3347 | return 0; | |
3348 | } | |
3349 | break; | |
bd60018a | 3350 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
e4a1d846 | 3351 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3352 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3353 | deemph_reg_value = 85; |
3354 | margin_reg_value = 78; | |
3355 | break; | |
bd60018a | 3356 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3357 | deemph_reg_value = 85; |
3358 | margin_reg_value = 116; | |
3359 | break; | |
bd60018a | 3360 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
e4a1d846 CML |
3361 | deemph_reg_value = 85; |
3362 | margin_reg_value = 154; | |
3363 | break; | |
3364 | default: | |
3365 | return 0; | |
3366 | } | |
3367 | break; | |
bd60018a | 3368 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
e4a1d846 | 3369 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3370 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3371 | deemph_reg_value = 64; |
3372 | margin_reg_value = 104; | |
3373 | break; | |
bd60018a | 3374 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
e4a1d846 CML |
3375 | deemph_reg_value = 64; |
3376 | margin_reg_value = 154; | |
3377 | break; | |
3378 | default: | |
3379 | return 0; | |
3380 | } | |
3381 | break; | |
bd60018a | 3382 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
e4a1d846 | 3383 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3384 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
e4a1d846 CML |
3385 | deemph_reg_value = 43; |
3386 | margin_reg_value = 154; | |
3387 | break; | |
3388 | default: | |
3389 | return 0; | |
3390 | } | |
3391 | break; | |
3392 | default: | |
3393 | return 0; | |
3394 | } | |
3395 | ||
b7fa22d8 ACO |
3396 | chv_set_phy_signal_level(encoder, deemph_reg_value, |
3397 | margin_reg_value, uniq_trans_scale); | |
e4a1d846 CML |
3398 | |
3399 | return 0; | |
3400 | } | |
3401 | ||
a4fc5ed6 | 3402 | static uint32_t |
5829975c | 3403 | gen4_signal_levels(uint8_t train_set) |
a4fc5ed6 | 3404 | { |
3cf2efb1 | 3405 | uint32_t signal_levels = 0; |
a4fc5ed6 | 3406 | |
3cf2efb1 | 3407 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
bd60018a | 3408 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: |
a4fc5ed6 KP |
3409 | default: |
3410 | signal_levels |= DP_VOLTAGE_0_4; | |
3411 | break; | |
bd60018a | 3412 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: |
a4fc5ed6 KP |
3413 | signal_levels |= DP_VOLTAGE_0_6; |
3414 | break; | |
bd60018a | 3415 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: |
a4fc5ed6 KP |
3416 | signal_levels |= DP_VOLTAGE_0_8; |
3417 | break; | |
bd60018a | 3418 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: |
a4fc5ed6 KP |
3419 | signal_levels |= DP_VOLTAGE_1_2; |
3420 | break; | |
3421 | } | |
3cf2efb1 | 3422 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
bd60018a | 3423 | case DP_TRAIN_PRE_EMPH_LEVEL_0: |
a4fc5ed6 KP |
3424 | default: |
3425 | signal_levels |= DP_PRE_EMPHASIS_0; | |
3426 | break; | |
bd60018a | 3427 | case DP_TRAIN_PRE_EMPH_LEVEL_1: |
a4fc5ed6 KP |
3428 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
3429 | break; | |
bd60018a | 3430 | case DP_TRAIN_PRE_EMPH_LEVEL_2: |
a4fc5ed6 KP |
3431 | signal_levels |= DP_PRE_EMPHASIS_6; |
3432 | break; | |
bd60018a | 3433 | case DP_TRAIN_PRE_EMPH_LEVEL_3: |
a4fc5ed6 KP |
3434 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
3435 | break; | |
3436 | } | |
3437 | return signal_levels; | |
3438 | } | |
3439 | ||
e3421a18 ZW |
3440 | /* Gen6's DP voltage swing and pre-emphasis control */ |
3441 | static uint32_t | |
5829975c | 3442 | gen6_edp_signal_levels(uint8_t train_set) |
e3421a18 | 3443 | { |
3c5a62b5 YL |
3444 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
3445 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3446 | switch (signal_levels) { | |
bd60018a SJ |
3447 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3448 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3449 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
bd60018a | 3450 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3c5a62b5 | 3451 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
bd60018a SJ |
3452 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
3453 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: | |
3c5a62b5 | 3454 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
bd60018a SJ |
3455 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
3456 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: | |
3c5a62b5 | 3457 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
bd60018a SJ |
3458 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
3459 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: | |
3c5a62b5 | 3460 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
e3421a18 | 3461 | default: |
3c5a62b5 YL |
3462 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
3463 | "0x%x\n", signal_levels); | |
3464 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; | |
e3421a18 ZW |
3465 | } |
3466 | } | |
3467 | ||
1a2eb460 KP |
3468 | /* Gen7's DP voltage swing and pre-emphasis control */ |
3469 | static uint32_t | |
5829975c | 3470 | gen7_edp_signal_levels(uint8_t train_set) |
1a2eb460 KP |
3471 | { |
3472 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | | |
3473 | DP_TRAIN_PRE_EMPHASIS_MASK); | |
3474 | switch (signal_levels) { | |
bd60018a | 3475 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3476 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
bd60018a | 3477 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 | 3478 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
bd60018a | 3479 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: |
1a2eb460 KP |
3480 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
3481 | ||
bd60018a | 3482 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3483 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
bd60018a | 3484 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3485 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
3486 | ||
bd60018a | 3487 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: |
1a2eb460 | 3488 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
bd60018a | 3489 | case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: |
1a2eb460 KP |
3490 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
3491 | ||
3492 | default: | |
3493 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" | |
3494 | "0x%x\n", signal_levels); | |
3495 | return EDP_LINK_TRAIN_500MV_0DB_IVB; | |
3496 | } | |
3497 | } | |
3498 | ||
94223d04 | 3499 | void |
f4eb692e | 3500 | intel_dp_set_signal_levels(struct intel_dp *intel_dp) |
f0a3424e PZ |
3501 | { |
3502 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
bc7d38a4 | 3503 | enum port port = intel_dig_port->port; |
f0a3424e | 3504 | struct drm_device *dev = intel_dig_port->base.base.dev; |
b905a915 | 3505 | struct drm_i915_private *dev_priv = to_i915(dev); |
f8896f5d | 3506 | uint32_t signal_levels, mask = 0; |
f0a3424e PZ |
3507 | uint8_t train_set = intel_dp->train_set[0]; |
3508 | ||
4f8036a2 | 3509 | if (HAS_DDI(dev_priv)) { |
f8896f5d DW |
3510 | signal_levels = ddi_signal_levels(intel_dp); |
3511 | ||
cf54ca8b | 3512 | if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) |
f8896f5d DW |
3513 | signal_levels = 0; |
3514 | else | |
3515 | mask = DDI_BUF_EMP_MASK; | |
920a14b2 | 3516 | } else if (IS_CHERRYVIEW(dev_priv)) { |
5829975c | 3517 | signal_levels = chv_signal_levels(intel_dp); |
11a914c2 | 3518 | } else if (IS_VALLEYVIEW(dev_priv)) { |
5829975c | 3519 | signal_levels = vlv_signal_levels(intel_dp); |
5db94019 | 3520 | } else if (IS_GEN7(dev_priv) && port == PORT_A) { |
5829975c | 3521 | signal_levels = gen7_edp_signal_levels(train_set); |
f0a3424e | 3522 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
5db94019 | 3523 | } else if (IS_GEN6(dev_priv) && port == PORT_A) { |
5829975c | 3524 | signal_levels = gen6_edp_signal_levels(train_set); |
f0a3424e PZ |
3525 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
3526 | } else { | |
5829975c | 3527 | signal_levels = gen4_signal_levels(train_set); |
f0a3424e PZ |
3528 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
3529 | } | |
3530 | ||
96fb9f9b VK |
3531 | if (mask) |
3532 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); | |
3533 | ||
3534 | DRM_DEBUG_KMS("Using vswing level %d\n", | |
3535 | train_set & DP_TRAIN_VOLTAGE_SWING_MASK); | |
3536 | DRM_DEBUG_KMS("Using pre-emphasis level %d\n", | |
3537 | (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> | |
3538 | DP_TRAIN_PRE_EMPHASIS_SHIFT); | |
f0a3424e | 3539 | |
f4eb692e | 3540 | intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; |
b905a915 ACO |
3541 | |
3542 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); | |
3543 | POSTING_READ(intel_dp->output_reg); | |
f0a3424e PZ |
3544 | } |
3545 | ||
94223d04 | 3546 | void |
e9c176d5 ACO |
3547 | intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, |
3548 | uint8_t dp_train_pat) | |
a4fc5ed6 | 3549 | { |
174edf1f | 3550 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
90a6b7b0 VS |
3551 | struct drm_i915_private *dev_priv = |
3552 | to_i915(intel_dig_port->base.base.dev); | |
a4fc5ed6 | 3553 | |
f4eb692e | 3554 | _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); |
47ea7542 | 3555 | |
f4eb692e | 3556 | I915_WRITE(intel_dp->output_reg, intel_dp->DP); |
ea5b213a | 3557 | POSTING_READ(intel_dp->output_reg); |
e9c176d5 ACO |
3558 | } |
3559 | ||
94223d04 | 3560 | void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
3ab9c637 ID |
3561 | { |
3562 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
3563 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 3564 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ab9c637 ID |
3565 | enum port port = intel_dig_port->port; |
3566 | uint32_t val; | |
3567 | ||
4f8036a2 | 3568 | if (!HAS_DDI(dev_priv)) |
3ab9c637 ID |
3569 | return; |
3570 | ||
3571 | val = I915_READ(DP_TP_CTL(port)); | |
3572 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; | |
3573 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; | |
3574 | I915_WRITE(DP_TP_CTL(port), val); | |
3575 | ||
3576 | /* | |
3577 | * On PORT_A we can have only eDP in SST mode. There the only reason | |
3578 | * we need to set idle transmission mode is to work around a HW issue | |
3579 | * where we enable the pipe while not in idle link-training mode. | |
3580 | * In this case there is requirement to wait for a minimum number of | |
3581 | * idle patterns to be sent. | |
3582 | */ | |
3583 | if (port == PORT_A) | |
3584 | return; | |
3585 | ||
a767017f CW |
3586 | if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port), |
3587 | DP_TP_STATUS_IDLE_DONE, | |
3588 | DP_TP_STATUS_IDLE_DONE, | |
3589 | 1)) | |
3ab9c637 ID |
3590 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
3591 | } | |
3592 | ||
a4fc5ed6 | 3593 | static void |
ea5b213a | 3594 | intel_dp_link_down(struct intel_dp *intel_dp) |
a4fc5ed6 | 3595 | { |
da63a9f2 | 3596 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1612c8bd | 3597 | struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); |
bc7d38a4 | 3598 | enum port port = intel_dig_port->port; |
da63a9f2 | 3599 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 3600 | struct drm_i915_private *dev_priv = to_i915(dev); |
ea5b213a | 3601 | uint32_t DP = intel_dp->DP; |
a4fc5ed6 | 3602 | |
4f8036a2 | 3603 | if (WARN_ON(HAS_DDI(dev_priv))) |
c19b0669 PZ |
3604 | return; |
3605 | ||
0c33d8d7 | 3606 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
1b39d6f3 CW |
3607 | return; |
3608 | ||
28c97730 | 3609 | DRM_DEBUG_KMS("\n"); |
32f9d658 | 3610 | |
5db94019 | 3611 | if ((IS_GEN7(dev_priv) && port == PORT_A) || |
6e266956 | 3612 | (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { |
e3421a18 | 3613 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
1612c8bd | 3614 | DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; |
e3421a18 | 3615 | } else { |
920a14b2 | 3616 | if (IS_CHERRYVIEW(dev_priv)) |
aad3d14d VS |
3617 | DP &= ~DP_LINK_TRAIN_MASK_CHV; |
3618 | else | |
3619 | DP &= ~DP_LINK_TRAIN_MASK; | |
1612c8bd | 3620 | DP |= DP_LINK_TRAIN_PAT_IDLE; |
e3421a18 | 3621 | } |
1612c8bd | 3622 | I915_WRITE(intel_dp->output_reg, DP); |
fe255d00 | 3623 | POSTING_READ(intel_dp->output_reg); |
5eb08b69 | 3624 | |
1612c8bd VS |
3625 | DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
3626 | I915_WRITE(intel_dp->output_reg, DP); | |
3627 | POSTING_READ(intel_dp->output_reg); | |
3628 | ||
3629 | /* | |
3630 | * HW workaround for IBX, we need to move the port | |
3631 | * to transcoder A after disabling it to allow the | |
3632 | * matching HDMI port to be enabled on transcoder A. | |
3633 | */ | |
6e266956 | 3634 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { |
0c241d5b VS |
3635 | /* |
3636 | * We get CPU/PCH FIFO underruns on the other pipe when | |
3637 | * doing the workaround. Sweep them under the rug. | |
3638 | */ | |
3639 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3640 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
3641 | ||
1612c8bd VS |
3642 | /* always enable with pattern 1 (as per spec) */ |
3643 | DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); | |
3644 | DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1; | |
3645 | I915_WRITE(intel_dp->output_reg, DP); | |
3646 | POSTING_READ(intel_dp->output_reg); | |
3647 | ||
3648 | DP &= ~DP_PORT_EN; | |
5bddd17f | 3649 | I915_WRITE(intel_dp->output_reg, DP); |
0ca09685 | 3650 | POSTING_READ(intel_dp->output_reg); |
0c241d5b | 3651 | |
0f0f74bc | 3652 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
3653 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
3654 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
5bddd17f EA |
3655 | } |
3656 | ||
f01eca2e | 3657 | msleep(intel_dp->panel_power_down_delay); |
6fec7662 VS |
3658 | |
3659 | intel_dp->DP = DP; | |
9f2bdb00 VS |
3660 | |
3661 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
3662 | pps_lock(intel_dp); | |
3663 | intel_dp->active_pipe = INVALID_PIPE; | |
3664 | pps_unlock(intel_dp); | |
3665 | } | |
a4fc5ed6 KP |
3666 | } |
3667 | ||
24e807e7 | 3668 | bool |
fe5a66f9 | 3669 | intel_dp_read_dpcd(struct intel_dp *intel_dp) |
92fd8fd1 | 3670 | { |
9f085ebb L |
3671 | if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, |
3672 | sizeof(intel_dp->dpcd)) < 0) | |
edb39244 | 3673 | return false; /* aux transfer failed */ |
92fd8fd1 | 3674 | |
a8e98153 | 3675 | DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); |
577c7a50 | 3676 | |
fe5a66f9 VS |
3677 | return intel_dp->dpcd[DP_DPCD_REV] != 0; |
3678 | } | |
edb39244 | 3679 | |
fe5a66f9 VS |
3680 | static bool |
3681 | intel_edp_init_dpcd(struct intel_dp *intel_dp) | |
3682 | { | |
3683 | struct drm_i915_private *dev_priv = | |
3684 | to_i915(dp_to_dig_port(intel_dp)->base.base.dev); | |
30d9aa42 | 3685 | |
fe5a66f9 VS |
3686 | /* this function is meant to be called only once */ |
3687 | WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0); | |
30d9aa42 | 3688 | |
fe5a66f9 | 3689 | if (!intel_dp_read_dpcd(intel_dp)) |
30d9aa42 SS |
3690 | return false; |
3691 | ||
84c36753 JN |
3692 | drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, |
3693 | drm_dp_is_branch(intel_dp->dpcd)); | |
12a47a42 | 3694 | |
fe5a66f9 VS |
3695 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
3696 | dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] & | |
3697 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; | |
474d1ec4 | 3698 | |
fe5a66f9 VS |
3699 | /* Check if the panel supports PSR */ |
3700 | drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, | |
3701 | intel_dp->psr_dpcd, | |
3702 | sizeof(intel_dp->psr_dpcd)); | |
3703 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { | |
3704 | dev_priv->psr.sink_support = true; | |
3705 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); | |
3706 | } | |
86ee27b5 | 3707 | |
fe5a66f9 VS |
3708 | if (INTEL_GEN(dev_priv) >= 9 && |
3709 | (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) { | |
3710 | uint8_t frame_sync_cap; | |
3711 | ||
3712 | dev_priv->psr.sink_support = true; | |
9bacd4b1 ID |
3713 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
3714 | DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP, | |
3715 | &frame_sync_cap) != 1) | |
3716 | frame_sync_cap = 0; | |
fe5a66f9 VS |
3717 | dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; |
3718 | /* PSR2 needs frame sync as well */ | |
3719 | dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; | |
3720 | DRM_DEBUG_KMS("PSR2 %s on sink", | |
3721 | dev_priv->psr.psr2_support ? "supported" : "not supported"); | |
97da2ef4 NV |
3722 | |
3723 | if (dev_priv->psr.psr2_support) { | |
3724 | dev_priv->psr.y_cord_support = | |
3725 | intel_dp_get_y_cord_status(intel_dp); | |
3726 | dev_priv->psr.colorimetry_support = | |
3727 | intel_dp_get_colorimetry_status(intel_dp); | |
340c93c0 NV |
3728 | dev_priv->psr.alpm = |
3729 | intel_dp_get_alpm_status(intel_dp); | |
97da2ef4 NV |
3730 | } |
3731 | ||
50003939 JN |
3732 | } |
3733 | ||
fe5a66f9 VS |
3734 | /* Read the eDP Display control capabilities registers */ |
3735 | if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && | |
3736 | drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, | |
f7170e2e DC |
3737 | intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == |
3738 | sizeof(intel_dp->edp_dpcd)) | |
fe5a66f9 VS |
3739 | DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd), |
3740 | intel_dp->edp_dpcd); | |
06ea66b6 | 3741 | |
fc0f8e25 | 3742 | /* Intermediate frequency support */ |
fe5a66f9 | 3743 | if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */ |
94ca719e | 3744 | __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; |
ea2d8a42 VS |
3745 | int i; |
3746 | ||
9f085ebb L |
3747 | drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, |
3748 | sink_rates, sizeof(sink_rates)); | |
ea2d8a42 | 3749 | |
94ca719e VS |
3750 | for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { |
3751 | int val = le16_to_cpu(sink_rates[i]); | |
ea2d8a42 VS |
3752 | |
3753 | if (val == 0) | |
3754 | break; | |
3755 | ||
fd81c44e DP |
3756 | /* Value read multiplied by 200kHz gives the per-lane |
3757 | * link rate in kHz. The source rates are, however, | |
3758 | * stored in terms of LS_Clk kHz. The full conversion | |
3759 | * back to symbols is | |
3760 | * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) | |
3761 | */ | |
af77b974 | 3762 | intel_dp->sink_rates[i] = (val * 200) / 10; |
ea2d8a42 | 3763 | } |
94ca719e | 3764 | intel_dp->num_sink_rates = i; |
fc0f8e25 | 3765 | } |
0336400e | 3766 | |
68f357cb JN |
3767 | if (intel_dp->num_sink_rates) |
3768 | intel_dp->use_rate_select = true; | |
3769 | else | |
3770 | intel_dp_set_sink_rates(intel_dp); | |
3771 | ||
975ee5fc JN |
3772 | intel_dp_set_common_rates(intel_dp); |
3773 | ||
fe5a66f9 VS |
3774 | return true; |
3775 | } | |
3776 | ||
3777 | ||
3778 | static bool | |
3779 | intel_dp_get_dpcd(struct intel_dp *intel_dp) | |
3780 | { | |
27dbefb9 JN |
3781 | u8 sink_count; |
3782 | ||
fe5a66f9 VS |
3783 | if (!intel_dp_read_dpcd(intel_dp)) |
3784 | return false; | |
3785 | ||
68f357cb | 3786 | /* Don't clobber cached eDP rates. */ |
1853a9da | 3787 | if (!intel_dp_is_edp(intel_dp)) { |
68f357cb | 3788 | intel_dp_set_sink_rates(intel_dp); |
975ee5fc JN |
3789 | intel_dp_set_common_rates(intel_dp); |
3790 | } | |
68f357cb | 3791 | |
27dbefb9 | 3792 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0) |
fe5a66f9 VS |
3793 | return false; |
3794 | ||
3795 | /* | |
3796 | * Sink count can change between short pulse hpd hence | |
3797 | * a member variable in intel_dp will track any changes | |
3798 | * between short pulse interrupts. | |
3799 | */ | |
27dbefb9 | 3800 | intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count); |
fe5a66f9 VS |
3801 | |
3802 | /* | |
3803 | * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that | |
3804 | * a dongle is present but no display. Unless we require to know | |
3805 | * if a dongle is present or not, we don't need to update | |
3806 | * downstream port information. So, an early return here saves | |
3807 | * time from performing other operations which are not required. | |
3808 | */ | |
1853a9da | 3809 | if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count) |
fe5a66f9 | 3810 | return false; |
0336400e | 3811 | |
c726ad01 | 3812 | if (!drm_dp_is_branch(intel_dp->dpcd)) |
edb39244 AJ |
3813 | return true; /* native DP sink */ |
3814 | ||
3815 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) | |
3816 | return true; /* no per-port downstream info */ | |
3817 | ||
9f085ebb L |
3818 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
3819 | intel_dp->downstream_ports, | |
3820 | DP_MAX_DOWNSTREAM_PORTS) < 0) | |
edb39244 AJ |
3821 | return false; /* downstream port status fetch failed */ |
3822 | ||
3823 | return true; | |
92fd8fd1 KP |
3824 | } |
3825 | ||
0e32b39c | 3826 | static bool |
c4e3170a | 3827 | intel_dp_can_mst(struct intel_dp *intel_dp) |
0e32b39c | 3828 | { |
010b9b39 | 3829 | u8 mstm_cap; |
0e32b39c | 3830 | |
7cc96139 NS |
3831 | if (!i915.enable_dp_mst) |
3832 | return false; | |
3833 | ||
0e32b39c DA |
3834 | if (!intel_dp->can_mst) |
3835 | return false; | |
3836 | ||
3837 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) | |
3838 | return false; | |
3839 | ||
010b9b39 | 3840 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1) |
c4e3170a | 3841 | return false; |
0e32b39c | 3842 | |
010b9b39 | 3843 | return mstm_cap & DP_MST_CAP; |
c4e3170a VS |
3844 | } |
3845 | ||
3846 | static void | |
3847 | intel_dp_configure_mst(struct intel_dp *intel_dp) | |
3848 | { | |
3849 | if (!i915.enable_dp_mst) | |
3850 | return; | |
3851 | ||
3852 | if (!intel_dp->can_mst) | |
3853 | return; | |
3854 | ||
3855 | intel_dp->is_mst = intel_dp_can_mst(intel_dp); | |
3856 | ||
3857 | if (intel_dp->is_mst) | |
3858 | DRM_DEBUG_KMS("Sink is MST capable\n"); | |
3859 | else | |
3860 | DRM_DEBUG_KMS("Sink is not MST capable\n"); | |
3861 | ||
3862 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
3863 | intel_dp->is_mst); | |
0e32b39c DA |
3864 | } |
3865 | ||
e5a1cab5 | 3866 | static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp) |
d2e216d0 | 3867 | { |
082dcc7c | 3868 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
0f0f74bc | 3869 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
082dcc7c | 3870 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
ad9dc91b | 3871 | u8 buf; |
e5a1cab5 | 3872 | int ret = 0; |
c6297843 RV |
3873 | int count = 0; |
3874 | int attempts = 10; | |
d2e216d0 | 3875 | |
082dcc7c RV |
3876 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) { |
3877 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); | |
e5a1cab5 RV |
3878 | ret = -EIO; |
3879 | goto out; | |
4373f0f2 PZ |
3880 | } |
3881 | ||
082dcc7c | 3882 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
e5a1cab5 | 3883 | buf & ~DP_TEST_SINK_START) < 0) { |
082dcc7c | 3884 | DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n"); |
e5a1cab5 RV |
3885 | ret = -EIO; |
3886 | goto out; | |
3887 | } | |
d2e216d0 | 3888 | |
c6297843 | 3889 | do { |
0f0f74bc | 3890 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
c6297843 RV |
3891 | |
3892 | if (drm_dp_dpcd_readb(&intel_dp->aux, | |
3893 | DP_TEST_SINK_MISC, &buf) < 0) { | |
3894 | ret = -EIO; | |
3895 | goto out; | |
3896 | } | |
3897 | count = buf & DP_TEST_COUNT_MASK; | |
3898 | } while (--attempts && count); | |
3899 | ||
3900 | if (attempts == 0) { | |
dc5a9037 | 3901 | DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n"); |
c6297843 RV |
3902 | ret = -ETIMEDOUT; |
3903 | } | |
3904 | ||
e5a1cab5 | 3905 | out: |
082dcc7c | 3906 | hsw_enable_ips(intel_crtc); |
e5a1cab5 | 3907 | return ret; |
082dcc7c RV |
3908 | } |
3909 | ||
3910 | static int intel_dp_sink_crc_start(struct intel_dp *intel_dp) | |
3911 | { | |
3912 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
0f0f74bc | 3913 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
082dcc7c RV |
3914 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
3915 | u8 buf; | |
e5a1cab5 RV |
3916 | int ret; |
3917 | ||
082dcc7c RV |
3918 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) |
3919 | return -EIO; | |
3920 | ||
3921 | if (!(buf & DP_TEST_CRC_SUPPORTED)) | |
3922 | return -ENOTTY; | |
3923 | ||
3924 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) | |
3925 | return -EIO; | |
3926 | ||
6d8175da RV |
3927 | if (buf & DP_TEST_SINK_START) { |
3928 | ret = intel_dp_sink_crc_stop(intel_dp); | |
3929 | if (ret) | |
3930 | return ret; | |
3931 | } | |
3932 | ||
082dcc7c | 3933 | hsw_disable_ips(intel_crtc); |
1dda5f93 | 3934 | |
9d1a1031 | 3935 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
082dcc7c RV |
3936 | buf | DP_TEST_SINK_START) < 0) { |
3937 | hsw_enable_ips(intel_crtc); | |
3938 | return -EIO; | |
4373f0f2 PZ |
3939 | } |
3940 | ||
0f0f74bc | 3941 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
082dcc7c RV |
3942 | return 0; |
3943 | } | |
3944 | ||
3945 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) | |
3946 | { | |
3947 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); | |
0f0f74bc | 3948 | struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); |
082dcc7c RV |
3949 | struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); |
3950 | u8 buf; | |
621d4c76 | 3951 | int count, ret; |
082dcc7c | 3952 | int attempts = 6; |
082dcc7c RV |
3953 | |
3954 | ret = intel_dp_sink_crc_start(intel_dp); | |
3955 | if (ret) | |
3956 | return ret; | |
3957 | ||
ad9dc91b | 3958 | do { |
0f0f74bc | 3959 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
621d4c76 | 3960 | |
1dda5f93 | 3961 | if (drm_dp_dpcd_readb(&intel_dp->aux, |
4373f0f2 PZ |
3962 | DP_TEST_SINK_MISC, &buf) < 0) { |
3963 | ret = -EIO; | |
afe0d67e | 3964 | goto stop; |
4373f0f2 | 3965 | } |
621d4c76 | 3966 | count = buf & DP_TEST_COUNT_MASK; |
aabc95dc | 3967 | |
7e38eeff | 3968 | } while (--attempts && count == 0); |
ad9dc91b RV |
3969 | |
3970 | if (attempts == 0) { | |
7e38eeff RV |
3971 | DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n"); |
3972 | ret = -ETIMEDOUT; | |
3973 | goto stop; | |
3974 | } | |
3975 | ||
3976 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) { | |
3977 | ret = -EIO; | |
3978 | goto stop; | |
ad9dc91b | 3979 | } |
d2e216d0 | 3980 | |
afe0d67e | 3981 | stop: |
082dcc7c | 3982 | intel_dp_sink_crc_stop(intel_dp); |
4373f0f2 | 3983 | return ret; |
d2e216d0 RV |
3984 | } |
3985 | ||
a60f0e38 JB |
3986 | static bool |
3987 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3988 | { | |
010b9b39 JN |
3989 | return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, |
3990 | sink_irq_vector) == 1; | |
a60f0e38 JB |
3991 | } |
3992 | ||
0e32b39c DA |
3993 | static bool |
3994 | intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) | |
3995 | { | |
3996 | int ret; | |
3997 | ||
9f085ebb | 3998 | ret = drm_dp_dpcd_read(&intel_dp->aux, |
0e32b39c DA |
3999 | DP_SINK_COUNT_ESI, |
4000 | sink_irq_vector, 14); | |
4001 | if (ret != 14) | |
4002 | return false; | |
4003 | ||
4004 | return true; | |
4005 | } | |
4006 | ||
c5d5ab7a TP |
4007 | static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp) |
4008 | { | |
da15f7cb | 4009 | int status = 0; |
140ef138 | 4010 | int test_link_rate; |
da15f7cb MN |
4011 | uint8_t test_lane_count, test_link_bw; |
4012 | /* (DP CTS 1.2) | |
4013 | * 4.3.1.11 | |
4014 | */ | |
4015 | /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */ | |
4016 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT, | |
4017 | &test_lane_count); | |
4018 | ||
4019 | if (status <= 0) { | |
4020 | DRM_DEBUG_KMS("Lane count read failed\n"); | |
4021 | return DP_TEST_NAK; | |
4022 | } | |
4023 | test_lane_count &= DP_MAX_LANE_COUNT_MASK; | |
da15f7cb MN |
4024 | |
4025 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, | |
4026 | &test_link_bw); | |
4027 | if (status <= 0) { | |
4028 | DRM_DEBUG_KMS("Link Rate read failed\n"); | |
4029 | return DP_TEST_NAK; | |
4030 | } | |
da15f7cb | 4031 | test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); |
140ef138 MN |
4032 | |
4033 | /* Validate the requested link rate and lane count */ | |
4034 | if (!intel_dp_link_params_valid(intel_dp, test_link_rate, | |
4035 | test_lane_count)) | |
da15f7cb MN |
4036 | return DP_TEST_NAK; |
4037 | ||
4038 | intel_dp->compliance.test_lane_count = test_lane_count; | |
4039 | intel_dp->compliance.test_link_rate = test_link_rate; | |
4040 | ||
4041 | return DP_TEST_ACK; | |
c5d5ab7a TP |
4042 | } |
4043 | ||
4044 | static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) | |
4045 | { | |
611032bf | 4046 | uint8_t test_pattern; |
010b9b39 | 4047 | uint8_t test_misc; |
611032bf MN |
4048 | __be16 h_width, v_height; |
4049 | int status = 0; | |
4050 | ||
4051 | /* Read the TEST_PATTERN (DP CTS 3.1.5) */ | |
010b9b39 JN |
4052 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN, |
4053 | &test_pattern); | |
611032bf MN |
4054 | if (status <= 0) { |
4055 | DRM_DEBUG_KMS("Test pattern read failed\n"); | |
4056 | return DP_TEST_NAK; | |
4057 | } | |
4058 | if (test_pattern != DP_COLOR_RAMP) | |
4059 | return DP_TEST_NAK; | |
4060 | ||
4061 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI, | |
4062 | &h_width, 2); | |
4063 | if (status <= 0) { | |
4064 | DRM_DEBUG_KMS("H Width read failed\n"); | |
4065 | return DP_TEST_NAK; | |
4066 | } | |
4067 | ||
4068 | status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI, | |
4069 | &v_height, 2); | |
4070 | if (status <= 0) { | |
4071 | DRM_DEBUG_KMS("V Height read failed\n"); | |
4072 | return DP_TEST_NAK; | |
4073 | } | |
4074 | ||
010b9b39 JN |
4075 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0, |
4076 | &test_misc); | |
611032bf MN |
4077 | if (status <= 0) { |
4078 | DRM_DEBUG_KMS("TEST MISC read failed\n"); | |
4079 | return DP_TEST_NAK; | |
4080 | } | |
4081 | if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB) | |
4082 | return DP_TEST_NAK; | |
4083 | if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA) | |
4084 | return DP_TEST_NAK; | |
4085 | switch (test_misc & DP_TEST_BIT_DEPTH_MASK) { | |
4086 | case DP_TEST_BIT_DEPTH_6: | |
4087 | intel_dp->compliance.test_data.bpc = 6; | |
4088 | break; | |
4089 | case DP_TEST_BIT_DEPTH_8: | |
4090 | intel_dp->compliance.test_data.bpc = 8; | |
4091 | break; | |
4092 | default: | |
4093 | return DP_TEST_NAK; | |
4094 | } | |
4095 | ||
4096 | intel_dp->compliance.test_data.video_pattern = test_pattern; | |
4097 | intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width); | |
4098 | intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height); | |
4099 | /* Set test active flag here so userspace doesn't interrupt things */ | |
4100 | intel_dp->compliance.test_active = 1; | |
4101 | ||
4102 | return DP_TEST_ACK; | |
c5d5ab7a TP |
4103 | } |
4104 | ||
4105 | static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp) | |
a60f0e38 | 4106 | { |
b48a5ba9 | 4107 | uint8_t test_result = DP_TEST_ACK; |
559be30c TP |
4108 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
4109 | struct drm_connector *connector = &intel_connector->base; | |
4110 | ||
4111 | if (intel_connector->detect_edid == NULL || | |
ac6f2e29 | 4112 | connector->edid_corrupt || |
559be30c TP |
4113 | intel_dp->aux.i2c_defer_count > 6) { |
4114 | /* Check EDID read for NACKs, DEFERs and corruption | |
4115 | * (DP CTS 1.2 Core r1.1) | |
4116 | * 4.2.2.4 : Failed EDID read, I2C_NAK | |
4117 | * 4.2.2.5 : Failed EDID read, I2C_DEFER | |
4118 | * 4.2.2.6 : EDID corruption detected | |
4119 | * Use failsafe mode for all cases | |
4120 | */ | |
4121 | if (intel_dp->aux.i2c_nack_count > 0 || | |
4122 | intel_dp->aux.i2c_defer_count > 0) | |
4123 | DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", | |
4124 | intel_dp->aux.i2c_nack_count, | |
4125 | intel_dp->aux.i2c_defer_count); | |
c1617abc | 4126 | intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE; |
559be30c | 4127 | } else { |
f79b468e TS |
4128 | struct edid *block = intel_connector->detect_edid; |
4129 | ||
4130 | /* We have to write the checksum | |
4131 | * of the last block read | |
4132 | */ | |
4133 | block += intel_connector->detect_edid->extensions; | |
4134 | ||
010b9b39 JN |
4135 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM, |
4136 | block->checksum) <= 0) | |
559be30c TP |
4137 | DRM_DEBUG_KMS("Failed to write EDID checksum\n"); |
4138 | ||
4139 | test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; | |
b48a5ba9 | 4140 | intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED; |
559be30c TP |
4141 | } |
4142 | ||
4143 | /* Set test active flag here so userspace doesn't interrupt things */ | |
c1617abc | 4144 | intel_dp->compliance.test_active = 1; |
559be30c | 4145 | |
c5d5ab7a TP |
4146 | return test_result; |
4147 | } | |
4148 | ||
4149 | static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) | |
a60f0e38 | 4150 | { |
c5d5ab7a TP |
4151 | uint8_t test_result = DP_TEST_NAK; |
4152 | return test_result; | |
4153 | } | |
4154 | ||
4155 | static void intel_dp_handle_test_request(struct intel_dp *intel_dp) | |
4156 | { | |
4157 | uint8_t response = DP_TEST_NAK; | |
5ec63bbd JN |
4158 | uint8_t request = 0; |
4159 | int status; | |
c5d5ab7a | 4160 | |
5ec63bbd | 4161 | status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request); |
c5d5ab7a TP |
4162 | if (status <= 0) { |
4163 | DRM_DEBUG_KMS("Could not read test request from sink\n"); | |
4164 | goto update_status; | |
4165 | } | |
4166 | ||
5ec63bbd | 4167 | switch (request) { |
c5d5ab7a TP |
4168 | case DP_TEST_LINK_TRAINING: |
4169 | DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); | |
c5d5ab7a TP |
4170 | response = intel_dp_autotest_link_training(intel_dp); |
4171 | break; | |
4172 | case DP_TEST_LINK_VIDEO_PATTERN: | |
4173 | DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); | |
c5d5ab7a TP |
4174 | response = intel_dp_autotest_video_pattern(intel_dp); |
4175 | break; | |
4176 | case DP_TEST_LINK_EDID_READ: | |
4177 | DRM_DEBUG_KMS("EDID test requested\n"); | |
c5d5ab7a TP |
4178 | response = intel_dp_autotest_edid(intel_dp); |
4179 | break; | |
4180 | case DP_TEST_LINK_PHY_TEST_PATTERN: | |
4181 | DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); | |
c5d5ab7a TP |
4182 | response = intel_dp_autotest_phy_pattern(intel_dp); |
4183 | break; | |
4184 | default: | |
5ec63bbd | 4185 | DRM_DEBUG_KMS("Invalid test request '%02x'\n", request); |
c5d5ab7a TP |
4186 | break; |
4187 | } | |
4188 | ||
5ec63bbd JN |
4189 | if (response & DP_TEST_ACK) |
4190 | intel_dp->compliance.test_type = request; | |
4191 | ||
c5d5ab7a | 4192 | update_status: |
5ec63bbd | 4193 | status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response); |
c5d5ab7a TP |
4194 | if (status <= 0) |
4195 | DRM_DEBUG_KMS("Could not write test response to sink\n"); | |
a60f0e38 JB |
4196 | } |
4197 | ||
0e32b39c DA |
4198 | static int |
4199 | intel_dp_check_mst_status(struct intel_dp *intel_dp) | |
4200 | { | |
4201 | bool bret; | |
4202 | ||
4203 | if (intel_dp->is_mst) { | |
4204 | u8 esi[16] = { 0 }; | |
4205 | int ret = 0; | |
4206 | int retry; | |
4207 | bool handled; | |
4208 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
4209 | go_again: | |
4210 | if (bret == true) { | |
4211 | ||
4212 | /* check link status - esi[10] = 0x200c */ | |
19e0b4ca | 4213 | if (intel_dp->active_mst_links && |
901c2daf | 4214 | !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { |
0e32b39c DA |
4215 | DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); |
4216 | intel_dp_start_link_train(intel_dp); | |
0e32b39c DA |
4217 | intel_dp_stop_link_train(intel_dp); |
4218 | } | |
4219 | ||
6f34cc39 | 4220 | DRM_DEBUG_KMS("got esi %3ph\n", esi); |
0e32b39c DA |
4221 | ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); |
4222 | ||
4223 | if (handled) { | |
4224 | for (retry = 0; retry < 3; retry++) { | |
4225 | int wret; | |
4226 | wret = drm_dp_dpcd_write(&intel_dp->aux, | |
4227 | DP_SINK_COUNT_ESI+1, | |
4228 | &esi[1], 3); | |
4229 | if (wret == 3) { | |
4230 | break; | |
4231 | } | |
4232 | } | |
4233 | ||
4234 | bret = intel_dp_get_sink_irq_esi(intel_dp, esi); | |
4235 | if (bret == true) { | |
6f34cc39 | 4236 | DRM_DEBUG_KMS("got esi2 %3ph\n", esi); |
0e32b39c DA |
4237 | goto go_again; |
4238 | } | |
4239 | } else | |
4240 | ret = 0; | |
4241 | ||
4242 | return ret; | |
4243 | } else { | |
4244 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4245 | DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); | |
4246 | intel_dp->is_mst = false; | |
4247 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst); | |
4248 | /* send a hotplug event */ | |
4249 | drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev); | |
4250 | } | |
4251 | } | |
4252 | return -EINVAL; | |
4253 | } | |
4254 | ||
bfd02b3c VS |
4255 | static void |
4256 | intel_dp_retrain_link(struct intel_dp *intel_dp) | |
4257 | { | |
4258 | struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; | |
4259 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
4260 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
4261 | ||
4262 | /* Suppress underruns caused by re-training */ | |
4263 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); | |
4264 | if (crtc->config->has_pch_encoder) | |
4265 | intel_set_pch_fifo_underrun_reporting(dev_priv, | |
4266 | intel_crtc_pch_transcoder(crtc), false); | |
4267 | ||
4268 | intel_dp_start_link_train(intel_dp); | |
4269 | intel_dp_stop_link_train(intel_dp); | |
4270 | ||
4271 | /* Keep underrun reporting disabled until things are stable */ | |
0f0f74bc | 4272 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
bfd02b3c VS |
4273 | |
4274 | intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); | |
4275 | if (crtc->config->has_pch_encoder) | |
4276 | intel_set_pch_fifo_underrun_reporting(dev_priv, | |
4277 | intel_crtc_pch_transcoder(crtc), true); | |
4278 | } | |
4279 | ||
5c9114d0 SS |
4280 | static void |
4281 | intel_dp_check_link_status(struct intel_dp *intel_dp) | |
4282 | { | |
4283 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; | |
4284 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
4285 | u8 link_status[DP_LINK_STATUS_SIZE]; | |
4286 | ||
4287 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); | |
4288 | ||
4289 | if (!intel_dp_get_link_status(intel_dp, link_status)) { | |
4290 | DRM_ERROR("Failed to get link status\n"); | |
4291 | return; | |
4292 | } | |
4293 | ||
4294 | if (!intel_encoder->base.crtc) | |
4295 | return; | |
4296 | ||
4297 | if (!to_intel_crtc(intel_encoder->base.crtc)->active) | |
4298 | return; | |
4299 | ||
14c562c0 MN |
4300 | /* |
4301 | * Validate the cached values of intel_dp->link_rate and | |
4302 | * intel_dp->lane_count before attempting to retrain. | |
4303 | */ | |
1a92c70e MN |
4304 | if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, |
4305 | intel_dp->lane_count)) | |
d4cb3fd9 MA |
4306 | return; |
4307 | ||
da15f7cb MN |
4308 | /* Retrain if Channel EQ or CR not ok */ |
4309 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { | |
5c9114d0 SS |
4310 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
4311 | intel_encoder->base.name); | |
bfd02b3c VS |
4312 | |
4313 | intel_dp_retrain_link(intel_dp); | |
5c9114d0 SS |
4314 | } |
4315 | } | |
4316 | ||
a4fc5ed6 KP |
4317 | /* |
4318 | * According to DP spec | |
4319 | * 5.1.2: | |
4320 | * 1. Read DPCD | |
4321 | * 2. Configure link according to Receiver Capabilities | |
4322 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 | |
4323 | * 4. Check link status on receipt of hot-plug interrupt | |
39ff747b SS |
4324 | * |
4325 | * intel_dp_short_pulse - handles short pulse interrupts | |
4326 | * when full detection is not required. | |
4327 | * Returns %true if short pulse is handled and full detection | |
4328 | * is NOT required and %false otherwise. | |
a4fc5ed6 | 4329 | */ |
39ff747b | 4330 | static bool |
5c9114d0 | 4331 | intel_dp_short_pulse(struct intel_dp *intel_dp) |
a4fc5ed6 | 4332 | { |
5b215bcf | 4333 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
da15f7cb | 4334 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
65fbb4e7 | 4335 | u8 sink_irq_vector = 0; |
39ff747b SS |
4336 | u8 old_sink_count = intel_dp->sink_count; |
4337 | bool ret; | |
5b215bcf | 4338 | |
4df6960e SS |
4339 | /* |
4340 | * Clearing compliance test variables to allow capturing | |
4341 | * of values for next automated test request. | |
4342 | */ | |
c1617abc | 4343 | memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); |
4df6960e | 4344 | |
39ff747b SS |
4345 | /* |
4346 | * Now read the DPCD to see if it's actually running | |
4347 | * If the current value of sink count doesn't match with | |
4348 | * the value that was stored earlier or dpcd read failed | |
4349 | * we need to do full detection | |
4350 | */ | |
4351 | ret = intel_dp_get_dpcd(intel_dp); | |
4352 | ||
4353 | if ((old_sink_count != intel_dp->sink_count) || !ret) { | |
4354 | /* No need to proceed if we are going to do full detect */ | |
4355 | return false; | |
59cd09e1 JB |
4356 | } |
4357 | ||
a60f0e38 JB |
4358 | /* Try to read the source of the interrupt */ |
4359 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
65fbb4e7 VS |
4360 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
4361 | sink_irq_vector != 0) { | |
a60f0e38 | 4362 | /* Clear interrupt source */ |
9d1a1031 JN |
4363 | drm_dp_dpcd_writeb(&intel_dp->aux, |
4364 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4365 | sink_irq_vector); | |
a60f0e38 JB |
4366 | |
4367 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
da15f7cb | 4368 | intel_dp_handle_test_request(intel_dp); |
a60f0e38 JB |
4369 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
4370 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4371 | } | |
4372 | ||
5c9114d0 SS |
4373 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
4374 | intel_dp_check_link_status(intel_dp); | |
4375 | drm_modeset_unlock(&dev->mode_config.connection_mutex); | |
da15f7cb MN |
4376 | if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { |
4377 | DRM_DEBUG_KMS("Link Training Compliance Test requested\n"); | |
4378 | /* Send a Hotplug Uevent to userspace to start modeset */ | |
4379 | drm_kms_helper_hotplug_event(intel_encoder->base.dev); | |
4380 | } | |
39ff747b SS |
4381 | |
4382 | return true; | |
a4fc5ed6 | 4383 | } |
a4fc5ed6 | 4384 | |
caf9ab24 | 4385 | /* XXX this is probably wrong for multiple downstream ports */ |
71ba9000 | 4386 | static enum drm_connector_status |
26d61aad | 4387 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
71ba9000 | 4388 | { |
e393d0d6 | 4389 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); |
caf9ab24 | 4390 | uint8_t *dpcd = intel_dp->dpcd; |
caf9ab24 AJ |
4391 | uint8_t type; |
4392 | ||
e393d0d6 ID |
4393 | if (lspcon->active) |
4394 | lspcon_resume(lspcon); | |
4395 | ||
caf9ab24 AJ |
4396 | if (!intel_dp_get_dpcd(intel_dp)) |
4397 | return connector_status_disconnected; | |
4398 | ||
1853a9da | 4399 | if (intel_dp_is_edp(intel_dp)) |
1034ce70 SS |
4400 | return connector_status_connected; |
4401 | ||
caf9ab24 | 4402 | /* if there's no downstream port, we're done */ |
c726ad01 | 4403 | if (!drm_dp_is_branch(dpcd)) |
26d61aad | 4404 | return connector_status_connected; |
caf9ab24 AJ |
4405 | |
4406 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ | |
c9ff160b JN |
4407 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
4408 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { | |
9d1a1031 | 4409 | |
30d9aa42 SS |
4410 | return intel_dp->sink_count ? |
4411 | connector_status_connected : connector_status_disconnected; | |
caf9ab24 AJ |
4412 | } |
4413 | ||
c4e3170a VS |
4414 | if (intel_dp_can_mst(intel_dp)) |
4415 | return connector_status_connected; | |
4416 | ||
caf9ab24 | 4417 | /* If no HPD, poke DDC gently */ |
0b99836f | 4418 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
26d61aad | 4419 | return connector_status_connected; |
caf9ab24 AJ |
4420 | |
4421 | /* Well we tried, say unknown for unreliable port types */ | |
c9ff160b JN |
4422 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
4423 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; | |
4424 | if (type == DP_DS_PORT_TYPE_VGA || | |
4425 | type == DP_DS_PORT_TYPE_NON_EDID) | |
4426 | return connector_status_unknown; | |
4427 | } else { | |
4428 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
4429 | DP_DWN_STRM_PORT_TYPE_MASK; | |
4430 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || | |
4431 | type == DP_DWN_STRM_PORT_TYPE_OTHER) | |
4432 | return connector_status_unknown; | |
4433 | } | |
caf9ab24 AJ |
4434 | |
4435 | /* Anything else is out of spec, warn and ignore */ | |
4436 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); | |
26d61aad | 4437 | return connector_status_disconnected; |
71ba9000 AJ |
4438 | } |
4439 | ||
d410b56d CW |
4440 | static enum drm_connector_status |
4441 | edp_detect(struct intel_dp *intel_dp) | |
4442 | { | |
4443 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
1650be74 | 4444 | struct drm_i915_private *dev_priv = to_i915(dev); |
d410b56d CW |
4445 | enum drm_connector_status status; |
4446 | ||
1650be74 | 4447 | status = intel_panel_detect(dev_priv); |
d410b56d CW |
4448 | if (status == connector_status_unknown) |
4449 | status = connector_status_connected; | |
4450 | ||
4451 | return status; | |
4452 | } | |
4453 | ||
b93433cc JN |
4454 | static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, |
4455 | struct intel_digital_port *port) | |
5eb08b69 | 4456 | { |
b93433cc | 4457 | u32 bit; |
01cb9ea6 | 4458 | |
0df53b77 | 4459 | switch (port->port) { |
0df53b77 JN |
4460 | case PORT_B: |
4461 | bit = SDE_PORTB_HOTPLUG; | |
4462 | break; | |
4463 | case PORT_C: | |
4464 | bit = SDE_PORTC_HOTPLUG; | |
4465 | break; | |
4466 | case PORT_D: | |
4467 | bit = SDE_PORTD_HOTPLUG; | |
4468 | break; | |
4469 | default: | |
4470 | MISSING_CASE(port->port); | |
4471 | return false; | |
4472 | } | |
4473 | ||
4474 | return I915_READ(SDEISR) & bit; | |
4475 | } | |
4476 | ||
4477 | static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv, | |
4478 | struct intel_digital_port *port) | |
4479 | { | |
4480 | u32 bit; | |
4481 | ||
4482 | switch (port->port) { | |
0df53b77 JN |
4483 | case PORT_B: |
4484 | bit = SDE_PORTB_HOTPLUG_CPT; | |
4485 | break; | |
4486 | case PORT_C: | |
4487 | bit = SDE_PORTC_HOTPLUG_CPT; | |
4488 | break; | |
4489 | case PORT_D: | |
4490 | bit = SDE_PORTD_HOTPLUG_CPT; | |
4491 | break; | |
93e5f0b6 VS |
4492 | default: |
4493 | MISSING_CASE(port->port); | |
4494 | return false; | |
4495 | } | |
4496 | ||
4497 | return I915_READ(SDEISR) & bit; | |
4498 | } | |
4499 | ||
4500 | static bool spt_digital_port_connected(struct drm_i915_private *dev_priv, | |
4501 | struct intel_digital_port *port) | |
4502 | { | |
4503 | u32 bit; | |
4504 | ||
4505 | switch (port->port) { | |
4506 | case PORT_A: | |
4507 | bit = SDE_PORTA_HOTPLUG_SPT; | |
4508 | break; | |
a78695d3 JN |
4509 | case PORT_E: |
4510 | bit = SDE_PORTE_HOTPLUG_SPT; | |
4511 | break; | |
0df53b77 | 4512 | default: |
93e5f0b6 | 4513 | return cpt_digital_port_connected(dev_priv, port); |
b93433cc | 4514 | } |
1b469639 | 4515 | |
b93433cc | 4516 | return I915_READ(SDEISR) & bit; |
5eb08b69 ZW |
4517 | } |
4518 | ||
7e66bcf2 | 4519 | static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv, |
1d245987 | 4520 | struct intel_digital_port *port) |
a4fc5ed6 | 4521 | { |
9642c81c | 4522 | u32 bit; |
5eb08b69 | 4523 | |
9642c81c JN |
4524 | switch (port->port) { |
4525 | case PORT_B: | |
4526 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; | |
4527 | break; | |
4528 | case PORT_C: | |
4529 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; | |
4530 | break; | |
4531 | case PORT_D: | |
4532 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; | |
4533 | break; | |
4534 | default: | |
4535 | MISSING_CASE(port->port); | |
4536 | return false; | |
4537 | } | |
4538 | ||
4539 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | |
4540 | } | |
4541 | ||
0780cd36 VS |
4542 | static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv, |
4543 | struct intel_digital_port *port) | |
9642c81c JN |
4544 | { |
4545 | u32 bit; | |
4546 | ||
4547 | switch (port->port) { | |
4548 | case PORT_B: | |
0780cd36 | 4549 | bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4550 | break; |
4551 | case PORT_C: | |
0780cd36 | 4552 | bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4553 | break; |
4554 | case PORT_D: | |
0780cd36 | 4555 | bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; |
9642c81c JN |
4556 | break; |
4557 | default: | |
4558 | MISSING_CASE(port->port); | |
4559 | return false; | |
a4fc5ed6 KP |
4560 | } |
4561 | ||
1d245987 | 4562 | return I915_READ(PORT_HOTPLUG_STAT) & bit; |
2a592bec DA |
4563 | } |
4564 | ||
93e5f0b6 VS |
4565 | static bool ilk_digital_port_connected(struct drm_i915_private *dev_priv, |
4566 | struct intel_digital_port *port) | |
4567 | { | |
4568 | if (port->port == PORT_A) | |
4569 | return I915_READ(DEISR) & DE_DP_A_HOTPLUG; | |
4570 | else | |
4571 | return ibx_digital_port_connected(dev_priv, port); | |
4572 | } | |
4573 | ||
4574 | static bool snb_digital_port_connected(struct drm_i915_private *dev_priv, | |
4575 | struct intel_digital_port *port) | |
4576 | { | |
4577 | if (port->port == PORT_A) | |
4578 | return I915_READ(DEISR) & DE_DP_A_HOTPLUG; | |
4579 | else | |
4580 | return cpt_digital_port_connected(dev_priv, port); | |
4581 | } | |
4582 | ||
4583 | static bool ivb_digital_port_connected(struct drm_i915_private *dev_priv, | |
4584 | struct intel_digital_port *port) | |
4585 | { | |
4586 | if (port->port == PORT_A) | |
4587 | return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB; | |
4588 | else | |
4589 | return cpt_digital_port_connected(dev_priv, port); | |
4590 | } | |
4591 | ||
4592 | static bool bdw_digital_port_connected(struct drm_i915_private *dev_priv, | |
4593 | struct intel_digital_port *port) | |
4594 | { | |
4595 | if (port->port == PORT_A) | |
4596 | return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG; | |
4597 | else | |
4598 | return cpt_digital_port_connected(dev_priv, port); | |
4599 | } | |
4600 | ||
e464bfde | 4601 | static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv, |
e2ec35a5 | 4602 | struct intel_digital_port *intel_dig_port) |
e464bfde | 4603 | { |
e2ec35a5 SJ |
4604 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
4605 | enum port port; | |
e464bfde JN |
4606 | u32 bit; |
4607 | ||
256cfdde | 4608 | port = intel_hpd_pin_to_port(intel_encoder->hpd_pin); |
e2ec35a5 | 4609 | switch (port) { |
e464bfde JN |
4610 | case PORT_A: |
4611 | bit = BXT_DE_PORT_HP_DDIA; | |
4612 | break; | |
4613 | case PORT_B: | |
4614 | bit = BXT_DE_PORT_HP_DDIB; | |
4615 | break; | |
4616 | case PORT_C: | |
4617 | bit = BXT_DE_PORT_HP_DDIC; | |
4618 | break; | |
4619 | default: | |
e2ec35a5 | 4620 | MISSING_CASE(port); |
e464bfde JN |
4621 | return false; |
4622 | } | |
4623 | ||
4624 | return I915_READ(GEN8_DE_PORT_ISR) & bit; | |
4625 | } | |
4626 | ||
7e66bcf2 JN |
4627 | /* |
4628 | * intel_digital_port_connected - is the specified port connected? | |
4629 | * @dev_priv: i915 private structure | |
4630 | * @port: the port to test | |
4631 | * | |
4632 | * Return %true if @port is connected, %false otherwise. | |
4633 | */ | |
390b4e00 ID |
4634 | bool intel_digital_port_connected(struct drm_i915_private *dev_priv, |
4635 | struct intel_digital_port *port) | |
7e66bcf2 | 4636 | { |
93e5f0b6 VS |
4637 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
4638 | if (IS_GM45(dev_priv)) | |
4639 | return gm45_digital_port_connected(dev_priv, port); | |
4640 | else | |
4641 | return g4x_digital_port_connected(dev_priv, port); | |
4642 | } | |
4643 | ||
4644 | if (IS_GEN5(dev_priv)) | |
4645 | return ilk_digital_port_connected(dev_priv, port); | |
4646 | else if (IS_GEN6(dev_priv)) | |
4647 | return snb_digital_port_connected(dev_priv, port); | |
4648 | else if (IS_GEN7(dev_priv)) | |
4649 | return ivb_digital_port_connected(dev_priv, port); | |
4650 | else if (IS_GEN8(dev_priv)) | |
4651 | return bdw_digital_port_connected(dev_priv, port); | |
cc3f90f0 | 4652 | else if (IS_GEN9_LP(dev_priv)) |
e464bfde | 4653 | return bxt_digital_port_connected(dev_priv, port); |
7e66bcf2 | 4654 | else |
93e5f0b6 | 4655 | return spt_digital_port_connected(dev_priv, port); |
7e66bcf2 JN |
4656 | } |
4657 | ||
8c241fef | 4658 | static struct edid * |
beb60608 | 4659 | intel_dp_get_edid(struct intel_dp *intel_dp) |
8c241fef | 4660 | { |
beb60608 | 4661 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
d6f24d0f | 4662 | |
9cd300e0 JN |
4663 | /* use cached edid if we have one */ |
4664 | if (intel_connector->edid) { | |
9cd300e0 JN |
4665 | /* invalid edid */ |
4666 | if (IS_ERR(intel_connector->edid)) | |
d6f24d0f JB |
4667 | return NULL; |
4668 | ||
55e9edeb | 4669 | return drm_edid_duplicate(intel_connector->edid); |
beb60608 CW |
4670 | } else |
4671 | return drm_get_edid(&intel_connector->base, | |
4672 | &intel_dp->aux.ddc); | |
4673 | } | |
8c241fef | 4674 | |
beb60608 CW |
4675 | static void |
4676 | intel_dp_set_edid(struct intel_dp *intel_dp) | |
4677 | { | |
4678 | struct intel_connector *intel_connector = intel_dp->attached_connector; | |
4679 | struct edid *edid; | |
8c241fef | 4680 | |
f21a2198 | 4681 | intel_dp_unset_edid(intel_dp); |
beb60608 CW |
4682 | edid = intel_dp_get_edid(intel_dp); |
4683 | intel_connector->detect_edid = edid; | |
4684 | ||
e6b72c94 | 4685 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
8c241fef KP |
4686 | } |
4687 | ||
beb60608 CW |
4688 | static void |
4689 | intel_dp_unset_edid(struct intel_dp *intel_dp) | |
8c241fef | 4690 | { |
beb60608 | 4691 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
8c241fef | 4692 | |
beb60608 CW |
4693 | kfree(intel_connector->detect_edid); |
4694 | intel_connector->detect_edid = NULL; | |
9cd300e0 | 4695 | |
beb60608 CW |
4696 | intel_dp->has_audio = false; |
4697 | } | |
d6f24d0f | 4698 | |
6c5ed5ae | 4699 | static int |
f21a2198 | 4700 | intel_dp_long_pulse(struct intel_connector *intel_connector) |
a9756bb5 | 4701 | { |
f21a2198 | 4702 | struct drm_connector *connector = &intel_connector->base; |
a9756bb5 | 4703 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
d63885da PZ |
4704 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
4705 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
fa90ecef | 4706 | struct drm_device *dev = connector->dev; |
a9756bb5 | 4707 | enum drm_connector_status status; |
65fbb4e7 | 4708 | u8 sink_irq_vector = 0; |
a9756bb5 | 4709 | |
6c5ed5ae ML |
4710 | WARN_ON(!drm_modeset_is_locked(&connector->dev->mode_config.connection_mutex)); |
4711 | ||
5432fcaf | 4712 | intel_display_power_get(to_i915(dev), intel_dp->aux_power_domain); |
a9756bb5 | 4713 | |
d410b56d | 4714 | /* Can't disconnect eDP, but you can close the lid... */ |
1853a9da | 4715 | if (intel_dp_is_edp(intel_dp)) |
d410b56d | 4716 | status = edp_detect(intel_dp); |
c555a81d ACO |
4717 | else if (intel_digital_port_connected(to_i915(dev), |
4718 | dp_to_dig_port(intel_dp))) | |
4719 | status = intel_dp_detect_dpcd(intel_dp); | |
a9756bb5 | 4720 | else |
c555a81d ACO |
4721 | status = connector_status_disconnected; |
4722 | ||
5cb651a7 | 4723 | if (status == connector_status_disconnected) { |
c1617abc | 4724 | memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); |
4df6960e | 4725 | |
0e505a08 | 4726 | if (intel_dp->is_mst) { |
4727 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
4728 | intel_dp->is_mst, | |
4729 | intel_dp->mst_mgr.mst_state); | |
4730 | intel_dp->is_mst = false; | |
4731 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
4732 | intel_dp->is_mst); | |
4733 | } | |
4734 | ||
c8c8fb33 | 4735 | goto out; |
4df6960e | 4736 | } |
a9756bb5 | 4737 | |
f21a2198 | 4738 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
cca0502b | 4739 | intel_encoder->type = INTEL_OUTPUT_DP; |
f21a2198 | 4740 | |
fe5a66f9 VS |
4741 | DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n", |
4742 | yesno(intel_dp_source_supports_hbr2(intel_dp)), | |
4743 | yesno(drm_dp_tps3_supported(intel_dp->dpcd))); | |
4744 | ||
d7e8ef02 | 4745 | if (intel_dp->reset_link_params) { |
540b0b7f JN |
4746 | /* Initial max link lane count */ |
4747 | intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); | |
f482984a | 4748 | |
540b0b7f JN |
4749 | /* Initial max link rate */ |
4750 | intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); | |
d7e8ef02 MN |
4751 | |
4752 | intel_dp->reset_link_params = false; | |
4753 | } | |
f482984a | 4754 | |
fe5a66f9 VS |
4755 | intel_dp_print_rates(intel_dp); |
4756 | ||
84c36753 JN |
4757 | drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, |
4758 | drm_dp_is_branch(intel_dp->dpcd)); | |
0e390a33 | 4759 | |
c4e3170a VS |
4760 | intel_dp_configure_mst(intel_dp); |
4761 | ||
4762 | if (intel_dp->is_mst) { | |
f21a2198 SS |
4763 | /* |
4764 | * If we are in MST mode then this connector | |
4765 | * won't appear connected or have anything | |
4766 | * with EDID on it | |
4767 | */ | |
0e32b39c DA |
4768 | status = connector_status_disconnected; |
4769 | goto out; | |
1a36147b VS |
4770 | } else { |
4771 | /* | |
4772 | * If display is now connected check links status, | |
4773 | * there has been known issues of link loss triggerring | |
4774 | * long pulse. | |
4775 | * | |
4776 | * Some sinks (eg. ASUS PB287Q) seem to perform some | |
4777 | * weird HPD ping pong during modesets. So we can apparently | |
4778 | * end up with HPD going low during a modeset, and then | |
4779 | * going back up soon after. And once that happens we must | |
4780 | * retrain the link to get a picture. That's in case no | |
4781 | * userspace component reacted to intermittent HPD dip. | |
4782 | */ | |
7d23e3c3 | 4783 | intel_dp_check_link_status(intel_dp); |
0e32b39c DA |
4784 | } |
4785 | ||
4df6960e SS |
4786 | /* |
4787 | * Clearing NACK and defer counts to get their exact values | |
4788 | * while reading EDID which are required by Compliance tests | |
4789 | * 4.2.2.4 and 4.2.2.5 | |
4790 | */ | |
4791 | intel_dp->aux.i2c_nack_count = 0; | |
4792 | intel_dp->aux.i2c_defer_count = 0; | |
4793 | ||
beb60608 | 4794 | intel_dp_set_edid(intel_dp); |
1853a9da | 4795 | if (intel_dp_is_edp(intel_dp) || intel_connector->detect_edid) |
5cb651a7 | 4796 | status = connector_status_connected; |
7d23e3c3 | 4797 | intel_dp->detect_done = true; |
c8c8fb33 | 4798 | |
09b1eb13 TP |
4799 | /* Try to read the source of the interrupt */ |
4800 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && | |
65fbb4e7 VS |
4801 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) && |
4802 | sink_irq_vector != 0) { | |
09b1eb13 TP |
4803 | /* Clear interrupt source */ |
4804 | drm_dp_dpcd_writeb(&intel_dp->aux, | |
4805 | DP_DEVICE_SERVICE_IRQ_VECTOR, | |
4806 | sink_irq_vector); | |
4807 | ||
4808 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) | |
4809 | intel_dp_handle_test_request(intel_dp); | |
4810 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) | |
4811 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); | |
4812 | } | |
4813 | ||
c8c8fb33 | 4814 | out: |
5cb651a7 | 4815 | if (status != connector_status_connected && !intel_dp->is_mst) |
f21a2198 | 4816 | intel_dp_unset_edid(intel_dp); |
7d23e3c3 | 4817 | |
5432fcaf | 4818 | intel_display_power_put(to_i915(dev), intel_dp->aux_power_domain); |
5cb651a7 | 4819 | return status; |
f21a2198 SS |
4820 | } |
4821 | ||
6c5ed5ae ML |
4822 | static int |
4823 | intel_dp_detect(struct drm_connector *connector, | |
4824 | struct drm_modeset_acquire_ctx *ctx, | |
4825 | bool force) | |
f21a2198 SS |
4826 | { |
4827 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
6c5ed5ae | 4828 | int status = connector->status; |
f21a2198 SS |
4829 | |
4830 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
4831 | connector->base.id, connector->name); | |
4832 | ||
7d23e3c3 SS |
4833 | /* If full detect is not performed yet, do a full detect */ |
4834 | if (!intel_dp->detect_done) | |
5cb651a7 | 4835 | status = intel_dp_long_pulse(intel_dp->attached_connector); |
7d23e3c3 SS |
4836 | |
4837 | intel_dp->detect_done = false; | |
f21a2198 | 4838 | |
5cb651a7 | 4839 | return status; |
a4fc5ed6 KP |
4840 | } |
4841 | ||
beb60608 CW |
4842 | static void |
4843 | intel_dp_force(struct drm_connector *connector) | |
a4fc5ed6 | 4844 | { |
df0e9248 | 4845 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
beb60608 | 4846 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
25f78f58 | 4847 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
a4fc5ed6 | 4848 | |
beb60608 CW |
4849 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
4850 | connector->base.id, connector->name); | |
4851 | intel_dp_unset_edid(intel_dp); | |
a4fc5ed6 | 4852 | |
beb60608 CW |
4853 | if (connector->status != connector_status_connected) |
4854 | return; | |
671dedd2 | 4855 | |
5432fcaf | 4856 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
beb60608 CW |
4857 | |
4858 | intel_dp_set_edid(intel_dp); | |
4859 | ||
5432fcaf | 4860 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
beb60608 CW |
4861 | |
4862 | if (intel_encoder->type != INTEL_OUTPUT_EDP) | |
cca0502b | 4863 | intel_encoder->type = INTEL_OUTPUT_DP; |
beb60608 CW |
4864 | } |
4865 | ||
4866 | static int intel_dp_get_modes(struct drm_connector *connector) | |
4867 | { | |
4868 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
4869 | struct edid *edid; | |
4870 | ||
4871 | edid = intel_connector->detect_edid; | |
4872 | if (edid) { | |
4873 | int ret = intel_connector_update_modes(connector, edid); | |
4874 | if (ret) | |
4875 | return ret; | |
4876 | } | |
32f9d658 | 4877 | |
f8779fda | 4878 | /* if eDP has no EDID, fall back to fixed mode */ |
1853a9da | 4879 | if (intel_dp_is_edp(intel_attached_dp(connector)) && |
beb60608 | 4880 | intel_connector->panel.fixed_mode) { |
f8779fda | 4881 | struct drm_display_mode *mode; |
beb60608 CW |
4882 | |
4883 | mode = drm_mode_duplicate(connector->dev, | |
dd06f90e | 4884 | intel_connector->panel.fixed_mode); |
f8779fda | 4885 | if (mode) { |
32f9d658 ZW |
4886 | drm_mode_probed_add(connector, mode); |
4887 | return 1; | |
4888 | } | |
4889 | } | |
beb60608 | 4890 | |
32f9d658 | 4891 | return 0; |
a4fc5ed6 KP |
4892 | } |
4893 | ||
7a418e34 CW |
4894 | static int |
4895 | intel_dp_connector_register(struct drm_connector *connector) | |
4896 | { | |
4897 | struct intel_dp *intel_dp = intel_attached_dp(connector); | |
1ebaa0b9 CW |
4898 | int ret; |
4899 | ||
4900 | ret = intel_connector_register(connector); | |
4901 | if (ret) | |
4902 | return ret; | |
7a418e34 CW |
4903 | |
4904 | i915_debugfs_connector_add(connector); | |
4905 | ||
4906 | DRM_DEBUG_KMS("registering %s bus for %s\n", | |
4907 | intel_dp->aux.name, connector->kdev->kobj.name); | |
4908 | ||
4909 | intel_dp->aux.dev = connector->kdev; | |
4910 | return drm_dp_aux_register(&intel_dp->aux); | |
4911 | } | |
4912 | ||
c191eca1 CW |
4913 | static void |
4914 | intel_dp_connector_unregister(struct drm_connector *connector) | |
4915 | { | |
4916 | drm_dp_aux_unregister(&intel_attached_dp(connector)->aux); | |
4917 | intel_connector_unregister(connector); | |
4918 | } | |
4919 | ||
a4fc5ed6 | 4920 | static void |
73845adf | 4921 | intel_dp_connector_destroy(struct drm_connector *connector) |
a4fc5ed6 | 4922 | { |
1d508706 | 4923 | struct intel_connector *intel_connector = to_intel_connector(connector); |
aaa6fd2a | 4924 | |
10e972d3 | 4925 | kfree(intel_connector->detect_edid); |
beb60608 | 4926 | |
9cd300e0 JN |
4927 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
4928 | kfree(intel_connector->edid); | |
4929 | ||
1853a9da JN |
4930 | /* |
4931 | * Can't call intel_dp_is_edp() since the encoder may have been | |
4932 | * destroyed already. | |
4933 | */ | |
acd8db10 | 4934 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
1d508706 | 4935 | intel_panel_fini(&intel_connector->panel); |
aaa6fd2a | 4936 | |
a4fc5ed6 | 4937 | drm_connector_cleanup(connector); |
55f78c43 | 4938 | kfree(connector); |
a4fc5ed6 KP |
4939 | } |
4940 | ||
00c09d70 | 4941 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
24d05927 | 4942 | { |
da63a9f2 PZ |
4943 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
4944 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
24d05927 | 4945 | |
0e32b39c | 4946 | intel_dp_mst_encoder_cleanup(intel_dig_port); |
1853a9da | 4947 | if (intel_dp_is_edp(intel_dp)) { |
bd943159 | 4948 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
951468f3 VS |
4949 | /* |
4950 | * vdd might still be enabled do to the delayed vdd off. | |
4951 | * Make sure vdd is actually turned off here. | |
4952 | */ | |
773538e8 | 4953 | pps_lock(intel_dp); |
4be73780 | 4954 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 VS |
4955 | pps_unlock(intel_dp); |
4956 | ||
01527b31 CT |
4957 | if (intel_dp->edp_notifier.notifier_call) { |
4958 | unregister_reboot_notifier(&intel_dp->edp_notifier); | |
4959 | intel_dp->edp_notifier.notifier_call = NULL; | |
4960 | } | |
bd943159 | 4961 | } |
99681886 CW |
4962 | |
4963 | intel_dp_aux_fini(intel_dp); | |
4964 | ||
c8bd0e49 | 4965 | drm_encoder_cleanup(encoder); |
da63a9f2 | 4966 | kfree(intel_dig_port); |
24d05927 DV |
4967 | } |
4968 | ||
bf93ba67 | 4969 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) |
07f9cd0b ID |
4970 | { |
4971 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
4972 | ||
1853a9da | 4973 | if (!intel_dp_is_edp(intel_dp)) |
07f9cd0b ID |
4974 | return; |
4975 | ||
951468f3 VS |
4976 | /* |
4977 | * vdd might still be enabled do to the delayed vdd off. | |
4978 | * Make sure vdd is actually turned off here. | |
4979 | */ | |
afa4e53a | 4980 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
773538e8 | 4981 | pps_lock(intel_dp); |
07f9cd0b | 4982 | edp_panel_vdd_off_sync(intel_dp); |
773538e8 | 4983 | pps_unlock(intel_dp); |
07f9cd0b ID |
4984 | } |
4985 | ||
49e6bc51 VS |
4986 | static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) |
4987 | { | |
4988 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
4989 | struct drm_device *dev = intel_dig_port->base.base.dev; | |
fac5e23e | 4990 | struct drm_i915_private *dev_priv = to_i915(dev); |
49e6bc51 VS |
4991 | |
4992 | lockdep_assert_held(&dev_priv->pps_mutex); | |
4993 | ||
4994 | if (!edp_have_panel_vdd(intel_dp)) | |
4995 | return; | |
4996 | ||
4997 | /* | |
4998 | * The VDD bit needs a power domain reference, so if the bit is | |
4999 | * already enabled when we boot or resume, grab this reference and | |
5000 | * schedule a vdd off, so we don't hold on to the reference | |
5001 | * indefinitely. | |
5002 | */ | |
5003 | DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); | |
5432fcaf | 5004 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
49e6bc51 VS |
5005 | |
5006 | edp_panel_vdd_schedule_off(intel_dp); | |
5007 | } | |
5008 | ||
9f2bdb00 VS |
5009 | static enum pipe vlv_active_pipe(struct intel_dp *intel_dp) |
5010 | { | |
5011 | struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp)); | |
5012 | ||
5013 | if ((intel_dp->DP & DP_PORT_EN) == 0) | |
5014 | return INVALID_PIPE; | |
5015 | ||
5016 | if (IS_CHERRYVIEW(dev_priv)) | |
5017 | return DP_PORT_TO_PIPE_CHV(intel_dp->DP); | |
5018 | else | |
5019 | return PORT_TO_PIPE(intel_dp->DP); | |
5020 | } | |
5021 | ||
bf93ba67 | 5022 | void intel_dp_encoder_reset(struct drm_encoder *encoder) |
6d93c0c4 | 5023 | { |
64989ca4 | 5024 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
dd75f6dd ID |
5025 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
5026 | struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); | |
64989ca4 VS |
5027 | |
5028 | if (!HAS_DDI(dev_priv)) | |
5029 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
49e6bc51 | 5030 | |
dd75f6dd | 5031 | if (lspcon->active) |
910530c0 SS |
5032 | lspcon_resume(lspcon); |
5033 | ||
d7e8ef02 MN |
5034 | intel_dp->reset_link_params = true; |
5035 | ||
49e6bc51 VS |
5036 | pps_lock(intel_dp); |
5037 | ||
9f2bdb00 VS |
5038 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
5039 | intel_dp->active_pipe = vlv_active_pipe(intel_dp); | |
5040 | ||
1853a9da | 5041 | if (intel_dp_is_edp(intel_dp)) { |
9f2bdb00 VS |
5042 | /* Reinit the power sequencer, in case BIOS did something with it. */ |
5043 | intel_dp_pps_init(encoder->dev, intel_dp); | |
5044 | intel_edp_panel_vdd_sanitize(intel_dp); | |
5045 | } | |
49e6bc51 VS |
5046 | |
5047 | pps_unlock(intel_dp); | |
6d93c0c4 ID |
5048 | } |
5049 | ||
a4fc5ed6 | 5050 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
beb60608 | 5051 | .force = intel_dp_force, |
a4fc5ed6 | 5052 | .fill_modes = drm_helper_probe_single_connector_modes, |
8f647a01 ML |
5053 | .atomic_get_property = intel_digital_connector_atomic_get_property, |
5054 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
7a418e34 | 5055 | .late_register = intel_dp_connector_register, |
c191eca1 | 5056 | .early_unregister = intel_dp_connector_unregister, |
73845adf | 5057 | .destroy = intel_dp_connector_destroy, |
c6f95f27 | 5058 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
8f647a01 | 5059 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
a4fc5ed6 KP |
5060 | }; |
5061 | ||
5062 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { | |
6c5ed5ae | 5063 | .detect_ctx = intel_dp_detect, |
a4fc5ed6 KP |
5064 | .get_modes = intel_dp_get_modes, |
5065 | .mode_valid = intel_dp_mode_valid, | |
8f647a01 | 5066 | .atomic_check = intel_digital_connector_atomic_check, |
a4fc5ed6 KP |
5067 | }; |
5068 | ||
a4fc5ed6 | 5069 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
6d93c0c4 | 5070 | .reset = intel_dp_encoder_reset, |
24d05927 | 5071 | .destroy = intel_dp_encoder_destroy, |
a4fc5ed6 KP |
5072 | }; |
5073 | ||
b2c5c181 | 5074 | enum irqreturn |
13cf5504 DA |
5075 | intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) |
5076 | { | |
5077 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
0e32b39c | 5078 | struct drm_device *dev = intel_dig_port->base.base.dev; |
fac5e23e | 5079 | struct drm_i915_private *dev_priv = to_i915(dev); |
b2c5c181 | 5080 | enum irqreturn ret = IRQ_NONE; |
1c767b33 | 5081 | |
2540058f TI |
5082 | if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && |
5083 | intel_dig_port->base.type != INTEL_OUTPUT_HDMI) | |
cca0502b | 5084 | intel_dig_port->base.type = INTEL_OUTPUT_DP; |
13cf5504 | 5085 | |
7a7f84cc VS |
5086 | if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { |
5087 | /* | |
5088 | * vdd off can generate a long pulse on eDP which | |
5089 | * would require vdd on to handle it, and thus we | |
5090 | * would end up in an endless cycle of | |
5091 | * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." | |
5092 | */ | |
5093 | DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", | |
5094 | port_name(intel_dig_port->port)); | |
a8b3d52f | 5095 | return IRQ_HANDLED; |
7a7f84cc VS |
5096 | } |
5097 | ||
26fbb774 VS |
5098 | DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", |
5099 | port_name(intel_dig_port->port), | |
0e32b39c | 5100 | long_hpd ? "long" : "short"); |
13cf5504 | 5101 | |
27d4efc5 | 5102 | if (long_hpd) { |
d7e8ef02 | 5103 | intel_dp->reset_link_params = true; |
27d4efc5 VS |
5104 | intel_dp->detect_done = false; |
5105 | return IRQ_NONE; | |
5106 | } | |
5107 | ||
5432fcaf | 5108 | intel_display_power_get(dev_priv, intel_dp->aux_power_domain); |
1c767b33 | 5109 | |
27d4efc5 VS |
5110 | if (intel_dp->is_mst) { |
5111 | if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { | |
5112 | /* | |
5113 | * If we were in MST mode, and device is not | |
5114 | * there, get out of MST mode | |
5115 | */ | |
5116 | DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", | |
5117 | intel_dp->is_mst, intel_dp->mst_mgr.mst_state); | |
5118 | intel_dp->is_mst = false; | |
5119 | drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, | |
5120 | intel_dp->is_mst); | |
5121 | intel_dp->detect_done = false; | |
5122 | goto put_power; | |
0e32b39c | 5123 | } |
27d4efc5 | 5124 | } |
0e32b39c | 5125 | |
27d4efc5 VS |
5126 | if (!intel_dp->is_mst) { |
5127 | if (!intel_dp_short_pulse(intel_dp)) { | |
5128 | intel_dp->detect_done = false; | |
5129 | goto put_power; | |
39ff747b | 5130 | } |
0e32b39c | 5131 | } |
b2c5c181 DV |
5132 | |
5133 | ret = IRQ_HANDLED; | |
5134 | ||
1c767b33 | 5135 | put_power: |
5432fcaf | 5136 | intel_display_power_put(dev_priv, intel_dp->aux_power_domain); |
1c767b33 ID |
5137 | |
5138 | return ret; | |
13cf5504 DA |
5139 | } |
5140 | ||
477ec328 | 5141 | /* check the VBT to see whether the eDP is on another port */ |
7b91bf7f | 5142 | bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port) |
36e83a18 | 5143 | { |
53ce81a7 VS |
5144 | /* |
5145 | * eDP not supported on g4x. so bail out early just | |
5146 | * for a bit extra safety in case the VBT is bonkers. | |
5147 | */ | |
dd11bc10 | 5148 | if (INTEL_GEN(dev_priv) < 5) |
53ce81a7 VS |
5149 | return false; |
5150 | ||
a98d9c1d | 5151 | if (INTEL_GEN(dev_priv) < 9 && port == PORT_A) |
3b32a35b VS |
5152 | return true; |
5153 | ||
951d9efe | 5154 | return intel_bios_is_port_edp(dev_priv, port); |
36e83a18 ZY |
5155 | } |
5156 | ||
200819ab | 5157 | static void |
f684960e CW |
5158 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
5159 | { | |
8b45330a ML |
5160 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
5161 | ||
3f43c48d | 5162 | intel_attach_force_audio_property(connector); |
e953fd7b | 5163 | intel_attach_broadcast_rgb_property(connector); |
53b41837 | 5164 | |
1853a9da | 5165 | if (intel_dp_is_edp(intel_dp)) { |
8b45330a ML |
5166 | u32 allowed_scalers; |
5167 | ||
5168 | allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); | |
5169 | if (!HAS_GMCH_DISPLAY(dev_priv)) | |
5170 | allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); | |
5171 | ||
5172 | drm_connector_attach_scaling_mode_property(connector, allowed_scalers); | |
5173 | ||
eead06df | 5174 | connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; |
8b45330a | 5175 | |
53b41837 | 5176 | } |
f684960e CW |
5177 | } |
5178 | ||
dada1a9f ID |
5179 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
5180 | { | |
d28d4731 | 5181 | intel_dp->panel_power_off_time = ktime_get_boottime(); |
dada1a9f ID |
5182 | intel_dp->last_power_on = jiffies; |
5183 | intel_dp->last_backlight_off = jiffies; | |
5184 | } | |
5185 | ||
67a54566 | 5186 | static void |
54648618 ID |
5187 | intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, |
5188 | struct intel_dp *intel_dp, struct edp_power_seq *seq) | |
67a54566 | 5189 | { |
b0a08bec | 5190 | u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0; |
8e8232d5 | 5191 | struct pps_registers regs; |
453c5420 | 5192 | |
8e8232d5 | 5193 | intel_pps_get_registers(dev_priv, intel_dp, ®s); |
67a54566 DV |
5194 | |
5195 | /* Workaround: Need to write PP_CONTROL with the unlock key as | |
5196 | * the very first thing. */ | |
b0a08bec | 5197 | pp_ctl = ironlake_get_pp_control(intel_dp); |
67a54566 | 5198 | |
8e8232d5 ID |
5199 | pp_on = I915_READ(regs.pp_on); |
5200 | pp_off = I915_READ(regs.pp_off); | |
938361e7 | 5201 | if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv)) { |
8e8232d5 ID |
5202 | I915_WRITE(regs.pp_ctrl, pp_ctl); |
5203 | pp_div = I915_READ(regs.pp_div); | |
b0a08bec | 5204 | } |
67a54566 DV |
5205 | |
5206 | /* Pull timing values out of registers */ | |
54648618 ID |
5207 | seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
5208 | PANEL_POWER_UP_DELAY_SHIFT; | |
67a54566 | 5209 | |
54648618 ID |
5210 | seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
5211 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
67a54566 | 5212 | |
54648618 ID |
5213 | seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
5214 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
67a54566 | 5215 | |
54648618 ID |
5216 | seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
5217 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
67a54566 | 5218 | |
938361e7 | 5219 | if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) { |
12c8ca9c MN |
5220 | seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> |
5221 | BXT_POWER_CYCLE_DELAY_SHIFT) * 1000; | |
b0a08bec | 5222 | } else { |
54648618 | 5223 | seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
67a54566 | 5224 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
b0a08bec | 5225 | } |
54648618 ID |
5226 | } |
5227 | ||
de9c1b6b ID |
5228 | static void |
5229 | intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) | |
5230 | { | |
5231 | DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", | |
5232 | state_name, | |
5233 | seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); | |
5234 | } | |
5235 | ||
5236 | static void | |
5237 | intel_pps_verify_state(struct drm_i915_private *dev_priv, | |
5238 | struct intel_dp *intel_dp) | |
5239 | { | |
5240 | struct edp_power_seq hw; | |
5241 | struct edp_power_seq *sw = &intel_dp->pps_delays; | |
5242 | ||
5243 | intel_pps_readout_hw_state(dev_priv, intel_dp, &hw); | |
5244 | ||
5245 | if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || | |
5246 | hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { | |
5247 | DRM_ERROR("PPS state mismatch\n"); | |
5248 | intel_pps_dump_state("sw", sw); | |
5249 | intel_pps_dump_state("hw", &hw); | |
5250 | } | |
5251 | } | |
5252 | ||
54648618 ID |
5253 | static void |
5254 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, | |
5255 | struct intel_dp *intel_dp) | |
5256 | { | |
fac5e23e | 5257 | struct drm_i915_private *dev_priv = to_i915(dev); |
54648618 ID |
5258 | struct edp_power_seq cur, vbt, spec, |
5259 | *final = &intel_dp->pps_delays; | |
5260 | ||
5261 | lockdep_assert_held(&dev_priv->pps_mutex); | |
5262 | ||
5263 | /* already initialized? */ | |
5264 | if (final->t11_t12 != 0) | |
5265 | return; | |
5266 | ||
5267 | intel_pps_readout_hw_state(dev_priv, intel_dp, &cur); | |
67a54566 | 5268 | |
de9c1b6b | 5269 | intel_pps_dump_state("cur", &cur); |
67a54566 | 5270 | |
6aa23e65 | 5271 | vbt = dev_priv->vbt.edp.pps; |
c99a259b MN |
5272 | /* On Toshiba Satellite P50-C-18C system the VBT T12 delay |
5273 | * of 500ms appears to be too short. Ocassionally the panel | |
5274 | * just fails to power back on. Increasing the delay to 800ms | |
5275 | * seems sufficient to avoid this problem. | |
5276 | */ | |
5277 | if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) { | |
5278 | vbt.t11_t12 = max_t(u16, vbt.t11_t12, 800 * 10); | |
5279 | DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n", | |
5280 | vbt.t11_t12); | |
5281 | } | |
770a17a5 MN |
5282 | /* T11_T12 delay is special and actually in units of 100ms, but zero |
5283 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
5284 | * table multiplies it with 1000 to make it in units of 100usec, | |
5285 | * too. */ | |
5286 | vbt.t11_t12 += 100 * 10; | |
67a54566 DV |
5287 | |
5288 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of | |
5289 | * our hw here, which are all in 100usec. */ | |
5290 | spec.t1_t3 = 210 * 10; | |
5291 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ | |
5292 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ | |
5293 | spec.t10 = 500 * 10; | |
5294 | /* This one is special and actually in units of 100ms, but zero | |
5295 | * based in the hw (so we need to add 100 ms). But the sw vbt | |
5296 | * table multiplies it with 1000 to make it in units of 100usec, | |
5297 | * too. */ | |
5298 | spec.t11_t12 = (510 + 100) * 10; | |
5299 | ||
de9c1b6b | 5300 | intel_pps_dump_state("vbt", &vbt); |
67a54566 DV |
5301 | |
5302 | /* Use the max of the register settings and vbt. If both are | |
5303 | * unset, fall back to the spec limits. */ | |
36b5f425 | 5304 | #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ |
67a54566 DV |
5305 | spec.field : \ |
5306 | max(cur.field, vbt.field)) | |
5307 | assign_final(t1_t3); | |
5308 | assign_final(t8); | |
5309 | assign_final(t9); | |
5310 | assign_final(t10); | |
5311 | assign_final(t11_t12); | |
5312 | #undef assign_final | |
5313 | ||
36b5f425 | 5314 | #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) |
67a54566 DV |
5315 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
5316 | intel_dp->backlight_on_delay = get_delay(t8); | |
5317 | intel_dp->backlight_off_delay = get_delay(t9); | |
5318 | intel_dp->panel_power_down_delay = get_delay(t10); | |
5319 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); | |
5320 | #undef get_delay | |
5321 | ||
f30d26e4 JN |
5322 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
5323 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, | |
5324 | intel_dp->panel_power_cycle_delay); | |
5325 | ||
5326 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", | |
5327 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); | |
de9c1b6b ID |
5328 | |
5329 | /* | |
5330 | * We override the HW backlight delays to 1 because we do manual waits | |
5331 | * on them. For T8, even BSpec recommends doing it. For T9, if we | |
5332 | * don't do this, we'll end up waiting for the backlight off delay | |
5333 | * twice: once when we do the manual sleep, and once when we disable | |
5334 | * the panel and wait for the PP_STATUS bit to become zero. | |
5335 | */ | |
5336 | final->t8 = 1; | |
5337 | final->t9 = 1; | |
f30d26e4 JN |
5338 | } |
5339 | ||
5340 | static void | |
5341 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, | |
5d5ab2d2 VS |
5342 | struct intel_dp *intel_dp, |
5343 | bool force_disable_vdd) | |
f30d26e4 | 5344 | { |
fac5e23e | 5345 | struct drm_i915_private *dev_priv = to_i915(dev); |
453c5420 | 5346 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
e7dc33f3 | 5347 | int div = dev_priv->rawclk_freq / 1000; |
8e8232d5 | 5348 | struct pps_registers regs; |
ad933b56 | 5349 | enum port port = dp_to_dig_port(intel_dp)->port; |
36b5f425 | 5350 | const struct edp_power_seq *seq = &intel_dp->pps_delays; |
453c5420 | 5351 | |
e39b999a | 5352 | lockdep_assert_held(&dev_priv->pps_mutex); |
453c5420 | 5353 | |
8e8232d5 | 5354 | intel_pps_get_registers(dev_priv, intel_dp, ®s); |
453c5420 | 5355 | |
5d5ab2d2 VS |
5356 | /* |
5357 | * On some VLV machines the BIOS can leave the VDD | |
5358 | * enabled even on power seqeuencers which aren't | |
5359 | * hooked up to any port. This would mess up the | |
5360 | * power domain tracking the first time we pick | |
5361 | * one of these power sequencers for use since | |
5362 | * edp_panel_vdd_on() would notice that the VDD was | |
5363 | * already on and therefore wouldn't grab the power | |
5364 | * domain reference. Disable VDD first to avoid this. | |
5365 | * This also avoids spuriously turning the VDD on as | |
5366 | * soon as the new power seqeuencer gets initialized. | |
5367 | */ | |
5368 | if (force_disable_vdd) { | |
5369 | u32 pp = ironlake_get_pp_control(intel_dp); | |
5370 | ||
5371 | WARN(pp & PANEL_POWER_ON, "Panel power already on\n"); | |
5372 | ||
5373 | if (pp & EDP_FORCE_VDD) | |
5374 | DRM_DEBUG_KMS("VDD already on, disabling first\n"); | |
5375 | ||
5376 | pp &= ~EDP_FORCE_VDD; | |
5377 | ||
5378 | I915_WRITE(regs.pp_ctrl, pp); | |
5379 | } | |
5380 | ||
f30d26e4 | 5381 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
de9c1b6b ID |
5382 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); |
5383 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | | |
f30d26e4 | 5384 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
67a54566 DV |
5385 | /* Compute the divisor for the pp clock, simply match the Bspec |
5386 | * formula. */ | |
938361e7 | 5387 | if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) { |
8e8232d5 | 5388 | pp_div = I915_READ(regs.pp_ctrl); |
b0a08bec | 5389 | pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; |
12c8ca9c | 5390 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
b0a08bec VK |
5391 | << BXT_POWER_CYCLE_DELAY_SHIFT); |
5392 | } else { | |
5393 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; | |
5394 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) | |
5395 | << PANEL_POWER_CYCLE_DELAY_SHIFT); | |
5396 | } | |
67a54566 DV |
5397 | |
5398 | /* Haswell doesn't have any port selection bits for the panel | |
5399 | * power sequencer any more. */ | |
920a14b2 | 5400 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
ad933b56 | 5401 | port_sel = PANEL_PORT_SELECT_VLV(port); |
6e266956 | 5402 | } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
ad933b56 | 5403 | if (port == PORT_A) |
a24c144c | 5404 | port_sel = PANEL_PORT_SELECT_DPA; |
67a54566 | 5405 | else |
a24c144c | 5406 | port_sel = PANEL_PORT_SELECT_DPD; |
67a54566 DV |
5407 | } |
5408 | ||
453c5420 JB |
5409 | pp_on |= port_sel; |
5410 | ||
8e8232d5 ID |
5411 | I915_WRITE(regs.pp_on, pp_on); |
5412 | I915_WRITE(regs.pp_off, pp_off); | |
938361e7 | 5413 | if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) |
8e8232d5 | 5414 | I915_WRITE(regs.pp_ctrl, pp_div); |
b0a08bec | 5415 | else |
8e8232d5 | 5416 | I915_WRITE(regs.pp_div, pp_div); |
67a54566 | 5417 | |
67a54566 | 5418 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
8e8232d5 ID |
5419 | I915_READ(regs.pp_on), |
5420 | I915_READ(regs.pp_off), | |
938361e7 | 5421 | (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)) ? |
8e8232d5 ID |
5422 | (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : |
5423 | I915_READ(regs.pp_div)); | |
f684960e CW |
5424 | } |
5425 | ||
335f752b ID |
5426 | static void intel_dp_pps_init(struct drm_device *dev, |
5427 | struct intel_dp *intel_dp) | |
5428 | { | |
920a14b2 TU |
5429 | struct drm_i915_private *dev_priv = to_i915(dev); |
5430 | ||
5431 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
335f752b ID |
5432 | vlv_initial_power_sequencer_setup(intel_dp); |
5433 | } else { | |
5434 | intel_dp_init_panel_power_sequencer(dev, intel_dp); | |
5d5ab2d2 | 5435 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false); |
335f752b ID |
5436 | } |
5437 | } | |
5438 | ||
b33a2815 VK |
5439 | /** |
5440 | * intel_dp_set_drrs_state - program registers for RR switch to take effect | |
5423adf1 | 5441 | * @dev_priv: i915 device |
e896402c | 5442 | * @crtc_state: a pointer to the active intel_crtc_state |
b33a2815 VK |
5443 | * @refresh_rate: RR to be programmed |
5444 | * | |
5445 | * This function gets called when refresh rate (RR) has to be changed from | |
5446 | * one frequency to another. Switches can be between high and low RR | |
5447 | * supported by the panel or to any other RR based on media playback (in | |
5448 | * this case, RR value needs to be passed from user space). | |
5449 | * | |
5450 | * The caller of this function needs to take a lock on dev_priv->drrs. | |
5451 | */ | |
85cb48a1 | 5452 | static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, |
5f88a9c6 | 5453 | const struct intel_crtc_state *crtc_state, |
85cb48a1 | 5454 | int refresh_rate) |
439d7ac0 | 5455 | { |
439d7ac0 | 5456 | struct intel_encoder *encoder; |
96178eeb VK |
5457 | struct intel_digital_port *dig_port = NULL; |
5458 | struct intel_dp *intel_dp = dev_priv->drrs.dp; | |
85cb48a1 | 5459 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
96178eeb | 5460 | enum drrs_refresh_rate_type index = DRRS_HIGH_RR; |
439d7ac0 PB |
5461 | |
5462 | if (refresh_rate <= 0) { | |
5463 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); | |
5464 | return; | |
5465 | } | |
5466 | ||
96178eeb VK |
5467 | if (intel_dp == NULL) { |
5468 | DRM_DEBUG_KMS("DRRS not supported.\n"); | |
439d7ac0 PB |
5469 | return; |
5470 | } | |
5471 | ||
1fcc9d1c | 5472 | /* |
e4d59f6b RV |
5473 | * FIXME: This needs proper synchronization with psr state for some |
5474 | * platforms that cannot have PSR and DRRS enabled at the same time. | |
1fcc9d1c | 5475 | */ |
439d7ac0 | 5476 | |
96178eeb VK |
5477 | dig_port = dp_to_dig_port(intel_dp); |
5478 | encoder = &dig_port->base; | |
723f9aab | 5479 | intel_crtc = to_intel_crtc(encoder->base.crtc); |
439d7ac0 PB |
5480 | |
5481 | if (!intel_crtc) { | |
5482 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); | |
5483 | return; | |
5484 | } | |
5485 | ||
96178eeb | 5486 | if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { |
439d7ac0 PB |
5487 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
5488 | return; | |
5489 | } | |
5490 | ||
96178eeb VK |
5491 | if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == |
5492 | refresh_rate) | |
439d7ac0 PB |
5493 | index = DRRS_LOW_RR; |
5494 | ||
96178eeb | 5495 | if (index == dev_priv->drrs.refresh_rate_type) { |
439d7ac0 PB |
5496 | DRM_DEBUG_KMS( |
5497 | "DRRS requested for previously set RR...ignoring\n"); | |
5498 | return; | |
5499 | } | |
5500 | ||
85cb48a1 | 5501 | if (!crtc_state->base.active) { |
439d7ac0 PB |
5502 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
5503 | return; | |
5504 | } | |
5505 | ||
85cb48a1 | 5506 | if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { |
a4c30b1d VK |
5507 | switch (index) { |
5508 | case DRRS_HIGH_RR: | |
5509 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
5510 | break; | |
5511 | case DRRS_LOW_RR: | |
5512 | intel_dp_set_m_n(intel_crtc, M2_N2); | |
5513 | break; | |
5514 | case DRRS_MAX_RR: | |
5515 | default: | |
5516 | DRM_ERROR("Unsupported refreshrate type\n"); | |
5517 | } | |
85cb48a1 ML |
5518 | } else if (INTEL_GEN(dev_priv) > 6) { |
5519 | i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); | |
649636ef | 5520 | u32 val; |
a4c30b1d | 5521 | |
649636ef | 5522 | val = I915_READ(reg); |
439d7ac0 | 5523 | if (index > DRRS_HIGH_RR) { |
85cb48a1 | 5524 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
5525 | val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5526 | else | |
5527 | val |= PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 | 5528 | } else { |
85cb48a1 | 5529 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6fa7aec1 VK |
5530 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; |
5531 | else | |
5532 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; | |
439d7ac0 PB |
5533 | } |
5534 | I915_WRITE(reg, val); | |
5535 | } | |
5536 | ||
4e9ac947 VK |
5537 | dev_priv->drrs.refresh_rate_type = index; |
5538 | ||
5539 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); | |
5540 | } | |
5541 | ||
b33a2815 VK |
5542 | /** |
5543 | * intel_edp_drrs_enable - init drrs struct if supported | |
5544 | * @intel_dp: DP struct | |
5423adf1 | 5545 | * @crtc_state: A pointer to the active crtc state. |
b33a2815 VK |
5546 | * |
5547 | * Initializes frontbuffer_bits and drrs.dp | |
5548 | */ | |
85cb48a1 | 5549 | void intel_edp_drrs_enable(struct intel_dp *intel_dp, |
5f88a9c6 | 5550 | const struct intel_crtc_state *crtc_state) |
c395578e VK |
5551 | { |
5552 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 5553 | struct drm_i915_private *dev_priv = to_i915(dev); |
c395578e | 5554 | |
85cb48a1 | 5555 | if (!crtc_state->has_drrs) { |
c395578e VK |
5556 | DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); |
5557 | return; | |
5558 | } | |
5559 | ||
5560 | mutex_lock(&dev_priv->drrs.mutex); | |
5561 | if (WARN_ON(dev_priv->drrs.dp)) { | |
5562 | DRM_ERROR("DRRS already enabled\n"); | |
5563 | goto unlock; | |
5564 | } | |
5565 | ||
5566 | dev_priv->drrs.busy_frontbuffer_bits = 0; | |
5567 | ||
5568 | dev_priv->drrs.dp = intel_dp; | |
5569 | ||
5570 | unlock: | |
5571 | mutex_unlock(&dev_priv->drrs.mutex); | |
5572 | } | |
5573 | ||
b33a2815 VK |
5574 | /** |
5575 | * intel_edp_drrs_disable - Disable DRRS | |
5576 | * @intel_dp: DP struct | |
5423adf1 | 5577 | * @old_crtc_state: Pointer to old crtc_state. |
b33a2815 VK |
5578 | * |
5579 | */ | |
85cb48a1 | 5580 | void intel_edp_drrs_disable(struct intel_dp *intel_dp, |
5f88a9c6 | 5581 | const struct intel_crtc_state *old_crtc_state) |
c395578e VK |
5582 | { |
5583 | struct drm_device *dev = intel_dp_to_dev(intel_dp); | |
fac5e23e | 5584 | struct drm_i915_private *dev_priv = to_i915(dev); |
c395578e | 5585 | |
85cb48a1 | 5586 | if (!old_crtc_state->has_drrs) |
c395578e VK |
5587 | return; |
5588 | ||
5589 | mutex_lock(&dev_priv->drrs.mutex); | |
5590 | if (!dev_priv->drrs.dp) { | |
5591 | mutex_unlock(&dev_priv->drrs.mutex); | |
5592 | return; | |
5593 | } | |
5594 | ||
5595 | if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) | |
85cb48a1 ML |
5596 | intel_dp_set_drrs_state(dev_priv, old_crtc_state, |
5597 | intel_dp->attached_connector->panel.fixed_mode->vrefresh); | |
c395578e VK |
5598 | |
5599 | dev_priv->drrs.dp = NULL; | |
5600 | mutex_unlock(&dev_priv->drrs.mutex); | |
5601 | ||
5602 | cancel_delayed_work_sync(&dev_priv->drrs.work); | |
5603 | } | |
5604 | ||
4e9ac947 VK |
5605 | static void intel_edp_drrs_downclock_work(struct work_struct *work) |
5606 | { | |
5607 | struct drm_i915_private *dev_priv = | |
5608 | container_of(work, typeof(*dev_priv), drrs.work.work); | |
5609 | struct intel_dp *intel_dp; | |
5610 | ||
5611 | mutex_lock(&dev_priv->drrs.mutex); | |
5612 | ||
5613 | intel_dp = dev_priv->drrs.dp; | |
5614 | ||
5615 | if (!intel_dp) | |
5616 | goto unlock; | |
5617 | ||
439d7ac0 | 5618 | /* |
4e9ac947 VK |
5619 | * The delayed work can race with an invalidate hence we need to |
5620 | * recheck. | |
439d7ac0 PB |
5621 | */ |
5622 | ||
4e9ac947 VK |
5623 | if (dev_priv->drrs.busy_frontbuffer_bits) |
5624 | goto unlock; | |
439d7ac0 | 5625 | |
85cb48a1 ML |
5626 | if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) { |
5627 | struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; | |
5628 | ||
5629 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, | |
5630 | intel_dp->attached_connector->panel.downclock_mode->vrefresh); | |
5631 | } | |
439d7ac0 | 5632 | |
4e9ac947 | 5633 | unlock: |
4e9ac947 | 5634 | mutex_unlock(&dev_priv->drrs.mutex); |
439d7ac0 PB |
5635 | } |
5636 | ||
b33a2815 | 5637 | /** |
0ddfd203 | 5638 | * intel_edp_drrs_invalidate - Disable Idleness DRRS |
5748b6a1 | 5639 | * @dev_priv: i915 device |
b33a2815 VK |
5640 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5641 | * | |
0ddfd203 R |
5642 | * This function gets called everytime rendering on the given planes start. |
5643 | * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). | |
b33a2815 VK |
5644 | * |
5645 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5646 | */ | |
5748b6a1 CW |
5647 | void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, |
5648 | unsigned int frontbuffer_bits) | |
a93fad0f | 5649 | { |
a93fad0f VK |
5650 | struct drm_crtc *crtc; |
5651 | enum pipe pipe; | |
5652 | ||
9da7d693 | 5653 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5654 | return; |
5655 | ||
88f933a8 | 5656 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5657 | |
a93fad0f | 5658 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5659 | if (!dev_priv->drrs.dp) { |
5660 | mutex_unlock(&dev_priv->drrs.mutex); | |
5661 | return; | |
5662 | } | |
5663 | ||
a93fad0f VK |
5664 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5665 | pipe = to_intel_crtc(crtc)->pipe; | |
5666 | ||
c1d038c6 DV |
5667 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); |
5668 | dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; | |
5669 | ||
0ddfd203 | 5670 | /* invalidate means busy screen hence upclock */ |
c1d038c6 | 5671 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 ML |
5672 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
5673 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); | |
a93fad0f | 5674 | |
a93fad0f VK |
5675 | mutex_unlock(&dev_priv->drrs.mutex); |
5676 | } | |
5677 | ||
b33a2815 | 5678 | /** |
0ddfd203 | 5679 | * intel_edp_drrs_flush - Restart Idleness DRRS |
5748b6a1 | 5680 | * @dev_priv: i915 device |
b33a2815 VK |
5681 | * @frontbuffer_bits: frontbuffer plane tracking bits |
5682 | * | |
0ddfd203 R |
5683 | * This function gets called every time rendering on the given planes has |
5684 | * completed or flip on a crtc is completed. So DRRS should be upclocked | |
5685 | * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, | |
5686 | * if no other planes are dirty. | |
b33a2815 VK |
5687 | * |
5688 | * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. | |
5689 | */ | |
5748b6a1 CW |
5690 | void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, |
5691 | unsigned int frontbuffer_bits) | |
a93fad0f | 5692 | { |
a93fad0f VK |
5693 | struct drm_crtc *crtc; |
5694 | enum pipe pipe; | |
5695 | ||
9da7d693 | 5696 | if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) |
a93fad0f VK |
5697 | return; |
5698 | ||
88f933a8 | 5699 | cancel_delayed_work(&dev_priv->drrs.work); |
3954e733 | 5700 | |
a93fad0f | 5701 | mutex_lock(&dev_priv->drrs.mutex); |
9da7d693 DV |
5702 | if (!dev_priv->drrs.dp) { |
5703 | mutex_unlock(&dev_priv->drrs.mutex); | |
5704 | return; | |
5705 | } | |
5706 | ||
a93fad0f VK |
5707 | crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; |
5708 | pipe = to_intel_crtc(crtc)->pipe; | |
c1d038c6 DV |
5709 | |
5710 | frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); | |
a93fad0f VK |
5711 | dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; |
5712 | ||
0ddfd203 | 5713 | /* flush means busy screen hence upclock */ |
c1d038c6 | 5714 | if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) |
85cb48a1 ML |
5715 | intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, |
5716 | dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); | |
0ddfd203 R |
5717 | |
5718 | /* | |
5719 | * flush also means no more activity hence schedule downclock, if all | |
5720 | * other fbs are quiescent too | |
5721 | */ | |
5722 | if (!dev_priv->drrs.busy_frontbuffer_bits) | |
a93fad0f VK |
5723 | schedule_delayed_work(&dev_priv->drrs.work, |
5724 | msecs_to_jiffies(1000)); | |
5725 | mutex_unlock(&dev_priv->drrs.mutex); | |
5726 | } | |
5727 | ||
b33a2815 VK |
5728 | /** |
5729 | * DOC: Display Refresh Rate Switching (DRRS) | |
5730 | * | |
5731 | * Display Refresh Rate Switching (DRRS) is a power conservation feature | |
5732 | * which enables swtching between low and high refresh rates, | |
5733 | * dynamically, based on the usage scenario. This feature is applicable | |
5734 | * for internal panels. | |
5735 | * | |
5736 | * Indication that the panel supports DRRS is given by the panel EDID, which | |
5737 | * would list multiple refresh rates for one resolution. | |
5738 | * | |
5739 | * DRRS is of 2 types - static and seamless. | |
5740 | * Static DRRS involves changing refresh rate (RR) by doing a full modeset | |
5741 | * (may appear as a blink on screen) and is used in dock-undock scenario. | |
5742 | * Seamless DRRS involves changing RR without any visual effect to the user | |
5743 | * and can be used during normal system usage. This is done by programming | |
5744 | * certain registers. | |
5745 | * | |
5746 | * Support for static/seamless DRRS may be indicated in the VBT based on | |
5747 | * inputs from the panel spec. | |
5748 | * | |
5749 | * DRRS saves power by switching to low RR based on usage scenarios. | |
5750 | * | |
2e7a5701 DV |
5751 | * The implementation is based on frontbuffer tracking implementation. When |
5752 | * there is a disturbance on the screen triggered by user activity or a periodic | |
5753 | * system activity, DRRS is disabled (RR is changed to high RR). When there is | |
5754 | * no movement on screen, after a timeout of 1 second, a switch to low RR is | |
5755 | * made. | |
5756 | * | |
5757 | * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() | |
5758 | * and intel_edp_drrs_flush() are called. | |
b33a2815 VK |
5759 | * |
5760 | * DRRS can be further extended to support other internal panels and also | |
5761 | * the scenario of video playback wherein RR is set based on the rate | |
5762 | * requested by userspace. | |
5763 | */ | |
5764 | ||
5765 | /** | |
5766 | * intel_dp_drrs_init - Init basic DRRS work and mutex. | |
5767 | * @intel_connector: eDP connector | |
5768 | * @fixed_mode: preferred mode of panel | |
5769 | * | |
5770 | * This function is called only once at driver load to initialize basic | |
5771 | * DRRS stuff. | |
5772 | * | |
5773 | * Returns: | |
5774 | * Downclock mode if panel supports it, else return NULL. | |
5775 | * DRRS support is determined by the presence of downclock mode (apart | |
5776 | * from VBT setting). | |
5777 | */ | |
4f9db5b5 | 5778 | static struct drm_display_mode * |
96178eeb VK |
5779 | intel_dp_drrs_init(struct intel_connector *intel_connector, |
5780 | struct drm_display_mode *fixed_mode) | |
4f9db5b5 PB |
5781 | { |
5782 | struct drm_connector *connector = &intel_connector->base; | |
96178eeb | 5783 | struct drm_device *dev = connector->dev; |
fac5e23e | 5784 | struct drm_i915_private *dev_priv = to_i915(dev); |
4f9db5b5 PB |
5785 | struct drm_display_mode *downclock_mode = NULL; |
5786 | ||
9da7d693 DV |
5787 | INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); |
5788 | mutex_init(&dev_priv->drrs.mutex); | |
5789 | ||
dd11bc10 | 5790 | if (INTEL_GEN(dev_priv) <= 6) { |
4f9db5b5 PB |
5791 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
5792 | return NULL; | |
5793 | } | |
5794 | ||
5795 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { | |
4079b8d1 | 5796 | DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); |
4f9db5b5 PB |
5797 | return NULL; |
5798 | } | |
5799 | ||
5800 | downclock_mode = intel_find_panel_downclock | |
a318b4c4 | 5801 | (dev_priv, fixed_mode, connector); |
4f9db5b5 PB |
5802 | |
5803 | if (!downclock_mode) { | |
a1d26342 | 5804 | DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); |
4f9db5b5 PB |
5805 | return NULL; |
5806 | } | |
5807 | ||
96178eeb | 5808 | dev_priv->drrs.type = dev_priv->vbt.drrs_type; |
4f9db5b5 | 5809 | |
96178eeb | 5810 | dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; |
4079b8d1 | 5811 | DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); |
4f9db5b5 PB |
5812 | return downclock_mode; |
5813 | } | |
5814 | ||
ed92f0b2 | 5815 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
36b5f425 | 5816 | struct intel_connector *intel_connector) |
ed92f0b2 PZ |
5817 | { |
5818 | struct drm_connector *connector = &intel_connector->base; | |
5819 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | |
63635217 PZ |
5820 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
5821 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 5822 | struct drm_i915_private *dev_priv = to_i915(dev); |
ed92f0b2 | 5823 | struct drm_display_mode *fixed_mode = NULL; |
dc911f5b | 5824 | struct drm_display_mode *alt_fixed_mode = NULL; |
4f9db5b5 | 5825 | struct drm_display_mode *downclock_mode = NULL; |
ed92f0b2 PZ |
5826 | bool has_dpcd; |
5827 | struct drm_display_mode *scan; | |
5828 | struct edid *edid; | |
6517d273 | 5829 | enum pipe pipe = INVALID_PIPE; |
ed92f0b2 | 5830 | |
1853a9da | 5831 | if (!intel_dp_is_edp(intel_dp)) |
ed92f0b2 PZ |
5832 | return true; |
5833 | ||
97a824e1 ID |
5834 | /* |
5835 | * On IBX/CPT we may get here with LVDS already registered. Since the | |
5836 | * driver uses the only internal power sequencer available for both | |
5837 | * eDP and LVDS bail out early in this case to prevent interfering | |
5838 | * with an already powered-on LVDS power sequencer. | |
5839 | */ | |
5840 | if (intel_get_lvds_encoder(dev)) { | |
5841 | WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); | |
5842 | DRM_INFO("LVDS was detected, not registering eDP\n"); | |
5843 | ||
5844 | return false; | |
5845 | } | |
5846 | ||
49e6bc51 | 5847 | pps_lock(intel_dp); |
b4d06ede ID |
5848 | |
5849 | intel_dp_init_panel_power_timestamps(intel_dp); | |
335f752b | 5850 | intel_dp_pps_init(dev, intel_dp); |
49e6bc51 | 5851 | intel_edp_panel_vdd_sanitize(intel_dp); |
b4d06ede | 5852 | |
49e6bc51 | 5853 | pps_unlock(intel_dp); |
63635217 | 5854 | |
ed92f0b2 | 5855 | /* Cache DPCD and EDID for edp. */ |
fe5a66f9 | 5856 | has_dpcd = intel_edp_init_dpcd(intel_dp); |
ed92f0b2 | 5857 | |
fe5a66f9 | 5858 | if (!has_dpcd) { |
ed92f0b2 PZ |
5859 | /* if this fails, presume the device is a ghost */ |
5860 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); | |
b4d06ede | 5861 | goto out_vdd_off; |
ed92f0b2 PZ |
5862 | } |
5863 | ||
060c8778 | 5864 | mutex_lock(&dev->mode_config.mutex); |
0b99836f | 5865 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
ed92f0b2 PZ |
5866 | if (edid) { |
5867 | if (drm_add_edid_modes(connector, edid)) { | |
5868 | drm_mode_connector_update_edid_property(connector, | |
5869 | edid); | |
5870 | drm_edid_to_eld(connector, edid); | |
5871 | } else { | |
5872 | kfree(edid); | |
5873 | edid = ERR_PTR(-EINVAL); | |
5874 | } | |
5875 | } else { | |
5876 | edid = ERR_PTR(-ENOENT); | |
5877 | } | |
5878 | intel_connector->edid = edid; | |
5879 | ||
dc911f5b | 5880 | /* prefer fixed mode from EDID if available, save an alt mode also */ |
ed92f0b2 PZ |
5881 | list_for_each_entry(scan, &connector->probed_modes, head) { |
5882 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { | |
5883 | fixed_mode = drm_mode_duplicate(dev, scan); | |
4f9db5b5 | 5884 | downclock_mode = intel_dp_drrs_init( |
4f9db5b5 | 5885 | intel_connector, fixed_mode); |
dc911f5b JB |
5886 | } else if (!alt_fixed_mode) { |
5887 | alt_fixed_mode = drm_mode_duplicate(dev, scan); | |
ed92f0b2 PZ |
5888 | } |
5889 | } | |
5890 | ||
5891 | /* fallback to VBT if available for eDP */ | |
5892 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { | |
5893 | fixed_mode = drm_mode_duplicate(dev, | |
5894 | dev_priv->vbt.lfp_lvds_vbt_mode); | |
df457245 | 5895 | if (fixed_mode) { |
ed92f0b2 | 5896 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
df457245 VS |
5897 | connector->display_info.width_mm = fixed_mode->width_mm; |
5898 | connector->display_info.height_mm = fixed_mode->height_mm; | |
5899 | } | |
ed92f0b2 | 5900 | } |
060c8778 | 5901 | mutex_unlock(&dev->mode_config.mutex); |
ed92f0b2 | 5902 | |
920a14b2 | 5903 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
01527b31 CT |
5904 | intel_dp->edp_notifier.notifier_call = edp_notify_handler; |
5905 | register_reboot_notifier(&intel_dp->edp_notifier); | |
6517d273 VS |
5906 | |
5907 | /* | |
5908 | * Figure out the current pipe for the initial backlight setup. | |
5909 | * If the current pipe isn't valid, try the PPS pipe, and if that | |
5910 | * fails just assume pipe A. | |
5911 | */ | |
9f2bdb00 | 5912 | pipe = vlv_active_pipe(intel_dp); |
6517d273 VS |
5913 | |
5914 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5915 | pipe = intel_dp->pps_pipe; | |
5916 | ||
5917 | if (pipe != PIPE_A && pipe != PIPE_B) | |
5918 | pipe = PIPE_A; | |
5919 | ||
5920 | DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", | |
5921 | pipe_name(pipe)); | |
01527b31 CT |
5922 | } |
5923 | ||
dc911f5b JB |
5924 | intel_panel_init(&intel_connector->panel, fixed_mode, alt_fixed_mode, |
5925 | downclock_mode); | |
5507faeb | 5926 | intel_connector->panel.backlight.power = intel_edp_backlight_power; |
6517d273 | 5927 | intel_panel_setup_backlight(connector, pipe); |
ed92f0b2 PZ |
5928 | |
5929 | return true; | |
b4d06ede ID |
5930 | |
5931 | out_vdd_off: | |
5932 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); | |
5933 | /* | |
5934 | * vdd might still be enabled do to the delayed vdd off. | |
5935 | * Make sure vdd is actually turned off here. | |
5936 | */ | |
5937 | pps_lock(intel_dp); | |
5938 | edp_panel_vdd_off_sync(intel_dp); | |
5939 | pps_unlock(intel_dp); | |
5940 | ||
5941 | return false; | |
ed92f0b2 PZ |
5942 | } |
5943 | ||
5432fcaf | 5944 | /* Set up the hotplug pin and aux power domain. */ |
b71953a1 ACO |
5945 | static void |
5946 | intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port) | |
5947 | { | |
5948 | struct intel_encoder *encoder = &intel_dig_port->base; | |
5432fcaf | 5949 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
b71953a1 | 5950 | |
f761bef2 RV |
5951 | encoder->hpd_pin = intel_hpd_pin(intel_dig_port->port); |
5952 | ||
b71953a1 ACO |
5953 | switch (intel_dig_port->port) { |
5954 | case PORT_A: | |
5432fcaf | 5955 | intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A; |
b71953a1 ACO |
5956 | break; |
5957 | case PORT_B: | |
5432fcaf | 5958 | intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B; |
b71953a1 ACO |
5959 | break; |
5960 | case PORT_C: | |
5432fcaf | 5961 | intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C; |
b71953a1 ACO |
5962 | break; |
5963 | case PORT_D: | |
5432fcaf | 5964 | intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D; |
b71953a1 ACO |
5965 | break; |
5966 | case PORT_E: | |
5432fcaf ACO |
5967 | /* FIXME: Check VBT for actual wiring of PORT E */ |
5968 | intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D; | |
b71953a1 ACO |
5969 | break; |
5970 | default: | |
5971 | MISSING_CASE(intel_dig_port->port); | |
5972 | } | |
5973 | } | |
5974 | ||
9301397a MN |
5975 | static void intel_dp_modeset_retry_work_fn(struct work_struct *work) |
5976 | { | |
5977 | struct intel_connector *intel_connector; | |
5978 | struct drm_connector *connector; | |
5979 | ||
5980 | intel_connector = container_of(work, typeof(*intel_connector), | |
5981 | modeset_retry_work); | |
5982 | connector = &intel_connector->base; | |
5983 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, | |
5984 | connector->name); | |
5985 | ||
5986 | /* Grab the locks before changing connector property*/ | |
5987 | mutex_lock(&connector->dev->mode_config.mutex); | |
5988 | /* Set connector link status to BAD and send a Uevent to notify | |
5989 | * userspace to do a modeset. | |
5990 | */ | |
5991 | drm_mode_connector_set_link_status_property(connector, | |
5992 | DRM_MODE_LINK_STATUS_BAD); | |
5993 | mutex_unlock(&connector->dev->mode_config.mutex); | |
5994 | /* Send Hotplug uevent so userspace can reprobe */ | |
5995 | drm_kms_helper_hotplug_event(connector->dev); | |
5996 | } | |
5997 | ||
16c25533 | 5998 | bool |
f0fec3f2 PZ |
5999 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
6000 | struct intel_connector *intel_connector) | |
a4fc5ed6 | 6001 | { |
f0fec3f2 PZ |
6002 | struct drm_connector *connector = &intel_connector->base; |
6003 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
6004 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
6005 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 6006 | struct drm_i915_private *dev_priv = to_i915(dev); |
174edf1f | 6007 | enum port port = intel_dig_port->port; |
7a418e34 | 6008 | int type; |
a4fc5ed6 | 6009 | |
9301397a MN |
6010 | /* Initialize the work for modeset in case of link train failure */ |
6011 | INIT_WORK(&intel_connector->modeset_retry_work, | |
6012 | intel_dp_modeset_retry_work_fn); | |
6013 | ||
ccb1a831 VS |
6014 | if (WARN(intel_dig_port->max_lanes < 1, |
6015 | "Not enough lanes (%d) for DP on port %c\n", | |
6016 | intel_dig_port->max_lanes, port_name(port))) | |
6017 | return false; | |
6018 | ||
55cfc580 JN |
6019 | intel_dp_set_source_rates(intel_dp); |
6020 | ||
d7e8ef02 | 6021 | intel_dp->reset_link_params = true; |
a4a5d2f8 | 6022 | intel_dp->pps_pipe = INVALID_PIPE; |
9f2bdb00 | 6023 | intel_dp->active_pipe = INVALID_PIPE; |
a4a5d2f8 | 6024 | |
ec5b01dd | 6025 | /* intel_dp vfuncs */ |
dd11bc10 | 6026 | if (INTEL_GEN(dev_priv) >= 9) |
b6b5e383 | 6027 | intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; |
8652744b | 6028 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ec5b01dd | 6029 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
6e266956 | 6030 | else if (HAS_PCH_SPLIT(dev_priv)) |
ec5b01dd DL |
6031 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
6032 | else | |
6ffb1be7 | 6033 | intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; |
ec5b01dd | 6034 | |
dd11bc10 | 6035 | if (INTEL_GEN(dev_priv) >= 9) |
b9ca5fad DL |
6036 | intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; |
6037 | else | |
6ffb1be7 | 6038 | intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; |
153b1100 | 6039 | |
4f8036a2 | 6040 | if (HAS_DDI(dev_priv)) |
ad64217b ACO |
6041 | intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain; |
6042 | ||
0767935e DV |
6043 | /* Preserve the current hw state. */ |
6044 | intel_dp->DP = I915_READ(intel_dp->output_reg); | |
dd06f90e | 6045 | intel_dp->attached_connector = intel_connector; |
3d3dc149 | 6046 | |
7b91bf7f | 6047 | if (intel_dp_is_port_edp(dev_priv, port)) |
b329530c | 6048 | type = DRM_MODE_CONNECTOR_eDP; |
3b32a35b VS |
6049 | else |
6050 | type = DRM_MODE_CONNECTOR_DisplayPort; | |
b329530c | 6051 | |
9f2bdb00 VS |
6052 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6053 | intel_dp->active_pipe = vlv_active_pipe(intel_dp); | |
6054 | ||
f7d24902 ID |
6055 | /* |
6056 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but | |
6057 | * for DP the encoder type can be set by the caller to | |
6058 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. | |
6059 | */ | |
6060 | if (type == DRM_MODE_CONNECTOR_eDP) | |
6061 | intel_encoder->type = INTEL_OUTPUT_EDP; | |
6062 | ||
c17ed5b5 | 6063 | /* eDP only on port B and/or C on vlv/chv */ |
920a14b2 | 6064 | if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
1853a9da JN |
6065 | intel_dp_is_edp(intel_dp) && |
6066 | port != PORT_B && port != PORT_C)) | |
c17ed5b5 VS |
6067 | return false; |
6068 | ||
e7281eab ID |
6069 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
6070 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", | |
6071 | port_name(port)); | |
6072 | ||
b329530c | 6073 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
a4fc5ed6 KP |
6074 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
6075 | ||
a4fc5ed6 KP |
6076 | connector->interlace_allowed = true; |
6077 | connector->doublescan_allowed = 0; | |
6078 | ||
5432fcaf ACO |
6079 | intel_dp_init_connector_port_info(intel_dig_port); |
6080 | ||
b6339585 | 6081 | intel_dp_aux_init(intel_dp); |
7a418e34 | 6082 | |
f0fec3f2 | 6083 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
4be73780 | 6084 | edp_panel_vdd_work); |
a4fc5ed6 | 6085 | |
df0e9248 | 6086 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
a4fc5ed6 | 6087 | |
4f8036a2 | 6088 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
6089 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
6090 | else | |
6091 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
6092 | ||
0e32b39c | 6093 | /* init MST on ports that can support it */ |
1853a9da | 6094 | if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) && |
0c9b3715 JN |
6095 | (port == PORT_B || port == PORT_C || port == PORT_D)) |
6096 | intel_dp_mst_encoder_init(intel_dig_port, | |
6097 | intel_connector->base.base.id); | |
0e32b39c | 6098 | |
36b5f425 | 6099 | if (!intel_edp_init_connector(intel_dp, intel_connector)) { |
a121f4e5 VS |
6100 | intel_dp_aux_fini(intel_dp); |
6101 | intel_dp_mst_encoder_cleanup(intel_dig_port); | |
6102 | goto fail; | |
b2f246a8 | 6103 | } |
32f9d658 | 6104 | |
f684960e CW |
6105 | intel_dp_add_properties(intel_dp, connector); |
6106 | ||
a4fc5ed6 KP |
6107 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
6108 | * 0xd. Failure to do so will result in spurious interrupts being | |
6109 | * generated on the port when a cable is not attached. | |
6110 | */ | |
50a0bc90 | 6111 | if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) { |
a4fc5ed6 KP |
6112 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
6113 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
6114 | } | |
16c25533 PZ |
6115 | |
6116 | return true; | |
a121f4e5 VS |
6117 | |
6118 | fail: | |
a121f4e5 VS |
6119 | drm_connector_cleanup(connector); |
6120 | ||
6121 | return false; | |
a4fc5ed6 | 6122 | } |
f0fec3f2 | 6123 | |
c39055b0 | 6124 | bool intel_dp_init(struct drm_i915_private *dev_priv, |
457c52d8 CW |
6125 | i915_reg_t output_reg, |
6126 | enum port port) | |
f0fec3f2 PZ |
6127 | { |
6128 | struct intel_digital_port *intel_dig_port; | |
6129 | struct intel_encoder *intel_encoder; | |
6130 | struct drm_encoder *encoder; | |
6131 | struct intel_connector *intel_connector; | |
6132 | ||
b14c5679 | 6133 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
f0fec3f2 | 6134 | if (!intel_dig_port) |
457c52d8 | 6135 | return false; |
f0fec3f2 | 6136 | |
08d9bc92 | 6137 | intel_connector = intel_connector_alloc(); |
11aee0f6 SM |
6138 | if (!intel_connector) |
6139 | goto err_connector_alloc; | |
f0fec3f2 PZ |
6140 | |
6141 | intel_encoder = &intel_dig_port->base; | |
6142 | encoder = &intel_encoder->base; | |
6143 | ||
c39055b0 ACO |
6144 | if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
6145 | &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS, | |
6146 | "DP %c", port_name(port))) | |
893da0c9 | 6147 | goto err_encoder_init; |
f0fec3f2 | 6148 | |
5bfe2ac0 | 6149 | intel_encoder->compute_config = intel_dp_compute_config; |
00c09d70 | 6150 | intel_encoder->disable = intel_disable_dp; |
00c09d70 | 6151 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
045ac3b5 | 6152 | intel_encoder->get_config = intel_dp_get_config; |
07f9cd0b | 6153 | intel_encoder->suspend = intel_dp_encoder_suspend; |
920a14b2 | 6154 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 6155 | intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; |
e4a1d846 CML |
6156 | intel_encoder->pre_enable = chv_pre_enable_dp; |
6157 | intel_encoder->enable = vlv_enable_dp; | |
580d3811 | 6158 | intel_encoder->post_disable = chv_post_disable_dp; |
d6db995f | 6159 | intel_encoder->post_pll_disable = chv_dp_post_pll_disable; |
11a914c2 | 6160 | } else if (IS_VALLEYVIEW(dev_priv)) { |
ecff4f3b | 6161 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
ab1f90f9 JN |
6162 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
6163 | intel_encoder->enable = vlv_enable_dp; | |
49277c31 | 6164 | intel_encoder->post_disable = vlv_post_disable_dp; |
ab1f90f9 | 6165 | } else { |
ecff4f3b JN |
6166 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
6167 | intel_encoder->enable = g4x_enable_dp; | |
dd11bc10 | 6168 | if (INTEL_GEN(dev_priv) >= 5) |
08aff3fe | 6169 | intel_encoder->post_disable = ilk_post_disable_dp; |
ab1f90f9 | 6170 | } |
f0fec3f2 | 6171 | |
174edf1f | 6172 | intel_dig_port->port = port; |
f0fec3f2 | 6173 | intel_dig_port->dp.output_reg = output_reg; |
ccb1a831 | 6174 | intel_dig_port->max_lanes = 4; |
f0fec3f2 | 6175 | |
cca0502b | 6176 | intel_encoder->type = INTEL_OUTPUT_DP; |
79f255a0 | 6177 | intel_encoder->power_domain = intel_port_to_power_domain(port); |
920a14b2 | 6178 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 VS |
6179 | if (port == PORT_D) |
6180 | intel_encoder->crtc_mask = 1 << 2; | |
6181 | else | |
6182 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
6183 | } else { | |
6184 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
6185 | } | |
bc079e8b | 6186 | intel_encoder->cloneable = 0; |
03cdc1d4 | 6187 | intel_encoder->port = port; |
f0fec3f2 | 6188 | |
13cf5504 | 6189 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
5fcece80 | 6190 | dev_priv->hotplug.irq_port[port] = intel_dig_port; |
13cf5504 | 6191 | |
385e4de0 VS |
6192 | if (port != PORT_A) |
6193 | intel_infoframe_init(intel_dig_port); | |
6194 | ||
11aee0f6 SM |
6195 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) |
6196 | goto err_init_connector; | |
6197 | ||
457c52d8 | 6198 | return true; |
11aee0f6 SM |
6199 | |
6200 | err_init_connector: | |
6201 | drm_encoder_cleanup(encoder); | |
893da0c9 | 6202 | err_encoder_init: |
11aee0f6 SM |
6203 | kfree(intel_connector); |
6204 | err_connector_alloc: | |
6205 | kfree(intel_dig_port); | |
457c52d8 | 6206 | return false; |
f0fec3f2 | 6207 | } |
0e32b39c DA |
6208 | |
6209 | void intel_dp_mst_suspend(struct drm_device *dev) | |
6210 | { | |
fac5e23e | 6211 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e32b39c DA |
6212 | int i; |
6213 | ||
6214 | /* disable MST */ | |
6215 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 6216 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
5aa56969 VS |
6217 | |
6218 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) | |
0e32b39c DA |
6219 | continue; |
6220 | ||
5aa56969 VS |
6221 | if (intel_dig_port->dp.is_mst) |
6222 | drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr); | |
0e32b39c DA |
6223 | } |
6224 | } | |
6225 | ||
6226 | void intel_dp_mst_resume(struct drm_device *dev) | |
6227 | { | |
fac5e23e | 6228 | struct drm_i915_private *dev_priv = to_i915(dev); |
0e32b39c DA |
6229 | int i; |
6230 | ||
6231 | for (i = 0; i < I915_MAX_PORTS; i++) { | |
5fcece80 | 6232 | struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i]; |
5aa56969 | 6233 | int ret; |
0e32b39c | 6234 | |
5aa56969 VS |
6235 | if (!intel_dig_port || !intel_dig_port->dp.can_mst) |
6236 | continue; | |
0e32b39c | 6237 | |
5aa56969 VS |
6238 | ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr); |
6239 | if (ret) | |
6240 | intel_dp_check_mst_status(&intel_dig_port->dp); | |
0e32b39c DA |
6241 | } |
6242 | } |