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drm/i915: Fix SRC_COPY width on 830/845g
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 114static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
293static enum pipe
294vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
298 struct drm_device *dev = intel_dig_port->base.base.dev;
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 enum port port = intel_dig_port->port;
301 enum pipe pipe;
302
303 /* modeset should have pipe */
304 if (crtc)
305 return to_intel_crtc(crtc)->pipe;
306
307 /* init time, try to find a pipe with this port selected */
308 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
309 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
310 PANEL_PORT_SELECT_MASK;
311 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
312 return pipe;
313 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
314 return pipe;
315 }
316
317 /* shrug */
318 return PIPE_A;
319}
320
321static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
322{
323 struct drm_device *dev = intel_dp_to_dev(intel_dp);
324
325 if (HAS_PCH_SPLIT(dev))
326 return PCH_PP_CONTROL;
327 else
328 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
329}
330
331static u32 _pp_stat_reg(struct intel_dp *intel_dp)
332{
333 struct drm_device *dev = intel_dp_to_dev(intel_dp);
334
335 if (HAS_PCH_SPLIT(dev))
336 return PCH_PP_STATUS;
337 else
338 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
339}
340
01527b31
CT		 341/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
342 This function only applicable when panel PM state is not to be tracked */
343static int edp_notify_handler(struct notifier_block *this, unsigned long code,
344 void *unused)
345{
346 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
347 edp_notifier);
348 struct drm_device *dev = intel_dp_to_dev(intel_dp);
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 u32 pp_div;
351 u32 pp_ctrl_reg, pp_div_reg;
352 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
353
354 if (!is_edp(intel_dp) || code != SYS_RESTART)
355 return 0;
356
357 if (IS_VALLEYVIEW(dev)) {
358 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
359 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
360 pp_div = I915_READ(pp_div_reg);
361 pp_div &= PP_REFERENCE_DIVIDER_MASK;
362
363 /* 0x1F write to PP_DIV_REG sets max cycle delay */
364 I915_WRITE(pp_div_reg, pp_div | 0x1F);
365 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
366 msleep(intel_dp->panel_power_cycle_delay);
367 }
368
369 return 0;
370}
371
4be73780 372static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 373{
30add22d 374 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 375 struct drm_i915_private *dev_priv = dev->dev_private;
376
bf13e81b 377 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 378}
379
4be73780 380static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 381{
30add22d 382 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 383 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 384 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
385 struct intel_encoder *intel_encoder = &intel_dig_port->base;
386 enum intel_display_power_domain power_domain;
ebf33b18 387
bb4932c4
ID		 388 power_domain = intel_display_port_power_domain(intel_encoder);
389 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 390 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 391}
392
9b984dae
KP		 393static void
394intel_dp_check_edp(struct intel_dp *intel_dp)
395{
30add22d 396 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 397 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 398
9b984dae
KP		 399 if (!is_edp(intel_dp))
400 return;
453c5420 401
4be73780 402 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 403 WARN(1, "eDP powered off while attempting aux channel communication.\n");
404 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 405 I915_READ(_pp_stat_reg(intel_dp)),
406 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 407 }
408}
409
9ee32fea
DV		 410static uint32_t
411intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
412{
413 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
414 struct drm_device *dev = intel_dig_port->base.base.dev;
415 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 416 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 417 uint32_t status;
418 bool done;
419
ef04f00d 420#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 421 if (has_aux_irq)
b18ac466 422 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 423 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 424 else
425 done = wait_for_atomic(C, 10) == 0;
426 if (!done)
427 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
428 has_aux_irq);
429#undef C
430
431 return status;
432}
433
ec5b01dd 434static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 435{
174edf1f
PZ		 436 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
437 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 438
ec5b01dd
DL		 439 /*
440 * The clock divider is based off the hrawclk, and would like to run at
441 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 442 */
ec5b01dd
DL		 443 return index ? 0 : intel_hrawclk(dev) / 2;
444}
445
446static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
447{
448 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
449 struct drm_device *dev = intel_dig_port->base.base.dev;
450
451 if (index)
452 return 0;
453
454 if (intel_dig_port->port == PORT_A) {
455 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 456 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 457 else
b84a1cf8 458 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 459 } else {
460 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
461 }
462}
463
464static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
465{
466 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
467 struct drm_device *dev = intel_dig_port->base.base.dev;
468 struct drm_i915_private *dev_priv = dev->dev_private;
469
470 if (intel_dig_port->port == PORT_A) {
471 if (index)
472 return 0;
473 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 474 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
475 /* Workaround for non-ULT HSW */
bc86625a
CW		 476 switch (index) {
477 case 0: return 63;
478 case 1: return 72;
479 default: return 0;
480 }
ec5b01dd 481 } else {
bc86625a 482 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 483 }
b84a1cf8
RV		 484}
485
ec5b01dd
DL		 486static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
487{
488 return index ? 0 : 100;
489}
490
5ed12a19
DL		 491static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
492 bool has_aux_irq,
493 int send_bytes,
494 uint32_t aux_clock_divider)
495{
496 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
497 struct drm_device *dev = intel_dig_port->base.base.dev;
498 uint32_t precharge, timeout;
499
500 if (IS_GEN6(dev))
501 precharge = 3;
502 else
503 precharge = 5;
504
505 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
506 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
507 else
508 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
509
510 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 511 DP_AUX_CH_CTL_DONE |
5ed12a19 512 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 513 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 514 timeout |
788d4433 515 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 516 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
517 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 518 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 519}
520
b84a1cf8
RV		 521static int
522intel_dp_aux_ch(struct intel_dp *intel_dp,
523 uint8_t *send, int send_bytes,
524 uint8_t *recv, int recv_size)
525{
526 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
527 struct drm_device *dev = intel_dig_port->base.base.dev;
528 struct drm_i915_private *dev_priv = dev->dev_private;
529 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
530 uint32_t ch_data = ch_ctl + 4;
bc86625a 531 uint32_t aux_clock_divider;
b84a1cf8
RV		 532 int i, ret, recv_bytes;
533 uint32_t status;
5ed12a19 534 int try, clock = 0;
4e6b788c 535 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 536 bool vdd;
537
538 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 539
540 /* dp aux is extremely sensitive to irq latency, hence request the
541 * lowest possible wakeup latency and so prevent the cpu from going into
542 * deep sleep states.
543 */
544 pm_qos_update_request(&dev_priv->pm_qos, 0);
545
546 intel_dp_check_edp(intel_dp);
5eb08b69 547
c67a470b
PZ		 548 intel_aux_display_runtime_get(dev_priv);
549
11bee43e
JB		 550 /* Try to wait for any previous AUX channel activity */
551 for (try = 0; try < 3; try++) {
ef04f00d 552 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 553 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
554 break;
555 msleep(1);
556 }
557
558 if (try == 3) {
559 WARN(1, "dp_aux_ch not started status 0x%08x\n",
560 I915_READ(ch_ctl));
9ee32fea
DV		 561 ret = -EBUSY;
562 goto out;
4f7f7b7e
CW		 563 }
564
46a5ae9f
PZ		 565 /* Only 5 data registers! */
566 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
567 ret = -E2BIG;
568 goto out;
569 }
570
ec5b01dd 571 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 572 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
573 has_aux_irq,
574 send_bytes,
575 aux_clock_divider);
5ed12a19 576
bc86625a
CW		 577 /* Must try at least 3 times according to DP spec */
578 for (try = 0; try < 5; try++) {
579 /* Load the send data into the aux channel data registers */
580 for (i = 0; i < send_bytes; i += 4)
581 I915_WRITE(ch_data + i,
582 pack_aux(send + i, send_bytes - i));
583
584 /* Send the command and wait for it to complete */
5ed12a19 585 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 586
587 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
588
589 /* Clear done status and any errors */
590 I915_WRITE(ch_ctl,
591 status |
592 DP_AUX_CH_CTL_DONE |
593 DP_AUX_CH_CTL_TIME_OUT_ERROR |
594 DP_AUX_CH_CTL_RECEIVE_ERROR);
595
596 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
597 DP_AUX_CH_CTL_RECEIVE_ERROR))
598 continue;
599 if (status & DP_AUX_CH_CTL_DONE)
600 break;
601 }
4f7f7b7e 602 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 603 break;
604 }
605
a4fc5ed6 606 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 607 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 608 ret = -EBUSY;
609 goto out;
a4fc5ed6
KP		 610 }
611
612 /* Check for timeout or receive error.
613 * Timeouts occur when the sink is not connected
614 */
a5b3da54 615 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 616 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 617 ret = -EIO;
618 goto out;
a5b3da54 619 }
1ae8c0a5
KP		 620
621 /* Timeouts occur when the device isn't connected, so they're
622 * "normal" -- don't fill the kernel log with these */
a5b3da54 623 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 624 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 625 ret = -ETIMEDOUT;
626 goto out;
a4fc5ed6
KP		 627 }
628
629 /* Unload any bytes sent back from the other side */
630 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
631 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 632 if (recv_bytes > recv_size)
633 recv_bytes = recv_size;
0206e353 634
4f7f7b7e
CW		 635 for (i = 0; i < recv_bytes; i += 4)
636 unpack_aux(I915_READ(ch_data + i),
637 recv + i, recv_bytes - i);
a4fc5ed6 638
9ee32fea
DV		 639 ret = recv_bytes;
640out:
641 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 642 intel_aux_display_runtime_put(dev_priv);
9ee32fea 643
884f19e9
JN		 644 if (vdd)
645 edp_panel_vdd_off(intel_dp, false);
646
9ee32fea 647 return ret;
a4fc5ed6
KP		 648}
649
a6c8aff0
JN		 650#define BARE_ADDRESS_SIZE 3
651#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 652static ssize_t
653intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 654{
9d1a1031
JN		 655 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
656 uint8_t txbuf[20], rxbuf[20];
657 size_t txsize, rxsize;
a4fc5ed6 658 int ret;
a4fc5ed6 659
9d1a1031
JN		 660 txbuf[0] = msg->request << 4;
661 txbuf[1] = msg->address >> 8;
662 txbuf[2] = msg->address & 0xff;
663 txbuf[3] = msg->size - 1;
46a5ae9f 664
9d1a1031
JN		 665 switch (msg->request & ~DP_AUX_I2C_MOT) {
666 case DP_AUX_NATIVE_WRITE:
667 case DP_AUX_I2C_WRITE:
a6c8aff0 668 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 669 rxsize = 1;
f51a44b9 670
9d1a1031
JN		 671 if (WARN_ON(txsize > 20))
672 return -E2BIG;
a4fc5ed6 673
9d1a1031 674 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 675
9d1a1031
JN		 676 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
677 if (ret > 0) {
678 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 679
9d1a1031
JN		 680 /* Return payload size. */
681 ret = msg->size;
682 }
683 break;
46a5ae9f 684
9d1a1031
JN		 685 case DP_AUX_NATIVE_READ:
686 case DP_AUX_I2C_READ:
a6c8aff0 687 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 688 rxsize = msg->size + 1;
a4fc5ed6 689
9d1a1031
JN		 690 if (WARN_ON(rxsize > 20))
691 return -E2BIG;
a4fc5ed6 692
9d1a1031
JN		 693 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
694 if (ret > 0) {
695 msg->reply = rxbuf[0] >> 4;
696 /*
697 * Assume happy day, and copy the data. The caller is
698 * expected to check msg->reply before touching it.
699 *
700 * Return payload size.
701 */
702 ret--;
703 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 704 }
9d1a1031
JN		 705 break;
706
707 default:
708 ret = -EINVAL;
709 break;
a4fc5ed6 710 }
f51a44b9 711
9d1a1031 712 return ret;
a4fc5ed6
KP		 713}
714
9d1a1031
JN		 715static void
716intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
717{
718 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 719 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
720 enum port port = intel_dig_port->port;
0b99836f 721 const char *name = NULL;
ab2c0672
DA		 722 int ret;
723
33ad6626
JN		 724 switch (port) {
725 case PORT_A:
726 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 727 name = "DPDDC-A";
ab2c0672 728 break;
33ad6626
JN		 729 case PORT_B:
730 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 731 name = "DPDDC-B";
ab2c0672 732 break;
33ad6626
JN		 733 case PORT_C:
734 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 735 name = "DPDDC-C";
ab2c0672 736 break;
33ad6626
JN		 737 case PORT_D:
738 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 739 name = "DPDDC-D";
33ad6626
JN		 740 break;
741 default:
742 BUG();
ab2c0672
DA		 743 }
744
33ad6626
JN		 745 if (!HAS_DDI(dev))
746 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 747
0b99836f 748 intel_dp->aux.name = name;
9d1a1031
JN		 749 intel_dp->aux.dev = dev->dev;
750 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 751
0b99836f
JN		 752 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
753 connector->base.kdev->kobj.name);
8316f337 754
4f71d0cb 755 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 756 if (ret < 0) {
4f71d0cb 757 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 758 name, ret);
759 return;
ab2c0672 760 }
8a5e6aeb 761
0b99836f
JN		 762 ret = sysfs_create_link(&connector->base.kdev->kobj,
763 &intel_dp->aux.ddc.dev.kobj,
764 intel_dp->aux.ddc.dev.kobj.name);
765 if (ret < 0) {
766 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 767 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 768 }
a4fc5ed6
KP		 769}
770
80f65de3
ID		 771static void
772intel_dp_connector_unregister(struct intel_connector *intel_connector)
773{
774 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
775
0e32b39c
DA		 776 if (!intel_connector->mst_port)
777 sysfs_remove_link(&intel_connector->base.kdev->kobj,
778 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 779 intel_connector_unregister(intel_connector);
780}
781
0e50338c
DV		 782static void
783hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
784{
785 switch (link_bw) {
786 case DP_LINK_BW_1_62:
787 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
788 break;
789 case DP_LINK_BW_2_7:
790 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
791 break;
792 case DP_LINK_BW_5_4:
793 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
794 break;
795 }
796}
797
c6bb3538
DV		 798static void
799intel_dp_set_clock(struct intel_encoder *encoder,
800 struct intel_crtc_config *pipe_config, int link_bw)
801{
802 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 803 const struct dp_link_dpll *divisor = NULL;
804 int i, count = 0;
c6bb3538
DV		 805
806 if (IS_G4X(dev)) {
9dd4ffdf
CML		 807 divisor = gen4_dpll;
808 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 809 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 810 divisor = pch_dpll;
811 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 812 } else if (IS_CHERRYVIEW(dev)) {
813 divisor = chv_dpll;
814 count = ARRAY_SIZE(chv_dpll);
c6bb3538 815 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 816 divisor = vlv_dpll;
817 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 818 }
9dd4ffdf
CML		 819
820 if (divisor && count) {
821 for (i = 0; i < count; i++) {
822 if (link_bw == divisor[i].link_bw) {
823 pipe_config->dpll = divisor[i].dpll;
824 pipe_config->clock_set = true;
825 break;
826 }
827 }
c6bb3538
DV		 828 }
829}
830
439d7ac0
PB		 831static void
832intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
833{
834 struct drm_device *dev = crtc->base.dev;
835 struct drm_i915_private *dev_priv = dev->dev_private;
836 enum transcoder transcoder = crtc->config.cpu_transcoder;
837
838 I915_WRITE(PIPE_DATA_M2(transcoder),
839 TU_SIZE(m_n->tu) | m_n->gmch_m);
840 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
841 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
842 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
843}
844
00c09d70 845bool
5bfe2ac0
DV		 846intel_dp_compute_config(struct intel_encoder *encoder,
847 struct intel_crtc_config *pipe_config)
a4fc5ed6 848{
5bfe2ac0 849 struct drm_device *dev = encoder->base.dev;
36008365 850 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 851 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 852 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 853 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 854 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 855 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 856 int lane_count, clock;
56071a20 857 int min_lane_count = 1;
eeb6324d 858 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 859 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 860 int min_clock = 0;
06ea66b6 861 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 862 int bpp, mode_rate;
06ea66b6 863 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 864 int link_avail, link_clock;
a4fc5ed6 865
bc7d38a4 866 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 867 pipe_config->has_pch_encoder = true;
868
03afc4a2 869 pipe_config->has_dp_encoder = true;
9ed109a7 870 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 871
dd06f90e
JN		 872 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
873 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
874 adjusted_mode);
2dd24552
JB		 875 if (!HAS_PCH_SPLIT(dev))
876 intel_gmch_panel_fitting(intel_crtc, pipe_config,
877 intel_connector->panel.fitting_mode);
878 else
b074cec8
JB		 879 intel_pch_panel_fitting(intel_crtc, pipe_config,
880 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 881 }
882
cb1793ce 883 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 884 return false;
885
083f9560
DV		 886 DRM_DEBUG_KMS("DP link computation with max lane count %i "
887 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 888 max_lane_count, bws[max_clock],
889 adjusted_mode->crtc_clock);
083f9560 890
36008365
DV		 891 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
892 * bpc in between. */
3e7ca985 893 bpp = pipe_config->pipe_bpp;
56071a20
JN		 894 if (is_edp(intel_dp)) {
895 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
896 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
897 dev_priv->vbt.edp_bpp);
898 bpp = dev_priv->vbt.edp_bpp;
899 }
900
f4cdbc21
JN		 901 if (IS_BROADWELL(dev)) {
902 /* Yes, it's an ugly hack. */
903 min_lane_count = max_lane_count;
904 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
905 min_lane_count);
906 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 907 min_lane_count = min(dev_priv->vbt.edp_lanes,
908 max_lane_count);
909 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
910 min_lane_count);
911 }
912
913 if (dev_priv->vbt.edp_rate) {
914 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
915 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
916 bws[min_clock]);
917 }
7984211e 918 }
657445fe 919
36008365 920 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 921 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
922 bpp);
36008365 923
c6930992
DA		 924 for (clock = min_clock; clock <= max_clock; clock++) {
925 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 926 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
927 link_avail = intel_dp_max_data_rate(link_clock,
928 lane_count);
929
930 if (mode_rate <= link_avail) {
931 goto found;
932 }
933 }
934 }
935 }
c4867936 936
36008365 937 return false;
3685a8f3 938
36008365 939found:
55bc60db
VS		 940 if (intel_dp->color_range_auto) {
941 /*
942 * See:
943 * CEA-861-E - 5.1 Default Encoding Parameters
944 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
945 */
18316c8c 946 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 947 intel_dp->color_range = DP_COLOR_RANGE_16_235;
948 else
949 intel_dp->color_range = 0;
950 }
951
3685a8f3 952 if (intel_dp->color_range)
50f3b016 953 pipe_config->limited_color_range = true;
a4fc5ed6 954
36008365
DV		 955 intel_dp->link_bw = bws[clock];
956 intel_dp->lane_count = lane_count;
657445fe 957 pipe_config->pipe_bpp = bpp;
ff9a6750 958 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 959
36008365
DV		 960 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
961 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 962 pipe_config->port_clock, bpp);
36008365
DV		 963 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
964 mode_rate, link_avail);
a4fc5ed6 965
03afc4a2 966 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 967 adjusted_mode->crtc_clock,
968 pipe_config->port_clock,
03afc4a2 969 &pipe_config->dp_m_n);
9d1a455b 970
439d7ac0
PB		 971 if (intel_connector->panel.downclock_mode != NULL &&
972 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
973 intel_link_compute_m_n(bpp, lane_count,
974 intel_connector->panel.downclock_mode->clock,
975 pipe_config->port_clock,
976 &pipe_config->dp_m2_n2);
977 }
978
0e50338c
DV		 979 if (HAS_DDI(dev))
980 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
981 else
982 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 983
03afc4a2 984 return true;
a4fc5ed6
KP		 985}
986
7c62a164 987static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 988{
7c62a164
DV		 989 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
990 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
991 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 992 struct drm_i915_private *dev_priv = dev->dev_private;
993 u32 dpa_ctl;
994
ff9a6750 995 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 996 dpa_ctl = I915_READ(DP_A);
997 dpa_ctl &= ~DP_PLL_FREQ_MASK;
998
ff9a6750 999 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1000 /* For a long time we've carried around a ILK-DevA w/a for the
1001 * 160MHz clock. If we're really unlucky, it's still required.
1002 */
1003 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1004 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1005 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1006 } else {
1007 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1008 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1009 }
1ce17038 1010
ea9b6006
DV		 1011 I915_WRITE(DP_A, dpa_ctl);
1012
1013 POSTING_READ(DP_A);
1014 udelay(500);
1015}
1016
8ac33ed3 1017static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1018{
b934223d 1019 struct drm_device *dev = encoder->base.dev;
417e822d 1020 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1021 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1022 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1023 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1024 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1025
417e822d 1026 /*
1a2eb460 1027 * There are four kinds of DP registers:
417e822d
KP		 1028 *
1029 * IBX PCH
1a2eb460
KP		 1030 * SNB CPU
1031 * IVB CPU
417e822d
KP		 1032 * CPT PCH
1033 *
1034 * IBX PCH and CPU are the same for almost everything,
1035 * except that the CPU DP PLL is configured in this
1036 * register
1037 *
1038 * CPT PCH is quite different, having many bits moved
1039 * to the TRANS_DP_CTL register instead. That
1040 * configuration happens (oddly) in ironlake_pch_enable
1041 */
9c9e7927 1042
417e822d
KP		 1043 /* Preserve the BIOS-computed detected bit. This is
1044 * supposed to be read-only.
1045 */
1046 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1047
417e822d 1048 /* Handle DP bits in common between all three register formats */
417e822d 1049 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1050 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1051
9ed109a7 1052 if (crtc->config.has_audio) {
e0dac65e 1053 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1054 pipe_name(crtc->pipe));
ea5b213a 1055 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1056 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1057 }
247d89f6 1058
417e822d 1059 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1060
bc7d38a4 1061 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1062 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1063 intel_dp->DP |= DP_SYNC_HS_HIGH;
1064 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1065 intel_dp->DP |= DP_SYNC_VS_HIGH;
1066 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1067
6aba5b6c 1068 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1069 intel_dp->DP |= DP_ENHANCED_FRAMING;
1070
7c62a164 1071 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1072 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1073 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1074 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1075
1076 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1077 intel_dp->DP |= DP_SYNC_HS_HIGH;
1078 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1079 intel_dp->DP |= DP_SYNC_VS_HIGH;
1080 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1081
6aba5b6c 1082 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1083 intel_dp->DP |= DP_ENHANCED_FRAMING;
1084
44f37d1f
CML		 1085 if (!IS_CHERRYVIEW(dev)) {
1086 if (crtc->pipe == 1)
1087 intel_dp->DP |= DP_PIPEB_SELECT;
1088 } else {
1089 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1090 }
417e822d
KP		 1091 } else {
1092 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1093 }
a4fc5ed6
KP		 1094}
1095
ffd6749d
PZ		 1096#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1097#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1098
1a5ef5b7
PZ		 1099#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1100#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1101
ffd6749d
PZ		 1102#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1103#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1104
4be73780 1105static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1106 u32 mask,
1107 u32 value)
bd943159 1108{
30add22d 1109 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1110 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1111 u32 pp_stat_reg, pp_ctrl_reg;
1112
bf13e81b
JN		 1113 pp_stat_reg = _pp_stat_reg(intel_dp);
1114 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1115
99ea7127 1116 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1117 mask, value,
1118 I915_READ(pp_stat_reg),
1119 I915_READ(pp_ctrl_reg));
32ce697c 1120
453c5420 1121 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1122 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1123 I915_READ(pp_stat_reg),
1124 I915_READ(pp_ctrl_reg));
32ce697c 1125 }
54c136d4
CW		 1126
1127 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1128}
32ce697c 1129
4be73780 1130static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1131{
1132 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1133 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1134}
1135
4be73780 1136static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1137{
1138 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1139 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1140}
1141
4be73780 1142static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1143{
1144 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1145
1146 /* When we disable the VDD override bit last we have to do the manual
1147 * wait. */
1148 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1149 intel_dp->panel_power_cycle_delay);
1150
4be73780 1151 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1152}
1153
4be73780 1154static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1155{
1156 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1157 intel_dp->backlight_on_delay);
1158}
1159
4be73780 1160static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1161{
1162 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1163 intel_dp->backlight_off_delay);
1164}
99ea7127 1165
832dd3c1
KP		 1166/* Read the current pp_control value, unlocking the register if it
1167 * is locked
1168 */
1169
453c5420 1170static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1171{
453c5420
JB		 1172 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1173 struct drm_i915_private *dev_priv = dev->dev_private;
1174 u32 control;
832dd3c1 1175
bf13e81b 1176 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1177 control &= ~PANEL_UNLOCK_MASK;
1178 control |= PANEL_UNLOCK_REGS;
1179 return control;
bd943159
KP		 1180}
1181
adddaaf4 1182static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1183{
30add22d 1184 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1185 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1186 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1187 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1188 enum intel_display_power_domain power_domain;
5d613501 1189 u32 pp;
453c5420 1190 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1191 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1192
97af61f5 1193 if (!is_edp(intel_dp))
adddaaf4 1194 return false;
bd943159
KP		 1195
1196 intel_dp->want_panel_vdd = true;
99ea7127 1197
4be73780 1198 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1199 return need_to_disable;
b0665d57 1200
4e6e1a54
ID		 1201 power_domain = intel_display_port_power_domain(intel_encoder);
1202 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1203
b0665d57 1204 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1205
4be73780
DV		 1206 if (!edp_have_panel_power(intel_dp))
1207 wait_panel_power_cycle(intel_dp);
99ea7127 1208
453c5420 1209 pp = ironlake_get_pp_control(intel_dp);
5d613501 1210 pp |= EDP_FORCE_VDD;
ebf33b18 1211
bf13e81b
JN		 1212 pp_stat_reg = _pp_stat_reg(intel_dp);
1213 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1214
1215 I915_WRITE(pp_ctrl_reg, pp);
1216 POSTING_READ(pp_ctrl_reg);
1217 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1218 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1219 /*
1220 * If the panel wasn't on, delay before accessing aux channel
1221 */
4be73780 1222 if (!edp_have_panel_power(intel_dp)) {
bd943159 1223 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1224 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1225 }
adddaaf4
JN		 1226
1227 return need_to_disable;
1228}
1229
b80d6c78 1230void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1231{
1232 if (is_edp(intel_dp)) {
1233 bool vdd = _edp_panel_vdd_on(intel_dp);
1234
1235 WARN(!vdd, "eDP VDD already requested on\n");
1236 }
5d613501
JB		 1237}
1238
4be73780 1239static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1240{
30add22d 1241 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1242 struct drm_i915_private *dev_priv = dev->dev_private;
1243 u32 pp;
453c5420 1244 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1245
51fd371b 1246 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
a0e99e68 1247
4be73780 1248 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
4e6e1a54
ID		 1249 struct intel_digital_port *intel_dig_port =
1250 dp_to_dig_port(intel_dp);
1251 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1252 enum intel_display_power_domain power_domain;
1253
b0665d57
PZ		 1254 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1255
453c5420 1256 pp = ironlake_get_pp_control(intel_dp);
bd943159 1257 pp &= ~EDP_FORCE_VDD;
bd943159 1258
9f08ef59
PZ		 1259 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1260 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1261
1262 I915_WRITE(pp_ctrl_reg, pp);
1263 POSTING_READ(pp_ctrl_reg);
99ea7127 1264
453c5420
JB		 1265 /* Make sure sequencer is idle before allowing subsequent activity */
1266 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1267 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1268
1269 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1270 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1271
4e6e1a54
ID		 1272 power_domain = intel_display_port_power_domain(intel_encoder);
1273 intel_display_power_put(dev_priv, power_domain);
bd943159
KP		 1274 }
1275}
5d613501 1276
4be73780 1277static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1278{
1279 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1280 struct intel_dp, panel_vdd_work);
30add22d 1281 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1282
51fd371b 1283 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 1284 edp_panel_vdd_off_sync(intel_dp);
51fd371b 1285 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159
KP		 1286}
1287
aba86890
ID		 1288static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1289{
1290 unsigned long delay;
1291
1292 /*
1293 * Queue the timer to fire a long time from now (relative to the power
1294 * down delay) to keep the panel power up across a sequence of
1295 * operations.
1296 */
1297 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1298 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1299}
1300
4be73780 1301static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1302{
97af61f5
KP		 1303 if (!is_edp(intel_dp))
1304 return;
5d613501 1305
bd943159 1306 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1307
bd943159
KP		 1308 intel_dp->want_panel_vdd = false;
1309
aba86890 1310 if (sync)
4be73780 1311 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1312 else
1313 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1314}
1315
4be73780 1316void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1317{
30add22d 1318 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1319 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1320 u32 pp;
453c5420 1321 u32 pp_ctrl_reg;
9934c132 1322
97af61f5 1323 if (!is_edp(intel_dp))
bd943159 1324 return;
99ea7127
KP		 1325
1326 DRM_DEBUG_KMS("Turn eDP power on\n");
1327
4be73780 1328 if (edp_have_panel_power(intel_dp)) {
99ea7127 1329 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1330 return;
99ea7127 1331 }
9934c132 1332
4be73780 1333 wait_panel_power_cycle(intel_dp);
37c6c9b0 1334
bf13e81b 1335 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1336 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1337 if (IS_GEN5(dev)) {
1338 /* ILK workaround: disable reset around power sequence */
1339 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1340 I915_WRITE(pp_ctrl_reg, pp);
1341 POSTING_READ(pp_ctrl_reg);
05ce1a49 1342 }
37c6c9b0 1343
1c0ae80a 1344 pp |= POWER_TARGET_ON;
99ea7127
KP		 1345 if (!IS_GEN5(dev))
1346 pp |= PANEL_POWER_RESET;
1347
453c5420
JB		 1348 I915_WRITE(pp_ctrl_reg, pp);
1349 POSTING_READ(pp_ctrl_reg);
9934c132 1350
4be73780 1351 wait_panel_on(intel_dp);
dce56b3c 1352 intel_dp->last_power_on = jiffies;
9934c132 1353
05ce1a49
KP		 1354 if (IS_GEN5(dev)) {
1355 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1356 I915_WRITE(pp_ctrl_reg, pp);
1357 POSTING_READ(pp_ctrl_reg);
05ce1a49 1358 }
9934c132
JB		 1359}
1360
4be73780 1361void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1362{
4e6e1a54
ID		 1363 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1364 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1365 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1366 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1367 enum intel_display_power_domain power_domain;
99ea7127 1368 u32 pp;
453c5420 1369 u32 pp_ctrl_reg;
9934c132 1370
97af61f5
KP		 1371 if (!is_edp(intel_dp))
1372 return;
37c6c9b0 1373
99ea7127 1374 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1375
24f3e092
JN		 1376 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1377
453c5420 1378 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1379 /* We need to switch off panel power _and_ force vdd, for otherwise some
1380 * panels get very unhappy and cease to work. */
b3064154
PJ		 1381 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1382 EDP_BLC_ENABLE);
453c5420 1383
bf13e81b 1384 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1385
849e39f5
PZ		 1386 intel_dp->want_panel_vdd = false;
1387
453c5420
JB		 1388 I915_WRITE(pp_ctrl_reg, pp);
1389 POSTING_READ(pp_ctrl_reg);
9934c132 1390
dce56b3c 1391 intel_dp->last_power_cycle = jiffies;
4be73780 1392 wait_panel_off(intel_dp);
849e39f5
PZ		 1393
1394 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1395 power_domain = intel_display_port_power_domain(intel_encoder);
1396 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1397}
1398
4be73780 1399void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1400{
da63a9f2
PZ		 1401 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1402 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1403 struct drm_i915_private *dev_priv = dev->dev_private;
1404 u32 pp;
453c5420 1405 u32 pp_ctrl_reg;
32f9d658 1406
f01eca2e
KP		 1407 if (!is_edp(intel_dp))
1408 return;
1409
28c97730 1410 DRM_DEBUG_KMS("\n");
f7d2323c
JB		 1411
1412 intel_panel_enable_backlight(intel_dp->attached_connector);
1413
01cb9ea6
JB		 1414 /*
1415 * If we enable the backlight right away following a panel power
1416 * on, we may see slight flicker as the panel syncs with the eDP
1417 * link. So delay a bit to make sure the image is solid before
1418 * allowing it to appear.
1419 */
4be73780 1420 wait_backlight_on(intel_dp);
453c5420 1421 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1422 pp |= EDP_BLC_ENABLE;
453c5420 1423
bf13e81b 1424 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1425
1426 I915_WRITE(pp_ctrl_reg, pp);
1427 POSTING_READ(pp_ctrl_reg);
32f9d658
ZW		 1428}
1429
4be73780 1430void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1431{
30add22d 1432 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1433 struct drm_i915_private *dev_priv = dev->dev_private;
1434 u32 pp;
453c5420 1435 u32 pp_ctrl_reg;
32f9d658 1436
f01eca2e
KP		 1437 if (!is_edp(intel_dp))
1438 return;
1439
28c97730 1440 DRM_DEBUG_KMS("\n");
453c5420 1441 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1442 pp &= ~EDP_BLC_ENABLE;
453c5420 1443
bf13e81b 1444 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1445
1446 I915_WRITE(pp_ctrl_reg, pp);
1447 POSTING_READ(pp_ctrl_reg);
dce56b3c 1448 intel_dp->last_backlight_off = jiffies;
f7d2323c
JB		 1449
1450 edp_wait_backlight_off(intel_dp);
1451
1452 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1453}
a4fc5ed6 1454
2bd2ad64 1455static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1456{
da63a9f2
PZ		 1457 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1458 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1459 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1460 struct drm_i915_private *dev_priv = dev->dev_private;
1461 u32 dpa_ctl;
1462
2bd2ad64
DV		 1463 assert_pipe_disabled(dev_priv,
1464 to_intel_crtc(crtc)->pipe);
1465
d240f20f
JB		 1466 DRM_DEBUG_KMS("\n");
1467 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1468 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1469 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1470
1471 /* We don't adjust intel_dp->DP while tearing down the link, to
1472 * facilitate link retraining (e.g. after hotplug). Hence clear all
1473 * enable bits here to ensure that we don't enable too much. */
1474 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1475 intel_dp->DP |= DP_PLL_ENABLE;
1476 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1477 POSTING_READ(DP_A);
1478 udelay(200);
d240f20f
JB		 1479}
1480
2bd2ad64 1481static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1482{
da63a9f2
PZ		 1483 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1484 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1485 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1486 struct drm_i915_private *dev_priv = dev->dev_private;
1487 u32 dpa_ctl;
1488
2bd2ad64
DV		 1489 assert_pipe_disabled(dev_priv,
1490 to_intel_crtc(crtc)->pipe);
1491
d240f20f 1492 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1493 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1494 "dp pll off, should be on\n");
1495 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1496
1497 /* We can't rely on the value tracked for the DP register in
1498 * intel_dp->DP because link_down must not change that (otherwise link
1499 * re-training will fail. */
298b0b39 1500 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1501 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1502 POSTING_READ(DP_A);
d240f20f
JB		 1503 udelay(200);
1504}
1505
c7ad3810 1506/* If the sink supports it, try to set the power state appropriately */
c19b0669 1507void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1508{
1509 int ret, i;
1510
1511 /* Should have a valid DPCD by this point */
1512 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1513 return;
1514
1515 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1516 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1517 DP_SET_POWER_D3);
c7ad3810
JB		 1518 if (ret != 1)
1519 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1520 } else {
1521 /*
1522 * When turning on, we need to retry for 1ms to give the sink
1523 * time to wake up.
1524 */
1525 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1526 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1527 DP_SET_POWER_D0);
c7ad3810
JB		 1528 if (ret == 1)
1529 break;
1530 msleep(1);
1531 }
1532 }
1533}
1534
19d8fe15
DV		 1535static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1536 enum pipe *pipe)
d240f20f 1537{
19d8fe15 1538 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1539 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1540 struct drm_device *dev = encoder->base.dev;
1541 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1542 enum intel_display_power_domain power_domain;
1543 u32 tmp;
1544
1545 power_domain = intel_display_port_power_domain(encoder);
1546 if (!intel_display_power_enabled(dev_priv, power_domain))
1547 return false;
1548
1549 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1550
1551 if (!(tmp & DP_PORT_EN))
1552 return false;
1553
bc7d38a4 1554 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1555 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1556 } else if (IS_CHERRYVIEW(dev)) {
1557 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1558 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1559 *pipe = PORT_TO_PIPE(tmp);
1560 } else {
1561 u32 trans_sel;
1562 u32 trans_dp;
1563 int i;
1564
1565 switch (intel_dp->output_reg) {
1566 case PCH_DP_B:
1567 trans_sel = TRANS_DP_PORT_SEL_B;
1568 break;
1569 case PCH_DP_C:
1570 trans_sel = TRANS_DP_PORT_SEL_C;
1571 break;
1572 case PCH_DP_D:
1573 trans_sel = TRANS_DP_PORT_SEL_D;
1574 break;
1575 default:
1576 return true;
1577 }
1578
1579 for_each_pipe(i) {
1580 trans_dp = I915_READ(TRANS_DP_CTL(i));
1581 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1582 *pipe = i;
1583 return true;
1584 }
1585 }
19d8fe15 1586
4a0833ec
DV		 1587 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1588 intel_dp->output_reg);
1589 }
d240f20f 1590
19d8fe15
DV		 1591 return true;
1592}
d240f20f 1593
045ac3b5
JB		 1594static void intel_dp_get_config(struct intel_encoder *encoder,
1595 struct intel_crtc_config *pipe_config)
1596{
1597 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1598 u32 tmp, flags = 0;
63000ef6
XZ		 1599 struct drm_device *dev = encoder->base.dev;
1600 struct drm_i915_private *dev_priv = dev->dev_private;
1601 enum port port = dp_to_dig_port(intel_dp)->port;
1602 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1603 int dotclock;
045ac3b5 1604
9ed109a7
DV		 1605 tmp = I915_READ(intel_dp->output_reg);
1606 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1607 pipe_config->has_audio = true;
1608
63000ef6 1609 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1610 if (tmp & DP_SYNC_HS_HIGH)
1611 flags |= DRM_MODE_FLAG_PHSYNC;
1612 else
1613 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1614
63000ef6
XZ		 1615 if (tmp & DP_SYNC_VS_HIGH)
1616 flags |= DRM_MODE_FLAG_PVSYNC;
1617 else
1618 flags |= DRM_MODE_FLAG_NVSYNC;
1619 } else {
1620 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1621 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1622 flags |= DRM_MODE_FLAG_PHSYNC;
1623 else
1624 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1625
63000ef6
XZ		 1626 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1627 flags |= DRM_MODE_FLAG_PVSYNC;
1628 else
1629 flags |= DRM_MODE_FLAG_NVSYNC;
1630 }
045ac3b5
JB		 1631
1632 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1633
eb14cb74
VS		 1634 pipe_config->has_dp_encoder = true;
1635
1636 intel_dp_get_m_n(crtc, pipe_config);
1637
18442d08 1638 if (port == PORT_A) {
f1f644dc
JB		 1639 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1640 pipe_config->port_clock = 162000;
1641 else
1642 pipe_config->port_clock = 270000;
1643 }
18442d08
VS		 1644
1645 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1646 &pipe_config->dp_m_n);
1647
1648 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1649 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1650
241bfc38 1651 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1652
c6cd2ee2
JN		 1653 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1654 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1655 /*
1656 * This is a big fat ugly hack.
1657 *
1658 * Some machines in UEFI boot mode provide us a VBT that has 18
1659 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1660 * unknown we fail to light up. Yet the same BIOS boots up with
1661 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1662 * max, not what it tells us to use.
1663 *
1664 * Note: This will still be broken if the eDP panel is not lit
1665 * up by the BIOS, and thus we can't get the mode at module
1666 * load.
1667 */
1668 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1669 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1670 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1671 }
045ac3b5
JB		 1672}
1673
34eb7579 1674static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1675{
34eb7579 1676 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1677}
1678
2b28bb1b
RV		 1679static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1680{
1681 struct drm_i915_private *dev_priv = dev->dev_private;
1682
18b5992c 1683 if (!HAS_PSR(dev))
2b28bb1b
RV		 1684 return false;
1685
18b5992c 1686 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1687}
1688
1689static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1690 struct edp_vsc_psr *vsc_psr)
1691{
1692 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1693 struct drm_device *dev = dig_port->base.base.dev;
1694 struct drm_i915_private *dev_priv = dev->dev_private;
1695 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1696 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1697 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1698 uint32_t *data = (uint32_t *) vsc_psr;
1699 unsigned int i;
1700
1701 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1702 the video DIP being updated before program video DIP data buffer
1703 registers for DIP being updated. */
1704 I915_WRITE(ctl_reg, 0);
1705 POSTING_READ(ctl_reg);
1706
1707 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1708 if (i < sizeof(struct edp_vsc_psr))
1709 I915_WRITE(data_reg + i, *data++);
1710 else
1711 I915_WRITE(data_reg + i, 0);
1712 }
1713
1714 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1715 POSTING_READ(ctl_reg);
1716}
1717
1718static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1719{
1720 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1721 struct drm_i915_private *dev_priv = dev->dev_private;
1722 struct edp_vsc_psr psr_vsc;
1723
2b28bb1b
RV		 1724 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1725 memset(&psr_vsc, 0, sizeof(psr_vsc));
1726 psr_vsc.sdp_header.HB0 = 0;
1727 psr_vsc.sdp_header.HB1 = 0x7;
1728 psr_vsc.sdp_header.HB2 = 0x2;
1729 psr_vsc.sdp_header.HB3 = 0x8;
1730 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1731
1732 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1733 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1734 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1735}
1736
1737static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1738{
0e0ae652
RV		 1739 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1740 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 1741 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1742 uint32_t aux_clock_divider;
2b28bb1b
RV		 1743 int precharge = 0x3;
1744 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 1745 bool only_standby = false;
2b28bb1b 1746
ec5b01dd
DL		 1747 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1748
0e0ae652
RV		 1749 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1750 only_standby = true;
1751
2b28bb1b 1752 /* Enable PSR in sink */
0e0ae652 1753 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 1754 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1755 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1756 else
9d1a1031
JN		 1757 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1758 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1759
1760 /* Setup AUX registers */
18b5992c
BW		 1761 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1762 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1763 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1764 DP_AUX_CH_CTL_TIME_OUT_400us |
1765 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1766 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1767 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1768}
1769
1770static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1771{
0e0ae652
RV		 1772 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1773 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 1774 struct drm_i915_private *dev_priv = dev->dev_private;
1775 uint32_t max_sleep_time = 0x1f;
1776 uint32_t idle_frames = 1;
1777 uint32_t val = 0x0;
ed8546ac 1778 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 1779 bool only_standby = false;
1780
1781 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1782 only_standby = true;
2b28bb1b 1783
0e0ae652 1784 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 1785 val |= EDP_PSR_LINK_STANDBY;
1786 val |= EDP_PSR_TP2_TP3_TIME_0us;
1787 val |= EDP_PSR_TP1_TIME_0us;
1788 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 1789 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 1790 } else
1791 val |= EDP_PSR_LINK_DISABLE;
1792
18b5992c 1793 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1794 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1795 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1796 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1797 EDP_PSR_ENABLE);
1798}
1799
3f51e471
RV		 1800static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1801{
1802 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1803 struct drm_device *dev = dig_port->base.base.dev;
1804 struct drm_i915_private *dev_priv = dev->dev_private;
1805 struct drm_crtc *crtc = dig_port->base.base.crtc;
1806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 1807
f0355c4a 1808 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 1809 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1810 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1811
a031d709
RV		 1812 dev_priv->psr.source_ok = false;
1813
9ca15301 1814 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 1815 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1816 return false;
1817 }
1818
d330a953 1819 if (!i915.enable_psr) {
105b7c11 1820 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1821 return false;
1822 }
1823
4c8c7000
RV		 1824 /* Below limitations aren't valid for Broadwell */
1825 if (IS_BROADWELL(dev))
1826 goto out;
1827
3f51e471
RV		 1828 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1829 S3D_ENABLE) {
1830 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1831 return false;
1832 }
1833
ca73b4f0 1834 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1835 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1836 return false;
1837 }
1838
4c8c7000 1839 out:
a031d709 1840 dev_priv->psr.source_ok = true;
3f51e471
RV		 1841 return true;
1842}
1843
3d739d92 1844static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 1845{
7c8f8a70
RV		 1846 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1847 struct drm_device *dev = intel_dig_port->base.base.dev;
1848 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 1849
3638379c
DV		 1850 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1851 WARN_ON(dev_priv->psr.active);
f0355c4a 1852 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 1853
2b28bb1b
RV		 1854 /* Enable PSR on the panel */
1855 intel_edp_psr_enable_sink(intel_dp);
1856
1857 /* Enable PSR on the host */
1858 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 1859
7c8f8a70 1860 dev_priv->psr.active = true;
2b28bb1b
RV		 1861}
1862
3d739d92
RV		 1863void intel_edp_psr_enable(struct intel_dp *intel_dp)
1864{
1865 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 1866 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 1867
4704c573
RV		 1868 if (!HAS_PSR(dev)) {
1869 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1870 return;
1871 }
1872
34eb7579
RV		 1873 if (!is_edp_psr(intel_dp)) {
1874 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1875 return;
1876 }
1877
f0355c4a 1878 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 1879 if (dev_priv->psr.enabled) {
1880 DRM_DEBUG_KMS("PSR already in use\n");
f0355c4a 1881 mutex_unlock(&dev_priv->psr.lock);
109fc2ad
DV		 1882 return;
1883 }
1884
9ca15301
DV		 1885 dev_priv->psr.busy_frontbuffer_bits = 0;
1886
16487254
RV		 1887 /* Setup PSR once */
1888 intel_edp_psr_setup(intel_dp);
1889
7c8f8a70 1890 if (intel_edp_psr_match_conditions(intel_dp))
9ca15301 1891 dev_priv->psr.enabled = intel_dp;
f0355c4a 1892 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 1893}
1894
2b28bb1b
RV		 1895void intel_edp_psr_disable(struct intel_dp *intel_dp)
1896{
1897 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1898 struct drm_i915_private *dev_priv = dev->dev_private;
1899
f0355c4a
DV		 1900 mutex_lock(&dev_priv->psr.lock);
1901 if (!dev_priv->psr.enabled) {
1902 mutex_unlock(&dev_priv->psr.lock);
1903 return;
1904 }
1905
3638379c
DV		 1906 if (dev_priv->psr.active) {
1907 I915_WRITE(EDP_PSR_CTL(dev),
1908 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1909
1910 /* Wait till PSR is idle */
1911 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1912 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1913 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 1914
3638379c
DV		 1915 dev_priv->psr.active = false;
1916 } else {
1917 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1918 }
7c8f8a70 1919
2807cf69 1920 dev_priv->psr.enabled = NULL;
f0355c4a 1921 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 1922
1923 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 1924}
1925
f02a326e 1926static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 1927{
1928 struct drm_i915_private *dev_priv =
1929 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 1930 struct intel_dp *intel_dp = dev_priv->psr.enabled;
1931
f0355c4a
DV		 1932 mutex_lock(&dev_priv->psr.lock);
1933 intel_dp = dev_priv->psr.enabled;
1934
2807cf69 1935 if (!intel_dp)
f0355c4a 1936 goto unlock;
2807cf69 1937
9ca15301
DV		 1938 /*
1939 * The delayed work can race with an invalidate hence we need to
1940 * recheck. Since psr_flush first clears this and then reschedules we
1941 * won't ever miss a flush when bailing out here.
1942 */
1943 if (dev_priv->psr.busy_frontbuffer_bits)
1944 goto unlock;
1945
1946 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 1947unlock:
1948 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 1949}
1950
9ca15301 1951static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 1952{
1953 struct drm_i915_private *dev_priv = dev->dev_private;
1954
3638379c
DV		 1955 if (dev_priv->psr.active) {
1956 u32 val = I915_READ(EDP_PSR_CTL(dev));
1957
1958 WARN_ON(!(val & EDP_PSR_ENABLE));
1959
1960 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
1961
1962 dev_priv->psr.active = false;
1963 }
7c8f8a70 1964
9ca15301
DV		 1965}
1966
1967void intel_edp_psr_invalidate(struct drm_device *dev,
1968 unsigned frontbuffer_bits)
1969{
1970 struct drm_i915_private *dev_priv = dev->dev_private;
1971 struct drm_crtc *crtc;
1972 enum pipe pipe;
1973
9ca15301
DV		 1974 mutex_lock(&dev_priv->psr.lock);
1975 if (!dev_priv->psr.enabled) {
1976 mutex_unlock(&dev_priv->psr.lock);
1977 return;
1978 }
1979
1980 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
1981 pipe = to_intel_crtc(crtc)->pipe;
1982
1983 intel_edp_psr_do_exit(dev);
1984
1985 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
1986
1987 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
1988 mutex_unlock(&dev_priv->psr.lock);
1989}
1990
1991void intel_edp_psr_flush(struct drm_device *dev,
1992 unsigned frontbuffer_bits)
1993{
1994 struct drm_i915_private *dev_priv = dev->dev_private;
1995 struct drm_crtc *crtc;
1996 enum pipe pipe;
1997
9ca15301
DV		 1998 mutex_lock(&dev_priv->psr.lock);
1999 if (!dev_priv->psr.enabled) {
2000 mutex_unlock(&dev_priv->psr.lock);
2001 return;
2002 }
2003
2004 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2005 pipe = to_intel_crtc(crtc)->pipe;
2006 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2007
2008 /*
2009 * On Haswell sprite plane updates don't result in a psr invalidating
2010 * signal in the hardware. Which means we need to manually fake this in
2011 * software for all flushes, not just when we've seen a preceding
2012 * invalidation through frontbuffer rendering.
2013 */
2014 if (IS_HASWELL(dev) &&
2015 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2016 intel_edp_psr_do_exit(dev);
2017
2018 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2019 schedule_delayed_work(&dev_priv->psr.work,
2020 msecs_to_jiffies(100));
f0355c4a 2021 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2022}
2023
2024void intel_edp_psr_init(struct drm_device *dev)
2025{
2026 struct drm_i915_private *dev_priv = dev->dev_private;
2027
7c8f8a70 2028 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2029 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2030}
2031
e8cb4558 2032static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2033{
e8cb4558 2034 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 2035 enum port port = dp_to_dig_port(intel_dp)->port;
2036 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2037
2038 /* Make sure the panel is off before trying to change the mode. But also
2039 * ensure that we have vdd while we switch off the panel. */
24f3e092 2040 intel_edp_panel_vdd_on(intel_dp);
4be73780 2041 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2042 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2043 intel_edp_panel_off(intel_dp);
3739850b
DV		 2044
2045 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 2046 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 2047 intel_dp_link_down(intel_dp);
d240f20f
JB		 2048}
2049
49277c31 2050static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2051{
2bd2ad64 2052 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2053 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2054
49277c31
VS		 2055 if (port != PORT_A)
2056 return;
2057
2058 intel_dp_link_down(intel_dp);
2059 ironlake_edp_pll_off(intel_dp);
2060}
2061
2062static void vlv_post_disable_dp(struct intel_encoder *encoder)
2063{
2064 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2065
2066 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2067}
2068
580d3811
VS		 2069static void chv_post_disable_dp(struct intel_encoder *encoder)
2070{
2071 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2072 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2073 struct drm_device *dev = encoder->base.dev;
2074 struct drm_i915_private *dev_priv = dev->dev_private;
2075 struct intel_crtc *intel_crtc =
2076 to_intel_crtc(encoder->base.crtc);
2077 enum dpio_channel ch = vlv_dport_to_channel(dport);
2078 enum pipe pipe = intel_crtc->pipe;
2079 u32 val;
2080
2081 intel_dp_link_down(intel_dp);
2082
2083 mutex_lock(&dev_priv->dpio_lock);
2084
2085 /* Propagate soft reset to data lane reset */
97fd4d5c 2086 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2087 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2088 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2089
97fd4d5c
VS		 2090 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2091 val |= CHV_PCS_REQ_SOFTRESET_EN;
2092 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2093
2094 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2095 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2096 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2097
2098 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2099 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2100 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2101
2102 mutex_unlock(&dev_priv->dpio_lock);
2103}
2104
e8cb4558 2105static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2106{
e8cb4558
DV		 2107 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2108 struct drm_device *dev = encoder->base.dev;
2109 struct drm_i915_private *dev_priv = dev->dev_private;
2110 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2111
0c33d8d7
DV		 2112 if (WARN_ON(dp_reg & DP_PORT_EN))
2113 return;
5d613501 2114
24f3e092 2115 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 2116 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2117 intel_dp_start_link_train(intel_dp);
4be73780
DV		 2118 intel_edp_panel_on(intel_dp);
2119 edp_panel_vdd_off(intel_dp, true);
33a34e4e 2120 intel_dp_complete_link_train(intel_dp);
3ab9c637 2121 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2122}
89b667f8 2123
ecff4f3b
JN		 2124static void g4x_enable_dp(struct intel_encoder *encoder)
2125{
828f5c6e
JN		 2126 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2127
ecff4f3b 2128 intel_enable_dp(encoder);
4be73780 2129 intel_edp_backlight_on(intel_dp);
ab1f90f9 2130}
89b667f8 2131
ab1f90f9
JN		 2132static void vlv_enable_dp(struct intel_encoder *encoder)
2133{
828f5c6e
JN		 2134 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2135
4be73780 2136 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2137}
2138
ecff4f3b 2139static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2140{
2141 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2142 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2143
8ac33ed3
DV		 2144 intel_dp_prepare(encoder);
2145
d41f1efb
DV		 2146 /* Only ilk+ has port A */
2147 if (dport->port == PORT_A) {
2148 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2149 ironlake_edp_pll_on(intel_dp);
d41f1efb 2150 }
ab1f90f9
JN		 2151}
2152
2153static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2154{
2bd2ad64 2155 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2156 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2157 struct drm_device *dev = encoder->base.dev;
89b667f8 2158 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2159 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2160 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 2161 int pipe = intel_crtc->pipe;
bf13e81b 2162 struct edp_power_seq power_seq;
ab1f90f9 2163 u32 val;
a4fc5ed6 2164
ab1f90f9 2165 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2166
ab3c759a 2167 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2168 val = 0;
2169 if (pipe)
2170 val |= (1<<21);
2171 else
2172 val &= ~(1<<21);
2173 val |= 0x001000c4;
ab3c759a
CML		 2174 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2175 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2176 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2177
ab1f90f9
JN		 2178 mutex_unlock(&dev_priv->dpio_lock);
2179
2cac613b
ID		 2180 if (is_edp(intel_dp)) {
2181 /* init power sequencer on this pipe and port */
2182 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2183 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2184 &power_seq);
2185 }
bf13e81b 2186
ab1f90f9
JN		 2187 intel_enable_dp(encoder);
2188
e4607fcf 2189 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2190}
2191
ecff4f3b 2192static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2193{
2194 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2195 struct drm_device *dev = encoder->base.dev;
2196 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2197 struct intel_crtc *intel_crtc =
2198 to_intel_crtc(encoder->base.crtc);
e4607fcf 2199 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2200 int pipe = intel_crtc->pipe;
89b667f8 2201
8ac33ed3
DV		 2202 intel_dp_prepare(encoder);
2203
89b667f8 2204 /* Program Tx lane resets to default */
0980a60f 2205 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2206 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2207 DPIO_PCS_TX_LANE2_RESET |
2208 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2209 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2210 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2211 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2212 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2213 DPIO_PCS_CLK_SOFT_RESET);
2214
2215 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2216 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2217 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2218 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2219 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2220}
2221
e4a1d846
CML		 2222static void chv_pre_enable_dp(struct intel_encoder *encoder)
2223{
2224 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2225 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2226 struct drm_device *dev = encoder->base.dev;
2227 struct drm_i915_private *dev_priv = dev->dev_private;
2228 struct edp_power_seq power_seq;
2229 struct intel_crtc *intel_crtc =
2230 to_intel_crtc(encoder->base.crtc);
2231 enum dpio_channel ch = vlv_dport_to_channel(dport);
2232 int pipe = intel_crtc->pipe;
2233 int data, i;
949c1d43 2234 u32 val;
e4a1d846 2235
e4a1d846 2236 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2237
2238 /* Deassert soft data lane reset*/
97fd4d5c 2239 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2240 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2241 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2242
2243 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2244 val |= CHV_PCS_REQ_SOFTRESET_EN;
2245 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2246
2247 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2248 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2249 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2250
97fd4d5c 2251 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2252 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2253 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2254
2255 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2256 for (i = 0; i < 4; i++) {
2257 /* Set the latency optimal bit */
2258 data = (i == 1) ? 0x0 : 0x6;
2259 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2260 data << DPIO_FRC_LATENCY_SHFIT);
2261
2262 /* Set the upar bit */
2263 data = (i == 1) ? 0x0 : 0x1;
2264 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2265 data << DPIO_UPAR_SHIFT);
2266 }
2267
2268 /* Data lane stagger programming */
2269 /* FIXME: Fix up value only after power analysis */
2270
2271 mutex_unlock(&dev_priv->dpio_lock);
2272
2273 if (is_edp(intel_dp)) {
2274 /* init power sequencer on this pipe and port */
2275 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2276 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2277 &power_seq);
2278 }
2279
2280 intel_enable_dp(encoder);
2281
2282 vlv_wait_port_ready(dev_priv, dport);
2283}
2284
9197c88b
VS		 2285static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2286{
2287 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2288 struct drm_device *dev = encoder->base.dev;
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2290 struct intel_crtc *intel_crtc =
2291 to_intel_crtc(encoder->base.crtc);
2292 enum dpio_channel ch = vlv_dport_to_channel(dport);
2293 enum pipe pipe = intel_crtc->pipe;
2294 u32 val;
2295
2296 mutex_lock(&dev_priv->dpio_lock);
2297
b9e5ac3c
VS		 2298 /* program left/right clock distribution */
2299 if (pipe != PIPE_B) {
2300 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2301 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2302 if (ch == DPIO_CH0)
2303 val |= CHV_BUFLEFTENA1_FORCE;
2304 if (ch == DPIO_CH1)
2305 val |= CHV_BUFRIGHTENA1_FORCE;
2306 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2307 } else {
2308 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2309 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2310 if (ch == DPIO_CH0)
2311 val |= CHV_BUFLEFTENA2_FORCE;
2312 if (ch == DPIO_CH1)
2313 val |= CHV_BUFRIGHTENA2_FORCE;
2314 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2315 }
2316
9197c88b
VS		 2317 /* program clock channel usage */
2318 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2319 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2320 if (pipe != PIPE_B)
2321 val &= ~CHV_PCS_USEDCLKCHANNEL;
2322 else
2323 val |= CHV_PCS_USEDCLKCHANNEL;
2324 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2325
2326 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2327 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2328 if (pipe != PIPE_B)
2329 val &= ~CHV_PCS_USEDCLKCHANNEL;
2330 else
2331 val |= CHV_PCS_USEDCLKCHANNEL;
2332 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2333
2334 /*
2335 * This a a bit weird since generally CL
2336 * matches the pipe, but here we need to
2337 * pick the CL based on the port.
2338 */
2339 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2340 if (pipe != PIPE_B)
2341 val &= ~CHV_CMN_USEDCLKCHANNEL;
2342 else
2343 val |= CHV_CMN_USEDCLKCHANNEL;
2344 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2345
2346 mutex_unlock(&dev_priv->dpio_lock);
2347}
2348
a4fc5ed6 2349/*
df0c237d
JB		 2350 * Native read with retry for link status and receiver capability reads for
2351 * cases where the sink may still be asleep.
9d1a1031
JN		 2352 *
2353 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2354 * supposed to retry 3 times per the spec.
a4fc5ed6 2355 */
9d1a1031
JN		 2356static ssize_t
2357intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2358 void *buffer, size_t size)
a4fc5ed6 2359{
9d1a1031
JN		 2360 ssize_t ret;
2361 int i;
61da5fab 2362
61da5fab 2363 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2364 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2365 if (ret == size)
2366 return ret;
61da5fab
JB		 2367 msleep(1);
2368 }
a4fc5ed6 2369
9d1a1031 2370 return ret;
a4fc5ed6
KP		 2371}
2372
2373/*
2374 * Fetch AUX CH registers 0x202 - 0x207 which contain
2375 * link status information
2376 */
2377static bool
93f62dad 2378intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2379{
9d1a1031
JN		 2380 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2381 DP_LANE0_1_STATUS,
2382 link_status,
2383 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2384}
2385
1100244e 2386/* These are source-specific values. */
a4fc5ed6 2387static uint8_t
1a2eb460 2388intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2389{
30add22d 2390 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2391 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2392
9576c27f 2393 if (IS_VALLEYVIEW(dev))
e2fa6fba 2394 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2395 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2396 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2397 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2398 return DP_TRAIN_VOLTAGE_SWING_1200;
2399 else
2400 return DP_TRAIN_VOLTAGE_SWING_800;
2401}
2402
2403static uint8_t
2404intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2405{
30add22d 2406 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2407 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2408
9576c27f 2409 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722
PZ		 2410 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2411 case DP_TRAIN_VOLTAGE_SWING_400:
2412 return DP_TRAIN_PRE_EMPHASIS_9_5;
2413 case DP_TRAIN_VOLTAGE_SWING_600:
2414 return DP_TRAIN_PRE_EMPHASIS_6;
2415 case DP_TRAIN_VOLTAGE_SWING_800:
2416 return DP_TRAIN_PRE_EMPHASIS_3_5;
2417 case DP_TRAIN_VOLTAGE_SWING_1200:
2418 default:
2419 return DP_TRAIN_PRE_EMPHASIS_0;
2420 }
e2fa6fba
P		 2421 } else if (IS_VALLEYVIEW(dev)) {
2422 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2423 case DP_TRAIN_VOLTAGE_SWING_400:
2424 return DP_TRAIN_PRE_EMPHASIS_9_5;
2425 case DP_TRAIN_VOLTAGE_SWING_600:
2426 return DP_TRAIN_PRE_EMPHASIS_6;
2427 case DP_TRAIN_VOLTAGE_SWING_800:
2428 return DP_TRAIN_PRE_EMPHASIS_3_5;
2429 case DP_TRAIN_VOLTAGE_SWING_1200:
2430 default:
2431 return DP_TRAIN_PRE_EMPHASIS_0;
2432 }
bc7d38a4 2433 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2434 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2435 case DP_TRAIN_VOLTAGE_SWING_400:
2436 return DP_TRAIN_PRE_EMPHASIS_6;
2437 case DP_TRAIN_VOLTAGE_SWING_600:
2438 case DP_TRAIN_VOLTAGE_SWING_800:
2439 return DP_TRAIN_PRE_EMPHASIS_3_5;
2440 default:
2441 return DP_TRAIN_PRE_EMPHASIS_0;
2442 }
2443 } else {
2444 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2445 case DP_TRAIN_VOLTAGE_SWING_400:
2446 return DP_TRAIN_PRE_EMPHASIS_6;
2447 case DP_TRAIN_VOLTAGE_SWING_600:
2448 return DP_TRAIN_PRE_EMPHASIS_6;
2449 case DP_TRAIN_VOLTAGE_SWING_800:
2450 return DP_TRAIN_PRE_EMPHASIS_3_5;
2451 case DP_TRAIN_VOLTAGE_SWING_1200:
2452 default:
2453 return DP_TRAIN_PRE_EMPHASIS_0;
2454 }
a4fc5ed6
KP		 2455 }
2456}
2457
e2fa6fba
P		 2458static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2459{
2460 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2461 struct drm_i915_private *dev_priv = dev->dev_private;
2462 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2463 struct intel_crtc *intel_crtc =
2464 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2465 unsigned long demph_reg_value, preemph_reg_value,
2466 uniqtranscale_reg_value;
2467 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2468 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2469 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2470
2471 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2472 case DP_TRAIN_PRE_EMPHASIS_0:
2473 preemph_reg_value = 0x0004000;
2474 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2475 case DP_TRAIN_VOLTAGE_SWING_400:
2476 demph_reg_value = 0x2B405555;
2477 uniqtranscale_reg_value = 0x552AB83A;
2478 break;
2479 case DP_TRAIN_VOLTAGE_SWING_600:
2480 demph_reg_value = 0x2B404040;
2481 uniqtranscale_reg_value = 0x5548B83A;
2482 break;
2483 case DP_TRAIN_VOLTAGE_SWING_800:
2484 demph_reg_value = 0x2B245555;
2485 uniqtranscale_reg_value = 0x5560B83A;
2486 break;
2487 case DP_TRAIN_VOLTAGE_SWING_1200:
2488 demph_reg_value = 0x2B405555;
2489 uniqtranscale_reg_value = 0x5598DA3A;
2490 break;
2491 default:
2492 return 0;
2493 }
2494 break;
2495 case DP_TRAIN_PRE_EMPHASIS_3_5:
2496 preemph_reg_value = 0x0002000;
2497 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2498 case DP_TRAIN_VOLTAGE_SWING_400:
2499 demph_reg_value = 0x2B404040;
2500 uniqtranscale_reg_value = 0x5552B83A;
2501 break;
2502 case DP_TRAIN_VOLTAGE_SWING_600:
2503 demph_reg_value = 0x2B404848;
2504 uniqtranscale_reg_value = 0x5580B83A;
2505 break;
2506 case DP_TRAIN_VOLTAGE_SWING_800:
2507 demph_reg_value = 0x2B404040;
2508 uniqtranscale_reg_value = 0x55ADDA3A;
2509 break;
2510 default:
2511 return 0;
2512 }
2513 break;
2514 case DP_TRAIN_PRE_EMPHASIS_6:
2515 preemph_reg_value = 0x0000000;
2516 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2517 case DP_TRAIN_VOLTAGE_SWING_400:
2518 demph_reg_value = 0x2B305555;
2519 uniqtranscale_reg_value = 0x5570B83A;
2520 break;
2521 case DP_TRAIN_VOLTAGE_SWING_600:
2522 demph_reg_value = 0x2B2B4040;
2523 uniqtranscale_reg_value = 0x55ADDA3A;
2524 break;
2525 default:
2526 return 0;
2527 }
2528 break;
2529 case DP_TRAIN_PRE_EMPHASIS_9_5:
2530 preemph_reg_value = 0x0006000;
2531 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2532 case DP_TRAIN_VOLTAGE_SWING_400:
2533 demph_reg_value = 0x1B405555;
2534 uniqtranscale_reg_value = 0x55ADDA3A;
2535 break;
2536 default:
2537 return 0;
2538 }
2539 break;
2540 default:
2541 return 0;
2542 }
2543
0980a60f 2544 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2545 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2546 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2547 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2548 uniqtranscale_reg_value);
ab3c759a
CML		 2549 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2550 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2551 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2552 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2553 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2554
2555 return 0;
2556}
2557
e4a1d846
CML		 2558static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2559{
2560 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2561 struct drm_i915_private *dev_priv = dev->dev_private;
2562 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2563 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2564 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2565 uint8_t train_set = intel_dp->train_set[0];
2566 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2567 enum pipe pipe = intel_crtc->pipe;
2568 int i;
e4a1d846
CML		 2569
2570 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2571 case DP_TRAIN_PRE_EMPHASIS_0:
2572 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2573 case DP_TRAIN_VOLTAGE_SWING_400:
2574 deemph_reg_value = 128;
2575 margin_reg_value = 52;
2576 break;
2577 case DP_TRAIN_VOLTAGE_SWING_600:
2578 deemph_reg_value = 128;
2579 margin_reg_value = 77;
2580 break;
2581 case DP_TRAIN_VOLTAGE_SWING_800:
2582 deemph_reg_value = 128;
2583 margin_reg_value = 102;
2584 break;
2585 case DP_TRAIN_VOLTAGE_SWING_1200:
2586 deemph_reg_value = 128;
2587 margin_reg_value = 154;
2588 /* FIXME extra to set for 1200 */
2589 break;
2590 default:
2591 return 0;
2592 }
2593 break;
2594 case DP_TRAIN_PRE_EMPHASIS_3_5:
2595 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2596 case DP_TRAIN_VOLTAGE_SWING_400:
2597 deemph_reg_value = 85;
2598 margin_reg_value = 78;
2599 break;
2600 case DP_TRAIN_VOLTAGE_SWING_600:
2601 deemph_reg_value = 85;
2602 margin_reg_value = 116;
2603 break;
2604 case DP_TRAIN_VOLTAGE_SWING_800:
2605 deemph_reg_value = 85;
2606 margin_reg_value = 154;
2607 break;
2608 default:
2609 return 0;
2610 }
2611 break;
2612 case DP_TRAIN_PRE_EMPHASIS_6:
2613 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2614 case DP_TRAIN_VOLTAGE_SWING_400:
2615 deemph_reg_value = 64;
2616 margin_reg_value = 104;
2617 break;
2618 case DP_TRAIN_VOLTAGE_SWING_600:
2619 deemph_reg_value = 64;
2620 margin_reg_value = 154;
2621 break;
2622 default:
2623 return 0;
2624 }
2625 break;
2626 case DP_TRAIN_PRE_EMPHASIS_9_5:
2627 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2628 case DP_TRAIN_VOLTAGE_SWING_400:
2629 deemph_reg_value = 43;
2630 margin_reg_value = 154;
2631 break;
2632 default:
2633 return 0;
2634 }
2635 break;
2636 default:
2637 return 0;
2638 }
2639
2640 mutex_lock(&dev_priv->dpio_lock);
2641
2642 /* Clear calc init */
1966e59e
VS		 2643 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2644 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2645 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2646
2647 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2648 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2649 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2650
2651 /* Program swing deemph */
f72df8db
VS		 2652 for (i = 0; i < 4; i++) {
2653 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2654 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2655 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2656 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2657 }
e4a1d846
CML		 2658
2659 /* Program swing margin */
f72df8db
VS		 2660 for (i = 0; i < 4; i++) {
2661 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2662 val &= ~DPIO_SWING_MARGIN_MASK;
2663 val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2664 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2665 }
e4a1d846
CML		 2666
2667 /* Disable unique transition scale */
f72df8db
VS		 2668 for (i = 0; i < 4; i++) {
2669 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2670 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2671 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2672 }
e4a1d846
CML		 2673
2674 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2675 == DP_TRAIN_PRE_EMPHASIS_0) &&
2676 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2677 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2678
2679 /*
2680 * The document said it needs to set bit 27 for ch0 and bit 26
2681 * for ch1. Might be a typo in the doc.
2682 * For now, for this unique transition scale selection, set bit
2683 * 27 for ch0 and ch1.
2684 */
f72df8db
VS		 2685 for (i = 0; i < 4; i++) {
2686 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2687 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2688 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2689 }
e4a1d846 2690
f72df8db
VS		 2691 for (i = 0; i < 4; i++) {
2692 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2693 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2694 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2695 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2696 }
e4a1d846
CML		 2697 }
2698
2699 /* Start swing calculation */
1966e59e
VS		 2700 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2701 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2702 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2703
2704 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2705 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2706 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2707
2708 /* LRC Bypass */
2709 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2710 val |= DPIO_LRC_BYPASS;
2711 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2712
2713 mutex_unlock(&dev_priv->dpio_lock);
2714
2715 return 0;
2716}
2717
a4fc5ed6 2718static void
0301b3ac
JN		 2719intel_get_adjust_train(struct intel_dp *intel_dp,
2720 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2721{
2722 uint8_t v = 0;
2723 uint8_t p = 0;
2724 int lane;
1a2eb460
KP		 2725 uint8_t voltage_max;
2726 uint8_t preemph_max;
a4fc5ed6 2727
33a34e4e 2728 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2729 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2730 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2731
2732 if (this_v > v)
2733 v = this_v;
2734 if (this_p > p)
2735 p = this_p;
2736 }
2737
1a2eb460 2738 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2739 if (v >= voltage_max)
2740 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2741
1a2eb460
KP		 2742 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2743 if (p >= preemph_max)
2744 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2745
2746 for (lane = 0; lane < 4; lane++)
33a34e4e 2747 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2748}
2749
2750static uint32_t
f0a3424e 2751intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2752{
3cf2efb1 2753 uint32_t signal_levels = 0;
a4fc5ed6 2754
3cf2efb1 2755 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2756 case DP_TRAIN_VOLTAGE_SWING_400:
2757 default:
2758 signal_levels |= DP_VOLTAGE_0_4;
2759 break;
2760 case DP_TRAIN_VOLTAGE_SWING_600:
2761 signal_levels |= DP_VOLTAGE_0_6;
2762 break;
2763 case DP_TRAIN_VOLTAGE_SWING_800:
2764 signal_levels |= DP_VOLTAGE_0_8;
2765 break;
2766 case DP_TRAIN_VOLTAGE_SWING_1200:
2767 signal_levels |= DP_VOLTAGE_1_2;
2768 break;
2769 }
3cf2efb1 2770 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2771 case DP_TRAIN_PRE_EMPHASIS_0:
2772 default:
2773 signal_levels |= DP_PRE_EMPHASIS_0;
2774 break;
2775 case DP_TRAIN_PRE_EMPHASIS_3_5:
2776 signal_levels |= DP_PRE_EMPHASIS_3_5;
2777 break;
2778 case DP_TRAIN_PRE_EMPHASIS_6:
2779 signal_levels |= DP_PRE_EMPHASIS_6;
2780 break;
2781 case DP_TRAIN_PRE_EMPHASIS_9_5:
2782 signal_levels |= DP_PRE_EMPHASIS_9_5;
2783 break;
2784 }
2785 return signal_levels;
2786}
2787
e3421a18
ZW		 2788/* Gen6's DP voltage swing and pre-emphasis control */
2789static uint32_t
2790intel_gen6_edp_signal_levels(uint8_t train_set)
2791{
3c5a62b5
YL		 2792 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2793 DP_TRAIN_PRE_EMPHASIS_MASK);
2794 switch (signal_levels) {
e3421a18 2795 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2796 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2797 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2798 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2799 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2800 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2801 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2802 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2803 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2804 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2805 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2806 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2807 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2808 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2809 default:
3c5a62b5
YL		 2810 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2811 "0x%x\n", signal_levels);
2812 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2813 }
2814}
2815
1a2eb460
KP		 2816/* Gen7's DP voltage swing and pre-emphasis control */
2817static uint32_t
2818intel_gen7_edp_signal_levels(uint8_t train_set)
2819{
2820 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2821 DP_TRAIN_PRE_EMPHASIS_MASK);
2822 switch (signal_levels) {
2823 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2824 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2825 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2826 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2827 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2828 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2829
2830 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2831 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2832 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2833 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2834
2835 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2836 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2837 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2838 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2839
2840 default:
2841 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2842 "0x%x\n", signal_levels);
2843 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2844 }
2845}
2846
d6c0d722
PZ		 2847/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2848static uint32_t
f0a3424e 2849intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2850{
d6c0d722
PZ		 2851 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2852 DP_TRAIN_PRE_EMPHASIS_MASK);
2853 switch (signal_levels) {
2854 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2855 return DDI_BUF_EMP_400MV_0DB_HSW;
2856 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2857 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2858 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2859 return DDI_BUF_EMP_400MV_6DB_HSW;
2860 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2861 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2862
d6c0d722
PZ		 2863 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2864 return DDI_BUF_EMP_600MV_0DB_HSW;
2865 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2866 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2867 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2868 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2869
d6c0d722
PZ		 2870 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2871 return DDI_BUF_EMP_800MV_0DB_HSW;
2872 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2873 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2874 default:
2875 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2876 "0x%x\n", signal_levels);
2877 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2878 }
a4fc5ed6
KP		 2879}
2880
f0a3424e
PZ		 2881/* Properly updates "DP" with the correct signal levels. */
2882static void
2883intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2884{
2885 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2886 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2887 struct drm_device *dev = intel_dig_port->base.base.dev;
2888 uint32_t signal_levels, mask;
2889 uint8_t train_set = intel_dp->train_set[0];
2890
9576c27f 2891 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 2892 signal_levels = intel_hsw_signal_levels(train_set);
2893 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 2894 } else if (IS_CHERRYVIEW(dev)) {
2895 signal_levels = intel_chv_signal_levels(intel_dp);
2896 mask = 0;
e2fa6fba
P		 2897 } else if (IS_VALLEYVIEW(dev)) {
2898 signal_levels = intel_vlv_signal_levels(intel_dp);
2899 mask = 0;
bc7d38a4 2900 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2901 signal_levels = intel_gen7_edp_signal_levels(train_set);
2902 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2903 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2904 signal_levels = intel_gen6_edp_signal_levels(train_set);
2905 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2906 } else {
2907 signal_levels = intel_gen4_signal_levels(train_set);
2908 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2909 }
2910
2911 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2912
2913 *DP = (*DP & ~mask) | signal_levels;
2914}
2915
a4fc5ed6 2916static bool
ea5b213a 2917intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2918 uint32_t *DP,
58e10eb9 2919 uint8_t dp_train_pat)
a4fc5ed6 2920{
174edf1f
PZ		 2921 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2922 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2923 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2924 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2925 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2926 int ret, len;
a4fc5ed6 2927
22b8bf17 2928 if (HAS_DDI(dev)) {
3ab9c637 2929 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2930
2931 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2932 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2933 else
2934 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2935
2936 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2937 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2938 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2939 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2940
2941 break;
2942 case DP_TRAINING_PATTERN_1:
2943 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2944 break;
2945 case DP_TRAINING_PATTERN_2:
2946 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2947 break;
2948 case DP_TRAINING_PATTERN_3:
2949 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2950 break;
2951 }
174edf1f 2952 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2953
bc7d38a4 2954 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2955 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2956
2957 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2958 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2959 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2960 break;
2961 case DP_TRAINING_PATTERN_1:
70aff66c 2962 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2963 break;
2964 case DP_TRAINING_PATTERN_2:
70aff66c 2965 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2966 break;
2967 case DP_TRAINING_PATTERN_3:
2968 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2969 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2970 break;
2971 }
2972
2973 } else {
70aff66c 2974 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2975
2976 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2977 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2978 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2979 break;
2980 case DP_TRAINING_PATTERN_1:
70aff66c 2981 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2982 break;
2983 case DP_TRAINING_PATTERN_2:
70aff66c 2984 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2985 break;
2986 case DP_TRAINING_PATTERN_3:
2987 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2988 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2989 break;
2990 }
2991 }
2992
70aff66c 2993 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2994 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2995
2cdfe6c8
JN		 2996 buf[0] = dp_train_pat;
2997 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2998 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2999 /* don't write DP_TRAINING_LANEx_SET on disable */
3000 len = 1;
3001 } else {
3002 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3003 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3004 len = intel_dp->lane_count + 1;
47ea7542 3005 }
a4fc5ed6 3006
9d1a1031
JN		 3007 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3008 buf, len);
2cdfe6c8
JN		 3009
3010 return ret == len;
a4fc5ed6
KP		 3011}
3012
70aff66c
JN		 3013static bool
3014intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3015 uint8_t dp_train_pat)
3016{
953d22e8 3017 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3018 intel_dp_set_signal_levels(intel_dp, DP);
3019 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3020}
3021
3022static bool
3023intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3024 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3025{
3026 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3027 struct drm_device *dev = intel_dig_port->base.base.dev;
3028 struct drm_i915_private *dev_priv = dev->dev_private;
3029 int ret;
3030
3031 intel_get_adjust_train(intel_dp, link_status);
3032 intel_dp_set_signal_levels(intel_dp, DP);
3033
3034 I915_WRITE(intel_dp->output_reg, *DP);
3035 POSTING_READ(intel_dp->output_reg);
3036
9d1a1031
JN		 3037 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3038 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3039
3040 return ret == intel_dp->lane_count;
3041}
3042
3ab9c637
ID		 3043static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3044{
3045 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3046 struct drm_device *dev = intel_dig_port->base.base.dev;
3047 struct drm_i915_private *dev_priv = dev->dev_private;
3048 enum port port = intel_dig_port->port;
3049 uint32_t val;
3050
3051 if (!HAS_DDI(dev))
3052 return;
3053
3054 val = I915_READ(DP_TP_CTL(port));
3055 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3056 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3057 I915_WRITE(DP_TP_CTL(port), val);
3058
3059 /*
3060 * On PORT_A we can have only eDP in SST mode. There the only reason
3061 * we need to set idle transmission mode is to work around a HW issue
3062 * where we enable the pipe while not in idle link-training mode.
3063 * In this case there is requirement to wait for a minimum number of
3064 * idle patterns to be sent.
3065 */
3066 if (port == PORT_A)
3067 return;
3068
3069 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3070 1))
3071 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3072}
3073
33a34e4e 3074/* Enable corresponding port and start training pattern 1 */
c19b0669 3075void
33a34e4e 3076intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3077{
da63a9f2 3078 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3079 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3080 int i;
3081 uint8_t voltage;
cdb0e95b 3082 int voltage_tries, loop_tries;
ea5b213a 3083 uint32_t DP = intel_dp->DP;
6aba5b6c 3084 uint8_t link_config[2];
a4fc5ed6 3085
affa9354 3086 if (HAS_DDI(dev))
c19b0669
PZ		 3087 intel_ddi_prepare_link_retrain(encoder);
3088
3cf2efb1 3089 /* Write the link configuration data */
6aba5b6c
JN		 3090 link_config[0] = intel_dp->link_bw;
3091 link_config[1] = intel_dp->lane_count;
3092 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3093 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3094 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3095
3096 link_config[0] = 0;
3097 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3098 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3099
3100 DP |= DP_PORT_EN;
1a2eb460 3101
70aff66c
JN		 3102 /* clock recovery */
3103 if (!intel_dp_reset_link_train(intel_dp, &DP,
3104 DP_TRAINING_PATTERN_1 |
3105 DP_LINK_SCRAMBLING_DISABLE)) {
3106 DRM_ERROR("failed to enable link training\n");
3107 return;
3108 }
3109
a4fc5ed6 3110 voltage = 0xff;
cdb0e95b
KP		 3111 voltage_tries = 0;
3112 loop_tries = 0;
a4fc5ed6 3113 for (;;) {
70aff66c 3114 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3115
a7c9655f 3116 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3117 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3118 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3119 break;
93f62dad 3120 }
a4fc5ed6 3121
01916270 3122 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3123 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3124 break;
3125 }
3126
3127 /* Check to see if we've tried the max voltage */
3128 for (i = 0; i < intel_dp->lane_count; i++)
3129 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3130 break;
3b4f819d 3131 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3132 ++loop_tries;
3133 if (loop_tries == 5) {
3def84b3 3134 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3135 break;
3136 }
70aff66c
JN		 3137 intel_dp_reset_link_train(intel_dp, &DP,
3138 DP_TRAINING_PATTERN_1 |
3139 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3140 voltage_tries = 0;
3141 continue;
3142 }
a4fc5ed6 3143
3cf2efb1 3144 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3145 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3146 ++voltage_tries;
b06fbda3 3147 if (voltage_tries == 5) {
3def84b3 3148 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3149 break;
3150 }
3151 } else
3152 voltage_tries = 0;
3153 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3154
70aff66c
JN		 3155 /* Update training set as requested by target */
3156 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3157 DRM_ERROR("failed to update link training\n");
3158 break;
3159 }
a4fc5ed6
KP		 3160 }
3161
33a34e4e
JB		 3162 intel_dp->DP = DP;
3163}
3164
c19b0669 3165void
33a34e4e
JB		 3166intel_dp_complete_link_train(struct intel_dp *intel_dp)
3167{
33a34e4e 3168 bool channel_eq = false;
37f80975 3169 int tries, cr_tries;
33a34e4e 3170 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3171 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3172
3173 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3174 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3175 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3176
a4fc5ed6 3177 /* channel equalization */
70aff66c 3178 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3179 training_pattern |
70aff66c
JN		 3180 DP_LINK_SCRAMBLING_DISABLE)) {
3181 DRM_ERROR("failed to start channel equalization\n");
3182 return;
3183 }
3184
a4fc5ed6 3185 tries = 0;
37f80975 3186 cr_tries = 0;
a4fc5ed6
KP		 3187 channel_eq = false;
3188 for (;;) {
70aff66c 3189 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3190
37f80975
JB		 3191 if (cr_tries > 5) {
3192 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3193 break;
3194 }
3195
a7c9655f 3196 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3197 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3198 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3199 break;
70aff66c 3200 }
a4fc5ed6 3201
37f80975 3202 /* Make sure clock is still ok */
01916270 3203 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3204 intel_dp_start_link_train(intel_dp);
70aff66c 3205 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3206 training_pattern |
70aff66c 3207 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3208 cr_tries++;
3209 continue;
3210 }
3211
1ffdff13 3212 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3213 channel_eq = true;
3214 break;
3215 }
a4fc5ed6 3216
37f80975
JB		 3217 /* Try 5 times, then try clock recovery if that fails */
3218 if (tries > 5) {
3219 intel_dp_link_down(intel_dp);
3220 intel_dp_start_link_train(intel_dp);
70aff66c 3221 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3222 training_pattern |
70aff66c 3223 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3224 tries = 0;
3225 cr_tries++;
3226 continue;
3227 }
a4fc5ed6 3228
70aff66c
JN		 3229 /* Update training set as requested by target */
3230 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3231 DRM_ERROR("failed to update link training\n");
3232 break;
3233 }
3cf2efb1 3234 ++tries;
869184a6 3235 }
3cf2efb1 3236
3ab9c637
ID		 3237 intel_dp_set_idle_link_train(intel_dp);
3238
3239 intel_dp->DP = DP;
3240
d6c0d722 3241 if (channel_eq)
07f42258 3242 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3243
3ab9c637
ID		 3244}
3245
3246void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3247{
70aff66c 3248 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3249 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3250}
3251
3252static void
ea5b213a 3253intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3254{
da63a9f2 3255 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3256 enum port port = intel_dig_port->port;
da63a9f2 3257 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3258 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3259 struct intel_crtc *intel_crtc =
3260 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3261 uint32_t DP = intel_dp->DP;
a4fc5ed6 3262
bc76e320 3263 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3264 return;
3265
0c33d8d7 3266 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3267 return;
3268
28c97730 3269 DRM_DEBUG_KMS("\n");
32f9d658 3270
bc7d38a4 3271 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3272 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3273 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 3274 } else {
3275 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3276 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3277 }
fe255d00 3278 POSTING_READ(intel_dp->output_reg);
5eb08b69 3279
493a7081 3280 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3281 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3282 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3283
5bddd17f
EA		 3284 /* Hardware workaround: leaving our transcoder select
3285 * set to transcoder B while it's off will prevent the
3286 * corresponding HDMI output on transcoder A.
3287 *
3288 * Combine this with another hardware workaround:
3289 * transcoder select bit can only be cleared while the
3290 * port is enabled.
3291 */
3292 DP &= ~DP_PIPEB_SELECT;
3293 I915_WRITE(intel_dp->output_reg, DP);
3294
3295 /* Changes to enable or select take place the vblank
3296 * after being written.
3297 */
ff50afe9
DV		 3298 if (WARN_ON(crtc == NULL)) {
3299 /* We should never try to disable a port without a crtc
3300 * attached. For paranoia keep the code around for a
3301 * bit. */
31acbcc4
CW		 3302 POSTING_READ(intel_dp->output_reg);
3303 msleep(50);
3304 } else
ab527efc 3305 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3306 }
3307
832afda6 3308 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3309 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3310 POSTING_READ(intel_dp->output_reg);
f01eca2e 3311 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3312}
3313
26d61aad
KP		 3314static bool
3315intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3316{
a031d709
RV		 3317 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3318 struct drm_device *dev = dig_port->base.base.dev;
3319 struct drm_i915_private *dev_priv = dev->dev_private;
3320
577c7a50
DL		 3321 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3322
9d1a1031
JN		 3323 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3324 sizeof(intel_dp->dpcd)) < 0)
edb39244 3325 return false; /* aux transfer failed */
92fd8fd1 3326
577c7a50
DL		 3327 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3328 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3329 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3330
edb39244
AJ		 3331 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3332 return false; /* DPCD not present */
3333
2293bb5c
SK		 3334 /* Check if the panel supports PSR */
3335 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3336 if (is_edp(intel_dp)) {
9d1a1031
JN		 3337 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3338 intel_dp->psr_dpcd,
3339 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3340 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3341 dev_priv->psr.sink_support = true;
50003939 3342 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3343 }
50003939
JN		 3344 }
3345
06ea66b6
TP		 3346 /* Training Pattern 3 support */
3347 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3348 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3349 intel_dp->use_tps3 = true;
3350 DRM_DEBUG_KMS("Displayport TPS3 supported");
3351 } else
3352 intel_dp->use_tps3 = false;
3353
edb39244
AJ		 3354 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3355 DP_DWN_STRM_PORT_PRESENT))
3356 return true; /* native DP sink */
3357
3358 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3359 return true; /* no per-port downstream info */
3360
9d1a1031
JN		 3361 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3362 intel_dp->downstream_ports,
3363 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3364 return false; /* downstream port status fetch failed */
3365
3366 return true;
92fd8fd1
KP		 3367}
3368
0d198328
AJ		 3369static void
3370intel_dp_probe_oui(struct intel_dp *intel_dp)
3371{
3372 u8 buf[3];
3373
3374 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3375 return;
3376
24f3e092 3377 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3378
9d1a1031 3379 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3380 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3381 buf[0], buf[1], buf[2]);
3382
9d1a1031 3383 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3384 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3385 buf[0], buf[1], buf[2]);
351cfc34 3386
4be73780 3387 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3388}
3389
0e32b39c
DA		 3390static bool
3391intel_dp_probe_mst(struct intel_dp *intel_dp)
3392{
3393 u8 buf[1];
3394
3395 if (!intel_dp->can_mst)
3396 return false;
3397
3398 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3399 return false;
3400
3401 _edp_panel_vdd_on(intel_dp);
3402 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3403 if (buf[0] & DP_MST_CAP) {
3404 DRM_DEBUG_KMS("Sink is MST capable\n");
3405 intel_dp->is_mst = true;
3406 } else {
3407 DRM_DEBUG_KMS("Sink is not MST capable\n");
3408 intel_dp->is_mst = false;
3409 }
3410 }
3411 edp_panel_vdd_off(intel_dp, false);
3412
3413 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3414 return intel_dp->is_mst;
3415}
3416
d2e216d0
RV		 3417int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3418{
3419 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3420 struct drm_device *dev = intel_dig_port->base.base.dev;
3421 struct intel_crtc *intel_crtc =
3422 to_intel_crtc(intel_dig_port->base.base.crtc);
3423 u8 buf[1];
3424
9d1a1031 3425 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3426 return -EAGAIN;
3427
3428 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3429 return -ENOTTY;
3430
9d1a1031
JN		 3431 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3432 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3433 return -EAGAIN;
3434
3435 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3436 intel_wait_for_vblank(dev, intel_crtc->pipe);
3437 intel_wait_for_vblank(dev, intel_crtc->pipe);
3438
9d1a1031 3439 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3440 return -EAGAIN;
3441
9d1a1031 3442 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3443 return 0;
3444}
3445
a60f0e38
JB		 3446static bool
3447intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3448{
9d1a1031
JN		 3449 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3450 DP_DEVICE_SERVICE_IRQ_VECTOR,
3451 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3452}
3453
0e32b39c
DA		 3454static bool
3455intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3456{
3457 int ret;
3458
3459 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3460 DP_SINK_COUNT_ESI,
3461 sink_irq_vector, 14);
3462 if (ret != 14)
3463 return false;
3464
3465 return true;
3466}
3467
a60f0e38
JB		 3468static void
3469intel_dp_handle_test_request(struct intel_dp *intel_dp)
3470{
3471 /* NAK by default */
9d1a1031 3472 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3473}
3474
0e32b39c
DA		 3475static int
3476intel_dp_check_mst_status(struct intel_dp *intel_dp)
3477{
3478 bool bret;
3479
3480 if (intel_dp->is_mst) {
3481 u8 esi[16] = { 0 };
3482 int ret = 0;
3483 int retry;
3484 bool handled;
3485 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3486go_again:
3487 if (bret == true) {
3488
3489 /* check link status - esi[10] = 0x200c */
3490 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3491 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3492 intel_dp_start_link_train(intel_dp);
3493 intel_dp_complete_link_train(intel_dp);
3494 intel_dp_stop_link_train(intel_dp);
3495 }
3496
3497 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3498 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3499
3500 if (handled) {
3501 for (retry = 0; retry < 3; retry++) {
3502 int wret;
3503 wret = drm_dp_dpcd_write(&intel_dp->aux,
3504 DP_SINK_COUNT_ESI+1,
3505 &esi[1], 3);
3506 if (wret == 3) {
3507 break;
3508 }
3509 }
3510
3511 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3512 if (bret == true) {
3513 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3514 goto go_again;
3515 }
3516 } else
3517 ret = 0;
3518
3519 return ret;
3520 } else {
3521 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3522 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3523 intel_dp->is_mst = false;
3524 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3525 /* send a hotplug event */
3526 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3527 }
3528 }
3529 return -EINVAL;
3530}
3531
a4fc5ed6
KP		 3532/*
3533 * According to DP spec
3534 * 5.1.2:
3535 * 1. Read DPCD
3536 * 2. Configure link according to Receiver Capabilities
3537 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3538 * 4. Check link status on receipt of hot-plug interrupt
3539 */
00c09d70 3540void
ea5b213a 3541intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3542{
5b215bcf 3543 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3544 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3545 u8 sink_irq_vector;
93f62dad 3546 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3547
5b215bcf
DA		 3548 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3549
da63a9f2 3550 if (!intel_encoder->connectors_active)
d2b996ac 3551 return;
59cd09e1 3552
da63a9f2 3553 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3554 return;
3555
1a125d8a
ID		 3556 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3557 return;
3558
92fd8fd1 3559 /* Try to read receiver status if the link appears to be up */
93f62dad 3560 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3561 return;
3562 }
3563
92fd8fd1 3564 /* Now read the DPCD to see if it's actually running */
26d61aad 3565 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3566 return;
3567 }
3568
a60f0e38
JB		 3569 /* Try to read the source of the interrupt */
3570 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3571 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3572 /* Clear interrupt source */
9d1a1031
JN		 3573 drm_dp_dpcd_writeb(&intel_dp->aux,
3574 DP_DEVICE_SERVICE_IRQ_VECTOR,
3575 sink_irq_vector);
a60f0e38
JB		 3576
3577 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3578 intel_dp_handle_test_request(intel_dp);
3579 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3580 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3581 }
3582
1ffdff13 3583 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3584 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3585 intel_encoder->base.name);
33a34e4e
JB		 3586 intel_dp_start_link_train(intel_dp);
3587 intel_dp_complete_link_train(intel_dp);
3ab9c637 3588 intel_dp_stop_link_train(intel_dp);
33a34e4e 3589 }
a4fc5ed6 3590}
a4fc5ed6 3591
caf9ab24 3592/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3593static enum drm_connector_status
26d61aad 3594intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3595{
caf9ab24 3596 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3597 uint8_t type;
3598
3599 if (!intel_dp_get_dpcd(intel_dp))
3600 return connector_status_disconnected;
3601
3602 /* if there's no downstream port, we're done */
3603 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3604 return connector_status_connected;
caf9ab24
AJ		 3605
3606 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3607 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3608 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3609 uint8_t reg;
9d1a1031
JN		 3610
3611 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3612 &reg, 1) < 0)
caf9ab24 3613 return connector_status_unknown;
9d1a1031 3614
23235177
AJ		 3615 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3616 : connector_status_disconnected;
caf9ab24
AJ		 3617 }
3618
3619 /* If no HPD, poke DDC gently */
0b99836f 3620 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3621 return connector_status_connected;
caf9ab24
AJ		 3622
3623 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3624 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3625 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3626 if (type == DP_DS_PORT_TYPE_VGA ||
3627 type == DP_DS_PORT_TYPE_NON_EDID)
3628 return connector_status_unknown;
3629 } else {
3630 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3631 DP_DWN_STRM_PORT_TYPE_MASK;
3632 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3633 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3634 return connector_status_unknown;
3635 }
caf9ab24
AJ		 3636
3637 /* Anything else is out of spec, warn and ignore */
3638 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3639 return connector_status_disconnected;
71ba9000
AJ		 3640}
3641
5eb08b69 3642static enum drm_connector_status
a9756bb5 3643ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3644{
30add22d 3645 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3646 struct drm_i915_private *dev_priv = dev->dev_private;
3647 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3648 enum drm_connector_status status;
3649
fe16d949
CW		 3650 /* Can't disconnect eDP, but you can close the lid... */
3651 if (is_edp(intel_dp)) {
30add22d 3652 status = intel_panel_detect(dev);
fe16d949
CW		 3653 if (status == connector_status_unknown)
3654 status = connector_status_connected;
3655 return status;
3656 }
01cb9ea6 3657
1b469639
DL		 3658 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3659 return connector_status_disconnected;
3660
26d61aad 3661 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3662}
3663
2a592bec
DA		 3664static int g4x_digital_port_connected(struct drm_device *dev,
3665 struct intel_digital_port *intel_dig_port)
a4fc5ed6 3666{
a4fc5ed6 3667 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 3668 uint32_t bit;
5eb08b69 3669
232a6ee9
TP		 3670 if (IS_VALLEYVIEW(dev)) {
3671 switch (intel_dig_port->port) {
3672 case PORT_B:
3673 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3674 break;
3675 case PORT_C:
3676 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3677 break;
3678 case PORT_D:
3679 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3680 break;
3681 default:
2a592bec 3682 return -EINVAL;
232a6ee9
TP		 3683 }
3684 } else {
3685 switch (intel_dig_port->port) {
3686 case PORT_B:
3687 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3688 break;
3689 case PORT_C:
3690 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3691 break;
3692 case PORT_D:
3693 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3694 break;
3695 default:
2a592bec 3696 return -EINVAL;
232a6ee9 3697 }
a4fc5ed6
KP		 3698 }
3699
10f76a38 3700 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 3701 return 0;
3702 return 1;
3703}
3704
3705static enum drm_connector_status
3706g4x_dp_detect(struct intel_dp *intel_dp)
3707{
3708 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3709 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3710 int ret;
3711
3712 /* Can't disconnect eDP, but you can close the lid... */
3713 if (is_edp(intel_dp)) {
3714 enum drm_connector_status status;
3715
3716 status = intel_panel_detect(dev);
3717 if (status == connector_status_unknown)
3718 status = connector_status_connected;
3719 return status;
3720 }
3721
3722 ret = g4x_digital_port_connected(dev, intel_dig_port);
3723 if (ret == -EINVAL)
3724 return connector_status_unknown;
3725 else if (ret == 0)
a4fc5ed6
KP		 3726 return connector_status_disconnected;
3727
26d61aad 3728 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3729}
3730
8c241fef
KP		 3731static struct edid *
3732intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3733{
9cd300e0 3734 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3735
9cd300e0
JN		 3736 /* use cached edid if we have one */
3737 if (intel_connector->edid) {
9cd300e0
JN		 3738 /* invalid edid */
3739 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3740 return NULL;
3741
55e9edeb 3742 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3743 }
8c241fef 3744
9cd300e0 3745 return drm_get_edid(connector, adapter);
8c241fef
KP		 3746}
3747
3748static int
3749intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3750{
9cd300e0 3751 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3752
9cd300e0
JN		 3753 /* use cached edid if we have one */
3754 if (intel_connector->edid) {
3755 /* invalid edid */
3756 if (IS_ERR(intel_connector->edid))
3757 return 0;
3758
3759 return intel_connector_update_modes(connector,
3760 intel_connector->edid);
d6f24d0f
JB		 3761 }
3762
9cd300e0 3763 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3764}
3765
a9756bb5
ZW		 3766static enum drm_connector_status
3767intel_dp_detect(struct drm_connector *connector, bool force)
3768{
3769 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3770 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3771 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3772 struct drm_device *dev = connector->dev;
c8c8fb33 3773 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3774 enum drm_connector_status status;
671dedd2 3775 enum intel_display_power_domain power_domain;
a9756bb5 3776 struct edid *edid = NULL;
0e32b39c 3777 bool ret;
a9756bb5 3778
671dedd2
ID		 3779 power_domain = intel_display_port_power_domain(intel_encoder);
3780 intel_display_power_get(dev_priv, power_domain);
3781
164c8598 3782 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 3783 connector->base.id, connector->name);
164c8598 3784
0e32b39c
DA		 3785 if (intel_dp->is_mst) {
3786 /* MST devices are disconnected from a monitor POV */
3787 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3788 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3789 status = connector_status_disconnected;
3790 goto out;
3791 }
3792
a9756bb5
ZW		 3793 intel_dp->has_audio = false;
3794
3795 if (HAS_PCH_SPLIT(dev))
3796 status = ironlake_dp_detect(intel_dp);
3797 else
3798 status = g4x_dp_detect(intel_dp);
1b9be9d0 3799
a9756bb5 3800 if (status != connector_status_connected)
c8c8fb33 3801 goto out;
a9756bb5 3802
0d198328
AJ		 3803 intel_dp_probe_oui(intel_dp);
3804
0e32b39c
DA		 3805 ret = intel_dp_probe_mst(intel_dp);
3806 if (ret) {
3807 /* if we are in MST mode then this connector
3808 won't appear connected or have anything with EDID on it */
3809 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3810 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3811 status = connector_status_disconnected;
3812 goto out;
3813 }
3814
c3e5f67b
DV		 3815 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3816 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3817 } else {
0b99836f 3818 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3819 if (edid) {
3820 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3821 kfree(edid);
3822 }
a9756bb5
ZW		 3823 }
3824
d63885da
PZ		 3825 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3826 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3827 status = connector_status_connected;
3828
3829out:
671dedd2 3830 intel_display_power_put(dev_priv, power_domain);
c8c8fb33 3831 return status;
a4fc5ed6
KP		 3832}
3833
3834static int intel_dp_get_modes(struct drm_connector *connector)
3835{
df0e9248 3836 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3837 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3838 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3839 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3840 struct drm_device *dev = connector->dev;
671dedd2
ID		 3841 struct drm_i915_private *dev_priv = dev->dev_private;
3842 enum intel_display_power_domain power_domain;
32f9d658 3843 int ret;
a4fc5ed6
KP		 3844
3845 /* We should parse the EDID data and find out if it has an audio sink
3846 */
3847
671dedd2
ID		 3848 power_domain = intel_display_port_power_domain(intel_encoder);
3849 intel_display_power_get(dev_priv, power_domain);
3850
0b99836f 3851 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3852 intel_display_power_put(dev_priv, power_domain);
f8779fda 3853 if (ret)
32f9d658
ZW		 3854 return ret;
3855
f8779fda 3856 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3857 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3858 struct drm_display_mode *mode;
dd06f90e
JN		 3859 mode = drm_mode_duplicate(dev,
3860 intel_connector->panel.fixed_mode);
f8779fda 3861 if (mode) {
32f9d658
ZW		 3862 drm_mode_probed_add(connector, mode);
3863 return 1;
3864 }
3865 }
3866 return 0;
a4fc5ed6
KP		 3867}
3868
1aad7ac0
CW		 3869static bool
3870intel_dp_detect_audio(struct drm_connector *connector)
3871{
3872 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3873 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3874 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3875 struct drm_device *dev = connector->dev;
3876 struct drm_i915_private *dev_priv = dev->dev_private;
3877 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3878 struct edid *edid;
3879 bool has_audio = false;
3880
671dedd2
ID		 3881 power_domain = intel_display_port_power_domain(intel_encoder);
3882 intel_display_power_get(dev_priv, power_domain);
3883
0b99836f 3884 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3885 if (edid) {
3886 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3887 kfree(edid);
3888 }
3889
671dedd2
ID		 3890 intel_display_power_put(dev_priv, power_domain);
3891
1aad7ac0
CW		 3892 return has_audio;
3893}
3894
f684960e
CW		 3895static int
3896intel_dp_set_property(struct drm_connector *connector,
3897 struct drm_property *property,
3898 uint64_t val)
3899{
e953fd7b 3900 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3901 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3902 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3903 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3904 int ret;
3905
662595df 3906 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3907 if (ret)
3908 return ret;
3909
3f43c48d 3910 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3911 int i = val;
3912 bool has_audio;
3913
3914 if (i == intel_dp->force_audio)
f684960e
CW		 3915 return 0;
3916
1aad7ac0 3917 intel_dp->force_audio = i;
f684960e 3918
c3e5f67b 3919 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3920 has_audio = intel_dp_detect_audio(connector);
3921 else
c3e5f67b 3922 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3923
3924 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3925 return 0;
3926
1aad7ac0 3927 intel_dp->has_audio = has_audio;
f684960e
CW		 3928 goto done;
3929 }
3930
e953fd7b 3931 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3932 bool old_auto = intel_dp->color_range_auto;
3933 uint32_t old_range = intel_dp->color_range;
3934
55bc60db
VS		 3935 switch (val) {
3936 case INTEL_BROADCAST_RGB_AUTO:
3937 intel_dp->color_range_auto = true;
3938 break;
3939 case INTEL_BROADCAST_RGB_FULL:
3940 intel_dp->color_range_auto = false;
3941 intel_dp->color_range = 0;
3942 break;
3943 case INTEL_BROADCAST_RGB_LIMITED:
3944 intel_dp->color_range_auto = false;
3945 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3946 break;
3947 default:
3948 return -EINVAL;
3949 }
ae4edb80
DV		 3950
3951 if (old_auto == intel_dp->color_range_auto &&
3952 old_range == intel_dp->color_range)
3953 return 0;
3954
e953fd7b
CW		 3955 goto done;
3956 }
3957
53b41837
YN		 3958 if (is_edp(intel_dp) &&
3959 property == connector->dev->mode_config.scaling_mode_property) {
3960 if (val == DRM_MODE_SCALE_NONE) {
3961 DRM_DEBUG_KMS("no scaling not supported\n");
3962 return -EINVAL;
3963 }
3964
3965 if (intel_connector->panel.fitting_mode == val) {
3966 /* the eDP scaling property is not changed */
3967 return 0;
3968 }
3969 intel_connector->panel.fitting_mode = val;
3970
3971 goto done;
3972 }
3973
f684960e
CW		 3974 return -EINVAL;
3975
3976done:
c0c36b94
CW		 3977 if (intel_encoder->base.crtc)
3978 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3979
3980 return 0;
3981}
3982
a4fc5ed6 3983static void
73845adf 3984intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3985{
1d508706 3986 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3987
9cd300e0
JN		 3988 if (!IS_ERR_OR_NULL(intel_connector->edid))
3989 kfree(intel_connector->edid);
3990
acd8db10
PZ		 3991 /* Can't call is_edp() since the encoder may have been destroyed
3992 * already. */
3993 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3994 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3995
a4fc5ed6 3996 drm_connector_cleanup(connector);
55f78c43 3997 kfree(connector);
a4fc5ed6
KP		 3998}
3999
00c09d70 4000void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4001{
da63a9f2
PZ		 4002 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4003 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 4004 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 4005
4f71d0cb 4006 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4007 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4008 drm_encoder_cleanup(encoder);
bd943159
KP		 4009 if (is_edp(intel_dp)) {
4010 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4011 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4012 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4013 drm_modeset_unlock(&dev->mode_config.connection_mutex);
01527b31
CT		 4014 if (intel_dp->edp_notifier.notifier_call) {
4015 unregister_reboot_notifier(&intel_dp->edp_notifier);
4016 intel_dp->edp_notifier.notifier_call = NULL;
4017 }
bd943159 4018 }
da63a9f2 4019 kfree(intel_dig_port);
24d05927
DV		 4020}
4021
07f9cd0b
ID		 4022static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4023{
4024 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4025
4026 if (!is_edp(intel_dp))
4027 return;
4028
4029 edp_panel_vdd_off_sync(intel_dp);
4030}
4031
6d93c0c4
ID		 4032static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4033{
4034 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4035}
4036
a4fc5ed6 4037static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4038 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 4039 .detect = intel_dp_detect,
4040 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4041 .set_property = intel_dp_set_property,
73845adf 4042 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4043};
4044
4045static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4046 .get_modes = intel_dp_get_modes,
4047 .mode_valid = intel_dp_mode_valid,
df0e9248 4048 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4049};
4050
a4fc5ed6 4051static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4052 .reset = intel_dp_encoder_reset,
24d05927 4053 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4054};
4055
0e32b39c 4056void
21d40d37 4057intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4058{
0e32b39c 4059 return;
c8110e52 4060}
6207937d 4061
13cf5504
DA		 4062bool
4063intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4064{
4065 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4066 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4067 struct drm_device *dev = intel_dig_port->base.base.dev;
4068 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4069 enum intel_display_power_domain power_domain;
4070 bool ret = true;
4071
0e32b39c
DA		 4072 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4073 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4074
0e32b39c
DA		 4075 DRM_DEBUG_KMS("got hpd irq on port %d - %s\n", intel_dig_port->port,
4076 long_hpd ? "long" : "short");
13cf5504 4077
1c767b33
ID		 4078 power_domain = intel_display_port_power_domain(intel_encoder);
4079 intel_display_power_get(dev_priv, power_domain);
4080
0e32b39c 4081 if (long_hpd) {
2a592bec
DA		 4082
4083 if (HAS_PCH_SPLIT(dev)) {
4084 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4085 goto mst_fail;
4086 } else {
4087 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4088 goto mst_fail;
4089 }
0e32b39c
DA		 4090
4091 if (!intel_dp_get_dpcd(intel_dp)) {
4092 goto mst_fail;
4093 }
4094
4095 intel_dp_probe_oui(intel_dp);
4096
4097 if (!intel_dp_probe_mst(intel_dp))
4098 goto mst_fail;
4099
4100 } else {
4101 if (intel_dp->is_mst) {
1c767b33 4102 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4103 goto mst_fail;
4104 }
4105
4106 if (!intel_dp->is_mst) {
4107 /*
4108 * we'll check the link status via the normal hot plug path later -
4109 * but for short hpds we should check it now
4110 */
5b215bcf 4111 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4112 intel_dp_check_link_status(intel_dp);
5b215bcf 4113 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4114 }
4115 }
1c767b33
ID		 4116 ret = false;
4117 goto put_power;
0e32b39c
DA		 4118mst_fail:
4119 /* if we were in MST mode, and device is not there get out of MST mode */
4120 if (intel_dp->is_mst) {
4121 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4122 intel_dp->is_mst = false;
4123 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4124 }
1c767b33
ID		 4125put_power:
4126 intel_display_power_put(dev_priv, power_domain);
4127
4128 return ret;
13cf5504
DA		 4129}
4130
e3421a18
ZW		 4131/* Return which DP Port should be selected for Transcoder DP control */
4132int
0206e353 4133intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4134{
4135 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4136 struct intel_encoder *intel_encoder;
4137 struct intel_dp *intel_dp;
e3421a18 4138
fa90ecef
PZ		 4139 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4140 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4141
fa90ecef
PZ		 4142 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4143 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4144 return intel_dp->output_reg;
e3421a18 4145 }
ea5b213a 4146
e3421a18
ZW		 4147 return -1;
4148}
4149
36e83a18 4150/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4151bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4152{
4153 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4154 union child_device_config *p_child;
36e83a18 4155 int i;
5d8a7752
VS		 4156 static const short port_mapping[] = {
4157 [PORT_B] = PORT_IDPB,
4158 [PORT_C] = PORT_IDPC,
4159 [PORT_D] = PORT_IDPD,
4160 };
36e83a18 4161
3b32a35b
VS		 4162 if (port == PORT_A)
4163 return true;
4164
41aa3448 4165 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4166 return false;
4167
41aa3448
RV		 4168 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4169 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4170
5d8a7752 4171 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4172 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4173 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4174 return true;
4175 }
4176 return false;
4177}
4178
0e32b39c 4179void
f684960e
CW		 4180intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4181{
53b41837
YN		 4182 struct intel_connector *intel_connector = to_intel_connector(connector);
4183
3f43c48d 4184 intel_attach_force_audio_property(connector);
e953fd7b 4185 intel_attach_broadcast_rgb_property(connector);
55bc60db 4186 intel_dp->color_range_auto = true;
53b41837
YN		 4187
4188 if (is_edp(intel_dp)) {
4189 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4190 drm_object_attach_property(
4191 &connector->base,
53b41837 4192 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4193 DRM_MODE_SCALE_ASPECT);
4194 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4195 }
f684960e
CW		 4196}
4197
dada1a9f
ID		 4198static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4199{
4200 intel_dp->last_power_cycle = jiffies;
4201 intel_dp->last_power_on = jiffies;
4202 intel_dp->last_backlight_off = jiffies;
4203}
4204
67a54566
DV		 4205static void
4206intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4207 struct intel_dp *intel_dp,
4208 struct edp_power_seq *out)
67a54566
DV		 4209{
4210 struct drm_i915_private *dev_priv = dev->dev_private;
4211 struct edp_power_seq cur, vbt, spec, final;
4212 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4213 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 4214
4215 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4216 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4217 pp_on_reg = PCH_PP_ON_DELAYS;
4218 pp_off_reg = PCH_PP_OFF_DELAYS;
4219 pp_div_reg = PCH_PP_DIVISOR;
4220 } else {
bf13e81b
JN		 4221 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4222
4223 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4224 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4225 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4226 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4227 }
67a54566
DV		 4228
4229 /* Workaround: Need to write PP_CONTROL with the unlock key as
4230 * the very first thing. */
453c5420 4231 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4232 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4233
453c5420
JB		 4234 pp_on = I915_READ(pp_on_reg);
4235 pp_off = I915_READ(pp_off_reg);
4236 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4237
4238 /* Pull timing values out of registers */
4239 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4240 PANEL_POWER_UP_DELAY_SHIFT;
4241
4242 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4243 PANEL_LIGHT_ON_DELAY_SHIFT;
4244
4245 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4246 PANEL_LIGHT_OFF_DELAY_SHIFT;
4247
4248 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4249 PANEL_POWER_DOWN_DELAY_SHIFT;
4250
4251 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4252 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4253
4254 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4255 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4256
41aa3448 4257 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4258
4259 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4260 * our hw here, which are all in 100usec. */
4261 spec.t1_t3 = 210 * 10;
4262 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4263 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4264 spec.t10 = 500 * 10;
4265 /* This one is special and actually in units of 100ms, but zero
4266 * based in the hw (so we need to add 100 ms). But the sw vbt
4267 * table multiplies it with 1000 to make it in units of 100usec,
4268 * too. */
4269 spec.t11_t12 = (510 + 100) * 10;
4270
4271 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4272 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4273
4274 /* Use the max of the register settings and vbt. If both are
4275 * unset, fall back to the spec limits. */
4276#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4277 spec.field : \
4278 max(cur.field, vbt.field))
4279 assign_final(t1_t3);
4280 assign_final(t8);
4281 assign_final(t9);
4282 assign_final(t10);
4283 assign_final(t11_t12);
4284#undef assign_final
4285
4286#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4287 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4288 intel_dp->backlight_on_delay = get_delay(t8);
4289 intel_dp->backlight_off_delay = get_delay(t9);
4290 intel_dp->panel_power_down_delay = get_delay(t10);
4291 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4292#undef get_delay
4293
f30d26e4
JN		 4294 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4295 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4296 intel_dp->panel_power_cycle_delay);
4297
4298 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4299 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4300
4301 if (out)
4302 *out = final;
4303}
4304
4305static void
4306intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4307 struct intel_dp *intel_dp,
4308 struct edp_power_seq *seq)
4309{
4310 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4311 u32 pp_on, pp_off, pp_div, port_sel = 0;
4312 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4313 int pp_on_reg, pp_off_reg, pp_div_reg;
4314
4315 if (HAS_PCH_SPLIT(dev)) {
4316 pp_on_reg = PCH_PP_ON_DELAYS;
4317 pp_off_reg = PCH_PP_OFF_DELAYS;
4318 pp_div_reg = PCH_PP_DIVISOR;
4319 } else {
bf13e81b
JN		 4320 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4321
4322 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4323 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4324 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4325 }
4326
b2f19d1a
PZ		 4327 /*
4328 * And finally store the new values in the power sequencer. The
4329 * backlight delays are set to 1 because we do manual waits on them. For
4330 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4331 * we'll end up waiting for the backlight off delay twice: once when we
4332 * do the manual sleep, and once when we disable the panel and wait for
4333 * the PP_STATUS bit to become zero.
4334 */
f30d26e4 4335 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4336 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4337 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4338 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4339 /* Compute the divisor for the pp clock, simply match the Bspec
4340 * formula. */
453c5420 4341 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4342 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4343 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4344
4345 /* Haswell doesn't have any port selection bits for the panel
4346 * power sequencer any more. */
bc7d38a4 4347 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 4348 if (dp_to_dig_port(intel_dp)->port == PORT_B)
4349 port_sel = PANEL_PORT_SELECT_DPB_VLV;
4350 else
4351 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 4352 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4353 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 4354 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4355 else
a24c144c 4356 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4357 }
4358
453c5420
JB		 4359 pp_on |= port_sel;
4360
4361 I915_WRITE(pp_on_reg, pp_on);
4362 I915_WRITE(pp_off_reg, pp_off);
4363 I915_WRITE(pp_div_reg, pp_div);
67a54566 4364
67a54566 4365 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4366 I915_READ(pp_on_reg),
4367 I915_READ(pp_off_reg),
4368 I915_READ(pp_div_reg));
f684960e
CW		 4369}
4370
439d7ac0
PB		 4371void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4372{
4373 struct drm_i915_private *dev_priv = dev->dev_private;
4374 struct intel_encoder *encoder;
4375 struct intel_dp *intel_dp = NULL;
4376 struct intel_crtc_config *config = NULL;
4377 struct intel_crtc *intel_crtc = NULL;
4378 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4379 u32 reg, val;
4380 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4381
4382 if (refresh_rate <= 0) {
4383 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4384 return;
4385 }
4386
4387 if (intel_connector == NULL) {
4388 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4389 return;
4390 }
4391
1fcc9d1c
DV		 4392 /*
4393 * FIXME: This needs proper synchronization with psr state. But really
4394 * hard to tell without seeing the user of this function of this code.
4395 * Check locking and ordering once that lands.
4396 */
439d7ac0
PB		 4397 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4398 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4399 return;
4400 }
4401
4402 encoder = intel_attached_encoder(&intel_connector->base);
4403 intel_dp = enc_to_intel_dp(&encoder->base);
4404 intel_crtc = encoder->new_crtc;
4405
4406 if (!intel_crtc) {
4407 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4408 return;
4409 }
4410
4411 config = &intel_crtc->config;
4412
4413 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4414 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4415 return;
4416 }
4417
4418 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4419 index = DRRS_LOW_RR;
4420
4421 if (index == intel_dp->drrs_state.refresh_rate_type) {
4422 DRM_DEBUG_KMS(
4423 "DRRS requested for previously set RR...ignoring\n");
4424 return;
4425 }
4426
4427 if (!intel_crtc->active) {
4428 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4429 return;
4430 }
4431
4432 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4433 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4434 val = I915_READ(reg);
4435 if (index > DRRS_HIGH_RR) {
4436 val |= PIPECONF_EDP_RR_MODE_SWITCH;
4437 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
4438 } else {
4439 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4440 }
4441 I915_WRITE(reg, val);
4442 }
4443
4444 /*
4445 * mutex taken to ensure that there is no race between differnt
4446 * drrs calls trying to update refresh rate. This scenario may occur
4447 * in future when idleness detection based DRRS in kernel and
4448 * possible calls from user space to set differnt RR are made.
4449 */
4450
4451 mutex_lock(&intel_dp->drrs_state.mutex);
4452
4453 intel_dp->drrs_state.refresh_rate_type = index;
4454
4455 mutex_unlock(&intel_dp->drrs_state.mutex);
4456
4457 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4458}
4459
4f9db5b5
PB		 4460static struct drm_display_mode *
4461intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4462 struct intel_connector *intel_connector,
4463 struct drm_display_mode *fixed_mode)
4464{
4465 struct drm_connector *connector = &intel_connector->base;
4466 struct intel_dp *intel_dp = &intel_dig_port->dp;
4467 struct drm_device *dev = intel_dig_port->base.base.dev;
4468 struct drm_i915_private *dev_priv = dev->dev_private;
4469 struct drm_display_mode *downclock_mode = NULL;
4470
4471 if (INTEL_INFO(dev)->gen <= 6) {
4472 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4473 return NULL;
4474 }
4475
4476 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4477 DRM_INFO("VBT doesn't support DRRS\n");
4478 return NULL;
4479 }
4480
4481 downclock_mode = intel_find_panel_downclock
4482 (dev, fixed_mode, connector);
4483
4484 if (!downclock_mode) {
4485 DRM_INFO("DRRS not supported\n");
4486 return NULL;
4487 }
4488
439d7ac0
PB		 4489 dev_priv->drrs.connector = intel_connector;
4490
4491 mutex_init(&intel_dp->drrs_state.mutex);
4492
4f9db5b5
PB		 4493 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4494
4495 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4496 DRM_INFO("seamless DRRS supported for eDP panel.\n");
4497 return downclock_mode;
4498}
4499
aba86890
ID		 4500void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4501{
4502 struct drm_device *dev = intel_encoder->base.dev;
4503 struct drm_i915_private *dev_priv = dev->dev_private;
4504 struct intel_dp *intel_dp;
4505 enum intel_display_power_domain power_domain;
4506
4507 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4508 return;
4509
4510 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4511 if (!edp_have_panel_vdd(intel_dp))
4512 return;
4513 /*
4514 * The VDD bit needs a power domain reference, so if the bit is
4515 * already enabled when we boot or resume, grab this reference and
4516 * schedule a vdd off, so we don't hold on to the reference
4517 * indefinitely.
4518 */
4519 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4520 power_domain = intel_display_port_power_domain(intel_encoder);
4521 intel_display_power_get(dev_priv, power_domain);
4522
4523 edp_panel_vdd_schedule_off(intel_dp);
4524}
4525
ed92f0b2 4526static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4527 struct intel_connector *intel_connector,
4528 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4529{
4530 struct drm_connector *connector = &intel_connector->base;
4531 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4532 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4533 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4534 struct drm_i915_private *dev_priv = dev->dev_private;
4535 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4536 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4537 bool has_dpcd;
4538 struct drm_display_mode *scan;
4539 struct edid *edid;
4540
4f9db5b5
PB		 4541 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4542
ed92f0b2
PZ		 4543 if (!is_edp(intel_dp))
4544 return true;
4545
aba86890 4546 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 4547
ed92f0b2 4548 /* Cache DPCD and EDID for edp. */
24f3e092 4549 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4550 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 4551 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4552
4553 if (has_dpcd) {
4554 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4555 dev_priv->no_aux_handshake =
4556 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4557 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4558 } else {
4559 /* if this fails, presume the device is a ghost */
4560 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4561 return false;
4562 }
4563
4564 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 4565 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 4566
060c8778 4567 mutex_lock(&dev->mode_config.mutex);
0b99836f 4568 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4569 if (edid) {
4570 if (drm_add_edid_modes(connector, edid)) {
4571 drm_mode_connector_update_edid_property(connector,
4572 edid);
4573 drm_edid_to_eld(connector, edid);
4574 } else {
4575 kfree(edid);
4576 edid = ERR_PTR(-EINVAL);
4577 }
4578 } else {
4579 edid = ERR_PTR(-ENOENT);
4580 }
4581 intel_connector->edid = edid;
4582
4583 /* prefer fixed mode from EDID if available */
4584 list_for_each_entry(scan, &connector->probed_modes, head) {
4585 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4586 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4587 downclock_mode = intel_dp_drrs_init(
4588 intel_dig_port,
4589 intel_connector, fixed_mode);
ed92f0b2
PZ		 4590 break;
4591 }
4592 }
4593
4594 /* fallback to VBT if available for eDP */
4595 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4596 fixed_mode = drm_mode_duplicate(dev,
4597 dev_priv->vbt.lfp_lvds_vbt_mode);
4598 if (fixed_mode)
4599 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4600 }
060c8778 4601 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4602
01527b31
CT		 4603 if (IS_VALLEYVIEW(dev)) {
4604 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4605 register_reboot_notifier(&intel_dp->edp_notifier);
4606 }
4607
4f9db5b5 4608 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
ed92f0b2
PZ		 4609 intel_panel_setup_backlight(connector);
4610
4611 return true;
4612}
4613
16c25533 4614bool
f0fec3f2
PZ		 4615intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4616 struct intel_connector *intel_connector)
a4fc5ed6 4617{
f0fec3f2
PZ		 4618 struct drm_connector *connector = &intel_connector->base;
4619 struct intel_dp *intel_dp = &intel_dig_port->dp;
4620 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4621 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4622 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4623 enum port port = intel_dig_port->port;
0095e6dc 4624 struct edp_power_seq power_seq = { 0 };
0b99836f 4625 int type;
a4fc5ed6 4626
ec5b01dd
DL		 4627 /* intel_dp vfuncs */
4628 if (IS_VALLEYVIEW(dev))
4629 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4630 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4631 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4632 else if (HAS_PCH_SPLIT(dev))
4633 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4634 else
4635 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4636
153b1100
DL		 4637 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4638
0767935e
DV		 4639 /* Preserve the current hw state. */
4640 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4641 intel_dp->attached_connector = intel_connector;
3d3dc149 4642
3b32a35b 4643 if (intel_dp_is_edp(dev, port))
b329530c 4644 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4645 else
4646 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4647
f7d24902
ID		 4648 /*
4649 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4650 * for DP the encoder type can be set by the caller to
4651 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4652 */
4653 if (type == DRM_MODE_CONNECTOR_eDP)
4654 intel_encoder->type = INTEL_OUTPUT_EDP;
4655
e7281eab
ID		 4656 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4657 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4658 port_name(port));
4659
b329530c 4660 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4661 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4662
a4fc5ed6
KP		 4663 connector->interlace_allowed = true;
4664 connector->doublescan_allowed = 0;
4665
f0fec3f2 4666 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4667 edp_panel_vdd_work);
a4fc5ed6 4668
df0e9248 4669 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 4670 drm_connector_register(connector);
a4fc5ed6 4671
affa9354 4672 if (HAS_DDI(dev))
bcbc889b
PZ		 4673 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4674 else
4675 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 4676 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 4677
0b99836f 4678 /* Set up the hotplug pin. */
ab9d7c30
PZ		 4679 switch (port) {
4680 case PORT_A:
1d843f9d 4681 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 4682 break;
4683 case PORT_B:
1d843f9d 4684 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 4685 break;
4686 case PORT_C:
1d843f9d 4687 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 4688 break;
4689 case PORT_D:
1d843f9d 4690 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 4691 break;
4692 default:
ad1c0b19 4693 BUG();
5eb08b69
ZW		 4694 }
4695
dada1a9f
ID		 4696 if (is_edp(intel_dp)) {
4697 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 4698 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 4699 }
0095e6dc 4700
9d1a1031 4701 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 4702
0e32b39c
DA		 4703 /* init MST on ports that can support it */
4704 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4705 if (port == PORT_B || port == PORT_C || port == PORT_D) {
4706 intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
4707 }
4708 }
4709
0095e6dc 4710 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 4711 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 4712 if (is_edp(intel_dp)) {
4713 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4714 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4715 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4716 drm_modeset_unlock(&dev->mode_config.connection_mutex);
15b1d171 4717 }
34ea3d38 4718 drm_connector_unregister(connector);
b2f246a8 4719 drm_connector_cleanup(connector);
16c25533 4720 return false;
b2f246a8 4721 }
32f9d658 4722
f684960e
CW		 4723 intel_dp_add_properties(intel_dp, connector);
4724
a4fc5ed6
KP		 4725 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4726 * 0xd. Failure to do so will result in spurious interrupts being
4727 * generated on the port when a cable is not attached.
4728 */
4729 if (IS_G4X(dev) && !IS_GM45(dev)) {
4730 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4731 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4732 }
16c25533
PZ		 4733
4734 return true;
a4fc5ed6 4735}
f0fec3f2
PZ		 4736
4737void
4738intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4739{
13cf5504 4740 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 4741 struct intel_digital_port *intel_dig_port;
4742 struct intel_encoder *intel_encoder;
4743 struct drm_encoder *encoder;
4744 struct intel_connector *intel_connector;
4745
b14c5679 4746 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 4747 if (!intel_dig_port)
4748 return;
4749
b14c5679 4750 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 4751 if (!intel_connector) {
4752 kfree(intel_dig_port);
4753 return;
4754 }
4755
4756 intel_encoder = &intel_dig_port->base;
4757 encoder = &intel_encoder->base;
4758
4759 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4760 DRM_MODE_ENCODER_TMDS);
4761
5bfe2ac0 4762 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 4763 intel_encoder->disable = intel_disable_dp;
00c09d70 4764 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4765 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 4766 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 4767 if (IS_CHERRYVIEW(dev)) {
9197c88b 4768 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 4769 intel_encoder->pre_enable = chv_pre_enable_dp;
4770 intel_encoder->enable = vlv_enable_dp;
580d3811 4771 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 4772 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4773 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4774 intel_encoder->pre_enable = vlv_pre_enable_dp;
4775 intel_encoder->enable = vlv_enable_dp;
49277c31 4776 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4777 } else {
ecff4f3b
JN		 4778 intel_encoder->pre_enable = g4x_pre_enable_dp;
4779 intel_encoder->enable = g4x_enable_dp;
49277c31 4780 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4781 }
f0fec3f2 4782
174edf1f 4783 intel_dig_port->port = port;
f0fec3f2
PZ		 4784 intel_dig_port->dp.output_reg = output_reg;
4785
00c09d70 4786 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 4787 if (IS_CHERRYVIEW(dev)) {
4788 if (port == PORT_D)
4789 intel_encoder->crtc_mask = 1 << 2;
4790 else
4791 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4792 } else {
4793 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4794 }
bc079e8b 4795 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4796 intel_encoder->hot_plug = intel_dp_hot_plug;
4797
13cf5504
DA		 4798 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4799 dev_priv->hpd_irq_port[port] = intel_dig_port;
4800
15b1d171
PZ		 4801 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4802 drm_encoder_cleanup(encoder);
4803 kfree(intel_dig_port);
b2f246a8 4804 kfree(intel_connector);
15b1d171 4805 }
f0fec3f2 4806}
0e32b39c
DA		 4807
4808void intel_dp_mst_suspend(struct drm_device *dev)
4809{
4810 struct drm_i915_private *dev_priv = dev->dev_private;
4811 int i;
4812
4813 /* disable MST */
4814 for (i = 0; i < I915_MAX_PORTS; i++) {
4815 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4816 if (!intel_dig_port)
4817 continue;
4818
4819 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4820 if (!intel_dig_port->dp.can_mst)
4821 continue;
4822 if (intel_dig_port->dp.is_mst)
4823 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
4824 }
4825 }
4826}
4827
4828void intel_dp_mst_resume(struct drm_device *dev)
4829{
4830 struct drm_i915_private *dev_priv = dev->dev_private;
4831 int i;
4832
4833 for (i = 0; i < I915_MAX_PORTS; i++) {
4834 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4835 if (!intel_dig_port)
4836 continue;
4837 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4838 int ret;
4839
4840 if (!intel_dig_port->dp.can_mst)
4841 continue;
4842
4843 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
4844 if (ret != 0) {
4845 intel_dp_check_mst_status(&intel_dig_port->dp);
4846 }
4847 }
4848 }
4849}
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