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drm/i915: Wait for PHY port ready before link training on VLV/CHV
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
093e3f13 116static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
a4fc5ed6 117
0e32b39c 118int
ea5b213a 119intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 120{
7183dc29 121 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 122 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 123
124 switch (max_link_bw) {
125 case DP_LINK_BW_1_62:
126 case DP_LINK_BW_2_7:
127 break;
d4eead50 128 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 129 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
130 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 131 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
132 max_link_bw = DP_LINK_BW_5_4;
133 else
134 max_link_bw = DP_LINK_BW_2_7;
d4eead50 135 break;
a4fc5ed6 136 default:
d4eead50
ID		 137 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
138 max_link_bw);
a4fc5ed6
KP		 139 max_link_bw = DP_LINK_BW_1_62;
140 break;
141 }
142 return max_link_bw;
143}
144
eeb6324d
PZ		 145static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
146{
147 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
148 struct drm_device *dev = intel_dig_port->base.base.dev;
149 u8 source_max, sink_max;
150
151 source_max = 4;
152 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
153 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
154 source_max = 2;
155
156 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
157
158 return min(source_max, sink_max);
159}
160
cd9dde44
AJ		 161/*
162 * The units on the numbers in the next two are... bizarre. Examples will
163 * make it clearer; this one parallels an example in the eDP spec.
164 *
165 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
166 *
167 * 270000 * 1 * 8 / 10 == 216000
168 *
169 * The actual data capacity of that configuration is 2.16Gbit/s, so the
170 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
171 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
172 * 119000. At 18bpp that's 2142000 kilobits per second.
173 *
174 * Thus the strange-looking division by 10 in intel_dp_link_required, to
175 * get the result in decakilobits instead of kilobits.
176 */
177
a4fc5ed6 178static int
c898261c 179intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 180{
cd9dde44 181 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 182}
183
fe27d53e
DA		 184static int
185intel_dp_max_data_rate(int max_link_clock, int max_lanes)
186{
187 return (max_link_clock * max_lanes * 8) / 10;
188}
189
c19de8eb 190static enum drm_mode_status
a4fc5ed6
KP		 191intel_dp_mode_valid(struct drm_connector *connector,
192 struct drm_display_mode *mode)
193{
df0e9248 194 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 195 struct intel_connector *intel_connector = to_intel_connector(connector);
196 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 197 int target_clock = mode->clock;
198 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 199
dd06f90e
JN		 200 if (is_edp(intel_dp) && fixed_mode) {
201 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 202 return MODE_PANEL;
203
dd06f90e 204 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 205 return MODE_PANEL;
03afc4a2
DV		 206
207 target_clock = fixed_mode->clock;
7de56f43
ZY		 208 }
209
36008365 210 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 211 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 212
213 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
214 mode_rate = intel_dp_link_required(target_clock, 18);
215
216 if (mode_rate > max_rate)
c4867936 217 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 218
219 if (mode->clock < 10000)
220 return MODE_CLOCK_LOW;
221
0af78a2b
DV		 222 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
223 return MODE_H_ILLEGAL;
224
a4fc5ed6
KP		 225 return MODE_OK;
226}
227
228static uint32_t
5ca476f8 229pack_aux(const uint8_t *src, int src_bytes)
a4fc5ed6
KP		 230{
231 int i;
232 uint32_t v = 0;
233
234 if (src_bytes > 4)
235 src_bytes = 4;
236 for (i = 0; i < src_bytes; i++)
237 v |= ((uint32_t) src[i]) << ((3-i) * 8);
238 return v;
239}
240
241static void
242unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
243{
244 int i;
245 if (dst_bytes > 4)
246 dst_bytes = 4;
247 for (i = 0; i < dst_bytes; i++)
248 dst[i] = src >> ((3-i) * 8);
249}
250
fb0f8fbf
KP		 251/* hrawclock is 1/4 the FSB frequency */
252static int
253intel_hrawclk(struct drm_device *dev)
254{
255 struct drm_i915_private *dev_priv = dev->dev_private;
256 uint32_t clkcfg;
257
9473c8f4
VP		 258 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
259 if (IS_VALLEYVIEW(dev))
260 return 200;
261
fb0f8fbf
KP		 262 clkcfg = I915_READ(CLKCFG);
263 switch (clkcfg & CLKCFG_FSB_MASK) {
264 case CLKCFG_FSB_400:
265 return 100;
266 case CLKCFG_FSB_533:
267 return 133;
268 case CLKCFG_FSB_667:
269 return 166;
270 case CLKCFG_FSB_800:
271 return 200;
272 case CLKCFG_FSB_1067:
273 return 266;
274 case CLKCFG_FSB_1333:
275 return 333;
276 /* these two are just a guess; one of them might be right */
277 case CLKCFG_FSB_1600:
278 case CLKCFG_FSB_1600_ALT:
279 return 400;
280 default:
281 return 133;
282 }
283}
284
bf13e81b
JN		 285static void
286intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 287 struct intel_dp *intel_dp);
bf13e81b
JN		 288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 290 struct intel_dp *intel_dp);
bf13e81b 291
773538e8
VS		 292static void pps_lock(struct intel_dp *intel_dp)
293{
294 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
295 struct intel_encoder *encoder = &intel_dig_port->base;
296 struct drm_device *dev = encoder->base.dev;
297 struct drm_i915_private *dev_priv = dev->dev_private;
298 enum intel_display_power_domain power_domain;
299
300 /*
301 * See vlv_power_sequencer_reset() why we need
302 * a power domain reference here.
303 */
304 power_domain = intel_display_port_power_domain(encoder);
305 intel_display_power_get(dev_priv, power_domain);
306
307 mutex_lock(&dev_priv->pps_mutex);
308}
309
310static void pps_unlock(struct intel_dp *intel_dp)
311{
312 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
313 struct intel_encoder *encoder = &intel_dig_port->base;
314 struct drm_device *dev = encoder->base.dev;
315 struct drm_i915_private *dev_priv = dev->dev_private;
316 enum intel_display_power_domain power_domain;
317
318 mutex_unlock(&dev_priv->pps_mutex);
319
320 power_domain = intel_display_port_power_domain(encoder);
321 intel_display_power_put(dev_priv, power_domain);
322}
323
bf13e81b
JN		 324static enum pipe
325vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
326{
327 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bf13e81b
JN		 328 struct drm_device *dev = intel_dig_port->base.base.dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 330 struct intel_encoder *encoder;
331 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
bf13e81b 332
e39b999a 333 lockdep_assert_held(&dev_priv->pps_mutex);
bf13e81b 334
a4a5d2f8
VS		 335 if (intel_dp->pps_pipe != INVALID_PIPE)
336 return intel_dp->pps_pipe;
337
338 /*
339 * We don't have power sequencer currently.
340 * Pick one that's not used by other ports.
341 */
342 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
343 base.head) {
344 struct intel_dp *tmp;
345
346 if (encoder->type != INTEL_OUTPUT_EDP)
347 continue;
348
349 tmp = enc_to_intel_dp(&encoder->base);
350
351 if (tmp->pps_pipe != INVALID_PIPE)
352 pipes &= ~(1 << tmp->pps_pipe);
353 }
354
355 /*
356 * Didn't find one. This should not happen since there
357 * are two power sequencers and up to two eDP ports.
358 */
359 if (WARN_ON(pipes == 0))
360 return PIPE_A;
361
362 intel_dp->pps_pipe = ffs(pipes) - 1;
363
364 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
365 pipe_name(intel_dp->pps_pipe),
366 port_name(intel_dig_port->port));
367
368 /* init power sequencer on this pipe and port */
36b5f425
VS		 369 intel_dp_init_panel_power_sequencer(dev, intel_dp);
370 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 371
372 return intel_dp->pps_pipe;
373}
374
6491ab27
VS		 375typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
376 enum pipe pipe);
377
378static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
379 enum pipe pipe)
380{
381 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
382}
383
384static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
385 enum pipe pipe)
386{
387 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
388}
389
390static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
391 enum pipe pipe)
392{
393 return true;
394}
bf13e81b 395
a4a5d2f8 396static enum pipe
6491ab27
VS		 397vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
398 enum port port,
399 vlv_pipe_check pipe_check)
a4a5d2f8
VS		 400{
401 enum pipe pipe;
bf13e81b 402
bf13e81b
JN		 403 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
404 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
405 PANEL_PORT_SELECT_MASK;
a4a5d2f8
VS		 406
407 if (port_sel != PANEL_PORT_SELECT_VLV(port))
408 continue;
409
6491ab27
VS		 410 if (!pipe_check(dev_priv, pipe))
411 continue;
412
a4a5d2f8 413 return pipe;
bf13e81b
JN		 414 }
415
a4a5d2f8
VS		 416 return INVALID_PIPE;
417}
418
419static void
420vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
421{
422 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
423 struct drm_device *dev = intel_dig_port->base.base.dev;
424 struct drm_i915_private *dev_priv = dev->dev_private;
a4a5d2f8
VS		 425 enum port port = intel_dig_port->port;
426
427 lockdep_assert_held(&dev_priv->pps_mutex);
428
429 /* try to find a pipe with this port selected */
6491ab27
VS		 430 /* first pick one where the panel is on */
431 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
432 vlv_pipe_has_pp_on);
433 /* didn't find one? pick one where vdd is on */
434 if (intel_dp->pps_pipe == INVALID_PIPE)
435 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
436 vlv_pipe_has_vdd_on);
437 /* didn't find one? pick one with just the correct port */
438 if (intel_dp->pps_pipe == INVALID_PIPE)
439 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
440 vlv_pipe_any);
a4a5d2f8
VS		 441
442 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
443 if (intel_dp->pps_pipe == INVALID_PIPE) {
444 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
445 port_name(port));
446 return;
bf13e81b
JN		 447 }
448
a4a5d2f8
VS		 449 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
450 port_name(port), pipe_name(intel_dp->pps_pipe));
451
36b5f425
VS		 452 intel_dp_init_panel_power_sequencer(dev, intel_dp);
453 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
bf13e81b
JN		 454}
455
773538e8
VS		 456void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
457{
458 struct drm_device *dev = dev_priv->dev;
459 struct intel_encoder *encoder;
460
461 if (WARN_ON(!IS_VALLEYVIEW(dev)))
462 return;
463
464 /*
465 * We can't grab pps_mutex here due to deadlock with power_domain
466 * mutex when power_domain functions are called while holding pps_mutex.
467 * That also means that in order to use pps_pipe the code needs to
468 * hold both a power domain reference and pps_mutex, and the power domain
469 * reference get/put must be done while _not_ holding pps_mutex.
470 * pps_{lock,unlock}() do these steps in the correct order, so one
471 * should use them always.
472 */
473
474 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
475 struct intel_dp *intel_dp;
476
477 if (encoder->type != INTEL_OUTPUT_EDP)
478 continue;
479
480 intel_dp = enc_to_intel_dp(&encoder->base);
481 intel_dp->pps_pipe = INVALID_PIPE;
482 }
bf13e81b
JN		 483}
484
485static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
486{
487 struct drm_device *dev = intel_dp_to_dev(intel_dp);
488
489 if (HAS_PCH_SPLIT(dev))
490 return PCH_PP_CONTROL;
491 else
492 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
493}
494
495static u32 _pp_stat_reg(struct intel_dp *intel_dp)
496{
497 struct drm_device *dev = intel_dp_to_dev(intel_dp);
498
499 if (HAS_PCH_SPLIT(dev))
500 return PCH_PP_STATUS;
501 else
502 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
503}
504
01527b31
CT		 505/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
506 This function only applicable when panel PM state is not to be tracked */
507static int edp_notify_handler(struct notifier_block *this, unsigned long code,
508 void *unused)
509{
510 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
511 edp_notifier);
512 struct drm_device *dev = intel_dp_to_dev(intel_dp);
513 struct drm_i915_private *dev_priv = dev->dev_private;
514 u32 pp_div;
515 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 516
517 if (!is_edp(intel_dp) || code != SYS_RESTART)
518 return 0;
519
773538e8 520 pps_lock(intel_dp);
e39b999a 521
01527b31 522 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 523 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
524
01527b31
CT		 525 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
526 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
527 pp_div = I915_READ(pp_div_reg);
528 pp_div &= PP_REFERENCE_DIVIDER_MASK;
529
530 /* 0x1F write to PP_DIV_REG sets max cycle delay */
531 I915_WRITE(pp_div_reg, pp_div | 0x1F);
532 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
533 msleep(intel_dp->panel_power_cycle_delay);
534 }
535
773538e8 536 pps_unlock(intel_dp);
e39b999a 537
01527b31
CT		 538 return 0;
539}
540
4be73780 541static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 542{
30add22d 543 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 544 struct drm_i915_private *dev_priv = dev->dev_private;
545
e39b999a
VS		 546 lockdep_assert_held(&dev_priv->pps_mutex);
547
bf13e81b 548 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 549}
550
4be73780 551static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 552{
30add22d 553 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 554 struct drm_i915_private *dev_priv = dev->dev_private;
555
e39b999a
VS		 556 lockdep_assert_held(&dev_priv->pps_mutex);
557
773538e8 558 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
ebf33b18
KP		 559}
560
9b984dae
KP		 561static void
562intel_dp_check_edp(struct intel_dp *intel_dp)
563{
30add22d 564 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 565 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 566
9b984dae
KP		 567 if (!is_edp(intel_dp))
568 return;
453c5420 569
4be73780 570 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 571 WARN(1, "eDP powered off while attempting aux channel communication.\n");
572 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 573 I915_READ(_pp_stat_reg(intel_dp)),
574 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 575 }
576}
577
9ee32fea
DV		 578static uint32_t
579intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
580{
581 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
582 struct drm_device *dev = intel_dig_port->base.base.dev;
583 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 584 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 585 uint32_t status;
586 bool done;
587
ef04f00d 588#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 589 if (has_aux_irq)
b18ac466 590 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 591 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 592 else
593 done = wait_for_atomic(C, 10) == 0;
594 if (!done)
595 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
596 has_aux_irq);
597#undef C
598
599 return status;
600}
601
ec5b01dd 602static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 603{
174edf1f
PZ		 604 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
605 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 606
ec5b01dd
DL		 607 /*
608 * The clock divider is based off the hrawclk, and would like to run at
609 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 610 */
ec5b01dd
DL		 611 return index ? 0 : intel_hrawclk(dev) / 2;
612}
613
614static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
615{
616 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
617 struct drm_device *dev = intel_dig_port->base.base.dev;
618
619 if (index)
620 return 0;
621
622 if (intel_dig_port->port == PORT_A) {
623 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 624 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 625 else
b84a1cf8 626 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 627 } else {
628 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
629 }
630}
631
632static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
633{
634 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
635 struct drm_device *dev = intel_dig_port->base.base.dev;
636 struct drm_i915_private *dev_priv = dev->dev_private;
637
638 if (intel_dig_port->port == PORT_A) {
639 if (index)
640 return 0;
641 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 642 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
643 /* Workaround for non-ULT HSW */
bc86625a
CW		 644 switch (index) {
645 case 0: return 63;
646 case 1: return 72;
647 default: return 0;
648 }
ec5b01dd 649 } else {
bc86625a 650 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 651 }
b84a1cf8
RV		 652}
653
ec5b01dd
DL		 654static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
655{
656 return index ? 0 : 100;
657}
658
b6b5e383
DL		 659static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
660{
661 /*
662 * SKL doesn't need us to program the AUX clock divider (Hardware will
663 * derive the clock from CDCLK automatically). We still implement the
664 * get_aux_clock_divider vfunc to plug-in into the existing code.
665 */
666 return index ? 0 : 1;
667}
668
5ed12a19
DL		 669static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
670 bool has_aux_irq,
671 int send_bytes,
672 uint32_t aux_clock_divider)
673{
674 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
675 struct drm_device *dev = intel_dig_port->base.base.dev;
676 uint32_t precharge, timeout;
677
678 if (IS_GEN6(dev))
679 precharge = 3;
680 else
681 precharge = 5;
682
683 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
684 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
685 else
686 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
687
688 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 689 DP_AUX_CH_CTL_DONE |
5ed12a19 690 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 691 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 692 timeout |
788d4433 693 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 694 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
695 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 696 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 697}
698
b9ca5fad
DL		 699static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
700 bool has_aux_irq,
701 int send_bytes,
702 uint32_t unused)
703{
704 return DP_AUX_CH_CTL_SEND_BUSY |
705 DP_AUX_CH_CTL_DONE |
706 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
707 DP_AUX_CH_CTL_TIME_OUT_ERROR |
708 DP_AUX_CH_CTL_TIME_OUT_1600us |
709 DP_AUX_CH_CTL_RECEIVE_ERROR |
710 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
711 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
712}
713
b84a1cf8
RV		 714static int
715intel_dp_aux_ch(struct intel_dp *intel_dp,
bd9f74a5 716 const uint8_t *send, int send_bytes,
b84a1cf8
RV		 717 uint8_t *recv, int recv_size)
718{
719 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
720 struct drm_device *dev = intel_dig_port->base.base.dev;
721 struct drm_i915_private *dev_priv = dev->dev_private;
722 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
723 uint32_t ch_data = ch_ctl + 4;
bc86625a 724 uint32_t aux_clock_divider;
b84a1cf8
RV		 725 int i, ret, recv_bytes;
726 uint32_t status;
5ed12a19 727 int try, clock = 0;
4e6b788c 728 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 729 bool vdd;
730
773538e8 731 pps_lock(intel_dp);
e39b999a 732
72c3500a
VS		 733 /*
734 * We will be called with VDD already enabled for dpcd/edid/oui reads.
735 * In such cases we want to leave VDD enabled and it's up to upper layers
736 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
737 * ourselves.
738 */
1e0560e0 739 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 740
741 /* dp aux is extremely sensitive to irq latency, hence request the
742 * lowest possible wakeup latency and so prevent the cpu from going into
743 * deep sleep states.
744 */
745 pm_qos_update_request(&dev_priv->pm_qos, 0);
746
747 intel_dp_check_edp(intel_dp);
5eb08b69 748
c67a470b
PZ		 749 intel_aux_display_runtime_get(dev_priv);
750
11bee43e
JB		 751 /* Try to wait for any previous AUX channel activity */
752 for (try = 0; try < 3; try++) {
ef04f00d 753 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 754 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
755 break;
756 msleep(1);
757 }
758
759 if (try == 3) {
760 WARN(1, "dp_aux_ch not started status 0x%08x\n",
761 I915_READ(ch_ctl));
9ee32fea
DV		 762 ret = -EBUSY;
763 goto out;
4f7f7b7e
CW		 764 }
765
46a5ae9f
PZ		 766 /* Only 5 data registers! */
767 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
768 ret = -E2BIG;
769 goto out;
770 }
771
ec5b01dd 772 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 773 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
774 has_aux_irq,
775 send_bytes,
776 aux_clock_divider);
5ed12a19 777
bc86625a
CW		 778 /* Must try at least 3 times according to DP spec */
779 for (try = 0; try < 5; try++) {
780 /* Load the send data into the aux channel data registers */
781 for (i = 0; i < send_bytes; i += 4)
782 I915_WRITE(ch_data + i,
783 pack_aux(send + i, send_bytes - i));
784
785 /* Send the command and wait for it to complete */
5ed12a19 786 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 787
788 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
789
790 /* Clear done status and any errors */
791 I915_WRITE(ch_ctl,
792 status |
793 DP_AUX_CH_CTL_DONE |
794 DP_AUX_CH_CTL_TIME_OUT_ERROR |
795 DP_AUX_CH_CTL_RECEIVE_ERROR);
796
797 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
798 DP_AUX_CH_CTL_RECEIVE_ERROR))
799 continue;
800 if (status & DP_AUX_CH_CTL_DONE)
801 break;
802 }
4f7f7b7e 803 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 804 break;
805 }
806
a4fc5ed6 807 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 808 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 809 ret = -EBUSY;
810 goto out;
a4fc5ed6
KP		 811 }
812
813 /* Check for timeout or receive error.
814 * Timeouts occur when the sink is not connected
815 */
a5b3da54 816 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 817 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 818 ret = -EIO;
819 goto out;
a5b3da54 820 }
1ae8c0a5
KP		 821
822 /* Timeouts occur when the device isn't connected, so they're
823 * "normal" -- don't fill the kernel log with these */
a5b3da54 824 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 825 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 826 ret = -ETIMEDOUT;
827 goto out;
a4fc5ed6
KP		 828 }
829
830 /* Unload any bytes sent back from the other side */
831 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
832 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 833 if (recv_bytes > recv_size)
834 recv_bytes = recv_size;
0206e353 835
4f7f7b7e
CW		 836 for (i = 0; i < recv_bytes; i += 4)
837 unpack_aux(I915_READ(ch_data + i),
838 recv + i, recv_bytes - i);
a4fc5ed6 839
9ee32fea
DV		 840 ret = recv_bytes;
841out:
842 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 843 intel_aux_display_runtime_put(dev_priv);
9ee32fea 844
884f19e9
JN		 845 if (vdd)
846 edp_panel_vdd_off(intel_dp, false);
847
773538e8 848 pps_unlock(intel_dp);
e39b999a 849
9ee32fea 850 return ret;
a4fc5ed6
KP		 851}
852
a6c8aff0
JN		 853#define BARE_ADDRESS_SIZE 3
854#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 855static ssize_t
856intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 857{
9d1a1031
JN		 858 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
859 uint8_t txbuf[20], rxbuf[20];
860 size_t txsize, rxsize;
a4fc5ed6 861 int ret;
a4fc5ed6 862
9d1a1031
JN		 863 txbuf[0] = msg->request << 4;
864 txbuf[1] = msg->address >> 8;
865 txbuf[2] = msg->address & 0xff;
866 txbuf[3] = msg->size - 1;
46a5ae9f 867
9d1a1031
JN		 868 switch (msg->request & ~DP_AUX_I2C_MOT) {
869 case DP_AUX_NATIVE_WRITE:
870 case DP_AUX_I2C_WRITE:
a6c8aff0 871 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 872 rxsize = 1;
f51a44b9 873
9d1a1031
JN		 874 if (WARN_ON(txsize > 20))
875 return -E2BIG;
a4fc5ed6 876
9d1a1031 877 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 878
9d1a1031
JN		 879 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
880 if (ret > 0) {
881 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 882
9d1a1031
JN		 883 /* Return payload size. */
884 ret = msg->size;
885 }
886 break;
46a5ae9f 887
9d1a1031
JN		 888 case DP_AUX_NATIVE_READ:
889 case DP_AUX_I2C_READ:
a6c8aff0 890 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 891 rxsize = msg->size + 1;
a4fc5ed6 892
9d1a1031
JN		 893 if (WARN_ON(rxsize > 20))
894 return -E2BIG;
a4fc5ed6 895
9d1a1031
JN		 896 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
897 if (ret > 0) {
898 msg->reply = rxbuf[0] >> 4;
899 /*
900 * Assume happy day, and copy the data. The caller is
901 * expected to check msg->reply before touching it.
902 *
903 * Return payload size.
904 */
905 ret--;
906 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 907 }
9d1a1031
JN		 908 break;
909
910 default:
911 ret = -EINVAL;
912 break;
a4fc5ed6 913 }
f51a44b9 914
9d1a1031 915 return ret;
a4fc5ed6
KP		 916}
917
9d1a1031
JN		 918static void
919intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
920{
921 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 922 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
923 enum port port = intel_dig_port->port;
0b99836f 924 const char *name = NULL;
ab2c0672
DA		 925 int ret;
926
33ad6626
JN		 927 switch (port) {
928 case PORT_A:
929 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 930 name = "DPDDC-A";
ab2c0672 931 break;
33ad6626
JN		 932 case PORT_B:
933 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 934 name = "DPDDC-B";
ab2c0672 935 break;
33ad6626
JN		 936 case PORT_C:
937 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 938 name = "DPDDC-C";
ab2c0672 939 break;
33ad6626
JN		 940 case PORT_D:
941 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 942 name = "DPDDC-D";
33ad6626
JN		 943 break;
944 default:
945 BUG();
ab2c0672
DA		 946 }
947
1b1aad75
DL		 948 /*
949 * The AUX_CTL register is usually DP_CTL + 0x10.
950 *
951 * On Haswell and Broadwell though:
952 * - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
953 * - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
954 *
955 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
956 */
957 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
33ad6626 958 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 959
0b99836f 960 intel_dp->aux.name = name;
9d1a1031
JN		 961 intel_dp->aux.dev = dev->dev;
962 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 963
0b99836f
JN		 964 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
965 connector->base.kdev->kobj.name);
8316f337 966
4f71d0cb 967 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 968 if (ret < 0) {
4f71d0cb 969 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 970 name, ret);
971 return;
ab2c0672 972 }
8a5e6aeb 973
0b99836f
JN		 974 ret = sysfs_create_link(&connector->base.kdev->kobj,
975 &intel_dp->aux.ddc.dev.kobj,
976 intel_dp->aux.ddc.dev.kobj.name);
977 if (ret < 0) {
978 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 979 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 980 }
a4fc5ed6
KP		 981}
982
80f65de3
ID		 983static void
984intel_dp_connector_unregister(struct intel_connector *intel_connector)
985{
986 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
987
0e32b39c
DA		 988 if (!intel_connector->mst_port)
989 sysfs_remove_link(&intel_connector->base.kdev->kobj,
990 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 991 intel_connector_unregister(intel_connector);
992}
993
0e50338c
DV		 994static void
995hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
996{
997 switch (link_bw) {
998 case DP_LINK_BW_1_62:
999 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1000 break;
1001 case DP_LINK_BW_2_7:
1002 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1003 break;
1004 case DP_LINK_BW_5_4:
1005 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1006 break;
1007 }
1008}
1009
c6bb3538
DV		 1010static void
1011intel_dp_set_clock(struct intel_encoder *encoder,
1012 struct intel_crtc_config *pipe_config, int link_bw)
1013{
1014 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 1015 const struct dp_link_dpll *divisor = NULL;
1016 int i, count = 0;
c6bb3538
DV		 1017
1018 if (IS_G4X(dev)) {
9dd4ffdf
CML		 1019 divisor = gen4_dpll;
1020 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 1021 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 1022 divisor = pch_dpll;
1023 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 1024 } else if (IS_CHERRYVIEW(dev)) {
1025 divisor = chv_dpll;
1026 count = ARRAY_SIZE(chv_dpll);
c6bb3538 1027 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 1028 divisor = vlv_dpll;
1029 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 1030 }
9dd4ffdf
CML		 1031
1032 if (divisor && count) {
1033 for (i = 0; i < count; i++) {
1034 if (link_bw == divisor[i].link_bw) {
1035 pipe_config->dpll = divisor[i].dpll;
1036 pipe_config->clock_set = true;
1037 break;
1038 }
1039 }
c6bb3538
DV		 1040 }
1041}
1042
00c09d70 1043bool
5bfe2ac0
DV		 1044intel_dp_compute_config(struct intel_encoder *encoder,
1045 struct intel_crtc_config *pipe_config)
a4fc5ed6 1046{
5bfe2ac0 1047 struct drm_device *dev = encoder->base.dev;
36008365 1048 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 1049 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 1050 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1051 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 1052 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 1053 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 1054 int lane_count, clock;
56071a20 1055 int min_lane_count = 1;
eeb6324d 1056 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 1057 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 1058 int min_clock = 0;
06ea66b6 1059 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 1060 int bpp, mode_rate;
06ea66b6 1061 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 1062 int link_avail, link_clock;
a4fc5ed6 1063
bc7d38a4 1064 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 1065 pipe_config->has_pch_encoder = true;
1066
03afc4a2 1067 pipe_config->has_dp_encoder = true;
f769cd24 1068 pipe_config->has_drrs = false;
9ed109a7 1069 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 1070
dd06f90e
JN		 1071 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1072 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1073 adjusted_mode);
2dd24552
JB		 1074 if (!HAS_PCH_SPLIT(dev))
1075 intel_gmch_panel_fitting(intel_crtc, pipe_config,
1076 intel_connector->panel.fitting_mode);
1077 else
b074cec8
JB		 1078 intel_pch_panel_fitting(intel_crtc, pipe_config,
1079 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 1080 }
1081
cb1793ce 1082 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 1083 return false;
1084
083f9560
DV		 1085 DRM_DEBUG_KMS("DP link computation with max lane count %i "
1086 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 1087 max_lane_count, bws[max_clock],
1088 adjusted_mode->crtc_clock);
083f9560 1089
36008365
DV		 1090 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1091 * bpc in between. */
3e7ca985 1092 bpp = pipe_config->pipe_bpp;
56071a20
JN		 1093 if (is_edp(intel_dp)) {
1094 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
1095 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1096 dev_priv->vbt.edp_bpp);
1097 bpp = dev_priv->vbt.edp_bpp;
1098 }
1099
344c5bbc
JN		 1100 /*
1101 * Use the maximum clock and number of lanes the eDP panel
1102 * advertizes being capable of. The panels are generally
1103 * designed to support only a single clock and lane
1104 * configuration, and typically these values correspond to the
1105 * native resolution of the panel.
1106 */
1107 min_lane_count = max_lane_count;
1108 min_clock = max_clock;
7984211e 1109 }
657445fe 1110
36008365 1111 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 1112 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1113 bpp);
36008365 1114
c6930992
DA		 1115 for (clock = min_clock; clock <= max_clock; clock++) {
1116 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 1117 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
1118 link_avail = intel_dp_max_data_rate(link_clock,
1119 lane_count);
1120
1121 if (mode_rate <= link_avail) {
1122 goto found;
1123 }
1124 }
1125 }
1126 }
c4867936 1127
36008365 1128 return false;
3685a8f3 1129
36008365 1130found:
55bc60db
VS		 1131 if (intel_dp->color_range_auto) {
1132 /*
1133 * See:
1134 * CEA-861-E - 5.1 Default Encoding Parameters
1135 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1136 */
18316c8c 1137 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 1138 intel_dp->color_range = DP_COLOR_RANGE_16_235;
1139 else
1140 intel_dp->color_range = 0;
1141 }
1142
3685a8f3 1143 if (intel_dp->color_range)
50f3b016 1144 pipe_config->limited_color_range = true;
a4fc5ed6 1145
36008365
DV		 1146 intel_dp->link_bw = bws[clock];
1147 intel_dp->lane_count = lane_count;
657445fe 1148 pipe_config->pipe_bpp = bpp;
ff9a6750 1149 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 1150
36008365
DV		 1151 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
1152 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 1153 pipe_config->port_clock, bpp);
36008365
DV		 1154 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1155 mode_rate, link_avail);
a4fc5ed6 1156
03afc4a2 1157 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 1158 adjusted_mode->crtc_clock,
1159 pipe_config->port_clock,
03afc4a2 1160 &pipe_config->dp_m_n);
9d1a455b 1161
439d7ac0
PB		 1162 if (intel_connector->panel.downclock_mode != NULL &&
1163 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 1164 pipe_config->has_drrs = true;
439d7ac0
PB		 1165 intel_link_compute_m_n(bpp, lane_count,
1166 intel_connector->panel.downclock_mode->clock,
1167 pipe_config->port_clock,
1168 &pipe_config->dp_m2_n2);
1169 }
1170
ea155f32 1171 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 1172 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
1173 else
1174 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 1175
03afc4a2 1176 return true;
a4fc5ed6
KP		 1177}
1178
7c62a164 1179static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 1180{
7c62a164
DV		 1181 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1182 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1183 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 1184 struct drm_i915_private *dev_priv = dev->dev_private;
1185 u32 dpa_ctl;
1186
ff9a6750 1187 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1188 dpa_ctl = I915_READ(DP_A);
1189 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1190
ff9a6750 1191 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1192 /* For a long time we've carried around a ILK-DevA w/a for the
1193 * 160MHz clock. If we're really unlucky, it's still required.
1194 */
1195 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1196 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1197 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1198 } else {
1199 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1200 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1201 }
1ce17038 1202
ea9b6006
DV		 1203 I915_WRITE(DP_A, dpa_ctl);
1204
1205 POSTING_READ(DP_A);
1206 udelay(500);
1207}
1208
8ac33ed3 1209static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1210{
b934223d 1211 struct drm_device *dev = encoder->base.dev;
417e822d 1212 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1213 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1214 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1215 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1216 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1217
417e822d 1218 /*
1a2eb460 1219 * There are four kinds of DP registers:
417e822d
KP		 1220 *
1221 * IBX PCH
1a2eb460
KP		 1222 * SNB CPU
1223 * IVB CPU
417e822d
KP		 1224 * CPT PCH
1225 *
1226 * IBX PCH and CPU are the same for almost everything,
1227 * except that the CPU DP PLL is configured in this
1228 * register
1229 *
1230 * CPT PCH is quite different, having many bits moved
1231 * to the TRANS_DP_CTL register instead. That
1232 * configuration happens (oddly) in ironlake_pch_enable
1233 */
9c9e7927 1234
417e822d
KP		 1235 /* Preserve the BIOS-computed detected bit. This is
1236 * supposed to be read-only.
1237 */
1238 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1239
417e822d 1240 /* Handle DP bits in common between all three register formats */
417e822d 1241 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1242 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1243
9ed109a7 1244 if (crtc->config.has_audio) {
e0dac65e 1245 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1246 pipe_name(crtc->pipe));
ea5b213a 1247 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
33d1e7c6 1248 intel_write_eld(encoder);
e0dac65e 1249 }
247d89f6 1250
417e822d 1251 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1252
bc7d38a4 1253 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1254 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1255 intel_dp->DP |= DP_SYNC_HS_HIGH;
1256 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1257 intel_dp->DP |= DP_SYNC_VS_HIGH;
1258 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1259
6aba5b6c 1260 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1261 intel_dp->DP |= DP_ENHANCED_FRAMING;
1262
7c62a164 1263 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1264 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1265 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1266 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1267
1268 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1269 intel_dp->DP |= DP_SYNC_HS_HIGH;
1270 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1271 intel_dp->DP |= DP_SYNC_VS_HIGH;
1272 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1273
6aba5b6c 1274 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1275 intel_dp->DP |= DP_ENHANCED_FRAMING;
1276
44f37d1f
CML		 1277 if (!IS_CHERRYVIEW(dev)) {
1278 if (crtc->pipe == 1)
1279 intel_dp->DP |= DP_PIPEB_SELECT;
1280 } else {
1281 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1282 }
417e822d
KP		 1283 } else {
1284 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1285 }
a4fc5ed6
KP		 1286}
1287
ffd6749d
PZ		 1288#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1289#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1290
1a5ef5b7
PZ		 1291#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1292#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1293
ffd6749d
PZ		 1294#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1295#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1296
4be73780 1297static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1298 u32 mask,
1299 u32 value)
bd943159 1300{
30add22d 1301 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1302 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1303 u32 pp_stat_reg, pp_ctrl_reg;
1304
e39b999a
VS		 1305 lockdep_assert_held(&dev_priv->pps_mutex);
1306
bf13e81b
JN		 1307 pp_stat_reg = _pp_stat_reg(intel_dp);
1308 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1309
99ea7127 1310 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1311 mask, value,
1312 I915_READ(pp_stat_reg),
1313 I915_READ(pp_ctrl_reg));
32ce697c 1314
453c5420 1315 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1316 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1317 I915_READ(pp_stat_reg),
1318 I915_READ(pp_ctrl_reg));
32ce697c 1319 }
54c136d4
CW		 1320
1321 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1322}
32ce697c 1323
4be73780 1324static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1325{
1326 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1327 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1328}
1329
4be73780 1330static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1331{
1332 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1333 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1334}
1335
4be73780 1336static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1337{
1338 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1339
1340 /* When we disable the VDD override bit last we have to do the manual
1341 * wait. */
1342 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1343 intel_dp->panel_power_cycle_delay);
1344
4be73780 1345 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1346}
1347
4be73780 1348static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1349{
1350 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1351 intel_dp->backlight_on_delay);
1352}
1353
4be73780 1354static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1355{
1356 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1357 intel_dp->backlight_off_delay);
1358}
99ea7127 1359
832dd3c1
KP		 1360/* Read the current pp_control value, unlocking the register if it
1361 * is locked
1362 */
1363
453c5420 1364static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1365{
453c5420
JB		 1366 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 u32 control;
832dd3c1 1369
e39b999a
VS		 1370 lockdep_assert_held(&dev_priv->pps_mutex);
1371
bf13e81b 1372 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1373 control &= ~PANEL_UNLOCK_MASK;
1374 control |= PANEL_UNLOCK_REGS;
1375 return control;
bd943159
KP		 1376}
1377
951468f3
VS		 1378/*
1379 * Must be paired with edp_panel_vdd_off().
1380 * Must hold pps_mutex around the whole on/off sequence.
1381 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1382 */
1e0560e0 1383static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1384{
30add22d 1385 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1386 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1387 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1388 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1389 enum intel_display_power_domain power_domain;
5d613501 1390 u32 pp;
453c5420 1391 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1392 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1393
e39b999a
VS		 1394 lockdep_assert_held(&dev_priv->pps_mutex);
1395
97af61f5 1396 if (!is_edp(intel_dp))
adddaaf4 1397 return false;
bd943159
KP		 1398
1399 intel_dp->want_panel_vdd = true;
99ea7127 1400
4be73780 1401 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1402 return need_to_disable;
b0665d57 1403
4e6e1a54
ID		 1404 power_domain = intel_display_port_power_domain(intel_encoder);
1405 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1406
b0665d57 1407 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1408
4be73780
DV		 1409 if (!edp_have_panel_power(intel_dp))
1410 wait_panel_power_cycle(intel_dp);
99ea7127 1411
453c5420 1412 pp = ironlake_get_pp_control(intel_dp);
5d613501 1413 pp |= EDP_FORCE_VDD;
ebf33b18 1414
bf13e81b
JN		 1415 pp_stat_reg = _pp_stat_reg(intel_dp);
1416 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1417
1418 I915_WRITE(pp_ctrl_reg, pp);
1419 POSTING_READ(pp_ctrl_reg);
1420 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1421 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1422 /*
1423 * If the panel wasn't on, delay before accessing aux channel
1424 */
4be73780 1425 if (!edp_have_panel_power(intel_dp)) {
bd943159 1426 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1427 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1428 }
adddaaf4
JN		 1429
1430 return need_to_disable;
1431}
1432
951468f3
VS		 1433/*
1434 * Must be paired with intel_edp_panel_vdd_off() or
1435 * intel_edp_panel_off().
1436 * Nested calls to these functions are not allowed since
1437 * we drop the lock. Caller must use some higher level
1438 * locking to prevent nested calls from other threads.
1439 */
b80d6c78 1440void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1441{
c695b6b6 1442 bool vdd;
adddaaf4 1443
c695b6b6
VS		 1444 if (!is_edp(intel_dp))
1445 return;
1446
773538e8 1447 pps_lock(intel_dp);
c695b6b6 1448 vdd = edp_panel_vdd_on(intel_dp);
773538e8 1449 pps_unlock(intel_dp);
c695b6b6
VS		 1450
1451 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1452}
1453
4be73780 1454static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1455{
30add22d 1456 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1457 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1458 struct intel_digital_port *intel_dig_port =
1459 dp_to_dig_port(intel_dp);
1460 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1461 enum intel_display_power_domain power_domain;
5d613501 1462 u32 pp;
453c5420 1463 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1464
e39b999a 1465 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1466
15e899a0 1467 WARN_ON(intel_dp->want_panel_vdd);
4e6e1a54 1468
15e899a0 1469 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1470 return;
b0665d57 1471
be2c9196 1472 DRM_DEBUG_KMS("Turning eDP VDD off\n");
bd943159 1473
be2c9196
VS		 1474 pp = ironlake_get_pp_control(intel_dp);
1475 pp &= ~EDP_FORCE_VDD;
453c5420 1476
be2c9196
VS		 1477 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1478 pp_stat_reg = _pp_stat_reg(intel_dp);
99ea7127 1479
be2c9196
VS		 1480 I915_WRITE(pp_ctrl_reg, pp);
1481 POSTING_READ(pp_ctrl_reg);
90791a5c 1482
be2c9196
VS		 1483 /* Make sure sequencer is idle before allowing subsequent activity */
1484 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1485 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
e9cb81a2 1486
be2c9196
VS		 1487 if ((pp & POWER_TARGET_ON) == 0)
1488 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1489
be2c9196
VS		 1490 power_domain = intel_display_port_power_domain(intel_encoder);
1491 intel_display_power_put(dev_priv, power_domain);
bd943159 1492}
5d613501 1493
4be73780 1494static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1495{
1496 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1497 struct intel_dp, panel_vdd_work);
bd943159 1498
773538e8 1499 pps_lock(intel_dp);
15e899a0
VS		 1500 if (!intel_dp->want_panel_vdd)
1501 edp_panel_vdd_off_sync(intel_dp);
773538e8 1502 pps_unlock(intel_dp);
bd943159
KP		 1503}
1504
aba86890
ID		 1505static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1506{
1507 unsigned long delay;
1508
1509 /*
1510 * Queue the timer to fire a long time from now (relative to the power
1511 * down delay) to keep the panel power up across a sequence of
1512 * operations.
1513 */
1514 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1515 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1516}
1517
951468f3
VS		 1518/*
1519 * Must be paired with edp_panel_vdd_on().
1520 * Must hold pps_mutex around the whole on/off sequence.
1521 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1522 */
4be73780 1523static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1524{
e39b999a
VS		 1525 struct drm_i915_private *dev_priv =
1526 intel_dp_to_dev(intel_dp)->dev_private;
1527
1528 lockdep_assert_held(&dev_priv->pps_mutex);
1529
97af61f5
KP		 1530 if (!is_edp(intel_dp))
1531 return;
5d613501 1532
bd943159 1533 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1534
bd943159
KP		 1535 intel_dp->want_panel_vdd = false;
1536
aba86890 1537 if (sync)
4be73780 1538 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1539 else
1540 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1541}
1542
9f0fb5be 1543static void edp_panel_on(struct intel_dp *intel_dp)
9934c132 1544{
30add22d 1545 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1546 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1547 u32 pp;
453c5420 1548 u32 pp_ctrl_reg;
9934c132 1549
9f0fb5be
VS		 1550 lockdep_assert_held(&dev_priv->pps_mutex);
1551
97af61f5 1552 if (!is_edp(intel_dp))
bd943159 1553 return;
99ea7127
KP		 1554
1555 DRM_DEBUG_KMS("Turn eDP power on\n");
1556
4be73780 1557 if (edp_have_panel_power(intel_dp)) {
99ea7127 1558 DRM_DEBUG_KMS("eDP power already on\n");
9f0fb5be 1559 return;
99ea7127 1560 }
9934c132 1561
4be73780 1562 wait_panel_power_cycle(intel_dp);
37c6c9b0 1563
bf13e81b 1564 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1565 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1566 if (IS_GEN5(dev)) {
1567 /* ILK workaround: disable reset around power sequence */
1568 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1569 I915_WRITE(pp_ctrl_reg, pp);
1570 POSTING_READ(pp_ctrl_reg);
05ce1a49 1571 }
37c6c9b0 1572
1c0ae80a 1573 pp |= POWER_TARGET_ON;
99ea7127
KP		 1574 if (!IS_GEN5(dev))
1575 pp |= PANEL_POWER_RESET;
1576
453c5420
JB		 1577 I915_WRITE(pp_ctrl_reg, pp);
1578 POSTING_READ(pp_ctrl_reg);
9934c132 1579
4be73780 1580 wait_panel_on(intel_dp);
dce56b3c 1581 intel_dp->last_power_on = jiffies;
9934c132 1582
05ce1a49
KP		 1583 if (IS_GEN5(dev)) {
1584 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1585 I915_WRITE(pp_ctrl_reg, pp);
1586 POSTING_READ(pp_ctrl_reg);
05ce1a49 1587 }
9f0fb5be 1588}
e39b999a 1589
9f0fb5be
VS		 1590void intel_edp_panel_on(struct intel_dp *intel_dp)
1591{
1592 if (!is_edp(intel_dp))
1593 return;
1594
1595 pps_lock(intel_dp);
1596 edp_panel_on(intel_dp);
773538e8 1597 pps_unlock(intel_dp);
9934c132
JB		 1598}
1599
9f0fb5be
VS		 1600
1601static void edp_panel_off(struct intel_dp *intel_dp)
9934c132 1602{
4e6e1a54
ID		 1603 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1604 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1605 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1606 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1607 enum intel_display_power_domain power_domain;
99ea7127 1608 u32 pp;
453c5420 1609 u32 pp_ctrl_reg;
9934c132 1610
9f0fb5be
VS		 1611 lockdep_assert_held(&dev_priv->pps_mutex);
1612
97af61f5
KP		 1613 if (!is_edp(intel_dp))
1614 return;
37c6c9b0 1615
99ea7127 1616 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1617
24f3e092
JN		 1618 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1619
453c5420 1620 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1621 /* We need to switch off panel power _and_ force vdd, for otherwise some
1622 * panels get very unhappy and cease to work. */
b3064154
PJ		 1623 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1624 EDP_BLC_ENABLE);
453c5420 1625
bf13e81b 1626 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1627
849e39f5
PZ		 1628 intel_dp->want_panel_vdd = false;
1629
453c5420
JB		 1630 I915_WRITE(pp_ctrl_reg, pp);
1631 POSTING_READ(pp_ctrl_reg);
9934c132 1632
dce56b3c 1633 intel_dp->last_power_cycle = jiffies;
4be73780 1634 wait_panel_off(intel_dp);
849e39f5
PZ		 1635
1636 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1637 power_domain = intel_display_port_power_domain(intel_encoder);
1638 intel_display_power_put(dev_priv, power_domain);
9f0fb5be 1639}
e39b999a 1640
9f0fb5be
VS		 1641void intel_edp_panel_off(struct intel_dp *intel_dp)
1642{
1643 if (!is_edp(intel_dp))
1644 return;
1645
1646 pps_lock(intel_dp);
1647 edp_panel_off(intel_dp);
773538e8 1648 pps_unlock(intel_dp);
9934c132
JB		 1649}
1650
1250d107
JN		 1651/* Enable backlight in the panel power control. */
1652static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1653{
da63a9f2
PZ		 1654 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1655 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657 u32 pp;
453c5420 1658 u32 pp_ctrl_reg;
32f9d658 1659
01cb9ea6
JB		 1660 /*
1661 * If we enable the backlight right away following a panel power
1662 * on, we may see slight flicker as the panel syncs with the eDP
1663 * link. So delay a bit to make sure the image is solid before
1664 * allowing it to appear.
1665 */
4be73780 1666 wait_backlight_on(intel_dp);
e39b999a 1667
773538e8 1668 pps_lock(intel_dp);
e39b999a 1669
453c5420 1670 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1671 pp |= EDP_BLC_ENABLE;
453c5420 1672
bf13e81b 1673 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1674
1675 I915_WRITE(pp_ctrl_reg, pp);
1676 POSTING_READ(pp_ctrl_reg);
e39b999a 1677
773538e8 1678 pps_unlock(intel_dp);
32f9d658
ZW		 1679}
1680
1250d107
JN		 1681/* Enable backlight PWM and backlight PP control. */
1682void intel_edp_backlight_on(struct intel_dp *intel_dp)
1683{
1684 if (!is_edp(intel_dp))
1685 return;
1686
1687 DRM_DEBUG_KMS("\n");
1688
1689 intel_panel_enable_backlight(intel_dp->attached_connector);
1690 _intel_edp_backlight_on(intel_dp);
1691}
1692
1693/* Disable backlight in the panel power control. */
1694static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1695{
30add22d 1696 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698 u32 pp;
453c5420 1699 u32 pp_ctrl_reg;
32f9d658 1700
f01eca2e
KP		 1701 if (!is_edp(intel_dp))
1702 return;
1703
773538e8 1704 pps_lock(intel_dp);
e39b999a 1705
453c5420 1706 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1707 pp &= ~EDP_BLC_ENABLE;
453c5420 1708
bf13e81b 1709 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1710
1711 I915_WRITE(pp_ctrl_reg, pp);
1712 POSTING_READ(pp_ctrl_reg);
f7d2323c 1713
773538e8 1714 pps_unlock(intel_dp);
e39b999a
VS		 1715
1716 intel_dp->last_backlight_off = jiffies;
f7d2323c 1717 edp_wait_backlight_off(intel_dp);
1250d107 1718}
f7d2323c 1719
1250d107
JN		 1720/* Disable backlight PP control and backlight PWM. */
1721void intel_edp_backlight_off(struct intel_dp *intel_dp)
1722{
1723 if (!is_edp(intel_dp))
1724 return;
1725
1726 DRM_DEBUG_KMS("\n");
f7d2323c 1727
1250d107 1728 _intel_edp_backlight_off(intel_dp);
f7d2323c 1729 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1730}
a4fc5ed6 1731
73580fb7
JN		 1732/*
1733 * Hook for controlling the panel power control backlight through the bl_power
1734 * sysfs attribute. Take care to handle multiple calls.
1735 */
1736static void intel_edp_backlight_power(struct intel_connector *connector,
1737 bool enable)
1738{
1739 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1740 bool is_enabled;
1741
773538e8 1742 pps_lock(intel_dp);
e39b999a 1743 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
773538e8 1744 pps_unlock(intel_dp);
73580fb7
JN		 1745
1746 if (is_enabled == enable)
1747 return;
1748
23ba9373
JN		 1749 DRM_DEBUG_KMS("panel power control backlight %s\n",
1750 enable ? "enable" : "disable");
73580fb7
JN		 1751
1752 if (enable)
1753 _intel_edp_backlight_on(intel_dp);
1754 else
1755 _intel_edp_backlight_off(intel_dp);
1756}
1757
2bd2ad64 1758static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1759{
da63a9f2
PZ		 1760 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1761 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1762 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1763 struct drm_i915_private *dev_priv = dev->dev_private;
1764 u32 dpa_ctl;
1765
2bd2ad64
DV		 1766 assert_pipe_disabled(dev_priv,
1767 to_intel_crtc(crtc)->pipe);
1768
d240f20f
JB		 1769 DRM_DEBUG_KMS("\n");
1770 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1771 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1772 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1773
1774 /* We don't adjust intel_dp->DP while tearing down the link, to
1775 * facilitate link retraining (e.g. after hotplug). Hence clear all
1776 * enable bits here to ensure that we don't enable too much. */
1777 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1778 intel_dp->DP |= DP_PLL_ENABLE;
1779 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1780 POSTING_READ(DP_A);
1781 udelay(200);
d240f20f
JB		 1782}
1783
2bd2ad64 1784static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1785{
da63a9f2
PZ		 1786 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1787 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1788 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1789 struct drm_i915_private *dev_priv = dev->dev_private;
1790 u32 dpa_ctl;
1791
2bd2ad64
DV		 1792 assert_pipe_disabled(dev_priv,
1793 to_intel_crtc(crtc)->pipe);
1794
d240f20f 1795 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1796 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1797 "dp pll off, should be on\n");
1798 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1799
1800 /* We can't rely on the value tracked for the DP register in
1801 * intel_dp->DP because link_down must not change that (otherwise link
1802 * re-training will fail. */
298b0b39 1803 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1804 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1805 POSTING_READ(DP_A);
d240f20f
JB		 1806 udelay(200);
1807}
1808
c7ad3810 1809/* If the sink supports it, try to set the power state appropriately */
c19b0669 1810void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1811{
1812 int ret, i;
1813
1814 /* Should have a valid DPCD by this point */
1815 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1816 return;
1817
1818 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1819 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1820 DP_SET_POWER_D3);
c7ad3810
JB		 1821 } else {
1822 /*
1823 * When turning on, we need to retry for 1ms to give the sink
1824 * time to wake up.
1825 */
1826 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1827 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1828 DP_SET_POWER_D0);
c7ad3810
JB		 1829 if (ret == 1)
1830 break;
1831 msleep(1);
1832 }
1833 }
f9cac721
JN		 1834
1835 if (ret != 1)
1836 DRM_DEBUG_KMS("failed to %s sink power state\n",
1837 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1838}
1839
19d8fe15
DV		 1840static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1841 enum pipe *pipe)
d240f20f 1842{
19d8fe15 1843 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1844 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1845 struct drm_device *dev = encoder->base.dev;
1846 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1847 enum intel_display_power_domain power_domain;
1848 u32 tmp;
1849
1850 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1851 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1852 return false;
1853
1854 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1855
1856 if (!(tmp & DP_PORT_EN))
1857 return false;
1858
bc7d38a4 1859 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1860 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1861 } else if (IS_CHERRYVIEW(dev)) {
1862 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1863 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1864 *pipe = PORT_TO_PIPE(tmp);
1865 } else {
1866 u32 trans_sel;
1867 u32 trans_dp;
1868 int i;
1869
1870 switch (intel_dp->output_reg) {
1871 case PCH_DP_B:
1872 trans_sel = TRANS_DP_PORT_SEL_B;
1873 break;
1874 case PCH_DP_C:
1875 trans_sel = TRANS_DP_PORT_SEL_C;
1876 break;
1877 case PCH_DP_D:
1878 trans_sel = TRANS_DP_PORT_SEL_D;
1879 break;
1880 default:
1881 return true;
1882 }
1883
055e393f 1884 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1885 trans_dp = I915_READ(TRANS_DP_CTL(i));
1886 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1887 *pipe = i;
1888 return true;
1889 }
1890 }
19d8fe15 1891
4a0833ec
DV		 1892 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1893 intel_dp->output_reg);
1894 }
d240f20f 1895
19d8fe15
DV		 1896 return true;
1897}
d240f20f 1898
045ac3b5
JB		 1899static void intel_dp_get_config(struct intel_encoder *encoder,
1900 struct intel_crtc_config *pipe_config)
1901{
1902 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1903 u32 tmp, flags = 0;
63000ef6
XZ		 1904 struct drm_device *dev = encoder->base.dev;
1905 struct drm_i915_private *dev_priv = dev->dev_private;
1906 enum port port = dp_to_dig_port(intel_dp)->port;
1907 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1908 int dotclock;
045ac3b5 1909
9ed109a7
DV		 1910 tmp = I915_READ(intel_dp->output_reg);
1911 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1912 pipe_config->has_audio = true;
1913
63000ef6 1914 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1915 if (tmp & DP_SYNC_HS_HIGH)
1916 flags |= DRM_MODE_FLAG_PHSYNC;
1917 else
1918 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1919
63000ef6
XZ		 1920 if (tmp & DP_SYNC_VS_HIGH)
1921 flags |= DRM_MODE_FLAG_PVSYNC;
1922 else
1923 flags |= DRM_MODE_FLAG_NVSYNC;
1924 } else {
1925 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1926 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1927 flags |= DRM_MODE_FLAG_PHSYNC;
1928 else
1929 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1930
63000ef6
XZ		 1931 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1932 flags |= DRM_MODE_FLAG_PVSYNC;
1933 else
1934 flags |= DRM_MODE_FLAG_NVSYNC;
1935 }
045ac3b5
JB		 1936
1937 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1938
8c875fca
VS		 1939 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1940 tmp & DP_COLOR_RANGE_16_235)
1941 pipe_config->limited_color_range = true;
1942
eb14cb74
VS		 1943 pipe_config->has_dp_encoder = true;
1944
1945 intel_dp_get_m_n(crtc, pipe_config);
1946
18442d08 1947 if (port == PORT_A) {
f1f644dc
JB		 1948 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1949 pipe_config->port_clock = 162000;
1950 else
1951 pipe_config->port_clock = 270000;
1952 }
18442d08
VS		 1953
1954 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1955 &pipe_config->dp_m_n);
1956
1957 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1958 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1959
241bfc38 1960 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1961
c6cd2ee2
JN		 1962 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1963 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1964 /*
1965 * This is a big fat ugly hack.
1966 *
1967 * Some machines in UEFI boot mode provide us a VBT that has 18
1968 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1969 * unknown we fail to light up. Yet the same BIOS boots up with
1970 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1971 * max, not what it tells us to use.
1972 *
1973 * Note: This will still be broken if the eDP panel is not lit
1974 * up by the BIOS, and thus we can't get the mode at module
1975 * load.
1976 */
1977 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1978 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1979 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1980 }
045ac3b5
JB		 1981}
1982
34eb7579 1983static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1984{
34eb7579 1985 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1986}
1987
2b28bb1b
RV		 1988static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1989{
1990 struct drm_i915_private *dev_priv = dev->dev_private;
1991
18b5992c 1992 if (!HAS_PSR(dev))
2b28bb1b
RV		 1993 return false;
1994
18b5992c 1995 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1996}
1997
1998static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1999 struct edp_vsc_psr *vsc_psr)
2000{
2001 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2002 struct drm_device *dev = dig_port->base.base.dev;
2003 struct drm_i915_private *dev_priv = dev->dev_private;
2004 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
2005 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
2006 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
2007 uint32_t *data = (uint32_t *) vsc_psr;
2008 unsigned int i;
2009
2010 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
2011 the video DIP being updated before program video DIP data buffer
2012 registers for DIP being updated. */
2013 I915_WRITE(ctl_reg, 0);
2014 POSTING_READ(ctl_reg);
2015
2016 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
2017 if (i < sizeof(struct edp_vsc_psr))
2018 I915_WRITE(data_reg + i, *data++);
2019 else
2020 I915_WRITE(data_reg + i, 0);
2021 }
2022
2023 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
2024 POSTING_READ(ctl_reg);
2025}
2026
ba80f4d4 2027static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp)
2b28bb1b 2028{
2b28bb1b
RV		 2029 struct edp_vsc_psr psr_vsc;
2030
2b28bb1b
RV		 2031 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
2032 memset(&psr_vsc, 0, sizeof(psr_vsc));
2033 psr_vsc.sdp_header.HB0 = 0;
2034 psr_vsc.sdp_header.HB1 = 0x7;
2035 psr_vsc.sdp_header.HB2 = 0x2;
2036 psr_vsc.sdp_header.HB3 = 0x8;
2037 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
2b28bb1b
RV		 2038}
2039
2040static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
2041{
0e0ae652
RV		 2042 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2043 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 2044 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 2045 uint32_t aux_clock_divider;
2b28bb1b 2046 int precharge = 0x3;
0e0ae652 2047 bool only_standby = false;
5ca476f8
VS		 2048 static const uint8_t aux_msg[] = {
2049 [0] = DP_AUX_NATIVE_WRITE << 4,
2050 [1] = DP_SET_POWER >> 8,
2051 [2] = DP_SET_POWER & 0xff,
2052 [3] = 1 - 1,
2053 [4] = DP_SET_POWER_D0,
2054 };
2055 int i;
2056
2057 BUILD_BUG_ON(sizeof(aux_msg) > 20);
2b28bb1b 2058
ec5b01dd
DL		 2059 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
2060
0e0ae652
RV		 2061 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2062 only_standby = true;
2063
2b28bb1b 2064 /* Enable PSR in sink */
0e0ae652 2065 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 2066 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2067 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 2068 else
9d1a1031
JN		 2069 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
2070 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 2071
2072 /* Setup AUX registers */
5ca476f8
VS		 2073 for (i = 0; i < sizeof(aux_msg); i += 4)
2074 I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
2075 pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
2076
18b5992c 2077 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b 2078 DP_AUX_CH_CTL_TIME_OUT_400us |
5ca476f8 2079 (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
2b28bb1b
RV		 2080 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
2081 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
2082}
2083
2084static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
2085{
0e0ae652
RV		 2086 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2087 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 2088 struct drm_i915_private *dev_priv = dev->dev_private;
2089 uint32_t max_sleep_time = 0x1f;
2090 uint32_t idle_frames = 1;
2091 uint32_t val = 0x0;
ed8546ac 2092 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 2093 bool only_standby = false;
2094
2095 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
2096 only_standby = true;
2b28bb1b 2097
0e0ae652 2098 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 2099 val |= EDP_PSR_LINK_STANDBY;
2100 val |= EDP_PSR_TP2_TP3_TIME_0us;
2101 val |= EDP_PSR_TP1_TIME_0us;
2102 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 2103 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 2104 } else
2105 val |= EDP_PSR_LINK_DISABLE;
2106
18b5992c 2107 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 2108 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 2109 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
2110 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
2111 EDP_PSR_ENABLE);
2112}
2113
3f51e471
RV		 2114static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
2115{
2116 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2117 struct drm_device *dev = dig_port->base.base.dev;
2118 struct drm_i915_private *dev_priv = dev->dev_private;
2119 struct drm_crtc *crtc = dig_port->base.base.crtc;
2120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 2121
f0355c4a 2122 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 2123 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
2124 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
2125
a031d709
RV		 2126 dev_priv->psr.source_ok = false;
2127
9ca15301 2128 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 2129 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 2130 return false;
2131 }
2132
d330a953 2133 if (!i915.enable_psr) {
105b7c11 2134 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 2135 return false;
2136 }
2137
4c8c7000
RV		 2138 /* Below limitations aren't valid for Broadwell */
2139 if (IS_BROADWELL(dev))
2140 goto out;
2141
3f51e471
RV		 2142 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
2143 S3D_ENABLE) {
2144 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 2145 return false;
2146 }
2147
ca73b4f0 2148 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 2149 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 2150 return false;
2151 }
2152
4c8c7000 2153 out:
a031d709 2154 dev_priv->psr.source_ok = true;
3f51e471
RV		 2155 return true;
2156}
2157
3d739d92 2158static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 2159{
7c8f8a70
RV		 2160 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2161 struct drm_device *dev = intel_dig_port->base.base.dev;
2162 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 2163
3638379c
DV		 2164 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2165 WARN_ON(dev_priv->psr.active);
f0355c4a 2166 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 2167
7ca5a41f 2168 /* Enable/Re-enable PSR on the host */
2b28bb1b 2169 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 2170
7c8f8a70 2171 dev_priv->psr.active = true;
2b28bb1b
RV		 2172}
2173
3d739d92
RV		 2174void intel_edp_psr_enable(struct intel_dp *intel_dp)
2175{
2176 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 2177 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 2178
4704c573
RV		 2179 if (!HAS_PSR(dev)) {
2180 DRM_DEBUG_KMS("PSR not supported on this platform\n");
2181 return;
2182 }
2183
34eb7579
RV		 2184 if (!is_edp_psr(intel_dp)) {
2185 DRM_DEBUG_KMS("PSR not supported by this panel\n");
2186 return;
2187 }
2188
f0355c4a 2189 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 2190 if (dev_priv->psr.enabled) {
2191 DRM_DEBUG_KMS("PSR already in use\n");
0aa48783 2192 goto unlock;
109fc2ad
DV		 2193 }
2194
0aa48783
RV		 2195 if (!intel_edp_psr_match_conditions(intel_dp))
2196 goto unlock;
2197
9ca15301
DV		 2198 dev_priv->psr.busy_frontbuffer_bits = 0;
2199
ba80f4d4 2200 intel_edp_psr_setup_vsc(intel_dp);
16487254 2201
ba80f4d4
RV		 2202 /* Avoid continuous PSR exit by masking memup and hpd */
2203 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
2204 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
16487254 2205
7ca5a41f
RV		 2206 /* Enable PSR on the panel */
2207 intel_edp_psr_enable_sink(intel_dp);
2208
0aa48783
RV		 2209 dev_priv->psr.enabled = intel_dp;
2210unlock:
f0355c4a 2211 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2212}
2213
2b28bb1b
RV		 2214void intel_edp_psr_disable(struct intel_dp *intel_dp)
2215{
2216 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2217 struct drm_i915_private *dev_priv = dev->dev_private;
2218
f0355c4a
DV		 2219 mutex_lock(&dev_priv->psr.lock);
2220 if (!dev_priv->psr.enabled) {
2221 mutex_unlock(&dev_priv->psr.lock);
2222 return;
2223 }
2224
3638379c
DV		 2225 if (dev_priv->psr.active) {
2226 I915_WRITE(EDP_PSR_CTL(dev),
2227 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2228
2229 /* Wait till PSR is idle */
2230 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2231 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2232 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2233
3638379c
DV		 2234 dev_priv->psr.active = false;
2235 } else {
2236 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2237 }
7c8f8a70 2238
2807cf69 2239 dev_priv->psr.enabled = NULL;
f0355c4a 2240 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2241
2242 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2243}
2244
f02a326e 2245static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2246{
2247 struct drm_i915_private *dev_priv =
2248 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2249 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2250
8d7f4fe9
RV		 2251 /* We have to make sure PSR is ready for re-enable
2252 * otherwise it keeps disabled until next full enable/disable cycle.
2253 * PSR might take some time to get fully disabled
2254 * and be ready for re-enable.
2255 */
2256 if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
2257 EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
2258 DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
2259 return;
2260 }
2261
f0355c4a
DV		 2262 mutex_lock(&dev_priv->psr.lock);
2263 intel_dp = dev_priv->psr.enabled;
2264
2807cf69 2265 if (!intel_dp)
f0355c4a 2266 goto unlock;
2807cf69 2267
9ca15301
DV		 2268 /*
2269 * The delayed work can race with an invalidate hence we need to
2270 * recheck. Since psr_flush first clears this and then reschedules we
2271 * won't ever miss a flush when bailing out here.
2272 */
2273 if (dev_priv->psr.busy_frontbuffer_bits)
2274 goto unlock;
2275
2276 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2277unlock:
2278 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2279}
2280
9ca15301 2281static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2282{
2283 struct drm_i915_private *dev_priv = dev->dev_private;
2284
3638379c
DV		 2285 if (dev_priv->psr.active) {
2286 u32 val = I915_READ(EDP_PSR_CTL(dev));
2287
2288 WARN_ON(!(val & EDP_PSR_ENABLE));
2289
2290 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2291
2292 dev_priv->psr.active = false;
2293 }
7c8f8a70 2294
9ca15301
DV		 2295}
2296
2297void intel_edp_psr_invalidate(struct drm_device *dev,
2298 unsigned frontbuffer_bits)
2299{
2300 struct drm_i915_private *dev_priv = dev->dev_private;
2301 struct drm_crtc *crtc;
2302 enum pipe pipe;
2303
9ca15301
DV		 2304 mutex_lock(&dev_priv->psr.lock);
2305 if (!dev_priv->psr.enabled) {
2306 mutex_unlock(&dev_priv->psr.lock);
2307 return;
2308 }
2309
2310 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2311 pipe = to_intel_crtc(crtc)->pipe;
2312
2313 intel_edp_psr_do_exit(dev);
2314
2315 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2316
2317 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2318 mutex_unlock(&dev_priv->psr.lock);
2319}
2320
2321void intel_edp_psr_flush(struct drm_device *dev,
2322 unsigned frontbuffer_bits)
2323{
2324 struct drm_i915_private *dev_priv = dev->dev_private;
2325 struct drm_crtc *crtc;
2326 enum pipe pipe;
2327
9ca15301
DV		 2328 mutex_lock(&dev_priv->psr.lock);
2329 if (!dev_priv->psr.enabled) {
2330 mutex_unlock(&dev_priv->psr.lock);
2331 return;
2332 }
2333
2334 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2335 pipe = to_intel_crtc(crtc)->pipe;
2336 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2337
2338 /*
2339 * On Haswell sprite plane updates don't result in a psr invalidating
2340 * signal in the hardware. Which means we need to manually fake this in
2341 * software for all flushes, not just when we've seen a preceding
2342 * invalidation through frontbuffer rendering.
2343 */
2344 if (IS_HASWELL(dev) &&
2345 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2346 intel_edp_psr_do_exit(dev);
2347
2348 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2349 schedule_delayed_work(&dev_priv->psr.work,
2350 msecs_to_jiffies(100));
f0355c4a 2351 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2352}
2353
2354void intel_edp_psr_init(struct drm_device *dev)
2355{
2356 struct drm_i915_private *dev_priv = dev->dev_private;
2357
7c8f8a70 2358 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2359 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2360}
2361
e8cb4558 2362static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2363{
e8cb4558 2364 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2365 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2366
2367 /* Make sure the panel is off before trying to change the mode. But also
2368 * ensure that we have vdd while we switch off the panel. */
24f3e092 2369 intel_edp_panel_vdd_on(intel_dp);
4be73780 2370 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2371 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2372 intel_edp_panel_off(intel_dp);
3739850b 2373
08aff3fe
VS		 2374 /* disable the port before the pipe on g4x */
2375 if (INTEL_INFO(dev)->gen < 5)
3739850b 2376 intel_dp_link_down(intel_dp);
d240f20f
JB		 2377}
2378
08aff3fe 2379static void ilk_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2380{
2bd2ad64 2381 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2382 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2383
49277c31 2384 intel_dp_link_down(intel_dp);
08aff3fe
VS		 2385 if (port == PORT_A)
2386 ironlake_edp_pll_off(intel_dp);
49277c31
VS		 2387}
2388
2389static void vlv_post_disable_dp(struct intel_encoder *encoder)
2390{
2391 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2392
2393 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2394}
2395
580d3811
VS		 2396static void chv_post_disable_dp(struct intel_encoder *encoder)
2397{
2398 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2399 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2400 struct drm_device *dev = encoder->base.dev;
2401 struct drm_i915_private *dev_priv = dev->dev_private;
2402 struct intel_crtc *intel_crtc =
2403 to_intel_crtc(encoder->base.crtc);
2404 enum dpio_channel ch = vlv_dport_to_channel(dport);
2405 enum pipe pipe = intel_crtc->pipe;
2406 u32 val;
2407
2408 intel_dp_link_down(intel_dp);
2409
2410 mutex_lock(&dev_priv->dpio_lock);
2411
2412 /* Propagate soft reset to data lane reset */
97fd4d5c 2413 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2414 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2415 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2416
97fd4d5c
VS		 2417 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2418 val |= CHV_PCS_REQ_SOFTRESET_EN;
2419 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2420
2421 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2422 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2423 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2424
2425 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2426 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2427 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2428
2429 mutex_unlock(&dev_priv->dpio_lock);
2430}
2431
7b13b58a
VS		 2432static void
2433_intel_dp_set_link_train(struct intel_dp *intel_dp,
2434 uint32_t *DP,
2435 uint8_t dp_train_pat)
2436{
2437 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2438 struct drm_device *dev = intel_dig_port->base.base.dev;
2439 struct drm_i915_private *dev_priv = dev->dev_private;
2440 enum port port = intel_dig_port->port;
2441
2442 if (HAS_DDI(dev)) {
2443 uint32_t temp = I915_READ(DP_TP_CTL(port));
2444
2445 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2446 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2447 else
2448 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2449
2450 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2451 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2452 case DP_TRAINING_PATTERN_DISABLE:
2453 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2454
2455 break;
2456 case DP_TRAINING_PATTERN_1:
2457 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2458 break;
2459 case DP_TRAINING_PATTERN_2:
2460 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2461 break;
2462 case DP_TRAINING_PATTERN_3:
2463 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2464 break;
2465 }
2466 I915_WRITE(DP_TP_CTL(port), temp);
2467
2468 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2469 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2470
2471 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2472 case DP_TRAINING_PATTERN_DISABLE:
2473 *DP |= DP_LINK_TRAIN_OFF_CPT;
2474 break;
2475 case DP_TRAINING_PATTERN_1:
2476 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2477 break;
2478 case DP_TRAINING_PATTERN_2:
2479 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2480 break;
2481 case DP_TRAINING_PATTERN_3:
2482 DRM_ERROR("DP training pattern 3 not supported\n");
2483 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2484 break;
2485 }
2486
2487 } else {
2488 if (IS_CHERRYVIEW(dev))
2489 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2490 else
2491 *DP &= ~DP_LINK_TRAIN_MASK;
2492
2493 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2494 case DP_TRAINING_PATTERN_DISABLE:
2495 *DP |= DP_LINK_TRAIN_OFF;
2496 break;
2497 case DP_TRAINING_PATTERN_1:
2498 *DP |= DP_LINK_TRAIN_PAT_1;
2499 break;
2500 case DP_TRAINING_PATTERN_2:
2501 *DP |= DP_LINK_TRAIN_PAT_2;
2502 break;
2503 case DP_TRAINING_PATTERN_3:
2504 if (IS_CHERRYVIEW(dev)) {
2505 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2506 } else {
2507 DRM_ERROR("DP training pattern 3 not supported\n");
2508 *DP |= DP_LINK_TRAIN_PAT_2;
2509 }
2510 break;
2511 }
2512 }
2513}
2514
2515static void intel_dp_enable_port(struct intel_dp *intel_dp)
2516{
2517 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2518 struct drm_i915_private *dev_priv = dev->dev_private;
2519
2520 intel_dp->DP |= DP_PORT_EN;
2521
2522 /* enable with pattern 1 (as per spec) */
2523 _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2524 DP_TRAINING_PATTERN_1);
2525
2526 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2527 POSTING_READ(intel_dp->output_reg);
580d3811
VS		 2528}
2529
e8cb4558 2530static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2531{
e8cb4558
DV		 2532 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2533 struct drm_device *dev = encoder->base.dev;
2534 struct drm_i915_private *dev_priv = dev->dev_private;
2535 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2536
0c33d8d7
DV		 2537 if (WARN_ON(dp_reg & DP_PORT_EN))
2538 return;
5d613501 2539
093e3f13
VS		 2540 pps_lock(intel_dp);
2541
2542 if (IS_VALLEYVIEW(dev))
2543 vlv_init_panel_power_sequencer(intel_dp);
2544
7b13b58a 2545 intel_dp_enable_port(intel_dp);
093e3f13
VS		 2546
2547 edp_panel_vdd_on(intel_dp);
2548 edp_panel_on(intel_dp);
2549 edp_panel_vdd_off(intel_dp, true);
2550
2551 pps_unlock(intel_dp);
2552
61234fa5
VS		 2553 if (IS_VALLEYVIEW(dev))
2554 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));
2555
f01eca2e 2556 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2557 intel_dp_start_link_train(intel_dp);
33a34e4e 2558 intel_dp_complete_link_train(intel_dp);
3ab9c637 2559 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2560}
89b667f8 2561
ecff4f3b
JN		 2562static void g4x_enable_dp(struct intel_encoder *encoder)
2563{
828f5c6e
JN		 2564 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2565
ecff4f3b 2566 intel_enable_dp(encoder);
4be73780 2567 intel_edp_backlight_on(intel_dp);
ab1f90f9 2568}
89b667f8 2569
ab1f90f9
JN		 2570static void vlv_enable_dp(struct intel_encoder *encoder)
2571{
828f5c6e
JN		 2572 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2573
4be73780 2574 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2575}
2576
ecff4f3b 2577static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2578{
2579 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2580 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2581
8ac33ed3
DV		 2582 intel_dp_prepare(encoder);
2583
d41f1efb
DV		 2584 /* Only ilk+ has port A */
2585 if (dport->port == PORT_A) {
2586 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2587 ironlake_edp_pll_on(intel_dp);
d41f1efb 2588 }
ab1f90f9
JN		 2589}
2590
a4a5d2f8
VS		 2591static void vlv_steal_power_sequencer(struct drm_device *dev,
2592 enum pipe pipe)
2593{
2594 struct drm_i915_private *dev_priv = dev->dev_private;
2595 struct intel_encoder *encoder;
2596
2597 lockdep_assert_held(&dev_priv->pps_mutex);
2598
2599 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2600 base.head) {
2601 struct intel_dp *intel_dp;
773538e8 2602 enum port port;
a4a5d2f8
VS		 2603
2604 if (encoder->type != INTEL_OUTPUT_EDP)
2605 continue;
2606
2607 intel_dp = enc_to_intel_dp(&encoder->base);
773538e8 2608 port = dp_to_dig_port(intel_dp)->port;
a4a5d2f8
VS		 2609
2610 if (intel_dp->pps_pipe != pipe)
2611 continue;
2612
2613 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
773538e8 2614 pipe_name(pipe), port_name(port));
a4a5d2f8
VS		 2615
2616 /* make sure vdd is off before we steal it */
2617 edp_panel_vdd_off_sync(intel_dp);
2618
2619 intel_dp->pps_pipe = INVALID_PIPE;
2620 }
2621}
2622
2623static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2624{
2625 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2626 struct intel_encoder *encoder = &intel_dig_port->base;
2627 struct drm_device *dev = encoder->base.dev;
2628 struct drm_i915_private *dev_priv = dev->dev_private;
2629 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
a4a5d2f8
VS		 2630
2631 lockdep_assert_held(&dev_priv->pps_mutex);
2632
093e3f13
VS		 2633 if (!is_edp(intel_dp))
2634 return;
2635
a4a5d2f8
VS		 2636 if (intel_dp->pps_pipe == crtc->pipe)
2637 return;
2638
2639 /*
2640 * If another power sequencer was being used on this
2641 * port previously make sure to turn off vdd there while
2642 * we still have control of it.
2643 */
2644 if (intel_dp->pps_pipe != INVALID_PIPE)
2645 edp_panel_vdd_off_sync(intel_dp);
2646
2647 /*
2648 * We may be stealing the power
2649 * sequencer from another port.
2650 */
2651 vlv_steal_power_sequencer(dev, crtc->pipe);
2652
2653 /* now it's all ours */
2654 intel_dp->pps_pipe = crtc->pipe;
2655
2656 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2657 pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2658
2659 /* init power sequencer on this pipe and port */
36b5f425
VS		 2660 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2661 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
a4a5d2f8
VS		 2662}
2663
ab1f90f9 2664static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2665{
2bd2ad64 2666 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2667 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2668 struct drm_device *dev = encoder->base.dev;
89b667f8 2669 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2670 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2671 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9
JN		 2672 int pipe = intel_crtc->pipe;
2673 u32 val;
a4fc5ed6 2674
ab1f90f9 2675 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2676
ab3c759a 2677 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2678 val = 0;
2679 if (pipe)
2680 val |= (1<<21);
2681 else
2682 val &= ~(1<<21);
2683 val |= 0x001000c4;
ab3c759a
CML		 2684 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2685 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2686 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2687
ab1f90f9
JN		 2688 mutex_unlock(&dev_priv->dpio_lock);
2689
2690 intel_enable_dp(encoder);
89b667f8
JB		 2691}
2692
ecff4f3b 2693static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2694{
2695 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2696 struct drm_device *dev = encoder->base.dev;
2697 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2698 struct intel_crtc *intel_crtc =
2699 to_intel_crtc(encoder->base.crtc);
e4607fcf 2700 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2701 int pipe = intel_crtc->pipe;
89b667f8 2702
8ac33ed3
DV		 2703 intel_dp_prepare(encoder);
2704
89b667f8 2705 /* Program Tx lane resets to default */
0980a60f 2706 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2707 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2708 DPIO_PCS_TX_LANE2_RESET |
2709 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2710 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2711 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2712 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2713 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2714 DPIO_PCS_CLK_SOFT_RESET);
2715
2716 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2717 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2718 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2719 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2720 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2721}
2722
e4a1d846
CML		 2723static void chv_pre_enable_dp(struct intel_encoder *encoder)
2724{
2725 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2726 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2727 struct drm_device *dev = encoder->base.dev;
2728 struct drm_i915_private *dev_priv = dev->dev_private;
e4a1d846
CML		 2729 struct intel_crtc *intel_crtc =
2730 to_intel_crtc(encoder->base.crtc);
2731 enum dpio_channel ch = vlv_dport_to_channel(dport);
2732 int pipe = intel_crtc->pipe;
2733 int data, i;
949c1d43 2734 u32 val;
e4a1d846 2735
e4a1d846 2736 mutex_lock(&dev_priv->dpio_lock);
949c1d43 2737
570e2a74
VS		 2738 /* allow hardware to manage TX FIFO reset source */
2739 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2740 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2741 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2742
2743 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2744 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2745 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
2746
949c1d43 2747 /* Deassert soft data lane reset*/
97fd4d5c 2748 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2749 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2750 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2751
2752 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2753 val |= CHV_PCS_REQ_SOFTRESET_EN;
2754 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2755
2756 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2757 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2758 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2759
97fd4d5c 2760 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2761 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2762 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2763
2764 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2765 for (i = 0; i < 4; i++) {
2766 /* Set the latency optimal bit */
2767 data = (i == 1) ? 0x0 : 0x6;
2768 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2769 data << DPIO_FRC_LATENCY_SHFIT);
2770
2771 /* Set the upar bit */
2772 data = (i == 1) ? 0x0 : 0x1;
2773 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2774 data << DPIO_UPAR_SHIFT);
2775 }
2776
2777 /* Data lane stagger programming */
2778 /* FIXME: Fix up value only after power analysis */
2779
2780 mutex_unlock(&dev_priv->dpio_lock);
2781
e4a1d846 2782 intel_enable_dp(encoder);
e4a1d846
CML		 2783}
2784
9197c88b
VS		 2785static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2786{
2787 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2788 struct drm_device *dev = encoder->base.dev;
2789 struct drm_i915_private *dev_priv = dev->dev_private;
2790 struct intel_crtc *intel_crtc =
2791 to_intel_crtc(encoder->base.crtc);
2792 enum dpio_channel ch = vlv_dport_to_channel(dport);
2793 enum pipe pipe = intel_crtc->pipe;
2794 u32 val;
2795
625695f8
VS		 2796 intel_dp_prepare(encoder);
2797
9197c88b
VS		 2798 mutex_lock(&dev_priv->dpio_lock);
2799
b9e5ac3c
VS		 2800 /* program left/right clock distribution */
2801 if (pipe != PIPE_B) {
2802 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2803 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2804 if (ch == DPIO_CH0)
2805 val |= CHV_BUFLEFTENA1_FORCE;
2806 if (ch == DPIO_CH1)
2807 val |= CHV_BUFRIGHTENA1_FORCE;
2808 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2809 } else {
2810 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2811 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2812 if (ch == DPIO_CH0)
2813 val |= CHV_BUFLEFTENA2_FORCE;
2814 if (ch == DPIO_CH1)
2815 val |= CHV_BUFRIGHTENA2_FORCE;
2816 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2817 }
2818
9197c88b
VS		 2819 /* program clock channel usage */
2820 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2821 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2822 if (pipe != PIPE_B)
2823 val &= ~CHV_PCS_USEDCLKCHANNEL;
2824 else
2825 val |= CHV_PCS_USEDCLKCHANNEL;
2826 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2827
2828 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2829 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2830 if (pipe != PIPE_B)
2831 val &= ~CHV_PCS_USEDCLKCHANNEL;
2832 else
2833 val |= CHV_PCS_USEDCLKCHANNEL;
2834 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2835
2836 /*
2837 * This a a bit weird since generally CL
2838 * matches the pipe, but here we need to
2839 * pick the CL based on the port.
2840 */
2841 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2842 if (pipe != PIPE_B)
2843 val &= ~CHV_CMN_USEDCLKCHANNEL;
2844 else
2845 val |= CHV_CMN_USEDCLKCHANNEL;
2846 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2847
2848 mutex_unlock(&dev_priv->dpio_lock);
2849}
2850
a4fc5ed6 2851/*
df0c237d
JB		 2852 * Native read with retry for link status and receiver capability reads for
2853 * cases where the sink may still be asleep.
9d1a1031
JN		 2854 *
2855 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2856 * supposed to retry 3 times per the spec.
a4fc5ed6 2857 */
9d1a1031
JN		 2858static ssize_t
2859intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2860 void *buffer, size_t size)
a4fc5ed6 2861{
9d1a1031
JN		 2862 ssize_t ret;
2863 int i;
61da5fab 2864
61da5fab 2865 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2866 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2867 if (ret == size)
2868 return ret;
61da5fab
JB		 2869 msleep(1);
2870 }
a4fc5ed6 2871
9d1a1031 2872 return ret;
a4fc5ed6
KP		 2873}
2874
2875/*
2876 * Fetch AUX CH registers 0x202 - 0x207 which contain
2877 * link status information
2878 */
2879static bool
93f62dad 2880intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2881{
9d1a1031
JN		 2882 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2883 DP_LANE0_1_STATUS,
2884 link_status,
2885 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2886}
2887
1100244e 2888/* These are source-specific values. */
a4fc5ed6 2889static uint8_t
1a2eb460 2890intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2891{
30add22d 2892 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2893 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2894
5a9d1f1a
DL		 2895 if (INTEL_INFO(dev)->gen >= 9)
2896 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
2897 else if (IS_VALLEYVIEW(dev))
bd60018a 2898 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2899 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2900 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2901 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2902 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2903 else
bd60018a 2904 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2905}
2906
2907static uint8_t
2908intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2909{
30add22d 2910 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2911 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2912
5a9d1f1a
DL		 2913 if (INTEL_INFO(dev)->gen >= 9) {
2914 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2915 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2916 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2917 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2918 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2919 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2920 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2921 default:
2922 return DP_TRAIN_PRE_EMPH_LEVEL_0;
2923 }
2924 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2925 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2926 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2927 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2928 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2929 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2930 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2931 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2932 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2933 default:
bd60018a 2934 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2935 }
e2fa6fba
P		 2936 } else if (IS_VALLEYVIEW(dev)) {
2937 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2938 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2939 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2940 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2941 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2942 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2943 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2944 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2945 default:
bd60018a 2946 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2947 }
bc7d38a4 2948 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2949 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2950 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2951 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2952 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2953 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2954 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2955 default:
bd60018a 2956 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2957 }
2958 } else {
2959 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2960 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2961 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2962 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2963 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2964 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2965 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2966 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2967 default:
bd60018a 2968 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2969 }
a4fc5ed6
KP		 2970 }
2971}
2972
e2fa6fba
P		 2973static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2974{
2975 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2976 struct drm_i915_private *dev_priv = dev->dev_private;
2977 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2978 struct intel_crtc *intel_crtc =
2979 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2980 unsigned long demph_reg_value, preemph_reg_value,
2981 uniqtranscale_reg_value;
2982 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2983 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2984 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2985
2986 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2987 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2988 preemph_reg_value = 0x0004000;
2989 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2990 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2991 demph_reg_value = 0x2B405555;
2992 uniqtranscale_reg_value = 0x552AB83A;
2993 break;
bd60018a 2994 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2995 demph_reg_value = 0x2B404040;
2996 uniqtranscale_reg_value = 0x5548B83A;
2997 break;
bd60018a 2998 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2999 demph_reg_value = 0x2B245555;
3000 uniqtranscale_reg_value = 0x5560B83A;
3001 break;
bd60018a 3002 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 3003 demph_reg_value = 0x2B405555;
3004 uniqtranscale_reg_value = 0x5598DA3A;
3005 break;
3006 default:
3007 return 0;
3008 }
3009 break;
bd60018a 3010 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 3011 preemph_reg_value = 0x0002000;
3012 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3013 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3014 demph_reg_value = 0x2B404040;
3015 uniqtranscale_reg_value = 0x5552B83A;
3016 break;
bd60018a 3017 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3018 demph_reg_value = 0x2B404848;
3019 uniqtranscale_reg_value = 0x5580B83A;
3020 break;
bd60018a 3021 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 3022 demph_reg_value = 0x2B404040;
3023 uniqtranscale_reg_value = 0x55ADDA3A;
3024 break;
3025 default:
3026 return 0;
3027 }
3028 break;
bd60018a 3029 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 3030 preemph_reg_value = 0x0000000;
3031 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3032 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3033 demph_reg_value = 0x2B305555;
3034 uniqtranscale_reg_value = 0x5570B83A;
3035 break;
bd60018a 3036 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 3037 demph_reg_value = 0x2B2B4040;
3038 uniqtranscale_reg_value = 0x55ADDA3A;
3039 break;
3040 default:
3041 return 0;
3042 }
3043 break;
bd60018a 3044 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 3045 preemph_reg_value = 0x0006000;
3046 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3047 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 3048 demph_reg_value = 0x1B405555;
3049 uniqtranscale_reg_value = 0x55ADDA3A;
3050 break;
3051 default:
3052 return 0;
3053 }
3054 break;
3055 default:
3056 return 0;
3057 }
3058
0980a60f 3059 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 3060 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3061 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3062 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 3063 uniqtranscale_reg_value);
ab3c759a
CML		 3064 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3065 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3066 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3067 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 3068 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 3069
3070 return 0;
3071}
3072
e4a1d846
CML		 3073static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
3074{
3075 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3076 struct drm_i915_private *dev_priv = dev->dev_private;
3077 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3078 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 3079 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 3080 uint8_t train_set = intel_dp->train_set[0];
3081 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 3082 enum pipe pipe = intel_crtc->pipe;
3083 int i;
e4a1d846
CML		 3084
3085 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3086 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 3087 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3088 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3089 deemph_reg_value = 128;
3090 margin_reg_value = 52;
3091 break;
bd60018a 3092 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3093 deemph_reg_value = 128;
3094 margin_reg_value = 77;
3095 break;
bd60018a 3096 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3097 deemph_reg_value = 128;
3098 margin_reg_value = 102;
3099 break;
bd60018a 3100 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 3101 deemph_reg_value = 128;
3102 margin_reg_value = 154;
3103 /* FIXME extra to set for 1200 */
3104 break;
3105 default:
3106 return 0;
3107 }
3108 break;
bd60018a 3109 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 3110 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3111 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3112 deemph_reg_value = 85;
3113 margin_reg_value = 78;
3114 break;
bd60018a 3115 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3116 deemph_reg_value = 85;
3117 margin_reg_value = 116;
3118 break;
bd60018a 3119 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 3120 deemph_reg_value = 85;
3121 margin_reg_value = 154;
3122 break;
3123 default:
3124 return 0;
3125 }
3126 break;
bd60018a 3127 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 3128 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3129 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3130 deemph_reg_value = 64;
3131 margin_reg_value = 104;
3132 break;
bd60018a 3133 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 3134 deemph_reg_value = 64;
3135 margin_reg_value = 154;
3136 break;
3137 default:
3138 return 0;
3139 }
3140 break;
bd60018a 3141 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 3142 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3143 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 3144 deemph_reg_value = 43;
3145 margin_reg_value = 154;
3146 break;
3147 default:
3148 return 0;
3149 }
3150 break;
3151 default:
3152 return 0;
3153 }
3154
3155 mutex_lock(&dev_priv->dpio_lock);
3156
3157 /* Clear calc init */
1966e59e
VS		 3158 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3159 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3160 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3161 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 3162 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3163
3164 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3165 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 3166 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3167 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 3168 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 3169
a02ef3c7
VS		 3170 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3171 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3172 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3173 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3174
3175 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3176 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3177 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3178 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3179
e4a1d846 3180 /* Program swing deemph */
f72df8db
VS		 3181 for (i = 0; i < 4; i++) {
3182 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3183 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3184 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3185 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3186 }
e4a1d846
CML		 3187
3188 /* Program swing margin */
f72df8db
VS		 3189 for (i = 0; i < 4; i++) {
3190 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 3191 val &= ~DPIO_SWING_MARGIN000_MASK;
3192 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 3193 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3194 }
e4a1d846
CML		 3195
3196 /* Disable unique transition scale */
f72df8db
VS		 3197 for (i = 0; i < 4; i++) {
3198 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3199 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3200 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3201 }
e4a1d846
CML		 3202
3203 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 3204 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 3205 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 3206 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 3207
3208 /*
3209 * The document said it needs to set bit 27 for ch0 and bit 26
3210 * for ch1. Might be a typo in the doc.
3211 * For now, for this unique transition scale selection, set bit
3212 * 27 for ch0 and ch1.
3213 */
f72df8db
VS		 3214 for (i = 0; i < 4; i++) {
3215 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3216 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3217 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3218 }
e4a1d846 3219
f72df8db
VS		 3220 for (i = 0; i < 4; i++) {
3221 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3222 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3223 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3224 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3225 }
e4a1d846
CML		 3226 }
3227
3228 /* Start swing calculation */
1966e59e
VS		 3229 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3230 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3231 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3232
3233 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3234 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3235 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 3236
3237 /* LRC Bypass */
3238 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
3239 val |= DPIO_LRC_BYPASS;
3240 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
3241
3242 mutex_unlock(&dev_priv->dpio_lock);
3243
3244 return 0;
3245}
3246
a4fc5ed6 3247static void
0301b3ac
JN		 3248intel_get_adjust_train(struct intel_dp *intel_dp,
3249 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 3250{
3251 uint8_t v = 0;
3252 uint8_t p = 0;
3253 int lane;
1a2eb460
KP		 3254 uint8_t voltage_max;
3255 uint8_t preemph_max;
a4fc5ed6 3256
33a34e4e 3257 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 3258 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
3259 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 3260
3261 if (this_v > v)
3262 v = this_v;
3263 if (this_p > p)
3264 p = this_p;
3265 }
3266
1a2eb460 3267 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 3268 if (v >= voltage_max)
3269 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 3270
1a2eb460
KP		 3271 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
3272 if (p >= preemph_max)
3273 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 3274
3275 for (lane = 0; lane < 4; lane++)
33a34e4e 3276 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 3277}
3278
3279static uint32_t
f0a3424e 3280intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 3281{
3cf2efb1 3282 uint32_t signal_levels = 0;
a4fc5ed6 3283
3cf2efb1 3284 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 3285 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 3286 default:
3287 signal_levels |= DP_VOLTAGE_0_4;
3288 break;
bd60018a 3289 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 3290 signal_levels |= DP_VOLTAGE_0_6;
3291 break;
bd60018a 3292 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 3293 signal_levels |= DP_VOLTAGE_0_8;
3294 break;
bd60018a 3295 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 3296 signal_levels |= DP_VOLTAGE_1_2;
3297 break;
3298 }
3cf2efb1 3299 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 3300 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 3301 default:
3302 signal_levels |= DP_PRE_EMPHASIS_0;
3303 break;
bd60018a 3304 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 3305 signal_levels |= DP_PRE_EMPHASIS_3_5;
3306 break;
bd60018a 3307 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 3308 signal_levels |= DP_PRE_EMPHASIS_6;
3309 break;
bd60018a 3310 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 3311 signal_levels |= DP_PRE_EMPHASIS_9_5;
3312 break;
3313 }
3314 return signal_levels;
3315}
3316
e3421a18
ZW		 3317/* Gen6's DP voltage swing and pre-emphasis control */
3318static uint32_t
3319intel_gen6_edp_signal_levels(uint8_t train_set)
3320{
3c5a62b5
YL		 3321 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3322 DP_TRAIN_PRE_EMPHASIS_MASK);
3323 switch (signal_levels) {
bd60018a
SJ		 3324 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3325 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3326 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 3327 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3328 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 3329 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3330 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 3331 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 3332 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3333 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 3334 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 3335 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3336 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 3337 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 3338 default:
3c5a62b5
YL		 3339 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3340 "0x%x\n", signal_levels);
3341 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 3342 }
3343}
3344
1a2eb460
KP		 3345/* Gen7's DP voltage swing and pre-emphasis control */
3346static uint32_t
3347intel_gen7_edp_signal_levels(uint8_t train_set)
3348{
3349 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3350 DP_TRAIN_PRE_EMPHASIS_MASK);
3351 switch (signal_levels) {
bd60018a 3352 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3353 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 3354 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 3355 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 3356 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 3357 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3358
bd60018a 3359 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3360 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 3361 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3362 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3363
bd60018a 3364 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 3365 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 3366 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 3367 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3368
3369 default:
3370 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3371 "0x%x\n", signal_levels);
3372 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3373 }
3374}
3375
d6c0d722
PZ		 3376/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
3377static uint32_t
f0a3424e 3378intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 3379{
d6c0d722
PZ		 3380 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3381 DP_TRAIN_PRE_EMPHASIS_MASK);
3382 switch (signal_levels) {
bd60018a 3383 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3384 return DDI_BUF_TRANS_SELECT(0);
bd60018a 3385 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3386 return DDI_BUF_TRANS_SELECT(1);
bd60018a 3387 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3388 return DDI_BUF_TRANS_SELECT(2);
bd60018a 3389 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 3390 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 3391
bd60018a 3392 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3393 return DDI_BUF_TRANS_SELECT(4);
bd60018a 3394 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3395 return DDI_BUF_TRANS_SELECT(5);
bd60018a 3396 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 3397 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 3398
bd60018a 3399 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 3400 return DDI_BUF_TRANS_SELECT(7);
bd60018a 3401 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 3402 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 3403 default:
3404 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3405 "0x%x\n", signal_levels);
c5fe6a06 3406 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 3407 }
a4fc5ed6
KP		 3408}
3409
f0a3424e
PZ		 3410/* Properly updates "DP" with the correct signal levels. */
3411static void
3412intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
3413{
3414 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3415 enum port port = intel_dig_port->port;
f0a3424e
PZ		 3416 struct drm_device *dev = intel_dig_port->base.base.dev;
3417 uint32_t signal_levels, mask;
3418 uint8_t train_set = intel_dp->train_set[0];
3419
5a9d1f1a 3420 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
f0a3424e
PZ		 3421 signal_levels = intel_hsw_signal_levels(train_set);
3422 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3423 } else if (IS_CHERRYVIEW(dev)) {
3424 signal_levels = intel_chv_signal_levels(intel_dp);
3425 mask = 0;
e2fa6fba
P		 3426 } else if (IS_VALLEYVIEW(dev)) {
3427 signal_levels = intel_vlv_signal_levels(intel_dp);
3428 mask = 0;
bc7d38a4 3429 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3430 signal_levels = intel_gen7_edp_signal_levels(train_set);
3431 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3432 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3433 signal_levels = intel_gen6_edp_signal_levels(train_set);
3434 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3435 } else {
3436 signal_levels = intel_gen4_signal_levels(train_set);
3437 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3438 }
3439
3440 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3441
3442 *DP = (*DP & ~mask) | signal_levels;
3443}
3444
a4fc5ed6 3445static bool
ea5b213a 3446intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3447 uint32_t *DP,
58e10eb9 3448 uint8_t dp_train_pat)
a4fc5ed6 3449{
174edf1f
PZ		 3450 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3451 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3452 struct drm_i915_private *dev_priv = dev->dev_private;
2cdfe6c8
JN		 3453 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3454 int ret, len;
a4fc5ed6 3455
7b13b58a 3456 _intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
47ea7542 3457
70aff66c 3458 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3459 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3460
2cdfe6c8
JN		 3461 buf[0] = dp_train_pat;
3462 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3463 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3464 /* don't write DP_TRAINING_LANEx_SET on disable */
3465 len = 1;
3466 } else {
3467 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3468 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3469 len = intel_dp->lane_count + 1;
47ea7542 3470 }
a4fc5ed6 3471
9d1a1031
JN		 3472 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3473 buf, len);
2cdfe6c8
JN		 3474
3475 return ret == len;
a4fc5ed6
KP		 3476}
3477
70aff66c
JN		 3478static bool
3479intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3480 uint8_t dp_train_pat)
3481{
953d22e8 3482 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3483 intel_dp_set_signal_levels(intel_dp, DP);
3484 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3485}
3486
3487static bool
3488intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3489 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3490{
3491 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3492 struct drm_device *dev = intel_dig_port->base.base.dev;
3493 struct drm_i915_private *dev_priv = dev->dev_private;
3494 int ret;
3495
3496 intel_get_adjust_train(intel_dp, link_status);
3497 intel_dp_set_signal_levels(intel_dp, DP);
3498
3499 I915_WRITE(intel_dp->output_reg, *DP);
3500 POSTING_READ(intel_dp->output_reg);
3501
9d1a1031
JN		 3502 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3503 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3504
3505 return ret == intel_dp->lane_count;
3506}
3507
3ab9c637
ID		 3508static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3509{
3510 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3511 struct drm_device *dev = intel_dig_port->base.base.dev;
3512 struct drm_i915_private *dev_priv = dev->dev_private;
3513 enum port port = intel_dig_port->port;
3514 uint32_t val;
3515
3516 if (!HAS_DDI(dev))
3517 return;
3518
3519 val = I915_READ(DP_TP_CTL(port));
3520 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3521 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3522 I915_WRITE(DP_TP_CTL(port), val);
3523
3524 /*
3525 * On PORT_A we can have only eDP in SST mode. There the only reason
3526 * we need to set idle transmission mode is to work around a HW issue
3527 * where we enable the pipe while not in idle link-training mode.
3528 * In this case there is requirement to wait for a minimum number of
3529 * idle patterns to be sent.
3530 */
3531 if (port == PORT_A)
3532 return;
3533
3534 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3535 1))
3536 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3537}
3538
33a34e4e 3539/* Enable corresponding port and start training pattern 1 */
c19b0669 3540void
33a34e4e 3541intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3542{
da63a9f2 3543 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3544 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3545 int i;
3546 uint8_t voltage;
cdb0e95b 3547 int voltage_tries, loop_tries;
ea5b213a 3548 uint32_t DP = intel_dp->DP;
6aba5b6c 3549 uint8_t link_config[2];
a4fc5ed6 3550
affa9354 3551 if (HAS_DDI(dev))
c19b0669
PZ		 3552 intel_ddi_prepare_link_retrain(encoder);
3553
3cf2efb1 3554 /* Write the link configuration data */
6aba5b6c
JN		 3555 link_config[0] = intel_dp->link_bw;
3556 link_config[1] = intel_dp->lane_count;
3557 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3558 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3559 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3560
3561 link_config[0] = 0;
3562 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3563 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3564
3565 DP |= DP_PORT_EN;
1a2eb460 3566
70aff66c
JN		 3567 /* clock recovery */
3568 if (!intel_dp_reset_link_train(intel_dp, &DP,
3569 DP_TRAINING_PATTERN_1 |
3570 DP_LINK_SCRAMBLING_DISABLE)) {
3571 DRM_ERROR("failed to enable link training\n");
3572 return;
3573 }
3574
a4fc5ed6 3575 voltage = 0xff;
cdb0e95b
KP		 3576 voltage_tries = 0;
3577 loop_tries = 0;
a4fc5ed6 3578 for (;;) {
70aff66c 3579 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3580
a7c9655f 3581 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3582 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3583 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3584 break;
93f62dad 3585 }
a4fc5ed6 3586
01916270 3587 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3588 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3589 break;
3590 }
3591
3592 /* Check to see if we've tried the max voltage */
3593 for (i = 0; i < intel_dp->lane_count; i++)
3594 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3595 break;
3b4f819d 3596 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3597 ++loop_tries;
3598 if (loop_tries == 5) {
3def84b3 3599 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3600 break;
3601 }
70aff66c
JN		 3602 intel_dp_reset_link_train(intel_dp, &DP,
3603 DP_TRAINING_PATTERN_1 |
3604 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3605 voltage_tries = 0;
3606 continue;
3607 }
a4fc5ed6 3608
3cf2efb1 3609 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3610 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3611 ++voltage_tries;
b06fbda3 3612 if (voltage_tries == 5) {
3def84b3 3613 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3614 break;
3615 }
3616 } else
3617 voltage_tries = 0;
3618 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3619
70aff66c
JN		 3620 /* Update training set as requested by target */
3621 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3622 DRM_ERROR("failed to update link training\n");
3623 break;
3624 }
a4fc5ed6
KP		 3625 }
3626
33a34e4e
JB		 3627 intel_dp->DP = DP;
3628}
3629
c19b0669 3630void
33a34e4e
JB		 3631intel_dp_complete_link_train(struct intel_dp *intel_dp)
3632{
33a34e4e 3633 bool channel_eq = false;
37f80975 3634 int tries, cr_tries;
33a34e4e 3635 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3636 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3637
3638 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3639 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3640 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3641
a4fc5ed6 3642 /* channel equalization */
70aff66c 3643 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3644 training_pattern |
70aff66c
JN		 3645 DP_LINK_SCRAMBLING_DISABLE)) {
3646 DRM_ERROR("failed to start channel equalization\n");
3647 return;
3648 }
3649
a4fc5ed6 3650 tries = 0;
37f80975 3651 cr_tries = 0;
a4fc5ed6
KP		 3652 channel_eq = false;
3653 for (;;) {
70aff66c 3654 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3655
37f80975
JB		 3656 if (cr_tries > 5) {
3657 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3658 break;
3659 }
3660
a7c9655f 3661 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3662 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3663 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3664 break;
70aff66c 3665 }
a4fc5ed6 3666
37f80975 3667 /* Make sure clock is still ok */
01916270 3668 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3669 intel_dp_start_link_train(intel_dp);
70aff66c 3670 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3671 training_pattern |
70aff66c 3672 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3673 cr_tries++;
3674 continue;
3675 }
3676
1ffdff13 3677 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3678 channel_eq = true;
3679 break;
3680 }
a4fc5ed6 3681
37f80975
JB		 3682 /* Try 5 times, then try clock recovery if that fails */
3683 if (tries > 5) {
3684 intel_dp_link_down(intel_dp);
3685 intel_dp_start_link_train(intel_dp);
70aff66c 3686 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3687 training_pattern |
70aff66c 3688 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3689 tries = 0;
3690 cr_tries++;
3691 continue;
3692 }
a4fc5ed6 3693
70aff66c
JN		 3694 /* Update training set as requested by target */
3695 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3696 DRM_ERROR("failed to update link training\n");
3697 break;
3698 }
3cf2efb1 3699 ++tries;
869184a6 3700 }
3cf2efb1 3701
3ab9c637
ID		 3702 intel_dp_set_idle_link_train(intel_dp);
3703
3704 intel_dp->DP = DP;
3705
d6c0d722 3706 if (channel_eq)
07f42258 3707 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3708
3ab9c637
ID		 3709}
3710
3711void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3712{
70aff66c 3713 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3714 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3715}
3716
3717static void
ea5b213a 3718intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3719{
da63a9f2 3720 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3721 enum port port = intel_dig_port->port;
da63a9f2 3722 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3723 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3724 struct intel_crtc *intel_crtc =
3725 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3726 uint32_t DP = intel_dp->DP;
a4fc5ed6 3727
bc76e320 3728 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3729 return;
3730
0c33d8d7 3731 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3732 return;
3733
28c97730 3734 DRM_DEBUG_KMS("\n");
32f9d658 3735
bc7d38a4 3736 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3737 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3738 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3739 } else {
aad3d14d
VS		 3740 if (IS_CHERRYVIEW(dev))
3741 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3742 else
3743 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3744 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3745 }
fe255d00 3746 POSTING_READ(intel_dp->output_reg);
5eb08b69 3747
493a7081 3748 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3749 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3750 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3751
5bddd17f
EA		 3752 /* Hardware workaround: leaving our transcoder select
3753 * set to transcoder B while it's off will prevent the
3754 * corresponding HDMI output on transcoder A.
3755 *
3756 * Combine this with another hardware workaround:
3757 * transcoder select bit can only be cleared while the
3758 * port is enabled.
3759 */
3760 DP &= ~DP_PIPEB_SELECT;
3761 I915_WRITE(intel_dp->output_reg, DP);
3762
3763 /* Changes to enable or select take place the vblank
3764 * after being written.
3765 */
ff50afe9
DV		 3766 if (WARN_ON(crtc == NULL)) {
3767 /* We should never try to disable a port without a crtc
3768 * attached. For paranoia keep the code around for a
3769 * bit. */
31acbcc4
CW		 3770 POSTING_READ(intel_dp->output_reg);
3771 msleep(50);
3772 } else
ab527efc 3773 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3774 }
3775
832afda6 3776 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3777 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3778 POSTING_READ(intel_dp->output_reg);
f01eca2e 3779 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3780}
3781
26d61aad
KP		 3782static bool
3783intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3784{
a031d709
RV		 3785 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3786 struct drm_device *dev = dig_port->base.base.dev;
3787 struct drm_i915_private *dev_priv = dev->dev_private;
3788
9d1a1031
JN		 3789 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3790 sizeof(intel_dp->dpcd)) < 0)
edb39244 3791 return false; /* aux transfer failed */
92fd8fd1 3792
a8e98153 3793 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3794
edb39244
AJ		 3795 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3796 return false; /* DPCD not present */
3797
2293bb5c
SK		 3798 /* Check if the panel supports PSR */
3799 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3800 if (is_edp(intel_dp)) {
9d1a1031
JN		 3801 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3802 intel_dp->psr_dpcd,
3803 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3804 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3805 dev_priv->psr.sink_support = true;
50003939 3806 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3807 }
50003939
JN		 3808 }
3809
06ea66b6
TP		 3810 /* Training Pattern 3 support */
3811 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3812 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3813 intel_dp->use_tps3 = true;
f8d8a672 3814 DRM_DEBUG_KMS("Displayport TPS3 supported\n");
06ea66b6
TP		 3815 } else
3816 intel_dp->use_tps3 = false;
3817
edb39244
AJ		 3818 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3819 DP_DWN_STRM_PORT_PRESENT))
3820 return true; /* native DP sink */
3821
3822 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3823 return true; /* no per-port downstream info */
3824
9d1a1031
JN		 3825 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3826 intel_dp->downstream_ports,
3827 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3828 return false; /* downstream port status fetch failed */
3829
3830 return true;
92fd8fd1
KP		 3831}
3832
0d198328
AJ		 3833static void
3834intel_dp_probe_oui(struct intel_dp *intel_dp)
3835{
3836 u8 buf[3];
3837
3838 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3839 return;
3840
9d1a1031 3841 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3842 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3843 buf[0], buf[1], buf[2]);
3844
9d1a1031 3845 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3846 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3847 buf[0], buf[1], buf[2]);
3848}
3849
0e32b39c
DA		 3850static bool
3851intel_dp_probe_mst(struct intel_dp *intel_dp)
3852{
3853 u8 buf[1];
3854
3855 if (!intel_dp->can_mst)
3856 return false;
3857
3858 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3859 return false;
3860
0e32b39c
DA		 3861 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3862 if (buf[0] & DP_MST_CAP) {
3863 DRM_DEBUG_KMS("Sink is MST capable\n");
3864 intel_dp->is_mst = true;
3865 } else {
3866 DRM_DEBUG_KMS("Sink is not MST capable\n");
3867 intel_dp->is_mst = false;
3868 }
3869 }
0e32b39c
DA		 3870
3871 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3872 return intel_dp->is_mst;
3873}
3874
d2e216d0
RV		 3875int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3876{
3877 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3878 struct drm_device *dev = intel_dig_port->base.base.dev;
3879 struct intel_crtc *intel_crtc =
3880 to_intel_crtc(intel_dig_port->base.base.crtc);
ad9dc91b
RV		 3881 u8 buf;
3882 int test_crc_count;
3883 int attempts = 6;
d2e216d0 3884
ad9dc91b 3885 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3886 return -EIO;
d2e216d0 3887
ad9dc91b 3888 if (!(buf & DP_TEST_CRC_SUPPORTED))
d2e216d0
RV		 3889 return -ENOTTY;
3890
1dda5f93
RV		 3891 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3892 return -EIO;
3893
9d1a1031 3894 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
ce31d9f4 3895 buf | DP_TEST_SINK_START) < 0)
bda0381e 3896 return -EIO;
d2e216d0 3897
1dda5f93 3898 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
bda0381e 3899 return -EIO;
ad9dc91b 3900 test_crc_count = buf & DP_TEST_COUNT_MASK;
d2e216d0 3901
ad9dc91b 3902 do {
1dda5f93
RV		 3903 if (drm_dp_dpcd_readb(&intel_dp->aux,
3904 DP_TEST_SINK_MISC, &buf) < 0)
3905 return -EIO;
ad9dc91b
RV		 3906 intel_wait_for_vblank(dev, intel_crtc->pipe);
3907 } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
3908
3909 if (attempts == 0) {
3910 DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
3911 return -EIO;
3912 }
d2e216d0 3913
9d1a1031 3914 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
bda0381e 3915 return -EIO;
d2e216d0 3916
1dda5f93
RV		 3917 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3918 return -EIO;
3919 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3920 buf & ~DP_TEST_SINK_START) < 0)
3921 return -EIO;
ce31d9f4 3922
d2e216d0
RV		 3923 return 0;
3924}
3925
a60f0e38
JB		 3926static bool
3927intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3928{
9d1a1031
JN		 3929 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3930 DP_DEVICE_SERVICE_IRQ_VECTOR,
3931 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3932}
3933
0e32b39c
DA		 3934static bool
3935intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3936{
3937 int ret;
3938
3939 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3940 DP_SINK_COUNT_ESI,
3941 sink_irq_vector, 14);
3942 if (ret != 14)
3943 return false;
3944
3945 return true;
3946}
3947
a60f0e38
JB		 3948static void
3949intel_dp_handle_test_request(struct intel_dp *intel_dp)
3950{
3951 /* NAK by default */
9d1a1031 3952 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3953}
3954
0e32b39c
DA		 3955static int
3956intel_dp_check_mst_status(struct intel_dp *intel_dp)
3957{
3958 bool bret;
3959
3960 if (intel_dp->is_mst) {
3961 u8 esi[16] = { 0 };
3962 int ret = 0;
3963 int retry;
3964 bool handled;
3965 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3966go_again:
3967 if (bret == true) {
3968
3969 /* check link status - esi[10] = 0x200c */
3970 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3971 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3972 intel_dp_start_link_train(intel_dp);
3973 intel_dp_complete_link_train(intel_dp);
3974 intel_dp_stop_link_train(intel_dp);
3975 }
3976
3977 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3978 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3979
3980 if (handled) {
3981 for (retry = 0; retry < 3; retry++) {
3982 int wret;
3983 wret = drm_dp_dpcd_write(&intel_dp->aux,
3984 DP_SINK_COUNT_ESI+1,
3985 &esi[1], 3);
3986 if (wret == 3) {
3987 break;
3988 }
3989 }
3990
3991 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3992 if (bret == true) {
3993 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3994 goto go_again;
3995 }
3996 } else
3997 ret = 0;
3998
3999 return ret;
4000 } else {
4001 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4002 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4003 intel_dp->is_mst = false;
4004 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4005 /* send a hotplug event */
4006 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4007 }
4008 }
4009 return -EINVAL;
4010}
4011
a4fc5ed6
KP		 4012/*
4013 * According to DP spec
4014 * 5.1.2:
4015 * 1. Read DPCD
4016 * 2. Configure link according to Receiver Capabilities
4017 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
4018 * 4. Check link status on receipt of hot-plug interrupt
4019 */
00c09d70 4020void
ea5b213a 4021intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 4022{
5b215bcf 4023 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 4024 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 4025 u8 sink_irq_vector;
93f62dad 4026 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 4027
5b215bcf
DA		 4028 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4029
da63a9f2 4030 if (!intel_encoder->connectors_active)
d2b996ac 4031 return;
59cd09e1 4032
da63a9f2 4033 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 4034 return;
4035
1a125d8a
ID		 4036 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4037 return;
4038
92fd8fd1 4039 /* Try to read receiver status if the link appears to be up */
93f62dad 4040 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 4041 return;
4042 }
4043
92fd8fd1 4044 /* Now read the DPCD to see if it's actually running */
26d61aad 4045 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 4046 return;
4047 }
4048
a60f0e38
JB		 4049 /* Try to read the source of the interrupt */
4050 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4051 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4052 /* Clear interrupt source */
9d1a1031
JN		 4053 drm_dp_dpcd_writeb(&intel_dp->aux,
4054 DP_DEVICE_SERVICE_IRQ_VECTOR,
4055 sink_irq_vector);
a60f0e38
JB		 4056
4057 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4058 intel_dp_handle_test_request(intel_dp);
4059 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4060 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4061 }
4062
1ffdff13 4063 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 4064 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 4065 intel_encoder->base.name);
33a34e4e
JB		 4066 intel_dp_start_link_train(intel_dp);
4067 intel_dp_complete_link_train(intel_dp);
3ab9c637 4068 intel_dp_stop_link_train(intel_dp);
33a34e4e 4069 }
a4fc5ed6 4070}
a4fc5ed6 4071
caf9ab24 4072/* XXX this is probably wrong for multiple downstream ports */
71ba9000 4073static enum drm_connector_status
26d61aad 4074intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 4075{
caf9ab24 4076 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 4077 uint8_t type;
4078
4079 if (!intel_dp_get_dpcd(intel_dp))
4080 return connector_status_disconnected;
4081
4082 /* if there's no downstream port, we're done */
4083 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 4084 return connector_status_connected;
caf9ab24
AJ		 4085
4086 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 4087 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4088 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 4089 uint8_t reg;
9d1a1031
JN		 4090
4091 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4092 &reg, 1) < 0)
caf9ab24 4093 return connector_status_unknown;
9d1a1031 4094
23235177
AJ		 4095 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4096 : connector_status_disconnected;
caf9ab24
AJ		 4097 }
4098
4099 /* If no HPD, poke DDC gently */
0b99836f 4100 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 4101 return connector_status_connected;
caf9ab24
AJ		 4102
4103 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 4104 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4105 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4106 if (type == DP_DS_PORT_TYPE_VGA ||
4107 type == DP_DS_PORT_TYPE_NON_EDID)
4108 return connector_status_unknown;
4109 } else {
4110 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4111 DP_DWN_STRM_PORT_TYPE_MASK;
4112 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4113 type == DP_DWN_STRM_PORT_TYPE_OTHER)
4114 return connector_status_unknown;
4115 }
caf9ab24
AJ		 4116
4117 /* Anything else is out of spec, warn and ignore */
4118 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 4119 return connector_status_disconnected;
71ba9000
AJ		 4120}
4121
d410b56d
CW		 4122static enum drm_connector_status
4123edp_detect(struct intel_dp *intel_dp)
4124{
4125 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4126 enum drm_connector_status status;
4127
4128 status = intel_panel_detect(dev);
4129 if (status == connector_status_unknown)
4130 status = connector_status_connected;
4131
4132 return status;
4133}
4134
5eb08b69 4135static enum drm_connector_status
a9756bb5 4136ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 4137{
30add22d 4138 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 4139 struct drm_i915_private *dev_priv = dev->dev_private;
4140 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 4141
1b469639
DL		 4142 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4143 return connector_status_disconnected;
4144
26d61aad 4145 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 4146}
4147
2a592bec
DA		 4148static int g4x_digital_port_connected(struct drm_device *dev,
4149 struct intel_digital_port *intel_dig_port)
a4fc5ed6 4150{
a4fc5ed6 4151 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 4152 uint32_t bit;
5eb08b69 4153
232a6ee9
TP		 4154 if (IS_VALLEYVIEW(dev)) {
4155 switch (intel_dig_port->port) {
4156 case PORT_B:
4157 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4158 break;
4159 case PORT_C:
4160 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4161 break;
4162 case PORT_D:
4163 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4164 break;
4165 default:
2a592bec 4166 return -EINVAL;
232a6ee9
TP		 4167 }
4168 } else {
4169 switch (intel_dig_port->port) {
4170 case PORT_B:
4171 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4172 break;
4173 case PORT_C:
4174 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4175 break;
4176 case PORT_D:
4177 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4178 break;
4179 default:
2a592bec 4180 return -EINVAL;
232a6ee9 4181 }
a4fc5ed6
KP		 4182 }
4183
10f76a38 4184 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2a592bec
DA		 4185 return 0;
4186 return 1;
4187}
4188
4189static enum drm_connector_status
4190g4x_dp_detect(struct intel_dp *intel_dp)
4191{
4192 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4193 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4194 int ret;
4195
4196 /* Can't disconnect eDP, but you can close the lid... */
4197 if (is_edp(intel_dp)) {
4198 enum drm_connector_status status;
4199
4200 status = intel_panel_detect(dev);
4201 if (status == connector_status_unknown)
4202 status = connector_status_connected;
4203 return status;
4204 }
4205
4206 ret = g4x_digital_port_connected(dev, intel_dig_port);
4207 if (ret == -EINVAL)
4208 return connector_status_unknown;
4209 else if (ret == 0)
a4fc5ed6
KP		 4210 return connector_status_disconnected;
4211
26d61aad 4212 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 4213}
4214
8c241fef 4215static struct edid *
beb60608 4216intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 4217{
beb60608 4218 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 4219
9cd300e0
JN		 4220 /* use cached edid if we have one */
4221 if (intel_connector->edid) {
9cd300e0
JN		 4222 /* invalid edid */
4223 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 4224 return NULL;
4225
55e9edeb 4226 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 4227 } else
4228 return drm_get_edid(&intel_connector->base,
4229 &intel_dp->aux.ddc);
4230}
8c241fef 4231
beb60608
CW		 4232static void
4233intel_dp_set_edid(struct intel_dp *intel_dp)
4234{
4235 struct intel_connector *intel_connector = intel_dp->attached_connector;
4236 struct edid *edid;
8c241fef 4237
beb60608
CW		 4238 edid = intel_dp_get_edid(intel_dp);
4239 intel_connector->detect_edid = edid;
4240
4241 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4242 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4243 else
4244 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 4245}
4246
beb60608
CW		 4247static void
4248intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 4249{
beb60608 4250 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 4251
beb60608
CW		 4252 kfree(intel_connector->detect_edid);
4253 intel_connector->detect_edid = NULL;
9cd300e0 4254
beb60608
CW		 4255 intel_dp->has_audio = false;
4256}
d6f24d0f 4257
beb60608
CW		 4258static enum intel_display_power_domain
4259intel_dp_power_get(struct intel_dp *dp)
4260{
4261 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4262 enum intel_display_power_domain power_domain;
4263
4264 power_domain = intel_display_port_power_domain(encoder);
4265 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
4266
4267 return power_domain;
4268}
d6f24d0f 4269
beb60608
CW		 4270static void
4271intel_dp_power_put(struct intel_dp *dp,
4272 enum intel_display_power_domain power_domain)
4273{
4274 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
4275 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 4276}
4277
a9756bb5
ZW		 4278static enum drm_connector_status
4279intel_dp_detect(struct drm_connector *connector, bool force)
4280{
4281 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 4282 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4283 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 4284 struct drm_device *dev = connector->dev;
a9756bb5 4285 enum drm_connector_status status;
671dedd2 4286 enum intel_display_power_domain power_domain;
0e32b39c 4287 bool ret;
a9756bb5 4288
164c8598 4289 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 4290 connector->base.id, connector->name);
beb60608 4291 intel_dp_unset_edid(intel_dp);
164c8598 4292
0e32b39c
DA		 4293 if (intel_dp->is_mst) {
4294 /* MST devices are disconnected from a monitor POV */
4295 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4296 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 4297 return connector_status_disconnected;
0e32b39c
DA		 4298 }
4299
beb60608 4300 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 4301
d410b56d
CW		 4302 /* Can't disconnect eDP, but you can close the lid... */
4303 if (is_edp(intel_dp))
4304 status = edp_detect(intel_dp);
4305 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 4306 status = ironlake_dp_detect(intel_dp);
4307 else
4308 status = g4x_dp_detect(intel_dp);
4309 if (status != connector_status_connected)
c8c8fb33 4310 goto out;
a9756bb5 4311
0d198328
AJ		 4312 intel_dp_probe_oui(intel_dp);
4313
0e32b39c
DA		 4314 ret = intel_dp_probe_mst(intel_dp);
4315 if (ret) {
4316 /* if we are in MST mode then this connector
4317 won't appear connected or have anything with EDID on it */
4318 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4319 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4320 status = connector_status_disconnected;
4321 goto out;
4322 }
4323
beb60608 4324 intel_dp_set_edid(intel_dp);
a9756bb5 4325
d63885da
PZ		 4326 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4327 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 4328 status = connector_status_connected;
4329
4330out:
beb60608 4331 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 4332 return status;
a4fc5ed6
KP		 4333}
4334
beb60608
CW		 4335static void
4336intel_dp_force(struct drm_connector *connector)
a4fc5ed6 4337{
df0e9248 4338 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 4339 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 4340 enum intel_display_power_domain power_domain;
a4fc5ed6 4341
beb60608
CW		 4342 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4343 connector->base.id, connector->name);
4344 intel_dp_unset_edid(intel_dp);
a4fc5ed6 4345
beb60608
CW		 4346 if (connector->status != connector_status_connected)
4347 return;
671dedd2 4348
beb60608
CW		 4349 power_domain = intel_dp_power_get(intel_dp);
4350
4351 intel_dp_set_edid(intel_dp);
4352
4353 intel_dp_power_put(intel_dp, power_domain);
4354
4355 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4356 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4357}
4358
4359static int intel_dp_get_modes(struct drm_connector *connector)
4360{
4361 struct intel_connector *intel_connector = to_intel_connector(connector);
4362 struct edid *edid;
4363
4364 edid = intel_connector->detect_edid;
4365 if (edid) {
4366 int ret = intel_connector_update_modes(connector, edid);
4367 if (ret)
4368 return ret;
4369 }
32f9d658 4370
f8779fda 4371 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 4372 if (is_edp(intel_attached_dp(connector)) &&
4373 intel_connector->panel.fixed_mode) {
f8779fda 4374 struct drm_display_mode *mode;
beb60608
CW		 4375
4376 mode = drm_mode_duplicate(connector->dev,
dd06f90e 4377 intel_connector->panel.fixed_mode);
f8779fda 4378 if (mode) {
32f9d658
ZW		 4379 drm_mode_probed_add(connector, mode);
4380 return 1;
4381 }
4382 }
beb60608 4383
32f9d658 4384 return 0;
a4fc5ed6
KP		 4385}
4386
1aad7ac0
CW		 4387static bool
4388intel_dp_detect_audio(struct drm_connector *connector)
4389{
1aad7ac0 4390 bool has_audio = false;
beb60608 4391 struct edid *edid;
1aad7ac0 4392
beb60608
CW		 4393 edid = to_intel_connector(connector)->detect_edid;
4394 if (edid)
1aad7ac0 4395 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4396
1aad7ac0
CW		 4397 return has_audio;
4398}
4399
f684960e
CW		 4400static int
4401intel_dp_set_property(struct drm_connector *connector,
4402 struct drm_property *property,
4403 uint64_t val)
4404{
e953fd7b 4405 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4406 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4407 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4408 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4409 int ret;
4410
662595df 4411 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4412 if (ret)
4413 return ret;
4414
3f43c48d 4415 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4416 int i = val;
4417 bool has_audio;
4418
4419 if (i == intel_dp->force_audio)
f684960e
CW		 4420 return 0;
4421
1aad7ac0 4422 intel_dp->force_audio = i;
f684960e 4423
c3e5f67b 4424 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4425 has_audio = intel_dp_detect_audio(connector);
4426 else
c3e5f67b 4427 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4428
4429 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4430 return 0;
4431
1aad7ac0 4432 intel_dp->has_audio = has_audio;
f684960e
CW		 4433 goto done;
4434 }
4435
e953fd7b 4436 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4437 bool old_auto = intel_dp->color_range_auto;
4438 uint32_t old_range = intel_dp->color_range;
4439
55bc60db
VS		 4440 switch (val) {
4441 case INTEL_BROADCAST_RGB_AUTO:
4442 intel_dp->color_range_auto = true;
4443 break;
4444 case INTEL_BROADCAST_RGB_FULL:
4445 intel_dp->color_range_auto = false;
4446 intel_dp->color_range = 0;
4447 break;
4448 case INTEL_BROADCAST_RGB_LIMITED:
4449 intel_dp->color_range_auto = false;
4450 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4451 break;
4452 default:
4453 return -EINVAL;
4454 }
ae4edb80
DV		 4455
4456 if (old_auto == intel_dp->color_range_auto &&
4457 old_range == intel_dp->color_range)
4458 return 0;
4459
e953fd7b
CW		 4460 goto done;
4461 }
4462
53b41837
YN		 4463 if (is_edp(intel_dp) &&
4464 property == connector->dev->mode_config.scaling_mode_property) {
4465 if (val == DRM_MODE_SCALE_NONE) {
4466 DRM_DEBUG_KMS("no scaling not supported\n");
4467 return -EINVAL;
4468 }
4469
4470 if (intel_connector->panel.fitting_mode == val) {
4471 /* the eDP scaling property is not changed */
4472 return 0;
4473 }
4474 intel_connector->panel.fitting_mode = val;
4475
4476 goto done;
4477 }
4478
f684960e
CW		 4479 return -EINVAL;
4480
4481done:
c0c36b94
CW		 4482 if (intel_encoder->base.crtc)
4483 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4484
4485 return 0;
4486}
4487
a4fc5ed6 4488static void
73845adf 4489intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4490{
1d508706 4491 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4492
10e972d3 4493 kfree(intel_connector->detect_edid);
beb60608 4494
9cd300e0
JN		 4495 if (!IS_ERR_OR_NULL(intel_connector->edid))
4496 kfree(intel_connector->edid);
4497
acd8db10
PZ		 4498 /* Can't call is_edp() since the encoder may have been destroyed
4499 * already. */
4500 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4501 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4502
a4fc5ed6 4503 drm_connector_cleanup(connector);
55f78c43 4504 kfree(connector);
a4fc5ed6
KP		 4505}
4506
00c09d70 4507void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4508{
da63a9f2
PZ		 4509 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4510 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927 4511
4f71d0cb 4512 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4513 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4514 drm_encoder_cleanup(encoder);
bd943159
KP		 4515 if (is_edp(intel_dp)) {
4516 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 4517 /*
4518 * vdd might still be enabled do to the delayed vdd off.
4519 * Make sure vdd is actually turned off here.
4520 */
773538e8 4521 pps_lock(intel_dp);
4be73780 4522 edp_panel_vdd_off_sync(intel_dp);
773538e8
VS		 4523 pps_unlock(intel_dp);
4524
01527b31
CT		 4525 if (intel_dp->edp_notifier.notifier_call) {
4526 unregister_reboot_notifier(&intel_dp->edp_notifier);
4527 intel_dp->edp_notifier.notifier_call = NULL;
4528 }
bd943159 4529 }
da63a9f2 4530 kfree(intel_dig_port);
24d05927
DV		 4531}
4532
07f9cd0b
ID		 4533static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4534{
4535 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4536
4537 if (!is_edp(intel_dp))
4538 return;
4539
951468f3
VS		 4540 /*
4541 * vdd might still be enabled do to the delayed vdd off.
4542 * Make sure vdd is actually turned off here.
4543 */
773538e8 4544 pps_lock(intel_dp);
07f9cd0b 4545 edp_panel_vdd_off_sync(intel_dp);
773538e8 4546 pps_unlock(intel_dp);
07f9cd0b
ID		 4547}
4548
6d93c0c4
ID		 4549static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4550{
4551 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4552}
4553
a4fc5ed6 4554static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4555 .dpms = intel_connector_dpms,
a4fc5ed6 4556 .detect = intel_dp_detect,
beb60608 4557 .force = intel_dp_force,
a4fc5ed6 4558 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4559 .set_property = intel_dp_set_property,
73845adf 4560 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4561};
4562
4563static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4564 .get_modes = intel_dp_get_modes,
4565 .mode_valid = intel_dp_mode_valid,
df0e9248 4566 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4567};
4568
a4fc5ed6 4569static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4570 .reset = intel_dp_encoder_reset,
24d05927 4571 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4572};
4573
0e32b39c 4574void
21d40d37 4575intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4576{
0e32b39c 4577 return;
c8110e52 4578}
6207937d 4579
13cf5504
DA		 4580bool
4581intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4582{
4583 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4584 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4585 struct drm_device *dev = intel_dig_port->base.base.dev;
4586 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4587 enum intel_display_power_domain power_domain;
4588 bool ret = true;
4589
0e32b39c
DA		 4590 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4591 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4592
26fbb774
VS		 4593 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4594 port_name(intel_dig_port->port),
0e32b39c 4595 long_hpd ? "long" : "short");
13cf5504 4596
1c767b33
ID		 4597 power_domain = intel_display_port_power_domain(intel_encoder);
4598 intel_display_power_get(dev_priv, power_domain);
4599
0e32b39c 4600 if (long_hpd) {
2a592bec
DA		 4601
4602 if (HAS_PCH_SPLIT(dev)) {
4603 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4604 goto mst_fail;
4605 } else {
4606 if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
4607 goto mst_fail;
4608 }
0e32b39c
DA		 4609
4610 if (!intel_dp_get_dpcd(intel_dp)) {
4611 goto mst_fail;
4612 }
4613
4614 intel_dp_probe_oui(intel_dp);
4615
4616 if (!intel_dp_probe_mst(intel_dp))
4617 goto mst_fail;
4618
4619 } else {
4620 if (intel_dp->is_mst) {
1c767b33 4621 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4622 goto mst_fail;
4623 }
4624
4625 if (!intel_dp->is_mst) {
4626 /*
4627 * we'll check the link status via the normal hot plug path later -
4628 * but for short hpds we should check it now
4629 */
5b215bcf 4630 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4631 intel_dp_check_link_status(intel_dp);
5b215bcf 4632 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4633 }
4634 }
1c767b33
ID		 4635 ret = false;
4636 goto put_power;
0e32b39c
DA		 4637mst_fail:
4638 /* if we were in MST mode, and device is not there get out of MST mode */
4639 if (intel_dp->is_mst) {
4640 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4641 intel_dp->is_mst = false;
4642 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4643 }
1c767b33
ID		 4644put_power:
4645 intel_display_power_put(dev_priv, power_domain);
4646
4647 return ret;
13cf5504
DA		 4648}
4649
e3421a18
ZW		 4650/* Return which DP Port should be selected for Transcoder DP control */
4651int
0206e353 4652intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4653{
4654 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4655 struct intel_encoder *intel_encoder;
4656 struct intel_dp *intel_dp;
e3421a18 4657
fa90ecef
PZ		 4658 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4659 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4660
fa90ecef
PZ		 4661 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4662 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4663 return intel_dp->output_reg;
e3421a18 4664 }
ea5b213a 4665
e3421a18
ZW		 4666 return -1;
4667}
4668
36e83a18 4669/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4670bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4671{
4672 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4673 union child_device_config *p_child;
36e83a18 4674 int i;
5d8a7752
VS		 4675 static const short port_mapping[] = {
4676 [PORT_B] = PORT_IDPB,
4677 [PORT_C] = PORT_IDPC,
4678 [PORT_D] = PORT_IDPD,
4679 };
36e83a18 4680
3b32a35b
VS		 4681 if (port == PORT_A)
4682 return true;
4683
41aa3448 4684 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4685 return false;
4686
41aa3448
RV		 4687 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4688 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4689
5d8a7752 4690 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4691 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4692 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4693 return true;
4694 }
4695 return false;
4696}
4697
0e32b39c 4698void
f684960e
CW		 4699intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4700{
53b41837
YN		 4701 struct intel_connector *intel_connector = to_intel_connector(connector);
4702
3f43c48d 4703 intel_attach_force_audio_property(connector);
e953fd7b 4704 intel_attach_broadcast_rgb_property(connector);
55bc60db 4705 intel_dp->color_range_auto = true;
53b41837
YN		 4706
4707 if (is_edp(intel_dp)) {
4708 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4709 drm_object_attach_property(
4710 &connector->base,
53b41837 4711 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4712 DRM_MODE_SCALE_ASPECT);
4713 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4714 }
f684960e
CW		 4715}
4716
dada1a9f
ID		 4717static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4718{
4719 intel_dp->last_power_cycle = jiffies;
4720 intel_dp->last_power_on = jiffies;
4721 intel_dp->last_backlight_off = jiffies;
4722}
4723
67a54566
DV		 4724static void
4725intel_dp_init_panel_power_sequencer(struct drm_device *dev,
36b5f425 4726 struct intel_dp *intel_dp)
67a54566
DV		 4727{
4728 struct drm_i915_private *dev_priv = dev->dev_private;
36b5f425
VS		 4729 struct edp_power_seq cur, vbt, spec,
4730 *final = &intel_dp->pps_delays;
67a54566 4731 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4732 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4733
e39b999a
VS		 4734 lockdep_assert_held(&dev_priv->pps_mutex);
4735
81ddbc69
VS		 4736 /* already initialized? */
4737 if (final->t11_t12 != 0)
4738 return;
4739
453c5420 4740 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4741 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4742 pp_on_reg = PCH_PP_ON_DELAYS;
4743 pp_off_reg = PCH_PP_OFF_DELAYS;
4744 pp_div_reg = PCH_PP_DIVISOR;
4745 } else {
bf13e81b
JN		 4746 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4747
4748 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4749 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4750 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4751 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4752 }
67a54566
DV		 4753
4754 /* Workaround: Need to write PP_CONTROL with the unlock key as
4755 * the very first thing. */
453c5420 4756 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4757 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4758
453c5420
JB		 4759 pp_on = I915_READ(pp_on_reg);
4760 pp_off = I915_READ(pp_off_reg);
4761 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4762
4763 /* Pull timing values out of registers */
4764 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4765 PANEL_POWER_UP_DELAY_SHIFT;
4766
4767 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4768 PANEL_LIGHT_ON_DELAY_SHIFT;
4769
4770 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4771 PANEL_LIGHT_OFF_DELAY_SHIFT;
4772
4773 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4774 PANEL_POWER_DOWN_DELAY_SHIFT;
4775
4776 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4777 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4778
4779 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4780 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4781
41aa3448 4782 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4783
4784 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4785 * our hw here, which are all in 100usec. */
4786 spec.t1_t3 = 210 * 10;
4787 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4788 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4789 spec.t10 = 500 * 10;
4790 /* This one is special and actually in units of 100ms, but zero
4791 * based in the hw (so we need to add 100 ms). But the sw vbt
4792 * table multiplies it with 1000 to make it in units of 100usec,
4793 * too. */
4794 spec.t11_t12 = (510 + 100) * 10;
4795
4796 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4797 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4798
4799 /* Use the max of the register settings and vbt. If both are
4800 * unset, fall back to the spec limits. */
36b5f425 4801#define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \
67a54566
DV		 4802 spec.field : \
4803 max(cur.field, vbt.field))
4804 assign_final(t1_t3);
4805 assign_final(t8);
4806 assign_final(t9);
4807 assign_final(t10);
4808 assign_final(t11_t12);
4809#undef assign_final
4810
36b5f425 4811#define get_delay(field) (DIV_ROUND_UP(final->field, 10))
67a54566
DV		 4812 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4813 intel_dp->backlight_on_delay = get_delay(t8);
4814 intel_dp->backlight_off_delay = get_delay(t9);
4815 intel_dp->panel_power_down_delay = get_delay(t10);
4816 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4817#undef get_delay
4818
f30d26e4
JN		 4819 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4820 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4821 intel_dp->panel_power_cycle_delay);
4822
4823 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4824 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
f30d26e4
JN		 4825}
4826
4827static void
4828intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
36b5f425 4829 struct intel_dp *intel_dp)
f30d26e4
JN		 4830{
4831 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4832 u32 pp_on, pp_off, pp_div, port_sel = 0;
4833 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4834 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4835 enum port port = dp_to_dig_port(intel_dp)->port;
36b5f425 4836 const struct edp_power_seq *seq = &intel_dp->pps_delays;
453c5420 4837
e39b999a 4838 lockdep_assert_held(&dev_priv->pps_mutex);
453c5420
JB		 4839
4840 if (HAS_PCH_SPLIT(dev)) {
4841 pp_on_reg = PCH_PP_ON_DELAYS;
4842 pp_off_reg = PCH_PP_OFF_DELAYS;
4843 pp_div_reg = PCH_PP_DIVISOR;
4844 } else {
bf13e81b
JN		 4845 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4846
4847 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4848 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4849 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4850 }
4851
b2f19d1a
PZ		 4852 /*
4853 * And finally store the new values in the power sequencer. The
4854 * backlight delays are set to 1 because we do manual waits on them. For
4855 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4856 * we'll end up waiting for the backlight off delay twice: once when we
4857 * do the manual sleep, and once when we disable the panel and wait for
4858 * the PP_STATUS bit to become zero.
4859 */
f30d26e4 4860 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4861 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4862 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4863 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4864 /* Compute the divisor for the pp clock, simply match the Bspec
4865 * formula. */
453c5420 4866 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4867 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4868 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4869
4870 /* Haswell doesn't have any port selection bits for the panel
4871 * power sequencer any more. */
bc7d38a4 4872 if (IS_VALLEYVIEW(dev)) {
ad933b56 4873 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4874 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4875 if (port == PORT_A)
a24c144c 4876 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4877 else
a24c144c 4878 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4879 }
4880
453c5420
JB		 4881 pp_on |= port_sel;
4882
4883 I915_WRITE(pp_on_reg, pp_on);
4884 I915_WRITE(pp_off_reg, pp_off);
4885 I915_WRITE(pp_div_reg, pp_div);
67a54566 4886
67a54566 4887 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4888 I915_READ(pp_on_reg),
4889 I915_READ(pp_off_reg),
4890 I915_READ(pp_div_reg));
f684960e
CW		 4891}
4892
439d7ac0
PB		 4893void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4894{
4895 struct drm_i915_private *dev_priv = dev->dev_private;
4896 struct intel_encoder *encoder;
4897 struct intel_dp *intel_dp = NULL;
4898 struct intel_crtc_config *config = NULL;
4899 struct intel_crtc *intel_crtc = NULL;
4900 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4901 u32 reg, val;
4902 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4903
4904 if (refresh_rate <= 0) {
4905 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4906 return;
4907 }
4908
4909 if (intel_connector == NULL) {
4910 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4911 return;
4912 }
4913
1fcc9d1c
DV		 4914 /*
4915 * FIXME: This needs proper synchronization with psr state. But really
4916 * hard to tell without seeing the user of this function of this code.
4917 * Check locking and ordering once that lands.
4918 */
439d7ac0
PB		 4919 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4920 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4921 return;
4922 }
4923
4924 encoder = intel_attached_encoder(&intel_connector->base);
4925 intel_dp = enc_to_intel_dp(&encoder->base);
4926 intel_crtc = encoder->new_crtc;
4927
4928 if (!intel_crtc) {
4929 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4930 return;
4931 }
4932
4933 config = &intel_crtc->config;
4934
4935 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4936 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4937 return;
4938 }
4939
4940 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4941 index = DRRS_LOW_RR;
4942
4943 if (index == intel_dp->drrs_state.refresh_rate_type) {
4944 DRM_DEBUG_KMS(
4945 "DRRS requested for previously set RR...ignoring\n");
4946 return;
4947 }
4948
4949 if (!intel_crtc->active) {
4950 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4951 return;
4952 }
4953
4954 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4955 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4956 val = I915_READ(reg);
4957 if (index > DRRS_HIGH_RR) {
4958 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4959 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4960 } else {
4961 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4962 }
4963 I915_WRITE(reg, val);
4964 }
4965
4966 /*
4967 * mutex taken to ensure that there is no race between differnt
4968 * drrs calls trying to update refresh rate. This scenario may occur
4969 * in future when idleness detection based DRRS in kernel and
4970 * possible calls from user space to set differnt RR are made.
4971 */
4972
4973 mutex_lock(&intel_dp->drrs_state.mutex);
4974
4975 intel_dp->drrs_state.refresh_rate_type = index;
4976
4977 mutex_unlock(&intel_dp->drrs_state.mutex);
4978
4979 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4980}
4981
4f9db5b5
PB		 4982static struct drm_display_mode *
4983intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4984 struct intel_connector *intel_connector,
4985 struct drm_display_mode *fixed_mode)
4986{
4987 struct drm_connector *connector = &intel_connector->base;
4988 struct intel_dp *intel_dp = &intel_dig_port->dp;
4989 struct drm_device *dev = intel_dig_port->base.base.dev;
4990 struct drm_i915_private *dev_priv = dev->dev_private;
4991 struct drm_display_mode *downclock_mode = NULL;
4992
4993 if (INTEL_INFO(dev)->gen <= 6) {
4994 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4995 return NULL;
4996 }
4997
4998 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4999 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 5000 return NULL;
5001 }
5002
5003 downclock_mode = intel_find_panel_downclock
5004 (dev, fixed_mode, connector);
5005
5006 if (!downclock_mode) {
4079b8d1 5007 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 5008 return NULL;
5009 }
5010
439d7ac0
PB		 5011 dev_priv->drrs.connector = intel_connector;
5012
5013 mutex_init(&intel_dp->drrs_state.mutex);
5014
4f9db5b5
PB		 5015 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
5016
5017 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 5018 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 5019 return downclock_mode;
5020}
5021
aba86890
ID		 5022void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
5023{
5024 struct drm_device *dev = intel_encoder->base.dev;
5025 struct drm_i915_private *dev_priv = dev->dev_private;
5026 struct intel_dp *intel_dp;
5027 enum intel_display_power_domain power_domain;
5028
5029 if (intel_encoder->type != INTEL_OUTPUT_EDP)
5030 return;
5031
5032 intel_dp = enc_to_intel_dp(&intel_encoder->base);
773538e8
VS		 5033
5034 pps_lock(intel_dp);
5035
aba86890 5036 if (!edp_have_panel_vdd(intel_dp))
e39b999a 5037 goto out;
aba86890
ID		 5038 /*
5039 * The VDD bit needs a power domain reference, so if the bit is
5040 * already enabled when we boot or resume, grab this reference and
5041 * schedule a vdd off, so we don't hold on to the reference
5042 * indefinitely.
5043 */
5044 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5045 power_domain = intel_display_port_power_domain(intel_encoder);
5046 intel_display_power_get(dev_priv, power_domain);
5047
5048 edp_panel_vdd_schedule_off(intel_dp);
e39b999a 5049 out:
773538e8 5050 pps_unlock(intel_dp);
aba86890
ID		 5051}
5052
ed92f0b2 5053static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425 5054 struct intel_connector *intel_connector)
ed92f0b2
PZ		 5055{
5056 struct drm_connector *connector = &intel_connector->base;
5057 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 5058 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5059 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 5060 struct drm_i915_private *dev_priv = dev->dev_private;
5061 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 5062 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 5063 bool has_dpcd;
5064 struct drm_display_mode *scan;
5065 struct edid *edid;
5066
4f9db5b5
PB		 5067 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
5068
ed92f0b2
PZ		 5069 if (!is_edp(intel_dp))
5070 return true;
5071
aba86890 5072 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 5073
ed92f0b2 5074 /* Cache DPCD and EDID for edp. */
ed92f0b2 5075 has_dpcd = intel_dp_get_dpcd(intel_dp);
ed92f0b2
PZ		 5076
5077 if (has_dpcd) {
5078 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5079 dev_priv->no_aux_handshake =
5080 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5081 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5082 } else {
5083 /* if this fails, presume the device is a ghost */
5084 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 5085 return false;
5086 }
5087
5088 /* We now know it's not a ghost, init power sequence regs. */
773538e8 5089 pps_lock(intel_dp);
36b5f425 5090 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
773538e8 5091 pps_unlock(intel_dp);
ed92f0b2 5092
060c8778 5093 mutex_lock(&dev->mode_config.mutex);
0b99836f 5094 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 5095 if (edid) {
5096 if (drm_add_edid_modes(connector, edid)) {
5097 drm_mode_connector_update_edid_property(connector,
5098 edid);
5099 drm_edid_to_eld(connector, edid);
5100 } else {
5101 kfree(edid);
5102 edid = ERR_PTR(-EINVAL);
5103 }
5104 } else {
5105 edid = ERR_PTR(-ENOENT);
5106 }
5107 intel_connector->edid = edid;
5108
5109 /* prefer fixed mode from EDID if available */
5110 list_for_each_entry(scan, &connector->probed_modes, head) {
5111 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5112 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 5113 downclock_mode = intel_dp_drrs_init(
5114 intel_dig_port,
5115 intel_connector, fixed_mode);
ed92f0b2
PZ		 5116 break;
5117 }
5118 }
5119
5120 /* fallback to VBT if available for eDP */
5121 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5122 fixed_mode = drm_mode_duplicate(dev,
5123 dev_priv->vbt.lfp_lvds_vbt_mode);
5124 if (fixed_mode)
5125 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5126 }
060c8778 5127 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 5128
01527b31
CT		 5129 if (IS_VALLEYVIEW(dev)) {
5130 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5131 register_reboot_notifier(&intel_dp->edp_notifier);
5132 }
5133
4f9db5b5 5134 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 5135 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 5136 intel_panel_setup_backlight(connector);
5137
5138 return true;
5139}
5140
16c25533 5141bool
f0fec3f2
PZ		 5142intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5143 struct intel_connector *intel_connector)
a4fc5ed6 5144{
f0fec3f2
PZ		 5145 struct drm_connector *connector = &intel_connector->base;
5146 struct intel_dp *intel_dp = &intel_dig_port->dp;
5147 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5148 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 5149 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 5150 enum port port = intel_dig_port->port;
0b99836f 5151 int type;
a4fc5ed6 5152
a4a5d2f8
VS		 5153 intel_dp->pps_pipe = INVALID_PIPE;
5154
ec5b01dd 5155 /* intel_dp vfuncs */
b6b5e383
DL		 5156 if (INTEL_INFO(dev)->gen >= 9)
5157 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5158 else if (IS_VALLEYVIEW(dev))
ec5b01dd
DL		 5159 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5160 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5161 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5162 else if (HAS_PCH_SPLIT(dev))
5163 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5164 else
5165 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5166
b9ca5fad
DL		 5167 if (INTEL_INFO(dev)->gen >= 9)
5168 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5169 else
5170 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
153b1100 5171
0767935e
DV		 5172 /* Preserve the current hw state. */
5173 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 5174 intel_dp->attached_connector = intel_connector;
3d3dc149 5175
3b32a35b 5176 if (intel_dp_is_edp(dev, port))
b329530c 5177 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 5178 else
5179 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 5180
f7d24902
ID		 5181 /*
5182 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5183 * for DP the encoder type can be set by the caller to
5184 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5185 */
5186 if (type == DRM_MODE_CONNECTOR_eDP)
5187 intel_encoder->type = INTEL_OUTPUT_EDP;
5188
c17ed5b5
VS		 5189 /* eDP only on port B and/or C on vlv/chv */
5190 if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
5191 port != PORT_B && port != PORT_C))
5192 return false;
5193
e7281eab
ID		 5194 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5195 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5196 port_name(port));
5197
b329530c 5198 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 5199 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5200
a4fc5ed6
KP		 5201 connector->interlace_allowed = true;
5202 connector->doublescan_allowed = 0;
5203
f0fec3f2 5204 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 5205 edp_panel_vdd_work);
a4fc5ed6 5206
df0e9248 5207 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 5208 drm_connector_register(connector);
a4fc5ed6 5209
affa9354 5210 if (HAS_DDI(dev))
bcbc889b
PZ		 5211 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5212 else
5213 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 5214 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 5215
0b99836f 5216 /* Set up the hotplug pin. */
ab9d7c30
PZ		 5217 switch (port) {
5218 case PORT_A:
1d843f9d 5219 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 5220 break;
5221 case PORT_B:
1d843f9d 5222 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 5223 break;
5224 case PORT_C:
1d843f9d 5225 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 5226 break;
5227 case PORT_D:
1d843f9d 5228 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 5229 break;
5230 default:
ad1c0b19 5231 BUG();
5eb08b69
ZW		 5232 }
5233
dada1a9f 5234 if (is_edp(intel_dp)) {
773538e8 5235 pps_lock(intel_dp);
a4a5d2f8
VS		 5236 if (IS_VALLEYVIEW(dev)) {
5237 vlv_initial_power_sequencer_setup(intel_dp);
5238 } else {
5239 intel_dp_init_panel_power_timestamps(intel_dp);
36b5f425 5240 intel_dp_init_panel_power_sequencer(dev, intel_dp);
a4a5d2f8 5241 }
773538e8 5242 pps_unlock(intel_dp);
dada1a9f 5243 }
0095e6dc 5244
9d1a1031 5245 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 5246
0e32b39c
DA		 5247 /* init MST on ports that can support it */
5248 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5249 if (port == PORT_B || port == PORT_C || port == PORT_D) {
a4a5d2f8
VS		 5250 intel_dp_mst_encoder_init(intel_dig_port,
5251 intel_connector->base.base.id);
0e32b39c
DA		 5252 }
5253 }
5254
36b5f425 5255 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
4f71d0cb 5256 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 5257 if (is_edp(intel_dp)) {
5258 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
951468f3
VS		 5259 /*
5260 * vdd might still be enabled do to the delayed vdd off.
5261 * Make sure vdd is actually turned off here.
5262 */
773538e8 5263 pps_lock(intel_dp);
4be73780 5264 edp_panel_vdd_off_sync(intel_dp);
773538e8 5265 pps_unlock(intel_dp);
15b1d171 5266 }
34ea3d38 5267 drm_connector_unregister(connector);
b2f246a8 5268 drm_connector_cleanup(connector);
16c25533 5269 return false;
b2f246a8 5270 }
32f9d658 5271
f684960e
CW		 5272 intel_dp_add_properties(intel_dp, connector);
5273
a4fc5ed6
KP		 5274 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5275 * 0xd. Failure to do so will result in spurious interrupts being
5276 * generated on the port when a cable is not attached.
5277 */
5278 if (IS_G4X(dev) && !IS_GM45(dev)) {
5279 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5280 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5281 }
16c25533
PZ		 5282
5283 return true;
a4fc5ed6 5284}
f0fec3f2
PZ		 5285
5286void
5287intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
5288{
13cf5504 5289 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 5290 struct intel_digital_port *intel_dig_port;
5291 struct intel_encoder *intel_encoder;
5292 struct drm_encoder *encoder;
5293 struct intel_connector *intel_connector;
5294
b14c5679 5295 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 5296 if (!intel_dig_port)
5297 return;
5298
b14c5679 5299 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 5300 if (!intel_connector) {
5301 kfree(intel_dig_port);
5302 return;
5303 }
5304
5305 intel_encoder = &intel_dig_port->base;
5306 encoder = &intel_encoder->base;
5307
5308 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
5309 DRM_MODE_ENCODER_TMDS);
5310
5bfe2ac0 5311 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 5312 intel_encoder->disable = intel_disable_dp;
00c09d70 5313 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 5314 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 5315 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 5316 if (IS_CHERRYVIEW(dev)) {
9197c88b 5317 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 5318 intel_encoder->pre_enable = chv_pre_enable_dp;
5319 intel_encoder->enable = vlv_enable_dp;
580d3811 5320 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 5321 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 5322 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 5323 intel_encoder->pre_enable = vlv_pre_enable_dp;
5324 intel_encoder->enable = vlv_enable_dp;
49277c31 5325 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 5326 } else {
ecff4f3b
JN		 5327 intel_encoder->pre_enable = g4x_pre_enable_dp;
5328 intel_encoder->enable = g4x_enable_dp;
08aff3fe
VS		 5329 if (INTEL_INFO(dev)->gen >= 5)
5330 intel_encoder->post_disable = ilk_post_disable_dp;
ab1f90f9 5331 }
f0fec3f2 5332
174edf1f 5333 intel_dig_port->port = port;
f0fec3f2
PZ		 5334 intel_dig_port->dp.output_reg = output_reg;
5335
00c09d70 5336 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 5337 if (IS_CHERRYVIEW(dev)) {
5338 if (port == PORT_D)
5339 intel_encoder->crtc_mask = 1 << 2;
5340 else
5341 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
5342 } else {
5343 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
5344 }
bc079e8b 5345 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 5346 intel_encoder->hot_plug = intel_dp_hot_plug;
5347
13cf5504
DA		 5348 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5349 dev_priv->hpd_irq_port[port] = intel_dig_port;
5350
15b1d171
PZ		 5351 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
5352 drm_encoder_cleanup(encoder);
5353 kfree(intel_dig_port);
b2f246a8 5354 kfree(intel_connector);
15b1d171 5355 }
f0fec3f2 5356}
0e32b39c
DA		 5357
5358void intel_dp_mst_suspend(struct drm_device *dev)
5359{
5360 struct drm_i915_private *dev_priv = dev->dev_private;
5361 int i;
5362
5363 /* disable MST */
5364 for (i = 0; i < I915_MAX_PORTS; i++) {
5365 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5366 if (!intel_dig_port)
5367 continue;
5368
5369 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5370 if (!intel_dig_port->dp.can_mst)
5371 continue;
5372 if (intel_dig_port->dp.is_mst)
5373 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
5374 }
5375 }
5376}
5377
5378void intel_dp_mst_resume(struct drm_device *dev)
5379{
5380 struct drm_i915_private *dev_priv = dev->dev_private;
5381 int i;
5382
5383 for (i = 0; i < I915_MAX_PORTS; i++) {
5384 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
5385 if (!intel_dig_port)
5386 continue;
5387 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
5388 int ret;
5389
5390 if (!intel_dig_port->dp.can_mst)
5391 continue;
5392
5393 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
5394 if (ret != 0) {
5395 intel_dp_check_mst_status(&intel_dig_port->dp);
5396 }
5397 }
5398 }
5399}
ubuntu-bionic-kernel mirror