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drm/i915: get port power domain in connector detect handlers
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
9dd4ffdf
CML		 41struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
65ce4bf5
CML		 60static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
58f6e632 62 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 63 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
cfcb0fc9
JB		 67/**
68 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
69 * @intel_dp: DP struct
70 *
71 * If a CPU or PCH DP output is attached to an eDP panel, this function
72 * will return true, and false otherwise.
73 */
74static bool is_edp(struct intel_dp *intel_dp)
75{
da63a9f2
PZ		 76 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
77
78 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 79}
80
68b4d824 81static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 82{
68b4d824
ID		 83 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
84
85 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 86}
87
df0e9248
CW		 88static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
89{
fa90ecef 90 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 91}
92
ea5b213a 93static void intel_dp_link_down(struct intel_dp *intel_dp);
4be73780
DV		 94static void edp_panel_vdd_on(struct intel_dp *intel_dp);
95static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 96
a4fc5ed6 97static int
ea5b213a 98intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 99{
7183dc29 100 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 101 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 102
103 switch (max_link_bw) {
104 case DP_LINK_BW_1_62:
105 case DP_LINK_BW_2_7:
106 break;
d4eead50 107 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
06ea66b6
TP		 108 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
109 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
110 max_link_bw = DP_LINK_BW_5_4;
111 else
112 max_link_bw = DP_LINK_BW_2_7;
d4eead50 113 break;
a4fc5ed6 114 default:
d4eead50
ID		 115 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
116 max_link_bw);
a4fc5ed6
KP		 117 max_link_bw = DP_LINK_BW_1_62;
118 break;
119 }
120 return max_link_bw;
121}
122
cd9dde44
AJ		 123/*
124 * The units on the numbers in the next two are... bizarre. Examples will
125 * make it clearer; this one parallels an example in the eDP spec.
126 *
127 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
128 *
129 * 270000 * 1 * 8 / 10 == 216000
130 *
131 * The actual data capacity of that configuration is 2.16Gbit/s, so the
132 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
133 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
134 * 119000. At 18bpp that's 2142000 kilobits per second.
135 *
136 * Thus the strange-looking division by 10 in intel_dp_link_required, to
137 * get the result in decakilobits instead of kilobits.
138 */
139
a4fc5ed6 140static int
c898261c 141intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 142{
cd9dde44 143 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 144}
145
fe27d53e
DA		 146static int
147intel_dp_max_data_rate(int max_link_clock, int max_lanes)
148{
149 return (max_link_clock * max_lanes * 8) / 10;
150}
151
c19de8eb 152static enum drm_mode_status
a4fc5ed6
KP		 153intel_dp_mode_valid(struct drm_connector *connector,
154 struct drm_display_mode *mode)
155{
df0e9248 156 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 157 struct intel_connector *intel_connector = to_intel_connector(connector);
158 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 159 int target_clock = mode->clock;
160 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 161
dd06f90e
JN		 162 if (is_edp(intel_dp) && fixed_mode) {
163 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 164 return MODE_PANEL;
165
dd06f90e 166 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 167 return MODE_PANEL;
03afc4a2
DV		 168
169 target_clock = fixed_mode->clock;
7de56f43
ZY		 170 }
171
36008365
DV		 172 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
173 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
174
175 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
176 mode_rate = intel_dp_link_required(target_clock, 18);
177
178 if (mode_rate > max_rate)
c4867936 179 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 180
181 if (mode->clock < 10000)
182 return MODE_CLOCK_LOW;
183
0af78a2b
DV		 184 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
185 return MODE_H_ILLEGAL;
186
a4fc5ed6
KP		 187 return MODE_OK;
188}
189
190static uint32_t
191pack_aux(uint8_t *src, int src_bytes)
192{
193 int i;
194 uint32_t v = 0;
195
196 if (src_bytes > 4)
197 src_bytes = 4;
198 for (i = 0; i < src_bytes; i++)
199 v |= ((uint32_t) src[i]) << ((3-i) * 8);
200 return v;
201}
202
203static void
204unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
205{
206 int i;
207 if (dst_bytes > 4)
208 dst_bytes = 4;
209 for (i = 0; i < dst_bytes; i++)
210 dst[i] = src >> ((3-i) * 8);
211}
212
fb0f8fbf
KP		 213/* hrawclock is 1/4 the FSB frequency */
214static int
215intel_hrawclk(struct drm_device *dev)
216{
217 struct drm_i915_private *dev_priv = dev->dev_private;
218 uint32_t clkcfg;
219
9473c8f4
VP		 220 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
221 if (IS_VALLEYVIEW(dev))
222 return 200;
223
fb0f8fbf
KP		 224 clkcfg = I915_READ(CLKCFG);
225 switch (clkcfg & CLKCFG_FSB_MASK) {
226 case CLKCFG_FSB_400:
227 return 100;
228 case CLKCFG_FSB_533:
229 return 133;
230 case CLKCFG_FSB_667:
231 return 166;
232 case CLKCFG_FSB_800:
233 return 200;
234 case CLKCFG_FSB_1067:
235 return 266;
236 case CLKCFG_FSB_1333:
237 return 333;
238 /* these two are just a guess; one of them might be right */
239 case CLKCFG_FSB_1600:
240 case CLKCFG_FSB_1600_ALT:
241 return 400;
242 default:
243 return 133;
244 }
245}
246
bf13e81b
JN		 247static void
248intel_dp_init_panel_power_sequencer(struct drm_device *dev,
249 struct intel_dp *intel_dp,
250 struct edp_power_seq *out);
251static void
252intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
253 struct intel_dp *intel_dp,
254 struct edp_power_seq *out);
255
256static enum pipe
257vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
258{
259 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
260 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
261 struct drm_device *dev = intel_dig_port->base.base.dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 enum port port = intel_dig_port->port;
264 enum pipe pipe;
265
266 /* modeset should have pipe */
267 if (crtc)
268 return to_intel_crtc(crtc)->pipe;
269
270 /* init time, try to find a pipe with this port selected */
271 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
272 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
273 PANEL_PORT_SELECT_MASK;
274 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
275 return pipe;
276 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
277 return pipe;
278 }
279
280 /* shrug */
281 return PIPE_A;
282}
283
284static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
285{
286 struct drm_device *dev = intel_dp_to_dev(intel_dp);
287
288 if (HAS_PCH_SPLIT(dev))
289 return PCH_PP_CONTROL;
290 else
291 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
292}
293
294static u32 _pp_stat_reg(struct intel_dp *intel_dp)
295{
296 struct drm_device *dev = intel_dp_to_dev(intel_dp);
297
298 if (HAS_PCH_SPLIT(dev))
299 return PCH_PP_STATUS;
300 else
301 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
302}
303
4be73780 304static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 305{
30add22d 306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 307 struct drm_i915_private *dev_priv = dev->dev_private;
308
bf13e81b 309 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 310}
311
4be73780 312static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 313{
30add22d 314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 315 struct drm_i915_private *dev_priv = dev->dev_private;
316
bf13e81b 317 return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 318}
319
9b984dae
KP		 320static void
321intel_dp_check_edp(struct intel_dp *intel_dp)
322{
30add22d 323 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 324 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 325
9b984dae
KP		 326 if (!is_edp(intel_dp))
327 return;
453c5420 328
4be73780 329 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 330 WARN(1, "eDP powered off while attempting aux channel communication.\n");
331 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 332 I915_READ(_pp_stat_reg(intel_dp)),
333 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 334 }
335}
336
9ee32fea
DV		 337static uint32_t
338intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
339{
340 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
341 struct drm_device *dev = intel_dig_port->base.base.dev;
342 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 343 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 344 uint32_t status;
345 bool done;
346
ef04f00d 347#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 348 if (has_aux_irq)
b18ac466 349 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 350 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 351 else
352 done = wait_for_atomic(C, 10) == 0;
353 if (!done)
354 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
355 has_aux_irq);
356#undef C
357
358 return status;
359}
360
ec5b01dd 361static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 362{
174edf1f
PZ		 363 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
364 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 365
ec5b01dd
DL		 366 /*
367 * The clock divider is based off the hrawclk, and would like to run at
368 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 369 */
ec5b01dd
DL		 370 return index ? 0 : intel_hrawclk(dev) / 2;
371}
372
373static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
374{
375 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
376 struct drm_device *dev = intel_dig_port->base.base.dev;
377
378 if (index)
379 return 0;
380
381 if (intel_dig_port->port == PORT_A) {
382 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 383 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 384 else
b84a1cf8 385 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 386 } else {
387 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
388 }
389}
390
391static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
392{
393 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
394 struct drm_device *dev = intel_dig_port->base.base.dev;
395 struct drm_i915_private *dev_priv = dev->dev_private;
396
397 if (intel_dig_port->port == PORT_A) {
398 if (index)
399 return 0;
400 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 401 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
402 /* Workaround for non-ULT HSW */
bc86625a
CW		 403 switch (index) {
404 case 0: return 63;
405 case 1: return 72;
406 default: return 0;
407 }
ec5b01dd 408 } else {
bc86625a 409 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 410 }
b84a1cf8
RV		 411}
412
ec5b01dd
DL		 413static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
414{
415 return index ? 0 : 100;
416}
417
5ed12a19
DL		 418static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
419 bool has_aux_irq,
420 int send_bytes,
421 uint32_t aux_clock_divider)
422{
423 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
424 struct drm_device *dev = intel_dig_port->base.base.dev;
425 uint32_t precharge, timeout;
426
427 if (IS_GEN6(dev))
428 precharge = 3;
429 else
430 precharge = 5;
431
432 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
433 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
434 else
435 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
436
437 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 438 DP_AUX_CH_CTL_DONE |
5ed12a19 439 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 440 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 441 timeout |
788d4433 442 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 443 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
444 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 445 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 446}
447
b84a1cf8
RV		 448static int
449intel_dp_aux_ch(struct intel_dp *intel_dp,
450 uint8_t *send, int send_bytes,
451 uint8_t *recv, int recv_size)
452{
453 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
454 struct drm_device *dev = intel_dig_port->base.base.dev;
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
457 uint32_t ch_data = ch_ctl + 4;
bc86625a 458 uint32_t aux_clock_divider;
b84a1cf8
RV		 459 int i, ret, recv_bytes;
460 uint32_t status;
5ed12a19 461 int try, clock = 0;
4aeebd74 462 bool has_aux_irq = true;
b84a1cf8
RV		 463
464 /* dp aux is extremely sensitive to irq latency, hence request the
465 * lowest possible wakeup latency and so prevent the cpu from going into
466 * deep sleep states.
467 */
468 pm_qos_update_request(&dev_priv->pm_qos, 0);
469
470 intel_dp_check_edp(intel_dp);
5eb08b69 471
c67a470b
PZ		 472 intel_aux_display_runtime_get(dev_priv);
473
11bee43e
JB		 474 /* Try to wait for any previous AUX channel activity */
475 for (try = 0; try < 3; try++) {
ef04f00d 476 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 477 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
478 break;
479 msleep(1);
480 }
481
482 if (try == 3) {
483 WARN(1, "dp_aux_ch not started status 0x%08x\n",
484 I915_READ(ch_ctl));
9ee32fea
DV		 485 ret = -EBUSY;
486 goto out;
4f7f7b7e
CW		 487 }
488
46a5ae9f
PZ		 489 /* Only 5 data registers! */
490 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
491 ret = -E2BIG;
492 goto out;
493 }
494
ec5b01dd 495 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 496 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
497 has_aux_irq,
498 send_bytes,
499 aux_clock_divider);
5ed12a19 500
bc86625a
CW		 501 /* Must try at least 3 times according to DP spec */
502 for (try = 0; try < 5; try++) {
503 /* Load the send data into the aux channel data registers */
504 for (i = 0; i < send_bytes; i += 4)
505 I915_WRITE(ch_data + i,
506 pack_aux(send + i, send_bytes - i));
507
508 /* Send the command and wait for it to complete */
5ed12a19 509 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 510
511 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
512
513 /* Clear done status and any errors */
514 I915_WRITE(ch_ctl,
515 status |
516 DP_AUX_CH_CTL_DONE |
517 DP_AUX_CH_CTL_TIME_OUT_ERROR |
518 DP_AUX_CH_CTL_RECEIVE_ERROR);
519
520 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
521 DP_AUX_CH_CTL_RECEIVE_ERROR))
522 continue;
523 if (status & DP_AUX_CH_CTL_DONE)
524 break;
525 }
4f7f7b7e 526 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 527 break;
528 }
529
a4fc5ed6 530 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 531 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 532 ret = -EBUSY;
533 goto out;
a4fc5ed6
KP		 534 }
535
536 /* Check for timeout or receive error.
537 * Timeouts occur when the sink is not connected
538 */
a5b3da54 539 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 540 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 541 ret = -EIO;
542 goto out;
a5b3da54 543 }
1ae8c0a5
KP		 544
545 /* Timeouts occur when the device isn't connected, so they're
546 * "normal" -- don't fill the kernel log with these */
a5b3da54 547 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 548 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 549 ret = -ETIMEDOUT;
550 goto out;
a4fc5ed6
KP		 551 }
552
553 /* Unload any bytes sent back from the other side */
554 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
555 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 556 if (recv_bytes > recv_size)
557 recv_bytes = recv_size;
0206e353 558
4f7f7b7e
CW		 559 for (i = 0; i < recv_bytes; i += 4)
560 unpack_aux(I915_READ(ch_data + i),
561 recv + i, recv_bytes - i);
a4fc5ed6 562
9ee32fea
DV		 563 ret = recv_bytes;
564out:
565 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 566 intel_aux_display_runtime_put(dev_priv);
9ee32fea
DV		 567
568 return ret;
a4fc5ed6
KP		 569}
570
571/* Write data to the aux channel in native mode */
572static int
ea5b213a 573intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 574 uint16_t address, uint8_t *send, int send_bytes)
575{
576 int ret;
577 uint8_t msg[20];
578 int msg_bytes;
579 uint8_t ack;
580
46a5ae9f
PZ		 581 if (WARN_ON(send_bytes > 16))
582 return -E2BIG;
583
9b984dae 584 intel_dp_check_edp(intel_dp);
6b27f7f0 585 msg[0] = DP_AUX_NATIVE_WRITE << 4;
a4fc5ed6 586 msg[1] = address >> 8;
eebc863e 587 msg[2] = address & 0xff;
a4fc5ed6
KP		 588 msg[3] = send_bytes - 1;
589 memcpy(&msg[4], send, send_bytes);
590 msg_bytes = send_bytes + 4;
591 for (;;) {
ea5b213a 592 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 593 if (ret < 0)
594 return ret;
6b27f7f0
TR		 595 ack >>= 4;
596 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
a4fc5ed6 597 break;
6b27f7f0 598 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
a4fc5ed6
KP		 599 udelay(100);
600 else
a5b3da54 601 return -EIO;
a4fc5ed6
KP		 602 }
603 return send_bytes;
604}
605
606/* Write a single byte to the aux channel in native mode */
607static int
ea5b213a 608intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 609 uint16_t address, uint8_t byte)
610{
ea5b213a 611 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 612}
613
614/* read bytes from a native aux channel */
615static int
ea5b213a 616intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 617 uint16_t address, uint8_t *recv, int recv_bytes)
618{
619 uint8_t msg[4];
620 int msg_bytes;
621 uint8_t reply[20];
622 int reply_bytes;
623 uint8_t ack;
624 int ret;
625
46a5ae9f
PZ		 626 if (WARN_ON(recv_bytes > 19))
627 return -E2BIG;
628
9b984dae 629 intel_dp_check_edp(intel_dp);
6b27f7f0 630 msg[0] = DP_AUX_NATIVE_READ << 4;
a4fc5ed6
KP		 631 msg[1] = address >> 8;
632 msg[2] = address & 0xff;
633 msg[3] = recv_bytes - 1;
634
635 msg_bytes = 4;
636 reply_bytes = recv_bytes + 1;
637
638 for (;;) {
ea5b213a 639 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 640 reply, reply_bytes);
a5b3da54
KP		 641 if (ret == 0)
642 return -EPROTO;
643 if (ret < 0)
a4fc5ed6 644 return ret;
6b27f7f0
TR		 645 ack = reply[0] >> 4;
646 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
a4fc5ed6
KP		 647 memcpy(recv, reply + 1, ret - 1);
648 return ret - 1;
649 }
6b27f7f0 650 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
a4fc5ed6
KP		 651 udelay(100);
652 else
a5b3da54 653 return -EIO;
a4fc5ed6
KP		 654 }
655}
656
657static int
ab2c0672
DA		 658intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
659 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 660{
ab2c0672 661 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 662 struct intel_dp *intel_dp = container_of(adapter,
663 struct intel_dp,
664 adapter);
ab2c0672
DA		 665 uint16_t address = algo_data->address;
666 uint8_t msg[5];
667 uint8_t reply[2];
8316f337 668 unsigned retry;
ab2c0672
DA		 669 int msg_bytes;
670 int reply_bytes;
671 int ret;
672
4be73780 673 edp_panel_vdd_on(intel_dp);
9b984dae 674 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 675 /* Set up the command byte */
676 if (mode & MODE_I2C_READ)
6b27f7f0 677 msg[0] = DP_AUX_I2C_READ << 4;
ab2c0672 678 else
6b27f7f0 679 msg[0] = DP_AUX_I2C_WRITE << 4;
ab2c0672
DA		 680
681 if (!(mode & MODE_I2C_STOP))
6b27f7f0 682 msg[0] |= DP_AUX_I2C_MOT << 4;
a4fc5ed6 683
ab2c0672
DA		 684 msg[1] = address >> 8;
685 msg[2] = address;
686
687 switch (mode) {
688 case MODE_I2C_WRITE:
689 msg[3] = 0;
690 msg[4] = write_byte;
691 msg_bytes = 5;
692 reply_bytes = 1;
693 break;
694 case MODE_I2C_READ:
695 msg[3] = 0;
696 msg_bytes = 4;
697 reply_bytes = 2;
698 break;
699 default:
700 msg_bytes = 3;
701 reply_bytes = 1;
702 break;
703 }
704
58c67ce9
JN		 705 /*
706 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
707 * required to retry at least seven times upon receiving AUX_DEFER
708 * before giving up the AUX transaction.
709 */
710 for (retry = 0; retry < 7; retry++) {
8316f337
DF		 711 ret = intel_dp_aux_ch(intel_dp,
712 msg, msg_bytes,
713 reply, reply_bytes);
ab2c0672 714 if (ret < 0) {
3ff99164 715 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
8a5e6aeb 716 goto out;
ab2c0672 717 }
8316f337 718
6b27f7f0
TR		 719 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
720 case DP_AUX_NATIVE_REPLY_ACK:
8316f337
DF		 721 /* I2C-over-AUX Reply field is only valid
722 * when paired with AUX ACK.
723 */
724 break;
6b27f7f0 725 case DP_AUX_NATIVE_REPLY_NACK:
8316f337 726 DRM_DEBUG_KMS("aux_ch native nack\n");
8a5e6aeb
PZ		 727 ret = -EREMOTEIO;
728 goto out;
6b27f7f0 729 case DP_AUX_NATIVE_REPLY_DEFER:
8d16f258
JN		 730 /*
731 * For now, just give more slack to branch devices. We
732 * could check the DPCD for I2C bit rate capabilities,
733 * and if available, adjust the interval. We could also
734 * be more careful with DP-to-Legacy adapters where a
735 * long legacy cable may force very low I2C bit rates.
736 */
737 if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
738 DP_DWN_STRM_PORT_PRESENT)
739 usleep_range(500, 600);
740 else
741 usleep_range(300, 400);
8316f337
DF		 742 continue;
743 default:
744 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
745 reply[0]);
8a5e6aeb
PZ		 746 ret = -EREMOTEIO;
747 goto out;
8316f337
DF		 748 }
749
6b27f7f0
TR		 750 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
751 case DP_AUX_I2C_REPLY_ACK:
ab2c0672
DA		 752 if (mode == MODE_I2C_READ) {
753 *read_byte = reply[1];
754 }
8a5e6aeb
PZ		 755 ret = reply_bytes - 1;
756 goto out;
6b27f7f0 757 case DP_AUX_I2C_REPLY_NACK:
8316f337 758 DRM_DEBUG_KMS("aux_i2c nack\n");
8a5e6aeb
PZ		 759 ret = -EREMOTEIO;
760 goto out;
6b27f7f0 761 case DP_AUX_I2C_REPLY_DEFER:
8316f337 762 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 763 udelay(100);
764 break;
765 default:
8316f337 766 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
8a5e6aeb
PZ		 767 ret = -EREMOTEIO;
768 goto out;
ab2c0672
DA		 769 }
770 }
8316f337
DF		 771
772 DRM_ERROR("too many retries, giving up\n");
8a5e6aeb
PZ		 773 ret = -EREMOTEIO;
774
775out:
4be73780 776 edp_panel_vdd_off(intel_dp, false);
8a5e6aeb 777 return ret;
a4fc5ed6
KP		 778}
779
80f65de3
ID		 780static void
781intel_dp_connector_unregister(struct intel_connector *intel_connector)
782{
783 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
784
785 sysfs_remove_link(&intel_connector->base.kdev->kobj,
786 intel_dp->adapter.dev.kobj.name);
787 intel_connector_unregister(intel_connector);
788}
789
a4fc5ed6 790static int
ea5b213a 791intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 792 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 793{
0b5c541b
KP		 794 int ret;
795
d54e9d28 796 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 797 intel_dp->algo.running = false;
798 intel_dp->algo.address = 0;
799 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
800
0206e353 801 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 802 intel_dp->adapter.owner = THIS_MODULE;
803 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 804 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 805 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
806 intel_dp->adapter.algo_data = &intel_dp->algo;
80f65de3 807 intel_dp->adapter.dev.parent = intel_connector->base.dev->dev;
ea5b213a 808
0b5c541b 809 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
80f65de3
ID		 810 if (ret < 0)
811 return ret;
812
813 ret = sysfs_create_link(&intel_connector->base.kdev->kobj,
814 &intel_dp->adapter.dev.kobj,
815 intel_dp->adapter.dev.kobj.name);
816
817 if (ret < 0)
818 i2c_del_adapter(&intel_dp->adapter);
819
0b5c541b 820 return ret;
a4fc5ed6
KP		 821}
822
c6bb3538
DV		 823static void
824intel_dp_set_clock(struct intel_encoder *encoder,
825 struct intel_crtc_config *pipe_config, int link_bw)
826{
827 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 828 const struct dp_link_dpll *divisor = NULL;
829 int i, count = 0;
c6bb3538
DV		 830
831 if (IS_G4X(dev)) {
9dd4ffdf
CML		 832 divisor = gen4_dpll;
833 count = ARRAY_SIZE(gen4_dpll);
c6bb3538
DV		 834 } else if (IS_HASWELL(dev)) {
835 /* Haswell has special-purpose DP DDI clocks. */
836 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 837 divisor = pch_dpll;
838 count = ARRAY_SIZE(pch_dpll);
c6bb3538 839 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 840 divisor = vlv_dpll;
841 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 842 }
9dd4ffdf
CML		 843
844 if (divisor && count) {
845 for (i = 0; i < count; i++) {
846 if (link_bw == divisor[i].link_bw) {
847 pipe_config->dpll = divisor[i].dpll;
848 pipe_config->clock_set = true;
849 break;
850 }
851 }
c6bb3538
DV		 852 }
853}
854
00c09d70 855bool
5bfe2ac0
DV		 856intel_dp_compute_config(struct intel_encoder *encoder,
857 struct intel_crtc_config *pipe_config)
a4fc5ed6 858{
5bfe2ac0 859 struct drm_device *dev = encoder->base.dev;
36008365 860 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 861 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 862 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 863 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 864 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 865 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 866 int lane_count, clock;
397fe157 867 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
06ea66b6
TP		 868 /* Conveniently, the link BW constants become indices with a shift...*/
869 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 870 int bpp, mode_rate;
06ea66b6 871 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 872 int link_avail, link_clock;
a4fc5ed6 873
bc7d38a4 874 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 875 pipe_config->has_pch_encoder = true;
876
03afc4a2 877 pipe_config->has_dp_encoder = true;
a4fc5ed6 878
dd06f90e
JN		 879 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
880 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
881 adjusted_mode);
2dd24552
JB		 882 if (!HAS_PCH_SPLIT(dev))
883 intel_gmch_panel_fitting(intel_crtc, pipe_config,
884 intel_connector->panel.fitting_mode);
885 else
b074cec8
JB		 886 intel_pch_panel_fitting(intel_crtc, pipe_config,
887 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 888 }
889
cb1793ce 890 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 891 return false;
892
083f9560
DV		 893 DRM_DEBUG_KMS("DP link computation with max lane count %i "
894 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 895 max_lane_count, bws[max_clock],
896 adjusted_mode->crtc_clock);
083f9560 897
36008365
DV		 898 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
899 * bpc in between. */
3e7ca985 900 bpp = pipe_config->pipe_bpp;
6da7f10d
JN		 901 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
902 dev_priv->vbt.edp_bpp < bpp) {
7984211e
ID		 903 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
904 dev_priv->vbt.edp_bpp);
6da7f10d 905 bpp = dev_priv->vbt.edp_bpp;
7984211e 906 }
657445fe 907
36008365 908 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 909 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
910 bpp);
36008365 911
38aecea0
DV		 912 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
913 for (clock = 0; clock <= max_clock; clock++) {
36008365
DV		 914 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
915 link_avail = intel_dp_max_data_rate(link_clock,
916 lane_count);
917
918 if (mode_rate <= link_avail) {
919 goto found;
920 }
921 }
922 }
923 }
c4867936 924
36008365 925 return false;
3685a8f3 926
36008365 927found:
55bc60db
VS		 928 if (intel_dp->color_range_auto) {
929 /*
930 * See:
931 * CEA-861-E - 5.1 Default Encoding Parameters
932 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
933 */
18316c8c 934 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 935 intel_dp->color_range = DP_COLOR_RANGE_16_235;
936 else
937 intel_dp->color_range = 0;
938 }
939
3685a8f3 940 if (intel_dp->color_range)
50f3b016 941 pipe_config->limited_color_range = true;
a4fc5ed6 942
36008365
DV		 943 intel_dp->link_bw = bws[clock];
944 intel_dp->lane_count = lane_count;
657445fe 945 pipe_config->pipe_bpp = bpp;
ff9a6750 946 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 947
36008365
DV		 948 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
949 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 950 pipe_config->port_clock, bpp);
36008365
DV		 951 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
952 mode_rate, link_avail);
a4fc5ed6 953
03afc4a2 954 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 955 adjusted_mode->crtc_clock,
956 pipe_config->port_clock,
03afc4a2 957 &pipe_config->dp_m_n);
9d1a455b 958
c6bb3538
DV		 959 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
960
03afc4a2 961 return true;
a4fc5ed6
KP		 962}
963
7c62a164 964static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 965{
7c62a164
DV		 966 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
967 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
968 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 969 struct drm_i915_private *dev_priv = dev->dev_private;
970 u32 dpa_ctl;
971
ff9a6750 972 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 973 dpa_ctl = I915_READ(DP_A);
974 dpa_ctl &= ~DP_PLL_FREQ_MASK;
975
ff9a6750 976 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 977 /* For a long time we've carried around a ILK-DevA w/a for the
978 * 160MHz clock. If we're really unlucky, it's still required.
979 */
980 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 981 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 982 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 983 } else {
984 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 985 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 986 }
1ce17038 987
ea9b6006
DV		 988 I915_WRITE(DP_A, dpa_ctl);
989
990 POSTING_READ(DP_A);
991 udelay(500);
992}
993
b934223d 994static void intel_dp_mode_set(struct intel_encoder *encoder)
a4fc5ed6 995{
b934223d 996 struct drm_device *dev = encoder->base.dev;
417e822d 997 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 998 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 999 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1000 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1001 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1002
417e822d 1003 /*
1a2eb460 1004 * There are four kinds of DP registers:
417e822d
KP		 1005 *
1006 * IBX PCH
1a2eb460
KP		 1007 * SNB CPU
1008 * IVB CPU
417e822d
KP		 1009 * CPT PCH
1010 *
1011 * IBX PCH and CPU are the same for almost everything,
1012 * except that the CPU DP PLL is configured in this
1013 * register
1014 *
1015 * CPT PCH is quite different, having many bits moved
1016 * to the TRANS_DP_CTL register instead. That
1017 * configuration happens (oddly) in ironlake_pch_enable
1018 */
9c9e7927 1019
417e822d
KP		 1020 /* Preserve the BIOS-computed detected bit. This is
1021 * supposed to be read-only.
1022 */
1023 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1024
417e822d 1025 /* Handle DP bits in common between all three register formats */
417e822d 1026 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1027 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1028
e0dac65e
WF		 1029 if (intel_dp->has_audio) {
1030 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1031 pipe_name(crtc->pipe));
ea5b213a 1032 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1033 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1034 }
247d89f6 1035
417e822d 1036 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1037
bc7d38a4 1038 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1039 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1040 intel_dp->DP |= DP_SYNC_HS_HIGH;
1041 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1042 intel_dp->DP |= DP_SYNC_VS_HIGH;
1043 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1044
6aba5b6c 1045 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1046 intel_dp->DP |= DP_ENHANCED_FRAMING;
1047
7c62a164 1048 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1049 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1050 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1051 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1052
1053 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1054 intel_dp->DP |= DP_SYNC_HS_HIGH;
1055 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1056 intel_dp->DP |= DP_SYNC_VS_HIGH;
1057 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1058
6aba5b6c 1059 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1060 intel_dp->DP |= DP_ENHANCED_FRAMING;
1061
7c62a164 1062 if (crtc->pipe == 1)
417e822d 1063 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 1064 } else {
1065 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1066 }
ea9b6006 1067
bc7d38a4 1068 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 1069 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 1070}
1071
ffd6749d
PZ		 1072#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1073#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1074
1a5ef5b7
PZ		 1075#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1076#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1077
ffd6749d
PZ		 1078#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1079#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1080
4be73780 1081static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1082 u32 mask,
1083 u32 value)
bd943159 1084{
30add22d 1085 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1086 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1087 u32 pp_stat_reg, pp_ctrl_reg;
1088
bf13e81b
JN		 1089 pp_stat_reg = _pp_stat_reg(intel_dp);
1090 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1091
99ea7127 1092 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1093 mask, value,
1094 I915_READ(pp_stat_reg),
1095 I915_READ(pp_ctrl_reg));
32ce697c 1096
453c5420 1097 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1098 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1099 I915_READ(pp_stat_reg),
1100 I915_READ(pp_ctrl_reg));
32ce697c 1101 }
54c136d4
CW		 1102
1103 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1104}
32ce697c 1105
4be73780 1106static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1107{
1108 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1109 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1110}
1111
4be73780 1112static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1113{
1114 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1115 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1116}
1117
4be73780 1118static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1119{
1120 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1121
1122 /* When we disable the VDD override bit last we have to do the manual
1123 * wait. */
1124 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1125 intel_dp->panel_power_cycle_delay);
1126
4be73780 1127 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1128}
1129
4be73780 1130static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1131{
1132 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1133 intel_dp->backlight_on_delay);
1134}
1135
4be73780 1136static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1137{
1138 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1139 intel_dp->backlight_off_delay);
1140}
99ea7127 1141
832dd3c1
KP		 1142/* Read the current pp_control value, unlocking the register if it
1143 * is locked
1144 */
1145
453c5420 1146static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1147{
453c5420
JB		 1148 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1149 struct drm_i915_private *dev_priv = dev->dev_private;
1150 u32 control;
832dd3c1 1151
bf13e81b 1152 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1153 control &= ~PANEL_UNLOCK_MASK;
1154 control |= PANEL_UNLOCK_REGS;
1155 return control;
bd943159
KP		 1156}
1157
4be73780 1158static void edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1159{
30add22d 1160 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1161 struct drm_i915_private *dev_priv = dev->dev_private;
1162 u32 pp;
453c5420 1163 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1164
97af61f5
KP		 1165 if (!is_edp(intel_dp))
1166 return;
5d613501 1167
bd943159
KP		 1168 WARN(intel_dp->want_panel_vdd,
1169 "eDP VDD already requested on\n");
1170
1171 intel_dp->want_panel_vdd = true;
99ea7127 1172
4be73780 1173 if (edp_have_panel_vdd(intel_dp))
bd943159 1174 return;
b0665d57 1175
e9cb81a2
PZ		 1176 intel_runtime_pm_get(dev_priv);
1177
b0665d57 1178 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1179
4be73780
DV		 1180 if (!edp_have_panel_power(intel_dp))
1181 wait_panel_power_cycle(intel_dp);
99ea7127 1182
453c5420 1183 pp = ironlake_get_pp_control(intel_dp);
5d613501 1184 pp |= EDP_FORCE_VDD;
ebf33b18 1185
bf13e81b
JN		 1186 pp_stat_reg = _pp_stat_reg(intel_dp);
1187 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1188
1189 I915_WRITE(pp_ctrl_reg, pp);
1190 POSTING_READ(pp_ctrl_reg);
1191 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1192 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1193 /*
1194 * If the panel wasn't on, delay before accessing aux channel
1195 */
4be73780 1196 if (!edp_have_panel_power(intel_dp)) {
bd943159 1197 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1198 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1199 }
5d613501
JB		 1200}
1201
4be73780 1202static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1203{
30add22d 1204 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1205 struct drm_i915_private *dev_priv = dev->dev_private;
1206 u32 pp;
453c5420 1207 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1208
a0e99e68
DV		 1209 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1210
4be73780 1211 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
b0665d57
PZ		 1212 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1213
453c5420 1214 pp = ironlake_get_pp_control(intel_dp);
bd943159 1215 pp &= ~EDP_FORCE_VDD;
bd943159 1216
9f08ef59
PZ		 1217 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1218 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1219
1220 I915_WRITE(pp_ctrl_reg, pp);
1221 POSTING_READ(pp_ctrl_reg);
99ea7127 1222
453c5420
JB		 1223 /* Make sure sequencer is idle before allowing subsequent activity */
1224 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1225 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1226
1227 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1228 intel_dp->last_power_cycle = jiffies;
e9cb81a2
PZ		 1229
1230 intel_runtime_pm_put(dev_priv);
bd943159
KP		 1231 }
1232}
5d613501 1233
4be73780 1234static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1235{
1236 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1237 struct intel_dp, panel_vdd_work);
30add22d 1238 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1239
627f7675 1240 mutex_lock(&dev->mode_config.mutex);
4be73780 1241 edp_panel_vdd_off_sync(intel_dp);
627f7675 1242 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1243}
1244
4be73780 1245static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1246{
97af61f5
KP		 1247 if (!is_edp(intel_dp))
1248 return;
5d613501 1249
bd943159 1250 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1251
bd943159
KP		 1252 intel_dp->want_panel_vdd = false;
1253
1254 if (sync) {
4be73780 1255 edp_panel_vdd_off_sync(intel_dp);
bd943159
KP		 1256 } else {
1257 /*
1258 * Queue the timer to fire a long
1259 * time from now (relative to the power down delay)
1260 * to keep the panel power up across a sequence of operations
1261 */
1262 schedule_delayed_work(&intel_dp->panel_vdd_work,
1263 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1264 }
5d613501
JB		 1265}
1266
4be73780 1267void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1268{
30add22d 1269 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1270 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1271 u32 pp;
453c5420 1272 u32 pp_ctrl_reg;
9934c132 1273
97af61f5 1274 if (!is_edp(intel_dp))
bd943159 1275 return;
99ea7127
KP		 1276
1277 DRM_DEBUG_KMS("Turn eDP power on\n");
1278
4be73780 1279 if (edp_have_panel_power(intel_dp)) {
99ea7127 1280 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1281 return;
99ea7127 1282 }
9934c132 1283
4be73780 1284 wait_panel_power_cycle(intel_dp);
37c6c9b0 1285
bf13e81b 1286 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1287 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1288 if (IS_GEN5(dev)) {
1289 /* ILK workaround: disable reset around power sequence */
1290 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1291 I915_WRITE(pp_ctrl_reg, pp);
1292 POSTING_READ(pp_ctrl_reg);
05ce1a49 1293 }
37c6c9b0 1294
1c0ae80a 1295 pp |= POWER_TARGET_ON;
99ea7127
KP		 1296 if (!IS_GEN5(dev))
1297 pp |= PANEL_POWER_RESET;
1298
453c5420
JB		 1299 I915_WRITE(pp_ctrl_reg, pp);
1300 POSTING_READ(pp_ctrl_reg);
9934c132 1301
4be73780 1302 wait_panel_on(intel_dp);
dce56b3c 1303 intel_dp->last_power_on = jiffies;
9934c132 1304
05ce1a49
KP		 1305 if (IS_GEN5(dev)) {
1306 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1307 I915_WRITE(pp_ctrl_reg, pp);
1308 POSTING_READ(pp_ctrl_reg);
05ce1a49 1309 }
9934c132
JB		 1310}
1311
4be73780 1312void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1313{
30add22d 1314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1315 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1316 u32 pp;
453c5420 1317 u32 pp_ctrl_reg;
9934c132 1318
97af61f5
KP		 1319 if (!is_edp(intel_dp))
1320 return;
37c6c9b0 1321
99ea7127 1322 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1323
4be73780 1324 edp_wait_backlight_off(intel_dp);
dce56b3c 1325
453c5420 1326 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1327 /* We need to switch off panel power _and_ force vdd, for otherwise some
1328 * panels get very unhappy and cease to work. */
b3064154
PJ		 1329 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1330 EDP_BLC_ENABLE);
453c5420 1331
bf13e81b 1332 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1333
1334 I915_WRITE(pp_ctrl_reg, pp);
1335 POSTING_READ(pp_ctrl_reg);
9934c132 1336
dce56b3c 1337 intel_dp->last_power_cycle = jiffies;
4be73780 1338 wait_panel_off(intel_dp);
9934c132
JB		 1339}
1340
4be73780 1341void intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1342{
da63a9f2
PZ		 1343 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1344 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1345 struct drm_i915_private *dev_priv = dev->dev_private;
1346 u32 pp;
453c5420 1347 u32 pp_ctrl_reg;
32f9d658 1348
f01eca2e
KP		 1349 if (!is_edp(intel_dp))
1350 return;
1351
28c97730 1352 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1353 /*
1354 * If we enable the backlight right away following a panel power
1355 * on, we may see slight flicker as the panel syncs with the eDP
1356 * link. So delay a bit to make sure the image is solid before
1357 * allowing it to appear.
1358 */
4be73780 1359 wait_backlight_on(intel_dp);
453c5420 1360 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1361 pp |= EDP_BLC_ENABLE;
453c5420 1362
bf13e81b 1363 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1364
1365 I915_WRITE(pp_ctrl_reg, pp);
1366 POSTING_READ(pp_ctrl_reg);
035aa3de 1367
752aa88a 1368 intel_panel_enable_backlight(intel_dp->attached_connector);
32f9d658
ZW		 1369}
1370
4be73780 1371void intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1372{
30add22d 1373 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1374 struct drm_i915_private *dev_priv = dev->dev_private;
1375 u32 pp;
453c5420 1376 u32 pp_ctrl_reg;
32f9d658 1377
f01eca2e
KP		 1378 if (!is_edp(intel_dp))
1379 return;
1380
752aa88a 1381 intel_panel_disable_backlight(intel_dp->attached_connector);
035aa3de 1382
28c97730 1383 DRM_DEBUG_KMS("\n");
453c5420 1384 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1385 pp &= ~EDP_BLC_ENABLE;
453c5420 1386
bf13e81b 1387 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1388
1389 I915_WRITE(pp_ctrl_reg, pp);
1390 POSTING_READ(pp_ctrl_reg);
dce56b3c 1391 intel_dp->last_backlight_off = jiffies;
32f9d658 1392}
a4fc5ed6 1393
2bd2ad64 1394static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1395{
da63a9f2
PZ		 1396 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1397 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1398 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1399 struct drm_i915_private *dev_priv = dev->dev_private;
1400 u32 dpa_ctl;
1401
2bd2ad64
DV		 1402 assert_pipe_disabled(dev_priv,
1403 to_intel_crtc(crtc)->pipe);
1404
d240f20f
JB		 1405 DRM_DEBUG_KMS("\n");
1406 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1407 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1408 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1409
1410 /* We don't adjust intel_dp->DP while tearing down the link, to
1411 * facilitate link retraining (e.g. after hotplug). Hence clear all
1412 * enable bits here to ensure that we don't enable too much. */
1413 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1414 intel_dp->DP |= DP_PLL_ENABLE;
1415 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1416 POSTING_READ(DP_A);
1417 udelay(200);
d240f20f
JB		 1418}
1419
2bd2ad64 1420static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1421{
da63a9f2
PZ		 1422 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1423 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1424 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1425 struct drm_i915_private *dev_priv = dev->dev_private;
1426 u32 dpa_ctl;
1427
2bd2ad64
DV		 1428 assert_pipe_disabled(dev_priv,
1429 to_intel_crtc(crtc)->pipe);
1430
d240f20f 1431 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1432 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1433 "dp pll off, should be on\n");
1434 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1435
1436 /* We can't rely on the value tracked for the DP register in
1437 * intel_dp->DP because link_down must not change that (otherwise link
1438 * re-training will fail. */
298b0b39 1439 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1440 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1441 POSTING_READ(DP_A);
d240f20f
JB		 1442 udelay(200);
1443}
1444
c7ad3810 1445/* If the sink supports it, try to set the power state appropriately */
c19b0669 1446void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1447{
1448 int ret, i;
1449
1450 /* Should have a valid DPCD by this point */
1451 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1452 return;
1453
1454 if (mode != DRM_MODE_DPMS_ON) {
1455 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1456 DP_SET_POWER_D3);
1457 if (ret != 1)
1458 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1459 } else {
1460 /*
1461 * When turning on, we need to retry for 1ms to give the sink
1462 * time to wake up.
1463 */
1464 for (i = 0; i < 3; i++) {
1465 ret = intel_dp_aux_native_write_1(intel_dp,
1466 DP_SET_POWER,
1467 DP_SET_POWER_D0);
1468 if (ret == 1)
1469 break;
1470 msleep(1);
1471 }
1472 }
1473}
1474
19d8fe15
DV		 1475static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1476 enum pipe *pipe)
d240f20f 1477{
19d8fe15 1478 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1479 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1480 struct drm_device *dev = encoder->base.dev;
1481 struct drm_i915_private *dev_priv = dev->dev_private;
1482 u32 tmp = I915_READ(intel_dp->output_reg);
1483
1484 if (!(tmp & DP_PORT_EN))
1485 return false;
1486
bc7d38a4 1487 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1488 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1489 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1490 *pipe = PORT_TO_PIPE(tmp);
1491 } else {
1492 u32 trans_sel;
1493 u32 trans_dp;
1494 int i;
1495
1496 switch (intel_dp->output_reg) {
1497 case PCH_DP_B:
1498 trans_sel = TRANS_DP_PORT_SEL_B;
1499 break;
1500 case PCH_DP_C:
1501 trans_sel = TRANS_DP_PORT_SEL_C;
1502 break;
1503 case PCH_DP_D:
1504 trans_sel = TRANS_DP_PORT_SEL_D;
1505 break;
1506 default:
1507 return true;
1508 }
1509
1510 for_each_pipe(i) {
1511 trans_dp = I915_READ(TRANS_DP_CTL(i));
1512 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1513 *pipe = i;
1514 return true;
1515 }
1516 }
19d8fe15 1517
4a0833ec
DV		 1518 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1519 intel_dp->output_reg);
1520 }
d240f20f 1521
19d8fe15
DV		 1522 return true;
1523}
d240f20f 1524
045ac3b5
JB		 1525static void intel_dp_get_config(struct intel_encoder *encoder,
1526 struct intel_crtc_config *pipe_config)
1527{
1528 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1529 u32 tmp, flags = 0;
63000ef6
XZ		 1530 struct drm_device *dev = encoder->base.dev;
1531 struct drm_i915_private *dev_priv = dev->dev_private;
1532 enum port port = dp_to_dig_port(intel_dp)->port;
1533 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1534 int dotclock;
045ac3b5 1535
63000ef6
XZ		 1536 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1537 tmp = I915_READ(intel_dp->output_reg);
1538 if (tmp & DP_SYNC_HS_HIGH)
1539 flags |= DRM_MODE_FLAG_PHSYNC;
1540 else
1541 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1542
63000ef6
XZ		 1543 if (tmp & DP_SYNC_VS_HIGH)
1544 flags |= DRM_MODE_FLAG_PVSYNC;
1545 else
1546 flags |= DRM_MODE_FLAG_NVSYNC;
1547 } else {
1548 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1549 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1550 flags |= DRM_MODE_FLAG_PHSYNC;
1551 else
1552 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1553
63000ef6
XZ		 1554 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1555 flags |= DRM_MODE_FLAG_PVSYNC;
1556 else
1557 flags |= DRM_MODE_FLAG_NVSYNC;
1558 }
045ac3b5
JB		 1559
1560 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1561
eb14cb74
VS		 1562 pipe_config->has_dp_encoder = true;
1563
1564 intel_dp_get_m_n(crtc, pipe_config);
1565
18442d08 1566 if (port == PORT_A) {
f1f644dc
JB		 1567 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1568 pipe_config->port_clock = 162000;
1569 else
1570 pipe_config->port_clock = 270000;
1571 }
18442d08
VS		 1572
1573 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1574 &pipe_config->dp_m_n);
1575
1576 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1577 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1578
241bfc38 1579 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1580
c6cd2ee2
JN		 1581 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1582 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1583 /*
1584 * This is a big fat ugly hack.
1585 *
1586 * Some machines in UEFI boot mode provide us a VBT that has 18
1587 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1588 * unknown we fail to light up. Yet the same BIOS boots up with
1589 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1590 * max, not what it tells us to use.
1591 *
1592 * Note: This will still be broken if the eDP panel is not lit
1593 * up by the BIOS, and thus we can't get the mode at module
1594 * load.
1595 */
1596 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1597 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1598 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1599 }
045ac3b5
JB		 1600}
1601
a031d709 1602static bool is_edp_psr(struct drm_device *dev)
2293bb5c 1603{
a031d709
RV		 1604 struct drm_i915_private *dev_priv = dev->dev_private;
1605
1606 return dev_priv->psr.sink_support;
2293bb5c
SK		 1607}
1608
2b28bb1b
RV		 1609static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1610{
1611 struct drm_i915_private *dev_priv = dev->dev_private;
1612
18b5992c 1613 if (!HAS_PSR(dev))
2b28bb1b
RV		 1614 return false;
1615
18b5992c 1616 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1617}
1618
1619static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1620 struct edp_vsc_psr *vsc_psr)
1621{
1622 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1623 struct drm_device *dev = dig_port->base.base.dev;
1624 struct drm_i915_private *dev_priv = dev->dev_private;
1625 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1626 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1627 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1628 uint32_t *data = (uint32_t *) vsc_psr;
1629 unsigned int i;
1630
1631 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1632 the video DIP being updated before program video DIP data buffer
1633 registers for DIP being updated. */
1634 I915_WRITE(ctl_reg, 0);
1635 POSTING_READ(ctl_reg);
1636
1637 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1638 if (i < sizeof(struct edp_vsc_psr))
1639 I915_WRITE(data_reg + i, *data++);
1640 else
1641 I915_WRITE(data_reg + i, 0);
1642 }
1643
1644 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1645 POSTING_READ(ctl_reg);
1646}
1647
1648static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1649{
1650 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1651 struct drm_i915_private *dev_priv = dev->dev_private;
1652 struct edp_vsc_psr psr_vsc;
1653
1654 if (intel_dp->psr_setup_done)
1655 return;
1656
1657 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1658 memset(&psr_vsc, 0, sizeof(psr_vsc));
1659 psr_vsc.sdp_header.HB0 = 0;
1660 psr_vsc.sdp_header.HB1 = 0x7;
1661 psr_vsc.sdp_header.HB2 = 0x2;
1662 psr_vsc.sdp_header.HB3 = 0x8;
1663 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1664
1665 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1666 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1667 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1668
1669 intel_dp->psr_setup_done = true;
1670}
1671
1672static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1673{
1674 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1675 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1676 uint32_t aux_clock_divider;
2b28bb1b
RV		 1677 int precharge = 0x3;
1678 int msg_size = 5; /* Header(4) + Message(1) */
1679
ec5b01dd
DL		 1680 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1681
2b28bb1b
RV		 1682 /* Enable PSR in sink */
1683 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1684 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1685 DP_PSR_ENABLE &
1686 ~DP_PSR_MAIN_LINK_ACTIVE);
1687 else
1688 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1689 DP_PSR_ENABLE |
1690 DP_PSR_MAIN_LINK_ACTIVE);
1691
1692 /* Setup AUX registers */
18b5992c
BW		 1693 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1694 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1695 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1696 DP_AUX_CH_CTL_TIME_OUT_400us |
1697 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1698 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1699 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1700}
1701
1702static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1703{
1704 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 uint32_t max_sleep_time = 0x1f;
1707 uint32_t idle_frames = 1;
1708 uint32_t val = 0x0;
ed8546ac 1709 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2b28bb1b
RV		 1710
1711 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1712 val |= EDP_PSR_LINK_STANDBY;
1713 val |= EDP_PSR_TP2_TP3_TIME_0us;
1714 val |= EDP_PSR_TP1_TIME_0us;
1715 val |= EDP_PSR_SKIP_AUX_EXIT;
1716 } else
1717 val |= EDP_PSR_LINK_DISABLE;
1718
18b5992c 1719 I915_WRITE(EDP_PSR_CTL(dev), val |
ed8546ac 1720 IS_BROADWELL(dev) ? 0 : link_entry_time |
2b28bb1b
RV		 1721 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1722 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1723 EDP_PSR_ENABLE);
1724}
1725
3f51e471
RV		 1726static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1727{
1728 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1729 struct drm_device *dev = dig_port->base.base.dev;
1730 struct drm_i915_private *dev_priv = dev->dev_private;
1731 struct drm_crtc *crtc = dig_port->base.base.crtc;
1732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1733 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1734 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1735
a031d709
RV		 1736 dev_priv->psr.source_ok = false;
1737
18b5992c 1738 if (!HAS_PSR(dev)) {
3f51e471 1739 DRM_DEBUG_KMS("PSR not supported on this platform\n");
3f51e471
RV		 1740 return false;
1741 }
1742
1743 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1744 (dig_port->port != PORT_A)) {
1745 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1746 return false;
1747 }
1748
d330a953 1749 if (!i915.enable_psr) {
105b7c11 1750 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1751 return false;
1752 }
1753
cd234b0b
CW		 1754 crtc = dig_port->base.base.crtc;
1755 if (crtc == NULL) {
1756 DRM_DEBUG_KMS("crtc not active for PSR\n");
cd234b0b
CW		 1757 return false;
1758 }
1759
1760 intel_crtc = to_intel_crtc(crtc);
20ddf665 1761 if (!intel_crtc_active(crtc)) {
3f51e471 1762 DRM_DEBUG_KMS("crtc not active for PSR\n");
3f51e471
RV		 1763 return false;
1764 }
1765
cd234b0b 1766 obj = to_intel_framebuffer(crtc->fb)->obj;
3f51e471
RV		 1767 if (obj->tiling_mode != I915_TILING_X ||
1768 obj->fence_reg == I915_FENCE_REG_NONE) {
1769 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
3f51e471
RV		 1770 return false;
1771 }
1772
1773 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1774 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
3f51e471
RV		 1775 return false;
1776 }
1777
1778 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1779 S3D_ENABLE) {
1780 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1781 return false;
1782 }
1783
ca73b4f0 1784 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1785 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1786 return false;
1787 }
1788
a031d709 1789 dev_priv->psr.source_ok = true;
3f51e471
RV		 1790 return true;
1791}
1792
3d739d92 1793static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1794{
1795 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1796
3f51e471
RV		 1797 if (!intel_edp_psr_match_conditions(intel_dp) ||
1798 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1799 return;
1800
1801 /* Setup PSR once */
1802 intel_edp_psr_setup(intel_dp);
1803
1804 /* Enable PSR on the panel */
1805 intel_edp_psr_enable_sink(intel_dp);
1806
1807 /* Enable PSR on the host */
1808 intel_edp_psr_enable_source(intel_dp);
1809}
1810
3d739d92
RV		 1811void intel_edp_psr_enable(struct intel_dp *intel_dp)
1812{
1813 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1814
1815 if (intel_edp_psr_match_conditions(intel_dp) &&
1816 !intel_edp_is_psr_enabled(dev))
1817 intel_edp_psr_do_enable(intel_dp);
1818}
1819
2b28bb1b
RV		 1820void intel_edp_psr_disable(struct intel_dp *intel_dp)
1821{
1822 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1823 struct drm_i915_private *dev_priv = dev->dev_private;
1824
1825 if (!intel_edp_is_psr_enabled(dev))
1826 return;
1827
18b5992c
BW		 1828 I915_WRITE(EDP_PSR_CTL(dev),
1829 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2b28bb1b
RV		 1830
1831 /* Wait till PSR is idle */
18b5992c 1832 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2b28bb1b
RV		 1833 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1834 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1835}
1836
3d739d92
RV		 1837void intel_edp_psr_update(struct drm_device *dev)
1838{
1839 struct intel_encoder *encoder;
1840 struct intel_dp *intel_dp = NULL;
1841
1842 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1843 if (encoder->type == INTEL_OUTPUT_EDP) {
1844 intel_dp = enc_to_intel_dp(&encoder->base);
1845
a031d709 1846 if (!is_edp_psr(dev))
3d739d92
RV		 1847 return;
1848
1849 if (!intel_edp_psr_match_conditions(intel_dp))
1850 intel_edp_psr_disable(intel_dp);
1851 else
1852 if (!intel_edp_is_psr_enabled(dev))
1853 intel_edp_psr_do_enable(intel_dp);
1854 }
1855}
1856
e8cb4558 1857static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1858{
e8cb4558 1859 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1860 enum port port = dp_to_dig_port(intel_dp)->port;
1861 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1862
1863 /* Make sure the panel is off before trying to change the mode. But also
1864 * ensure that we have vdd while we switch off the panel. */
b3064154 1865 edp_panel_vdd_on(intel_dp);
4be73780 1866 intel_edp_backlight_off(intel_dp);
fdbc3b1f 1867 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 1868 intel_edp_panel_off(intel_dp);
b3064154 1869 edp_panel_vdd_off(intel_dp, true);
3739850b
DV		 1870
1871 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1872 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1873 intel_dp_link_down(intel_dp);
d240f20f
JB		 1874}
1875
2bd2ad64 1876static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1877{
2bd2ad64 1878 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1879 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1880 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1881
982a3866 1882 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1883 intel_dp_link_down(intel_dp);
b2634017
JB		 1884 if (!IS_VALLEYVIEW(dev))
1885 ironlake_edp_pll_off(intel_dp);
3739850b 1886 }
2bd2ad64
DV		 1887}
1888
e8cb4558 1889static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1890{
e8cb4558
DV		 1891 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1892 struct drm_device *dev = encoder->base.dev;
1893 struct drm_i915_private *dev_priv = dev->dev_private;
1894 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1895
0c33d8d7
DV		 1896 if (WARN_ON(dp_reg & DP_PORT_EN))
1897 return;
5d613501 1898
4be73780 1899 edp_panel_vdd_on(intel_dp);
f01eca2e 1900 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1901 intel_dp_start_link_train(intel_dp);
4be73780
DV		 1902 intel_edp_panel_on(intel_dp);
1903 edp_panel_vdd_off(intel_dp, true);
33a34e4e 1904 intel_dp_complete_link_train(intel_dp);
3ab9c637 1905 intel_dp_stop_link_train(intel_dp);
ab1f90f9 1906}
89b667f8 1907
ecff4f3b
JN		 1908static void g4x_enable_dp(struct intel_encoder *encoder)
1909{
828f5c6e
JN		 1910 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1911
ecff4f3b 1912 intel_enable_dp(encoder);
4be73780 1913 intel_edp_backlight_on(intel_dp);
ab1f90f9 1914}
89b667f8 1915
ab1f90f9
JN		 1916static void vlv_enable_dp(struct intel_encoder *encoder)
1917{
828f5c6e
JN		 1918 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1919
4be73780 1920 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 1921}
1922
ecff4f3b 1923static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 1924{
1925 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1926 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1927
1928 if (dport->port == PORT_A)
1929 ironlake_edp_pll_on(intel_dp);
1930}
1931
1932static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1933{
2bd2ad64 1934 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1935 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1936 struct drm_device *dev = encoder->base.dev;
89b667f8 1937 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 1938 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 1939 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 1940 int pipe = intel_crtc->pipe;
bf13e81b 1941 struct edp_power_seq power_seq;
ab1f90f9 1942 u32 val;
a4fc5ed6 1943
ab1f90f9 1944 mutex_lock(&dev_priv->dpio_lock);
89b667f8 1945
ab3c759a 1946 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 1947 val = 0;
1948 if (pipe)
1949 val |= (1<<21);
1950 else
1951 val &= ~(1<<21);
1952 val |= 0x001000c4;
ab3c759a
CML		 1953 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1954 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1955 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 1956
ab1f90f9
JN		 1957 mutex_unlock(&dev_priv->dpio_lock);
1958
bf13e81b
JN		 1959 /* init power sequencer on this pipe and port */
1960 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1961 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1962 &power_seq);
1963
ab1f90f9
JN		 1964 intel_enable_dp(encoder);
1965
e4607fcf 1966 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 1967}
1968
ecff4f3b 1969static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1970{
1971 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1972 struct drm_device *dev = encoder->base.dev;
1973 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1974 struct intel_crtc *intel_crtc =
1975 to_intel_crtc(encoder->base.crtc);
e4607fcf 1976 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1977 int pipe = intel_crtc->pipe;
89b667f8 1978
89b667f8 1979 /* Program Tx lane resets to default */
0980a60f 1980 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 1981 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 1982 DPIO_PCS_TX_LANE2_RESET |
1983 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 1984 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 1985 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1986 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1987 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1988 DPIO_PCS_CLK_SOFT_RESET);
1989
1990 /* Fix up inter-pair skew failure */
ab3c759a
CML		 1991 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1992 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1993 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 1994 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 1995}
1996
1997/*
df0c237d
JB		 1998 * Native read with retry for link status and receiver capability reads for
1999 * cases where the sink may still be asleep.
a4fc5ed6
KP		 2000 */
2001static bool
df0c237d
JB		 2002intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
2003 uint8_t *recv, int recv_bytes)
a4fc5ed6 2004{
61da5fab
JB		 2005 int ret, i;
2006
df0c237d
JB		 2007 /*
2008 * Sinks are *supposed* to come up within 1ms from an off state,
2009 * but we're also supposed to retry 3 times per the spec.
2010 */
61da5fab 2011 for (i = 0; i < 3; i++) {
df0c237d
JB		 2012 ret = intel_dp_aux_native_read(intel_dp, address, recv,
2013 recv_bytes);
2014 if (ret == recv_bytes)
61da5fab
JB		 2015 return true;
2016 msleep(1);
2017 }
a4fc5ed6 2018
61da5fab 2019 return false;
a4fc5ed6
KP		 2020}
2021
2022/*
2023 * Fetch AUX CH registers 0x202 - 0x207 which contain
2024 * link status information
2025 */
2026static bool
93f62dad 2027intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2028{
df0c237d
JB		 2029 return intel_dp_aux_native_read_retry(intel_dp,
2030 DP_LANE0_1_STATUS,
93f62dad 2031 link_status,
df0c237d 2032 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 2033}
2034
a4fc5ed6
KP		 2035/*
2036 * These are source-specific values; current Intel hardware supports
2037 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2038 */
a4fc5ed6
KP		 2039
2040static uint8_t
1a2eb460 2041intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2042{
30add22d 2043 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2044 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2045
8f93f4f1 2046 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
e2fa6fba 2047 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2048 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2049 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2050 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2051 return DP_TRAIN_VOLTAGE_SWING_1200;
2052 else
2053 return DP_TRAIN_VOLTAGE_SWING_800;
2054}
2055
2056static uint8_t
2057intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2058{
30add22d 2059 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2060 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2061
8f93f4f1
PZ		 2062 if (IS_BROADWELL(dev)) {
2063 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2064 case DP_TRAIN_VOLTAGE_SWING_400:
2065 case DP_TRAIN_VOLTAGE_SWING_600:
2066 return DP_TRAIN_PRE_EMPHASIS_6;
2067 case DP_TRAIN_VOLTAGE_SWING_800:
2068 return DP_TRAIN_PRE_EMPHASIS_3_5;
2069 case DP_TRAIN_VOLTAGE_SWING_1200:
2070 default:
2071 return DP_TRAIN_PRE_EMPHASIS_0;
2072 }
2073 } else if (IS_HASWELL(dev)) {
d6c0d722
PZ		 2074 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2075 case DP_TRAIN_VOLTAGE_SWING_400:
2076 return DP_TRAIN_PRE_EMPHASIS_9_5;
2077 case DP_TRAIN_VOLTAGE_SWING_600:
2078 return DP_TRAIN_PRE_EMPHASIS_6;
2079 case DP_TRAIN_VOLTAGE_SWING_800:
2080 return DP_TRAIN_PRE_EMPHASIS_3_5;
2081 case DP_TRAIN_VOLTAGE_SWING_1200:
2082 default:
2083 return DP_TRAIN_PRE_EMPHASIS_0;
2084 }
e2fa6fba
P		 2085 } else if (IS_VALLEYVIEW(dev)) {
2086 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2087 case DP_TRAIN_VOLTAGE_SWING_400:
2088 return DP_TRAIN_PRE_EMPHASIS_9_5;
2089 case DP_TRAIN_VOLTAGE_SWING_600:
2090 return DP_TRAIN_PRE_EMPHASIS_6;
2091 case DP_TRAIN_VOLTAGE_SWING_800:
2092 return DP_TRAIN_PRE_EMPHASIS_3_5;
2093 case DP_TRAIN_VOLTAGE_SWING_1200:
2094 default:
2095 return DP_TRAIN_PRE_EMPHASIS_0;
2096 }
bc7d38a4 2097 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2098 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2099 case DP_TRAIN_VOLTAGE_SWING_400:
2100 return DP_TRAIN_PRE_EMPHASIS_6;
2101 case DP_TRAIN_VOLTAGE_SWING_600:
2102 case DP_TRAIN_VOLTAGE_SWING_800:
2103 return DP_TRAIN_PRE_EMPHASIS_3_5;
2104 default:
2105 return DP_TRAIN_PRE_EMPHASIS_0;
2106 }
2107 } else {
2108 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2109 case DP_TRAIN_VOLTAGE_SWING_400:
2110 return DP_TRAIN_PRE_EMPHASIS_6;
2111 case DP_TRAIN_VOLTAGE_SWING_600:
2112 return DP_TRAIN_PRE_EMPHASIS_6;
2113 case DP_TRAIN_VOLTAGE_SWING_800:
2114 return DP_TRAIN_PRE_EMPHASIS_3_5;
2115 case DP_TRAIN_VOLTAGE_SWING_1200:
2116 default:
2117 return DP_TRAIN_PRE_EMPHASIS_0;
2118 }
a4fc5ed6
KP		 2119 }
2120}
2121
e2fa6fba
P		 2122static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2123{
2124 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2125 struct drm_i915_private *dev_priv = dev->dev_private;
2126 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2127 struct intel_crtc *intel_crtc =
2128 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2129 unsigned long demph_reg_value, preemph_reg_value,
2130 uniqtranscale_reg_value;
2131 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2132 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2133 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2134
2135 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2136 case DP_TRAIN_PRE_EMPHASIS_0:
2137 preemph_reg_value = 0x0004000;
2138 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2139 case DP_TRAIN_VOLTAGE_SWING_400:
2140 demph_reg_value = 0x2B405555;
2141 uniqtranscale_reg_value = 0x552AB83A;
2142 break;
2143 case DP_TRAIN_VOLTAGE_SWING_600:
2144 demph_reg_value = 0x2B404040;
2145 uniqtranscale_reg_value = 0x5548B83A;
2146 break;
2147 case DP_TRAIN_VOLTAGE_SWING_800:
2148 demph_reg_value = 0x2B245555;
2149 uniqtranscale_reg_value = 0x5560B83A;
2150 break;
2151 case DP_TRAIN_VOLTAGE_SWING_1200:
2152 demph_reg_value = 0x2B405555;
2153 uniqtranscale_reg_value = 0x5598DA3A;
2154 break;
2155 default:
2156 return 0;
2157 }
2158 break;
2159 case DP_TRAIN_PRE_EMPHASIS_3_5:
2160 preemph_reg_value = 0x0002000;
2161 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2162 case DP_TRAIN_VOLTAGE_SWING_400:
2163 demph_reg_value = 0x2B404040;
2164 uniqtranscale_reg_value = 0x5552B83A;
2165 break;
2166 case DP_TRAIN_VOLTAGE_SWING_600:
2167 demph_reg_value = 0x2B404848;
2168 uniqtranscale_reg_value = 0x5580B83A;
2169 break;
2170 case DP_TRAIN_VOLTAGE_SWING_800:
2171 demph_reg_value = 0x2B404040;
2172 uniqtranscale_reg_value = 0x55ADDA3A;
2173 break;
2174 default:
2175 return 0;
2176 }
2177 break;
2178 case DP_TRAIN_PRE_EMPHASIS_6:
2179 preemph_reg_value = 0x0000000;
2180 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2181 case DP_TRAIN_VOLTAGE_SWING_400:
2182 demph_reg_value = 0x2B305555;
2183 uniqtranscale_reg_value = 0x5570B83A;
2184 break;
2185 case DP_TRAIN_VOLTAGE_SWING_600:
2186 demph_reg_value = 0x2B2B4040;
2187 uniqtranscale_reg_value = 0x55ADDA3A;
2188 break;
2189 default:
2190 return 0;
2191 }
2192 break;
2193 case DP_TRAIN_PRE_EMPHASIS_9_5:
2194 preemph_reg_value = 0x0006000;
2195 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2196 case DP_TRAIN_VOLTAGE_SWING_400:
2197 demph_reg_value = 0x1B405555;
2198 uniqtranscale_reg_value = 0x55ADDA3A;
2199 break;
2200 default:
2201 return 0;
2202 }
2203 break;
2204 default:
2205 return 0;
2206 }
2207
0980a60f 2208 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2209 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2210 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2211 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2212 uniqtranscale_reg_value);
ab3c759a
CML		 2213 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2214 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2215 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2216 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2217 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2218
2219 return 0;
2220}
2221
a4fc5ed6 2222static void
0301b3ac
JN		 2223intel_get_adjust_train(struct intel_dp *intel_dp,
2224 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2225{
2226 uint8_t v = 0;
2227 uint8_t p = 0;
2228 int lane;
1a2eb460
KP		 2229 uint8_t voltage_max;
2230 uint8_t preemph_max;
a4fc5ed6 2231
33a34e4e 2232 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2233 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2234 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2235
2236 if (this_v > v)
2237 v = this_v;
2238 if (this_p > p)
2239 p = this_p;
2240 }
2241
1a2eb460 2242 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2243 if (v >= voltage_max)
2244 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2245
1a2eb460
KP		 2246 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2247 if (p >= preemph_max)
2248 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2249
2250 for (lane = 0; lane < 4; lane++)
33a34e4e 2251 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2252}
2253
2254static uint32_t
f0a3424e 2255intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2256{
3cf2efb1 2257 uint32_t signal_levels = 0;
a4fc5ed6 2258
3cf2efb1 2259 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2260 case DP_TRAIN_VOLTAGE_SWING_400:
2261 default:
2262 signal_levels |= DP_VOLTAGE_0_4;
2263 break;
2264 case DP_TRAIN_VOLTAGE_SWING_600:
2265 signal_levels |= DP_VOLTAGE_0_6;
2266 break;
2267 case DP_TRAIN_VOLTAGE_SWING_800:
2268 signal_levels |= DP_VOLTAGE_0_8;
2269 break;
2270 case DP_TRAIN_VOLTAGE_SWING_1200:
2271 signal_levels |= DP_VOLTAGE_1_2;
2272 break;
2273 }
3cf2efb1 2274 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2275 case DP_TRAIN_PRE_EMPHASIS_0:
2276 default:
2277 signal_levels |= DP_PRE_EMPHASIS_0;
2278 break;
2279 case DP_TRAIN_PRE_EMPHASIS_3_5:
2280 signal_levels |= DP_PRE_EMPHASIS_3_5;
2281 break;
2282 case DP_TRAIN_PRE_EMPHASIS_6:
2283 signal_levels |= DP_PRE_EMPHASIS_6;
2284 break;
2285 case DP_TRAIN_PRE_EMPHASIS_9_5:
2286 signal_levels |= DP_PRE_EMPHASIS_9_5;
2287 break;
2288 }
2289 return signal_levels;
2290}
2291
e3421a18
ZW		 2292/* Gen6's DP voltage swing and pre-emphasis control */
2293static uint32_t
2294intel_gen6_edp_signal_levels(uint8_t train_set)
2295{
3c5a62b5
YL		 2296 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2297 DP_TRAIN_PRE_EMPHASIS_MASK);
2298 switch (signal_levels) {
e3421a18 2299 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2300 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2301 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2302 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2303 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2304 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2305 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2306 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2307 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2308 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2309 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2310 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2311 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2312 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2313 default:
3c5a62b5
YL		 2314 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2315 "0x%x\n", signal_levels);
2316 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2317 }
2318}
2319
1a2eb460
KP		 2320/* Gen7's DP voltage swing and pre-emphasis control */
2321static uint32_t
2322intel_gen7_edp_signal_levels(uint8_t train_set)
2323{
2324 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2325 DP_TRAIN_PRE_EMPHASIS_MASK);
2326 switch (signal_levels) {
2327 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2328 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2329 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2330 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2331 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2332 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2333
2334 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2335 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2336 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2337 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2338
2339 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2340 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2341 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2342 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2343
2344 default:
2345 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2346 "0x%x\n", signal_levels);
2347 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2348 }
2349}
2350
d6c0d722
PZ		 2351/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2352static uint32_t
f0a3424e 2353intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2354{
d6c0d722
PZ		 2355 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2356 DP_TRAIN_PRE_EMPHASIS_MASK);
2357 switch (signal_levels) {
2358 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2359 return DDI_BUF_EMP_400MV_0DB_HSW;
2360 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2361 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2362 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2363 return DDI_BUF_EMP_400MV_6DB_HSW;
2364 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2365 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2366
d6c0d722
PZ		 2367 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2368 return DDI_BUF_EMP_600MV_0DB_HSW;
2369 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2370 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2371 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2372 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2373
d6c0d722
PZ		 2374 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2375 return DDI_BUF_EMP_800MV_0DB_HSW;
2376 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2377 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2378 default:
2379 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2380 "0x%x\n", signal_levels);
2381 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2382 }
a4fc5ed6
KP		 2383}
2384
8f93f4f1
PZ		 2385static uint32_t
2386intel_bdw_signal_levels(uint8_t train_set)
2387{
2388 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2389 DP_TRAIN_PRE_EMPHASIS_MASK);
2390 switch (signal_levels) {
2391 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2392 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2393 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2394 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2395 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2396 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2397
2398 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2399 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2400 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2401 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2402 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2403 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2404
2405 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2406 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2407 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2408 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2409
2410 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2411 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2412
2413 default:
2414 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2415 "0x%x\n", signal_levels);
2416 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2417 }
2418}
2419
f0a3424e
PZ		 2420/* Properly updates "DP" with the correct signal levels. */
2421static void
2422intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2423{
2424 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2425 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2426 struct drm_device *dev = intel_dig_port->base.base.dev;
2427 uint32_t signal_levels, mask;
2428 uint8_t train_set = intel_dp->train_set[0];
2429
8f93f4f1
PZ		 2430 if (IS_BROADWELL(dev)) {
2431 signal_levels = intel_bdw_signal_levels(train_set);
2432 mask = DDI_BUF_EMP_MASK;
2433 } else if (IS_HASWELL(dev)) {
f0a3424e
PZ		 2434 signal_levels = intel_hsw_signal_levels(train_set);
2435 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2436 } else if (IS_VALLEYVIEW(dev)) {
2437 signal_levels = intel_vlv_signal_levels(intel_dp);
2438 mask = 0;
bc7d38a4 2439 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2440 signal_levels = intel_gen7_edp_signal_levels(train_set);
2441 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2442 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2443 signal_levels = intel_gen6_edp_signal_levels(train_set);
2444 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2445 } else {
2446 signal_levels = intel_gen4_signal_levels(train_set);
2447 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2448 }
2449
2450 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2451
2452 *DP = (*DP & ~mask) | signal_levels;
2453}
2454
a4fc5ed6 2455static bool
ea5b213a 2456intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2457 uint32_t *DP,
58e10eb9 2458 uint8_t dp_train_pat)
a4fc5ed6 2459{
174edf1f
PZ		 2460 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2461 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2462 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2463 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2464 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2465 int ret, len;
a4fc5ed6 2466
22b8bf17 2467 if (HAS_DDI(dev)) {
3ab9c637 2468 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2469
2470 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2471 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2472 else
2473 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2474
2475 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2476 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2477 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2478 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2479
2480 break;
2481 case DP_TRAINING_PATTERN_1:
2482 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2483 break;
2484 case DP_TRAINING_PATTERN_2:
2485 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2486 break;
2487 case DP_TRAINING_PATTERN_3:
2488 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2489 break;
2490 }
174edf1f 2491 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2492
bc7d38a4 2493 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2494 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2495
2496 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2497 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2498 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2499 break;
2500 case DP_TRAINING_PATTERN_1:
70aff66c 2501 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2502 break;
2503 case DP_TRAINING_PATTERN_2:
70aff66c 2504 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2505 break;
2506 case DP_TRAINING_PATTERN_3:
2507 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2508 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2509 break;
2510 }
2511
2512 } else {
70aff66c 2513 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2514
2515 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2516 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2517 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2518 break;
2519 case DP_TRAINING_PATTERN_1:
70aff66c 2520 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2521 break;
2522 case DP_TRAINING_PATTERN_2:
70aff66c 2523 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2524 break;
2525 case DP_TRAINING_PATTERN_3:
2526 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2527 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2528 break;
2529 }
2530 }
2531
70aff66c 2532 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 2533 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2534
2cdfe6c8
JN		 2535 buf[0] = dp_train_pat;
2536 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 2537 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 2538 /* don't write DP_TRAINING_LANEx_SET on disable */
2539 len = 1;
2540 } else {
2541 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2542 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2543 len = intel_dp->lane_count + 1;
47ea7542 2544 }
a4fc5ed6 2545
2cdfe6c8
JN		 2546 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2547 buf, len);
2548
2549 return ret == len;
a4fc5ed6
KP		 2550}
2551
70aff66c
JN		 2552static bool
2553intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2554 uint8_t dp_train_pat)
2555{
953d22e8 2556 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 2557 intel_dp_set_signal_levels(intel_dp, DP);
2558 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2559}
2560
2561static bool
2562intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 2563 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 2564{
2565 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2566 struct drm_device *dev = intel_dig_port->base.base.dev;
2567 struct drm_i915_private *dev_priv = dev->dev_private;
2568 int ret;
2569
2570 intel_get_adjust_train(intel_dp, link_status);
2571 intel_dp_set_signal_levels(intel_dp, DP);
2572
2573 I915_WRITE(intel_dp->output_reg, *DP);
2574 POSTING_READ(intel_dp->output_reg);
2575
2576 ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2577 intel_dp->train_set,
2578 intel_dp->lane_count);
2579
2580 return ret == intel_dp->lane_count;
2581}
2582
3ab9c637
ID		 2583static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2584{
2585 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2586 struct drm_device *dev = intel_dig_port->base.base.dev;
2587 struct drm_i915_private *dev_priv = dev->dev_private;
2588 enum port port = intel_dig_port->port;
2589 uint32_t val;
2590
2591 if (!HAS_DDI(dev))
2592 return;
2593
2594 val = I915_READ(DP_TP_CTL(port));
2595 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2596 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2597 I915_WRITE(DP_TP_CTL(port), val);
2598
2599 /*
2600 * On PORT_A we can have only eDP in SST mode. There the only reason
2601 * we need to set idle transmission mode is to work around a HW issue
2602 * where we enable the pipe while not in idle link-training mode.
2603 * In this case there is requirement to wait for a minimum number of
2604 * idle patterns to be sent.
2605 */
2606 if (port == PORT_A)
2607 return;
2608
2609 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2610 1))
2611 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2612}
2613
33a34e4e 2614/* Enable corresponding port and start training pattern 1 */
c19b0669 2615void
33a34e4e 2616intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2617{
da63a9f2 2618 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2619 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2620 int i;
2621 uint8_t voltage;
cdb0e95b 2622 int voltage_tries, loop_tries;
ea5b213a 2623 uint32_t DP = intel_dp->DP;
6aba5b6c 2624 uint8_t link_config[2];
a4fc5ed6 2625
affa9354 2626 if (HAS_DDI(dev))
c19b0669
PZ		 2627 intel_ddi_prepare_link_retrain(encoder);
2628
3cf2efb1 2629 /* Write the link configuration data */
6aba5b6c
JN		 2630 link_config[0] = intel_dp->link_bw;
2631 link_config[1] = intel_dp->lane_count;
2632 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2633 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2634 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2635
2636 link_config[0] = 0;
2637 link_config[1] = DP_SET_ANSI_8B10B;
2638 intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 2639
2640 DP |= DP_PORT_EN;
1a2eb460 2641
70aff66c
JN		 2642 /* clock recovery */
2643 if (!intel_dp_reset_link_train(intel_dp, &DP,
2644 DP_TRAINING_PATTERN_1 |
2645 DP_LINK_SCRAMBLING_DISABLE)) {
2646 DRM_ERROR("failed to enable link training\n");
2647 return;
2648 }
2649
a4fc5ed6 2650 voltage = 0xff;
cdb0e95b
KP		 2651 voltage_tries = 0;
2652 loop_tries = 0;
a4fc5ed6 2653 for (;;) {
70aff66c 2654 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 2655
a7c9655f 2656 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2657 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2658 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2659 break;
93f62dad 2660 }
a4fc5ed6 2661
01916270 2662 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2663 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2664 break;
2665 }
2666
2667 /* Check to see if we've tried the max voltage */
2668 for (i = 0; i < intel_dp->lane_count; i++)
2669 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2670 break;
3b4f819d 2671 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2672 ++loop_tries;
2673 if (loop_tries == 5) {
3def84b3 2674 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 2675 break;
2676 }
70aff66c
JN		 2677 intel_dp_reset_link_train(intel_dp, &DP,
2678 DP_TRAINING_PATTERN_1 |
2679 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 2680 voltage_tries = 0;
2681 continue;
2682 }
a4fc5ed6 2683
3cf2efb1 2684 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2685 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2686 ++voltage_tries;
b06fbda3 2687 if (voltage_tries == 5) {
3def84b3 2688 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 2689 break;
2690 }
2691 } else
2692 voltage_tries = 0;
2693 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2694
70aff66c
JN		 2695 /* Update training set as requested by target */
2696 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2697 DRM_ERROR("failed to update link training\n");
2698 break;
2699 }
a4fc5ed6
KP		 2700 }
2701
33a34e4e
JB		 2702 intel_dp->DP = DP;
2703}
2704
c19b0669 2705void
33a34e4e
JB		 2706intel_dp_complete_link_train(struct intel_dp *intel_dp)
2707{
33a34e4e 2708 bool channel_eq = false;
37f80975 2709 int tries, cr_tries;
33a34e4e 2710 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 2711 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2712
2713 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2714 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2715 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 2716
a4fc5ed6 2717 /* channel equalization */
70aff66c 2718 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2719 training_pattern |
70aff66c
JN		 2720 DP_LINK_SCRAMBLING_DISABLE)) {
2721 DRM_ERROR("failed to start channel equalization\n");
2722 return;
2723 }
2724
a4fc5ed6 2725 tries = 0;
37f80975 2726 cr_tries = 0;
a4fc5ed6
KP		 2727 channel_eq = false;
2728 for (;;) {
70aff66c 2729 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2730
37f80975
JB		 2731 if (cr_tries > 5) {
2732 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 2733 break;
2734 }
2735
a7c9655f 2736 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 2737 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2738 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2739 break;
70aff66c 2740 }
a4fc5ed6 2741
37f80975 2742 /* Make sure clock is still ok */
01916270 2743 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 2744 intel_dp_start_link_train(intel_dp);
70aff66c 2745 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2746 training_pattern |
70aff66c 2747 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2748 cr_tries++;
2749 continue;
2750 }
2751
1ffdff13 2752 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2753 channel_eq = true;
2754 break;
2755 }
a4fc5ed6 2756
37f80975
JB		 2757 /* Try 5 times, then try clock recovery if that fails */
2758 if (tries > 5) {
2759 intel_dp_link_down(intel_dp);
2760 intel_dp_start_link_train(intel_dp);
70aff66c 2761 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 2762 training_pattern |
70aff66c 2763 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 2764 tries = 0;
2765 cr_tries++;
2766 continue;
2767 }
a4fc5ed6 2768
70aff66c
JN		 2769 /* Update training set as requested by target */
2770 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2771 DRM_ERROR("failed to update link training\n");
2772 break;
2773 }
3cf2efb1 2774 ++tries;
869184a6 2775 }
3cf2efb1 2776
3ab9c637
ID		 2777 intel_dp_set_idle_link_train(intel_dp);
2778
2779 intel_dp->DP = DP;
2780
d6c0d722 2781 if (channel_eq)
07f42258 2782 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2783
3ab9c637
ID		 2784}
2785
2786void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2787{
70aff66c 2788 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 2789 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2790}
2791
2792static void
ea5b213a 2793intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2794{
da63a9f2 2795 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2796 enum port port = intel_dig_port->port;
da63a9f2 2797 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2798 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2799 struct intel_crtc *intel_crtc =
2800 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2801 uint32_t DP = intel_dp->DP;
a4fc5ed6 2802
c19b0669
PZ		 2803 /*
2804 * DDI code has a strict mode set sequence and we should try to respect
2805 * it, otherwise we might hang the machine in many different ways. So we
2806 * really should be disabling the port only on a complete crtc_disable
2807 * sequence. This function is just called under two conditions on DDI
2808 * code:
2809 * - Link train failed while doing crtc_enable, and on this case we
2810 * really should respect the mode set sequence and wait for a
2811 * crtc_disable.
2812 * - Someone turned the monitor off and intel_dp_check_link_status
2813 * called us. We don't need to disable the whole port on this case, so
2814 * when someone turns the monitor on again,
2815 * intel_ddi_prepare_link_retrain will take care of redoing the link
2816 * train.
2817 */
affa9354 2818 if (HAS_DDI(dev))
c19b0669
PZ		 2819 return;
2820
0c33d8d7 2821 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2822 return;
2823
28c97730 2824 DRM_DEBUG_KMS("\n");
32f9d658 2825
bc7d38a4 2826 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2827 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2828 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2829 } else {
2830 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2831 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2832 }
fe255d00 2833 POSTING_READ(intel_dp->output_reg);
5eb08b69 2834
ab527efc
DV		 2835 /* We don't really know why we're doing this */
2836 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2837
493a7081 2838 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2839 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2840 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2841
5bddd17f
EA		 2842 /* Hardware workaround: leaving our transcoder select
2843 * set to transcoder B while it's off will prevent the
2844 * corresponding HDMI output on transcoder A.
2845 *
2846 * Combine this with another hardware workaround:
2847 * transcoder select bit can only be cleared while the
2848 * port is enabled.
2849 */
2850 DP &= ~DP_PIPEB_SELECT;
2851 I915_WRITE(intel_dp->output_reg, DP);
2852
2853 /* Changes to enable or select take place the vblank
2854 * after being written.
2855 */
ff50afe9
DV		 2856 if (WARN_ON(crtc == NULL)) {
2857 /* We should never try to disable a port without a crtc
2858 * attached. For paranoia keep the code around for a
2859 * bit. */
31acbcc4
CW		 2860 POSTING_READ(intel_dp->output_reg);
2861 msleep(50);
2862 } else
ab527efc 2863 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2864 }
2865
832afda6 2866 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2867 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2868 POSTING_READ(intel_dp->output_reg);
f01eca2e 2869 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2870}
2871
26d61aad
KP		 2872static bool
2873intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2874{
a031d709
RV		 2875 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2876 struct drm_device *dev = dig_port->base.base.dev;
2877 struct drm_i915_private *dev_priv = dev->dev_private;
2878
577c7a50
DL		 2879 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2880
92fd8fd1 2881 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2882 sizeof(intel_dp->dpcd)) == 0)
2883 return false; /* aux transfer failed */
92fd8fd1 2884
577c7a50
DL		 2885 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2886 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2887 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2888
edb39244
AJ		 2889 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2890 return false; /* DPCD not present */
2891
2293bb5c
SK		 2892 /* Check if the panel supports PSR */
2893 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939
JN		 2894 if (is_edp(intel_dp)) {
2895 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2896 intel_dp->psr_dpcd,
2897 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 2898 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2899 dev_priv->psr.sink_support = true;
50003939 2900 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 2901 }
50003939
JN		 2902 }
2903
06ea66b6
TP		 2904 /* Training Pattern 3 support */
2905 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
2906 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
2907 intel_dp->use_tps3 = true;
2908 DRM_DEBUG_KMS("Displayport TPS3 supported");
2909 } else
2910 intel_dp->use_tps3 = false;
2911
edb39244
AJ		 2912 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2913 DP_DWN_STRM_PORT_PRESENT))
2914 return true; /* native DP sink */
2915
2916 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2917 return true; /* no per-port downstream info */
2918
2919 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2920 intel_dp->downstream_ports,
2921 DP_MAX_DOWNSTREAM_PORTS) == 0)
2922 return false; /* downstream port status fetch failed */
2923
2924 return true;
92fd8fd1
KP		 2925}
2926
0d198328
AJ		 2927static void
2928intel_dp_probe_oui(struct intel_dp *intel_dp)
2929{
2930 u8 buf[3];
2931
2932 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2933 return;
2934
4be73780 2935 edp_panel_vdd_on(intel_dp);
351cfc34 2936
0d198328
AJ		 2937 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2938 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2939 buf[0], buf[1], buf[2]);
2940
2941 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2942 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2943 buf[0], buf[1], buf[2]);
351cfc34 2944
4be73780 2945 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2946}
2947
d2e216d0
RV		 2948int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
2949{
2950 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2951 struct drm_device *dev = intel_dig_port->base.base.dev;
2952 struct intel_crtc *intel_crtc =
2953 to_intel_crtc(intel_dig_port->base.base.crtc);
2954 u8 buf[1];
2955
2956 if (!intel_dp_aux_native_read(intel_dp, DP_TEST_SINK_MISC, buf, 1))
2957 return -EAGAIN;
2958
2959 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
2960 return -ENOTTY;
2961
2962 if (!intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK,
2963 DP_TEST_SINK_START))
2964 return -EAGAIN;
2965
2966 /* Wait 2 vblanks to be sure we will have the correct CRC value */
2967 intel_wait_for_vblank(dev, intel_crtc->pipe);
2968 intel_wait_for_vblank(dev, intel_crtc->pipe);
2969
2970 if (!intel_dp_aux_native_read(intel_dp, DP_TEST_CRC_R_CR, crc, 6))
2971 return -EAGAIN;
2972
2973 intel_dp_aux_native_write_1(intel_dp, DP_TEST_SINK, 0);
2974 return 0;
2975}
2976
a60f0e38
JB		 2977static bool
2978intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2979{
2980 int ret;
2981
2982 ret = intel_dp_aux_native_read_retry(intel_dp,
2983 DP_DEVICE_SERVICE_IRQ_VECTOR,
2984 sink_irq_vector, 1);
2985 if (!ret)
2986 return false;
2987
2988 return true;
2989}
2990
2991static void
2992intel_dp_handle_test_request(struct intel_dp *intel_dp)
2993{
2994 /* NAK by default */
9324cf7f 2995 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2996}
2997
a4fc5ed6
KP		 2998/*
2999 * According to DP spec
3000 * 5.1.2:
3001 * 1. Read DPCD
3002 * 2. Configure link according to Receiver Capabilities
3003 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3004 * 4. Check link status on receipt of hot-plug interrupt
3005 */
3006
00c09d70 3007void
ea5b213a 3008intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3009{
da63a9f2 3010 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3011 u8 sink_irq_vector;
93f62dad 3012 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3013
da63a9f2 3014 if (!intel_encoder->connectors_active)
d2b996ac 3015 return;
59cd09e1 3016
da63a9f2 3017 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3018 return;
3019
92fd8fd1 3020 /* Try to read receiver status if the link appears to be up */
93f62dad 3021 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3022 return;
3023 }
3024
92fd8fd1 3025 /* Now read the DPCD to see if it's actually running */
26d61aad 3026 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3027 return;
3028 }
3029
a60f0e38
JB		 3030 /* Try to read the source of the interrupt */
3031 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3032 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3033 /* Clear interrupt source */
3034 intel_dp_aux_native_write_1(intel_dp,
3035 DP_DEVICE_SERVICE_IRQ_VECTOR,
3036 sink_irq_vector);
3037
3038 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3039 intel_dp_handle_test_request(intel_dp);
3040 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3041 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3042 }
3043
1ffdff13 3044 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3045 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 3046 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 3047 intel_dp_start_link_train(intel_dp);
3048 intel_dp_complete_link_train(intel_dp);
3ab9c637 3049 intel_dp_stop_link_train(intel_dp);
33a34e4e 3050 }
a4fc5ed6 3051}
a4fc5ed6 3052
caf9ab24 3053/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3054static enum drm_connector_status
26d61aad 3055intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3056{
caf9ab24 3057 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3058 uint8_t type;
3059
3060 if (!intel_dp_get_dpcd(intel_dp))
3061 return connector_status_disconnected;
3062
3063 /* if there's no downstream port, we're done */
3064 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3065 return connector_status_connected;
caf9ab24
AJ		 3066
3067 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3068 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3069 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3070 uint8_t reg;
caf9ab24 3071 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 3072 &reg, 1))
caf9ab24 3073 return connector_status_unknown;
23235177
AJ		 3074 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3075 : connector_status_disconnected;
caf9ab24
AJ		 3076 }
3077
3078 /* If no HPD, poke DDC gently */
3079 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 3080 return connector_status_connected;
caf9ab24
AJ		 3081
3082 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3083 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3084 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3085 if (type == DP_DS_PORT_TYPE_VGA ||
3086 type == DP_DS_PORT_TYPE_NON_EDID)
3087 return connector_status_unknown;
3088 } else {
3089 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3090 DP_DWN_STRM_PORT_TYPE_MASK;
3091 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3092 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3093 return connector_status_unknown;
3094 }
caf9ab24
AJ		 3095
3096 /* Anything else is out of spec, warn and ignore */
3097 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3098 return connector_status_disconnected;
71ba9000
AJ		 3099}
3100
5eb08b69 3101static enum drm_connector_status
a9756bb5 3102ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3103{
30add22d 3104 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3105 struct drm_i915_private *dev_priv = dev->dev_private;
3106 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3107 enum drm_connector_status status;
3108
fe16d949
CW		 3109 /* Can't disconnect eDP, but you can close the lid... */
3110 if (is_edp(intel_dp)) {
30add22d 3111 status = intel_panel_detect(dev);
fe16d949
CW		 3112 if (status == connector_status_unknown)
3113 status = connector_status_connected;
3114 return status;
3115 }
01cb9ea6 3116
1b469639
DL		 3117 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3118 return connector_status_disconnected;
3119
26d61aad 3120 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3121}
3122
a4fc5ed6 3123static enum drm_connector_status
a9756bb5 3124g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3125{
30add22d 3126 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3127 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3128 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3129 uint32_t bit;
5eb08b69 3130
35aad75f
JB		 3131 /* Can't disconnect eDP, but you can close the lid... */
3132 if (is_edp(intel_dp)) {
3133 enum drm_connector_status status;
3134
3135 status = intel_panel_detect(dev);
3136 if (status == connector_status_unknown)
3137 status = connector_status_connected;
3138 return status;
3139 }
3140
232a6ee9
TP		 3141 if (IS_VALLEYVIEW(dev)) {
3142 switch (intel_dig_port->port) {
3143 case PORT_B:
3144 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3145 break;
3146 case PORT_C:
3147 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3148 break;
3149 case PORT_D:
3150 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3151 break;
3152 default:
3153 return connector_status_unknown;
3154 }
3155 } else {
3156 switch (intel_dig_port->port) {
3157 case PORT_B:
3158 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3159 break;
3160 case PORT_C:
3161 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3162 break;
3163 case PORT_D:
3164 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3165 break;
3166 default:
3167 return connector_status_unknown;
3168 }
a4fc5ed6
KP		 3169 }
3170
10f76a38 3171 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3172 return connector_status_disconnected;
3173
26d61aad 3174 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3175}
3176
8c241fef
KP		 3177static struct edid *
3178intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3179{
9cd300e0 3180 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3181
9cd300e0
JN		 3182 /* use cached edid if we have one */
3183 if (intel_connector->edid) {
9cd300e0
JN		 3184 /* invalid edid */
3185 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3186 return NULL;
3187
55e9edeb 3188 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3189 }
8c241fef 3190
9cd300e0 3191 return drm_get_edid(connector, adapter);
8c241fef
KP		 3192}
3193
3194static int
3195intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3196{
9cd300e0 3197 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3198
9cd300e0
JN		 3199 /* use cached edid if we have one */
3200 if (intel_connector->edid) {
3201 /* invalid edid */
3202 if (IS_ERR(intel_connector->edid))
3203 return 0;
3204
3205 return intel_connector_update_modes(connector,
3206 intel_connector->edid);
d6f24d0f
JB		 3207 }
3208
9cd300e0 3209 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3210}
3211
a9756bb5
ZW		 3212static enum drm_connector_status
3213intel_dp_detect(struct drm_connector *connector, bool force)
3214{
3215 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3216 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3217 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3218 struct drm_device *dev = connector->dev;
c8c8fb33 3219 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3220 enum drm_connector_status status;
671dedd2 3221 enum intel_display_power_domain power_domain;
a9756bb5
ZW		 3222 struct edid *edid = NULL;
3223
c8c8fb33
PZ		 3224 intel_runtime_pm_get(dev_priv);
3225
671dedd2
ID		 3226 power_domain = intel_display_port_power_domain(intel_encoder);
3227 intel_display_power_get(dev_priv, power_domain);
3228
164c8598
CW		 3229 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3230 connector->base.id, drm_get_connector_name(connector));
3231
a9756bb5
ZW		 3232 intel_dp->has_audio = false;
3233
3234 if (HAS_PCH_SPLIT(dev))
3235 status = ironlake_dp_detect(intel_dp);
3236 else
3237 status = g4x_dp_detect(intel_dp);
1b9be9d0 3238
a9756bb5 3239 if (status != connector_status_connected)
c8c8fb33 3240 goto out;
a9756bb5 3241
0d198328
AJ		 3242 intel_dp_probe_oui(intel_dp);
3243
c3e5f67b
DV		 3244 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3245 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3246 } else {
8c241fef 3247 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 3248 if (edid) {
3249 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3250 kfree(edid);
3251 }
a9756bb5
ZW		 3252 }
3253
d63885da
PZ		 3254 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3255 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3256 status = connector_status_connected;
3257
3258out:
671dedd2
ID		 3259 intel_display_power_put(dev_priv, power_domain);
3260
c8c8fb33 3261 intel_runtime_pm_put(dev_priv);
671dedd2 3262
c8c8fb33 3263 return status;
a4fc5ed6
KP		 3264}
3265
3266static int intel_dp_get_modes(struct drm_connector *connector)
3267{
df0e9248 3268 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3269 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3270 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3271 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3272 struct drm_device *dev = connector->dev;
671dedd2
ID		 3273 struct drm_i915_private *dev_priv = dev->dev_private;
3274 enum intel_display_power_domain power_domain;
32f9d658 3275 int ret;
a4fc5ed6
KP		 3276
3277 /* We should parse the EDID data and find out if it has an audio sink
3278 */
3279
671dedd2
ID		 3280 power_domain = intel_display_port_power_domain(intel_encoder);
3281 intel_display_power_get(dev_priv, power_domain);
3282
8c241fef 3283 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
671dedd2 3284 intel_display_power_put(dev_priv, power_domain);
f8779fda 3285 if (ret)
32f9d658
ZW		 3286 return ret;
3287
f8779fda 3288 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3289 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3290 struct drm_display_mode *mode;
dd06f90e
JN		 3291 mode = drm_mode_duplicate(dev,
3292 intel_connector->panel.fixed_mode);
f8779fda 3293 if (mode) {
32f9d658
ZW		 3294 drm_mode_probed_add(connector, mode);
3295 return 1;
3296 }
3297 }
3298 return 0;
a4fc5ed6
KP		 3299}
3300
1aad7ac0
CW		 3301static bool
3302intel_dp_detect_audio(struct drm_connector *connector)
3303{
3304 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3305 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3306 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3307 struct drm_device *dev = connector->dev;
3308 struct drm_i915_private *dev_priv = dev->dev_private;
3309 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3310 struct edid *edid;
3311 bool has_audio = false;
3312
671dedd2
ID		 3313 power_domain = intel_display_port_power_domain(intel_encoder);
3314 intel_display_power_get(dev_priv, power_domain);
3315
8c241fef 3316 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 3317 if (edid) {
3318 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3319 kfree(edid);
3320 }
3321
671dedd2
ID		 3322 intel_display_power_put(dev_priv, power_domain);
3323
1aad7ac0
CW		 3324 return has_audio;
3325}
3326
f684960e
CW		 3327static int
3328intel_dp_set_property(struct drm_connector *connector,
3329 struct drm_property *property,
3330 uint64_t val)
3331{
e953fd7b 3332 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3333 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3334 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3335 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3336 int ret;
3337
662595df 3338 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3339 if (ret)
3340 return ret;
3341
3f43c48d 3342 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3343 int i = val;
3344 bool has_audio;
3345
3346 if (i == intel_dp->force_audio)
f684960e
CW		 3347 return 0;
3348
1aad7ac0 3349 intel_dp->force_audio = i;
f684960e 3350
c3e5f67b 3351 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3352 has_audio = intel_dp_detect_audio(connector);
3353 else
c3e5f67b 3354 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3355
3356 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3357 return 0;
3358
1aad7ac0 3359 intel_dp->has_audio = has_audio;
f684960e
CW		 3360 goto done;
3361 }
3362
e953fd7b 3363 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3364 bool old_auto = intel_dp->color_range_auto;
3365 uint32_t old_range = intel_dp->color_range;
3366
55bc60db
VS		 3367 switch (val) {
3368 case INTEL_BROADCAST_RGB_AUTO:
3369 intel_dp->color_range_auto = true;
3370 break;
3371 case INTEL_BROADCAST_RGB_FULL:
3372 intel_dp->color_range_auto = false;
3373 intel_dp->color_range = 0;
3374 break;
3375 case INTEL_BROADCAST_RGB_LIMITED:
3376 intel_dp->color_range_auto = false;
3377 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3378 break;
3379 default:
3380 return -EINVAL;
3381 }
ae4edb80
DV		 3382
3383 if (old_auto == intel_dp->color_range_auto &&
3384 old_range == intel_dp->color_range)
3385 return 0;
3386
e953fd7b
CW		 3387 goto done;
3388 }
3389
53b41837
YN		 3390 if (is_edp(intel_dp) &&
3391 property == connector->dev->mode_config.scaling_mode_property) {
3392 if (val == DRM_MODE_SCALE_NONE) {
3393 DRM_DEBUG_KMS("no scaling not supported\n");
3394 return -EINVAL;
3395 }
3396
3397 if (intel_connector->panel.fitting_mode == val) {
3398 /* the eDP scaling property is not changed */
3399 return 0;
3400 }
3401 intel_connector->panel.fitting_mode = val;
3402
3403 goto done;
3404 }
3405
f684960e
CW		 3406 return -EINVAL;
3407
3408done:
c0c36b94
CW		 3409 if (intel_encoder->base.crtc)
3410 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3411
3412 return 0;
3413}
3414
a4fc5ed6 3415static void
73845adf 3416intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3417{
1d508706 3418 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3419
9cd300e0
JN		 3420 if (!IS_ERR_OR_NULL(intel_connector->edid))
3421 kfree(intel_connector->edid);
3422
acd8db10
PZ		 3423 /* Can't call is_edp() since the encoder may have been destroyed
3424 * already. */
3425 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3426 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3427
a4fc5ed6 3428 drm_connector_cleanup(connector);
55f78c43 3429 kfree(connector);
a4fc5ed6
KP		 3430}
3431
00c09d70 3432void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 3433{
da63a9f2
PZ		 3434 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3435 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 3436 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 3437
3438 i2c_del_adapter(&intel_dp->adapter);
3439 drm_encoder_cleanup(encoder);
bd943159
KP		 3440 if (is_edp(intel_dp)) {
3441 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3442 mutex_lock(&dev->mode_config.mutex);
4be73780 3443 edp_panel_vdd_off_sync(intel_dp);
bd173813 3444 mutex_unlock(&dev->mode_config.mutex);
bd943159 3445 }
da63a9f2 3446 kfree(intel_dig_port);
24d05927
DV		 3447}
3448
a4fc5ed6 3449static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3450 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3451 .detect = intel_dp_detect,
3452 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3453 .set_property = intel_dp_set_property,
73845adf 3454 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3455};
3456
3457static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3458 .get_modes = intel_dp_get_modes,
3459 .mode_valid = intel_dp_mode_valid,
df0e9248 3460 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3461};
3462
a4fc5ed6 3463static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3464 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3465};
3466
995b6762 3467static void
21d40d37 3468intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3469{
fa90ecef 3470 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3471
885a5014 3472 intel_dp_check_link_status(intel_dp);
c8110e52 3473}
6207937d 3474
e3421a18
ZW		 3475/* Return which DP Port should be selected for Transcoder DP control */
3476int
0206e353 3477intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3478{
3479 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3480 struct intel_encoder *intel_encoder;
3481 struct intel_dp *intel_dp;
e3421a18 3482
fa90ecef
PZ		 3483 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3484 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3485
fa90ecef
PZ		 3486 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3487 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3488 return intel_dp->output_reg;
e3421a18 3489 }
ea5b213a 3490
e3421a18
ZW		 3491 return -1;
3492}
3493
36e83a18 3494/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 3495bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 3496{
3497 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 3498 union child_device_config *p_child;
36e83a18 3499 int i;
5d8a7752
VS		 3500 static const short port_mapping[] = {
3501 [PORT_B] = PORT_IDPB,
3502 [PORT_C] = PORT_IDPC,
3503 [PORT_D] = PORT_IDPD,
3504 };
36e83a18 3505
3b32a35b
VS		 3506 if (port == PORT_A)
3507 return true;
3508
41aa3448 3509 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3510 return false;
3511
41aa3448
RV		 3512 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3513 p_child = dev_priv->vbt.child_dev + i;
36e83a18 3514
5d8a7752 3515 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 3516 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3517 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 3518 return true;
3519 }
3520 return false;
3521}
3522
f684960e
CW		 3523static void
3524intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3525{
53b41837
YN		 3526 struct intel_connector *intel_connector = to_intel_connector(connector);
3527
3f43c48d 3528 intel_attach_force_audio_property(connector);
e953fd7b 3529 intel_attach_broadcast_rgb_property(connector);
55bc60db 3530 intel_dp->color_range_auto = true;
53b41837
YN		 3531
3532 if (is_edp(intel_dp)) {
3533 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3534 drm_object_attach_property(
3535 &connector->base,
53b41837 3536 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3537 DRM_MODE_SCALE_ASPECT);
3538 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3539 }
f684960e
CW		 3540}
3541
dada1a9f
ID		 3542static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3543{
3544 intel_dp->last_power_cycle = jiffies;
3545 intel_dp->last_power_on = jiffies;
3546 intel_dp->last_backlight_off = jiffies;
3547}
3548
67a54566
DV		 3549static void
3550intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3551 struct intel_dp *intel_dp,
3552 struct edp_power_seq *out)
67a54566
DV		 3553{
3554 struct drm_i915_private *dev_priv = dev->dev_private;
3555 struct edp_power_seq cur, vbt, spec, final;
3556 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 3557 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 3558
3559 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 3560 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 3561 pp_on_reg = PCH_PP_ON_DELAYS;
3562 pp_off_reg = PCH_PP_OFF_DELAYS;
3563 pp_div_reg = PCH_PP_DIVISOR;
3564 } else {
bf13e81b
JN		 3565 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3566
3567 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3568 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3569 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3570 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 3571 }
67a54566
DV		 3572
3573 /* Workaround: Need to write PP_CONTROL with the unlock key as
3574 * the very first thing. */
453c5420 3575 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 3576 I915_WRITE(pp_ctrl_reg, pp);
67a54566 3577
453c5420
JB		 3578 pp_on = I915_READ(pp_on_reg);
3579 pp_off = I915_READ(pp_off_reg);
3580 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3581
3582 /* Pull timing values out of registers */
3583 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3584 PANEL_POWER_UP_DELAY_SHIFT;
3585
3586 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3587 PANEL_LIGHT_ON_DELAY_SHIFT;
3588
3589 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3590 PANEL_LIGHT_OFF_DELAY_SHIFT;
3591
3592 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3593 PANEL_POWER_DOWN_DELAY_SHIFT;
3594
3595 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3596 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3597
3598 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3599 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3600
41aa3448 3601 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3602
3603 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3604 * our hw here, which are all in 100usec. */
3605 spec.t1_t3 = 210 * 10;
3606 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3607 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3608 spec.t10 = 500 * 10;
3609 /* This one is special and actually in units of 100ms, but zero
3610 * based in the hw (so we need to add 100 ms). But the sw vbt
3611 * table multiplies it with 1000 to make it in units of 100usec,
3612 * too. */
3613 spec.t11_t12 = (510 + 100) * 10;
3614
3615 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3616 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3617
3618 /* Use the max of the register settings and vbt. If both are
3619 * unset, fall back to the spec limits. */
3620#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3621 spec.field : \
3622 max(cur.field, vbt.field))
3623 assign_final(t1_t3);
3624 assign_final(t8);
3625 assign_final(t9);
3626 assign_final(t10);
3627 assign_final(t11_t12);
3628#undef assign_final
3629
3630#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3631 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3632 intel_dp->backlight_on_delay = get_delay(t8);
3633 intel_dp->backlight_off_delay = get_delay(t9);
3634 intel_dp->panel_power_down_delay = get_delay(t10);
3635 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3636#undef get_delay
3637
f30d26e4
JN		 3638 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3639 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3640 intel_dp->panel_power_cycle_delay);
3641
3642 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3643 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3644
3645 if (out)
3646 *out = final;
3647}
3648
3649static void
3650intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3651 struct intel_dp *intel_dp,
3652 struct edp_power_seq *seq)
3653{
3654 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3655 u32 pp_on, pp_off, pp_div, port_sel = 0;
3656 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3657 int pp_on_reg, pp_off_reg, pp_div_reg;
3658
3659 if (HAS_PCH_SPLIT(dev)) {
3660 pp_on_reg = PCH_PP_ON_DELAYS;
3661 pp_off_reg = PCH_PP_OFF_DELAYS;
3662 pp_div_reg = PCH_PP_DIVISOR;
3663 } else {
bf13e81b
JN		 3664 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3665
3666 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3667 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3668 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 3669 }
3670
b2f19d1a
PZ		 3671 /*
3672 * And finally store the new values in the power sequencer. The
3673 * backlight delays are set to 1 because we do manual waits on them. For
3674 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3675 * we'll end up waiting for the backlight off delay twice: once when we
3676 * do the manual sleep, and once when we disable the panel and wait for
3677 * the PP_STATUS bit to become zero.
3678 */
f30d26e4 3679 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 3680 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3681 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 3682 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3683 /* Compute the divisor for the pp clock, simply match the Bspec
3684 * formula. */
453c5420 3685 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3686 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3687 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3688
3689 /* Haswell doesn't have any port selection bits for the panel
3690 * power sequencer any more. */
bc7d38a4 3691 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 3692 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3693 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3694 else
3695 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 3696 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3697 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 3698 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 3699 else
a24c144c 3700 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 3701 }
3702
453c5420
JB		 3703 pp_on |= port_sel;
3704
3705 I915_WRITE(pp_on_reg, pp_on);
3706 I915_WRITE(pp_off_reg, pp_off);
3707 I915_WRITE(pp_div_reg, pp_div);
67a54566 3708
67a54566 3709 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3710 I915_READ(pp_on_reg),
3711 I915_READ(pp_off_reg),
3712 I915_READ(pp_div_reg));
f684960e
CW		 3713}
3714
ed92f0b2 3715static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 3716 struct intel_connector *intel_connector,
3717 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 3718{
3719 struct drm_connector *connector = &intel_connector->base;
3720 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3721 struct drm_device *dev = intel_dig_port->base.base.dev;
3722 struct drm_i915_private *dev_priv = dev->dev_private;
3723 struct drm_display_mode *fixed_mode = NULL;
ed92f0b2
PZ		 3724 bool has_dpcd;
3725 struct drm_display_mode *scan;
3726 struct edid *edid;
3727
3728 if (!is_edp(intel_dp))
3729 return true;
3730
ed92f0b2 3731 /* Cache DPCD and EDID for edp. */
4be73780 3732 edp_panel_vdd_on(intel_dp);
ed92f0b2 3733 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 3734 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 3735
3736 if (has_dpcd) {
3737 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3738 dev_priv->no_aux_handshake =
3739 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3740 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3741 } else {
3742 /* if this fails, presume the device is a ghost */
3743 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3744 return false;
3745 }
3746
3747 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 3748 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 3749
ed92f0b2
PZ		 3750 edid = drm_get_edid(connector, &intel_dp->adapter);
3751 if (edid) {
3752 if (drm_add_edid_modes(connector, edid)) {
3753 drm_mode_connector_update_edid_property(connector,
3754 edid);
3755 drm_edid_to_eld(connector, edid);
3756 } else {
3757 kfree(edid);
3758 edid = ERR_PTR(-EINVAL);
3759 }
3760 } else {
3761 edid = ERR_PTR(-ENOENT);
3762 }
3763 intel_connector->edid = edid;
3764
3765 /* prefer fixed mode from EDID if available */
3766 list_for_each_entry(scan, &connector->probed_modes, head) {
3767 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3768 fixed_mode = drm_mode_duplicate(dev, scan);
3769 break;
3770 }
3771 }
3772
3773 /* fallback to VBT if available for eDP */
3774 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3775 fixed_mode = drm_mode_duplicate(dev,
3776 dev_priv->vbt.lfp_lvds_vbt_mode);
3777 if (fixed_mode)
3778 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3779 }
3780
4b6ed685 3781 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
ed92f0b2
PZ		 3782 intel_panel_setup_backlight(connector);
3783
3784 return true;
3785}
3786
16c25533 3787bool
f0fec3f2
PZ		 3788intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3789 struct intel_connector *intel_connector)
a4fc5ed6 3790{
f0fec3f2
PZ		 3791 struct drm_connector *connector = &intel_connector->base;
3792 struct intel_dp *intel_dp = &intel_dig_port->dp;
3793 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3794 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3795 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3796 enum port port = intel_dig_port->port;
0095e6dc 3797 struct edp_power_seq power_seq = { 0 };
5eb08b69 3798 const char *name = NULL;
b2a14755 3799 int type, error;
a4fc5ed6 3800
ec5b01dd
DL		 3801 /* intel_dp vfuncs */
3802 if (IS_VALLEYVIEW(dev))
3803 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
3804 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3805 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
3806 else if (HAS_PCH_SPLIT(dev))
3807 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
3808 else
3809 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
3810
153b1100
DL		 3811 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
3812
0767935e
DV		 3813 /* Preserve the current hw state. */
3814 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3815 intel_dp->attached_connector = intel_connector;
3d3dc149 3816
3b32a35b 3817 if (intel_dp_is_edp(dev, port))
b329530c 3818 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 3819 else
3820 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 3821
f7d24902
ID		 3822 /*
3823 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3824 * for DP the encoder type can be set by the caller to
3825 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3826 */
3827 if (type == DRM_MODE_CONNECTOR_eDP)
3828 intel_encoder->type = INTEL_OUTPUT_EDP;
3829
e7281eab
ID		 3830 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3831 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3832 port_name(port));
3833
b329530c 3834 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3835 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3836
a4fc5ed6
KP		 3837 connector->interlace_allowed = true;
3838 connector->doublescan_allowed = 0;
3839
f0fec3f2 3840 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 3841 edp_panel_vdd_work);
a4fc5ed6 3842
df0e9248 3843 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3844 drm_sysfs_connector_add(connector);
3845
affa9354 3846 if (HAS_DDI(dev))
bcbc889b
PZ		 3847 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3848 else
3849 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 3850 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 3851
9ed35ab1
PZ		 3852 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3853 if (HAS_DDI(dev)) {
3854 switch (intel_dig_port->port) {
3855 case PORT_A:
3856 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3857 break;
3858 case PORT_B:
3859 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3860 break;
3861 case PORT_C:
3862 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3863 break;
3864 case PORT_D:
3865 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3866 break;
3867 default:
3868 BUG();
3869 }
3870 }
e8cb4558 3871
a4fc5ed6 3872 /* Set up the DDC bus. */
ab9d7c30
PZ		 3873 switch (port) {
3874 case PORT_A:
1d843f9d 3875 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3876 name = "DPDDC-A";
3877 break;
3878 case PORT_B:
1d843f9d 3879 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3880 name = "DPDDC-B";
3881 break;
3882 case PORT_C:
1d843f9d 3883 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3884 name = "DPDDC-C";
3885 break;
3886 case PORT_D:
1d843f9d 3887 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3888 name = "DPDDC-D";
3889 break;
3890 default:
ad1c0b19 3891 BUG();
5eb08b69
ZW		 3892 }
3893
dada1a9f
ID		 3894 if (is_edp(intel_dp)) {
3895 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 3896 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 3897 }
0095e6dc 3898
b2a14755
PZ		 3899 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3900 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3901 error, port_name(port));
c1f05264 3902
2b28bb1b
RV		 3903 intel_dp->psr_setup_done = false;
3904
0095e6dc 3905 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
15b1d171
PZ		 3906 i2c_del_adapter(&intel_dp->adapter);
3907 if (is_edp(intel_dp)) {
3908 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3909 mutex_lock(&dev->mode_config.mutex);
4be73780 3910 edp_panel_vdd_off_sync(intel_dp);
15b1d171
PZ		 3911 mutex_unlock(&dev->mode_config.mutex);
3912 }
b2f246a8
PZ		 3913 drm_sysfs_connector_remove(connector);
3914 drm_connector_cleanup(connector);
16c25533 3915 return false;
b2f246a8 3916 }
32f9d658 3917
f684960e
CW		 3918 intel_dp_add_properties(intel_dp, connector);
3919
a4fc5ed6
KP		 3920 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3921 * 0xd. Failure to do so will result in spurious interrupts being
3922 * generated on the port when a cable is not attached.
3923 */
3924 if (IS_G4X(dev) && !IS_GM45(dev)) {
3925 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3926 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3927 }
16c25533
PZ		 3928
3929 return true;
a4fc5ed6 3930}
f0fec3f2
PZ		 3931
3932void
3933intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3934{
3935 struct intel_digital_port *intel_dig_port;
3936 struct intel_encoder *intel_encoder;
3937 struct drm_encoder *encoder;
3938 struct intel_connector *intel_connector;
3939
b14c5679 3940 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 3941 if (!intel_dig_port)
3942 return;
3943
b14c5679 3944 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 3945 if (!intel_connector) {
3946 kfree(intel_dig_port);
3947 return;
3948 }
3949
3950 intel_encoder = &intel_dig_port->base;
3951 encoder = &intel_encoder->base;
3952
3953 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3954 DRM_MODE_ENCODER_TMDS);
3955
5bfe2ac0 3956 intel_encoder->compute_config = intel_dp_compute_config;
b934223d 3957 intel_encoder->mode_set = intel_dp_mode_set;
00c09d70
PZ		 3958 intel_encoder->disable = intel_disable_dp;
3959 intel_encoder->post_disable = intel_post_disable_dp;
3960 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3961 intel_encoder->get_config = intel_dp_get_config;
ab1f90f9 3962 if (IS_VALLEYVIEW(dev)) {
ecff4f3b 3963 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 3964 intel_encoder->pre_enable = vlv_pre_enable_dp;
3965 intel_encoder->enable = vlv_enable_dp;
3966 } else {
ecff4f3b
JN		 3967 intel_encoder->pre_enable = g4x_pre_enable_dp;
3968 intel_encoder->enable = g4x_enable_dp;
ab1f90f9 3969 }
f0fec3f2 3970
174edf1f 3971 intel_dig_port->port = port;
f0fec3f2
PZ		 3972 intel_dig_port->dp.output_reg = output_reg;
3973
00c09d70 3974 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3975 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3976 intel_encoder->cloneable = false;
3977 intel_encoder->hot_plug = intel_dp_hot_plug;
3978
15b1d171
PZ		 3979 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3980 drm_encoder_cleanup(encoder);
3981 kfree(intel_dig_port);
b2f246a8 3982 kfree(intel_connector);
15b1d171 3983 }
f0fec3f2 3984}
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